1 // SPDX-License-Identifier: GPL-2.0-only 1 // SPDX-License-Identifier: GPL-2.0-only
2 /* 2 /*
3 * Copyright (c) 2014-2015, The Linux Foundati 3 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
4 */ 4 */
5 5
6 #include <dt-bindings/interrupt-controller/arm 6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-msm8996.h 7 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
8 #include <dt-bindings/clock/qcom,mmcc-msm8996. 8 #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
9 #include <dt-bindings/clock/qcom,rpmcc.h> 9 #include <dt-bindings/clock/qcom,rpmcc.h>
10 #include <dt-bindings/interconnect/qcom,msm899 10 #include <dt-bindings/interconnect/qcom,msm8996.h>
11 #include <dt-bindings/interconnect/qcom,msm899 11 #include <dt-bindings/interconnect/qcom,msm8996-cbf.h>
12 #include <dt-bindings/firmware/qcom,scm.h> 12 #include <dt-bindings/firmware/qcom,scm.h>
13 #include <dt-bindings/gpio/gpio.h> 13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/power/qcom-rpmpd.h> 14 #include <dt-bindings/power/qcom-rpmpd.h>
15 #include <dt-bindings/soc/qcom,apr.h> 15 #include <dt-bindings/soc/qcom,apr.h>
16 #include <dt-bindings/thermal/thermal.h> 16 #include <dt-bindings/thermal/thermal.h>
17 17
18 / { 18 / {
19 interrupt-parent = <&intc>; 19 interrupt-parent = <&intc>;
20 20
21 #address-cells = <2>; 21 #address-cells = <2>;
22 #size-cells = <2>; 22 #size-cells = <2>;
23 23
24 chosen { }; 24 chosen { };
25 25
26 clocks { 26 clocks {
27 xo_board: xo-board { 27 xo_board: xo-board {
28 compatible = "fixed-cl 28 compatible = "fixed-clock";
29 #clock-cells = <0>; 29 #clock-cells = <0>;
30 clock-frequency = <192 30 clock-frequency = <19200000>;
31 clock-output-names = " 31 clock-output-names = "xo_board";
32 }; 32 };
33 33
34 sleep_clk: sleep-clk { 34 sleep_clk: sleep-clk {
35 compatible = "fixed-cl 35 compatible = "fixed-clock";
36 #clock-cells = <0>; 36 #clock-cells = <0>;
37 clock-frequency = <327 37 clock-frequency = <32764>;
38 clock-output-names = " 38 clock-output-names = "sleep_clk";
39 }; 39 };
40 }; 40 };
41 41
42 cpus { 42 cpus {
43 #address-cells = <2>; 43 #address-cells = <2>;
44 #size-cells = <0>; 44 #size-cells = <0>;
45 45
46 CPU0: cpu@0 { 46 CPU0: cpu@0 {
47 device_type = "cpu"; 47 device_type = "cpu";
48 compatible = "qcom,kry 48 compatible = "qcom,kryo";
49 reg = <0x0 0x0>; 49 reg = <0x0 0x0>;
50 enable-method = "psci" 50 enable-method = "psci";
51 cpu-idle-states = <&CP 51 cpu-idle-states = <&CPU_SLEEP_0>;
52 capacity-dmips-mhz = < 52 capacity-dmips-mhz = <1024>;
53 clocks = <&kryocc 0>; 53 clocks = <&kryocc 0>;
54 interconnects = <&cbf 54 interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>;
55 operating-points-v2 = 55 operating-points-v2 = <&cluster0_opp>;
56 #cooling-cells = <2>; 56 #cooling-cells = <2>;
57 next-level-cache = <&L 57 next-level-cache = <&L2_0>;
58 L2_0: l2-cache { 58 L2_0: l2-cache {
59 compatible = " 59 compatible = "cache";
60 cache-level = 60 cache-level = <2>;
61 cache-unified; 61 cache-unified;
62 }; 62 };
63 }; 63 };
64 64
65 CPU1: cpu@1 { 65 CPU1: cpu@1 {
66 device_type = "cpu"; 66 device_type = "cpu";
67 compatible = "qcom,kry 67 compatible = "qcom,kryo";
68 reg = <0x0 0x1>; 68 reg = <0x0 0x1>;
69 enable-method = "psci" 69 enable-method = "psci";
70 cpu-idle-states = <&CP 70 cpu-idle-states = <&CPU_SLEEP_0>;
71 capacity-dmips-mhz = < 71 capacity-dmips-mhz = <1024>;
72 clocks = <&kryocc 0>; 72 clocks = <&kryocc 0>;
73 interconnects = <&cbf 73 interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>;
74 operating-points-v2 = 74 operating-points-v2 = <&cluster0_opp>;
75 #cooling-cells = <2>; 75 #cooling-cells = <2>;
76 next-level-cache = <&L 76 next-level-cache = <&L2_0>;
77 }; 77 };
78 78
79 CPU2: cpu@100 { 79 CPU2: cpu@100 {
80 device_type = "cpu"; 80 device_type = "cpu";
81 compatible = "qcom,kry 81 compatible = "qcom,kryo";
82 reg = <0x0 0x100>; 82 reg = <0x0 0x100>;
83 enable-method = "psci" 83 enable-method = "psci";
84 cpu-idle-states = <&CP 84 cpu-idle-states = <&CPU_SLEEP_0>;
85 capacity-dmips-mhz = < 85 capacity-dmips-mhz = <1024>;
86 clocks = <&kryocc 1>; 86 clocks = <&kryocc 1>;
87 interconnects = <&cbf 87 interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>;
88 operating-points-v2 = 88 operating-points-v2 = <&cluster1_opp>;
89 #cooling-cells = <2>; 89 #cooling-cells = <2>;
90 next-level-cache = <&L 90 next-level-cache = <&L2_1>;
91 L2_1: l2-cache { 91 L2_1: l2-cache {
92 compatible = " 92 compatible = "cache";
93 cache-level = 93 cache-level = <2>;
94 cache-unified; 94 cache-unified;
95 }; 95 };
96 }; 96 };
97 97
98 CPU3: cpu@101 { 98 CPU3: cpu@101 {
99 device_type = "cpu"; 99 device_type = "cpu";
100 compatible = "qcom,kry 100 compatible = "qcom,kryo";
101 reg = <0x0 0x101>; 101 reg = <0x0 0x101>;
102 enable-method = "psci" 102 enable-method = "psci";
103 cpu-idle-states = <&CP 103 cpu-idle-states = <&CPU_SLEEP_0>;
104 capacity-dmips-mhz = < 104 capacity-dmips-mhz = <1024>;
105 clocks = <&kryocc 1>; 105 clocks = <&kryocc 1>;
106 interconnects = <&cbf 106 interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>;
107 operating-points-v2 = 107 operating-points-v2 = <&cluster1_opp>;
108 #cooling-cells = <2>; 108 #cooling-cells = <2>;
109 next-level-cache = <&L 109 next-level-cache = <&L2_1>;
110 }; 110 };
111 111
112 cpu-map { 112 cpu-map {
113 cluster0 { 113 cluster0 {
114 core0 { 114 core0 {
115 cpu = 115 cpu = <&CPU0>;
116 }; 116 };
117 117
118 core1 { 118 core1 {
119 cpu = 119 cpu = <&CPU1>;
120 }; 120 };
121 }; 121 };
122 122
123 cluster1 { 123 cluster1 {
124 core0 { 124 core0 {
125 cpu = 125 cpu = <&CPU2>;
126 }; 126 };
127 127
128 core1 { 128 core1 {
129 cpu = 129 cpu = <&CPU3>;
130 }; 130 };
131 }; 131 };
132 }; 132 };
133 133
134 idle-states { 134 idle-states {
135 entry-method = "psci"; 135 entry-method = "psci";
136 136
137 CPU_SLEEP_0: cpu-sleep 137 CPU_SLEEP_0: cpu-sleep-0 {
138 compatible = " 138 compatible = "arm,idle-state";
139 idle-state-nam 139 idle-state-name = "standalone-power-collapse";
140 arm,psci-suspe 140 arm,psci-suspend-param = <0x00000004>;
141 entry-latency- 141 entry-latency-us = <130>;
142 exit-latency-u 142 exit-latency-us = <80>;
143 min-residency- 143 min-residency-us = <300>;
144 }; 144 };
145 }; 145 };
146 }; 146 };
147 147
148 cluster0_opp: opp-table-cluster0 { 148 cluster0_opp: opp-table-cluster0 {
149 compatible = "operating-points 149 compatible = "operating-points-v2-kryo-cpu";
150 nvmem-cells = <&speedbin_efuse 150 nvmem-cells = <&speedbin_efuse>;
151 opp-shared; 151 opp-shared;
152 152
153 /* Nominal fmax for now */ 153 /* Nominal fmax for now */
154 opp-307200000 { 154 opp-307200000 {
155 opp-hz = /bits/ 64 <30 155 opp-hz = /bits/ 64 <307200000>;
156 opp-supported-hw = <0x 156 opp-supported-hw = <0xf>;
157 clock-latency-ns = <20 157 clock-latency-ns = <200000>;
158 opp-peak-kBps = <30720 158 opp-peak-kBps = <307200>;
159 }; 159 };
160 opp-422400000 { 160 opp-422400000 {
161 opp-hz = /bits/ 64 <42 161 opp-hz = /bits/ 64 <422400000>;
162 opp-supported-hw = <0x 162 opp-supported-hw = <0xf>;
163 clock-latency-ns = <20 163 clock-latency-ns = <200000>;
164 opp-peak-kBps = <30720 164 opp-peak-kBps = <307200>;
165 }; 165 };
166 opp-480000000 { 166 opp-480000000 {
167 opp-hz = /bits/ 64 <48 167 opp-hz = /bits/ 64 <480000000>;
168 opp-supported-hw = <0x 168 opp-supported-hw = <0xf>;
169 clock-latency-ns = <20 169 clock-latency-ns = <200000>;
170 opp-peak-kBps = <30720 170 opp-peak-kBps = <307200>;
171 }; 171 };
172 opp-556800000 { 172 opp-556800000 {
173 opp-hz = /bits/ 64 <55 173 opp-hz = /bits/ 64 <556800000>;
174 opp-supported-hw = <0x 174 opp-supported-hw = <0xf>;
175 clock-latency-ns = <20 175 clock-latency-ns = <200000>;
176 opp-peak-kBps = <30720 176 opp-peak-kBps = <307200>;
177 }; 177 };
178 opp-652800000 { 178 opp-652800000 {
179 opp-hz = /bits/ 64 <65 179 opp-hz = /bits/ 64 <652800000>;
180 opp-supported-hw = <0x 180 opp-supported-hw = <0xf>;
181 clock-latency-ns = <20 181 clock-latency-ns = <200000>;
182 opp-peak-kBps = <38400 182 opp-peak-kBps = <384000>;
183 }; 183 };
184 opp-729600000 { 184 opp-729600000 {
185 opp-hz = /bits/ 64 <72 185 opp-hz = /bits/ 64 <729600000>;
186 opp-supported-hw = <0x 186 opp-supported-hw = <0xf>;
187 clock-latency-ns = <20 187 clock-latency-ns = <200000>;
188 opp-peak-kBps = <46080 188 opp-peak-kBps = <460800>;
189 }; 189 };
190 opp-844800000 { 190 opp-844800000 {
191 opp-hz = /bits/ 64 <84 191 opp-hz = /bits/ 64 <844800000>;
192 opp-supported-hw = <0x 192 opp-supported-hw = <0xf>;
193 clock-latency-ns = <20 193 clock-latency-ns = <200000>;
194 opp-peak-kBps = <53760 194 opp-peak-kBps = <537600>;
195 }; 195 };
196 opp-960000000 { 196 opp-960000000 {
197 opp-hz = /bits/ 64 <96 197 opp-hz = /bits/ 64 <960000000>;
198 opp-supported-hw = <0x 198 opp-supported-hw = <0xf>;
199 clock-latency-ns = <20 199 clock-latency-ns = <200000>;
200 opp-peak-kBps = <67200 200 opp-peak-kBps = <672000>;
201 }; 201 };
202 opp-1036800000 { 202 opp-1036800000 {
203 opp-hz = /bits/ 64 <10 203 opp-hz = /bits/ 64 <1036800000>;
204 opp-supported-hw = <0x 204 opp-supported-hw = <0xf>;
205 clock-latency-ns = <20 205 clock-latency-ns = <200000>;
206 opp-peak-kBps = <67200 206 opp-peak-kBps = <672000>;
207 }; 207 };
208 opp-1113600000 { 208 opp-1113600000 {
209 opp-hz = /bits/ 64 <11 209 opp-hz = /bits/ 64 <1113600000>;
210 opp-supported-hw = <0x 210 opp-supported-hw = <0xf>;
211 clock-latency-ns = <20 211 clock-latency-ns = <200000>;
212 opp-peak-kBps = <82560 212 opp-peak-kBps = <825600>;
213 }; 213 };
214 opp-1190400000 { 214 opp-1190400000 {
215 opp-hz = /bits/ 64 <11 215 opp-hz = /bits/ 64 <1190400000>;
216 opp-supported-hw = <0x 216 opp-supported-hw = <0xf>;
217 clock-latency-ns = <20 217 clock-latency-ns = <200000>;
218 opp-peak-kBps = <82560 218 opp-peak-kBps = <825600>;
219 }; 219 };
220 opp-1228800000 { 220 opp-1228800000 {
221 opp-hz = /bits/ 64 <12 221 opp-hz = /bits/ 64 <1228800000>;
222 opp-supported-hw = <0x 222 opp-supported-hw = <0xf>;
223 clock-latency-ns = <20 223 clock-latency-ns = <200000>;
224 opp-peak-kBps = <90240 224 opp-peak-kBps = <902400>;
225 }; 225 };
226 opp-1324800000 { 226 opp-1324800000 {
227 opp-hz = /bits/ 64 <13 227 opp-hz = /bits/ 64 <1324800000>;
228 opp-supported-hw = <0x 228 opp-supported-hw = <0xd>;
229 clock-latency-ns = <20 229 clock-latency-ns = <200000>;
230 opp-peak-kBps = <10560 230 opp-peak-kBps = <1056000>;
231 }; 231 };
232 opp-1363200000 { 232 opp-1363200000 {
233 opp-hz = /bits/ 64 <13 233 opp-hz = /bits/ 64 <1363200000>;
234 opp-supported-hw = <0x 234 opp-supported-hw = <0x2>;
235 clock-latency-ns = <20 235 clock-latency-ns = <200000>;
236 opp-peak-kBps = <11328 236 opp-peak-kBps = <1132800>;
237 }; 237 };
238 opp-1401600000 { 238 opp-1401600000 {
239 opp-hz = /bits/ 64 <14 239 opp-hz = /bits/ 64 <1401600000>;
240 opp-supported-hw = <0x 240 opp-supported-hw = <0xd>;
241 clock-latency-ns = <20 241 clock-latency-ns = <200000>;
242 opp-peak-kBps = <11328 242 opp-peak-kBps = <1132800>;
243 }; 243 };
244 opp-1478400000 { 244 opp-1478400000 {
245 opp-hz = /bits/ 64 <14 245 opp-hz = /bits/ 64 <1478400000>;
246 opp-supported-hw = <0x 246 opp-supported-hw = <0x9>;
247 clock-latency-ns = <20 247 clock-latency-ns = <200000>;
248 opp-peak-kBps = <11904 248 opp-peak-kBps = <1190400>;
249 }; 249 };
250 opp-1497600000 { 250 opp-1497600000 {
251 opp-hz = /bits/ 64 <14 251 opp-hz = /bits/ 64 <1497600000>;
252 opp-supported-hw = <0x 252 opp-supported-hw = <0x04>;
253 clock-latency-ns = <20 253 clock-latency-ns = <200000>;
254 opp-peak-kBps = <13056 254 opp-peak-kBps = <1305600>;
255 }; 255 };
256 opp-1593600000 { 256 opp-1593600000 {
257 opp-hz = /bits/ 64 <15 257 opp-hz = /bits/ 64 <1593600000>;
258 opp-supported-hw = <0x 258 opp-supported-hw = <0x9>;
259 clock-latency-ns = <20 259 clock-latency-ns = <200000>;
260 opp-peak-kBps = <13824 260 opp-peak-kBps = <1382400>;
261 }; 261 };
262 }; 262 };
263 263
264 cluster1_opp: opp-table-cluster1 { 264 cluster1_opp: opp-table-cluster1 {
265 compatible = "operating-points 265 compatible = "operating-points-v2-kryo-cpu";
266 nvmem-cells = <&speedbin_efuse 266 nvmem-cells = <&speedbin_efuse>;
267 opp-shared; 267 opp-shared;
268 268
269 /* Nominal fmax for now */ 269 /* Nominal fmax for now */
270 opp-307200000 { 270 opp-307200000 {
271 opp-hz = /bits/ 64 <30 271 opp-hz = /bits/ 64 <307200000>;
272 opp-supported-hw = <0x 272 opp-supported-hw = <0xf>;
273 clock-latency-ns = <20 273 clock-latency-ns = <200000>;
274 opp-peak-kBps = <30720 274 opp-peak-kBps = <307200>;
275 }; 275 };
276 opp-403200000 { 276 opp-403200000 {
277 opp-hz = /bits/ 64 <40 277 opp-hz = /bits/ 64 <403200000>;
278 opp-supported-hw = <0x 278 opp-supported-hw = <0xf>;
279 clock-latency-ns = <20 279 clock-latency-ns = <200000>;
280 opp-peak-kBps = <30720 280 opp-peak-kBps = <307200>;
281 }; 281 };
282 opp-480000000 { 282 opp-480000000 {
283 opp-hz = /bits/ 64 <48 283 opp-hz = /bits/ 64 <480000000>;
284 opp-supported-hw = <0x 284 opp-supported-hw = <0xf>;
285 clock-latency-ns = <20 285 clock-latency-ns = <200000>;
286 opp-peak-kBps = <30720 286 opp-peak-kBps = <307200>;
287 }; 287 };
288 opp-556800000 { 288 opp-556800000 {
289 opp-hz = /bits/ 64 <55 289 opp-hz = /bits/ 64 <556800000>;
290 opp-supported-hw = <0x 290 opp-supported-hw = <0xf>;
291 clock-latency-ns = <20 291 clock-latency-ns = <200000>;
292 opp-peak-kBps = <30720 292 opp-peak-kBps = <307200>;
293 }; 293 };
294 opp-652800000 { 294 opp-652800000 {
295 opp-hz = /bits/ 64 <65 295 opp-hz = /bits/ 64 <652800000>;
296 opp-supported-hw = <0x 296 opp-supported-hw = <0xf>;
297 clock-latency-ns = <20 297 clock-latency-ns = <200000>;
298 opp-peak-kBps = <30720 298 opp-peak-kBps = <307200>;
299 }; 299 };
300 opp-729600000 { 300 opp-729600000 {
301 opp-hz = /bits/ 64 <72 301 opp-hz = /bits/ 64 <729600000>;
302 opp-supported-hw = <0x 302 opp-supported-hw = <0xf>;
303 clock-latency-ns = <20 303 clock-latency-ns = <200000>;
304 opp-peak-kBps = <30720 304 opp-peak-kBps = <307200>;
305 }; 305 };
306 opp-806400000 { 306 opp-806400000 {
307 opp-hz = /bits/ 64 <80 307 opp-hz = /bits/ 64 <806400000>;
308 opp-supported-hw = <0x 308 opp-supported-hw = <0xf>;
309 clock-latency-ns = <20 309 clock-latency-ns = <200000>;
310 opp-peak-kBps = <38400 310 opp-peak-kBps = <384000>;
311 }; 311 };
312 opp-883200000 { 312 opp-883200000 {
313 opp-hz = /bits/ 64 <88 313 opp-hz = /bits/ 64 <883200000>;
314 opp-supported-hw = <0x 314 opp-supported-hw = <0xf>;
315 clock-latency-ns = <20 315 clock-latency-ns = <200000>;
316 opp-peak-kBps = <46080 316 opp-peak-kBps = <460800>;
317 }; 317 };
318 opp-940800000 { 318 opp-940800000 {
319 opp-hz = /bits/ 64 <94 319 opp-hz = /bits/ 64 <940800000>;
320 opp-supported-hw = <0x 320 opp-supported-hw = <0xf>;
321 clock-latency-ns = <20 321 clock-latency-ns = <200000>;
322 opp-peak-kBps = <53760 322 opp-peak-kBps = <537600>;
323 }; 323 };
324 opp-1036800000 { 324 opp-1036800000 {
325 opp-hz = /bits/ 64 <10 325 opp-hz = /bits/ 64 <1036800000>;
326 opp-supported-hw = <0x 326 opp-supported-hw = <0xf>;
327 clock-latency-ns = <20 327 clock-latency-ns = <200000>;
328 opp-peak-kBps = <59520 328 opp-peak-kBps = <595200>;
329 }; 329 };
330 opp-1113600000 { 330 opp-1113600000 {
331 opp-hz = /bits/ 64 <11 331 opp-hz = /bits/ 64 <1113600000>;
332 opp-supported-hw = <0x 332 opp-supported-hw = <0xf>;
333 clock-latency-ns = <20 333 clock-latency-ns = <200000>;
334 opp-peak-kBps = <67200 334 opp-peak-kBps = <672000>;
335 }; 335 };
336 opp-1190400000 { 336 opp-1190400000 {
337 opp-hz = /bits/ 64 <11 337 opp-hz = /bits/ 64 <1190400000>;
338 opp-supported-hw = <0x 338 opp-supported-hw = <0xf>;
339 clock-latency-ns = <20 339 clock-latency-ns = <200000>;
340 opp-peak-kBps = <67200 340 opp-peak-kBps = <672000>;
341 }; 341 };
342 opp-1248000000 { 342 opp-1248000000 {
343 opp-hz = /bits/ 64 <12 343 opp-hz = /bits/ 64 <1248000000>;
344 opp-supported-hw = <0x 344 opp-supported-hw = <0xf>;
345 clock-latency-ns = <20 345 clock-latency-ns = <200000>;
346 opp-peak-kBps = <74880 346 opp-peak-kBps = <748800>;
347 }; 347 };
348 opp-1324800000 { 348 opp-1324800000 {
349 opp-hz = /bits/ 64 <13 349 opp-hz = /bits/ 64 <1324800000>;
350 opp-supported-hw = <0x 350 opp-supported-hw = <0xf>;
351 clock-latency-ns = <20 351 clock-latency-ns = <200000>;
352 opp-peak-kBps = <82560 352 opp-peak-kBps = <825600>;
353 }; 353 };
354 opp-1401600000 { 354 opp-1401600000 {
355 opp-hz = /bits/ 64 <14 355 opp-hz = /bits/ 64 <1401600000>;
356 opp-supported-hw = <0x 356 opp-supported-hw = <0xf>;
357 clock-latency-ns = <20 357 clock-latency-ns = <200000>;
358 opp-peak-kBps = <90240 358 opp-peak-kBps = <902400>;
359 }; 359 };
360 opp-1478400000 { 360 opp-1478400000 {
361 opp-hz = /bits/ 64 <14 361 opp-hz = /bits/ 64 <1478400000>;
362 opp-supported-hw = <0x 362 opp-supported-hw = <0xf>;
363 clock-latency-ns = <20 363 clock-latency-ns = <200000>;
364 opp-peak-kBps = <97920 364 opp-peak-kBps = <979200>;
365 }; 365 };
366 opp-1555200000 { 366 opp-1555200000 {
367 opp-hz = /bits/ 64 <15 367 opp-hz = /bits/ 64 <1555200000>;
368 opp-supported-hw = <0x 368 opp-supported-hw = <0xf>;
369 clock-latency-ns = <20 369 clock-latency-ns = <200000>;
370 opp-peak-kBps = <10560 370 opp-peak-kBps = <1056000>;
371 }; 371 };
372 opp-1632000000 { 372 opp-1632000000 {
373 opp-hz = /bits/ 64 <16 373 opp-hz = /bits/ 64 <1632000000>;
374 opp-supported-hw = <0x 374 opp-supported-hw = <0xf>;
375 clock-latency-ns = <20 375 clock-latency-ns = <200000>;
376 opp-peak-kBps = <11904 376 opp-peak-kBps = <1190400>;
377 }; 377 };
378 opp-1708800000 { 378 opp-1708800000 {
379 opp-hz = /bits/ 64 <17 379 opp-hz = /bits/ 64 <1708800000>;
380 opp-supported-hw = <0x 380 opp-supported-hw = <0xf>;
381 clock-latency-ns = <20 381 clock-latency-ns = <200000>;
382 opp-peak-kBps = <12288 382 opp-peak-kBps = <1228800>;
383 }; 383 };
384 opp-1785600000 { 384 opp-1785600000 {
385 opp-hz = /bits/ 64 <17 385 opp-hz = /bits/ 64 <1785600000>;
386 opp-supported-hw = <0x 386 opp-supported-hw = <0xf>;
387 clock-latency-ns = <20 387 clock-latency-ns = <200000>;
388 opp-peak-kBps = <13056 388 opp-peak-kBps = <1305600>;
389 }; 389 };
390 opp-1804800000 { 390 opp-1804800000 {
391 opp-hz = /bits/ 64 <18 391 opp-hz = /bits/ 64 <1804800000>;
392 opp-supported-hw = <0x 392 opp-supported-hw = <0xe>;
393 clock-latency-ns = <20 393 clock-latency-ns = <200000>;
394 opp-peak-kBps = <13056 394 opp-peak-kBps = <1305600>;
395 }; 395 };
396 opp-1824000000 { 396 opp-1824000000 {
397 opp-hz = /bits/ 64 <18 397 opp-hz = /bits/ 64 <1824000000>;
398 opp-supported-hw = <0x 398 opp-supported-hw = <0x1>;
399 clock-latency-ns = <20 399 clock-latency-ns = <200000>;
400 opp-peak-kBps = <13824 400 opp-peak-kBps = <1382400>;
401 }; 401 };
402 opp-1900800000 { 402 opp-1900800000 {
403 opp-hz = /bits/ 64 <19 403 opp-hz = /bits/ 64 <1900800000>;
404 opp-supported-hw = <0x 404 opp-supported-hw = <0x4>;
405 clock-latency-ns = <20 405 clock-latency-ns = <200000>;
406 opp-peak-kBps = <13056 406 opp-peak-kBps = <1305600>;
407 }; 407 };
408 opp-1920000000 { 408 opp-1920000000 {
409 opp-hz = /bits/ 64 <19 409 opp-hz = /bits/ 64 <1920000000>;
410 opp-supported-hw = <0x 410 opp-supported-hw = <0x1>;
411 clock-latency-ns = <20 411 clock-latency-ns = <200000>;
412 opp-peak-kBps = <14592 412 opp-peak-kBps = <1459200>;
413 }; 413 };
414 opp-1996800000 { 414 opp-1996800000 {
415 opp-hz = /bits/ 64 <19 415 opp-hz = /bits/ 64 <1996800000>;
416 opp-supported-hw = <0x 416 opp-supported-hw = <0x1>;
417 clock-latency-ns = <20 417 clock-latency-ns = <200000>;
418 opp-peak-kBps = <15936 418 opp-peak-kBps = <1593600>;
419 }; 419 };
420 opp-2073600000 { 420 opp-2073600000 {
421 opp-hz = /bits/ 64 <20 421 opp-hz = /bits/ 64 <2073600000>;
422 opp-supported-hw = <0x 422 opp-supported-hw = <0x1>;
423 clock-latency-ns = <20 423 clock-latency-ns = <200000>;
424 opp-peak-kBps = <15936 424 opp-peak-kBps = <1593600>;
425 }; 425 };
426 opp-2150400000 { 426 opp-2150400000 {
427 opp-hz = /bits/ 64 <21 427 opp-hz = /bits/ 64 <2150400000>;
428 opp-supported-hw = <0x 428 opp-supported-hw = <0x1>;
429 clock-latency-ns = <20 429 clock-latency-ns = <200000>;
430 opp-peak-kBps = <15936 430 opp-peak-kBps = <1593600>;
431 }; 431 };
432 }; 432 };
433 433
434 firmware { 434 firmware {
435 scm { 435 scm {
436 compatible = "qcom,scm 436 compatible = "qcom,scm-msm8996", "qcom,scm";
437 qcom,dload-mode = <&tc 437 qcom,dload-mode = <&tcsr_2 0x13000>;
438 }; 438 };
439 }; 439 };
440 440
441 memory@80000000 { 441 memory@80000000 {
442 device_type = "memory"; 442 device_type = "memory";
443 /* We expect the bootloader to 443 /* We expect the bootloader to fill in the reg */
444 reg = <0x0 0x80000000 0x0 0x0> 444 reg = <0x0 0x80000000 0x0 0x0>;
445 }; 445 };
446 446
447 etm { 447 etm {
448 compatible = "qcom,coresight-r 448 compatible = "qcom,coresight-remote-etm";
449 449
450 out-ports { 450 out-ports {
451 port { 451 port {
452 modem_etm_out_ 452 modem_etm_out_funnel_in2: endpoint {
453 remote 453 remote-endpoint =
454 <&fu 454 <&funnel_in2_in_modem_etm>;
455 }; 455 };
456 }; 456 };
457 }; 457 };
458 }; 458 };
459 459
460 psci { 460 psci {
461 compatible = "arm,psci-1.0"; 461 compatible = "arm,psci-1.0";
462 method = "smc"; 462 method = "smc";
463 }; 463 };
464 464
465 rpm: remoteproc { 465 rpm: remoteproc {
466 compatible = "qcom,msm8996-rpm 466 compatible = "qcom,msm8996-rpm-proc", "qcom,rpm-proc";
467 467
468 glink-edge { 468 glink-edge {
469 compatible = "qcom,gli 469 compatible = "qcom,glink-rpm";
470 interrupts = <GIC_SPI 470 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
471 qcom,rpm-msg-ram = <&r 471 qcom,rpm-msg-ram = <&rpm_msg_ram>;
472 mboxes = <&apcs_glb 0> 472 mboxes = <&apcs_glb 0>;
473 473
474 rpm_requests: rpm-requ 474 rpm_requests: rpm-requests {
475 compatible = " !! 475 compatible = "qcom,rpm-msm8996";
476 qcom,glink-cha 476 qcom,glink-channels = "rpm_requests";
477 477
478 rpmcc: clock-c 478 rpmcc: clock-controller {
479 compat 479 compatible = "qcom,rpmcc-msm8996", "qcom,rpmcc";
480 #clock 480 #clock-cells = <1>;
481 clocks 481 clocks = <&xo_board>;
482 clock- 482 clock-names = "xo";
483 }; 483 };
484 484
485 rpmpd: power-c 485 rpmpd: power-controller {
486 compat 486 compatible = "qcom,msm8996-rpmpd";
487 #power 487 #power-domain-cells = <1>;
488 operat 488 operating-points-v2 = <&rpmpd_opp_table>;
489 489
490 rpmpd_ 490 rpmpd_opp_table: opp-table {
491 491 compatible = "operating-points-v2";
492 492
493 493 rpmpd_opp1: opp1 {
494 494 opp-level = <1>;
495 495 };
496 496
497 497 rpmpd_opp2: opp2 {
498 498 opp-level = <2>;
499 499 };
500 500
501 501 rpmpd_opp3: opp3 {
502 502 opp-level = <3>;
503 503 };
504 504
505 505 rpmpd_opp4: opp4 {
506 506 opp-level = <4>;
507 507 };
508 508
509 509 rpmpd_opp5: opp5 {
510 510 opp-level = <5>;
511 511 };
512 512
513 513 rpmpd_opp6: opp6 {
514 514 opp-level = <6>;
515 515 };
516 }; 516 };
517 }; 517 };
518 }; 518 };
519 }; 519 };
520 }; 520 };
521 521
522 reserved-memory { 522 reserved-memory {
523 #address-cells = <2>; 523 #address-cells = <2>;
524 #size-cells = <2>; 524 #size-cells = <2>;
525 ranges; 525 ranges;
526 526
527 hyp_mem: memory@85800000 { 527 hyp_mem: memory@85800000 {
528 reg = <0x0 0x85800000 528 reg = <0x0 0x85800000 0x0 0x600000>;
529 no-map; 529 no-map;
530 }; 530 };
531 531
532 xbl_mem: memory@85e00000 { 532 xbl_mem: memory@85e00000 {
533 reg = <0x0 0x85e00000 533 reg = <0x0 0x85e00000 0x0 0x200000>;
534 no-map; 534 no-map;
535 }; 535 };
536 536
537 smem_mem: smem-mem@86000000 { 537 smem_mem: smem-mem@86000000 {
538 reg = <0x0 0x86000000 538 reg = <0x0 0x86000000 0x0 0x200000>;
539 no-map; 539 no-map;
540 }; 540 };
541 541
542 tz_mem: memory@86200000 { 542 tz_mem: memory@86200000 {
543 reg = <0x0 0x86200000 543 reg = <0x0 0x86200000 0x0 0x2600000>;
544 no-map; 544 no-map;
545 }; 545 };
546 546
547 rmtfs_mem: rmtfs { 547 rmtfs_mem: rmtfs {
548 compatible = "qcom,rmt 548 compatible = "qcom,rmtfs-mem";
549 549
550 size = <0x0 0x200000>; 550 size = <0x0 0x200000>;
551 alloc-ranges = <0x0 0x 551 alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
552 no-map; 552 no-map;
553 553
554 qcom,client-id = <1>; 554 qcom,client-id = <1>;
555 qcom,vmid = <QCOM_SCM_ 555 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>;
556 }; 556 };
557 557
558 mpss_mem: mpss@88800000 { 558 mpss_mem: mpss@88800000 {
559 reg = <0x0 0x88800000 559 reg = <0x0 0x88800000 0x0 0x6200000>;
560 no-map; 560 no-map;
561 }; 561 };
562 562
563 adsp_mem: adsp@8ea00000 { 563 adsp_mem: adsp@8ea00000 {
564 reg = <0x0 0x8ea00000 564 reg = <0x0 0x8ea00000 0x0 0x1b00000>;
565 no-map; 565 no-map;
566 }; 566 };
567 567
568 slpi_mem: slpi@90500000 { 568 slpi_mem: slpi@90500000 {
569 reg = <0x0 0x90500000 569 reg = <0x0 0x90500000 0x0 0xa00000>;
570 no-map; 570 no-map;
571 }; 571 };
572 572
573 gpu_mem: gpu@90f00000 { 573 gpu_mem: gpu@90f00000 {
574 compatible = "shared-d 574 compatible = "shared-dma-pool";
575 reg = <0x0 0x90f00000 575 reg = <0x0 0x90f00000 0x0 0x100000>;
576 no-map; 576 no-map;
577 }; 577 };
578 578
579 venus_mem: venus@91000000 { 579 venus_mem: venus@91000000 {
580 reg = <0x0 0x91000000 580 reg = <0x0 0x91000000 0x0 0x500000>;
581 no-map; 581 no-map;
582 }; 582 };
583 583
584 mba_mem: mba@91500000 { 584 mba_mem: mba@91500000 {
585 reg = <0x0 0x91500000 585 reg = <0x0 0x91500000 0x0 0x200000>;
586 no-map; 586 no-map;
587 }; 587 };
588 588
589 mdata_mem: mpss-metadata { 589 mdata_mem: mpss-metadata {
590 alloc-ranges = <0x0 0x 590 alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>;
591 size = <0x0 0x4000>; 591 size = <0x0 0x4000>;
592 no-map; 592 no-map;
593 }; 593 };
594 }; 594 };
595 595
596 smem { 596 smem {
597 compatible = "qcom,smem"; 597 compatible = "qcom,smem";
598 memory-region = <&smem_mem>; 598 memory-region = <&smem_mem>;
599 hwlocks = <&tcsr_mutex 3>; 599 hwlocks = <&tcsr_mutex 3>;
600 }; 600 };
601 601
602 smp2p-adsp { 602 smp2p-adsp {
603 compatible = "qcom,smp2p"; 603 compatible = "qcom,smp2p";
604 qcom,smem = <443>, <429>; 604 qcom,smem = <443>, <429>;
605 605
606 interrupts = <GIC_SPI 158 IRQ_ 606 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
607 607
608 mboxes = <&apcs_glb 10>; 608 mboxes = <&apcs_glb 10>;
609 609
610 qcom,local-pid = <0>; 610 qcom,local-pid = <0>;
611 qcom,remote-pid = <2>; 611 qcom,remote-pid = <2>;
612 612
613 adsp_smp2p_out: master-kernel 613 adsp_smp2p_out: master-kernel {
614 qcom,entry-name = "mas 614 qcom,entry-name = "master-kernel";
615 #qcom,smem-state-cells 615 #qcom,smem-state-cells = <1>;
616 }; 616 };
617 617
618 adsp_smp2p_in: slave-kernel { 618 adsp_smp2p_in: slave-kernel {
619 qcom,entry-name = "sla 619 qcom,entry-name = "slave-kernel";
620 620
621 interrupt-controller; 621 interrupt-controller;
622 #interrupt-cells = <2> 622 #interrupt-cells = <2>;
623 }; 623 };
624 }; 624 };
625 625
626 smp2p-mpss { 626 smp2p-mpss {
627 compatible = "qcom,smp2p"; 627 compatible = "qcom,smp2p";
628 qcom,smem = <435>, <428>; 628 qcom,smem = <435>, <428>;
629 629
630 interrupts = <GIC_SPI 451 IRQ_ 630 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
631 631
632 mboxes = <&apcs_glb 14>; 632 mboxes = <&apcs_glb 14>;
633 633
634 qcom,local-pid = <0>; 634 qcom,local-pid = <0>;
635 qcom,remote-pid = <1>; 635 qcom,remote-pid = <1>;
636 636
637 mpss_smp2p_out: master-kernel 637 mpss_smp2p_out: master-kernel {
638 qcom,entry-name = "mas 638 qcom,entry-name = "master-kernel";
639 #qcom,smem-state-cells 639 #qcom,smem-state-cells = <1>;
640 }; 640 };
641 641
642 mpss_smp2p_in: slave-kernel { 642 mpss_smp2p_in: slave-kernel {
643 qcom,entry-name = "sla 643 qcom,entry-name = "slave-kernel";
644 644
645 interrupt-controller; 645 interrupt-controller;
646 #interrupt-cells = <2> 646 #interrupt-cells = <2>;
647 }; 647 };
648 }; 648 };
649 649
650 smp2p-slpi { 650 smp2p-slpi {
651 compatible = "qcom,smp2p"; 651 compatible = "qcom,smp2p";
652 qcom,smem = <481>, <430>; 652 qcom,smem = <481>, <430>;
653 653
654 interrupts = <GIC_SPI 178 IRQ_ 654 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
655 655
656 mboxes = <&apcs_glb 26>; 656 mboxes = <&apcs_glb 26>;
657 657
658 qcom,local-pid = <0>; 658 qcom,local-pid = <0>;
659 qcom,remote-pid = <3>; 659 qcom,remote-pid = <3>;
660 660
661 slpi_smp2p_out: master-kernel 661 slpi_smp2p_out: master-kernel {
662 qcom,entry-name = "mas 662 qcom,entry-name = "master-kernel";
663 #qcom,smem-state-cells 663 #qcom,smem-state-cells = <1>;
664 }; 664 };
665 665
666 slpi_smp2p_in: slave-kernel { 666 slpi_smp2p_in: slave-kernel {
667 qcom,entry-name = "sla 667 qcom,entry-name = "slave-kernel";
668 668
669 interrupt-controller; 669 interrupt-controller;
670 #interrupt-cells = <2> 670 #interrupt-cells = <2>;
671 }; 671 };
672 }; 672 };
673 673
674 soc: soc@0 { 674 soc: soc@0 {
675 #address-cells = <1>; 675 #address-cells = <1>;
676 #size-cells = <1>; 676 #size-cells = <1>;
677 ranges = <0 0 0 0xffffffff>; 677 ranges = <0 0 0 0xffffffff>;
678 compatible = "simple-bus"; 678 compatible = "simple-bus";
679 679
680 pcie_phy: phy-wrapper@34000 { 680 pcie_phy: phy-wrapper@34000 {
681 compatible = "qcom,msm 681 compatible = "qcom,msm8996-qmp-pcie-phy";
682 reg = <0x00034000 0x48 682 reg = <0x00034000 0x488>;
683 #address-cells = <1>; 683 #address-cells = <1>;
684 #size-cells = <1>; 684 #size-cells = <1>;
685 ranges = <0x0 0x000340 685 ranges = <0x0 0x00034000 0x4000>;
686 686
687 clocks = <&gcc GCC_PCI 687 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
688 <&gcc GCC_PCIE 688 <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
689 <&gcc GCC_PCIE 689 <&gcc GCC_PCIE_CLKREF_CLK>;
690 clock-names = "aux", " 690 clock-names = "aux", "cfg_ahb", "ref";
691 691
692 resets = <&gcc GCC_PCI 692 resets = <&gcc GCC_PCIE_PHY_BCR>,
693 <&gcc GCC_PCIE 693 <&gcc GCC_PCIE_PHY_COM_BCR>,
694 <&gcc GCC_PCIE 694 <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
695 reset-names = "phy", " 695 reset-names = "phy", "common", "cfg";
696 696
697 status = "disabled"; 697 status = "disabled";
698 698
699 pciephy_0: phy@1000 { 699 pciephy_0: phy@1000 {
700 reg = <0x1000 700 reg = <0x1000 0x130>,
701 <0x1200 701 <0x1200 0x200>,
702 <0x1400 702 <0x1400 0x1dc>;
703 703
704 clocks = <&gcc 704 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
705 clock-names = 705 clock-names = "pipe0";
706 resets = <&gcc 706 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
707 reset-names = 707 reset-names = "lane0";
708 708
709 #clock-cells = 709 #clock-cells = <0>;
710 clock-output-n 710 clock-output-names = "pcie_0_pipe_clk_src";
711 711
712 #phy-cells = < 712 #phy-cells = <0>;
713 }; 713 };
714 714
715 pciephy_1: phy@2000 { 715 pciephy_1: phy@2000 {
716 reg = <0x2000 716 reg = <0x2000 0x130>,
717 <0x2200 717 <0x2200 0x200>,
718 <0x2400 718 <0x2400 0x1dc>;
719 719
720 clocks = <&gcc 720 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
721 clock-names = 721 clock-names = "pipe1";
722 resets = <&gcc 722 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
723 reset-names = 723 reset-names = "lane1";
724 724
725 #clock-cells = 725 #clock-cells = <0>;
726 clock-output-n 726 clock-output-names = "pcie_1_pipe_clk_src";
727 727
728 #phy-cells = < 728 #phy-cells = <0>;
729 }; 729 };
730 730
731 pciephy_2: phy@3000 { 731 pciephy_2: phy@3000 {
732 reg = <0x3000 732 reg = <0x3000 0x130>,
733 <0x3200 733 <0x3200 0x200>,
734 <0x3400 734 <0x3400 0x1dc>;
735 735
736 clocks = <&gcc 736 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
737 clock-names = 737 clock-names = "pipe2";
738 resets = <&gcc 738 resets = <&gcc GCC_PCIE_2_PHY_BCR>;
739 reset-names = 739 reset-names = "lane2";
740 740
741 #clock-cells = 741 #clock-cells = <0>;
742 clock-output-n 742 clock-output-names = "pcie_2_pipe_clk_src";
743 743
744 #phy-cells = < 744 #phy-cells = <0>;
745 }; 745 };
746 }; 746 };
747 747
748 rpm_msg_ram: sram@68000 { 748 rpm_msg_ram: sram@68000 {
749 compatible = "qcom,rpm 749 compatible = "qcom,rpm-msg-ram";
750 reg = <0x00068000 0x60 750 reg = <0x00068000 0x6000>;
751 }; 751 };
752 752
753 qfprom@74000 { 753 qfprom@74000 {
754 compatible = "qcom,msm 754 compatible = "qcom,msm8996-qfprom", "qcom,qfprom";
755 reg = <0x00074000 0x8f 755 reg = <0x00074000 0x8ff>;
756 #address-cells = <1>; 756 #address-cells = <1>;
757 #size-cells = <1>; 757 #size-cells = <1>;
758 758
759 qusb2p_hstx_trim: hstx !! 759 qusb2p_hstx_trim: hstx_trim@24e {
760 reg = <0x24e 0 760 reg = <0x24e 0x2>;
761 bits = <5 4>; 761 bits = <5 4>;
762 }; 762 };
763 763
764 qusb2s_hstx_trim: hstx !! 764 qusb2s_hstx_trim: hstx_trim@24f {
765 reg = <0x24f 0 765 reg = <0x24f 0x1>;
766 bits = <1 4>; 766 bits = <1 4>;
767 }; 767 };
768 768
769 speedbin_efuse: speedb 769 speedbin_efuse: speedbin@133 {
770 reg = <0x133 0 770 reg = <0x133 0x1>;
771 bits = <5 3>; 771 bits = <5 3>;
772 }; 772 };
773 }; 773 };
774 774
775 rng: rng@83000 { 775 rng: rng@83000 {
776 compatible = "qcom,prn 776 compatible = "qcom,prng-ee";
777 reg = <0x00083000 0x10 777 reg = <0x00083000 0x1000>;
778 clocks = <&gcc GCC_PRN 778 clocks = <&gcc GCC_PRNG_AHB_CLK>;
779 clock-names = "core"; 779 clock-names = "core";
780 }; 780 };
781 781
782 gcc: clock-controller@300000 { 782 gcc: clock-controller@300000 {
783 compatible = "qcom,gcc 783 compatible = "qcom,gcc-msm8996";
784 #clock-cells = <1>; 784 #clock-cells = <1>;
785 #reset-cells = <1>; 785 #reset-cells = <1>;
786 #power-domain-cells = 786 #power-domain-cells = <1>;
787 reg = <0x00300000 0x90 787 reg = <0x00300000 0x90000>;
788 788
789 clocks = <&rpmcc RPM_S 789 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
790 <&rpmcc RPM_S 790 <&rpmcc RPM_SMD_LN_BB_CLK>,
791 <&sleep_clk>, 791 <&sleep_clk>,
792 <&pciephy_0>, 792 <&pciephy_0>,
793 <&pciephy_1>, 793 <&pciephy_1>,
794 <&pciephy_2>, 794 <&pciephy_2>,
795 <&usb3phy>, !! 795 <&ssusb_phy_0>,
796 <&ufsphy 0>, !! 796 <&ufsphy_lane 0>,
797 <&ufsphy 1>, !! 797 <&ufsphy_lane 1>,
798 <&ufsphy 2>; !! 798 <&ufsphy_lane 2>;
799 clock-names = "cxo", 799 clock-names = "cxo",
800 "cxo2", 800 "cxo2",
801 "sleep_c 801 "sleep_clk",
802 "pcie_0_ 802 "pcie_0_pipe_clk_src",
803 "pcie_1_ 803 "pcie_1_pipe_clk_src",
804 "pcie_2_ 804 "pcie_2_pipe_clk_src",
805 "usb3_ph 805 "usb3_phy_pipe_clk_src",
806 "ufs_rx_ 806 "ufs_rx_symbol_0_clk_src",
807 "ufs_rx_ 807 "ufs_rx_symbol_1_clk_src",
808 "ufs_tx_ 808 "ufs_tx_symbol_0_clk_src";
809 }; 809 };
810 810
811 bimc: interconnect@408000 { 811 bimc: interconnect@408000 {
812 compatible = "qcom,msm 812 compatible = "qcom,msm8996-bimc";
813 reg = <0x00408000 0x5a 813 reg = <0x00408000 0x5a000>;
814 #interconnect-cells = 814 #interconnect-cells = <1>;
>> 815 clock-names = "bus", "bus_a";
>> 816 clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
>> 817 <&rpmcc RPM_SMD_BIMC_A_CLK>;
815 }; 818 };
816 819
817 tsens0: thermal-sensor@4a9000 820 tsens0: thermal-sensor@4a9000 {
818 compatible = "qcom,msm 821 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
819 reg = <0x004a9000 0x10 822 reg = <0x004a9000 0x1000>, /* TM */
820 <0x004a8000 0x10 823 <0x004a8000 0x1000>; /* SROT */
821 #qcom,sensors = <13>; 824 #qcom,sensors = <13>;
822 interrupts = <GIC_SPI 825 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
823 <GIC_SPI 826 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
824 interrupt-names = "upl 827 interrupt-names = "uplow", "critical";
825 #thermal-sensor-cells 828 #thermal-sensor-cells = <1>;
826 }; 829 };
827 830
828 tsens1: thermal-sensor@4ad000 831 tsens1: thermal-sensor@4ad000 {
829 compatible = "qcom,msm 832 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
830 reg = <0x004ad000 0x10 833 reg = <0x004ad000 0x1000>, /* TM */
831 <0x004ac000 0x10 834 <0x004ac000 0x1000>; /* SROT */
832 #qcom,sensors = <8>; 835 #qcom,sensors = <8>;
833 interrupts = <GIC_SPI 836 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
834 <GIC_SPI 837 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
835 interrupt-names = "upl 838 interrupt-names = "uplow", "critical";
836 #thermal-sensor-cells 839 #thermal-sensor-cells = <1>;
837 }; 840 };
838 841
839 cryptobam: dma-controller@6440 842 cryptobam: dma-controller@644000 {
840 compatible = "qcom,bam 843 compatible = "qcom,bam-v1.7.0";
841 reg = <0x00644000 0x24 844 reg = <0x00644000 0x24000>;
842 interrupts = <GIC_SPI 845 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
843 clocks = <&gcc GCC_CE1 846 clocks = <&gcc GCC_CE1_CLK>;
844 clock-names = "bam_clk 847 clock-names = "bam_clk";
845 #dma-cells = <1>; 848 #dma-cells = <1>;
846 qcom,ee = <0>; 849 qcom,ee = <0>;
847 qcom,controlled-remote 850 qcom,controlled-remotely;
848 }; 851 };
849 852
850 crypto: crypto@67a000 { 853 crypto: crypto@67a000 {
851 compatible = "qcom,cry 854 compatible = "qcom,crypto-v5.4";
852 reg = <0x0067a000 0x60 855 reg = <0x0067a000 0x6000>;
853 clocks = <&gcc GCC_CE1 856 clocks = <&gcc GCC_CE1_AHB_CLK>,
854 <&gcc GCC_CE1 857 <&gcc GCC_CE1_AXI_CLK>,
855 <&gcc GCC_CE1 858 <&gcc GCC_CE1_CLK>;
856 clock-names = "iface", 859 clock-names = "iface", "bus", "core";
857 dmas = <&cryptobam 6>, 860 dmas = <&cryptobam 6>, <&cryptobam 7>;
858 dma-names = "rx", "tx" 861 dma-names = "rx", "tx";
859 }; 862 };
860 863
861 cnoc: interconnect@500000 { 864 cnoc: interconnect@500000 {
862 compatible = "qcom,msm 865 compatible = "qcom,msm8996-cnoc";
863 reg = <0x00500000 0x10 866 reg = <0x00500000 0x1000>;
864 #interconnect-cells = 867 #interconnect-cells = <1>;
>> 868 clock-names = "bus", "bus_a";
>> 869 clocks = <&rpmcc RPM_SMD_CNOC_CLK>,
>> 870 <&rpmcc RPM_SMD_CNOC_A_CLK>;
865 }; 871 };
866 872
867 snoc: interconnect@524000 { 873 snoc: interconnect@524000 {
868 compatible = "qcom,msm 874 compatible = "qcom,msm8996-snoc";
869 reg = <0x00524000 0x1c 875 reg = <0x00524000 0x1c000>;
870 #interconnect-cells = 876 #interconnect-cells = <1>;
>> 877 clock-names = "bus", "bus_a";
>> 878 clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
>> 879 <&rpmcc RPM_SMD_SNOC_A_CLK>;
871 }; 880 };
872 881
873 a0noc: interconnect@543000 { 882 a0noc: interconnect@543000 {
874 compatible = "qcom,msm 883 compatible = "qcom,msm8996-a0noc";
875 reg = <0x00543000 0x60 884 reg = <0x00543000 0x6000>;
876 #interconnect-cells = 885 #interconnect-cells = <1>;
877 clock-names = "aggre0_ 886 clock-names = "aggre0_snoc_axi",
878 "aggre0_ 887 "aggre0_cnoc_ahb",
879 "aggre0_ 888 "aggre0_noc_mpu_cfg";
880 clocks = <&gcc GCC_AGG 889 clocks = <&gcc GCC_AGGRE0_SNOC_AXI_CLK>,
881 <&gcc GCC_AGG 890 <&gcc GCC_AGGRE0_CNOC_AHB_CLK>,
882 <&gcc GCC_AGG 891 <&gcc GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK>;
883 power-domains = <&gcc 892 power-domains = <&gcc AGGRE0_NOC_GDSC>;
884 }; 893 };
885 894
886 a1noc: interconnect@562000 { 895 a1noc: interconnect@562000 {
887 compatible = "qcom,msm 896 compatible = "qcom,msm8996-a1noc";
888 reg = <0x00562000 0x50 897 reg = <0x00562000 0x5000>;
889 #interconnect-cells = 898 #interconnect-cells = <1>;
>> 899 clock-names = "bus", "bus_a";
>> 900 clocks = <&rpmcc RPM_SMD_AGGR1_NOC_CLK>,
>> 901 <&rpmcc RPM_SMD_AGGR1_NOC_A_CLK>;
890 }; 902 };
891 903
892 a2noc: interconnect@583000 { 904 a2noc: interconnect@583000 {
893 compatible = "qcom,msm 905 compatible = "qcom,msm8996-a2noc";
894 reg = <0x00583000 0x70 906 reg = <0x00583000 0x7000>;
895 #interconnect-cells = 907 #interconnect-cells = <1>;
896 clock-names = "aggre2_ !! 908 clock-names = "bus", "bus_a", "aggre2_ufs_axi", "ufs_axi";
897 clocks = <&gcc GCC_AGG !! 909 clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>,
>> 910 <&rpmcc RPM_SMD_AGGR2_NOC_A_CLK>,
>> 911 <&gcc GCC_AGGRE2_UFS_AXI_CLK>,
898 <&gcc GCC_UFS 912 <&gcc GCC_UFS_AXI_CLK>;
899 }; 913 };
900 914
901 mnoc: interconnect@5a4000 { 915 mnoc: interconnect@5a4000 {
902 compatible = "qcom,msm 916 compatible = "qcom,msm8996-mnoc";
903 reg = <0x005a4000 0x1c 917 reg = <0x005a4000 0x1c000>;
904 #interconnect-cells = 918 #interconnect-cells = <1>;
905 clock-names = "iface"; !! 919 clock-names = "bus", "bus_a", "iface";
906 clocks = <&mmcc AHB_CL !! 920 clocks = <&rpmcc RPM_SMD_MMAXI_CLK>,
>> 921 <&rpmcc RPM_SMD_MMAXI_A_CLK>,
>> 922 <&mmcc AHB_CLK_SRC>;
907 }; 923 };
908 924
909 pnoc: interconnect@5c0000 { 925 pnoc: interconnect@5c0000 {
910 compatible = "qcom,msm 926 compatible = "qcom,msm8996-pnoc";
911 reg = <0x005c0000 0x30 927 reg = <0x005c0000 0x3000>;
912 #interconnect-cells = 928 #interconnect-cells = <1>;
>> 929 clock-names = "bus", "bus_a";
>> 930 clocks = <&rpmcc RPM_SMD_PCNOC_CLK>,
>> 931 <&rpmcc RPM_SMD_PCNOC_A_CLK>;
913 }; 932 };
914 933
915 tcsr_mutex: hwlock@740000 { 934 tcsr_mutex: hwlock@740000 {
916 compatible = "qcom,tcs 935 compatible = "qcom,tcsr-mutex";
917 reg = <0x00740000 0x20 936 reg = <0x00740000 0x20000>;
918 #hwlock-cells = <1>; 937 #hwlock-cells = <1>;
919 }; 938 };
920 939
921 tcsr_1: syscon@760000 { 940 tcsr_1: syscon@760000 {
922 compatible = "qcom,tcs 941 compatible = "qcom,tcsr-msm8996", "syscon";
923 reg = <0x00760000 0x20 942 reg = <0x00760000 0x20000>;
924 }; 943 };
925 944
926 tcsr_2: syscon@7a0000 { 945 tcsr_2: syscon@7a0000 {
927 compatible = "qcom,tcs 946 compatible = "qcom,tcsr-msm8996", "syscon";
928 reg = <0x007a0000 0x18 947 reg = <0x007a0000 0x18000>;
929 }; 948 };
930 949
931 mmcc: clock-controller@8c0000 950 mmcc: clock-controller@8c0000 {
932 compatible = "qcom,mmc 951 compatible = "qcom,mmcc-msm8996";
933 #clock-cells = <1>; 952 #clock-cells = <1>;
934 #reset-cells = <1>; 953 #reset-cells = <1>;
935 #power-domain-cells = 954 #power-domain-cells = <1>;
936 reg = <0x008c0000 0x40 955 reg = <0x008c0000 0x40000>;
937 clocks = <&xo_board>, 956 clocks = <&xo_board>,
938 <&gcc GPLL0>, 957 <&gcc GPLL0>,
939 <&gcc GCC_MMS 958 <&gcc GCC_MMSS_NOC_CFG_AHB_CLK>,
940 <&mdss_dsi0_p 959 <&mdss_dsi0_phy 1>,
941 <&mdss_dsi0_p 960 <&mdss_dsi0_phy 0>,
942 <&mdss_dsi1_p 961 <&mdss_dsi1_phy 1>,
943 <&mdss_dsi1_p 962 <&mdss_dsi1_phy 0>,
944 <&mdss_hdmi_p 963 <&mdss_hdmi_phy>;
945 clock-names = "xo", 964 clock-names = "xo",
946 "gpll0", 965 "gpll0",
947 "gcc_mms 966 "gcc_mmss_noc_cfg_ahb_clk",
948 "dsi0pll 967 "dsi0pll",
949 "dsi0pll 968 "dsi0pllbyte",
950 "dsi1pll 969 "dsi1pll",
951 "dsi1pll 970 "dsi1pllbyte",
952 "hdmipll 971 "hdmipll";
953 assigned-clocks = <&mm 972 assigned-clocks = <&mmcc MMPLL9_PLL>,
954 <&mm 973 <&mmcc MMPLL1_PLL>,
955 <&mm 974 <&mmcc MMPLL3_PLL>,
956 <&mm 975 <&mmcc MMPLL4_PLL>,
957 <&mm 976 <&mmcc MMPLL5_PLL>;
958 assigned-clock-rates = 977 assigned-clock-rates = <624000000>,
959 978 <810000000>,
960 979 <980000000>,
961 980 <960000000>,
962 981 <825000000>;
963 }; 982 };
964 983
965 mdss: display-subsystem@900000 984 mdss: display-subsystem@900000 {
966 compatible = "qcom,mds 985 compatible = "qcom,mdss";
967 986
968 reg = <0x00900000 0x10 987 reg = <0x00900000 0x1000>,
969 <0x009b0000 0x10 988 <0x009b0000 0x1040>,
970 <0x009b8000 0x10 989 <0x009b8000 0x1040>;
971 reg-names = "mdss_phys 990 reg-names = "mdss_phys",
972 "vbif_phys 991 "vbif_phys",
973 "vbif_nrt_ 992 "vbif_nrt_phys";
974 993
975 power-domains = <&mmcc 994 power-domains = <&mmcc MDSS_GDSC>;
976 interrupts = <GIC_SPI 995 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
977 996
978 interrupt-controller; 997 interrupt-controller;
979 #interrupt-cells = <1> 998 #interrupt-cells = <1>;
980 999
981 clocks = <&mmcc MDSS_A 1000 clocks = <&mmcc MDSS_AHB_CLK>,
982 <&mmcc MDSS_M 1001 <&mmcc MDSS_MDP_CLK>;
983 clock-names = "iface", 1002 clock-names = "iface", "core";
984 1003
985 resets = <&mmcc MDSS_B <<
986 <<
987 #address-cells = <1>; 1004 #address-cells = <1>;
988 #size-cells = <1>; 1005 #size-cells = <1>;
989 ranges; 1006 ranges;
990 1007
991 status = "disabled"; 1008 status = "disabled";
992 1009
993 mdp: display-controlle 1010 mdp: display-controller@901000 {
994 compatible = " 1011 compatible = "qcom,msm8996-mdp5", "qcom,mdp5";
995 reg = <0x00901 1012 reg = <0x00901000 0x90000>;
996 reg-names = "m 1013 reg-names = "mdp_phys";
997 1014
998 interrupt-pare 1015 interrupt-parent = <&mdss>;
999 interrupts = < 1016 interrupts = <0>;
1000 1017
1001 clocks = <&mm 1018 clocks = <&mmcc MDSS_AHB_CLK>,
1002 <&mm 1019 <&mmcc MDSS_AXI_CLK>,
1003 <&mm 1020 <&mmcc MDSS_MDP_CLK>,
1004 <&mm 1021 <&mmcc SMMU_MDP_AXI_CLK>,
1005 <&mm 1022 <&mmcc MDSS_VSYNC_CLK>;
1006 clock-names = 1023 clock-names = "iface",
1007 1024 "bus",
1008 1025 "core",
1009 1026 "iommu",
1010 1027 "vsync";
1011 1028
1012 iommus = <&md 1029 iommus = <&mdp_smmu 0>;
1013 1030
1014 assigned-cloc 1031 assigned-clocks = <&mmcc MDSS_MDP_CLK>,
1015 <&mm 1032 <&mmcc MDSS_VSYNC_CLK>;
1016 assigned-cloc 1033 assigned-clock-rates = <300000000>,
1017 <192 1034 <19200000>;
1018 1035
1019 interconnects 1036 interconnects = <&mnoc MASTER_MDP_PORT0 &bimc SLAVE_EBI_CH0>,
1020 1037 <&mnoc MASTER_MDP_PORT1 &bimc SLAVE_EBI_CH0>,
1021 1038 <&mnoc MASTER_ROTATOR &bimc SLAVE_EBI_CH0>;
1022 interconnect- 1039 interconnect-names = "mdp0-mem", "mdp1-mem", "rotator-mem";
1023 1040
1024 ports { 1041 ports {
1025 #addr 1042 #address-cells = <1>;
1026 #size 1043 #size-cells = <0>;
1027 1044
1028 port@ 1045 port@0 {
1029 1046 reg = <0>;
1030 1047 mdp5_intf3_out: endpoint {
1031 1048 remote-endpoint = <&mdss_hdmi_in>;
1032 1049 };
1033 }; 1050 };
1034 1051
1035 port@ 1052 port@1 {
1036 1053 reg = <1>;
1037 1054 mdp5_intf1_out: endpoint {
1038 1055 remote-endpoint = <&mdss_dsi0_in>;
1039 1056 };
1040 }; 1057 };
1041 1058
1042 port@ 1059 port@2 {
1043 1060 reg = <2>;
1044 1061 mdp5_intf2_out: endpoint {
1045 1062 remote-endpoint = <&mdss_dsi1_in>;
1046 1063 };
1047 }; 1064 };
1048 }; 1065 };
1049 }; 1066 };
1050 1067
1051 mdss_dsi0: dsi@994000 1068 mdss_dsi0: dsi@994000 {
1052 compatible = 1069 compatible = "qcom,msm8996-dsi-ctrl",
1053 1070 "qcom,mdss-dsi-ctrl";
1054 reg = <0x0099 1071 reg = <0x00994000 0x400>;
1055 reg-names = " 1072 reg-names = "dsi_ctrl";
1056 1073
1057 interrupt-par 1074 interrupt-parent = <&mdss>;
1058 interrupts = 1075 interrupts = <4>;
1059 1076
1060 clocks = <&mm 1077 clocks = <&mmcc MDSS_MDP_CLK>,
1061 <&mm 1078 <&mmcc MDSS_BYTE0_CLK>,
1062 <&mm 1079 <&mmcc MDSS_AHB_CLK>,
1063 <&mm 1080 <&mmcc MDSS_AXI_CLK>,
1064 <&mm 1081 <&mmcc MMSS_MISC_AHB_CLK>,
1065 <&mm 1082 <&mmcc MDSS_PCLK0_CLK>,
1066 <&mm 1083 <&mmcc MDSS_ESC0_CLK>;
1067 clock-names = 1084 clock-names = "mdp_core",
1068 1085 "byte",
1069 1086 "iface",
1070 1087 "bus",
1071 1088 "core_mmss",
1072 1089 "pixel",
1073 1090 "core";
1074 assigned-cloc 1091 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>;
1075 assigned-cloc 1092 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
1076 1093
1077 phys = <&mdss 1094 phys = <&mdss_dsi0_phy>;
1078 status = "dis 1095 status = "disabled";
1079 1096
1080 #address-cell 1097 #address-cells = <1>;
1081 #size-cells = 1098 #size-cells = <0>;
1082 1099
1083 ports { 1100 ports {
1084 #addr 1101 #address-cells = <1>;
1085 #size 1102 #size-cells = <0>;
1086 1103
1087 port@ 1104 port@0 {
1088 1105 reg = <0>;
1089 1106 mdss_dsi0_in: endpoint {
1090 1107 remote-endpoint = <&mdp5_intf1_out>;
1091 1108 };
1092 }; 1109 };
1093 1110
1094 port@ 1111 port@1 {
1095 1112 reg = <1>;
1096 1113 mdss_dsi0_out: endpoint {
1097 1114 };
1098 }; 1115 };
1099 }; 1116 };
1100 }; 1117 };
1101 1118
1102 mdss_dsi0_phy: phy@99 1119 mdss_dsi0_phy: phy@994400 {
1103 compatible = 1120 compatible = "qcom,dsi-phy-14nm";
1104 reg = <0x0099 1121 reg = <0x00994400 0x100>,
1105 <0x0099 1122 <0x00994500 0x300>,
1106 <0x0099 1123 <0x00994800 0x188>;
1107 reg-names = " 1124 reg-names = "dsi_phy",
1108 " 1125 "dsi_phy_lane",
1109 " 1126 "dsi_pll";
1110 1127
1111 #clock-cells 1128 #clock-cells = <1>;
1112 #phy-cells = 1129 #phy-cells = <0>;
1113 1130
1114 clocks = <&mm 1131 clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
1115 clock-names = 1132 clock-names = "iface", "ref";
1116 status = "dis 1133 status = "disabled";
1117 }; 1134 };
1118 1135
1119 mdss_dsi1: dsi@996000 1136 mdss_dsi1: dsi@996000 {
1120 compatible = 1137 compatible = "qcom,msm8996-dsi-ctrl",
1121 1138 "qcom,mdss-dsi-ctrl";
1122 reg = <0x0099 1139 reg = <0x00996000 0x400>;
1123 reg-names = " 1140 reg-names = "dsi_ctrl";
1124 1141
1125 interrupt-par 1142 interrupt-parent = <&mdss>;
1126 interrupts = 1143 interrupts = <5>;
1127 1144
1128 clocks = <&mm 1145 clocks = <&mmcc MDSS_MDP_CLK>,
1129 <&mm 1146 <&mmcc MDSS_BYTE1_CLK>,
1130 <&mm 1147 <&mmcc MDSS_AHB_CLK>,
1131 <&mm 1148 <&mmcc MDSS_AXI_CLK>,
1132 <&mm 1149 <&mmcc MMSS_MISC_AHB_CLK>,
1133 <&mm 1150 <&mmcc MDSS_PCLK1_CLK>,
1134 <&mm 1151 <&mmcc MDSS_ESC1_CLK>;
1135 clock-names = 1152 clock-names = "mdp_core",
1136 1153 "byte",
1137 1154 "iface",
1138 1155 "bus",
1139 1156 "core_mmss",
1140 1157 "pixel",
1141 1158 "core";
1142 assigned-cloc 1159 assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>;
1143 assigned-cloc 1160 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
1144 1161
1145 phys = <&mdss 1162 phys = <&mdss_dsi1_phy>;
1146 status = "dis 1163 status = "disabled";
1147 1164
1148 #address-cell 1165 #address-cells = <1>;
1149 #size-cells = 1166 #size-cells = <0>;
1150 1167
1151 ports { 1168 ports {
1152 #addr 1169 #address-cells = <1>;
1153 #size 1170 #size-cells = <0>;
1154 1171
1155 port@ 1172 port@0 {
1156 1173 reg = <0>;
1157 1174 mdss_dsi1_in: endpoint {
1158 1175 remote-endpoint = <&mdp5_intf2_out>;
1159 1176 };
1160 }; 1177 };
1161 1178
1162 port@ 1179 port@1 {
1163 1180 reg = <1>;
1164 1181 mdss_dsi1_out: endpoint {
1165 1182 };
1166 }; 1183 };
1167 }; 1184 };
1168 }; 1185 };
1169 1186
1170 mdss_dsi1_phy: phy@99 1187 mdss_dsi1_phy: phy@996400 {
1171 compatible = 1188 compatible = "qcom,dsi-phy-14nm";
1172 reg = <0x0099 1189 reg = <0x00996400 0x100>,
1173 <0x0099 1190 <0x00996500 0x300>,
1174 <0x0099 1191 <0x00996800 0x188>;
1175 reg-names = " 1192 reg-names = "dsi_phy",
1176 " 1193 "dsi_phy_lane",
1177 " 1194 "dsi_pll";
1178 1195
1179 #clock-cells 1196 #clock-cells = <1>;
1180 #phy-cells = 1197 #phy-cells = <0>;
1181 1198
1182 clocks = <&mm 1199 clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
1183 clock-names = 1200 clock-names = "iface", "ref";
1184 status = "dis 1201 status = "disabled";
1185 }; 1202 };
1186 1203
1187 mdss_hdmi: hdmi-tx@9a 1204 mdss_hdmi: hdmi-tx@9a0000 {
1188 compatible = 1205 compatible = "qcom,hdmi-tx-8996";
1189 reg = <0x009a 1206 reg = <0x009a0000 0x50c>,
1190 <0x0007 1207 <0x00070000 0x6158>,
1191 <0x009e 1208 <0x009e0000 0xfff>;
1192 reg-names = " 1209 reg-names = "core_physical",
1193 " 1210 "qfprom_physical",
1194 " 1211 "hdcp_physical";
1195 1212
1196 interrupt-par 1213 interrupt-parent = <&mdss>;
1197 interrupts = 1214 interrupts = <8>;
1198 1215
1199 clocks = <&mm 1216 clocks = <&mmcc MDSS_MDP_CLK>,
1200 <&mm 1217 <&mmcc MDSS_AHB_CLK>,
1201 <&mm 1218 <&mmcc MDSS_HDMI_CLK>,
1202 <&mm 1219 <&mmcc MDSS_HDMI_AHB_CLK>,
1203 <&mm 1220 <&mmcc MDSS_EXTPCLK_CLK>;
1204 clock-names = 1221 clock-names =
1205 "mdp_ 1222 "mdp_core",
1206 "ifac 1223 "iface",
1207 "core 1224 "core",
1208 "alt_ 1225 "alt_iface",
1209 "extp 1226 "extp";
1210 1227
1211 phys = <&mdss 1228 phys = <&mdss_hdmi_phy>;
1212 #sound-dai-ce 1229 #sound-dai-cells = <1>;
1213 1230
1214 status = "dis 1231 status = "disabled";
1215 1232
1216 ports { 1233 ports {
1217 #addr 1234 #address-cells = <1>;
1218 #size 1235 #size-cells = <0>;
1219 1236
1220 port@ 1237 port@0 {
1221 1238 reg = <0>;
1222 1239 mdss_hdmi_in: endpoint {
1223 1240 remote-endpoint = <&mdp5_intf3_out>;
1224 1241 };
1225 }; 1242 };
1226 }; 1243 };
1227 }; 1244 };
1228 1245
1229 mdss_hdmi_phy: phy@9a 1246 mdss_hdmi_phy: phy@9a0600 {
1230 #phy-cells = 1247 #phy-cells = <0>;
1231 compatible = 1248 compatible = "qcom,hdmi-phy-8996";
1232 reg = <0x009a 1249 reg = <0x009a0600 0x1c4>,
1233 <0x009a 1250 <0x009a0a00 0x124>,
1234 <0x009a 1251 <0x009a0c00 0x124>,
1235 <0x009a 1252 <0x009a0e00 0x124>,
1236 <0x009a 1253 <0x009a1000 0x124>,
1237 <0x009a 1254 <0x009a1200 0x0c8>;
1238 reg-names = " 1255 reg-names = "hdmi_pll",
1239 " 1256 "hdmi_tx_l0",
1240 " 1257 "hdmi_tx_l1",
1241 " 1258 "hdmi_tx_l2",
1242 " 1259 "hdmi_tx_l3",
1243 " 1260 "hdmi_phy";
1244 1261
1245 clocks = <&mm 1262 clocks = <&mmcc MDSS_AHB_CLK>,
1246 <&gc 1263 <&gcc GCC_HDMI_CLKREF_CLK>,
1247 <&xo 1264 <&xo_board>;
1248 clock-names = 1265 clock-names = "iface",
1249 1266 "ref",
1250 1267 "xo";
1251 1268
1252 #clock-cells 1269 #clock-cells = <0>;
1253 1270
1254 status = "dis 1271 status = "disabled";
1255 }; 1272 };
1256 }; 1273 };
1257 1274
1258 gpu: gpu@b00000 { 1275 gpu: gpu@b00000 {
1259 compatible = "qcom,ad 1276 compatible = "qcom,adreno-530.2", "qcom,adreno";
1260 1277
1261 reg = <0x00b00000 0x3 1278 reg = <0x00b00000 0x3f000>;
1262 reg-names = "kgsl_3d0 1279 reg-names = "kgsl_3d0_reg_memory";
1263 1280
1264 interrupts = <GIC_SPI 1281 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
1265 1282
1266 clocks = <&mmcc GPU_G 1283 clocks = <&mmcc GPU_GX_GFX3D_CLK>,
1267 <&mmcc GPU_AH 1284 <&mmcc GPU_AHB_CLK>,
1268 <&mmcc GPU_GX 1285 <&mmcc GPU_GX_RBBMTIMER_CLK>,
1269 <&gcc GCC_BIM 1286 <&gcc GCC_BIMC_GFX_CLK>,
1270 <&gcc GCC_MMS 1287 <&gcc GCC_MMSS_BIMC_GFX_CLK>;
1271 1288
1272 clock-names = "core", 1289 clock-names = "core",
1273 "iface", 1290 "iface",
1274 "rbbmtimer", 1291 "rbbmtimer",
1275 "mem", 1292 "mem",
1276 "mem_iface"; 1293 "mem_iface";
1277 1294
1278 interconnects = <&bim 1295 interconnects = <&bimc MASTER_GRAPHICS_3D &bimc SLAVE_EBI_CH0>;
1279 interconnect-names = 1296 interconnect-names = "gfx-mem";
1280 1297
1281 power-domains = <&mmc 1298 power-domains = <&mmcc GPU_GX_GDSC>;
1282 iommus = <&adreno_smm 1299 iommus = <&adreno_smmu 0>;
1283 1300
1284 nvmem-cells = <&speed 1301 nvmem-cells = <&speedbin_efuse>;
1285 nvmem-cell-names = "s 1302 nvmem-cell-names = "speed_bin";
1286 1303
1287 operating-points-v2 = 1304 operating-points-v2 = <&gpu_opp_table>;
1288 1305
1289 status = "disabled"; 1306 status = "disabled";
1290 1307
1291 #cooling-cells = <2>; 1308 #cooling-cells = <2>;
1292 1309
1293 gpu_opp_table: opp-ta 1310 gpu_opp_table: opp-table {
1294 compatible = 1311 compatible = "operating-points-v2";
1295 1312
1296 /* 1313 /*
1297 * 624Mhz is 1314 * 624Mhz is only available on speed bins 0 and 3.
1298 * 560Mhz is 1315 * 560Mhz is only available on speed bins 0, 2 and 3.
1299 * All the re 1316 * All the rest are available on all bins of the hardware.
1300 */ 1317 */
1301 opp-624000000 1318 opp-624000000 {
1302 opp-h 1319 opp-hz = /bits/ 64 <624000000>;
1303 opp-s 1320 opp-supported-hw = <0x09>;
1304 }; 1321 };
1305 opp-560000000 1322 opp-560000000 {
1306 opp-h 1323 opp-hz = /bits/ 64 <560000000>;
1307 opp-s 1324 opp-supported-hw = <0x0d>;
1308 }; 1325 };
1309 opp-510000000 1326 opp-510000000 {
1310 opp-h 1327 opp-hz = /bits/ 64 <510000000>;
1311 opp-s 1328 opp-supported-hw = <0xff>;
1312 }; 1329 };
1313 opp-401800000 1330 opp-401800000 {
1314 opp-h 1331 opp-hz = /bits/ 64 <401800000>;
1315 opp-s 1332 opp-supported-hw = <0xff>;
1316 }; 1333 };
1317 opp-315000000 1334 opp-315000000 {
1318 opp-h 1335 opp-hz = /bits/ 64 <315000000>;
1319 opp-s 1336 opp-supported-hw = <0xff>;
1320 }; 1337 };
1321 opp-214000000 1338 opp-214000000 {
1322 opp-h 1339 opp-hz = /bits/ 64 <214000000>;
1323 opp-s 1340 opp-supported-hw = <0xff>;
1324 }; 1341 };
1325 opp-133000000 1342 opp-133000000 {
1326 opp-h 1343 opp-hz = /bits/ 64 <133000000>;
1327 opp-s 1344 opp-supported-hw = <0xff>;
1328 }; 1345 };
1329 }; 1346 };
1330 1347
1331 zap-shader { 1348 zap-shader {
1332 memory-region 1349 memory-region = <&gpu_mem>;
1333 }; 1350 };
1334 }; 1351 };
1335 1352
1336 tlmm: pinctrl@1010000 { 1353 tlmm: pinctrl@1010000 {
1337 compatible = "qcom,ms 1354 compatible = "qcom,msm8996-pinctrl";
1338 reg = <0x01010000 0x3 1355 reg = <0x01010000 0x300000>;
1339 interrupts = <GIC_SPI 1356 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1340 gpio-controller; 1357 gpio-controller;
1341 gpio-ranges = <&tlmm 1358 gpio-ranges = <&tlmm 0 0 150>;
1342 #gpio-cells = <2>; 1359 #gpio-cells = <2>;
1343 interrupt-controller; 1360 interrupt-controller;
1344 #interrupt-cells = <2 1361 #interrupt-cells = <2>;
1345 1362
1346 blsp1_spi1_default: b 1363 blsp1_spi1_default: blsp1-spi1-default-state {
1347 spi-pins { 1364 spi-pins {
1348 pins 1365 pins = "gpio0", "gpio1", "gpio3";
1349 funct 1366 function = "blsp_spi1";
1350 drive 1367 drive-strength = <12>;
1351 bias- 1368 bias-disable;
1352 }; 1369 };
1353 1370
1354 cs-pins { 1371 cs-pins {
1355 pins 1372 pins = "gpio2";
1356 funct 1373 function = "gpio";
1357 drive 1374 drive-strength = <16>;
1358 bias- 1375 bias-disable;
1359 outpu 1376 output-high;
1360 }; 1377 };
1361 }; 1378 };
1362 1379
1363 blsp1_spi1_sleep: bls 1380 blsp1_spi1_sleep: blsp1-spi1-sleep-state {
1364 pins = "gpio0 1381 pins = "gpio0", "gpio1", "gpio2", "gpio3";
1365 function = "g 1382 function = "gpio";
1366 drive-strengt 1383 drive-strength = <2>;
1367 bias-pull-dow 1384 bias-pull-down;
1368 }; 1385 };
1369 1386
1370 blsp2_uart2_2pins_def 1387 blsp2_uart2_2pins_default: blsp2-uart2-2pins-state {
1371 pins = "gpio4 1388 pins = "gpio4", "gpio5";
1372 function = "b 1389 function = "blsp_uart8";
1373 drive-strengt 1390 drive-strength = <16>;
1374 bias-disable; 1391 bias-disable;
1375 }; 1392 };
1376 1393
1377 blsp2_uart2_2pins_sle 1394 blsp2_uart2_2pins_sleep: blsp2-uart2-2pins-sleep-state {
1378 pins = "gpio4 1395 pins = "gpio4", "gpio5";
1379 function = "g 1396 function = "gpio";
1380 drive-strengt 1397 drive-strength = <2>;
1381 bias-disable; 1398 bias-disable;
1382 }; 1399 };
1383 1400
1384 blsp2_i2c2_default: b 1401 blsp2_i2c2_default: blsp2-i2c2-state {
1385 pins = "gpio6 1402 pins = "gpio6", "gpio7";
1386 function = "b 1403 function = "blsp_i2c8";
1387 drive-strengt 1404 drive-strength = <16>;
1388 bias-disable; 1405 bias-disable;
1389 }; 1406 };
1390 1407
1391 blsp2_i2c2_sleep: bls 1408 blsp2_i2c2_sleep: blsp2-i2c2-sleep-state {
1392 pins = "gpio6 1409 pins = "gpio6", "gpio7";
1393 function = "g 1410 function = "gpio";
1394 drive-strengt 1411 drive-strength = <2>;
1395 bias-disable; 1412 bias-disable;
1396 }; 1413 };
1397 1414
1398 blsp1_i2c6_default: b 1415 blsp1_i2c6_default: blsp1-i2c6-state {
1399 pins = "gpio2 1416 pins = "gpio27", "gpio28";
1400 function = "b 1417 function = "blsp_i2c6";
1401 drive-strengt 1418 drive-strength = <16>;
1402 bias-disable; 1419 bias-disable;
1403 }; 1420 };
1404 1421
1405 blsp1_i2c6_sleep: bls 1422 blsp1_i2c6_sleep: blsp1-i2c6-sleep-state {
1406 pins = "gpio2 1423 pins = "gpio27", "gpio28";
1407 function = "g 1424 function = "gpio";
1408 drive-strengt 1425 drive-strength = <2>;
1409 bias-pull-up; 1426 bias-pull-up;
1410 }; 1427 };
1411 1428
1412 cci0_default: cci0-de 1429 cci0_default: cci0-default-state {
1413 pins = "gpio1 1430 pins = "gpio17", "gpio18";
1414 function = "c 1431 function = "cci_i2c";
1415 drive-strengt 1432 drive-strength = <16>;
1416 bias-disable; 1433 bias-disable;
1417 }; 1434 };
1418 1435
1419 camera0_state_on: 1436 camera0_state_on:
1420 camera_rear_default: 1437 camera_rear_default: camera-rear-default-state {
1421 camera0_mclk: 1438 camera0_mclk: mclk0-pins {
1422 pins 1439 pins = "gpio13";
1423 funct 1440 function = "cam_mclk";
1424 drive 1441 drive-strength = <16>;
1425 bias- 1442 bias-disable;
1426 }; 1443 };
1427 1444
1428 camera0_rst: 1445 camera0_rst: rst-pins {
1429 pins 1446 pins = "gpio25";
1430 funct 1447 function = "gpio";
1431 drive 1448 drive-strength = <16>;
1432 bias- 1449 bias-disable;
1433 }; 1450 };
1434 1451
1435 camera0_pwdn: 1452 camera0_pwdn: pwdn-pins {
1436 pins 1453 pins = "gpio26";
1437 funct 1454 function = "gpio";
1438 drive 1455 drive-strength = <16>;
1439 bias- 1456 bias-disable;
1440 }; 1457 };
1441 }; 1458 };
1442 1459
1443 cci1_default: cci1-de 1460 cci1_default: cci1-default-state {
1444 pins = "gpio1 1461 pins = "gpio19", "gpio20";
1445 function = "c 1462 function = "cci_i2c";
1446 drive-strengt 1463 drive-strength = <16>;
1447 bias-disable; 1464 bias-disable;
1448 }; 1465 };
1449 1466
1450 camera1_state_on: 1467 camera1_state_on:
1451 camera_board_default: 1468 camera_board_default: camera-board-default-state {
1452 mclk1-pins { 1469 mclk1-pins {
1453 pins 1470 pins = "gpio14";
1454 funct 1471 function = "cam_mclk";
1455 drive 1472 drive-strength = <16>;
1456 bias- 1473 bias-disable;
1457 }; 1474 };
1458 1475
1459 pwdn-pins { 1476 pwdn-pins {
1460 pins 1477 pins = "gpio98";
1461 funct 1478 function = "gpio";
1462 drive 1479 drive-strength = <16>;
1463 bias- 1480 bias-disable;
1464 }; 1481 };
1465 1482
1466 rst-pins { 1483 rst-pins {
1467 pins 1484 pins = "gpio104";
1468 funct 1485 function = "gpio";
1469 drive 1486 drive-strength = <16>;
1470 bias- 1487 bias-disable;
1471 }; 1488 };
1472 }; 1489 };
1473 1490
1474 camera2_state_on: 1491 camera2_state_on:
1475 camera_front_default: 1492 camera_front_default: camera-front-default-state {
1476 camera2_mclk: 1493 camera2_mclk: mclk2-pins {
1477 pins 1494 pins = "gpio15";
1478 funct 1495 function = "cam_mclk";
1479 drive 1496 drive-strength = <16>;
1480 bias- 1497 bias-disable;
1481 }; 1498 };
1482 1499
1483 camera2_rst: 1500 camera2_rst: rst-pins {
1484 pins 1501 pins = "gpio23";
1485 funct 1502 function = "gpio";
1486 drive 1503 drive-strength = <16>;
1487 bias- 1504 bias-disable;
1488 }; 1505 };
1489 1506
1490 pwdn-pins { 1507 pwdn-pins {
1491 pins 1508 pins = "gpio133";
1492 funct 1509 function = "gpio";
1493 drive 1510 drive-strength = <16>;
1494 bias- 1511 bias-disable;
1495 }; 1512 };
1496 }; 1513 };
1497 1514
1498 pcie0_state_on: pcie0 1515 pcie0_state_on: pcie0-state-on-state {
1499 perst-pins { 1516 perst-pins {
1500 pins 1517 pins = "gpio35";
1501 funct 1518 function = "gpio";
1502 drive 1519 drive-strength = <2>;
1503 bias- 1520 bias-pull-down;
1504 }; 1521 };
1505 1522
1506 clkreq-pins { 1523 clkreq-pins {
1507 pins 1524 pins = "gpio36";
1508 funct 1525 function = "pci_e0";
1509 drive 1526 drive-strength = <2>;
1510 bias- 1527 bias-pull-up;
1511 }; 1528 };
1512 1529
1513 wake-pins { 1530 wake-pins {
1514 pins 1531 pins = "gpio37";
1515 funct 1532 function = "gpio";
1516 drive 1533 drive-strength = <2>;
1517 bias- 1534 bias-pull-up;
1518 }; 1535 };
1519 }; 1536 };
1520 1537
1521 pcie0_state_off: pcie 1538 pcie0_state_off: pcie0-state-off-state {
1522 perst-pins { 1539 perst-pins {
1523 pins 1540 pins = "gpio35";
1524 funct 1541 function = "gpio";
1525 drive 1542 drive-strength = <2>;
1526 bias- 1543 bias-pull-down;
1527 }; 1544 };
1528 1545
1529 clkreq-pins { 1546 clkreq-pins {
1530 pins 1547 pins = "gpio36";
1531 funct 1548 function = "gpio";
1532 drive 1549 drive-strength = <2>;
1533 bias- 1550 bias-disable;
1534 }; 1551 };
1535 1552
1536 wake-pins { 1553 wake-pins {
1537 pins 1554 pins = "gpio37";
1538 funct 1555 function = "gpio";
1539 drive 1556 drive-strength = <2>;
1540 bias- 1557 bias-disable;
1541 }; 1558 };
1542 }; 1559 };
1543 1560
1544 blsp1_uart2_default: 1561 blsp1_uart2_default: blsp1-uart2-default-state {
1545 pins = "gpio4 1562 pins = "gpio41", "gpio42", "gpio43", "gpio44";
1546 function = "b 1563 function = "blsp_uart2";
1547 drive-strengt 1564 drive-strength = <16>;
1548 bias-disable; 1565 bias-disable;
1549 }; 1566 };
1550 1567
1551 blsp1_uart2_sleep: bl 1568 blsp1_uart2_sleep: blsp1-uart2-sleep-state {
1552 pins = "gpio4 1569 pins = "gpio41", "gpio42", "gpio43", "gpio44";
1553 function = "g 1570 function = "gpio";
1554 drive-strengt 1571 drive-strength = <2>;
1555 bias-disable; 1572 bias-disable;
1556 }; 1573 };
1557 1574
1558 blsp1_i2c3_default: b 1575 blsp1_i2c3_default: blsp1-i2c3-default-state {
1559 pins = "gpio4 1576 pins = "gpio47", "gpio48";
1560 function = "b 1577 function = "blsp_i2c3";
1561 drive-strengt 1578 drive-strength = <16>;
1562 bias-disable; 1579 bias-disable;
1563 }; 1580 };
1564 1581
1565 blsp1_i2c3_sleep: bls 1582 blsp1_i2c3_sleep: blsp1-i2c3-sleep-state {
1566 pins = "gpio4 1583 pins = "gpio47", "gpio48";
1567 function = "g 1584 function = "gpio";
1568 drive-strengt 1585 drive-strength = <2>;
1569 bias-disable; 1586 bias-disable;
1570 }; 1587 };
1571 1588
1572 blsp2_uart3_4pins_def 1589 blsp2_uart3_4pins_default: blsp2-uart3-4pins-state {
1573 pins = "gpio4 1590 pins = "gpio49", "gpio50", "gpio51", "gpio52";
1574 function = "b 1591 function = "blsp_uart9";
1575 drive-strengt 1592 drive-strength = <16>;
1576 bias-disable; 1593 bias-disable;
1577 }; 1594 };
1578 1595
1579 blsp2_uart3_4pins_sle 1596 blsp2_uart3_4pins_sleep: blsp2-uart3-4pins-sleep-state {
1580 pins = "gpio4 1597 pins = "gpio49", "gpio50", "gpio51", "gpio52";
1581 function = "b 1598 function = "blsp_uart9";
1582 drive-strengt 1599 drive-strength = <2>;
1583 bias-disable; 1600 bias-disable;
1584 }; 1601 };
1585 1602
1586 blsp2_i2c3_default: b 1603 blsp2_i2c3_default: blsp2-i2c3-state-state {
1587 pins = "gpio5 1604 pins = "gpio51", "gpio52";
1588 function = "b 1605 function = "blsp_i2c9";
1589 drive-strengt 1606 drive-strength = <16>;
1590 bias-disable; 1607 bias-disable;
1591 }; 1608 };
1592 1609
1593 blsp2_i2c3_sleep: bls 1610 blsp2_i2c3_sleep: blsp2-i2c3-sleep-state {
1594 pins = "gpio5 1611 pins = "gpio51", "gpio52";
1595 function = "g 1612 function = "gpio";
1596 drive-strengt 1613 drive-strength = <2>;
1597 bias-disable; 1614 bias-disable;
1598 }; 1615 };
1599 1616
1600 wcd_intr_default: wcd 1617 wcd_intr_default: wcd-intr-default-state {
1601 pins = "gpio5 1618 pins = "gpio54";
1602 function = "g 1619 function = "gpio";
1603 drive-strengt 1620 drive-strength = <2>;
1604 bias-pull-dow 1621 bias-pull-down;
1605 }; 1622 };
1606 1623
1607 blsp2_i2c1_default: b 1624 blsp2_i2c1_default: blsp2-i2c1-state {
1608 pins = "gpio5 1625 pins = "gpio55", "gpio56";
1609 function = "b 1626 function = "blsp_i2c7";
1610 drive-strengt 1627 drive-strength = <16>;
1611 bias-disable; 1628 bias-disable;
1612 }; 1629 };
1613 1630
1614 blsp2_i2c1_sleep: bls 1631 blsp2_i2c1_sleep: blsp2-i2c1-sleep-state {
1615 pins = "gpio5 1632 pins = "gpio55", "gpio56";
1616 function = "g 1633 function = "gpio";
1617 drive-strengt 1634 drive-strength = <2>;
1618 bias-disable; 1635 bias-disable;
1619 }; 1636 };
1620 1637
1621 blsp2_i2c5_default: b 1638 blsp2_i2c5_default: blsp2-i2c5-state {
1622 pins = "gpio6 1639 pins = "gpio60", "gpio61";
1623 function = "b 1640 function = "blsp_i2c11";
1624 drive-strengt 1641 drive-strength = <2>;
1625 bias-disable; 1642 bias-disable;
1626 }; 1643 };
1627 1644
1628 /* Sleep state for BL 1645 /* Sleep state for BLSP2_I2C5 is missing.. */
1629 1646
1630 cdc_reset_active: cdc 1647 cdc_reset_active: cdc-reset-active-state {
1631 pins = "gpio6 1648 pins = "gpio64";
1632 function = "g 1649 function = "gpio";
1633 drive-strengt 1650 drive-strength = <16>;
1634 bias-pull-dow 1651 bias-pull-down;
1635 output-high; 1652 output-high;
1636 }; 1653 };
1637 1654
1638 cdc_reset_sleep: cdc- 1655 cdc_reset_sleep: cdc-reset-sleep-state {
1639 pins = "gpio6 1656 pins = "gpio64";
1640 function = "g 1657 function = "gpio";
1641 drive-strengt 1658 drive-strength = <16>;
1642 bias-disable; 1659 bias-disable;
1643 output-low; 1660 output-low;
1644 }; 1661 };
1645 1662
1646 blsp2_spi6_default: b 1663 blsp2_spi6_default: blsp2-spi6-default-state {
1647 spi-pins { 1664 spi-pins {
1648 pins 1665 pins = "gpio85", "gpio86", "gpio88";
1649 funct 1666 function = "blsp_spi12";
1650 drive 1667 drive-strength = <12>;
1651 bias- 1668 bias-disable;
1652 }; 1669 };
1653 1670
1654 cs-pins { 1671 cs-pins {
1655 pins 1672 pins = "gpio87";
1656 funct 1673 function = "gpio";
1657 drive 1674 drive-strength = <16>;
1658 bias- 1675 bias-disable;
1659 outpu 1676 output-high;
1660 }; 1677 };
1661 }; 1678 };
1662 1679
1663 blsp2_spi6_sleep: bls 1680 blsp2_spi6_sleep: blsp2-spi6-sleep-state {
1664 pins = "gpio8 1681 pins = "gpio85", "gpio86", "gpio87", "gpio88";
1665 function = "g 1682 function = "gpio";
1666 drive-strengt 1683 drive-strength = <2>;
1667 bias-pull-dow 1684 bias-pull-down;
1668 }; 1685 };
1669 1686
1670 blsp2_i2c6_default: b 1687 blsp2_i2c6_default: blsp2-i2c6-state {
1671 pins = "gpio8 1688 pins = "gpio87", "gpio88";
1672 function = "b 1689 function = "blsp_i2c12";
1673 drive-strengt 1690 drive-strength = <16>;
1674 bias-disable; 1691 bias-disable;
1675 }; 1692 };
1676 1693
1677 blsp2_i2c6_sleep: bls 1694 blsp2_i2c6_sleep: blsp2-i2c6-sleep-state {
1678 pins = "gpio8 1695 pins = "gpio87", "gpio88";
1679 function = "g 1696 function = "gpio";
1680 drive-strengt 1697 drive-strength = <2>;
1681 bias-disable; 1698 bias-disable;
1682 }; 1699 };
1683 1700
1684 pcie1_state_on: pcie1 1701 pcie1_state_on: pcie1-on-state {
1685 perst-pins { 1702 perst-pins {
1686 pins 1703 pins = "gpio130";
1687 funct 1704 function = "gpio";
1688 drive 1705 drive-strength = <2>;
1689 bias- 1706 bias-pull-down;
1690 }; 1707 };
1691 1708
1692 clkreq-pins { 1709 clkreq-pins {
1693 pins 1710 pins = "gpio131";
1694 funct 1711 function = "pci_e1";
1695 drive 1712 drive-strength = <2>;
1696 bias- 1713 bias-pull-up;
1697 }; 1714 };
1698 1715
1699 wake-pins { 1716 wake-pins {
1700 pins 1717 pins = "gpio132";
1701 funct 1718 function = "gpio";
1702 drive 1719 drive-strength = <2>;
1703 bias- 1720 bias-pull-down;
1704 }; 1721 };
1705 }; 1722 };
1706 1723
1707 pcie1_state_off: pcie 1724 pcie1_state_off: pcie1-off-state {
1708 /* Perst is m 1725 /* Perst is missing? */
1709 clkreq-pins { 1726 clkreq-pins {
1710 pins 1727 pins = "gpio131";
1711 funct 1728 function = "gpio";
1712 drive 1729 drive-strength = <2>;
1713 bias- 1730 bias-disable;
1714 }; 1731 };
1715 1732
1716 wake-pins { 1733 wake-pins {
1717 pins 1734 pins = "gpio132";
1718 funct 1735 function = "gpio";
1719 drive 1736 drive-strength = <2>;
1720 bias- 1737 bias-disable;
1721 }; 1738 };
1722 }; 1739 };
1723 1740
1724 pcie2_state_on: pcie2 1741 pcie2_state_on: pcie2-on-state {
1725 perst-pins { 1742 perst-pins {
1726 pins 1743 pins = "gpio114";
1727 funct 1744 function = "gpio";
1728 drive 1745 drive-strength = <2>;
1729 bias- 1746 bias-pull-down;
1730 }; 1747 };
1731 1748
1732 clkreq-pins { 1749 clkreq-pins {
1733 pins 1750 pins = "gpio115";
1734 funct 1751 function = "pci_e2";
1735 drive 1752 drive-strength = <2>;
1736 bias- 1753 bias-pull-up;
1737 }; 1754 };
1738 1755
1739 wake-pins { 1756 wake-pins {
1740 pins 1757 pins = "gpio116";
1741 funct 1758 function = "gpio";
1742 drive 1759 drive-strength = <2>;
1743 bias- 1760 bias-pull-down;
1744 }; 1761 };
1745 }; 1762 };
1746 1763
1747 pcie2_state_off: pcie 1764 pcie2_state_off: pcie2-off-state {
1748 /* Perst is m 1765 /* Perst is missing? */
1749 clkreq-pins { 1766 clkreq-pins {
1750 pins 1767 pins = "gpio115";
1751 funct 1768 function = "gpio";
1752 drive 1769 drive-strength = <2>;
1753 bias- 1770 bias-disable;
1754 }; 1771 };
1755 1772
1756 wake-pins { 1773 wake-pins {
1757 pins 1774 pins = "gpio116";
1758 funct 1775 function = "gpio";
1759 drive 1776 drive-strength = <2>;
1760 bias- 1777 bias-disable;
1761 }; 1778 };
1762 }; 1779 };
1763 1780
1764 sdc1_state_on: sdc1-o 1781 sdc1_state_on: sdc1-on-state {
1765 clk-pins { 1782 clk-pins {
1766 pins 1783 pins = "sdc1_clk";
1767 bias- 1784 bias-disable;
1768 drive 1785 drive-strength = <16>;
1769 }; 1786 };
1770 1787
1771 cmd-pins { 1788 cmd-pins {
1772 pins 1789 pins = "sdc1_cmd";
1773 bias- 1790 bias-pull-up;
1774 drive 1791 drive-strength = <10>;
1775 }; 1792 };
1776 1793
1777 data-pins { 1794 data-pins {
1778 pins 1795 pins = "sdc1_data";
1779 bias- 1796 bias-pull-up;
1780 drive 1797 drive-strength = <10>;
1781 }; 1798 };
1782 1799
1783 rclk-pins { 1800 rclk-pins {
1784 pins 1801 pins = "sdc1_rclk";
1785 bias- 1802 bias-pull-down;
1786 }; 1803 };
1787 }; 1804 };
1788 1805
1789 sdc1_state_off: sdc1- 1806 sdc1_state_off: sdc1-off-state {
1790 clk-pins { 1807 clk-pins {
1791 pins 1808 pins = "sdc1_clk";
1792 bias- 1809 bias-disable;
1793 drive 1810 drive-strength = <2>;
1794 }; 1811 };
1795 1812
1796 cmd-pins { 1813 cmd-pins {
1797 pins 1814 pins = "sdc1_cmd";
1798 bias- 1815 bias-pull-up;
1799 drive 1816 drive-strength = <2>;
1800 }; 1817 };
1801 1818
1802 data-pins { 1819 data-pins {
1803 pins 1820 pins = "sdc1_data";
1804 bias- 1821 bias-pull-up;
1805 drive 1822 drive-strength = <2>;
1806 }; 1823 };
1807 1824
1808 rclk-pins { 1825 rclk-pins {
1809 pins 1826 pins = "sdc1_rclk";
1810 bias- 1827 bias-pull-down;
1811 }; 1828 };
1812 }; 1829 };
1813 1830
1814 sdc2_state_on: sdc2-o 1831 sdc2_state_on: sdc2-on-state {
1815 clk-pins { 1832 clk-pins {
1816 pins 1833 pins = "sdc2_clk";
1817 bias- 1834 bias-disable;
1818 drive 1835 drive-strength = <16>;
1819 }; 1836 };
1820 1837
1821 cmd-pins { 1838 cmd-pins {
1822 pins 1839 pins = "sdc2_cmd";
1823 bias- 1840 bias-pull-up;
1824 drive 1841 drive-strength = <10>;
1825 }; 1842 };
1826 1843
1827 data-pins { 1844 data-pins {
1828 pins 1845 pins = "sdc2_data";
1829 bias- 1846 bias-pull-up;
1830 drive 1847 drive-strength = <10>;
1831 }; 1848 };
1832 }; 1849 };
1833 1850
1834 sdc2_state_off: sdc2- 1851 sdc2_state_off: sdc2-off-state {
1835 clk-pins { 1852 clk-pins {
1836 pins 1853 pins = "sdc2_clk";
1837 bias- 1854 bias-disable;
1838 drive 1855 drive-strength = <2>;
1839 }; 1856 };
1840 1857
1841 cmd-pins { 1858 cmd-pins {
1842 pins 1859 pins = "sdc2_cmd";
1843 bias- 1860 bias-pull-up;
1844 drive 1861 drive-strength = <2>;
1845 }; 1862 };
1846 1863
1847 data-pins { 1864 data-pins {
1848 pins 1865 pins = "sdc2_data";
1849 bias- 1866 bias-pull-up;
1850 drive 1867 drive-strength = <2>;
1851 }; 1868 };
1852 }; 1869 };
1853 }; 1870 };
1854 1871
1855 sram@290000 { 1872 sram@290000 {
1856 compatible = "qcom,rp 1873 compatible = "qcom,rpm-stats";
1857 reg = <0x00290000 0x1 1874 reg = <0x00290000 0x10000>;
1858 }; 1875 };
1859 1876
1860 spmi_bus: spmi@400f000 { 1877 spmi_bus: spmi@400f000 {
1861 compatible = "qcom,sp 1878 compatible = "qcom,spmi-pmic-arb";
1862 reg = <0x0400f000 0x1 1879 reg = <0x0400f000 0x1000>,
1863 <0x04400000 0x8 1880 <0x04400000 0x800000>,
1864 <0x04c00000 0x8 1881 <0x04c00000 0x800000>,
1865 <0x05800000 0x2 1882 <0x05800000 0x200000>,
1866 <0x0400a000 0x0 1883 <0x0400a000 0x002100>;
1867 reg-names = "core", " 1884 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1868 interrupt-names = "pe 1885 interrupt-names = "periph_irq";
1869 interrupts = <GIC_SPI 1886 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
1870 qcom,ee = <0>; 1887 qcom,ee = <0>;
1871 qcom,channel = <0>; 1888 qcom,channel = <0>;
1872 #address-cells = <2>; 1889 #address-cells = <2>;
1873 #size-cells = <0>; 1890 #size-cells = <0>;
1874 interrupt-controller; 1891 interrupt-controller;
1875 #interrupt-cells = <4 1892 #interrupt-cells = <4>;
1876 }; 1893 };
1877 1894
1878 bus@0 { 1895 bus@0 {
1879 power-domains = <&gcc 1896 power-domains = <&gcc AGGRE0_NOC_GDSC>;
1880 compatible = "simple- 1897 compatible = "simple-pm-bus";
1881 #address-cells = <1>; 1898 #address-cells = <1>;
1882 #size-cells = <1>; 1899 #size-cells = <1>;
1883 ranges = <0x0 0x0 0xf 1900 ranges = <0x0 0x0 0xffffffff>;
1884 1901
1885 pcie0: pcie@600000 { 1902 pcie0: pcie@600000 {
1886 compatible = 1903 compatible = "qcom,pcie-msm8996";
1887 status = "dis 1904 status = "disabled";
1888 power-domains 1905 power-domains = <&gcc PCIE0_GDSC>;
1889 bus-range = < 1906 bus-range = <0x00 0xff>;
1890 num-lanes = < 1907 num-lanes = <1>;
1891 1908
1892 reg = <0x0060 1909 reg = <0x00600000 0x2000>,
1893 <0x0c00 1910 <0x0c000000 0xf1d>,
1894 <0x0c00 1911 <0x0c000f20 0xa8>,
1895 <0x0c10 1912 <0x0c100000 0x100000>;
1896 reg-names = " 1913 reg-names = "parf", "dbi", "elbi","config";
1897 1914
1898 phys = <&pcie 1915 phys = <&pciephy_0>;
1899 phy-names = " 1916 phy-names = "pciephy";
1900 1917
1901 #address-cell 1918 #address-cells = <3>;
1902 #size-cells = 1919 #size-cells = <2>;
1903 ranges = <0x0 1920 ranges = <0x01000000 0x0 0x00000000 0x0c200000 0x0 0x100000>,
1904 <0x0 1921 <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;
1905 1922
1906 device_type = 1923 device_type = "pci";
1907 1924
1908 interrupts = 1925 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
1909 interrupt-nam 1926 interrupt-names = "msi";
1910 #interrupt-ce 1927 #interrupt-cells = <1>;
1911 interrupt-map 1928 interrupt-map-mask = <0 0 0 0x7>;
1912 interrupt-map 1929 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1913 1930 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1914 1931 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1915 1932 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1916 1933
1917 pinctrl-names 1934 pinctrl-names = "default", "sleep";
1918 pinctrl-0 = < 1935 pinctrl-0 = <&pcie0_state_on>;
1919 pinctrl-1 = < 1936 pinctrl-1 = <&pcie0_state_off>;
1920 1937
1921 linux,pci-dom 1938 linux,pci-domain = <0>;
1922 1939
1923 clocks = <&gc 1940 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1924 <&gcc 1941 <&gcc GCC_PCIE_0_AUX_CLK>,
1925 <&gcc 1942 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1926 <&gcc 1943 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1927 <&gcc 1944 <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
1928 1945
1929 clock-names = 1946 clock-names = "pipe",
1930 1947 "aux",
1931 1948 "cfg",
1932 1949 "bus_master",
1933 1950 "bus_slave";
1934 <<
1935 pcie@0 { <<
1936 devic <<
1937 reg = <<
1938 bus-r <<
1939 <<
1940 #addr <<
1941 #size <<
1942 range <<
1943 }; <<
1944 }; 1951 };
1945 1952
1946 pcie1: pcie@608000 { 1953 pcie1: pcie@608000 {
1947 compatible = 1954 compatible = "qcom,pcie-msm8996";
1948 power-domains 1955 power-domains = <&gcc PCIE1_GDSC>;
1949 bus-range = < 1956 bus-range = <0x00 0xff>;
1950 num-lanes = < 1957 num-lanes = <1>;
1951 1958
1952 status = "dis 1959 status = "disabled";
1953 1960
1954 reg = <0x0060 1961 reg = <0x00608000 0x2000>,
1955 <0x0d00 1962 <0x0d000000 0xf1d>,
1956 <0x0d00 1963 <0x0d000f20 0xa8>,
1957 <0x0d10 1964 <0x0d100000 0x100000>;
1958 1965
1959 reg-names = " 1966 reg-names = "parf", "dbi", "elbi","config";
1960 1967
1961 phys = <&pcie 1968 phys = <&pciephy_1>;
1962 phy-names = " 1969 phy-names = "pciephy";
1963 1970
1964 #address-cell 1971 #address-cells = <3>;
1965 #size-cells = 1972 #size-cells = <2>;
1966 ranges = <0x0 1973 ranges = <0x01000000 0x0 0x00000000 0x0d200000 0x0 0x100000>,
1967 <0x0 1974 <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>;
1968 1975
1969 device_type = 1976 device_type = "pci";
1970 1977
1971 interrupts = 1978 interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
1972 interrupt-nam 1979 interrupt-names = "msi";
1973 #interrupt-ce 1980 #interrupt-cells = <1>;
1974 interrupt-map 1981 interrupt-map-mask = <0 0 0 0x7>;
1975 interrupt-map 1982 interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1976 1983 <0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1977 1984 <0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1978 1985 <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1979 1986
1980 pinctrl-names 1987 pinctrl-names = "default", "sleep";
1981 pinctrl-0 = < 1988 pinctrl-0 = <&pcie1_state_on>;
1982 pinctrl-1 = < 1989 pinctrl-1 = <&pcie1_state_off>;
1983 1990
1984 linux,pci-dom 1991 linux,pci-domain = <1>;
1985 1992
1986 clocks = <&gc 1993 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1987 <&gcc 1994 <&gcc GCC_PCIE_1_AUX_CLK>,
1988 <&gcc 1995 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1989 <&gcc 1996 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1990 <&gcc 1997 <&gcc GCC_PCIE_1_SLV_AXI_CLK>;
1991 1998
1992 clock-names = 1999 clock-names = "pipe",
1993 2000 "aux",
1994 2001 "cfg",
1995 2002 "bus_master",
1996 2003 "bus_slave";
1997 <<
1998 pcie@0 { <<
1999 devic <<
2000 reg = <<
2001 bus-r <<
2002 <<
2003 #addr <<
2004 #size <<
2005 range <<
2006 }; <<
2007 }; 2004 };
2008 2005
2009 pcie2: pcie@610000 { 2006 pcie2: pcie@610000 {
2010 compatible = 2007 compatible = "qcom,pcie-msm8996";
2011 power-domains 2008 power-domains = <&gcc PCIE2_GDSC>;
2012 bus-range = < 2009 bus-range = <0x00 0xff>;
2013 num-lanes = < 2010 num-lanes = <1>;
2014 status = "dis 2011 status = "disabled";
2015 reg = <0x0061 2012 reg = <0x00610000 0x2000>,
2016 <0x0e00 2013 <0x0e000000 0xf1d>,
2017 <0x0e00 2014 <0x0e000f20 0xa8>,
2018 <0x0e10 2015 <0x0e100000 0x100000>;
2019 2016
2020 reg-names = " 2017 reg-names = "parf", "dbi", "elbi","config";
2021 2018
2022 phys = <&pcie 2019 phys = <&pciephy_2>;
2023 phy-names = " 2020 phy-names = "pciephy";
2024 2021
2025 #address-cell 2022 #address-cells = <3>;
2026 #size-cells = 2023 #size-cells = <2>;
2027 ranges = <0x0 2024 ranges = <0x01000000 0x0 0x00000000 0x0e200000 0x0 0x100000>,
2028 <0x0 2025 <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>;
2029 2026
2030 device_type = 2027 device_type = "pci";
2031 2028
2032 interrupts = 2029 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
2033 interrupt-nam 2030 interrupt-names = "msi";
2034 #interrupt-ce 2031 #interrupt-cells = <1>;
2035 interrupt-map 2032 interrupt-map-mask = <0 0 0 0x7>;
2036 interrupt-map 2033 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2037 2034 <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2038 2035 <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2039 2036 <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2040 2037
2041 pinctrl-names 2038 pinctrl-names = "default", "sleep";
2042 pinctrl-0 = < 2039 pinctrl-0 = <&pcie2_state_on>;
2043 pinctrl-1 = < 2040 pinctrl-1 = <&pcie2_state_off>;
2044 2041
2045 linux,pci-dom 2042 linux,pci-domain = <2>;
2046 clocks = <&gc 2043 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
2047 <&gcc 2044 <&gcc GCC_PCIE_2_AUX_CLK>,
2048 <&gcc 2045 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2049 <&gcc 2046 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
2050 <&gcc 2047 <&gcc GCC_PCIE_2_SLV_AXI_CLK>;
2051 2048
2052 clock-names = 2049 clock-names = "pipe",
2053 2050 "aux",
2054 2051 "cfg",
2055 2052 "bus_master",
2056 2053 "bus_slave";
2057 <<
2058 pcie@0 { <<
2059 devic <<
2060 reg = <<
2061 bus-r <<
2062 <<
2063 #addr <<
2064 #size <<
2065 range <<
2066 }; <<
2067 }; 2054 };
2068 }; 2055 };
2069 2056
2070 ufshc: ufshc@624000 { 2057 ufshc: ufshc@624000 {
2071 compatible = "qcom,ms 2058 compatible = "qcom,msm8996-ufshc", "qcom,ufshc",
2072 "jedec,u 2059 "jedec,ufs-2.0";
2073 reg = <0x00624000 0x2 2060 reg = <0x00624000 0x2500>;
2074 interrupts = <GIC_SPI 2061 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2075 2062
2076 phys = <&ufsphy>; !! 2063 phys = <&ufsphy_lane>;
2077 phy-names = "ufsphy"; 2064 phy-names = "ufsphy";
2078 2065
2079 power-domains = <&gcc 2066 power-domains = <&gcc UFS_GDSC>;
2080 2067
2081 clock-names = 2068 clock-names =
>> 2069 "core_clk_src",
2082 "core_clk", 2070 "core_clk",
2083 "bus_clk", 2071 "bus_clk",
2084 "bus_aggr_clk 2072 "bus_aggr_clk",
2085 "iface_clk", 2073 "iface_clk",
>> 2074 "core_clk_unipro_src",
2086 "core_clk_uni 2075 "core_clk_unipro",
2087 "core_clk_ice 2076 "core_clk_ice",
2088 "ref_clk", 2077 "ref_clk",
2089 "tx_lane0_syn 2078 "tx_lane0_sync_clk",
2090 "rx_lane0_syn 2079 "rx_lane0_sync_clk";
2091 clocks = 2080 clocks =
>> 2081 <&gcc UFS_AXI_CLK_SRC>,
2092 <&gcc GCC_UFS 2082 <&gcc GCC_UFS_AXI_CLK>,
2093 <&gcc GCC_SYS 2083 <&gcc GCC_SYS_NOC_UFS_AXI_CLK>,
2094 <&gcc GCC_AGG 2084 <&gcc GCC_AGGRE2_UFS_AXI_CLK>,
2095 <&gcc GCC_UFS 2085 <&gcc GCC_UFS_AHB_CLK>,
>> 2086 <&gcc UFS_ICE_CORE_CLK_SRC>,
2096 <&gcc GCC_UFS 2087 <&gcc GCC_UFS_UNIPRO_CORE_CLK>,
2097 <&gcc GCC_UFS 2088 <&gcc GCC_UFS_ICE_CORE_CLK>,
2098 <&rpmcc RPM_S 2089 <&rpmcc RPM_SMD_LN_BB_CLK>,
2099 <&gcc GCC_UFS 2090 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
2100 <&gcc GCC_UFS 2091 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>;
2101 freq-table-hz = 2092 freq-table-hz =
2102 <100000000 20 2093 <100000000 200000000>,
2103 <0 0>, 2094 <0 0>,
2104 <0 0>, 2095 <0 0>,
2105 <0 0>, 2096 <0 0>,
2106 <75000000 150 !! 2097 <0 0>,
2107 <150000000 30 2098 <150000000 300000000>,
2108 <0 0>, 2099 <0 0>,
2109 <0 0>, 2100 <0 0>,
>> 2101 <0 0>,
>> 2102 <0 0>,
2110 <0 0>; 2103 <0 0>;
2111 2104
2112 interconnects = <&a2n 2105 interconnects = <&a2noc MASTER_UFS &bimc SLAVE_EBI_CH0>,
2113 <&bim 2106 <&bimc MASTER_AMPSS_M0 &cnoc SLAVE_UFS_CFG>;
2114 interconnect-names = 2107 interconnect-names = "ufs-ddr", "cpu-ufs";
2115 2108
2116 lanes-per-direction = 2109 lanes-per-direction = <1>;
2117 #reset-cells = <1>; 2110 #reset-cells = <1>;
2118 status = "disabled"; 2111 status = "disabled";
2119 }; 2112 };
2120 2113
2121 ufsphy: phy@627000 { 2114 ufsphy: phy@627000 {
2122 compatible = "qcom,ms 2115 compatible = "qcom,msm8996-qmp-ufs-phy";
2123 reg = <0x00627000 0x1 !! 2116 reg = <0x00627000 0x1c4>;
>> 2117 #address-cells = <1>;
>> 2118 #size-cells = <1>;
>> 2119 ranges;
2124 2120
2125 clocks = <&rpmcc RPM_ !! 2121 clocks = <&gcc GCC_UFS_CLKREF_CLK>;
2126 clock-names = "ref", !! 2122 clock-names = "ref";
2127 2123
2128 resets = <&ufshc 0>; 2124 resets = <&ufshc 0>;
2129 reset-names = "ufsphy 2125 reset-names = "ufsphy";
2130 <<
2131 #clock-cells = <1>; <<
2132 #phy-cells = <0>; <<
2133 <<
2134 status = "disabled"; 2126 status = "disabled";
>> 2127
>> 2128 ufsphy_lane: phy@627400 {
>> 2129 reg = <0x627400 0x12c>,
>> 2130 <0x627600 0x200>,
>> 2131 <0x627c00 0x1b4>;
>> 2132 #clock-cells = <1>;
>> 2133 #phy-cells = <0>;
>> 2134 };
2135 }; 2135 };
2136 2136
2137 camss: camss@a34000 { 2137 camss: camss@a34000 {
2138 compatible = "qcom,ms 2138 compatible = "qcom,msm8996-camss";
2139 reg = <0x00a34000 0x1 2139 reg = <0x00a34000 0x1000>,
2140 <0x00a00030 0x4 2140 <0x00a00030 0x4>,
2141 <0x00a35000 0x1 2141 <0x00a35000 0x1000>,
2142 <0x00a00038 0x4 2142 <0x00a00038 0x4>,
2143 <0x00a36000 0x1 2143 <0x00a36000 0x1000>,
2144 <0x00a00040 0x4 2144 <0x00a00040 0x4>,
2145 <0x00a30000 0x1 2145 <0x00a30000 0x100>,
2146 <0x00a30400 0x1 2146 <0x00a30400 0x100>,
2147 <0x00a30800 0x1 2147 <0x00a30800 0x100>,
2148 <0x00a30c00 0x1 2148 <0x00a30c00 0x100>,
2149 <0x00a31000 0x5 2149 <0x00a31000 0x500>,
2150 <0x00a00020 0x1 2150 <0x00a00020 0x10>,
2151 <0x00a10000 0x1 2151 <0x00a10000 0x1000>,
2152 <0x00a14000 0x1 2152 <0x00a14000 0x1000>;
2153 reg-names = "csiphy0" 2153 reg-names = "csiphy0",
2154 "csiphy0_clk_ 2154 "csiphy0_clk_mux",
2155 "csiphy1", 2155 "csiphy1",
2156 "csiphy1_clk_ 2156 "csiphy1_clk_mux",
2157 "csiphy2", 2157 "csiphy2",
2158 "csiphy2_clk_ 2158 "csiphy2_clk_mux",
2159 "csid0", 2159 "csid0",
2160 "csid1", 2160 "csid1",
2161 "csid2", 2161 "csid2",
2162 "csid3", 2162 "csid3",
2163 "ispif", 2163 "ispif",
2164 "csi_clk_mux" 2164 "csi_clk_mux",
2165 "vfe0", 2165 "vfe0",
2166 "vfe1"; 2166 "vfe1";
2167 interrupts = <GIC_SPI 2167 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
2168 <GIC_SPI 79 I 2168 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
2169 <GIC_SPI 80 I 2169 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
2170 <GIC_SPI 296 2170 <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
2171 <GIC_SPI 297 2171 <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
2172 <GIC_SPI 298 2172 <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
2173 <GIC_SPI 299 2173 <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
2174 <GIC_SPI 309 2174 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>,
2175 <GIC_SPI 314 2175 <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
2176 <GIC_SPI 315 2176 <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>;
2177 interrupt-names = "cs 2177 interrupt-names = "csiphy0",
2178 "csiphy1", 2178 "csiphy1",
2179 "csiphy2", 2179 "csiphy2",
2180 "csid0", 2180 "csid0",
2181 "csid1", 2181 "csid1",
2182 "csid2", 2182 "csid2",
2183 "csid3", 2183 "csid3",
2184 "ispif", 2184 "ispif",
2185 "vfe0", 2185 "vfe0",
2186 "vfe1"; 2186 "vfe1";
2187 power-domains = <&mmc 2187 power-domains = <&mmcc VFE0_GDSC>,
2188 <&mmc 2188 <&mmcc VFE1_GDSC>;
2189 clocks = <&mmcc CAMSS 2189 clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
2190 <&mmcc CAMSS_ 2190 <&mmcc CAMSS_ISPIF_AHB_CLK>,
2191 <&mmcc CAMSS_ 2191 <&mmcc CAMSS_CSI0PHYTIMER_CLK>,
2192 <&mmcc CAMSS_ 2192 <&mmcc CAMSS_CSI1PHYTIMER_CLK>,
2193 <&mmcc CAMSS_ 2193 <&mmcc CAMSS_CSI2PHYTIMER_CLK>,
2194 <&mmcc CAMSS_ 2194 <&mmcc CAMSS_CSI0_AHB_CLK>,
2195 <&mmcc CAMSS_ 2195 <&mmcc CAMSS_CSI0_CLK>,
2196 <&mmcc CAMSS_ 2196 <&mmcc CAMSS_CSI0PHY_CLK>,
2197 <&mmcc CAMSS_ 2197 <&mmcc CAMSS_CSI0PIX_CLK>,
2198 <&mmcc CAMSS_ 2198 <&mmcc CAMSS_CSI0RDI_CLK>,
2199 <&mmcc CAMSS_ 2199 <&mmcc CAMSS_CSI1_AHB_CLK>,
2200 <&mmcc CAMSS_ 2200 <&mmcc CAMSS_CSI1_CLK>,
2201 <&mmcc CAMSS_ 2201 <&mmcc CAMSS_CSI1PHY_CLK>,
2202 <&mmcc CAMSS_ 2202 <&mmcc CAMSS_CSI1PIX_CLK>,
2203 <&mmcc CAMSS_ 2203 <&mmcc CAMSS_CSI1RDI_CLK>,
2204 <&mmcc CAMSS_ 2204 <&mmcc CAMSS_CSI2_AHB_CLK>,
2205 <&mmcc CAMSS_ 2205 <&mmcc CAMSS_CSI2_CLK>,
2206 <&mmcc CAMSS_ 2206 <&mmcc CAMSS_CSI2PHY_CLK>,
2207 <&mmcc CAMSS_ 2207 <&mmcc CAMSS_CSI2PIX_CLK>,
2208 <&mmcc CAMSS_ 2208 <&mmcc CAMSS_CSI2RDI_CLK>,
2209 <&mmcc CAMSS_ 2209 <&mmcc CAMSS_CSI3_AHB_CLK>,
2210 <&mmcc CAMSS_ 2210 <&mmcc CAMSS_CSI3_CLK>,
2211 <&mmcc CAMSS_ 2211 <&mmcc CAMSS_CSI3PHY_CLK>,
2212 <&mmcc CAMSS_ 2212 <&mmcc CAMSS_CSI3PIX_CLK>,
2213 <&mmcc CAMSS_ 2213 <&mmcc CAMSS_CSI3RDI_CLK>,
2214 <&mmcc CAMSS_ 2214 <&mmcc CAMSS_AHB_CLK>,
2215 <&mmcc CAMSS_ 2215 <&mmcc CAMSS_VFE0_CLK>,
2216 <&mmcc CAMSS_ 2216 <&mmcc CAMSS_CSI_VFE0_CLK>,
2217 <&mmcc CAMSS_ 2217 <&mmcc CAMSS_VFE0_AHB_CLK>,
2218 <&mmcc CAMSS_ 2218 <&mmcc CAMSS_VFE0_STREAM_CLK>,
2219 <&mmcc CAMSS_ 2219 <&mmcc CAMSS_VFE1_CLK>,
2220 <&mmcc CAMSS_ 2220 <&mmcc CAMSS_CSI_VFE1_CLK>,
2221 <&mmcc CAMSS_ 2221 <&mmcc CAMSS_VFE1_AHB_CLK>,
2222 <&mmcc CAMSS_ 2222 <&mmcc CAMSS_VFE1_STREAM_CLK>,
2223 <&mmcc CAMSS_ 2223 <&mmcc CAMSS_VFE_AHB_CLK>,
2224 <&mmcc CAMSS_ 2224 <&mmcc CAMSS_VFE_AXI_CLK>;
2225 clock-names = "top_ah 2225 clock-names = "top_ahb",
2226 "ispif_ahb", 2226 "ispif_ahb",
2227 "csiphy0_time 2227 "csiphy0_timer",
2228 "csiphy1_time 2228 "csiphy1_timer",
2229 "csiphy2_time 2229 "csiphy2_timer",
2230 "csi0_ahb", 2230 "csi0_ahb",
2231 "csi0", 2231 "csi0",
2232 "csi0_phy", 2232 "csi0_phy",
2233 "csi0_pix", 2233 "csi0_pix",
2234 "csi0_rdi", 2234 "csi0_rdi",
2235 "csi1_ahb", 2235 "csi1_ahb",
2236 "csi1", 2236 "csi1",
2237 "csi1_phy", 2237 "csi1_phy",
2238 "csi1_pix", 2238 "csi1_pix",
2239 "csi1_rdi", 2239 "csi1_rdi",
2240 "csi2_ahb", 2240 "csi2_ahb",
2241 "csi2", 2241 "csi2",
2242 "csi2_phy", 2242 "csi2_phy",
2243 "csi2_pix", 2243 "csi2_pix",
2244 "csi2_rdi", 2244 "csi2_rdi",
2245 "csi3_ahb", 2245 "csi3_ahb",
2246 "csi3", 2246 "csi3",
2247 "csi3_phy", 2247 "csi3_phy",
2248 "csi3_pix", 2248 "csi3_pix",
2249 "csi3_rdi", 2249 "csi3_rdi",
2250 "ahb", 2250 "ahb",
2251 "vfe0", 2251 "vfe0",
2252 "csi_vfe0", 2252 "csi_vfe0",
2253 "vfe0_ahb", 2253 "vfe0_ahb",
2254 "vfe0_stream" 2254 "vfe0_stream",
2255 "vfe1", 2255 "vfe1",
2256 "csi_vfe1", 2256 "csi_vfe1",
2257 "vfe1_ahb", 2257 "vfe1_ahb",
2258 "vfe1_stream" 2258 "vfe1_stream",
2259 "vfe_ahb", 2259 "vfe_ahb",
2260 "vfe_axi"; 2260 "vfe_axi";
2261 iommus = <&vfe_smmu 0 2261 iommus = <&vfe_smmu 0>,
2262 <&vfe_smmu 1 2262 <&vfe_smmu 1>,
2263 <&vfe_smmu 2 2263 <&vfe_smmu 2>,
2264 <&vfe_smmu 3 2264 <&vfe_smmu 3>;
2265 status = "disabled"; 2265 status = "disabled";
2266 ports { 2266 ports {
2267 #address-cell 2267 #address-cells = <1>;
2268 #size-cells = 2268 #size-cells = <0>;
2269 }; 2269 };
2270 }; 2270 };
2271 2271
2272 cci: cci@a0c000 { 2272 cci: cci@a0c000 {
2273 compatible = "qcom,ms 2273 compatible = "qcom,msm8996-cci";
2274 #address-cells = <1>; 2274 #address-cells = <1>;
2275 #size-cells = <0>; 2275 #size-cells = <0>;
2276 reg = <0xa0c000 0x100 2276 reg = <0xa0c000 0x1000>;
2277 interrupts = <GIC_SPI 2277 interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>;
2278 power-domains = <&mmc 2278 power-domains = <&mmcc CAMSS_GDSC>;
2279 clocks = <&mmcc CAMSS 2279 clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
2280 <&mmcc CAMSS 2280 <&mmcc CAMSS_CCI_AHB_CLK>,
2281 <&mmcc CAMSS 2281 <&mmcc CAMSS_CCI_CLK>,
2282 <&mmcc CAMSS 2282 <&mmcc CAMSS_AHB_CLK>;
2283 clock-names = "camss_ 2283 clock-names = "camss_top_ahb",
2284 "cci_ah 2284 "cci_ahb",
2285 "cci", 2285 "cci",
2286 "camss_ 2286 "camss_ahb";
2287 assigned-clocks = <&m 2287 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>,
2288 <&m 2288 <&mmcc CAMSS_CCI_CLK>;
2289 assigned-clock-rates 2289 assigned-clock-rates = <80000000>, <37500000>;
2290 pinctrl-names = "defa 2290 pinctrl-names = "default";
2291 pinctrl-0 = <&cci0_de 2291 pinctrl-0 = <&cci0_default &cci1_default>;
2292 status = "disabled"; 2292 status = "disabled";
2293 2293
2294 cci_i2c0: i2c-bus@0 { 2294 cci_i2c0: i2c-bus@0 {
2295 reg = <0>; 2295 reg = <0>;
2296 clock-frequen 2296 clock-frequency = <400000>;
2297 #address-cell 2297 #address-cells = <1>;
2298 #size-cells = 2298 #size-cells = <0>;
2299 }; 2299 };
2300 2300
2301 cci_i2c1: i2c-bus@1 { 2301 cci_i2c1: i2c-bus@1 {
2302 reg = <1>; 2302 reg = <1>;
2303 clock-frequen 2303 clock-frequency = <400000>;
2304 #address-cell 2304 #address-cells = <1>;
2305 #size-cells = 2305 #size-cells = <0>;
2306 }; 2306 };
2307 }; 2307 };
2308 2308
2309 adreno_smmu: iommu@b40000 { 2309 adreno_smmu: iommu@b40000 {
2310 compatible = "qcom,ms 2310 compatible = "qcom,msm8996-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
2311 reg = <0x00b40000 0x1 2311 reg = <0x00b40000 0x10000>;
2312 2312
2313 #global-interrupts = 2313 #global-interrupts = <1>;
2314 interrupts = <GIC_SPI 2314 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
2315 <GIC_SPI 2315 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
2316 <GIC_SPI 2316 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
2317 #iommu-cells = <1>; 2317 #iommu-cells = <1>;
2318 2318
2319 clocks = <&gcc GCC_MM 2319 clocks = <&gcc GCC_MMSS_BIMC_GFX_CLK>,
2320 <&mmcc GPU_A 2320 <&mmcc GPU_AHB_CLK>;
2321 clock-names = "bus", 2321 clock-names = "bus", "iface";
2322 2322
2323 power-domains = <&mmc 2323 power-domains = <&mmcc GPU_GDSC>;
2324 }; 2324 };
2325 2325
2326 venus: video-codec@c00000 { 2326 venus: video-codec@c00000 {
2327 compatible = "qcom,ms 2327 compatible = "qcom,msm8996-venus";
2328 reg = <0x00c00000 0xf 2328 reg = <0x00c00000 0xff000>;
2329 interrupts = <GIC_SPI 2329 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
2330 power-domains = <&mmc 2330 power-domains = <&mmcc VENUS_GDSC>;
2331 clocks = <&mmcc VIDEO 2331 clocks = <&mmcc VIDEO_CORE_CLK>,
2332 <&mmcc VIDEO 2332 <&mmcc VIDEO_AHB_CLK>,
2333 <&mmcc VIDEO 2333 <&mmcc VIDEO_AXI_CLK>,
2334 <&mmcc VIDEO 2334 <&mmcc VIDEO_MAXI_CLK>;
2335 clock-names = "core", 2335 clock-names = "core", "iface", "bus", "mbus";
2336 interconnects = <&mno 2336 interconnects = <&mnoc MASTER_VIDEO_P0 &bimc SLAVE_EBI_CH0>,
2337 <&bim 2337 <&bimc MASTER_AMPSS_M0 &mnoc SLAVE_VENUS_CFG>;
2338 interconnect-names = 2338 interconnect-names = "video-mem", "cpu-cfg";
2339 iommus = <&venus_smmu 2339 iommus = <&venus_smmu 0x00>,
2340 <&venus_smmu 2340 <&venus_smmu 0x01>,
2341 <&venus_smmu 2341 <&venus_smmu 0x0a>,
2342 <&venus_smmu 2342 <&venus_smmu 0x07>,
2343 <&venus_smmu 2343 <&venus_smmu 0x0e>,
2344 <&venus_smmu 2344 <&venus_smmu 0x0f>,
2345 <&venus_smmu 2345 <&venus_smmu 0x08>,
2346 <&venus_smmu 2346 <&venus_smmu 0x09>,
2347 <&venus_smmu 2347 <&venus_smmu 0x0b>,
2348 <&venus_smmu 2348 <&venus_smmu 0x0c>,
2349 <&venus_smmu 2349 <&venus_smmu 0x0d>,
2350 <&venus_smmu 2350 <&venus_smmu 0x10>,
2351 <&venus_smmu 2351 <&venus_smmu 0x11>,
2352 <&venus_smmu 2352 <&venus_smmu 0x21>,
2353 <&venus_smmu 2353 <&venus_smmu 0x28>,
2354 <&venus_smmu 2354 <&venus_smmu 0x29>,
2355 <&venus_smmu 2355 <&venus_smmu 0x2b>,
2356 <&venus_smmu 2356 <&venus_smmu 0x2c>,
2357 <&venus_smmu 2357 <&venus_smmu 0x2d>,
2358 <&venus_smmu 2358 <&venus_smmu 0x31>;
2359 memory-region = <&ven 2359 memory-region = <&venus_mem>;
2360 status = "disabled"; 2360 status = "disabled";
2361 2361
2362 video-decoder { 2362 video-decoder {
2363 compatible = 2363 compatible = "venus-decoder";
2364 clocks = <&mm 2364 clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
2365 clock-names = 2365 clock-names = "core";
2366 power-domains 2366 power-domains = <&mmcc VENUS_CORE0_GDSC>;
2367 }; 2367 };
2368 2368
2369 video-encoder { 2369 video-encoder {
2370 compatible = 2370 compatible = "venus-encoder";
2371 clocks = <&mm 2371 clocks = <&mmcc VIDEO_SUBCORE1_CLK>;
2372 clock-names = 2372 clock-names = "core";
2373 power-domains 2373 power-domains = <&mmcc VENUS_CORE1_GDSC>;
2374 }; 2374 };
2375 }; 2375 };
2376 2376
2377 mdp_smmu: iommu@d00000 { 2377 mdp_smmu: iommu@d00000 {
2378 compatible = "qcom,ms 2378 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2379 reg = <0x00d00000 0x1 2379 reg = <0x00d00000 0x10000>;
2380 2380
2381 #global-interrupts = 2381 #global-interrupts = <1>;
2382 interrupts = <GIC_SPI 2382 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
2383 <GIC_SPI 2383 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
2384 <GIC_SPI 2384 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
2385 #iommu-cells = <1>; 2385 #iommu-cells = <1>;
2386 clocks = <&mmcc SMMU_ 2386 clocks = <&mmcc SMMU_MDP_AXI_CLK>,
2387 <&mmcc SMMU_ 2387 <&mmcc SMMU_MDP_AHB_CLK>;
2388 clock-names = "bus", 2388 clock-names = "bus", "iface";
2389 2389
2390 power-domains = <&mmc 2390 power-domains = <&mmcc MDSS_GDSC>;
2391 }; 2391 };
2392 2392
2393 venus_smmu: iommu@d40000 { 2393 venus_smmu: iommu@d40000 {
2394 compatible = "qcom,ms 2394 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2395 reg = <0x00d40000 0x2 2395 reg = <0x00d40000 0x20000>;
2396 #global-interrupts = 2396 #global-interrupts = <1>;
2397 interrupts = <GIC_SPI 2397 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
2398 <GIC_SPI 2398 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
2399 <GIC_SPI 2399 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
2400 <GIC_SPI 2400 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
2401 <GIC_SPI 2401 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
2402 <GIC_SPI 2402 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
2403 <GIC_SPI 2403 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
2404 <GIC_SPI 2404 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
2405 power-domains = <&mmc 2405 power-domains = <&mmcc MMAGIC_VIDEO_GDSC>;
2406 clocks = <&mmcc SMMU_ 2406 clocks = <&mmcc SMMU_VIDEO_AXI_CLK>,
2407 <&mmcc SMMU_ 2407 <&mmcc SMMU_VIDEO_AHB_CLK>;
2408 clock-names = "bus", 2408 clock-names = "bus", "iface";
2409 #iommu-cells = <1>; 2409 #iommu-cells = <1>;
2410 status = "okay"; 2410 status = "okay";
2411 }; 2411 };
2412 2412
2413 vfe_smmu: iommu@da0000 { 2413 vfe_smmu: iommu@da0000 {
2414 compatible = "qcom,ms 2414 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2415 reg = <0x00da0000 0x1 2415 reg = <0x00da0000 0x10000>;
2416 2416
2417 #global-interrupts = 2417 #global-interrupts = <1>;
2418 interrupts = <GIC_SPI 2418 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
2419 <GIC_SPI 2419 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
2420 <GIC_SPI 2420 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
2421 power-domains = <&mmc 2421 power-domains = <&mmcc MMAGIC_CAMSS_GDSC>;
2422 clocks = <&mmcc SMMU_ 2422 clocks = <&mmcc SMMU_VFE_AXI_CLK>,
2423 <&mmcc SMMU_ 2423 <&mmcc SMMU_VFE_AHB_CLK>;
2424 clock-names = "bus", 2424 clock-names = "bus", "iface";
2425 #iommu-cells = <1>; 2425 #iommu-cells = <1>;
2426 }; 2426 };
2427 2427
2428 lpass_q6_smmu: iommu@1600000 2428 lpass_q6_smmu: iommu@1600000 {
2429 compatible = "qcom,ms 2429 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2430 reg = <0x01600000 0x2 2430 reg = <0x01600000 0x20000>;
2431 #iommu-cells = <1>; 2431 #iommu-cells = <1>;
2432 power-domains = <&gcc 2432 power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>;
2433 2433
2434 #global-interrupts = 2434 #global-interrupts = <1>;
2435 interrupts = <GIC_SPI 2435 interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
2436 <GIC_SPI 226 2436 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
2437 <GIC_SPI 393 2437 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
2438 <GIC_SPI 394 2438 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
2439 <GIC_SPI 395 2439 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
2440 <GIC_SPI 396 2440 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
2441 <GIC_SPI 397 2441 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
2442 <GIC_SPI 398 2442 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
2443 <GIC_SPI 399 2443 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
2444 <GIC_SPI 400 2444 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
2445 <GIC_SPI 401 2445 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
2446 <GIC_SPI 402 2446 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
2447 <GIC_SPI 403 2447 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>;
2448 2448
2449 clocks = <&gcc GCC_HL 2449 clocks = <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>,
2450 <&gcc GCC_HL 2450 <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>;
2451 clock-names = "bus", 2451 clock-names = "bus", "iface";
2452 }; 2452 };
2453 2453
2454 slpi_pil: remoteproc@1c00000 2454 slpi_pil: remoteproc@1c00000 {
2455 compatible = "qcom,ms 2455 compatible = "qcom,msm8996-slpi-pil";
2456 reg = <0x01c00000 0x4 2456 reg = <0x01c00000 0x4000>;
2457 2457
2458 interrupts-extended = 2458 interrupts-extended = <&intc 0 390 IRQ_TYPE_EDGE_RISING>,
2459 2459 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2460 2460 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2461 2461 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2462 2462 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2463 interrupt-names = "wd 2463 interrupt-names = "wdog",
2464 "fa 2464 "fatal",
2465 "re 2465 "ready",
2466 "ha 2466 "handover",
2467 "st 2467 "stop-ack";
2468 2468
2469 clocks = <&xo_board>; !! 2469 clocks = <&xo_board>,
2470 clock-names = "xo"; !! 2470 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
>> 2471 clock-names = "xo", "aggre2";
2471 2472
2472 memory-region = <&slp 2473 memory-region = <&slpi_mem>;
2473 2474
2474 qcom,smem-states = <& 2475 qcom,smem-states = <&slpi_smp2p_out 0>;
2475 qcom,smem-state-names 2476 qcom,smem-state-names = "stop";
2476 2477
2477 power-domains = <&rpm 2478 power-domains = <&rpmpd MSM8996_VDDSSCX>;
2478 power-domain-names = 2479 power-domain-names = "ssc_cx";
2479 2480
2480 status = "disabled"; 2481 status = "disabled";
2481 2482
2482 glink-edge { <<
2483 interrupts = <<
2484 label = "dsps <<
2485 qcom,remote-p <<
2486 mboxes = <&ap <<
2487 }; <<
2488 <<
2489 smd-edge { 2483 smd-edge {
2490 interrupts = 2484 interrupts = <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>;
2491 2485
2492 label = "dsps 2486 label = "dsps";
2493 mboxes = <&ap 2487 mboxes = <&apcs_glb 25>;
2494 qcom,smd-edge 2488 qcom,smd-edge = <3>;
2495 qcom,remote-p 2489 qcom,remote-pid = <3>;
2496 }; 2490 };
2497 }; 2491 };
2498 2492
2499 mss_pil: remoteproc@2080000 { 2493 mss_pil: remoteproc@2080000 {
2500 compatible = "qcom,ms 2494 compatible = "qcom,msm8996-mss-pil";
2501 reg = <0x2080000 0x10 2495 reg = <0x2080000 0x100>,
2502 <0x2180000 0x02 2496 <0x2180000 0x020>;
2503 reg-names = "qdsp6", 2497 reg-names = "qdsp6", "rmb";
2504 2498
2505 interrupts-extended = 2499 interrupts-extended = <&intc 0 448 IRQ_TYPE_EDGE_RISING>,
2506 2500 <&mpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2507 2501 <&mpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2508 2502 <&mpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2509 2503 <&mpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
2510 2504 <&mpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
2511 interrupt-names = "wd 2505 interrupt-names = "wdog", "fatal", "ready",
2512 "ha 2506 "handover", "stop-ack",
2513 "sh 2507 "shutdown-ack";
2514 2508
2515 clocks = <&gcc GCC_MS 2509 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
2516 <&gcc GCC_MS 2510 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
2517 <&gcc GCC_BO 2511 <&gcc GCC_BOOT_ROM_AHB_CLK>,
2518 <&xo_board>, 2512 <&xo_board>,
2519 <&gcc GCC_MS 2513 <&gcc GCC_MSS_GPLL0_DIV_CLK>,
2520 <&gcc GCC_MS 2514 <&gcc GCC_MSS_SNOC_AXI_CLK>,
2521 <&gcc GCC_MS 2515 <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>,
>> 2516 <&rpmcc RPM_SMD_PCNOC_CLK>,
2522 <&rpmcc RPM_ 2517 <&rpmcc RPM_SMD_QDSS_CLK>;
2523 clock-names = "iface" !! 2518 clock-names = "iface", "bus", "mem", "xo", "gpll0_mss",
2524 "bus", !! 2519 "snoc_axi", "mnoc_axi", "pnoc", "qdss";
2525 "mem", <<
2526 "xo", <<
2527 "gpll0_ <<
2528 "snoc_a <<
2529 "mnoc_a <<
2530 "qdss"; <<
2531 2520
2532 resets = <&gcc GCC_MS 2521 resets = <&gcc GCC_MSS_RESTART>;
2533 reset-names = "mss_re 2522 reset-names = "mss_restart";
2534 2523
2535 power-domains = <&rpm 2524 power-domains = <&rpmpd MSM8996_VDDCX>,
2536 <&rpm 2525 <&rpmpd MSM8996_VDDMX>;
2537 power-domain-names = 2526 power-domain-names = "cx", "mx";
2538 2527
2539 qcom,smem-states = <& 2528 qcom,smem-states = <&mpss_smp2p_out 0>;
2540 qcom,smem-state-names 2529 qcom,smem-state-names = "stop";
2541 2530
2542 qcom,halt-regs = <&tc 2531 qcom,halt-regs = <&tcsr_1 0x3000 0x5000 0x4000>;
2543 2532
2544 status = "disabled"; 2533 status = "disabled";
2545 2534
2546 mba { 2535 mba {
2547 memory-region 2536 memory-region = <&mba_mem>;
2548 }; 2537 };
2549 2538
2550 mpss { 2539 mpss {
2551 memory-region 2540 memory-region = <&mpss_mem>;
2552 }; 2541 };
2553 2542
2554 metadata { 2543 metadata {
2555 memory-region 2544 memory-region = <&mdata_mem>;
2556 }; 2545 };
2557 2546
2558 glink-edge { <<
2559 interrupts = <<
2560 label = "mode <<
2561 qcom,remote-p <<
2562 mboxes = <&ap <<
2563 }; <<
2564 <<
2565 smd-edge { 2547 smd-edge {
2566 interrupts = 2548 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
2567 2549
2568 label = "mpss 2550 label = "mpss";
2569 mboxes = <&ap 2551 mboxes = <&apcs_glb 12>;
2570 qcom,smd-edge 2552 qcom,smd-edge = <0>;
2571 qcom,remote-p 2553 qcom,remote-pid = <1>;
2572 }; 2554 };
2573 }; 2555 };
2574 2556
2575 stm@3002000 { 2557 stm@3002000 {
2576 compatible = "arm,cor 2558 compatible = "arm,coresight-stm", "arm,primecell";
2577 reg = <0x3002000 0x10 2559 reg = <0x3002000 0x1000>,
2578 <0x8280000 0x18 2560 <0x8280000 0x180000>;
2579 reg-names = "stm-base 2561 reg-names = "stm-base", "stm-stimulus-base";
2580 2562
2581 clocks = <&rpmcc RPM_ 2563 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2582 clock-names = "apb_pc 2564 clock-names = "apb_pclk", "atclk";
2583 2565
2584 out-ports { 2566 out-ports {
2585 port { 2567 port {
2586 stm_o 2568 stm_out: endpoint {
2587 2569 remote-endpoint =
2588 2570 <&funnel0_in>;
2589 }; 2571 };
2590 }; 2572 };
2591 }; 2573 };
2592 }; 2574 };
2593 2575
2594 tpiu@3020000 { 2576 tpiu@3020000 {
2595 compatible = "arm,cor 2577 compatible = "arm,coresight-tpiu", "arm,primecell";
2596 reg = <0x3020000 0x10 2578 reg = <0x3020000 0x1000>;
2597 2579
2598 clocks = <&rpmcc RPM_ 2580 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2599 clock-names = "apb_pc 2581 clock-names = "apb_pclk", "atclk";
2600 2582
2601 in-ports { 2583 in-ports {
2602 port { 2584 port {
2603 tpiu_ 2585 tpiu_in: endpoint {
2604 2586 remote-endpoint =
2605 2587 <&replicator_out1>;
2606 }; 2588 };
2607 }; 2589 };
2608 }; 2590 };
2609 }; 2591 };
2610 2592
2611 funnel@3021000 { 2593 funnel@3021000 {
2612 compatible = "arm,cor 2594 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2613 reg = <0x3021000 0x10 2595 reg = <0x3021000 0x1000>;
2614 2596
2615 clocks = <&rpmcc RPM_ 2597 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2616 clock-names = "apb_pc 2598 clock-names = "apb_pclk", "atclk";
2617 2599
2618 in-ports { 2600 in-ports {
2619 #address-cell 2601 #address-cells = <1>;
2620 #size-cells = 2602 #size-cells = <0>;
2621 2603
2622 port@7 { 2604 port@7 {
2623 reg = 2605 reg = <7>;
2624 funne 2606 funnel0_in: endpoint {
2625 2607 remote-endpoint =
2626 2608 <&stm_out>;
2627 }; 2609 };
2628 }; 2610 };
2629 }; 2611 };
2630 2612
2631 out-ports { 2613 out-ports {
2632 port { 2614 port {
2633 funne 2615 funnel0_out: endpoint {
2634 2616 remote-endpoint =
2635 2617 <&merge_funnel_in0>;
2636 }; 2618 };
2637 }; 2619 };
2638 }; 2620 };
2639 }; 2621 };
2640 2622
2641 funnel@3022000 { 2623 funnel@3022000 {
2642 compatible = "arm,cor 2624 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2643 reg = <0x3022000 0x10 2625 reg = <0x3022000 0x1000>;
2644 2626
2645 clocks = <&rpmcc RPM_ 2627 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2646 clock-names = "apb_pc 2628 clock-names = "apb_pclk", "atclk";
2647 2629
2648 in-ports { 2630 in-ports {
2649 #address-cell 2631 #address-cells = <1>;
2650 #size-cells = 2632 #size-cells = <0>;
2651 2633
2652 port@6 { 2634 port@6 {
2653 reg = 2635 reg = <6>;
2654 funne 2636 funnel1_in: endpoint {
2655 2637 remote-endpoint =
2656 2638 <&apss_merge_funnel_out>;
2657 }; 2639 };
2658 }; 2640 };
2659 }; 2641 };
2660 2642
2661 out-ports { 2643 out-ports {
2662 port { 2644 port {
2663 funne 2645 funnel1_out: endpoint {
2664 2646 remote-endpoint =
2665 2647 <&merge_funnel_in1>;
2666 }; 2648 };
2667 }; 2649 };
2668 }; 2650 };
2669 }; 2651 };
2670 2652
2671 funnel@3023000 { 2653 funnel@3023000 {
2672 compatible = "arm,cor 2654 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2673 reg = <0x3023000 0x10 2655 reg = <0x3023000 0x1000>;
2674 2656
2675 clocks = <&rpmcc RPM_ 2657 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2676 clock-names = "apb_pc 2658 clock-names = "apb_pclk", "atclk";
2677 2659
2678 in-ports { 2660 in-ports {
2679 port { 2661 port {
2680 funne 2662 funnel_in2_in_modem_etm: endpoint {
2681 2663 remote-endpoint =
2682 2664 <&modem_etm_out_funnel_in2>;
2683 }; 2665 };
2684 }; 2666 };
2685 }; 2667 };
2686 2668
2687 out-ports { 2669 out-ports {
2688 port { 2670 port {
2689 funne 2671 funnel2_out: endpoint {
2690 2672 remote-endpoint =
2691 2673 <&merge_funnel_in2>;
2692 }; 2674 };
2693 }; 2675 };
2694 }; 2676 };
2695 }; 2677 };
2696 2678
2697 funnel@3025000 { 2679 funnel@3025000 {
2698 compatible = "arm,cor 2680 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2699 reg = <0x3025000 0x10 2681 reg = <0x3025000 0x1000>;
2700 2682
2701 clocks = <&rpmcc RPM_ 2683 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2702 clock-names = "apb_pc 2684 clock-names = "apb_pclk", "atclk";
2703 2685
2704 in-ports { 2686 in-ports {
2705 #address-cell 2687 #address-cells = <1>;
2706 #size-cells = 2688 #size-cells = <0>;
2707 2689
2708 port@0 { 2690 port@0 {
2709 reg = 2691 reg = <0>;
2710 merge 2692 merge_funnel_in0: endpoint {
2711 2693 remote-endpoint =
2712 2694 <&funnel0_out>;
2713 }; 2695 };
2714 }; 2696 };
2715 2697
2716 port@1 { 2698 port@1 {
2717 reg = 2699 reg = <1>;
2718 merge 2700 merge_funnel_in1: endpoint {
2719 2701 remote-endpoint =
2720 2702 <&funnel1_out>;
2721 }; 2703 };
2722 }; 2704 };
2723 2705
2724 port@2 { 2706 port@2 {
2725 reg = 2707 reg = <2>;
2726 merge 2708 merge_funnel_in2: endpoint {
2727 2709 remote-endpoint =
2728 2710 <&funnel2_out>;
2729 }; 2711 };
2730 }; 2712 };
2731 }; 2713 };
2732 2714
2733 out-ports { 2715 out-ports {
2734 port { 2716 port {
2735 merge 2717 merge_funnel_out: endpoint {
2736 2718 remote-endpoint =
2737 2719 <&etf_in>;
2738 }; 2720 };
2739 }; 2721 };
2740 }; 2722 };
2741 }; 2723 };
2742 2724
2743 replicator@3026000 { 2725 replicator@3026000 {
2744 compatible = "arm,cor 2726 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2745 reg = <0x3026000 0x10 2727 reg = <0x3026000 0x1000>;
2746 2728
2747 clocks = <&rpmcc RPM_ 2729 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2748 clock-names = "apb_pc 2730 clock-names = "apb_pclk", "atclk";
2749 2731
2750 in-ports { 2732 in-ports {
2751 port { 2733 port {
2752 repli 2734 replicator_in: endpoint {
2753 2735 remote-endpoint =
2754 2736 <&etf_out>;
2755 }; 2737 };
2756 }; 2738 };
2757 }; 2739 };
2758 2740
2759 out-ports { 2741 out-ports {
2760 #address-cell 2742 #address-cells = <1>;
2761 #size-cells = 2743 #size-cells = <0>;
2762 2744
2763 port@0 { 2745 port@0 {
2764 reg = 2746 reg = <0>;
2765 repli 2747 replicator_out0: endpoint {
2766 2748 remote-endpoint =
2767 2749 <&etr_in>;
2768 }; 2750 };
2769 }; 2751 };
2770 2752
2771 port@1 { 2753 port@1 {
2772 reg = 2754 reg = <1>;
2773 repli 2755 replicator_out1: endpoint {
2774 2756 remote-endpoint =
2775 2757 <&tpiu_in>;
2776 }; 2758 };
2777 }; 2759 };
2778 }; 2760 };
2779 }; 2761 };
2780 2762
2781 etf@3027000 { 2763 etf@3027000 {
2782 compatible = "arm,cor 2764 compatible = "arm,coresight-tmc", "arm,primecell";
2783 reg = <0x3027000 0x10 2765 reg = <0x3027000 0x1000>;
2784 2766
2785 clocks = <&rpmcc RPM_ 2767 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2786 clock-names = "apb_pc 2768 clock-names = "apb_pclk", "atclk";
2787 2769
2788 in-ports { 2770 in-ports {
2789 port { 2771 port {
2790 etf_i 2772 etf_in: endpoint {
2791 2773 remote-endpoint =
2792 2774 <&merge_funnel_out>;
2793 }; 2775 };
2794 }; 2776 };
2795 }; 2777 };
2796 2778
2797 out-ports { 2779 out-ports {
2798 port { 2780 port {
2799 etf_o 2781 etf_out: endpoint {
2800 2782 remote-endpoint =
2801 2783 <&replicator_in>;
2802 }; 2784 };
2803 }; 2785 };
2804 }; 2786 };
2805 }; 2787 };
2806 2788
2807 etr@3028000 { 2789 etr@3028000 {
2808 compatible = "arm,cor 2790 compatible = "arm,coresight-tmc", "arm,primecell";
2809 reg = <0x3028000 0x10 2791 reg = <0x3028000 0x1000>;
2810 2792
2811 clocks = <&rpmcc RPM_ 2793 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2812 clock-names = "apb_pc 2794 clock-names = "apb_pclk", "atclk";
2813 arm,scatter-gather; 2795 arm,scatter-gather;
2814 2796
2815 in-ports { 2797 in-ports {
2816 port { 2798 port {
2817 etr_i 2799 etr_in: endpoint {
2818 2800 remote-endpoint =
2819 2801 <&replicator_out0>;
2820 }; 2802 };
2821 }; 2803 };
2822 }; 2804 };
2823 }; 2805 };
2824 2806
2825 debug@3810000 { 2807 debug@3810000 {
2826 compatible = "arm,cor 2808 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2827 reg = <0x3810000 0x10 2809 reg = <0x3810000 0x1000>;
2828 2810
2829 clocks = <&rpmcc RPM_ 2811 clocks = <&rpmcc RPM_QDSS_CLK>;
2830 clock-names = "apb_pc 2812 clock-names = "apb_pclk";
2831 2813
2832 cpu = <&CPU0>; 2814 cpu = <&CPU0>;
2833 }; 2815 };
2834 2816
2835 etm@3840000 { 2817 etm@3840000 {
2836 compatible = "arm,cor 2818 compatible = "arm,coresight-etm4x", "arm,primecell";
2837 reg = <0x3840000 0x10 2819 reg = <0x3840000 0x1000>;
2838 2820
2839 clocks = <&rpmcc RPM_ 2821 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2840 clock-names = "apb_pc 2822 clock-names = "apb_pclk", "atclk";
2841 2823
2842 cpu = <&CPU0>; 2824 cpu = <&CPU0>;
2843 2825
2844 out-ports { 2826 out-ports {
2845 port { 2827 port {
2846 etm0_ 2828 etm0_out: endpoint {
2847 2829 remote-endpoint =
2848 2830 <&apss_funnel0_in0>;
2849 }; 2831 };
2850 }; 2832 };
2851 }; 2833 };
2852 }; 2834 };
2853 2835
2854 debug@3910000 { 2836 debug@3910000 {
2855 compatible = "arm,cor 2837 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2856 reg = <0x3910000 0x10 2838 reg = <0x3910000 0x1000>;
2857 2839
2858 clocks = <&rpmcc RPM_ 2840 clocks = <&rpmcc RPM_QDSS_CLK>;
2859 clock-names = "apb_pc 2841 clock-names = "apb_pclk";
2860 2842
2861 cpu = <&CPU1>; 2843 cpu = <&CPU1>;
2862 }; 2844 };
2863 2845
2864 etm@3940000 { 2846 etm@3940000 {
2865 compatible = "arm,cor 2847 compatible = "arm,coresight-etm4x", "arm,primecell";
2866 reg = <0x3940000 0x10 2848 reg = <0x3940000 0x1000>;
2867 2849
2868 clocks = <&rpmcc RPM_ 2850 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2869 clock-names = "apb_pc 2851 clock-names = "apb_pclk", "atclk";
2870 2852
2871 cpu = <&CPU1>; 2853 cpu = <&CPU1>;
2872 2854
2873 out-ports { 2855 out-ports {
2874 port { 2856 port {
2875 etm1_ 2857 etm1_out: endpoint {
2876 2858 remote-endpoint =
2877 2859 <&apss_funnel0_in1>;
2878 }; 2860 };
2879 }; 2861 };
2880 }; 2862 };
2881 }; 2863 };
2882 2864
2883 funnel@39b0000 { /* APSS Funn 2865 funnel@39b0000 { /* APSS Funnel 0 */
2884 compatible = "arm,cor 2866 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2885 reg = <0x39b0000 0x10 2867 reg = <0x39b0000 0x1000>;
2886 2868
2887 clocks = <&rpmcc RPM_ 2869 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2888 clock-names = "apb_pc 2870 clock-names = "apb_pclk", "atclk";
2889 2871
2890 in-ports { 2872 in-ports {
2891 #address-cell 2873 #address-cells = <1>;
2892 #size-cells = 2874 #size-cells = <0>;
2893 2875
2894 port@0 { 2876 port@0 {
2895 reg = 2877 reg = <0>;
2896 apss_ 2878 apss_funnel0_in0: endpoint {
2897 2879 remote-endpoint = <&etm0_out>;
2898 }; 2880 };
2899 }; 2881 };
2900 2882
2901 port@1 { 2883 port@1 {
2902 reg = 2884 reg = <1>;
2903 apss_ 2885 apss_funnel0_in1: endpoint {
2904 2886 remote-endpoint = <&etm1_out>;
2905 }; 2887 };
2906 }; 2888 };
2907 }; 2889 };
2908 2890
2909 out-ports { 2891 out-ports {
2910 port { 2892 port {
2911 apss_ 2893 apss_funnel0_out: endpoint {
2912 2894 remote-endpoint =
2913 2895 <&apss_merge_funnel_in0>;
2914 }; 2896 };
2915 }; 2897 };
2916 }; 2898 };
2917 }; 2899 };
2918 2900
2919 debug@3a10000 { 2901 debug@3a10000 {
2920 compatible = "arm,cor 2902 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2921 reg = <0x3a10000 0x10 2903 reg = <0x3a10000 0x1000>;
2922 2904
2923 clocks = <&rpmcc RPM_ 2905 clocks = <&rpmcc RPM_QDSS_CLK>;
2924 clock-names = "apb_pc 2906 clock-names = "apb_pclk";
2925 2907
2926 cpu = <&CPU2>; 2908 cpu = <&CPU2>;
2927 }; 2909 };
2928 2910
2929 etm@3a40000 { 2911 etm@3a40000 {
2930 compatible = "arm,cor 2912 compatible = "arm,coresight-etm4x", "arm,primecell";
2931 reg = <0x3a40000 0x10 2913 reg = <0x3a40000 0x1000>;
2932 2914
2933 clocks = <&rpmcc RPM_ 2915 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2934 clock-names = "apb_pc 2916 clock-names = "apb_pclk", "atclk";
2935 2917
2936 cpu = <&CPU2>; 2918 cpu = <&CPU2>;
2937 2919
2938 out-ports { 2920 out-ports {
2939 port { 2921 port {
2940 etm2_ 2922 etm2_out: endpoint {
2941 2923 remote-endpoint =
2942 2924 <&apss_funnel1_in0>;
2943 }; 2925 };
2944 }; 2926 };
2945 }; 2927 };
2946 }; 2928 };
2947 2929
2948 debug@3b10000 { 2930 debug@3b10000 {
2949 compatible = "arm,cor 2931 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2950 reg = <0x3b10000 0x10 2932 reg = <0x3b10000 0x1000>;
2951 2933
2952 clocks = <&rpmcc RPM_ 2934 clocks = <&rpmcc RPM_QDSS_CLK>;
2953 clock-names = "apb_pc 2935 clock-names = "apb_pclk";
2954 2936
2955 cpu = <&CPU3>; 2937 cpu = <&CPU3>;
2956 }; 2938 };
2957 2939
2958 etm@3b40000 { 2940 etm@3b40000 {
2959 compatible = "arm,cor 2941 compatible = "arm,coresight-etm4x", "arm,primecell";
2960 reg = <0x3b40000 0x10 2942 reg = <0x3b40000 0x1000>;
2961 2943
2962 clocks = <&rpmcc RPM_ 2944 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2963 clock-names = "apb_pc 2945 clock-names = "apb_pclk", "atclk";
2964 2946
2965 cpu = <&CPU3>; 2947 cpu = <&CPU3>;
2966 2948
2967 out-ports { 2949 out-ports {
2968 port { 2950 port {
2969 etm3_ 2951 etm3_out: endpoint {
2970 2952 remote-endpoint =
2971 2953 <&apss_funnel1_in1>;
2972 }; 2954 };
2973 }; 2955 };
2974 }; 2956 };
2975 }; 2957 };
2976 2958
2977 funnel@3bb0000 { /* APSS Funn 2959 funnel@3bb0000 { /* APSS Funnel 1 */
2978 compatible = "arm,cor 2960 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2979 reg = <0x3bb0000 0x10 2961 reg = <0x3bb0000 0x1000>;
2980 2962
2981 clocks = <&rpmcc RPM_ 2963 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2982 clock-names = "apb_pc 2964 clock-names = "apb_pclk", "atclk";
2983 2965
2984 in-ports { 2966 in-ports {
2985 #address-cell 2967 #address-cells = <1>;
2986 #size-cells = 2968 #size-cells = <0>;
2987 2969
2988 port@0 { 2970 port@0 {
2989 reg = 2971 reg = <0>;
2990 apss_ 2972 apss_funnel1_in0: endpoint {
2991 2973 remote-endpoint = <&etm2_out>;
2992 }; 2974 };
2993 }; 2975 };
2994 2976
2995 port@1 { 2977 port@1 {
2996 reg = 2978 reg = <1>;
2997 apss_ 2979 apss_funnel1_in1: endpoint {
2998 2980 remote-endpoint = <&etm3_out>;
2999 }; 2981 };
3000 }; 2982 };
3001 }; 2983 };
3002 2984
3003 out-ports { 2985 out-ports {
3004 port { 2986 port {
3005 apss_ 2987 apss_funnel1_out: endpoint {
3006 2988 remote-endpoint =
3007 2989 <&apss_merge_funnel_in1>;
3008 }; 2990 };
3009 }; 2991 };
3010 }; 2992 };
3011 }; 2993 };
3012 2994
3013 funnel@3bc0000 { 2995 funnel@3bc0000 {
3014 compatible = "arm,cor 2996 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3015 reg = <0x3bc0000 0x10 2997 reg = <0x3bc0000 0x1000>;
3016 2998
3017 clocks = <&rpmcc RPM_ 2999 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
3018 clock-names = "apb_pc 3000 clock-names = "apb_pclk", "atclk";
3019 3001
3020 in-ports { 3002 in-ports {
3021 #address-cell 3003 #address-cells = <1>;
3022 #size-cells = 3004 #size-cells = <0>;
3023 3005
3024 port@0 { 3006 port@0 {
3025 reg = 3007 reg = <0>;
3026 apss_ 3008 apss_merge_funnel_in0: endpoint {
3027 3009 remote-endpoint =
3028 3010 <&apss_funnel0_out>;
3029 }; 3011 };
3030 }; 3012 };
3031 3013
3032 port@1 { 3014 port@1 {
3033 reg = 3015 reg = <1>;
3034 apss_ 3016 apss_merge_funnel_in1: endpoint {
3035 3017 remote-endpoint =
3036 3018 <&apss_funnel1_out>;
3037 }; 3019 };
3038 }; 3020 };
3039 }; 3021 };
3040 3022
3041 out-ports { 3023 out-ports {
3042 port { 3024 port {
3043 apss_ 3025 apss_merge_funnel_out: endpoint {
3044 3026 remote-endpoint =
3045 3027 <&funnel1_in>;
3046 }; 3028 };
3047 }; 3029 };
3048 }; 3030 };
3049 }; 3031 };
3050 3032
3051 kryocc: clock-controller@6400 3033 kryocc: clock-controller@6400000 {
3052 compatible = "qcom,ms 3034 compatible = "qcom,msm8996-apcc";
3053 reg = <0x06400000 0x9 3035 reg = <0x06400000 0x90000>;
3054 3036
3055 clock-names = "xo", " 3037 clock-names = "xo", "sys_apcs_aux";
3056 clocks = <&rpmcc RPM_ 3038 clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>, <&apcs_glb>;
3057 3039
3058 #clock-cells = <1>; 3040 #clock-cells = <1>;
3059 }; 3041 };
3060 3042
3061 usb3: usb@6af8800 { 3043 usb3: usb@6af8800 {
3062 compatible = "qcom,ms 3044 compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
3063 reg = <0x06af8800 0x4 3045 reg = <0x06af8800 0x400>;
3064 #address-cells = <1>; 3046 #address-cells = <1>;
3065 #size-cells = <1>; 3047 #size-cells = <1>;
3066 ranges; 3048 ranges;
3067 3049
3068 interrupts = <GIC_SPI 3050 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
3069 <GIC_SPI 3051 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
3070 interrupt-names = "hs 3052 interrupt-names = "hs_phy_irq", "ss_phy_irq";
3071 3053
3072 clocks = <&gcc GCC_SY 3054 clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
3073 <&gcc GCC_US 3055 <&gcc GCC_USB30_MASTER_CLK>,
3074 <&gcc GCC_AG 3056 <&gcc GCC_AGGRE2_USB3_AXI_CLK>,
3075 <&gcc GCC_US 3057 <&gcc GCC_USB30_SLEEP_CLK>,
3076 <&gcc GCC_US 3058 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
3077 clock-names = "cfg_no 3059 clock-names = "cfg_noc",
3078 "core", 3060 "core",
3079 "iface" 3061 "iface",
3080 "sleep" 3062 "sleep",
3081 "mock_u 3063 "mock_utmi";
3082 3064
3083 assigned-clocks = <&g 3065 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
3084 <&g 3066 <&gcc GCC_USB30_MASTER_CLK>;
3085 assigned-clock-rates 3067 assigned-clock-rates = <19200000>, <120000000>;
3086 3068
3087 interconnects = <&a2n 3069 interconnects = <&a2noc MASTER_USB3 &bimc SLAVE_EBI_CH0>,
3088 <&bim 3070 <&bimc MASTER_AMPSS_M0 &snoc SLAVE_USB3>;
3089 interconnect-names = 3071 interconnect-names = "usb-ddr", "apps-usb";
3090 3072
3091 power-domains = <&gcc 3073 power-domains = <&gcc USB30_GDSC>;
3092 status = "disabled"; 3074 status = "disabled";
3093 3075
3094 usb3_dwc3: usb@6a0000 3076 usb3_dwc3: usb@6a00000 {
3095 compatible = 3077 compatible = "snps,dwc3";
3096 reg = <0x06a0 3078 reg = <0x06a00000 0xcc00>;
3097 interrupts = 3079 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
3098 phys = <&hsus !! 3080 phys = <&hsusb_phy1>, <&ssusb_phy_0>;
3099 phy-names = " 3081 phy-names = "usb2-phy", "usb3-phy";
3100 snps,hird-thr 3082 snps,hird-threshold = /bits/ 8 <0>;
3101 snps,dis_u2_s 3083 snps,dis_u2_susphy_quirk;
3102 snps,dis_enbl 3084 snps,dis_enblslpm_quirk;
3103 snps,is-utmi- 3085 snps,is-utmi-l1-suspend;
3104 snps,parkmode <<
3105 tx-fifo-resiz 3086 tx-fifo-resize;
3106 }; 3087 };
3107 }; 3088 };
3108 3089
3109 usb3phy: phy@7410000 { 3090 usb3phy: phy@7410000 {
3110 compatible = "qcom,ms 3091 compatible = "qcom,msm8996-qmp-usb3-phy";
3111 reg = <0x07410000 0x1 !! 3092 reg = <0x07410000 0x1c4>;
>> 3093 #address-cells = <1>;
>> 3094 #size-cells = <1>;
>> 3095 ranges;
3112 3096
3113 clocks = <&gcc GCC_US 3097 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
3114 <&gcc GCC_US !! 3098 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3115 <&gcc GCC_US !! 3099 <&gcc GCC_USB3_CLKREF_CLK>;
3116 <&gcc GCC_US !! 3100 clock-names = "aux", "cfg_ahb", "ref";
3117 clock-names = "aux", <<
3118 "ref", <<
3119 "cfg_ah <<
3120 "pipe"; <<
3121 clock-output-names = <<
3122 #clock-cells = <0>; <<
3123 #phy-cells = <0>; <<
3124 3101
3125 resets = <&gcc GCC_US 3102 resets = <&gcc GCC_USB3_PHY_BCR>,
3126 <&gcc GCC_US !! 3103 <&gcc GCC_USB3PHY_PHY_BCR>;
3127 reset-names = "phy", !! 3104 reset-names = "phy", "common";
3128 "phy_ph <<
3129 <<
3130 status = "disabled"; 3105 status = "disabled";
>> 3106
>> 3107 ssusb_phy_0: phy@7410200 {
>> 3108 reg = <0x07410200 0x200>,
>> 3109 <0x07410400 0x130>,
>> 3110 <0x07410600 0x1a8>;
>> 3111 #phy-cells = <0>;
>> 3112
>> 3113 #clock-cells = <0>;
>> 3114 clock-output-names = "usb3_phy_pipe_clk_src";
>> 3115 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
>> 3116 clock-names = "pipe0";
>> 3117 };
3131 }; 3118 };
3132 3119
3133 hsusb_phy1: phy@7411000 { 3120 hsusb_phy1: phy@7411000 {
3134 compatible = "qcom,ms 3121 compatible = "qcom,msm8996-qusb2-phy";
3135 reg = <0x07411000 0x1 3122 reg = <0x07411000 0x180>;
3136 #phy-cells = <0>; 3123 #phy-cells = <0>;
3137 3124
3138 clocks = <&gcc GCC_US 3125 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3139 <&gcc GCC_RX1 3126 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
3140 clock-names = "cfg_ah 3127 clock-names = "cfg_ahb", "ref";
3141 3128
3142 resets = <&gcc GCC_QU 3129 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3143 nvmem-cells = <&qusb2 3130 nvmem-cells = <&qusb2p_hstx_trim>;
3144 status = "disabled"; 3131 status = "disabled";
3145 }; 3132 };
3146 3133
3147 hsusb_phy2: phy@7412000 { 3134 hsusb_phy2: phy@7412000 {
3148 compatible = "qcom,ms 3135 compatible = "qcom,msm8996-qusb2-phy";
3149 reg = <0x07412000 0x1 3136 reg = <0x07412000 0x180>;
3150 #phy-cells = <0>; 3137 #phy-cells = <0>;
3151 3138
3152 clocks = <&gcc GCC_US 3139 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3153 <&gcc GCC_RX2 3140 <&gcc GCC_RX2_USB2_CLKREF_CLK>;
3154 clock-names = "cfg_ah 3141 clock-names = "cfg_ahb", "ref";
3155 3142
3156 resets = <&gcc GCC_QU 3143 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3157 nvmem-cells = <&qusb2 3144 nvmem-cells = <&qusb2s_hstx_trim>;
3158 status = "disabled"; 3145 status = "disabled";
3159 }; 3146 };
3160 3147
3161 sdhc1: mmc@7464900 { 3148 sdhc1: mmc@7464900 {
3162 compatible = "qcom,ms 3149 compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4";
3163 reg = <0x07464900 0x1 3150 reg = <0x07464900 0x11c>, <0x07464000 0x800>;
3164 reg-names = "hc", "co 3151 reg-names = "hc", "core";
3165 3152
3166 interrupts = <GIC_SPI 3153 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
3167 <GIC_ 3154 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
3168 interrupt-names = "hc 3155 interrupt-names = "hc_irq", "pwr_irq";
3169 3156
3170 clock-names = "iface" 3157 clock-names = "iface", "core", "xo";
3171 clocks = <&gcc GCC_SD 3158 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
3172 <&gcc GCC_SDC 3159 <&gcc GCC_SDCC1_APPS_CLK>,
3173 <&rpmcc RPM_S 3160 <&rpmcc RPM_SMD_XO_CLK_SRC>;
3174 resets = <&gcc GCC_SD 3161 resets = <&gcc GCC_SDCC1_BCR>;
3175 3162
3176 pinctrl-names = "defa 3163 pinctrl-names = "default", "sleep";
3177 pinctrl-0 = <&sdc1_st 3164 pinctrl-0 = <&sdc1_state_on>;
3178 pinctrl-1 = <&sdc1_st 3165 pinctrl-1 = <&sdc1_state_off>;
3179 3166
3180 bus-width = <8>; 3167 bus-width = <8>;
3181 non-removable; 3168 non-removable;
3182 status = "disabled"; 3169 status = "disabled";
3183 }; 3170 };
3184 3171
3185 sdhc2: mmc@74a4900 { 3172 sdhc2: mmc@74a4900 {
3186 compatible = "qcom,ms 3173 compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4";
3187 reg = <0x074a4900 0x3 3174 reg = <0x074a4900 0x314>, <0x074a4000 0x800>;
3188 reg-names = "hc", "co 3175 reg-names = "hc", "core";
3189 3176
3190 interrupts = <GIC_SPI 3177 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
3191 <GIC_SP 3178 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
3192 interrupt-names = "hc 3179 interrupt-names = "hc_irq", "pwr_irq";
3193 3180
3194 clock-names = "iface" 3181 clock-names = "iface", "core", "xo";
3195 clocks = <&gcc GCC_SD 3182 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3196 <&gcc GCC_SDC 3183 <&gcc GCC_SDCC2_APPS_CLK>,
3197 <&rpmcc RPM_S 3184 <&rpmcc RPM_SMD_XO_CLK_SRC>;
3198 resets = <&gcc GCC_SD 3185 resets = <&gcc GCC_SDCC2_BCR>;
3199 3186
3200 pinctrl-names = "defa 3187 pinctrl-names = "default", "sleep";
3201 pinctrl-0 = <&sdc2_st 3188 pinctrl-0 = <&sdc2_state_on>;
3202 pinctrl-1 = <&sdc2_st 3189 pinctrl-1 = <&sdc2_state_off>;
3203 3190
3204 bus-width = <4>; 3191 bus-width = <4>;
3205 status = "disabled"; 3192 status = "disabled";
3206 }; 3193 };
3207 3194
3208 blsp1_dma: dma-controller@754 3195 blsp1_dma: dma-controller@7544000 {
3209 compatible = "qcom,ba 3196 compatible = "qcom,bam-v1.7.0";
3210 reg = <0x07544000 0x2 3197 reg = <0x07544000 0x2b000>;
3211 interrupts = <GIC_SPI 3198 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
3212 clocks = <&gcc GCC_BL 3199 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
3213 clock-names = "bam_cl 3200 clock-names = "bam_clk";
3214 qcom,controlled-remot 3201 qcom,controlled-remotely;
3215 #dma-cells = <1>; 3202 #dma-cells = <1>;
3216 qcom,ee = <0>; 3203 qcom,ee = <0>;
3217 }; 3204 };
3218 3205
3219 blsp1_uart2: serial@7570000 { 3206 blsp1_uart2: serial@7570000 {
3220 compatible = "qcom,ms 3207 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
3221 reg = <0x07570000 0x1 3208 reg = <0x07570000 0x1000>;
3222 interrupts = <GIC_SPI 3209 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
3223 clocks = <&gcc GCC_BL 3210 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
3224 <&gcc GCC_BL 3211 <&gcc GCC_BLSP1_AHB_CLK>;
3225 clock-names = "core", 3212 clock-names = "core", "iface";
3226 pinctrl-names = "defa 3213 pinctrl-names = "default", "sleep";
3227 pinctrl-0 = <&blsp1_u 3214 pinctrl-0 = <&blsp1_uart2_default>;
3228 pinctrl-1 = <&blsp1_u 3215 pinctrl-1 = <&blsp1_uart2_sleep>;
3229 dmas = <&blsp1_dma 2> 3216 dmas = <&blsp1_dma 2>, <&blsp1_dma 3>;
3230 dma-names = "tx", "rx 3217 dma-names = "tx", "rx";
3231 status = "disabled"; 3218 status = "disabled";
3232 }; 3219 };
3233 3220
3234 blsp1_spi1: spi@7575000 { 3221 blsp1_spi1: spi@7575000 {
3235 compatible = "qcom,sp 3222 compatible = "qcom,spi-qup-v2.2.1";
3236 reg = <0x07575000 0x6 3223 reg = <0x07575000 0x600>;
3237 interrupts = <GIC_SPI 3224 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
3238 clocks = <&gcc GCC_BL 3225 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
3239 <&gcc GCC_BL 3226 <&gcc GCC_BLSP1_AHB_CLK>;
3240 clock-names = "core", 3227 clock-names = "core", "iface";
3241 pinctrl-names = "defa 3228 pinctrl-names = "default", "sleep";
3242 pinctrl-0 = <&blsp1_s 3229 pinctrl-0 = <&blsp1_spi1_default>;
3243 pinctrl-1 = <&blsp1_s 3230 pinctrl-1 = <&blsp1_spi1_sleep>;
3244 dmas = <&blsp1_dma 12 3231 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
3245 dma-names = "tx", "rx 3232 dma-names = "tx", "rx";
3246 #address-cells = <1>; 3233 #address-cells = <1>;
3247 #size-cells = <0>; 3234 #size-cells = <0>;
3248 status = "disabled"; 3235 status = "disabled";
3249 }; 3236 };
3250 3237
3251 blsp1_i2c3: i2c@7577000 { 3238 blsp1_i2c3: i2c@7577000 {
3252 compatible = "qcom,i2 3239 compatible = "qcom,i2c-qup-v2.2.1";
3253 reg = <0x07577000 0x1 3240 reg = <0x07577000 0x1000>;
3254 interrupts = <GIC_SPI 3241 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
3255 clocks = <&gcc GCC_BL 3242 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
3256 <&gcc GCC_BL 3243 <&gcc GCC_BLSP1_AHB_CLK>;
3257 clock-names = "core", 3244 clock-names = "core", "iface";
3258 pinctrl-names = "defa 3245 pinctrl-names = "default", "sleep";
3259 pinctrl-0 = <&blsp1_i 3246 pinctrl-0 = <&blsp1_i2c3_default>;
3260 pinctrl-1 = <&blsp1_i 3247 pinctrl-1 = <&blsp1_i2c3_sleep>;
3261 dmas = <&blsp1_dma 16 3248 dmas = <&blsp1_dma 16>, <&blsp1_dma 17>;
3262 dma-names = "tx", "rx 3249 dma-names = "tx", "rx";
3263 #address-cells = <1>; 3250 #address-cells = <1>;
3264 #size-cells = <0>; 3251 #size-cells = <0>;
3265 status = "disabled"; 3252 status = "disabled";
3266 }; 3253 };
3267 3254
3268 blsp1_i2c6: i2c@757a000 { 3255 blsp1_i2c6: i2c@757a000 {
3269 compatible = "qcom,i2 3256 compatible = "qcom,i2c-qup-v2.2.1";
3270 reg = <0x757a000 0x10 3257 reg = <0x757a000 0x1000>;
3271 interrupts = <GIC_SPI 3258 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
3272 clocks = <&gcc GCC_BL 3259 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
3273 <&gcc GCC_BL 3260 <&gcc GCC_BLSP1_AHB_CLK>;
3274 clock-names = "core", 3261 clock-names = "core", "iface";
3275 pinctrl-names = "defa 3262 pinctrl-names = "default", "sleep";
3276 pinctrl-0 = <&blsp1_i 3263 pinctrl-0 = <&blsp1_i2c6_default>;
3277 pinctrl-1 = <&blsp1_i 3264 pinctrl-1 = <&blsp1_i2c6_sleep>;
3278 dmas = <&blsp1_dma 22 3265 dmas = <&blsp1_dma 22>, <&blsp1_dma 23>;
3279 dma-names = "tx", "rx 3266 dma-names = "tx", "rx";
3280 #address-cells = <1>; 3267 #address-cells = <1>;
3281 #size-cells = <0>; 3268 #size-cells = <0>;
3282 status = "disabled"; 3269 status = "disabled";
3283 }; 3270 };
3284 3271
3285 blsp2_dma: dma-controller@758 3272 blsp2_dma: dma-controller@7584000 {
3286 compatible = "qcom,ba 3273 compatible = "qcom,bam-v1.7.0";
3287 reg = <0x07584000 0x2 3274 reg = <0x07584000 0x2b000>;
3288 interrupts = <GIC_SPI 3275 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
3289 clocks = <&gcc GCC_BL 3276 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
3290 clock-names = "bam_cl 3277 clock-names = "bam_clk";
3291 qcom,controlled-remot 3278 qcom,controlled-remotely;
3292 #dma-cells = <1>; 3279 #dma-cells = <1>;
3293 qcom,ee = <0>; 3280 qcom,ee = <0>;
3294 }; 3281 };
3295 3282
3296 blsp2_uart2: serial@75b0000 { 3283 blsp2_uart2: serial@75b0000 {
3297 compatible = "qcom,ms 3284 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
3298 reg = <0x075b0000 0x1 3285 reg = <0x075b0000 0x1000>;
3299 interrupts = <GIC_SPI 3286 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
3300 clocks = <&gcc GCC_BL 3287 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
3301 <&gcc GCC_BL 3288 <&gcc GCC_BLSP2_AHB_CLK>;
3302 clock-names = "core", 3289 clock-names = "core", "iface";
3303 status = "disabled"; 3290 status = "disabled";
3304 }; 3291 };
3305 3292
3306 blsp2_uart3: serial@75b1000 { 3293 blsp2_uart3: serial@75b1000 {
3307 compatible = "qcom,ms 3294 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
3308 reg = <0x075b1000 0x1 3295 reg = <0x075b1000 0x1000>;
3309 interrupts = <GIC_SPI 3296 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
3310 clocks = <&gcc GCC_BL 3297 clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>,
3311 <&gcc GCC_BL 3298 <&gcc GCC_BLSP2_AHB_CLK>;
3312 clock-names = "core", 3299 clock-names = "core", "iface";
3313 status = "disabled"; 3300 status = "disabled";
3314 }; 3301 };
3315 3302
3316 blsp2_i2c1: i2c@75b5000 { 3303 blsp2_i2c1: i2c@75b5000 {
3317 compatible = "qcom,i2 3304 compatible = "qcom,i2c-qup-v2.2.1";
3318 reg = <0x075b5000 0x1 3305 reg = <0x075b5000 0x1000>;
3319 interrupts = <GIC_SPI 3306 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
3320 clocks = <&gcc GCC_BL 3307 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
3321 <&gcc GCC_BL 3308 <&gcc GCC_BLSP2_AHB_CLK>;
3322 clock-names = "core", 3309 clock-names = "core", "iface";
3323 pinctrl-names = "defa 3310 pinctrl-names = "default", "sleep";
3324 pinctrl-0 = <&blsp2_i 3311 pinctrl-0 = <&blsp2_i2c1_default>;
3325 pinctrl-1 = <&blsp2_i 3312 pinctrl-1 = <&blsp2_i2c1_sleep>;
3326 dmas = <&blsp2_dma 12 3313 dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
3327 dma-names = "tx", "rx 3314 dma-names = "tx", "rx";
3328 #address-cells = <1>; 3315 #address-cells = <1>;
3329 #size-cells = <0>; 3316 #size-cells = <0>;
3330 status = "disabled"; 3317 status = "disabled";
3331 }; 3318 };
3332 3319
3333 blsp2_i2c2: i2c@75b6000 { 3320 blsp2_i2c2: i2c@75b6000 {
3334 compatible = "qcom,i2 3321 compatible = "qcom,i2c-qup-v2.2.1";
3335 reg = <0x075b6000 0x1 3322 reg = <0x075b6000 0x1000>;
3336 interrupts = <GIC_SPI 3323 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
3337 clocks = <&gcc GCC_BL 3324 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
3338 <&gcc GCC_BL 3325 <&gcc GCC_BLSP2_AHB_CLK>;
3339 clock-names = "core", 3326 clock-names = "core", "iface";
3340 pinctrl-names = "defa 3327 pinctrl-names = "default", "sleep";
3341 pinctrl-0 = <&blsp2_i 3328 pinctrl-0 = <&blsp2_i2c2_default>;
3342 pinctrl-1 = <&blsp2_i 3329 pinctrl-1 = <&blsp2_i2c2_sleep>;
3343 dmas = <&blsp2_dma 14 3330 dmas = <&blsp2_dma 14>, <&blsp2_dma 15>;
3344 dma-names = "tx", "rx 3331 dma-names = "tx", "rx";
3345 #address-cells = <1>; 3332 #address-cells = <1>;
3346 #size-cells = <0>; 3333 #size-cells = <0>;
3347 status = "disabled"; 3334 status = "disabled";
3348 }; 3335 };
3349 3336
3350 blsp2_i2c3: i2c@75b7000 { 3337 blsp2_i2c3: i2c@75b7000 {
3351 compatible = "qcom,i2 3338 compatible = "qcom,i2c-qup-v2.2.1";
3352 reg = <0x075b7000 0x1 3339 reg = <0x075b7000 0x1000>;
3353 interrupts = <GIC_SPI 3340 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
3354 clocks = <&gcc GCC_BL 3341 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
3355 <&gcc GCC_BL 3342 <&gcc GCC_BLSP2_AHB_CLK>;
3356 clock-names = "core", 3343 clock-names = "core", "iface";
3357 clock-frequency = <40 3344 clock-frequency = <400000>;
3358 pinctrl-names = "defa 3345 pinctrl-names = "default", "sleep";
3359 pinctrl-0 = <&blsp2_i 3346 pinctrl-0 = <&blsp2_i2c3_default>;
3360 pinctrl-1 = <&blsp2_i 3347 pinctrl-1 = <&blsp2_i2c3_sleep>;
3361 dmas = <&blsp2_dma 16 3348 dmas = <&blsp2_dma 16>, <&blsp2_dma 17>;
3362 dma-names = "tx", "rx 3349 dma-names = "tx", "rx";
3363 #address-cells = <1>; 3350 #address-cells = <1>;
3364 #size-cells = <0>; 3351 #size-cells = <0>;
3365 status = "disabled"; 3352 status = "disabled";
3366 }; 3353 };
3367 3354
3368 blsp2_i2c5: i2c@75b9000 { 3355 blsp2_i2c5: i2c@75b9000 {
3369 compatible = "qcom,i2 3356 compatible = "qcom,i2c-qup-v2.2.1";
3370 reg = <0x75b9000 0x10 3357 reg = <0x75b9000 0x1000>;
3371 interrupts = <GIC_SPI 3358 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
3372 clocks = <&gcc GCC_BL 3359 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,
3373 <&gcc GCC_BL 3360 <&gcc GCC_BLSP2_AHB_CLK>;
3374 clock-names = "core", 3361 clock-names = "core", "iface";
3375 pinctrl-names = "defa 3362 pinctrl-names = "default";
3376 pinctrl-0 = <&blsp2_i 3363 pinctrl-0 = <&blsp2_i2c5_default>;
3377 dmas = <&blsp2_dma 20 3364 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
3378 dma-names = "tx", "rx 3365 dma-names = "tx", "rx";
3379 #address-cells = <1>; 3366 #address-cells = <1>;
3380 #size-cells = <0>; 3367 #size-cells = <0>;
3381 status = "disabled"; 3368 status = "disabled";
3382 }; 3369 };
3383 3370
3384 blsp2_i2c6: i2c@75ba000 { 3371 blsp2_i2c6: i2c@75ba000 {
3385 compatible = "qcom,i2 3372 compatible = "qcom,i2c-qup-v2.2.1";
3386 reg = <0x75ba000 0x10 3373 reg = <0x75ba000 0x1000>;
3387 interrupts = <GIC_SPI 3374 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
3388 clocks = <&gcc GCC_BL 3375 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>,
3389 <&gcc GCC_BL 3376 <&gcc GCC_BLSP2_AHB_CLK>;
3390 clock-names = "core", 3377 clock-names = "core", "iface";
3391 pinctrl-names = "defa 3378 pinctrl-names = "default", "sleep";
3392 pinctrl-0 = <&blsp2_i 3379 pinctrl-0 = <&blsp2_i2c6_default>;
3393 pinctrl-1 = <&blsp2_i 3380 pinctrl-1 = <&blsp2_i2c6_sleep>;
3394 dmas = <&blsp2_dma 22 3381 dmas = <&blsp2_dma 22>, <&blsp2_dma 23>;
3395 dma-names = "tx", "rx 3382 dma-names = "tx", "rx";
3396 #address-cells = <1>; 3383 #address-cells = <1>;
3397 #size-cells = <0>; 3384 #size-cells = <0>;
3398 status = "disabled"; 3385 status = "disabled";
3399 }; 3386 };
3400 3387
3401 blsp2_spi6: spi@75ba000 { 3388 blsp2_spi6: spi@75ba000 {
3402 compatible = "qcom,sp 3389 compatible = "qcom,spi-qup-v2.2.1";
3403 reg = <0x075ba000 0x6 3390 reg = <0x075ba000 0x600>;
3404 interrupts = <GIC_SPI 3391 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
3405 clocks = <&gcc GCC_BL 3392 clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>,
3406 <&gcc GCC_BL 3393 <&gcc GCC_BLSP2_AHB_CLK>;
3407 clock-names = "core", 3394 clock-names = "core", "iface";
3408 pinctrl-names = "defa 3395 pinctrl-names = "default", "sleep";
3409 pinctrl-0 = <&blsp2_s 3396 pinctrl-0 = <&blsp2_spi6_default>;
3410 pinctrl-1 = <&blsp2_s 3397 pinctrl-1 = <&blsp2_spi6_sleep>;
3411 dmas = <&blsp2_dma 22 3398 dmas = <&blsp2_dma 22>, <&blsp2_dma 23>;
3412 dma-names = "tx", "rx 3399 dma-names = "tx", "rx";
3413 #address-cells = <1>; 3400 #address-cells = <1>;
3414 #size-cells = <0>; 3401 #size-cells = <0>;
3415 status = "disabled"; 3402 status = "disabled";
3416 }; 3403 };
3417 3404
3418 usb2: usb@76f8800 { 3405 usb2: usb@76f8800 {
3419 compatible = "qcom,ms 3406 compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
3420 reg = <0x076f8800 0x4 3407 reg = <0x076f8800 0x400>;
3421 #address-cells = <1>; 3408 #address-cells = <1>;
3422 #size-cells = <1>; 3409 #size-cells = <1>;
3423 ranges; 3410 ranges;
3424 3411
3425 interrupts = <GIC_SPI !! 3412 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
3426 <GIC_SPI !! 3413 interrupt-names = "hs_phy_irq";
3427 <GIC_SPI <<
3428 interrupt-names = "pw <<
3429 "qu <<
3430 "hs <<
3431 3414
3432 clocks = <&gcc GCC_PE 3415 clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>,
3433 <&gcc GCC_USB 3416 <&gcc GCC_USB20_MASTER_CLK>,
3434 <&gcc GCC_USB 3417 <&gcc GCC_USB20_MOCK_UTMI_CLK>,
3435 <&gcc GCC_USB 3418 <&gcc GCC_USB20_SLEEP_CLK>,
3436 <&gcc GCC_USB 3419 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
3437 clock-names = "cfg_no 3420 clock-names = "cfg_noc",
3438 "core", 3421 "core",
3439 "iface" 3422 "iface",
3440 "sleep" 3423 "sleep",
3441 "mock_u 3424 "mock_utmi";
3442 3425
3443 assigned-clocks = <&g 3426 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
3444 <&g 3427 <&gcc GCC_USB20_MASTER_CLK>;
3445 assigned-clock-rates 3428 assigned-clock-rates = <19200000>, <60000000>;
3446 3429
3447 power-domains = <&gcc 3430 power-domains = <&gcc USB30_GDSC>;
3448 qcom,select-utmi-as-p 3431 qcom,select-utmi-as-pipe-clk;
3449 status = "disabled"; 3432 status = "disabled";
3450 3433
3451 usb2_dwc3: usb@760000 3434 usb2_dwc3: usb@7600000 {
3452 compatible = 3435 compatible = "snps,dwc3";
3453 reg = <0x0760 3436 reg = <0x07600000 0xcc00>;
3454 interrupts = 3437 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
3455 phys = <&hsus 3438 phys = <&hsusb_phy2>;
3456 phy-names = " 3439 phy-names = "usb2-phy";
3457 maximum-speed 3440 maximum-speed = "high-speed";
3458 snps,dis_u2_s 3441 snps,dis_u2_susphy_quirk;
3459 snps,dis_enbl 3442 snps,dis_enblslpm_quirk;
3460 }; 3443 };
3461 }; 3444 };
3462 3445
3463 slimbam: dma-controller@91840 3446 slimbam: dma-controller@9184000 {
3464 compatible = "qcom,ba 3447 compatible = "qcom,bam-v1.7.0";
3465 qcom,controlled-remot 3448 qcom,controlled-remotely;
3466 reg = <0x09184000 0x3 3449 reg = <0x09184000 0x32000>;
3467 num-channels = <31>; 3450 num-channels = <31>;
3468 interrupts = <GIC_SPI 3451 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
3469 #dma-cells = <1>; 3452 #dma-cells = <1>;
3470 qcom,ee = <1>; 3453 qcom,ee = <1>;
3471 qcom,num-ees = <2>; 3454 qcom,num-ees = <2>;
3472 }; 3455 };
3473 3456
3474 slim_msm: slim-ngd@91c0000 { 3457 slim_msm: slim-ngd@91c0000 {
3475 compatible = "qcom,sl 3458 compatible = "qcom,slim-ngd-v1.5.0";
3476 reg = <0x091c0000 0x2 3459 reg = <0x091c0000 0x2c000>;
3477 interrupts = <GIC_SPI 3460 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
3478 dmas = <&slimbam 3>, 3461 dmas = <&slimbam 3>, <&slimbam 4>;
3479 dma-names = "rx", "tx 3462 dma-names = "rx", "tx";
3480 #address-cells = <1>; 3463 #address-cells = <1>;
3481 #size-cells = <0>; 3464 #size-cells = <0>;
3482 3465
3483 status = "disabled"; 3466 status = "disabled";
3484 }; 3467 };
3485 3468
3486 adsp_pil: remoteproc@9300000 3469 adsp_pil: remoteproc@9300000 {
3487 compatible = "qcom,ms 3470 compatible = "qcom,msm8996-adsp-pil";
3488 reg = <0x09300000 0x8 3471 reg = <0x09300000 0x80000>;
3489 3472
3490 interrupts-extended = 3473 interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
3491 3474 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3492 3475 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3493 3476 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3494 3477 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
3495 interrupt-names = "wd 3478 interrupt-names = "wdog", "fatal", "ready",
3496 "ha 3479 "handover", "stop-ack";
3497 3480
3498 clocks = <&rpmcc RPM_ 3481 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
3499 clock-names = "xo"; 3482 clock-names = "xo";
3500 3483
3501 memory-region = <&ads 3484 memory-region = <&adsp_mem>;
3502 3485
3503 qcom,smem-states = <& 3486 qcom,smem-states = <&adsp_smp2p_out 0>;
3504 qcom,smem-state-names 3487 qcom,smem-state-names = "stop";
3505 3488
3506 power-domains = <&rpm 3489 power-domains = <&rpmpd MSM8996_VDDCX>;
3507 power-domain-names = 3490 power-domain-names = "cx";
3508 3491
3509 status = "disabled"; 3492 status = "disabled";
3510 3493
3511 glink-edge { <<
3512 interrupts = <<
3513 label = "lpas <<
3514 qcom,remote-p <<
3515 mboxes = <&ap <<
3516 }; <<
3517 <<
3518 <<
3519 smd-edge { 3494 smd-edge {
3520 interrupts = 3495 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
3521 3496
3522 label = "lpas 3497 label = "lpass";
3523 mboxes = <&ap 3498 mboxes = <&apcs_glb 8>;
3524 qcom,smd-edge 3499 qcom,smd-edge = <1>;
3525 qcom,remote-p 3500 qcom,remote-pid = <2>;
3526 3501
3527 apr { 3502 apr {
3528 power 3503 power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>;
3529 compa 3504 compatible = "qcom,apr-v2";
3530 qcom, 3505 qcom,smd-channels = "apr_audio_svc";
3531 qcom, 3506 qcom,domain = <APR_DOMAIN_ADSP>;
3532 #addr 3507 #address-cells = <1>;
3533 #size 3508 #size-cells = <0>;
3534 3509
3535 servi 3510 service@3 {
3536 3511 reg = <APR_SVC_ADSP_CORE>;
3537 3512 compatible = "qcom,q6core";
3538 }; 3513 };
3539 3514
3540 q6afe 3515 q6afe: service@4 {
3541 3516 compatible = "qcom,q6afe";
3542 3517 reg = <APR_SVC_AFE>;
3543 3518 q6afedai: dais {
3544 3519 compatible = "qcom,q6afe-dais";
3545 3520 #address-cells = <1>;
3546 3521 #size-cells = <0>;
3547 3522 #sound-dai-cells = <1>;
3548 3523 dai@1 {
3549 3524 reg = <1>;
3550 3525 };
3551 3526 };
3552 }; 3527 };
3553 3528
3554 q6asm 3529 q6asm: service@7 {
3555 3530 compatible = "qcom,q6asm";
3556 3531 reg = <APR_SVC_ASM>;
3557 3532 q6asmdai: dais {
3558 3533 compatible = "qcom,q6asm-dais";
3559 3534 #address-cells = <1>;
3560 3535 #size-cells = <0>;
3561 3536 #sound-dai-cells = <1>;
3562 3537 iommus = <&lpass_q6_smmu 1>;
3563 3538 };
3564 }; 3539 };
3565 3540
3566 q6adm 3541 q6adm: service@8 {
3567 3542 compatible = "qcom,q6adm";
3568 3543 reg = <APR_SVC_ADM>;
3569 3544 q6routing: routing {
3570 3545 compatible = "qcom,q6adm-routing";
3571 3546 #sound-dai-cells = <0>;
3572 3547 };
3573 }; 3548 };
3574 }; 3549 };
3575 <<
3576 fastrpc { <<
3577 compa <<
3578 qcom, <<
3579 label <<
3580 qcom, <<
3581 #addr <<
3582 #size <<
3583 <<
3584 cb@5 <<
3585 <<
3586 <<
3587 <<
3588 }; <<
3589 <<
3590 cb@6 <<
3591 <<
3592 <<
3593 <<
3594 }; <<
3595 <<
3596 cb@7 <<
3597 <<
3598 <<
3599 <<
3600 }; <<
3601 <<
3602 cb@8 <<
3603 <<
3604 <<
3605 <<
3606 }; <<
3607 <<
3608 cb@9 <<
3609 <<
3610 <<
3611 <<
3612 }; <<
3613 <<
3614 cb@10 <<
3615 <<
3616 <<
3617 <<
3618 }; <<
3619 <<
3620 cb@11 <<
3621 <<
3622 <<
3623 <<
3624 }; <<
3625 <<
3626 cb@12 <<
3627 <<
3628 <<
3629 <<
3630 }; <<
3631 }; <<
3632 }; 3550 };
3633 }; 3551 };
3634 3552
3635 apcs_glb: mailbox@9820000 { 3553 apcs_glb: mailbox@9820000 {
3636 compatible = "qcom,ms 3554 compatible = "qcom,msm8996-apcs-hmss-global";
3637 reg = <0x09820000 0x1 3555 reg = <0x09820000 0x1000>;
3638 3556
3639 #mbox-cells = <1>; 3557 #mbox-cells = <1>;
3640 #clock-cells = <0>; 3558 #clock-cells = <0>;
3641 }; 3559 };
3642 3560
3643 timer@9840000 { 3561 timer@9840000 {
3644 #address-cells = <1>; 3562 #address-cells = <1>;
3645 #size-cells = <1>; 3563 #size-cells = <1>;
3646 ranges; 3564 ranges;
3647 compatible = "arm,arm 3565 compatible = "arm,armv7-timer-mem";
3648 reg = <0x09840000 0x1 3566 reg = <0x09840000 0x1000>;
3649 clock-frequency = <19 3567 clock-frequency = <19200000>;
3650 3568
3651 frame@9850000 { 3569 frame@9850000 {
3652 frame-number 3570 frame-number = <0>;
3653 interrupts = 3571 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
3654 3572 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
3655 reg = <0x0985 3573 reg = <0x09850000 0x1000>,
3656 <0x0986 3574 <0x09860000 0x1000>;
3657 }; 3575 };
3658 3576
3659 frame@9870000 { 3577 frame@9870000 {
3660 frame-number 3578 frame-number = <1>;
3661 interrupts = 3579 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
3662 reg = <0x0987 3580 reg = <0x09870000 0x1000>;
3663 status = "dis 3581 status = "disabled";
3664 }; 3582 };
3665 3583
3666 frame@9880000 { 3584 frame@9880000 {
3667 frame-number 3585 frame-number = <2>;
3668 interrupts = 3586 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
3669 reg = <0x0988 3587 reg = <0x09880000 0x1000>;
3670 status = "dis 3588 status = "disabled";
3671 }; 3589 };
3672 3590
3673 frame@9890000 { 3591 frame@9890000 {
3674 frame-number 3592 frame-number = <3>;
3675 interrupts = 3593 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
3676 reg = <0x0989 3594 reg = <0x09890000 0x1000>;
3677 status = "dis 3595 status = "disabled";
3678 }; 3596 };
3679 3597
3680 frame@98a0000 { 3598 frame@98a0000 {
3681 frame-number 3599 frame-number = <4>;
3682 interrupts = 3600 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
3683 reg = <0x098a 3601 reg = <0x098a0000 0x1000>;
3684 status = "dis 3602 status = "disabled";
3685 }; 3603 };
3686 3604
3687 frame@98b0000 { 3605 frame@98b0000 {
3688 frame-number 3606 frame-number = <5>;
3689 interrupts = 3607 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
3690 reg = <0x098b 3608 reg = <0x098b0000 0x1000>;
3691 status = "dis 3609 status = "disabled";
3692 }; 3610 };
3693 3611
3694 frame@98c0000 { 3612 frame@98c0000 {
3695 frame-number 3613 frame-number = <6>;
3696 interrupts = 3614 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
3697 reg = <0x098c 3615 reg = <0x098c0000 0x1000>;
3698 status = "dis 3616 status = "disabled";
3699 }; 3617 };
3700 }; 3618 };
3701 3619
3702 saw3: syscon@9a10000 { 3620 saw3: syscon@9a10000 {
3703 compatible = "syscon" 3621 compatible = "syscon";
3704 reg = <0x09a10000 0x1 3622 reg = <0x09a10000 0x1000>;
3705 }; 3623 };
3706 3624
3707 cbf: clock-controller@9a11000 3625 cbf: clock-controller@9a11000 {
3708 compatible = "qcom,ms 3626 compatible = "qcom,msm8996-cbf";
3709 reg = <0x09a11000 0x1 3627 reg = <0x09a11000 0x10000>;
3710 clocks = <&rpmcc RPM_ 3628 clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>, <&apcs_glb>;
3711 #clock-cells = <0>; 3629 #clock-cells = <0>;
3712 #interconnect-cells = 3630 #interconnect-cells = <1>;
3713 }; 3631 };
3714 3632
3715 intc: interrupt-controller@9b 3633 intc: interrupt-controller@9bc0000 {
3716 compatible = "qcom,ms 3634 compatible = "qcom,msm8996-gic-v3", "arm,gic-v3";
3717 #interrupt-cells = <3 3635 #interrupt-cells = <3>;
3718 interrupt-controller; 3636 interrupt-controller;
3719 #redistributor-region 3637 #redistributor-regions = <1>;
3720 redistributor-stride 3638 redistributor-stride = <0x0 0x40000>;
3721 reg = <0x09bc0000 0x1 3639 reg = <0x09bc0000 0x10000>,
3722 <0x09c00000 0x1 3640 <0x09c00000 0x100000>;
3723 interrupts = <GIC_PPI 3641 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3724 }; 3642 };
3725 }; 3643 };
3726 3644
3727 sound: sound { 3645 sound: sound {
3728 }; 3646 };
3729 3647
3730 thermal-zones { 3648 thermal-zones {
3731 cpu0-thermal { 3649 cpu0-thermal {
3732 polling-delay-passive 3650 polling-delay-passive = <250>;
>> 3651 polling-delay = <1000>;
3733 3652
3734 thermal-sensors = <&t 3653 thermal-sensors = <&tsens0 3>;
3735 3654
3736 trips { 3655 trips {
3737 cpu0_alert0: 3656 cpu0_alert0: trip-point0 {
3738 tempe 3657 temperature = <75000>;
3739 hyste 3658 hysteresis = <2000>;
3740 type 3659 type = "passive";
3741 }; 3660 };
3742 3661
3743 cpu0_crit: cp 3662 cpu0_crit: cpu-crit {
3744 tempe 3663 temperature = <110000>;
3745 hyste 3664 hysteresis = <2000>;
3746 type 3665 type = "critical";
3747 }; 3666 };
3748 }; 3667 };
3749 }; 3668 };
3750 3669
3751 cpu1-thermal { 3670 cpu1-thermal {
3752 polling-delay-passive 3671 polling-delay-passive = <250>;
>> 3672 polling-delay = <1000>;
3753 3673
3754 thermal-sensors = <&t 3674 thermal-sensors = <&tsens0 5>;
3755 3675
3756 trips { 3676 trips {
3757 cpu1_alert0: 3677 cpu1_alert0: trip-point0 {
3758 tempe 3678 temperature = <75000>;
3759 hyste 3679 hysteresis = <2000>;
3760 type 3680 type = "passive";
3761 }; 3681 };
3762 3682
3763 cpu1_crit: cp 3683 cpu1_crit: cpu-crit {
3764 tempe 3684 temperature = <110000>;
3765 hyste 3685 hysteresis = <2000>;
3766 type 3686 type = "critical";
3767 }; 3687 };
3768 }; 3688 };
3769 }; 3689 };
3770 3690
3771 cpu2-thermal { 3691 cpu2-thermal {
3772 polling-delay-passive 3692 polling-delay-passive = <250>;
>> 3693 polling-delay = <1000>;
3773 3694
3774 thermal-sensors = <&t 3695 thermal-sensors = <&tsens0 8>;
3775 3696
3776 trips { 3697 trips {
3777 cpu2_alert0: 3698 cpu2_alert0: trip-point0 {
3778 tempe 3699 temperature = <75000>;
3779 hyste 3700 hysteresis = <2000>;
3780 type 3701 type = "passive";
3781 }; 3702 };
3782 3703
3783 cpu2_crit: cp 3704 cpu2_crit: cpu-crit {
3784 tempe 3705 temperature = <110000>;
3785 hyste 3706 hysteresis = <2000>;
3786 type 3707 type = "critical";
3787 }; 3708 };
3788 }; 3709 };
3789 }; 3710 };
3790 3711
3791 cpu3-thermal { 3712 cpu3-thermal {
3792 polling-delay-passive 3713 polling-delay-passive = <250>;
>> 3714 polling-delay = <1000>;
3793 3715
3794 thermal-sensors = <&t 3716 thermal-sensors = <&tsens0 10>;
3795 3717
3796 trips { 3718 trips {
3797 cpu3_alert0: 3719 cpu3_alert0: trip-point0 {
3798 tempe 3720 temperature = <75000>;
3799 hyste 3721 hysteresis = <2000>;
3800 type 3722 type = "passive";
3801 }; 3723 };
3802 3724
3803 cpu3_crit: cp 3725 cpu3_crit: cpu-crit {
3804 tempe 3726 temperature = <110000>;
3805 hyste 3727 hysteresis = <2000>;
3806 type 3728 type = "critical";
3807 }; 3729 };
3808 }; 3730 };
3809 }; 3731 };
3810 3732
3811 gpu-top-thermal { 3733 gpu-top-thermal {
3812 polling-delay-passive 3734 polling-delay-passive = <250>;
>> 3735 polling-delay = <1000>;
3813 3736
3814 thermal-sensors = <&t 3737 thermal-sensors = <&tsens1 6>;
3815 3738
3816 trips { 3739 trips {
3817 gpu1_alert0: 3740 gpu1_alert0: trip-point0 {
3818 tempe 3741 temperature = <90000>;
3819 hyste 3742 hysteresis = <2000>;
3820 type 3743 type = "passive";
3821 }; 3744 };
3822 }; 3745 };
3823 3746
3824 cooling-maps { 3747 cooling-maps {
3825 map0 { 3748 map0 {
3826 trip 3749 trip = <&gpu1_alert0>;
3827 cooli 3750 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3828 }; 3751 };
3829 }; 3752 };
3830 }; 3753 };
3831 3754
3832 gpu-bottom-thermal { 3755 gpu-bottom-thermal {
3833 polling-delay-passive 3756 polling-delay-passive = <250>;
>> 3757 polling-delay = <1000>;
3834 3758
3835 thermal-sensors = <&t 3759 thermal-sensors = <&tsens1 7>;
3836 3760
3837 trips { 3761 trips {
3838 gpu2_alert0: 3762 gpu2_alert0: trip-point0 {
3839 tempe 3763 temperature = <90000>;
3840 hyste 3764 hysteresis = <2000>;
3841 type 3765 type = "passive";
3842 }; 3766 };
3843 }; 3767 };
3844 3768
3845 cooling-maps { 3769 cooling-maps {
3846 map0 { 3770 map0 {
3847 trip 3771 trip = <&gpu2_alert0>;
3848 cooli 3772 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3849 }; 3773 };
3850 }; 3774 };
3851 }; 3775 };
3852 3776
3853 m4m-thermal { 3777 m4m-thermal {
3854 polling-delay-passive 3778 polling-delay-passive = <250>;
>> 3779 polling-delay = <1000>;
3855 3780
3856 thermal-sensors = <&t 3781 thermal-sensors = <&tsens0 1>;
3857 3782
3858 trips { 3783 trips {
3859 m4m_alert0: t 3784 m4m_alert0: trip-point0 {
3860 tempe 3785 temperature = <90000>;
3861 hyste 3786 hysteresis = <2000>;
3862 type 3787 type = "hot";
3863 }; 3788 };
3864 }; 3789 };
3865 }; 3790 };
3866 3791
3867 l3-or-venus-thermal { 3792 l3-or-venus-thermal {
3868 polling-delay-passive 3793 polling-delay-passive = <250>;
>> 3794 polling-delay = <1000>;
3869 3795
3870 thermal-sensors = <&t 3796 thermal-sensors = <&tsens0 2>;
3871 3797
3872 trips { 3798 trips {
3873 l3_or_venus_a 3799 l3_or_venus_alert0: trip-point0 {
3874 tempe 3800 temperature = <90000>;
3875 hyste 3801 hysteresis = <2000>;
3876 type 3802 type = "hot";
3877 }; 3803 };
3878 }; 3804 };
3879 }; 3805 };
3880 3806
3881 cluster0-l2-thermal { 3807 cluster0-l2-thermal {
3882 polling-delay-passive 3808 polling-delay-passive = <250>;
>> 3809 polling-delay = <1000>;
3883 3810
3884 thermal-sensors = <&t 3811 thermal-sensors = <&tsens0 7>;
3885 3812
3886 trips { 3813 trips {
3887 cluster0_l2_a 3814 cluster0_l2_alert0: trip-point0 {
3888 tempe 3815 temperature = <90000>;
3889 hyste 3816 hysteresis = <2000>;
3890 type 3817 type = "hot";
3891 }; 3818 };
3892 }; 3819 };
3893 }; 3820 };
3894 3821
3895 cluster1-l2-thermal { 3822 cluster1-l2-thermal {
3896 polling-delay-passive 3823 polling-delay-passive = <250>;
>> 3824 polling-delay = <1000>;
3897 3825
3898 thermal-sensors = <&t 3826 thermal-sensors = <&tsens0 12>;
3899 3827
3900 trips { 3828 trips {
3901 cluster1_l2_a 3829 cluster1_l2_alert0: trip-point0 {
3902 tempe 3830 temperature = <90000>;
3903 hyste 3831 hysteresis = <2000>;
3904 type 3832 type = "hot";
3905 }; 3833 };
3906 }; 3834 };
3907 }; 3835 };
3908 3836
3909 camera-thermal { 3837 camera-thermal {
3910 polling-delay-passive 3838 polling-delay-passive = <250>;
>> 3839 polling-delay = <1000>;
3911 3840
3912 thermal-sensors = <&t 3841 thermal-sensors = <&tsens1 1>;
3913 3842
3914 trips { 3843 trips {
3915 camera_alert0 3844 camera_alert0: trip-point0 {
3916 tempe 3845 temperature = <90000>;
3917 hyste 3846 hysteresis = <2000>;
3918 type 3847 type = "hot";
3919 }; 3848 };
3920 }; 3849 };
3921 }; 3850 };
3922 3851
3923 q6-dsp-thermal { 3852 q6-dsp-thermal {
3924 polling-delay-passive 3853 polling-delay-passive = <250>;
>> 3854 polling-delay = <1000>;
3925 3855
3926 thermal-sensors = <&t 3856 thermal-sensors = <&tsens1 2>;
3927 3857
3928 trips { 3858 trips {
3929 q6_dsp_alert0 3859 q6_dsp_alert0: trip-point0 {
3930 tempe 3860 temperature = <90000>;
3931 hyste 3861 hysteresis = <2000>;
3932 type 3862 type = "hot";
3933 }; 3863 };
3934 }; 3864 };
3935 }; 3865 };
3936 3866
3937 mem-thermal { 3867 mem-thermal {
3938 polling-delay-passive 3868 polling-delay-passive = <250>;
>> 3869 polling-delay = <1000>;
3939 3870
3940 thermal-sensors = <&t 3871 thermal-sensors = <&tsens1 3>;
3941 3872
3942 trips { 3873 trips {
3943 mem_alert0: t 3874 mem_alert0: trip-point0 {
3944 tempe 3875 temperature = <90000>;
3945 hyste 3876 hysteresis = <2000>;
3946 type 3877 type = "hot";
3947 }; 3878 };
3948 }; 3879 };
3949 }; 3880 };
3950 3881
3951 modemtx-thermal { 3882 modemtx-thermal {
3952 polling-delay-passive 3883 polling-delay-passive = <250>;
>> 3884 polling-delay = <1000>;
3953 3885
3954 thermal-sensors = <&t 3886 thermal-sensors = <&tsens1 4>;
3955 3887
3956 trips { 3888 trips {
3957 modemtx_alert 3889 modemtx_alert0: trip-point0 {
3958 tempe 3890 temperature = <90000>;
3959 hyste 3891 hysteresis = <2000>;
3960 type 3892 type = "hot";
3961 }; 3893 };
3962 }; 3894 };
3963 }; 3895 };
3964 }; 3896 };
3965 3897
3966 timer { 3898 timer {
3967 compatible = "arm,armv8-timer 3899 compatible = "arm,armv8-timer";
3968 interrupts = <GIC_PPI 13 IRQ_ 3900 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
3969 <GIC_PPI 14 IRQ_ 3901 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
3970 <GIC_PPI 11 IRQ_ 3902 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
3971 <GIC_PPI 10 IRQ_ 3903 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
3972 }; 3904 };
3973 }; 3905 };
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