1 // SPDX-License-Identifier: GPL-2.0-only 1 // SPDX-License-Identifier: GPL-2.0-only
2 /* 2 /*
3 * Copyright (c) 2014-2015, The Linux Foundati 3 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
4 */ 4 */
5 5
6 #include <dt-bindings/interrupt-controller/arm 6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-msm8996.h 7 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
8 #include <dt-bindings/clock/qcom,mmcc-msm8996. 8 #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
9 #include <dt-bindings/clock/qcom,rpmcc.h> 9 #include <dt-bindings/clock/qcom,rpmcc.h>
10 #include <dt-bindings/interconnect/qcom,msm899 10 #include <dt-bindings/interconnect/qcom,msm8996.h>
11 #include <dt-bindings/interconnect/qcom,msm899 11 #include <dt-bindings/interconnect/qcom,msm8996-cbf.h>
12 #include <dt-bindings/firmware/qcom,scm.h> 12 #include <dt-bindings/firmware/qcom,scm.h>
13 #include <dt-bindings/gpio/gpio.h> 13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/power/qcom-rpmpd.h> 14 #include <dt-bindings/power/qcom-rpmpd.h>
15 #include <dt-bindings/soc/qcom,apr.h> 15 #include <dt-bindings/soc/qcom,apr.h>
16 #include <dt-bindings/thermal/thermal.h> 16 #include <dt-bindings/thermal/thermal.h>
17 17
18 / { 18 / {
19 interrupt-parent = <&intc>; 19 interrupt-parent = <&intc>;
20 20
21 #address-cells = <2>; 21 #address-cells = <2>;
22 #size-cells = <2>; 22 #size-cells = <2>;
23 23
24 chosen { }; 24 chosen { };
25 25
26 clocks { 26 clocks {
27 xo_board: xo-board { 27 xo_board: xo-board {
28 compatible = "fixed-cl 28 compatible = "fixed-clock";
29 #clock-cells = <0>; 29 #clock-cells = <0>;
30 clock-frequency = <192 30 clock-frequency = <19200000>;
31 clock-output-names = " 31 clock-output-names = "xo_board";
32 }; 32 };
33 33
34 sleep_clk: sleep-clk { 34 sleep_clk: sleep-clk {
35 compatible = "fixed-cl 35 compatible = "fixed-clock";
36 #clock-cells = <0>; 36 #clock-cells = <0>;
37 clock-frequency = <327 37 clock-frequency = <32764>;
38 clock-output-names = " 38 clock-output-names = "sleep_clk";
39 }; 39 };
40 }; 40 };
41 41
42 cpus { 42 cpus {
43 #address-cells = <2>; 43 #address-cells = <2>;
44 #size-cells = <0>; 44 #size-cells = <0>;
45 45
46 CPU0: cpu@0 { 46 CPU0: cpu@0 {
47 device_type = "cpu"; 47 device_type = "cpu";
48 compatible = "qcom,kry 48 compatible = "qcom,kryo";
49 reg = <0x0 0x0>; 49 reg = <0x0 0x0>;
50 enable-method = "psci" 50 enable-method = "psci";
51 cpu-idle-states = <&CP 51 cpu-idle-states = <&CPU_SLEEP_0>;
52 capacity-dmips-mhz = < 52 capacity-dmips-mhz = <1024>;
53 clocks = <&kryocc 0>; 53 clocks = <&kryocc 0>;
54 interconnects = <&cbf 54 interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>;
55 operating-points-v2 = 55 operating-points-v2 = <&cluster0_opp>;
56 #cooling-cells = <2>; 56 #cooling-cells = <2>;
57 next-level-cache = <&L 57 next-level-cache = <&L2_0>;
58 L2_0: l2-cache { 58 L2_0: l2-cache {
59 compatible = " 59 compatible = "cache";
60 cache-level = 60 cache-level = <2>;
61 cache-unified; 61 cache-unified;
62 }; 62 };
63 }; 63 };
64 64
65 CPU1: cpu@1 { 65 CPU1: cpu@1 {
66 device_type = "cpu"; 66 device_type = "cpu";
67 compatible = "qcom,kry 67 compatible = "qcom,kryo";
68 reg = <0x0 0x1>; 68 reg = <0x0 0x1>;
69 enable-method = "psci" 69 enable-method = "psci";
70 cpu-idle-states = <&CP 70 cpu-idle-states = <&CPU_SLEEP_0>;
71 capacity-dmips-mhz = < 71 capacity-dmips-mhz = <1024>;
72 clocks = <&kryocc 0>; 72 clocks = <&kryocc 0>;
73 interconnects = <&cbf 73 interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>;
74 operating-points-v2 = 74 operating-points-v2 = <&cluster0_opp>;
75 #cooling-cells = <2>; 75 #cooling-cells = <2>;
76 next-level-cache = <&L 76 next-level-cache = <&L2_0>;
77 }; 77 };
78 78
79 CPU2: cpu@100 { 79 CPU2: cpu@100 {
80 device_type = "cpu"; 80 device_type = "cpu";
81 compatible = "qcom,kry 81 compatible = "qcom,kryo";
82 reg = <0x0 0x100>; 82 reg = <0x0 0x100>;
83 enable-method = "psci" 83 enable-method = "psci";
84 cpu-idle-states = <&CP 84 cpu-idle-states = <&CPU_SLEEP_0>;
85 capacity-dmips-mhz = < 85 capacity-dmips-mhz = <1024>;
86 clocks = <&kryocc 1>; 86 clocks = <&kryocc 1>;
87 interconnects = <&cbf 87 interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>;
88 operating-points-v2 = 88 operating-points-v2 = <&cluster1_opp>;
89 #cooling-cells = <2>; 89 #cooling-cells = <2>;
90 next-level-cache = <&L 90 next-level-cache = <&L2_1>;
91 L2_1: l2-cache { 91 L2_1: l2-cache {
92 compatible = " 92 compatible = "cache";
93 cache-level = 93 cache-level = <2>;
94 cache-unified; 94 cache-unified;
95 }; 95 };
96 }; 96 };
97 97
98 CPU3: cpu@101 { 98 CPU3: cpu@101 {
99 device_type = "cpu"; 99 device_type = "cpu";
100 compatible = "qcom,kry 100 compatible = "qcom,kryo";
101 reg = <0x0 0x101>; 101 reg = <0x0 0x101>;
102 enable-method = "psci" 102 enable-method = "psci";
103 cpu-idle-states = <&CP 103 cpu-idle-states = <&CPU_SLEEP_0>;
104 capacity-dmips-mhz = < 104 capacity-dmips-mhz = <1024>;
105 clocks = <&kryocc 1>; 105 clocks = <&kryocc 1>;
106 interconnects = <&cbf 106 interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>;
107 operating-points-v2 = 107 operating-points-v2 = <&cluster1_opp>;
108 #cooling-cells = <2>; 108 #cooling-cells = <2>;
109 next-level-cache = <&L 109 next-level-cache = <&L2_1>;
110 }; 110 };
111 111
112 cpu-map { 112 cpu-map {
113 cluster0 { 113 cluster0 {
114 core0 { 114 core0 {
115 cpu = 115 cpu = <&CPU0>;
116 }; 116 };
117 117
118 core1 { 118 core1 {
119 cpu = 119 cpu = <&CPU1>;
120 }; 120 };
121 }; 121 };
122 122
123 cluster1 { 123 cluster1 {
124 core0 { 124 core0 {
125 cpu = 125 cpu = <&CPU2>;
126 }; 126 };
127 127
128 core1 { 128 core1 {
129 cpu = 129 cpu = <&CPU3>;
130 }; 130 };
131 }; 131 };
132 }; 132 };
133 133
134 idle-states { 134 idle-states {
135 entry-method = "psci"; 135 entry-method = "psci";
136 136
137 CPU_SLEEP_0: cpu-sleep 137 CPU_SLEEP_0: cpu-sleep-0 {
138 compatible = " 138 compatible = "arm,idle-state";
139 idle-state-nam 139 idle-state-name = "standalone-power-collapse";
140 arm,psci-suspe 140 arm,psci-suspend-param = <0x00000004>;
141 entry-latency- 141 entry-latency-us = <130>;
142 exit-latency-u 142 exit-latency-us = <80>;
143 min-residency- 143 min-residency-us = <300>;
144 }; 144 };
145 }; 145 };
146 }; 146 };
147 147
148 cluster0_opp: opp-table-cluster0 { 148 cluster0_opp: opp-table-cluster0 {
149 compatible = "operating-points 149 compatible = "operating-points-v2-kryo-cpu";
150 nvmem-cells = <&speedbin_efuse 150 nvmem-cells = <&speedbin_efuse>;
151 opp-shared; 151 opp-shared;
152 152
153 /* Nominal fmax for now */ 153 /* Nominal fmax for now */
154 opp-307200000 { 154 opp-307200000 {
155 opp-hz = /bits/ 64 <30 155 opp-hz = /bits/ 64 <307200000>;
156 opp-supported-hw = <0x 156 opp-supported-hw = <0xf>;
157 clock-latency-ns = <20 157 clock-latency-ns = <200000>;
158 opp-peak-kBps = <30720 158 opp-peak-kBps = <307200>;
159 }; 159 };
160 opp-422400000 { 160 opp-422400000 {
161 opp-hz = /bits/ 64 <42 161 opp-hz = /bits/ 64 <422400000>;
162 opp-supported-hw = <0x 162 opp-supported-hw = <0xf>;
163 clock-latency-ns = <20 163 clock-latency-ns = <200000>;
164 opp-peak-kBps = <30720 164 opp-peak-kBps = <307200>;
165 }; 165 };
166 opp-480000000 { 166 opp-480000000 {
167 opp-hz = /bits/ 64 <48 167 opp-hz = /bits/ 64 <480000000>;
168 opp-supported-hw = <0x 168 opp-supported-hw = <0xf>;
169 clock-latency-ns = <20 169 clock-latency-ns = <200000>;
170 opp-peak-kBps = <30720 170 opp-peak-kBps = <307200>;
171 }; 171 };
172 opp-556800000 { 172 opp-556800000 {
173 opp-hz = /bits/ 64 <55 173 opp-hz = /bits/ 64 <556800000>;
174 opp-supported-hw = <0x 174 opp-supported-hw = <0xf>;
175 clock-latency-ns = <20 175 clock-latency-ns = <200000>;
176 opp-peak-kBps = <30720 176 opp-peak-kBps = <307200>;
177 }; 177 };
178 opp-652800000 { 178 opp-652800000 {
179 opp-hz = /bits/ 64 <65 179 opp-hz = /bits/ 64 <652800000>;
180 opp-supported-hw = <0x 180 opp-supported-hw = <0xf>;
181 clock-latency-ns = <20 181 clock-latency-ns = <200000>;
182 opp-peak-kBps = <38400 182 opp-peak-kBps = <384000>;
183 }; 183 };
184 opp-729600000 { 184 opp-729600000 {
185 opp-hz = /bits/ 64 <72 185 opp-hz = /bits/ 64 <729600000>;
186 opp-supported-hw = <0x 186 opp-supported-hw = <0xf>;
187 clock-latency-ns = <20 187 clock-latency-ns = <200000>;
188 opp-peak-kBps = <46080 188 opp-peak-kBps = <460800>;
189 }; 189 };
190 opp-844800000 { 190 opp-844800000 {
191 opp-hz = /bits/ 64 <84 191 opp-hz = /bits/ 64 <844800000>;
192 opp-supported-hw = <0x 192 opp-supported-hw = <0xf>;
193 clock-latency-ns = <20 193 clock-latency-ns = <200000>;
194 opp-peak-kBps = <53760 194 opp-peak-kBps = <537600>;
195 }; 195 };
196 opp-960000000 { 196 opp-960000000 {
197 opp-hz = /bits/ 64 <96 197 opp-hz = /bits/ 64 <960000000>;
198 opp-supported-hw = <0x 198 opp-supported-hw = <0xf>;
199 clock-latency-ns = <20 199 clock-latency-ns = <200000>;
200 opp-peak-kBps = <67200 200 opp-peak-kBps = <672000>;
201 }; 201 };
202 opp-1036800000 { 202 opp-1036800000 {
203 opp-hz = /bits/ 64 <10 203 opp-hz = /bits/ 64 <1036800000>;
204 opp-supported-hw = <0x 204 opp-supported-hw = <0xf>;
205 clock-latency-ns = <20 205 clock-latency-ns = <200000>;
206 opp-peak-kBps = <67200 206 opp-peak-kBps = <672000>;
207 }; 207 };
208 opp-1113600000 { 208 opp-1113600000 {
209 opp-hz = /bits/ 64 <11 209 opp-hz = /bits/ 64 <1113600000>;
210 opp-supported-hw = <0x 210 opp-supported-hw = <0xf>;
211 clock-latency-ns = <20 211 clock-latency-ns = <200000>;
212 opp-peak-kBps = <82560 212 opp-peak-kBps = <825600>;
213 }; 213 };
214 opp-1190400000 { 214 opp-1190400000 {
215 opp-hz = /bits/ 64 <11 215 opp-hz = /bits/ 64 <1190400000>;
216 opp-supported-hw = <0x 216 opp-supported-hw = <0xf>;
217 clock-latency-ns = <20 217 clock-latency-ns = <200000>;
218 opp-peak-kBps = <82560 218 opp-peak-kBps = <825600>;
219 }; 219 };
220 opp-1228800000 { 220 opp-1228800000 {
221 opp-hz = /bits/ 64 <12 221 opp-hz = /bits/ 64 <1228800000>;
222 opp-supported-hw = <0x 222 opp-supported-hw = <0xf>;
223 clock-latency-ns = <20 223 clock-latency-ns = <200000>;
224 opp-peak-kBps = <90240 224 opp-peak-kBps = <902400>;
225 }; 225 };
226 opp-1324800000 { 226 opp-1324800000 {
227 opp-hz = /bits/ 64 <13 227 opp-hz = /bits/ 64 <1324800000>;
228 opp-supported-hw = <0x 228 opp-supported-hw = <0xd>;
229 clock-latency-ns = <20 229 clock-latency-ns = <200000>;
230 opp-peak-kBps = <10560 230 opp-peak-kBps = <1056000>;
231 }; 231 };
232 opp-1363200000 { 232 opp-1363200000 {
233 opp-hz = /bits/ 64 <13 233 opp-hz = /bits/ 64 <1363200000>;
234 opp-supported-hw = <0x 234 opp-supported-hw = <0x2>;
235 clock-latency-ns = <20 235 clock-latency-ns = <200000>;
236 opp-peak-kBps = <11328 236 opp-peak-kBps = <1132800>;
237 }; 237 };
238 opp-1401600000 { 238 opp-1401600000 {
239 opp-hz = /bits/ 64 <14 239 opp-hz = /bits/ 64 <1401600000>;
240 opp-supported-hw = <0x 240 opp-supported-hw = <0xd>;
241 clock-latency-ns = <20 241 clock-latency-ns = <200000>;
242 opp-peak-kBps = <11328 242 opp-peak-kBps = <1132800>;
243 }; 243 };
244 opp-1478400000 { 244 opp-1478400000 {
245 opp-hz = /bits/ 64 <14 245 opp-hz = /bits/ 64 <1478400000>;
246 opp-supported-hw = <0x 246 opp-supported-hw = <0x9>;
247 clock-latency-ns = <20 247 clock-latency-ns = <200000>;
248 opp-peak-kBps = <11904 248 opp-peak-kBps = <1190400>;
249 }; 249 };
250 opp-1497600000 { 250 opp-1497600000 {
251 opp-hz = /bits/ 64 <14 251 opp-hz = /bits/ 64 <1497600000>;
252 opp-supported-hw = <0x 252 opp-supported-hw = <0x04>;
253 clock-latency-ns = <20 253 clock-latency-ns = <200000>;
254 opp-peak-kBps = <13056 254 opp-peak-kBps = <1305600>;
255 }; 255 };
256 opp-1593600000 { 256 opp-1593600000 {
257 opp-hz = /bits/ 64 <15 257 opp-hz = /bits/ 64 <1593600000>;
258 opp-supported-hw = <0x 258 opp-supported-hw = <0x9>;
259 clock-latency-ns = <20 259 clock-latency-ns = <200000>;
260 opp-peak-kBps = <13824 260 opp-peak-kBps = <1382400>;
261 }; 261 };
262 }; 262 };
263 263
264 cluster1_opp: opp-table-cluster1 { 264 cluster1_opp: opp-table-cluster1 {
265 compatible = "operating-points 265 compatible = "operating-points-v2-kryo-cpu";
266 nvmem-cells = <&speedbin_efuse 266 nvmem-cells = <&speedbin_efuse>;
267 opp-shared; 267 opp-shared;
268 268
269 /* Nominal fmax for now */ 269 /* Nominal fmax for now */
270 opp-307200000 { 270 opp-307200000 {
271 opp-hz = /bits/ 64 <30 271 opp-hz = /bits/ 64 <307200000>;
272 opp-supported-hw = <0x 272 opp-supported-hw = <0xf>;
273 clock-latency-ns = <20 273 clock-latency-ns = <200000>;
274 opp-peak-kBps = <30720 274 opp-peak-kBps = <307200>;
275 }; 275 };
276 opp-403200000 { 276 opp-403200000 {
277 opp-hz = /bits/ 64 <40 277 opp-hz = /bits/ 64 <403200000>;
278 opp-supported-hw = <0x 278 opp-supported-hw = <0xf>;
279 clock-latency-ns = <20 279 clock-latency-ns = <200000>;
280 opp-peak-kBps = <30720 280 opp-peak-kBps = <307200>;
281 }; 281 };
282 opp-480000000 { 282 opp-480000000 {
283 opp-hz = /bits/ 64 <48 283 opp-hz = /bits/ 64 <480000000>;
284 opp-supported-hw = <0x 284 opp-supported-hw = <0xf>;
285 clock-latency-ns = <20 285 clock-latency-ns = <200000>;
286 opp-peak-kBps = <30720 286 opp-peak-kBps = <307200>;
287 }; 287 };
288 opp-556800000 { 288 opp-556800000 {
289 opp-hz = /bits/ 64 <55 289 opp-hz = /bits/ 64 <556800000>;
290 opp-supported-hw = <0x 290 opp-supported-hw = <0xf>;
291 clock-latency-ns = <20 291 clock-latency-ns = <200000>;
292 opp-peak-kBps = <30720 292 opp-peak-kBps = <307200>;
293 }; 293 };
294 opp-652800000 { 294 opp-652800000 {
295 opp-hz = /bits/ 64 <65 295 opp-hz = /bits/ 64 <652800000>;
296 opp-supported-hw = <0x 296 opp-supported-hw = <0xf>;
297 clock-latency-ns = <20 297 clock-latency-ns = <200000>;
298 opp-peak-kBps = <30720 298 opp-peak-kBps = <307200>;
299 }; 299 };
300 opp-729600000 { 300 opp-729600000 {
301 opp-hz = /bits/ 64 <72 301 opp-hz = /bits/ 64 <729600000>;
302 opp-supported-hw = <0x 302 opp-supported-hw = <0xf>;
303 clock-latency-ns = <20 303 clock-latency-ns = <200000>;
304 opp-peak-kBps = <30720 304 opp-peak-kBps = <307200>;
305 }; 305 };
306 opp-806400000 { 306 opp-806400000 {
307 opp-hz = /bits/ 64 <80 307 opp-hz = /bits/ 64 <806400000>;
308 opp-supported-hw = <0x 308 opp-supported-hw = <0xf>;
309 clock-latency-ns = <20 309 clock-latency-ns = <200000>;
310 opp-peak-kBps = <38400 310 opp-peak-kBps = <384000>;
311 }; 311 };
312 opp-883200000 { 312 opp-883200000 {
313 opp-hz = /bits/ 64 <88 313 opp-hz = /bits/ 64 <883200000>;
314 opp-supported-hw = <0x 314 opp-supported-hw = <0xf>;
315 clock-latency-ns = <20 315 clock-latency-ns = <200000>;
316 opp-peak-kBps = <46080 316 opp-peak-kBps = <460800>;
317 }; 317 };
318 opp-940800000 { 318 opp-940800000 {
319 opp-hz = /bits/ 64 <94 319 opp-hz = /bits/ 64 <940800000>;
320 opp-supported-hw = <0x 320 opp-supported-hw = <0xf>;
321 clock-latency-ns = <20 321 clock-latency-ns = <200000>;
322 opp-peak-kBps = <53760 322 opp-peak-kBps = <537600>;
323 }; 323 };
324 opp-1036800000 { 324 opp-1036800000 {
325 opp-hz = /bits/ 64 <10 325 opp-hz = /bits/ 64 <1036800000>;
326 opp-supported-hw = <0x 326 opp-supported-hw = <0xf>;
327 clock-latency-ns = <20 327 clock-latency-ns = <200000>;
328 opp-peak-kBps = <59520 328 opp-peak-kBps = <595200>;
329 }; 329 };
330 opp-1113600000 { 330 opp-1113600000 {
331 opp-hz = /bits/ 64 <11 331 opp-hz = /bits/ 64 <1113600000>;
332 opp-supported-hw = <0x 332 opp-supported-hw = <0xf>;
333 clock-latency-ns = <20 333 clock-latency-ns = <200000>;
334 opp-peak-kBps = <67200 334 opp-peak-kBps = <672000>;
335 }; 335 };
336 opp-1190400000 { 336 opp-1190400000 {
337 opp-hz = /bits/ 64 <11 337 opp-hz = /bits/ 64 <1190400000>;
338 opp-supported-hw = <0x 338 opp-supported-hw = <0xf>;
339 clock-latency-ns = <20 339 clock-latency-ns = <200000>;
340 opp-peak-kBps = <67200 340 opp-peak-kBps = <672000>;
341 }; 341 };
342 opp-1248000000 { 342 opp-1248000000 {
343 opp-hz = /bits/ 64 <12 343 opp-hz = /bits/ 64 <1248000000>;
344 opp-supported-hw = <0x 344 opp-supported-hw = <0xf>;
345 clock-latency-ns = <20 345 clock-latency-ns = <200000>;
346 opp-peak-kBps = <74880 346 opp-peak-kBps = <748800>;
347 }; 347 };
348 opp-1324800000 { 348 opp-1324800000 {
349 opp-hz = /bits/ 64 <13 349 opp-hz = /bits/ 64 <1324800000>;
350 opp-supported-hw = <0x 350 opp-supported-hw = <0xf>;
351 clock-latency-ns = <20 351 clock-latency-ns = <200000>;
352 opp-peak-kBps = <82560 352 opp-peak-kBps = <825600>;
353 }; 353 };
354 opp-1401600000 { 354 opp-1401600000 {
355 opp-hz = /bits/ 64 <14 355 opp-hz = /bits/ 64 <1401600000>;
356 opp-supported-hw = <0x 356 opp-supported-hw = <0xf>;
357 clock-latency-ns = <20 357 clock-latency-ns = <200000>;
358 opp-peak-kBps = <90240 358 opp-peak-kBps = <902400>;
359 }; 359 };
360 opp-1478400000 { 360 opp-1478400000 {
361 opp-hz = /bits/ 64 <14 361 opp-hz = /bits/ 64 <1478400000>;
362 opp-supported-hw = <0x 362 opp-supported-hw = <0xf>;
363 clock-latency-ns = <20 363 clock-latency-ns = <200000>;
364 opp-peak-kBps = <97920 364 opp-peak-kBps = <979200>;
365 }; 365 };
366 opp-1555200000 { 366 opp-1555200000 {
367 opp-hz = /bits/ 64 <15 367 opp-hz = /bits/ 64 <1555200000>;
368 opp-supported-hw = <0x 368 opp-supported-hw = <0xf>;
369 clock-latency-ns = <20 369 clock-latency-ns = <200000>;
370 opp-peak-kBps = <10560 370 opp-peak-kBps = <1056000>;
371 }; 371 };
372 opp-1632000000 { 372 opp-1632000000 {
373 opp-hz = /bits/ 64 <16 373 opp-hz = /bits/ 64 <1632000000>;
374 opp-supported-hw = <0x 374 opp-supported-hw = <0xf>;
375 clock-latency-ns = <20 375 clock-latency-ns = <200000>;
376 opp-peak-kBps = <11904 376 opp-peak-kBps = <1190400>;
377 }; 377 };
378 opp-1708800000 { 378 opp-1708800000 {
379 opp-hz = /bits/ 64 <17 379 opp-hz = /bits/ 64 <1708800000>;
380 opp-supported-hw = <0x 380 opp-supported-hw = <0xf>;
381 clock-latency-ns = <20 381 clock-latency-ns = <200000>;
382 opp-peak-kBps = <12288 382 opp-peak-kBps = <1228800>;
383 }; 383 };
384 opp-1785600000 { 384 opp-1785600000 {
385 opp-hz = /bits/ 64 <17 385 opp-hz = /bits/ 64 <1785600000>;
386 opp-supported-hw = <0x 386 opp-supported-hw = <0xf>;
387 clock-latency-ns = <20 387 clock-latency-ns = <200000>;
388 opp-peak-kBps = <13056 388 opp-peak-kBps = <1305600>;
389 }; 389 };
390 opp-1804800000 { 390 opp-1804800000 {
391 opp-hz = /bits/ 64 <18 391 opp-hz = /bits/ 64 <1804800000>;
392 opp-supported-hw = <0x 392 opp-supported-hw = <0xe>;
393 clock-latency-ns = <20 393 clock-latency-ns = <200000>;
394 opp-peak-kBps = <13056 394 opp-peak-kBps = <1305600>;
395 }; 395 };
396 opp-1824000000 { 396 opp-1824000000 {
397 opp-hz = /bits/ 64 <18 397 opp-hz = /bits/ 64 <1824000000>;
398 opp-supported-hw = <0x 398 opp-supported-hw = <0x1>;
399 clock-latency-ns = <20 399 clock-latency-ns = <200000>;
400 opp-peak-kBps = <13824 400 opp-peak-kBps = <1382400>;
401 }; 401 };
402 opp-1900800000 { 402 opp-1900800000 {
403 opp-hz = /bits/ 64 <19 403 opp-hz = /bits/ 64 <1900800000>;
404 opp-supported-hw = <0x 404 opp-supported-hw = <0x4>;
405 clock-latency-ns = <20 405 clock-latency-ns = <200000>;
406 opp-peak-kBps = <13056 406 opp-peak-kBps = <1305600>;
407 }; 407 };
408 opp-1920000000 { 408 opp-1920000000 {
409 opp-hz = /bits/ 64 <19 409 opp-hz = /bits/ 64 <1920000000>;
410 opp-supported-hw = <0x 410 opp-supported-hw = <0x1>;
411 clock-latency-ns = <20 411 clock-latency-ns = <200000>;
412 opp-peak-kBps = <14592 412 opp-peak-kBps = <1459200>;
413 }; 413 };
414 opp-1996800000 { 414 opp-1996800000 {
415 opp-hz = /bits/ 64 <19 415 opp-hz = /bits/ 64 <1996800000>;
416 opp-supported-hw = <0x 416 opp-supported-hw = <0x1>;
417 clock-latency-ns = <20 417 clock-latency-ns = <200000>;
418 opp-peak-kBps = <15936 418 opp-peak-kBps = <1593600>;
419 }; 419 };
420 opp-2073600000 { 420 opp-2073600000 {
421 opp-hz = /bits/ 64 <20 421 opp-hz = /bits/ 64 <2073600000>;
422 opp-supported-hw = <0x 422 opp-supported-hw = <0x1>;
423 clock-latency-ns = <20 423 clock-latency-ns = <200000>;
424 opp-peak-kBps = <15936 424 opp-peak-kBps = <1593600>;
425 }; 425 };
426 opp-2150400000 { 426 opp-2150400000 {
427 opp-hz = /bits/ 64 <21 427 opp-hz = /bits/ 64 <2150400000>;
428 opp-supported-hw = <0x 428 opp-supported-hw = <0x1>;
429 clock-latency-ns = <20 429 clock-latency-ns = <200000>;
430 opp-peak-kBps = <15936 430 opp-peak-kBps = <1593600>;
431 }; 431 };
432 }; 432 };
433 433
434 firmware { 434 firmware {
435 scm { 435 scm {
436 compatible = "qcom,scm 436 compatible = "qcom,scm-msm8996", "qcom,scm";
437 qcom,dload-mode = <&tc 437 qcom,dload-mode = <&tcsr_2 0x13000>;
438 }; 438 };
439 }; 439 };
440 440
441 memory@80000000 { 441 memory@80000000 {
442 device_type = "memory"; 442 device_type = "memory";
443 /* We expect the bootloader to 443 /* We expect the bootloader to fill in the reg */
444 reg = <0x0 0x80000000 0x0 0x0> 444 reg = <0x0 0x80000000 0x0 0x0>;
445 }; 445 };
446 446
447 etm { 447 etm {
448 compatible = "qcom,coresight-r 448 compatible = "qcom,coresight-remote-etm";
449 449
450 out-ports { 450 out-ports {
451 port { 451 port {
452 modem_etm_out_ 452 modem_etm_out_funnel_in2: endpoint {
453 remote 453 remote-endpoint =
454 <&fu 454 <&funnel_in2_in_modem_etm>;
455 }; 455 };
456 }; 456 };
457 }; 457 };
458 }; 458 };
459 459
460 psci { 460 psci {
461 compatible = "arm,psci-1.0"; 461 compatible = "arm,psci-1.0";
462 method = "smc"; 462 method = "smc";
463 }; 463 };
464 464
465 rpm: remoteproc { 465 rpm: remoteproc {
466 compatible = "qcom,msm8996-rpm 466 compatible = "qcom,msm8996-rpm-proc", "qcom,rpm-proc";
467 467
468 glink-edge { 468 glink-edge {
469 compatible = "qcom,gli 469 compatible = "qcom,glink-rpm";
470 interrupts = <GIC_SPI 470 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
471 qcom,rpm-msg-ram = <&r 471 qcom,rpm-msg-ram = <&rpm_msg_ram>;
472 mboxes = <&apcs_glb 0> 472 mboxes = <&apcs_glb 0>;
473 473
474 rpm_requests: rpm-requ 474 rpm_requests: rpm-requests {
475 compatible = " !! 475 compatible = "qcom,rpm-msm8996";
476 qcom,glink-cha 476 qcom,glink-channels = "rpm_requests";
477 477
478 rpmcc: clock-c 478 rpmcc: clock-controller {
479 compat 479 compatible = "qcom,rpmcc-msm8996", "qcom,rpmcc";
480 #clock 480 #clock-cells = <1>;
481 clocks 481 clocks = <&xo_board>;
482 clock- 482 clock-names = "xo";
483 }; 483 };
484 484
485 rpmpd: power-c 485 rpmpd: power-controller {
486 compat 486 compatible = "qcom,msm8996-rpmpd";
487 #power 487 #power-domain-cells = <1>;
488 operat 488 operating-points-v2 = <&rpmpd_opp_table>;
489 489
490 rpmpd_ 490 rpmpd_opp_table: opp-table {
491 491 compatible = "operating-points-v2";
492 492
493 493 rpmpd_opp1: opp1 {
494 494 opp-level = <1>;
495 495 };
496 496
497 497 rpmpd_opp2: opp2 {
498 498 opp-level = <2>;
499 499 };
500 500
501 501 rpmpd_opp3: opp3 {
502 502 opp-level = <3>;
503 503 };
504 504
505 505 rpmpd_opp4: opp4 {
506 506 opp-level = <4>;
507 507 };
508 508
509 509 rpmpd_opp5: opp5 {
510 510 opp-level = <5>;
511 511 };
512 512
513 513 rpmpd_opp6: opp6 {
514 514 opp-level = <6>;
515 515 };
516 }; 516 };
517 }; 517 };
518 }; 518 };
519 }; 519 };
520 }; 520 };
521 521
522 reserved-memory { 522 reserved-memory {
523 #address-cells = <2>; 523 #address-cells = <2>;
524 #size-cells = <2>; 524 #size-cells = <2>;
525 ranges; 525 ranges;
526 526
527 hyp_mem: memory@85800000 { 527 hyp_mem: memory@85800000 {
528 reg = <0x0 0x85800000 528 reg = <0x0 0x85800000 0x0 0x600000>;
529 no-map; 529 no-map;
530 }; 530 };
531 531
532 xbl_mem: memory@85e00000 { 532 xbl_mem: memory@85e00000 {
533 reg = <0x0 0x85e00000 533 reg = <0x0 0x85e00000 0x0 0x200000>;
534 no-map; 534 no-map;
535 }; 535 };
536 536
537 smem_mem: smem-mem@86000000 { 537 smem_mem: smem-mem@86000000 {
538 reg = <0x0 0x86000000 538 reg = <0x0 0x86000000 0x0 0x200000>;
539 no-map; 539 no-map;
540 }; 540 };
541 541
542 tz_mem: memory@86200000 { 542 tz_mem: memory@86200000 {
543 reg = <0x0 0x86200000 543 reg = <0x0 0x86200000 0x0 0x2600000>;
544 no-map; 544 no-map;
545 }; 545 };
546 546
547 rmtfs_mem: rmtfs { 547 rmtfs_mem: rmtfs {
548 compatible = "qcom,rmt 548 compatible = "qcom,rmtfs-mem";
549 549
550 size = <0x0 0x200000>; 550 size = <0x0 0x200000>;
551 alloc-ranges = <0x0 0x 551 alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
552 no-map; 552 no-map;
553 553
554 qcom,client-id = <1>; 554 qcom,client-id = <1>;
555 qcom,vmid = <QCOM_SCM_ 555 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>;
556 }; 556 };
557 557
558 mpss_mem: mpss@88800000 { 558 mpss_mem: mpss@88800000 {
559 reg = <0x0 0x88800000 559 reg = <0x0 0x88800000 0x0 0x6200000>;
560 no-map; 560 no-map;
561 }; 561 };
562 562
563 adsp_mem: adsp@8ea00000 { 563 adsp_mem: adsp@8ea00000 {
564 reg = <0x0 0x8ea00000 564 reg = <0x0 0x8ea00000 0x0 0x1b00000>;
565 no-map; 565 no-map;
566 }; 566 };
567 567
568 slpi_mem: slpi@90500000 { 568 slpi_mem: slpi@90500000 {
569 reg = <0x0 0x90500000 569 reg = <0x0 0x90500000 0x0 0xa00000>;
570 no-map; 570 no-map;
571 }; 571 };
572 572
573 gpu_mem: gpu@90f00000 { 573 gpu_mem: gpu@90f00000 {
574 compatible = "shared-d 574 compatible = "shared-dma-pool";
575 reg = <0x0 0x90f00000 575 reg = <0x0 0x90f00000 0x0 0x100000>;
576 no-map; 576 no-map;
577 }; 577 };
578 578
579 venus_mem: venus@91000000 { 579 venus_mem: venus@91000000 {
580 reg = <0x0 0x91000000 580 reg = <0x0 0x91000000 0x0 0x500000>;
581 no-map; 581 no-map;
582 }; 582 };
583 583
584 mba_mem: mba@91500000 { 584 mba_mem: mba@91500000 {
585 reg = <0x0 0x91500000 585 reg = <0x0 0x91500000 0x0 0x200000>;
586 no-map; 586 no-map;
587 }; 587 };
588 588
589 mdata_mem: mpss-metadata { 589 mdata_mem: mpss-metadata {
590 alloc-ranges = <0x0 0x 590 alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>;
591 size = <0x0 0x4000>; 591 size = <0x0 0x4000>;
592 no-map; 592 no-map;
593 }; 593 };
594 }; 594 };
595 595
596 smem { 596 smem {
597 compatible = "qcom,smem"; 597 compatible = "qcom,smem";
598 memory-region = <&smem_mem>; 598 memory-region = <&smem_mem>;
599 hwlocks = <&tcsr_mutex 3>; 599 hwlocks = <&tcsr_mutex 3>;
600 }; 600 };
601 601
602 smp2p-adsp { 602 smp2p-adsp {
603 compatible = "qcom,smp2p"; 603 compatible = "qcom,smp2p";
604 qcom,smem = <443>, <429>; 604 qcom,smem = <443>, <429>;
605 605
606 interrupts = <GIC_SPI 158 IRQ_ 606 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
607 607
608 mboxes = <&apcs_glb 10>; 608 mboxes = <&apcs_glb 10>;
609 609
610 qcom,local-pid = <0>; 610 qcom,local-pid = <0>;
611 qcom,remote-pid = <2>; 611 qcom,remote-pid = <2>;
612 612
613 adsp_smp2p_out: master-kernel 613 adsp_smp2p_out: master-kernel {
614 qcom,entry-name = "mas 614 qcom,entry-name = "master-kernel";
615 #qcom,smem-state-cells 615 #qcom,smem-state-cells = <1>;
616 }; 616 };
617 617
618 adsp_smp2p_in: slave-kernel { 618 adsp_smp2p_in: slave-kernel {
619 qcom,entry-name = "sla 619 qcom,entry-name = "slave-kernel";
620 620
621 interrupt-controller; 621 interrupt-controller;
622 #interrupt-cells = <2> 622 #interrupt-cells = <2>;
623 }; 623 };
624 }; 624 };
625 625
626 smp2p-mpss { 626 smp2p-mpss {
627 compatible = "qcom,smp2p"; 627 compatible = "qcom,smp2p";
628 qcom,smem = <435>, <428>; 628 qcom,smem = <435>, <428>;
629 629
630 interrupts = <GIC_SPI 451 IRQ_ 630 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
631 631
632 mboxes = <&apcs_glb 14>; 632 mboxes = <&apcs_glb 14>;
633 633
634 qcom,local-pid = <0>; 634 qcom,local-pid = <0>;
635 qcom,remote-pid = <1>; 635 qcom,remote-pid = <1>;
636 636
637 mpss_smp2p_out: master-kernel 637 mpss_smp2p_out: master-kernel {
638 qcom,entry-name = "mas 638 qcom,entry-name = "master-kernel";
639 #qcom,smem-state-cells 639 #qcom,smem-state-cells = <1>;
640 }; 640 };
641 641
642 mpss_smp2p_in: slave-kernel { 642 mpss_smp2p_in: slave-kernel {
643 qcom,entry-name = "sla 643 qcom,entry-name = "slave-kernel";
644 644
645 interrupt-controller; 645 interrupt-controller;
646 #interrupt-cells = <2> 646 #interrupt-cells = <2>;
647 }; 647 };
648 }; 648 };
649 649
650 smp2p-slpi { 650 smp2p-slpi {
651 compatible = "qcom,smp2p"; 651 compatible = "qcom,smp2p";
652 qcom,smem = <481>, <430>; 652 qcom,smem = <481>, <430>;
653 653
654 interrupts = <GIC_SPI 178 IRQ_ 654 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
655 655
656 mboxes = <&apcs_glb 26>; 656 mboxes = <&apcs_glb 26>;
657 657
658 qcom,local-pid = <0>; 658 qcom,local-pid = <0>;
659 qcom,remote-pid = <3>; 659 qcom,remote-pid = <3>;
660 660
661 slpi_smp2p_out: master-kernel 661 slpi_smp2p_out: master-kernel {
662 qcom,entry-name = "mas 662 qcom,entry-name = "master-kernel";
663 #qcom,smem-state-cells 663 #qcom,smem-state-cells = <1>;
664 }; 664 };
665 665
666 slpi_smp2p_in: slave-kernel { 666 slpi_smp2p_in: slave-kernel {
667 qcom,entry-name = "sla 667 qcom,entry-name = "slave-kernel";
668 668
669 interrupt-controller; 669 interrupt-controller;
670 #interrupt-cells = <2> 670 #interrupt-cells = <2>;
671 }; 671 };
672 }; 672 };
673 673
674 soc: soc@0 { 674 soc: soc@0 {
675 #address-cells = <1>; 675 #address-cells = <1>;
676 #size-cells = <1>; 676 #size-cells = <1>;
677 ranges = <0 0 0 0xffffffff>; 677 ranges = <0 0 0 0xffffffff>;
678 compatible = "simple-bus"; 678 compatible = "simple-bus";
679 679
680 pcie_phy: phy-wrapper@34000 { 680 pcie_phy: phy-wrapper@34000 {
681 compatible = "qcom,msm 681 compatible = "qcom,msm8996-qmp-pcie-phy";
682 reg = <0x00034000 0x48 682 reg = <0x00034000 0x488>;
683 #address-cells = <1>; 683 #address-cells = <1>;
684 #size-cells = <1>; 684 #size-cells = <1>;
685 ranges = <0x0 0x000340 685 ranges = <0x0 0x00034000 0x4000>;
686 686
687 clocks = <&gcc GCC_PCI 687 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
688 <&gcc GCC_PCIE 688 <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
689 <&gcc GCC_PCIE 689 <&gcc GCC_PCIE_CLKREF_CLK>;
690 clock-names = "aux", " 690 clock-names = "aux", "cfg_ahb", "ref";
691 691
692 resets = <&gcc GCC_PCI 692 resets = <&gcc GCC_PCIE_PHY_BCR>,
693 <&gcc GCC_PCIE 693 <&gcc GCC_PCIE_PHY_COM_BCR>,
694 <&gcc GCC_PCIE 694 <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
695 reset-names = "phy", " 695 reset-names = "phy", "common", "cfg";
696 696
697 status = "disabled"; 697 status = "disabled";
698 698
699 pciephy_0: phy@1000 { 699 pciephy_0: phy@1000 {
700 reg = <0x1000 700 reg = <0x1000 0x130>,
701 <0x1200 701 <0x1200 0x200>,
702 <0x1400 702 <0x1400 0x1dc>;
703 703
704 clocks = <&gcc 704 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
705 clock-names = 705 clock-names = "pipe0";
706 resets = <&gcc 706 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
707 reset-names = 707 reset-names = "lane0";
708 708
709 #clock-cells = 709 #clock-cells = <0>;
710 clock-output-n 710 clock-output-names = "pcie_0_pipe_clk_src";
711 711
712 #phy-cells = < 712 #phy-cells = <0>;
713 }; 713 };
714 714
715 pciephy_1: phy@2000 { 715 pciephy_1: phy@2000 {
716 reg = <0x2000 716 reg = <0x2000 0x130>,
717 <0x2200 717 <0x2200 0x200>,
718 <0x2400 718 <0x2400 0x1dc>;
719 719
720 clocks = <&gcc 720 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
721 clock-names = 721 clock-names = "pipe1";
722 resets = <&gcc 722 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
723 reset-names = 723 reset-names = "lane1";
724 724
725 #clock-cells = 725 #clock-cells = <0>;
726 clock-output-n 726 clock-output-names = "pcie_1_pipe_clk_src";
727 727
728 #phy-cells = < 728 #phy-cells = <0>;
729 }; 729 };
730 730
731 pciephy_2: phy@3000 { 731 pciephy_2: phy@3000 {
732 reg = <0x3000 732 reg = <0x3000 0x130>,
733 <0x3200 733 <0x3200 0x200>,
734 <0x3400 734 <0x3400 0x1dc>;
735 735
736 clocks = <&gcc 736 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
737 clock-names = 737 clock-names = "pipe2";
738 resets = <&gcc 738 resets = <&gcc GCC_PCIE_2_PHY_BCR>;
739 reset-names = 739 reset-names = "lane2";
740 740
741 #clock-cells = 741 #clock-cells = <0>;
742 clock-output-n 742 clock-output-names = "pcie_2_pipe_clk_src";
743 743
744 #phy-cells = < 744 #phy-cells = <0>;
745 }; 745 };
746 }; 746 };
747 747
748 rpm_msg_ram: sram@68000 { 748 rpm_msg_ram: sram@68000 {
749 compatible = "qcom,rpm 749 compatible = "qcom,rpm-msg-ram";
750 reg = <0x00068000 0x60 750 reg = <0x00068000 0x6000>;
751 }; 751 };
752 752
753 qfprom@74000 { 753 qfprom@74000 {
754 compatible = "qcom,msm 754 compatible = "qcom,msm8996-qfprom", "qcom,qfprom";
755 reg = <0x00074000 0x8f 755 reg = <0x00074000 0x8ff>;
756 #address-cells = <1>; 756 #address-cells = <1>;
757 #size-cells = <1>; 757 #size-cells = <1>;
758 758
759 qusb2p_hstx_trim: hstx 759 qusb2p_hstx_trim: hstx-trim@24e {
760 reg = <0x24e 0 760 reg = <0x24e 0x2>;
761 bits = <5 4>; 761 bits = <5 4>;
762 }; 762 };
763 763
764 qusb2s_hstx_trim: hstx 764 qusb2s_hstx_trim: hstx-trim@24f {
765 reg = <0x24f 0 765 reg = <0x24f 0x1>;
766 bits = <1 4>; 766 bits = <1 4>;
767 }; 767 };
768 768
769 speedbin_efuse: speedb 769 speedbin_efuse: speedbin@133 {
770 reg = <0x133 0 770 reg = <0x133 0x1>;
771 bits = <5 3>; 771 bits = <5 3>;
772 }; 772 };
773 }; 773 };
774 774
775 rng: rng@83000 { 775 rng: rng@83000 {
776 compatible = "qcom,prn 776 compatible = "qcom,prng-ee";
777 reg = <0x00083000 0x10 777 reg = <0x00083000 0x1000>;
778 clocks = <&gcc GCC_PRN 778 clocks = <&gcc GCC_PRNG_AHB_CLK>;
779 clock-names = "core"; 779 clock-names = "core";
780 }; 780 };
781 781
782 gcc: clock-controller@300000 { 782 gcc: clock-controller@300000 {
783 compatible = "qcom,gcc 783 compatible = "qcom,gcc-msm8996";
784 #clock-cells = <1>; 784 #clock-cells = <1>;
785 #reset-cells = <1>; 785 #reset-cells = <1>;
786 #power-domain-cells = 786 #power-domain-cells = <1>;
787 reg = <0x00300000 0x90 787 reg = <0x00300000 0x90000>;
788 788
789 clocks = <&rpmcc RPM_S 789 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
790 <&rpmcc RPM_S 790 <&rpmcc RPM_SMD_LN_BB_CLK>,
791 <&sleep_clk>, 791 <&sleep_clk>,
792 <&pciephy_0>, 792 <&pciephy_0>,
793 <&pciephy_1>, 793 <&pciephy_1>,
794 <&pciephy_2>, 794 <&pciephy_2>,
795 <&usb3phy>, 795 <&usb3phy>,
796 <&ufsphy 0>, 796 <&ufsphy 0>,
797 <&ufsphy 1>, 797 <&ufsphy 1>,
798 <&ufsphy 2>; 798 <&ufsphy 2>;
799 clock-names = "cxo", 799 clock-names = "cxo",
800 "cxo2", 800 "cxo2",
801 "sleep_c 801 "sleep_clk",
802 "pcie_0_ 802 "pcie_0_pipe_clk_src",
803 "pcie_1_ 803 "pcie_1_pipe_clk_src",
804 "pcie_2_ 804 "pcie_2_pipe_clk_src",
805 "usb3_ph 805 "usb3_phy_pipe_clk_src",
806 "ufs_rx_ 806 "ufs_rx_symbol_0_clk_src",
807 "ufs_rx_ 807 "ufs_rx_symbol_1_clk_src",
808 "ufs_tx_ 808 "ufs_tx_symbol_0_clk_src";
809 }; 809 };
810 810
811 bimc: interconnect@408000 { 811 bimc: interconnect@408000 {
812 compatible = "qcom,msm 812 compatible = "qcom,msm8996-bimc";
813 reg = <0x00408000 0x5a 813 reg = <0x00408000 0x5a000>;
814 #interconnect-cells = 814 #interconnect-cells = <1>;
815 }; 815 };
816 816
817 tsens0: thermal-sensor@4a9000 817 tsens0: thermal-sensor@4a9000 {
818 compatible = "qcom,msm 818 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
819 reg = <0x004a9000 0x10 819 reg = <0x004a9000 0x1000>, /* TM */
820 <0x004a8000 0x10 820 <0x004a8000 0x1000>; /* SROT */
821 #qcom,sensors = <13>; 821 #qcom,sensors = <13>;
822 interrupts = <GIC_SPI 822 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
823 <GIC_SPI 823 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
824 interrupt-names = "upl 824 interrupt-names = "uplow", "critical";
825 #thermal-sensor-cells 825 #thermal-sensor-cells = <1>;
826 }; 826 };
827 827
828 tsens1: thermal-sensor@4ad000 828 tsens1: thermal-sensor@4ad000 {
829 compatible = "qcom,msm 829 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
830 reg = <0x004ad000 0x10 830 reg = <0x004ad000 0x1000>, /* TM */
831 <0x004ac000 0x10 831 <0x004ac000 0x1000>; /* SROT */
832 #qcom,sensors = <8>; 832 #qcom,sensors = <8>;
833 interrupts = <GIC_SPI 833 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
834 <GIC_SPI 834 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
835 interrupt-names = "upl 835 interrupt-names = "uplow", "critical";
836 #thermal-sensor-cells 836 #thermal-sensor-cells = <1>;
837 }; 837 };
838 838
839 cryptobam: dma-controller@6440 839 cryptobam: dma-controller@644000 {
840 compatible = "qcom,bam 840 compatible = "qcom,bam-v1.7.0";
841 reg = <0x00644000 0x24 841 reg = <0x00644000 0x24000>;
842 interrupts = <GIC_SPI 842 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
843 clocks = <&gcc GCC_CE1 843 clocks = <&gcc GCC_CE1_CLK>;
844 clock-names = "bam_clk 844 clock-names = "bam_clk";
845 #dma-cells = <1>; 845 #dma-cells = <1>;
846 qcom,ee = <0>; 846 qcom,ee = <0>;
847 qcom,controlled-remote 847 qcom,controlled-remotely;
848 }; 848 };
849 849
850 crypto: crypto@67a000 { 850 crypto: crypto@67a000 {
851 compatible = "qcom,cry 851 compatible = "qcom,crypto-v5.4";
852 reg = <0x0067a000 0x60 852 reg = <0x0067a000 0x6000>;
853 clocks = <&gcc GCC_CE1 853 clocks = <&gcc GCC_CE1_AHB_CLK>,
854 <&gcc GCC_CE1 854 <&gcc GCC_CE1_AXI_CLK>,
855 <&gcc GCC_CE1 855 <&gcc GCC_CE1_CLK>;
856 clock-names = "iface", 856 clock-names = "iface", "bus", "core";
857 dmas = <&cryptobam 6>, 857 dmas = <&cryptobam 6>, <&cryptobam 7>;
858 dma-names = "rx", "tx" 858 dma-names = "rx", "tx";
859 }; 859 };
860 860
861 cnoc: interconnect@500000 { 861 cnoc: interconnect@500000 {
862 compatible = "qcom,msm 862 compatible = "qcom,msm8996-cnoc";
863 reg = <0x00500000 0x10 863 reg = <0x00500000 0x1000>;
864 #interconnect-cells = 864 #interconnect-cells = <1>;
865 }; 865 };
866 866
867 snoc: interconnect@524000 { 867 snoc: interconnect@524000 {
868 compatible = "qcom,msm 868 compatible = "qcom,msm8996-snoc";
869 reg = <0x00524000 0x1c 869 reg = <0x00524000 0x1c000>;
870 #interconnect-cells = 870 #interconnect-cells = <1>;
871 }; 871 };
872 872
873 a0noc: interconnect@543000 { 873 a0noc: interconnect@543000 {
874 compatible = "qcom,msm 874 compatible = "qcom,msm8996-a0noc";
875 reg = <0x00543000 0x60 875 reg = <0x00543000 0x6000>;
876 #interconnect-cells = 876 #interconnect-cells = <1>;
877 clock-names = "aggre0_ 877 clock-names = "aggre0_snoc_axi",
878 "aggre0_ 878 "aggre0_cnoc_ahb",
879 "aggre0_ 879 "aggre0_noc_mpu_cfg";
880 clocks = <&gcc GCC_AGG 880 clocks = <&gcc GCC_AGGRE0_SNOC_AXI_CLK>,
881 <&gcc GCC_AGG 881 <&gcc GCC_AGGRE0_CNOC_AHB_CLK>,
882 <&gcc GCC_AGG 882 <&gcc GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK>;
883 power-domains = <&gcc 883 power-domains = <&gcc AGGRE0_NOC_GDSC>;
884 }; 884 };
885 885
886 a1noc: interconnect@562000 { 886 a1noc: interconnect@562000 {
887 compatible = "qcom,msm 887 compatible = "qcom,msm8996-a1noc";
888 reg = <0x00562000 0x50 888 reg = <0x00562000 0x5000>;
889 #interconnect-cells = 889 #interconnect-cells = <1>;
890 }; 890 };
891 891
892 a2noc: interconnect@583000 { 892 a2noc: interconnect@583000 {
893 compatible = "qcom,msm 893 compatible = "qcom,msm8996-a2noc";
894 reg = <0x00583000 0x70 894 reg = <0x00583000 0x7000>;
895 #interconnect-cells = 895 #interconnect-cells = <1>;
896 clock-names = "aggre2_ 896 clock-names = "aggre2_ufs_axi", "ufs_axi";
897 clocks = <&gcc GCC_AGG 897 clocks = <&gcc GCC_AGGRE2_UFS_AXI_CLK>,
898 <&gcc GCC_UFS 898 <&gcc GCC_UFS_AXI_CLK>;
899 }; 899 };
900 900
901 mnoc: interconnect@5a4000 { 901 mnoc: interconnect@5a4000 {
902 compatible = "qcom,msm 902 compatible = "qcom,msm8996-mnoc";
903 reg = <0x005a4000 0x1c 903 reg = <0x005a4000 0x1c000>;
904 #interconnect-cells = 904 #interconnect-cells = <1>;
905 clock-names = "iface"; 905 clock-names = "iface";
906 clocks = <&mmcc AHB_CL 906 clocks = <&mmcc AHB_CLK_SRC>;
907 }; 907 };
908 908
909 pnoc: interconnect@5c0000 { 909 pnoc: interconnect@5c0000 {
910 compatible = "qcom,msm 910 compatible = "qcom,msm8996-pnoc";
911 reg = <0x005c0000 0x30 911 reg = <0x005c0000 0x3000>;
912 #interconnect-cells = 912 #interconnect-cells = <1>;
913 }; 913 };
914 914
915 tcsr_mutex: hwlock@740000 { 915 tcsr_mutex: hwlock@740000 {
916 compatible = "qcom,tcs 916 compatible = "qcom,tcsr-mutex";
917 reg = <0x00740000 0x20 917 reg = <0x00740000 0x20000>;
918 #hwlock-cells = <1>; 918 #hwlock-cells = <1>;
919 }; 919 };
920 920
921 tcsr_1: syscon@760000 { 921 tcsr_1: syscon@760000 {
922 compatible = "qcom,tcs 922 compatible = "qcom,tcsr-msm8996", "syscon";
923 reg = <0x00760000 0x20 923 reg = <0x00760000 0x20000>;
924 }; 924 };
925 925
926 tcsr_2: syscon@7a0000 { 926 tcsr_2: syscon@7a0000 {
927 compatible = "qcom,tcs 927 compatible = "qcom,tcsr-msm8996", "syscon";
928 reg = <0x007a0000 0x18 928 reg = <0x007a0000 0x18000>;
929 }; 929 };
930 930
931 mmcc: clock-controller@8c0000 931 mmcc: clock-controller@8c0000 {
932 compatible = "qcom,mmc 932 compatible = "qcom,mmcc-msm8996";
933 #clock-cells = <1>; 933 #clock-cells = <1>;
934 #reset-cells = <1>; 934 #reset-cells = <1>;
935 #power-domain-cells = 935 #power-domain-cells = <1>;
936 reg = <0x008c0000 0x40 936 reg = <0x008c0000 0x40000>;
937 clocks = <&xo_board>, 937 clocks = <&xo_board>,
938 <&gcc GPLL0>, 938 <&gcc GPLL0>,
939 <&gcc GCC_MMS 939 <&gcc GCC_MMSS_NOC_CFG_AHB_CLK>,
940 <&mdss_dsi0_p 940 <&mdss_dsi0_phy 1>,
941 <&mdss_dsi0_p 941 <&mdss_dsi0_phy 0>,
942 <&mdss_dsi1_p 942 <&mdss_dsi1_phy 1>,
943 <&mdss_dsi1_p 943 <&mdss_dsi1_phy 0>,
944 <&mdss_hdmi_p 944 <&mdss_hdmi_phy>;
945 clock-names = "xo", 945 clock-names = "xo",
946 "gpll0", 946 "gpll0",
947 "gcc_mms 947 "gcc_mmss_noc_cfg_ahb_clk",
948 "dsi0pll 948 "dsi0pll",
949 "dsi0pll 949 "dsi0pllbyte",
950 "dsi1pll 950 "dsi1pll",
951 "dsi1pll 951 "dsi1pllbyte",
952 "hdmipll 952 "hdmipll";
953 assigned-clocks = <&mm 953 assigned-clocks = <&mmcc MMPLL9_PLL>,
954 <&mm 954 <&mmcc MMPLL1_PLL>,
955 <&mm 955 <&mmcc MMPLL3_PLL>,
956 <&mm 956 <&mmcc MMPLL4_PLL>,
957 <&mm 957 <&mmcc MMPLL5_PLL>;
958 assigned-clock-rates = 958 assigned-clock-rates = <624000000>,
959 959 <810000000>,
960 960 <980000000>,
961 961 <960000000>,
962 962 <825000000>;
963 }; 963 };
964 964
965 mdss: display-subsystem@900000 965 mdss: display-subsystem@900000 {
966 compatible = "qcom,mds 966 compatible = "qcom,mdss";
967 967
968 reg = <0x00900000 0x10 968 reg = <0x00900000 0x1000>,
969 <0x009b0000 0x10 969 <0x009b0000 0x1040>,
970 <0x009b8000 0x10 970 <0x009b8000 0x1040>;
971 reg-names = "mdss_phys 971 reg-names = "mdss_phys",
972 "vbif_phys 972 "vbif_phys",
973 "vbif_nrt_ 973 "vbif_nrt_phys";
974 974
975 power-domains = <&mmcc 975 power-domains = <&mmcc MDSS_GDSC>;
976 interrupts = <GIC_SPI 976 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
977 977
978 interrupt-controller; 978 interrupt-controller;
979 #interrupt-cells = <1> 979 #interrupt-cells = <1>;
980 980
981 clocks = <&mmcc MDSS_A 981 clocks = <&mmcc MDSS_AHB_CLK>,
982 <&mmcc MDSS_M 982 <&mmcc MDSS_MDP_CLK>;
983 clock-names = "iface", 983 clock-names = "iface", "core";
984 984
985 resets = <&mmcc MDSS_B <<
986 <<
987 #address-cells = <1>; 985 #address-cells = <1>;
988 #size-cells = <1>; 986 #size-cells = <1>;
989 ranges; 987 ranges;
990 988
991 status = "disabled"; 989 status = "disabled";
992 990
993 mdp: display-controlle 991 mdp: display-controller@901000 {
994 compatible = " 992 compatible = "qcom,msm8996-mdp5", "qcom,mdp5";
995 reg = <0x00901 993 reg = <0x00901000 0x90000>;
996 reg-names = "m 994 reg-names = "mdp_phys";
997 995
998 interrupt-pare 996 interrupt-parent = <&mdss>;
999 interrupts = < 997 interrupts = <0>;
1000 998
1001 clocks = <&mm 999 clocks = <&mmcc MDSS_AHB_CLK>,
1002 <&mm 1000 <&mmcc MDSS_AXI_CLK>,
1003 <&mm 1001 <&mmcc MDSS_MDP_CLK>,
1004 <&mm 1002 <&mmcc SMMU_MDP_AXI_CLK>,
1005 <&mm 1003 <&mmcc MDSS_VSYNC_CLK>;
1006 clock-names = 1004 clock-names = "iface",
1007 1005 "bus",
1008 1006 "core",
1009 1007 "iommu",
1010 1008 "vsync";
1011 1009
1012 iommus = <&md 1010 iommus = <&mdp_smmu 0>;
1013 1011
1014 assigned-cloc 1012 assigned-clocks = <&mmcc MDSS_MDP_CLK>,
1015 <&mm 1013 <&mmcc MDSS_VSYNC_CLK>;
1016 assigned-cloc 1014 assigned-clock-rates = <300000000>,
1017 <192 1015 <19200000>;
1018 1016
1019 interconnects 1017 interconnects = <&mnoc MASTER_MDP_PORT0 &bimc SLAVE_EBI_CH0>,
1020 1018 <&mnoc MASTER_MDP_PORT1 &bimc SLAVE_EBI_CH0>,
1021 1019 <&mnoc MASTER_ROTATOR &bimc SLAVE_EBI_CH0>;
1022 interconnect- 1020 interconnect-names = "mdp0-mem", "mdp1-mem", "rotator-mem";
1023 1021
1024 ports { 1022 ports {
1025 #addr 1023 #address-cells = <1>;
1026 #size 1024 #size-cells = <0>;
1027 1025
1028 port@ 1026 port@0 {
1029 1027 reg = <0>;
1030 1028 mdp5_intf3_out: endpoint {
1031 1029 remote-endpoint = <&mdss_hdmi_in>;
1032 1030 };
1033 }; 1031 };
1034 1032
1035 port@ 1033 port@1 {
1036 1034 reg = <1>;
1037 1035 mdp5_intf1_out: endpoint {
1038 1036 remote-endpoint = <&mdss_dsi0_in>;
1039 1037 };
1040 }; 1038 };
1041 1039
1042 port@ 1040 port@2 {
1043 1041 reg = <2>;
1044 1042 mdp5_intf2_out: endpoint {
1045 1043 remote-endpoint = <&mdss_dsi1_in>;
1046 1044 };
1047 }; 1045 };
1048 }; 1046 };
1049 }; 1047 };
1050 1048
1051 mdss_dsi0: dsi@994000 1049 mdss_dsi0: dsi@994000 {
1052 compatible = 1050 compatible = "qcom,msm8996-dsi-ctrl",
1053 1051 "qcom,mdss-dsi-ctrl";
1054 reg = <0x0099 1052 reg = <0x00994000 0x400>;
1055 reg-names = " 1053 reg-names = "dsi_ctrl";
1056 1054
1057 interrupt-par 1055 interrupt-parent = <&mdss>;
1058 interrupts = 1056 interrupts = <4>;
1059 1057
1060 clocks = <&mm 1058 clocks = <&mmcc MDSS_MDP_CLK>,
1061 <&mm 1059 <&mmcc MDSS_BYTE0_CLK>,
1062 <&mm 1060 <&mmcc MDSS_AHB_CLK>,
1063 <&mm 1061 <&mmcc MDSS_AXI_CLK>,
1064 <&mm 1062 <&mmcc MMSS_MISC_AHB_CLK>,
1065 <&mm 1063 <&mmcc MDSS_PCLK0_CLK>,
1066 <&mm 1064 <&mmcc MDSS_ESC0_CLK>;
1067 clock-names = 1065 clock-names = "mdp_core",
1068 1066 "byte",
1069 1067 "iface",
1070 1068 "bus",
1071 1069 "core_mmss",
1072 1070 "pixel",
1073 1071 "core";
1074 assigned-cloc 1072 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>;
1075 assigned-cloc 1073 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
1076 1074
1077 phys = <&mdss 1075 phys = <&mdss_dsi0_phy>;
1078 status = "dis 1076 status = "disabled";
1079 1077
1080 #address-cell 1078 #address-cells = <1>;
1081 #size-cells = 1079 #size-cells = <0>;
1082 1080
1083 ports { 1081 ports {
1084 #addr 1082 #address-cells = <1>;
1085 #size 1083 #size-cells = <0>;
1086 1084
1087 port@ 1085 port@0 {
1088 1086 reg = <0>;
1089 1087 mdss_dsi0_in: endpoint {
1090 1088 remote-endpoint = <&mdp5_intf1_out>;
1091 1089 };
1092 }; 1090 };
1093 1091
1094 port@ 1092 port@1 {
1095 1093 reg = <1>;
1096 1094 mdss_dsi0_out: endpoint {
1097 1095 };
1098 }; 1096 };
1099 }; 1097 };
1100 }; 1098 };
1101 1099
1102 mdss_dsi0_phy: phy@99 1100 mdss_dsi0_phy: phy@994400 {
1103 compatible = 1101 compatible = "qcom,dsi-phy-14nm";
1104 reg = <0x0099 1102 reg = <0x00994400 0x100>,
1105 <0x0099 1103 <0x00994500 0x300>,
1106 <0x0099 1104 <0x00994800 0x188>;
1107 reg-names = " 1105 reg-names = "dsi_phy",
1108 " 1106 "dsi_phy_lane",
1109 " 1107 "dsi_pll";
1110 1108
1111 #clock-cells 1109 #clock-cells = <1>;
1112 #phy-cells = 1110 #phy-cells = <0>;
1113 1111
1114 clocks = <&mm 1112 clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
1115 clock-names = 1113 clock-names = "iface", "ref";
1116 status = "dis 1114 status = "disabled";
1117 }; 1115 };
1118 1116
1119 mdss_dsi1: dsi@996000 1117 mdss_dsi1: dsi@996000 {
1120 compatible = 1118 compatible = "qcom,msm8996-dsi-ctrl",
1121 1119 "qcom,mdss-dsi-ctrl";
1122 reg = <0x0099 1120 reg = <0x00996000 0x400>;
1123 reg-names = " 1121 reg-names = "dsi_ctrl";
1124 1122
1125 interrupt-par 1123 interrupt-parent = <&mdss>;
1126 interrupts = 1124 interrupts = <5>;
1127 1125
1128 clocks = <&mm 1126 clocks = <&mmcc MDSS_MDP_CLK>,
1129 <&mm 1127 <&mmcc MDSS_BYTE1_CLK>,
1130 <&mm 1128 <&mmcc MDSS_AHB_CLK>,
1131 <&mm 1129 <&mmcc MDSS_AXI_CLK>,
1132 <&mm 1130 <&mmcc MMSS_MISC_AHB_CLK>,
1133 <&mm 1131 <&mmcc MDSS_PCLK1_CLK>,
1134 <&mm 1132 <&mmcc MDSS_ESC1_CLK>;
1135 clock-names = 1133 clock-names = "mdp_core",
1136 1134 "byte",
1137 1135 "iface",
1138 1136 "bus",
1139 1137 "core_mmss",
1140 1138 "pixel",
1141 1139 "core";
1142 assigned-cloc 1140 assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>;
1143 assigned-cloc 1141 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
1144 1142
1145 phys = <&mdss 1143 phys = <&mdss_dsi1_phy>;
1146 status = "dis 1144 status = "disabled";
1147 1145
1148 #address-cell 1146 #address-cells = <1>;
1149 #size-cells = 1147 #size-cells = <0>;
1150 1148
1151 ports { 1149 ports {
1152 #addr 1150 #address-cells = <1>;
1153 #size 1151 #size-cells = <0>;
1154 1152
1155 port@ 1153 port@0 {
1156 1154 reg = <0>;
1157 1155 mdss_dsi1_in: endpoint {
1158 1156 remote-endpoint = <&mdp5_intf2_out>;
1159 1157 };
1160 }; 1158 };
1161 1159
1162 port@ 1160 port@1 {
1163 1161 reg = <1>;
1164 1162 mdss_dsi1_out: endpoint {
1165 1163 };
1166 }; 1164 };
1167 }; 1165 };
1168 }; 1166 };
1169 1167
1170 mdss_dsi1_phy: phy@99 1168 mdss_dsi1_phy: phy@996400 {
1171 compatible = 1169 compatible = "qcom,dsi-phy-14nm";
1172 reg = <0x0099 1170 reg = <0x00996400 0x100>,
1173 <0x0099 1171 <0x00996500 0x300>,
1174 <0x0099 1172 <0x00996800 0x188>;
1175 reg-names = " 1173 reg-names = "dsi_phy",
1176 " 1174 "dsi_phy_lane",
1177 " 1175 "dsi_pll";
1178 1176
1179 #clock-cells 1177 #clock-cells = <1>;
1180 #phy-cells = 1178 #phy-cells = <0>;
1181 1179
1182 clocks = <&mm 1180 clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
1183 clock-names = 1181 clock-names = "iface", "ref";
1184 status = "dis 1182 status = "disabled";
1185 }; 1183 };
1186 1184
1187 mdss_hdmi: hdmi-tx@9a 1185 mdss_hdmi: hdmi-tx@9a0000 {
1188 compatible = 1186 compatible = "qcom,hdmi-tx-8996";
1189 reg = <0x009a 1187 reg = <0x009a0000 0x50c>,
1190 <0x0007 1188 <0x00070000 0x6158>,
1191 <0x009e 1189 <0x009e0000 0xfff>;
1192 reg-names = " 1190 reg-names = "core_physical",
1193 " 1191 "qfprom_physical",
1194 " 1192 "hdcp_physical";
1195 1193
1196 interrupt-par 1194 interrupt-parent = <&mdss>;
1197 interrupts = 1195 interrupts = <8>;
1198 1196
1199 clocks = <&mm 1197 clocks = <&mmcc MDSS_MDP_CLK>,
1200 <&mm 1198 <&mmcc MDSS_AHB_CLK>,
1201 <&mm 1199 <&mmcc MDSS_HDMI_CLK>,
1202 <&mm 1200 <&mmcc MDSS_HDMI_AHB_CLK>,
1203 <&mm 1201 <&mmcc MDSS_EXTPCLK_CLK>;
1204 clock-names = 1202 clock-names =
1205 "mdp_ 1203 "mdp_core",
1206 "ifac 1204 "iface",
1207 "core 1205 "core",
1208 "alt_ 1206 "alt_iface",
1209 "extp 1207 "extp";
1210 1208
1211 phys = <&mdss 1209 phys = <&mdss_hdmi_phy>;
1212 #sound-dai-ce 1210 #sound-dai-cells = <1>;
1213 1211
1214 status = "dis 1212 status = "disabled";
1215 1213
1216 ports { 1214 ports {
1217 #addr 1215 #address-cells = <1>;
1218 #size 1216 #size-cells = <0>;
1219 1217
1220 port@ 1218 port@0 {
1221 1219 reg = <0>;
1222 1220 mdss_hdmi_in: endpoint {
1223 1221 remote-endpoint = <&mdp5_intf3_out>;
1224 1222 };
1225 }; 1223 };
1226 }; 1224 };
1227 }; 1225 };
1228 1226
1229 mdss_hdmi_phy: phy@9a 1227 mdss_hdmi_phy: phy@9a0600 {
1230 #phy-cells = 1228 #phy-cells = <0>;
1231 compatible = 1229 compatible = "qcom,hdmi-phy-8996";
1232 reg = <0x009a 1230 reg = <0x009a0600 0x1c4>,
1233 <0x009a 1231 <0x009a0a00 0x124>,
1234 <0x009a 1232 <0x009a0c00 0x124>,
1235 <0x009a 1233 <0x009a0e00 0x124>,
1236 <0x009a 1234 <0x009a1000 0x124>,
1237 <0x009a 1235 <0x009a1200 0x0c8>;
1238 reg-names = " 1236 reg-names = "hdmi_pll",
1239 " 1237 "hdmi_tx_l0",
1240 " 1238 "hdmi_tx_l1",
1241 " 1239 "hdmi_tx_l2",
1242 " 1240 "hdmi_tx_l3",
1243 " 1241 "hdmi_phy";
1244 1242
1245 clocks = <&mm 1243 clocks = <&mmcc MDSS_AHB_CLK>,
1246 <&gc 1244 <&gcc GCC_HDMI_CLKREF_CLK>,
1247 <&xo 1245 <&xo_board>;
1248 clock-names = 1246 clock-names = "iface",
1249 1247 "ref",
1250 1248 "xo";
1251 1249
1252 #clock-cells 1250 #clock-cells = <0>;
1253 1251
1254 status = "dis 1252 status = "disabled";
1255 }; 1253 };
1256 }; 1254 };
1257 1255
1258 gpu: gpu@b00000 { 1256 gpu: gpu@b00000 {
1259 compatible = "qcom,ad 1257 compatible = "qcom,adreno-530.2", "qcom,adreno";
1260 1258
1261 reg = <0x00b00000 0x3 1259 reg = <0x00b00000 0x3f000>;
1262 reg-names = "kgsl_3d0 1260 reg-names = "kgsl_3d0_reg_memory";
1263 1261
1264 interrupts = <GIC_SPI 1262 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
1265 1263
1266 clocks = <&mmcc GPU_G 1264 clocks = <&mmcc GPU_GX_GFX3D_CLK>,
1267 <&mmcc GPU_AH 1265 <&mmcc GPU_AHB_CLK>,
1268 <&mmcc GPU_GX 1266 <&mmcc GPU_GX_RBBMTIMER_CLK>,
1269 <&gcc GCC_BIM 1267 <&gcc GCC_BIMC_GFX_CLK>,
1270 <&gcc GCC_MMS 1268 <&gcc GCC_MMSS_BIMC_GFX_CLK>;
1271 1269
1272 clock-names = "core", 1270 clock-names = "core",
1273 "iface", 1271 "iface",
1274 "rbbmtimer", 1272 "rbbmtimer",
1275 "mem", 1273 "mem",
1276 "mem_iface"; 1274 "mem_iface";
1277 1275
1278 interconnects = <&bim 1276 interconnects = <&bimc MASTER_GRAPHICS_3D &bimc SLAVE_EBI_CH0>;
1279 interconnect-names = 1277 interconnect-names = "gfx-mem";
1280 1278
1281 power-domains = <&mmc 1279 power-domains = <&mmcc GPU_GX_GDSC>;
1282 iommus = <&adreno_smm 1280 iommus = <&adreno_smmu 0>;
1283 1281
1284 nvmem-cells = <&speed 1282 nvmem-cells = <&speedbin_efuse>;
1285 nvmem-cell-names = "s 1283 nvmem-cell-names = "speed_bin";
1286 1284
1287 operating-points-v2 = 1285 operating-points-v2 = <&gpu_opp_table>;
1288 1286
1289 status = "disabled"; 1287 status = "disabled";
1290 1288
1291 #cooling-cells = <2>; 1289 #cooling-cells = <2>;
1292 1290
1293 gpu_opp_table: opp-ta 1291 gpu_opp_table: opp-table {
1294 compatible = 1292 compatible = "operating-points-v2";
1295 1293
1296 /* 1294 /*
1297 * 624Mhz is 1295 * 624Mhz is only available on speed bins 0 and 3.
1298 * 560Mhz is 1296 * 560Mhz is only available on speed bins 0, 2 and 3.
1299 * All the re 1297 * All the rest are available on all bins of the hardware.
1300 */ 1298 */
1301 opp-624000000 1299 opp-624000000 {
1302 opp-h 1300 opp-hz = /bits/ 64 <624000000>;
1303 opp-s 1301 opp-supported-hw = <0x09>;
1304 }; 1302 };
1305 opp-560000000 1303 opp-560000000 {
1306 opp-h 1304 opp-hz = /bits/ 64 <560000000>;
1307 opp-s 1305 opp-supported-hw = <0x0d>;
1308 }; 1306 };
1309 opp-510000000 1307 opp-510000000 {
1310 opp-h 1308 opp-hz = /bits/ 64 <510000000>;
1311 opp-s 1309 opp-supported-hw = <0xff>;
1312 }; 1310 };
1313 opp-401800000 1311 opp-401800000 {
1314 opp-h 1312 opp-hz = /bits/ 64 <401800000>;
1315 opp-s 1313 opp-supported-hw = <0xff>;
1316 }; 1314 };
1317 opp-315000000 1315 opp-315000000 {
1318 opp-h 1316 opp-hz = /bits/ 64 <315000000>;
1319 opp-s 1317 opp-supported-hw = <0xff>;
1320 }; 1318 };
1321 opp-214000000 1319 opp-214000000 {
1322 opp-h 1320 opp-hz = /bits/ 64 <214000000>;
1323 opp-s 1321 opp-supported-hw = <0xff>;
1324 }; 1322 };
1325 opp-133000000 1323 opp-133000000 {
1326 opp-h 1324 opp-hz = /bits/ 64 <133000000>;
1327 opp-s 1325 opp-supported-hw = <0xff>;
1328 }; 1326 };
1329 }; 1327 };
1330 1328
1331 zap-shader { 1329 zap-shader {
1332 memory-region 1330 memory-region = <&gpu_mem>;
1333 }; 1331 };
1334 }; 1332 };
1335 1333
1336 tlmm: pinctrl@1010000 { 1334 tlmm: pinctrl@1010000 {
1337 compatible = "qcom,ms 1335 compatible = "qcom,msm8996-pinctrl";
1338 reg = <0x01010000 0x3 1336 reg = <0x01010000 0x300000>;
1339 interrupts = <GIC_SPI 1337 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1340 gpio-controller; 1338 gpio-controller;
1341 gpio-ranges = <&tlmm 1339 gpio-ranges = <&tlmm 0 0 150>;
1342 #gpio-cells = <2>; 1340 #gpio-cells = <2>;
1343 interrupt-controller; 1341 interrupt-controller;
1344 #interrupt-cells = <2 1342 #interrupt-cells = <2>;
1345 1343
1346 blsp1_spi1_default: b 1344 blsp1_spi1_default: blsp1-spi1-default-state {
1347 spi-pins { 1345 spi-pins {
1348 pins 1346 pins = "gpio0", "gpio1", "gpio3";
1349 funct 1347 function = "blsp_spi1";
1350 drive 1348 drive-strength = <12>;
1351 bias- 1349 bias-disable;
1352 }; 1350 };
1353 1351
1354 cs-pins { 1352 cs-pins {
1355 pins 1353 pins = "gpio2";
1356 funct 1354 function = "gpio";
1357 drive 1355 drive-strength = <16>;
1358 bias- 1356 bias-disable;
1359 outpu 1357 output-high;
1360 }; 1358 };
1361 }; 1359 };
1362 1360
1363 blsp1_spi1_sleep: bls 1361 blsp1_spi1_sleep: blsp1-spi1-sleep-state {
1364 pins = "gpio0 1362 pins = "gpio0", "gpio1", "gpio2", "gpio3";
1365 function = "g 1363 function = "gpio";
1366 drive-strengt 1364 drive-strength = <2>;
1367 bias-pull-dow 1365 bias-pull-down;
1368 }; 1366 };
1369 1367
1370 blsp2_uart2_2pins_def 1368 blsp2_uart2_2pins_default: blsp2-uart2-2pins-state {
1371 pins = "gpio4 1369 pins = "gpio4", "gpio5";
1372 function = "b 1370 function = "blsp_uart8";
1373 drive-strengt 1371 drive-strength = <16>;
1374 bias-disable; 1372 bias-disable;
1375 }; 1373 };
1376 1374
1377 blsp2_uart2_2pins_sle 1375 blsp2_uart2_2pins_sleep: blsp2-uart2-2pins-sleep-state {
1378 pins = "gpio4 1376 pins = "gpio4", "gpio5";
1379 function = "g 1377 function = "gpio";
1380 drive-strengt 1378 drive-strength = <2>;
1381 bias-disable; 1379 bias-disable;
1382 }; 1380 };
1383 1381
1384 blsp2_i2c2_default: b 1382 blsp2_i2c2_default: blsp2-i2c2-state {
1385 pins = "gpio6 1383 pins = "gpio6", "gpio7";
1386 function = "b 1384 function = "blsp_i2c8";
1387 drive-strengt 1385 drive-strength = <16>;
1388 bias-disable; 1386 bias-disable;
1389 }; 1387 };
1390 1388
1391 blsp2_i2c2_sleep: bls 1389 blsp2_i2c2_sleep: blsp2-i2c2-sleep-state {
1392 pins = "gpio6 1390 pins = "gpio6", "gpio7";
1393 function = "g 1391 function = "gpio";
1394 drive-strengt 1392 drive-strength = <2>;
1395 bias-disable; 1393 bias-disable;
1396 }; 1394 };
1397 1395
1398 blsp1_i2c6_default: b 1396 blsp1_i2c6_default: blsp1-i2c6-state {
1399 pins = "gpio2 1397 pins = "gpio27", "gpio28";
1400 function = "b 1398 function = "blsp_i2c6";
1401 drive-strengt 1399 drive-strength = <16>;
1402 bias-disable; 1400 bias-disable;
1403 }; 1401 };
1404 1402
1405 blsp1_i2c6_sleep: bls 1403 blsp1_i2c6_sleep: blsp1-i2c6-sleep-state {
1406 pins = "gpio2 1404 pins = "gpio27", "gpio28";
1407 function = "g 1405 function = "gpio";
1408 drive-strengt 1406 drive-strength = <2>;
1409 bias-pull-up; 1407 bias-pull-up;
1410 }; 1408 };
1411 1409
1412 cci0_default: cci0-de 1410 cci0_default: cci0-default-state {
1413 pins = "gpio1 1411 pins = "gpio17", "gpio18";
1414 function = "c 1412 function = "cci_i2c";
1415 drive-strengt 1413 drive-strength = <16>;
1416 bias-disable; 1414 bias-disable;
1417 }; 1415 };
1418 1416
1419 camera0_state_on: 1417 camera0_state_on:
1420 camera_rear_default: 1418 camera_rear_default: camera-rear-default-state {
1421 camera0_mclk: 1419 camera0_mclk: mclk0-pins {
1422 pins 1420 pins = "gpio13";
1423 funct 1421 function = "cam_mclk";
1424 drive 1422 drive-strength = <16>;
1425 bias- 1423 bias-disable;
1426 }; 1424 };
1427 1425
1428 camera0_rst: 1426 camera0_rst: rst-pins {
1429 pins 1427 pins = "gpio25";
1430 funct 1428 function = "gpio";
1431 drive 1429 drive-strength = <16>;
1432 bias- 1430 bias-disable;
1433 }; 1431 };
1434 1432
1435 camera0_pwdn: 1433 camera0_pwdn: pwdn-pins {
1436 pins 1434 pins = "gpio26";
1437 funct 1435 function = "gpio";
1438 drive 1436 drive-strength = <16>;
1439 bias- 1437 bias-disable;
1440 }; 1438 };
1441 }; 1439 };
1442 1440
1443 cci1_default: cci1-de 1441 cci1_default: cci1-default-state {
1444 pins = "gpio1 1442 pins = "gpio19", "gpio20";
1445 function = "c 1443 function = "cci_i2c";
1446 drive-strengt 1444 drive-strength = <16>;
1447 bias-disable; 1445 bias-disable;
1448 }; 1446 };
1449 1447
1450 camera1_state_on: 1448 camera1_state_on:
1451 camera_board_default: 1449 camera_board_default: camera-board-default-state {
1452 mclk1-pins { 1450 mclk1-pins {
1453 pins 1451 pins = "gpio14";
1454 funct 1452 function = "cam_mclk";
1455 drive 1453 drive-strength = <16>;
1456 bias- 1454 bias-disable;
1457 }; 1455 };
1458 1456
1459 pwdn-pins { 1457 pwdn-pins {
1460 pins 1458 pins = "gpio98";
1461 funct 1459 function = "gpio";
1462 drive 1460 drive-strength = <16>;
1463 bias- 1461 bias-disable;
1464 }; 1462 };
1465 1463
1466 rst-pins { 1464 rst-pins {
1467 pins 1465 pins = "gpio104";
1468 funct 1466 function = "gpio";
1469 drive 1467 drive-strength = <16>;
1470 bias- 1468 bias-disable;
1471 }; 1469 };
1472 }; 1470 };
1473 1471
1474 camera2_state_on: 1472 camera2_state_on:
1475 camera_front_default: 1473 camera_front_default: camera-front-default-state {
1476 camera2_mclk: 1474 camera2_mclk: mclk2-pins {
1477 pins 1475 pins = "gpio15";
1478 funct 1476 function = "cam_mclk";
1479 drive 1477 drive-strength = <16>;
1480 bias- 1478 bias-disable;
1481 }; 1479 };
1482 1480
1483 camera2_rst: 1481 camera2_rst: rst-pins {
1484 pins 1482 pins = "gpio23";
1485 funct 1483 function = "gpio";
1486 drive 1484 drive-strength = <16>;
1487 bias- 1485 bias-disable;
1488 }; 1486 };
1489 1487
1490 pwdn-pins { 1488 pwdn-pins {
1491 pins 1489 pins = "gpio133";
1492 funct 1490 function = "gpio";
1493 drive 1491 drive-strength = <16>;
1494 bias- 1492 bias-disable;
1495 }; 1493 };
1496 }; 1494 };
1497 1495
1498 pcie0_state_on: pcie0 1496 pcie0_state_on: pcie0-state-on-state {
1499 perst-pins { 1497 perst-pins {
1500 pins 1498 pins = "gpio35";
1501 funct 1499 function = "gpio";
1502 drive 1500 drive-strength = <2>;
1503 bias- 1501 bias-pull-down;
1504 }; 1502 };
1505 1503
1506 clkreq-pins { 1504 clkreq-pins {
1507 pins 1505 pins = "gpio36";
1508 funct 1506 function = "pci_e0";
1509 drive 1507 drive-strength = <2>;
1510 bias- 1508 bias-pull-up;
1511 }; 1509 };
1512 1510
1513 wake-pins { 1511 wake-pins {
1514 pins 1512 pins = "gpio37";
1515 funct 1513 function = "gpio";
1516 drive 1514 drive-strength = <2>;
1517 bias- 1515 bias-pull-up;
1518 }; 1516 };
1519 }; 1517 };
1520 1518
1521 pcie0_state_off: pcie 1519 pcie0_state_off: pcie0-state-off-state {
1522 perst-pins { 1520 perst-pins {
1523 pins 1521 pins = "gpio35";
1524 funct 1522 function = "gpio";
1525 drive 1523 drive-strength = <2>;
1526 bias- 1524 bias-pull-down;
1527 }; 1525 };
1528 1526
1529 clkreq-pins { 1527 clkreq-pins {
1530 pins 1528 pins = "gpio36";
1531 funct 1529 function = "gpio";
1532 drive 1530 drive-strength = <2>;
1533 bias- 1531 bias-disable;
1534 }; 1532 };
1535 1533
1536 wake-pins { 1534 wake-pins {
1537 pins 1535 pins = "gpio37";
1538 funct 1536 function = "gpio";
1539 drive 1537 drive-strength = <2>;
1540 bias- 1538 bias-disable;
1541 }; 1539 };
1542 }; 1540 };
1543 1541
1544 blsp1_uart2_default: 1542 blsp1_uart2_default: blsp1-uart2-default-state {
1545 pins = "gpio4 1543 pins = "gpio41", "gpio42", "gpio43", "gpio44";
1546 function = "b 1544 function = "blsp_uart2";
1547 drive-strengt 1545 drive-strength = <16>;
1548 bias-disable; 1546 bias-disable;
1549 }; 1547 };
1550 1548
1551 blsp1_uart2_sleep: bl 1549 blsp1_uart2_sleep: blsp1-uart2-sleep-state {
1552 pins = "gpio4 1550 pins = "gpio41", "gpio42", "gpio43", "gpio44";
1553 function = "g 1551 function = "gpio";
1554 drive-strengt 1552 drive-strength = <2>;
1555 bias-disable; 1553 bias-disable;
1556 }; 1554 };
1557 1555
1558 blsp1_i2c3_default: b 1556 blsp1_i2c3_default: blsp1-i2c3-default-state {
1559 pins = "gpio4 1557 pins = "gpio47", "gpio48";
1560 function = "b 1558 function = "blsp_i2c3";
1561 drive-strengt 1559 drive-strength = <16>;
1562 bias-disable; 1560 bias-disable;
1563 }; 1561 };
1564 1562
1565 blsp1_i2c3_sleep: bls 1563 blsp1_i2c3_sleep: blsp1-i2c3-sleep-state {
1566 pins = "gpio4 1564 pins = "gpio47", "gpio48";
1567 function = "g 1565 function = "gpio";
1568 drive-strengt 1566 drive-strength = <2>;
1569 bias-disable; 1567 bias-disable;
1570 }; 1568 };
1571 1569
1572 blsp2_uart3_4pins_def 1570 blsp2_uart3_4pins_default: blsp2-uart3-4pins-state {
1573 pins = "gpio4 1571 pins = "gpio49", "gpio50", "gpio51", "gpio52";
1574 function = "b 1572 function = "blsp_uart9";
1575 drive-strengt 1573 drive-strength = <16>;
1576 bias-disable; 1574 bias-disable;
1577 }; 1575 };
1578 1576
1579 blsp2_uart3_4pins_sle 1577 blsp2_uart3_4pins_sleep: blsp2-uart3-4pins-sleep-state {
1580 pins = "gpio4 1578 pins = "gpio49", "gpio50", "gpio51", "gpio52";
1581 function = "b 1579 function = "blsp_uart9";
1582 drive-strengt 1580 drive-strength = <2>;
1583 bias-disable; 1581 bias-disable;
1584 }; 1582 };
1585 1583
1586 blsp2_i2c3_default: b 1584 blsp2_i2c3_default: blsp2-i2c3-state-state {
1587 pins = "gpio5 1585 pins = "gpio51", "gpio52";
1588 function = "b 1586 function = "blsp_i2c9";
1589 drive-strengt 1587 drive-strength = <16>;
1590 bias-disable; 1588 bias-disable;
1591 }; 1589 };
1592 1590
1593 blsp2_i2c3_sleep: bls 1591 blsp2_i2c3_sleep: blsp2-i2c3-sleep-state {
1594 pins = "gpio5 1592 pins = "gpio51", "gpio52";
1595 function = "g 1593 function = "gpio";
1596 drive-strengt 1594 drive-strength = <2>;
1597 bias-disable; 1595 bias-disable;
1598 }; 1596 };
1599 1597
1600 wcd_intr_default: wcd 1598 wcd_intr_default: wcd-intr-default-state {
1601 pins = "gpio5 1599 pins = "gpio54";
1602 function = "g 1600 function = "gpio";
1603 drive-strengt 1601 drive-strength = <2>;
1604 bias-pull-dow 1602 bias-pull-down;
1605 }; 1603 };
1606 1604
1607 blsp2_i2c1_default: b 1605 blsp2_i2c1_default: blsp2-i2c1-state {
1608 pins = "gpio5 1606 pins = "gpio55", "gpio56";
1609 function = "b 1607 function = "blsp_i2c7";
1610 drive-strengt 1608 drive-strength = <16>;
1611 bias-disable; 1609 bias-disable;
1612 }; 1610 };
1613 1611
1614 blsp2_i2c1_sleep: bls 1612 blsp2_i2c1_sleep: blsp2-i2c1-sleep-state {
1615 pins = "gpio5 1613 pins = "gpio55", "gpio56";
1616 function = "g 1614 function = "gpio";
1617 drive-strengt 1615 drive-strength = <2>;
1618 bias-disable; 1616 bias-disable;
1619 }; 1617 };
1620 1618
1621 blsp2_i2c5_default: b 1619 blsp2_i2c5_default: blsp2-i2c5-state {
1622 pins = "gpio6 1620 pins = "gpio60", "gpio61";
1623 function = "b 1621 function = "blsp_i2c11";
1624 drive-strengt 1622 drive-strength = <2>;
1625 bias-disable; 1623 bias-disable;
1626 }; 1624 };
1627 1625
1628 /* Sleep state for BL 1626 /* Sleep state for BLSP2_I2C5 is missing.. */
1629 1627
1630 cdc_reset_active: cdc 1628 cdc_reset_active: cdc-reset-active-state {
1631 pins = "gpio6 1629 pins = "gpio64";
1632 function = "g 1630 function = "gpio";
1633 drive-strengt 1631 drive-strength = <16>;
1634 bias-pull-dow 1632 bias-pull-down;
1635 output-high; 1633 output-high;
1636 }; 1634 };
1637 1635
1638 cdc_reset_sleep: cdc- 1636 cdc_reset_sleep: cdc-reset-sleep-state {
1639 pins = "gpio6 1637 pins = "gpio64";
1640 function = "g 1638 function = "gpio";
1641 drive-strengt 1639 drive-strength = <16>;
1642 bias-disable; 1640 bias-disable;
1643 output-low; 1641 output-low;
1644 }; 1642 };
1645 1643
1646 blsp2_spi6_default: b 1644 blsp2_spi6_default: blsp2-spi6-default-state {
1647 spi-pins { 1645 spi-pins {
1648 pins 1646 pins = "gpio85", "gpio86", "gpio88";
1649 funct 1647 function = "blsp_spi12";
1650 drive 1648 drive-strength = <12>;
1651 bias- 1649 bias-disable;
1652 }; 1650 };
1653 1651
1654 cs-pins { 1652 cs-pins {
1655 pins 1653 pins = "gpio87";
1656 funct 1654 function = "gpio";
1657 drive 1655 drive-strength = <16>;
1658 bias- 1656 bias-disable;
1659 outpu 1657 output-high;
1660 }; 1658 };
1661 }; 1659 };
1662 1660
1663 blsp2_spi6_sleep: bls 1661 blsp2_spi6_sleep: blsp2-spi6-sleep-state {
1664 pins = "gpio8 1662 pins = "gpio85", "gpio86", "gpio87", "gpio88";
1665 function = "g 1663 function = "gpio";
1666 drive-strengt 1664 drive-strength = <2>;
1667 bias-pull-dow 1665 bias-pull-down;
1668 }; 1666 };
1669 1667
1670 blsp2_i2c6_default: b 1668 blsp2_i2c6_default: blsp2-i2c6-state {
1671 pins = "gpio8 1669 pins = "gpio87", "gpio88";
1672 function = "b 1670 function = "blsp_i2c12";
1673 drive-strengt 1671 drive-strength = <16>;
1674 bias-disable; 1672 bias-disable;
1675 }; 1673 };
1676 1674
1677 blsp2_i2c6_sleep: bls 1675 blsp2_i2c6_sleep: blsp2-i2c6-sleep-state {
1678 pins = "gpio8 1676 pins = "gpio87", "gpio88";
1679 function = "g 1677 function = "gpio";
1680 drive-strengt 1678 drive-strength = <2>;
1681 bias-disable; 1679 bias-disable;
1682 }; 1680 };
1683 1681
1684 pcie1_state_on: pcie1 1682 pcie1_state_on: pcie1-on-state {
1685 perst-pins { 1683 perst-pins {
1686 pins 1684 pins = "gpio130";
1687 funct 1685 function = "gpio";
1688 drive 1686 drive-strength = <2>;
1689 bias- 1687 bias-pull-down;
1690 }; 1688 };
1691 1689
1692 clkreq-pins { 1690 clkreq-pins {
1693 pins 1691 pins = "gpio131";
1694 funct 1692 function = "pci_e1";
1695 drive 1693 drive-strength = <2>;
1696 bias- 1694 bias-pull-up;
1697 }; 1695 };
1698 1696
1699 wake-pins { 1697 wake-pins {
1700 pins 1698 pins = "gpio132";
1701 funct 1699 function = "gpio";
1702 drive 1700 drive-strength = <2>;
1703 bias- 1701 bias-pull-down;
1704 }; 1702 };
1705 }; 1703 };
1706 1704
1707 pcie1_state_off: pcie 1705 pcie1_state_off: pcie1-off-state {
1708 /* Perst is m 1706 /* Perst is missing? */
1709 clkreq-pins { 1707 clkreq-pins {
1710 pins 1708 pins = "gpio131";
1711 funct 1709 function = "gpio";
1712 drive 1710 drive-strength = <2>;
1713 bias- 1711 bias-disable;
1714 }; 1712 };
1715 1713
1716 wake-pins { 1714 wake-pins {
1717 pins 1715 pins = "gpio132";
1718 funct 1716 function = "gpio";
1719 drive 1717 drive-strength = <2>;
1720 bias- 1718 bias-disable;
1721 }; 1719 };
1722 }; 1720 };
1723 1721
1724 pcie2_state_on: pcie2 1722 pcie2_state_on: pcie2-on-state {
1725 perst-pins { 1723 perst-pins {
1726 pins 1724 pins = "gpio114";
1727 funct 1725 function = "gpio";
1728 drive 1726 drive-strength = <2>;
1729 bias- 1727 bias-pull-down;
1730 }; 1728 };
1731 1729
1732 clkreq-pins { 1730 clkreq-pins {
1733 pins 1731 pins = "gpio115";
1734 funct 1732 function = "pci_e2";
1735 drive 1733 drive-strength = <2>;
1736 bias- 1734 bias-pull-up;
1737 }; 1735 };
1738 1736
1739 wake-pins { 1737 wake-pins {
1740 pins 1738 pins = "gpio116";
1741 funct 1739 function = "gpio";
1742 drive 1740 drive-strength = <2>;
1743 bias- 1741 bias-pull-down;
1744 }; 1742 };
1745 }; 1743 };
1746 1744
1747 pcie2_state_off: pcie 1745 pcie2_state_off: pcie2-off-state {
1748 /* Perst is m 1746 /* Perst is missing? */
1749 clkreq-pins { 1747 clkreq-pins {
1750 pins 1748 pins = "gpio115";
1751 funct 1749 function = "gpio";
1752 drive 1750 drive-strength = <2>;
1753 bias- 1751 bias-disable;
1754 }; 1752 };
1755 1753
1756 wake-pins { 1754 wake-pins {
1757 pins 1755 pins = "gpio116";
1758 funct 1756 function = "gpio";
1759 drive 1757 drive-strength = <2>;
1760 bias- 1758 bias-disable;
1761 }; 1759 };
1762 }; 1760 };
1763 1761
1764 sdc1_state_on: sdc1-o 1762 sdc1_state_on: sdc1-on-state {
1765 clk-pins { 1763 clk-pins {
1766 pins 1764 pins = "sdc1_clk";
1767 bias- 1765 bias-disable;
1768 drive 1766 drive-strength = <16>;
1769 }; 1767 };
1770 1768
1771 cmd-pins { 1769 cmd-pins {
1772 pins 1770 pins = "sdc1_cmd";
1773 bias- 1771 bias-pull-up;
1774 drive 1772 drive-strength = <10>;
1775 }; 1773 };
1776 1774
1777 data-pins { 1775 data-pins {
1778 pins 1776 pins = "sdc1_data";
1779 bias- 1777 bias-pull-up;
1780 drive 1778 drive-strength = <10>;
1781 }; 1779 };
1782 1780
1783 rclk-pins { 1781 rclk-pins {
1784 pins 1782 pins = "sdc1_rclk";
1785 bias- 1783 bias-pull-down;
1786 }; 1784 };
1787 }; 1785 };
1788 1786
1789 sdc1_state_off: sdc1- 1787 sdc1_state_off: sdc1-off-state {
1790 clk-pins { 1788 clk-pins {
1791 pins 1789 pins = "sdc1_clk";
1792 bias- 1790 bias-disable;
1793 drive 1791 drive-strength = <2>;
1794 }; 1792 };
1795 1793
1796 cmd-pins { 1794 cmd-pins {
1797 pins 1795 pins = "sdc1_cmd";
1798 bias- 1796 bias-pull-up;
1799 drive 1797 drive-strength = <2>;
1800 }; 1798 };
1801 1799
1802 data-pins { 1800 data-pins {
1803 pins 1801 pins = "sdc1_data";
1804 bias- 1802 bias-pull-up;
1805 drive 1803 drive-strength = <2>;
1806 }; 1804 };
1807 1805
1808 rclk-pins { 1806 rclk-pins {
1809 pins 1807 pins = "sdc1_rclk";
1810 bias- 1808 bias-pull-down;
1811 }; 1809 };
1812 }; 1810 };
1813 1811
1814 sdc2_state_on: sdc2-o 1812 sdc2_state_on: sdc2-on-state {
1815 clk-pins { 1813 clk-pins {
1816 pins 1814 pins = "sdc2_clk";
1817 bias- 1815 bias-disable;
1818 drive 1816 drive-strength = <16>;
1819 }; 1817 };
1820 1818
1821 cmd-pins { 1819 cmd-pins {
1822 pins 1820 pins = "sdc2_cmd";
1823 bias- 1821 bias-pull-up;
1824 drive 1822 drive-strength = <10>;
1825 }; 1823 };
1826 1824
1827 data-pins { 1825 data-pins {
1828 pins 1826 pins = "sdc2_data";
1829 bias- 1827 bias-pull-up;
1830 drive 1828 drive-strength = <10>;
1831 }; 1829 };
1832 }; 1830 };
1833 1831
1834 sdc2_state_off: sdc2- 1832 sdc2_state_off: sdc2-off-state {
1835 clk-pins { 1833 clk-pins {
1836 pins 1834 pins = "sdc2_clk";
1837 bias- 1835 bias-disable;
1838 drive 1836 drive-strength = <2>;
1839 }; 1837 };
1840 1838
1841 cmd-pins { 1839 cmd-pins {
1842 pins 1840 pins = "sdc2_cmd";
1843 bias- 1841 bias-pull-up;
1844 drive 1842 drive-strength = <2>;
1845 }; 1843 };
1846 1844
1847 data-pins { 1845 data-pins {
1848 pins 1846 pins = "sdc2_data";
1849 bias- 1847 bias-pull-up;
1850 drive 1848 drive-strength = <2>;
1851 }; 1849 };
1852 }; 1850 };
1853 }; 1851 };
1854 1852
1855 sram@290000 { 1853 sram@290000 {
1856 compatible = "qcom,rp 1854 compatible = "qcom,rpm-stats";
1857 reg = <0x00290000 0x1 1855 reg = <0x00290000 0x10000>;
1858 }; 1856 };
1859 1857
1860 spmi_bus: spmi@400f000 { 1858 spmi_bus: spmi@400f000 {
1861 compatible = "qcom,sp 1859 compatible = "qcom,spmi-pmic-arb";
1862 reg = <0x0400f000 0x1 1860 reg = <0x0400f000 0x1000>,
1863 <0x04400000 0x8 1861 <0x04400000 0x800000>,
1864 <0x04c00000 0x8 1862 <0x04c00000 0x800000>,
1865 <0x05800000 0x2 1863 <0x05800000 0x200000>,
1866 <0x0400a000 0x0 1864 <0x0400a000 0x002100>;
1867 reg-names = "core", " 1865 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1868 interrupt-names = "pe 1866 interrupt-names = "periph_irq";
1869 interrupts = <GIC_SPI 1867 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
1870 qcom,ee = <0>; 1868 qcom,ee = <0>;
1871 qcom,channel = <0>; 1869 qcom,channel = <0>;
1872 #address-cells = <2>; 1870 #address-cells = <2>;
1873 #size-cells = <0>; 1871 #size-cells = <0>;
1874 interrupt-controller; 1872 interrupt-controller;
1875 #interrupt-cells = <4 1873 #interrupt-cells = <4>;
1876 }; 1874 };
1877 1875
1878 bus@0 { 1876 bus@0 {
1879 power-domains = <&gcc 1877 power-domains = <&gcc AGGRE0_NOC_GDSC>;
1880 compatible = "simple- 1878 compatible = "simple-pm-bus";
1881 #address-cells = <1>; 1879 #address-cells = <1>;
1882 #size-cells = <1>; 1880 #size-cells = <1>;
1883 ranges = <0x0 0x0 0xf 1881 ranges = <0x0 0x0 0xffffffff>;
1884 1882
1885 pcie0: pcie@600000 { 1883 pcie0: pcie@600000 {
1886 compatible = 1884 compatible = "qcom,pcie-msm8996";
1887 status = "dis 1885 status = "disabled";
1888 power-domains 1886 power-domains = <&gcc PCIE0_GDSC>;
1889 bus-range = < 1887 bus-range = <0x00 0xff>;
1890 num-lanes = < 1888 num-lanes = <1>;
1891 1889
1892 reg = <0x0060 1890 reg = <0x00600000 0x2000>,
1893 <0x0c00 1891 <0x0c000000 0xf1d>,
1894 <0x0c00 1892 <0x0c000f20 0xa8>,
1895 <0x0c10 1893 <0x0c100000 0x100000>;
1896 reg-names = " 1894 reg-names = "parf", "dbi", "elbi","config";
1897 1895
1898 phys = <&pcie 1896 phys = <&pciephy_0>;
1899 phy-names = " 1897 phy-names = "pciephy";
1900 1898
1901 #address-cell 1899 #address-cells = <3>;
1902 #size-cells = 1900 #size-cells = <2>;
1903 ranges = <0x0 1901 ranges = <0x01000000 0x0 0x00000000 0x0c200000 0x0 0x100000>,
1904 <0x0 1902 <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;
1905 1903
1906 device_type = 1904 device_type = "pci";
1907 1905
1908 interrupts = 1906 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
1909 interrupt-nam 1907 interrupt-names = "msi";
1910 #interrupt-ce 1908 #interrupt-cells = <1>;
1911 interrupt-map 1909 interrupt-map-mask = <0 0 0 0x7>;
1912 interrupt-map 1910 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1913 1911 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1914 1912 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1915 1913 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1916 1914
1917 pinctrl-names 1915 pinctrl-names = "default", "sleep";
1918 pinctrl-0 = < 1916 pinctrl-0 = <&pcie0_state_on>;
1919 pinctrl-1 = < 1917 pinctrl-1 = <&pcie0_state_off>;
1920 1918
1921 linux,pci-dom 1919 linux,pci-domain = <0>;
1922 1920
1923 clocks = <&gc 1921 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1924 <&gcc 1922 <&gcc GCC_PCIE_0_AUX_CLK>,
1925 <&gcc 1923 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1926 <&gcc 1924 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1927 <&gcc 1925 <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
1928 1926
1929 clock-names = 1927 clock-names = "pipe",
1930 1928 "aux",
1931 1929 "cfg",
1932 1930 "bus_master",
1933 1931 "bus_slave";
1934 <<
1935 pcie@0 { <<
1936 devic <<
1937 reg = <<
1938 bus-r <<
1939 <<
1940 #addr <<
1941 #size <<
1942 range <<
1943 }; <<
1944 }; 1932 };
1945 1933
1946 pcie1: pcie@608000 { 1934 pcie1: pcie@608000 {
1947 compatible = 1935 compatible = "qcom,pcie-msm8996";
1948 power-domains 1936 power-domains = <&gcc PCIE1_GDSC>;
1949 bus-range = < 1937 bus-range = <0x00 0xff>;
1950 num-lanes = < 1938 num-lanes = <1>;
1951 1939
1952 status = "dis 1940 status = "disabled";
1953 1941
1954 reg = <0x0060 1942 reg = <0x00608000 0x2000>,
1955 <0x0d00 1943 <0x0d000000 0xf1d>,
1956 <0x0d00 1944 <0x0d000f20 0xa8>,
1957 <0x0d10 1945 <0x0d100000 0x100000>;
1958 1946
1959 reg-names = " 1947 reg-names = "parf", "dbi", "elbi","config";
1960 1948
1961 phys = <&pcie 1949 phys = <&pciephy_1>;
1962 phy-names = " 1950 phy-names = "pciephy";
1963 1951
1964 #address-cell 1952 #address-cells = <3>;
1965 #size-cells = 1953 #size-cells = <2>;
1966 ranges = <0x0 1954 ranges = <0x01000000 0x0 0x00000000 0x0d200000 0x0 0x100000>,
1967 <0x0 1955 <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>;
1968 1956
1969 device_type = 1957 device_type = "pci";
1970 1958
1971 interrupts = 1959 interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
1972 interrupt-nam 1960 interrupt-names = "msi";
1973 #interrupt-ce 1961 #interrupt-cells = <1>;
1974 interrupt-map 1962 interrupt-map-mask = <0 0 0 0x7>;
1975 interrupt-map 1963 interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1976 1964 <0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1977 1965 <0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1978 1966 <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1979 1967
1980 pinctrl-names 1968 pinctrl-names = "default", "sleep";
1981 pinctrl-0 = < 1969 pinctrl-0 = <&pcie1_state_on>;
1982 pinctrl-1 = < 1970 pinctrl-1 = <&pcie1_state_off>;
1983 1971
1984 linux,pci-dom 1972 linux,pci-domain = <1>;
1985 1973
1986 clocks = <&gc 1974 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1987 <&gcc 1975 <&gcc GCC_PCIE_1_AUX_CLK>,
1988 <&gcc 1976 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1989 <&gcc 1977 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1990 <&gcc 1978 <&gcc GCC_PCIE_1_SLV_AXI_CLK>;
1991 1979
1992 clock-names = 1980 clock-names = "pipe",
1993 1981 "aux",
1994 1982 "cfg",
1995 1983 "bus_master",
1996 1984 "bus_slave";
1997 <<
1998 pcie@0 { <<
1999 devic <<
2000 reg = <<
2001 bus-r <<
2002 <<
2003 #addr <<
2004 #size <<
2005 range <<
2006 }; <<
2007 }; 1985 };
2008 1986
2009 pcie2: pcie@610000 { 1987 pcie2: pcie@610000 {
2010 compatible = 1988 compatible = "qcom,pcie-msm8996";
2011 power-domains 1989 power-domains = <&gcc PCIE2_GDSC>;
2012 bus-range = < 1990 bus-range = <0x00 0xff>;
2013 num-lanes = < 1991 num-lanes = <1>;
2014 status = "dis 1992 status = "disabled";
2015 reg = <0x0061 1993 reg = <0x00610000 0x2000>,
2016 <0x0e00 1994 <0x0e000000 0xf1d>,
2017 <0x0e00 1995 <0x0e000f20 0xa8>,
2018 <0x0e10 1996 <0x0e100000 0x100000>;
2019 1997
2020 reg-names = " 1998 reg-names = "parf", "dbi", "elbi","config";
2021 1999
2022 phys = <&pcie 2000 phys = <&pciephy_2>;
2023 phy-names = " 2001 phy-names = "pciephy";
2024 2002
2025 #address-cell 2003 #address-cells = <3>;
2026 #size-cells = 2004 #size-cells = <2>;
2027 ranges = <0x0 2005 ranges = <0x01000000 0x0 0x00000000 0x0e200000 0x0 0x100000>,
2028 <0x0 2006 <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>;
2029 2007
2030 device_type = 2008 device_type = "pci";
2031 2009
2032 interrupts = 2010 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
2033 interrupt-nam 2011 interrupt-names = "msi";
2034 #interrupt-ce 2012 #interrupt-cells = <1>;
2035 interrupt-map 2013 interrupt-map-mask = <0 0 0 0x7>;
2036 interrupt-map 2014 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2037 2015 <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2038 2016 <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2039 2017 <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2040 2018
2041 pinctrl-names 2019 pinctrl-names = "default", "sleep";
2042 pinctrl-0 = < 2020 pinctrl-0 = <&pcie2_state_on>;
2043 pinctrl-1 = < 2021 pinctrl-1 = <&pcie2_state_off>;
2044 2022
2045 linux,pci-dom 2023 linux,pci-domain = <2>;
2046 clocks = <&gc 2024 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
2047 <&gcc 2025 <&gcc GCC_PCIE_2_AUX_CLK>,
2048 <&gcc 2026 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2049 <&gcc 2027 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
2050 <&gcc 2028 <&gcc GCC_PCIE_2_SLV_AXI_CLK>;
2051 2029
2052 clock-names = 2030 clock-names = "pipe",
2053 2031 "aux",
2054 2032 "cfg",
2055 2033 "bus_master",
2056 2034 "bus_slave";
2057 <<
2058 pcie@0 { <<
2059 devic <<
2060 reg = <<
2061 bus-r <<
2062 <<
2063 #addr <<
2064 #size <<
2065 range <<
2066 }; <<
2067 }; 2035 };
2068 }; 2036 };
2069 2037
2070 ufshc: ufshc@624000 { 2038 ufshc: ufshc@624000 {
2071 compatible = "qcom,ms 2039 compatible = "qcom,msm8996-ufshc", "qcom,ufshc",
2072 "jedec,u 2040 "jedec,ufs-2.0";
2073 reg = <0x00624000 0x2 2041 reg = <0x00624000 0x2500>;
2074 interrupts = <GIC_SPI 2042 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2075 2043
2076 phys = <&ufsphy>; 2044 phys = <&ufsphy>;
2077 phy-names = "ufsphy"; 2045 phy-names = "ufsphy";
2078 2046
2079 power-domains = <&gcc 2047 power-domains = <&gcc UFS_GDSC>;
2080 2048
2081 clock-names = 2049 clock-names =
>> 2050 "core_clk_src",
2082 "core_clk", 2051 "core_clk",
2083 "bus_clk", 2052 "bus_clk",
2084 "bus_aggr_clk 2053 "bus_aggr_clk",
2085 "iface_clk", 2054 "iface_clk",
>> 2055 "core_clk_unipro_src",
2086 "core_clk_uni 2056 "core_clk_unipro",
2087 "core_clk_ice 2057 "core_clk_ice",
2088 "ref_clk", 2058 "ref_clk",
2089 "tx_lane0_syn 2059 "tx_lane0_sync_clk",
2090 "rx_lane0_syn 2060 "rx_lane0_sync_clk";
2091 clocks = 2061 clocks =
>> 2062 <&gcc UFS_AXI_CLK_SRC>,
2092 <&gcc GCC_UFS 2063 <&gcc GCC_UFS_AXI_CLK>,
2093 <&gcc GCC_SYS 2064 <&gcc GCC_SYS_NOC_UFS_AXI_CLK>,
2094 <&gcc GCC_AGG 2065 <&gcc GCC_AGGRE2_UFS_AXI_CLK>,
2095 <&gcc GCC_UFS 2066 <&gcc GCC_UFS_AHB_CLK>,
>> 2067 <&gcc UFS_ICE_CORE_CLK_SRC>,
2096 <&gcc GCC_UFS 2068 <&gcc GCC_UFS_UNIPRO_CORE_CLK>,
2097 <&gcc GCC_UFS 2069 <&gcc GCC_UFS_ICE_CORE_CLK>,
2098 <&rpmcc RPM_S 2070 <&rpmcc RPM_SMD_LN_BB_CLK>,
2099 <&gcc GCC_UFS 2071 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
2100 <&gcc GCC_UFS 2072 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>;
2101 freq-table-hz = 2073 freq-table-hz =
2102 <100000000 20 2074 <100000000 200000000>,
2103 <0 0>, 2075 <0 0>,
2104 <0 0>, 2076 <0 0>,
2105 <0 0>, 2077 <0 0>,
2106 <75000000 150 !! 2078 <0 0>,
2107 <150000000 30 2079 <150000000 300000000>,
>> 2080 <75000000 150000000>,
>> 2081 <0 0>,
2108 <0 0>, 2082 <0 0>,
2109 <0 0>, 2083 <0 0>,
2110 <0 0>; 2084 <0 0>;
2111 2085
2112 interconnects = <&a2n 2086 interconnects = <&a2noc MASTER_UFS &bimc SLAVE_EBI_CH0>,
2113 <&bim 2087 <&bimc MASTER_AMPSS_M0 &cnoc SLAVE_UFS_CFG>;
2114 interconnect-names = 2088 interconnect-names = "ufs-ddr", "cpu-ufs";
2115 2089
2116 lanes-per-direction = 2090 lanes-per-direction = <1>;
2117 #reset-cells = <1>; 2091 #reset-cells = <1>;
2118 status = "disabled"; 2092 status = "disabled";
2119 }; 2093 };
2120 2094
2121 ufsphy: phy@627000 { 2095 ufsphy: phy@627000 {
2122 compatible = "qcom,ms 2096 compatible = "qcom,msm8996-qmp-ufs-phy";
2123 reg = <0x00627000 0x1 2097 reg = <0x00627000 0x1000>;
2124 2098
2125 clocks = <&rpmcc RPM_ 2099 clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, <&gcc GCC_UFS_CLKREF_CLK>;
2126 clock-names = "ref", 2100 clock-names = "ref", "qref";
2127 2101
2128 resets = <&ufshc 0>; 2102 resets = <&ufshc 0>;
2129 reset-names = "ufsphy 2103 reset-names = "ufsphy";
2130 2104
2131 #clock-cells = <1>; 2105 #clock-cells = <1>;
2132 #phy-cells = <0>; 2106 #phy-cells = <0>;
2133 2107
2134 status = "disabled"; 2108 status = "disabled";
2135 }; 2109 };
2136 2110
2137 camss: camss@a34000 { 2111 camss: camss@a34000 {
2138 compatible = "qcom,ms 2112 compatible = "qcom,msm8996-camss";
2139 reg = <0x00a34000 0x1 2113 reg = <0x00a34000 0x1000>,
2140 <0x00a00030 0x4 2114 <0x00a00030 0x4>,
2141 <0x00a35000 0x1 2115 <0x00a35000 0x1000>,
2142 <0x00a00038 0x4 2116 <0x00a00038 0x4>,
2143 <0x00a36000 0x1 2117 <0x00a36000 0x1000>,
2144 <0x00a00040 0x4 2118 <0x00a00040 0x4>,
2145 <0x00a30000 0x1 2119 <0x00a30000 0x100>,
2146 <0x00a30400 0x1 2120 <0x00a30400 0x100>,
2147 <0x00a30800 0x1 2121 <0x00a30800 0x100>,
2148 <0x00a30c00 0x1 2122 <0x00a30c00 0x100>,
2149 <0x00a31000 0x5 2123 <0x00a31000 0x500>,
2150 <0x00a00020 0x1 2124 <0x00a00020 0x10>,
2151 <0x00a10000 0x1 2125 <0x00a10000 0x1000>,
2152 <0x00a14000 0x1 2126 <0x00a14000 0x1000>;
2153 reg-names = "csiphy0" 2127 reg-names = "csiphy0",
2154 "csiphy0_clk_ 2128 "csiphy0_clk_mux",
2155 "csiphy1", 2129 "csiphy1",
2156 "csiphy1_clk_ 2130 "csiphy1_clk_mux",
2157 "csiphy2", 2131 "csiphy2",
2158 "csiphy2_clk_ 2132 "csiphy2_clk_mux",
2159 "csid0", 2133 "csid0",
2160 "csid1", 2134 "csid1",
2161 "csid2", 2135 "csid2",
2162 "csid3", 2136 "csid3",
2163 "ispif", 2137 "ispif",
2164 "csi_clk_mux" 2138 "csi_clk_mux",
2165 "vfe0", 2139 "vfe0",
2166 "vfe1"; 2140 "vfe1";
2167 interrupts = <GIC_SPI 2141 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
2168 <GIC_SPI 79 I 2142 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
2169 <GIC_SPI 80 I 2143 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
2170 <GIC_SPI 296 2144 <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
2171 <GIC_SPI 297 2145 <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
2172 <GIC_SPI 298 2146 <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
2173 <GIC_SPI 299 2147 <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
2174 <GIC_SPI 309 2148 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>,
2175 <GIC_SPI 314 2149 <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
2176 <GIC_SPI 315 2150 <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>;
2177 interrupt-names = "cs 2151 interrupt-names = "csiphy0",
2178 "csiphy1", 2152 "csiphy1",
2179 "csiphy2", 2153 "csiphy2",
2180 "csid0", 2154 "csid0",
2181 "csid1", 2155 "csid1",
2182 "csid2", 2156 "csid2",
2183 "csid3", 2157 "csid3",
2184 "ispif", 2158 "ispif",
2185 "vfe0", 2159 "vfe0",
2186 "vfe1"; 2160 "vfe1";
2187 power-domains = <&mmc 2161 power-domains = <&mmcc VFE0_GDSC>,
2188 <&mmc 2162 <&mmcc VFE1_GDSC>;
2189 clocks = <&mmcc CAMSS 2163 clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
2190 <&mmcc CAMSS_ 2164 <&mmcc CAMSS_ISPIF_AHB_CLK>,
2191 <&mmcc CAMSS_ 2165 <&mmcc CAMSS_CSI0PHYTIMER_CLK>,
2192 <&mmcc CAMSS_ 2166 <&mmcc CAMSS_CSI1PHYTIMER_CLK>,
2193 <&mmcc CAMSS_ 2167 <&mmcc CAMSS_CSI2PHYTIMER_CLK>,
2194 <&mmcc CAMSS_ 2168 <&mmcc CAMSS_CSI0_AHB_CLK>,
2195 <&mmcc CAMSS_ 2169 <&mmcc CAMSS_CSI0_CLK>,
2196 <&mmcc CAMSS_ 2170 <&mmcc CAMSS_CSI0PHY_CLK>,
2197 <&mmcc CAMSS_ 2171 <&mmcc CAMSS_CSI0PIX_CLK>,
2198 <&mmcc CAMSS_ 2172 <&mmcc CAMSS_CSI0RDI_CLK>,
2199 <&mmcc CAMSS_ 2173 <&mmcc CAMSS_CSI1_AHB_CLK>,
2200 <&mmcc CAMSS_ 2174 <&mmcc CAMSS_CSI1_CLK>,
2201 <&mmcc CAMSS_ 2175 <&mmcc CAMSS_CSI1PHY_CLK>,
2202 <&mmcc CAMSS_ 2176 <&mmcc CAMSS_CSI1PIX_CLK>,
2203 <&mmcc CAMSS_ 2177 <&mmcc CAMSS_CSI1RDI_CLK>,
2204 <&mmcc CAMSS_ 2178 <&mmcc CAMSS_CSI2_AHB_CLK>,
2205 <&mmcc CAMSS_ 2179 <&mmcc CAMSS_CSI2_CLK>,
2206 <&mmcc CAMSS_ 2180 <&mmcc CAMSS_CSI2PHY_CLK>,
2207 <&mmcc CAMSS_ 2181 <&mmcc CAMSS_CSI2PIX_CLK>,
2208 <&mmcc CAMSS_ 2182 <&mmcc CAMSS_CSI2RDI_CLK>,
2209 <&mmcc CAMSS_ 2183 <&mmcc CAMSS_CSI3_AHB_CLK>,
2210 <&mmcc CAMSS_ 2184 <&mmcc CAMSS_CSI3_CLK>,
2211 <&mmcc CAMSS_ 2185 <&mmcc CAMSS_CSI3PHY_CLK>,
2212 <&mmcc CAMSS_ 2186 <&mmcc CAMSS_CSI3PIX_CLK>,
2213 <&mmcc CAMSS_ 2187 <&mmcc CAMSS_CSI3RDI_CLK>,
2214 <&mmcc CAMSS_ 2188 <&mmcc CAMSS_AHB_CLK>,
2215 <&mmcc CAMSS_ 2189 <&mmcc CAMSS_VFE0_CLK>,
2216 <&mmcc CAMSS_ 2190 <&mmcc CAMSS_CSI_VFE0_CLK>,
2217 <&mmcc CAMSS_ 2191 <&mmcc CAMSS_VFE0_AHB_CLK>,
2218 <&mmcc CAMSS_ 2192 <&mmcc CAMSS_VFE0_STREAM_CLK>,
2219 <&mmcc CAMSS_ 2193 <&mmcc CAMSS_VFE1_CLK>,
2220 <&mmcc CAMSS_ 2194 <&mmcc CAMSS_CSI_VFE1_CLK>,
2221 <&mmcc CAMSS_ 2195 <&mmcc CAMSS_VFE1_AHB_CLK>,
2222 <&mmcc CAMSS_ 2196 <&mmcc CAMSS_VFE1_STREAM_CLK>,
2223 <&mmcc CAMSS_ 2197 <&mmcc CAMSS_VFE_AHB_CLK>,
2224 <&mmcc CAMSS_ 2198 <&mmcc CAMSS_VFE_AXI_CLK>;
2225 clock-names = "top_ah 2199 clock-names = "top_ahb",
2226 "ispif_ahb", 2200 "ispif_ahb",
2227 "csiphy0_time 2201 "csiphy0_timer",
2228 "csiphy1_time 2202 "csiphy1_timer",
2229 "csiphy2_time 2203 "csiphy2_timer",
2230 "csi0_ahb", 2204 "csi0_ahb",
2231 "csi0", 2205 "csi0",
2232 "csi0_phy", 2206 "csi0_phy",
2233 "csi0_pix", 2207 "csi0_pix",
2234 "csi0_rdi", 2208 "csi0_rdi",
2235 "csi1_ahb", 2209 "csi1_ahb",
2236 "csi1", 2210 "csi1",
2237 "csi1_phy", 2211 "csi1_phy",
2238 "csi1_pix", 2212 "csi1_pix",
2239 "csi1_rdi", 2213 "csi1_rdi",
2240 "csi2_ahb", 2214 "csi2_ahb",
2241 "csi2", 2215 "csi2",
2242 "csi2_phy", 2216 "csi2_phy",
2243 "csi2_pix", 2217 "csi2_pix",
2244 "csi2_rdi", 2218 "csi2_rdi",
2245 "csi3_ahb", 2219 "csi3_ahb",
2246 "csi3", 2220 "csi3",
2247 "csi3_phy", 2221 "csi3_phy",
2248 "csi3_pix", 2222 "csi3_pix",
2249 "csi3_rdi", 2223 "csi3_rdi",
2250 "ahb", 2224 "ahb",
2251 "vfe0", 2225 "vfe0",
2252 "csi_vfe0", 2226 "csi_vfe0",
2253 "vfe0_ahb", 2227 "vfe0_ahb",
2254 "vfe0_stream" 2228 "vfe0_stream",
2255 "vfe1", 2229 "vfe1",
2256 "csi_vfe1", 2230 "csi_vfe1",
2257 "vfe1_ahb", 2231 "vfe1_ahb",
2258 "vfe1_stream" 2232 "vfe1_stream",
2259 "vfe_ahb", 2233 "vfe_ahb",
2260 "vfe_axi"; 2234 "vfe_axi";
2261 iommus = <&vfe_smmu 0 2235 iommus = <&vfe_smmu 0>,
2262 <&vfe_smmu 1 2236 <&vfe_smmu 1>,
2263 <&vfe_smmu 2 2237 <&vfe_smmu 2>,
2264 <&vfe_smmu 3 2238 <&vfe_smmu 3>;
2265 status = "disabled"; 2239 status = "disabled";
2266 ports { 2240 ports {
2267 #address-cell 2241 #address-cells = <1>;
2268 #size-cells = 2242 #size-cells = <0>;
2269 }; 2243 };
2270 }; 2244 };
2271 2245
2272 cci: cci@a0c000 { 2246 cci: cci@a0c000 {
2273 compatible = "qcom,ms 2247 compatible = "qcom,msm8996-cci";
2274 #address-cells = <1>; 2248 #address-cells = <1>;
2275 #size-cells = <0>; 2249 #size-cells = <0>;
2276 reg = <0xa0c000 0x100 2250 reg = <0xa0c000 0x1000>;
2277 interrupts = <GIC_SPI 2251 interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>;
2278 power-domains = <&mmc 2252 power-domains = <&mmcc CAMSS_GDSC>;
2279 clocks = <&mmcc CAMSS 2253 clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
2280 <&mmcc CAMSS 2254 <&mmcc CAMSS_CCI_AHB_CLK>,
2281 <&mmcc CAMSS 2255 <&mmcc CAMSS_CCI_CLK>,
2282 <&mmcc CAMSS 2256 <&mmcc CAMSS_AHB_CLK>;
2283 clock-names = "camss_ 2257 clock-names = "camss_top_ahb",
2284 "cci_ah 2258 "cci_ahb",
2285 "cci", 2259 "cci",
2286 "camss_ 2260 "camss_ahb";
2287 assigned-clocks = <&m 2261 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>,
2288 <&m 2262 <&mmcc CAMSS_CCI_CLK>;
2289 assigned-clock-rates 2263 assigned-clock-rates = <80000000>, <37500000>;
2290 pinctrl-names = "defa 2264 pinctrl-names = "default";
2291 pinctrl-0 = <&cci0_de 2265 pinctrl-0 = <&cci0_default &cci1_default>;
2292 status = "disabled"; 2266 status = "disabled";
2293 2267
2294 cci_i2c0: i2c-bus@0 { 2268 cci_i2c0: i2c-bus@0 {
2295 reg = <0>; 2269 reg = <0>;
2296 clock-frequen 2270 clock-frequency = <400000>;
2297 #address-cell 2271 #address-cells = <1>;
2298 #size-cells = 2272 #size-cells = <0>;
2299 }; 2273 };
2300 2274
2301 cci_i2c1: i2c-bus@1 { 2275 cci_i2c1: i2c-bus@1 {
2302 reg = <1>; 2276 reg = <1>;
2303 clock-frequen 2277 clock-frequency = <400000>;
2304 #address-cell 2278 #address-cells = <1>;
2305 #size-cells = 2279 #size-cells = <0>;
2306 }; 2280 };
2307 }; 2281 };
2308 2282
2309 adreno_smmu: iommu@b40000 { 2283 adreno_smmu: iommu@b40000 {
2310 compatible = "qcom,ms 2284 compatible = "qcom,msm8996-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
2311 reg = <0x00b40000 0x1 2285 reg = <0x00b40000 0x10000>;
2312 2286
2313 #global-interrupts = 2287 #global-interrupts = <1>;
2314 interrupts = <GIC_SPI 2288 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
2315 <GIC_SPI 2289 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
2316 <GIC_SPI 2290 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
2317 #iommu-cells = <1>; 2291 #iommu-cells = <1>;
2318 2292
2319 clocks = <&gcc GCC_MM 2293 clocks = <&gcc GCC_MMSS_BIMC_GFX_CLK>,
2320 <&mmcc GPU_A 2294 <&mmcc GPU_AHB_CLK>;
2321 clock-names = "bus", 2295 clock-names = "bus", "iface";
2322 2296
2323 power-domains = <&mmc 2297 power-domains = <&mmcc GPU_GDSC>;
2324 }; 2298 };
2325 2299
2326 venus: video-codec@c00000 { 2300 venus: video-codec@c00000 {
2327 compatible = "qcom,ms 2301 compatible = "qcom,msm8996-venus";
2328 reg = <0x00c00000 0xf 2302 reg = <0x00c00000 0xff000>;
2329 interrupts = <GIC_SPI 2303 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
2330 power-domains = <&mmc 2304 power-domains = <&mmcc VENUS_GDSC>;
2331 clocks = <&mmcc VIDEO 2305 clocks = <&mmcc VIDEO_CORE_CLK>,
2332 <&mmcc VIDEO 2306 <&mmcc VIDEO_AHB_CLK>,
2333 <&mmcc VIDEO 2307 <&mmcc VIDEO_AXI_CLK>,
2334 <&mmcc VIDEO 2308 <&mmcc VIDEO_MAXI_CLK>;
2335 clock-names = "core", 2309 clock-names = "core", "iface", "bus", "mbus";
2336 interconnects = <&mno 2310 interconnects = <&mnoc MASTER_VIDEO_P0 &bimc SLAVE_EBI_CH0>,
2337 <&bim 2311 <&bimc MASTER_AMPSS_M0 &mnoc SLAVE_VENUS_CFG>;
2338 interconnect-names = 2312 interconnect-names = "video-mem", "cpu-cfg";
2339 iommus = <&venus_smmu 2313 iommus = <&venus_smmu 0x00>,
2340 <&venus_smmu 2314 <&venus_smmu 0x01>,
2341 <&venus_smmu 2315 <&venus_smmu 0x0a>,
2342 <&venus_smmu 2316 <&venus_smmu 0x07>,
2343 <&venus_smmu 2317 <&venus_smmu 0x0e>,
2344 <&venus_smmu 2318 <&venus_smmu 0x0f>,
2345 <&venus_smmu 2319 <&venus_smmu 0x08>,
2346 <&venus_smmu 2320 <&venus_smmu 0x09>,
2347 <&venus_smmu 2321 <&venus_smmu 0x0b>,
2348 <&venus_smmu 2322 <&venus_smmu 0x0c>,
2349 <&venus_smmu 2323 <&venus_smmu 0x0d>,
2350 <&venus_smmu 2324 <&venus_smmu 0x10>,
2351 <&venus_smmu 2325 <&venus_smmu 0x11>,
2352 <&venus_smmu 2326 <&venus_smmu 0x21>,
2353 <&venus_smmu 2327 <&venus_smmu 0x28>,
2354 <&venus_smmu 2328 <&venus_smmu 0x29>,
2355 <&venus_smmu 2329 <&venus_smmu 0x2b>,
2356 <&venus_smmu 2330 <&venus_smmu 0x2c>,
2357 <&venus_smmu 2331 <&venus_smmu 0x2d>,
2358 <&venus_smmu 2332 <&venus_smmu 0x31>;
2359 memory-region = <&ven 2333 memory-region = <&venus_mem>;
2360 status = "disabled"; 2334 status = "disabled";
2361 2335
2362 video-decoder { 2336 video-decoder {
2363 compatible = 2337 compatible = "venus-decoder";
2364 clocks = <&mm 2338 clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
2365 clock-names = 2339 clock-names = "core";
2366 power-domains 2340 power-domains = <&mmcc VENUS_CORE0_GDSC>;
2367 }; 2341 };
2368 2342
2369 video-encoder { 2343 video-encoder {
2370 compatible = 2344 compatible = "venus-encoder";
2371 clocks = <&mm 2345 clocks = <&mmcc VIDEO_SUBCORE1_CLK>;
2372 clock-names = 2346 clock-names = "core";
2373 power-domains 2347 power-domains = <&mmcc VENUS_CORE1_GDSC>;
2374 }; 2348 };
2375 }; 2349 };
2376 2350
2377 mdp_smmu: iommu@d00000 { 2351 mdp_smmu: iommu@d00000 {
2378 compatible = "qcom,ms 2352 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2379 reg = <0x00d00000 0x1 2353 reg = <0x00d00000 0x10000>;
2380 2354
2381 #global-interrupts = 2355 #global-interrupts = <1>;
2382 interrupts = <GIC_SPI 2356 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
2383 <GIC_SPI 2357 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
2384 <GIC_SPI 2358 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
2385 #iommu-cells = <1>; 2359 #iommu-cells = <1>;
2386 clocks = <&mmcc SMMU_ 2360 clocks = <&mmcc SMMU_MDP_AXI_CLK>,
2387 <&mmcc SMMU_ 2361 <&mmcc SMMU_MDP_AHB_CLK>;
2388 clock-names = "bus", 2362 clock-names = "bus", "iface";
2389 2363
2390 power-domains = <&mmc 2364 power-domains = <&mmcc MDSS_GDSC>;
2391 }; 2365 };
2392 2366
2393 venus_smmu: iommu@d40000 { 2367 venus_smmu: iommu@d40000 {
2394 compatible = "qcom,ms 2368 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2395 reg = <0x00d40000 0x2 2369 reg = <0x00d40000 0x20000>;
2396 #global-interrupts = 2370 #global-interrupts = <1>;
2397 interrupts = <GIC_SPI 2371 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
2398 <GIC_SPI 2372 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
2399 <GIC_SPI 2373 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
2400 <GIC_SPI 2374 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
2401 <GIC_SPI 2375 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
2402 <GIC_SPI 2376 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
2403 <GIC_SPI 2377 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
2404 <GIC_SPI 2378 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
2405 power-domains = <&mmc 2379 power-domains = <&mmcc MMAGIC_VIDEO_GDSC>;
2406 clocks = <&mmcc SMMU_ 2380 clocks = <&mmcc SMMU_VIDEO_AXI_CLK>,
2407 <&mmcc SMMU_ 2381 <&mmcc SMMU_VIDEO_AHB_CLK>;
2408 clock-names = "bus", 2382 clock-names = "bus", "iface";
2409 #iommu-cells = <1>; 2383 #iommu-cells = <1>;
2410 status = "okay"; 2384 status = "okay";
2411 }; 2385 };
2412 2386
2413 vfe_smmu: iommu@da0000 { 2387 vfe_smmu: iommu@da0000 {
2414 compatible = "qcom,ms 2388 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2415 reg = <0x00da0000 0x1 2389 reg = <0x00da0000 0x10000>;
2416 2390
2417 #global-interrupts = 2391 #global-interrupts = <1>;
2418 interrupts = <GIC_SPI 2392 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
2419 <GIC_SPI 2393 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
2420 <GIC_SPI 2394 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
2421 power-domains = <&mmc 2395 power-domains = <&mmcc MMAGIC_CAMSS_GDSC>;
2422 clocks = <&mmcc SMMU_ 2396 clocks = <&mmcc SMMU_VFE_AXI_CLK>,
2423 <&mmcc SMMU_ 2397 <&mmcc SMMU_VFE_AHB_CLK>;
2424 clock-names = "bus", 2398 clock-names = "bus", "iface";
2425 #iommu-cells = <1>; 2399 #iommu-cells = <1>;
2426 }; 2400 };
2427 2401
2428 lpass_q6_smmu: iommu@1600000 2402 lpass_q6_smmu: iommu@1600000 {
2429 compatible = "qcom,ms 2403 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2430 reg = <0x01600000 0x2 2404 reg = <0x01600000 0x20000>;
2431 #iommu-cells = <1>; 2405 #iommu-cells = <1>;
2432 power-domains = <&gcc 2406 power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>;
2433 2407
2434 #global-interrupts = 2408 #global-interrupts = <1>;
2435 interrupts = <GIC_SPI 2409 interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
2436 <GIC_SPI 226 2410 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
2437 <GIC_SPI 393 2411 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
2438 <GIC_SPI 394 2412 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
2439 <GIC_SPI 395 2413 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
2440 <GIC_SPI 396 2414 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
2441 <GIC_SPI 397 2415 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
2442 <GIC_SPI 398 2416 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
2443 <GIC_SPI 399 2417 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
2444 <GIC_SPI 400 2418 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
2445 <GIC_SPI 401 2419 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
2446 <GIC_SPI 402 2420 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
2447 <GIC_SPI 403 2421 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>;
2448 2422
2449 clocks = <&gcc GCC_HL 2423 clocks = <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>,
2450 <&gcc GCC_HL 2424 <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>;
2451 clock-names = "bus", 2425 clock-names = "bus", "iface";
2452 }; 2426 };
2453 2427
2454 slpi_pil: remoteproc@1c00000 2428 slpi_pil: remoteproc@1c00000 {
2455 compatible = "qcom,ms 2429 compatible = "qcom,msm8996-slpi-pil";
2456 reg = <0x01c00000 0x4 2430 reg = <0x01c00000 0x4000>;
2457 2431
2458 interrupts-extended = 2432 interrupts-extended = <&intc 0 390 IRQ_TYPE_EDGE_RISING>,
2459 2433 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2460 2434 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2461 2435 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2462 2436 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2463 interrupt-names = "wd 2437 interrupt-names = "wdog",
2464 "fa 2438 "fatal",
2465 "re 2439 "ready",
2466 "ha 2440 "handover",
2467 "st 2441 "stop-ack";
2468 2442
2469 clocks = <&xo_board>; 2443 clocks = <&xo_board>;
2470 clock-names = "xo"; 2444 clock-names = "xo";
2471 2445
2472 memory-region = <&slp 2446 memory-region = <&slpi_mem>;
2473 2447
2474 qcom,smem-states = <& 2448 qcom,smem-states = <&slpi_smp2p_out 0>;
2475 qcom,smem-state-names 2449 qcom,smem-state-names = "stop";
2476 2450
2477 power-domains = <&rpm 2451 power-domains = <&rpmpd MSM8996_VDDSSCX>;
2478 power-domain-names = 2452 power-domain-names = "ssc_cx";
2479 2453
2480 status = "disabled"; 2454 status = "disabled";
2481 2455
2482 glink-edge { <<
2483 interrupts = <<
2484 label = "dsps <<
2485 qcom,remote-p <<
2486 mboxes = <&ap <<
2487 }; <<
2488 <<
2489 smd-edge { 2456 smd-edge {
2490 interrupts = 2457 interrupts = <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>;
2491 2458
2492 label = "dsps 2459 label = "dsps";
2493 mboxes = <&ap 2460 mboxes = <&apcs_glb 25>;
2494 qcom,smd-edge 2461 qcom,smd-edge = <3>;
2495 qcom,remote-p 2462 qcom,remote-pid = <3>;
2496 }; 2463 };
2497 }; 2464 };
2498 2465
2499 mss_pil: remoteproc@2080000 { 2466 mss_pil: remoteproc@2080000 {
2500 compatible = "qcom,ms 2467 compatible = "qcom,msm8996-mss-pil";
2501 reg = <0x2080000 0x10 2468 reg = <0x2080000 0x100>,
2502 <0x2180000 0x02 2469 <0x2180000 0x020>;
2503 reg-names = "qdsp6", 2470 reg-names = "qdsp6", "rmb";
2504 2471
2505 interrupts-extended = 2472 interrupts-extended = <&intc 0 448 IRQ_TYPE_EDGE_RISING>,
2506 2473 <&mpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2507 2474 <&mpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2508 2475 <&mpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2509 2476 <&mpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
2510 2477 <&mpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
2511 interrupt-names = "wd 2478 interrupt-names = "wdog", "fatal", "ready",
2512 "ha 2479 "handover", "stop-ack",
2513 "sh 2480 "shutdown-ack";
2514 2481
2515 clocks = <&gcc GCC_MS 2482 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
2516 <&gcc GCC_MS 2483 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
2517 <&gcc GCC_BO 2484 <&gcc GCC_BOOT_ROM_AHB_CLK>,
2518 <&xo_board>, 2485 <&xo_board>,
2519 <&gcc GCC_MS 2486 <&gcc GCC_MSS_GPLL0_DIV_CLK>,
2520 <&gcc GCC_MS 2487 <&gcc GCC_MSS_SNOC_AXI_CLK>,
2521 <&gcc GCC_MS 2488 <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>,
2522 <&rpmcc RPM_ 2489 <&rpmcc RPM_SMD_QDSS_CLK>;
2523 clock-names = "iface" 2490 clock-names = "iface",
2524 "bus", 2491 "bus",
2525 "mem", 2492 "mem",
2526 "xo", 2493 "xo",
2527 "gpll0_ 2494 "gpll0_mss",
2528 "snoc_a 2495 "snoc_axi",
2529 "mnoc_a 2496 "mnoc_axi",
2530 "qdss"; 2497 "qdss";
2531 2498
2532 resets = <&gcc GCC_MS 2499 resets = <&gcc GCC_MSS_RESTART>;
2533 reset-names = "mss_re 2500 reset-names = "mss_restart";
2534 2501
2535 power-domains = <&rpm 2502 power-domains = <&rpmpd MSM8996_VDDCX>,
2536 <&rpm 2503 <&rpmpd MSM8996_VDDMX>;
2537 power-domain-names = 2504 power-domain-names = "cx", "mx";
2538 2505
2539 qcom,smem-states = <& 2506 qcom,smem-states = <&mpss_smp2p_out 0>;
2540 qcom,smem-state-names 2507 qcom,smem-state-names = "stop";
2541 2508
2542 qcom,halt-regs = <&tc 2509 qcom,halt-regs = <&tcsr_1 0x3000 0x5000 0x4000>;
2543 2510
2544 status = "disabled"; 2511 status = "disabled";
2545 2512
2546 mba { 2513 mba {
2547 memory-region 2514 memory-region = <&mba_mem>;
2548 }; 2515 };
2549 2516
2550 mpss { 2517 mpss {
2551 memory-region 2518 memory-region = <&mpss_mem>;
2552 }; 2519 };
2553 2520
2554 metadata { 2521 metadata {
2555 memory-region 2522 memory-region = <&mdata_mem>;
2556 }; 2523 };
2557 2524
2558 glink-edge { <<
2559 interrupts = <<
2560 label = "mode <<
2561 qcom,remote-p <<
2562 mboxes = <&ap <<
2563 }; <<
2564 <<
2565 smd-edge { 2525 smd-edge {
2566 interrupts = 2526 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
2567 2527
2568 label = "mpss 2528 label = "mpss";
2569 mboxes = <&ap 2529 mboxes = <&apcs_glb 12>;
2570 qcom,smd-edge 2530 qcom,smd-edge = <0>;
2571 qcom,remote-p 2531 qcom,remote-pid = <1>;
2572 }; 2532 };
2573 }; 2533 };
2574 2534
2575 stm@3002000 { 2535 stm@3002000 {
2576 compatible = "arm,cor 2536 compatible = "arm,coresight-stm", "arm,primecell";
2577 reg = <0x3002000 0x10 2537 reg = <0x3002000 0x1000>,
2578 <0x8280000 0x18 2538 <0x8280000 0x180000>;
2579 reg-names = "stm-base 2539 reg-names = "stm-base", "stm-stimulus-base";
2580 2540
2581 clocks = <&rpmcc RPM_ 2541 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2582 clock-names = "apb_pc 2542 clock-names = "apb_pclk", "atclk";
2583 2543
2584 out-ports { 2544 out-ports {
2585 port { 2545 port {
2586 stm_o 2546 stm_out: endpoint {
2587 2547 remote-endpoint =
2588 2548 <&funnel0_in>;
2589 }; 2549 };
2590 }; 2550 };
2591 }; 2551 };
2592 }; 2552 };
2593 2553
2594 tpiu@3020000 { 2554 tpiu@3020000 {
2595 compatible = "arm,cor 2555 compatible = "arm,coresight-tpiu", "arm,primecell";
2596 reg = <0x3020000 0x10 2556 reg = <0x3020000 0x1000>;
2597 2557
2598 clocks = <&rpmcc RPM_ 2558 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2599 clock-names = "apb_pc 2559 clock-names = "apb_pclk", "atclk";
2600 2560
2601 in-ports { 2561 in-ports {
2602 port { 2562 port {
2603 tpiu_ 2563 tpiu_in: endpoint {
2604 2564 remote-endpoint =
2605 2565 <&replicator_out1>;
2606 }; 2566 };
2607 }; 2567 };
2608 }; 2568 };
2609 }; 2569 };
2610 2570
2611 funnel@3021000 { 2571 funnel@3021000 {
2612 compatible = "arm,cor 2572 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2613 reg = <0x3021000 0x10 2573 reg = <0x3021000 0x1000>;
2614 2574
2615 clocks = <&rpmcc RPM_ 2575 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2616 clock-names = "apb_pc 2576 clock-names = "apb_pclk", "atclk";
2617 2577
2618 in-ports { 2578 in-ports {
2619 #address-cell 2579 #address-cells = <1>;
2620 #size-cells = 2580 #size-cells = <0>;
2621 2581
2622 port@7 { 2582 port@7 {
2623 reg = 2583 reg = <7>;
2624 funne 2584 funnel0_in: endpoint {
2625 2585 remote-endpoint =
2626 2586 <&stm_out>;
2627 }; 2587 };
2628 }; 2588 };
2629 }; 2589 };
2630 2590
2631 out-ports { 2591 out-ports {
2632 port { 2592 port {
2633 funne 2593 funnel0_out: endpoint {
2634 2594 remote-endpoint =
2635 2595 <&merge_funnel_in0>;
2636 }; 2596 };
2637 }; 2597 };
2638 }; 2598 };
2639 }; 2599 };
2640 2600
2641 funnel@3022000 { 2601 funnel@3022000 {
2642 compatible = "arm,cor 2602 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2643 reg = <0x3022000 0x10 2603 reg = <0x3022000 0x1000>;
2644 2604
2645 clocks = <&rpmcc RPM_ 2605 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2646 clock-names = "apb_pc 2606 clock-names = "apb_pclk", "atclk";
2647 2607
2648 in-ports { 2608 in-ports {
2649 #address-cell 2609 #address-cells = <1>;
2650 #size-cells = 2610 #size-cells = <0>;
2651 2611
2652 port@6 { 2612 port@6 {
2653 reg = 2613 reg = <6>;
2654 funne 2614 funnel1_in: endpoint {
2655 2615 remote-endpoint =
2656 2616 <&apss_merge_funnel_out>;
2657 }; 2617 };
2658 }; 2618 };
2659 }; 2619 };
2660 2620
2661 out-ports { 2621 out-ports {
2662 port { 2622 port {
2663 funne 2623 funnel1_out: endpoint {
2664 2624 remote-endpoint =
2665 2625 <&merge_funnel_in1>;
2666 }; 2626 };
2667 }; 2627 };
2668 }; 2628 };
2669 }; 2629 };
2670 2630
2671 funnel@3023000 { 2631 funnel@3023000 {
2672 compatible = "arm,cor 2632 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2673 reg = <0x3023000 0x10 2633 reg = <0x3023000 0x1000>;
2674 2634
2675 clocks = <&rpmcc RPM_ 2635 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2676 clock-names = "apb_pc 2636 clock-names = "apb_pclk", "atclk";
2677 2637
2678 in-ports { 2638 in-ports {
2679 port { 2639 port {
2680 funne 2640 funnel_in2_in_modem_etm: endpoint {
2681 2641 remote-endpoint =
2682 2642 <&modem_etm_out_funnel_in2>;
2683 }; 2643 };
2684 }; 2644 };
2685 }; 2645 };
2686 2646
2687 out-ports { 2647 out-ports {
2688 port { 2648 port {
2689 funne 2649 funnel2_out: endpoint {
2690 2650 remote-endpoint =
2691 2651 <&merge_funnel_in2>;
2692 }; 2652 };
2693 }; 2653 };
2694 }; 2654 };
2695 }; 2655 };
2696 2656
2697 funnel@3025000 { 2657 funnel@3025000 {
2698 compatible = "arm,cor 2658 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2699 reg = <0x3025000 0x10 2659 reg = <0x3025000 0x1000>;
2700 2660
2701 clocks = <&rpmcc RPM_ 2661 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2702 clock-names = "apb_pc 2662 clock-names = "apb_pclk", "atclk";
2703 2663
2704 in-ports { 2664 in-ports {
2705 #address-cell 2665 #address-cells = <1>;
2706 #size-cells = 2666 #size-cells = <0>;
2707 2667
2708 port@0 { 2668 port@0 {
2709 reg = 2669 reg = <0>;
2710 merge 2670 merge_funnel_in0: endpoint {
2711 2671 remote-endpoint =
2712 2672 <&funnel0_out>;
2713 }; 2673 };
2714 }; 2674 };
2715 2675
2716 port@1 { 2676 port@1 {
2717 reg = 2677 reg = <1>;
2718 merge 2678 merge_funnel_in1: endpoint {
2719 2679 remote-endpoint =
2720 2680 <&funnel1_out>;
2721 }; 2681 };
2722 }; 2682 };
2723 2683
2724 port@2 { 2684 port@2 {
2725 reg = 2685 reg = <2>;
2726 merge 2686 merge_funnel_in2: endpoint {
2727 2687 remote-endpoint =
2728 2688 <&funnel2_out>;
2729 }; 2689 };
2730 }; 2690 };
2731 }; 2691 };
2732 2692
2733 out-ports { 2693 out-ports {
2734 port { 2694 port {
2735 merge 2695 merge_funnel_out: endpoint {
2736 2696 remote-endpoint =
2737 2697 <&etf_in>;
2738 }; 2698 };
2739 }; 2699 };
2740 }; 2700 };
2741 }; 2701 };
2742 2702
2743 replicator@3026000 { 2703 replicator@3026000 {
2744 compatible = "arm,cor 2704 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2745 reg = <0x3026000 0x10 2705 reg = <0x3026000 0x1000>;
2746 2706
2747 clocks = <&rpmcc RPM_ 2707 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2748 clock-names = "apb_pc 2708 clock-names = "apb_pclk", "atclk";
2749 2709
2750 in-ports { 2710 in-ports {
2751 port { 2711 port {
2752 repli 2712 replicator_in: endpoint {
2753 2713 remote-endpoint =
2754 2714 <&etf_out>;
2755 }; 2715 };
2756 }; 2716 };
2757 }; 2717 };
2758 2718
2759 out-ports { 2719 out-ports {
2760 #address-cell 2720 #address-cells = <1>;
2761 #size-cells = 2721 #size-cells = <0>;
2762 2722
2763 port@0 { 2723 port@0 {
2764 reg = 2724 reg = <0>;
2765 repli 2725 replicator_out0: endpoint {
2766 2726 remote-endpoint =
2767 2727 <&etr_in>;
2768 }; 2728 };
2769 }; 2729 };
2770 2730
2771 port@1 { 2731 port@1 {
2772 reg = 2732 reg = <1>;
2773 repli 2733 replicator_out1: endpoint {
2774 2734 remote-endpoint =
2775 2735 <&tpiu_in>;
2776 }; 2736 };
2777 }; 2737 };
2778 }; 2738 };
2779 }; 2739 };
2780 2740
2781 etf@3027000 { 2741 etf@3027000 {
2782 compatible = "arm,cor 2742 compatible = "arm,coresight-tmc", "arm,primecell";
2783 reg = <0x3027000 0x10 2743 reg = <0x3027000 0x1000>;
2784 2744
2785 clocks = <&rpmcc RPM_ 2745 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2786 clock-names = "apb_pc 2746 clock-names = "apb_pclk", "atclk";
2787 2747
2788 in-ports { 2748 in-ports {
2789 port { 2749 port {
2790 etf_i 2750 etf_in: endpoint {
2791 2751 remote-endpoint =
2792 2752 <&merge_funnel_out>;
2793 }; 2753 };
2794 }; 2754 };
2795 }; 2755 };
2796 2756
2797 out-ports { 2757 out-ports {
2798 port { 2758 port {
2799 etf_o 2759 etf_out: endpoint {
2800 2760 remote-endpoint =
2801 2761 <&replicator_in>;
2802 }; 2762 };
2803 }; 2763 };
2804 }; 2764 };
2805 }; 2765 };
2806 2766
2807 etr@3028000 { 2767 etr@3028000 {
2808 compatible = "arm,cor 2768 compatible = "arm,coresight-tmc", "arm,primecell";
2809 reg = <0x3028000 0x10 2769 reg = <0x3028000 0x1000>;
2810 2770
2811 clocks = <&rpmcc RPM_ 2771 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2812 clock-names = "apb_pc 2772 clock-names = "apb_pclk", "atclk";
2813 arm,scatter-gather; 2773 arm,scatter-gather;
2814 2774
2815 in-ports { 2775 in-ports {
2816 port { 2776 port {
2817 etr_i 2777 etr_in: endpoint {
2818 2778 remote-endpoint =
2819 2779 <&replicator_out0>;
2820 }; 2780 };
2821 }; 2781 };
2822 }; 2782 };
2823 }; 2783 };
2824 2784
2825 debug@3810000 { 2785 debug@3810000 {
2826 compatible = "arm,cor 2786 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2827 reg = <0x3810000 0x10 2787 reg = <0x3810000 0x1000>;
2828 2788
2829 clocks = <&rpmcc RPM_ 2789 clocks = <&rpmcc RPM_QDSS_CLK>;
2830 clock-names = "apb_pc 2790 clock-names = "apb_pclk";
2831 2791
2832 cpu = <&CPU0>; 2792 cpu = <&CPU0>;
2833 }; 2793 };
2834 2794
2835 etm@3840000 { 2795 etm@3840000 {
2836 compatible = "arm,cor 2796 compatible = "arm,coresight-etm4x", "arm,primecell";
2837 reg = <0x3840000 0x10 2797 reg = <0x3840000 0x1000>;
2838 2798
2839 clocks = <&rpmcc RPM_ 2799 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2840 clock-names = "apb_pc 2800 clock-names = "apb_pclk", "atclk";
2841 2801
2842 cpu = <&CPU0>; 2802 cpu = <&CPU0>;
2843 2803
2844 out-ports { 2804 out-ports {
2845 port { 2805 port {
2846 etm0_ 2806 etm0_out: endpoint {
2847 2807 remote-endpoint =
2848 2808 <&apss_funnel0_in0>;
2849 }; 2809 };
2850 }; 2810 };
2851 }; 2811 };
2852 }; 2812 };
2853 2813
2854 debug@3910000 { 2814 debug@3910000 {
2855 compatible = "arm,cor 2815 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2856 reg = <0x3910000 0x10 2816 reg = <0x3910000 0x1000>;
2857 2817
2858 clocks = <&rpmcc RPM_ 2818 clocks = <&rpmcc RPM_QDSS_CLK>;
2859 clock-names = "apb_pc 2819 clock-names = "apb_pclk";
2860 2820
2861 cpu = <&CPU1>; 2821 cpu = <&CPU1>;
2862 }; 2822 };
2863 2823
2864 etm@3940000 { 2824 etm@3940000 {
2865 compatible = "arm,cor 2825 compatible = "arm,coresight-etm4x", "arm,primecell";
2866 reg = <0x3940000 0x10 2826 reg = <0x3940000 0x1000>;
2867 2827
2868 clocks = <&rpmcc RPM_ 2828 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2869 clock-names = "apb_pc 2829 clock-names = "apb_pclk", "atclk";
2870 2830
2871 cpu = <&CPU1>; 2831 cpu = <&CPU1>;
2872 2832
2873 out-ports { 2833 out-ports {
2874 port { 2834 port {
2875 etm1_ 2835 etm1_out: endpoint {
2876 2836 remote-endpoint =
2877 2837 <&apss_funnel0_in1>;
2878 }; 2838 };
2879 }; 2839 };
2880 }; 2840 };
2881 }; 2841 };
2882 2842
2883 funnel@39b0000 { /* APSS Funn 2843 funnel@39b0000 { /* APSS Funnel 0 */
2884 compatible = "arm,cor 2844 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2885 reg = <0x39b0000 0x10 2845 reg = <0x39b0000 0x1000>;
2886 2846
2887 clocks = <&rpmcc RPM_ 2847 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2888 clock-names = "apb_pc 2848 clock-names = "apb_pclk", "atclk";
2889 2849
2890 in-ports { 2850 in-ports {
2891 #address-cell 2851 #address-cells = <1>;
2892 #size-cells = 2852 #size-cells = <0>;
2893 2853
2894 port@0 { 2854 port@0 {
2895 reg = 2855 reg = <0>;
2896 apss_ 2856 apss_funnel0_in0: endpoint {
2897 2857 remote-endpoint = <&etm0_out>;
2898 }; 2858 };
2899 }; 2859 };
2900 2860
2901 port@1 { 2861 port@1 {
2902 reg = 2862 reg = <1>;
2903 apss_ 2863 apss_funnel0_in1: endpoint {
2904 2864 remote-endpoint = <&etm1_out>;
2905 }; 2865 };
2906 }; 2866 };
2907 }; 2867 };
2908 2868
2909 out-ports { 2869 out-ports {
2910 port { 2870 port {
2911 apss_ 2871 apss_funnel0_out: endpoint {
2912 2872 remote-endpoint =
2913 2873 <&apss_merge_funnel_in0>;
2914 }; 2874 };
2915 }; 2875 };
2916 }; 2876 };
2917 }; 2877 };
2918 2878
2919 debug@3a10000 { 2879 debug@3a10000 {
2920 compatible = "arm,cor 2880 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2921 reg = <0x3a10000 0x10 2881 reg = <0x3a10000 0x1000>;
2922 2882
2923 clocks = <&rpmcc RPM_ 2883 clocks = <&rpmcc RPM_QDSS_CLK>;
2924 clock-names = "apb_pc 2884 clock-names = "apb_pclk";
2925 2885
2926 cpu = <&CPU2>; 2886 cpu = <&CPU2>;
2927 }; 2887 };
2928 2888
2929 etm@3a40000 { 2889 etm@3a40000 {
2930 compatible = "arm,cor 2890 compatible = "arm,coresight-etm4x", "arm,primecell";
2931 reg = <0x3a40000 0x10 2891 reg = <0x3a40000 0x1000>;
2932 2892
2933 clocks = <&rpmcc RPM_ 2893 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2934 clock-names = "apb_pc 2894 clock-names = "apb_pclk", "atclk";
2935 2895
2936 cpu = <&CPU2>; 2896 cpu = <&CPU2>;
2937 2897
2938 out-ports { 2898 out-ports {
2939 port { 2899 port {
2940 etm2_ 2900 etm2_out: endpoint {
2941 2901 remote-endpoint =
2942 2902 <&apss_funnel1_in0>;
2943 }; 2903 };
2944 }; 2904 };
2945 }; 2905 };
2946 }; 2906 };
2947 2907
2948 debug@3b10000 { 2908 debug@3b10000 {
2949 compatible = "arm,cor 2909 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2950 reg = <0x3b10000 0x10 2910 reg = <0x3b10000 0x1000>;
2951 2911
2952 clocks = <&rpmcc RPM_ 2912 clocks = <&rpmcc RPM_QDSS_CLK>;
2953 clock-names = "apb_pc 2913 clock-names = "apb_pclk";
2954 2914
2955 cpu = <&CPU3>; 2915 cpu = <&CPU3>;
2956 }; 2916 };
2957 2917
2958 etm@3b40000 { 2918 etm@3b40000 {
2959 compatible = "arm,cor 2919 compatible = "arm,coresight-etm4x", "arm,primecell";
2960 reg = <0x3b40000 0x10 2920 reg = <0x3b40000 0x1000>;
2961 2921
2962 clocks = <&rpmcc RPM_ 2922 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2963 clock-names = "apb_pc 2923 clock-names = "apb_pclk", "atclk";
2964 2924
2965 cpu = <&CPU3>; 2925 cpu = <&CPU3>;
2966 2926
2967 out-ports { 2927 out-ports {
2968 port { 2928 port {
2969 etm3_ 2929 etm3_out: endpoint {
2970 2930 remote-endpoint =
2971 2931 <&apss_funnel1_in1>;
2972 }; 2932 };
2973 }; 2933 };
2974 }; 2934 };
2975 }; 2935 };
2976 2936
2977 funnel@3bb0000 { /* APSS Funn 2937 funnel@3bb0000 { /* APSS Funnel 1 */
2978 compatible = "arm,cor 2938 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2979 reg = <0x3bb0000 0x10 2939 reg = <0x3bb0000 0x1000>;
2980 2940
2981 clocks = <&rpmcc RPM_ 2941 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2982 clock-names = "apb_pc 2942 clock-names = "apb_pclk", "atclk";
2983 2943
2984 in-ports { 2944 in-ports {
2985 #address-cell 2945 #address-cells = <1>;
2986 #size-cells = 2946 #size-cells = <0>;
2987 2947
2988 port@0 { 2948 port@0 {
2989 reg = 2949 reg = <0>;
2990 apss_ 2950 apss_funnel1_in0: endpoint {
2991 2951 remote-endpoint = <&etm2_out>;
2992 }; 2952 };
2993 }; 2953 };
2994 2954
2995 port@1 { 2955 port@1 {
2996 reg = 2956 reg = <1>;
2997 apss_ 2957 apss_funnel1_in1: endpoint {
2998 2958 remote-endpoint = <&etm3_out>;
2999 }; 2959 };
3000 }; 2960 };
3001 }; 2961 };
3002 2962
3003 out-ports { 2963 out-ports {
3004 port { 2964 port {
3005 apss_ 2965 apss_funnel1_out: endpoint {
3006 2966 remote-endpoint =
3007 2967 <&apss_merge_funnel_in1>;
3008 }; 2968 };
3009 }; 2969 };
3010 }; 2970 };
3011 }; 2971 };
3012 2972
3013 funnel@3bc0000 { 2973 funnel@3bc0000 {
3014 compatible = "arm,cor 2974 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3015 reg = <0x3bc0000 0x10 2975 reg = <0x3bc0000 0x1000>;
3016 2976
3017 clocks = <&rpmcc RPM_ 2977 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
3018 clock-names = "apb_pc 2978 clock-names = "apb_pclk", "atclk";
3019 2979
3020 in-ports { 2980 in-ports {
3021 #address-cell 2981 #address-cells = <1>;
3022 #size-cells = 2982 #size-cells = <0>;
3023 2983
3024 port@0 { 2984 port@0 {
3025 reg = 2985 reg = <0>;
3026 apss_ 2986 apss_merge_funnel_in0: endpoint {
3027 2987 remote-endpoint =
3028 2988 <&apss_funnel0_out>;
3029 }; 2989 };
3030 }; 2990 };
3031 2991
3032 port@1 { 2992 port@1 {
3033 reg = 2993 reg = <1>;
3034 apss_ 2994 apss_merge_funnel_in1: endpoint {
3035 2995 remote-endpoint =
3036 2996 <&apss_funnel1_out>;
3037 }; 2997 };
3038 }; 2998 };
3039 }; 2999 };
3040 3000
3041 out-ports { 3001 out-ports {
3042 port { 3002 port {
3043 apss_ 3003 apss_merge_funnel_out: endpoint {
3044 3004 remote-endpoint =
3045 3005 <&funnel1_in>;
3046 }; 3006 };
3047 }; 3007 };
3048 }; 3008 };
3049 }; 3009 };
3050 3010
3051 kryocc: clock-controller@6400 3011 kryocc: clock-controller@6400000 {
3052 compatible = "qcom,ms 3012 compatible = "qcom,msm8996-apcc";
3053 reg = <0x06400000 0x9 3013 reg = <0x06400000 0x90000>;
3054 3014
3055 clock-names = "xo", " 3015 clock-names = "xo", "sys_apcs_aux";
3056 clocks = <&rpmcc RPM_ 3016 clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>, <&apcs_glb>;
3057 3017
3058 #clock-cells = <1>; 3018 #clock-cells = <1>;
3059 }; 3019 };
3060 3020
3061 usb3: usb@6af8800 { 3021 usb3: usb@6af8800 {
3062 compatible = "qcom,ms 3022 compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
3063 reg = <0x06af8800 0x4 3023 reg = <0x06af8800 0x400>;
3064 #address-cells = <1>; 3024 #address-cells = <1>;
3065 #size-cells = <1>; 3025 #size-cells = <1>;
3066 ranges; 3026 ranges;
3067 3027
3068 interrupts = <GIC_SPI 3028 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
3069 <GIC_SPI 3029 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
3070 interrupt-names = "hs 3030 interrupt-names = "hs_phy_irq", "ss_phy_irq";
3071 3031
3072 clocks = <&gcc GCC_SY 3032 clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
3073 <&gcc GCC_US 3033 <&gcc GCC_USB30_MASTER_CLK>,
3074 <&gcc GCC_AG 3034 <&gcc GCC_AGGRE2_USB3_AXI_CLK>,
3075 <&gcc GCC_US 3035 <&gcc GCC_USB30_SLEEP_CLK>,
3076 <&gcc GCC_US 3036 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
3077 clock-names = "cfg_no 3037 clock-names = "cfg_noc",
3078 "core", 3038 "core",
3079 "iface" 3039 "iface",
3080 "sleep" 3040 "sleep",
3081 "mock_u 3041 "mock_utmi";
3082 3042
3083 assigned-clocks = <&g 3043 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
3084 <&g 3044 <&gcc GCC_USB30_MASTER_CLK>;
3085 assigned-clock-rates 3045 assigned-clock-rates = <19200000>, <120000000>;
3086 3046
3087 interconnects = <&a2n 3047 interconnects = <&a2noc MASTER_USB3 &bimc SLAVE_EBI_CH0>,
3088 <&bim 3048 <&bimc MASTER_AMPSS_M0 &snoc SLAVE_USB3>;
3089 interconnect-names = 3049 interconnect-names = "usb-ddr", "apps-usb";
3090 3050
3091 power-domains = <&gcc 3051 power-domains = <&gcc USB30_GDSC>;
3092 status = "disabled"; 3052 status = "disabled";
3093 3053
3094 usb3_dwc3: usb@6a0000 3054 usb3_dwc3: usb@6a00000 {
3095 compatible = 3055 compatible = "snps,dwc3";
3096 reg = <0x06a0 3056 reg = <0x06a00000 0xcc00>;
3097 interrupts = 3057 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
3098 phys = <&hsus 3058 phys = <&hsusb_phy1>, <&usb3phy>;
3099 phy-names = " 3059 phy-names = "usb2-phy", "usb3-phy";
3100 snps,hird-thr 3060 snps,hird-threshold = /bits/ 8 <0>;
3101 snps,dis_u2_s 3061 snps,dis_u2_susphy_quirk;
3102 snps,dis_enbl 3062 snps,dis_enblslpm_quirk;
3103 snps,is-utmi- 3063 snps,is-utmi-l1-suspend;
3104 snps,parkmode 3064 snps,parkmode-disable-ss-quirk;
3105 tx-fifo-resiz 3065 tx-fifo-resize;
3106 }; 3066 };
3107 }; 3067 };
3108 3068
3109 usb3phy: phy@7410000 { 3069 usb3phy: phy@7410000 {
3110 compatible = "qcom,ms 3070 compatible = "qcom,msm8996-qmp-usb3-phy";
3111 reg = <0x07410000 0x1 3071 reg = <0x07410000 0x1000>;
3112 3072
3113 clocks = <&gcc GCC_US 3073 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
3114 <&gcc GCC_US 3074 <&gcc GCC_USB3_CLKREF_CLK>,
3115 <&gcc GCC_US 3075 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3116 <&gcc GCC_US 3076 <&gcc GCC_USB3_PHY_PIPE_CLK>;
3117 clock-names = "aux", 3077 clock-names = "aux",
3118 "ref", 3078 "ref",
3119 "cfg_ah 3079 "cfg_ahb",
3120 "pipe"; 3080 "pipe";
3121 clock-output-names = 3081 clock-output-names = "usb3_phy_pipe_clk_src";
3122 #clock-cells = <0>; 3082 #clock-cells = <0>;
3123 #phy-cells = <0>; 3083 #phy-cells = <0>;
3124 3084
3125 resets = <&gcc GCC_US 3085 resets = <&gcc GCC_USB3_PHY_BCR>,
3126 <&gcc GCC_US 3086 <&gcc GCC_USB3PHY_PHY_BCR>;
3127 reset-names = "phy", 3087 reset-names = "phy",
3128 "phy_ph 3088 "phy_phy";
3129 3089
3130 status = "disabled"; 3090 status = "disabled";
3131 }; 3091 };
3132 3092
3133 hsusb_phy1: phy@7411000 { 3093 hsusb_phy1: phy@7411000 {
3134 compatible = "qcom,ms 3094 compatible = "qcom,msm8996-qusb2-phy";
3135 reg = <0x07411000 0x1 3095 reg = <0x07411000 0x180>;
3136 #phy-cells = <0>; 3096 #phy-cells = <0>;
3137 3097
3138 clocks = <&gcc GCC_US 3098 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3139 <&gcc GCC_RX1 3099 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
3140 clock-names = "cfg_ah 3100 clock-names = "cfg_ahb", "ref";
3141 3101
3142 resets = <&gcc GCC_QU 3102 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3143 nvmem-cells = <&qusb2 3103 nvmem-cells = <&qusb2p_hstx_trim>;
3144 status = "disabled"; 3104 status = "disabled";
3145 }; 3105 };
3146 3106
3147 hsusb_phy2: phy@7412000 { 3107 hsusb_phy2: phy@7412000 {
3148 compatible = "qcom,ms 3108 compatible = "qcom,msm8996-qusb2-phy";
3149 reg = <0x07412000 0x1 3109 reg = <0x07412000 0x180>;
3150 #phy-cells = <0>; 3110 #phy-cells = <0>;
3151 3111
3152 clocks = <&gcc GCC_US 3112 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3153 <&gcc GCC_RX2 3113 <&gcc GCC_RX2_USB2_CLKREF_CLK>;
3154 clock-names = "cfg_ah 3114 clock-names = "cfg_ahb", "ref";
3155 3115
3156 resets = <&gcc GCC_QU 3116 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3157 nvmem-cells = <&qusb2 3117 nvmem-cells = <&qusb2s_hstx_trim>;
3158 status = "disabled"; 3118 status = "disabled";
3159 }; 3119 };
3160 3120
3161 sdhc1: mmc@7464900 { 3121 sdhc1: mmc@7464900 {
3162 compatible = "qcom,ms 3122 compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4";
3163 reg = <0x07464900 0x1 3123 reg = <0x07464900 0x11c>, <0x07464000 0x800>;
3164 reg-names = "hc", "co 3124 reg-names = "hc", "core";
3165 3125
3166 interrupts = <GIC_SPI 3126 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
3167 <GIC_ 3127 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
3168 interrupt-names = "hc 3128 interrupt-names = "hc_irq", "pwr_irq";
3169 3129
3170 clock-names = "iface" 3130 clock-names = "iface", "core", "xo";
3171 clocks = <&gcc GCC_SD 3131 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
3172 <&gcc GCC_SDC 3132 <&gcc GCC_SDCC1_APPS_CLK>,
3173 <&rpmcc RPM_S 3133 <&rpmcc RPM_SMD_XO_CLK_SRC>;
3174 resets = <&gcc GCC_SD 3134 resets = <&gcc GCC_SDCC1_BCR>;
3175 3135
3176 pinctrl-names = "defa 3136 pinctrl-names = "default", "sleep";
3177 pinctrl-0 = <&sdc1_st 3137 pinctrl-0 = <&sdc1_state_on>;
3178 pinctrl-1 = <&sdc1_st 3138 pinctrl-1 = <&sdc1_state_off>;
3179 3139
3180 bus-width = <8>; 3140 bus-width = <8>;
3181 non-removable; 3141 non-removable;
3182 status = "disabled"; 3142 status = "disabled";
3183 }; 3143 };
3184 3144
3185 sdhc2: mmc@74a4900 { 3145 sdhc2: mmc@74a4900 {
3186 compatible = "qcom,ms 3146 compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4";
3187 reg = <0x074a4900 0x3 3147 reg = <0x074a4900 0x314>, <0x074a4000 0x800>;
3188 reg-names = "hc", "co 3148 reg-names = "hc", "core";
3189 3149
3190 interrupts = <GIC_SPI 3150 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
3191 <GIC_SP 3151 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
3192 interrupt-names = "hc 3152 interrupt-names = "hc_irq", "pwr_irq";
3193 3153
3194 clock-names = "iface" 3154 clock-names = "iface", "core", "xo";
3195 clocks = <&gcc GCC_SD 3155 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3196 <&gcc GCC_SDC 3156 <&gcc GCC_SDCC2_APPS_CLK>,
3197 <&rpmcc RPM_S 3157 <&rpmcc RPM_SMD_XO_CLK_SRC>;
3198 resets = <&gcc GCC_SD 3158 resets = <&gcc GCC_SDCC2_BCR>;
3199 3159
3200 pinctrl-names = "defa 3160 pinctrl-names = "default", "sleep";
3201 pinctrl-0 = <&sdc2_st 3161 pinctrl-0 = <&sdc2_state_on>;
3202 pinctrl-1 = <&sdc2_st 3162 pinctrl-1 = <&sdc2_state_off>;
3203 3163
3204 bus-width = <4>; 3164 bus-width = <4>;
3205 status = "disabled"; 3165 status = "disabled";
3206 }; 3166 };
3207 3167
3208 blsp1_dma: dma-controller@754 3168 blsp1_dma: dma-controller@7544000 {
3209 compatible = "qcom,ba 3169 compatible = "qcom,bam-v1.7.0";
3210 reg = <0x07544000 0x2 3170 reg = <0x07544000 0x2b000>;
3211 interrupts = <GIC_SPI 3171 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
3212 clocks = <&gcc GCC_BL 3172 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
3213 clock-names = "bam_cl 3173 clock-names = "bam_clk";
3214 qcom,controlled-remot 3174 qcom,controlled-remotely;
3215 #dma-cells = <1>; 3175 #dma-cells = <1>;
3216 qcom,ee = <0>; 3176 qcom,ee = <0>;
3217 }; 3177 };
3218 3178
3219 blsp1_uart2: serial@7570000 { 3179 blsp1_uart2: serial@7570000 {
3220 compatible = "qcom,ms 3180 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
3221 reg = <0x07570000 0x1 3181 reg = <0x07570000 0x1000>;
3222 interrupts = <GIC_SPI 3182 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
3223 clocks = <&gcc GCC_BL 3183 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
3224 <&gcc GCC_BL 3184 <&gcc GCC_BLSP1_AHB_CLK>;
3225 clock-names = "core", 3185 clock-names = "core", "iface";
3226 pinctrl-names = "defa 3186 pinctrl-names = "default", "sleep";
3227 pinctrl-0 = <&blsp1_u 3187 pinctrl-0 = <&blsp1_uart2_default>;
3228 pinctrl-1 = <&blsp1_u 3188 pinctrl-1 = <&blsp1_uart2_sleep>;
3229 dmas = <&blsp1_dma 2> 3189 dmas = <&blsp1_dma 2>, <&blsp1_dma 3>;
3230 dma-names = "tx", "rx 3190 dma-names = "tx", "rx";
3231 status = "disabled"; 3191 status = "disabled";
3232 }; 3192 };
3233 3193
3234 blsp1_spi1: spi@7575000 { 3194 blsp1_spi1: spi@7575000 {
3235 compatible = "qcom,sp 3195 compatible = "qcom,spi-qup-v2.2.1";
3236 reg = <0x07575000 0x6 3196 reg = <0x07575000 0x600>;
3237 interrupts = <GIC_SPI 3197 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
3238 clocks = <&gcc GCC_BL 3198 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
3239 <&gcc GCC_BL 3199 <&gcc GCC_BLSP1_AHB_CLK>;
3240 clock-names = "core", 3200 clock-names = "core", "iface";
3241 pinctrl-names = "defa 3201 pinctrl-names = "default", "sleep";
3242 pinctrl-0 = <&blsp1_s 3202 pinctrl-0 = <&blsp1_spi1_default>;
3243 pinctrl-1 = <&blsp1_s 3203 pinctrl-1 = <&blsp1_spi1_sleep>;
3244 dmas = <&blsp1_dma 12 3204 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
3245 dma-names = "tx", "rx 3205 dma-names = "tx", "rx";
3246 #address-cells = <1>; 3206 #address-cells = <1>;
3247 #size-cells = <0>; 3207 #size-cells = <0>;
3248 status = "disabled"; 3208 status = "disabled";
3249 }; 3209 };
3250 3210
3251 blsp1_i2c3: i2c@7577000 { 3211 blsp1_i2c3: i2c@7577000 {
3252 compatible = "qcom,i2 3212 compatible = "qcom,i2c-qup-v2.2.1";
3253 reg = <0x07577000 0x1 3213 reg = <0x07577000 0x1000>;
3254 interrupts = <GIC_SPI 3214 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
3255 clocks = <&gcc GCC_BL 3215 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
3256 <&gcc GCC_BL 3216 <&gcc GCC_BLSP1_AHB_CLK>;
3257 clock-names = "core", 3217 clock-names = "core", "iface";
3258 pinctrl-names = "defa 3218 pinctrl-names = "default", "sleep";
3259 pinctrl-0 = <&blsp1_i 3219 pinctrl-0 = <&blsp1_i2c3_default>;
3260 pinctrl-1 = <&blsp1_i 3220 pinctrl-1 = <&blsp1_i2c3_sleep>;
3261 dmas = <&blsp1_dma 16 3221 dmas = <&blsp1_dma 16>, <&blsp1_dma 17>;
3262 dma-names = "tx", "rx 3222 dma-names = "tx", "rx";
3263 #address-cells = <1>; 3223 #address-cells = <1>;
3264 #size-cells = <0>; 3224 #size-cells = <0>;
3265 status = "disabled"; 3225 status = "disabled";
3266 }; 3226 };
3267 3227
3268 blsp1_i2c6: i2c@757a000 { 3228 blsp1_i2c6: i2c@757a000 {
3269 compatible = "qcom,i2 3229 compatible = "qcom,i2c-qup-v2.2.1";
3270 reg = <0x757a000 0x10 3230 reg = <0x757a000 0x1000>;
3271 interrupts = <GIC_SPI 3231 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
3272 clocks = <&gcc GCC_BL 3232 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
3273 <&gcc GCC_BL 3233 <&gcc GCC_BLSP1_AHB_CLK>;
3274 clock-names = "core", 3234 clock-names = "core", "iface";
3275 pinctrl-names = "defa 3235 pinctrl-names = "default", "sleep";
3276 pinctrl-0 = <&blsp1_i 3236 pinctrl-0 = <&blsp1_i2c6_default>;
3277 pinctrl-1 = <&blsp1_i 3237 pinctrl-1 = <&blsp1_i2c6_sleep>;
3278 dmas = <&blsp1_dma 22 3238 dmas = <&blsp1_dma 22>, <&blsp1_dma 23>;
3279 dma-names = "tx", "rx 3239 dma-names = "tx", "rx";
3280 #address-cells = <1>; 3240 #address-cells = <1>;
3281 #size-cells = <0>; 3241 #size-cells = <0>;
3282 status = "disabled"; 3242 status = "disabled";
3283 }; 3243 };
3284 3244
3285 blsp2_dma: dma-controller@758 3245 blsp2_dma: dma-controller@7584000 {
3286 compatible = "qcom,ba 3246 compatible = "qcom,bam-v1.7.0";
3287 reg = <0x07584000 0x2 3247 reg = <0x07584000 0x2b000>;
3288 interrupts = <GIC_SPI 3248 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
3289 clocks = <&gcc GCC_BL 3249 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
3290 clock-names = "bam_cl 3250 clock-names = "bam_clk";
3291 qcom,controlled-remot 3251 qcom,controlled-remotely;
3292 #dma-cells = <1>; 3252 #dma-cells = <1>;
3293 qcom,ee = <0>; 3253 qcom,ee = <0>;
3294 }; 3254 };
3295 3255
3296 blsp2_uart2: serial@75b0000 { 3256 blsp2_uart2: serial@75b0000 {
3297 compatible = "qcom,ms 3257 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
3298 reg = <0x075b0000 0x1 3258 reg = <0x075b0000 0x1000>;
3299 interrupts = <GIC_SPI 3259 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
3300 clocks = <&gcc GCC_BL 3260 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
3301 <&gcc GCC_BL 3261 <&gcc GCC_BLSP2_AHB_CLK>;
3302 clock-names = "core", 3262 clock-names = "core", "iface";
3303 status = "disabled"; 3263 status = "disabled";
3304 }; 3264 };
3305 3265
3306 blsp2_uart3: serial@75b1000 { 3266 blsp2_uart3: serial@75b1000 {
3307 compatible = "qcom,ms 3267 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
3308 reg = <0x075b1000 0x1 3268 reg = <0x075b1000 0x1000>;
3309 interrupts = <GIC_SPI 3269 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
3310 clocks = <&gcc GCC_BL 3270 clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>,
3311 <&gcc GCC_BL 3271 <&gcc GCC_BLSP2_AHB_CLK>;
3312 clock-names = "core", 3272 clock-names = "core", "iface";
3313 status = "disabled"; 3273 status = "disabled";
3314 }; 3274 };
3315 3275
3316 blsp2_i2c1: i2c@75b5000 { 3276 blsp2_i2c1: i2c@75b5000 {
3317 compatible = "qcom,i2 3277 compatible = "qcom,i2c-qup-v2.2.1";
3318 reg = <0x075b5000 0x1 3278 reg = <0x075b5000 0x1000>;
3319 interrupts = <GIC_SPI 3279 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
3320 clocks = <&gcc GCC_BL 3280 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
3321 <&gcc GCC_BL 3281 <&gcc GCC_BLSP2_AHB_CLK>;
3322 clock-names = "core", 3282 clock-names = "core", "iface";
3323 pinctrl-names = "defa 3283 pinctrl-names = "default", "sleep";
3324 pinctrl-0 = <&blsp2_i 3284 pinctrl-0 = <&blsp2_i2c1_default>;
3325 pinctrl-1 = <&blsp2_i 3285 pinctrl-1 = <&blsp2_i2c1_sleep>;
3326 dmas = <&blsp2_dma 12 3286 dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
3327 dma-names = "tx", "rx 3287 dma-names = "tx", "rx";
3328 #address-cells = <1>; 3288 #address-cells = <1>;
3329 #size-cells = <0>; 3289 #size-cells = <0>;
3330 status = "disabled"; 3290 status = "disabled";
3331 }; 3291 };
3332 3292
3333 blsp2_i2c2: i2c@75b6000 { 3293 blsp2_i2c2: i2c@75b6000 {
3334 compatible = "qcom,i2 3294 compatible = "qcom,i2c-qup-v2.2.1";
3335 reg = <0x075b6000 0x1 3295 reg = <0x075b6000 0x1000>;
3336 interrupts = <GIC_SPI 3296 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
3337 clocks = <&gcc GCC_BL 3297 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
3338 <&gcc GCC_BL 3298 <&gcc GCC_BLSP2_AHB_CLK>;
3339 clock-names = "core", 3299 clock-names = "core", "iface";
3340 pinctrl-names = "defa 3300 pinctrl-names = "default", "sleep";
3341 pinctrl-0 = <&blsp2_i 3301 pinctrl-0 = <&blsp2_i2c2_default>;
3342 pinctrl-1 = <&blsp2_i 3302 pinctrl-1 = <&blsp2_i2c2_sleep>;
3343 dmas = <&blsp2_dma 14 3303 dmas = <&blsp2_dma 14>, <&blsp2_dma 15>;
3344 dma-names = "tx", "rx 3304 dma-names = "tx", "rx";
3345 #address-cells = <1>; 3305 #address-cells = <1>;
3346 #size-cells = <0>; 3306 #size-cells = <0>;
3347 status = "disabled"; 3307 status = "disabled";
3348 }; 3308 };
3349 3309
3350 blsp2_i2c3: i2c@75b7000 { 3310 blsp2_i2c3: i2c@75b7000 {
3351 compatible = "qcom,i2 3311 compatible = "qcom,i2c-qup-v2.2.1";
3352 reg = <0x075b7000 0x1 3312 reg = <0x075b7000 0x1000>;
3353 interrupts = <GIC_SPI 3313 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
3354 clocks = <&gcc GCC_BL 3314 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
3355 <&gcc GCC_BL 3315 <&gcc GCC_BLSP2_AHB_CLK>;
3356 clock-names = "core", 3316 clock-names = "core", "iface";
3357 clock-frequency = <40 3317 clock-frequency = <400000>;
3358 pinctrl-names = "defa 3318 pinctrl-names = "default", "sleep";
3359 pinctrl-0 = <&blsp2_i 3319 pinctrl-0 = <&blsp2_i2c3_default>;
3360 pinctrl-1 = <&blsp2_i 3320 pinctrl-1 = <&blsp2_i2c3_sleep>;
3361 dmas = <&blsp2_dma 16 3321 dmas = <&blsp2_dma 16>, <&blsp2_dma 17>;
3362 dma-names = "tx", "rx 3322 dma-names = "tx", "rx";
3363 #address-cells = <1>; 3323 #address-cells = <1>;
3364 #size-cells = <0>; 3324 #size-cells = <0>;
3365 status = "disabled"; 3325 status = "disabled";
3366 }; 3326 };
3367 3327
3368 blsp2_i2c5: i2c@75b9000 { 3328 blsp2_i2c5: i2c@75b9000 {
3369 compatible = "qcom,i2 3329 compatible = "qcom,i2c-qup-v2.2.1";
3370 reg = <0x75b9000 0x10 3330 reg = <0x75b9000 0x1000>;
3371 interrupts = <GIC_SPI 3331 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
3372 clocks = <&gcc GCC_BL 3332 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,
3373 <&gcc GCC_BL 3333 <&gcc GCC_BLSP2_AHB_CLK>;
3374 clock-names = "core", 3334 clock-names = "core", "iface";
3375 pinctrl-names = "defa 3335 pinctrl-names = "default";
3376 pinctrl-0 = <&blsp2_i 3336 pinctrl-0 = <&blsp2_i2c5_default>;
3377 dmas = <&blsp2_dma 20 3337 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
3378 dma-names = "tx", "rx 3338 dma-names = "tx", "rx";
3379 #address-cells = <1>; 3339 #address-cells = <1>;
3380 #size-cells = <0>; 3340 #size-cells = <0>;
3381 status = "disabled"; 3341 status = "disabled";
3382 }; 3342 };
3383 3343
3384 blsp2_i2c6: i2c@75ba000 { 3344 blsp2_i2c6: i2c@75ba000 {
3385 compatible = "qcom,i2 3345 compatible = "qcom,i2c-qup-v2.2.1";
3386 reg = <0x75ba000 0x10 3346 reg = <0x75ba000 0x1000>;
3387 interrupts = <GIC_SPI 3347 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
3388 clocks = <&gcc GCC_BL 3348 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>,
3389 <&gcc GCC_BL 3349 <&gcc GCC_BLSP2_AHB_CLK>;
3390 clock-names = "core", 3350 clock-names = "core", "iface";
3391 pinctrl-names = "defa 3351 pinctrl-names = "default", "sleep";
3392 pinctrl-0 = <&blsp2_i 3352 pinctrl-0 = <&blsp2_i2c6_default>;
3393 pinctrl-1 = <&blsp2_i 3353 pinctrl-1 = <&blsp2_i2c6_sleep>;
3394 dmas = <&blsp2_dma 22 3354 dmas = <&blsp2_dma 22>, <&blsp2_dma 23>;
3395 dma-names = "tx", "rx 3355 dma-names = "tx", "rx";
3396 #address-cells = <1>; 3356 #address-cells = <1>;
3397 #size-cells = <0>; 3357 #size-cells = <0>;
3398 status = "disabled"; 3358 status = "disabled";
3399 }; 3359 };
3400 3360
3401 blsp2_spi6: spi@75ba000 { 3361 blsp2_spi6: spi@75ba000 {
3402 compatible = "qcom,sp 3362 compatible = "qcom,spi-qup-v2.2.1";
3403 reg = <0x075ba000 0x6 3363 reg = <0x075ba000 0x600>;
3404 interrupts = <GIC_SPI 3364 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
3405 clocks = <&gcc GCC_BL 3365 clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>,
3406 <&gcc GCC_BL 3366 <&gcc GCC_BLSP2_AHB_CLK>;
3407 clock-names = "core", 3367 clock-names = "core", "iface";
3408 pinctrl-names = "defa 3368 pinctrl-names = "default", "sleep";
3409 pinctrl-0 = <&blsp2_s 3369 pinctrl-0 = <&blsp2_spi6_default>;
3410 pinctrl-1 = <&blsp2_s 3370 pinctrl-1 = <&blsp2_spi6_sleep>;
3411 dmas = <&blsp2_dma 22 3371 dmas = <&blsp2_dma 22>, <&blsp2_dma 23>;
3412 dma-names = "tx", "rx 3372 dma-names = "tx", "rx";
3413 #address-cells = <1>; 3373 #address-cells = <1>;
3414 #size-cells = <0>; 3374 #size-cells = <0>;
3415 status = "disabled"; 3375 status = "disabled";
3416 }; 3376 };
3417 3377
3418 usb2: usb@76f8800 { 3378 usb2: usb@76f8800 {
3419 compatible = "qcom,ms 3379 compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
3420 reg = <0x076f8800 0x4 3380 reg = <0x076f8800 0x400>;
3421 #address-cells = <1>; 3381 #address-cells = <1>;
3422 #size-cells = <1>; 3382 #size-cells = <1>;
3423 ranges; 3383 ranges;
3424 3384
3425 interrupts = <GIC_SPI 3385 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
3426 <GIC_SPI 3386 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
3427 <GIC_SPI 3387 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
3428 interrupt-names = "pw 3388 interrupt-names = "pwr_event",
3429 "qu 3389 "qusb2_phy",
3430 "hs 3390 "hs_phy_irq";
3431 3391
3432 clocks = <&gcc GCC_PE 3392 clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>,
3433 <&gcc GCC_USB 3393 <&gcc GCC_USB20_MASTER_CLK>,
3434 <&gcc GCC_USB 3394 <&gcc GCC_USB20_MOCK_UTMI_CLK>,
3435 <&gcc GCC_USB 3395 <&gcc GCC_USB20_SLEEP_CLK>,
3436 <&gcc GCC_USB 3396 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
3437 clock-names = "cfg_no 3397 clock-names = "cfg_noc",
3438 "core", 3398 "core",
3439 "iface" 3399 "iface",
3440 "sleep" 3400 "sleep",
3441 "mock_u 3401 "mock_utmi";
3442 3402
3443 assigned-clocks = <&g 3403 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
3444 <&g 3404 <&gcc GCC_USB20_MASTER_CLK>;
3445 assigned-clock-rates 3405 assigned-clock-rates = <19200000>, <60000000>;
3446 3406
3447 power-domains = <&gcc 3407 power-domains = <&gcc USB30_GDSC>;
3448 qcom,select-utmi-as-p 3408 qcom,select-utmi-as-pipe-clk;
3449 status = "disabled"; 3409 status = "disabled";
3450 3410
3451 usb2_dwc3: usb@760000 3411 usb2_dwc3: usb@7600000 {
3452 compatible = 3412 compatible = "snps,dwc3";
3453 reg = <0x0760 3413 reg = <0x07600000 0xcc00>;
3454 interrupts = 3414 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
3455 phys = <&hsus 3415 phys = <&hsusb_phy2>;
3456 phy-names = " 3416 phy-names = "usb2-phy";
3457 maximum-speed 3417 maximum-speed = "high-speed";
3458 snps,dis_u2_s 3418 snps,dis_u2_susphy_quirk;
3459 snps,dis_enbl 3419 snps,dis_enblslpm_quirk;
3460 }; 3420 };
3461 }; 3421 };
3462 3422
3463 slimbam: dma-controller@91840 3423 slimbam: dma-controller@9184000 {
3464 compatible = "qcom,ba 3424 compatible = "qcom,bam-v1.7.0";
3465 qcom,controlled-remot 3425 qcom,controlled-remotely;
3466 reg = <0x09184000 0x3 3426 reg = <0x09184000 0x32000>;
3467 num-channels = <31>; 3427 num-channels = <31>;
3468 interrupts = <GIC_SPI 3428 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
3469 #dma-cells = <1>; 3429 #dma-cells = <1>;
3470 qcom,ee = <1>; 3430 qcom,ee = <1>;
3471 qcom,num-ees = <2>; 3431 qcom,num-ees = <2>;
3472 }; 3432 };
3473 3433
3474 slim_msm: slim-ngd@91c0000 { 3434 slim_msm: slim-ngd@91c0000 {
3475 compatible = "qcom,sl 3435 compatible = "qcom,slim-ngd-v1.5.0";
3476 reg = <0x091c0000 0x2 3436 reg = <0x091c0000 0x2c000>;
3477 interrupts = <GIC_SPI 3437 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
3478 dmas = <&slimbam 3>, 3438 dmas = <&slimbam 3>, <&slimbam 4>;
3479 dma-names = "rx", "tx 3439 dma-names = "rx", "tx";
3480 #address-cells = <1>; 3440 #address-cells = <1>;
3481 #size-cells = <0>; 3441 #size-cells = <0>;
3482 3442
3483 status = "disabled"; 3443 status = "disabled";
3484 }; 3444 };
3485 3445
3486 adsp_pil: remoteproc@9300000 3446 adsp_pil: remoteproc@9300000 {
3487 compatible = "qcom,ms 3447 compatible = "qcom,msm8996-adsp-pil";
3488 reg = <0x09300000 0x8 3448 reg = <0x09300000 0x80000>;
3489 3449
3490 interrupts-extended = 3450 interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
3491 3451 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3492 3452 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3493 3453 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3494 3454 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
3495 interrupt-names = "wd 3455 interrupt-names = "wdog", "fatal", "ready",
3496 "ha 3456 "handover", "stop-ack";
3497 3457
3498 clocks = <&rpmcc RPM_ 3458 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
3499 clock-names = "xo"; 3459 clock-names = "xo";
3500 3460
3501 memory-region = <&ads 3461 memory-region = <&adsp_mem>;
3502 3462
3503 qcom,smem-states = <& 3463 qcom,smem-states = <&adsp_smp2p_out 0>;
3504 qcom,smem-state-names 3464 qcom,smem-state-names = "stop";
3505 3465
3506 power-domains = <&rpm 3466 power-domains = <&rpmpd MSM8996_VDDCX>;
3507 power-domain-names = 3467 power-domain-names = "cx";
3508 3468
3509 status = "disabled"; 3469 status = "disabled";
3510 3470
3511 glink-edge { <<
3512 interrupts = <<
3513 label = "lpas <<
3514 qcom,remote-p <<
3515 mboxes = <&ap <<
3516 }; <<
3517 <<
3518 <<
3519 smd-edge { 3471 smd-edge {
3520 interrupts = 3472 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
3521 3473
3522 label = "lpas 3474 label = "lpass";
3523 mboxes = <&ap 3475 mboxes = <&apcs_glb 8>;
3524 qcom,smd-edge 3476 qcom,smd-edge = <1>;
3525 qcom,remote-p 3477 qcom,remote-pid = <2>;
3526 3478
3527 apr { 3479 apr {
3528 power 3480 power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>;
3529 compa 3481 compatible = "qcom,apr-v2";
3530 qcom, 3482 qcom,smd-channels = "apr_audio_svc";
3531 qcom, 3483 qcom,domain = <APR_DOMAIN_ADSP>;
3532 #addr 3484 #address-cells = <1>;
3533 #size 3485 #size-cells = <0>;
3534 3486
3535 servi 3487 service@3 {
3536 3488 reg = <APR_SVC_ADSP_CORE>;
3537 3489 compatible = "qcom,q6core";
3538 }; 3490 };
3539 3491
3540 q6afe 3492 q6afe: service@4 {
3541 3493 compatible = "qcom,q6afe";
3542 3494 reg = <APR_SVC_AFE>;
3543 3495 q6afedai: dais {
3544 3496 compatible = "qcom,q6afe-dais";
3545 3497 #address-cells = <1>;
3546 3498 #size-cells = <0>;
3547 3499 #sound-dai-cells = <1>;
3548 3500 dai@1 {
3549 3501 reg = <1>;
3550 3502 };
3551 3503 };
3552 }; 3504 };
3553 3505
3554 q6asm 3506 q6asm: service@7 {
3555 3507 compatible = "qcom,q6asm";
3556 3508 reg = <APR_SVC_ASM>;
3557 3509 q6asmdai: dais {
3558 3510 compatible = "qcom,q6asm-dais";
3559 3511 #address-cells = <1>;
3560 3512 #size-cells = <0>;
3561 3513 #sound-dai-cells = <1>;
3562 3514 iommus = <&lpass_q6_smmu 1>;
3563 3515 };
3564 }; 3516 };
3565 3517
3566 q6adm 3518 q6adm: service@8 {
3567 3519 compatible = "qcom,q6adm";
3568 3520 reg = <APR_SVC_ADM>;
3569 3521 q6routing: routing {
3570 3522 compatible = "qcom,q6adm-routing";
3571 3523 #sound-dai-cells = <0>;
3572 3524 };
3573 }; 3525 };
3574 }; 3526 };
3575 <<
3576 fastrpc { <<
3577 compa <<
3578 qcom, <<
3579 label <<
3580 qcom, <<
3581 #addr <<
3582 #size <<
3583 <<
3584 cb@5 <<
3585 <<
3586 <<
3587 <<
3588 }; <<
3589 <<
3590 cb@6 <<
3591 <<
3592 <<
3593 <<
3594 }; <<
3595 <<
3596 cb@7 <<
3597 <<
3598 <<
3599 <<
3600 }; <<
3601 <<
3602 cb@8 <<
3603 <<
3604 <<
3605 <<
3606 }; <<
3607 <<
3608 cb@9 <<
3609 <<
3610 <<
3611 <<
3612 }; <<
3613 <<
3614 cb@10 <<
3615 <<
3616 <<
3617 <<
3618 }; <<
3619 <<
3620 cb@11 <<
3621 <<
3622 <<
3623 <<
3624 }; <<
3625 <<
3626 cb@12 <<
3627 <<
3628 <<
3629 <<
3630 }; <<
3631 }; <<
3632 }; 3527 };
3633 }; 3528 };
3634 3529
3635 apcs_glb: mailbox@9820000 { 3530 apcs_glb: mailbox@9820000 {
3636 compatible = "qcom,ms 3531 compatible = "qcom,msm8996-apcs-hmss-global";
3637 reg = <0x09820000 0x1 3532 reg = <0x09820000 0x1000>;
3638 3533
3639 #mbox-cells = <1>; 3534 #mbox-cells = <1>;
3640 #clock-cells = <0>; 3535 #clock-cells = <0>;
3641 }; 3536 };
3642 3537
3643 timer@9840000 { 3538 timer@9840000 {
3644 #address-cells = <1>; 3539 #address-cells = <1>;
3645 #size-cells = <1>; 3540 #size-cells = <1>;
3646 ranges; 3541 ranges;
3647 compatible = "arm,arm 3542 compatible = "arm,armv7-timer-mem";
3648 reg = <0x09840000 0x1 3543 reg = <0x09840000 0x1000>;
3649 clock-frequency = <19 3544 clock-frequency = <19200000>;
3650 3545
3651 frame@9850000 { 3546 frame@9850000 {
3652 frame-number 3547 frame-number = <0>;
3653 interrupts = 3548 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
3654 3549 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
3655 reg = <0x0985 3550 reg = <0x09850000 0x1000>,
3656 <0x0986 3551 <0x09860000 0x1000>;
3657 }; 3552 };
3658 3553
3659 frame@9870000 { 3554 frame@9870000 {
3660 frame-number 3555 frame-number = <1>;
3661 interrupts = 3556 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
3662 reg = <0x0987 3557 reg = <0x09870000 0x1000>;
3663 status = "dis 3558 status = "disabled";
3664 }; 3559 };
3665 3560
3666 frame@9880000 { 3561 frame@9880000 {
3667 frame-number 3562 frame-number = <2>;
3668 interrupts = 3563 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
3669 reg = <0x0988 3564 reg = <0x09880000 0x1000>;
3670 status = "dis 3565 status = "disabled";
3671 }; 3566 };
3672 3567
3673 frame@9890000 { 3568 frame@9890000 {
3674 frame-number 3569 frame-number = <3>;
3675 interrupts = 3570 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
3676 reg = <0x0989 3571 reg = <0x09890000 0x1000>;
3677 status = "dis 3572 status = "disabled";
3678 }; 3573 };
3679 3574
3680 frame@98a0000 { 3575 frame@98a0000 {
3681 frame-number 3576 frame-number = <4>;
3682 interrupts = 3577 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
3683 reg = <0x098a 3578 reg = <0x098a0000 0x1000>;
3684 status = "dis 3579 status = "disabled";
3685 }; 3580 };
3686 3581
3687 frame@98b0000 { 3582 frame@98b0000 {
3688 frame-number 3583 frame-number = <5>;
3689 interrupts = 3584 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
3690 reg = <0x098b 3585 reg = <0x098b0000 0x1000>;
3691 status = "dis 3586 status = "disabled";
3692 }; 3587 };
3693 3588
3694 frame@98c0000 { 3589 frame@98c0000 {
3695 frame-number 3590 frame-number = <6>;
3696 interrupts = 3591 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
3697 reg = <0x098c 3592 reg = <0x098c0000 0x1000>;
3698 status = "dis 3593 status = "disabled";
3699 }; 3594 };
3700 }; 3595 };
3701 3596
3702 saw3: syscon@9a10000 { 3597 saw3: syscon@9a10000 {
3703 compatible = "syscon" 3598 compatible = "syscon";
3704 reg = <0x09a10000 0x1 3599 reg = <0x09a10000 0x1000>;
3705 }; 3600 };
3706 3601
3707 cbf: clock-controller@9a11000 3602 cbf: clock-controller@9a11000 {
3708 compatible = "qcom,ms 3603 compatible = "qcom,msm8996-cbf";
3709 reg = <0x09a11000 0x1 3604 reg = <0x09a11000 0x10000>;
3710 clocks = <&rpmcc RPM_ 3605 clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>, <&apcs_glb>;
3711 #clock-cells = <0>; 3606 #clock-cells = <0>;
3712 #interconnect-cells = 3607 #interconnect-cells = <1>;
3713 }; 3608 };
3714 3609
3715 intc: interrupt-controller@9b 3610 intc: interrupt-controller@9bc0000 {
3716 compatible = "qcom,ms 3611 compatible = "qcom,msm8996-gic-v3", "arm,gic-v3";
3717 #interrupt-cells = <3 3612 #interrupt-cells = <3>;
3718 interrupt-controller; 3613 interrupt-controller;
3719 #redistributor-region 3614 #redistributor-regions = <1>;
3720 redistributor-stride 3615 redistributor-stride = <0x0 0x40000>;
3721 reg = <0x09bc0000 0x1 3616 reg = <0x09bc0000 0x10000>,
3722 <0x09c00000 0x1 3617 <0x09c00000 0x100000>;
3723 interrupts = <GIC_PPI 3618 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3724 }; 3619 };
3725 }; 3620 };
3726 3621
3727 sound: sound { 3622 sound: sound {
3728 }; 3623 };
3729 3624
3730 thermal-zones { 3625 thermal-zones {
3731 cpu0-thermal { 3626 cpu0-thermal {
3732 polling-delay-passive 3627 polling-delay-passive = <250>;
>> 3628 polling-delay = <1000>;
3733 3629
3734 thermal-sensors = <&t 3630 thermal-sensors = <&tsens0 3>;
3735 3631
3736 trips { 3632 trips {
3737 cpu0_alert0: 3633 cpu0_alert0: trip-point0 {
3738 tempe 3634 temperature = <75000>;
3739 hyste 3635 hysteresis = <2000>;
3740 type 3636 type = "passive";
3741 }; 3637 };
3742 3638
3743 cpu0_crit: cp 3639 cpu0_crit: cpu-crit {
3744 tempe 3640 temperature = <110000>;
3745 hyste 3641 hysteresis = <2000>;
3746 type 3642 type = "critical";
3747 }; 3643 };
3748 }; 3644 };
3749 }; 3645 };
3750 3646
3751 cpu1-thermal { 3647 cpu1-thermal {
3752 polling-delay-passive 3648 polling-delay-passive = <250>;
>> 3649 polling-delay = <1000>;
3753 3650
3754 thermal-sensors = <&t 3651 thermal-sensors = <&tsens0 5>;
3755 3652
3756 trips { 3653 trips {
3757 cpu1_alert0: 3654 cpu1_alert0: trip-point0 {
3758 tempe 3655 temperature = <75000>;
3759 hyste 3656 hysteresis = <2000>;
3760 type 3657 type = "passive";
3761 }; 3658 };
3762 3659
3763 cpu1_crit: cp 3660 cpu1_crit: cpu-crit {
3764 tempe 3661 temperature = <110000>;
3765 hyste 3662 hysteresis = <2000>;
3766 type 3663 type = "critical";
3767 }; 3664 };
3768 }; 3665 };
3769 }; 3666 };
3770 3667
3771 cpu2-thermal { 3668 cpu2-thermal {
3772 polling-delay-passive 3669 polling-delay-passive = <250>;
>> 3670 polling-delay = <1000>;
3773 3671
3774 thermal-sensors = <&t 3672 thermal-sensors = <&tsens0 8>;
3775 3673
3776 trips { 3674 trips {
3777 cpu2_alert0: 3675 cpu2_alert0: trip-point0 {
3778 tempe 3676 temperature = <75000>;
3779 hyste 3677 hysteresis = <2000>;
3780 type 3678 type = "passive";
3781 }; 3679 };
3782 3680
3783 cpu2_crit: cp 3681 cpu2_crit: cpu-crit {
3784 tempe 3682 temperature = <110000>;
3785 hyste 3683 hysteresis = <2000>;
3786 type 3684 type = "critical";
3787 }; 3685 };
3788 }; 3686 };
3789 }; 3687 };
3790 3688
3791 cpu3-thermal { 3689 cpu3-thermal {
3792 polling-delay-passive 3690 polling-delay-passive = <250>;
>> 3691 polling-delay = <1000>;
3793 3692
3794 thermal-sensors = <&t 3693 thermal-sensors = <&tsens0 10>;
3795 3694
3796 trips { 3695 trips {
3797 cpu3_alert0: 3696 cpu3_alert0: trip-point0 {
3798 tempe 3697 temperature = <75000>;
3799 hyste 3698 hysteresis = <2000>;
3800 type 3699 type = "passive";
3801 }; 3700 };
3802 3701
3803 cpu3_crit: cp 3702 cpu3_crit: cpu-crit {
3804 tempe 3703 temperature = <110000>;
3805 hyste 3704 hysteresis = <2000>;
3806 type 3705 type = "critical";
3807 }; 3706 };
3808 }; 3707 };
3809 }; 3708 };
3810 3709
3811 gpu-top-thermal { 3710 gpu-top-thermal {
3812 polling-delay-passive 3711 polling-delay-passive = <250>;
>> 3712 polling-delay = <1000>;
3813 3713
3814 thermal-sensors = <&t 3714 thermal-sensors = <&tsens1 6>;
3815 3715
3816 trips { 3716 trips {
3817 gpu1_alert0: 3717 gpu1_alert0: trip-point0 {
3818 tempe 3718 temperature = <90000>;
3819 hyste 3719 hysteresis = <2000>;
3820 type 3720 type = "passive";
3821 }; 3721 };
3822 }; 3722 };
3823 3723
3824 cooling-maps { 3724 cooling-maps {
3825 map0 { 3725 map0 {
3826 trip 3726 trip = <&gpu1_alert0>;
3827 cooli 3727 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3828 }; 3728 };
3829 }; 3729 };
3830 }; 3730 };
3831 3731
3832 gpu-bottom-thermal { 3732 gpu-bottom-thermal {
3833 polling-delay-passive 3733 polling-delay-passive = <250>;
>> 3734 polling-delay = <1000>;
3834 3735
3835 thermal-sensors = <&t 3736 thermal-sensors = <&tsens1 7>;
3836 3737
3837 trips { 3738 trips {
3838 gpu2_alert0: 3739 gpu2_alert0: trip-point0 {
3839 tempe 3740 temperature = <90000>;
3840 hyste 3741 hysteresis = <2000>;
3841 type 3742 type = "passive";
3842 }; 3743 };
3843 }; 3744 };
3844 3745
3845 cooling-maps { 3746 cooling-maps {
3846 map0 { 3747 map0 {
3847 trip 3748 trip = <&gpu2_alert0>;
3848 cooli 3749 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3849 }; 3750 };
3850 }; 3751 };
3851 }; 3752 };
3852 3753
3853 m4m-thermal { 3754 m4m-thermal {
3854 polling-delay-passive 3755 polling-delay-passive = <250>;
>> 3756 polling-delay = <1000>;
3855 3757
3856 thermal-sensors = <&t 3758 thermal-sensors = <&tsens0 1>;
3857 3759
3858 trips { 3760 trips {
3859 m4m_alert0: t 3761 m4m_alert0: trip-point0 {
3860 tempe 3762 temperature = <90000>;
3861 hyste 3763 hysteresis = <2000>;
3862 type 3764 type = "hot";
3863 }; 3765 };
3864 }; 3766 };
3865 }; 3767 };
3866 3768
3867 l3-or-venus-thermal { 3769 l3-or-venus-thermal {
3868 polling-delay-passive 3770 polling-delay-passive = <250>;
>> 3771 polling-delay = <1000>;
3869 3772
3870 thermal-sensors = <&t 3773 thermal-sensors = <&tsens0 2>;
3871 3774
3872 trips { 3775 trips {
3873 l3_or_venus_a 3776 l3_or_venus_alert0: trip-point0 {
3874 tempe 3777 temperature = <90000>;
3875 hyste 3778 hysteresis = <2000>;
3876 type 3779 type = "hot";
3877 }; 3780 };
3878 }; 3781 };
3879 }; 3782 };
3880 3783
3881 cluster0-l2-thermal { 3784 cluster0-l2-thermal {
3882 polling-delay-passive 3785 polling-delay-passive = <250>;
>> 3786 polling-delay = <1000>;
3883 3787
3884 thermal-sensors = <&t 3788 thermal-sensors = <&tsens0 7>;
3885 3789
3886 trips { 3790 trips {
3887 cluster0_l2_a 3791 cluster0_l2_alert0: trip-point0 {
3888 tempe 3792 temperature = <90000>;
3889 hyste 3793 hysteresis = <2000>;
3890 type 3794 type = "hot";
3891 }; 3795 };
3892 }; 3796 };
3893 }; 3797 };
3894 3798
3895 cluster1-l2-thermal { 3799 cluster1-l2-thermal {
3896 polling-delay-passive 3800 polling-delay-passive = <250>;
>> 3801 polling-delay = <1000>;
3897 3802
3898 thermal-sensors = <&t 3803 thermal-sensors = <&tsens0 12>;
3899 3804
3900 trips { 3805 trips {
3901 cluster1_l2_a 3806 cluster1_l2_alert0: trip-point0 {
3902 tempe 3807 temperature = <90000>;
3903 hyste 3808 hysteresis = <2000>;
3904 type 3809 type = "hot";
3905 }; 3810 };
3906 }; 3811 };
3907 }; 3812 };
3908 3813
3909 camera-thermal { 3814 camera-thermal {
3910 polling-delay-passive 3815 polling-delay-passive = <250>;
>> 3816 polling-delay = <1000>;
3911 3817
3912 thermal-sensors = <&t 3818 thermal-sensors = <&tsens1 1>;
3913 3819
3914 trips { 3820 trips {
3915 camera_alert0 3821 camera_alert0: trip-point0 {
3916 tempe 3822 temperature = <90000>;
3917 hyste 3823 hysteresis = <2000>;
3918 type 3824 type = "hot";
3919 }; 3825 };
3920 }; 3826 };
3921 }; 3827 };
3922 3828
3923 q6-dsp-thermal { 3829 q6-dsp-thermal {
3924 polling-delay-passive 3830 polling-delay-passive = <250>;
>> 3831 polling-delay = <1000>;
3925 3832
3926 thermal-sensors = <&t 3833 thermal-sensors = <&tsens1 2>;
3927 3834
3928 trips { 3835 trips {
3929 q6_dsp_alert0 3836 q6_dsp_alert0: trip-point0 {
3930 tempe 3837 temperature = <90000>;
3931 hyste 3838 hysteresis = <2000>;
3932 type 3839 type = "hot";
3933 }; 3840 };
3934 }; 3841 };
3935 }; 3842 };
3936 3843
3937 mem-thermal { 3844 mem-thermal {
3938 polling-delay-passive 3845 polling-delay-passive = <250>;
>> 3846 polling-delay = <1000>;
3939 3847
3940 thermal-sensors = <&t 3848 thermal-sensors = <&tsens1 3>;
3941 3849
3942 trips { 3850 trips {
3943 mem_alert0: t 3851 mem_alert0: trip-point0 {
3944 tempe 3852 temperature = <90000>;
3945 hyste 3853 hysteresis = <2000>;
3946 type 3854 type = "hot";
3947 }; 3855 };
3948 }; 3856 };
3949 }; 3857 };
3950 3858
3951 modemtx-thermal { 3859 modemtx-thermal {
3952 polling-delay-passive 3860 polling-delay-passive = <250>;
>> 3861 polling-delay = <1000>;
3953 3862
3954 thermal-sensors = <&t 3863 thermal-sensors = <&tsens1 4>;
3955 3864
3956 trips { 3865 trips {
3957 modemtx_alert 3866 modemtx_alert0: trip-point0 {
3958 tempe 3867 temperature = <90000>;
3959 hyste 3868 hysteresis = <2000>;
3960 type 3869 type = "hot";
3961 }; 3870 };
3962 }; 3871 };
3963 }; 3872 };
3964 }; 3873 };
3965 3874
3966 timer { 3875 timer {
3967 compatible = "arm,armv8-timer 3876 compatible = "arm,armv8-timer";
3968 interrupts = <GIC_PPI 13 IRQ_ 3877 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
3969 <GIC_PPI 14 IRQ_ 3878 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
3970 <GIC_PPI 11 IRQ_ 3879 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
3971 <GIC_PPI 10 IRQ_ 3880 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
3972 }; 3881 };
3973 }; 3882 };
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