1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2016, The Linux Foundation. A 2 /* Copyright (c) 2016, The Linux Foundation. All rights reserved. */
3 3
4 #include <dt-bindings/interrupt-controller/arm 4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-msm8998.h 5 #include <dt-bindings/clock/qcom,gcc-msm8998.h>
6 #include <dt-bindings/clock/qcom,gpucc-msm8998 6 #include <dt-bindings/clock/qcom,gpucc-msm8998.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8998. <<
8 #include <dt-bindings/clock/qcom,rpmcc.h> 7 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/firmware/qcom,scm.h> <<
10 #include <dt-bindings/power/qcom-rpmpd.h> 8 #include <dt-bindings/power/qcom-rpmpd.h>
11 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/gpio/gpio.h>
12 10
13 / { 11 / {
14 interrupt-parent = <&intc>; 12 interrupt-parent = <&intc>;
15 13
16 qcom,msm-id = <292 0x0>; 14 qcom,msm-id = <292 0x0>;
17 15
18 #address-cells = <2>; 16 #address-cells = <2>;
19 #size-cells = <2>; 17 #size-cells = <2>;
20 18
21 chosen { }; 19 chosen { };
22 20
23 memory@80000000 { !! 21 memory {
24 device_type = "memory"; 22 device_type = "memory";
25 /* We expect the bootloader to 23 /* We expect the bootloader to fill in the reg */
26 reg = <0x0 0x80000000 0x0 0x0> !! 24 reg = <0 0 0 0>;
27 }; 25 };
28 26
29 reserved-memory { 27 reserved-memory {
30 #address-cells = <2>; 28 #address-cells = <2>;
31 #size-cells = <2>; 29 #size-cells = <2>;
32 ranges; 30 ranges;
33 31
34 hyp_mem: memory@85800000 { 32 hyp_mem: memory@85800000 {
35 reg = <0x0 0x85800000 33 reg = <0x0 0x85800000 0x0 0x600000>;
36 no-map; 34 no-map;
37 }; 35 };
38 36
39 xbl_mem: memory@85e00000 { 37 xbl_mem: memory@85e00000 {
40 reg = <0x0 0x85e00000 38 reg = <0x0 0x85e00000 0x0 0x100000>;
41 no-map; 39 no-map;
42 }; 40 };
43 41
44 smem_mem: smem-mem@86000000 { 42 smem_mem: smem-mem@86000000 {
45 reg = <0x0 0x86000000 43 reg = <0x0 0x86000000 0x0 0x200000>;
46 no-map; 44 no-map;
47 }; 45 };
48 46
49 tz_mem: memory@86200000 { 47 tz_mem: memory@86200000 {
50 reg = <0x0 0x86200000 48 reg = <0x0 0x86200000 0x0 0x2d00000>;
51 no-map; 49 no-map;
52 }; 50 };
53 51
54 rmtfs_mem: memory@88f00000 { 52 rmtfs_mem: memory@88f00000 {
55 compatible = "qcom,rmt 53 compatible = "qcom,rmtfs-mem";
56 reg = <0x0 0x88f00000 54 reg = <0x0 0x88f00000 0x0 0x200000>;
57 no-map; 55 no-map;
58 56
59 qcom,client-id = <1>; 57 qcom,client-id = <1>;
60 qcom,vmid = <QCOM_SCM_ !! 58 qcom,vmid = <15>;
61 }; 59 };
62 60
63 spss_mem: memory@8ab00000 { 61 spss_mem: memory@8ab00000 {
64 reg = <0x0 0x8ab00000 62 reg = <0x0 0x8ab00000 0x0 0x700000>;
65 no-map; 63 no-map;
66 }; 64 };
67 65
68 adsp_mem: memory@8b200000 { 66 adsp_mem: memory@8b200000 {
69 reg = <0x0 0x8b200000 67 reg = <0x0 0x8b200000 0x0 0x1a00000>;
70 no-map; 68 no-map;
71 }; 69 };
72 70
73 mpss_mem: memory@8cc00000 { 71 mpss_mem: memory@8cc00000 {
74 reg = <0x0 0x8cc00000 72 reg = <0x0 0x8cc00000 0x0 0x7000000>;
75 no-map; 73 no-map;
76 }; 74 };
77 75
78 venus_mem: memory@93c00000 { 76 venus_mem: memory@93c00000 {
79 reg = <0x0 0x93c00000 77 reg = <0x0 0x93c00000 0x0 0x500000>;
80 no-map; 78 no-map;
81 }; 79 };
82 80
83 mba_mem: memory@94100000 { 81 mba_mem: memory@94100000 {
84 reg = <0x0 0x94100000 82 reg = <0x0 0x94100000 0x0 0x200000>;
85 no-map; 83 no-map;
86 }; 84 };
87 85
88 slpi_mem: memory@94300000 { 86 slpi_mem: memory@94300000 {
89 reg = <0x0 0x94300000 87 reg = <0x0 0x94300000 0x0 0xf00000>;
90 no-map; 88 no-map;
91 }; 89 };
92 90
93 ipa_fw_mem: memory@95200000 { 91 ipa_fw_mem: memory@95200000 {
94 reg = <0x0 0x95200000 92 reg = <0x0 0x95200000 0x0 0x10000>;
95 no-map; 93 no-map;
96 }; 94 };
97 95
98 ipa_gsi_mem: memory@95210000 { 96 ipa_gsi_mem: memory@95210000 {
99 reg = <0x0 0x95210000 97 reg = <0x0 0x95210000 0x0 0x5000>;
100 no-map; 98 no-map;
101 }; 99 };
102 100
103 gpu_mem: memory@95600000 { 101 gpu_mem: memory@95600000 {
104 reg = <0x0 0x95600000 102 reg = <0x0 0x95600000 0x0 0x100000>;
105 no-map; 103 no-map;
106 }; 104 };
107 105
108 wlan_msa_mem: memory@95700000 106 wlan_msa_mem: memory@95700000 {
109 reg = <0x0 0x95700000 107 reg = <0x0 0x95700000 0x0 0x100000>;
110 no-map; 108 no-map;
111 }; 109 };
112 <<
113 mdata_mem: mpss-metadata { <<
114 alloc-ranges = <0x0 0x <<
115 size = <0x0 0x4000>; <<
116 no-map; <<
117 }; <<
118 }; 110 };
119 111
120 clocks { 112 clocks {
121 xo: xo-board { 113 xo: xo-board {
122 compatible = "fixed-cl 114 compatible = "fixed-clock";
123 #clock-cells = <0>; 115 #clock-cells = <0>;
124 clock-frequency = <192 116 clock-frequency = <19200000>;
125 clock-output-names = " 117 clock-output-names = "xo_board";
126 }; 118 };
127 119
128 sleep_clk: sleep-clk { !! 120 sleep_clk {
129 compatible = "fixed-cl 121 compatible = "fixed-clock";
130 #clock-cells = <0>; 122 #clock-cells = <0>;
131 clock-frequency = <327 123 clock-frequency = <32764>;
132 }; 124 };
133 }; 125 };
134 126
135 cpus { 127 cpus {
136 #address-cells = <2>; 128 #address-cells = <2>;
137 #size-cells = <0>; 129 #size-cells = <0>;
138 130
139 CPU0: cpu@0 { 131 CPU0: cpu@0 {
140 device_type = "cpu"; 132 device_type = "cpu";
141 compatible = "qcom,kry 133 compatible = "qcom,kryo280";
142 reg = <0x0 0x0>; 134 reg = <0x0 0x0>;
143 enable-method = "psci" 135 enable-method = "psci";
144 capacity-dmips-mhz = < <<
145 cpu-idle-states = <&LI 136 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
146 next-level-cache = <&L 137 next-level-cache = <&L2_0>;
147 L2_0: l2-cache { 138 L2_0: l2-cache {
148 compatible = " !! 139 compatible = "arm,arch-cache";
149 cache-level = 140 cache-level = <2>;
150 cache-unified; !! 141 };
>> 142 L1_I_0: l1-icache {
>> 143 compatible = "arm,arch-cache";
>> 144 };
>> 145 L1_D_0: l1-dcache {
>> 146 compatible = "arm,arch-cache";
151 }; 147 };
152 }; 148 };
153 149
154 CPU1: cpu@1 { 150 CPU1: cpu@1 {
155 device_type = "cpu"; 151 device_type = "cpu";
156 compatible = "qcom,kry 152 compatible = "qcom,kryo280";
157 reg = <0x0 0x1>; 153 reg = <0x0 0x1>;
158 enable-method = "psci" 154 enable-method = "psci";
159 capacity-dmips-mhz = < <<
160 cpu-idle-states = <&LI 155 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
161 next-level-cache = <&L 156 next-level-cache = <&L2_0>;
>> 157 L1_I_1: l1-icache {
>> 158 compatible = "arm,arch-cache";
>> 159 };
>> 160 L1_D_1: l1-dcache {
>> 161 compatible = "arm,arch-cache";
>> 162 };
162 }; 163 };
163 164
164 CPU2: cpu@2 { 165 CPU2: cpu@2 {
165 device_type = "cpu"; 166 device_type = "cpu";
166 compatible = "qcom,kry 167 compatible = "qcom,kryo280";
167 reg = <0x0 0x2>; 168 reg = <0x0 0x2>;
168 enable-method = "psci" 169 enable-method = "psci";
169 capacity-dmips-mhz = < <<
170 cpu-idle-states = <&LI 170 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
171 next-level-cache = <&L 171 next-level-cache = <&L2_0>;
>> 172 L1_I_2: l1-icache {
>> 173 compatible = "arm,arch-cache";
>> 174 };
>> 175 L1_D_2: l1-dcache {
>> 176 compatible = "arm,arch-cache";
>> 177 };
172 }; 178 };
173 179
174 CPU3: cpu@3 { 180 CPU3: cpu@3 {
175 device_type = "cpu"; 181 device_type = "cpu";
176 compatible = "qcom,kry 182 compatible = "qcom,kryo280";
177 reg = <0x0 0x3>; 183 reg = <0x0 0x3>;
178 enable-method = "psci" 184 enable-method = "psci";
179 capacity-dmips-mhz = < <<
180 cpu-idle-states = <&LI 185 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
181 next-level-cache = <&L 186 next-level-cache = <&L2_0>;
>> 187 L1_I_3: l1-icache {
>> 188 compatible = "arm,arch-cache";
>> 189 };
>> 190 L1_D_3: l1-dcache {
>> 191 compatible = "arm,arch-cache";
>> 192 };
182 }; 193 };
183 194
184 CPU4: cpu@100 { 195 CPU4: cpu@100 {
185 device_type = "cpu"; 196 device_type = "cpu";
186 compatible = "qcom,kry 197 compatible = "qcom,kryo280";
187 reg = <0x0 0x100>; 198 reg = <0x0 0x100>;
188 enable-method = "psci" 199 enable-method = "psci";
189 capacity-dmips-mhz = < <<
190 cpu-idle-states = <&BI 200 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
191 next-level-cache = <&L 201 next-level-cache = <&L2_1>;
192 L2_1: l2-cache { 202 L2_1: l2-cache {
193 compatible = " !! 203 compatible = "arm,arch-cache";
194 cache-level = 204 cache-level = <2>;
195 cache-unified; !! 205 };
>> 206 L1_I_100: l1-icache {
>> 207 compatible = "arm,arch-cache";
>> 208 };
>> 209 L1_D_100: l1-dcache {
>> 210 compatible = "arm,arch-cache";
196 }; 211 };
197 }; 212 };
198 213
199 CPU5: cpu@101 { 214 CPU5: cpu@101 {
200 device_type = "cpu"; 215 device_type = "cpu";
201 compatible = "qcom,kry 216 compatible = "qcom,kryo280";
202 reg = <0x0 0x101>; 217 reg = <0x0 0x101>;
203 enable-method = "psci" 218 enable-method = "psci";
204 capacity-dmips-mhz = < <<
205 cpu-idle-states = <&BI 219 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
206 next-level-cache = <&L 220 next-level-cache = <&L2_1>;
>> 221 L1_I_101: l1-icache {
>> 222 compatible = "arm,arch-cache";
>> 223 };
>> 224 L1_D_101: l1-dcache {
>> 225 compatible = "arm,arch-cache";
>> 226 };
207 }; 227 };
208 228
209 CPU6: cpu@102 { 229 CPU6: cpu@102 {
210 device_type = "cpu"; 230 device_type = "cpu";
211 compatible = "qcom,kry 231 compatible = "qcom,kryo280";
212 reg = <0x0 0x102>; 232 reg = <0x0 0x102>;
213 enable-method = "psci" 233 enable-method = "psci";
214 capacity-dmips-mhz = < <<
215 cpu-idle-states = <&BI 234 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
216 next-level-cache = <&L 235 next-level-cache = <&L2_1>;
>> 236 L1_I_102: l1-icache {
>> 237 compatible = "arm,arch-cache";
>> 238 };
>> 239 L1_D_102: l1-dcache {
>> 240 compatible = "arm,arch-cache";
>> 241 };
217 }; 242 };
218 243
219 CPU7: cpu@103 { 244 CPU7: cpu@103 {
220 device_type = "cpu"; 245 device_type = "cpu";
221 compatible = "qcom,kry 246 compatible = "qcom,kryo280";
222 reg = <0x0 0x103>; 247 reg = <0x0 0x103>;
223 enable-method = "psci" 248 enable-method = "psci";
224 capacity-dmips-mhz = < <<
225 cpu-idle-states = <&BI 249 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
226 next-level-cache = <&L 250 next-level-cache = <&L2_1>;
>> 251 L1_I_103: l1-icache {
>> 252 compatible = "arm,arch-cache";
>> 253 };
>> 254 L1_D_103: l1-dcache {
>> 255 compatible = "arm,arch-cache";
>> 256 };
227 }; 257 };
228 258
229 cpu-map { 259 cpu-map {
230 cluster0 { 260 cluster0 {
231 core0 { 261 core0 {
232 cpu = 262 cpu = <&CPU0>;
233 }; 263 };
234 264
235 core1 { 265 core1 {
236 cpu = 266 cpu = <&CPU1>;
237 }; 267 };
238 268
239 core2 { 269 core2 {
240 cpu = 270 cpu = <&CPU2>;
241 }; 271 };
242 272
243 core3 { 273 core3 {
244 cpu = 274 cpu = <&CPU3>;
245 }; 275 };
246 }; 276 };
247 277
248 cluster1 { 278 cluster1 {
249 core0 { 279 core0 {
250 cpu = 280 cpu = <&CPU4>;
251 }; 281 };
252 282
253 core1 { 283 core1 {
254 cpu = 284 cpu = <&CPU5>;
255 }; 285 };
256 286
257 core2 { 287 core2 {
258 cpu = 288 cpu = <&CPU6>;
259 }; 289 };
260 290
261 core3 { 291 core3 {
262 cpu = 292 cpu = <&CPU7>;
263 }; 293 };
264 }; 294 };
265 }; 295 };
266 296
267 idle-states { 297 idle-states {
268 entry-method = "psci"; 298 entry-method = "psci";
269 299
270 LITTLE_CPU_SLEEP_0: cp 300 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
271 compatible = " 301 compatible = "arm,idle-state";
272 idle-state-nam 302 idle-state-name = "little-retention";
273 /* CPU Retenti 303 /* CPU Retention (C2D), L2 Active */
274 arm,psci-suspe 304 arm,psci-suspend-param = <0x00000002>;
275 entry-latency- 305 entry-latency-us = <81>;
276 exit-latency-u 306 exit-latency-us = <86>;
277 min-residency- 307 min-residency-us = <504>;
278 }; 308 };
279 309
280 LITTLE_CPU_SLEEP_1: cp 310 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
281 compatible = " 311 compatible = "arm,idle-state";
282 idle-state-nam 312 idle-state-name = "little-power-collapse";
283 /* CPU + L2 Po 313 /* CPU + L2 Power Collapse (C3, D4) */
284 arm,psci-suspe 314 arm,psci-suspend-param = <0x40000003>;
285 entry-latency- 315 entry-latency-us = <814>;
286 exit-latency-u 316 exit-latency-us = <4562>;
287 min-residency- 317 min-residency-us = <9183>;
288 local-timer-st 318 local-timer-stop;
289 }; 319 };
290 320
291 BIG_CPU_SLEEP_0: cpu-s 321 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
292 compatible = " 322 compatible = "arm,idle-state";
293 idle-state-nam 323 idle-state-name = "big-retention";
294 /* CPU Retenti 324 /* CPU Retention (C2D), L2 Active */
295 arm,psci-suspe 325 arm,psci-suspend-param = <0x00000002>;
296 entry-latency- 326 entry-latency-us = <79>;
297 exit-latency-u 327 exit-latency-us = <82>;
298 min-residency- 328 min-residency-us = <1302>;
299 }; 329 };
300 330
301 BIG_CPU_SLEEP_1: cpu-s 331 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
302 compatible = " 332 compatible = "arm,idle-state";
303 idle-state-nam 333 idle-state-name = "big-power-collapse";
304 /* CPU + L2 Po 334 /* CPU + L2 Power Collapse (C3, D4) */
305 arm,psci-suspe 335 arm,psci-suspend-param = <0x40000003>;
306 entry-latency- 336 entry-latency-us = <724>;
307 exit-latency-u 337 exit-latency-us = <2027>;
308 min-residency- 338 min-residency-us = <9419>;
309 local-timer-st 339 local-timer-stop;
310 }; 340 };
311 }; 341 };
312 }; 342 };
313 343
314 firmware { 344 firmware {
315 scm { 345 scm {
316 compatible = "qcom,scm 346 compatible = "qcom,scm-msm8998", "qcom,scm";
317 }; 347 };
318 }; 348 };
319 349
320 dsi_opp_table: opp-table-dsi { !! 350 tcsr_mutex: hwlock {
321 compatible = "operating-points !! 351 compatible = "qcom,tcsr-mutex";
322 !! 352 syscon = <&tcsr_mutex_regs 0 0x1000>;
323 opp-131250000 { !! 353 #hwlock-cells = <1>;
324 opp-hz = /bits/ 64 <13 <<
325 required-opps = <&rpmp <<
326 }; <<
327 <<
328 opp-210000000 { <<
329 opp-hz = /bits/ 64 <21 <<
330 required-opps = <&rpmp <<
331 }; <<
332 <<
333 opp-312500000 { <<
334 opp-hz = /bits/ 64 <31 <<
335 required-opps = <&rpmp <<
336 }; <<
337 }; 354 };
338 355
339 psci { 356 psci {
340 compatible = "arm,psci-1.0"; 357 compatible = "arm,psci-1.0";
341 method = "smc"; 358 method = "smc";
342 }; 359 };
343 360
344 rpm: remoteproc { !! 361 rpm-glink {
345 compatible = "qcom,msm8998-rpm !! 362 compatible = "qcom,glink-rpm";
346 363
347 glink-edge { !! 364 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
348 compatible = "qcom,gli !! 365 qcom,rpm-msg-ram = <&rpm_msg_ram>;
>> 366 mboxes = <&apcs_glb 0>;
>> 367
>> 368 rpm_requests: rpm-requests {
>> 369 compatible = "qcom,rpm-msm8998";
>> 370 qcom,glink-channels = "rpm_requests";
349 371
350 interrupts = <GIC_SPI !! 372 rpmcc: clock-controller {
351 qcom,rpm-msg-ram = <&r !! 373 compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc";
352 mboxes = <&apcs_glb 0> !! 374 #clock-cells = <1>;
353 !! 375 };
354 rpm_requests: rpm-requ !! 376
355 compatible = " !! 377 rpmpd: power-controller {
356 qcom,glink-cha !! 378 compatible = "qcom,msm8998-rpmpd";
357 !! 379 #power-domain-cells = <1>;
358 rpmcc: clock-c !! 380 operating-points-v2 = <&rpmpd_opp_table>;
359 compat !! 381
360 clocks !! 382 rpmpd_opp_table: opp-table {
361 clock- !! 383 compatible = "operating-points-v2";
362 #clock !! 384
363 }; !! 385 rpmpd_opp_ret: opp1 {
364 !! 386 opp-level = <16>;
365 rpmpd: power-c !! 387 };
366 compat !! 388
367 #power !! 389 rpmpd_opp_ret_plus: opp2 {
368 operat !! 390 opp-level = <32>;
369 !! 391 };
370 rpmpd_ !! 392
371 !! 393 rpmpd_opp_min_svs: opp3 {
372 !! 394 opp-level = <48>;
373 !! 395 };
374 !! 396
375 !! 397 rpmpd_opp_low_svs: opp4 {
376 !! 398 opp-level = <64>;
377 !! 399 };
378 !! 400
379 !! 401 rpmpd_opp_svs: opp5 {
380 !! 402 opp-level = <128>;
381 !! 403 };
382 !! 404
383 !! 405 rpmpd_opp_svs_plus: opp6 {
384 !! 406 opp-level = <192>;
385 !! 407 };
386 !! 408
387 !! 409 rpmpd_opp_nom: opp7 {
388 !! 410 opp-level = <256>;
389 !! 411 };
390 !! 412
391 !! 413 rpmpd_opp_nom_plus: opp8 {
392 !! 414 opp-level = <320>;
393 !! 415 };
394 !! 416
395 !! 417 rpmpd_opp_turbo: opp9 {
396 !! 418 opp-level = <384>;
397 !! 419 };
398 !! 420
399 !! 421 rpmpd_opp_turbo_plus: opp10 {
400 !! 422 opp-level = <512>;
401 <<
402 <<
403 <<
404 <<
405 <<
406 <<
407 <<
408 <<
409 <<
410 <<
411 <<
412 }; 423 };
413 }; 424 };
414 }; 425 };
415 }; 426 };
416 }; 427 };
417 428
418 smem { 429 smem {
419 compatible = "qcom,smem"; 430 compatible = "qcom,smem";
420 memory-region = <&smem_mem>; 431 memory-region = <&smem_mem>;
421 hwlocks = <&tcsr_mutex 3>; 432 hwlocks = <&tcsr_mutex 3>;
422 }; 433 };
423 434
424 smp2p-lpass { 435 smp2p-lpass {
425 compatible = "qcom,smp2p"; 436 compatible = "qcom,smp2p";
426 qcom,smem = <443>, <429>; 437 qcom,smem = <443>, <429>;
427 438
428 interrupts = <GIC_SPI 158 IRQ_ 439 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
429 440
430 mboxes = <&apcs_glb 10>; 441 mboxes = <&apcs_glb 10>;
431 442
432 qcom,local-pid = <0>; 443 qcom,local-pid = <0>;
433 qcom,remote-pid = <2>; 444 qcom,remote-pid = <2>;
434 445
435 adsp_smp2p_out: master-kernel 446 adsp_smp2p_out: master-kernel {
436 qcom,entry-name = "mas 447 qcom,entry-name = "master-kernel";
437 #qcom,smem-state-cells 448 #qcom,smem-state-cells = <1>;
438 }; 449 };
439 450
440 adsp_smp2p_in: slave-kernel { 451 adsp_smp2p_in: slave-kernel {
441 qcom,entry-name = "sla 452 qcom,entry-name = "slave-kernel";
442 453
443 interrupt-controller; 454 interrupt-controller;
444 #interrupt-cells = <2> 455 #interrupt-cells = <2>;
445 }; 456 };
446 }; 457 };
447 458
448 smp2p-mpss { 459 smp2p-mpss {
449 compatible = "qcom,smp2p"; 460 compatible = "qcom,smp2p";
450 qcom,smem = <435>, <428>; 461 qcom,smem = <435>, <428>;
451 interrupts = <GIC_SPI 451 IRQ_ 462 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
452 mboxes = <&apcs_glb 14>; 463 mboxes = <&apcs_glb 14>;
453 qcom,local-pid = <0>; 464 qcom,local-pid = <0>;
454 qcom,remote-pid = <1>; 465 qcom,remote-pid = <1>;
455 466
456 modem_smp2p_out: master-kernel 467 modem_smp2p_out: master-kernel {
457 qcom,entry-name = "mas 468 qcom,entry-name = "master-kernel";
458 #qcom,smem-state-cells 469 #qcom,smem-state-cells = <1>;
459 }; 470 };
460 471
461 modem_smp2p_in: slave-kernel { 472 modem_smp2p_in: slave-kernel {
462 qcom,entry-name = "sla 473 qcom,entry-name = "slave-kernel";
463 interrupt-controller; 474 interrupt-controller;
464 #interrupt-cells = <2> 475 #interrupt-cells = <2>;
465 }; 476 };
466 }; 477 };
467 478
468 smp2p-slpi { 479 smp2p-slpi {
469 compatible = "qcom,smp2p"; 480 compatible = "qcom,smp2p";
470 qcom,smem = <481>, <430>; 481 qcom,smem = <481>, <430>;
471 interrupts = <GIC_SPI 178 IRQ_ 482 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
472 mboxes = <&apcs_glb 26>; 483 mboxes = <&apcs_glb 26>;
473 qcom,local-pid = <0>; 484 qcom,local-pid = <0>;
474 qcom,remote-pid = <3>; 485 qcom,remote-pid = <3>;
475 486
476 slpi_smp2p_out: master-kernel 487 slpi_smp2p_out: master-kernel {
477 qcom,entry-name = "mas 488 qcom,entry-name = "master-kernel";
478 #qcom,smem-state-cells 489 #qcom,smem-state-cells = <1>;
479 }; 490 };
480 491
481 slpi_smp2p_in: slave-kernel { 492 slpi_smp2p_in: slave-kernel {
482 qcom,entry-name = "sla 493 qcom,entry-name = "slave-kernel";
483 interrupt-controller; 494 interrupt-controller;
484 #interrupt-cells = <2> 495 #interrupt-cells = <2>;
485 }; 496 };
486 }; 497 };
487 498
488 thermal-zones { 499 thermal-zones {
489 cpu0-thermal { 500 cpu0-thermal {
490 polling-delay-passive 501 polling-delay-passive = <250>;
>> 502 polling-delay = <1000>;
491 503
492 thermal-sensors = <&ts 504 thermal-sensors = <&tsens0 1>;
493 505
494 trips { 506 trips {
495 cpu0_alert0: t 507 cpu0_alert0: trip-point0 {
496 temper 508 temperature = <75000>;
497 hyster 509 hysteresis = <2000>;
498 type = 510 type = "passive";
499 }; 511 };
500 512
501 cpu0_crit: cpu !! 513 cpu0_crit: cpu_crit {
502 temper 514 temperature = <110000>;
503 hyster 515 hysteresis = <2000>;
504 type = 516 type = "critical";
505 }; 517 };
506 }; 518 };
507 }; 519 };
508 520
509 cpu1-thermal { 521 cpu1-thermal {
510 polling-delay-passive 522 polling-delay-passive = <250>;
>> 523 polling-delay = <1000>;
511 524
512 thermal-sensors = <&ts 525 thermal-sensors = <&tsens0 2>;
513 526
514 trips { 527 trips {
515 cpu1_alert0: t 528 cpu1_alert0: trip-point0 {
516 temper 529 temperature = <75000>;
517 hyster 530 hysteresis = <2000>;
518 type = 531 type = "passive";
519 }; 532 };
520 533
521 cpu1_crit: cpu !! 534 cpu1_crit: cpu_crit {
522 temper 535 temperature = <110000>;
523 hyster 536 hysteresis = <2000>;
524 type = 537 type = "critical";
525 }; 538 };
526 }; 539 };
527 }; 540 };
528 541
529 cpu2-thermal { 542 cpu2-thermal {
530 polling-delay-passive 543 polling-delay-passive = <250>;
>> 544 polling-delay = <1000>;
531 545
532 thermal-sensors = <&ts 546 thermal-sensors = <&tsens0 3>;
533 547
534 trips { 548 trips {
535 cpu2_alert0: t 549 cpu2_alert0: trip-point0 {
536 temper 550 temperature = <75000>;
537 hyster 551 hysteresis = <2000>;
538 type = 552 type = "passive";
539 }; 553 };
540 554
541 cpu2_crit: cpu !! 555 cpu2_crit: cpu_crit {
542 temper 556 temperature = <110000>;
543 hyster 557 hysteresis = <2000>;
544 type = 558 type = "critical";
545 }; 559 };
546 }; 560 };
547 }; 561 };
548 562
549 cpu3-thermal { 563 cpu3-thermal {
550 polling-delay-passive 564 polling-delay-passive = <250>;
>> 565 polling-delay = <1000>;
551 566
552 thermal-sensors = <&ts 567 thermal-sensors = <&tsens0 4>;
553 568
554 trips { 569 trips {
555 cpu3_alert0: t 570 cpu3_alert0: trip-point0 {
556 temper 571 temperature = <75000>;
557 hyster 572 hysteresis = <2000>;
558 type = 573 type = "passive";
559 }; 574 };
560 575
561 cpu3_crit: cpu !! 576 cpu3_crit: cpu_crit {
562 temper 577 temperature = <110000>;
563 hyster 578 hysteresis = <2000>;
564 type = 579 type = "critical";
565 }; 580 };
566 }; 581 };
567 }; 582 };
568 583
569 cpu4-thermal { 584 cpu4-thermal {
570 polling-delay-passive 585 polling-delay-passive = <250>;
>> 586 polling-delay = <1000>;
571 587
572 thermal-sensors = <&ts 588 thermal-sensors = <&tsens0 7>;
573 589
574 trips { 590 trips {
575 cpu4_alert0: t 591 cpu4_alert0: trip-point0 {
576 temper 592 temperature = <75000>;
577 hyster 593 hysteresis = <2000>;
578 type = 594 type = "passive";
579 }; 595 };
580 596
581 cpu4_crit: cpu !! 597 cpu4_crit: cpu_crit {
582 temper 598 temperature = <110000>;
583 hyster 599 hysteresis = <2000>;
584 type = 600 type = "critical";
585 }; 601 };
586 }; 602 };
587 }; 603 };
588 604
589 cpu5-thermal { 605 cpu5-thermal {
590 polling-delay-passive 606 polling-delay-passive = <250>;
>> 607 polling-delay = <1000>;
591 608
592 thermal-sensors = <&ts 609 thermal-sensors = <&tsens0 8>;
593 610
594 trips { 611 trips {
595 cpu5_alert0: t 612 cpu5_alert0: trip-point0 {
596 temper 613 temperature = <75000>;
597 hyster 614 hysteresis = <2000>;
598 type = 615 type = "passive";
599 }; 616 };
600 617
601 cpu5_crit: cpu !! 618 cpu5_crit: cpu_crit {
602 temper 619 temperature = <110000>;
603 hyster 620 hysteresis = <2000>;
604 type = 621 type = "critical";
605 }; 622 };
606 }; 623 };
607 }; 624 };
608 625
609 cpu6-thermal { 626 cpu6-thermal {
610 polling-delay-passive 627 polling-delay-passive = <250>;
>> 628 polling-delay = <1000>;
611 629
612 thermal-sensors = <&ts 630 thermal-sensors = <&tsens0 9>;
613 631
614 trips { 632 trips {
615 cpu6_alert0: t 633 cpu6_alert0: trip-point0 {
616 temper 634 temperature = <75000>;
617 hyster 635 hysteresis = <2000>;
618 type = 636 type = "passive";
619 }; 637 };
620 638
621 cpu6_crit: cpu !! 639 cpu6_crit: cpu_crit {
622 temper 640 temperature = <110000>;
623 hyster 641 hysteresis = <2000>;
624 type = 642 type = "critical";
625 }; 643 };
626 }; 644 };
627 }; 645 };
628 646
629 cpu7-thermal { 647 cpu7-thermal {
630 polling-delay-passive 648 polling-delay-passive = <250>;
>> 649 polling-delay = <1000>;
631 650
632 thermal-sensors = <&ts 651 thermal-sensors = <&tsens0 10>;
633 652
634 trips { 653 trips {
635 cpu7_alert0: t 654 cpu7_alert0: trip-point0 {
636 temper 655 temperature = <75000>;
637 hyster 656 hysteresis = <2000>;
638 type = 657 type = "passive";
639 }; 658 };
640 659
641 cpu7_crit: cpu !! 660 cpu7_crit: cpu_crit {
642 temper 661 temperature = <110000>;
643 hyster 662 hysteresis = <2000>;
644 type = 663 type = "critical";
645 }; 664 };
646 }; 665 };
647 }; 666 };
648 667
649 gpu-bottom-thermal { !! 668 gpu-thermal-bottom {
650 polling-delay-passive 669 polling-delay-passive = <250>;
>> 670 polling-delay = <1000>;
651 671
652 thermal-sensors = <&ts 672 thermal-sensors = <&tsens0 12>;
653 673
654 trips { 674 trips {
655 gpu1_alert0: t 675 gpu1_alert0: trip-point0 {
656 temper 676 temperature = <90000>;
657 hyster 677 hysteresis = <2000>;
658 type = 678 type = "hot";
659 }; 679 };
660 }; 680 };
661 }; 681 };
662 682
663 gpu-top-thermal { !! 683 gpu-thermal-top {
664 polling-delay-passive 684 polling-delay-passive = <250>;
>> 685 polling-delay = <1000>;
665 686
666 thermal-sensors = <&ts 687 thermal-sensors = <&tsens0 13>;
667 688
668 trips { 689 trips {
669 gpu2_alert0: t 690 gpu2_alert0: trip-point0 {
670 temper 691 temperature = <90000>;
671 hyster 692 hysteresis = <2000>;
672 type = 693 type = "hot";
673 }; 694 };
674 }; 695 };
675 }; 696 };
676 697
677 clust0-mhm-thermal { 698 clust0-mhm-thermal {
678 polling-delay-passive 699 polling-delay-passive = <250>;
>> 700 polling-delay = <1000>;
679 701
680 thermal-sensors = <&ts 702 thermal-sensors = <&tsens0 5>;
681 703
682 trips { 704 trips {
683 cluster0_mhm_a 705 cluster0_mhm_alert0: trip-point0 {
684 temper 706 temperature = <90000>;
685 hyster 707 hysteresis = <2000>;
686 type = 708 type = "hot";
687 }; 709 };
688 }; 710 };
689 }; 711 };
690 712
691 clust1-mhm-thermal { 713 clust1-mhm-thermal {
692 polling-delay-passive 714 polling-delay-passive = <250>;
>> 715 polling-delay = <1000>;
693 716
694 thermal-sensors = <&ts 717 thermal-sensors = <&tsens0 6>;
695 718
696 trips { 719 trips {
697 cluster1_mhm_a 720 cluster1_mhm_alert0: trip-point0 {
698 temper 721 temperature = <90000>;
699 hyster 722 hysteresis = <2000>;
700 type = 723 type = "hot";
701 }; 724 };
702 }; 725 };
703 }; 726 };
704 727
705 cluster1-l2-thermal { 728 cluster1-l2-thermal {
706 polling-delay-passive 729 polling-delay-passive = <250>;
>> 730 polling-delay = <1000>;
707 731
708 thermal-sensors = <&ts 732 thermal-sensors = <&tsens0 11>;
709 733
710 trips { 734 trips {
711 cluster1_l2_al 735 cluster1_l2_alert0: trip-point0 {
712 temper 736 temperature = <90000>;
713 hyster 737 hysteresis = <2000>;
714 type = 738 type = "hot";
715 }; 739 };
716 }; 740 };
717 }; 741 };
718 742
719 modem-thermal { 743 modem-thermal {
720 polling-delay-passive 744 polling-delay-passive = <250>;
>> 745 polling-delay = <1000>;
721 746
722 thermal-sensors = <&ts 747 thermal-sensors = <&tsens1 1>;
723 748
724 trips { 749 trips {
725 modem_alert0: 750 modem_alert0: trip-point0 {
726 temper 751 temperature = <90000>;
727 hyster 752 hysteresis = <2000>;
728 type = 753 type = "hot";
729 }; 754 };
730 }; 755 };
731 }; 756 };
732 757
733 mem-thermal { 758 mem-thermal {
734 polling-delay-passive 759 polling-delay-passive = <250>;
>> 760 polling-delay = <1000>;
735 761
736 thermal-sensors = <&ts 762 thermal-sensors = <&tsens1 2>;
737 763
738 trips { 764 trips {
739 mem_alert0: tr 765 mem_alert0: trip-point0 {
740 temper 766 temperature = <90000>;
741 hyster 767 hysteresis = <2000>;
742 type = 768 type = "hot";
743 }; 769 };
744 }; 770 };
745 }; 771 };
746 772
747 wlan-thermal { 773 wlan-thermal {
748 polling-delay-passive 774 polling-delay-passive = <250>;
>> 775 polling-delay = <1000>;
749 776
750 thermal-sensors = <&ts 777 thermal-sensors = <&tsens1 3>;
751 778
752 trips { 779 trips {
753 wlan_alert0: t 780 wlan_alert0: trip-point0 {
754 temper 781 temperature = <90000>;
755 hyster 782 hysteresis = <2000>;
756 type = 783 type = "hot";
757 }; 784 };
758 }; 785 };
759 }; 786 };
760 787
761 q6-dsp-thermal { 788 q6-dsp-thermal {
762 polling-delay-passive 789 polling-delay-passive = <250>;
>> 790 polling-delay = <1000>;
763 791
764 thermal-sensors = <&ts 792 thermal-sensors = <&tsens1 4>;
765 793
766 trips { 794 trips {
767 q6_dsp_alert0: 795 q6_dsp_alert0: trip-point0 {
768 temper 796 temperature = <90000>;
769 hyster 797 hysteresis = <2000>;
770 type = 798 type = "hot";
771 }; 799 };
772 }; 800 };
773 }; 801 };
774 802
775 camera-thermal { 803 camera-thermal {
776 polling-delay-passive 804 polling-delay-passive = <250>;
>> 805 polling-delay = <1000>;
777 806
778 thermal-sensors = <&ts 807 thermal-sensors = <&tsens1 5>;
779 808
780 trips { 809 trips {
781 camera_alert0: 810 camera_alert0: trip-point0 {
782 temper 811 temperature = <90000>;
783 hyster 812 hysteresis = <2000>;
784 type = 813 type = "hot";
785 }; 814 };
786 }; 815 };
787 }; 816 };
788 817
789 multimedia-thermal { 818 multimedia-thermal {
790 polling-delay-passive 819 polling-delay-passive = <250>;
>> 820 polling-delay = <1000>;
791 821
792 thermal-sensors = <&ts 822 thermal-sensors = <&tsens1 6>;
793 823
794 trips { 824 trips {
795 multimedia_ale 825 multimedia_alert0: trip-point0 {
796 temper 826 temperature = <90000>;
797 hyster 827 hysteresis = <2000>;
798 type = 828 type = "hot";
799 }; 829 };
800 }; 830 };
801 }; 831 };
802 }; 832 };
803 833
804 timer { 834 timer {
805 compatible = "arm,armv8-timer" 835 compatible = "arm,armv8-timer";
806 interrupts = <GIC_PPI 1 IRQ_TY 836 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
807 <GIC_PPI 2 IRQ_TY 837 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
808 <GIC_PPI 3 IRQ_TY 838 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
809 <GIC_PPI 0 IRQ_TY 839 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
810 }; 840 };
811 841
812 soc: soc@0 { !! 842 soc: soc {
813 #address-cells = <1>; 843 #address-cells = <1>;
814 #size-cells = <1>; 844 #size-cells = <1>;
815 ranges = <0 0 0 0xffffffff>; 845 ranges = <0 0 0 0xffffffff>;
816 compatible = "simple-bus"; 846 compatible = "simple-bus";
817 847
818 gcc: clock-controller@100000 { 848 gcc: clock-controller@100000 {
819 compatible = "qcom,gcc 849 compatible = "qcom,gcc-msm8998";
820 #clock-cells = <1>; 850 #clock-cells = <1>;
821 #reset-cells = <1>; 851 #reset-cells = <1>;
822 #power-domain-cells = 852 #power-domain-cells = <1>;
823 reg = <0x00100000 0xb0 853 reg = <0x00100000 0xb0000>;
824 <<
825 clock-names = "xo", "s <<
826 clocks = <&rpmcc RPM_S <<
827 <<
828 /* <<
829 * The hypervisor typi <<
830 * reside as read-only <<
831 * these clocks on a d <<
832 * enabled but unused <<
833 * to reboot. <<
834 * In light of that, w <<
835 * as protected. The b <<
836 * list of protected c <<
837 * desired for the HLO <<
838 */ <<
839 protected-clocks = <AG <<
840 <SS <<
841 <SS <<
842 }; 854 };
843 855
844 rpm_msg_ram: sram@778000 { !! 856 rpm_msg_ram: memory@778000 {
845 compatible = "qcom,rpm 857 compatible = "qcom,rpm-msg-ram";
846 reg = <0x00778000 0x70 858 reg = <0x00778000 0x7000>;
847 }; 859 };
848 860
849 qfprom: qfprom@784000 { !! 861 qfprom: qfprom@780000 {
850 compatible = "qcom,msm !! 862 compatible = "qcom,qfprom";
851 reg = <0x00784000 0x62 !! 863 reg = <0x00780000 0x621c>;
852 #address-cells = <1>; 864 #address-cells = <1>;
853 #size-cells = <1>; 865 #size-cells = <1>;
854 866
855 qusb2_hstx_trim: hstx- !! 867 qusb2_hstx_trim: hstx-trim@423a {
856 reg = <0x23a 0 !! 868 reg = <0x423a 0x1>;
857 bits = <0 4>; 869 bits = <0 4>;
858 }; 870 };
859 }; 871 };
860 872
861 tsens0: thermal@10ab000 { 873 tsens0: thermal@10ab000 {
862 compatible = "qcom,msm 874 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
863 reg = <0x010ab000 0x10 875 reg = <0x010ab000 0x1000>, /* TM */
864 <0x010aa000 0x10 876 <0x010aa000 0x1000>; /* SROT */
865 #qcom,sensors = <14>; 877 #qcom,sensors = <14>;
866 interrupts = <GIC_SPI 878 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
867 <GIC_SPI 879 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
868 interrupt-names = "upl 880 interrupt-names = "uplow", "critical";
869 #thermal-sensor-cells 881 #thermal-sensor-cells = <1>;
870 }; 882 };
871 883
872 tsens1: thermal@10ae000 { 884 tsens1: thermal@10ae000 {
873 compatible = "qcom,msm 885 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
874 reg = <0x010ae000 0x10 886 reg = <0x010ae000 0x1000>, /* TM */
875 <0x010ad000 0x10 887 <0x010ad000 0x1000>; /* SROT */
876 #qcom,sensors = <8>; 888 #qcom,sensors = <8>;
877 interrupts = <GIC_SPI 889 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
878 <GIC_SPI 890 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
879 interrupt-names = "upl 891 interrupt-names = "uplow", "critical";
880 #thermal-sensor-cells 892 #thermal-sensor-cells = <1>;
881 }; 893 };
882 894
883 anoc1_smmu: iommu@1680000 { 895 anoc1_smmu: iommu@1680000 {
884 compatible = "qcom,msm 896 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
885 reg = <0x01680000 0x10 897 reg = <0x01680000 0x10000>;
886 #iommu-cells = <1>; 898 #iommu-cells = <1>;
887 899
888 #global-interrupts = < 900 #global-interrupts = <0>;
889 interrupts = 901 interrupts =
890 <GIC_SPI 364 I 902 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
891 <GIC_SPI 365 I 903 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
892 <GIC_SPI 366 I 904 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
893 <GIC_SPI 367 I 905 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
894 <GIC_SPI 368 I 906 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
895 <GIC_SPI 369 I 907 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>;
896 }; 908 };
897 909
898 anoc2_smmu: iommu@16c0000 { 910 anoc2_smmu: iommu@16c0000 {
899 compatible = "qcom,msm 911 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
900 reg = <0x016c0000 0x40 912 reg = <0x016c0000 0x40000>;
901 #iommu-cells = <1>; 913 #iommu-cells = <1>;
902 914
903 #global-interrupts = < 915 #global-interrupts = <0>;
904 interrupts = 916 interrupts =
905 <GIC_SPI 373 I 917 <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>,
906 <GIC_SPI 374 I 918 <GIC_SPI 374 IRQ_TYPE_EDGE_RISING>,
907 <GIC_SPI 375 I 919 <GIC_SPI 375 IRQ_TYPE_EDGE_RISING>,
908 <GIC_SPI 376 I 920 <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>,
909 <GIC_SPI 377 I 921 <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>,
910 <GIC_SPI 378 I 922 <GIC_SPI 378 IRQ_TYPE_EDGE_RISING>,
911 <GIC_SPI 462 I 923 <GIC_SPI 462 IRQ_TYPE_EDGE_RISING>,
912 <GIC_SPI 463 I 924 <GIC_SPI 463 IRQ_TYPE_EDGE_RISING>,
913 <GIC_SPI 464 I 925 <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
914 <GIC_SPI 465 I 926 <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>;
915 }; 927 };
916 928
917 pcie0: pcie@1c00000 { !! 929 pcie0: pci@1c00000 {
918 compatible = "qcom,pci !! 930 compatible = "qcom,pcie-msm8996";
919 reg = <0x01c00000 0x20 !! 931 reg = <0x01c00000 0x2000>,
920 <0x1b000000 0xf1 !! 932 <0x1b000000 0xf1d>,
921 <0x1b000f20 0xa8 !! 933 <0x1b000f20 0xa8>,
922 <0x1b100000 0x10 !! 934 <0x1b100000 0x100000>;
923 reg-names = "parf", "d 935 reg-names = "parf", "dbi", "elbi", "config";
924 device_type = "pci"; 936 device_type = "pci";
925 linux,pci-domain = <0> 937 linux,pci-domain = <0>;
926 bus-range = <0x00 0xff 938 bus-range = <0x00 0xff>;
927 #address-cells = <3>; 939 #address-cells = <3>;
928 #size-cells = <2>; 940 #size-cells = <2>;
929 num-lanes = <1>; 941 num-lanes = <1>;
930 phys = <&pcie_phy>; !! 942 phys = <&pciephy>;
931 phy-names = "pciephy"; 943 phy-names = "pciephy";
932 status = "disabled"; <<
933 944
934 ranges = <0x01000000 0 945 ranges = <0x01000000 0x0 0x00000000 0x1b200000 0x0 0x100000>,
935 <0x02000000 0 946 <0x02000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>;
936 947
937 #interrupt-cells = <1> 948 #interrupt-cells = <1>;
938 interrupts = <GIC_SPI 949 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
939 interrupt-names = "msi 950 interrupt-names = "msi";
940 interrupt-map-mask = < 951 interrupt-map-mask = <0 0 0 0x7>;
941 interrupt-map = <0 0 0 !! 952 interrupt-map = <0 0 0 1 &intc 0 0 135 IRQ_TYPE_LEVEL_HIGH>,
942 <0 0 0 953 <0 0 0 2 &intc 0 0 136 IRQ_TYPE_LEVEL_HIGH>,
943 <0 0 0 954 <0 0 0 3 &intc 0 0 138 IRQ_TYPE_LEVEL_HIGH>,
944 <0 0 0 955 <0 0 0 4 &intc 0 0 139 IRQ_TYPE_LEVEL_HIGH>;
945 956
946 clocks = <&gcc GCC_PCI 957 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
947 <&gcc GCC_PCI <<
948 <&gcc GCC_PCI <<
949 <&gcc GCC_PCI 958 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
950 <&gcc GCC_PCI !! 959 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
951 clock-names = "pipe", !! 960 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
>> 961 <&gcc GCC_PCIE_0_AUX_CLK>;
>> 962 clock-names = "pipe", "bus_master", "bus_slave", "cfg", "aux";
952 963
953 power-domains = <&gcc 964 power-domains = <&gcc PCIE_0_GDSC>;
954 iommu-map = <0x100 &an 965 iommu-map = <0x100 &anoc1_smmu 0x1480 1>;
955 perst-gpios = <&tlmm 3 966 perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
956 <<
957 pcie@0 { <<
958 device_type = <<
959 reg = <0x0 0x0 <<
960 bus-range = <0 <<
961 <<
962 #address-cells <<
963 #size-cells = <<
964 ranges; <<
965 }; <<
966 }; 967 };
967 968
968 pcie_phy: phy@1c06000 { !! 969 phy@1c06000 {
969 compatible = "qcom,msm 970 compatible = "qcom,msm8998-qmp-pcie-phy";
970 reg = <0x01c06000 0x10 !! 971 reg = <0x01c06000 0x18c>;
971 status = "disabled"; !! 972 #address-cells = <1>;
>> 973 #size-cells = <1>;
>> 974 ranges;
972 975
973 clocks = <&gcc GCC_PCI 976 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
974 <&gcc GCC_PCI 977 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
975 <&gcc GCC_PCI !! 978 <&gcc GCC_PCIE_CLKREF_CLK>;
976 <&gcc GCC_PCI !! 979 clock-names = "aux", "cfg_ahb", "ref";
977 clock-names = "aux", <<
978 "cfg_ahb <<
979 "ref", <<
980 "pipe"; <<
981 <<
982 clock-output-names = " <<
983 #clock-cells = <0>; <<
984 <<
985 #phy-cells = <0>; <<
986 980
987 resets = <&gcc GCC_PCI 981 resets = <&gcc GCC_PCIE_0_PHY_BCR>, <&gcc GCC_PCIE_PHY_BCR>;
988 reset-names = "phy", " 982 reset-names = "phy", "common";
989 983
990 vdda-phy-supply = <&vr 984 vdda-phy-supply = <&vreg_l1a_0p875>;
991 vdda-pll-supply = <&vr 985 vdda-pll-supply = <&vreg_l2a_1p2>;
>> 986
>> 987 pciephy: lane@1c06800 {
>> 988 reg = <0x01c06200 0x128>, <0x01c06400 0x1fc>, <0x01c06800 0x20c>;
>> 989 #phy-cells = <0>;
>> 990
>> 991 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
>> 992 clock-names = "pipe0";
>> 993 clock-output-names = "pcie_0_pipe_clk_src";
>> 994 #clock-cells = <0>;
>> 995 };
992 }; 996 };
993 997
994 ufshc: ufshc@1da4000 { 998 ufshc: ufshc@1da4000 {
995 compatible = "qcom,msm 999 compatible = "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
996 reg = <0x01da4000 0x25 1000 reg = <0x01da4000 0x2500>;
997 interrupts = <GIC_SPI 1001 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
998 phys = <&ufsphy>; !! 1002 phys = <&ufsphy_lanes>;
999 phy-names = "ufsphy"; 1003 phy-names = "ufsphy";
1000 lanes-per-direction = 1004 lanes-per-direction = <2>;
1001 power-domains = <&gcc 1005 power-domains = <&gcc UFS_GDSC>;
1002 status = "disabled"; <<
1003 #reset-cells = <1>; 1006 #reset-cells = <1>;
1004 1007
1005 clock-names = 1008 clock-names =
1006 "core_clk", 1009 "core_clk",
1007 "bus_aggr_clk 1010 "bus_aggr_clk",
1008 "iface_clk", 1011 "iface_clk",
1009 "core_clk_uni 1012 "core_clk_unipro",
1010 "ref_clk", 1013 "ref_clk",
1011 "tx_lane0_syn 1014 "tx_lane0_sync_clk",
1012 "rx_lane0_syn 1015 "rx_lane0_sync_clk",
1013 "rx_lane1_syn 1016 "rx_lane1_sync_clk";
1014 clocks = 1017 clocks =
1015 <&gcc GCC_UFS 1018 <&gcc GCC_UFS_AXI_CLK>,
1016 <&gcc GCC_AGG 1019 <&gcc GCC_AGGRE1_UFS_AXI_CLK>,
1017 <&gcc GCC_UFS 1020 <&gcc GCC_UFS_AHB_CLK>,
1018 <&gcc GCC_UFS 1021 <&gcc GCC_UFS_UNIPRO_CORE_CLK>,
1019 <&rpmcc RPM_S 1022 <&rpmcc RPM_SMD_LN_BB_CLK1>,
1020 <&gcc GCC_UFS 1023 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
1021 <&gcc GCC_UFS 1024 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>,
1022 <&gcc GCC_UFS 1025 <&gcc GCC_UFS_RX_SYMBOL_1_CLK>;
1023 freq-table-hz = 1026 freq-table-hz =
1024 <50000000 200 1027 <50000000 200000000>,
1025 <0 0>, 1028 <0 0>,
1026 <0 0>, 1029 <0 0>,
1027 <37500000 150 1030 <37500000 150000000>,
1028 <0 0>, 1031 <0 0>,
1029 <0 0>, 1032 <0 0>,
1030 <0 0>, 1033 <0 0>,
1031 <0 0>; 1034 <0 0>;
1032 1035
1033 resets = <&gcc GCC_UF 1036 resets = <&gcc GCC_UFS_BCR>;
1034 reset-names = "rst"; 1037 reset-names = "rst";
1035 }; 1038 };
1036 1039
1037 ufsphy: phy@1da7000 { 1040 ufsphy: phy@1da7000 {
1038 compatible = "qcom,ms 1041 compatible = "qcom,msm8998-qmp-ufs-phy";
1039 reg = <0x01da7000 0x1 !! 1042 reg = <0x01da7000 0x18c>;
>> 1043 #address-cells = <1>;
>> 1044 #size-cells = <1>;
>> 1045 ranges;
1040 1046
1041 clocks = <&rpmcc RPM_ !! 1047 clock-names =
1042 <&gcc GCC_UF !! 1048 "ref",
1043 <&gcc GCC_UF !! 1049 "ref_aux";
1044 clock-names = "ref", !! 1050 clocks =
1045 "ref_au !! 1051 <&gcc GCC_UFS_CLKREF_CLK>,
1046 "qref"; !! 1052 <&gcc GCC_UFS_PHY_AUX_CLK>;
1047 1053
1048 reset-names = "ufsphy 1054 reset-names = "ufsphy";
1049 resets = <&ufshc 0>; 1055 resets = <&ufshc 0>;
1050 1056
1051 #phy-cells = <0>; !! 1057 ufsphy_lanes: lanes@1da7400 {
1052 status = "disabled"; !! 1058 reg = <0x01da7400 0x128>,
1053 }; !! 1059 <0x01da7600 0x1fc>,
1054 !! 1060 <0x01da7c00 0x1dc>,
1055 tcsr_mutex: hwlock@1f40000 { !! 1061 <0x01da7800 0x128>,
1056 compatible = "qcom,tc !! 1062 <0x01da7a00 0x1fc>;
1057 reg = <0x01f40000 0x2 !! 1063 #phy-cells = <0>;
1058 #hwlock-cells = <1>; !! 1064 };
1059 }; <<
1060 <<
1061 tcsr_regs_1: syscon@1f60000 { <<
1062 compatible = "qcom,ms <<
1063 reg = <0x01f60000 0x2 <<
1064 }; 1065 };
1065 1066
1066 tcsr_regs_2: syscon@1fc0000 { !! 1067 tcsr_mutex_regs: syscon@1f40000 {
1067 compatible = "qcom,ms !! 1068 compatible = "syscon";
1068 reg = <0x01fc0000 0x2 !! 1069 reg = <0x01f40000 0x40000>;
1069 }; 1070 };
1070 1071
1071 tlmm: pinctrl@3400000 { 1072 tlmm: pinctrl@3400000 {
1072 compatible = "qcom,ms 1073 compatible = "qcom,msm8998-pinctrl";
1073 reg = <0x03400000 0xc 1074 reg = <0x03400000 0xc00000>;
1074 interrupts = <GIC_SPI 1075 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1075 gpio-ranges = <&tlmm <<
1076 gpio-controller; 1076 gpio-controller;
1077 #gpio-cells = <2>; !! 1077 #gpio-cells = <0x2>;
1078 interrupt-controller; 1078 interrupt-controller;
1079 #interrupt-cells = <2 !! 1079 #interrupt-cells = <0x2>;
1080 <<
1081 sdc2_on: sdc2-on-stat <<
1082 clk-pins { <<
1083 pins <<
1084 drive <<
1085 bias- <<
1086 }; <<
1087 <<
1088 cmd-pins { <<
1089 pins <<
1090 drive <<
1091 bias- <<
1092 }; <<
1093 <<
1094 data-pins { <<
1095 pins <<
1096 drive <<
1097 bias- <<
1098 }; <<
1099 }; <<
1100 <<
1101 sdc2_off: sdc2-off-st <<
1102 clk-pins { <<
1103 pins <<
1104 drive <<
1105 bias- <<
1106 }; <<
1107 <<
1108 cmd-pins { <<
1109 pins <<
1110 drive <<
1111 bias- <<
1112 }; <<
1113 <<
1114 data-pins { <<
1115 pins <<
1116 drive <<
1117 bias- <<
1118 }; <<
1119 }; <<
1120 <<
1121 sdc2_cd: sdc2-cd-stat <<
1122 pins = "gpio9 <<
1123 function = "g <<
1124 bias-pull-up; <<
1125 drive-strengt <<
1126 }; <<
1127 <<
1128 blsp1_uart3_on: blsp1 <<
1129 tx-pins { <<
1130 pins <<
1131 funct <<
1132 drive <<
1133 bias- <<
1134 }; <<
1135 <<
1136 rx-pins { <<
1137 pins <<
1138 funct <<
1139 drive <<
1140 bias- <<
1141 }; <<
1142 <<
1143 cts-pins { <<
1144 pins <<
1145 funct <<
1146 drive <<
1147 bias- <<
1148 }; <<
1149 <<
1150 rfr-pins { <<
1151 pins <<
1152 funct <<
1153 drive <<
1154 bias- <<
1155 }; <<
1156 }; <<
1157 <<
1158 blsp1_i2c1_default: b <<
1159 pins = "gpio2 <<
1160 function = "b <<
1161 drive-strengt <<
1162 bias-disable; <<
1163 }; <<
1164 <<
1165 blsp1_i2c1_sleep: bls <<
1166 pins = "gpio2 <<
1167 function = "b <<
1168 drive-strengt <<
1169 bias-pull-up; <<
1170 }; <<
1171 <<
1172 blsp1_i2c2_default: b <<
1173 pins = "gpio3 <<
1174 function = "b <<
1175 drive-strengt <<
1176 bias-disable; <<
1177 }; <<
1178 <<
1179 blsp1_i2c2_sleep: bls <<
1180 pins = "gpio3 <<
1181 function = "b <<
1182 drive-strengt <<
1183 bias-pull-up; <<
1184 }; <<
1185 <<
1186 blsp1_i2c3_default: b <<
1187 pins = "gpio4 <<
1188 function = "b <<
1189 drive-strengt <<
1190 bias-disable; <<
1191 }; <<
1192 <<
1193 blsp1_i2c3_sleep: bls <<
1194 pins = "gpio4 <<
1195 function = "b <<
1196 drive-strengt <<
1197 bias-pull-up; <<
1198 }; <<
1199 <<
1200 blsp1_i2c4_default: b <<
1201 pins = "gpio1 <<
1202 function = "b <<
1203 drive-strengt <<
1204 bias-disable; <<
1205 }; <<
1206 <<
1207 blsp1_i2c4_sleep: bls <<
1208 pins = "gpio1 <<
1209 function = "b <<
1210 drive-strengt <<
1211 bias-pull-up; <<
1212 }; <<
1213 <<
1214 blsp1_i2c5_default: b <<
1215 pins = "gpio8 <<
1216 function = "b <<
1217 drive-strengt <<
1218 bias-disable; <<
1219 }; <<
1220 <<
1221 blsp1_i2c5_sleep: bls <<
1222 pins = "gpio8 <<
1223 function = "b <<
1224 drive-strengt <<
1225 bias-pull-up; <<
1226 }; <<
1227 <<
1228 blsp1_i2c6_default: b <<
1229 pins = "gpio4 <<
1230 function = "b <<
1231 drive-strengt <<
1232 bias-disable; <<
1233 }; <<
1234 <<
1235 blsp1_i2c6_sleep: bls <<
1236 pins = "gpio4 <<
1237 function = "b <<
1238 drive-strengt <<
1239 bias-pull-up; <<
1240 }; <<
1241 <<
1242 blsp1_spi_b_default: <<
1243 pins = "gpio2 <<
1244 function = "b <<
1245 drive-strengt <<
1246 bias-disable; <<
1247 }; <<
1248 <<
1249 blsp1_spi1_default: b <<
1250 pins = "gpio0 <<
1251 function = "b <<
1252 drive-strengt <<
1253 bias-disable; <<
1254 }; <<
1255 <<
1256 blsp1_spi2_default: b <<
1257 pins = "gpio3 <<
1258 function = "b <<
1259 drive-strengt <<
1260 bias-disable; <<
1261 }; <<
1262 <<
1263 blsp1_spi3_default: b <<
1264 pins = "gpio4 <<
1265 function = "b <<
1266 drive-strengt <<
1267 bias-disable; <<
1268 }; <<
1269 <<
1270 blsp1_spi4_default: b <<
1271 pins = "gpio8 <<
1272 function = "b <<
1273 drive-strengt <<
1274 bias-disable; <<
1275 }; <<
1276 <<
1277 blsp1_spi5_default: b <<
1278 pins = "gpio8 <<
1279 function = "b <<
1280 drive-strengt <<
1281 bias-disable; <<
1282 }; <<
1283 <<
1284 blsp1_spi6_default: b <<
1285 pins = "gpio4 <<
1286 function = "b <<
1287 drive-strengt <<
1288 bias-disable; <<
1289 }; <<
1290 <<
1291 <<
1292 /* 6 interfaces per Q <<
1293 blsp2_i2c1_default: b <<
1294 pins = "gpio5 <<
1295 function = "b <<
1296 drive-strengt <<
1297 bias-disable; <<
1298 }; <<
1299 <<
1300 blsp2_i2c1_sleep: bls <<
1301 pins = "gpio5 <<
1302 function = "b <<
1303 drive-strengt <<
1304 bias-pull-up; <<
1305 }; <<
1306 <<
1307 blsp2_i2c2_default: b <<
1308 pins = "gpio6 <<
1309 function = "b <<
1310 drive-strengt <<
1311 bias-disable; <<
1312 }; <<
1313 <<
1314 blsp2_i2c2_sleep: bls <<
1315 pins = "gpio6 <<
1316 function = "b <<
1317 drive-strengt <<
1318 bias-pull-up; <<
1319 }; <<
1320 <<
1321 blsp2_i2c3_default: b <<
1322 pins = "gpio5 <<
1323 function = "b <<
1324 drive-strengt <<
1325 bias-disable; <<
1326 }; <<
1327 <<
1328 blsp2_i2c3_sleep: bls <<
1329 pins = "gpio5 <<
1330 function = "b <<
1331 drive-strengt <<
1332 bias-pull-up; <<
1333 }; <<
1334 <<
1335 blsp2_i2c4_default: b <<
1336 pins = "gpio6 <<
1337 function = "b <<
1338 drive-strengt <<
1339 bias-disable; <<
1340 }; <<
1341 <<
1342 blsp2_i2c4_sleep: bls <<
1343 pins = "gpio6 <<
1344 function = "b <<
1345 drive-strengt <<
1346 bias-pull-up; <<
1347 }; <<
1348 <<
1349 blsp2_i2c5_default: b <<
1350 pins = "gpio6 <<
1351 function = "b <<
1352 drive-strengt <<
1353 bias-disable; <<
1354 }; <<
1355 <<
1356 blsp2_i2c5_sleep: bls <<
1357 pins = "gpio6 <<
1358 function = "b <<
1359 drive-strengt <<
1360 bias-pull-up; <<
1361 }; <<
1362 <<
1363 blsp2_i2c6_default: b <<
1364 pins = "gpio8 <<
1365 function = "b <<
1366 drive-strengt <<
1367 bias-disable; <<
1368 }; <<
1369 <<
1370 blsp2_i2c6_sleep: bls <<
1371 pins = "gpio8 <<
1372 function = "b <<
1373 drive-strengt <<
1374 bias-pull-up; <<
1375 }; <<
1376 <<
1377 blsp2_spi1_default: b <<
1378 pins = "gpio5 <<
1379 function = "b <<
1380 drive-strengt <<
1381 bias-disable; <<
1382 }; <<
1383 <<
1384 blsp2_spi2_default: b <<
1385 pins = "gpio4 <<
1386 function = "b <<
1387 drive-strengt <<
1388 bias-disable; <<
1389 }; <<
1390 <<
1391 blsp2_spi3_default: b <<
1392 pins = "gpio4 <<
1393 function = "b <<
1394 drive-strengt <<
1395 bias-disable; <<
1396 }; <<
1397 <<
1398 blsp2_spi4_default: b <<
1399 pins = "gpio6 <<
1400 function = "b <<
1401 drive-strengt <<
1402 bias-disable; <<
1403 }; <<
1404 <<
1405 blsp2_spi5_default: b <<
1406 pins = "gpio5 <<
1407 function = "b <<
1408 drive-strengt <<
1409 bias-disable; <<
1410 }; <<
1411 <<
1412 blsp2_spi6_default: b <<
1413 pins = "gpio8 <<
1414 function = "b <<
1415 drive-strengt <<
1416 bias-disable; <<
1417 }; <<
1418 }; 1080 };
1419 1081
1420 remoteproc_mss: remoteproc@40 1082 remoteproc_mss: remoteproc@4080000 {
1421 compatible = "qcom,ms 1083 compatible = "qcom,msm8998-mss-pil";
1422 reg = <0x04080000 0x1 1084 reg = <0x04080000 0x100>, <0x04180000 0x20>;
1423 reg-names = "qdsp6", 1085 reg-names = "qdsp6", "rmb";
1424 1086
1425 interrupts-extended = 1087 interrupts-extended =
1426 <&intc GIC_SP 1088 <&intc GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
1427 <&modem_smp2p 1089 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1428 <&modem_smp2p 1090 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1429 <&modem_smp2p 1091 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1430 <&modem_smp2p 1092 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
1431 <&modem_smp2p 1093 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
1432 interrupt-names = "wd 1094 interrupt-names = "wdog", "fatal", "ready",
1433 "ha 1095 "handover", "stop-ack",
1434 "sh 1096 "shutdown-ack";
1435 1097
1436 clocks = <&gcc GCC_MS 1098 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
1437 <&gcc GCC_BI 1099 <&gcc GCC_BIMC_MSS_Q6_AXI_CLK>,
1438 <&gcc GCC_BO 1100 <&gcc GCC_BOOT_ROM_AHB_CLK>,
1439 <&gcc GCC_MS 1101 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
1440 <&gcc GCC_MS 1102 <&gcc GCC_MSS_SNOC_AXI_CLK>,
1441 <&gcc GCC_MS 1103 <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>,
1442 <&rpmcc RPM_ 1104 <&rpmcc RPM_SMD_QDSS_CLK>,
1443 <&rpmcc RPM_ 1105 <&rpmcc RPM_SMD_XO_CLK_SRC>;
1444 clock-names = "iface" 1106 clock-names = "iface", "bus", "mem", "gpll0_mss",
1445 "snoc_a 1107 "snoc_axi", "mnoc_axi", "qdss", "xo";
1446 1108
1447 qcom,smem-states = <& 1109 qcom,smem-states = <&modem_smp2p_out 0>;
1448 qcom,smem-state-names 1110 qcom,smem-state-names = "stop";
1449 1111
1450 resets = <&gcc GCC_MS 1112 resets = <&gcc GCC_MSS_RESTART>;
1451 reset-names = "mss_re 1113 reset-names = "mss_restart";
1452 1114
1453 qcom,halt-regs = <&tc !! 1115 qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
1454 1116
1455 power-domains = <&rpm 1117 power-domains = <&rpmpd MSM8998_VDDCX>,
1456 <&rpm 1118 <&rpmpd MSM8998_VDDMX>;
1457 power-domain-names = 1119 power-domain-names = "cx", "mx";
1458 1120
1459 status = "disabled"; <<
1460 <<
1461 mba { 1121 mba {
1462 memory-region 1122 memory-region = <&mba_mem>;
1463 }; 1123 };
1464 1124
1465 mpss { 1125 mpss {
1466 memory-region 1126 memory-region = <&mpss_mem>;
1467 }; 1127 };
1468 1128
1469 metadata { <<
1470 memory-region <<
1471 }; <<
1472 <<
1473 glink-edge { 1129 glink-edge {
1474 interrupts = 1130 interrupts = <GIC_SPI 452 IRQ_TYPE_EDGE_RISING>;
1475 label = "mode 1131 label = "modem";
1476 qcom,remote-p 1132 qcom,remote-pid = <1>;
1477 mboxes = <&ap 1133 mboxes = <&apcs_glb 15>;
1478 }; 1134 };
1479 }; 1135 };
1480 1136
1481 adreno_gpu: gpu@5000000 { <<
1482 compatible = "qcom,ad <<
1483 reg = <0x05000000 0x4 <<
1484 reg-names = "kgsl_3d0 <<
1485 <<
1486 clocks = <&gcc GCC_GP <<
1487 <&gpucc RBBMT <<
1488 <&gcc GCC_BIM <<
1489 <&gcc GCC_GPU <<
1490 <&gpucc RBCPR <<
1491 <&gpucc GFX3D <<
1492 clock-names = "iface" <<
1493 "rbbmtimer", <<
1494 "mem", <<
1495 "mem_iface", <<
1496 "rbcpr", <<
1497 "core"; <<
1498 <<
1499 interrupts = <GIC_SPI <<
1500 iommus = <&adreno_smm <<
1501 operating-points-v2 = <<
1502 power-domains = <&rpm <<
1503 status = "disabled"; <<
1504 <<
1505 gpu_opp_table: opp-ta <<
1506 compatible = <<
1507 opp-710000097 <<
1508 opp-h <<
1509 opp-l <<
1510 opp-s <<
1511 }; <<
1512 <<
1513 opp-670000048 <<
1514 opp-h <<
1515 opp-l <<
1516 opp-s <<
1517 }; <<
1518 <<
1519 opp-596000097 <<
1520 opp-h <<
1521 opp-l <<
1522 opp-s <<
1523 }; <<
1524 <<
1525 opp-515000097 <<
1526 opp-h <<
1527 opp-l <<
1528 opp-s <<
1529 }; <<
1530 <<
1531 opp-414000000 <<
1532 opp-h <<
1533 opp-l <<
1534 opp-s <<
1535 }; <<
1536 <<
1537 opp-342000000 <<
1538 opp-h <<
1539 opp-l <<
1540 opp-s <<
1541 }; <<
1542 <<
1543 opp-257000000 <<
1544 opp-h <<
1545 opp-l <<
1546 opp-s <<
1547 }; <<
1548 }; <<
1549 }; <<
1550 <<
1551 adreno_smmu: iommu@5040000 { <<
1552 compatible = "qcom,ms <<
1553 reg = <0x05040000 0x1 <<
1554 clocks = <&gcc GCC_GP <<
1555 <&gcc GCC_BI <<
1556 <&gcc GCC_GP <<
1557 clock-names = "iface" <<
1558 <<
1559 #global-interrupts = <<
1560 #iommu-cells = <1>; <<
1561 interrupts = <<
1562 <GIC_SPI 329 <<
1563 <GIC_SPI 330 <<
1564 <GIC_SPI 331 <<
1565 /* <<
1566 * GPU-GX GDSC's pare <<
1567 * GPU-CX for SMMU bu <<
1568 * Contemporarily, we <<
1569 * domain in the Adre <<
1570 * Enable GPU CX/GX G <<
1571 * SoC VDDMX RPM Powe <<
1572 */ <<
1573 power-domains = <&gpu <<
1574 }; <<
1575 <<
1576 gpucc: clock-controller@50650 1137 gpucc: clock-controller@5065000 {
1577 compatible = "qcom,ms 1138 compatible = "qcom,msm8998-gpucc";
1578 #clock-cells = <1>; 1139 #clock-cells = <1>;
1579 #reset-cells = <1>; 1140 #reset-cells = <1>;
1580 #power-domain-cells = 1141 #power-domain-cells = <1>;
1581 reg = <0x05065000 0x9 1142 reg = <0x05065000 0x9000>;
1582 1143
1583 clocks = <&rpmcc RPM_ 1144 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1584 <&gcc GCC_GP !! 1145 <&gcc GPLL0_OUT_MAIN>;
1585 clock-names = "xo", 1146 clock-names = "xo",
1586 "gpll0" 1147 "gpll0";
1587 }; 1148 };
1588 1149
1589 lpass_q6_smmu: iommu@5100000 <<
1590 compatible = "qcom,ms <<
1591 reg = <0x05100000 0x4 <<
1592 clocks = <&gcc HLOS1_ <<
1593 clock-names = "bus"; <<
1594 <<
1595 #global-interrupts = <<
1596 #iommu-cells = <1>; <<
1597 interrupts = <<
1598 <GIC_SPI 226 <<
1599 <GIC_SPI 393 <<
1600 <GIC_SPI 394 <<
1601 <GIC_SPI 395 <<
1602 <GIC_SPI 396 <<
1603 <GIC_SPI 397 <<
1604 <GIC_SPI 398 <<
1605 <GIC_SPI 399 <<
1606 <GIC_SPI 400 <<
1607 <GIC_SPI 401 <<
1608 <GIC_SPI 402 <<
1609 <GIC_SPI 403 <<
1610 <GIC_SPI 137 <<
1611 <<
1612 power-domains = <&gcc <<
1613 status = "disabled"; <<
1614 }; <<
1615 <<
1616 remoteproc_slpi: remoteproc@5 1150 remoteproc_slpi: remoteproc@5800000 {
1617 compatible = "qcom,ms 1151 compatible = "qcom,msm8998-slpi-pas";
1618 reg = <0x05800000 0x4 1152 reg = <0x05800000 0x4040>;
1619 1153
1620 interrupts-extended = 1154 interrupts-extended = <&intc GIC_SPI 390 IRQ_TYPE_EDGE_RISING>,
1621 1155 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1622 1156 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1623 1157 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1624 1158 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1625 interrupt-names = "wd 1159 interrupt-names = "wdog", "fatal", "ready",
1626 "ha 1160 "handover", "stop-ack";
1627 1161
1628 px-supply = <&vreg_lv 1162 px-supply = <&vreg_lvs2a_1p8>;
1629 1163
1630 clocks = <&rpmcc RPM_ !! 1164 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1631 clock-names = "xo"; !! 1165 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
>> 1166 clock-names = "xo", "aggre2";
1632 1167
1633 memory-region = <&slp 1168 memory-region = <&slpi_mem>;
1634 1169
1635 qcom,smem-states = <& 1170 qcom,smem-states = <&slpi_smp2p_out 0>;
1636 qcom,smem-state-names 1171 qcom,smem-state-names = "stop";
1637 1172
1638 power-domains = <&rpm 1173 power-domains = <&rpmpd MSM8998_SSCCX>;
1639 power-domain-names = 1174 power-domain-names = "ssc_cx";
1640 1175
1641 status = "disabled"; 1176 status = "disabled";
1642 1177
1643 glink-edge { 1178 glink-edge {
1644 interrupts = 1179 interrupts = <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>;
1645 label = "dsps 1180 label = "dsps";
1646 qcom,remote-p 1181 qcom,remote-pid = <3>;
1647 mboxes = <&ap 1182 mboxes = <&apcs_glb 27>;
1648 }; 1183 };
1649 }; 1184 };
1650 1185
1651 stm: stm@6002000 { 1186 stm: stm@6002000 {
1652 compatible = "arm,cor 1187 compatible = "arm,coresight-stm", "arm,primecell";
1653 reg = <0x06002000 0x1 1188 reg = <0x06002000 0x1000>,
1654 <0x16280000 0x1 1189 <0x16280000 0x180000>;
1655 reg-names = "stm-base 1190 reg-names = "stm-base", "stm-stimulus-base";
1656 status = "disabled"; 1191 status = "disabled";
1657 1192
1658 clocks = <&rpmcc RPM_ 1193 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1659 clock-names = "apb_pc 1194 clock-names = "apb_pclk", "atclk";
1660 1195
1661 out-ports { 1196 out-ports {
1662 port { 1197 port {
1663 stm_o 1198 stm_out: endpoint {
1664 1199 remote-endpoint = <&funnel0_in7>;
1665 }; 1200 };
1666 }; 1201 };
1667 }; 1202 };
1668 }; 1203 };
1669 1204
1670 funnel1: funnel@6041000 { 1205 funnel1: funnel@6041000 {
1671 compatible = "arm,cor 1206 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1672 reg = <0x06041000 0x1 1207 reg = <0x06041000 0x1000>;
1673 status = "disabled"; 1208 status = "disabled";
1674 1209
1675 clocks = <&rpmcc RPM_ 1210 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1676 clock-names = "apb_pc 1211 clock-names = "apb_pclk", "atclk";
1677 1212
1678 out-ports { 1213 out-ports {
1679 port { 1214 port {
1680 funne 1215 funnel0_out: endpoint {
1681 1216 remote-endpoint =
1682 1217 <&merge_funnel_in0>;
1683 }; 1218 };
1684 }; 1219 };
1685 }; 1220 };
1686 1221
1687 in-ports { 1222 in-ports {
1688 #address-cell 1223 #address-cells = <1>;
1689 #size-cells = 1224 #size-cells = <0>;
1690 1225
1691 port@7 { 1226 port@7 {
1692 reg = 1227 reg = <7>;
1693 funne 1228 funnel0_in7: endpoint {
1694 1229 remote-endpoint = <&stm_out>;
1695 }; 1230 };
1696 }; 1231 };
1697 }; 1232 };
1698 }; 1233 };
1699 1234
1700 funnel2: funnel@6042000 { 1235 funnel2: funnel@6042000 {
1701 compatible = "arm,cor 1236 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1702 reg = <0x06042000 0x1 1237 reg = <0x06042000 0x1000>;
1703 status = "disabled"; 1238 status = "disabled";
1704 1239
1705 clocks = <&rpmcc RPM_ 1240 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1706 clock-names = "apb_pc 1241 clock-names = "apb_pclk", "atclk";
1707 1242
1708 out-ports { 1243 out-ports {
1709 port { 1244 port {
1710 funne 1245 funnel1_out: endpoint {
1711 1246 remote-endpoint =
1712 1247 <&merge_funnel_in1>;
1713 }; 1248 };
1714 }; 1249 };
1715 }; 1250 };
1716 1251
1717 in-ports { 1252 in-ports {
1718 #address-cell 1253 #address-cells = <1>;
1719 #size-cells = 1254 #size-cells = <0>;
1720 1255
1721 port@6 { 1256 port@6 {
1722 reg = 1257 reg = <6>;
1723 funne 1258 funnel1_in6: endpoint {
1724 1259 remote-endpoint =
1725 1260 <&apss_merge_funnel_out>;
1726 }; 1261 };
1727 }; 1262 };
1728 }; 1263 };
1729 }; 1264 };
1730 1265
1731 funnel3: funnel@6045000 { 1266 funnel3: funnel@6045000 {
1732 compatible = "arm,cor 1267 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1733 reg = <0x06045000 0x1 1268 reg = <0x06045000 0x1000>;
1734 status = "disabled"; 1269 status = "disabled";
1735 1270
1736 clocks = <&rpmcc RPM_ 1271 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1737 clock-names = "apb_pc 1272 clock-names = "apb_pclk", "atclk";
1738 1273
1739 out-ports { 1274 out-ports {
1740 port { 1275 port {
1741 merge 1276 merge_funnel_out: endpoint {
1742 1277 remote-endpoint =
1743 1278 <&etf_in>;
1744 }; 1279 };
1745 }; 1280 };
1746 }; 1281 };
1747 1282
1748 in-ports { 1283 in-ports {
1749 #address-cell 1284 #address-cells = <1>;
1750 #size-cells = 1285 #size-cells = <0>;
1751 1286
1752 port@0 { 1287 port@0 {
1753 reg = 1288 reg = <0>;
1754 merge 1289 merge_funnel_in0: endpoint {
1755 1290 remote-endpoint =
1756 1291 <&funnel0_out>;
1757 }; 1292 };
1758 }; 1293 };
1759 1294
1760 port@1 { 1295 port@1 {
1761 reg = 1296 reg = <1>;
1762 merge 1297 merge_funnel_in1: endpoint {
1763 1298 remote-endpoint =
1764 1299 <&funnel1_out>;
1765 }; 1300 };
1766 }; 1301 };
1767 }; 1302 };
1768 }; 1303 };
1769 1304
1770 replicator1: replicator@60460 1305 replicator1: replicator@6046000 {
1771 compatible = "arm,cor 1306 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
1772 reg = <0x06046000 0x1 1307 reg = <0x06046000 0x1000>;
1773 status = "disabled"; 1308 status = "disabled";
1774 1309
1775 clocks = <&rpmcc RPM_ 1310 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1776 clock-names = "apb_pc 1311 clock-names = "apb_pclk", "atclk";
1777 1312
1778 out-ports { 1313 out-ports {
1779 port { 1314 port {
1780 repli 1315 replicator_out: endpoint {
1781 1316 remote-endpoint = <&etr_in>;
1782 }; 1317 };
1783 }; 1318 };
1784 }; 1319 };
1785 1320
1786 in-ports { 1321 in-ports {
1787 port { 1322 port {
1788 repli 1323 replicator_in: endpoint {
1789 1324 remote-endpoint = <&etf_out>;
1790 }; 1325 };
1791 }; 1326 };
1792 }; 1327 };
1793 }; 1328 };
1794 1329
1795 etf: etf@6047000 { 1330 etf: etf@6047000 {
1796 compatible = "arm,cor 1331 compatible = "arm,coresight-tmc", "arm,primecell";
1797 reg = <0x06047000 0x1 1332 reg = <0x06047000 0x1000>;
1798 status = "disabled"; 1333 status = "disabled";
1799 1334
1800 clocks = <&rpmcc RPM_ 1335 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1801 clock-names = "apb_pc 1336 clock-names = "apb_pclk", "atclk";
1802 1337
1803 out-ports { 1338 out-ports {
1804 port { 1339 port {
1805 etf_o 1340 etf_out: endpoint {
1806 1341 remote-endpoint =
1807 1342 <&replicator_in>;
1808 }; 1343 };
1809 }; 1344 };
1810 }; 1345 };
1811 1346
1812 in-ports { 1347 in-ports {
1813 port { 1348 port {
1814 etf_i 1349 etf_in: endpoint {
1815 1350 remote-endpoint =
1816 1351 <&merge_funnel_out>;
1817 }; 1352 };
1818 }; 1353 };
1819 }; 1354 };
1820 }; 1355 };
1821 1356
1822 etr: etr@6048000 { 1357 etr: etr@6048000 {
1823 compatible = "arm,cor 1358 compatible = "arm,coresight-tmc", "arm,primecell";
1824 reg = <0x06048000 0x1 1359 reg = <0x06048000 0x1000>;
1825 status = "disabled"; 1360 status = "disabled";
1826 1361
1827 clocks = <&rpmcc RPM_ 1362 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1828 clock-names = "apb_pc 1363 clock-names = "apb_pclk", "atclk";
1829 arm,scatter-gather; 1364 arm,scatter-gather;
1830 1365
1831 in-ports { 1366 in-ports {
1832 port { 1367 port {
1833 etr_i 1368 etr_in: endpoint {
1834 1369 remote-endpoint =
1835 1370 <&replicator_out>;
1836 }; 1371 };
1837 }; 1372 };
1838 }; 1373 };
1839 }; 1374 };
1840 1375
1841 etm1: etm@7840000 { 1376 etm1: etm@7840000 {
1842 compatible = "arm,cor 1377 compatible = "arm,coresight-etm4x", "arm,primecell";
1843 reg = <0x07840000 0x1 1378 reg = <0x07840000 0x1000>;
1844 status = "disabled"; 1379 status = "disabled";
1845 1380
1846 clocks = <&rpmcc RPM_ 1381 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1847 clock-names = "apb_pc 1382 clock-names = "apb_pclk", "atclk";
1848 1383
1849 cpu = <&CPU0>; 1384 cpu = <&CPU0>;
1850 1385
1851 out-ports { 1386 out-ports {
1852 port { 1387 port {
1853 etm0_ 1388 etm0_out: endpoint {
1854 1389 remote-endpoint =
1855 1390 <&apss_funnel_in0>;
1856 }; 1391 };
1857 }; 1392 };
1858 }; 1393 };
1859 }; 1394 };
1860 1395
1861 etm2: etm@7940000 { 1396 etm2: etm@7940000 {
1862 compatible = "arm,cor 1397 compatible = "arm,coresight-etm4x", "arm,primecell";
1863 reg = <0x07940000 0x1 1398 reg = <0x07940000 0x1000>;
1864 status = "disabled"; 1399 status = "disabled";
1865 1400
1866 clocks = <&rpmcc RPM_ 1401 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1867 clock-names = "apb_pc 1402 clock-names = "apb_pclk", "atclk";
1868 1403
1869 cpu = <&CPU1>; 1404 cpu = <&CPU1>;
1870 1405
1871 out-ports { 1406 out-ports {
1872 port { 1407 port {
1873 etm1_ 1408 etm1_out: endpoint {
1874 1409 remote-endpoint =
1875 1410 <&apss_funnel_in1>;
1876 }; 1411 };
1877 }; 1412 };
1878 }; 1413 };
1879 }; 1414 };
1880 1415
1881 etm3: etm@7a40000 { 1416 etm3: etm@7a40000 {
1882 compatible = "arm,cor 1417 compatible = "arm,coresight-etm4x", "arm,primecell";
1883 reg = <0x07a40000 0x1 1418 reg = <0x07a40000 0x1000>;
1884 status = "disabled"; 1419 status = "disabled";
1885 1420
1886 clocks = <&rpmcc RPM_ 1421 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1887 clock-names = "apb_pc 1422 clock-names = "apb_pclk", "atclk";
1888 1423
1889 cpu = <&CPU2>; 1424 cpu = <&CPU2>;
1890 1425
1891 out-ports { 1426 out-ports {
1892 port { 1427 port {
1893 etm2_ 1428 etm2_out: endpoint {
1894 1429 remote-endpoint =
1895 1430 <&apss_funnel_in2>;
1896 }; 1431 };
1897 }; 1432 };
1898 }; 1433 };
1899 }; 1434 };
1900 1435
1901 etm4: etm@7b40000 { 1436 etm4: etm@7b40000 {
1902 compatible = "arm,cor 1437 compatible = "arm,coresight-etm4x", "arm,primecell";
1903 reg = <0x07b40000 0x1 1438 reg = <0x07b40000 0x1000>;
1904 status = "disabled"; 1439 status = "disabled";
1905 1440
1906 clocks = <&rpmcc RPM_ 1441 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1907 clock-names = "apb_pc 1442 clock-names = "apb_pclk", "atclk";
1908 1443
1909 cpu = <&CPU3>; 1444 cpu = <&CPU3>;
1910 1445
1911 out-ports { 1446 out-ports {
1912 port { 1447 port {
1913 etm3_ 1448 etm3_out: endpoint {
1914 1449 remote-endpoint =
1915 1450 <&apss_funnel_in3>;
1916 }; 1451 };
1917 }; 1452 };
1918 }; 1453 };
1919 }; 1454 };
1920 1455
1921 funnel4: funnel@7b60000 { /* 1456 funnel4: funnel@7b60000 { /* APSS Funnel */
1922 compatible = "arm,cor 1457 compatible = "arm,coresight-etm4x", "arm,primecell";
1923 reg = <0x07b60000 0x1 1458 reg = <0x07b60000 0x1000>;
1924 status = "disabled"; 1459 status = "disabled";
1925 1460
1926 clocks = <&rpmcc RPM_ 1461 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1927 clock-names = "apb_pc 1462 clock-names = "apb_pclk", "atclk";
1928 1463
1929 out-ports { 1464 out-ports {
1930 port { 1465 port {
1931 apss_ 1466 apss_funnel_out: endpoint {
1932 1467 remote-endpoint =
1933 1468 <&apss_merge_funnel_in>;
1934 }; 1469 };
1935 }; 1470 };
1936 }; 1471 };
1937 1472
1938 in-ports { 1473 in-ports {
1939 #address-cell 1474 #address-cells = <1>;
1940 #size-cells = 1475 #size-cells = <0>;
1941 1476
1942 port@0 { 1477 port@0 {
1943 reg = 1478 reg = <0>;
1944 apss_ 1479 apss_funnel_in0: endpoint {
1945 1480 remote-endpoint =
1946 1481 <&etm0_out>;
1947 }; 1482 };
1948 }; 1483 };
1949 1484
1950 port@1 { 1485 port@1 {
1951 reg = 1486 reg = <1>;
1952 apss_ 1487 apss_funnel_in1: endpoint {
1953 1488 remote-endpoint =
1954 1489 <&etm1_out>;
1955 }; 1490 };
1956 }; 1491 };
1957 1492
1958 port@2 { 1493 port@2 {
1959 reg = 1494 reg = <2>;
1960 apss_ 1495 apss_funnel_in2: endpoint {
1961 1496 remote-endpoint =
1962 1497 <&etm2_out>;
1963 }; 1498 };
1964 }; 1499 };
1965 1500
1966 port@3 { 1501 port@3 {
1967 reg = 1502 reg = <3>;
1968 apss_ 1503 apss_funnel_in3: endpoint {
1969 1504 remote-endpoint =
1970 1505 <&etm3_out>;
1971 }; 1506 };
1972 }; 1507 };
1973 1508
1974 port@4 { 1509 port@4 {
1975 reg = 1510 reg = <4>;
1976 apss_ 1511 apss_funnel_in4: endpoint {
1977 1512 remote-endpoint =
1978 1513 <&etm4_out>;
1979 }; 1514 };
1980 }; 1515 };
1981 1516
1982 port@5 { 1517 port@5 {
1983 reg = 1518 reg = <5>;
1984 apss_ 1519 apss_funnel_in5: endpoint {
1985 1520 remote-endpoint =
1986 1521 <&etm5_out>;
1987 }; 1522 };
1988 }; 1523 };
1989 1524
1990 port@6 { 1525 port@6 {
1991 reg = 1526 reg = <6>;
1992 apss_ 1527 apss_funnel_in6: endpoint {
1993 1528 remote-endpoint =
1994 1529 <&etm6_out>;
1995 }; 1530 };
1996 }; 1531 };
1997 1532
1998 port@7 { 1533 port@7 {
1999 reg = 1534 reg = <7>;
2000 apss_ 1535 apss_funnel_in7: endpoint {
2001 1536 remote-endpoint =
2002 1537 <&etm7_out>;
2003 }; 1538 };
2004 }; 1539 };
2005 }; 1540 };
2006 }; 1541 };
2007 1542
2008 funnel5: funnel@7b70000 { 1543 funnel5: funnel@7b70000 {
2009 compatible = "arm,cor 1544 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2010 reg = <0x07b70000 0x1 1545 reg = <0x07b70000 0x1000>;
2011 status = "disabled"; 1546 status = "disabled";
2012 1547
2013 clocks = <&rpmcc RPM_ 1548 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2014 clock-names = "apb_pc 1549 clock-names = "apb_pclk", "atclk";
2015 1550
2016 out-ports { 1551 out-ports {
2017 port { 1552 port {
2018 apss_ 1553 apss_merge_funnel_out: endpoint {
2019 1554 remote-endpoint =
2020 1555 <&funnel1_in6>;
2021 }; 1556 };
2022 }; 1557 };
2023 }; 1558 };
2024 1559
2025 in-ports { 1560 in-ports {
2026 port { 1561 port {
2027 apss_ 1562 apss_merge_funnel_in: endpoint {
2028 1563 remote-endpoint =
2029 1564 <&apss_funnel_out>;
2030 }; 1565 };
2031 }; 1566 };
2032 }; 1567 };
2033 }; 1568 };
2034 1569
2035 etm5: etm@7c40000 { 1570 etm5: etm@7c40000 {
2036 compatible = "arm,cor 1571 compatible = "arm,coresight-etm4x", "arm,primecell";
2037 reg = <0x07c40000 0x1 1572 reg = <0x07c40000 0x1000>;
2038 status = "disabled"; 1573 status = "disabled";
2039 1574
2040 clocks = <&rpmcc RPM_ 1575 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2041 clock-names = "apb_pc 1576 clock-names = "apb_pclk", "atclk";
2042 1577
2043 cpu = <&CPU4>; 1578 cpu = <&CPU4>;
2044 1579
2045 out-ports { 1580 out-ports {
2046 port { !! 1581 port{
2047 etm4_ 1582 etm4_out: endpoint {
2048 1583 remote-endpoint = <&apss_funnel_in4>;
2049 }; 1584 };
2050 }; 1585 };
2051 }; 1586 };
2052 }; 1587 };
2053 1588
2054 etm6: etm@7d40000 { 1589 etm6: etm@7d40000 {
2055 compatible = "arm,cor 1590 compatible = "arm,coresight-etm4x", "arm,primecell";
2056 reg = <0x07d40000 0x1 1591 reg = <0x07d40000 0x1000>;
2057 status = "disabled"; 1592 status = "disabled";
2058 1593
2059 clocks = <&rpmcc RPM_ 1594 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2060 clock-names = "apb_pc 1595 clock-names = "apb_pclk", "atclk";
2061 1596
2062 cpu = <&CPU5>; 1597 cpu = <&CPU5>;
2063 1598
2064 out-ports { 1599 out-ports {
2065 port { !! 1600 port{
2066 etm5_ 1601 etm5_out: endpoint {
2067 1602 remote-endpoint = <&apss_funnel_in5>;
2068 }; 1603 };
2069 }; 1604 };
2070 }; 1605 };
2071 }; 1606 };
2072 1607
2073 etm7: etm@7e40000 { 1608 etm7: etm@7e40000 {
2074 compatible = "arm,cor 1609 compatible = "arm,coresight-etm4x", "arm,primecell";
2075 reg = <0x07e40000 0x1 1610 reg = <0x07e40000 0x1000>;
2076 status = "disabled"; 1611 status = "disabled";
2077 1612
2078 clocks = <&rpmcc RPM_ 1613 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2079 clock-names = "apb_pc 1614 clock-names = "apb_pclk", "atclk";
2080 1615
2081 cpu = <&CPU6>; 1616 cpu = <&CPU6>;
2082 1617
2083 out-ports { 1618 out-ports {
2084 port { !! 1619 port{
2085 etm6_ 1620 etm6_out: endpoint {
2086 1621 remote-endpoint = <&apss_funnel_in6>;
2087 }; 1622 };
2088 }; 1623 };
2089 }; 1624 };
2090 }; 1625 };
2091 1626
2092 etm8: etm@7f40000 { 1627 etm8: etm@7f40000 {
2093 compatible = "arm,cor 1628 compatible = "arm,coresight-etm4x", "arm,primecell";
2094 reg = <0x07f40000 0x1 1629 reg = <0x07f40000 0x1000>;
2095 status = "disabled"; 1630 status = "disabled";
2096 1631
2097 clocks = <&rpmcc RPM_ 1632 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2098 clock-names = "apb_pc 1633 clock-names = "apb_pclk", "atclk";
2099 1634
2100 cpu = <&CPU7>; 1635 cpu = <&CPU7>;
2101 1636
2102 out-ports { 1637 out-ports {
2103 port { !! 1638 port{
2104 etm7_ 1639 etm7_out: endpoint {
2105 1640 remote-endpoint = <&apss_funnel_in7>;
2106 }; 1641 };
2107 }; 1642 };
2108 }; 1643 };
2109 }; 1644 };
2110 1645
2111 sram@290000 { <<
2112 compatible = "qcom,rp <<
2113 reg = <0x00290000 0x1 <<
2114 }; <<
2115 <<
2116 spmi_bus: spmi@800f000 { 1646 spmi_bus: spmi@800f000 {
2117 compatible = "qcom,sp 1647 compatible = "qcom,spmi-pmic-arb";
2118 reg = <0x0800f000 0x1 !! 1648 reg = <0x0800f000 0x1000>,
2119 <0x08400000 0x1 !! 1649 <0x08400000 0x1000000>,
2120 <0x09400000 0x1 !! 1650 <0x09400000 0x1000000>,
2121 <0x0a400000 0x2 !! 1651 <0x0a400000 0x220000>,
2122 <0x0800a000 0x3 !! 1652 <0x0800a000 0x3000>;
2123 reg-names = "core", " 1653 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
2124 interrupt-names = "pe 1654 interrupt-names = "periph_irq";
2125 interrupts = <GIC_SPI 1655 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
2126 qcom,ee = <0>; 1656 qcom,ee = <0>;
2127 qcom,channel = <0>; 1657 qcom,channel = <0>;
2128 #address-cells = <2>; 1658 #address-cells = <2>;
2129 #size-cells = <0>; 1659 #size-cells = <0>;
2130 interrupt-controller; 1660 interrupt-controller;
2131 #interrupt-cells = <4 1661 #interrupt-cells = <4>;
>> 1662 cell-index = <0>;
2132 }; 1663 };
2133 1664
2134 usb3: usb@a8f8800 { 1665 usb3: usb@a8f8800 {
2135 compatible = "qcom,ms 1666 compatible = "qcom,msm8998-dwc3", "qcom,dwc3";
2136 reg = <0x0a8f8800 0x4 1667 reg = <0x0a8f8800 0x400>;
2137 status = "disabled"; 1668 status = "disabled";
2138 #address-cells = <1>; 1669 #address-cells = <1>;
2139 #size-cells = <1>; 1670 #size-cells = <1>;
2140 ranges; 1671 ranges;
2141 1672
2142 clocks = <&gcc GCC_CF 1673 clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>,
2143 <&gcc GCC_US 1674 <&gcc GCC_USB30_MASTER_CLK>,
2144 <&gcc GCC_AG 1675 <&gcc GCC_AGGRE1_USB3_AXI_CLK>,
2145 <&gcc GCC_US !! 1676 <&gcc GCC_USB30_MOCK_UTMI_CLK>,
2146 <&gcc GCC_US !! 1677 <&gcc GCC_USB30_SLEEP_CLK>;
2147 clock-names = "cfg_no !! 1678 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
2148 "core", !! 1679 "sleep";
2149 "iface" <<
2150 "sleep" <<
2151 "mock_u <<
2152 1680
2153 assigned-clocks = <&g 1681 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
2154 <&g 1682 <&gcc GCC_USB30_MASTER_CLK>;
2155 assigned-clock-rates 1683 assigned-clock-rates = <19200000>, <120000000>;
2156 1684
2157 interrupts = <GIC_SPI !! 1685 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
2158 <GIC_SPI <<
2159 <GIC_SPI 1686 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
2160 interrupt-names = "pw !! 1687 interrupt-names = "hs_phy_irq", "ss_phy_irq";
2161 "qu <<
2162 "ss <<
2163 1688
2164 power-domains = <&gcc 1689 power-domains = <&gcc USB_30_GDSC>;
2165 1690
2166 resets = <&gcc GCC_US 1691 resets = <&gcc GCC_USB_30_BCR>;
2167 1692
2168 usb3_dwc3: usb@a80000 !! 1693 usb3_dwc3: dwc3@a800000 {
2169 compatible = 1694 compatible = "snps,dwc3";
2170 reg = <0x0a80 1695 reg = <0x0a800000 0xcd00>;
2171 interrupts = 1696 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
2172 snps,dis_u2_s 1697 snps,dis_u2_susphy_quirk;
2173 snps,dis_enbl 1698 snps,dis_enblslpm_quirk;
2174 snps,parkmode !! 1699 phys = <&qusb2phy>, <&usb1_ssphy>;
2175 phys = <&qusb <<
2176 phy-names = " 1700 phy-names = "usb2-phy", "usb3-phy";
2177 snps,has-lpm- 1701 snps,has-lpm-erratum;
2178 snps,hird-thr 1702 snps,hird-threshold = /bits/ 8 <0x10>;
2179 }; 1703 };
2180 }; 1704 };
2181 1705
2182 usb3phy: phy@c010000 { 1706 usb3phy: phy@c010000 {
2183 compatible = "qcom,ms 1707 compatible = "qcom,msm8998-qmp-usb3-phy";
2184 reg = <0x0c010000 0x1 !! 1708 reg = <0x0c010000 0x18c>;
>> 1709 status = "disabled";
>> 1710 #clock-cells = <1>;
>> 1711 #address-cells = <1>;
>> 1712 #size-cells = <1>;
>> 1713 ranges;
2185 1714
2186 clocks = <&gcc GCC_US 1715 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
2187 <&gcc GCC_US <<
2188 <&gcc GCC_US 1716 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2189 <&gcc GCC_US !! 1717 <&gcc GCC_USB3_CLKREF_CLK>;
2190 clock-names = "aux", !! 1718 clock-names = "aux", "cfg_ahb", "ref";
2191 "ref", <<
2192 "cfg_ah <<
2193 "pipe"; <<
2194 clock-output-names = <<
2195 #clock-cells = <0>; <<
2196 #phy-cells = <0>; <<
2197 1719
2198 resets = <&gcc GCC_US 1720 resets = <&gcc GCC_USB3_PHY_BCR>,
2199 <&gcc GCC_US 1721 <&gcc GCC_USB3PHY_PHY_BCR>;
2200 reset-names = "phy", !! 1722 reset-names = "phy", "common";
2201 "phy_ph <<
2202 <<
2203 qcom,tcsr-reg = <&tcs <<
2204 1723
2205 status = "disabled"; !! 1724 usb1_ssphy: lane@c010200 {
>> 1725 reg = <0xc010200 0x128>,
>> 1726 <0xc010400 0x200>,
>> 1727 <0xc010c00 0x20c>,
>> 1728 <0xc010600 0x128>,
>> 1729 <0xc010800 0x200>;
>> 1730 #phy-cells = <0>;
>> 1731 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
>> 1732 clock-names = "pipe0";
>> 1733 clock-output-names = "usb3_phy_pipe_clk_src";
>> 1734 };
2206 }; 1735 };
2207 1736
2208 qusb2phy: phy@c012000 { 1737 qusb2phy: phy@c012000 {
2209 compatible = "qcom,ms 1738 compatible = "qcom,msm8998-qusb2-phy";
2210 reg = <0x0c012000 0x2 1739 reg = <0x0c012000 0x2a8>;
2211 status = "disabled"; 1740 status = "disabled";
2212 #phy-cells = <0>; 1741 #phy-cells = <0>;
2213 1742
2214 clocks = <&gcc GCC_US 1743 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2215 <&gcc GCC_RX 1744 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
2216 clock-names = "cfg_ah 1745 clock-names = "cfg_ahb", "ref";
2217 1746
2218 resets = <&gcc GCC_QU 1747 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2219 1748
2220 nvmem-cells = <&qusb2 1749 nvmem-cells = <&qusb2_hstx_trim>;
2221 }; 1750 };
2222 1751
2223 sdhc2: mmc@c0a4900 { !! 1752 sdhc2: sdhci@c0a4900 {
2224 compatible = "qcom,ms !! 1753 compatible = "qcom,sdhci-msm-v4";
2225 reg = <0x0c0a4900 0x3 1754 reg = <0x0c0a4900 0x314>, <0x0c0a4000 0x800>;
2226 reg-names = "hc", "co !! 1755 reg-names = "hc_mem", "core_mem";
2227 1756
2228 interrupts = <GIC_SPI 1757 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
2229 <GIC_SPI 1758 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
2230 interrupt-names = "hc 1759 interrupt-names = "hc_irq", "pwr_irq";
2231 1760
2232 clock-names = "iface" 1761 clock-names = "iface", "core", "xo";
2233 clocks = <&gcc GCC_SD 1762 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2234 <&gcc GCC_SD 1763 <&gcc GCC_SDCC2_APPS_CLK>,
2235 <&rpmcc RPM_ !! 1764 <&xo>;
2236 bus-width = <4>; 1765 bus-width = <4>;
2237 status = "disabled"; 1766 status = "disabled";
2238 }; 1767 };
2239 1768
2240 blsp1_dma: dma-controller@c14 !! 1769 blsp1_dma: dma@c144000 {
2241 compatible = "qcom,ba 1770 compatible = "qcom,bam-v1.7.0";
2242 reg = <0x0c144000 0x2 1771 reg = <0x0c144000 0x25000>;
2243 interrupts = <GIC_SPI 1772 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
2244 clocks = <&gcc GCC_BL 1773 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
2245 clock-names = "bam_cl 1774 clock-names = "bam_clk";
2246 #dma-cells = <1>; 1775 #dma-cells = <1>;
2247 qcom,ee = <0>; 1776 qcom,ee = <0>;
2248 qcom,controlled-remot 1777 qcom,controlled-remotely;
2249 num-channels = <18>; 1778 num-channels = <18>;
2250 qcom,num-ees = <4>; 1779 qcom,num-ees = <4>;
2251 }; 1780 };
2252 1781
2253 blsp1_uart3: serial@c171000 { 1782 blsp1_uart3: serial@c171000 {
2254 compatible = "qcom,ms 1783 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2255 reg = <0x0c171000 0x1 1784 reg = <0x0c171000 0x1000>;
2256 interrupts = <GIC_SPI 1785 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
2257 clocks = <&gcc GCC_BL 1786 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
2258 <&gcc GCC_BL 1787 <&gcc GCC_BLSP1_AHB_CLK>;
2259 clock-names = "core", 1788 clock-names = "core", "iface";
2260 dmas = <&blsp1_dma 4> 1789 dmas = <&blsp1_dma 4>, <&blsp1_dma 5>;
2261 dma-names = "tx", "rx 1790 dma-names = "tx", "rx";
2262 pinctrl-names = "defa 1791 pinctrl-names = "default";
2263 pinctrl-0 = <&blsp1_u 1792 pinctrl-0 = <&blsp1_uart3_on>;
2264 status = "disabled"; 1793 status = "disabled";
2265 }; 1794 };
2266 1795
2267 blsp1_i2c1: i2c@c175000 { 1796 blsp1_i2c1: i2c@c175000 {
2268 compatible = "qcom,i2 1797 compatible = "qcom,i2c-qup-v2.2.1";
2269 reg = <0x0c175000 0x6 1798 reg = <0x0c175000 0x600>;
2270 interrupts = <GIC_SPI 1799 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
2271 1800
2272 clocks = <&gcc GCC_BL 1801 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
2273 <&gcc GCC_BL 1802 <&gcc GCC_BLSP1_AHB_CLK>;
2274 clock-names = "core", 1803 clock-names = "core", "iface";
2275 dmas = <&blsp1_dma 6> <<
2276 dma-names = "tx", "rx <<
2277 pinctrl-names = "defa <<
2278 pinctrl-0 = <&blsp1_i <<
2279 pinctrl-1 = <&blsp1_i <<
2280 clock-frequency = <40 1804 clock-frequency = <400000>;
2281 1805
2282 status = "disabled"; 1806 status = "disabled";
2283 #address-cells = <1>; 1807 #address-cells = <1>;
2284 #size-cells = <0>; 1808 #size-cells = <0>;
2285 }; 1809 };
2286 1810
2287 blsp1_i2c2: i2c@c176000 { 1811 blsp1_i2c2: i2c@c176000 {
2288 compatible = "qcom,i2 1812 compatible = "qcom,i2c-qup-v2.2.1";
2289 reg = <0x0c176000 0x6 1813 reg = <0x0c176000 0x600>;
2290 interrupts = <GIC_SPI 1814 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
2291 1815
2292 clocks = <&gcc GCC_BL 1816 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
2293 <&gcc GCC_BL 1817 <&gcc GCC_BLSP1_AHB_CLK>;
2294 clock-names = "core", 1818 clock-names = "core", "iface";
2295 dmas = <&blsp1_dma 8> <<
2296 dma-names = "tx", "rx <<
2297 pinctrl-names = "defa <<
2298 pinctrl-0 = <&blsp1_i <<
2299 pinctrl-1 = <&blsp1_i <<
2300 clock-frequency = <40 1819 clock-frequency = <400000>;
2301 1820
2302 status = "disabled"; 1821 status = "disabled";
2303 #address-cells = <1>; 1822 #address-cells = <1>;
2304 #size-cells = <0>; 1823 #size-cells = <0>;
2305 }; 1824 };
2306 1825
2307 blsp1_i2c3: i2c@c177000 { 1826 blsp1_i2c3: i2c@c177000 {
2308 compatible = "qcom,i2 1827 compatible = "qcom,i2c-qup-v2.2.1";
2309 reg = <0x0c177000 0x6 1828 reg = <0x0c177000 0x600>;
2310 interrupts = <GIC_SPI 1829 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
2311 1830
2312 clocks = <&gcc GCC_BL 1831 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
2313 <&gcc GCC_BL 1832 <&gcc GCC_BLSP1_AHB_CLK>;
2314 clock-names = "core", 1833 clock-names = "core", "iface";
2315 dmas = <&blsp1_dma 10 <<
2316 dma-names = "tx", "rx <<
2317 pinctrl-names = "defa <<
2318 pinctrl-0 = <&blsp1_i <<
2319 pinctrl-1 = <&blsp1_i <<
2320 clock-frequency = <40 1834 clock-frequency = <400000>;
2321 1835
2322 status = "disabled"; 1836 status = "disabled";
2323 #address-cells = <1>; 1837 #address-cells = <1>;
2324 #size-cells = <0>; 1838 #size-cells = <0>;
2325 }; 1839 };
2326 1840
2327 blsp1_i2c4: i2c@c178000 { 1841 blsp1_i2c4: i2c@c178000 {
2328 compatible = "qcom,i2 1842 compatible = "qcom,i2c-qup-v2.2.1";
2329 reg = <0x0c178000 0x6 1843 reg = <0x0c178000 0x600>;
2330 interrupts = <GIC_SPI 1844 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
2331 1845
2332 clocks = <&gcc GCC_BL 1846 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
2333 <&gcc GCC_BL 1847 <&gcc GCC_BLSP1_AHB_CLK>;
2334 clock-names = "core", 1848 clock-names = "core", "iface";
2335 dmas = <&blsp1_dma 12 <<
2336 dma-names = "tx", "rx <<
2337 pinctrl-names = "defa <<
2338 pinctrl-0 = <&blsp1_i <<
2339 pinctrl-1 = <&blsp1_i <<
2340 clock-frequency = <40 1849 clock-frequency = <400000>;
2341 1850
2342 status = "disabled"; 1851 status = "disabled";
2343 #address-cells = <1>; 1852 #address-cells = <1>;
2344 #size-cells = <0>; 1853 #size-cells = <0>;
2345 }; 1854 };
2346 1855
2347 blsp1_i2c5: i2c@c179000 { 1856 blsp1_i2c5: i2c@c179000 {
2348 compatible = "qcom,i2 1857 compatible = "qcom,i2c-qup-v2.2.1";
2349 reg = <0x0c179000 0x6 1858 reg = <0x0c179000 0x600>;
2350 interrupts = <GIC_SPI 1859 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
2351 1860
2352 clocks = <&gcc GCC_BL 1861 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
2353 <&gcc GCC_BL 1862 <&gcc GCC_BLSP1_AHB_CLK>;
2354 clock-names = "core", 1863 clock-names = "core", "iface";
2355 dmas = <&blsp1_dma 14 <<
2356 dma-names = "tx", "rx <<
2357 pinctrl-names = "defa <<
2358 pinctrl-0 = <&blsp1_i <<
2359 pinctrl-1 = <&blsp1_i <<
2360 clock-frequency = <40 1864 clock-frequency = <400000>;
2361 1865
2362 status = "disabled"; 1866 status = "disabled";
2363 #address-cells = <1>; 1867 #address-cells = <1>;
2364 #size-cells = <0>; 1868 #size-cells = <0>;
2365 }; 1869 };
2366 1870
2367 blsp1_i2c6: i2c@c17a000 { 1871 blsp1_i2c6: i2c@c17a000 {
2368 compatible = "qcom,i2 1872 compatible = "qcom,i2c-qup-v2.2.1";
2369 reg = <0x0c17a000 0x6 1873 reg = <0x0c17a000 0x600>;
2370 interrupts = <GIC_SPI 1874 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
2371 1875
2372 clocks = <&gcc GCC_BL 1876 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
2373 <&gcc GCC_BL 1877 <&gcc GCC_BLSP1_AHB_CLK>;
2374 clock-names = "core", 1878 clock-names = "core", "iface";
2375 dmas = <&blsp1_dma 16 <<
2376 dma-names = "tx", "rx <<
2377 pinctrl-names = "defa <<
2378 pinctrl-0 = <&blsp1_i <<
2379 pinctrl-1 = <&blsp1_i <<
2380 clock-frequency = <40 1879 clock-frequency = <400000>;
2381 1880
2382 status = "disabled"; 1881 status = "disabled";
2383 #address-cells = <1>; 1882 #address-cells = <1>;
2384 #size-cells = <0>; 1883 #size-cells = <0>;
2385 }; 1884 };
2386 1885
2387 blsp1_spi1: spi@c175000 { <<
2388 compatible = "qcom,sp <<
2389 reg = <0x0c175000 0x6 <<
2390 interrupts = <GIC_SPI <<
2391 <<
2392 clocks = <&gcc GCC_BL <<
2393 <&gcc GCC_BL <<
2394 clock-names = "core", <<
2395 dmas = <&blsp1_dma 6> <<
2396 dma-names = "tx", "rx <<
2397 pinctrl-names = "defa <<
2398 pinctrl-0 = <&blsp1_s <<
2399 <<
2400 status = "disabled"; <<
2401 #address-cells = <1>; <<
2402 #size-cells = <0>; <<
2403 }; <<
2404 <<
2405 blsp1_spi2: spi@c176000 { <<
2406 compatible = "qcom,sp <<
2407 reg = <0x0c176000 0x6 <<
2408 interrupts = <GIC_SPI <<
2409 <<
2410 clocks = <&gcc GCC_BL <<
2411 <&gcc GCC_BL <<
2412 clock-names = "core", <<
2413 dmas = <&blsp1_dma 8> <<
2414 dma-names = "tx", "rx <<
2415 pinctrl-names = "defa <<
2416 pinctrl-0 = <&blsp1_s <<
2417 <<
2418 status = "disabled"; <<
2419 #address-cells = <1>; <<
2420 #size-cells = <0>; <<
2421 }; <<
2422 <<
2423 blsp1_spi3: spi@c177000 { <<
2424 compatible = "qcom,sp <<
2425 reg = <0x0c177000 0x6 <<
2426 interrupts = <GIC_SPI <<
2427 <<
2428 clocks = <&gcc GCC_BL <<
2429 <&gcc GCC_BL <<
2430 clock-names = "core", <<
2431 dmas = <&blsp1_dma 10 <<
2432 dma-names = "tx", "rx <<
2433 pinctrl-names = "defa <<
2434 pinctrl-0 = <&blsp1_s <<
2435 <<
2436 status = "disabled"; <<
2437 #address-cells = <1>; <<
2438 #size-cells = <0>; <<
2439 }; <<
2440 <<
2441 blsp1_spi4: spi@c178000 { <<
2442 compatible = "qcom,sp <<
2443 reg = <0x0c178000 0x6 <<
2444 interrupts = <GIC_SPI <<
2445 <<
2446 clocks = <&gcc GCC_BL <<
2447 <&gcc GCC_BL <<
2448 clock-names = "core", <<
2449 dmas = <&blsp1_dma 12 <<
2450 dma-names = "tx", "rx <<
2451 pinctrl-names = "defa <<
2452 pinctrl-0 = <&blsp1_s <<
2453 <<
2454 status = "disabled"; <<
2455 #address-cells = <1>; <<
2456 #size-cells = <0>; <<
2457 }; <<
2458 <<
2459 blsp1_spi5: spi@c179000 { <<
2460 compatible = "qcom,sp <<
2461 reg = <0x0c179000 0x6 <<
2462 interrupts = <GIC_SPI <<
2463 <<
2464 clocks = <&gcc GCC_BL <<
2465 <&gcc GCC_BL <<
2466 clock-names = "core", <<
2467 dmas = <&blsp1_dma 14 <<
2468 dma-names = "tx", "rx <<
2469 pinctrl-names = "defa <<
2470 pinctrl-0 = <&blsp1_s <<
2471 <<
2472 status = "disabled"; <<
2473 #address-cells = <1>; <<
2474 #size-cells = <0>; <<
2475 }; <<
2476 <<
2477 blsp1_spi6: spi@c17a000 { <<
2478 compatible = "qcom,sp <<
2479 reg = <0x0c17a000 0x6 <<
2480 interrupts = <GIC_SPI <<
2481 <<
2482 clocks = <&gcc GCC_BL <<
2483 <&gcc GCC_BL <<
2484 clock-names = "core", <<
2485 dmas = <&blsp1_dma 16 <<
2486 dma-names = "tx", "rx <<
2487 pinctrl-names = "defa <<
2488 pinctrl-0 = <&blsp1_s <<
2489 <<
2490 status = "disabled"; <<
2491 #address-cells = <1>; <<
2492 #size-cells = <0>; <<
2493 }; <<
2494 <<
2495 blsp2_dma: dma-controller@c18 <<
2496 compatible = "qcom,ba <<
2497 reg = <0x0c184000 0x2 <<
2498 interrupts = <GIC_SPI <<
2499 clocks = <&gcc GCC_BL <<
2500 clock-names = "bam_cl <<
2501 #dma-cells = <1>; <<
2502 qcom,ee = <0>; <<
2503 qcom,controlled-remot <<
2504 num-channels = <18>; <<
2505 qcom,num-ees = <4>; <<
2506 }; <<
2507 <<
2508 blsp2_uart1: serial@c1b0000 { 1886 blsp2_uart1: serial@c1b0000 {
2509 compatible = "qcom,ms 1887 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2510 reg = <0x0c1b0000 0x1 1888 reg = <0x0c1b0000 0x1000>;
2511 interrupts = <GIC_SPI 1889 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
2512 clocks = <&gcc GCC_BL 1890 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
2513 <&gcc GCC_BL 1891 <&gcc GCC_BLSP2_AHB_CLK>;
2514 clock-names = "core", 1892 clock-names = "core", "iface";
2515 status = "disabled"; 1893 status = "disabled";
2516 }; 1894 };
2517 1895
2518 blsp2_i2c1: i2c@c1b5000 { !! 1896 blsp2_i2c0: i2c@c1b5000 {
2519 compatible = "qcom,i2 1897 compatible = "qcom,i2c-qup-v2.2.1";
2520 reg = <0x0c1b5000 0x6 1898 reg = <0x0c1b5000 0x600>;
2521 interrupts = <GIC_SPI 1899 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
2522 1900
2523 clocks = <&gcc GCC_BL 1901 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
2524 <&gcc GCC_BL 1902 <&gcc GCC_BLSP2_AHB_CLK>;
2525 clock-names = "core", 1903 clock-names = "core", "iface";
2526 dmas = <&blsp2_dma 6> <<
2527 dma-names = "tx", "rx <<
2528 pinctrl-names = "defa <<
2529 pinctrl-0 = <&blsp2_i <<
2530 pinctrl-1 = <&blsp2_i <<
2531 clock-frequency = <40 1904 clock-frequency = <400000>;
2532 1905
2533 status = "disabled"; 1906 status = "disabled";
2534 #address-cells = <1>; 1907 #address-cells = <1>;
2535 #size-cells = <0>; 1908 #size-cells = <0>;
2536 }; 1909 };
2537 1910
2538 blsp2_i2c2: i2c@c1b6000 { !! 1911 blsp2_i2c1: i2c@c1b6000 {
2539 compatible = "qcom,i2 1912 compatible = "qcom,i2c-qup-v2.2.1";
2540 reg = <0x0c1b6000 0x6 1913 reg = <0x0c1b6000 0x600>;
2541 interrupts = <GIC_SPI 1914 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
2542 1915
2543 clocks = <&gcc GCC_BL 1916 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
2544 <&gcc GCC_BL 1917 <&gcc GCC_BLSP2_AHB_CLK>;
2545 clock-names = "core", 1918 clock-names = "core", "iface";
2546 dmas = <&blsp2_dma 8> <<
2547 dma-names = "tx", "rx <<
2548 pinctrl-names = "defa <<
2549 pinctrl-0 = <&blsp2_i <<
2550 pinctrl-1 = <&blsp2_i <<
2551 clock-frequency = <40 1919 clock-frequency = <400000>;
2552 1920
2553 status = "disabled"; 1921 status = "disabled";
2554 #address-cells = <1>; 1922 #address-cells = <1>;
2555 #size-cells = <0>; 1923 #size-cells = <0>;
2556 }; 1924 };
2557 1925
2558 blsp2_i2c3: i2c@c1b7000 { !! 1926 blsp2_i2c2: i2c@c1b7000 {
2559 compatible = "qcom,i2 1927 compatible = "qcom,i2c-qup-v2.2.1";
2560 reg = <0x0c1b7000 0x6 1928 reg = <0x0c1b7000 0x600>;
2561 interrupts = <GIC_SPI 1929 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
2562 1930
2563 clocks = <&gcc GCC_BL 1931 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
2564 <&gcc GCC_BL 1932 <&gcc GCC_BLSP2_AHB_CLK>;
2565 clock-names = "core", 1933 clock-names = "core", "iface";
2566 dmas = <&blsp2_dma 10 <<
2567 dma-names = "tx", "rx <<
2568 pinctrl-names = "defa <<
2569 pinctrl-0 = <&blsp2_i <<
2570 pinctrl-1 = <&blsp2_i <<
2571 clock-frequency = <40 1934 clock-frequency = <400000>;
2572 1935
2573 status = "disabled"; 1936 status = "disabled";
2574 #address-cells = <1>; 1937 #address-cells = <1>;
2575 #size-cells = <0>; 1938 #size-cells = <0>;
2576 }; 1939 };
2577 1940
2578 blsp2_i2c4: i2c@c1b8000 { !! 1941 blsp2_i2c3: i2c@c1b8000 {
2579 compatible = "qcom,i2 1942 compatible = "qcom,i2c-qup-v2.2.1";
2580 reg = <0x0c1b8000 0x6 1943 reg = <0x0c1b8000 0x600>;
2581 interrupts = <GIC_SPI 1944 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
2582 1945
2583 clocks = <&gcc GCC_BL 1946 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>,
2584 <&gcc GCC_BL 1947 <&gcc GCC_BLSP2_AHB_CLK>;
2585 clock-names = "core", 1948 clock-names = "core", "iface";
2586 dmas = <&blsp2_dma 12 <<
2587 dma-names = "tx", "rx <<
2588 pinctrl-names = "defa <<
2589 pinctrl-0 = <&blsp2_i <<
2590 pinctrl-1 = <&blsp2_i <<
2591 clock-frequency = <40 1949 clock-frequency = <400000>;
2592 1950
2593 status = "disabled"; 1951 status = "disabled";
2594 #address-cells = <1>; 1952 #address-cells = <1>;
2595 #size-cells = <0>; 1953 #size-cells = <0>;
2596 }; 1954 };
2597 1955
2598 blsp2_i2c5: i2c@c1b9000 { !! 1956 blsp2_i2c4: i2c@c1b9000 {
2599 compatible = "qcom,i2 1957 compatible = "qcom,i2c-qup-v2.2.1";
2600 reg = <0x0c1b9000 0x6 1958 reg = <0x0c1b9000 0x600>;
2601 interrupts = <GIC_SPI 1959 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
2602 1960
2603 clocks = <&gcc GCC_BL 1961 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,
2604 <&gcc GCC_BL 1962 <&gcc GCC_BLSP2_AHB_CLK>;
2605 clock-names = "core", 1963 clock-names = "core", "iface";
2606 dmas = <&blsp2_dma 14 <<
2607 dma-names = "tx", "rx <<
2608 pinctrl-names = "defa <<
2609 pinctrl-0 = <&blsp2_i <<
2610 pinctrl-1 = <&blsp2_i <<
2611 clock-frequency = <40 1964 clock-frequency = <400000>;
2612 1965
2613 status = "disabled"; 1966 status = "disabled";
2614 #address-cells = <1>; 1967 #address-cells = <1>;
2615 #size-cells = <0>; 1968 #size-cells = <0>;
2616 }; 1969 };
2617 1970
2618 blsp2_i2c6: i2c@c1ba000 { !! 1971 blsp2_i2c5: i2c@c1ba000 {
2619 compatible = "qcom,i2 1972 compatible = "qcom,i2c-qup-v2.2.1";
2620 reg = <0x0c1ba000 0x6 1973 reg = <0x0c1ba000 0x600>;
2621 interrupts = <GIC_SPI 1974 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
2622 1975
2623 clocks = <&gcc GCC_BL 1976 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>,
2624 <&gcc GCC_BL 1977 <&gcc GCC_BLSP2_AHB_CLK>;
2625 clock-names = "core", 1978 clock-names = "core", "iface";
2626 dmas = <&blsp2_dma 16 <<
2627 dma-names = "tx", "rx <<
2628 pinctrl-names = "defa <<
2629 pinctrl-0 = <&blsp2_i <<
2630 pinctrl-1 = <&blsp2_i <<
2631 clock-frequency = <40 1979 clock-frequency = <400000>;
2632 1980
2633 status = "disabled"; 1981 status = "disabled";
2634 #address-cells = <1>; 1982 #address-cells = <1>;
2635 #size-cells = <0>; 1983 #size-cells = <0>;
2636 }; 1984 };
2637 1985
2638 blsp2_spi1: spi@c1b5000 { <<
2639 compatible = "qcom,sp <<
2640 reg = <0x0c1b5000 0x6 <<
2641 interrupts = <GIC_SPI <<
2642 <<
2643 clocks = <&gcc GCC_BL <<
2644 <&gcc GCC_BL <<
2645 clock-names = "core", <<
2646 dmas = <&blsp2_dma 6> <<
2647 dma-names = "tx", "rx <<
2648 pinctrl-names = "defa <<
2649 pinctrl-0 = <&blsp2_s <<
2650 <<
2651 status = "disabled"; <<
2652 #address-cells = <1>; <<
2653 #size-cells = <0>; <<
2654 }; <<
2655 <<
2656 blsp2_spi2: spi@c1b6000 { <<
2657 compatible = "qcom,sp <<
2658 reg = <0x0c1b6000 0x6 <<
2659 interrupts = <GIC_SPI <<
2660 <<
2661 clocks = <&gcc GCC_BL <<
2662 <&gcc GCC_BL <<
2663 clock-names = "core", <<
2664 dmas = <&blsp2_dma 8> <<
2665 dma-names = "tx", "rx <<
2666 pinctrl-names = "defa <<
2667 pinctrl-0 = <&blsp2_s <<
2668 <<
2669 status = "disabled"; <<
2670 #address-cells = <1>; <<
2671 #size-cells = <0>; <<
2672 }; <<
2673 <<
2674 blsp2_spi3: spi@c1b7000 { <<
2675 compatible = "qcom,sp <<
2676 reg = <0x0c1b7000 0x6 <<
2677 interrupts = <GIC_SPI <<
2678 <<
2679 clocks = <&gcc GCC_BL <<
2680 <&gcc GCC_BL <<
2681 clock-names = "core", <<
2682 dmas = <&blsp2_dma 10 <<
2683 dma-names = "tx", "rx <<
2684 pinctrl-names = "defa <<
2685 pinctrl-0 = <&blsp2_s <<
2686 <<
2687 status = "disabled"; <<
2688 #address-cells = <1>; <<
2689 #size-cells = <0>; <<
2690 }; <<
2691 <<
2692 blsp2_spi4: spi@c1b8000 { <<
2693 compatible = "qcom,sp <<
2694 reg = <0x0c1b8000 0x6 <<
2695 interrupts = <GIC_SPI <<
2696 <<
2697 clocks = <&gcc GCC_BL <<
2698 <&gcc GCC_BL <<
2699 clock-names = "core", <<
2700 dmas = <&blsp2_dma 12 <<
2701 dma-names = "tx", "rx <<
2702 pinctrl-names = "defa <<
2703 pinctrl-0 = <&blsp2_s <<
2704 <<
2705 status = "disabled"; <<
2706 #address-cells = <1>; <<
2707 #size-cells = <0>; <<
2708 }; <<
2709 <<
2710 blsp2_spi5: spi@c1b9000 { <<
2711 compatible = "qcom,sp <<
2712 reg = <0x0c1b9000 0x6 <<
2713 interrupts = <GIC_SPI <<
2714 <<
2715 clocks = <&gcc GCC_BL <<
2716 <&gcc GCC_BL <<
2717 clock-names = "core", <<
2718 dmas = <&blsp2_dma 14 <<
2719 dma-names = "tx", "rx <<
2720 pinctrl-names = "defa <<
2721 pinctrl-0 = <&blsp2_s <<
2722 <<
2723 status = "disabled"; <<
2724 #address-cells = <1>; <<
2725 #size-cells = <0>; <<
2726 }; <<
2727 <<
2728 blsp2_spi6: spi@c1ba000 { <<
2729 compatible = "qcom,sp <<
2730 reg = <0x0c1ba000 0x6 <<
2731 interrupts = <GIC_SPI <<
2732 <<
2733 clocks = <&gcc GCC_BL <<
2734 <&gcc GCC_BL <<
2735 clock-names = "core", <<
2736 dmas = <&blsp2_dma 16 <<
2737 dma-names = "tx", "rx <<
2738 pinctrl-names = "defa <<
2739 pinctrl-0 = <&blsp2_s <<
2740 <<
2741 status = "disabled"; <<
2742 #address-cells = <1>; <<
2743 #size-cells = <0>; <<
2744 }; <<
2745 <<
2746 mmcc: clock-controller@c8c000 <<
2747 compatible = "qcom,mm <<
2748 #clock-cells = <1>; <<
2749 #reset-cells = <1>; <<
2750 #power-domain-cells = <<
2751 reg = <0xc8c0000 0x40 <<
2752 <<
2753 clock-names = "xo", <<
2754 "gpll0" <<
2755 "dsi0ds <<
2756 "dsi0by <<
2757 "dsi1ds <<
2758 "dsi1by <<
2759 "hdmipl <<
2760 "dplink <<
2761 "dpvco" <<
2762 "gpll0_ <<
2763 clocks = <&rpmcc RPM_ <<
2764 <&gcc GCC_MM <<
2765 <&mdss_dsi0_ <<
2766 <&mdss_dsi0_ <<
2767 <&mdss_dsi1_ <<
2768 <&mdss_dsi1_ <<
2769 <0>, <<
2770 <0>, <<
2771 <0>, <<
2772 <&gcc GCC_MM <<
2773 }; <<
2774 <<
2775 mdss: display-subsystem@c9000 <<
2776 compatible = "qcom,ms <<
2777 reg = <0x0c900000 0x1 <<
2778 reg-names = "mdss"; <<
2779 <<
2780 interrupts = <GIC_SPI <<
2781 interrupt-controller; <<
2782 #interrupt-cells = <1 <<
2783 <<
2784 clocks = <&mmcc MDSS_ <<
2785 <&mmcc MDSS_ <<
2786 <&mmcc MDSS_ <<
2787 clock-names = "iface" <<
2788 "bus", <<
2789 "core"; <<
2790 <<
2791 power-domains = <&mmc <<
2792 iommus = <&mmss_smmu <<
2793 <<
2794 #address-cells = <1>; <<
2795 #size-cells = <1>; <<
2796 ranges; <<
2797 <<
2798 status = "disabled"; <<
2799 <<
2800 mdss_mdp: display-con <<
2801 compatible = <<
2802 reg = <0x0c90 <<
2803 <0x0c9a <<
2804 <0x0c9b <<
2805 <0x0c9b <<
2806 reg-names = " <<
2807 " <<
2808 " <<
2809 " <<
2810 <<
2811 interrupt-par <<
2812 interrupts = <<
2813 <<
2814 clocks = <&mm <<
2815 <&mm <<
2816 <&mm <<
2817 <&mm <<
2818 <&mm <<
2819 clock-names = <<
2820 <<
2821 <<
2822 <<
2823 <<
2824 <<
2825 assigned-cloc <<
2826 assigned-cloc <<
2827 <<
2828 operating-poi <<
2829 power-domains <<
2830 <<
2831 mdp_opp_table <<
2832 compa <<
2833 <<
2834 opp-1 <<
2835 <<
2836 <<
2837 }; <<
2838 <<
2839 opp-2 <<
2840 <<
2841 <<
2842 }; <<
2843 <<
2844 opp-3 <<
2845 <<
2846 <<
2847 }; <<
2848 <<
2849 opp-4 <<
2850 <<
2851 <<
2852 }; <<
2853 }; <<
2854 <<
2855 ports { <<
2856 #addr <<
2857 #size <<
2858 <<
2859 port@ <<
2860 <<
2861 <<
2862 <<
2863 <<
2864 <<
2865 }; <<
2866 <<
2867 port@ <<
2868 <<
2869 <<
2870 <<
2871 <<
2872 <<
2873 }; <<
2874 }; <<
2875 }; <<
2876 <<
2877 mdss_dsi0: dsi@c99400 <<
2878 compatible = <<
2879 reg = <0x0c99 <<
2880 reg-names = " <<
2881 <<
2882 interrupt-par <<
2883 interrupts = <<
2884 <<
2885 clocks = <&mm <<
2886 <&mm <<
2887 <&mm <<
2888 <&mm <<
2889 <&mm <<
2890 <&mm <<
2891 clock-names = <<
2892 <<
2893 <<
2894 <<
2895 <<
2896 <<
2897 assigned-cloc <<
2898 <<
2899 assigned-cloc <<
2900 <<
2901 <<
2902 operating-poi <<
2903 power-domains <<
2904 <<
2905 phys = <&mdss <<
2906 phy-names = " <<
2907 <<
2908 #address-cell <<
2909 #size-cells = <<
2910 <<
2911 status = "dis <<
2912 <<
2913 ports { <<
2914 #addr <<
2915 #size <<
2916 <<
2917 port@ <<
2918 <<
2919 <<
2920 <<
2921 <<
2922 <<
2923 }; <<
2924 <<
2925 port@ <<
2926 <<
2927 <<
2928 <<
2929 <<
2930 }; <<
2931 }; <<
2932 }; <<
2933 <<
2934 mdss_dsi0_phy: phy@c9 <<
2935 compatible = <<
2936 reg = <0x0c99 <<
2937 <0x0c99 <<
2938 <0x0c99 <<
2939 reg-names = " <<
2940 " <<
2941 " <<
2942 <<
2943 clocks = <&mm <<
2944 <&rp <<
2945 clock-names = <<
2946 <<
2947 #clock-cells <<
2948 #phy-cells = <<
2949 <<
2950 status = "dis <<
2951 }; <<
2952 <<
2953 mdss_dsi1: dsi@c99600 <<
2954 compatible = <<
2955 reg = <0x0c99 <<
2956 reg-names = " <<
2957 <<
2958 interrupt-par <<
2959 interrupts = <<
2960 <<
2961 clocks = <&mm <<
2962 <&mm <<
2963 <&mm <<
2964 <&mm <<
2965 <&mm <<
2966 <&mm <<
2967 clock-names = <<
2968 <<
2969 <<
2970 <<
2971 <<
2972 <<
2973 assigned-cloc <<
2974 <<
2975 assigned-cloc <<
2976 <<
2977 <<
2978 operating-poi <<
2979 power-domains <<
2980 <<
2981 phys = <&mdss <<
2982 phy-names = " <<
2983 <<
2984 #address-cell <<
2985 #size-cells = <<
2986 <<
2987 status = "dis <<
2988 <<
2989 ports { <<
2990 #addr <<
2991 #size <<
2992 <<
2993 port@ <<
2994 <<
2995 <<
2996 <<
2997 <<
2998 <<
2999 }; <<
3000 <<
3001 port@ <<
3002 <<
3003 <<
3004 <<
3005 <<
3006 }; <<
3007 }; <<
3008 }; <<
3009 <<
3010 mdss_dsi1_phy: phy@c9 <<
3011 compatible = <<
3012 reg = <0x0c99 <<
3013 <0x0c99 <<
3014 <0x0c99 <<
3015 reg-names = " <<
3016 " <<
3017 " <<
3018 <<
3019 clocks = <&mm <<
3020 <&rp <<
3021 clock-names = <<
3022 <<
3023 <<
3024 #clock-cells <<
3025 #phy-cells = <<
3026 <<
3027 status = "dis <<
3028 }; <<
3029 }; <<
3030 <<
3031 venus: video-codec@cc00000 { <<
3032 compatible = "qcom,ms <<
3033 reg = <0x0cc00000 0xf <<
3034 interrupts = <GIC_SPI <<
3035 power-domains = <&mmc <<
3036 clocks = <&mmcc VIDEO <<
3037 <&mmcc VIDEO <<
3038 <&mmcc VIDEO <<
3039 <&mmcc VIDEO <<
3040 clock-names = "core", <<
3041 iommus = <&mmss_smmu <<
3042 <&mmss_smmu <<
3043 <&mmss_smmu <<
3044 <&mmss_smmu <<
3045 <&mmss_smmu <<
3046 <&mmss_smmu <<
3047 <&mmss_smmu <<
3048 <&mmss_smmu <<
3049 <&mmss_smmu <<
3050 <&mmss_smmu <<
3051 <&mmss_smmu <<
3052 <&mmss_smmu <<
3053 <&mmss_smmu <<
3054 <&mmss_smmu <<
3055 <&mmss_smmu <<
3056 <&mmss_smmu <<
3057 <&mmss_smmu <<
3058 <&mmss_smmu <<
3059 <&mmss_smmu <<
3060 <&mmss_smmu <<
3061 memory-region = <&ven <<
3062 status = "disabled"; <<
3063 <<
3064 video-decoder { <<
3065 compatible = <<
3066 clocks = <&mm <<
3067 clock-names = <<
3068 power-domains <<
3069 }; <<
3070 <<
3071 video-encoder { <<
3072 compatible = <<
3073 clocks = <&mm <<
3074 clock-names = <<
3075 power-domains <<
3076 }; <<
3077 }; <<
3078 <<
3079 mmss_smmu: iommu@cd00000 { <<
3080 compatible = "qcom,ms <<
3081 reg = <0x0cd00000 0x4 <<
3082 #iommu-cells = <1>; <<
3083 <<
3084 clocks = <&mmcc MNOC_ <<
3085 <&mmcc BIMC_ <<
3086 <&mmcc BIMC_ <<
3087 clock-names = "iface- <<
3088 "iface- <<
3089 "bus-sm <<
3090 <<
3091 #global-interrupts = <<
3092 interrupts = <<
3093 <GIC_SPI 263 <<
3094 <GIC_SPI 266 <<
3095 <GIC_SPI 267 <<
3096 <GIC_SPI 268 <<
3097 <GIC_SPI 244 <<
3098 <GIC_SPI 245 <<
3099 <GIC_SPI 247 <<
3100 <GIC_SPI 248 <<
3101 <GIC_SPI 249 <<
3102 <GIC_SPI 250 <<
3103 <GIC_SPI 251 <<
3104 <GIC_SPI 252 <<
3105 <GIC_SPI 253 <<
3106 <GIC_SPI 254 <<
3107 <GIC_SPI 255 <<
3108 <GIC_SPI 256 <<
3109 <GIC_SPI 260 <<
3110 <GIC_SPI 261 <<
3111 <GIC_SPI 262 <<
3112 <GIC_SPI 272 <<
3113 <<
3114 power-domains = <&mmc <<
3115 }; <<
3116 <<
3117 remoteproc_adsp: remoteproc@1 1986 remoteproc_adsp: remoteproc@17300000 {
3118 compatible = "qcom,ms 1987 compatible = "qcom,msm8998-adsp-pas";
3119 reg = <0x17300000 0x4 1988 reg = <0x17300000 0x4040>;
3120 1989
3121 interrupts-extended = 1990 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
3122 1991 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3123 1992 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3124 1993 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3125 1994 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
3126 interrupt-names = "wd 1995 interrupt-names = "wdog", "fatal", "ready",
3127 "ha 1996 "handover", "stop-ack";
3128 1997
3129 clocks = <&rpmcc RPM_ 1998 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
3130 clock-names = "xo"; 1999 clock-names = "xo";
3131 2000
3132 memory-region = <&ads 2001 memory-region = <&adsp_mem>;
3133 2002
3134 qcom,smem-states = <& 2003 qcom,smem-states = <&adsp_smp2p_out 0>;
3135 qcom,smem-state-names 2004 qcom,smem-state-names = "stop";
3136 2005
3137 power-domains = <&rpm 2006 power-domains = <&rpmpd MSM8998_VDDCX>;
3138 power-domain-names = 2007 power-domain-names = "cx";
3139 2008
3140 status = "disabled"; 2009 status = "disabled";
3141 2010
3142 glink-edge { 2011 glink-edge {
3143 interrupts = 2012 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
3144 label = "lpas 2013 label = "lpass";
3145 qcom,remote-p 2014 qcom,remote-pid = <2>;
3146 mboxes = <&ap 2015 mboxes = <&apcs_glb 9>;
3147 }; 2016 };
3148 }; 2017 };
3149 2018
3150 apcs_glb: mailbox@17911000 { 2019 apcs_glb: mailbox@17911000 {
3151 compatible = "qcom,ms !! 2020 compatible = "qcom,msm8998-apcs-hmss-global";
3152 "qcom,ms <<
3153 reg = <0x17911000 0x1 2021 reg = <0x17911000 0x1000>;
3154 2022
3155 #mbox-cells = <1>; 2023 #mbox-cells = <1>;
3156 }; 2024 };
3157 2025
3158 timer@17920000 { 2026 timer@17920000 {
3159 #address-cells = <1>; 2027 #address-cells = <1>;
3160 #size-cells = <1>; 2028 #size-cells = <1>;
3161 ranges; 2029 ranges;
3162 compatible = "arm,arm 2030 compatible = "arm,armv7-timer-mem";
3163 reg = <0x17920000 0x1 2031 reg = <0x17920000 0x1000>;
3164 2032
3165 frame@17921000 { 2033 frame@17921000 {
3166 frame-number 2034 frame-number = <0>;
3167 interrupts = 2035 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
3168 2036 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
3169 reg = <0x1792 2037 reg = <0x17921000 0x1000>,
3170 <0x1792 2038 <0x17922000 0x1000>;
3171 }; 2039 };
3172 2040
3173 frame@17923000 { 2041 frame@17923000 {
3174 frame-number 2042 frame-number = <1>;
3175 interrupts = 2043 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
3176 reg = <0x1792 2044 reg = <0x17923000 0x1000>;
3177 status = "dis 2045 status = "disabled";
3178 }; 2046 };
3179 2047
3180 frame@17924000 { 2048 frame@17924000 {
3181 frame-number 2049 frame-number = <2>;
3182 interrupts = 2050 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
3183 reg = <0x1792 2051 reg = <0x17924000 0x1000>;
3184 status = "dis 2052 status = "disabled";
3185 }; 2053 };
3186 2054
3187 frame@17925000 { 2055 frame@17925000 {
3188 frame-number 2056 frame-number = <3>;
3189 interrupts = 2057 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3190 reg = <0x1792 2058 reg = <0x17925000 0x1000>;
3191 status = "dis 2059 status = "disabled";
3192 }; 2060 };
3193 2061
3194 frame@17926000 { 2062 frame@17926000 {
3195 frame-number 2063 frame-number = <4>;
3196 interrupts = 2064 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3197 reg = <0x1792 2065 reg = <0x17926000 0x1000>;
3198 status = "dis 2066 status = "disabled";
3199 }; 2067 };
3200 2068
3201 frame@17927000 { 2069 frame@17927000 {
3202 frame-number 2070 frame-number = <5>;
3203 interrupts = 2071 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3204 reg = <0x1792 2072 reg = <0x17927000 0x1000>;
3205 status = "dis 2073 status = "disabled";
3206 }; 2074 };
3207 2075
3208 frame@17928000 { 2076 frame@17928000 {
3209 frame-number 2077 frame-number = <6>;
3210 interrupts = 2078 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
3211 reg = <0x1792 2079 reg = <0x17928000 0x1000>;
3212 status = "dis 2080 status = "disabled";
3213 }; 2081 };
3214 }; 2082 };
3215 2083
3216 intc: interrupt-controller@17 2084 intc: interrupt-controller@17a00000 {
3217 compatible = "arm,gic 2085 compatible = "arm,gic-v3";
3218 reg = <0x17a00000 0x1 2086 reg = <0x17a00000 0x10000>, /* GICD */
3219 <0x17b00000 0x1 2087 <0x17b00000 0x100000>; /* GICR * 8 */
3220 #interrupt-cells = <3 2088 #interrupt-cells = <3>;
3221 #address-cells = <1>; 2089 #address-cells = <1>;
3222 #size-cells = <1>; 2090 #size-cells = <1>;
3223 ranges; 2091 ranges;
3224 interrupt-controller; 2092 interrupt-controller;
3225 #redistributor-region 2093 #redistributor-regions = <1>;
3226 redistributor-stride 2094 redistributor-stride = <0x0 0x20000>;
3227 interrupts = <GIC_PPI 2095 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3228 }; 2096 };
3229 2097
3230 wifi: wifi@18800000 { 2098 wifi: wifi@18800000 {
3231 compatible = "qcom,wc 2099 compatible = "qcom,wcn3990-wifi";
3232 status = "disabled"; 2100 status = "disabled";
3233 reg = <0x18800000 0x8 2101 reg = <0x18800000 0x800000>;
3234 reg-names = "membase" 2102 reg-names = "membase";
3235 memory-region = <&wla 2103 memory-region = <&wlan_msa_mem>;
3236 clocks = <&rpmcc RPM_ 2104 clocks = <&rpmcc RPM_SMD_RF_CLK2_PIN>;
3237 clock-names = "cxo_re 2105 clock-names = "cxo_ref_clk_pin";
3238 interrupts = 2106 interrupts =
3239 <GIC_SPI 413 2107 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
3240 <GIC_SPI 414 2108 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
3241 <GIC_SPI 415 2109 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
3242 <GIC_SPI 416 2110 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
3243 <GIC_SPI 417 2111 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
3244 <GIC_SPI 418 2112 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
3245 <GIC_SPI 420 2113 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
3246 <GIC_SPI 421 2114 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
3247 <GIC_SPI 422 2115 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
3248 <GIC_SPI 423 2116 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
3249 <GIC_SPI 424 2117 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
3250 <GIC_SPI 425 2118 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
3251 iommus = <&anoc2_smmu 2119 iommus = <&anoc2_smmu 0x1900>,
3252 <&anoc2_smmu 2120 <&anoc2_smmu 0x1901>;
3253 qcom,snoc-host-cap-8b 2121 qcom,snoc-host-cap-8bit-quirk;
3254 qcom,no-msa-ready-ind <<
3255 }; 2122 };
3256 }; 2123 };
3257 }; 2124 };
>> 2125
>> 2126 #include "msm8998-pins.dtsi"
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