1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2016, The Linux Foundation. A 2 /* Copyright (c) 2016, The Linux Foundation. All rights reserved. */
3 3
4 #include <dt-bindings/interrupt-controller/arm 4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-msm8998.h 5 #include <dt-bindings/clock/qcom,gcc-msm8998.h>
6 #include <dt-bindings/clock/qcom,gpucc-msm8998 6 #include <dt-bindings/clock/qcom,gpucc-msm8998.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8998. <<
8 #include <dt-bindings/clock/qcom,rpmcc.h> 7 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/firmware/qcom,scm.h> <<
10 #include <dt-bindings/power/qcom-rpmpd.h> 8 #include <dt-bindings/power/qcom-rpmpd.h>
11 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/gpio/gpio.h>
12 10
13 / { 11 / {
14 interrupt-parent = <&intc>; 12 interrupt-parent = <&intc>;
15 13
16 qcom,msm-id = <292 0x0>; 14 qcom,msm-id = <292 0x0>;
17 15
18 #address-cells = <2>; 16 #address-cells = <2>;
19 #size-cells = <2>; 17 #size-cells = <2>;
20 18
21 chosen { }; 19 chosen { };
22 20
23 memory@80000000 { !! 21 memory {
24 device_type = "memory"; 22 device_type = "memory";
25 /* We expect the bootloader to 23 /* We expect the bootloader to fill in the reg */
26 reg = <0x0 0x80000000 0x0 0x0> !! 24 reg = <0 0 0 0>;
27 }; 25 };
28 26
29 reserved-memory { 27 reserved-memory {
30 #address-cells = <2>; 28 #address-cells = <2>;
31 #size-cells = <2>; 29 #size-cells = <2>;
32 ranges; 30 ranges;
33 31
34 hyp_mem: memory@85800000 { 32 hyp_mem: memory@85800000 {
35 reg = <0x0 0x85800000 33 reg = <0x0 0x85800000 0x0 0x600000>;
36 no-map; 34 no-map;
37 }; 35 };
38 36
39 xbl_mem: memory@85e00000 { 37 xbl_mem: memory@85e00000 {
40 reg = <0x0 0x85e00000 38 reg = <0x0 0x85e00000 0x0 0x100000>;
41 no-map; 39 no-map;
42 }; 40 };
43 41
44 smem_mem: smem-mem@86000000 { 42 smem_mem: smem-mem@86000000 {
45 reg = <0x0 0x86000000 43 reg = <0x0 0x86000000 0x0 0x200000>;
46 no-map; 44 no-map;
47 }; 45 };
48 46
49 tz_mem: memory@86200000 { 47 tz_mem: memory@86200000 {
50 reg = <0x0 0x86200000 48 reg = <0x0 0x86200000 0x0 0x2d00000>;
51 no-map; 49 no-map;
52 }; 50 };
53 51
54 rmtfs_mem: memory@88f00000 { 52 rmtfs_mem: memory@88f00000 {
55 compatible = "qcom,rmt 53 compatible = "qcom,rmtfs-mem";
56 reg = <0x0 0x88f00000 54 reg = <0x0 0x88f00000 0x0 0x200000>;
57 no-map; 55 no-map;
58 56
59 qcom,client-id = <1>; 57 qcom,client-id = <1>;
60 qcom,vmid = <QCOM_SCM_ !! 58 qcom,vmid = <15>;
61 }; 59 };
62 60
63 spss_mem: memory@8ab00000 { 61 spss_mem: memory@8ab00000 {
64 reg = <0x0 0x8ab00000 62 reg = <0x0 0x8ab00000 0x0 0x700000>;
65 no-map; 63 no-map;
66 }; 64 };
67 65
68 adsp_mem: memory@8b200000 { 66 adsp_mem: memory@8b200000 {
69 reg = <0x0 0x8b200000 67 reg = <0x0 0x8b200000 0x0 0x1a00000>;
70 no-map; 68 no-map;
71 }; 69 };
72 70
73 mpss_mem: memory@8cc00000 { 71 mpss_mem: memory@8cc00000 {
74 reg = <0x0 0x8cc00000 72 reg = <0x0 0x8cc00000 0x0 0x7000000>;
75 no-map; 73 no-map;
76 }; 74 };
77 75
78 venus_mem: memory@93c00000 { 76 venus_mem: memory@93c00000 {
79 reg = <0x0 0x93c00000 77 reg = <0x0 0x93c00000 0x0 0x500000>;
80 no-map; 78 no-map;
81 }; 79 };
82 80
83 mba_mem: memory@94100000 { 81 mba_mem: memory@94100000 {
84 reg = <0x0 0x94100000 82 reg = <0x0 0x94100000 0x0 0x200000>;
85 no-map; 83 no-map;
86 }; 84 };
87 85
88 slpi_mem: memory@94300000 { 86 slpi_mem: memory@94300000 {
89 reg = <0x0 0x94300000 87 reg = <0x0 0x94300000 0x0 0xf00000>;
90 no-map; 88 no-map;
91 }; 89 };
92 90
93 ipa_fw_mem: memory@95200000 { 91 ipa_fw_mem: memory@95200000 {
94 reg = <0x0 0x95200000 92 reg = <0x0 0x95200000 0x0 0x10000>;
95 no-map; 93 no-map;
96 }; 94 };
97 95
98 ipa_gsi_mem: memory@95210000 { 96 ipa_gsi_mem: memory@95210000 {
99 reg = <0x0 0x95210000 97 reg = <0x0 0x95210000 0x0 0x5000>;
100 no-map; 98 no-map;
101 }; 99 };
102 100
103 gpu_mem: memory@95600000 { 101 gpu_mem: memory@95600000 {
104 reg = <0x0 0x95600000 102 reg = <0x0 0x95600000 0x0 0x100000>;
105 no-map; 103 no-map;
106 }; 104 };
107 105
108 wlan_msa_mem: memory@95700000 106 wlan_msa_mem: memory@95700000 {
109 reg = <0x0 0x95700000 107 reg = <0x0 0x95700000 0x0 0x100000>;
110 no-map; 108 no-map;
111 }; 109 };
112 <<
113 mdata_mem: mpss-metadata { <<
114 alloc-ranges = <0x0 0x <<
115 size = <0x0 0x4000>; <<
116 no-map; <<
117 }; <<
118 }; 110 };
119 111
120 clocks { 112 clocks {
121 xo: xo-board { 113 xo: xo-board {
122 compatible = "fixed-cl 114 compatible = "fixed-clock";
123 #clock-cells = <0>; 115 #clock-cells = <0>;
124 clock-frequency = <192 116 clock-frequency = <19200000>;
125 clock-output-names = " 117 clock-output-names = "xo_board";
126 }; 118 };
127 119
128 sleep_clk: sleep-clk { !! 120 sleep_clk {
129 compatible = "fixed-cl 121 compatible = "fixed-clock";
130 #clock-cells = <0>; 122 #clock-cells = <0>;
131 clock-frequency = <327 123 clock-frequency = <32764>;
132 }; 124 };
133 }; 125 };
134 126
135 cpus { 127 cpus {
136 #address-cells = <2>; 128 #address-cells = <2>;
137 #size-cells = <0>; 129 #size-cells = <0>;
138 130
139 CPU0: cpu@0 { 131 CPU0: cpu@0 {
140 device_type = "cpu"; 132 device_type = "cpu";
141 compatible = "qcom,kry 133 compatible = "qcom,kryo280";
142 reg = <0x0 0x0>; 134 reg = <0x0 0x0>;
143 enable-method = "psci" 135 enable-method = "psci";
144 capacity-dmips-mhz = < 136 capacity-dmips-mhz = <1024>;
145 cpu-idle-states = <&LI 137 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
146 next-level-cache = <&L 138 next-level-cache = <&L2_0>;
147 L2_0: l2-cache { 139 L2_0: l2-cache {
148 compatible = " !! 140 compatible = "arm,arch-cache";
149 cache-level = 141 cache-level = <2>;
150 cache-unified; !! 142 };
>> 143 L1_I_0: l1-icache {
>> 144 compatible = "arm,arch-cache";
>> 145 };
>> 146 L1_D_0: l1-dcache {
>> 147 compatible = "arm,arch-cache";
151 }; 148 };
152 }; 149 };
153 150
154 CPU1: cpu@1 { 151 CPU1: cpu@1 {
155 device_type = "cpu"; 152 device_type = "cpu";
156 compatible = "qcom,kry 153 compatible = "qcom,kryo280";
157 reg = <0x0 0x1>; 154 reg = <0x0 0x1>;
158 enable-method = "psci" 155 enable-method = "psci";
159 capacity-dmips-mhz = < 156 capacity-dmips-mhz = <1024>;
160 cpu-idle-states = <&LI 157 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
161 next-level-cache = <&L 158 next-level-cache = <&L2_0>;
>> 159 L1_I_1: l1-icache {
>> 160 compatible = "arm,arch-cache";
>> 161 };
>> 162 L1_D_1: l1-dcache {
>> 163 compatible = "arm,arch-cache";
>> 164 };
162 }; 165 };
163 166
164 CPU2: cpu@2 { 167 CPU2: cpu@2 {
165 device_type = "cpu"; 168 device_type = "cpu";
166 compatible = "qcom,kry 169 compatible = "qcom,kryo280";
167 reg = <0x0 0x2>; 170 reg = <0x0 0x2>;
168 enable-method = "psci" 171 enable-method = "psci";
169 capacity-dmips-mhz = < 172 capacity-dmips-mhz = <1024>;
170 cpu-idle-states = <&LI 173 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
171 next-level-cache = <&L 174 next-level-cache = <&L2_0>;
>> 175 L1_I_2: l1-icache {
>> 176 compatible = "arm,arch-cache";
>> 177 };
>> 178 L1_D_2: l1-dcache {
>> 179 compatible = "arm,arch-cache";
>> 180 };
172 }; 181 };
173 182
174 CPU3: cpu@3 { 183 CPU3: cpu@3 {
175 device_type = "cpu"; 184 device_type = "cpu";
176 compatible = "qcom,kry 185 compatible = "qcom,kryo280";
177 reg = <0x0 0x3>; 186 reg = <0x0 0x3>;
178 enable-method = "psci" 187 enable-method = "psci";
179 capacity-dmips-mhz = < 188 capacity-dmips-mhz = <1024>;
180 cpu-idle-states = <&LI 189 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
181 next-level-cache = <&L 190 next-level-cache = <&L2_0>;
>> 191 L1_I_3: l1-icache {
>> 192 compatible = "arm,arch-cache";
>> 193 };
>> 194 L1_D_3: l1-dcache {
>> 195 compatible = "arm,arch-cache";
>> 196 };
182 }; 197 };
183 198
184 CPU4: cpu@100 { 199 CPU4: cpu@100 {
185 device_type = "cpu"; 200 device_type = "cpu";
186 compatible = "qcom,kry 201 compatible = "qcom,kryo280";
187 reg = <0x0 0x100>; 202 reg = <0x0 0x100>;
188 enable-method = "psci" 203 enable-method = "psci";
189 capacity-dmips-mhz = < 204 capacity-dmips-mhz = <1536>;
190 cpu-idle-states = <&BI 205 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
191 next-level-cache = <&L 206 next-level-cache = <&L2_1>;
192 L2_1: l2-cache { 207 L2_1: l2-cache {
193 compatible = " !! 208 compatible = "arm,arch-cache";
194 cache-level = 209 cache-level = <2>;
195 cache-unified; !! 210 };
>> 211 L1_I_100: l1-icache {
>> 212 compatible = "arm,arch-cache";
>> 213 };
>> 214 L1_D_100: l1-dcache {
>> 215 compatible = "arm,arch-cache";
196 }; 216 };
197 }; 217 };
198 218
199 CPU5: cpu@101 { 219 CPU5: cpu@101 {
200 device_type = "cpu"; 220 device_type = "cpu";
201 compatible = "qcom,kry 221 compatible = "qcom,kryo280";
202 reg = <0x0 0x101>; 222 reg = <0x0 0x101>;
203 enable-method = "psci" 223 enable-method = "psci";
204 capacity-dmips-mhz = < 224 capacity-dmips-mhz = <1536>;
205 cpu-idle-states = <&BI 225 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
206 next-level-cache = <&L 226 next-level-cache = <&L2_1>;
>> 227 L1_I_101: l1-icache {
>> 228 compatible = "arm,arch-cache";
>> 229 };
>> 230 L1_D_101: l1-dcache {
>> 231 compatible = "arm,arch-cache";
>> 232 };
207 }; 233 };
208 234
209 CPU6: cpu@102 { 235 CPU6: cpu@102 {
210 device_type = "cpu"; 236 device_type = "cpu";
211 compatible = "qcom,kry 237 compatible = "qcom,kryo280";
212 reg = <0x0 0x102>; 238 reg = <0x0 0x102>;
213 enable-method = "psci" 239 enable-method = "psci";
214 capacity-dmips-mhz = < 240 capacity-dmips-mhz = <1536>;
215 cpu-idle-states = <&BI 241 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
216 next-level-cache = <&L 242 next-level-cache = <&L2_1>;
>> 243 L1_I_102: l1-icache {
>> 244 compatible = "arm,arch-cache";
>> 245 };
>> 246 L1_D_102: l1-dcache {
>> 247 compatible = "arm,arch-cache";
>> 248 };
217 }; 249 };
218 250
219 CPU7: cpu@103 { 251 CPU7: cpu@103 {
220 device_type = "cpu"; 252 device_type = "cpu";
221 compatible = "qcom,kry 253 compatible = "qcom,kryo280";
222 reg = <0x0 0x103>; 254 reg = <0x0 0x103>;
223 enable-method = "psci" 255 enable-method = "psci";
224 capacity-dmips-mhz = < 256 capacity-dmips-mhz = <1536>;
225 cpu-idle-states = <&BI 257 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
226 next-level-cache = <&L 258 next-level-cache = <&L2_1>;
>> 259 L1_I_103: l1-icache {
>> 260 compatible = "arm,arch-cache";
>> 261 };
>> 262 L1_D_103: l1-dcache {
>> 263 compatible = "arm,arch-cache";
>> 264 };
227 }; 265 };
228 266
229 cpu-map { 267 cpu-map {
230 cluster0 { 268 cluster0 {
231 core0 { 269 core0 {
232 cpu = 270 cpu = <&CPU0>;
233 }; 271 };
234 272
235 core1 { 273 core1 {
236 cpu = 274 cpu = <&CPU1>;
237 }; 275 };
238 276
239 core2 { 277 core2 {
240 cpu = 278 cpu = <&CPU2>;
241 }; 279 };
242 280
243 core3 { 281 core3 {
244 cpu = 282 cpu = <&CPU3>;
245 }; 283 };
246 }; 284 };
247 285
248 cluster1 { 286 cluster1 {
249 core0 { 287 core0 {
250 cpu = 288 cpu = <&CPU4>;
251 }; 289 };
252 290
253 core1 { 291 core1 {
254 cpu = 292 cpu = <&CPU5>;
255 }; 293 };
256 294
257 core2 { 295 core2 {
258 cpu = 296 cpu = <&CPU6>;
259 }; 297 };
260 298
261 core3 { 299 core3 {
262 cpu = 300 cpu = <&CPU7>;
263 }; 301 };
264 }; 302 };
265 }; 303 };
266 304
267 idle-states { 305 idle-states {
268 entry-method = "psci"; 306 entry-method = "psci";
269 307
270 LITTLE_CPU_SLEEP_0: cp 308 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
271 compatible = " 309 compatible = "arm,idle-state";
272 idle-state-nam 310 idle-state-name = "little-retention";
273 /* CPU Retenti <<
274 arm,psci-suspe 311 arm,psci-suspend-param = <0x00000002>;
275 entry-latency- 312 entry-latency-us = <81>;
276 exit-latency-u 313 exit-latency-us = <86>;
277 min-residency- !! 314 min-residency-us = <200>;
278 }; 315 };
279 316
280 LITTLE_CPU_SLEEP_1: cp 317 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
281 compatible = " 318 compatible = "arm,idle-state";
282 idle-state-nam 319 idle-state-name = "little-power-collapse";
283 /* CPU + L2 Po <<
284 arm,psci-suspe 320 arm,psci-suspend-param = <0x40000003>;
285 entry-latency- !! 321 entry-latency-us = <273>;
286 exit-latency-u !! 322 exit-latency-us = <612>;
287 min-residency- !! 323 min-residency-us = <1000>;
288 local-timer-st 324 local-timer-stop;
289 }; 325 };
290 326
291 BIG_CPU_SLEEP_0: cpu-s 327 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
292 compatible = " 328 compatible = "arm,idle-state";
293 idle-state-nam 329 idle-state-name = "big-retention";
294 /* CPU Retenti <<
295 arm,psci-suspe 330 arm,psci-suspend-param = <0x00000002>;
296 entry-latency- 331 entry-latency-us = <79>;
297 exit-latency-u 332 exit-latency-us = <82>;
298 min-residency- !! 333 min-residency-us = <200>;
299 }; 334 };
300 335
301 BIG_CPU_SLEEP_1: cpu-s 336 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
302 compatible = " 337 compatible = "arm,idle-state";
303 idle-state-nam 338 idle-state-name = "big-power-collapse";
304 /* CPU + L2 Po <<
305 arm,psci-suspe 339 arm,psci-suspend-param = <0x40000003>;
306 entry-latency- !! 340 entry-latency-us = <336>;
307 exit-latency-u !! 341 exit-latency-us = <525>;
308 min-residency- !! 342 min-residency-us = <1000>;
309 local-timer-st 343 local-timer-stop;
310 }; 344 };
311 }; 345 };
312 }; 346 };
313 347
314 firmware { 348 firmware {
315 scm { 349 scm {
316 compatible = "qcom,scm 350 compatible = "qcom,scm-msm8998", "qcom,scm";
317 }; 351 };
318 }; 352 };
319 353
320 dsi_opp_table: opp-table-dsi { !! 354 tcsr_mutex: hwlock {
321 compatible = "operating-points !! 355 compatible = "qcom,tcsr-mutex";
322 !! 356 syscon = <&tcsr_mutex_regs 0 0x1000>;
323 opp-131250000 { !! 357 #hwlock-cells = <1>;
324 opp-hz = /bits/ 64 <13 <<
325 required-opps = <&rpmp <<
326 }; <<
327 <<
328 opp-210000000 { <<
329 opp-hz = /bits/ 64 <21 <<
330 required-opps = <&rpmp <<
331 }; <<
332 <<
333 opp-312500000 { <<
334 opp-hz = /bits/ 64 <31 <<
335 required-opps = <&rpmp <<
336 }; <<
337 }; 358 };
338 359
339 psci { 360 psci {
340 compatible = "arm,psci-1.0"; 361 compatible = "arm,psci-1.0";
341 method = "smc"; 362 method = "smc";
342 }; 363 };
343 364
344 rpm: remoteproc { !! 365 rpm-glink {
345 compatible = "qcom,msm8998-rpm !! 366 compatible = "qcom,glink-rpm";
>> 367
>> 368 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
>> 369 qcom,rpm-msg-ram = <&rpm_msg_ram>;
>> 370 mboxes = <&apcs_glb 0>;
>> 371
>> 372 rpm_requests: rpm-requests {
>> 373 compatible = "qcom,rpm-msm8998";
>> 374 qcom,glink-channels = "rpm_requests";
>> 375
>> 376 rpmcc: clock-controller {
>> 377 compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc";
>> 378 #clock-cells = <1>;
>> 379 };
>> 380
>> 381 rpmpd: power-controller {
>> 382 compatible = "qcom,msm8998-rpmpd";
>> 383 #power-domain-cells = <1>;
>> 384 operating-points-v2 = <&rpmpd_opp_table>;
346 385
347 glink-edge { !! 386 rpmpd_opp_table: opp-table {
348 compatible = "qcom,gli !! 387 compatible = "operating-points-v2";
349 388
350 interrupts = <GIC_SPI !! 389 rpmpd_opp_ret: opp1 {
351 qcom,rpm-msg-ram = <&r !! 390 opp-level = <RPM_SMD_LEVEL_RETENTION>;
352 mboxes = <&apcs_glb 0> !! 391 };
353 !! 392
354 rpm_requests: rpm-requ !! 393 rpmpd_opp_ret_plus: opp2 {
355 compatible = " !! 394 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
356 qcom,glink-cha !! 395 };
357 !! 396
358 rpmcc: clock-c !! 397 rpmpd_opp_min_svs: opp3 {
359 compat !! 398 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
360 clocks !! 399 };
361 clock- !! 400
362 #clock !! 401 rpmpd_opp_low_svs: opp4 {
363 }; !! 402 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
364 !! 403 };
365 rpmpd: power-c !! 404
366 compat !! 405 rpmpd_opp_svs: opp5 {
367 #power !! 406 opp-level = <RPM_SMD_LEVEL_SVS>;
368 operat !! 407 };
369 !! 408
370 rpmpd_ !! 409 rpmpd_opp_svs_plus: opp6 {
371 !! 410 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
372 !! 411 };
373 !! 412
374 !! 413 rpmpd_opp_nom: opp7 {
375 !! 414 opp-level = <RPM_SMD_LEVEL_NOM>;
376 !! 415 };
377 !! 416
378 !! 417 rpmpd_opp_nom_plus: opp8 {
379 !! 418 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
380 !! 419 };
381 !! 420
382 !! 421 rpmpd_opp_turbo: opp9 {
383 !! 422 opp-level = <RPM_SMD_LEVEL_TURBO>;
384 !! 423 };
385 !! 424
386 !! 425 rpmpd_opp_turbo_plus: opp10 {
387 !! 426 opp-level = <RPM_SMD_LEVEL_BINNING>;
388 <<
389 <<
390 <<
391 <<
392 <<
393 <<
394 <<
395 <<
396 <<
397 <<
398 <<
399 <<
400 <<
401 <<
402 <<
403 <<
404 <<
405 <<
406 <<
407 <<
408 <<
409 <<
410 <<
411 <<
412 }; 427 };
413 }; 428 };
414 }; 429 };
415 }; 430 };
416 }; 431 };
417 432
418 smem { 433 smem {
419 compatible = "qcom,smem"; 434 compatible = "qcom,smem";
420 memory-region = <&smem_mem>; 435 memory-region = <&smem_mem>;
421 hwlocks = <&tcsr_mutex 3>; 436 hwlocks = <&tcsr_mutex 3>;
422 }; 437 };
423 438
424 smp2p-lpass { 439 smp2p-lpass {
425 compatible = "qcom,smp2p"; 440 compatible = "qcom,smp2p";
426 qcom,smem = <443>, <429>; 441 qcom,smem = <443>, <429>;
427 442
428 interrupts = <GIC_SPI 158 IRQ_ 443 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
429 444
430 mboxes = <&apcs_glb 10>; 445 mboxes = <&apcs_glb 10>;
431 446
432 qcom,local-pid = <0>; 447 qcom,local-pid = <0>;
433 qcom,remote-pid = <2>; 448 qcom,remote-pid = <2>;
434 449
435 adsp_smp2p_out: master-kernel 450 adsp_smp2p_out: master-kernel {
436 qcom,entry-name = "mas 451 qcom,entry-name = "master-kernel";
437 #qcom,smem-state-cells 452 #qcom,smem-state-cells = <1>;
438 }; 453 };
439 454
440 adsp_smp2p_in: slave-kernel { 455 adsp_smp2p_in: slave-kernel {
441 qcom,entry-name = "sla 456 qcom,entry-name = "slave-kernel";
442 457
443 interrupt-controller; 458 interrupt-controller;
444 #interrupt-cells = <2> 459 #interrupt-cells = <2>;
445 }; 460 };
446 }; 461 };
447 462
448 smp2p-mpss { 463 smp2p-mpss {
449 compatible = "qcom,smp2p"; 464 compatible = "qcom,smp2p";
450 qcom,smem = <435>, <428>; 465 qcom,smem = <435>, <428>;
451 interrupts = <GIC_SPI 451 IRQ_ 466 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
452 mboxes = <&apcs_glb 14>; 467 mboxes = <&apcs_glb 14>;
453 qcom,local-pid = <0>; 468 qcom,local-pid = <0>;
454 qcom,remote-pid = <1>; 469 qcom,remote-pid = <1>;
455 470
456 modem_smp2p_out: master-kernel 471 modem_smp2p_out: master-kernel {
457 qcom,entry-name = "mas 472 qcom,entry-name = "master-kernel";
458 #qcom,smem-state-cells 473 #qcom,smem-state-cells = <1>;
459 }; 474 };
460 475
461 modem_smp2p_in: slave-kernel { 476 modem_smp2p_in: slave-kernel {
462 qcom,entry-name = "sla 477 qcom,entry-name = "slave-kernel";
463 interrupt-controller; 478 interrupt-controller;
464 #interrupt-cells = <2> 479 #interrupt-cells = <2>;
465 }; 480 };
466 }; 481 };
467 482
468 smp2p-slpi { 483 smp2p-slpi {
469 compatible = "qcom,smp2p"; 484 compatible = "qcom,smp2p";
470 qcom,smem = <481>, <430>; 485 qcom,smem = <481>, <430>;
471 interrupts = <GIC_SPI 178 IRQ_ 486 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
472 mboxes = <&apcs_glb 26>; 487 mboxes = <&apcs_glb 26>;
473 qcom,local-pid = <0>; 488 qcom,local-pid = <0>;
474 qcom,remote-pid = <3>; 489 qcom,remote-pid = <3>;
475 490
476 slpi_smp2p_out: master-kernel 491 slpi_smp2p_out: master-kernel {
477 qcom,entry-name = "mas 492 qcom,entry-name = "master-kernel";
478 #qcom,smem-state-cells 493 #qcom,smem-state-cells = <1>;
479 }; 494 };
480 495
481 slpi_smp2p_in: slave-kernel { 496 slpi_smp2p_in: slave-kernel {
482 qcom,entry-name = "sla 497 qcom,entry-name = "slave-kernel";
483 interrupt-controller; 498 interrupt-controller;
484 #interrupt-cells = <2> 499 #interrupt-cells = <2>;
485 }; 500 };
486 }; 501 };
487 502
488 thermal-zones { 503 thermal-zones {
489 cpu0-thermal { 504 cpu0-thermal {
490 polling-delay-passive 505 polling-delay-passive = <250>;
>> 506 polling-delay = <1000>;
491 507
492 thermal-sensors = <&ts 508 thermal-sensors = <&tsens0 1>;
493 509
494 trips { 510 trips {
495 cpu0_alert0: t 511 cpu0_alert0: trip-point0 {
496 temper 512 temperature = <75000>;
497 hyster 513 hysteresis = <2000>;
498 type = 514 type = "passive";
499 }; 515 };
500 516
501 cpu0_crit: cpu !! 517 cpu0_crit: cpu_crit {
502 temper 518 temperature = <110000>;
503 hyster 519 hysteresis = <2000>;
504 type = 520 type = "critical";
505 }; 521 };
506 }; 522 };
507 }; 523 };
508 524
509 cpu1-thermal { 525 cpu1-thermal {
510 polling-delay-passive 526 polling-delay-passive = <250>;
>> 527 polling-delay = <1000>;
511 528
512 thermal-sensors = <&ts 529 thermal-sensors = <&tsens0 2>;
513 530
514 trips { 531 trips {
515 cpu1_alert0: t 532 cpu1_alert0: trip-point0 {
516 temper 533 temperature = <75000>;
517 hyster 534 hysteresis = <2000>;
518 type = 535 type = "passive";
519 }; 536 };
520 537
521 cpu1_crit: cpu !! 538 cpu1_crit: cpu_crit {
522 temper 539 temperature = <110000>;
523 hyster 540 hysteresis = <2000>;
524 type = 541 type = "critical";
525 }; 542 };
526 }; 543 };
527 }; 544 };
528 545
529 cpu2-thermal { 546 cpu2-thermal {
530 polling-delay-passive 547 polling-delay-passive = <250>;
>> 548 polling-delay = <1000>;
531 549
532 thermal-sensors = <&ts 550 thermal-sensors = <&tsens0 3>;
533 551
534 trips { 552 trips {
535 cpu2_alert0: t 553 cpu2_alert0: trip-point0 {
536 temper 554 temperature = <75000>;
537 hyster 555 hysteresis = <2000>;
538 type = 556 type = "passive";
539 }; 557 };
540 558
541 cpu2_crit: cpu !! 559 cpu2_crit: cpu_crit {
542 temper 560 temperature = <110000>;
543 hyster 561 hysteresis = <2000>;
544 type = 562 type = "critical";
545 }; 563 };
546 }; 564 };
547 }; 565 };
548 566
549 cpu3-thermal { 567 cpu3-thermal {
550 polling-delay-passive 568 polling-delay-passive = <250>;
>> 569 polling-delay = <1000>;
551 570
552 thermal-sensors = <&ts 571 thermal-sensors = <&tsens0 4>;
553 572
554 trips { 573 trips {
555 cpu3_alert0: t 574 cpu3_alert0: trip-point0 {
556 temper 575 temperature = <75000>;
557 hyster 576 hysteresis = <2000>;
558 type = 577 type = "passive";
559 }; 578 };
560 579
561 cpu3_crit: cpu !! 580 cpu3_crit: cpu_crit {
562 temper 581 temperature = <110000>;
563 hyster 582 hysteresis = <2000>;
564 type = 583 type = "critical";
565 }; 584 };
566 }; 585 };
567 }; 586 };
568 587
569 cpu4-thermal { 588 cpu4-thermal {
570 polling-delay-passive 589 polling-delay-passive = <250>;
>> 590 polling-delay = <1000>;
571 591
572 thermal-sensors = <&ts 592 thermal-sensors = <&tsens0 7>;
573 593
574 trips { 594 trips {
575 cpu4_alert0: t 595 cpu4_alert0: trip-point0 {
576 temper 596 temperature = <75000>;
577 hyster 597 hysteresis = <2000>;
578 type = 598 type = "passive";
579 }; 599 };
580 600
581 cpu4_crit: cpu !! 601 cpu4_crit: cpu_crit {
582 temper 602 temperature = <110000>;
583 hyster 603 hysteresis = <2000>;
584 type = 604 type = "critical";
585 }; 605 };
586 }; 606 };
587 }; 607 };
588 608
589 cpu5-thermal { 609 cpu5-thermal {
590 polling-delay-passive 610 polling-delay-passive = <250>;
>> 611 polling-delay = <1000>;
591 612
592 thermal-sensors = <&ts 613 thermal-sensors = <&tsens0 8>;
593 614
594 trips { 615 trips {
595 cpu5_alert0: t 616 cpu5_alert0: trip-point0 {
596 temper 617 temperature = <75000>;
597 hyster 618 hysteresis = <2000>;
598 type = 619 type = "passive";
599 }; 620 };
600 621
601 cpu5_crit: cpu !! 622 cpu5_crit: cpu_crit {
602 temper 623 temperature = <110000>;
603 hyster 624 hysteresis = <2000>;
604 type = 625 type = "critical";
605 }; 626 };
606 }; 627 };
607 }; 628 };
608 629
609 cpu6-thermal { 630 cpu6-thermal {
610 polling-delay-passive 631 polling-delay-passive = <250>;
>> 632 polling-delay = <1000>;
611 633
612 thermal-sensors = <&ts 634 thermal-sensors = <&tsens0 9>;
613 635
614 trips { 636 trips {
615 cpu6_alert0: t 637 cpu6_alert0: trip-point0 {
616 temper 638 temperature = <75000>;
617 hyster 639 hysteresis = <2000>;
618 type = 640 type = "passive";
619 }; 641 };
620 642
621 cpu6_crit: cpu !! 643 cpu6_crit: cpu_crit {
622 temper 644 temperature = <110000>;
623 hyster 645 hysteresis = <2000>;
624 type = 646 type = "critical";
625 }; 647 };
626 }; 648 };
627 }; 649 };
628 650
629 cpu7-thermal { 651 cpu7-thermal {
630 polling-delay-passive 652 polling-delay-passive = <250>;
>> 653 polling-delay = <1000>;
631 654
632 thermal-sensors = <&ts 655 thermal-sensors = <&tsens0 10>;
633 656
634 trips { 657 trips {
635 cpu7_alert0: t 658 cpu7_alert0: trip-point0 {
636 temper 659 temperature = <75000>;
637 hyster 660 hysteresis = <2000>;
638 type = 661 type = "passive";
639 }; 662 };
640 663
641 cpu7_crit: cpu !! 664 cpu7_crit: cpu_crit {
642 temper 665 temperature = <110000>;
643 hyster 666 hysteresis = <2000>;
644 type = 667 type = "critical";
645 }; 668 };
646 }; 669 };
647 }; 670 };
648 671
649 gpu-bottom-thermal { !! 672 gpu-thermal-bottom {
650 polling-delay-passive 673 polling-delay-passive = <250>;
>> 674 polling-delay = <1000>;
651 675
652 thermal-sensors = <&ts 676 thermal-sensors = <&tsens0 12>;
653 677
654 trips { 678 trips {
655 gpu1_alert0: t 679 gpu1_alert0: trip-point0 {
656 temper 680 temperature = <90000>;
657 hyster 681 hysteresis = <2000>;
658 type = 682 type = "hot";
659 }; 683 };
660 }; 684 };
661 }; 685 };
662 686
663 gpu-top-thermal { !! 687 gpu-thermal-top {
664 polling-delay-passive 688 polling-delay-passive = <250>;
>> 689 polling-delay = <1000>;
665 690
666 thermal-sensors = <&ts 691 thermal-sensors = <&tsens0 13>;
667 692
668 trips { 693 trips {
669 gpu2_alert0: t 694 gpu2_alert0: trip-point0 {
670 temper 695 temperature = <90000>;
671 hyster 696 hysteresis = <2000>;
672 type = 697 type = "hot";
673 }; 698 };
674 }; 699 };
675 }; 700 };
676 701
677 clust0-mhm-thermal { 702 clust0-mhm-thermal {
678 polling-delay-passive 703 polling-delay-passive = <250>;
>> 704 polling-delay = <1000>;
679 705
680 thermal-sensors = <&ts 706 thermal-sensors = <&tsens0 5>;
681 707
682 trips { 708 trips {
683 cluster0_mhm_a 709 cluster0_mhm_alert0: trip-point0 {
684 temper 710 temperature = <90000>;
685 hyster 711 hysteresis = <2000>;
686 type = 712 type = "hot";
687 }; 713 };
688 }; 714 };
689 }; 715 };
690 716
691 clust1-mhm-thermal { 717 clust1-mhm-thermal {
692 polling-delay-passive 718 polling-delay-passive = <250>;
>> 719 polling-delay = <1000>;
693 720
694 thermal-sensors = <&ts 721 thermal-sensors = <&tsens0 6>;
695 722
696 trips { 723 trips {
697 cluster1_mhm_a 724 cluster1_mhm_alert0: trip-point0 {
698 temper 725 temperature = <90000>;
699 hyster 726 hysteresis = <2000>;
700 type = 727 type = "hot";
701 }; 728 };
702 }; 729 };
703 }; 730 };
704 731
705 cluster1-l2-thermal { 732 cluster1-l2-thermal {
706 polling-delay-passive 733 polling-delay-passive = <250>;
>> 734 polling-delay = <1000>;
707 735
708 thermal-sensors = <&ts 736 thermal-sensors = <&tsens0 11>;
709 737
710 trips { 738 trips {
711 cluster1_l2_al 739 cluster1_l2_alert0: trip-point0 {
712 temper 740 temperature = <90000>;
713 hyster 741 hysteresis = <2000>;
714 type = 742 type = "hot";
715 }; 743 };
716 }; 744 };
717 }; 745 };
718 746
719 modem-thermal { 747 modem-thermal {
720 polling-delay-passive 748 polling-delay-passive = <250>;
>> 749 polling-delay = <1000>;
721 750
722 thermal-sensors = <&ts 751 thermal-sensors = <&tsens1 1>;
723 752
724 trips { 753 trips {
725 modem_alert0: 754 modem_alert0: trip-point0 {
726 temper 755 temperature = <90000>;
727 hyster 756 hysteresis = <2000>;
728 type = 757 type = "hot";
729 }; 758 };
730 }; 759 };
731 }; 760 };
732 761
733 mem-thermal { 762 mem-thermal {
734 polling-delay-passive 763 polling-delay-passive = <250>;
>> 764 polling-delay = <1000>;
735 765
736 thermal-sensors = <&ts 766 thermal-sensors = <&tsens1 2>;
737 767
738 trips { 768 trips {
739 mem_alert0: tr 769 mem_alert0: trip-point0 {
740 temper 770 temperature = <90000>;
741 hyster 771 hysteresis = <2000>;
742 type = 772 type = "hot";
743 }; 773 };
744 }; 774 };
745 }; 775 };
746 776
747 wlan-thermal { 777 wlan-thermal {
748 polling-delay-passive 778 polling-delay-passive = <250>;
>> 779 polling-delay = <1000>;
749 780
750 thermal-sensors = <&ts 781 thermal-sensors = <&tsens1 3>;
751 782
752 trips { 783 trips {
753 wlan_alert0: t 784 wlan_alert0: trip-point0 {
754 temper 785 temperature = <90000>;
755 hyster 786 hysteresis = <2000>;
756 type = 787 type = "hot";
757 }; 788 };
758 }; 789 };
759 }; 790 };
760 791
761 q6-dsp-thermal { 792 q6-dsp-thermal {
762 polling-delay-passive 793 polling-delay-passive = <250>;
>> 794 polling-delay = <1000>;
763 795
764 thermal-sensors = <&ts 796 thermal-sensors = <&tsens1 4>;
765 797
766 trips { 798 trips {
767 q6_dsp_alert0: 799 q6_dsp_alert0: trip-point0 {
768 temper 800 temperature = <90000>;
769 hyster 801 hysteresis = <2000>;
770 type = 802 type = "hot";
771 }; 803 };
772 }; 804 };
773 }; 805 };
774 806
775 camera-thermal { 807 camera-thermal {
776 polling-delay-passive 808 polling-delay-passive = <250>;
>> 809 polling-delay = <1000>;
777 810
778 thermal-sensors = <&ts 811 thermal-sensors = <&tsens1 5>;
779 812
780 trips { 813 trips {
781 camera_alert0: 814 camera_alert0: trip-point0 {
782 temper 815 temperature = <90000>;
783 hyster 816 hysteresis = <2000>;
784 type = 817 type = "hot";
785 }; 818 };
786 }; 819 };
787 }; 820 };
788 821
789 multimedia-thermal { 822 multimedia-thermal {
790 polling-delay-passive 823 polling-delay-passive = <250>;
>> 824 polling-delay = <1000>;
791 825
792 thermal-sensors = <&ts 826 thermal-sensors = <&tsens1 6>;
793 827
794 trips { 828 trips {
795 multimedia_ale 829 multimedia_alert0: trip-point0 {
796 temper 830 temperature = <90000>;
797 hyster 831 hysteresis = <2000>;
798 type = 832 type = "hot";
799 }; 833 };
800 }; 834 };
801 }; 835 };
802 }; 836 };
803 837
804 timer { 838 timer {
805 compatible = "arm,armv8-timer" 839 compatible = "arm,armv8-timer";
806 interrupts = <GIC_PPI 1 IRQ_TY 840 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
807 <GIC_PPI 2 IRQ_TY 841 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
808 <GIC_PPI 3 IRQ_TY 842 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
809 <GIC_PPI 0 IRQ_TY 843 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
810 }; 844 };
811 845
812 soc: soc@0 { !! 846 soc: soc {
813 #address-cells = <1>; 847 #address-cells = <1>;
814 #size-cells = <1>; 848 #size-cells = <1>;
815 ranges = <0 0 0 0xffffffff>; 849 ranges = <0 0 0 0xffffffff>;
816 compatible = "simple-bus"; 850 compatible = "simple-bus";
817 851
818 gcc: clock-controller@100000 { 852 gcc: clock-controller@100000 {
819 compatible = "qcom,gcc 853 compatible = "qcom,gcc-msm8998";
820 #clock-cells = <1>; 854 #clock-cells = <1>;
821 #reset-cells = <1>; 855 #reset-cells = <1>;
822 #power-domain-cells = 856 #power-domain-cells = <1>;
823 reg = <0x00100000 0xb0 857 reg = <0x00100000 0xb0000>;
824 <<
825 clock-names = "xo", "s <<
826 clocks = <&rpmcc RPM_S <<
827 <<
828 /* <<
829 * The hypervisor typi <<
830 * reside as read-only <<
831 * these clocks on a d <<
832 * enabled but unused <<
833 * to reboot. <<
834 * In light of that, w <<
835 * as protected. The b <<
836 * list of protected c <<
837 * desired for the HLO <<
838 */ <<
839 protected-clocks = <AG <<
840 <SS <<
841 <SS <<
842 }; 858 };
843 859
844 rpm_msg_ram: sram@778000 { !! 860 rpm_msg_ram: memory@778000 {
845 compatible = "qcom,rpm 861 compatible = "qcom,rpm-msg-ram";
846 reg = <0x00778000 0x70 862 reg = <0x00778000 0x7000>;
847 }; 863 };
848 864
849 qfprom: qfprom@784000 { !! 865 qfprom: qfprom@780000 {
850 compatible = "qcom,msm !! 866 compatible = "qcom,qfprom";
851 reg = <0x00784000 0x62 !! 867 reg = <0x00780000 0x621c>;
852 #address-cells = <1>; 868 #address-cells = <1>;
853 #size-cells = <1>; 869 #size-cells = <1>;
854 870
855 qusb2_hstx_trim: hstx- !! 871 qusb2_hstx_trim: hstx-trim@423a {
856 reg = <0x23a 0 !! 872 reg = <0x423a 0x1>;
857 bits = <0 4>; 873 bits = <0 4>;
858 }; 874 };
859 }; 875 };
860 876
861 tsens0: thermal@10ab000 { 877 tsens0: thermal@10ab000 {
862 compatible = "qcom,msm 878 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
863 reg = <0x010ab000 0x10 879 reg = <0x010ab000 0x1000>, /* TM */
864 <0x010aa000 0x10 880 <0x010aa000 0x1000>; /* SROT */
865 #qcom,sensors = <14>; 881 #qcom,sensors = <14>;
866 interrupts = <GIC_SPI 882 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
867 <GIC_SPI 883 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
868 interrupt-names = "upl 884 interrupt-names = "uplow", "critical";
869 #thermal-sensor-cells 885 #thermal-sensor-cells = <1>;
870 }; 886 };
871 887
872 tsens1: thermal@10ae000 { 888 tsens1: thermal@10ae000 {
873 compatible = "qcom,msm 889 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
874 reg = <0x010ae000 0x10 890 reg = <0x010ae000 0x1000>, /* TM */
875 <0x010ad000 0x10 891 <0x010ad000 0x1000>; /* SROT */
876 #qcom,sensors = <8>; 892 #qcom,sensors = <8>;
877 interrupts = <GIC_SPI 893 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
878 <GIC_SPI 894 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
879 interrupt-names = "upl 895 interrupt-names = "uplow", "critical";
880 #thermal-sensor-cells 896 #thermal-sensor-cells = <1>;
881 }; 897 };
882 898
883 anoc1_smmu: iommu@1680000 { 899 anoc1_smmu: iommu@1680000 {
884 compatible = "qcom,msm 900 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
885 reg = <0x01680000 0x10 901 reg = <0x01680000 0x10000>;
886 #iommu-cells = <1>; 902 #iommu-cells = <1>;
887 903
888 #global-interrupts = < 904 #global-interrupts = <0>;
889 interrupts = 905 interrupts =
890 <GIC_SPI 364 I 906 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
891 <GIC_SPI 365 I 907 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
892 <GIC_SPI 366 I 908 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
893 <GIC_SPI 367 I 909 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
894 <GIC_SPI 368 I 910 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
895 <GIC_SPI 369 I 911 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>;
896 }; 912 };
897 913
898 anoc2_smmu: iommu@16c0000 { 914 anoc2_smmu: iommu@16c0000 {
899 compatible = "qcom,msm 915 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
900 reg = <0x016c0000 0x40 916 reg = <0x016c0000 0x40000>;
901 #iommu-cells = <1>; 917 #iommu-cells = <1>;
902 918
903 #global-interrupts = < 919 #global-interrupts = <0>;
904 interrupts = 920 interrupts =
905 <GIC_SPI 373 I 921 <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>,
906 <GIC_SPI 374 I 922 <GIC_SPI 374 IRQ_TYPE_EDGE_RISING>,
907 <GIC_SPI 375 I 923 <GIC_SPI 375 IRQ_TYPE_EDGE_RISING>,
908 <GIC_SPI 376 I 924 <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>,
909 <GIC_SPI 377 I 925 <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>,
910 <GIC_SPI 378 I 926 <GIC_SPI 378 IRQ_TYPE_EDGE_RISING>,
911 <GIC_SPI 462 I 927 <GIC_SPI 462 IRQ_TYPE_EDGE_RISING>,
912 <GIC_SPI 463 I 928 <GIC_SPI 463 IRQ_TYPE_EDGE_RISING>,
913 <GIC_SPI 464 I 929 <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
914 <GIC_SPI 465 I 930 <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>;
915 }; 931 };
916 932
917 pcie0: pcie@1c00000 { !! 933 pcie0: pci@1c00000 {
918 compatible = "qcom,pci !! 934 compatible = "qcom,pcie-msm8996";
919 reg = <0x01c00000 0x20 !! 935 reg = <0x01c00000 0x2000>,
920 <0x1b000000 0xf1 !! 936 <0x1b000000 0xf1d>,
921 <0x1b000f20 0xa8 !! 937 <0x1b000f20 0xa8>,
922 <0x1b100000 0x10 !! 938 <0x1b100000 0x100000>;
923 reg-names = "parf", "d 939 reg-names = "parf", "dbi", "elbi", "config";
924 device_type = "pci"; 940 device_type = "pci";
925 linux,pci-domain = <0> 941 linux,pci-domain = <0>;
926 bus-range = <0x00 0xff 942 bus-range = <0x00 0xff>;
927 #address-cells = <3>; 943 #address-cells = <3>;
928 #size-cells = <2>; 944 #size-cells = <2>;
929 num-lanes = <1>; 945 num-lanes = <1>;
930 phys = <&pcie_phy>; !! 946 phys = <&pciephy>;
931 phy-names = "pciephy"; 947 phy-names = "pciephy";
932 status = "disabled"; 948 status = "disabled";
933 949
934 ranges = <0x01000000 0 !! 950 ranges = <0x01000000 0x0 0x1b200000 0x1b200000 0x0 0x100000>,
935 <0x02000000 0 951 <0x02000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>;
936 952
937 #interrupt-cells = <1> 953 #interrupt-cells = <1>;
938 interrupts = <GIC_SPI 954 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
939 interrupt-names = "msi 955 interrupt-names = "msi";
940 interrupt-map-mask = < 956 interrupt-map-mask = <0 0 0 0x7>;
941 interrupt-map = <0 0 0 !! 957 interrupt-map = <0 0 0 1 &intc 0 135 IRQ_TYPE_LEVEL_HIGH>,
942 <0 0 0 !! 958 <0 0 0 2 &intc 0 136 IRQ_TYPE_LEVEL_HIGH>,
943 <0 0 0 !! 959 <0 0 0 3 &intc 0 138 IRQ_TYPE_LEVEL_HIGH>,
944 <0 0 0 !! 960 <0 0 0 4 &intc 0 139 IRQ_TYPE_LEVEL_HIGH>;
945 961
946 clocks = <&gcc GCC_PCI 962 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
947 <&gcc GCC_PCI <<
948 <&gcc GCC_PCI <<
949 <&gcc GCC_PCI 963 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
950 <&gcc GCC_PCI !! 964 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
951 clock-names = "pipe", !! 965 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
>> 966 <&gcc GCC_PCIE_0_AUX_CLK>;
>> 967 clock-names = "pipe", "bus_master", "bus_slave", "cfg", "aux";
952 968
953 power-domains = <&gcc 969 power-domains = <&gcc PCIE_0_GDSC>;
954 iommu-map = <0x100 &an 970 iommu-map = <0x100 &anoc1_smmu 0x1480 1>;
955 perst-gpios = <&tlmm 3 971 perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
956 <<
957 pcie@0 { <<
958 device_type = <<
959 reg = <0x0 0x0 <<
960 bus-range = <0 <<
961 <<
962 #address-cells <<
963 #size-cells = <<
964 ranges; <<
965 }; <<
966 }; 972 };
967 973
968 pcie_phy: phy@1c06000 { 974 pcie_phy: phy@1c06000 {
969 compatible = "qcom,msm 975 compatible = "qcom,msm8998-qmp-pcie-phy";
970 reg = <0x01c06000 0x10 !! 976 reg = <0x01c06000 0x18c>;
>> 977 #address-cells = <1>;
>> 978 #size-cells = <1>;
971 status = "disabled"; 979 status = "disabled";
>> 980 ranges;
972 981
973 clocks = <&gcc GCC_PCI 982 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
974 <&gcc GCC_PCI 983 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
975 <&gcc GCC_PCI !! 984 <&gcc GCC_PCIE_CLKREF_CLK>;
976 <&gcc GCC_PCI !! 985 clock-names = "aux", "cfg_ahb", "ref";
977 clock-names = "aux", <<
978 "cfg_ahb <<
979 "ref", <<
980 "pipe"; <<
981 <<
982 clock-output-names = " <<
983 #clock-cells = <0>; <<
984 <<
985 #phy-cells = <0>; <<
986 986
987 resets = <&gcc GCC_PCI 987 resets = <&gcc GCC_PCIE_0_PHY_BCR>, <&gcc GCC_PCIE_PHY_BCR>;
988 reset-names = "phy", " 988 reset-names = "phy", "common";
989 989
990 vdda-phy-supply = <&vr 990 vdda-phy-supply = <&vreg_l1a_0p875>;
991 vdda-pll-supply = <&vr 991 vdda-pll-supply = <&vreg_l2a_1p2>;
>> 992
>> 993 pciephy: lane@1c06800 {
>> 994 reg = <0x01c06200 0x128>, <0x01c06400 0x1fc>, <0x01c06800 0x20c>;
>> 995 #phy-cells = <0>;
>> 996
>> 997 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
>> 998 clock-names = "pipe0";
>> 999 clock-output-names = "pcie_0_pipe_clk_src";
>> 1000 #clock-cells = <0>;
>> 1001 };
992 }; 1002 };
993 1003
994 ufshc: ufshc@1da4000 { 1004 ufshc: ufshc@1da4000 {
995 compatible = "qcom,msm 1005 compatible = "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
996 reg = <0x01da4000 0x25 1006 reg = <0x01da4000 0x2500>;
997 interrupts = <GIC_SPI 1007 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
998 phys = <&ufsphy>; !! 1008 phys = <&ufsphy_lanes>;
999 phy-names = "ufsphy"; 1009 phy-names = "ufsphy";
1000 lanes-per-direction = 1010 lanes-per-direction = <2>;
1001 power-domains = <&gcc 1011 power-domains = <&gcc UFS_GDSC>;
1002 status = "disabled"; 1012 status = "disabled";
1003 #reset-cells = <1>; 1013 #reset-cells = <1>;
1004 1014
1005 clock-names = 1015 clock-names =
1006 "core_clk", 1016 "core_clk",
1007 "bus_aggr_clk 1017 "bus_aggr_clk",
1008 "iface_clk", 1018 "iface_clk",
1009 "core_clk_uni 1019 "core_clk_unipro",
1010 "ref_clk", 1020 "ref_clk",
1011 "tx_lane0_syn 1021 "tx_lane0_sync_clk",
1012 "rx_lane0_syn 1022 "rx_lane0_sync_clk",
1013 "rx_lane1_syn 1023 "rx_lane1_sync_clk";
1014 clocks = 1024 clocks =
1015 <&gcc GCC_UFS 1025 <&gcc GCC_UFS_AXI_CLK>,
1016 <&gcc GCC_AGG 1026 <&gcc GCC_AGGRE1_UFS_AXI_CLK>,
1017 <&gcc GCC_UFS 1027 <&gcc GCC_UFS_AHB_CLK>,
1018 <&gcc GCC_UFS 1028 <&gcc GCC_UFS_UNIPRO_CORE_CLK>,
1019 <&rpmcc RPM_S 1029 <&rpmcc RPM_SMD_LN_BB_CLK1>,
1020 <&gcc GCC_UFS 1030 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
1021 <&gcc GCC_UFS 1031 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>,
1022 <&gcc GCC_UFS 1032 <&gcc GCC_UFS_RX_SYMBOL_1_CLK>;
1023 freq-table-hz = 1033 freq-table-hz =
1024 <50000000 200 1034 <50000000 200000000>,
1025 <0 0>, 1035 <0 0>,
1026 <0 0>, 1036 <0 0>,
1027 <37500000 150 1037 <37500000 150000000>,
1028 <0 0>, 1038 <0 0>,
1029 <0 0>, 1039 <0 0>,
1030 <0 0>, 1040 <0 0>,
1031 <0 0>; 1041 <0 0>;
1032 1042
1033 resets = <&gcc GCC_UF 1043 resets = <&gcc GCC_UFS_BCR>;
1034 reset-names = "rst"; 1044 reset-names = "rst";
1035 }; 1045 };
1036 1046
1037 ufsphy: phy@1da7000 { 1047 ufsphy: phy@1da7000 {
1038 compatible = "qcom,ms 1048 compatible = "qcom,msm8998-qmp-ufs-phy";
1039 reg = <0x01da7000 0x1 !! 1049 reg = <0x01da7000 0x18c>;
>> 1050 #address-cells = <1>;
>> 1051 #size-cells = <1>;
>> 1052 status = "disabled";
>> 1053 ranges;
1040 1054
1041 clocks = <&rpmcc RPM_ !! 1055 clock-names =
1042 <&gcc GCC_UF !! 1056 "ref",
1043 <&gcc GCC_UF !! 1057 "ref_aux";
1044 clock-names = "ref", !! 1058 clocks =
1045 "ref_au !! 1059 <&gcc GCC_UFS_CLKREF_CLK>,
1046 "qref"; !! 1060 <&gcc GCC_UFS_PHY_AUX_CLK>;
1047 1061
1048 reset-names = "ufsphy 1062 reset-names = "ufsphy";
1049 resets = <&ufshc 0>; 1063 resets = <&ufshc 0>;
1050 1064
1051 #phy-cells = <0>; !! 1065 ufsphy_lanes: lanes@1da7400 {
1052 status = "disabled"; !! 1066 reg = <0x01da7400 0x128>,
1053 }; !! 1067 <0x01da7600 0x1fc>,
1054 !! 1068 <0x01da7c00 0x1dc>,
1055 tcsr_mutex: hwlock@1f40000 { !! 1069 <0x01da7800 0x128>,
1056 compatible = "qcom,tc !! 1070 <0x01da7a00 0x1fc>;
1057 reg = <0x01f40000 0x2 !! 1071 #phy-cells = <0>;
1058 #hwlock-cells = <1>; !! 1072 };
1059 }; <<
1060 <<
1061 tcsr_regs_1: syscon@1f60000 { <<
1062 compatible = "qcom,ms <<
1063 reg = <0x01f60000 0x2 <<
1064 }; 1073 };
1065 1074
1066 tcsr_regs_2: syscon@1fc0000 { !! 1075 tcsr_mutex_regs: syscon@1f40000 {
1067 compatible = "qcom,ms !! 1076 compatible = "syscon";
1068 reg = <0x01fc0000 0x2 !! 1077 reg = <0x01f40000 0x40000>;
1069 }; 1078 };
1070 1079
1071 tlmm: pinctrl@3400000 { 1080 tlmm: pinctrl@3400000 {
1072 compatible = "qcom,ms 1081 compatible = "qcom,msm8998-pinctrl";
1073 reg = <0x03400000 0xc 1082 reg = <0x03400000 0xc00000>;
1074 interrupts = <GIC_SPI 1083 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1075 gpio-ranges = <&tlmm <<
1076 gpio-controller; 1084 gpio-controller;
1077 #gpio-cells = <2>; !! 1085 #gpio-cells = <0x2>;
1078 interrupt-controller; 1086 interrupt-controller;
1079 #interrupt-cells = <2 !! 1087 #interrupt-cells = <0x2>;
1080 1088
1081 sdc2_on: sdc2-on-stat !! 1089 sdc2_clk_on: sdc2_clk_on {
1082 clk-pins { !! 1090 config {
1083 pins 1091 pins = "sdc2_clk";
>> 1092 bias-disable;
1084 drive 1093 drive-strength = <16>;
>> 1094 };
>> 1095 };
>> 1096
>> 1097 sdc2_clk_off: sdc2_clk_off {
>> 1098 config {
>> 1099 pins = "sdc2_clk";
1085 bias- 1100 bias-disable;
>> 1101 drive-strength = <2>;
1086 }; 1102 };
>> 1103 };
1087 1104
1088 cmd-pins { !! 1105 sdc2_cmd_on: sdc2_cmd_on {
>> 1106 config {
1089 pins 1107 pins = "sdc2_cmd";
>> 1108 bias-pull-up;
1090 drive 1109 drive-strength = <10>;
>> 1110 };
>> 1111 };
>> 1112
>> 1113 sdc2_cmd_off: sdc2_cmd_off {
>> 1114 config {
>> 1115 pins = "sdc2_cmd";
1091 bias- 1116 bias-pull-up;
>> 1117 drive-strength = <2>;
1092 }; 1118 };
>> 1119 };
1093 1120
1094 data-pins { !! 1121 sdc2_data_on: sdc2_data_on {
>> 1122 config {
1095 pins 1123 pins = "sdc2_data";
1096 drive <<
1097 bias- 1124 bias-pull-up;
>> 1125 drive-strength = <10>;
1098 }; 1126 };
1099 }; 1127 };
1100 1128
1101 sdc2_off: sdc2-off-st !! 1129 sdc2_data_off: sdc2_data_off {
1102 clk-pins { !! 1130 config {
1103 pins !! 1131 pins = "sdc2_data";
>> 1132 bias-pull-up;
1104 drive 1133 drive-strength = <2>;
1105 bias- <<
1106 }; 1134 };
>> 1135 };
1107 1136
1108 cmd-pins { !! 1137 sdc2_cd_on: sdc2_cd_on {
1109 pins !! 1138 mux {
1110 drive !! 1139 pins = "gpio95";
1111 bias- !! 1140 function = "gpio";
1112 }; 1141 };
1113 1142
1114 data-pins { !! 1143 config {
1115 pins !! 1144 pins = "gpio95";
1116 drive <<
1117 bias- 1145 bias-pull-up;
>> 1146 drive-strength = <2>;
1118 }; 1147 };
1119 }; 1148 };
1120 1149
1121 sdc2_cd: sdc2-cd-stat !! 1150 sdc2_cd_off: sdc2_cd_off {
1122 pins = "gpio9 !! 1151 mux {
1123 function = "g !! 1152 pins = "gpio95";
1124 bias-pull-up; !! 1153 function = "gpio";
1125 drive-strengt !! 1154 };
>> 1155
>> 1156 config {
>> 1157 pins = "gpio95";
>> 1158 bias-pull-up;
>> 1159 drive-strength = <2>;
>> 1160 };
1126 }; 1161 };
1127 1162
1128 blsp1_uart3_on: blsp1 !! 1163 blsp1_uart3_on: blsp1_uart3_on {
1129 tx-pins { !! 1164 tx {
1130 pins 1165 pins = "gpio45";
1131 funct 1166 function = "blsp_uart3_a";
1132 drive 1167 drive-strength = <2>;
1133 bias- 1168 bias-disable;
1134 }; 1169 };
1135 1170
1136 rx-pins { !! 1171 rx {
1137 pins 1172 pins = "gpio46";
1138 funct 1173 function = "blsp_uart3_a";
1139 drive 1174 drive-strength = <2>;
1140 bias- 1175 bias-disable;
1141 }; 1176 };
1142 1177
1143 cts-pins { !! 1178 cts {
1144 pins 1179 pins = "gpio47";
1145 funct 1180 function = "blsp_uart3_a";
1146 drive 1181 drive-strength = <2>;
1147 bias- 1182 bias-disable;
1148 }; 1183 };
1149 1184
1150 rfr-pins { !! 1185 rfr {
1151 pins 1186 pins = "gpio48";
1152 funct 1187 function = "blsp_uart3_a";
1153 drive 1188 drive-strength = <2>;
1154 bias- 1189 bias-disable;
1155 }; 1190 };
1156 }; 1191 };
1157 1192
1158 blsp1_i2c1_default: b !! 1193 blsp1_i2c1_default: blsp1-i2c1-default {
1159 pins = "gpio2 1194 pins = "gpio2", "gpio3";
1160 function = "b 1195 function = "blsp_i2c1";
1161 drive-strengt 1196 drive-strength = <2>;
1162 bias-disable; 1197 bias-disable;
1163 }; 1198 };
1164 1199
1165 blsp1_i2c1_sleep: bls !! 1200 blsp1_i2c1_sleep: blsp1-i2c1-sleep {
1166 pins = "gpio2 1201 pins = "gpio2", "gpio3";
1167 function = "b 1202 function = "blsp_i2c1";
1168 drive-strengt 1203 drive-strength = <2>;
1169 bias-pull-up; 1204 bias-pull-up;
1170 }; 1205 };
1171 1206
1172 blsp1_i2c2_default: b !! 1207 blsp1_i2c2_default: blsp1-i2c2-default {
1173 pins = "gpio3 1208 pins = "gpio32", "gpio33";
1174 function = "b 1209 function = "blsp_i2c2";
1175 drive-strengt 1210 drive-strength = <2>;
1176 bias-disable; 1211 bias-disable;
1177 }; 1212 };
1178 1213
1179 blsp1_i2c2_sleep: bls !! 1214 blsp1_i2c2_sleep: blsp1-i2c2-sleep {
1180 pins = "gpio3 1215 pins = "gpio32", "gpio33";
1181 function = "b 1216 function = "blsp_i2c2";
1182 drive-strengt 1217 drive-strength = <2>;
1183 bias-pull-up; 1218 bias-pull-up;
1184 }; 1219 };
1185 1220
1186 blsp1_i2c3_default: b !! 1221 blsp1_i2c3_default: blsp1-i2c3-default {
1187 pins = "gpio4 1222 pins = "gpio47", "gpio48";
1188 function = "b 1223 function = "blsp_i2c3";
1189 drive-strengt 1224 drive-strength = <2>;
1190 bias-disable; 1225 bias-disable;
1191 }; 1226 };
1192 1227
1193 blsp1_i2c3_sleep: bls !! 1228 blsp1_i2c3_sleep: blsp1-i2c3-sleep {
1194 pins = "gpio4 1229 pins = "gpio47", "gpio48";
1195 function = "b 1230 function = "blsp_i2c3";
1196 drive-strengt 1231 drive-strength = <2>;
1197 bias-pull-up; 1232 bias-pull-up;
1198 }; 1233 };
1199 1234
1200 blsp1_i2c4_default: b !! 1235 blsp1_i2c4_default: blsp1-i2c4-default {
1201 pins = "gpio1 1236 pins = "gpio10", "gpio11";
1202 function = "b 1237 function = "blsp_i2c4";
1203 drive-strengt 1238 drive-strength = <2>;
1204 bias-disable; 1239 bias-disable;
1205 }; 1240 };
1206 1241
1207 blsp1_i2c4_sleep: bls !! 1242 blsp1_i2c4_sleep: blsp1-i2c4-sleep {
1208 pins = "gpio1 1243 pins = "gpio10", "gpio11";
1209 function = "b 1244 function = "blsp_i2c4";
1210 drive-strengt 1245 drive-strength = <2>;
1211 bias-pull-up; 1246 bias-pull-up;
1212 }; 1247 };
1213 1248
1214 blsp1_i2c5_default: b !! 1249 blsp1_i2c5_default: blsp1-i2c5-default {
1215 pins = "gpio8 1250 pins = "gpio87", "gpio88";
1216 function = "b 1251 function = "blsp_i2c5";
1217 drive-strengt 1252 drive-strength = <2>;
1218 bias-disable; 1253 bias-disable;
1219 }; 1254 };
1220 1255
1221 blsp1_i2c5_sleep: bls !! 1256 blsp1_i2c5_sleep: blsp1-i2c5-sleep {
1222 pins = "gpio8 1257 pins = "gpio87", "gpio88";
1223 function = "b 1258 function = "blsp_i2c5";
1224 drive-strengt 1259 drive-strength = <2>;
1225 bias-pull-up; 1260 bias-pull-up;
1226 }; 1261 };
1227 1262
1228 blsp1_i2c6_default: b !! 1263 blsp1_i2c6_default: blsp1-i2c6-default {
1229 pins = "gpio4 1264 pins = "gpio43", "gpio44";
1230 function = "b 1265 function = "blsp_i2c6";
1231 drive-strengt 1266 drive-strength = <2>;
1232 bias-disable; 1267 bias-disable;
1233 }; 1268 };
1234 1269
1235 blsp1_i2c6_sleep: bls !! 1270 blsp1_i2c6_sleep: blsp1-i2c6-sleep {
1236 pins = "gpio4 1271 pins = "gpio43", "gpio44";
1237 function = "b 1272 function = "blsp_i2c6";
1238 drive-strengt 1273 drive-strength = <2>;
1239 bias-pull-up; 1274 bias-pull-up;
1240 }; 1275 };
1241 <<
1242 blsp1_spi_b_default: <<
1243 pins = "gpio2 <<
1244 function = "b <<
1245 drive-strengt <<
1246 bias-disable; <<
1247 }; <<
1248 <<
1249 blsp1_spi1_default: b <<
1250 pins = "gpio0 <<
1251 function = "b <<
1252 drive-strengt <<
1253 bias-disable; <<
1254 }; <<
1255 <<
1256 blsp1_spi2_default: b <<
1257 pins = "gpio3 <<
1258 function = "b <<
1259 drive-strengt <<
1260 bias-disable; <<
1261 }; <<
1262 <<
1263 blsp1_spi3_default: b <<
1264 pins = "gpio4 <<
1265 function = "b <<
1266 drive-strengt <<
1267 bias-disable; <<
1268 }; <<
1269 <<
1270 blsp1_spi4_default: b <<
1271 pins = "gpio8 <<
1272 function = "b <<
1273 drive-strengt <<
1274 bias-disable; <<
1275 }; <<
1276 <<
1277 blsp1_spi5_default: b <<
1278 pins = "gpio8 <<
1279 function = "b <<
1280 drive-strengt <<
1281 bias-disable; <<
1282 }; <<
1283 <<
1284 blsp1_spi6_default: b <<
1285 pins = "gpio4 <<
1286 function = "b <<
1287 drive-strengt <<
1288 bias-disable; <<
1289 }; <<
1290 <<
1291 <<
1292 /* 6 interfaces per Q 1276 /* 6 interfaces per QUP, BLSP2 indexes are numbered (n)+6 */
1293 blsp2_i2c1_default: b !! 1277 blsp2_i2c1_default: blsp2-i2c1-default {
1294 pins = "gpio5 1278 pins = "gpio55", "gpio56";
1295 function = "b 1279 function = "blsp_i2c7";
1296 drive-strengt 1280 drive-strength = <2>;
1297 bias-disable; 1281 bias-disable;
1298 }; 1282 };
1299 1283
1300 blsp2_i2c1_sleep: bls !! 1284 blsp2_i2c1_sleep: blsp2-i2c1-sleep {
1301 pins = "gpio5 1285 pins = "gpio55", "gpio56";
1302 function = "b 1286 function = "blsp_i2c7";
1303 drive-strengt 1287 drive-strength = <2>;
1304 bias-pull-up; 1288 bias-pull-up;
1305 }; 1289 };
1306 1290
1307 blsp2_i2c2_default: b !! 1291 blsp2_i2c2_default: blsp2-i2c2-default {
1308 pins = "gpio6 1292 pins = "gpio6", "gpio7";
1309 function = "b 1293 function = "blsp_i2c8";
1310 drive-strengt 1294 drive-strength = <2>;
1311 bias-disable; 1295 bias-disable;
1312 }; 1296 };
1313 1297
1314 blsp2_i2c2_sleep: bls !! 1298 blsp2_i2c2_sleep: blsp2-i2c2-sleep {
1315 pins = "gpio6 1299 pins = "gpio6", "gpio7";
1316 function = "b 1300 function = "blsp_i2c8";
1317 drive-strengt 1301 drive-strength = <2>;
1318 bias-pull-up; 1302 bias-pull-up;
1319 }; 1303 };
1320 1304
1321 blsp2_i2c3_default: b !! 1305 blsp2_i2c3_default: blsp2-i2c3-default {
1322 pins = "gpio5 1306 pins = "gpio51", "gpio52";
1323 function = "b 1307 function = "blsp_i2c9";
1324 drive-strengt 1308 drive-strength = <2>;
1325 bias-disable; 1309 bias-disable;
1326 }; 1310 };
1327 1311
1328 blsp2_i2c3_sleep: bls !! 1312 blsp2_i2c3_sleep: blsp2-i2c3-sleep {
1329 pins = "gpio5 1313 pins = "gpio51", "gpio52";
1330 function = "b 1314 function = "blsp_i2c9";
1331 drive-strengt 1315 drive-strength = <2>;
1332 bias-pull-up; 1316 bias-pull-up;
1333 }; 1317 };
1334 1318
1335 blsp2_i2c4_default: b !! 1319 blsp2_i2c4_default: blsp2-i2c4-default {
1336 pins = "gpio6 1320 pins = "gpio67", "gpio68";
1337 function = "b 1321 function = "blsp_i2c10";
1338 drive-strengt 1322 drive-strength = <2>;
1339 bias-disable; 1323 bias-disable;
1340 }; 1324 };
1341 1325
1342 blsp2_i2c4_sleep: bls !! 1326 blsp2_i2c4_sleep: blsp2-i2c4-sleep {
1343 pins = "gpio6 1327 pins = "gpio67", "gpio68";
1344 function = "b 1328 function = "blsp_i2c10";
1345 drive-strengt 1329 drive-strength = <2>;
1346 bias-pull-up; 1330 bias-pull-up;
1347 }; 1331 };
1348 1332
1349 blsp2_i2c5_default: b !! 1333 blsp2_i2c5_default: blsp2-i2c5-default {
1350 pins = "gpio6 1334 pins = "gpio60", "gpio61";
1351 function = "b 1335 function = "blsp_i2c11";
1352 drive-strengt 1336 drive-strength = <2>;
1353 bias-disable; 1337 bias-disable;
1354 }; 1338 };
1355 1339
1356 blsp2_i2c5_sleep: bls !! 1340 blsp2_i2c5_sleep: blsp2-i2c5-sleep {
1357 pins = "gpio6 1341 pins = "gpio60", "gpio61";
1358 function = "b 1342 function = "blsp_i2c11";
1359 drive-strengt 1343 drive-strength = <2>;
1360 bias-pull-up; 1344 bias-pull-up;
1361 }; 1345 };
1362 1346
1363 blsp2_i2c6_default: b !! 1347 blsp2_i2c6_default: blsp2-i2c6-default {
1364 pins = "gpio8 1348 pins = "gpio83", "gpio84";
1365 function = "b 1349 function = "blsp_i2c12";
1366 drive-strengt 1350 drive-strength = <2>;
1367 bias-disable; 1351 bias-disable;
1368 }; 1352 };
1369 1353
1370 blsp2_i2c6_sleep: bls !! 1354 blsp2_i2c6_sleep: blsp2-i2c6-sleep {
1371 pins = "gpio8 1355 pins = "gpio83", "gpio84";
1372 function = "b 1356 function = "blsp_i2c12";
1373 drive-strengt 1357 drive-strength = <2>;
1374 bias-pull-up; 1358 bias-pull-up;
1375 }; 1359 };
1376 <<
1377 blsp2_spi1_default: b <<
1378 pins = "gpio5 <<
1379 function = "b <<
1380 drive-strengt <<
1381 bias-disable; <<
1382 }; <<
1383 <<
1384 blsp2_spi2_default: b <<
1385 pins = "gpio4 <<
1386 function = "b <<
1387 drive-strengt <<
1388 bias-disable; <<
1389 }; <<
1390 <<
1391 blsp2_spi3_default: b <<
1392 pins = "gpio4 <<
1393 function = "b <<
1394 drive-strengt <<
1395 bias-disable; <<
1396 }; <<
1397 <<
1398 blsp2_spi4_default: b <<
1399 pins = "gpio6 <<
1400 function = "b <<
1401 drive-strengt <<
1402 bias-disable; <<
1403 }; <<
1404 <<
1405 blsp2_spi5_default: b <<
1406 pins = "gpio5 <<
1407 function = "b <<
1408 drive-strengt <<
1409 bias-disable; <<
1410 }; <<
1411 <<
1412 blsp2_spi6_default: b <<
1413 pins = "gpio8 <<
1414 function = "b <<
1415 drive-strengt <<
1416 bias-disable; <<
1417 }; <<
1418 }; 1360 };
1419 1361
1420 remoteproc_mss: remoteproc@40 1362 remoteproc_mss: remoteproc@4080000 {
1421 compatible = "qcom,ms 1363 compatible = "qcom,msm8998-mss-pil";
1422 reg = <0x04080000 0x1 1364 reg = <0x04080000 0x100>, <0x04180000 0x20>;
1423 reg-names = "qdsp6", 1365 reg-names = "qdsp6", "rmb";
1424 1366
1425 interrupts-extended = 1367 interrupts-extended =
1426 <&intc GIC_SP 1368 <&intc GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
1427 <&modem_smp2p 1369 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1428 <&modem_smp2p 1370 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1429 <&modem_smp2p 1371 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1430 <&modem_smp2p 1372 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
1431 <&modem_smp2p 1373 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
1432 interrupt-names = "wd 1374 interrupt-names = "wdog", "fatal", "ready",
1433 "ha 1375 "handover", "stop-ack",
1434 "sh 1376 "shutdown-ack";
1435 1377
1436 clocks = <&gcc GCC_MS 1378 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
1437 <&gcc GCC_BI 1379 <&gcc GCC_BIMC_MSS_Q6_AXI_CLK>,
1438 <&gcc GCC_BO 1380 <&gcc GCC_BOOT_ROM_AHB_CLK>,
1439 <&gcc GCC_MS 1381 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
1440 <&gcc GCC_MS 1382 <&gcc GCC_MSS_SNOC_AXI_CLK>,
1441 <&gcc GCC_MS 1383 <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>,
1442 <&rpmcc RPM_ 1384 <&rpmcc RPM_SMD_QDSS_CLK>,
1443 <&rpmcc RPM_ 1385 <&rpmcc RPM_SMD_XO_CLK_SRC>;
1444 clock-names = "iface" 1386 clock-names = "iface", "bus", "mem", "gpll0_mss",
1445 "snoc_a 1387 "snoc_axi", "mnoc_axi", "qdss", "xo";
1446 1388
1447 qcom,smem-states = <& 1389 qcom,smem-states = <&modem_smp2p_out 0>;
1448 qcom,smem-state-names 1390 qcom,smem-state-names = "stop";
1449 1391
1450 resets = <&gcc GCC_MS 1392 resets = <&gcc GCC_MSS_RESTART>;
1451 reset-names = "mss_re 1393 reset-names = "mss_restart";
1452 1394
1453 qcom,halt-regs = <&tc !! 1395 qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
1454 1396
1455 power-domains = <&rpm 1397 power-domains = <&rpmpd MSM8998_VDDCX>,
1456 <&rpm 1398 <&rpmpd MSM8998_VDDMX>;
1457 power-domain-names = 1399 power-domain-names = "cx", "mx";
1458 1400
1459 status = "disabled"; 1401 status = "disabled";
1460 1402
1461 mba { 1403 mba {
1462 memory-region 1404 memory-region = <&mba_mem>;
1463 }; 1405 };
1464 1406
1465 mpss { 1407 mpss {
1466 memory-region 1408 memory-region = <&mpss_mem>;
1467 }; 1409 };
1468 1410
1469 metadata { <<
1470 memory-region <<
1471 }; <<
1472 <<
1473 glink-edge { 1411 glink-edge {
1474 interrupts = 1412 interrupts = <GIC_SPI 452 IRQ_TYPE_EDGE_RISING>;
1475 label = "mode 1413 label = "modem";
1476 qcom,remote-p 1414 qcom,remote-pid = <1>;
1477 mboxes = <&ap 1415 mboxes = <&apcs_glb 15>;
1478 }; 1416 };
1479 }; 1417 };
1480 1418
1481 adreno_gpu: gpu@5000000 { <<
1482 compatible = "qcom,ad <<
1483 reg = <0x05000000 0x4 <<
1484 reg-names = "kgsl_3d0 <<
1485 <<
1486 clocks = <&gcc GCC_GP <<
1487 <&gpucc RBBMT <<
1488 <&gcc GCC_BIM <<
1489 <&gcc GCC_GPU <<
1490 <&gpucc RBCPR <<
1491 <&gpucc GFX3D <<
1492 clock-names = "iface" <<
1493 "rbbmtimer", <<
1494 "mem", <<
1495 "mem_iface", <<
1496 "rbcpr", <<
1497 "core"; <<
1498 <<
1499 interrupts = <GIC_SPI <<
1500 iommus = <&adreno_smm <<
1501 operating-points-v2 = <<
1502 power-domains = <&rpm <<
1503 status = "disabled"; <<
1504 <<
1505 gpu_opp_table: opp-ta <<
1506 compatible = <<
1507 opp-710000097 <<
1508 opp-h <<
1509 opp-l <<
1510 opp-s <<
1511 }; <<
1512 <<
1513 opp-670000048 <<
1514 opp-h <<
1515 opp-l <<
1516 opp-s <<
1517 }; <<
1518 <<
1519 opp-596000097 <<
1520 opp-h <<
1521 opp-l <<
1522 opp-s <<
1523 }; <<
1524 <<
1525 opp-515000097 <<
1526 opp-h <<
1527 opp-l <<
1528 opp-s <<
1529 }; <<
1530 <<
1531 opp-414000000 <<
1532 opp-h <<
1533 opp-l <<
1534 opp-s <<
1535 }; <<
1536 <<
1537 opp-342000000 <<
1538 opp-h <<
1539 opp-l <<
1540 opp-s <<
1541 }; <<
1542 <<
1543 opp-257000000 <<
1544 opp-h <<
1545 opp-l <<
1546 opp-s <<
1547 }; <<
1548 }; <<
1549 }; <<
1550 <<
1551 adreno_smmu: iommu@5040000 { <<
1552 compatible = "qcom,ms <<
1553 reg = <0x05040000 0x1 <<
1554 clocks = <&gcc GCC_GP <<
1555 <&gcc GCC_BI <<
1556 <&gcc GCC_GP <<
1557 clock-names = "iface" <<
1558 <<
1559 #global-interrupts = <<
1560 #iommu-cells = <1>; <<
1561 interrupts = <<
1562 <GIC_SPI 329 <<
1563 <GIC_SPI 330 <<
1564 <GIC_SPI 331 <<
1565 /* <<
1566 * GPU-GX GDSC's pare <<
1567 * GPU-CX for SMMU bu <<
1568 * Contemporarily, we <<
1569 * domain in the Adre <<
1570 * Enable GPU CX/GX G <<
1571 * SoC VDDMX RPM Powe <<
1572 */ <<
1573 power-domains = <&gpu <<
1574 }; <<
1575 <<
1576 gpucc: clock-controller@50650 1419 gpucc: clock-controller@5065000 {
1577 compatible = "qcom,ms 1420 compatible = "qcom,msm8998-gpucc";
1578 #clock-cells = <1>; 1421 #clock-cells = <1>;
1579 #reset-cells = <1>; 1422 #reset-cells = <1>;
1580 #power-domain-cells = 1423 #power-domain-cells = <1>;
1581 reg = <0x05065000 0x9 1424 reg = <0x05065000 0x9000>;
1582 1425
1583 clocks = <&rpmcc RPM_ 1426 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1584 <&gcc GCC_GP !! 1427 <&gcc GPLL0_OUT_MAIN>;
1585 clock-names = "xo", 1428 clock-names = "xo",
1586 "gpll0" 1429 "gpll0";
1587 }; 1430 };
1588 1431
1589 lpass_q6_smmu: iommu@5100000 <<
1590 compatible = "qcom,ms <<
1591 reg = <0x05100000 0x4 <<
1592 clocks = <&gcc HLOS1_ <<
1593 clock-names = "bus"; <<
1594 <<
1595 #global-interrupts = <<
1596 #iommu-cells = <1>; <<
1597 interrupts = <<
1598 <GIC_SPI 226 <<
1599 <GIC_SPI 393 <<
1600 <GIC_SPI 394 <<
1601 <GIC_SPI 395 <<
1602 <GIC_SPI 396 <<
1603 <GIC_SPI 397 <<
1604 <GIC_SPI 398 <<
1605 <GIC_SPI 399 <<
1606 <GIC_SPI 400 <<
1607 <GIC_SPI 401 <<
1608 <GIC_SPI 402 <<
1609 <GIC_SPI 403 <<
1610 <GIC_SPI 137 <<
1611 <<
1612 power-domains = <&gcc <<
1613 status = "disabled"; <<
1614 }; <<
1615 <<
1616 remoteproc_slpi: remoteproc@5 1432 remoteproc_slpi: remoteproc@5800000 {
1617 compatible = "qcom,ms 1433 compatible = "qcom,msm8998-slpi-pas";
1618 reg = <0x05800000 0x4 1434 reg = <0x05800000 0x4040>;
1619 1435
1620 interrupts-extended = 1436 interrupts-extended = <&intc GIC_SPI 390 IRQ_TYPE_EDGE_RISING>,
1621 1437 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1622 1438 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1623 1439 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1624 1440 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1625 interrupt-names = "wd 1441 interrupt-names = "wdog", "fatal", "ready",
1626 "ha 1442 "handover", "stop-ack";
1627 1443
1628 px-supply = <&vreg_lv 1444 px-supply = <&vreg_lvs2a_1p8>;
1629 1445
1630 clocks = <&rpmcc RPM_ !! 1446 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1631 clock-names = "xo"; !! 1447 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
>> 1448 clock-names = "xo", "aggre2";
1632 1449
1633 memory-region = <&slp 1450 memory-region = <&slpi_mem>;
1634 1451
1635 qcom,smem-states = <& 1452 qcom,smem-states = <&slpi_smp2p_out 0>;
1636 qcom,smem-state-names 1453 qcom,smem-state-names = "stop";
1637 1454
1638 power-domains = <&rpm 1455 power-domains = <&rpmpd MSM8998_SSCCX>;
1639 power-domain-names = 1456 power-domain-names = "ssc_cx";
1640 1457
1641 status = "disabled"; 1458 status = "disabled";
1642 1459
1643 glink-edge { 1460 glink-edge {
1644 interrupts = 1461 interrupts = <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>;
1645 label = "dsps 1462 label = "dsps";
1646 qcom,remote-p 1463 qcom,remote-pid = <3>;
1647 mboxes = <&ap 1464 mboxes = <&apcs_glb 27>;
1648 }; 1465 };
1649 }; 1466 };
1650 1467
1651 stm: stm@6002000 { 1468 stm: stm@6002000 {
1652 compatible = "arm,cor 1469 compatible = "arm,coresight-stm", "arm,primecell";
1653 reg = <0x06002000 0x1 1470 reg = <0x06002000 0x1000>,
1654 <0x16280000 0x1 1471 <0x16280000 0x180000>;
1655 reg-names = "stm-base !! 1472 reg-names = "stm-base", "stm-data-base";
1656 status = "disabled"; 1473 status = "disabled";
1657 1474
1658 clocks = <&rpmcc RPM_ 1475 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1659 clock-names = "apb_pc 1476 clock-names = "apb_pclk", "atclk";
1660 1477
1661 out-ports { 1478 out-ports {
1662 port { 1479 port {
1663 stm_o 1480 stm_out: endpoint {
1664 1481 remote-endpoint = <&funnel0_in7>;
1665 }; 1482 };
1666 }; 1483 };
1667 }; 1484 };
1668 }; 1485 };
1669 1486
1670 funnel1: funnel@6041000 { 1487 funnel1: funnel@6041000 {
1671 compatible = "arm,cor 1488 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1672 reg = <0x06041000 0x1 1489 reg = <0x06041000 0x1000>;
1673 status = "disabled"; 1490 status = "disabled";
1674 1491
1675 clocks = <&rpmcc RPM_ 1492 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1676 clock-names = "apb_pc 1493 clock-names = "apb_pclk", "atclk";
1677 1494
1678 out-ports { 1495 out-ports {
1679 port { 1496 port {
1680 funne 1497 funnel0_out: endpoint {
1681 1498 remote-endpoint =
1682 1499 <&merge_funnel_in0>;
1683 }; 1500 };
1684 }; 1501 };
1685 }; 1502 };
1686 1503
1687 in-ports { 1504 in-ports {
1688 #address-cell 1505 #address-cells = <1>;
1689 #size-cells = 1506 #size-cells = <0>;
1690 1507
1691 port@7 { 1508 port@7 {
1692 reg = 1509 reg = <7>;
1693 funne 1510 funnel0_in7: endpoint {
1694 1511 remote-endpoint = <&stm_out>;
1695 }; 1512 };
1696 }; 1513 };
1697 }; 1514 };
1698 }; 1515 };
1699 1516
1700 funnel2: funnel@6042000 { 1517 funnel2: funnel@6042000 {
1701 compatible = "arm,cor 1518 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1702 reg = <0x06042000 0x1 1519 reg = <0x06042000 0x1000>;
1703 status = "disabled"; 1520 status = "disabled";
1704 1521
1705 clocks = <&rpmcc RPM_ 1522 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1706 clock-names = "apb_pc 1523 clock-names = "apb_pclk", "atclk";
1707 1524
1708 out-ports { 1525 out-ports {
1709 port { 1526 port {
1710 funne 1527 funnel1_out: endpoint {
1711 1528 remote-endpoint =
1712 1529 <&merge_funnel_in1>;
1713 }; 1530 };
1714 }; 1531 };
1715 }; 1532 };
1716 1533
1717 in-ports { 1534 in-ports {
1718 #address-cell 1535 #address-cells = <1>;
1719 #size-cells = 1536 #size-cells = <0>;
1720 1537
1721 port@6 { 1538 port@6 {
1722 reg = 1539 reg = <6>;
1723 funne 1540 funnel1_in6: endpoint {
1724 1541 remote-endpoint =
1725 1542 <&apss_merge_funnel_out>;
1726 }; 1543 };
1727 }; 1544 };
1728 }; 1545 };
1729 }; 1546 };
1730 1547
1731 funnel3: funnel@6045000 { 1548 funnel3: funnel@6045000 {
1732 compatible = "arm,cor 1549 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1733 reg = <0x06045000 0x1 1550 reg = <0x06045000 0x1000>;
1734 status = "disabled"; 1551 status = "disabled";
1735 1552
1736 clocks = <&rpmcc RPM_ 1553 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1737 clock-names = "apb_pc 1554 clock-names = "apb_pclk", "atclk";
1738 1555
1739 out-ports { 1556 out-ports {
1740 port { 1557 port {
1741 merge 1558 merge_funnel_out: endpoint {
1742 1559 remote-endpoint =
1743 1560 <&etf_in>;
1744 }; 1561 };
1745 }; 1562 };
1746 }; 1563 };
1747 1564
1748 in-ports { 1565 in-ports {
1749 #address-cell 1566 #address-cells = <1>;
1750 #size-cells = 1567 #size-cells = <0>;
1751 1568
1752 port@0 { 1569 port@0 {
1753 reg = 1570 reg = <0>;
1754 merge 1571 merge_funnel_in0: endpoint {
1755 1572 remote-endpoint =
1756 1573 <&funnel0_out>;
1757 }; 1574 };
1758 }; 1575 };
1759 1576
1760 port@1 { 1577 port@1 {
1761 reg = 1578 reg = <1>;
1762 merge 1579 merge_funnel_in1: endpoint {
1763 1580 remote-endpoint =
1764 1581 <&funnel1_out>;
1765 }; 1582 };
1766 }; 1583 };
1767 }; 1584 };
1768 }; 1585 };
1769 1586
1770 replicator1: replicator@60460 1587 replicator1: replicator@6046000 {
1771 compatible = "arm,cor 1588 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
1772 reg = <0x06046000 0x1 1589 reg = <0x06046000 0x1000>;
1773 status = "disabled"; 1590 status = "disabled";
1774 1591
1775 clocks = <&rpmcc RPM_ 1592 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1776 clock-names = "apb_pc 1593 clock-names = "apb_pclk", "atclk";
1777 1594
1778 out-ports { 1595 out-ports {
1779 port { 1596 port {
1780 repli 1597 replicator_out: endpoint {
1781 1598 remote-endpoint = <&etr_in>;
1782 }; 1599 };
1783 }; 1600 };
1784 }; 1601 };
1785 1602
1786 in-ports { 1603 in-ports {
1787 port { 1604 port {
1788 repli 1605 replicator_in: endpoint {
1789 1606 remote-endpoint = <&etf_out>;
1790 }; 1607 };
1791 }; 1608 };
1792 }; 1609 };
1793 }; 1610 };
1794 1611
1795 etf: etf@6047000 { 1612 etf: etf@6047000 {
1796 compatible = "arm,cor 1613 compatible = "arm,coresight-tmc", "arm,primecell";
1797 reg = <0x06047000 0x1 1614 reg = <0x06047000 0x1000>;
1798 status = "disabled"; 1615 status = "disabled";
1799 1616
1800 clocks = <&rpmcc RPM_ 1617 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1801 clock-names = "apb_pc 1618 clock-names = "apb_pclk", "atclk";
1802 1619
1803 out-ports { 1620 out-ports {
1804 port { 1621 port {
1805 etf_o 1622 etf_out: endpoint {
1806 1623 remote-endpoint =
1807 1624 <&replicator_in>;
1808 }; 1625 };
1809 }; 1626 };
1810 }; 1627 };
1811 1628
1812 in-ports { 1629 in-ports {
1813 port { 1630 port {
1814 etf_i 1631 etf_in: endpoint {
1815 1632 remote-endpoint =
1816 1633 <&merge_funnel_out>;
1817 }; 1634 };
1818 }; 1635 };
1819 }; 1636 };
1820 }; 1637 };
1821 1638
1822 etr: etr@6048000 { 1639 etr: etr@6048000 {
1823 compatible = "arm,cor 1640 compatible = "arm,coresight-tmc", "arm,primecell";
1824 reg = <0x06048000 0x1 1641 reg = <0x06048000 0x1000>;
1825 status = "disabled"; 1642 status = "disabled";
1826 1643
1827 clocks = <&rpmcc RPM_ 1644 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1828 clock-names = "apb_pc 1645 clock-names = "apb_pclk", "atclk";
1829 arm,scatter-gather; 1646 arm,scatter-gather;
1830 1647
1831 in-ports { 1648 in-ports {
1832 port { 1649 port {
1833 etr_i 1650 etr_in: endpoint {
1834 1651 remote-endpoint =
1835 1652 <&replicator_out>;
1836 }; 1653 };
1837 }; 1654 };
1838 }; 1655 };
1839 }; 1656 };
1840 1657
1841 etm1: etm@7840000 { 1658 etm1: etm@7840000 {
1842 compatible = "arm,cor 1659 compatible = "arm,coresight-etm4x", "arm,primecell";
1843 reg = <0x07840000 0x1 1660 reg = <0x07840000 0x1000>;
1844 status = "disabled"; 1661 status = "disabled";
1845 1662
1846 clocks = <&rpmcc RPM_ 1663 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1847 clock-names = "apb_pc 1664 clock-names = "apb_pclk", "atclk";
1848 1665
1849 cpu = <&CPU0>; 1666 cpu = <&CPU0>;
1850 1667
1851 out-ports { 1668 out-ports {
1852 port { 1669 port {
1853 etm0_ 1670 etm0_out: endpoint {
1854 1671 remote-endpoint =
1855 1672 <&apss_funnel_in0>;
1856 }; 1673 };
1857 }; 1674 };
1858 }; 1675 };
1859 }; 1676 };
1860 1677
1861 etm2: etm@7940000 { 1678 etm2: etm@7940000 {
1862 compatible = "arm,cor 1679 compatible = "arm,coresight-etm4x", "arm,primecell";
1863 reg = <0x07940000 0x1 1680 reg = <0x07940000 0x1000>;
1864 status = "disabled"; 1681 status = "disabled";
1865 1682
1866 clocks = <&rpmcc RPM_ 1683 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1867 clock-names = "apb_pc 1684 clock-names = "apb_pclk", "atclk";
1868 1685
1869 cpu = <&CPU1>; 1686 cpu = <&CPU1>;
1870 1687
1871 out-ports { 1688 out-ports {
1872 port { 1689 port {
1873 etm1_ 1690 etm1_out: endpoint {
1874 1691 remote-endpoint =
1875 1692 <&apss_funnel_in1>;
1876 }; 1693 };
1877 }; 1694 };
1878 }; 1695 };
1879 }; 1696 };
1880 1697
1881 etm3: etm@7a40000 { 1698 etm3: etm@7a40000 {
1882 compatible = "arm,cor 1699 compatible = "arm,coresight-etm4x", "arm,primecell";
1883 reg = <0x07a40000 0x1 1700 reg = <0x07a40000 0x1000>;
1884 status = "disabled"; 1701 status = "disabled";
1885 1702
1886 clocks = <&rpmcc RPM_ 1703 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1887 clock-names = "apb_pc 1704 clock-names = "apb_pclk", "atclk";
1888 1705
1889 cpu = <&CPU2>; 1706 cpu = <&CPU2>;
1890 1707
1891 out-ports { 1708 out-ports {
1892 port { 1709 port {
1893 etm2_ 1710 etm2_out: endpoint {
1894 1711 remote-endpoint =
1895 1712 <&apss_funnel_in2>;
1896 }; 1713 };
1897 }; 1714 };
1898 }; 1715 };
1899 }; 1716 };
1900 1717
1901 etm4: etm@7b40000 { 1718 etm4: etm@7b40000 {
1902 compatible = "arm,cor 1719 compatible = "arm,coresight-etm4x", "arm,primecell";
1903 reg = <0x07b40000 0x1 1720 reg = <0x07b40000 0x1000>;
1904 status = "disabled"; 1721 status = "disabled";
1905 1722
1906 clocks = <&rpmcc RPM_ 1723 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1907 clock-names = "apb_pc 1724 clock-names = "apb_pclk", "atclk";
1908 1725
1909 cpu = <&CPU3>; 1726 cpu = <&CPU3>;
1910 1727
1911 out-ports { 1728 out-ports {
1912 port { 1729 port {
1913 etm3_ 1730 etm3_out: endpoint {
1914 1731 remote-endpoint =
1915 1732 <&apss_funnel_in3>;
1916 }; 1733 };
1917 }; 1734 };
1918 }; 1735 };
1919 }; 1736 };
1920 1737
1921 funnel4: funnel@7b60000 { /* 1738 funnel4: funnel@7b60000 { /* APSS Funnel */
1922 compatible = "arm,cor 1739 compatible = "arm,coresight-etm4x", "arm,primecell";
1923 reg = <0x07b60000 0x1 1740 reg = <0x07b60000 0x1000>;
1924 status = "disabled"; 1741 status = "disabled";
1925 1742
1926 clocks = <&rpmcc RPM_ 1743 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1927 clock-names = "apb_pc 1744 clock-names = "apb_pclk", "atclk";
1928 1745
1929 out-ports { 1746 out-ports {
1930 port { 1747 port {
1931 apss_ 1748 apss_funnel_out: endpoint {
1932 1749 remote-endpoint =
1933 1750 <&apss_merge_funnel_in>;
1934 }; 1751 };
1935 }; 1752 };
1936 }; 1753 };
1937 1754
1938 in-ports { 1755 in-ports {
1939 #address-cell 1756 #address-cells = <1>;
1940 #size-cells = 1757 #size-cells = <0>;
1941 1758
1942 port@0 { 1759 port@0 {
1943 reg = 1760 reg = <0>;
1944 apss_ 1761 apss_funnel_in0: endpoint {
1945 1762 remote-endpoint =
1946 1763 <&etm0_out>;
1947 }; 1764 };
1948 }; 1765 };
1949 1766
1950 port@1 { 1767 port@1 {
1951 reg = 1768 reg = <1>;
1952 apss_ 1769 apss_funnel_in1: endpoint {
1953 1770 remote-endpoint =
1954 1771 <&etm1_out>;
1955 }; 1772 };
1956 }; 1773 };
1957 1774
1958 port@2 { 1775 port@2 {
1959 reg = 1776 reg = <2>;
1960 apss_ 1777 apss_funnel_in2: endpoint {
1961 1778 remote-endpoint =
1962 1779 <&etm2_out>;
1963 }; 1780 };
1964 }; 1781 };
1965 1782
1966 port@3 { 1783 port@3 {
1967 reg = 1784 reg = <3>;
1968 apss_ 1785 apss_funnel_in3: endpoint {
1969 1786 remote-endpoint =
1970 1787 <&etm3_out>;
1971 }; 1788 };
1972 }; 1789 };
1973 1790
1974 port@4 { 1791 port@4 {
1975 reg = 1792 reg = <4>;
1976 apss_ 1793 apss_funnel_in4: endpoint {
1977 1794 remote-endpoint =
1978 1795 <&etm4_out>;
1979 }; 1796 };
1980 }; 1797 };
1981 1798
1982 port@5 { 1799 port@5 {
1983 reg = 1800 reg = <5>;
1984 apss_ 1801 apss_funnel_in5: endpoint {
1985 1802 remote-endpoint =
1986 1803 <&etm5_out>;
1987 }; 1804 };
1988 }; 1805 };
1989 1806
1990 port@6 { 1807 port@6 {
1991 reg = 1808 reg = <6>;
1992 apss_ 1809 apss_funnel_in6: endpoint {
1993 1810 remote-endpoint =
1994 1811 <&etm6_out>;
1995 }; 1812 };
1996 }; 1813 };
1997 1814
1998 port@7 { 1815 port@7 {
1999 reg = 1816 reg = <7>;
2000 apss_ 1817 apss_funnel_in7: endpoint {
2001 1818 remote-endpoint =
2002 1819 <&etm7_out>;
2003 }; 1820 };
2004 }; 1821 };
2005 }; 1822 };
2006 }; 1823 };
2007 1824
2008 funnel5: funnel@7b70000 { 1825 funnel5: funnel@7b70000 {
2009 compatible = "arm,cor 1826 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2010 reg = <0x07b70000 0x1 1827 reg = <0x07b70000 0x1000>;
2011 status = "disabled"; 1828 status = "disabled";
2012 1829
2013 clocks = <&rpmcc RPM_ 1830 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2014 clock-names = "apb_pc 1831 clock-names = "apb_pclk", "atclk";
2015 1832
2016 out-ports { 1833 out-ports {
2017 port { 1834 port {
2018 apss_ 1835 apss_merge_funnel_out: endpoint {
2019 1836 remote-endpoint =
2020 1837 <&funnel1_in6>;
2021 }; 1838 };
2022 }; 1839 };
2023 }; 1840 };
2024 1841
2025 in-ports { 1842 in-ports {
2026 port { 1843 port {
2027 apss_ 1844 apss_merge_funnel_in: endpoint {
2028 1845 remote-endpoint =
2029 1846 <&apss_funnel_out>;
2030 }; 1847 };
2031 }; 1848 };
2032 }; 1849 };
2033 }; 1850 };
2034 1851
2035 etm5: etm@7c40000 { 1852 etm5: etm@7c40000 {
2036 compatible = "arm,cor 1853 compatible = "arm,coresight-etm4x", "arm,primecell";
2037 reg = <0x07c40000 0x1 1854 reg = <0x07c40000 0x1000>;
2038 status = "disabled"; 1855 status = "disabled";
2039 1856
2040 clocks = <&rpmcc RPM_ 1857 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2041 clock-names = "apb_pc 1858 clock-names = "apb_pclk", "atclk";
2042 1859
2043 cpu = <&CPU4>; 1860 cpu = <&CPU4>;
2044 1861
2045 out-ports { !! 1862 port{
2046 port { !! 1863 etm4_out: endpoint {
2047 etm4_ !! 1864 remote-endpoint = <&apss_funnel_in4>;
2048 <<
2049 }; <<
2050 }; 1865 };
2051 }; 1866 };
2052 }; 1867 };
2053 1868
2054 etm6: etm@7d40000 { 1869 etm6: etm@7d40000 {
2055 compatible = "arm,cor 1870 compatible = "arm,coresight-etm4x", "arm,primecell";
2056 reg = <0x07d40000 0x1 1871 reg = <0x07d40000 0x1000>;
2057 status = "disabled"; 1872 status = "disabled";
2058 1873
2059 clocks = <&rpmcc RPM_ 1874 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2060 clock-names = "apb_pc 1875 clock-names = "apb_pclk", "atclk";
2061 1876
2062 cpu = <&CPU5>; 1877 cpu = <&CPU5>;
2063 1878
2064 out-ports { !! 1879 port{
2065 port { !! 1880 etm5_out: endpoint {
2066 etm5_ !! 1881 remote-endpoint = <&apss_funnel_in5>;
2067 <<
2068 }; <<
2069 }; 1882 };
2070 }; 1883 };
2071 }; 1884 };
2072 1885
2073 etm7: etm@7e40000 { 1886 etm7: etm@7e40000 {
2074 compatible = "arm,cor 1887 compatible = "arm,coresight-etm4x", "arm,primecell";
2075 reg = <0x07e40000 0x1 1888 reg = <0x07e40000 0x1000>;
2076 status = "disabled"; 1889 status = "disabled";
2077 1890
2078 clocks = <&rpmcc RPM_ 1891 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2079 clock-names = "apb_pc 1892 clock-names = "apb_pclk", "atclk";
2080 1893
2081 cpu = <&CPU6>; 1894 cpu = <&CPU6>;
2082 1895
2083 out-ports { !! 1896 port{
2084 port { !! 1897 etm6_out: endpoint {
2085 etm6_ !! 1898 remote-endpoint = <&apss_funnel_in6>;
2086 <<
2087 }; <<
2088 }; 1899 };
2089 }; 1900 };
2090 }; 1901 };
2091 1902
2092 etm8: etm@7f40000 { 1903 etm8: etm@7f40000 {
2093 compatible = "arm,cor 1904 compatible = "arm,coresight-etm4x", "arm,primecell";
2094 reg = <0x07f40000 0x1 1905 reg = <0x07f40000 0x1000>;
2095 status = "disabled"; 1906 status = "disabled";
2096 1907
2097 clocks = <&rpmcc RPM_ 1908 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2098 clock-names = "apb_pc 1909 clock-names = "apb_pclk", "atclk";
2099 1910
2100 cpu = <&CPU7>; 1911 cpu = <&CPU7>;
2101 1912
2102 out-ports { !! 1913 port{
2103 port { !! 1914 etm7_out: endpoint {
2104 etm7_ !! 1915 remote-endpoint = <&apss_funnel_in7>;
2105 <<
2106 }; <<
2107 }; 1916 };
2108 }; 1917 };
2109 }; 1918 };
2110 1919
2111 sram@290000 { <<
2112 compatible = "qcom,rp <<
2113 reg = <0x00290000 0x1 <<
2114 }; <<
2115 <<
2116 spmi_bus: spmi@800f000 { 1920 spmi_bus: spmi@800f000 {
2117 compatible = "qcom,sp 1921 compatible = "qcom,spmi-pmic-arb";
2118 reg = <0x0800f000 0x1 !! 1922 reg = <0x0800f000 0x1000>,
2119 <0x08400000 0x1 !! 1923 <0x08400000 0x1000000>,
2120 <0x09400000 0x1 !! 1924 <0x09400000 0x1000000>,
2121 <0x0a400000 0x2 !! 1925 <0x0a400000 0x220000>,
2122 <0x0800a000 0x3 !! 1926 <0x0800a000 0x3000>;
2123 reg-names = "core", " 1927 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
2124 interrupt-names = "pe 1928 interrupt-names = "periph_irq";
2125 interrupts = <GIC_SPI 1929 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
2126 qcom,ee = <0>; 1930 qcom,ee = <0>;
2127 qcom,channel = <0>; 1931 qcom,channel = <0>;
2128 #address-cells = <2>; 1932 #address-cells = <2>;
2129 #size-cells = <0>; 1933 #size-cells = <0>;
2130 interrupt-controller; 1934 interrupt-controller;
2131 #interrupt-cells = <4 1935 #interrupt-cells = <4>;
>> 1936 cell-index = <0>;
2132 }; 1937 };
2133 1938
2134 usb3: usb@a8f8800 { 1939 usb3: usb@a8f8800 {
2135 compatible = "qcom,ms 1940 compatible = "qcom,msm8998-dwc3", "qcom,dwc3";
2136 reg = <0x0a8f8800 0x4 1941 reg = <0x0a8f8800 0x400>;
2137 status = "disabled"; 1942 status = "disabled";
2138 #address-cells = <1>; 1943 #address-cells = <1>;
2139 #size-cells = <1>; 1944 #size-cells = <1>;
2140 ranges; 1945 ranges;
2141 1946
2142 clocks = <&gcc GCC_CF 1947 clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>,
2143 <&gcc GCC_US 1948 <&gcc GCC_USB30_MASTER_CLK>,
2144 <&gcc GCC_AG 1949 <&gcc GCC_AGGRE1_USB3_AXI_CLK>,
2145 <&gcc GCC_US !! 1950 <&gcc GCC_USB30_MOCK_UTMI_CLK>,
2146 <&gcc GCC_US !! 1951 <&gcc GCC_USB30_SLEEP_CLK>;
2147 clock-names = "cfg_no !! 1952 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
2148 "core", !! 1953 "sleep";
2149 "iface" <<
2150 "sleep" <<
2151 "mock_u <<
2152 1954
2153 assigned-clocks = <&g 1955 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
2154 <&g 1956 <&gcc GCC_USB30_MASTER_CLK>;
2155 assigned-clock-rates 1957 assigned-clock-rates = <19200000>, <120000000>;
2156 1958
2157 interrupts = <GIC_SPI !! 1959 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
2158 <GIC_SPI <<
2159 <GIC_SPI 1960 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
2160 interrupt-names = "pw !! 1961 interrupt-names = "hs_phy_irq", "ss_phy_irq";
2161 "qu <<
2162 "ss <<
2163 1962
2164 power-domains = <&gcc 1963 power-domains = <&gcc USB_30_GDSC>;
2165 1964
2166 resets = <&gcc GCC_US 1965 resets = <&gcc GCC_USB_30_BCR>;
2167 1966
2168 usb3_dwc3: usb@a80000 !! 1967 usb3_dwc3: dwc3@a800000 {
2169 compatible = 1968 compatible = "snps,dwc3";
2170 reg = <0x0a80 1969 reg = <0x0a800000 0xcd00>;
2171 interrupts = 1970 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
2172 snps,dis_u2_s 1971 snps,dis_u2_susphy_quirk;
2173 snps,dis_enbl 1972 snps,dis_enblslpm_quirk;
2174 snps,parkmode !! 1973 phys = <&qusb2phy>, <&usb1_ssphy>;
2175 phys = <&qusb <<
2176 phy-names = " 1974 phy-names = "usb2-phy", "usb3-phy";
2177 snps,has-lpm- 1975 snps,has-lpm-erratum;
2178 snps,hird-thr 1976 snps,hird-threshold = /bits/ 8 <0x10>;
2179 }; 1977 };
2180 }; 1978 };
2181 1979
2182 usb3phy: phy@c010000 { 1980 usb3phy: phy@c010000 {
2183 compatible = "qcom,ms 1981 compatible = "qcom,msm8998-qmp-usb3-phy";
2184 reg = <0x0c010000 0x1 !! 1982 reg = <0x0c010000 0x18c>;
>> 1983 status = "disabled";
>> 1984 #clock-cells = <1>;
>> 1985 #address-cells = <1>;
>> 1986 #size-cells = <1>;
>> 1987 ranges;
2185 1988
2186 clocks = <&gcc GCC_US 1989 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
2187 <&gcc GCC_US <<
2188 <&gcc GCC_US 1990 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2189 <&gcc GCC_US !! 1991 <&gcc GCC_USB3_CLKREF_CLK>;
2190 clock-names = "aux", !! 1992 clock-names = "aux", "cfg_ahb", "ref";
2191 "ref", <<
2192 "cfg_ah <<
2193 "pipe"; <<
2194 clock-output-names = <<
2195 #clock-cells = <0>; <<
2196 #phy-cells = <0>; <<
2197 1993
2198 resets = <&gcc GCC_US 1994 resets = <&gcc GCC_USB3_PHY_BCR>,
2199 <&gcc GCC_US 1995 <&gcc GCC_USB3PHY_PHY_BCR>;
2200 reset-names = "phy", !! 1996 reset-names = "phy", "common";
2201 "phy_ph <<
2202 <<
2203 qcom,tcsr-reg = <&tcs <<
2204 1997
2205 status = "disabled"; !! 1998 usb1_ssphy: lane@c010200 {
>> 1999 reg = <0xc010200 0x128>,
>> 2000 <0xc010400 0x200>,
>> 2001 <0xc010c00 0x20c>,
>> 2002 <0xc010600 0x128>,
>> 2003 <0xc010800 0x200>;
>> 2004 #phy-cells = <0>;
>> 2005 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
>> 2006 clock-names = "pipe0";
>> 2007 clock-output-names = "usb3_phy_pipe_clk_src";
>> 2008 };
2206 }; 2009 };
2207 2010
2208 qusb2phy: phy@c012000 { 2011 qusb2phy: phy@c012000 {
2209 compatible = "qcom,ms 2012 compatible = "qcom,msm8998-qusb2-phy";
2210 reg = <0x0c012000 0x2 2013 reg = <0x0c012000 0x2a8>;
2211 status = "disabled"; 2014 status = "disabled";
2212 #phy-cells = <0>; 2015 #phy-cells = <0>;
2213 2016
2214 clocks = <&gcc GCC_US 2017 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2215 <&gcc GCC_RX 2018 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
2216 clock-names = "cfg_ah 2019 clock-names = "cfg_ahb", "ref";
2217 2020
2218 resets = <&gcc GCC_QU 2021 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2219 2022
2220 nvmem-cells = <&qusb2 2023 nvmem-cells = <&qusb2_hstx_trim>;
2221 }; 2024 };
2222 2025
2223 sdhc2: mmc@c0a4900 { !! 2026 sdhc2: sdhci@c0a4900 {
2224 compatible = "qcom,ms !! 2027 compatible = "qcom,sdhci-msm-v4";
2225 reg = <0x0c0a4900 0x3 2028 reg = <0x0c0a4900 0x314>, <0x0c0a4000 0x800>;
2226 reg-names = "hc", "co !! 2029 reg-names = "hc_mem", "core_mem";
2227 2030
2228 interrupts = <GIC_SPI 2031 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
2229 <GIC_SPI 2032 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
2230 interrupt-names = "hc 2033 interrupt-names = "hc_irq", "pwr_irq";
2231 2034
2232 clock-names = "iface" 2035 clock-names = "iface", "core", "xo";
2233 clocks = <&gcc GCC_SD 2036 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2234 <&gcc GCC_SD 2037 <&gcc GCC_SDCC2_APPS_CLK>,
2235 <&rpmcc RPM_ !! 2038 <&xo>;
2236 bus-width = <4>; 2039 bus-width = <4>;
2237 status = "disabled"; 2040 status = "disabled";
2238 }; 2041 };
2239 2042
2240 blsp1_dma: dma-controller@c14 2043 blsp1_dma: dma-controller@c144000 {
2241 compatible = "qcom,ba 2044 compatible = "qcom,bam-v1.7.0";
2242 reg = <0x0c144000 0x2 2045 reg = <0x0c144000 0x25000>;
2243 interrupts = <GIC_SPI 2046 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
2244 clocks = <&gcc GCC_BL 2047 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
2245 clock-names = "bam_cl 2048 clock-names = "bam_clk";
2246 #dma-cells = <1>; 2049 #dma-cells = <1>;
2247 qcom,ee = <0>; 2050 qcom,ee = <0>;
2248 qcom,controlled-remot 2051 qcom,controlled-remotely;
2249 num-channels = <18>; 2052 num-channels = <18>;
2250 qcom,num-ees = <4>; 2053 qcom,num-ees = <4>;
2251 }; 2054 };
2252 2055
2253 blsp1_uart3: serial@c171000 { 2056 blsp1_uart3: serial@c171000 {
2254 compatible = "qcom,ms 2057 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2255 reg = <0x0c171000 0x1 2058 reg = <0x0c171000 0x1000>;
2256 interrupts = <GIC_SPI 2059 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
2257 clocks = <&gcc GCC_BL 2060 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
2258 <&gcc GCC_BL 2061 <&gcc GCC_BLSP1_AHB_CLK>;
2259 clock-names = "core", 2062 clock-names = "core", "iface";
2260 dmas = <&blsp1_dma 4> 2063 dmas = <&blsp1_dma 4>, <&blsp1_dma 5>;
2261 dma-names = "tx", "rx 2064 dma-names = "tx", "rx";
2262 pinctrl-names = "defa 2065 pinctrl-names = "default";
2263 pinctrl-0 = <&blsp1_u 2066 pinctrl-0 = <&blsp1_uart3_on>;
2264 status = "disabled"; 2067 status = "disabled";
2265 }; 2068 };
2266 2069
2267 blsp1_i2c1: i2c@c175000 { 2070 blsp1_i2c1: i2c@c175000 {
2268 compatible = "qcom,i2 2071 compatible = "qcom,i2c-qup-v2.2.1";
2269 reg = <0x0c175000 0x6 2072 reg = <0x0c175000 0x600>;
2270 interrupts = <GIC_SPI 2073 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
2271 2074
2272 clocks = <&gcc GCC_BL 2075 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
2273 <&gcc GCC_BL 2076 <&gcc GCC_BLSP1_AHB_CLK>;
2274 clock-names = "core", 2077 clock-names = "core", "iface";
2275 dmas = <&blsp1_dma 6> 2078 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>;
2276 dma-names = "tx", "rx 2079 dma-names = "tx", "rx";
2277 pinctrl-names = "defa 2080 pinctrl-names = "default", "sleep";
2278 pinctrl-0 = <&blsp1_i 2081 pinctrl-0 = <&blsp1_i2c1_default>;
2279 pinctrl-1 = <&blsp1_i 2082 pinctrl-1 = <&blsp1_i2c1_sleep>;
2280 clock-frequency = <40 2083 clock-frequency = <400000>;
2281 2084
2282 status = "disabled"; 2085 status = "disabled";
2283 #address-cells = <1>; 2086 #address-cells = <1>;
2284 #size-cells = <0>; 2087 #size-cells = <0>;
2285 }; 2088 };
2286 2089
2287 blsp1_i2c2: i2c@c176000 { 2090 blsp1_i2c2: i2c@c176000 {
2288 compatible = "qcom,i2 2091 compatible = "qcom,i2c-qup-v2.2.1";
2289 reg = <0x0c176000 0x6 2092 reg = <0x0c176000 0x600>;
2290 interrupts = <GIC_SPI 2093 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
2291 2094
2292 clocks = <&gcc GCC_BL 2095 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
2293 <&gcc GCC_BL 2096 <&gcc GCC_BLSP1_AHB_CLK>;
2294 clock-names = "core", 2097 clock-names = "core", "iface";
2295 dmas = <&blsp1_dma 8> 2098 dmas = <&blsp1_dma 8>, <&blsp1_dma 9>;
2296 dma-names = "tx", "rx 2099 dma-names = "tx", "rx";
2297 pinctrl-names = "defa 2100 pinctrl-names = "default", "sleep";
2298 pinctrl-0 = <&blsp1_i 2101 pinctrl-0 = <&blsp1_i2c2_default>;
2299 pinctrl-1 = <&blsp1_i 2102 pinctrl-1 = <&blsp1_i2c2_sleep>;
2300 clock-frequency = <40 2103 clock-frequency = <400000>;
2301 2104
2302 status = "disabled"; 2105 status = "disabled";
2303 #address-cells = <1>; 2106 #address-cells = <1>;
2304 #size-cells = <0>; 2107 #size-cells = <0>;
2305 }; 2108 };
2306 2109
2307 blsp1_i2c3: i2c@c177000 { 2110 blsp1_i2c3: i2c@c177000 {
2308 compatible = "qcom,i2 2111 compatible = "qcom,i2c-qup-v2.2.1";
2309 reg = <0x0c177000 0x6 2112 reg = <0x0c177000 0x600>;
2310 interrupts = <GIC_SPI 2113 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
2311 2114
2312 clocks = <&gcc GCC_BL 2115 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
2313 <&gcc GCC_BL 2116 <&gcc GCC_BLSP1_AHB_CLK>;
2314 clock-names = "core", 2117 clock-names = "core", "iface";
2315 dmas = <&blsp1_dma 10 2118 dmas = <&blsp1_dma 10>, <&blsp1_dma 11>;
2316 dma-names = "tx", "rx 2119 dma-names = "tx", "rx";
2317 pinctrl-names = "defa 2120 pinctrl-names = "default", "sleep";
2318 pinctrl-0 = <&blsp1_i 2121 pinctrl-0 = <&blsp1_i2c3_default>;
2319 pinctrl-1 = <&blsp1_i 2122 pinctrl-1 = <&blsp1_i2c3_sleep>;
2320 clock-frequency = <40 2123 clock-frequency = <400000>;
2321 2124
2322 status = "disabled"; 2125 status = "disabled";
2323 #address-cells = <1>; 2126 #address-cells = <1>;
2324 #size-cells = <0>; 2127 #size-cells = <0>;
2325 }; 2128 };
2326 2129
2327 blsp1_i2c4: i2c@c178000 { 2130 blsp1_i2c4: i2c@c178000 {
2328 compatible = "qcom,i2 2131 compatible = "qcom,i2c-qup-v2.2.1";
2329 reg = <0x0c178000 0x6 2132 reg = <0x0c178000 0x600>;
2330 interrupts = <GIC_SPI 2133 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
2331 2134
2332 clocks = <&gcc GCC_BL 2135 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
2333 <&gcc GCC_BL 2136 <&gcc GCC_BLSP1_AHB_CLK>;
2334 clock-names = "core", 2137 clock-names = "core", "iface";
2335 dmas = <&blsp1_dma 12 2138 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
2336 dma-names = "tx", "rx 2139 dma-names = "tx", "rx";
2337 pinctrl-names = "defa 2140 pinctrl-names = "default", "sleep";
2338 pinctrl-0 = <&blsp1_i 2141 pinctrl-0 = <&blsp1_i2c4_default>;
2339 pinctrl-1 = <&blsp1_i 2142 pinctrl-1 = <&blsp1_i2c4_sleep>;
2340 clock-frequency = <40 2143 clock-frequency = <400000>;
2341 2144
2342 status = "disabled"; 2145 status = "disabled";
2343 #address-cells = <1>; 2146 #address-cells = <1>;
2344 #size-cells = <0>; 2147 #size-cells = <0>;
2345 }; 2148 };
2346 2149
2347 blsp1_i2c5: i2c@c179000 { 2150 blsp1_i2c5: i2c@c179000 {
2348 compatible = "qcom,i2 2151 compatible = "qcom,i2c-qup-v2.2.1";
2349 reg = <0x0c179000 0x6 2152 reg = <0x0c179000 0x600>;
2350 interrupts = <GIC_SPI 2153 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
2351 2154
2352 clocks = <&gcc GCC_BL 2155 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
2353 <&gcc GCC_BL 2156 <&gcc GCC_BLSP1_AHB_CLK>;
2354 clock-names = "core", 2157 clock-names = "core", "iface";
2355 dmas = <&blsp1_dma 14 2158 dmas = <&blsp1_dma 14>, <&blsp1_dma 15>;
2356 dma-names = "tx", "rx 2159 dma-names = "tx", "rx";
2357 pinctrl-names = "defa 2160 pinctrl-names = "default", "sleep";
2358 pinctrl-0 = <&blsp1_i 2161 pinctrl-0 = <&blsp1_i2c5_default>;
2359 pinctrl-1 = <&blsp1_i 2162 pinctrl-1 = <&blsp1_i2c5_sleep>;
2360 clock-frequency = <40 2163 clock-frequency = <400000>;
2361 2164
2362 status = "disabled"; 2165 status = "disabled";
2363 #address-cells = <1>; 2166 #address-cells = <1>;
2364 #size-cells = <0>; 2167 #size-cells = <0>;
2365 }; 2168 };
2366 2169
2367 blsp1_i2c6: i2c@c17a000 { 2170 blsp1_i2c6: i2c@c17a000 {
2368 compatible = "qcom,i2 2171 compatible = "qcom,i2c-qup-v2.2.1";
2369 reg = <0x0c17a000 0x6 2172 reg = <0x0c17a000 0x600>;
2370 interrupts = <GIC_SPI 2173 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
2371 2174
2372 clocks = <&gcc GCC_BL 2175 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
2373 <&gcc GCC_BL 2176 <&gcc GCC_BLSP1_AHB_CLK>;
2374 clock-names = "core", 2177 clock-names = "core", "iface";
2375 dmas = <&blsp1_dma 16 2178 dmas = <&blsp1_dma 16>, <&blsp1_dma 17>;
2376 dma-names = "tx", "rx 2179 dma-names = "tx", "rx";
2377 pinctrl-names = "defa 2180 pinctrl-names = "default", "sleep";
2378 pinctrl-0 = <&blsp1_i 2181 pinctrl-0 = <&blsp1_i2c6_default>;
2379 pinctrl-1 = <&blsp1_i 2182 pinctrl-1 = <&blsp1_i2c6_sleep>;
2380 clock-frequency = <40 2183 clock-frequency = <400000>;
2381 2184
2382 status = "disabled"; 2185 status = "disabled";
2383 #address-cells = <1>; 2186 #address-cells = <1>;
2384 #size-cells = <0>; 2187 #size-cells = <0>;
2385 }; 2188 };
2386 2189
2387 blsp1_spi1: spi@c175000 { !! 2190 blsp2_dma: dma@c184000 {
2388 compatible = "qcom,sp <<
2389 reg = <0x0c175000 0x6 <<
2390 interrupts = <GIC_SPI <<
2391 <<
2392 clocks = <&gcc GCC_BL <<
2393 <&gcc GCC_BL <<
2394 clock-names = "core", <<
2395 dmas = <&blsp1_dma 6> <<
2396 dma-names = "tx", "rx <<
2397 pinctrl-names = "defa <<
2398 pinctrl-0 = <&blsp1_s <<
2399 <<
2400 status = "disabled"; <<
2401 #address-cells = <1>; <<
2402 #size-cells = <0>; <<
2403 }; <<
2404 <<
2405 blsp1_spi2: spi@c176000 { <<
2406 compatible = "qcom,sp <<
2407 reg = <0x0c176000 0x6 <<
2408 interrupts = <GIC_SPI <<
2409 <<
2410 clocks = <&gcc GCC_BL <<
2411 <&gcc GCC_BL <<
2412 clock-names = "core", <<
2413 dmas = <&blsp1_dma 8> <<
2414 dma-names = "tx", "rx <<
2415 pinctrl-names = "defa <<
2416 pinctrl-0 = <&blsp1_s <<
2417 <<
2418 status = "disabled"; <<
2419 #address-cells = <1>; <<
2420 #size-cells = <0>; <<
2421 }; <<
2422 <<
2423 blsp1_spi3: spi@c177000 { <<
2424 compatible = "qcom,sp <<
2425 reg = <0x0c177000 0x6 <<
2426 interrupts = <GIC_SPI <<
2427 <<
2428 clocks = <&gcc GCC_BL <<
2429 <&gcc GCC_BL <<
2430 clock-names = "core", <<
2431 dmas = <&blsp1_dma 10 <<
2432 dma-names = "tx", "rx <<
2433 pinctrl-names = "defa <<
2434 pinctrl-0 = <&blsp1_s <<
2435 <<
2436 status = "disabled"; <<
2437 #address-cells = <1>; <<
2438 #size-cells = <0>; <<
2439 }; <<
2440 <<
2441 blsp1_spi4: spi@c178000 { <<
2442 compatible = "qcom,sp <<
2443 reg = <0x0c178000 0x6 <<
2444 interrupts = <GIC_SPI <<
2445 <<
2446 clocks = <&gcc GCC_BL <<
2447 <&gcc GCC_BL <<
2448 clock-names = "core", <<
2449 dmas = <&blsp1_dma 12 <<
2450 dma-names = "tx", "rx <<
2451 pinctrl-names = "defa <<
2452 pinctrl-0 = <&blsp1_s <<
2453 <<
2454 status = "disabled"; <<
2455 #address-cells = <1>; <<
2456 #size-cells = <0>; <<
2457 }; <<
2458 <<
2459 blsp1_spi5: spi@c179000 { <<
2460 compatible = "qcom,sp <<
2461 reg = <0x0c179000 0x6 <<
2462 interrupts = <GIC_SPI <<
2463 <<
2464 clocks = <&gcc GCC_BL <<
2465 <&gcc GCC_BL <<
2466 clock-names = "core", <<
2467 dmas = <&blsp1_dma 14 <<
2468 dma-names = "tx", "rx <<
2469 pinctrl-names = "defa <<
2470 pinctrl-0 = <&blsp1_s <<
2471 <<
2472 status = "disabled"; <<
2473 #address-cells = <1>; <<
2474 #size-cells = <0>; <<
2475 }; <<
2476 <<
2477 blsp1_spi6: spi@c17a000 { <<
2478 compatible = "qcom,sp <<
2479 reg = <0x0c17a000 0x6 <<
2480 interrupts = <GIC_SPI <<
2481 <<
2482 clocks = <&gcc GCC_BL <<
2483 <&gcc GCC_BL <<
2484 clock-names = "core", <<
2485 dmas = <&blsp1_dma 16 <<
2486 dma-names = "tx", "rx <<
2487 pinctrl-names = "defa <<
2488 pinctrl-0 = <&blsp1_s <<
2489 <<
2490 status = "disabled"; <<
2491 #address-cells = <1>; <<
2492 #size-cells = <0>; <<
2493 }; <<
2494 <<
2495 blsp2_dma: dma-controller@c18 <<
2496 compatible = "qcom,ba 2191 compatible = "qcom,bam-v1.7.0";
2497 reg = <0x0c184000 0x2 2192 reg = <0x0c184000 0x25000>;
2498 interrupts = <GIC_SPI 2193 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
2499 clocks = <&gcc GCC_BL 2194 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
2500 clock-names = "bam_cl 2195 clock-names = "bam_clk";
2501 #dma-cells = <1>; 2196 #dma-cells = <1>;
2502 qcom,ee = <0>; 2197 qcom,ee = <0>;
2503 qcom,controlled-remot 2198 qcom,controlled-remotely;
2504 num-channels = <18>; 2199 num-channels = <18>;
2505 qcom,num-ees = <4>; 2200 qcom,num-ees = <4>;
2506 }; 2201 };
2507 2202
2508 blsp2_uart1: serial@c1b0000 { 2203 blsp2_uart1: serial@c1b0000 {
2509 compatible = "qcom,ms 2204 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2510 reg = <0x0c1b0000 0x1 2205 reg = <0x0c1b0000 0x1000>;
2511 interrupts = <GIC_SPI 2206 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
2512 clocks = <&gcc GCC_BL 2207 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
2513 <&gcc GCC_BL 2208 <&gcc GCC_BLSP2_AHB_CLK>;
2514 clock-names = "core", 2209 clock-names = "core", "iface";
2515 status = "disabled"; 2210 status = "disabled";
2516 }; 2211 };
2517 2212
2518 blsp2_i2c1: i2c@c1b5000 { 2213 blsp2_i2c1: i2c@c1b5000 {
2519 compatible = "qcom,i2 2214 compatible = "qcom,i2c-qup-v2.2.1";
2520 reg = <0x0c1b5000 0x6 2215 reg = <0x0c1b5000 0x600>;
2521 interrupts = <GIC_SPI 2216 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
2522 2217
2523 clocks = <&gcc GCC_BL 2218 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
2524 <&gcc GCC_BL 2219 <&gcc GCC_BLSP2_AHB_CLK>;
2525 clock-names = "core", 2220 clock-names = "core", "iface";
2526 dmas = <&blsp2_dma 6> 2221 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>;
2527 dma-names = "tx", "rx 2222 dma-names = "tx", "rx";
2528 pinctrl-names = "defa 2223 pinctrl-names = "default", "sleep";
2529 pinctrl-0 = <&blsp2_i 2224 pinctrl-0 = <&blsp2_i2c1_default>;
2530 pinctrl-1 = <&blsp2_i 2225 pinctrl-1 = <&blsp2_i2c1_sleep>;
2531 clock-frequency = <40 2226 clock-frequency = <400000>;
2532 2227
2533 status = "disabled"; 2228 status = "disabled";
2534 #address-cells = <1>; 2229 #address-cells = <1>;
2535 #size-cells = <0>; 2230 #size-cells = <0>;
2536 }; 2231 };
2537 2232
2538 blsp2_i2c2: i2c@c1b6000 { 2233 blsp2_i2c2: i2c@c1b6000 {
2539 compatible = "qcom,i2 2234 compatible = "qcom,i2c-qup-v2.2.1";
2540 reg = <0x0c1b6000 0x6 2235 reg = <0x0c1b6000 0x600>;
2541 interrupts = <GIC_SPI 2236 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
2542 2237
2543 clocks = <&gcc GCC_BL 2238 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
2544 <&gcc GCC_BL 2239 <&gcc GCC_BLSP2_AHB_CLK>;
2545 clock-names = "core", 2240 clock-names = "core", "iface";
2546 dmas = <&blsp2_dma 8> 2241 dmas = <&blsp2_dma 8>, <&blsp2_dma 9>;
2547 dma-names = "tx", "rx 2242 dma-names = "tx", "rx";
2548 pinctrl-names = "defa 2243 pinctrl-names = "default", "sleep";
2549 pinctrl-0 = <&blsp2_i 2244 pinctrl-0 = <&blsp2_i2c2_default>;
2550 pinctrl-1 = <&blsp2_i 2245 pinctrl-1 = <&blsp2_i2c2_sleep>;
2551 clock-frequency = <40 2246 clock-frequency = <400000>;
2552 2247
2553 status = "disabled"; 2248 status = "disabled";
2554 #address-cells = <1>; 2249 #address-cells = <1>;
2555 #size-cells = <0>; 2250 #size-cells = <0>;
2556 }; 2251 };
2557 2252
2558 blsp2_i2c3: i2c@c1b7000 { 2253 blsp2_i2c3: i2c@c1b7000 {
2559 compatible = "qcom,i2 2254 compatible = "qcom,i2c-qup-v2.2.1";
2560 reg = <0x0c1b7000 0x6 2255 reg = <0x0c1b7000 0x600>;
2561 interrupts = <GIC_SPI 2256 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
2562 2257
2563 clocks = <&gcc GCC_BL 2258 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
2564 <&gcc GCC_BL 2259 <&gcc GCC_BLSP2_AHB_CLK>;
2565 clock-names = "core", 2260 clock-names = "core", "iface";
2566 dmas = <&blsp2_dma 10 2261 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>;
2567 dma-names = "tx", "rx 2262 dma-names = "tx", "rx";
2568 pinctrl-names = "defa 2263 pinctrl-names = "default", "sleep";
2569 pinctrl-0 = <&blsp2_i 2264 pinctrl-0 = <&blsp2_i2c3_default>;
2570 pinctrl-1 = <&blsp2_i 2265 pinctrl-1 = <&blsp2_i2c3_sleep>;
2571 clock-frequency = <40 2266 clock-frequency = <400000>;
2572 2267
2573 status = "disabled"; 2268 status = "disabled";
2574 #address-cells = <1>; 2269 #address-cells = <1>;
2575 #size-cells = <0>; 2270 #size-cells = <0>;
2576 }; 2271 };
2577 2272
2578 blsp2_i2c4: i2c@c1b8000 { 2273 blsp2_i2c4: i2c@c1b8000 {
2579 compatible = "qcom,i2 2274 compatible = "qcom,i2c-qup-v2.2.1";
2580 reg = <0x0c1b8000 0x6 2275 reg = <0x0c1b8000 0x600>;
2581 interrupts = <GIC_SPI 2276 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
2582 2277
2583 clocks = <&gcc GCC_BL 2278 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>,
2584 <&gcc GCC_BL 2279 <&gcc GCC_BLSP2_AHB_CLK>;
2585 clock-names = "core", 2280 clock-names = "core", "iface";
2586 dmas = <&blsp2_dma 12 2281 dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
2587 dma-names = "tx", "rx 2282 dma-names = "tx", "rx";
2588 pinctrl-names = "defa 2283 pinctrl-names = "default", "sleep";
2589 pinctrl-0 = <&blsp2_i 2284 pinctrl-0 = <&blsp2_i2c4_default>;
2590 pinctrl-1 = <&blsp2_i 2285 pinctrl-1 = <&blsp2_i2c4_sleep>;
2591 clock-frequency = <40 2286 clock-frequency = <400000>;
2592 2287
2593 status = "disabled"; 2288 status = "disabled";
2594 #address-cells = <1>; 2289 #address-cells = <1>;
2595 #size-cells = <0>; 2290 #size-cells = <0>;
2596 }; 2291 };
2597 2292
2598 blsp2_i2c5: i2c@c1b9000 { 2293 blsp2_i2c5: i2c@c1b9000 {
2599 compatible = "qcom,i2 2294 compatible = "qcom,i2c-qup-v2.2.1";
2600 reg = <0x0c1b9000 0x6 2295 reg = <0x0c1b9000 0x600>;
2601 interrupts = <GIC_SPI 2296 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
2602 2297
2603 clocks = <&gcc GCC_BL 2298 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,
2604 <&gcc GCC_BL 2299 <&gcc GCC_BLSP2_AHB_CLK>;
2605 clock-names = "core", 2300 clock-names = "core", "iface";
2606 dmas = <&blsp2_dma 14 2301 dmas = <&blsp2_dma 14>, <&blsp2_dma 15>;
2607 dma-names = "tx", "rx 2302 dma-names = "tx", "rx";
2608 pinctrl-names = "defa 2303 pinctrl-names = "default", "sleep";
2609 pinctrl-0 = <&blsp2_i 2304 pinctrl-0 = <&blsp2_i2c5_default>;
2610 pinctrl-1 = <&blsp2_i 2305 pinctrl-1 = <&blsp2_i2c5_sleep>;
2611 clock-frequency = <40 2306 clock-frequency = <400000>;
2612 2307
2613 status = "disabled"; 2308 status = "disabled";
2614 #address-cells = <1>; 2309 #address-cells = <1>;
2615 #size-cells = <0>; 2310 #size-cells = <0>;
2616 }; 2311 };
2617 2312
2618 blsp2_i2c6: i2c@c1ba000 { 2313 blsp2_i2c6: i2c@c1ba000 {
2619 compatible = "qcom,i2 2314 compatible = "qcom,i2c-qup-v2.2.1";
2620 reg = <0x0c1ba000 0x6 2315 reg = <0x0c1ba000 0x600>;
2621 interrupts = <GIC_SPI 2316 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
2622 2317
2623 clocks = <&gcc GCC_BL 2318 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>,
2624 <&gcc GCC_BL 2319 <&gcc GCC_BLSP2_AHB_CLK>;
2625 clock-names = "core", 2320 clock-names = "core", "iface";
2626 dmas = <&blsp2_dma 16 2321 dmas = <&blsp2_dma 16>, <&blsp2_dma 17>;
2627 dma-names = "tx", "rx 2322 dma-names = "tx", "rx";
2628 pinctrl-names = "defa 2323 pinctrl-names = "default", "sleep";
2629 pinctrl-0 = <&blsp2_i 2324 pinctrl-0 = <&blsp2_i2c6_default>;
2630 pinctrl-1 = <&blsp2_i 2325 pinctrl-1 = <&blsp2_i2c6_sleep>;
2631 clock-frequency = <40 2326 clock-frequency = <400000>;
2632 2327
2633 status = "disabled"; 2328 status = "disabled";
2634 #address-cells = <1>; 2329 #address-cells = <1>;
2635 #size-cells = <0>; 2330 #size-cells = <0>;
2636 }; 2331 };
2637 2332
2638 blsp2_spi1: spi@c1b5000 { <<
2639 compatible = "qcom,sp <<
2640 reg = <0x0c1b5000 0x6 <<
2641 interrupts = <GIC_SPI <<
2642 <<
2643 clocks = <&gcc GCC_BL <<
2644 <&gcc GCC_BL <<
2645 clock-names = "core", <<
2646 dmas = <&blsp2_dma 6> <<
2647 dma-names = "tx", "rx <<
2648 pinctrl-names = "defa <<
2649 pinctrl-0 = <&blsp2_s <<
2650 <<
2651 status = "disabled"; <<
2652 #address-cells = <1>; <<
2653 #size-cells = <0>; <<
2654 }; <<
2655 <<
2656 blsp2_spi2: spi@c1b6000 { <<
2657 compatible = "qcom,sp <<
2658 reg = <0x0c1b6000 0x6 <<
2659 interrupts = <GIC_SPI <<
2660 <<
2661 clocks = <&gcc GCC_BL <<
2662 <&gcc GCC_BL <<
2663 clock-names = "core", <<
2664 dmas = <&blsp2_dma 8> <<
2665 dma-names = "tx", "rx <<
2666 pinctrl-names = "defa <<
2667 pinctrl-0 = <&blsp2_s <<
2668 <<
2669 status = "disabled"; <<
2670 #address-cells = <1>; <<
2671 #size-cells = <0>; <<
2672 }; <<
2673 <<
2674 blsp2_spi3: spi@c1b7000 { <<
2675 compatible = "qcom,sp <<
2676 reg = <0x0c1b7000 0x6 <<
2677 interrupts = <GIC_SPI <<
2678 <<
2679 clocks = <&gcc GCC_BL <<
2680 <&gcc GCC_BL <<
2681 clock-names = "core", <<
2682 dmas = <&blsp2_dma 10 <<
2683 dma-names = "tx", "rx <<
2684 pinctrl-names = "defa <<
2685 pinctrl-0 = <&blsp2_s <<
2686 <<
2687 status = "disabled"; <<
2688 #address-cells = <1>; <<
2689 #size-cells = <0>; <<
2690 }; <<
2691 <<
2692 blsp2_spi4: spi@c1b8000 { <<
2693 compatible = "qcom,sp <<
2694 reg = <0x0c1b8000 0x6 <<
2695 interrupts = <GIC_SPI <<
2696 <<
2697 clocks = <&gcc GCC_BL <<
2698 <&gcc GCC_BL <<
2699 clock-names = "core", <<
2700 dmas = <&blsp2_dma 12 <<
2701 dma-names = "tx", "rx <<
2702 pinctrl-names = "defa <<
2703 pinctrl-0 = <&blsp2_s <<
2704 <<
2705 status = "disabled"; <<
2706 #address-cells = <1>; <<
2707 #size-cells = <0>; <<
2708 }; <<
2709 <<
2710 blsp2_spi5: spi@c1b9000 { <<
2711 compatible = "qcom,sp <<
2712 reg = <0x0c1b9000 0x6 <<
2713 interrupts = <GIC_SPI <<
2714 <<
2715 clocks = <&gcc GCC_BL <<
2716 <&gcc GCC_BL <<
2717 clock-names = "core", <<
2718 dmas = <&blsp2_dma 14 <<
2719 dma-names = "tx", "rx <<
2720 pinctrl-names = "defa <<
2721 pinctrl-0 = <&blsp2_s <<
2722 <<
2723 status = "disabled"; <<
2724 #address-cells = <1>; <<
2725 #size-cells = <0>; <<
2726 }; <<
2727 <<
2728 blsp2_spi6: spi@c1ba000 { <<
2729 compatible = "qcom,sp <<
2730 reg = <0x0c1ba000 0x6 <<
2731 interrupts = <GIC_SPI <<
2732 <<
2733 clocks = <&gcc GCC_BL <<
2734 <&gcc GCC_BL <<
2735 clock-names = "core", <<
2736 dmas = <&blsp2_dma 16 <<
2737 dma-names = "tx", "rx <<
2738 pinctrl-names = "defa <<
2739 pinctrl-0 = <&blsp2_s <<
2740 <<
2741 status = "disabled"; <<
2742 #address-cells = <1>; <<
2743 #size-cells = <0>; <<
2744 }; <<
2745 <<
2746 mmcc: clock-controller@c8c000 <<
2747 compatible = "qcom,mm <<
2748 #clock-cells = <1>; <<
2749 #reset-cells = <1>; <<
2750 #power-domain-cells = <<
2751 reg = <0xc8c0000 0x40 <<
2752 <<
2753 clock-names = "xo", <<
2754 "gpll0" <<
2755 "dsi0ds <<
2756 "dsi0by <<
2757 "dsi1ds <<
2758 "dsi1by <<
2759 "hdmipl <<
2760 "dplink <<
2761 "dpvco" <<
2762 "gpll0_ <<
2763 clocks = <&rpmcc RPM_ <<
2764 <&gcc GCC_MM <<
2765 <&mdss_dsi0_ <<
2766 <&mdss_dsi0_ <<
2767 <&mdss_dsi1_ <<
2768 <&mdss_dsi1_ <<
2769 <0>, <<
2770 <0>, <<
2771 <0>, <<
2772 <&gcc GCC_MM <<
2773 }; <<
2774 <<
2775 mdss: display-subsystem@c9000 <<
2776 compatible = "qcom,ms <<
2777 reg = <0x0c900000 0x1 <<
2778 reg-names = "mdss"; <<
2779 <<
2780 interrupts = <GIC_SPI <<
2781 interrupt-controller; <<
2782 #interrupt-cells = <1 <<
2783 <<
2784 clocks = <&mmcc MDSS_ <<
2785 <&mmcc MDSS_ <<
2786 <&mmcc MDSS_ <<
2787 clock-names = "iface" <<
2788 "bus", <<
2789 "core"; <<
2790 <<
2791 power-domains = <&mmc <<
2792 iommus = <&mmss_smmu <<
2793 <<
2794 #address-cells = <1>; <<
2795 #size-cells = <1>; <<
2796 ranges; <<
2797 <<
2798 status = "disabled"; <<
2799 <<
2800 mdss_mdp: display-con <<
2801 compatible = <<
2802 reg = <0x0c90 <<
2803 <0x0c9a <<
2804 <0x0c9b <<
2805 <0x0c9b <<
2806 reg-names = " <<
2807 " <<
2808 " <<
2809 " <<
2810 <<
2811 interrupt-par <<
2812 interrupts = <<
2813 <<
2814 clocks = <&mm <<
2815 <&mm <<
2816 <&mm <<
2817 <&mm <<
2818 <&mm <<
2819 clock-names = <<
2820 <<
2821 <<
2822 <<
2823 <<
2824 <<
2825 assigned-cloc <<
2826 assigned-cloc <<
2827 <<
2828 operating-poi <<
2829 power-domains <<
2830 <<
2831 mdp_opp_table <<
2832 compa <<
2833 <<
2834 opp-1 <<
2835 <<
2836 <<
2837 }; <<
2838 <<
2839 opp-2 <<
2840 <<
2841 <<
2842 }; <<
2843 <<
2844 opp-3 <<
2845 <<
2846 <<
2847 }; <<
2848 <<
2849 opp-4 <<
2850 <<
2851 <<
2852 }; <<
2853 }; <<
2854 <<
2855 ports { <<
2856 #addr <<
2857 #size <<
2858 <<
2859 port@ <<
2860 <<
2861 <<
2862 <<
2863 <<
2864 <<
2865 }; <<
2866 <<
2867 port@ <<
2868 <<
2869 <<
2870 <<
2871 <<
2872 <<
2873 }; <<
2874 }; <<
2875 }; <<
2876 <<
2877 mdss_dsi0: dsi@c99400 <<
2878 compatible = <<
2879 reg = <0x0c99 <<
2880 reg-names = " <<
2881 <<
2882 interrupt-par <<
2883 interrupts = <<
2884 <<
2885 clocks = <&mm <<
2886 <&mm <<
2887 <&mm <<
2888 <&mm <<
2889 <&mm <<
2890 <&mm <<
2891 clock-names = <<
2892 <<
2893 <<
2894 <<
2895 <<
2896 <<
2897 assigned-cloc <<
2898 <<
2899 assigned-cloc <<
2900 <<
2901 <<
2902 operating-poi <<
2903 power-domains <<
2904 <<
2905 phys = <&mdss <<
2906 phy-names = " <<
2907 <<
2908 #address-cell <<
2909 #size-cells = <<
2910 <<
2911 status = "dis <<
2912 <<
2913 ports { <<
2914 #addr <<
2915 #size <<
2916 <<
2917 port@ <<
2918 <<
2919 <<
2920 <<
2921 <<
2922 <<
2923 }; <<
2924 <<
2925 port@ <<
2926 <<
2927 <<
2928 <<
2929 <<
2930 }; <<
2931 }; <<
2932 }; <<
2933 <<
2934 mdss_dsi0_phy: phy@c9 <<
2935 compatible = <<
2936 reg = <0x0c99 <<
2937 <0x0c99 <<
2938 <0x0c99 <<
2939 reg-names = " <<
2940 " <<
2941 " <<
2942 <<
2943 clocks = <&mm <<
2944 <&rp <<
2945 clock-names = <<
2946 <<
2947 #clock-cells <<
2948 #phy-cells = <<
2949 <<
2950 status = "dis <<
2951 }; <<
2952 <<
2953 mdss_dsi1: dsi@c99600 <<
2954 compatible = <<
2955 reg = <0x0c99 <<
2956 reg-names = " <<
2957 <<
2958 interrupt-par <<
2959 interrupts = <<
2960 <<
2961 clocks = <&mm <<
2962 <&mm <<
2963 <&mm <<
2964 <&mm <<
2965 <&mm <<
2966 <&mm <<
2967 clock-names = <<
2968 <<
2969 <<
2970 <<
2971 <<
2972 <<
2973 assigned-cloc <<
2974 <<
2975 assigned-cloc <<
2976 <<
2977 <<
2978 operating-poi <<
2979 power-domains <<
2980 <<
2981 phys = <&mdss <<
2982 phy-names = " <<
2983 <<
2984 #address-cell <<
2985 #size-cells = <<
2986 <<
2987 status = "dis <<
2988 <<
2989 ports { <<
2990 #addr <<
2991 #size <<
2992 <<
2993 port@ <<
2994 <<
2995 <<
2996 <<
2997 <<
2998 <<
2999 }; <<
3000 <<
3001 port@ <<
3002 <<
3003 <<
3004 <<
3005 <<
3006 }; <<
3007 }; <<
3008 }; <<
3009 <<
3010 mdss_dsi1_phy: phy@c9 <<
3011 compatible = <<
3012 reg = <0x0c99 <<
3013 <0x0c99 <<
3014 <0x0c99 <<
3015 reg-names = " <<
3016 " <<
3017 " <<
3018 <<
3019 clocks = <&mm <<
3020 <&rp <<
3021 clock-names = <<
3022 <<
3023 <<
3024 #clock-cells <<
3025 #phy-cells = <<
3026 <<
3027 status = "dis <<
3028 }; <<
3029 }; <<
3030 <<
3031 venus: video-codec@cc00000 { <<
3032 compatible = "qcom,ms <<
3033 reg = <0x0cc00000 0xf <<
3034 interrupts = <GIC_SPI <<
3035 power-domains = <&mmc <<
3036 clocks = <&mmcc VIDEO <<
3037 <&mmcc VIDEO <<
3038 <&mmcc VIDEO <<
3039 <&mmcc VIDEO <<
3040 clock-names = "core", <<
3041 iommus = <&mmss_smmu <<
3042 <&mmss_smmu <<
3043 <&mmss_smmu <<
3044 <&mmss_smmu <<
3045 <&mmss_smmu <<
3046 <&mmss_smmu <<
3047 <&mmss_smmu <<
3048 <&mmss_smmu <<
3049 <&mmss_smmu <<
3050 <&mmss_smmu <<
3051 <&mmss_smmu <<
3052 <&mmss_smmu <<
3053 <&mmss_smmu <<
3054 <&mmss_smmu <<
3055 <&mmss_smmu <<
3056 <&mmss_smmu <<
3057 <&mmss_smmu <<
3058 <&mmss_smmu <<
3059 <&mmss_smmu <<
3060 <&mmss_smmu <<
3061 memory-region = <&ven <<
3062 status = "disabled"; <<
3063 <<
3064 video-decoder { <<
3065 compatible = <<
3066 clocks = <&mm <<
3067 clock-names = <<
3068 power-domains <<
3069 }; <<
3070 <<
3071 video-encoder { <<
3072 compatible = <<
3073 clocks = <&mm <<
3074 clock-names = <<
3075 power-domains <<
3076 }; <<
3077 }; <<
3078 <<
3079 mmss_smmu: iommu@cd00000 { <<
3080 compatible = "qcom,ms <<
3081 reg = <0x0cd00000 0x4 <<
3082 #iommu-cells = <1>; <<
3083 <<
3084 clocks = <&mmcc MNOC_ <<
3085 <&mmcc BIMC_ <<
3086 <&mmcc BIMC_ <<
3087 clock-names = "iface- <<
3088 "iface- <<
3089 "bus-sm <<
3090 <<
3091 #global-interrupts = <<
3092 interrupts = <<
3093 <GIC_SPI 263 <<
3094 <GIC_SPI 266 <<
3095 <GIC_SPI 267 <<
3096 <GIC_SPI 268 <<
3097 <GIC_SPI 244 <<
3098 <GIC_SPI 245 <<
3099 <GIC_SPI 247 <<
3100 <GIC_SPI 248 <<
3101 <GIC_SPI 249 <<
3102 <GIC_SPI 250 <<
3103 <GIC_SPI 251 <<
3104 <GIC_SPI 252 <<
3105 <GIC_SPI 253 <<
3106 <GIC_SPI 254 <<
3107 <GIC_SPI 255 <<
3108 <GIC_SPI 256 <<
3109 <GIC_SPI 260 <<
3110 <GIC_SPI 261 <<
3111 <GIC_SPI 262 <<
3112 <GIC_SPI 272 <<
3113 <<
3114 power-domains = <&mmc <<
3115 }; <<
3116 <<
3117 remoteproc_adsp: remoteproc@1 2333 remoteproc_adsp: remoteproc@17300000 {
3118 compatible = "qcom,ms 2334 compatible = "qcom,msm8998-adsp-pas";
3119 reg = <0x17300000 0x4 2335 reg = <0x17300000 0x4040>;
3120 2336
3121 interrupts-extended = 2337 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
3122 2338 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3123 2339 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3124 2340 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3125 2341 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
3126 interrupt-names = "wd 2342 interrupt-names = "wdog", "fatal", "ready",
3127 "ha 2343 "handover", "stop-ack";
3128 2344
3129 clocks = <&rpmcc RPM_ 2345 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
3130 clock-names = "xo"; 2346 clock-names = "xo";
3131 2347
3132 memory-region = <&ads 2348 memory-region = <&adsp_mem>;
3133 2349
3134 qcom,smem-states = <& 2350 qcom,smem-states = <&adsp_smp2p_out 0>;
3135 qcom,smem-state-names 2351 qcom,smem-state-names = "stop";
3136 2352
3137 power-domains = <&rpm 2353 power-domains = <&rpmpd MSM8998_VDDCX>;
3138 power-domain-names = 2354 power-domain-names = "cx";
3139 2355
3140 status = "disabled"; 2356 status = "disabled";
3141 2357
3142 glink-edge { 2358 glink-edge {
3143 interrupts = 2359 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
3144 label = "lpas 2360 label = "lpass";
3145 qcom,remote-p 2361 qcom,remote-pid = <2>;
3146 mboxes = <&ap 2362 mboxes = <&apcs_glb 9>;
3147 }; 2363 };
3148 }; 2364 };
3149 2365
3150 apcs_glb: mailbox@17911000 { 2366 apcs_glb: mailbox@17911000 {
3151 compatible = "qcom,ms !! 2367 compatible = "qcom,msm8998-apcs-hmss-global";
3152 "qcom,ms <<
3153 reg = <0x17911000 0x1 2368 reg = <0x17911000 0x1000>;
3154 2369
3155 #mbox-cells = <1>; 2370 #mbox-cells = <1>;
3156 }; 2371 };
3157 2372
3158 timer@17920000 { 2373 timer@17920000 {
3159 #address-cells = <1>; 2374 #address-cells = <1>;
3160 #size-cells = <1>; 2375 #size-cells = <1>;
3161 ranges; 2376 ranges;
3162 compatible = "arm,arm 2377 compatible = "arm,armv7-timer-mem";
3163 reg = <0x17920000 0x1 2378 reg = <0x17920000 0x1000>;
3164 2379
3165 frame@17921000 { 2380 frame@17921000 {
3166 frame-number 2381 frame-number = <0>;
3167 interrupts = 2382 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
3168 2383 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
3169 reg = <0x1792 2384 reg = <0x17921000 0x1000>,
3170 <0x1792 2385 <0x17922000 0x1000>;
3171 }; 2386 };
3172 2387
3173 frame@17923000 { 2388 frame@17923000 {
3174 frame-number 2389 frame-number = <1>;
3175 interrupts = 2390 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
3176 reg = <0x1792 2391 reg = <0x17923000 0x1000>;
3177 status = "dis 2392 status = "disabled";
3178 }; 2393 };
3179 2394
3180 frame@17924000 { 2395 frame@17924000 {
3181 frame-number 2396 frame-number = <2>;
3182 interrupts = 2397 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
3183 reg = <0x1792 2398 reg = <0x17924000 0x1000>;
3184 status = "dis 2399 status = "disabled";
3185 }; 2400 };
3186 2401
3187 frame@17925000 { 2402 frame@17925000 {
3188 frame-number 2403 frame-number = <3>;
3189 interrupts = 2404 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3190 reg = <0x1792 2405 reg = <0x17925000 0x1000>;
3191 status = "dis 2406 status = "disabled";
3192 }; 2407 };
3193 2408
3194 frame@17926000 { 2409 frame@17926000 {
3195 frame-number 2410 frame-number = <4>;
3196 interrupts = 2411 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3197 reg = <0x1792 2412 reg = <0x17926000 0x1000>;
3198 status = "dis 2413 status = "disabled";
3199 }; 2414 };
3200 2415
3201 frame@17927000 { 2416 frame@17927000 {
3202 frame-number 2417 frame-number = <5>;
3203 interrupts = 2418 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3204 reg = <0x1792 2419 reg = <0x17927000 0x1000>;
3205 status = "dis 2420 status = "disabled";
3206 }; 2421 };
3207 2422
3208 frame@17928000 { 2423 frame@17928000 {
3209 frame-number 2424 frame-number = <6>;
3210 interrupts = 2425 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
3211 reg = <0x1792 2426 reg = <0x17928000 0x1000>;
3212 status = "dis 2427 status = "disabled";
3213 }; 2428 };
3214 }; 2429 };
3215 2430
3216 intc: interrupt-controller@17 2431 intc: interrupt-controller@17a00000 {
3217 compatible = "arm,gic 2432 compatible = "arm,gic-v3";
3218 reg = <0x17a00000 0x1 2433 reg = <0x17a00000 0x10000>, /* GICD */
3219 <0x17b00000 0x1 2434 <0x17b00000 0x100000>; /* GICR * 8 */
3220 #interrupt-cells = <3 2435 #interrupt-cells = <3>;
3221 #address-cells = <1>; 2436 #address-cells = <1>;
3222 #size-cells = <1>; 2437 #size-cells = <1>;
3223 ranges; 2438 ranges;
3224 interrupt-controller; 2439 interrupt-controller;
3225 #redistributor-region 2440 #redistributor-regions = <1>;
3226 redistributor-stride 2441 redistributor-stride = <0x0 0x20000>;
3227 interrupts = <GIC_PPI 2442 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3228 }; 2443 };
3229 2444
3230 wifi: wifi@18800000 { 2445 wifi: wifi@18800000 {
3231 compatible = "qcom,wc 2446 compatible = "qcom,wcn3990-wifi";
3232 status = "disabled"; 2447 status = "disabled";
3233 reg = <0x18800000 0x8 2448 reg = <0x18800000 0x800000>;
3234 reg-names = "membase" 2449 reg-names = "membase";
3235 memory-region = <&wla 2450 memory-region = <&wlan_msa_mem>;
3236 clocks = <&rpmcc RPM_ 2451 clocks = <&rpmcc RPM_SMD_RF_CLK2_PIN>;
3237 clock-names = "cxo_re 2452 clock-names = "cxo_ref_clk_pin";
3238 interrupts = 2453 interrupts =
3239 <GIC_SPI 413 2454 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
3240 <GIC_SPI 414 2455 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
3241 <GIC_SPI 415 2456 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
3242 <GIC_SPI 416 2457 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
3243 <GIC_SPI 417 2458 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
3244 <GIC_SPI 418 2459 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
3245 <GIC_SPI 420 2460 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
3246 <GIC_SPI 421 2461 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
3247 <GIC_SPI 422 2462 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
3248 <GIC_SPI 423 2463 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
3249 <GIC_SPI 424 2464 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
3250 <GIC_SPI 425 2465 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
3251 iommus = <&anoc2_smmu 2466 iommus = <&anoc2_smmu 0x1900>,
3252 <&anoc2_smmu 2467 <&anoc2_smmu 0x1901>;
3253 qcom,snoc-host-cap-8b 2468 qcom,snoc-host-cap-8bit-quirk;
3254 qcom,no-msa-ready-ind <<
3255 }; 2469 };
3256 }; 2470 };
3257 }; 2471 };
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