1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2016, The Linux Foundation. A 2 /* Copyright (c) 2016, The Linux Foundation. All rights reserved. */
3 3
4 #include <dt-bindings/interrupt-controller/arm 4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-msm8998.h 5 #include <dt-bindings/clock/qcom,gcc-msm8998.h>
6 #include <dt-bindings/clock/qcom,gpucc-msm8998 6 #include <dt-bindings/clock/qcom,gpucc-msm8998.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8998. <<
8 #include <dt-bindings/clock/qcom,rpmcc.h> 7 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/firmware/qcom,scm.h> <<
10 #include <dt-bindings/power/qcom-rpmpd.h> 8 #include <dt-bindings/power/qcom-rpmpd.h>
11 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/gpio/gpio.h>
12 10
13 / { 11 / {
14 interrupt-parent = <&intc>; 12 interrupt-parent = <&intc>;
15 13
16 qcom,msm-id = <292 0x0>; 14 qcom,msm-id = <292 0x0>;
17 15
18 #address-cells = <2>; 16 #address-cells = <2>;
19 #size-cells = <2>; 17 #size-cells = <2>;
20 18
21 chosen { }; 19 chosen { };
22 20
23 memory@80000000 { 21 memory@80000000 {
24 device_type = "memory"; 22 device_type = "memory";
25 /* We expect the bootloader to 23 /* We expect the bootloader to fill in the reg */
26 reg = <0x0 0x80000000 0x0 0x0> 24 reg = <0x0 0x80000000 0x0 0x0>;
27 }; 25 };
28 26
29 reserved-memory { 27 reserved-memory {
30 #address-cells = <2>; 28 #address-cells = <2>;
31 #size-cells = <2>; 29 #size-cells = <2>;
32 ranges; 30 ranges;
33 31
34 hyp_mem: memory@85800000 { 32 hyp_mem: memory@85800000 {
35 reg = <0x0 0x85800000 33 reg = <0x0 0x85800000 0x0 0x600000>;
36 no-map; 34 no-map;
37 }; 35 };
38 36
39 xbl_mem: memory@85e00000 { 37 xbl_mem: memory@85e00000 {
40 reg = <0x0 0x85e00000 38 reg = <0x0 0x85e00000 0x0 0x100000>;
41 no-map; 39 no-map;
42 }; 40 };
43 41
44 smem_mem: smem-mem@86000000 { 42 smem_mem: smem-mem@86000000 {
45 reg = <0x0 0x86000000 43 reg = <0x0 0x86000000 0x0 0x200000>;
46 no-map; 44 no-map;
47 }; 45 };
48 46
49 tz_mem: memory@86200000 { 47 tz_mem: memory@86200000 {
50 reg = <0x0 0x86200000 48 reg = <0x0 0x86200000 0x0 0x2d00000>;
51 no-map; 49 no-map;
52 }; 50 };
53 51
54 rmtfs_mem: memory@88f00000 { 52 rmtfs_mem: memory@88f00000 {
55 compatible = "qcom,rmt 53 compatible = "qcom,rmtfs-mem";
56 reg = <0x0 0x88f00000 54 reg = <0x0 0x88f00000 0x0 0x200000>;
57 no-map; 55 no-map;
58 56
59 qcom,client-id = <1>; 57 qcom,client-id = <1>;
60 qcom,vmid = <QCOM_SCM_ !! 58 qcom,vmid = <15>;
61 }; 59 };
62 60
63 spss_mem: memory@8ab00000 { 61 spss_mem: memory@8ab00000 {
64 reg = <0x0 0x8ab00000 62 reg = <0x0 0x8ab00000 0x0 0x700000>;
65 no-map; 63 no-map;
66 }; 64 };
67 65
68 adsp_mem: memory@8b200000 { 66 adsp_mem: memory@8b200000 {
69 reg = <0x0 0x8b200000 67 reg = <0x0 0x8b200000 0x0 0x1a00000>;
70 no-map; 68 no-map;
71 }; 69 };
72 70
73 mpss_mem: memory@8cc00000 { 71 mpss_mem: memory@8cc00000 {
74 reg = <0x0 0x8cc00000 72 reg = <0x0 0x8cc00000 0x0 0x7000000>;
75 no-map; 73 no-map;
76 }; 74 };
77 75
78 venus_mem: memory@93c00000 { 76 venus_mem: memory@93c00000 {
79 reg = <0x0 0x93c00000 77 reg = <0x0 0x93c00000 0x0 0x500000>;
80 no-map; 78 no-map;
81 }; 79 };
82 80
83 mba_mem: memory@94100000 { 81 mba_mem: memory@94100000 {
84 reg = <0x0 0x94100000 82 reg = <0x0 0x94100000 0x0 0x200000>;
85 no-map; 83 no-map;
86 }; 84 };
87 85
88 slpi_mem: memory@94300000 { 86 slpi_mem: memory@94300000 {
89 reg = <0x0 0x94300000 87 reg = <0x0 0x94300000 0x0 0xf00000>;
90 no-map; 88 no-map;
91 }; 89 };
92 90
93 ipa_fw_mem: memory@95200000 { 91 ipa_fw_mem: memory@95200000 {
94 reg = <0x0 0x95200000 92 reg = <0x0 0x95200000 0x0 0x10000>;
95 no-map; 93 no-map;
96 }; 94 };
97 95
98 ipa_gsi_mem: memory@95210000 { 96 ipa_gsi_mem: memory@95210000 {
99 reg = <0x0 0x95210000 97 reg = <0x0 0x95210000 0x0 0x5000>;
100 no-map; 98 no-map;
101 }; 99 };
102 100
103 gpu_mem: memory@95600000 { 101 gpu_mem: memory@95600000 {
104 reg = <0x0 0x95600000 102 reg = <0x0 0x95600000 0x0 0x100000>;
105 no-map; 103 no-map;
106 }; 104 };
107 105
108 wlan_msa_mem: memory@95700000 106 wlan_msa_mem: memory@95700000 {
109 reg = <0x0 0x95700000 107 reg = <0x0 0x95700000 0x0 0x100000>;
110 no-map; 108 no-map;
111 }; 109 };
112 <<
113 mdata_mem: mpss-metadata { <<
114 alloc-ranges = <0x0 0x <<
115 size = <0x0 0x4000>; <<
116 no-map; <<
117 }; <<
118 }; 110 };
119 111
120 clocks { 112 clocks {
121 xo: xo-board { 113 xo: xo-board {
122 compatible = "fixed-cl 114 compatible = "fixed-clock";
123 #clock-cells = <0>; 115 #clock-cells = <0>;
124 clock-frequency = <192 116 clock-frequency = <19200000>;
125 clock-output-names = " 117 clock-output-names = "xo_board";
126 }; 118 };
127 119
128 sleep_clk: sleep-clk { !! 120 sleep_clk {
129 compatible = "fixed-cl 121 compatible = "fixed-clock";
130 #clock-cells = <0>; 122 #clock-cells = <0>;
131 clock-frequency = <327 123 clock-frequency = <32764>;
132 }; 124 };
133 }; 125 };
134 126
135 cpus { 127 cpus {
136 #address-cells = <2>; 128 #address-cells = <2>;
137 #size-cells = <0>; 129 #size-cells = <0>;
138 130
139 CPU0: cpu@0 { 131 CPU0: cpu@0 {
140 device_type = "cpu"; 132 device_type = "cpu";
141 compatible = "qcom,kry 133 compatible = "qcom,kryo280";
142 reg = <0x0 0x0>; 134 reg = <0x0 0x0>;
143 enable-method = "psci" 135 enable-method = "psci";
144 capacity-dmips-mhz = < 136 capacity-dmips-mhz = <1024>;
145 cpu-idle-states = <&LI 137 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
146 next-level-cache = <&L 138 next-level-cache = <&L2_0>;
147 L2_0: l2-cache { 139 L2_0: l2-cache {
148 compatible = " !! 140 compatible = "arm,arch-cache";
149 cache-level = 141 cache-level = <2>;
150 cache-unified; !! 142 };
>> 143 L1_I_0: l1-icache {
>> 144 compatible = "arm,arch-cache";
>> 145 };
>> 146 L1_D_0: l1-dcache {
>> 147 compatible = "arm,arch-cache";
151 }; 148 };
152 }; 149 };
153 150
154 CPU1: cpu@1 { 151 CPU1: cpu@1 {
155 device_type = "cpu"; 152 device_type = "cpu";
156 compatible = "qcom,kry 153 compatible = "qcom,kryo280";
157 reg = <0x0 0x1>; 154 reg = <0x0 0x1>;
158 enable-method = "psci" 155 enable-method = "psci";
159 capacity-dmips-mhz = < 156 capacity-dmips-mhz = <1024>;
160 cpu-idle-states = <&LI 157 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
161 next-level-cache = <&L 158 next-level-cache = <&L2_0>;
>> 159 L1_I_1: l1-icache {
>> 160 compatible = "arm,arch-cache";
>> 161 };
>> 162 L1_D_1: l1-dcache {
>> 163 compatible = "arm,arch-cache";
>> 164 };
162 }; 165 };
163 166
164 CPU2: cpu@2 { 167 CPU2: cpu@2 {
165 device_type = "cpu"; 168 device_type = "cpu";
166 compatible = "qcom,kry 169 compatible = "qcom,kryo280";
167 reg = <0x0 0x2>; 170 reg = <0x0 0x2>;
168 enable-method = "psci" 171 enable-method = "psci";
169 capacity-dmips-mhz = < 172 capacity-dmips-mhz = <1024>;
170 cpu-idle-states = <&LI 173 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
171 next-level-cache = <&L 174 next-level-cache = <&L2_0>;
>> 175 L1_I_2: l1-icache {
>> 176 compatible = "arm,arch-cache";
>> 177 };
>> 178 L1_D_2: l1-dcache {
>> 179 compatible = "arm,arch-cache";
>> 180 };
172 }; 181 };
173 182
174 CPU3: cpu@3 { 183 CPU3: cpu@3 {
175 device_type = "cpu"; 184 device_type = "cpu";
176 compatible = "qcom,kry 185 compatible = "qcom,kryo280";
177 reg = <0x0 0x3>; 186 reg = <0x0 0x3>;
178 enable-method = "psci" 187 enable-method = "psci";
179 capacity-dmips-mhz = < 188 capacity-dmips-mhz = <1024>;
180 cpu-idle-states = <&LI 189 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
181 next-level-cache = <&L 190 next-level-cache = <&L2_0>;
>> 191 L1_I_3: l1-icache {
>> 192 compatible = "arm,arch-cache";
>> 193 };
>> 194 L1_D_3: l1-dcache {
>> 195 compatible = "arm,arch-cache";
>> 196 };
182 }; 197 };
183 198
184 CPU4: cpu@100 { 199 CPU4: cpu@100 {
185 device_type = "cpu"; 200 device_type = "cpu";
186 compatible = "qcom,kry 201 compatible = "qcom,kryo280";
187 reg = <0x0 0x100>; 202 reg = <0x0 0x100>;
188 enable-method = "psci" 203 enable-method = "psci";
189 capacity-dmips-mhz = < 204 capacity-dmips-mhz = <1536>;
190 cpu-idle-states = <&BI 205 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
191 next-level-cache = <&L 206 next-level-cache = <&L2_1>;
192 L2_1: l2-cache { 207 L2_1: l2-cache {
193 compatible = " !! 208 compatible = "arm,arch-cache";
194 cache-level = 209 cache-level = <2>;
195 cache-unified; !! 210 };
>> 211 L1_I_100: l1-icache {
>> 212 compatible = "arm,arch-cache";
>> 213 };
>> 214 L1_D_100: l1-dcache {
>> 215 compatible = "arm,arch-cache";
196 }; 216 };
197 }; 217 };
198 218
199 CPU5: cpu@101 { 219 CPU5: cpu@101 {
200 device_type = "cpu"; 220 device_type = "cpu";
201 compatible = "qcom,kry 221 compatible = "qcom,kryo280";
202 reg = <0x0 0x101>; 222 reg = <0x0 0x101>;
203 enable-method = "psci" 223 enable-method = "psci";
204 capacity-dmips-mhz = < 224 capacity-dmips-mhz = <1536>;
205 cpu-idle-states = <&BI 225 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
206 next-level-cache = <&L 226 next-level-cache = <&L2_1>;
>> 227 L1_I_101: l1-icache {
>> 228 compatible = "arm,arch-cache";
>> 229 };
>> 230 L1_D_101: l1-dcache {
>> 231 compatible = "arm,arch-cache";
>> 232 };
207 }; 233 };
208 234
209 CPU6: cpu@102 { 235 CPU6: cpu@102 {
210 device_type = "cpu"; 236 device_type = "cpu";
211 compatible = "qcom,kry 237 compatible = "qcom,kryo280";
212 reg = <0x0 0x102>; 238 reg = <0x0 0x102>;
213 enable-method = "psci" 239 enable-method = "psci";
214 capacity-dmips-mhz = < 240 capacity-dmips-mhz = <1536>;
215 cpu-idle-states = <&BI 241 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
216 next-level-cache = <&L 242 next-level-cache = <&L2_1>;
>> 243 L1_I_102: l1-icache {
>> 244 compatible = "arm,arch-cache";
>> 245 };
>> 246 L1_D_102: l1-dcache {
>> 247 compatible = "arm,arch-cache";
>> 248 };
217 }; 249 };
218 250
219 CPU7: cpu@103 { 251 CPU7: cpu@103 {
220 device_type = "cpu"; 252 device_type = "cpu";
221 compatible = "qcom,kry 253 compatible = "qcom,kryo280";
222 reg = <0x0 0x103>; 254 reg = <0x0 0x103>;
223 enable-method = "psci" 255 enable-method = "psci";
224 capacity-dmips-mhz = < 256 capacity-dmips-mhz = <1536>;
225 cpu-idle-states = <&BI 257 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
226 next-level-cache = <&L 258 next-level-cache = <&L2_1>;
>> 259 L1_I_103: l1-icache {
>> 260 compatible = "arm,arch-cache";
>> 261 };
>> 262 L1_D_103: l1-dcache {
>> 263 compatible = "arm,arch-cache";
>> 264 };
227 }; 265 };
228 266
229 cpu-map { 267 cpu-map {
230 cluster0 { 268 cluster0 {
231 core0 { 269 core0 {
232 cpu = 270 cpu = <&CPU0>;
233 }; 271 };
234 272
235 core1 { 273 core1 {
236 cpu = 274 cpu = <&CPU1>;
237 }; 275 };
238 276
239 core2 { 277 core2 {
240 cpu = 278 cpu = <&CPU2>;
241 }; 279 };
242 280
243 core3 { 281 core3 {
244 cpu = 282 cpu = <&CPU3>;
245 }; 283 };
246 }; 284 };
247 285
248 cluster1 { 286 cluster1 {
249 core0 { 287 core0 {
250 cpu = 288 cpu = <&CPU4>;
251 }; 289 };
252 290
253 core1 { 291 core1 {
254 cpu = 292 cpu = <&CPU5>;
255 }; 293 };
256 294
257 core2 { 295 core2 {
258 cpu = 296 cpu = <&CPU6>;
259 }; 297 };
260 298
261 core3 { 299 core3 {
262 cpu = 300 cpu = <&CPU7>;
263 }; 301 };
264 }; 302 };
265 }; 303 };
266 304
267 idle-states { 305 idle-states {
268 entry-method = "psci"; 306 entry-method = "psci";
269 307
270 LITTLE_CPU_SLEEP_0: cp 308 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
271 compatible = " 309 compatible = "arm,idle-state";
272 idle-state-nam 310 idle-state-name = "little-retention";
273 /* CPU Retenti 311 /* CPU Retention (C2D), L2 Active */
274 arm,psci-suspe 312 arm,psci-suspend-param = <0x00000002>;
275 entry-latency- 313 entry-latency-us = <81>;
276 exit-latency-u 314 exit-latency-us = <86>;
277 min-residency- 315 min-residency-us = <504>;
278 }; 316 };
279 317
280 LITTLE_CPU_SLEEP_1: cp 318 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
281 compatible = " 319 compatible = "arm,idle-state";
282 idle-state-nam 320 idle-state-name = "little-power-collapse";
283 /* CPU + L2 Po 321 /* CPU + L2 Power Collapse (C3, D4) */
284 arm,psci-suspe 322 arm,psci-suspend-param = <0x40000003>;
285 entry-latency- 323 entry-latency-us = <814>;
286 exit-latency-u 324 exit-latency-us = <4562>;
287 min-residency- 325 min-residency-us = <9183>;
288 local-timer-st 326 local-timer-stop;
289 }; 327 };
290 328
291 BIG_CPU_SLEEP_0: cpu-s 329 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
292 compatible = " 330 compatible = "arm,idle-state";
293 idle-state-nam 331 idle-state-name = "big-retention";
294 /* CPU Retenti 332 /* CPU Retention (C2D), L2 Active */
295 arm,psci-suspe 333 arm,psci-suspend-param = <0x00000002>;
296 entry-latency- 334 entry-latency-us = <79>;
297 exit-latency-u 335 exit-latency-us = <82>;
298 min-residency- 336 min-residency-us = <1302>;
299 }; 337 };
300 338
301 BIG_CPU_SLEEP_1: cpu-s 339 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
302 compatible = " 340 compatible = "arm,idle-state";
303 idle-state-nam 341 idle-state-name = "big-power-collapse";
304 /* CPU + L2 Po 342 /* CPU + L2 Power Collapse (C3, D4) */
305 arm,psci-suspe 343 arm,psci-suspend-param = <0x40000003>;
306 entry-latency- 344 entry-latency-us = <724>;
307 exit-latency-u 345 exit-latency-us = <2027>;
308 min-residency- 346 min-residency-us = <9419>;
309 local-timer-st 347 local-timer-stop;
310 }; 348 };
311 }; 349 };
312 }; 350 };
313 351
314 firmware { 352 firmware {
315 scm { 353 scm {
316 compatible = "qcom,scm 354 compatible = "qcom,scm-msm8998", "qcom,scm";
317 }; 355 };
318 }; 356 };
319 357
320 dsi_opp_table: opp-table-dsi { !! 358 tcsr_mutex: hwlock {
321 compatible = "operating-points !! 359 compatible = "qcom,tcsr-mutex";
322 !! 360 syscon = <&tcsr_mutex_regs 0 0x1000>;
323 opp-131250000 { !! 361 #hwlock-cells = <1>;
324 opp-hz = /bits/ 64 <13 <<
325 required-opps = <&rpmp <<
326 }; <<
327 <<
328 opp-210000000 { <<
329 opp-hz = /bits/ 64 <21 <<
330 required-opps = <&rpmp <<
331 }; <<
332 <<
333 opp-312500000 { <<
334 opp-hz = /bits/ 64 <31 <<
335 required-opps = <&rpmp <<
336 }; <<
337 }; 362 };
338 363
339 psci { 364 psci {
340 compatible = "arm,psci-1.0"; 365 compatible = "arm,psci-1.0";
341 method = "smc"; 366 method = "smc";
342 }; 367 };
343 368
344 rpm: remoteproc { !! 369 rpm-glink {
345 compatible = "qcom,msm8998-rpm !! 370 compatible = "qcom,glink-rpm";
>> 371
>> 372 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
>> 373 qcom,rpm-msg-ram = <&rpm_msg_ram>;
>> 374 mboxes = <&apcs_glb 0>;
>> 375
>> 376 rpm_requests: rpm-requests {
>> 377 compatible = "qcom,rpm-msm8998";
>> 378 qcom,glink-channels = "rpm_requests";
346 379
347 glink-edge { !! 380 rpmcc: clock-controller {
348 compatible = "qcom,gli !! 381 compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc";
>> 382 #clock-cells = <1>;
>> 383 };
>> 384
>> 385 rpmpd: power-controller {
>> 386 compatible = "qcom,msm8998-rpmpd";
>> 387 #power-domain-cells = <1>;
>> 388 operating-points-v2 = <&rpmpd_opp_table>;
>> 389
>> 390 rpmpd_opp_table: opp-table {
>> 391 compatible = "operating-points-v2";
349 392
350 interrupts = <GIC_SPI !! 393 rpmpd_opp_ret: opp1 {
351 qcom,rpm-msg-ram = <&r !! 394 opp-level = <RPM_SMD_LEVEL_RETENTION>;
352 mboxes = <&apcs_glb 0> !! 395 };
353 !! 396
354 rpm_requests: rpm-requ !! 397 rpmpd_opp_ret_plus: opp2 {
355 compatible = " !! 398 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
356 qcom,glink-cha !! 399 };
357 !! 400
358 rpmcc: clock-c !! 401 rpmpd_opp_min_svs: opp3 {
359 compat !! 402 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
360 clocks !! 403 };
361 clock- !! 404
362 #clock !! 405 rpmpd_opp_low_svs: opp4 {
363 }; !! 406 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
364 !! 407 };
365 rpmpd: power-c !! 408
366 compat !! 409 rpmpd_opp_svs: opp5 {
367 #power !! 410 opp-level = <RPM_SMD_LEVEL_SVS>;
368 operat !! 411 };
369 !! 412
370 rpmpd_ !! 413 rpmpd_opp_svs_plus: opp6 {
371 !! 414 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
372 !! 415 };
373 !! 416
374 !! 417 rpmpd_opp_nom: opp7 {
375 !! 418 opp-level = <RPM_SMD_LEVEL_NOM>;
376 !! 419 };
377 !! 420
378 !! 421 rpmpd_opp_nom_plus: opp8 {
379 !! 422 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
380 !! 423 };
381 !! 424
382 !! 425 rpmpd_opp_turbo: opp9 {
383 !! 426 opp-level = <RPM_SMD_LEVEL_TURBO>;
384 !! 427 };
385 !! 428
386 !! 429 rpmpd_opp_turbo_plus: opp10 {
387 !! 430 opp-level = <RPM_SMD_LEVEL_BINNING>;
388 <<
389 <<
390 <<
391 <<
392 <<
393 <<
394 <<
395 <<
396 <<
397 <<
398 <<
399 <<
400 <<
401 <<
402 <<
403 <<
404 <<
405 <<
406 <<
407 <<
408 <<
409 <<
410 <<
411 <<
412 }; 431 };
413 }; 432 };
414 }; 433 };
415 }; 434 };
416 }; 435 };
417 436
418 smem { 437 smem {
419 compatible = "qcom,smem"; 438 compatible = "qcom,smem";
420 memory-region = <&smem_mem>; 439 memory-region = <&smem_mem>;
421 hwlocks = <&tcsr_mutex 3>; 440 hwlocks = <&tcsr_mutex 3>;
422 }; 441 };
423 442
424 smp2p-lpass { 443 smp2p-lpass {
425 compatible = "qcom,smp2p"; 444 compatible = "qcom,smp2p";
426 qcom,smem = <443>, <429>; 445 qcom,smem = <443>, <429>;
427 446
428 interrupts = <GIC_SPI 158 IRQ_ 447 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
429 448
430 mboxes = <&apcs_glb 10>; 449 mboxes = <&apcs_glb 10>;
431 450
432 qcom,local-pid = <0>; 451 qcom,local-pid = <0>;
433 qcom,remote-pid = <2>; 452 qcom,remote-pid = <2>;
434 453
435 adsp_smp2p_out: master-kernel 454 adsp_smp2p_out: master-kernel {
436 qcom,entry-name = "mas 455 qcom,entry-name = "master-kernel";
437 #qcom,smem-state-cells 456 #qcom,smem-state-cells = <1>;
438 }; 457 };
439 458
440 adsp_smp2p_in: slave-kernel { 459 adsp_smp2p_in: slave-kernel {
441 qcom,entry-name = "sla 460 qcom,entry-name = "slave-kernel";
442 461
443 interrupt-controller; 462 interrupt-controller;
444 #interrupt-cells = <2> 463 #interrupt-cells = <2>;
445 }; 464 };
446 }; 465 };
447 466
448 smp2p-mpss { 467 smp2p-mpss {
449 compatible = "qcom,smp2p"; 468 compatible = "qcom,smp2p";
450 qcom,smem = <435>, <428>; 469 qcom,smem = <435>, <428>;
451 interrupts = <GIC_SPI 451 IRQ_ 470 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
452 mboxes = <&apcs_glb 14>; 471 mboxes = <&apcs_glb 14>;
453 qcom,local-pid = <0>; 472 qcom,local-pid = <0>;
454 qcom,remote-pid = <1>; 473 qcom,remote-pid = <1>;
455 474
456 modem_smp2p_out: master-kernel 475 modem_smp2p_out: master-kernel {
457 qcom,entry-name = "mas 476 qcom,entry-name = "master-kernel";
458 #qcom,smem-state-cells 477 #qcom,smem-state-cells = <1>;
459 }; 478 };
460 479
461 modem_smp2p_in: slave-kernel { 480 modem_smp2p_in: slave-kernel {
462 qcom,entry-name = "sla 481 qcom,entry-name = "slave-kernel";
463 interrupt-controller; 482 interrupt-controller;
464 #interrupt-cells = <2> 483 #interrupt-cells = <2>;
465 }; 484 };
466 }; 485 };
467 486
468 smp2p-slpi { 487 smp2p-slpi {
469 compatible = "qcom,smp2p"; 488 compatible = "qcom,smp2p";
470 qcom,smem = <481>, <430>; 489 qcom,smem = <481>, <430>;
471 interrupts = <GIC_SPI 178 IRQ_ 490 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
472 mboxes = <&apcs_glb 26>; 491 mboxes = <&apcs_glb 26>;
473 qcom,local-pid = <0>; 492 qcom,local-pid = <0>;
474 qcom,remote-pid = <3>; 493 qcom,remote-pid = <3>;
475 494
476 slpi_smp2p_out: master-kernel 495 slpi_smp2p_out: master-kernel {
477 qcom,entry-name = "mas 496 qcom,entry-name = "master-kernel";
478 #qcom,smem-state-cells 497 #qcom,smem-state-cells = <1>;
479 }; 498 };
480 499
481 slpi_smp2p_in: slave-kernel { 500 slpi_smp2p_in: slave-kernel {
482 qcom,entry-name = "sla 501 qcom,entry-name = "slave-kernel";
483 interrupt-controller; 502 interrupt-controller;
484 #interrupt-cells = <2> 503 #interrupt-cells = <2>;
485 }; 504 };
486 }; 505 };
487 506
488 thermal-zones { 507 thermal-zones {
489 cpu0-thermal { 508 cpu0-thermal {
490 polling-delay-passive 509 polling-delay-passive = <250>;
>> 510 polling-delay = <1000>;
491 511
492 thermal-sensors = <&ts 512 thermal-sensors = <&tsens0 1>;
493 513
494 trips { 514 trips {
495 cpu0_alert0: t 515 cpu0_alert0: trip-point0 {
496 temper 516 temperature = <75000>;
497 hyster 517 hysteresis = <2000>;
498 type = 518 type = "passive";
499 }; 519 };
500 520
501 cpu0_crit: cpu !! 521 cpu0_crit: cpu_crit {
502 temper 522 temperature = <110000>;
503 hyster 523 hysteresis = <2000>;
504 type = 524 type = "critical";
505 }; 525 };
506 }; 526 };
507 }; 527 };
508 528
509 cpu1-thermal { 529 cpu1-thermal {
510 polling-delay-passive 530 polling-delay-passive = <250>;
>> 531 polling-delay = <1000>;
511 532
512 thermal-sensors = <&ts 533 thermal-sensors = <&tsens0 2>;
513 534
514 trips { 535 trips {
515 cpu1_alert0: t 536 cpu1_alert0: trip-point0 {
516 temper 537 temperature = <75000>;
517 hyster 538 hysteresis = <2000>;
518 type = 539 type = "passive";
519 }; 540 };
520 541
521 cpu1_crit: cpu !! 542 cpu1_crit: cpu_crit {
522 temper 543 temperature = <110000>;
523 hyster 544 hysteresis = <2000>;
524 type = 545 type = "critical";
525 }; 546 };
526 }; 547 };
527 }; 548 };
528 549
529 cpu2-thermal { 550 cpu2-thermal {
530 polling-delay-passive 551 polling-delay-passive = <250>;
>> 552 polling-delay = <1000>;
531 553
532 thermal-sensors = <&ts 554 thermal-sensors = <&tsens0 3>;
533 555
534 trips { 556 trips {
535 cpu2_alert0: t 557 cpu2_alert0: trip-point0 {
536 temper 558 temperature = <75000>;
537 hyster 559 hysteresis = <2000>;
538 type = 560 type = "passive";
539 }; 561 };
540 562
541 cpu2_crit: cpu !! 563 cpu2_crit: cpu_crit {
542 temper 564 temperature = <110000>;
543 hyster 565 hysteresis = <2000>;
544 type = 566 type = "critical";
545 }; 567 };
546 }; 568 };
547 }; 569 };
548 570
549 cpu3-thermal { 571 cpu3-thermal {
550 polling-delay-passive 572 polling-delay-passive = <250>;
>> 573 polling-delay = <1000>;
551 574
552 thermal-sensors = <&ts 575 thermal-sensors = <&tsens0 4>;
553 576
554 trips { 577 trips {
555 cpu3_alert0: t 578 cpu3_alert0: trip-point0 {
556 temper 579 temperature = <75000>;
557 hyster 580 hysteresis = <2000>;
558 type = 581 type = "passive";
559 }; 582 };
560 583
561 cpu3_crit: cpu !! 584 cpu3_crit: cpu_crit {
562 temper 585 temperature = <110000>;
563 hyster 586 hysteresis = <2000>;
564 type = 587 type = "critical";
565 }; 588 };
566 }; 589 };
567 }; 590 };
568 591
569 cpu4-thermal { 592 cpu4-thermal {
570 polling-delay-passive 593 polling-delay-passive = <250>;
>> 594 polling-delay = <1000>;
571 595
572 thermal-sensors = <&ts 596 thermal-sensors = <&tsens0 7>;
573 597
574 trips { 598 trips {
575 cpu4_alert0: t 599 cpu4_alert0: trip-point0 {
576 temper 600 temperature = <75000>;
577 hyster 601 hysteresis = <2000>;
578 type = 602 type = "passive";
579 }; 603 };
580 604
581 cpu4_crit: cpu !! 605 cpu4_crit: cpu_crit {
582 temper 606 temperature = <110000>;
583 hyster 607 hysteresis = <2000>;
584 type = 608 type = "critical";
585 }; 609 };
586 }; 610 };
587 }; 611 };
588 612
589 cpu5-thermal { 613 cpu5-thermal {
590 polling-delay-passive 614 polling-delay-passive = <250>;
>> 615 polling-delay = <1000>;
591 616
592 thermal-sensors = <&ts 617 thermal-sensors = <&tsens0 8>;
593 618
594 trips { 619 trips {
595 cpu5_alert0: t 620 cpu5_alert0: trip-point0 {
596 temper 621 temperature = <75000>;
597 hyster 622 hysteresis = <2000>;
598 type = 623 type = "passive";
599 }; 624 };
600 625
601 cpu5_crit: cpu !! 626 cpu5_crit: cpu_crit {
602 temper 627 temperature = <110000>;
603 hyster 628 hysteresis = <2000>;
604 type = 629 type = "critical";
605 }; 630 };
606 }; 631 };
607 }; 632 };
608 633
609 cpu6-thermal { 634 cpu6-thermal {
610 polling-delay-passive 635 polling-delay-passive = <250>;
>> 636 polling-delay = <1000>;
611 637
612 thermal-sensors = <&ts 638 thermal-sensors = <&tsens0 9>;
613 639
614 trips { 640 trips {
615 cpu6_alert0: t 641 cpu6_alert0: trip-point0 {
616 temper 642 temperature = <75000>;
617 hyster 643 hysteresis = <2000>;
618 type = 644 type = "passive";
619 }; 645 };
620 646
621 cpu6_crit: cpu !! 647 cpu6_crit: cpu_crit {
622 temper 648 temperature = <110000>;
623 hyster 649 hysteresis = <2000>;
624 type = 650 type = "critical";
625 }; 651 };
626 }; 652 };
627 }; 653 };
628 654
629 cpu7-thermal { 655 cpu7-thermal {
630 polling-delay-passive 656 polling-delay-passive = <250>;
>> 657 polling-delay = <1000>;
631 658
632 thermal-sensors = <&ts 659 thermal-sensors = <&tsens0 10>;
633 660
634 trips { 661 trips {
635 cpu7_alert0: t 662 cpu7_alert0: trip-point0 {
636 temper 663 temperature = <75000>;
637 hyster 664 hysteresis = <2000>;
638 type = 665 type = "passive";
639 }; 666 };
640 667
641 cpu7_crit: cpu !! 668 cpu7_crit: cpu_crit {
642 temper 669 temperature = <110000>;
643 hyster 670 hysteresis = <2000>;
644 type = 671 type = "critical";
645 }; 672 };
646 }; 673 };
647 }; 674 };
648 675
649 gpu-bottom-thermal { !! 676 gpu-thermal-bottom {
650 polling-delay-passive 677 polling-delay-passive = <250>;
>> 678 polling-delay = <1000>;
651 679
652 thermal-sensors = <&ts 680 thermal-sensors = <&tsens0 12>;
653 681
654 trips { 682 trips {
655 gpu1_alert0: t 683 gpu1_alert0: trip-point0 {
656 temper 684 temperature = <90000>;
657 hyster 685 hysteresis = <2000>;
658 type = 686 type = "hot";
659 }; 687 };
660 }; 688 };
661 }; 689 };
662 690
663 gpu-top-thermal { !! 691 gpu-thermal-top {
664 polling-delay-passive 692 polling-delay-passive = <250>;
>> 693 polling-delay = <1000>;
665 694
666 thermal-sensors = <&ts 695 thermal-sensors = <&tsens0 13>;
667 696
668 trips { 697 trips {
669 gpu2_alert0: t 698 gpu2_alert0: trip-point0 {
670 temper 699 temperature = <90000>;
671 hyster 700 hysteresis = <2000>;
672 type = 701 type = "hot";
673 }; 702 };
674 }; 703 };
675 }; 704 };
676 705
677 clust0-mhm-thermal { 706 clust0-mhm-thermal {
678 polling-delay-passive 707 polling-delay-passive = <250>;
>> 708 polling-delay = <1000>;
679 709
680 thermal-sensors = <&ts 710 thermal-sensors = <&tsens0 5>;
681 711
682 trips { 712 trips {
683 cluster0_mhm_a 713 cluster0_mhm_alert0: trip-point0 {
684 temper 714 temperature = <90000>;
685 hyster 715 hysteresis = <2000>;
686 type = 716 type = "hot";
687 }; 717 };
688 }; 718 };
689 }; 719 };
690 720
691 clust1-mhm-thermal { 721 clust1-mhm-thermal {
692 polling-delay-passive 722 polling-delay-passive = <250>;
>> 723 polling-delay = <1000>;
693 724
694 thermal-sensors = <&ts 725 thermal-sensors = <&tsens0 6>;
695 726
696 trips { 727 trips {
697 cluster1_mhm_a 728 cluster1_mhm_alert0: trip-point0 {
698 temper 729 temperature = <90000>;
699 hyster 730 hysteresis = <2000>;
700 type = 731 type = "hot";
701 }; 732 };
702 }; 733 };
703 }; 734 };
704 735
705 cluster1-l2-thermal { 736 cluster1-l2-thermal {
706 polling-delay-passive 737 polling-delay-passive = <250>;
>> 738 polling-delay = <1000>;
707 739
708 thermal-sensors = <&ts 740 thermal-sensors = <&tsens0 11>;
709 741
710 trips { 742 trips {
711 cluster1_l2_al 743 cluster1_l2_alert0: trip-point0 {
712 temper 744 temperature = <90000>;
713 hyster 745 hysteresis = <2000>;
714 type = 746 type = "hot";
715 }; 747 };
716 }; 748 };
717 }; 749 };
718 750
719 modem-thermal { 751 modem-thermal {
720 polling-delay-passive 752 polling-delay-passive = <250>;
>> 753 polling-delay = <1000>;
721 754
722 thermal-sensors = <&ts 755 thermal-sensors = <&tsens1 1>;
723 756
724 trips { 757 trips {
725 modem_alert0: 758 modem_alert0: trip-point0 {
726 temper 759 temperature = <90000>;
727 hyster 760 hysteresis = <2000>;
728 type = 761 type = "hot";
729 }; 762 };
730 }; 763 };
731 }; 764 };
732 765
733 mem-thermal { 766 mem-thermal {
734 polling-delay-passive 767 polling-delay-passive = <250>;
>> 768 polling-delay = <1000>;
735 769
736 thermal-sensors = <&ts 770 thermal-sensors = <&tsens1 2>;
737 771
738 trips { 772 trips {
739 mem_alert0: tr 773 mem_alert0: trip-point0 {
740 temper 774 temperature = <90000>;
741 hyster 775 hysteresis = <2000>;
742 type = 776 type = "hot";
743 }; 777 };
744 }; 778 };
745 }; 779 };
746 780
747 wlan-thermal { 781 wlan-thermal {
748 polling-delay-passive 782 polling-delay-passive = <250>;
>> 783 polling-delay = <1000>;
749 784
750 thermal-sensors = <&ts 785 thermal-sensors = <&tsens1 3>;
751 786
752 trips { 787 trips {
753 wlan_alert0: t 788 wlan_alert0: trip-point0 {
754 temper 789 temperature = <90000>;
755 hyster 790 hysteresis = <2000>;
756 type = 791 type = "hot";
757 }; 792 };
758 }; 793 };
759 }; 794 };
760 795
761 q6-dsp-thermal { 796 q6-dsp-thermal {
762 polling-delay-passive 797 polling-delay-passive = <250>;
>> 798 polling-delay = <1000>;
763 799
764 thermal-sensors = <&ts 800 thermal-sensors = <&tsens1 4>;
765 801
766 trips { 802 trips {
767 q6_dsp_alert0: 803 q6_dsp_alert0: trip-point0 {
768 temper 804 temperature = <90000>;
769 hyster 805 hysteresis = <2000>;
770 type = 806 type = "hot";
771 }; 807 };
772 }; 808 };
773 }; 809 };
774 810
775 camera-thermal { 811 camera-thermal {
776 polling-delay-passive 812 polling-delay-passive = <250>;
>> 813 polling-delay = <1000>;
777 814
778 thermal-sensors = <&ts 815 thermal-sensors = <&tsens1 5>;
779 816
780 trips { 817 trips {
781 camera_alert0: 818 camera_alert0: trip-point0 {
782 temper 819 temperature = <90000>;
783 hyster 820 hysteresis = <2000>;
784 type = 821 type = "hot";
785 }; 822 };
786 }; 823 };
787 }; 824 };
788 825
789 multimedia-thermal { 826 multimedia-thermal {
790 polling-delay-passive 827 polling-delay-passive = <250>;
>> 828 polling-delay = <1000>;
791 829
792 thermal-sensors = <&ts 830 thermal-sensors = <&tsens1 6>;
793 831
794 trips { 832 trips {
795 multimedia_ale 833 multimedia_alert0: trip-point0 {
796 temper 834 temperature = <90000>;
797 hyster 835 hysteresis = <2000>;
798 type = 836 type = "hot";
799 }; 837 };
800 }; 838 };
801 }; 839 };
802 }; 840 };
803 841
804 timer { 842 timer {
805 compatible = "arm,armv8-timer" 843 compatible = "arm,armv8-timer";
806 interrupts = <GIC_PPI 1 IRQ_TY 844 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
807 <GIC_PPI 2 IRQ_TY 845 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
808 <GIC_PPI 3 IRQ_TY 846 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
809 <GIC_PPI 0 IRQ_TY 847 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
810 }; 848 };
811 849
812 soc: soc@0 { !! 850 soc: soc {
813 #address-cells = <1>; 851 #address-cells = <1>;
814 #size-cells = <1>; 852 #size-cells = <1>;
815 ranges = <0 0 0 0xffffffff>; 853 ranges = <0 0 0 0xffffffff>;
816 compatible = "simple-bus"; 854 compatible = "simple-bus";
817 855
818 gcc: clock-controller@100000 { 856 gcc: clock-controller@100000 {
819 compatible = "qcom,gcc 857 compatible = "qcom,gcc-msm8998";
820 #clock-cells = <1>; 858 #clock-cells = <1>;
821 #reset-cells = <1>; 859 #reset-cells = <1>;
822 #power-domain-cells = 860 #power-domain-cells = <1>;
823 reg = <0x00100000 0xb0 861 reg = <0x00100000 0xb0000>;
824 <<
825 clock-names = "xo", "s <<
826 clocks = <&rpmcc RPM_S <<
827 <<
828 /* <<
829 * The hypervisor typi <<
830 * reside as read-only <<
831 * these clocks on a d <<
832 * enabled but unused <<
833 * to reboot. <<
834 * In light of that, w <<
835 * as protected. The b <<
836 * list of protected c <<
837 * desired for the HLO <<
838 */ <<
839 protected-clocks = <AG <<
840 <SS <<
841 <SS <<
842 }; 862 };
843 863
844 rpm_msg_ram: sram@778000 { 864 rpm_msg_ram: sram@778000 {
845 compatible = "qcom,rpm 865 compatible = "qcom,rpm-msg-ram";
846 reg = <0x00778000 0x70 866 reg = <0x00778000 0x7000>;
847 }; 867 };
848 868
849 qfprom: qfprom@784000 { !! 869 qfprom: qfprom@780000 {
850 compatible = "qcom,msm !! 870 compatible = "qcom,qfprom";
851 reg = <0x00784000 0x62 !! 871 reg = <0x00780000 0x621c>;
852 #address-cells = <1>; 872 #address-cells = <1>;
853 #size-cells = <1>; 873 #size-cells = <1>;
854 874
855 qusb2_hstx_trim: hstx- !! 875 qusb2_hstx_trim: hstx-trim@423a {
856 reg = <0x23a 0 !! 876 reg = <0x423a 0x1>;
857 bits = <0 4>; 877 bits = <0 4>;
858 }; 878 };
859 }; 879 };
860 880
861 tsens0: thermal@10ab000 { 881 tsens0: thermal@10ab000 {
862 compatible = "qcom,msm 882 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
863 reg = <0x010ab000 0x10 883 reg = <0x010ab000 0x1000>, /* TM */
864 <0x010aa000 0x10 884 <0x010aa000 0x1000>; /* SROT */
865 #qcom,sensors = <14>; 885 #qcom,sensors = <14>;
866 interrupts = <GIC_SPI 886 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
867 <GIC_SPI 887 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
868 interrupt-names = "upl 888 interrupt-names = "uplow", "critical";
869 #thermal-sensor-cells 889 #thermal-sensor-cells = <1>;
870 }; 890 };
871 891
872 tsens1: thermal@10ae000 { 892 tsens1: thermal@10ae000 {
873 compatible = "qcom,msm 893 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
874 reg = <0x010ae000 0x10 894 reg = <0x010ae000 0x1000>, /* TM */
875 <0x010ad000 0x10 895 <0x010ad000 0x1000>; /* SROT */
876 #qcom,sensors = <8>; 896 #qcom,sensors = <8>;
877 interrupts = <GIC_SPI 897 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
878 <GIC_SPI 898 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
879 interrupt-names = "upl 899 interrupt-names = "uplow", "critical";
880 #thermal-sensor-cells 900 #thermal-sensor-cells = <1>;
881 }; 901 };
882 902
883 anoc1_smmu: iommu@1680000 { 903 anoc1_smmu: iommu@1680000 {
884 compatible = "qcom,msm 904 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
885 reg = <0x01680000 0x10 905 reg = <0x01680000 0x10000>;
886 #iommu-cells = <1>; 906 #iommu-cells = <1>;
887 907
888 #global-interrupts = < 908 #global-interrupts = <0>;
889 interrupts = 909 interrupts =
890 <GIC_SPI 364 I 910 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
891 <GIC_SPI 365 I 911 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
892 <GIC_SPI 366 I 912 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
893 <GIC_SPI 367 I 913 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
894 <GIC_SPI 368 I 914 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
895 <GIC_SPI 369 I 915 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>;
896 }; 916 };
897 917
898 anoc2_smmu: iommu@16c0000 { 918 anoc2_smmu: iommu@16c0000 {
899 compatible = "qcom,msm 919 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
900 reg = <0x016c0000 0x40 920 reg = <0x016c0000 0x40000>;
901 #iommu-cells = <1>; 921 #iommu-cells = <1>;
902 922
903 #global-interrupts = < 923 #global-interrupts = <0>;
904 interrupts = 924 interrupts =
905 <GIC_SPI 373 I 925 <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>,
906 <GIC_SPI 374 I 926 <GIC_SPI 374 IRQ_TYPE_EDGE_RISING>,
907 <GIC_SPI 375 I 927 <GIC_SPI 375 IRQ_TYPE_EDGE_RISING>,
908 <GIC_SPI 376 I 928 <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>,
909 <GIC_SPI 377 I 929 <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>,
910 <GIC_SPI 378 I 930 <GIC_SPI 378 IRQ_TYPE_EDGE_RISING>,
911 <GIC_SPI 462 I 931 <GIC_SPI 462 IRQ_TYPE_EDGE_RISING>,
912 <GIC_SPI 463 I 932 <GIC_SPI 463 IRQ_TYPE_EDGE_RISING>,
913 <GIC_SPI 464 I 933 <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
914 <GIC_SPI 465 I 934 <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>;
915 }; 935 };
916 936
917 pcie0: pcie@1c00000 { !! 937 pcie0: pci@1c00000 {
918 compatible = "qcom,pci !! 938 compatible = "qcom,pcie-msm8996";
919 reg = <0x01c00000 0x20 !! 939 reg = <0x01c00000 0x2000>,
920 <0x1b000000 0xf1 !! 940 <0x1b000000 0xf1d>,
921 <0x1b000f20 0xa8 !! 941 <0x1b000f20 0xa8>,
922 <0x1b100000 0x10 !! 942 <0x1b100000 0x100000>;
923 reg-names = "parf", "d 943 reg-names = "parf", "dbi", "elbi", "config";
924 device_type = "pci"; 944 device_type = "pci";
925 linux,pci-domain = <0> 945 linux,pci-domain = <0>;
926 bus-range = <0x00 0xff 946 bus-range = <0x00 0xff>;
927 #address-cells = <3>; 947 #address-cells = <3>;
928 #size-cells = <2>; 948 #size-cells = <2>;
929 num-lanes = <1>; 949 num-lanes = <1>;
930 phys = <&pcie_phy>; !! 950 phys = <&pciephy>;
931 phy-names = "pciephy"; 951 phy-names = "pciephy";
932 status = "disabled"; 952 status = "disabled";
933 953
934 ranges = <0x01000000 0 954 ranges = <0x01000000 0x0 0x00000000 0x1b200000 0x0 0x100000>,
935 <0x02000000 0 955 <0x02000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>;
936 956
937 #interrupt-cells = <1> 957 #interrupt-cells = <1>;
938 interrupts = <GIC_SPI 958 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
939 interrupt-names = "msi 959 interrupt-names = "msi";
940 interrupt-map-mask = < 960 interrupt-map-mask = <0 0 0 0x7>;
941 interrupt-map = <0 0 0 !! 961 interrupt-map = <0 0 0 1 &intc 0 0 135 IRQ_TYPE_LEVEL_HIGH>,
942 <0 0 0 962 <0 0 0 2 &intc 0 0 136 IRQ_TYPE_LEVEL_HIGH>,
943 <0 0 0 963 <0 0 0 3 &intc 0 0 138 IRQ_TYPE_LEVEL_HIGH>,
944 <0 0 0 964 <0 0 0 4 &intc 0 0 139 IRQ_TYPE_LEVEL_HIGH>;
945 965
946 clocks = <&gcc GCC_PCI 966 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
947 <&gcc GCC_PCI <<
948 <&gcc GCC_PCI <<
949 <&gcc GCC_PCI 967 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
950 <&gcc GCC_PCI !! 968 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
951 clock-names = "pipe", !! 969 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
>> 970 <&gcc GCC_PCIE_0_AUX_CLK>;
>> 971 clock-names = "pipe", "bus_master", "bus_slave", "cfg", "aux";
952 972
953 power-domains = <&gcc 973 power-domains = <&gcc PCIE_0_GDSC>;
954 iommu-map = <0x100 &an 974 iommu-map = <0x100 &anoc1_smmu 0x1480 1>;
955 perst-gpios = <&tlmm 3 975 perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
956 <<
957 pcie@0 { <<
958 device_type = <<
959 reg = <0x0 0x0 <<
960 bus-range = <0 <<
961 <<
962 #address-cells <<
963 #size-cells = <<
964 ranges; <<
965 }; <<
966 }; 976 };
967 977
968 pcie_phy: phy@1c06000 { 978 pcie_phy: phy@1c06000 {
969 compatible = "qcom,msm 979 compatible = "qcom,msm8998-qmp-pcie-phy";
970 reg = <0x01c06000 0x10 !! 980 reg = <0x01c06000 0x18c>;
>> 981 #address-cells = <1>;
>> 982 #size-cells = <1>;
971 status = "disabled"; 983 status = "disabled";
>> 984 ranges;
972 985
973 clocks = <&gcc GCC_PCI 986 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
974 <&gcc GCC_PCI 987 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
975 <&gcc GCC_PCI !! 988 <&gcc GCC_PCIE_CLKREF_CLK>;
976 <&gcc GCC_PCI !! 989 clock-names = "aux", "cfg_ahb", "ref";
977 clock-names = "aux", <<
978 "cfg_ahb <<
979 "ref", <<
980 "pipe"; <<
981 <<
982 clock-output-names = " <<
983 #clock-cells = <0>; <<
984 <<
985 #phy-cells = <0>; <<
986 990
987 resets = <&gcc GCC_PCI 991 resets = <&gcc GCC_PCIE_0_PHY_BCR>, <&gcc GCC_PCIE_PHY_BCR>;
988 reset-names = "phy", " 992 reset-names = "phy", "common";
989 993
990 vdda-phy-supply = <&vr 994 vdda-phy-supply = <&vreg_l1a_0p875>;
991 vdda-pll-supply = <&vr 995 vdda-pll-supply = <&vreg_l2a_1p2>;
>> 996
>> 997 pciephy: phy@1c06800 {
>> 998 reg = <0x01c06200 0x128>, <0x01c06400 0x1fc>, <0x01c06800 0x20c>;
>> 999 #phy-cells = <0>;
>> 1000
>> 1001 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
>> 1002 clock-names = "pipe0";
>> 1003 clock-output-names = "pcie_0_pipe_clk_src";
>> 1004 #clock-cells = <0>;
>> 1005 };
992 }; 1006 };
993 1007
994 ufshc: ufshc@1da4000 { 1008 ufshc: ufshc@1da4000 {
995 compatible = "qcom,msm 1009 compatible = "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
996 reg = <0x01da4000 0x25 1010 reg = <0x01da4000 0x2500>;
997 interrupts = <GIC_SPI 1011 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
998 phys = <&ufsphy>; !! 1012 phys = <&ufsphy_lanes>;
999 phy-names = "ufsphy"; 1013 phy-names = "ufsphy";
1000 lanes-per-direction = 1014 lanes-per-direction = <2>;
1001 power-domains = <&gcc 1015 power-domains = <&gcc UFS_GDSC>;
1002 status = "disabled"; 1016 status = "disabled";
1003 #reset-cells = <1>; 1017 #reset-cells = <1>;
1004 1018
1005 clock-names = 1019 clock-names =
1006 "core_clk", 1020 "core_clk",
1007 "bus_aggr_clk 1021 "bus_aggr_clk",
1008 "iface_clk", 1022 "iface_clk",
1009 "core_clk_uni 1023 "core_clk_unipro",
1010 "ref_clk", 1024 "ref_clk",
1011 "tx_lane0_syn 1025 "tx_lane0_sync_clk",
1012 "rx_lane0_syn 1026 "rx_lane0_sync_clk",
1013 "rx_lane1_syn 1027 "rx_lane1_sync_clk";
1014 clocks = 1028 clocks =
1015 <&gcc GCC_UFS 1029 <&gcc GCC_UFS_AXI_CLK>,
1016 <&gcc GCC_AGG 1030 <&gcc GCC_AGGRE1_UFS_AXI_CLK>,
1017 <&gcc GCC_UFS 1031 <&gcc GCC_UFS_AHB_CLK>,
1018 <&gcc GCC_UFS 1032 <&gcc GCC_UFS_UNIPRO_CORE_CLK>,
1019 <&rpmcc RPM_S 1033 <&rpmcc RPM_SMD_LN_BB_CLK1>,
1020 <&gcc GCC_UFS 1034 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
1021 <&gcc GCC_UFS 1035 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>,
1022 <&gcc GCC_UFS 1036 <&gcc GCC_UFS_RX_SYMBOL_1_CLK>;
1023 freq-table-hz = 1037 freq-table-hz =
1024 <50000000 200 1038 <50000000 200000000>,
1025 <0 0>, 1039 <0 0>,
1026 <0 0>, 1040 <0 0>,
1027 <37500000 150 1041 <37500000 150000000>,
1028 <0 0>, 1042 <0 0>,
1029 <0 0>, 1043 <0 0>,
1030 <0 0>, 1044 <0 0>,
1031 <0 0>; 1045 <0 0>;
1032 1046
1033 resets = <&gcc GCC_UF 1047 resets = <&gcc GCC_UFS_BCR>;
1034 reset-names = "rst"; 1048 reset-names = "rst";
1035 }; 1049 };
1036 1050
1037 ufsphy: phy@1da7000 { 1051 ufsphy: phy@1da7000 {
1038 compatible = "qcom,ms 1052 compatible = "qcom,msm8998-qmp-ufs-phy";
1039 reg = <0x01da7000 0x1 !! 1053 reg = <0x01da7000 0x18c>;
>> 1054 #address-cells = <1>;
>> 1055 #size-cells = <1>;
>> 1056 status = "disabled";
>> 1057 ranges;
1040 1058
1041 clocks = <&rpmcc RPM_ !! 1059 clock-names =
1042 <&gcc GCC_UF !! 1060 "ref",
1043 <&gcc GCC_UF !! 1061 "ref_aux";
1044 clock-names = "ref", !! 1062 clocks =
1045 "ref_au !! 1063 <&gcc GCC_UFS_CLKREF_CLK>,
1046 "qref"; !! 1064 <&gcc GCC_UFS_PHY_AUX_CLK>;
1047 1065
1048 reset-names = "ufsphy 1066 reset-names = "ufsphy";
1049 resets = <&ufshc 0>; 1067 resets = <&ufshc 0>;
1050 1068
1051 #phy-cells = <0>; !! 1069 ufsphy_lanes: phy@1da7400 {
1052 status = "disabled"; !! 1070 reg = <0x01da7400 0x128>,
1053 }; !! 1071 <0x01da7600 0x1fc>,
1054 !! 1072 <0x01da7c00 0x1dc>,
1055 tcsr_mutex: hwlock@1f40000 { !! 1073 <0x01da7800 0x128>,
1056 compatible = "qcom,tc !! 1074 <0x01da7a00 0x1fc>;
1057 reg = <0x01f40000 0x2 !! 1075 #phy-cells = <0>;
1058 #hwlock-cells = <1>; !! 1076 };
1059 }; <<
1060 <<
1061 tcsr_regs_1: syscon@1f60000 { <<
1062 compatible = "qcom,ms <<
1063 reg = <0x01f60000 0x2 <<
1064 }; 1077 };
1065 1078
1066 tcsr_regs_2: syscon@1fc0000 { !! 1079 tcsr_mutex_regs: syscon@1f40000 {
1067 compatible = "qcom,ms !! 1080 compatible = "syscon";
1068 reg = <0x01fc0000 0x2 !! 1081 reg = <0x01f40000 0x40000>;
1069 }; 1082 };
1070 1083
1071 tlmm: pinctrl@3400000 { 1084 tlmm: pinctrl@3400000 {
1072 compatible = "qcom,ms 1085 compatible = "qcom,msm8998-pinctrl";
1073 reg = <0x03400000 0xc 1086 reg = <0x03400000 0xc00000>;
1074 interrupts = <GIC_SPI 1087 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1075 gpio-ranges = <&tlmm <<
1076 gpio-controller; 1088 gpio-controller;
1077 #gpio-cells = <2>; !! 1089 #gpio-cells = <0x2>;
1078 interrupt-controller; 1090 interrupt-controller;
1079 #interrupt-cells = <2 !! 1091 #interrupt-cells = <0x2>;
1080 1092
1081 sdc2_on: sdc2-on-stat !! 1093 sdc2_clk_on: sdc2_clk_on {
1082 clk-pins { !! 1094 config {
1083 pins 1095 pins = "sdc2_clk";
>> 1096 bias-disable;
1084 drive 1097 drive-strength = <16>;
>> 1098 };
>> 1099 };
>> 1100
>> 1101 sdc2_clk_off: sdc2_clk_off {
>> 1102 config {
>> 1103 pins = "sdc2_clk";
1085 bias- 1104 bias-disable;
>> 1105 drive-strength = <2>;
1086 }; 1106 };
>> 1107 };
1087 1108
1088 cmd-pins { !! 1109 sdc2_cmd_on: sdc2_cmd_on {
>> 1110 config {
1089 pins 1111 pins = "sdc2_cmd";
>> 1112 bias-pull-up;
1090 drive 1113 drive-strength = <10>;
>> 1114 };
>> 1115 };
>> 1116
>> 1117 sdc2_cmd_off: sdc2_cmd_off {
>> 1118 config {
>> 1119 pins = "sdc2_cmd";
1091 bias- 1120 bias-pull-up;
>> 1121 drive-strength = <2>;
1092 }; 1122 };
>> 1123 };
1093 1124
1094 data-pins { !! 1125 sdc2_data_on: sdc2_data_on {
>> 1126 config {
1095 pins 1127 pins = "sdc2_data";
1096 drive <<
1097 bias- 1128 bias-pull-up;
>> 1129 drive-strength = <10>;
1098 }; 1130 };
1099 }; 1131 };
1100 1132
1101 sdc2_off: sdc2-off-st !! 1133 sdc2_data_off: sdc2_data_off {
1102 clk-pins { !! 1134 config {
1103 pins !! 1135 pins = "sdc2_data";
>> 1136 bias-pull-up;
1104 drive 1137 drive-strength = <2>;
1105 bias- <<
1106 }; 1138 };
>> 1139 };
1107 1140
1108 cmd-pins { !! 1141 sdc2_cd_on: sdc2_cd_on {
1109 pins !! 1142 mux {
1110 drive !! 1143 pins = "gpio95";
1111 bias- !! 1144 function = "gpio";
1112 }; 1145 };
1113 1146
1114 data-pins { !! 1147 config {
1115 pins !! 1148 pins = "gpio95";
1116 drive <<
1117 bias- 1149 bias-pull-up;
>> 1150 drive-strength = <2>;
1118 }; 1151 };
1119 }; 1152 };
1120 1153
1121 sdc2_cd: sdc2-cd-stat !! 1154 sdc2_cd_off: sdc2_cd_off {
1122 pins = "gpio9 !! 1155 mux {
1123 function = "g !! 1156 pins = "gpio95";
1124 bias-pull-up; !! 1157 function = "gpio";
1125 drive-strengt !! 1158 };
>> 1159
>> 1160 config {
>> 1161 pins = "gpio95";
>> 1162 bias-pull-up;
>> 1163 drive-strength = <2>;
>> 1164 };
1126 }; 1165 };
1127 1166
1128 blsp1_uart3_on: blsp1 !! 1167 blsp1_uart3_on: blsp1_uart3_on {
1129 tx-pins { !! 1168 tx {
1130 pins 1169 pins = "gpio45";
1131 funct 1170 function = "blsp_uart3_a";
1132 drive 1171 drive-strength = <2>;
1133 bias- 1172 bias-disable;
1134 }; 1173 };
1135 1174
1136 rx-pins { !! 1175 rx {
1137 pins 1176 pins = "gpio46";
1138 funct 1177 function = "blsp_uart3_a";
1139 drive 1178 drive-strength = <2>;
1140 bias- 1179 bias-disable;
1141 }; 1180 };
1142 1181
1143 cts-pins { !! 1182 cts {
1144 pins 1183 pins = "gpio47";
1145 funct 1184 function = "blsp_uart3_a";
1146 drive 1185 drive-strength = <2>;
1147 bias- 1186 bias-disable;
1148 }; 1187 };
1149 1188
1150 rfr-pins { !! 1189 rfr {
1151 pins 1190 pins = "gpio48";
1152 funct 1191 function = "blsp_uart3_a";
1153 drive 1192 drive-strength = <2>;
1154 bias- 1193 bias-disable;
1155 }; 1194 };
1156 }; 1195 };
1157 1196
1158 blsp1_i2c1_default: b !! 1197 blsp1_i2c1_default: blsp1-i2c1-default {
1159 pins = "gpio2 1198 pins = "gpio2", "gpio3";
1160 function = "b 1199 function = "blsp_i2c1";
1161 drive-strengt 1200 drive-strength = <2>;
1162 bias-disable; 1201 bias-disable;
1163 }; 1202 };
1164 1203
1165 blsp1_i2c1_sleep: bls !! 1204 blsp1_i2c1_sleep: blsp1-i2c1-sleep {
1166 pins = "gpio2 1205 pins = "gpio2", "gpio3";
1167 function = "b 1206 function = "blsp_i2c1";
1168 drive-strengt 1207 drive-strength = <2>;
1169 bias-pull-up; 1208 bias-pull-up;
1170 }; 1209 };
1171 1210
1172 blsp1_i2c2_default: b !! 1211 blsp1_i2c2_default: blsp1-i2c2-default {
1173 pins = "gpio3 1212 pins = "gpio32", "gpio33";
1174 function = "b 1213 function = "blsp_i2c2";
1175 drive-strengt 1214 drive-strength = <2>;
1176 bias-disable; 1215 bias-disable;
1177 }; 1216 };
1178 1217
1179 blsp1_i2c2_sleep: bls !! 1218 blsp1_i2c2_sleep: blsp1-i2c2-sleep {
1180 pins = "gpio3 1219 pins = "gpio32", "gpio33";
1181 function = "b 1220 function = "blsp_i2c2";
1182 drive-strengt 1221 drive-strength = <2>;
1183 bias-pull-up; 1222 bias-pull-up;
1184 }; 1223 };
1185 1224
1186 blsp1_i2c3_default: b !! 1225 blsp1_i2c3_default: blsp1-i2c3-default {
1187 pins = "gpio4 1226 pins = "gpio47", "gpio48";
1188 function = "b 1227 function = "blsp_i2c3";
1189 drive-strengt 1228 drive-strength = <2>;
1190 bias-disable; 1229 bias-disable;
1191 }; 1230 };
1192 1231
1193 blsp1_i2c3_sleep: bls !! 1232 blsp1_i2c3_sleep: blsp1-i2c3-sleep {
1194 pins = "gpio4 1233 pins = "gpio47", "gpio48";
1195 function = "b 1234 function = "blsp_i2c3";
1196 drive-strengt 1235 drive-strength = <2>;
1197 bias-pull-up; 1236 bias-pull-up;
1198 }; 1237 };
1199 1238
1200 blsp1_i2c4_default: b !! 1239 blsp1_i2c4_default: blsp1-i2c4-default {
1201 pins = "gpio1 1240 pins = "gpio10", "gpio11";
1202 function = "b 1241 function = "blsp_i2c4";
1203 drive-strengt 1242 drive-strength = <2>;
1204 bias-disable; 1243 bias-disable;
1205 }; 1244 };
1206 1245
1207 blsp1_i2c4_sleep: bls !! 1246 blsp1_i2c4_sleep: blsp1-i2c4-sleep {
1208 pins = "gpio1 1247 pins = "gpio10", "gpio11";
1209 function = "b 1248 function = "blsp_i2c4";
1210 drive-strengt 1249 drive-strength = <2>;
1211 bias-pull-up; 1250 bias-pull-up;
1212 }; 1251 };
1213 1252
1214 blsp1_i2c5_default: b !! 1253 blsp1_i2c5_default: blsp1-i2c5-default {
1215 pins = "gpio8 1254 pins = "gpio87", "gpio88";
1216 function = "b 1255 function = "blsp_i2c5";
1217 drive-strengt 1256 drive-strength = <2>;
1218 bias-disable; 1257 bias-disable;
1219 }; 1258 };
1220 1259
1221 blsp1_i2c5_sleep: bls !! 1260 blsp1_i2c5_sleep: blsp1-i2c5-sleep {
1222 pins = "gpio8 1261 pins = "gpio87", "gpio88";
1223 function = "b 1262 function = "blsp_i2c5";
1224 drive-strengt 1263 drive-strength = <2>;
1225 bias-pull-up; 1264 bias-pull-up;
1226 }; 1265 };
1227 1266
1228 blsp1_i2c6_default: b !! 1267 blsp1_i2c6_default: blsp1-i2c6-default {
1229 pins = "gpio4 1268 pins = "gpio43", "gpio44";
1230 function = "b 1269 function = "blsp_i2c6";
1231 drive-strengt 1270 drive-strength = <2>;
1232 bias-disable; 1271 bias-disable;
1233 }; 1272 };
1234 1273
1235 blsp1_i2c6_sleep: bls !! 1274 blsp1_i2c6_sleep: blsp1-i2c6-sleep {
1236 pins = "gpio4 1275 pins = "gpio43", "gpio44";
1237 function = "b 1276 function = "blsp_i2c6";
1238 drive-strengt 1277 drive-strength = <2>;
1239 bias-pull-up; 1278 bias-pull-up;
1240 }; 1279 };
1241 <<
1242 blsp1_spi_b_default: <<
1243 pins = "gpio2 <<
1244 function = "b <<
1245 drive-strengt <<
1246 bias-disable; <<
1247 }; <<
1248 <<
1249 blsp1_spi1_default: b <<
1250 pins = "gpio0 <<
1251 function = "b <<
1252 drive-strengt <<
1253 bias-disable; <<
1254 }; <<
1255 <<
1256 blsp1_spi2_default: b <<
1257 pins = "gpio3 <<
1258 function = "b <<
1259 drive-strengt <<
1260 bias-disable; <<
1261 }; <<
1262 <<
1263 blsp1_spi3_default: b <<
1264 pins = "gpio4 <<
1265 function = "b <<
1266 drive-strengt <<
1267 bias-disable; <<
1268 }; <<
1269 <<
1270 blsp1_spi4_default: b <<
1271 pins = "gpio8 <<
1272 function = "b <<
1273 drive-strengt <<
1274 bias-disable; <<
1275 }; <<
1276 <<
1277 blsp1_spi5_default: b <<
1278 pins = "gpio8 <<
1279 function = "b <<
1280 drive-strengt <<
1281 bias-disable; <<
1282 }; <<
1283 <<
1284 blsp1_spi6_default: b <<
1285 pins = "gpio4 <<
1286 function = "b <<
1287 drive-strengt <<
1288 bias-disable; <<
1289 }; <<
1290 <<
1291 <<
1292 /* 6 interfaces per Q 1280 /* 6 interfaces per QUP, BLSP2 indexes are numbered (n)+6 */
1293 blsp2_i2c1_default: b !! 1281 blsp2_i2c1_default: blsp2-i2c1-default {
1294 pins = "gpio5 1282 pins = "gpio55", "gpio56";
1295 function = "b 1283 function = "blsp_i2c7";
1296 drive-strengt 1284 drive-strength = <2>;
1297 bias-disable; 1285 bias-disable;
1298 }; 1286 };
1299 1287
1300 blsp2_i2c1_sleep: bls !! 1288 blsp2_i2c1_sleep: blsp2-i2c1-sleep {
1301 pins = "gpio5 1289 pins = "gpio55", "gpio56";
1302 function = "b 1290 function = "blsp_i2c7";
1303 drive-strengt 1291 drive-strength = <2>;
1304 bias-pull-up; 1292 bias-pull-up;
1305 }; 1293 };
1306 1294
1307 blsp2_i2c2_default: b !! 1295 blsp2_i2c2_default: blsp2-i2c2-default {
1308 pins = "gpio6 1296 pins = "gpio6", "gpio7";
1309 function = "b 1297 function = "blsp_i2c8";
1310 drive-strengt 1298 drive-strength = <2>;
1311 bias-disable; 1299 bias-disable;
1312 }; 1300 };
1313 1301
1314 blsp2_i2c2_sleep: bls !! 1302 blsp2_i2c2_sleep: blsp2-i2c2-sleep {
1315 pins = "gpio6 1303 pins = "gpio6", "gpio7";
1316 function = "b 1304 function = "blsp_i2c8";
1317 drive-strengt 1305 drive-strength = <2>;
1318 bias-pull-up; 1306 bias-pull-up;
1319 }; 1307 };
1320 1308
1321 blsp2_i2c3_default: b !! 1309 blsp2_i2c3_default: blsp2-i2c3-default {
1322 pins = "gpio5 1310 pins = "gpio51", "gpio52";
1323 function = "b 1311 function = "blsp_i2c9";
1324 drive-strengt 1312 drive-strength = <2>;
1325 bias-disable; 1313 bias-disable;
1326 }; 1314 };
1327 1315
1328 blsp2_i2c3_sleep: bls !! 1316 blsp2_i2c3_sleep: blsp2-i2c3-sleep {
1329 pins = "gpio5 1317 pins = "gpio51", "gpio52";
1330 function = "b 1318 function = "blsp_i2c9";
1331 drive-strengt 1319 drive-strength = <2>;
1332 bias-pull-up; 1320 bias-pull-up;
1333 }; 1321 };
1334 1322
1335 blsp2_i2c4_default: b !! 1323 blsp2_i2c4_default: blsp2-i2c4-default {
1336 pins = "gpio6 1324 pins = "gpio67", "gpio68";
1337 function = "b 1325 function = "blsp_i2c10";
1338 drive-strengt 1326 drive-strength = <2>;
1339 bias-disable; 1327 bias-disable;
1340 }; 1328 };
1341 1329
1342 blsp2_i2c4_sleep: bls !! 1330 blsp2_i2c4_sleep: blsp2-i2c4-sleep {
1343 pins = "gpio6 1331 pins = "gpio67", "gpio68";
1344 function = "b 1332 function = "blsp_i2c10";
1345 drive-strengt 1333 drive-strength = <2>;
1346 bias-pull-up; 1334 bias-pull-up;
1347 }; 1335 };
1348 1336
1349 blsp2_i2c5_default: b !! 1337 blsp2_i2c5_default: blsp2-i2c5-default {
1350 pins = "gpio6 1338 pins = "gpio60", "gpio61";
1351 function = "b 1339 function = "blsp_i2c11";
1352 drive-strengt 1340 drive-strength = <2>;
1353 bias-disable; 1341 bias-disable;
1354 }; 1342 };
1355 1343
1356 blsp2_i2c5_sleep: bls !! 1344 blsp2_i2c5_sleep: blsp2-i2c5-sleep {
1357 pins = "gpio6 1345 pins = "gpio60", "gpio61";
1358 function = "b 1346 function = "blsp_i2c11";
1359 drive-strengt 1347 drive-strength = <2>;
1360 bias-pull-up; 1348 bias-pull-up;
1361 }; 1349 };
1362 1350
1363 blsp2_i2c6_default: b !! 1351 blsp2_i2c6_default: blsp2-i2c6-default {
1364 pins = "gpio8 1352 pins = "gpio83", "gpio84";
1365 function = "b 1353 function = "blsp_i2c12";
1366 drive-strengt 1354 drive-strength = <2>;
1367 bias-disable; 1355 bias-disable;
1368 }; 1356 };
1369 1357
1370 blsp2_i2c6_sleep: bls !! 1358 blsp2_i2c6_sleep: blsp2-i2c6-sleep {
1371 pins = "gpio8 1359 pins = "gpio83", "gpio84";
1372 function = "b 1360 function = "blsp_i2c12";
1373 drive-strengt 1361 drive-strength = <2>;
1374 bias-pull-up; 1362 bias-pull-up;
1375 }; 1363 };
1376 <<
1377 blsp2_spi1_default: b <<
1378 pins = "gpio5 <<
1379 function = "b <<
1380 drive-strengt <<
1381 bias-disable; <<
1382 }; <<
1383 <<
1384 blsp2_spi2_default: b <<
1385 pins = "gpio4 <<
1386 function = "b <<
1387 drive-strengt <<
1388 bias-disable; <<
1389 }; <<
1390 <<
1391 blsp2_spi3_default: b <<
1392 pins = "gpio4 <<
1393 function = "b <<
1394 drive-strengt <<
1395 bias-disable; <<
1396 }; <<
1397 <<
1398 blsp2_spi4_default: b <<
1399 pins = "gpio6 <<
1400 function = "b <<
1401 drive-strengt <<
1402 bias-disable; <<
1403 }; <<
1404 <<
1405 blsp2_spi5_default: b <<
1406 pins = "gpio5 <<
1407 function = "b <<
1408 drive-strengt <<
1409 bias-disable; <<
1410 }; <<
1411 <<
1412 blsp2_spi6_default: b <<
1413 pins = "gpio8 <<
1414 function = "b <<
1415 drive-strengt <<
1416 bias-disable; <<
1417 }; <<
1418 }; 1364 };
1419 1365
1420 remoteproc_mss: remoteproc@40 1366 remoteproc_mss: remoteproc@4080000 {
1421 compatible = "qcom,ms 1367 compatible = "qcom,msm8998-mss-pil";
1422 reg = <0x04080000 0x1 1368 reg = <0x04080000 0x100>, <0x04180000 0x20>;
1423 reg-names = "qdsp6", 1369 reg-names = "qdsp6", "rmb";
1424 1370
1425 interrupts-extended = 1371 interrupts-extended =
1426 <&intc GIC_SP 1372 <&intc GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
1427 <&modem_smp2p 1373 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1428 <&modem_smp2p 1374 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1429 <&modem_smp2p 1375 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1430 <&modem_smp2p 1376 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
1431 <&modem_smp2p 1377 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
1432 interrupt-names = "wd 1378 interrupt-names = "wdog", "fatal", "ready",
1433 "ha 1379 "handover", "stop-ack",
1434 "sh 1380 "shutdown-ack";
1435 1381
1436 clocks = <&gcc GCC_MS 1382 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
1437 <&gcc GCC_BI 1383 <&gcc GCC_BIMC_MSS_Q6_AXI_CLK>,
1438 <&gcc GCC_BO 1384 <&gcc GCC_BOOT_ROM_AHB_CLK>,
1439 <&gcc GCC_MS 1385 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
1440 <&gcc GCC_MS 1386 <&gcc GCC_MSS_SNOC_AXI_CLK>,
1441 <&gcc GCC_MS 1387 <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>,
1442 <&rpmcc RPM_ 1388 <&rpmcc RPM_SMD_QDSS_CLK>,
1443 <&rpmcc RPM_ 1389 <&rpmcc RPM_SMD_XO_CLK_SRC>;
1444 clock-names = "iface" 1390 clock-names = "iface", "bus", "mem", "gpll0_mss",
1445 "snoc_a 1391 "snoc_axi", "mnoc_axi", "qdss", "xo";
1446 1392
1447 qcom,smem-states = <& 1393 qcom,smem-states = <&modem_smp2p_out 0>;
1448 qcom,smem-state-names 1394 qcom,smem-state-names = "stop";
1449 1395
1450 resets = <&gcc GCC_MS 1396 resets = <&gcc GCC_MSS_RESTART>;
1451 reset-names = "mss_re 1397 reset-names = "mss_restart";
1452 1398
1453 qcom,halt-regs = <&tc !! 1399 qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
1454 1400
1455 power-domains = <&rpm 1401 power-domains = <&rpmpd MSM8998_VDDCX>,
1456 <&rpm 1402 <&rpmpd MSM8998_VDDMX>;
1457 power-domain-names = 1403 power-domain-names = "cx", "mx";
1458 1404
1459 status = "disabled"; 1405 status = "disabled";
1460 1406
1461 mba { 1407 mba {
1462 memory-region 1408 memory-region = <&mba_mem>;
1463 }; 1409 };
1464 1410
1465 mpss { 1411 mpss {
1466 memory-region 1412 memory-region = <&mpss_mem>;
1467 }; 1413 };
1468 1414
1469 metadata { <<
1470 memory-region <<
1471 }; <<
1472 <<
1473 glink-edge { 1415 glink-edge {
1474 interrupts = 1416 interrupts = <GIC_SPI 452 IRQ_TYPE_EDGE_RISING>;
1475 label = "mode 1417 label = "modem";
1476 qcom,remote-p 1418 qcom,remote-pid = <1>;
1477 mboxes = <&ap 1419 mboxes = <&apcs_glb 15>;
1478 }; 1420 };
1479 }; 1421 };
1480 1422
1481 adreno_gpu: gpu@5000000 { <<
1482 compatible = "qcom,ad <<
1483 reg = <0x05000000 0x4 <<
1484 reg-names = "kgsl_3d0 <<
1485 <<
1486 clocks = <&gcc GCC_GP <<
1487 <&gpucc RBBMT <<
1488 <&gcc GCC_BIM <<
1489 <&gcc GCC_GPU <<
1490 <&gpucc RBCPR <<
1491 <&gpucc GFX3D <<
1492 clock-names = "iface" <<
1493 "rbbmtimer", <<
1494 "mem", <<
1495 "mem_iface", <<
1496 "rbcpr", <<
1497 "core"; <<
1498 <<
1499 interrupts = <GIC_SPI <<
1500 iommus = <&adreno_smm <<
1501 operating-points-v2 = <<
1502 power-domains = <&rpm <<
1503 status = "disabled"; <<
1504 <<
1505 gpu_opp_table: opp-ta <<
1506 compatible = <<
1507 opp-710000097 <<
1508 opp-h <<
1509 opp-l <<
1510 opp-s <<
1511 }; <<
1512 <<
1513 opp-670000048 <<
1514 opp-h <<
1515 opp-l <<
1516 opp-s <<
1517 }; <<
1518 <<
1519 opp-596000097 <<
1520 opp-h <<
1521 opp-l <<
1522 opp-s <<
1523 }; <<
1524 <<
1525 opp-515000097 <<
1526 opp-h <<
1527 opp-l <<
1528 opp-s <<
1529 }; <<
1530 <<
1531 opp-414000000 <<
1532 opp-h <<
1533 opp-l <<
1534 opp-s <<
1535 }; <<
1536 <<
1537 opp-342000000 <<
1538 opp-h <<
1539 opp-l <<
1540 opp-s <<
1541 }; <<
1542 <<
1543 opp-257000000 <<
1544 opp-h <<
1545 opp-l <<
1546 opp-s <<
1547 }; <<
1548 }; <<
1549 }; <<
1550 <<
1551 adreno_smmu: iommu@5040000 { <<
1552 compatible = "qcom,ms <<
1553 reg = <0x05040000 0x1 <<
1554 clocks = <&gcc GCC_GP <<
1555 <&gcc GCC_BI <<
1556 <&gcc GCC_GP <<
1557 clock-names = "iface" <<
1558 <<
1559 #global-interrupts = <<
1560 #iommu-cells = <1>; <<
1561 interrupts = <<
1562 <GIC_SPI 329 <<
1563 <GIC_SPI 330 <<
1564 <GIC_SPI 331 <<
1565 /* <<
1566 * GPU-GX GDSC's pare <<
1567 * GPU-CX for SMMU bu <<
1568 * Contemporarily, we <<
1569 * domain in the Adre <<
1570 * Enable GPU CX/GX G <<
1571 * SoC VDDMX RPM Powe <<
1572 */ <<
1573 power-domains = <&gpu <<
1574 }; <<
1575 <<
1576 gpucc: clock-controller@50650 1423 gpucc: clock-controller@5065000 {
1577 compatible = "qcom,ms 1424 compatible = "qcom,msm8998-gpucc";
1578 #clock-cells = <1>; 1425 #clock-cells = <1>;
1579 #reset-cells = <1>; 1426 #reset-cells = <1>;
1580 #power-domain-cells = 1427 #power-domain-cells = <1>;
1581 reg = <0x05065000 0x9 1428 reg = <0x05065000 0x9000>;
1582 1429
1583 clocks = <&rpmcc RPM_ 1430 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1584 <&gcc GCC_GP !! 1431 <&gcc GPLL0_OUT_MAIN>;
1585 clock-names = "xo", 1432 clock-names = "xo",
1586 "gpll0" 1433 "gpll0";
1587 }; 1434 };
1588 1435
1589 lpass_q6_smmu: iommu@5100000 <<
1590 compatible = "qcom,ms <<
1591 reg = <0x05100000 0x4 <<
1592 clocks = <&gcc HLOS1_ <<
1593 clock-names = "bus"; <<
1594 <<
1595 #global-interrupts = <<
1596 #iommu-cells = <1>; <<
1597 interrupts = <<
1598 <GIC_SPI 226 <<
1599 <GIC_SPI 393 <<
1600 <GIC_SPI 394 <<
1601 <GIC_SPI 395 <<
1602 <GIC_SPI 396 <<
1603 <GIC_SPI 397 <<
1604 <GIC_SPI 398 <<
1605 <GIC_SPI 399 <<
1606 <GIC_SPI 400 <<
1607 <GIC_SPI 401 <<
1608 <GIC_SPI 402 <<
1609 <GIC_SPI 403 <<
1610 <GIC_SPI 137 <<
1611 <<
1612 power-domains = <&gcc <<
1613 status = "disabled"; <<
1614 }; <<
1615 <<
1616 remoteproc_slpi: remoteproc@5 1436 remoteproc_slpi: remoteproc@5800000 {
1617 compatible = "qcom,ms 1437 compatible = "qcom,msm8998-slpi-pas";
1618 reg = <0x05800000 0x4 1438 reg = <0x05800000 0x4040>;
1619 1439
1620 interrupts-extended = 1440 interrupts-extended = <&intc GIC_SPI 390 IRQ_TYPE_EDGE_RISING>,
1621 1441 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1622 1442 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1623 1443 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1624 1444 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1625 interrupt-names = "wd 1445 interrupt-names = "wdog", "fatal", "ready",
1626 "ha 1446 "handover", "stop-ack";
1627 1447
1628 px-supply = <&vreg_lv 1448 px-supply = <&vreg_lvs2a_1p8>;
1629 1449
1630 clocks = <&rpmcc RPM_ !! 1450 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1631 clock-names = "xo"; !! 1451 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
>> 1452 clock-names = "xo", "aggre2";
1632 1453
1633 memory-region = <&slp 1454 memory-region = <&slpi_mem>;
1634 1455
1635 qcom,smem-states = <& 1456 qcom,smem-states = <&slpi_smp2p_out 0>;
1636 qcom,smem-state-names 1457 qcom,smem-state-names = "stop";
1637 1458
1638 power-domains = <&rpm 1459 power-domains = <&rpmpd MSM8998_SSCCX>;
1639 power-domain-names = 1460 power-domain-names = "ssc_cx";
1640 1461
1641 status = "disabled"; 1462 status = "disabled";
1642 1463
1643 glink-edge { 1464 glink-edge {
1644 interrupts = 1465 interrupts = <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>;
1645 label = "dsps 1466 label = "dsps";
1646 qcom,remote-p 1467 qcom,remote-pid = <3>;
1647 mboxes = <&ap 1468 mboxes = <&apcs_glb 27>;
1648 }; 1469 };
1649 }; 1470 };
1650 1471
1651 stm: stm@6002000 { 1472 stm: stm@6002000 {
1652 compatible = "arm,cor 1473 compatible = "arm,coresight-stm", "arm,primecell";
1653 reg = <0x06002000 0x1 1474 reg = <0x06002000 0x1000>,
1654 <0x16280000 0x1 1475 <0x16280000 0x180000>;
1655 reg-names = "stm-base 1476 reg-names = "stm-base", "stm-stimulus-base";
1656 status = "disabled"; 1477 status = "disabled";
1657 1478
1658 clocks = <&rpmcc RPM_ 1479 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1659 clock-names = "apb_pc 1480 clock-names = "apb_pclk", "atclk";
1660 1481
1661 out-ports { 1482 out-ports {
1662 port { 1483 port {
1663 stm_o 1484 stm_out: endpoint {
1664 1485 remote-endpoint = <&funnel0_in7>;
1665 }; 1486 };
1666 }; 1487 };
1667 }; 1488 };
1668 }; 1489 };
1669 1490
1670 funnel1: funnel@6041000 { 1491 funnel1: funnel@6041000 {
1671 compatible = "arm,cor 1492 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1672 reg = <0x06041000 0x1 1493 reg = <0x06041000 0x1000>;
1673 status = "disabled"; 1494 status = "disabled";
1674 1495
1675 clocks = <&rpmcc RPM_ 1496 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1676 clock-names = "apb_pc 1497 clock-names = "apb_pclk", "atclk";
1677 1498
1678 out-ports { 1499 out-ports {
1679 port { 1500 port {
1680 funne 1501 funnel0_out: endpoint {
1681 1502 remote-endpoint =
1682 1503 <&merge_funnel_in0>;
1683 }; 1504 };
1684 }; 1505 };
1685 }; 1506 };
1686 1507
1687 in-ports { 1508 in-ports {
1688 #address-cell 1509 #address-cells = <1>;
1689 #size-cells = 1510 #size-cells = <0>;
1690 1511
1691 port@7 { 1512 port@7 {
1692 reg = 1513 reg = <7>;
1693 funne 1514 funnel0_in7: endpoint {
1694 1515 remote-endpoint = <&stm_out>;
1695 }; 1516 };
1696 }; 1517 };
1697 }; 1518 };
1698 }; 1519 };
1699 1520
1700 funnel2: funnel@6042000 { 1521 funnel2: funnel@6042000 {
1701 compatible = "arm,cor 1522 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1702 reg = <0x06042000 0x1 1523 reg = <0x06042000 0x1000>;
1703 status = "disabled"; 1524 status = "disabled";
1704 1525
1705 clocks = <&rpmcc RPM_ 1526 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1706 clock-names = "apb_pc 1527 clock-names = "apb_pclk", "atclk";
1707 1528
1708 out-ports { 1529 out-ports {
1709 port { 1530 port {
1710 funne 1531 funnel1_out: endpoint {
1711 1532 remote-endpoint =
1712 1533 <&merge_funnel_in1>;
1713 }; 1534 };
1714 }; 1535 };
1715 }; 1536 };
1716 1537
1717 in-ports { 1538 in-ports {
1718 #address-cell 1539 #address-cells = <1>;
1719 #size-cells = 1540 #size-cells = <0>;
1720 1541
1721 port@6 { 1542 port@6 {
1722 reg = 1543 reg = <6>;
1723 funne 1544 funnel1_in6: endpoint {
1724 1545 remote-endpoint =
1725 1546 <&apss_merge_funnel_out>;
1726 }; 1547 };
1727 }; 1548 };
1728 }; 1549 };
1729 }; 1550 };
1730 1551
1731 funnel3: funnel@6045000 { 1552 funnel3: funnel@6045000 {
1732 compatible = "arm,cor 1553 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1733 reg = <0x06045000 0x1 1554 reg = <0x06045000 0x1000>;
1734 status = "disabled"; 1555 status = "disabled";
1735 1556
1736 clocks = <&rpmcc RPM_ 1557 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1737 clock-names = "apb_pc 1558 clock-names = "apb_pclk", "atclk";
1738 1559
1739 out-ports { 1560 out-ports {
1740 port { 1561 port {
1741 merge 1562 merge_funnel_out: endpoint {
1742 1563 remote-endpoint =
1743 1564 <&etf_in>;
1744 }; 1565 };
1745 }; 1566 };
1746 }; 1567 };
1747 1568
1748 in-ports { 1569 in-ports {
1749 #address-cell 1570 #address-cells = <1>;
1750 #size-cells = 1571 #size-cells = <0>;
1751 1572
1752 port@0 { 1573 port@0 {
1753 reg = 1574 reg = <0>;
1754 merge 1575 merge_funnel_in0: endpoint {
1755 1576 remote-endpoint =
1756 1577 <&funnel0_out>;
1757 }; 1578 };
1758 }; 1579 };
1759 1580
1760 port@1 { 1581 port@1 {
1761 reg = 1582 reg = <1>;
1762 merge 1583 merge_funnel_in1: endpoint {
1763 1584 remote-endpoint =
1764 1585 <&funnel1_out>;
1765 }; 1586 };
1766 }; 1587 };
1767 }; 1588 };
1768 }; 1589 };
1769 1590
1770 replicator1: replicator@60460 1591 replicator1: replicator@6046000 {
1771 compatible = "arm,cor 1592 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
1772 reg = <0x06046000 0x1 1593 reg = <0x06046000 0x1000>;
1773 status = "disabled"; 1594 status = "disabled";
1774 1595
1775 clocks = <&rpmcc RPM_ 1596 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1776 clock-names = "apb_pc 1597 clock-names = "apb_pclk", "atclk";
1777 1598
1778 out-ports { 1599 out-ports {
1779 port { 1600 port {
1780 repli 1601 replicator_out: endpoint {
1781 1602 remote-endpoint = <&etr_in>;
1782 }; 1603 };
1783 }; 1604 };
1784 }; 1605 };
1785 1606
1786 in-ports { 1607 in-ports {
1787 port { 1608 port {
1788 repli 1609 replicator_in: endpoint {
1789 1610 remote-endpoint = <&etf_out>;
1790 }; 1611 };
1791 }; 1612 };
1792 }; 1613 };
1793 }; 1614 };
1794 1615
1795 etf: etf@6047000 { 1616 etf: etf@6047000 {
1796 compatible = "arm,cor 1617 compatible = "arm,coresight-tmc", "arm,primecell";
1797 reg = <0x06047000 0x1 1618 reg = <0x06047000 0x1000>;
1798 status = "disabled"; 1619 status = "disabled";
1799 1620
1800 clocks = <&rpmcc RPM_ 1621 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1801 clock-names = "apb_pc 1622 clock-names = "apb_pclk", "atclk";
1802 1623
1803 out-ports { 1624 out-ports {
1804 port { 1625 port {
1805 etf_o 1626 etf_out: endpoint {
1806 1627 remote-endpoint =
1807 1628 <&replicator_in>;
1808 }; 1629 };
1809 }; 1630 };
1810 }; 1631 };
1811 1632
1812 in-ports { 1633 in-ports {
1813 port { 1634 port {
1814 etf_i 1635 etf_in: endpoint {
1815 1636 remote-endpoint =
1816 1637 <&merge_funnel_out>;
1817 }; 1638 };
1818 }; 1639 };
1819 }; 1640 };
1820 }; 1641 };
1821 1642
1822 etr: etr@6048000 { 1643 etr: etr@6048000 {
1823 compatible = "arm,cor 1644 compatible = "arm,coresight-tmc", "arm,primecell";
1824 reg = <0x06048000 0x1 1645 reg = <0x06048000 0x1000>;
1825 status = "disabled"; 1646 status = "disabled";
1826 1647
1827 clocks = <&rpmcc RPM_ 1648 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1828 clock-names = "apb_pc 1649 clock-names = "apb_pclk", "atclk";
1829 arm,scatter-gather; 1650 arm,scatter-gather;
1830 1651
1831 in-ports { 1652 in-ports {
1832 port { 1653 port {
1833 etr_i 1654 etr_in: endpoint {
1834 1655 remote-endpoint =
1835 1656 <&replicator_out>;
1836 }; 1657 };
1837 }; 1658 };
1838 }; 1659 };
1839 }; 1660 };
1840 1661
1841 etm1: etm@7840000 { 1662 etm1: etm@7840000 {
1842 compatible = "arm,cor 1663 compatible = "arm,coresight-etm4x", "arm,primecell";
1843 reg = <0x07840000 0x1 1664 reg = <0x07840000 0x1000>;
1844 status = "disabled"; 1665 status = "disabled";
1845 1666
1846 clocks = <&rpmcc RPM_ 1667 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1847 clock-names = "apb_pc 1668 clock-names = "apb_pclk", "atclk";
1848 1669
1849 cpu = <&CPU0>; 1670 cpu = <&CPU0>;
1850 1671
1851 out-ports { 1672 out-ports {
1852 port { 1673 port {
1853 etm0_ 1674 etm0_out: endpoint {
1854 1675 remote-endpoint =
1855 1676 <&apss_funnel_in0>;
1856 }; 1677 };
1857 }; 1678 };
1858 }; 1679 };
1859 }; 1680 };
1860 1681
1861 etm2: etm@7940000 { 1682 etm2: etm@7940000 {
1862 compatible = "arm,cor 1683 compatible = "arm,coresight-etm4x", "arm,primecell";
1863 reg = <0x07940000 0x1 1684 reg = <0x07940000 0x1000>;
1864 status = "disabled"; 1685 status = "disabled";
1865 1686
1866 clocks = <&rpmcc RPM_ 1687 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1867 clock-names = "apb_pc 1688 clock-names = "apb_pclk", "atclk";
1868 1689
1869 cpu = <&CPU1>; 1690 cpu = <&CPU1>;
1870 1691
1871 out-ports { 1692 out-ports {
1872 port { 1693 port {
1873 etm1_ 1694 etm1_out: endpoint {
1874 1695 remote-endpoint =
1875 1696 <&apss_funnel_in1>;
1876 }; 1697 };
1877 }; 1698 };
1878 }; 1699 };
1879 }; 1700 };
1880 1701
1881 etm3: etm@7a40000 { 1702 etm3: etm@7a40000 {
1882 compatible = "arm,cor 1703 compatible = "arm,coresight-etm4x", "arm,primecell";
1883 reg = <0x07a40000 0x1 1704 reg = <0x07a40000 0x1000>;
1884 status = "disabled"; 1705 status = "disabled";
1885 1706
1886 clocks = <&rpmcc RPM_ 1707 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1887 clock-names = "apb_pc 1708 clock-names = "apb_pclk", "atclk";
1888 1709
1889 cpu = <&CPU2>; 1710 cpu = <&CPU2>;
1890 1711
1891 out-ports { 1712 out-ports {
1892 port { 1713 port {
1893 etm2_ 1714 etm2_out: endpoint {
1894 1715 remote-endpoint =
1895 1716 <&apss_funnel_in2>;
1896 }; 1717 };
1897 }; 1718 };
1898 }; 1719 };
1899 }; 1720 };
1900 1721
1901 etm4: etm@7b40000 { 1722 etm4: etm@7b40000 {
1902 compatible = "arm,cor 1723 compatible = "arm,coresight-etm4x", "arm,primecell";
1903 reg = <0x07b40000 0x1 1724 reg = <0x07b40000 0x1000>;
1904 status = "disabled"; 1725 status = "disabled";
1905 1726
1906 clocks = <&rpmcc RPM_ 1727 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1907 clock-names = "apb_pc 1728 clock-names = "apb_pclk", "atclk";
1908 1729
1909 cpu = <&CPU3>; 1730 cpu = <&CPU3>;
1910 1731
1911 out-ports { 1732 out-ports {
1912 port { 1733 port {
1913 etm3_ 1734 etm3_out: endpoint {
1914 1735 remote-endpoint =
1915 1736 <&apss_funnel_in3>;
1916 }; 1737 };
1917 }; 1738 };
1918 }; 1739 };
1919 }; 1740 };
1920 1741
1921 funnel4: funnel@7b60000 { /* 1742 funnel4: funnel@7b60000 { /* APSS Funnel */
1922 compatible = "arm,cor 1743 compatible = "arm,coresight-etm4x", "arm,primecell";
1923 reg = <0x07b60000 0x1 1744 reg = <0x07b60000 0x1000>;
1924 status = "disabled"; 1745 status = "disabled";
1925 1746
1926 clocks = <&rpmcc RPM_ 1747 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1927 clock-names = "apb_pc 1748 clock-names = "apb_pclk", "atclk";
1928 1749
1929 out-ports { 1750 out-ports {
1930 port { 1751 port {
1931 apss_ 1752 apss_funnel_out: endpoint {
1932 1753 remote-endpoint =
1933 1754 <&apss_merge_funnel_in>;
1934 }; 1755 };
1935 }; 1756 };
1936 }; 1757 };
1937 1758
1938 in-ports { 1759 in-ports {
1939 #address-cell 1760 #address-cells = <1>;
1940 #size-cells = 1761 #size-cells = <0>;
1941 1762
1942 port@0 { 1763 port@0 {
1943 reg = 1764 reg = <0>;
1944 apss_ 1765 apss_funnel_in0: endpoint {
1945 1766 remote-endpoint =
1946 1767 <&etm0_out>;
1947 }; 1768 };
1948 }; 1769 };
1949 1770
1950 port@1 { 1771 port@1 {
1951 reg = 1772 reg = <1>;
1952 apss_ 1773 apss_funnel_in1: endpoint {
1953 1774 remote-endpoint =
1954 1775 <&etm1_out>;
1955 }; 1776 };
1956 }; 1777 };
1957 1778
1958 port@2 { 1779 port@2 {
1959 reg = 1780 reg = <2>;
1960 apss_ 1781 apss_funnel_in2: endpoint {
1961 1782 remote-endpoint =
1962 1783 <&etm2_out>;
1963 }; 1784 };
1964 }; 1785 };
1965 1786
1966 port@3 { 1787 port@3 {
1967 reg = 1788 reg = <3>;
1968 apss_ 1789 apss_funnel_in3: endpoint {
1969 1790 remote-endpoint =
1970 1791 <&etm3_out>;
1971 }; 1792 };
1972 }; 1793 };
1973 1794
1974 port@4 { 1795 port@4 {
1975 reg = 1796 reg = <4>;
1976 apss_ 1797 apss_funnel_in4: endpoint {
1977 1798 remote-endpoint =
1978 1799 <&etm4_out>;
1979 }; 1800 };
1980 }; 1801 };
1981 1802
1982 port@5 { 1803 port@5 {
1983 reg = 1804 reg = <5>;
1984 apss_ 1805 apss_funnel_in5: endpoint {
1985 1806 remote-endpoint =
1986 1807 <&etm5_out>;
1987 }; 1808 };
1988 }; 1809 };
1989 1810
1990 port@6 { 1811 port@6 {
1991 reg = 1812 reg = <6>;
1992 apss_ 1813 apss_funnel_in6: endpoint {
1993 1814 remote-endpoint =
1994 1815 <&etm6_out>;
1995 }; 1816 };
1996 }; 1817 };
1997 1818
1998 port@7 { 1819 port@7 {
1999 reg = 1820 reg = <7>;
2000 apss_ 1821 apss_funnel_in7: endpoint {
2001 1822 remote-endpoint =
2002 1823 <&etm7_out>;
2003 }; 1824 };
2004 }; 1825 };
2005 }; 1826 };
2006 }; 1827 };
2007 1828
2008 funnel5: funnel@7b70000 { 1829 funnel5: funnel@7b70000 {
2009 compatible = "arm,cor 1830 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2010 reg = <0x07b70000 0x1 1831 reg = <0x07b70000 0x1000>;
2011 status = "disabled"; 1832 status = "disabled";
2012 1833
2013 clocks = <&rpmcc RPM_ 1834 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2014 clock-names = "apb_pc 1835 clock-names = "apb_pclk", "atclk";
2015 1836
2016 out-ports { 1837 out-ports {
2017 port { 1838 port {
2018 apss_ 1839 apss_merge_funnel_out: endpoint {
2019 1840 remote-endpoint =
2020 1841 <&funnel1_in6>;
2021 }; 1842 };
2022 }; 1843 };
2023 }; 1844 };
2024 1845
2025 in-ports { 1846 in-ports {
2026 port { 1847 port {
2027 apss_ 1848 apss_merge_funnel_in: endpoint {
2028 1849 remote-endpoint =
2029 1850 <&apss_funnel_out>;
2030 }; 1851 };
2031 }; 1852 };
2032 }; 1853 };
2033 }; 1854 };
2034 1855
2035 etm5: etm@7c40000 { 1856 etm5: etm@7c40000 {
2036 compatible = "arm,cor 1857 compatible = "arm,coresight-etm4x", "arm,primecell";
2037 reg = <0x07c40000 0x1 1858 reg = <0x07c40000 0x1000>;
2038 status = "disabled"; 1859 status = "disabled";
2039 1860
2040 clocks = <&rpmcc RPM_ 1861 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2041 clock-names = "apb_pc 1862 clock-names = "apb_pclk", "atclk";
2042 1863
2043 cpu = <&CPU4>; 1864 cpu = <&CPU4>;
2044 1865
2045 out-ports { 1866 out-ports {
2046 port { !! 1867 port{
2047 etm4_ 1868 etm4_out: endpoint {
2048 1869 remote-endpoint = <&apss_funnel_in4>;
2049 }; 1870 };
2050 }; 1871 };
2051 }; 1872 };
2052 }; 1873 };
2053 1874
2054 etm6: etm@7d40000 { 1875 etm6: etm@7d40000 {
2055 compatible = "arm,cor 1876 compatible = "arm,coresight-etm4x", "arm,primecell";
2056 reg = <0x07d40000 0x1 1877 reg = <0x07d40000 0x1000>;
2057 status = "disabled"; 1878 status = "disabled";
2058 1879
2059 clocks = <&rpmcc RPM_ 1880 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2060 clock-names = "apb_pc 1881 clock-names = "apb_pclk", "atclk";
2061 1882
2062 cpu = <&CPU5>; 1883 cpu = <&CPU5>;
2063 1884
2064 out-ports { 1885 out-ports {
2065 port { !! 1886 port{
2066 etm5_ 1887 etm5_out: endpoint {
2067 1888 remote-endpoint = <&apss_funnel_in5>;
2068 }; 1889 };
2069 }; 1890 };
2070 }; 1891 };
2071 }; 1892 };
2072 1893
2073 etm7: etm@7e40000 { 1894 etm7: etm@7e40000 {
2074 compatible = "arm,cor 1895 compatible = "arm,coresight-etm4x", "arm,primecell";
2075 reg = <0x07e40000 0x1 1896 reg = <0x07e40000 0x1000>;
2076 status = "disabled"; 1897 status = "disabled";
2077 1898
2078 clocks = <&rpmcc RPM_ 1899 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2079 clock-names = "apb_pc 1900 clock-names = "apb_pclk", "atclk";
2080 1901
2081 cpu = <&CPU6>; 1902 cpu = <&CPU6>;
2082 1903
2083 out-ports { 1904 out-ports {
2084 port { !! 1905 port{
2085 etm6_ 1906 etm6_out: endpoint {
2086 1907 remote-endpoint = <&apss_funnel_in6>;
2087 }; 1908 };
2088 }; 1909 };
2089 }; 1910 };
2090 }; 1911 };
2091 1912
2092 etm8: etm@7f40000 { 1913 etm8: etm@7f40000 {
2093 compatible = "arm,cor 1914 compatible = "arm,coresight-etm4x", "arm,primecell";
2094 reg = <0x07f40000 0x1 1915 reg = <0x07f40000 0x1000>;
2095 status = "disabled"; 1916 status = "disabled";
2096 1917
2097 clocks = <&rpmcc RPM_ 1918 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2098 clock-names = "apb_pc 1919 clock-names = "apb_pclk", "atclk";
2099 1920
2100 cpu = <&CPU7>; 1921 cpu = <&CPU7>;
2101 1922
2102 out-ports { 1923 out-ports {
2103 port { !! 1924 port{
2104 etm7_ 1925 etm7_out: endpoint {
2105 1926 remote-endpoint = <&apss_funnel_in7>;
2106 }; 1927 };
2107 }; 1928 };
2108 }; 1929 };
2109 }; 1930 };
2110 1931
2111 sram@290000 { <<
2112 compatible = "qcom,rp <<
2113 reg = <0x00290000 0x1 <<
2114 }; <<
2115 <<
2116 spmi_bus: spmi@800f000 { 1932 spmi_bus: spmi@800f000 {
2117 compatible = "qcom,sp 1933 compatible = "qcom,spmi-pmic-arb";
2118 reg = <0x0800f000 0x1 !! 1934 reg = <0x0800f000 0x1000>,
2119 <0x08400000 0x1 !! 1935 <0x08400000 0x1000000>,
2120 <0x09400000 0x1 !! 1936 <0x09400000 0x1000000>,
2121 <0x0a400000 0x2 !! 1937 <0x0a400000 0x220000>,
2122 <0x0800a000 0x3 !! 1938 <0x0800a000 0x3000>;
2123 reg-names = "core", " 1939 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
2124 interrupt-names = "pe 1940 interrupt-names = "periph_irq";
2125 interrupts = <GIC_SPI 1941 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
2126 qcom,ee = <0>; 1942 qcom,ee = <0>;
2127 qcom,channel = <0>; 1943 qcom,channel = <0>;
2128 #address-cells = <2>; 1944 #address-cells = <2>;
2129 #size-cells = <0>; 1945 #size-cells = <0>;
2130 interrupt-controller; 1946 interrupt-controller;
2131 #interrupt-cells = <4 1947 #interrupt-cells = <4>;
>> 1948 cell-index = <0>;
2132 }; 1949 };
2133 1950
2134 usb3: usb@a8f8800 { 1951 usb3: usb@a8f8800 {
2135 compatible = "qcom,ms 1952 compatible = "qcom,msm8998-dwc3", "qcom,dwc3";
2136 reg = <0x0a8f8800 0x4 1953 reg = <0x0a8f8800 0x400>;
2137 status = "disabled"; 1954 status = "disabled";
2138 #address-cells = <1>; 1955 #address-cells = <1>;
2139 #size-cells = <1>; 1956 #size-cells = <1>;
2140 ranges; 1957 ranges;
2141 1958
2142 clocks = <&gcc GCC_CF 1959 clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>,
2143 <&gcc GCC_US 1960 <&gcc GCC_USB30_MASTER_CLK>,
2144 <&gcc GCC_AG 1961 <&gcc GCC_AGGRE1_USB3_AXI_CLK>,
2145 <&gcc GCC_US !! 1962 <&gcc GCC_USB30_MOCK_UTMI_CLK>,
2146 <&gcc GCC_US !! 1963 <&gcc GCC_USB30_SLEEP_CLK>;
2147 clock-names = "cfg_no !! 1964 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
2148 "core", !! 1965 "sleep";
2149 "iface" <<
2150 "sleep" <<
2151 "mock_u <<
2152 1966
2153 assigned-clocks = <&g 1967 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
2154 <&g 1968 <&gcc GCC_USB30_MASTER_CLK>;
2155 assigned-clock-rates 1969 assigned-clock-rates = <19200000>, <120000000>;
2156 1970
2157 interrupts = <GIC_SPI !! 1971 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
2158 <GIC_SPI <<
2159 <GIC_SPI 1972 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
2160 interrupt-names = "pw !! 1973 interrupt-names = "hs_phy_irq", "ss_phy_irq";
2161 "qu <<
2162 "ss <<
2163 1974
2164 power-domains = <&gcc 1975 power-domains = <&gcc USB_30_GDSC>;
2165 1976
2166 resets = <&gcc GCC_US 1977 resets = <&gcc GCC_USB_30_BCR>;
2167 1978
2168 usb3_dwc3: usb@a80000 !! 1979 usb3_dwc3: dwc3@a800000 {
2169 compatible = 1980 compatible = "snps,dwc3";
2170 reg = <0x0a80 1981 reg = <0x0a800000 0xcd00>;
2171 interrupts = 1982 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
2172 snps,dis_u2_s 1983 snps,dis_u2_susphy_quirk;
2173 snps,dis_enbl 1984 snps,dis_enblslpm_quirk;
2174 snps,parkmode 1985 snps,parkmode-disable-ss-quirk;
2175 phys = <&qusb 1986 phys = <&qusb2phy>, <&usb3phy>;
2176 phy-names = " 1987 phy-names = "usb2-phy", "usb3-phy";
2177 snps,has-lpm- 1988 snps,has-lpm-erratum;
2178 snps,hird-thr 1989 snps,hird-threshold = /bits/ 8 <0x10>;
2179 }; 1990 };
2180 }; 1991 };
2181 1992
2182 usb3phy: phy@c010000 { 1993 usb3phy: phy@c010000 {
2183 compatible = "qcom,ms 1994 compatible = "qcom,msm8998-qmp-usb3-phy";
2184 reg = <0x0c010000 0x1 1995 reg = <0x0c010000 0x1000>;
2185 1996
2186 clocks = <&gcc GCC_US 1997 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
2187 <&gcc GCC_US 1998 <&gcc GCC_USB3_CLKREF_CLK>,
2188 <&gcc GCC_US 1999 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2189 <&gcc GCC_US 2000 <&gcc GCC_USB3_PHY_PIPE_CLK>;
2190 clock-names = "aux", 2001 clock-names = "aux",
2191 "ref", 2002 "ref",
2192 "cfg_ah 2003 "cfg_ahb",
2193 "pipe"; 2004 "pipe";
2194 clock-output-names = 2005 clock-output-names = "usb3_phy_pipe_clk_src";
2195 #clock-cells = <0>; 2006 #clock-cells = <0>;
2196 #phy-cells = <0>; 2007 #phy-cells = <0>;
2197 2008
2198 resets = <&gcc GCC_US 2009 resets = <&gcc GCC_USB3_PHY_BCR>,
2199 <&gcc GCC_US 2010 <&gcc GCC_USB3PHY_PHY_BCR>;
2200 reset-names = "phy", 2011 reset-names = "phy",
2201 "phy_ph 2012 "phy_phy";
2202 2013
2203 qcom,tcsr-reg = <&tcs <<
2204 <<
2205 status = "disabled"; 2014 status = "disabled";
2206 }; 2015 };
2207 2016
2208 qusb2phy: phy@c012000 { 2017 qusb2phy: phy@c012000 {
2209 compatible = "qcom,ms 2018 compatible = "qcom,msm8998-qusb2-phy";
2210 reg = <0x0c012000 0x2 2019 reg = <0x0c012000 0x2a8>;
2211 status = "disabled"; 2020 status = "disabled";
2212 #phy-cells = <0>; 2021 #phy-cells = <0>;
2213 2022
2214 clocks = <&gcc GCC_US 2023 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2215 <&gcc GCC_RX 2024 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
2216 clock-names = "cfg_ah 2025 clock-names = "cfg_ahb", "ref";
2217 2026
2218 resets = <&gcc GCC_QU 2027 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2219 2028
2220 nvmem-cells = <&qusb2 2029 nvmem-cells = <&qusb2_hstx_trim>;
2221 }; 2030 };
2222 2031
2223 sdhc2: mmc@c0a4900 { !! 2032 sdhc2: sdhci@c0a4900 {
2224 compatible = "qcom,ms !! 2033 compatible = "qcom,sdhci-msm-v4";
2225 reg = <0x0c0a4900 0x3 2034 reg = <0x0c0a4900 0x314>, <0x0c0a4000 0x800>;
2226 reg-names = "hc", "co !! 2035 reg-names = "hc_mem", "core_mem";
2227 2036
2228 interrupts = <GIC_SPI 2037 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
2229 <GIC_SPI 2038 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
2230 interrupt-names = "hc 2039 interrupt-names = "hc_irq", "pwr_irq";
2231 2040
2232 clock-names = "iface" 2041 clock-names = "iface", "core", "xo";
2233 clocks = <&gcc GCC_SD 2042 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2234 <&gcc GCC_SD 2043 <&gcc GCC_SDCC2_APPS_CLK>,
2235 <&rpmcc RPM_ !! 2044 <&xo>;
2236 bus-width = <4>; 2045 bus-width = <4>;
2237 status = "disabled"; 2046 status = "disabled";
2238 }; 2047 };
2239 2048
2240 blsp1_dma: dma-controller@c14 2049 blsp1_dma: dma-controller@c144000 {
2241 compatible = "qcom,ba 2050 compatible = "qcom,bam-v1.7.0";
2242 reg = <0x0c144000 0x2 2051 reg = <0x0c144000 0x25000>;
2243 interrupts = <GIC_SPI 2052 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
2244 clocks = <&gcc GCC_BL 2053 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
2245 clock-names = "bam_cl 2054 clock-names = "bam_clk";
2246 #dma-cells = <1>; 2055 #dma-cells = <1>;
2247 qcom,ee = <0>; 2056 qcom,ee = <0>;
2248 qcom,controlled-remot 2057 qcom,controlled-remotely;
2249 num-channels = <18>; 2058 num-channels = <18>;
2250 qcom,num-ees = <4>; 2059 qcom,num-ees = <4>;
2251 }; 2060 };
2252 2061
2253 blsp1_uart3: serial@c171000 { 2062 blsp1_uart3: serial@c171000 {
2254 compatible = "qcom,ms 2063 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2255 reg = <0x0c171000 0x1 2064 reg = <0x0c171000 0x1000>;
2256 interrupts = <GIC_SPI 2065 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
2257 clocks = <&gcc GCC_BL 2066 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
2258 <&gcc GCC_BL 2067 <&gcc GCC_BLSP1_AHB_CLK>;
2259 clock-names = "core", 2068 clock-names = "core", "iface";
2260 dmas = <&blsp1_dma 4> 2069 dmas = <&blsp1_dma 4>, <&blsp1_dma 5>;
2261 dma-names = "tx", "rx 2070 dma-names = "tx", "rx";
2262 pinctrl-names = "defa 2071 pinctrl-names = "default";
2263 pinctrl-0 = <&blsp1_u 2072 pinctrl-0 = <&blsp1_uart3_on>;
2264 status = "disabled"; 2073 status = "disabled";
2265 }; 2074 };
2266 2075
2267 blsp1_i2c1: i2c@c175000 { 2076 blsp1_i2c1: i2c@c175000 {
2268 compatible = "qcom,i2 2077 compatible = "qcom,i2c-qup-v2.2.1";
2269 reg = <0x0c175000 0x6 2078 reg = <0x0c175000 0x600>;
2270 interrupts = <GIC_SPI 2079 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
2271 2080
2272 clocks = <&gcc GCC_BL 2081 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
2273 <&gcc GCC_BL 2082 <&gcc GCC_BLSP1_AHB_CLK>;
2274 clock-names = "core", 2083 clock-names = "core", "iface";
2275 dmas = <&blsp1_dma 6> 2084 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>;
2276 dma-names = "tx", "rx 2085 dma-names = "tx", "rx";
2277 pinctrl-names = "defa 2086 pinctrl-names = "default", "sleep";
2278 pinctrl-0 = <&blsp1_i 2087 pinctrl-0 = <&blsp1_i2c1_default>;
2279 pinctrl-1 = <&blsp1_i 2088 pinctrl-1 = <&blsp1_i2c1_sleep>;
2280 clock-frequency = <40 2089 clock-frequency = <400000>;
2281 2090
2282 status = "disabled"; 2091 status = "disabled";
2283 #address-cells = <1>; 2092 #address-cells = <1>;
2284 #size-cells = <0>; 2093 #size-cells = <0>;
2285 }; 2094 };
2286 2095
2287 blsp1_i2c2: i2c@c176000 { 2096 blsp1_i2c2: i2c@c176000 {
2288 compatible = "qcom,i2 2097 compatible = "qcom,i2c-qup-v2.2.1";
2289 reg = <0x0c176000 0x6 2098 reg = <0x0c176000 0x600>;
2290 interrupts = <GIC_SPI 2099 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
2291 2100
2292 clocks = <&gcc GCC_BL 2101 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
2293 <&gcc GCC_BL 2102 <&gcc GCC_BLSP1_AHB_CLK>;
2294 clock-names = "core", 2103 clock-names = "core", "iface";
2295 dmas = <&blsp1_dma 8> 2104 dmas = <&blsp1_dma 8>, <&blsp1_dma 9>;
2296 dma-names = "tx", "rx 2105 dma-names = "tx", "rx";
2297 pinctrl-names = "defa 2106 pinctrl-names = "default", "sleep";
2298 pinctrl-0 = <&blsp1_i 2107 pinctrl-0 = <&blsp1_i2c2_default>;
2299 pinctrl-1 = <&blsp1_i 2108 pinctrl-1 = <&blsp1_i2c2_sleep>;
2300 clock-frequency = <40 2109 clock-frequency = <400000>;
2301 2110
2302 status = "disabled"; 2111 status = "disabled";
2303 #address-cells = <1>; 2112 #address-cells = <1>;
2304 #size-cells = <0>; 2113 #size-cells = <0>;
2305 }; 2114 };
2306 2115
2307 blsp1_i2c3: i2c@c177000 { 2116 blsp1_i2c3: i2c@c177000 {
2308 compatible = "qcom,i2 2117 compatible = "qcom,i2c-qup-v2.2.1";
2309 reg = <0x0c177000 0x6 2118 reg = <0x0c177000 0x600>;
2310 interrupts = <GIC_SPI 2119 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
2311 2120
2312 clocks = <&gcc GCC_BL 2121 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
2313 <&gcc GCC_BL 2122 <&gcc GCC_BLSP1_AHB_CLK>;
2314 clock-names = "core", 2123 clock-names = "core", "iface";
2315 dmas = <&blsp1_dma 10 2124 dmas = <&blsp1_dma 10>, <&blsp1_dma 11>;
2316 dma-names = "tx", "rx 2125 dma-names = "tx", "rx";
2317 pinctrl-names = "defa 2126 pinctrl-names = "default", "sleep";
2318 pinctrl-0 = <&blsp1_i 2127 pinctrl-0 = <&blsp1_i2c3_default>;
2319 pinctrl-1 = <&blsp1_i 2128 pinctrl-1 = <&blsp1_i2c3_sleep>;
2320 clock-frequency = <40 2129 clock-frequency = <400000>;
2321 2130
2322 status = "disabled"; 2131 status = "disabled";
2323 #address-cells = <1>; 2132 #address-cells = <1>;
2324 #size-cells = <0>; 2133 #size-cells = <0>;
2325 }; 2134 };
2326 2135
2327 blsp1_i2c4: i2c@c178000 { 2136 blsp1_i2c4: i2c@c178000 {
2328 compatible = "qcom,i2 2137 compatible = "qcom,i2c-qup-v2.2.1";
2329 reg = <0x0c178000 0x6 2138 reg = <0x0c178000 0x600>;
2330 interrupts = <GIC_SPI 2139 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
2331 2140
2332 clocks = <&gcc GCC_BL 2141 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
2333 <&gcc GCC_BL 2142 <&gcc GCC_BLSP1_AHB_CLK>;
2334 clock-names = "core", 2143 clock-names = "core", "iface";
2335 dmas = <&blsp1_dma 12 2144 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
2336 dma-names = "tx", "rx 2145 dma-names = "tx", "rx";
2337 pinctrl-names = "defa 2146 pinctrl-names = "default", "sleep";
2338 pinctrl-0 = <&blsp1_i 2147 pinctrl-0 = <&blsp1_i2c4_default>;
2339 pinctrl-1 = <&blsp1_i 2148 pinctrl-1 = <&blsp1_i2c4_sleep>;
2340 clock-frequency = <40 2149 clock-frequency = <400000>;
2341 2150
2342 status = "disabled"; 2151 status = "disabled";
2343 #address-cells = <1>; 2152 #address-cells = <1>;
2344 #size-cells = <0>; 2153 #size-cells = <0>;
2345 }; 2154 };
2346 2155
2347 blsp1_i2c5: i2c@c179000 { 2156 blsp1_i2c5: i2c@c179000 {
2348 compatible = "qcom,i2 2157 compatible = "qcom,i2c-qup-v2.2.1";
2349 reg = <0x0c179000 0x6 2158 reg = <0x0c179000 0x600>;
2350 interrupts = <GIC_SPI 2159 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
2351 2160
2352 clocks = <&gcc GCC_BL 2161 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
2353 <&gcc GCC_BL 2162 <&gcc GCC_BLSP1_AHB_CLK>;
2354 clock-names = "core", 2163 clock-names = "core", "iface";
2355 dmas = <&blsp1_dma 14 2164 dmas = <&blsp1_dma 14>, <&blsp1_dma 15>;
2356 dma-names = "tx", "rx 2165 dma-names = "tx", "rx";
2357 pinctrl-names = "defa 2166 pinctrl-names = "default", "sleep";
2358 pinctrl-0 = <&blsp1_i 2167 pinctrl-0 = <&blsp1_i2c5_default>;
2359 pinctrl-1 = <&blsp1_i 2168 pinctrl-1 = <&blsp1_i2c5_sleep>;
2360 clock-frequency = <40 2169 clock-frequency = <400000>;
2361 2170
2362 status = "disabled"; 2171 status = "disabled";
2363 #address-cells = <1>; 2172 #address-cells = <1>;
2364 #size-cells = <0>; 2173 #size-cells = <0>;
2365 }; 2174 };
2366 2175
2367 blsp1_i2c6: i2c@c17a000 { 2176 blsp1_i2c6: i2c@c17a000 {
2368 compatible = "qcom,i2 2177 compatible = "qcom,i2c-qup-v2.2.1";
2369 reg = <0x0c17a000 0x6 2178 reg = <0x0c17a000 0x600>;
2370 interrupts = <GIC_SPI 2179 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
2371 2180
2372 clocks = <&gcc GCC_BL 2181 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
2373 <&gcc GCC_BL 2182 <&gcc GCC_BLSP1_AHB_CLK>;
2374 clock-names = "core", 2183 clock-names = "core", "iface";
2375 dmas = <&blsp1_dma 16 2184 dmas = <&blsp1_dma 16>, <&blsp1_dma 17>;
2376 dma-names = "tx", "rx 2185 dma-names = "tx", "rx";
2377 pinctrl-names = "defa 2186 pinctrl-names = "default", "sleep";
2378 pinctrl-0 = <&blsp1_i 2187 pinctrl-0 = <&blsp1_i2c6_default>;
2379 pinctrl-1 = <&blsp1_i 2188 pinctrl-1 = <&blsp1_i2c6_sleep>;
2380 clock-frequency = <40 2189 clock-frequency = <400000>;
2381 2190
2382 status = "disabled"; 2191 status = "disabled";
2383 #address-cells = <1>; 2192 #address-cells = <1>;
2384 #size-cells = <0>; 2193 #size-cells = <0>;
2385 }; 2194 };
2386 2195
2387 blsp1_spi1: spi@c175000 { !! 2196 blsp2_dma: dma@c184000 {
2388 compatible = "qcom,sp <<
2389 reg = <0x0c175000 0x6 <<
2390 interrupts = <GIC_SPI <<
2391 <<
2392 clocks = <&gcc GCC_BL <<
2393 <&gcc GCC_BL <<
2394 clock-names = "core", <<
2395 dmas = <&blsp1_dma 6> <<
2396 dma-names = "tx", "rx <<
2397 pinctrl-names = "defa <<
2398 pinctrl-0 = <&blsp1_s <<
2399 <<
2400 status = "disabled"; <<
2401 #address-cells = <1>; <<
2402 #size-cells = <0>; <<
2403 }; <<
2404 <<
2405 blsp1_spi2: spi@c176000 { <<
2406 compatible = "qcom,sp <<
2407 reg = <0x0c176000 0x6 <<
2408 interrupts = <GIC_SPI <<
2409 <<
2410 clocks = <&gcc GCC_BL <<
2411 <&gcc GCC_BL <<
2412 clock-names = "core", <<
2413 dmas = <&blsp1_dma 8> <<
2414 dma-names = "tx", "rx <<
2415 pinctrl-names = "defa <<
2416 pinctrl-0 = <&blsp1_s <<
2417 <<
2418 status = "disabled"; <<
2419 #address-cells = <1>; <<
2420 #size-cells = <0>; <<
2421 }; <<
2422 <<
2423 blsp1_spi3: spi@c177000 { <<
2424 compatible = "qcom,sp <<
2425 reg = <0x0c177000 0x6 <<
2426 interrupts = <GIC_SPI <<
2427 <<
2428 clocks = <&gcc GCC_BL <<
2429 <&gcc GCC_BL <<
2430 clock-names = "core", <<
2431 dmas = <&blsp1_dma 10 <<
2432 dma-names = "tx", "rx <<
2433 pinctrl-names = "defa <<
2434 pinctrl-0 = <&blsp1_s <<
2435 <<
2436 status = "disabled"; <<
2437 #address-cells = <1>; <<
2438 #size-cells = <0>; <<
2439 }; <<
2440 <<
2441 blsp1_spi4: spi@c178000 { <<
2442 compatible = "qcom,sp <<
2443 reg = <0x0c178000 0x6 <<
2444 interrupts = <GIC_SPI <<
2445 <<
2446 clocks = <&gcc GCC_BL <<
2447 <&gcc GCC_BL <<
2448 clock-names = "core", <<
2449 dmas = <&blsp1_dma 12 <<
2450 dma-names = "tx", "rx <<
2451 pinctrl-names = "defa <<
2452 pinctrl-0 = <&blsp1_s <<
2453 <<
2454 status = "disabled"; <<
2455 #address-cells = <1>; <<
2456 #size-cells = <0>; <<
2457 }; <<
2458 <<
2459 blsp1_spi5: spi@c179000 { <<
2460 compatible = "qcom,sp <<
2461 reg = <0x0c179000 0x6 <<
2462 interrupts = <GIC_SPI <<
2463 <<
2464 clocks = <&gcc GCC_BL <<
2465 <&gcc GCC_BL <<
2466 clock-names = "core", <<
2467 dmas = <&blsp1_dma 14 <<
2468 dma-names = "tx", "rx <<
2469 pinctrl-names = "defa <<
2470 pinctrl-0 = <&blsp1_s <<
2471 <<
2472 status = "disabled"; <<
2473 #address-cells = <1>; <<
2474 #size-cells = <0>; <<
2475 }; <<
2476 <<
2477 blsp1_spi6: spi@c17a000 { <<
2478 compatible = "qcom,sp <<
2479 reg = <0x0c17a000 0x6 <<
2480 interrupts = <GIC_SPI <<
2481 <<
2482 clocks = <&gcc GCC_BL <<
2483 <&gcc GCC_BL <<
2484 clock-names = "core", <<
2485 dmas = <&blsp1_dma 16 <<
2486 dma-names = "tx", "rx <<
2487 pinctrl-names = "defa <<
2488 pinctrl-0 = <&blsp1_s <<
2489 <<
2490 status = "disabled"; <<
2491 #address-cells = <1>; <<
2492 #size-cells = <0>; <<
2493 }; <<
2494 <<
2495 blsp2_dma: dma-controller@c18 <<
2496 compatible = "qcom,ba 2197 compatible = "qcom,bam-v1.7.0";
2497 reg = <0x0c184000 0x2 2198 reg = <0x0c184000 0x25000>;
2498 interrupts = <GIC_SPI 2199 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
2499 clocks = <&gcc GCC_BL 2200 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
2500 clock-names = "bam_cl 2201 clock-names = "bam_clk";
2501 #dma-cells = <1>; 2202 #dma-cells = <1>;
2502 qcom,ee = <0>; 2203 qcom,ee = <0>;
2503 qcom,controlled-remot 2204 qcom,controlled-remotely;
2504 num-channels = <18>; 2205 num-channels = <18>;
2505 qcom,num-ees = <4>; 2206 qcom,num-ees = <4>;
2506 }; 2207 };
2507 2208
2508 blsp2_uart1: serial@c1b0000 { 2209 blsp2_uart1: serial@c1b0000 {
2509 compatible = "qcom,ms 2210 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2510 reg = <0x0c1b0000 0x1 2211 reg = <0x0c1b0000 0x1000>;
2511 interrupts = <GIC_SPI 2212 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
2512 clocks = <&gcc GCC_BL 2213 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
2513 <&gcc GCC_BL 2214 <&gcc GCC_BLSP2_AHB_CLK>;
2514 clock-names = "core", 2215 clock-names = "core", "iface";
2515 status = "disabled"; 2216 status = "disabled";
2516 }; 2217 };
2517 2218
2518 blsp2_i2c1: i2c@c1b5000 { 2219 blsp2_i2c1: i2c@c1b5000 {
2519 compatible = "qcom,i2 2220 compatible = "qcom,i2c-qup-v2.2.1";
2520 reg = <0x0c1b5000 0x6 2221 reg = <0x0c1b5000 0x600>;
2521 interrupts = <GIC_SPI 2222 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
2522 2223
2523 clocks = <&gcc GCC_BL 2224 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
2524 <&gcc GCC_BL 2225 <&gcc GCC_BLSP2_AHB_CLK>;
2525 clock-names = "core", 2226 clock-names = "core", "iface";
2526 dmas = <&blsp2_dma 6> 2227 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>;
2527 dma-names = "tx", "rx 2228 dma-names = "tx", "rx";
2528 pinctrl-names = "defa 2229 pinctrl-names = "default", "sleep";
2529 pinctrl-0 = <&blsp2_i 2230 pinctrl-0 = <&blsp2_i2c1_default>;
2530 pinctrl-1 = <&blsp2_i 2231 pinctrl-1 = <&blsp2_i2c1_sleep>;
2531 clock-frequency = <40 2232 clock-frequency = <400000>;
2532 2233
2533 status = "disabled"; 2234 status = "disabled";
2534 #address-cells = <1>; 2235 #address-cells = <1>;
2535 #size-cells = <0>; 2236 #size-cells = <0>;
2536 }; 2237 };
2537 2238
2538 blsp2_i2c2: i2c@c1b6000 { 2239 blsp2_i2c2: i2c@c1b6000 {
2539 compatible = "qcom,i2 2240 compatible = "qcom,i2c-qup-v2.2.1";
2540 reg = <0x0c1b6000 0x6 2241 reg = <0x0c1b6000 0x600>;
2541 interrupts = <GIC_SPI 2242 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
2542 2243
2543 clocks = <&gcc GCC_BL 2244 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
2544 <&gcc GCC_BL 2245 <&gcc GCC_BLSP2_AHB_CLK>;
2545 clock-names = "core", 2246 clock-names = "core", "iface";
2546 dmas = <&blsp2_dma 8> 2247 dmas = <&blsp2_dma 8>, <&blsp2_dma 9>;
2547 dma-names = "tx", "rx 2248 dma-names = "tx", "rx";
2548 pinctrl-names = "defa 2249 pinctrl-names = "default", "sleep";
2549 pinctrl-0 = <&blsp2_i 2250 pinctrl-0 = <&blsp2_i2c2_default>;
2550 pinctrl-1 = <&blsp2_i 2251 pinctrl-1 = <&blsp2_i2c2_sleep>;
2551 clock-frequency = <40 2252 clock-frequency = <400000>;
2552 2253
2553 status = "disabled"; 2254 status = "disabled";
2554 #address-cells = <1>; 2255 #address-cells = <1>;
2555 #size-cells = <0>; 2256 #size-cells = <0>;
2556 }; 2257 };
2557 2258
2558 blsp2_i2c3: i2c@c1b7000 { 2259 blsp2_i2c3: i2c@c1b7000 {
2559 compatible = "qcom,i2 2260 compatible = "qcom,i2c-qup-v2.2.1";
2560 reg = <0x0c1b7000 0x6 2261 reg = <0x0c1b7000 0x600>;
2561 interrupts = <GIC_SPI 2262 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
2562 2263
2563 clocks = <&gcc GCC_BL 2264 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
2564 <&gcc GCC_BL 2265 <&gcc GCC_BLSP2_AHB_CLK>;
2565 clock-names = "core", 2266 clock-names = "core", "iface";
2566 dmas = <&blsp2_dma 10 2267 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>;
2567 dma-names = "tx", "rx 2268 dma-names = "tx", "rx";
2568 pinctrl-names = "defa 2269 pinctrl-names = "default", "sleep";
2569 pinctrl-0 = <&blsp2_i 2270 pinctrl-0 = <&blsp2_i2c3_default>;
2570 pinctrl-1 = <&blsp2_i 2271 pinctrl-1 = <&blsp2_i2c3_sleep>;
2571 clock-frequency = <40 2272 clock-frequency = <400000>;
2572 2273
2573 status = "disabled"; 2274 status = "disabled";
2574 #address-cells = <1>; 2275 #address-cells = <1>;
2575 #size-cells = <0>; 2276 #size-cells = <0>;
2576 }; 2277 };
2577 2278
2578 blsp2_i2c4: i2c@c1b8000 { 2279 blsp2_i2c4: i2c@c1b8000 {
2579 compatible = "qcom,i2 2280 compatible = "qcom,i2c-qup-v2.2.1";
2580 reg = <0x0c1b8000 0x6 2281 reg = <0x0c1b8000 0x600>;
2581 interrupts = <GIC_SPI 2282 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
2582 2283
2583 clocks = <&gcc GCC_BL 2284 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>,
2584 <&gcc GCC_BL 2285 <&gcc GCC_BLSP2_AHB_CLK>;
2585 clock-names = "core", 2286 clock-names = "core", "iface";
2586 dmas = <&blsp2_dma 12 2287 dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
2587 dma-names = "tx", "rx 2288 dma-names = "tx", "rx";
2588 pinctrl-names = "defa 2289 pinctrl-names = "default", "sleep";
2589 pinctrl-0 = <&blsp2_i 2290 pinctrl-0 = <&blsp2_i2c4_default>;
2590 pinctrl-1 = <&blsp2_i 2291 pinctrl-1 = <&blsp2_i2c4_sleep>;
2591 clock-frequency = <40 2292 clock-frequency = <400000>;
2592 2293
2593 status = "disabled"; 2294 status = "disabled";
2594 #address-cells = <1>; 2295 #address-cells = <1>;
2595 #size-cells = <0>; 2296 #size-cells = <0>;
2596 }; 2297 };
2597 2298
2598 blsp2_i2c5: i2c@c1b9000 { 2299 blsp2_i2c5: i2c@c1b9000 {
2599 compatible = "qcom,i2 2300 compatible = "qcom,i2c-qup-v2.2.1";
2600 reg = <0x0c1b9000 0x6 2301 reg = <0x0c1b9000 0x600>;
2601 interrupts = <GIC_SPI 2302 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
2602 2303
2603 clocks = <&gcc GCC_BL 2304 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,
2604 <&gcc GCC_BL 2305 <&gcc GCC_BLSP2_AHB_CLK>;
2605 clock-names = "core", 2306 clock-names = "core", "iface";
2606 dmas = <&blsp2_dma 14 2307 dmas = <&blsp2_dma 14>, <&blsp2_dma 15>;
2607 dma-names = "tx", "rx 2308 dma-names = "tx", "rx";
2608 pinctrl-names = "defa 2309 pinctrl-names = "default", "sleep";
2609 pinctrl-0 = <&blsp2_i 2310 pinctrl-0 = <&blsp2_i2c5_default>;
2610 pinctrl-1 = <&blsp2_i 2311 pinctrl-1 = <&blsp2_i2c5_sleep>;
2611 clock-frequency = <40 2312 clock-frequency = <400000>;
2612 2313
2613 status = "disabled"; 2314 status = "disabled";
2614 #address-cells = <1>; 2315 #address-cells = <1>;
2615 #size-cells = <0>; 2316 #size-cells = <0>;
2616 }; 2317 };
2617 2318
2618 blsp2_i2c6: i2c@c1ba000 { 2319 blsp2_i2c6: i2c@c1ba000 {
2619 compatible = "qcom,i2 2320 compatible = "qcom,i2c-qup-v2.2.1";
2620 reg = <0x0c1ba000 0x6 2321 reg = <0x0c1ba000 0x600>;
2621 interrupts = <GIC_SPI 2322 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
2622 2323
2623 clocks = <&gcc GCC_BL 2324 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>,
2624 <&gcc GCC_BL 2325 <&gcc GCC_BLSP2_AHB_CLK>;
2625 clock-names = "core", 2326 clock-names = "core", "iface";
2626 dmas = <&blsp2_dma 16 2327 dmas = <&blsp2_dma 16>, <&blsp2_dma 17>;
2627 dma-names = "tx", "rx 2328 dma-names = "tx", "rx";
2628 pinctrl-names = "defa 2329 pinctrl-names = "default", "sleep";
2629 pinctrl-0 = <&blsp2_i 2330 pinctrl-0 = <&blsp2_i2c6_default>;
2630 pinctrl-1 = <&blsp2_i 2331 pinctrl-1 = <&blsp2_i2c6_sleep>;
2631 clock-frequency = <40 2332 clock-frequency = <400000>;
2632 2333
2633 status = "disabled"; 2334 status = "disabled";
2634 #address-cells = <1>; 2335 #address-cells = <1>;
2635 #size-cells = <0>; 2336 #size-cells = <0>;
2636 }; 2337 };
2637 2338
2638 blsp2_spi1: spi@c1b5000 { <<
2639 compatible = "qcom,sp <<
2640 reg = <0x0c1b5000 0x6 <<
2641 interrupts = <GIC_SPI <<
2642 <<
2643 clocks = <&gcc GCC_BL <<
2644 <&gcc GCC_BL <<
2645 clock-names = "core", <<
2646 dmas = <&blsp2_dma 6> <<
2647 dma-names = "tx", "rx <<
2648 pinctrl-names = "defa <<
2649 pinctrl-0 = <&blsp2_s <<
2650 <<
2651 status = "disabled"; <<
2652 #address-cells = <1>; <<
2653 #size-cells = <0>; <<
2654 }; <<
2655 <<
2656 blsp2_spi2: spi@c1b6000 { <<
2657 compatible = "qcom,sp <<
2658 reg = <0x0c1b6000 0x6 <<
2659 interrupts = <GIC_SPI <<
2660 <<
2661 clocks = <&gcc GCC_BL <<
2662 <&gcc GCC_BL <<
2663 clock-names = "core", <<
2664 dmas = <&blsp2_dma 8> <<
2665 dma-names = "tx", "rx <<
2666 pinctrl-names = "defa <<
2667 pinctrl-0 = <&blsp2_s <<
2668 <<
2669 status = "disabled"; <<
2670 #address-cells = <1>; <<
2671 #size-cells = <0>; <<
2672 }; <<
2673 <<
2674 blsp2_spi3: spi@c1b7000 { <<
2675 compatible = "qcom,sp <<
2676 reg = <0x0c1b7000 0x6 <<
2677 interrupts = <GIC_SPI <<
2678 <<
2679 clocks = <&gcc GCC_BL <<
2680 <&gcc GCC_BL <<
2681 clock-names = "core", <<
2682 dmas = <&blsp2_dma 10 <<
2683 dma-names = "tx", "rx <<
2684 pinctrl-names = "defa <<
2685 pinctrl-0 = <&blsp2_s <<
2686 <<
2687 status = "disabled"; <<
2688 #address-cells = <1>; <<
2689 #size-cells = <0>; <<
2690 }; <<
2691 <<
2692 blsp2_spi4: spi@c1b8000 { <<
2693 compatible = "qcom,sp <<
2694 reg = <0x0c1b8000 0x6 <<
2695 interrupts = <GIC_SPI <<
2696 <<
2697 clocks = <&gcc GCC_BL <<
2698 <&gcc GCC_BL <<
2699 clock-names = "core", <<
2700 dmas = <&blsp2_dma 12 <<
2701 dma-names = "tx", "rx <<
2702 pinctrl-names = "defa <<
2703 pinctrl-0 = <&blsp2_s <<
2704 <<
2705 status = "disabled"; <<
2706 #address-cells = <1>; <<
2707 #size-cells = <0>; <<
2708 }; <<
2709 <<
2710 blsp2_spi5: spi@c1b9000 { <<
2711 compatible = "qcom,sp <<
2712 reg = <0x0c1b9000 0x6 <<
2713 interrupts = <GIC_SPI <<
2714 <<
2715 clocks = <&gcc GCC_BL <<
2716 <&gcc GCC_BL <<
2717 clock-names = "core", <<
2718 dmas = <&blsp2_dma 14 <<
2719 dma-names = "tx", "rx <<
2720 pinctrl-names = "defa <<
2721 pinctrl-0 = <&blsp2_s <<
2722 <<
2723 status = "disabled"; <<
2724 #address-cells = <1>; <<
2725 #size-cells = <0>; <<
2726 }; <<
2727 <<
2728 blsp2_spi6: spi@c1ba000 { <<
2729 compatible = "qcom,sp <<
2730 reg = <0x0c1ba000 0x6 <<
2731 interrupts = <GIC_SPI <<
2732 <<
2733 clocks = <&gcc GCC_BL <<
2734 <&gcc GCC_BL <<
2735 clock-names = "core", <<
2736 dmas = <&blsp2_dma 16 <<
2737 dma-names = "tx", "rx <<
2738 pinctrl-names = "defa <<
2739 pinctrl-0 = <&blsp2_s <<
2740 <<
2741 status = "disabled"; <<
2742 #address-cells = <1>; <<
2743 #size-cells = <0>; <<
2744 }; <<
2745 <<
2746 mmcc: clock-controller@c8c000 <<
2747 compatible = "qcom,mm <<
2748 #clock-cells = <1>; <<
2749 #reset-cells = <1>; <<
2750 #power-domain-cells = <<
2751 reg = <0xc8c0000 0x40 <<
2752 <<
2753 clock-names = "xo", <<
2754 "gpll0" <<
2755 "dsi0ds <<
2756 "dsi0by <<
2757 "dsi1ds <<
2758 "dsi1by <<
2759 "hdmipl <<
2760 "dplink <<
2761 "dpvco" <<
2762 "gpll0_ <<
2763 clocks = <&rpmcc RPM_ <<
2764 <&gcc GCC_MM <<
2765 <&mdss_dsi0_ <<
2766 <&mdss_dsi0_ <<
2767 <&mdss_dsi1_ <<
2768 <&mdss_dsi1_ <<
2769 <0>, <<
2770 <0>, <<
2771 <0>, <<
2772 <&gcc GCC_MM <<
2773 }; <<
2774 <<
2775 mdss: display-subsystem@c9000 <<
2776 compatible = "qcom,ms <<
2777 reg = <0x0c900000 0x1 <<
2778 reg-names = "mdss"; <<
2779 <<
2780 interrupts = <GIC_SPI <<
2781 interrupt-controller; <<
2782 #interrupt-cells = <1 <<
2783 <<
2784 clocks = <&mmcc MDSS_ <<
2785 <&mmcc MDSS_ <<
2786 <&mmcc MDSS_ <<
2787 clock-names = "iface" <<
2788 "bus", <<
2789 "core"; <<
2790 <<
2791 power-domains = <&mmc <<
2792 iommus = <&mmss_smmu <<
2793 <<
2794 #address-cells = <1>; <<
2795 #size-cells = <1>; <<
2796 ranges; <<
2797 <<
2798 status = "disabled"; <<
2799 <<
2800 mdss_mdp: display-con <<
2801 compatible = <<
2802 reg = <0x0c90 <<
2803 <0x0c9a <<
2804 <0x0c9b <<
2805 <0x0c9b <<
2806 reg-names = " <<
2807 " <<
2808 " <<
2809 " <<
2810 <<
2811 interrupt-par <<
2812 interrupts = <<
2813 <<
2814 clocks = <&mm <<
2815 <&mm <<
2816 <&mm <<
2817 <&mm <<
2818 <&mm <<
2819 clock-names = <<
2820 <<
2821 <<
2822 <<
2823 <<
2824 <<
2825 assigned-cloc <<
2826 assigned-cloc <<
2827 <<
2828 operating-poi <<
2829 power-domains <<
2830 <<
2831 mdp_opp_table <<
2832 compa <<
2833 <<
2834 opp-1 <<
2835 <<
2836 <<
2837 }; <<
2838 <<
2839 opp-2 <<
2840 <<
2841 <<
2842 }; <<
2843 <<
2844 opp-3 <<
2845 <<
2846 <<
2847 }; <<
2848 <<
2849 opp-4 <<
2850 <<
2851 <<
2852 }; <<
2853 }; <<
2854 <<
2855 ports { <<
2856 #addr <<
2857 #size <<
2858 <<
2859 port@ <<
2860 <<
2861 <<
2862 <<
2863 <<
2864 <<
2865 }; <<
2866 <<
2867 port@ <<
2868 <<
2869 <<
2870 <<
2871 <<
2872 <<
2873 }; <<
2874 }; <<
2875 }; <<
2876 <<
2877 mdss_dsi0: dsi@c99400 <<
2878 compatible = <<
2879 reg = <0x0c99 <<
2880 reg-names = " <<
2881 <<
2882 interrupt-par <<
2883 interrupts = <<
2884 <<
2885 clocks = <&mm <<
2886 <&mm <<
2887 <&mm <<
2888 <&mm <<
2889 <&mm <<
2890 <&mm <<
2891 clock-names = <<
2892 <<
2893 <<
2894 <<
2895 <<
2896 <<
2897 assigned-cloc <<
2898 <<
2899 assigned-cloc <<
2900 <<
2901 <<
2902 operating-poi <<
2903 power-domains <<
2904 <<
2905 phys = <&mdss <<
2906 phy-names = " <<
2907 <<
2908 #address-cell <<
2909 #size-cells = <<
2910 <<
2911 status = "dis <<
2912 <<
2913 ports { <<
2914 #addr <<
2915 #size <<
2916 <<
2917 port@ <<
2918 <<
2919 <<
2920 <<
2921 <<
2922 <<
2923 }; <<
2924 <<
2925 port@ <<
2926 <<
2927 <<
2928 <<
2929 <<
2930 }; <<
2931 }; <<
2932 }; <<
2933 <<
2934 mdss_dsi0_phy: phy@c9 <<
2935 compatible = <<
2936 reg = <0x0c99 <<
2937 <0x0c99 <<
2938 <0x0c99 <<
2939 reg-names = " <<
2940 " <<
2941 " <<
2942 <<
2943 clocks = <&mm <<
2944 <&rp <<
2945 clock-names = <<
2946 <<
2947 #clock-cells <<
2948 #phy-cells = <<
2949 <<
2950 status = "dis <<
2951 }; <<
2952 <<
2953 mdss_dsi1: dsi@c99600 <<
2954 compatible = <<
2955 reg = <0x0c99 <<
2956 reg-names = " <<
2957 <<
2958 interrupt-par <<
2959 interrupts = <<
2960 <<
2961 clocks = <&mm <<
2962 <&mm <<
2963 <&mm <<
2964 <&mm <<
2965 <&mm <<
2966 <&mm <<
2967 clock-names = <<
2968 <<
2969 <<
2970 <<
2971 <<
2972 <<
2973 assigned-cloc <<
2974 <<
2975 assigned-cloc <<
2976 <<
2977 <<
2978 operating-poi <<
2979 power-domains <<
2980 <<
2981 phys = <&mdss <<
2982 phy-names = " <<
2983 <<
2984 #address-cell <<
2985 #size-cells = <<
2986 <<
2987 status = "dis <<
2988 <<
2989 ports { <<
2990 #addr <<
2991 #size <<
2992 <<
2993 port@ <<
2994 <<
2995 <<
2996 <<
2997 <<
2998 <<
2999 }; <<
3000 <<
3001 port@ <<
3002 <<
3003 <<
3004 <<
3005 <<
3006 }; <<
3007 }; <<
3008 }; <<
3009 <<
3010 mdss_dsi1_phy: phy@c9 <<
3011 compatible = <<
3012 reg = <0x0c99 <<
3013 <0x0c99 <<
3014 <0x0c99 <<
3015 reg-names = " <<
3016 " <<
3017 " <<
3018 <<
3019 clocks = <&mm <<
3020 <&rp <<
3021 clock-names = <<
3022 <<
3023 <<
3024 #clock-cells <<
3025 #phy-cells = <<
3026 <<
3027 status = "dis <<
3028 }; <<
3029 }; <<
3030 <<
3031 venus: video-codec@cc00000 { <<
3032 compatible = "qcom,ms <<
3033 reg = <0x0cc00000 0xf <<
3034 interrupts = <GIC_SPI <<
3035 power-domains = <&mmc <<
3036 clocks = <&mmcc VIDEO <<
3037 <&mmcc VIDEO <<
3038 <&mmcc VIDEO <<
3039 <&mmcc VIDEO <<
3040 clock-names = "core", <<
3041 iommus = <&mmss_smmu <<
3042 <&mmss_smmu <<
3043 <&mmss_smmu <<
3044 <&mmss_smmu <<
3045 <&mmss_smmu <<
3046 <&mmss_smmu <<
3047 <&mmss_smmu <<
3048 <&mmss_smmu <<
3049 <&mmss_smmu <<
3050 <&mmss_smmu <<
3051 <&mmss_smmu <<
3052 <&mmss_smmu <<
3053 <&mmss_smmu <<
3054 <&mmss_smmu <<
3055 <&mmss_smmu <<
3056 <&mmss_smmu <<
3057 <&mmss_smmu <<
3058 <&mmss_smmu <<
3059 <&mmss_smmu <<
3060 <&mmss_smmu <<
3061 memory-region = <&ven <<
3062 status = "disabled"; <<
3063 <<
3064 video-decoder { <<
3065 compatible = <<
3066 clocks = <&mm <<
3067 clock-names = <<
3068 power-domains <<
3069 }; <<
3070 <<
3071 video-encoder { <<
3072 compatible = <<
3073 clocks = <&mm <<
3074 clock-names = <<
3075 power-domains <<
3076 }; <<
3077 }; <<
3078 <<
3079 mmss_smmu: iommu@cd00000 { <<
3080 compatible = "qcom,ms <<
3081 reg = <0x0cd00000 0x4 <<
3082 #iommu-cells = <1>; <<
3083 <<
3084 clocks = <&mmcc MNOC_ <<
3085 <&mmcc BIMC_ <<
3086 <&mmcc BIMC_ <<
3087 clock-names = "iface- <<
3088 "iface- <<
3089 "bus-sm <<
3090 <<
3091 #global-interrupts = <<
3092 interrupts = <<
3093 <GIC_SPI 263 <<
3094 <GIC_SPI 266 <<
3095 <GIC_SPI 267 <<
3096 <GIC_SPI 268 <<
3097 <GIC_SPI 244 <<
3098 <GIC_SPI 245 <<
3099 <GIC_SPI 247 <<
3100 <GIC_SPI 248 <<
3101 <GIC_SPI 249 <<
3102 <GIC_SPI 250 <<
3103 <GIC_SPI 251 <<
3104 <GIC_SPI 252 <<
3105 <GIC_SPI 253 <<
3106 <GIC_SPI 254 <<
3107 <GIC_SPI 255 <<
3108 <GIC_SPI 256 <<
3109 <GIC_SPI 260 <<
3110 <GIC_SPI 261 <<
3111 <GIC_SPI 262 <<
3112 <GIC_SPI 272 <<
3113 <<
3114 power-domains = <&mmc <<
3115 }; <<
3116 <<
3117 remoteproc_adsp: remoteproc@1 2339 remoteproc_adsp: remoteproc@17300000 {
3118 compatible = "qcom,ms 2340 compatible = "qcom,msm8998-adsp-pas";
3119 reg = <0x17300000 0x4 2341 reg = <0x17300000 0x4040>;
3120 2342
3121 interrupts-extended = 2343 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
3122 2344 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3123 2345 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3124 2346 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3125 2347 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
3126 interrupt-names = "wd 2348 interrupt-names = "wdog", "fatal", "ready",
3127 "ha 2349 "handover", "stop-ack";
3128 2350
3129 clocks = <&rpmcc RPM_ 2351 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
3130 clock-names = "xo"; 2352 clock-names = "xo";
3131 2353
3132 memory-region = <&ads 2354 memory-region = <&adsp_mem>;
3133 2355
3134 qcom,smem-states = <& 2356 qcom,smem-states = <&adsp_smp2p_out 0>;
3135 qcom,smem-state-names 2357 qcom,smem-state-names = "stop";
3136 2358
3137 power-domains = <&rpm 2359 power-domains = <&rpmpd MSM8998_VDDCX>;
3138 power-domain-names = 2360 power-domain-names = "cx";
3139 2361
3140 status = "disabled"; 2362 status = "disabled";
3141 2363
3142 glink-edge { 2364 glink-edge {
3143 interrupts = 2365 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
3144 label = "lpas 2366 label = "lpass";
3145 qcom,remote-p 2367 qcom,remote-pid = <2>;
3146 mboxes = <&ap 2368 mboxes = <&apcs_glb 9>;
3147 }; 2369 };
3148 }; 2370 };
3149 2371
3150 apcs_glb: mailbox@17911000 { 2372 apcs_glb: mailbox@17911000 {
3151 compatible = "qcom,ms !! 2373 compatible = "qcom,msm8998-apcs-hmss-global";
3152 "qcom,ms <<
3153 reg = <0x17911000 0x1 2374 reg = <0x17911000 0x1000>;
3154 2375
3155 #mbox-cells = <1>; 2376 #mbox-cells = <1>;
3156 }; 2377 };
3157 2378
3158 timer@17920000 { 2379 timer@17920000 {
3159 #address-cells = <1>; 2380 #address-cells = <1>;
3160 #size-cells = <1>; 2381 #size-cells = <1>;
3161 ranges; 2382 ranges;
3162 compatible = "arm,arm 2383 compatible = "arm,armv7-timer-mem";
3163 reg = <0x17920000 0x1 2384 reg = <0x17920000 0x1000>;
3164 2385
3165 frame@17921000 { 2386 frame@17921000 {
3166 frame-number 2387 frame-number = <0>;
3167 interrupts = 2388 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
3168 2389 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
3169 reg = <0x1792 2390 reg = <0x17921000 0x1000>,
3170 <0x1792 2391 <0x17922000 0x1000>;
3171 }; 2392 };
3172 2393
3173 frame@17923000 { 2394 frame@17923000 {
3174 frame-number 2395 frame-number = <1>;
3175 interrupts = 2396 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
3176 reg = <0x1792 2397 reg = <0x17923000 0x1000>;
3177 status = "dis 2398 status = "disabled";
3178 }; 2399 };
3179 2400
3180 frame@17924000 { 2401 frame@17924000 {
3181 frame-number 2402 frame-number = <2>;
3182 interrupts = 2403 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
3183 reg = <0x1792 2404 reg = <0x17924000 0x1000>;
3184 status = "dis 2405 status = "disabled";
3185 }; 2406 };
3186 2407
3187 frame@17925000 { 2408 frame@17925000 {
3188 frame-number 2409 frame-number = <3>;
3189 interrupts = 2410 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3190 reg = <0x1792 2411 reg = <0x17925000 0x1000>;
3191 status = "dis 2412 status = "disabled";
3192 }; 2413 };
3193 2414
3194 frame@17926000 { 2415 frame@17926000 {
3195 frame-number 2416 frame-number = <4>;
3196 interrupts = 2417 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3197 reg = <0x1792 2418 reg = <0x17926000 0x1000>;
3198 status = "dis 2419 status = "disabled";
3199 }; 2420 };
3200 2421
3201 frame@17927000 { 2422 frame@17927000 {
3202 frame-number 2423 frame-number = <5>;
3203 interrupts = 2424 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3204 reg = <0x1792 2425 reg = <0x17927000 0x1000>;
3205 status = "dis 2426 status = "disabled";
3206 }; 2427 };
3207 2428
3208 frame@17928000 { 2429 frame@17928000 {
3209 frame-number 2430 frame-number = <6>;
3210 interrupts = 2431 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
3211 reg = <0x1792 2432 reg = <0x17928000 0x1000>;
3212 status = "dis 2433 status = "disabled";
3213 }; 2434 };
3214 }; 2435 };
3215 2436
3216 intc: interrupt-controller@17 2437 intc: interrupt-controller@17a00000 {
3217 compatible = "arm,gic 2438 compatible = "arm,gic-v3";
3218 reg = <0x17a00000 0x1 2439 reg = <0x17a00000 0x10000>, /* GICD */
3219 <0x17b00000 0x1 2440 <0x17b00000 0x100000>; /* GICR * 8 */
3220 #interrupt-cells = <3 2441 #interrupt-cells = <3>;
3221 #address-cells = <1>; 2442 #address-cells = <1>;
3222 #size-cells = <1>; 2443 #size-cells = <1>;
3223 ranges; 2444 ranges;
3224 interrupt-controller; 2445 interrupt-controller;
3225 #redistributor-region 2446 #redistributor-regions = <1>;
3226 redistributor-stride 2447 redistributor-stride = <0x0 0x20000>;
3227 interrupts = <GIC_PPI 2448 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3228 }; 2449 };
3229 2450
3230 wifi: wifi@18800000 { 2451 wifi: wifi@18800000 {
3231 compatible = "qcom,wc 2452 compatible = "qcom,wcn3990-wifi";
3232 status = "disabled"; 2453 status = "disabled";
3233 reg = <0x18800000 0x8 2454 reg = <0x18800000 0x800000>;
3234 reg-names = "membase" 2455 reg-names = "membase";
3235 memory-region = <&wla 2456 memory-region = <&wlan_msa_mem>;
3236 clocks = <&rpmcc RPM_ 2457 clocks = <&rpmcc RPM_SMD_RF_CLK2_PIN>;
3237 clock-names = "cxo_re 2458 clock-names = "cxo_ref_clk_pin";
3238 interrupts = 2459 interrupts =
3239 <GIC_SPI 413 2460 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
3240 <GIC_SPI 414 2461 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
3241 <GIC_SPI 415 2462 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
3242 <GIC_SPI 416 2463 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
3243 <GIC_SPI 417 2464 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
3244 <GIC_SPI 418 2465 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
3245 <GIC_SPI 420 2466 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
3246 <GIC_SPI 421 2467 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
3247 <GIC_SPI 422 2468 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
3248 <GIC_SPI 423 2469 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
3249 <GIC_SPI 424 2470 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
3250 <GIC_SPI 425 2471 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
3251 iommus = <&anoc2_smmu 2472 iommus = <&anoc2_smmu 0x1900>,
3252 <&anoc2_smmu 2473 <&anoc2_smmu 0x1901>;
3253 qcom,snoc-host-cap-8b 2474 qcom,snoc-host-cap-8bit-quirk;
3254 qcom,no-msa-ready-ind <<
3255 }; 2475 };
3256 }; 2476 };
3257 }; 2477 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.