1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2016, The Linux Foundation. A 2 /* Copyright (c) 2016, The Linux Foundation. All rights reserved. */
3 3
4 #include <dt-bindings/interrupt-controller/arm 4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-msm8998.h 5 #include <dt-bindings/clock/qcom,gcc-msm8998.h>
6 #include <dt-bindings/clock/qcom,gpucc-msm8998 6 #include <dt-bindings/clock/qcom,gpucc-msm8998.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8998. 7 #include <dt-bindings/clock/qcom,mmcc-msm8998.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h> 8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/firmware/qcom,scm.h> <<
10 #include <dt-bindings/power/qcom-rpmpd.h> 9 #include <dt-bindings/power/qcom-rpmpd.h>
11 #include <dt-bindings/gpio/gpio.h> 10 #include <dt-bindings/gpio/gpio.h>
12 11
13 / { 12 / {
14 interrupt-parent = <&intc>; 13 interrupt-parent = <&intc>;
15 14
16 qcom,msm-id = <292 0x0>; 15 qcom,msm-id = <292 0x0>;
17 16
18 #address-cells = <2>; 17 #address-cells = <2>;
19 #size-cells = <2>; 18 #size-cells = <2>;
20 19
21 chosen { }; 20 chosen { };
22 21
23 memory@80000000 { 22 memory@80000000 {
24 device_type = "memory"; 23 device_type = "memory";
25 /* We expect the bootloader to 24 /* We expect the bootloader to fill in the reg */
26 reg = <0x0 0x80000000 0x0 0x0> 25 reg = <0x0 0x80000000 0x0 0x0>;
27 }; 26 };
28 27
29 reserved-memory { 28 reserved-memory {
30 #address-cells = <2>; 29 #address-cells = <2>;
31 #size-cells = <2>; 30 #size-cells = <2>;
32 ranges; 31 ranges;
33 32
34 hyp_mem: memory@85800000 { 33 hyp_mem: memory@85800000 {
35 reg = <0x0 0x85800000 34 reg = <0x0 0x85800000 0x0 0x600000>;
36 no-map; 35 no-map;
37 }; 36 };
38 37
39 xbl_mem: memory@85e00000 { 38 xbl_mem: memory@85e00000 {
40 reg = <0x0 0x85e00000 39 reg = <0x0 0x85e00000 0x0 0x100000>;
41 no-map; 40 no-map;
42 }; 41 };
43 42
44 smem_mem: smem-mem@86000000 { 43 smem_mem: smem-mem@86000000 {
45 reg = <0x0 0x86000000 44 reg = <0x0 0x86000000 0x0 0x200000>;
46 no-map; 45 no-map;
47 }; 46 };
48 47
49 tz_mem: memory@86200000 { 48 tz_mem: memory@86200000 {
50 reg = <0x0 0x86200000 49 reg = <0x0 0x86200000 0x0 0x2d00000>;
51 no-map; 50 no-map;
52 }; 51 };
53 52
54 rmtfs_mem: memory@88f00000 { 53 rmtfs_mem: memory@88f00000 {
55 compatible = "qcom,rmt 54 compatible = "qcom,rmtfs-mem";
56 reg = <0x0 0x88f00000 55 reg = <0x0 0x88f00000 0x0 0x200000>;
57 no-map; 56 no-map;
58 57
59 qcom,client-id = <1>; 58 qcom,client-id = <1>;
60 qcom,vmid = <QCOM_SCM_ !! 59 qcom,vmid = <15>;
61 }; 60 };
62 61
63 spss_mem: memory@8ab00000 { 62 spss_mem: memory@8ab00000 {
64 reg = <0x0 0x8ab00000 63 reg = <0x0 0x8ab00000 0x0 0x700000>;
65 no-map; 64 no-map;
66 }; 65 };
67 66
68 adsp_mem: memory@8b200000 { 67 adsp_mem: memory@8b200000 {
69 reg = <0x0 0x8b200000 68 reg = <0x0 0x8b200000 0x0 0x1a00000>;
70 no-map; 69 no-map;
71 }; 70 };
72 71
73 mpss_mem: memory@8cc00000 { 72 mpss_mem: memory@8cc00000 {
74 reg = <0x0 0x8cc00000 73 reg = <0x0 0x8cc00000 0x0 0x7000000>;
75 no-map; 74 no-map;
76 }; 75 };
77 76
78 venus_mem: memory@93c00000 { 77 venus_mem: memory@93c00000 {
79 reg = <0x0 0x93c00000 78 reg = <0x0 0x93c00000 0x0 0x500000>;
80 no-map; 79 no-map;
81 }; 80 };
82 81
83 mba_mem: memory@94100000 { 82 mba_mem: memory@94100000 {
84 reg = <0x0 0x94100000 83 reg = <0x0 0x94100000 0x0 0x200000>;
85 no-map; 84 no-map;
86 }; 85 };
87 86
88 slpi_mem: memory@94300000 { 87 slpi_mem: memory@94300000 {
89 reg = <0x0 0x94300000 88 reg = <0x0 0x94300000 0x0 0xf00000>;
90 no-map; 89 no-map;
91 }; 90 };
92 91
93 ipa_fw_mem: memory@95200000 { 92 ipa_fw_mem: memory@95200000 {
94 reg = <0x0 0x95200000 93 reg = <0x0 0x95200000 0x0 0x10000>;
95 no-map; 94 no-map;
96 }; 95 };
97 96
98 ipa_gsi_mem: memory@95210000 { 97 ipa_gsi_mem: memory@95210000 {
99 reg = <0x0 0x95210000 98 reg = <0x0 0x95210000 0x0 0x5000>;
100 no-map; 99 no-map;
101 }; 100 };
102 101
103 gpu_mem: memory@95600000 { 102 gpu_mem: memory@95600000 {
104 reg = <0x0 0x95600000 103 reg = <0x0 0x95600000 0x0 0x100000>;
105 no-map; 104 no-map;
106 }; 105 };
107 106
108 wlan_msa_mem: memory@95700000 107 wlan_msa_mem: memory@95700000 {
109 reg = <0x0 0x95700000 108 reg = <0x0 0x95700000 0x0 0x100000>;
110 no-map; 109 no-map;
111 }; 110 };
112 <<
113 mdata_mem: mpss-metadata { <<
114 alloc-ranges = <0x0 0x <<
115 size = <0x0 0x4000>; <<
116 no-map; <<
117 }; <<
118 }; 111 };
119 112
120 clocks { 113 clocks {
121 xo: xo-board { 114 xo: xo-board {
122 compatible = "fixed-cl 115 compatible = "fixed-clock";
123 #clock-cells = <0>; 116 #clock-cells = <0>;
124 clock-frequency = <192 117 clock-frequency = <19200000>;
125 clock-output-names = " 118 clock-output-names = "xo_board";
126 }; 119 };
127 120
128 sleep_clk: sleep-clk { 121 sleep_clk: sleep-clk {
129 compatible = "fixed-cl 122 compatible = "fixed-clock";
130 #clock-cells = <0>; 123 #clock-cells = <0>;
131 clock-frequency = <327 124 clock-frequency = <32764>;
132 }; 125 };
133 }; 126 };
134 127
135 cpus { 128 cpus {
136 #address-cells = <2>; 129 #address-cells = <2>;
137 #size-cells = <0>; 130 #size-cells = <0>;
138 131
139 CPU0: cpu@0 { 132 CPU0: cpu@0 {
140 device_type = "cpu"; 133 device_type = "cpu";
141 compatible = "qcom,kry 134 compatible = "qcom,kryo280";
142 reg = <0x0 0x0>; 135 reg = <0x0 0x0>;
143 enable-method = "psci" 136 enable-method = "psci";
144 capacity-dmips-mhz = < 137 capacity-dmips-mhz = <1024>;
145 cpu-idle-states = <&LI 138 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
146 next-level-cache = <&L 139 next-level-cache = <&L2_0>;
147 L2_0: l2-cache { 140 L2_0: l2-cache {
148 compatible = " !! 141 compatible = "arm,arch-cache";
149 cache-level = 142 cache-level = <2>;
150 cache-unified; !! 143 };
>> 144 L1_I_0: l1-icache {
>> 145 compatible = "arm,arch-cache";
>> 146 };
>> 147 L1_D_0: l1-dcache {
>> 148 compatible = "arm,arch-cache";
151 }; 149 };
152 }; 150 };
153 151
154 CPU1: cpu@1 { 152 CPU1: cpu@1 {
155 device_type = "cpu"; 153 device_type = "cpu";
156 compatible = "qcom,kry 154 compatible = "qcom,kryo280";
157 reg = <0x0 0x1>; 155 reg = <0x0 0x1>;
158 enable-method = "psci" 156 enable-method = "psci";
159 capacity-dmips-mhz = < 157 capacity-dmips-mhz = <1024>;
160 cpu-idle-states = <&LI 158 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
161 next-level-cache = <&L 159 next-level-cache = <&L2_0>;
>> 160 L1_I_1: l1-icache {
>> 161 compatible = "arm,arch-cache";
>> 162 };
>> 163 L1_D_1: l1-dcache {
>> 164 compatible = "arm,arch-cache";
>> 165 };
162 }; 166 };
163 167
164 CPU2: cpu@2 { 168 CPU2: cpu@2 {
165 device_type = "cpu"; 169 device_type = "cpu";
166 compatible = "qcom,kry 170 compatible = "qcom,kryo280";
167 reg = <0x0 0x2>; 171 reg = <0x0 0x2>;
168 enable-method = "psci" 172 enable-method = "psci";
169 capacity-dmips-mhz = < 173 capacity-dmips-mhz = <1024>;
170 cpu-idle-states = <&LI 174 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
171 next-level-cache = <&L 175 next-level-cache = <&L2_0>;
>> 176 L1_I_2: l1-icache {
>> 177 compatible = "arm,arch-cache";
>> 178 };
>> 179 L1_D_2: l1-dcache {
>> 180 compatible = "arm,arch-cache";
>> 181 };
172 }; 182 };
173 183
174 CPU3: cpu@3 { 184 CPU3: cpu@3 {
175 device_type = "cpu"; 185 device_type = "cpu";
176 compatible = "qcom,kry 186 compatible = "qcom,kryo280";
177 reg = <0x0 0x3>; 187 reg = <0x0 0x3>;
178 enable-method = "psci" 188 enable-method = "psci";
179 capacity-dmips-mhz = < 189 capacity-dmips-mhz = <1024>;
180 cpu-idle-states = <&LI 190 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
181 next-level-cache = <&L 191 next-level-cache = <&L2_0>;
>> 192 L1_I_3: l1-icache {
>> 193 compatible = "arm,arch-cache";
>> 194 };
>> 195 L1_D_3: l1-dcache {
>> 196 compatible = "arm,arch-cache";
>> 197 };
182 }; 198 };
183 199
184 CPU4: cpu@100 { 200 CPU4: cpu@100 {
185 device_type = "cpu"; 201 device_type = "cpu";
186 compatible = "qcom,kry 202 compatible = "qcom,kryo280";
187 reg = <0x0 0x100>; 203 reg = <0x0 0x100>;
188 enable-method = "psci" 204 enable-method = "psci";
189 capacity-dmips-mhz = < 205 capacity-dmips-mhz = <1536>;
190 cpu-idle-states = <&BI 206 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
191 next-level-cache = <&L 207 next-level-cache = <&L2_1>;
192 L2_1: l2-cache { 208 L2_1: l2-cache {
193 compatible = " !! 209 compatible = "arm,arch-cache";
194 cache-level = 210 cache-level = <2>;
195 cache-unified; !! 211 };
>> 212 L1_I_100: l1-icache {
>> 213 compatible = "arm,arch-cache";
>> 214 };
>> 215 L1_D_100: l1-dcache {
>> 216 compatible = "arm,arch-cache";
196 }; 217 };
197 }; 218 };
198 219
199 CPU5: cpu@101 { 220 CPU5: cpu@101 {
200 device_type = "cpu"; 221 device_type = "cpu";
201 compatible = "qcom,kry 222 compatible = "qcom,kryo280";
202 reg = <0x0 0x101>; 223 reg = <0x0 0x101>;
203 enable-method = "psci" 224 enable-method = "psci";
204 capacity-dmips-mhz = < 225 capacity-dmips-mhz = <1536>;
205 cpu-idle-states = <&BI 226 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
206 next-level-cache = <&L 227 next-level-cache = <&L2_1>;
>> 228 L1_I_101: l1-icache {
>> 229 compatible = "arm,arch-cache";
>> 230 };
>> 231 L1_D_101: l1-dcache {
>> 232 compatible = "arm,arch-cache";
>> 233 };
207 }; 234 };
208 235
209 CPU6: cpu@102 { 236 CPU6: cpu@102 {
210 device_type = "cpu"; 237 device_type = "cpu";
211 compatible = "qcom,kry 238 compatible = "qcom,kryo280";
212 reg = <0x0 0x102>; 239 reg = <0x0 0x102>;
213 enable-method = "psci" 240 enable-method = "psci";
214 capacity-dmips-mhz = < 241 capacity-dmips-mhz = <1536>;
215 cpu-idle-states = <&BI 242 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
216 next-level-cache = <&L 243 next-level-cache = <&L2_1>;
>> 244 L1_I_102: l1-icache {
>> 245 compatible = "arm,arch-cache";
>> 246 };
>> 247 L1_D_102: l1-dcache {
>> 248 compatible = "arm,arch-cache";
>> 249 };
217 }; 250 };
218 251
219 CPU7: cpu@103 { 252 CPU7: cpu@103 {
220 device_type = "cpu"; 253 device_type = "cpu";
221 compatible = "qcom,kry 254 compatible = "qcom,kryo280";
222 reg = <0x0 0x103>; 255 reg = <0x0 0x103>;
223 enable-method = "psci" 256 enable-method = "psci";
224 capacity-dmips-mhz = < 257 capacity-dmips-mhz = <1536>;
225 cpu-idle-states = <&BI 258 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
226 next-level-cache = <&L 259 next-level-cache = <&L2_1>;
>> 260 L1_I_103: l1-icache {
>> 261 compatible = "arm,arch-cache";
>> 262 };
>> 263 L1_D_103: l1-dcache {
>> 264 compatible = "arm,arch-cache";
>> 265 };
227 }; 266 };
228 267
229 cpu-map { 268 cpu-map {
230 cluster0 { 269 cluster0 {
231 core0 { 270 core0 {
232 cpu = 271 cpu = <&CPU0>;
233 }; 272 };
234 273
235 core1 { 274 core1 {
236 cpu = 275 cpu = <&CPU1>;
237 }; 276 };
238 277
239 core2 { 278 core2 {
240 cpu = 279 cpu = <&CPU2>;
241 }; 280 };
242 281
243 core3 { 282 core3 {
244 cpu = 283 cpu = <&CPU3>;
245 }; 284 };
246 }; 285 };
247 286
248 cluster1 { 287 cluster1 {
249 core0 { 288 core0 {
250 cpu = 289 cpu = <&CPU4>;
251 }; 290 };
252 291
253 core1 { 292 core1 {
254 cpu = 293 cpu = <&CPU5>;
255 }; 294 };
256 295
257 core2 { 296 core2 {
258 cpu = 297 cpu = <&CPU6>;
259 }; 298 };
260 299
261 core3 { 300 core3 {
262 cpu = 301 cpu = <&CPU7>;
263 }; 302 };
264 }; 303 };
265 }; 304 };
266 305
267 idle-states { 306 idle-states {
268 entry-method = "psci"; 307 entry-method = "psci";
269 308
270 LITTLE_CPU_SLEEP_0: cp 309 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
271 compatible = " 310 compatible = "arm,idle-state";
272 idle-state-nam 311 idle-state-name = "little-retention";
273 /* CPU Retenti 312 /* CPU Retention (C2D), L2 Active */
274 arm,psci-suspe 313 arm,psci-suspend-param = <0x00000002>;
275 entry-latency- 314 entry-latency-us = <81>;
276 exit-latency-u 315 exit-latency-us = <86>;
277 min-residency- 316 min-residency-us = <504>;
278 }; 317 };
279 318
280 LITTLE_CPU_SLEEP_1: cp 319 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
281 compatible = " 320 compatible = "arm,idle-state";
282 idle-state-nam 321 idle-state-name = "little-power-collapse";
283 /* CPU + L2 Po 322 /* CPU + L2 Power Collapse (C3, D4) */
284 arm,psci-suspe 323 arm,psci-suspend-param = <0x40000003>;
285 entry-latency- 324 entry-latency-us = <814>;
286 exit-latency-u 325 exit-latency-us = <4562>;
287 min-residency- 326 min-residency-us = <9183>;
288 local-timer-st 327 local-timer-stop;
289 }; 328 };
290 329
291 BIG_CPU_SLEEP_0: cpu-s 330 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
292 compatible = " 331 compatible = "arm,idle-state";
293 idle-state-nam 332 idle-state-name = "big-retention";
294 /* CPU Retenti 333 /* CPU Retention (C2D), L2 Active */
295 arm,psci-suspe 334 arm,psci-suspend-param = <0x00000002>;
296 entry-latency- 335 entry-latency-us = <79>;
297 exit-latency-u 336 exit-latency-us = <82>;
298 min-residency- 337 min-residency-us = <1302>;
299 }; 338 };
300 339
301 BIG_CPU_SLEEP_1: cpu-s 340 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
302 compatible = " 341 compatible = "arm,idle-state";
303 idle-state-nam 342 idle-state-name = "big-power-collapse";
304 /* CPU + L2 Po 343 /* CPU + L2 Power Collapse (C3, D4) */
305 arm,psci-suspe 344 arm,psci-suspend-param = <0x40000003>;
306 entry-latency- 345 entry-latency-us = <724>;
307 exit-latency-u 346 exit-latency-us = <2027>;
308 min-residency- 347 min-residency-us = <9419>;
309 local-timer-st 348 local-timer-stop;
310 }; 349 };
311 }; 350 };
312 }; 351 };
313 352
314 firmware { 353 firmware {
315 scm { 354 scm {
316 compatible = "qcom,scm 355 compatible = "qcom,scm-msm8998", "qcom,scm";
317 }; 356 };
318 }; 357 };
319 358
320 dsi_opp_table: opp-table-dsi { !! 359 tcsr_mutex: hwlock {
321 compatible = "operating-points !! 360 compatible = "qcom,tcsr-mutex";
322 !! 361 syscon = <&tcsr_mutex_regs 0 0x1000>;
323 opp-131250000 { !! 362 #hwlock-cells = <1>;
324 opp-hz = /bits/ 64 <13 <<
325 required-opps = <&rpmp <<
326 }; <<
327 <<
328 opp-210000000 { <<
329 opp-hz = /bits/ 64 <21 <<
330 required-opps = <&rpmp <<
331 }; <<
332 <<
333 opp-312500000 { <<
334 opp-hz = /bits/ 64 <31 <<
335 required-opps = <&rpmp <<
336 }; <<
337 }; 363 };
338 364
339 psci { 365 psci {
340 compatible = "arm,psci-1.0"; 366 compatible = "arm,psci-1.0";
341 method = "smc"; 367 method = "smc";
342 }; 368 };
343 369
344 rpm: remoteproc { !! 370 rpm-glink {
345 compatible = "qcom,msm8998-rpm !! 371 compatible = "qcom,glink-rpm";
>> 372
>> 373 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
>> 374 qcom,rpm-msg-ram = <&rpm_msg_ram>;
>> 375 mboxes = <&apcs_glb 0>;
>> 376
>> 377 rpm_requests: rpm-requests {
>> 378 compatible = "qcom,rpm-msm8998";
>> 379 qcom,glink-channels = "rpm_requests";
>> 380
>> 381 rpmcc: clock-controller {
>> 382 compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc";
>> 383 #clock-cells = <1>;
>> 384 };
>> 385
>> 386 rpmpd: power-controller {
>> 387 compatible = "qcom,msm8998-rpmpd";
>> 388 #power-domain-cells = <1>;
>> 389 operating-points-v2 = <&rpmpd_opp_table>;
>> 390
>> 391 rpmpd_opp_table: opp-table {
>> 392 compatible = "operating-points-v2";
>> 393
>> 394 rpmpd_opp_ret: opp1 {
>> 395 opp-level = <RPM_SMD_LEVEL_RETENTION>;
>> 396 };
>> 397
>> 398 rpmpd_opp_ret_plus: opp2 {
>> 399 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
>> 400 };
346 401
347 glink-edge { !! 402 rpmpd_opp_min_svs: opp3 {
348 compatible = "qcom,gli !! 403 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
>> 404 };
349 405
350 interrupts = <GIC_SPI !! 406 rpmpd_opp_low_svs: opp4 {
351 qcom,rpm-msg-ram = <&r !! 407 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
352 mboxes = <&apcs_glb 0> !! 408 };
353 !! 409
354 rpm_requests: rpm-requ !! 410 rpmpd_opp_svs: opp5 {
355 compatible = " !! 411 opp-level = <RPM_SMD_LEVEL_SVS>;
356 qcom,glink-cha !! 412 };
357 !! 413
358 rpmcc: clock-c !! 414 rpmpd_opp_svs_plus: opp6 {
359 compat !! 415 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
360 clocks !! 416 };
361 clock- !! 417
362 #clock !! 418 rpmpd_opp_nom: opp7 {
363 }; !! 419 opp-level = <RPM_SMD_LEVEL_NOM>;
364 !! 420 };
365 rpmpd: power-c !! 421
366 compat !! 422 rpmpd_opp_nom_plus: opp8 {
367 #power !! 423 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
368 operat !! 424 };
369 !! 425
370 rpmpd_ !! 426 rpmpd_opp_turbo: opp9 {
371 !! 427 opp-level = <RPM_SMD_LEVEL_TURBO>;
372 !! 428 };
373 !! 429
374 !! 430 rpmpd_opp_turbo_plus: opp10 {
375 !! 431 opp-level = <RPM_SMD_LEVEL_BINNING>;
376 <<
377 <<
378 <<
379 <<
380 <<
381 <<
382 <<
383 <<
384 <<
385 <<
386 <<
387 <<
388 <<
389 <<
390 <<
391 <<
392 <<
393 <<
394 <<
395 <<
396 <<
397 <<
398 <<
399 <<
400 <<
401 <<
402 <<
403 <<
404 <<
405 <<
406 <<
407 <<
408 <<
409 <<
410 <<
411 <<
412 }; 432 };
413 }; 433 };
414 }; 434 };
415 }; 435 };
416 }; 436 };
417 437
418 smem { 438 smem {
419 compatible = "qcom,smem"; 439 compatible = "qcom,smem";
420 memory-region = <&smem_mem>; 440 memory-region = <&smem_mem>;
421 hwlocks = <&tcsr_mutex 3>; 441 hwlocks = <&tcsr_mutex 3>;
422 }; 442 };
423 443
424 smp2p-lpass { 444 smp2p-lpass {
425 compatible = "qcom,smp2p"; 445 compatible = "qcom,smp2p";
426 qcom,smem = <443>, <429>; 446 qcom,smem = <443>, <429>;
427 447
428 interrupts = <GIC_SPI 158 IRQ_ 448 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
429 449
430 mboxes = <&apcs_glb 10>; 450 mboxes = <&apcs_glb 10>;
431 451
432 qcom,local-pid = <0>; 452 qcom,local-pid = <0>;
433 qcom,remote-pid = <2>; 453 qcom,remote-pid = <2>;
434 454
435 adsp_smp2p_out: master-kernel 455 adsp_smp2p_out: master-kernel {
436 qcom,entry-name = "mas 456 qcom,entry-name = "master-kernel";
437 #qcom,smem-state-cells 457 #qcom,smem-state-cells = <1>;
438 }; 458 };
439 459
440 adsp_smp2p_in: slave-kernel { 460 adsp_smp2p_in: slave-kernel {
441 qcom,entry-name = "sla 461 qcom,entry-name = "slave-kernel";
442 462
443 interrupt-controller; 463 interrupt-controller;
444 #interrupt-cells = <2> 464 #interrupt-cells = <2>;
445 }; 465 };
446 }; 466 };
447 467
448 smp2p-mpss { 468 smp2p-mpss {
449 compatible = "qcom,smp2p"; 469 compatible = "qcom,smp2p";
450 qcom,smem = <435>, <428>; 470 qcom,smem = <435>, <428>;
451 interrupts = <GIC_SPI 451 IRQ_ 471 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
452 mboxes = <&apcs_glb 14>; 472 mboxes = <&apcs_glb 14>;
453 qcom,local-pid = <0>; 473 qcom,local-pid = <0>;
454 qcom,remote-pid = <1>; 474 qcom,remote-pid = <1>;
455 475
456 modem_smp2p_out: master-kernel 476 modem_smp2p_out: master-kernel {
457 qcom,entry-name = "mas 477 qcom,entry-name = "master-kernel";
458 #qcom,smem-state-cells 478 #qcom,smem-state-cells = <1>;
459 }; 479 };
460 480
461 modem_smp2p_in: slave-kernel { 481 modem_smp2p_in: slave-kernel {
462 qcom,entry-name = "sla 482 qcom,entry-name = "slave-kernel";
463 interrupt-controller; 483 interrupt-controller;
464 #interrupt-cells = <2> 484 #interrupt-cells = <2>;
465 }; 485 };
466 }; 486 };
467 487
468 smp2p-slpi { 488 smp2p-slpi {
469 compatible = "qcom,smp2p"; 489 compatible = "qcom,smp2p";
470 qcom,smem = <481>, <430>; 490 qcom,smem = <481>, <430>;
471 interrupts = <GIC_SPI 178 IRQ_ 491 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
472 mboxes = <&apcs_glb 26>; 492 mboxes = <&apcs_glb 26>;
473 qcom,local-pid = <0>; 493 qcom,local-pid = <0>;
474 qcom,remote-pid = <3>; 494 qcom,remote-pid = <3>;
475 495
476 slpi_smp2p_out: master-kernel 496 slpi_smp2p_out: master-kernel {
477 qcom,entry-name = "mas 497 qcom,entry-name = "master-kernel";
478 #qcom,smem-state-cells 498 #qcom,smem-state-cells = <1>;
479 }; 499 };
480 500
481 slpi_smp2p_in: slave-kernel { 501 slpi_smp2p_in: slave-kernel {
482 qcom,entry-name = "sla 502 qcom,entry-name = "slave-kernel";
483 interrupt-controller; 503 interrupt-controller;
484 #interrupt-cells = <2> 504 #interrupt-cells = <2>;
485 }; 505 };
486 }; 506 };
487 507
488 thermal-zones { 508 thermal-zones {
489 cpu0-thermal { 509 cpu0-thermal {
490 polling-delay-passive 510 polling-delay-passive = <250>;
>> 511 polling-delay = <1000>;
491 512
492 thermal-sensors = <&ts 513 thermal-sensors = <&tsens0 1>;
493 514
494 trips { 515 trips {
495 cpu0_alert0: t 516 cpu0_alert0: trip-point0 {
496 temper 517 temperature = <75000>;
497 hyster 518 hysteresis = <2000>;
498 type = 519 type = "passive";
499 }; 520 };
500 521
501 cpu0_crit: cpu !! 522 cpu0_crit: cpu_crit {
502 temper 523 temperature = <110000>;
503 hyster 524 hysteresis = <2000>;
504 type = 525 type = "critical";
505 }; 526 };
506 }; 527 };
507 }; 528 };
508 529
509 cpu1-thermal { 530 cpu1-thermal {
510 polling-delay-passive 531 polling-delay-passive = <250>;
>> 532 polling-delay = <1000>;
511 533
512 thermal-sensors = <&ts 534 thermal-sensors = <&tsens0 2>;
513 535
514 trips { 536 trips {
515 cpu1_alert0: t 537 cpu1_alert0: trip-point0 {
516 temper 538 temperature = <75000>;
517 hyster 539 hysteresis = <2000>;
518 type = 540 type = "passive";
519 }; 541 };
520 542
521 cpu1_crit: cpu !! 543 cpu1_crit: cpu_crit {
522 temper 544 temperature = <110000>;
523 hyster 545 hysteresis = <2000>;
524 type = 546 type = "critical";
525 }; 547 };
526 }; 548 };
527 }; 549 };
528 550
529 cpu2-thermal { 551 cpu2-thermal {
530 polling-delay-passive 552 polling-delay-passive = <250>;
>> 553 polling-delay = <1000>;
531 554
532 thermal-sensors = <&ts 555 thermal-sensors = <&tsens0 3>;
533 556
534 trips { 557 trips {
535 cpu2_alert0: t 558 cpu2_alert0: trip-point0 {
536 temper 559 temperature = <75000>;
537 hyster 560 hysteresis = <2000>;
538 type = 561 type = "passive";
539 }; 562 };
540 563
541 cpu2_crit: cpu !! 564 cpu2_crit: cpu_crit {
542 temper 565 temperature = <110000>;
543 hyster 566 hysteresis = <2000>;
544 type = 567 type = "critical";
545 }; 568 };
546 }; 569 };
547 }; 570 };
548 571
549 cpu3-thermal { 572 cpu3-thermal {
550 polling-delay-passive 573 polling-delay-passive = <250>;
>> 574 polling-delay = <1000>;
551 575
552 thermal-sensors = <&ts 576 thermal-sensors = <&tsens0 4>;
553 577
554 trips { 578 trips {
555 cpu3_alert0: t 579 cpu3_alert0: trip-point0 {
556 temper 580 temperature = <75000>;
557 hyster 581 hysteresis = <2000>;
558 type = 582 type = "passive";
559 }; 583 };
560 584
561 cpu3_crit: cpu !! 585 cpu3_crit: cpu_crit {
562 temper 586 temperature = <110000>;
563 hyster 587 hysteresis = <2000>;
564 type = 588 type = "critical";
565 }; 589 };
566 }; 590 };
567 }; 591 };
568 592
569 cpu4-thermal { 593 cpu4-thermal {
570 polling-delay-passive 594 polling-delay-passive = <250>;
>> 595 polling-delay = <1000>;
571 596
572 thermal-sensors = <&ts 597 thermal-sensors = <&tsens0 7>;
573 598
574 trips { 599 trips {
575 cpu4_alert0: t 600 cpu4_alert0: trip-point0 {
576 temper 601 temperature = <75000>;
577 hyster 602 hysteresis = <2000>;
578 type = 603 type = "passive";
579 }; 604 };
580 605
581 cpu4_crit: cpu !! 606 cpu4_crit: cpu_crit {
582 temper 607 temperature = <110000>;
583 hyster 608 hysteresis = <2000>;
584 type = 609 type = "critical";
585 }; 610 };
586 }; 611 };
587 }; 612 };
588 613
589 cpu5-thermal { 614 cpu5-thermal {
590 polling-delay-passive 615 polling-delay-passive = <250>;
>> 616 polling-delay = <1000>;
591 617
592 thermal-sensors = <&ts 618 thermal-sensors = <&tsens0 8>;
593 619
594 trips { 620 trips {
595 cpu5_alert0: t 621 cpu5_alert0: trip-point0 {
596 temper 622 temperature = <75000>;
597 hyster 623 hysteresis = <2000>;
598 type = 624 type = "passive";
599 }; 625 };
600 626
601 cpu5_crit: cpu !! 627 cpu5_crit: cpu_crit {
602 temper 628 temperature = <110000>;
603 hyster 629 hysteresis = <2000>;
604 type = 630 type = "critical";
605 }; 631 };
606 }; 632 };
607 }; 633 };
608 634
609 cpu6-thermal { 635 cpu6-thermal {
610 polling-delay-passive 636 polling-delay-passive = <250>;
>> 637 polling-delay = <1000>;
611 638
612 thermal-sensors = <&ts 639 thermal-sensors = <&tsens0 9>;
613 640
614 trips { 641 trips {
615 cpu6_alert0: t 642 cpu6_alert0: trip-point0 {
616 temper 643 temperature = <75000>;
617 hyster 644 hysteresis = <2000>;
618 type = 645 type = "passive";
619 }; 646 };
620 647
621 cpu6_crit: cpu !! 648 cpu6_crit: cpu_crit {
622 temper 649 temperature = <110000>;
623 hyster 650 hysteresis = <2000>;
624 type = 651 type = "critical";
625 }; 652 };
626 }; 653 };
627 }; 654 };
628 655
629 cpu7-thermal { 656 cpu7-thermal {
630 polling-delay-passive 657 polling-delay-passive = <250>;
>> 658 polling-delay = <1000>;
631 659
632 thermal-sensors = <&ts 660 thermal-sensors = <&tsens0 10>;
633 661
634 trips { 662 trips {
635 cpu7_alert0: t 663 cpu7_alert0: trip-point0 {
636 temper 664 temperature = <75000>;
637 hyster 665 hysteresis = <2000>;
638 type = 666 type = "passive";
639 }; 667 };
640 668
641 cpu7_crit: cpu !! 669 cpu7_crit: cpu_crit {
642 temper 670 temperature = <110000>;
643 hyster 671 hysteresis = <2000>;
644 type = 672 type = "critical";
645 }; 673 };
646 }; 674 };
647 }; 675 };
648 676
649 gpu-bottom-thermal { !! 677 gpu-thermal-bottom {
650 polling-delay-passive 678 polling-delay-passive = <250>;
>> 679 polling-delay = <1000>;
651 680
652 thermal-sensors = <&ts 681 thermal-sensors = <&tsens0 12>;
653 682
654 trips { 683 trips {
655 gpu1_alert0: t 684 gpu1_alert0: trip-point0 {
656 temper 685 temperature = <90000>;
657 hyster 686 hysteresis = <2000>;
658 type = 687 type = "hot";
659 }; 688 };
660 }; 689 };
661 }; 690 };
662 691
663 gpu-top-thermal { !! 692 gpu-thermal-top {
664 polling-delay-passive 693 polling-delay-passive = <250>;
>> 694 polling-delay = <1000>;
665 695
666 thermal-sensors = <&ts 696 thermal-sensors = <&tsens0 13>;
667 697
668 trips { 698 trips {
669 gpu2_alert0: t 699 gpu2_alert0: trip-point0 {
670 temper 700 temperature = <90000>;
671 hyster 701 hysteresis = <2000>;
672 type = 702 type = "hot";
673 }; 703 };
674 }; 704 };
675 }; 705 };
676 706
677 clust0-mhm-thermal { 707 clust0-mhm-thermal {
678 polling-delay-passive 708 polling-delay-passive = <250>;
>> 709 polling-delay = <1000>;
679 710
680 thermal-sensors = <&ts 711 thermal-sensors = <&tsens0 5>;
681 712
682 trips { 713 trips {
683 cluster0_mhm_a 714 cluster0_mhm_alert0: trip-point0 {
684 temper 715 temperature = <90000>;
685 hyster 716 hysteresis = <2000>;
686 type = 717 type = "hot";
687 }; 718 };
688 }; 719 };
689 }; 720 };
690 721
691 clust1-mhm-thermal { 722 clust1-mhm-thermal {
692 polling-delay-passive 723 polling-delay-passive = <250>;
>> 724 polling-delay = <1000>;
693 725
694 thermal-sensors = <&ts 726 thermal-sensors = <&tsens0 6>;
695 727
696 trips { 728 trips {
697 cluster1_mhm_a 729 cluster1_mhm_alert0: trip-point0 {
698 temper 730 temperature = <90000>;
699 hyster 731 hysteresis = <2000>;
700 type = 732 type = "hot";
701 }; 733 };
702 }; 734 };
703 }; 735 };
704 736
705 cluster1-l2-thermal { 737 cluster1-l2-thermal {
706 polling-delay-passive 738 polling-delay-passive = <250>;
>> 739 polling-delay = <1000>;
707 740
708 thermal-sensors = <&ts 741 thermal-sensors = <&tsens0 11>;
709 742
710 trips { 743 trips {
711 cluster1_l2_al 744 cluster1_l2_alert0: trip-point0 {
712 temper 745 temperature = <90000>;
713 hyster 746 hysteresis = <2000>;
714 type = 747 type = "hot";
715 }; 748 };
716 }; 749 };
717 }; 750 };
718 751
719 modem-thermal { 752 modem-thermal {
720 polling-delay-passive 753 polling-delay-passive = <250>;
>> 754 polling-delay = <1000>;
721 755
722 thermal-sensors = <&ts 756 thermal-sensors = <&tsens1 1>;
723 757
724 trips { 758 trips {
725 modem_alert0: 759 modem_alert0: trip-point0 {
726 temper 760 temperature = <90000>;
727 hyster 761 hysteresis = <2000>;
728 type = 762 type = "hot";
729 }; 763 };
730 }; 764 };
731 }; 765 };
732 766
733 mem-thermal { 767 mem-thermal {
734 polling-delay-passive 768 polling-delay-passive = <250>;
>> 769 polling-delay = <1000>;
735 770
736 thermal-sensors = <&ts 771 thermal-sensors = <&tsens1 2>;
737 772
738 trips { 773 trips {
739 mem_alert0: tr 774 mem_alert0: trip-point0 {
740 temper 775 temperature = <90000>;
741 hyster 776 hysteresis = <2000>;
742 type = 777 type = "hot";
743 }; 778 };
744 }; 779 };
745 }; 780 };
746 781
747 wlan-thermal { 782 wlan-thermal {
748 polling-delay-passive 783 polling-delay-passive = <250>;
>> 784 polling-delay = <1000>;
749 785
750 thermal-sensors = <&ts 786 thermal-sensors = <&tsens1 3>;
751 787
752 trips { 788 trips {
753 wlan_alert0: t 789 wlan_alert0: trip-point0 {
754 temper 790 temperature = <90000>;
755 hyster 791 hysteresis = <2000>;
756 type = 792 type = "hot";
757 }; 793 };
758 }; 794 };
759 }; 795 };
760 796
761 q6-dsp-thermal { 797 q6-dsp-thermal {
762 polling-delay-passive 798 polling-delay-passive = <250>;
>> 799 polling-delay = <1000>;
763 800
764 thermal-sensors = <&ts 801 thermal-sensors = <&tsens1 4>;
765 802
766 trips { 803 trips {
767 q6_dsp_alert0: 804 q6_dsp_alert0: trip-point0 {
768 temper 805 temperature = <90000>;
769 hyster 806 hysteresis = <2000>;
770 type = 807 type = "hot";
771 }; 808 };
772 }; 809 };
773 }; 810 };
774 811
775 camera-thermal { 812 camera-thermal {
776 polling-delay-passive 813 polling-delay-passive = <250>;
>> 814 polling-delay = <1000>;
777 815
778 thermal-sensors = <&ts 816 thermal-sensors = <&tsens1 5>;
779 817
780 trips { 818 trips {
781 camera_alert0: 819 camera_alert0: trip-point0 {
782 temper 820 temperature = <90000>;
783 hyster 821 hysteresis = <2000>;
784 type = 822 type = "hot";
785 }; 823 };
786 }; 824 };
787 }; 825 };
788 826
789 multimedia-thermal { 827 multimedia-thermal {
790 polling-delay-passive 828 polling-delay-passive = <250>;
>> 829 polling-delay = <1000>;
791 830
792 thermal-sensors = <&ts 831 thermal-sensors = <&tsens1 6>;
793 832
794 trips { 833 trips {
795 multimedia_ale 834 multimedia_alert0: trip-point0 {
796 temper 835 temperature = <90000>;
797 hyster 836 hysteresis = <2000>;
798 type = 837 type = "hot";
799 }; 838 };
800 }; 839 };
801 }; 840 };
802 }; 841 };
803 842
804 timer { 843 timer {
805 compatible = "arm,armv8-timer" 844 compatible = "arm,armv8-timer";
806 interrupts = <GIC_PPI 1 IRQ_TY 845 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
807 <GIC_PPI 2 IRQ_TY 846 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
808 <GIC_PPI 3 IRQ_TY 847 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
809 <GIC_PPI 0 IRQ_TY 848 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
810 }; 849 };
811 850
812 soc: soc@0 { !! 851 soc: soc {
813 #address-cells = <1>; 852 #address-cells = <1>;
814 #size-cells = <1>; 853 #size-cells = <1>;
815 ranges = <0 0 0 0xffffffff>; 854 ranges = <0 0 0 0xffffffff>;
816 compatible = "simple-bus"; 855 compatible = "simple-bus";
817 856
818 gcc: clock-controller@100000 { 857 gcc: clock-controller@100000 {
819 compatible = "qcom,gcc 858 compatible = "qcom,gcc-msm8998";
820 #clock-cells = <1>; 859 #clock-cells = <1>;
821 #reset-cells = <1>; 860 #reset-cells = <1>;
822 #power-domain-cells = 861 #power-domain-cells = <1>;
823 reg = <0x00100000 0xb0 862 reg = <0x00100000 0xb0000>;
824 863
825 clock-names = "xo", "s 864 clock-names = "xo", "sleep_clk";
826 clocks = <&rpmcc RPM_S !! 865 clocks = <&xo>, <&sleep_clk>;
827 <<
828 /* <<
829 * The hypervisor typi <<
830 * reside as read-only <<
831 * these clocks on a d <<
832 * enabled but unused <<
833 * to reboot. <<
834 * In light of that, w <<
835 * as protected. The b <<
836 * list of protected c <<
837 * desired for the HLO <<
838 */ <<
839 protected-clocks = <AG <<
840 <SS <<
841 <SS <<
842 }; 866 };
843 867
844 rpm_msg_ram: sram@778000 { 868 rpm_msg_ram: sram@778000 {
845 compatible = "qcom,rpm 869 compatible = "qcom,rpm-msg-ram";
846 reg = <0x00778000 0x70 870 reg = <0x00778000 0x7000>;
847 }; 871 };
848 872
849 qfprom: qfprom@784000 { 873 qfprom: qfprom@784000 {
850 compatible = "qcom,msm !! 874 compatible = "qcom,qfprom";
851 reg = <0x00784000 0x62 875 reg = <0x00784000 0x621c>;
852 #address-cells = <1>; 876 #address-cells = <1>;
853 #size-cells = <1>; 877 #size-cells = <1>;
854 878
855 qusb2_hstx_trim: hstx- 879 qusb2_hstx_trim: hstx-trim@23a {
856 reg = <0x23a 0 880 reg = <0x23a 0x1>;
857 bits = <0 4>; 881 bits = <0 4>;
858 }; 882 };
859 }; 883 };
860 884
861 tsens0: thermal@10ab000 { 885 tsens0: thermal@10ab000 {
862 compatible = "qcom,msm 886 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
863 reg = <0x010ab000 0x10 887 reg = <0x010ab000 0x1000>, /* TM */
864 <0x010aa000 0x10 888 <0x010aa000 0x1000>; /* SROT */
865 #qcom,sensors = <14>; 889 #qcom,sensors = <14>;
866 interrupts = <GIC_SPI 890 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
867 <GIC_SPI 891 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
868 interrupt-names = "upl 892 interrupt-names = "uplow", "critical";
869 #thermal-sensor-cells 893 #thermal-sensor-cells = <1>;
870 }; 894 };
871 895
872 tsens1: thermal@10ae000 { 896 tsens1: thermal@10ae000 {
873 compatible = "qcom,msm 897 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
874 reg = <0x010ae000 0x10 898 reg = <0x010ae000 0x1000>, /* TM */
875 <0x010ad000 0x10 899 <0x010ad000 0x1000>; /* SROT */
876 #qcom,sensors = <8>; 900 #qcom,sensors = <8>;
877 interrupts = <GIC_SPI 901 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
878 <GIC_SPI 902 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
879 interrupt-names = "upl 903 interrupt-names = "uplow", "critical";
880 #thermal-sensor-cells 904 #thermal-sensor-cells = <1>;
881 }; 905 };
882 906
883 anoc1_smmu: iommu@1680000 { 907 anoc1_smmu: iommu@1680000 {
884 compatible = "qcom,msm 908 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
885 reg = <0x01680000 0x10 909 reg = <0x01680000 0x10000>;
886 #iommu-cells = <1>; 910 #iommu-cells = <1>;
887 911
888 #global-interrupts = < 912 #global-interrupts = <0>;
889 interrupts = 913 interrupts =
890 <GIC_SPI 364 I 914 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
891 <GIC_SPI 365 I 915 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
892 <GIC_SPI 366 I 916 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
893 <GIC_SPI 367 I 917 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
894 <GIC_SPI 368 I 918 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
895 <GIC_SPI 369 I 919 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>;
896 }; 920 };
897 921
898 anoc2_smmu: iommu@16c0000 { 922 anoc2_smmu: iommu@16c0000 {
899 compatible = "qcom,msm 923 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
900 reg = <0x016c0000 0x40 924 reg = <0x016c0000 0x40000>;
901 #iommu-cells = <1>; 925 #iommu-cells = <1>;
902 926
903 #global-interrupts = < 927 #global-interrupts = <0>;
904 interrupts = 928 interrupts =
905 <GIC_SPI 373 I 929 <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>,
906 <GIC_SPI 374 I 930 <GIC_SPI 374 IRQ_TYPE_EDGE_RISING>,
907 <GIC_SPI 375 I 931 <GIC_SPI 375 IRQ_TYPE_EDGE_RISING>,
908 <GIC_SPI 376 I 932 <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>,
909 <GIC_SPI 377 I 933 <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>,
910 <GIC_SPI 378 I 934 <GIC_SPI 378 IRQ_TYPE_EDGE_RISING>,
911 <GIC_SPI 462 I 935 <GIC_SPI 462 IRQ_TYPE_EDGE_RISING>,
912 <GIC_SPI 463 I 936 <GIC_SPI 463 IRQ_TYPE_EDGE_RISING>,
913 <GIC_SPI 464 I 937 <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
914 <GIC_SPI 465 I 938 <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>;
915 }; 939 };
916 940
917 pcie0: pcie@1c00000 { !! 941 pcie0: pci@1c00000 {
918 compatible = "qcom,pci !! 942 compatible = "qcom,pcie-msm8996";
919 reg = <0x01c00000 0x20 !! 943 reg = <0x01c00000 0x2000>,
920 <0x1b000000 0xf1 !! 944 <0x1b000000 0xf1d>,
921 <0x1b000f20 0xa8 !! 945 <0x1b000f20 0xa8>,
922 <0x1b100000 0x10 !! 946 <0x1b100000 0x100000>;
923 reg-names = "parf", "d 947 reg-names = "parf", "dbi", "elbi", "config";
924 device_type = "pci"; 948 device_type = "pci";
925 linux,pci-domain = <0> 949 linux,pci-domain = <0>;
926 bus-range = <0x00 0xff 950 bus-range = <0x00 0xff>;
927 #address-cells = <3>; 951 #address-cells = <3>;
928 #size-cells = <2>; 952 #size-cells = <2>;
929 num-lanes = <1>; 953 num-lanes = <1>;
930 phys = <&pcie_phy>; !! 954 phys = <&pciephy>;
931 phy-names = "pciephy"; 955 phy-names = "pciephy";
932 status = "disabled"; 956 status = "disabled";
933 957
934 ranges = <0x01000000 0 !! 958 ranges = <0x01000000 0x0 0x1b200000 0x1b200000 0x0 0x100000>,
935 <0x02000000 0 959 <0x02000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>;
936 960
937 #interrupt-cells = <1> 961 #interrupt-cells = <1>;
938 interrupts = <GIC_SPI 962 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
939 interrupt-names = "msi 963 interrupt-names = "msi";
940 interrupt-map-mask = < 964 interrupt-map-mask = <0 0 0 0x7>;
941 interrupt-map = <0 0 0 !! 965 interrupt-map = <0 0 0 1 &intc 0 0 135 IRQ_TYPE_LEVEL_HIGH>,
942 <0 0 0 966 <0 0 0 2 &intc 0 0 136 IRQ_TYPE_LEVEL_HIGH>,
943 <0 0 0 967 <0 0 0 3 &intc 0 0 138 IRQ_TYPE_LEVEL_HIGH>,
944 <0 0 0 968 <0 0 0 4 &intc 0 0 139 IRQ_TYPE_LEVEL_HIGH>;
945 969
946 clocks = <&gcc GCC_PCI 970 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
947 <&gcc GCC_PCI <<
948 <&gcc GCC_PCI <<
949 <&gcc GCC_PCI 971 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
950 <&gcc GCC_PCI !! 972 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
951 clock-names = "pipe", !! 973 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
>> 974 <&gcc GCC_PCIE_0_AUX_CLK>;
>> 975 clock-names = "pipe", "bus_master", "bus_slave", "cfg", "aux";
952 976
953 power-domains = <&gcc 977 power-domains = <&gcc PCIE_0_GDSC>;
954 iommu-map = <0x100 &an 978 iommu-map = <0x100 &anoc1_smmu 0x1480 1>;
955 perst-gpios = <&tlmm 3 979 perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
956 <<
957 pcie@0 { <<
958 device_type = <<
959 reg = <0x0 0x0 <<
960 bus-range = <0 <<
961 <<
962 #address-cells <<
963 #size-cells = <<
964 ranges; <<
965 }; <<
966 }; 980 };
967 981
968 pcie_phy: phy@1c06000 { 982 pcie_phy: phy@1c06000 {
969 compatible = "qcom,msm 983 compatible = "qcom,msm8998-qmp-pcie-phy";
970 reg = <0x01c06000 0x10 !! 984 reg = <0x01c06000 0x18c>;
>> 985 #address-cells = <1>;
>> 986 #size-cells = <1>;
971 status = "disabled"; 987 status = "disabled";
>> 988 ranges;
972 989
973 clocks = <&gcc GCC_PCI 990 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
974 <&gcc GCC_PCI 991 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
975 <&gcc GCC_PCI !! 992 <&gcc GCC_PCIE_CLKREF_CLK>;
976 <&gcc GCC_PCI !! 993 clock-names = "aux", "cfg_ahb", "ref";
977 clock-names = "aux", <<
978 "cfg_ahb <<
979 "ref", <<
980 "pipe"; <<
981 <<
982 clock-output-names = " <<
983 #clock-cells = <0>; <<
984 <<
985 #phy-cells = <0>; <<
986 994
987 resets = <&gcc GCC_PCI 995 resets = <&gcc GCC_PCIE_0_PHY_BCR>, <&gcc GCC_PCIE_PHY_BCR>;
988 reset-names = "phy", " 996 reset-names = "phy", "common";
989 997
990 vdda-phy-supply = <&vr 998 vdda-phy-supply = <&vreg_l1a_0p875>;
991 vdda-pll-supply = <&vr 999 vdda-pll-supply = <&vreg_l2a_1p2>;
>> 1000
>> 1001 pciephy: phy@1c06800 {
>> 1002 reg = <0x01c06200 0x128>, <0x01c06400 0x1fc>, <0x01c06800 0x20c>;
>> 1003 #phy-cells = <0>;
>> 1004
>> 1005 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
>> 1006 clock-names = "pipe0";
>> 1007 clock-output-names = "pcie_0_pipe_clk_src";
>> 1008 #clock-cells = <0>;
>> 1009 };
992 }; 1010 };
993 1011
994 ufshc: ufshc@1da4000 { 1012 ufshc: ufshc@1da4000 {
995 compatible = "qcom,msm 1013 compatible = "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
996 reg = <0x01da4000 0x25 1014 reg = <0x01da4000 0x2500>;
997 interrupts = <GIC_SPI 1015 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
998 phys = <&ufsphy>; !! 1016 phys = <&ufsphy_lanes>;
999 phy-names = "ufsphy"; 1017 phy-names = "ufsphy";
1000 lanes-per-direction = 1018 lanes-per-direction = <2>;
1001 power-domains = <&gcc 1019 power-domains = <&gcc UFS_GDSC>;
1002 status = "disabled"; 1020 status = "disabled";
1003 #reset-cells = <1>; 1021 #reset-cells = <1>;
1004 1022
1005 clock-names = 1023 clock-names =
1006 "core_clk", 1024 "core_clk",
1007 "bus_aggr_clk 1025 "bus_aggr_clk",
1008 "iface_clk", 1026 "iface_clk",
1009 "core_clk_uni 1027 "core_clk_unipro",
1010 "ref_clk", 1028 "ref_clk",
1011 "tx_lane0_syn 1029 "tx_lane0_sync_clk",
1012 "rx_lane0_syn 1030 "rx_lane0_sync_clk",
1013 "rx_lane1_syn 1031 "rx_lane1_sync_clk";
1014 clocks = 1032 clocks =
1015 <&gcc GCC_UFS 1033 <&gcc GCC_UFS_AXI_CLK>,
1016 <&gcc GCC_AGG 1034 <&gcc GCC_AGGRE1_UFS_AXI_CLK>,
1017 <&gcc GCC_UFS 1035 <&gcc GCC_UFS_AHB_CLK>,
1018 <&gcc GCC_UFS 1036 <&gcc GCC_UFS_UNIPRO_CORE_CLK>,
1019 <&rpmcc RPM_S 1037 <&rpmcc RPM_SMD_LN_BB_CLK1>,
1020 <&gcc GCC_UFS 1038 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
1021 <&gcc GCC_UFS 1039 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>,
1022 <&gcc GCC_UFS 1040 <&gcc GCC_UFS_RX_SYMBOL_1_CLK>;
1023 freq-table-hz = 1041 freq-table-hz =
1024 <50000000 200 1042 <50000000 200000000>,
1025 <0 0>, 1043 <0 0>,
1026 <0 0>, 1044 <0 0>,
1027 <37500000 150 1045 <37500000 150000000>,
1028 <0 0>, 1046 <0 0>,
1029 <0 0>, 1047 <0 0>,
1030 <0 0>, 1048 <0 0>,
1031 <0 0>; 1049 <0 0>;
1032 1050
1033 resets = <&gcc GCC_UF 1051 resets = <&gcc GCC_UFS_BCR>;
1034 reset-names = "rst"; 1052 reset-names = "rst";
1035 }; 1053 };
1036 1054
1037 ufsphy: phy@1da7000 { 1055 ufsphy: phy@1da7000 {
1038 compatible = "qcom,ms 1056 compatible = "qcom,msm8998-qmp-ufs-phy";
1039 reg = <0x01da7000 0x1 !! 1057 reg = <0x01da7000 0x18c>;
>> 1058 #address-cells = <1>;
>> 1059 #size-cells = <1>;
>> 1060 status = "disabled";
>> 1061 ranges;
1040 1062
1041 clocks = <&rpmcc RPM_ !! 1063 clock-names =
1042 <&gcc GCC_UF !! 1064 "ref",
1043 <&gcc GCC_UF !! 1065 "ref_aux";
1044 clock-names = "ref", !! 1066 clocks =
1045 "ref_au !! 1067 <&gcc GCC_UFS_CLKREF_CLK>,
1046 "qref"; !! 1068 <&gcc GCC_UFS_PHY_AUX_CLK>;
1047 1069
1048 reset-names = "ufsphy 1070 reset-names = "ufsphy";
1049 resets = <&ufshc 0>; 1071 resets = <&ufshc 0>;
1050 1072
1051 #phy-cells = <0>; !! 1073 ufsphy_lanes: phy@1da7400 {
1052 status = "disabled"; !! 1074 reg = <0x01da7400 0x128>,
1053 }; !! 1075 <0x01da7600 0x1fc>,
1054 !! 1076 <0x01da7c00 0x1dc>,
1055 tcsr_mutex: hwlock@1f40000 { !! 1077 <0x01da7800 0x128>,
1056 compatible = "qcom,tc !! 1078 <0x01da7a00 0x1fc>;
1057 reg = <0x01f40000 0x2 !! 1079 #phy-cells = <0>;
1058 #hwlock-cells = <1>; !! 1080 };
1059 }; <<
1060 <<
1061 tcsr_regs_1: syscon@1f60000 { <<
1062 compatible = "qcom,ms <<
1063 reg = <0x01f60000 0x2 <<
1064 }; 1081 };
1065 1082
1066 tcsr_regs_2: syscon@1fc0000 { !! 1083 tcsr_mutex_regs: syscon@1f40000 {
1067 compatible = "qcom,ms !! 1084 compatible = "syscon";
1068 reg = <0x01fc0000 0x2 !! 1085 reg = <0x01f40000 0x40000>;
1069 }; 1086 };
1070 1087
1071 tlmm: pinctrl@3400000 { 1088 tlmm: pinctrl@3400000 {
1072 compatible = "qcom,ms 1089 compatible = "qcom,msm8998-pinctrl";
1073 reg = <0x03400000 0xc 1090 reg = <0x03400000 0xc00000>;
1074 interrupts = <GIC_SPI 1091 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1075 gpio-ranges = <&tlmm <<
1076 gpio-controller; 1092 gpio-controller;
1077 #gpio-cells = <2>; !! 1093 #gpio-cells = <0x2>;
1078 interrupt-controller; 1094 interrupt-controller;
1079 #interrupt-cells = <2 !! 1095 #interrupt-cells = <0x2>;
1080 1096
1081 sdc2_on: sdc2-on-stat !! 1097 sdc2_clk_on: sdc2_clk_on {
1082 clk-pins { !! 1098 config {
1083 pins 1099 pins = "sdc2_clk";
>> 1100 bias-disable;
1084 drive 1101 drive-strength = <16>;
>> 1102 };
>> 1103 };
>> 1104
>> 1105 sdc2_clk_off: sdc2_clk_off {
>> 1106 config {
>> 1107 pins = "sdc2_clk";
1085 bias- 1108 bias-disable;
>> 1109 drive-strength = <2>;
1086 }; 1110 };
>> 1111 };
1087 1112
1088 cmd-pins { !! 1113 sdc2_cmd_on: sdc2_cmd_on {
>> 1114 config {
1089 pins 1115 pins = "sdc2_cmd";
>> 1116 bias-pull-up;
1090 drive 1117 drive-strength = <10>;
>> 1118 };
>> 1119 };
>> 1120
>> 1121 sdc2_cmd_off: sdc2_cmd_off {
>> 1122 config {
>> 1123 pins = "sdc2_cmd";
1091 bias- 1124 bias-pull-up;
>> 1125 drive-strength = <2>;
1092 }; 1126 };
>> 1127 };
1093 1128
1094 data-pins { !! 1129 sdc2_data_on: sdc2_data_on {
>> 1130 config {
1095 pins 1131 pins = "sdc2_data";
1096 drive <<
1097 bias- 1132 bias-pull-up;
>> 1133 drive-strength = <10>;
1098 }; 1134 };
1099 }; 1135 };
1100 1136
1101 sdc2_off: sdc2-off-st !! 1137 sdc2_data_off: sdc2_data_off {
1102 clk-pins { !! 1138 config {
1103 pins !! 1139 pins = "sdc2_data";
>> 1140 bias-pull-up;
1104 drive 1141 drive-strength = <2>;
1105 bias- <<
1106 }; 1142 };
>> 1143 };
1107 1144
1108 cmd-pins { !! 1145 sdc2_cd_on: sdc2_cd_on {
1109 pins !! 1146 mux {
1110 drive !! 1147 pins = "gpio95";
1111 bias- !! 1148 function = "gpio";
1112 }; 1149 };
1113 1150
1114 data-pins { !! 1151 config {
1115 pins !! 1152 pins = "gpio95";
1116 drive <<
1117 bias- 1153 bias-pull-up;
>> 1154 drive-strength = <2>;
1118 }; 1155 };
1119 }; 1156 };
1120 1157
1121 sdc2_cd: sdc2-cd-stat !! 1158 sdc2_cd_off: sdc2_cd_off {
1122 pins = "gpio9 !! 1159 mux {
1123 function = "g !! 1160 pins = "gpio95";
1124 bias-pull-up; !! 1161 function = "gpio";
1125 drive-strengt !! 1162 };
>> 1163
>> 1164 config {
>> 1165 pins = "gpio95";
>> 1166 bias-pull-up;
>> 1167 drive-strength = <2>;
>> 1168 };
1126 }; 1169 };
1127 1170
1128 blsp1_uart3_on: blsp1 !! 1171 blsp1_uart3_on: blsp1_uart3_on {
1129 tx-pins { !! 1172 tx {
1130 pins 1173 pins = "gpio45";
1131 funct 1174 function = "blsp_uart3_a";
1132 drive 1175 drive-strength = <2>;
1133 bias- 1176 bias-disable;
1134 }; 1177 };
1135 1178
1136 rx-pins { !! 1179 rx {
1137 pins 1180 pins = "gpio46";
1138 funct 1181 function = "blsp_uart3_a";
1139 drive 1182 drive-strength = <2>;
1140 bias- 1183 bias-disable;
1141 }; 1184 };
1142 1185
1143 cts-pins { !! 1186 cts {
1144 pins 1187 pins = "gpio47";
1145 funct 1188 function = "blsp_uart3_a";
1146 drive 1189 drive-strength = <2>;
1147 bias- 1190 bias-disable;
1148 }; 1191 };
1149 1192
1150 rfr-pins { !! 1193 rfr {
1151 pins 1194 pins = "gpio48";
1152 funct 1195 function = "blsp_uart3_a";
1153 drive 1196 drive-strength = <2>;
1154 bias- 1197 bias-disable;
1155 }; 1198 };
1156 }; 1199 };
1157 1200
1158 blsp1_i2c1_default: b !! 1201 blsp1_i2c1_default: blsp1-i2c1-default {
1159 pins = "gpio2 1202 pins = "gpio2", "gpio3";
1160 function = "b 1203 function = "blsp_i2c1";
1161 drive-strengt 1204 drive-strength = <2>;
1162 bias-disable; 1205 bias-disable;
1163 }; 1206 };
1164 1207
1165 blsp1_i2c1_sleep: bls !! 1208 blsp1_i2c1_sleep: blsp1-i2c1-sleep {
1166 pins = "gpio2 1209 pins = "gpio2", "gpio3";
1167 function = "b 1210 function = "blsp_i2c1";
1168 drive-strengt 1211 drive-strength = <2>;
1169 bias-pull-up; 1212 bias-pull-up;
1170 }; 1213 };
1171 1214
1172 blsp1_i2c2_default: b !! 1215 blsp1_i2c2_default: blsp1-i2c2-default {
1173 pins = "gpio3 1216 pins = "gpio32", "gpio33";
1174 function = "b 1217 function = "blsp_i2c2";
1175 drive-strengt 1218 drive-strength = <2>;
1176 bias-disable; 1219 bias-disable;
1177 }; 1220 };
1178 1221
1179 blsp1_i2c2_sleep: bls !! 1222 blsp1_i2c2_sleep: blsp1-i2c2-sleep {
1180 pins = "gpio3 1223 pins = "gpio32", "gpio33";
1181 function = "b 1224 function = "blsp_i2c2";
1182 drive-strengt 1225 drive-strength = <2>;
1183 bias-pull-up; 1226 bias-pull-up;
1184 }; 1227 };
1185 1228
1186 blsp1_i2c3_default: b !! 1229 blsp1_i2c3_default: blsp1-i2c3-default {
1187 pins = "gpio4 1230 pins = "gpio47", "gpio48";
1188 function = "b 1231 function = "blsp_i2c3";
1189 drive-strengt 1232 drive-strength = <2>;
1190 bias-disable; 1233 bias-disable;
1191 }; 1234 };
1192 1235
1193 blsp1_i2c3_sleep: bls !! 1236 blsp1_i2c3_sleep: blsp1-i2c3-sleep {
1194 pins = "gpio4 1237 pins = "gpio47", "gpio48";
1195 function = "b 1238 function = "blsp_i2c3";
1196 drive-strengt 1239 drive-strength = <2>;
1197 bias-pull-up; 1240 bias-pull-up;
1198 }; 1241 };
1199 1242
1200 blsp1_i2c4_default: b !! 1243 blsp1_i2c4_default: blsp1-i2c4-default {
1201 pins = "gpio1 1244 pins = "gpio10", "gpio11";
1202 function = "b 1245 function = "blsp_i2c4";
1203 drive-strengt 1246 drive-strength = <2>;
1204 bias-disable; 1247 bias-disable;
1205 }; 1248 };
1206 1249
1207 blsp1_i2c4_sleep: bls !! 1250 blsp1_i2c4_sleep: blsp1-i2c4-sleep {
1208 pins = "gpio1 1251 pins = "gpio10", "gpio11";
1209 function = "b 1252 function = "blsp_i2c4";
1210 drive-strengt 1253 drive-strength = <2>;
1211 bias-pull-up; 1254 bias-pull-up;
1212 }; 1255 };
1213 1256
1214 blsp1_i2c5_default: b !! 1257 blsp1_i2c5_default: blsp1-i2c5-default {
1215 pins = "gpio8 1258 pins = "gpio87", "gpio88";
1216 function = "b 1259 function = "blsp_i2c5";
1217 drive-strengt 1260 drive-strength = <2>;
1218 bias-disable; 1261 bias-disable;
1219 }; 1262 };
1220 1263
1221 blsp1_i2c5_sleep: bls !! 1264 blsp1_i2c5_sleep: blsp1-i2c5-sleep {
1222 pins = "gpio8 1265 pins = "gpio87", "gpio88";
1223 function = "b 1266 function = "blsp_i2c5";
1224 drive-strengt 1267 drive-strength = <2>;
1225 bias-pull-up; 1268 bias-pull-up;
1226 }; 1269 };
1227 1270
1228 blsp1_i2c6_default: b !! 1271 blsp1_i2c6_default: blsp1-i2c6-default {
1229 pins = "gpio4 1272 pins = "gpio43", "gpio44";
1230 function = "b 1273 function = "blsp_i2c6";
1231 drive-strengt 1274 drive-strength = <2>;
1232 bias-disable; 1275 bias-disable;
1233 }; 1276 };
1234 1277
1235 blsp1_i2c6_sleep: bls !! 1278 blsp1_i2c6_sleep: blsp1-i2c6-sleep {
1236 pins = "gpio4 1279 pins = "gpio43", "gpio44";
1237 function = "b 1280 function = "blsp_i2c6";
1238 drive-strengt 1281 drive-strength = <2>;
1239 bias-pull-up; 1282 bias-pull-up;
1240 }; 1283 };
1241 <<
1242 blsp1_spi_b_default: <<
1243 pins = "gpio2 <<
1244 function = "b <<
1245 drive-strengt <<
1246 bias-disable; <<
1247 }; <<
1248 <<
1249 blsp1_spi1_default: b <<
1250 pins = "gpio0 <<
1251 function = "b <<
1252 drive-strengt <<
1253 bias-disable; <<
1254 }; <<
1255 <<
1256 blsp1_spi2_default: b <<
1257 pins = "gpio3 <<
1258 function = "b <<
1259 drive-strengt <<
1260 bias-disable; <<
1261 }; <<
1262 <<
1263 blsp1_spi3_default: b <<
1264 pins = "gpio4 <<
1265 function = "b <<
1266 drive-strengt <<
1267 bias-disable; <<
1268 }; <<
1269 <<
1270 blsp1_spi4_default: b <<
1271 pins = "gpio8 <<
1272 function = "b <<
1273 drive-strengt <<
1274 bias-disable; <<
1275 }; <<
1276 <<
1277 blsp1_spi5_default: b <<
1278 pins = "gpio8 <<
1279 function = "b <<
1280 drive-strengt <<
1281 bias-disable; <<
1282 }; <<
1283 <<
1284 blsp1_spi6_default: b <<
1285 pins = "gpio4 <<
1286 function = "b <<
1287 drive-strengt <<
1288 bias-disable; <<
1289 }; <<
1290 <<
1291 <<
1292 /* 6 interfaces per Q 1284 /* 6 interfaces per QUP, BLSP2 indexes are numbered (n)+6 */
1293 blsp2_i2c1_default: b !! 1285 blsp2_i2c1_default: blsp2-i2c1-default {
1294 pins = "gpio5 1286 pins = "gpio55", "gpio56";
1295 function = "b 1287 function = "blsp_i2c7";
1296 drive-strengt 1288 drive-strength = <2>;
1297 bias-disable; 1289 bias-disable;
1298 }; 1290 };
1299 1291
1300 blsp2_i2c1_sleep: bls !! 1292 blsp2_i2c1_sleep: blsp2-i2c1-sleep {
1301 pins = "gpio5 1293 pins = "gpio55", "gpio56";
1302 function = "b 1294 function = "blsp_i2c7";
1303 drive-strengt 1295 drive-strength = <2>;
1304 bias-pull-up; 1296 bias-pull-up;
1305 }; 1297 };
1306 1298
1307 blsp2_i2c2_default: b !! 1299 blsp2_i2c2_default: blsp2-i2c2-default {
1308 pins = "gpio6 1300 pins = "gpio6", "gpio7";
1309 function = "b 1301 function = "blsp_i2c8";
1310 drive-strengt 1302 drive-strength = <2>;
1311 bias-disable; 1303 bias-disable;
1312 }; 1304 };
1313 1305
1314 blsp2_i2c2_sleep: bls !! 1306 blsp2_i2c2_sleep: blsp2-i2c2-sleep {
1315 pins = "gpio6 1307 pins = "gpio6", "gpio7";
1316 function = "b 1308 function = "blsp_i2c8";
1317 drive-strengt 1309 drive-strength = <2>;
1318 bias-pull-up; 1310 bias-pull-up;
1319 }; 1311 };
1320 1312
1321 blsp2_i2c3_default: b !! 1313 blsp2_i2c3_default: blsp2-i2c3-default {
1322 pins = "gpio5 1314 pins = "gpio51", "gpio52";
1323 function = "b 1315 function = "blsp_i2c9";
1324 drive-strengt 1316 drive-strength = <2>;
1325 bias-disable; 1317 bias-disable;
1326 }; 1318 };
1327 1319
1328 blsp2_i2c3_sleep: bls !! 1320 blsp2_i2c3_sleep: blsp2-i2c3-sleep {
1329 pins = "gpio5 1321 pins = "gpio51", "gpio52";
1330 function = "b 1322 function = "blsp_i2c9";
1331 drive-strengt 1323 drive-strength = <2>;
1332 bias-pull-up; 1324 bias-pull-up;
1333 }; 1325 };
1334 1326
1335 blsp2_i2c4_default: b !! 1327 blsp2_i2c4_default: blsp2-i2c4-default {
1336 pins = "gpio6 1328 pins = "gpio67", "gpio68";
1337 function = "b 1329 function = "blsp_i2c10";
1338 drive-strengt 1330 drive-strength = <2>;
1339 bias-disable; 1331 bias-disable;
1340 }; 1332 };
1341 1333
1342 blsp2_i2c4_sleep: bls !! 1334 blsp2_i2c4_sleep: blsp2-i2c4-sleep {
1343 pins = "gpio6 1335 pins = "gpio67", "gpio68";
1344 function = "b 1336 function = "blsp_i2c10";
1345 drive-strengt 1337 drive-strength = <2>;
1346 bias-pull-up; 1338 bias-pull-up;
1347 }; 1339 };
1348 1340
1349 blsp2_i2c5_default: b !! 1341 blsp2_i2c5_default: blsp2-i2c5-default {
1350 pins = "gpio6 1342 pins = "gpio60", "gpio61";
1351 function = "b 1343 function = "blsp_i2c11";
1352 drive-strengt 1344 drive-strength = <2>;
1353 bias-disable; 1345 bias-disable;
1354 }; 1346 };
1355 1347
1356 blsp2_i2c5_sleep: bls !! 1348 blsp2_i2c5_sleep: blsp2-i2c5-sleep {
1357 pins = "gpio6 1349 pins = "gpio60", "gpio61";
1358 function = "b 1350 function = "blsp_i2c11";
1359 drive-strengt 1351 drive-strength = <2>;
1360 bias-pull-up; 1352 bias-pull-up;
1361 }; 1353 };
1362 1354
1363 blsp2_i2c6_default: b !! 1355 blsp2_i2c6_default: blsp2-i2c6-default {
1364 pins = "gpio8 1356 pins = "gpio83", "gpio84";
1365 function = "b 1357 function = "blsp_i2c12";
1366 drive-strengt 1358 drive-strength = <2>;
1367 bias-disable; 1359 bias-disable;
1368 }; 1360 };
1369 1361
1370 blsp2_i2c6_sleep: bls !! 1362 blsp2_i2c6_sleep: blsp2-i2c6-sleep {
1371 pins = "gpio8 1363 pins = "gpio83", "gpio84";
1372 function = "b 1364 function = "blsp_i2c12";
1373 drive-strengt 1365 drive-strength = <2>;
1374 bias-pull-up; 1366 bias-pull-up;
1375 }; 1367 };
1376 <<
1377 blsp2_spi1_default: b <<
1378 pins = "gpio5 <<
1379 function = "b <<
1380 drive-strengt <<
1381 bias-disable; <<
1382 }; <<
1383 <<
1384 blsp2_spi2_default: b <<
1385 pins = "gpio4 <<
1386 function = "b <<
1387 drive-strengt <<
1388 bias-disable; <<
1389 }; <<
1390 <<
1391 blsp2_spi3_default: b <<
1392 pins = "gpio4 <<
1393 function = "b <<
1394 drive-strengt <<
1395 bias-disable; <<
1396 }; <<
1397 <<
1398 blsp2_spi4_default: b <<
1399 pins = "gpio6 <<
1400 function = "b <<
1401 drive-strengt <<
1402 bias-disable; <<
1403 }; <<
1404 <<
1405 blsp2_spi5_default: b <<
1406 pins = "gpio5 <<
1407 function = "b <<
1408 drive-strengt <<
1409 bias-disable; <<
1410 }; <<
1411 <<
1412 blsp2_spi6_default: b <<
1413 pins = "gpio8 <<
1414 function = "b <<
1415 drive-strengt <<
1416 bias-disable; <<
1417 }; <<
1418 }; 1368 };
1419 1369
1420 remoteproc_mss: remoteproc@40 1370 remoteproc_mss: remoteproc@4080000 {
1421 compatible = "qcom,ms 1371 compatible = "qcom,msm8998-mss-pil";
1422 reg = <0x04080000 0x1 1372 reg = <0x04080000 0x100>, <0x04180000 0x20>;
1423 reg-names = "qdsp6", 1373 reg-names = "qdsp6", "rmb";
1424 1374
1425 interrupts-extended = 1375 interrupts-extended =
1426 <&intc GIC_SP 1376 <&intc GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
1427 <&modem_smp2p 1377 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1428 <&modem_smp2p 1378 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1429 <&modem_smp2p 1379 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1430 <&modem_smp2p 1380 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
1431 <&modem_smp2p 1381 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
1432 interrupt-names = "wd 1382 interrupt-names = "wdog", "fatal", "ready",
1433 "ha 1383 "handover", "stop-ack",
1434 "sh 1384 "shutdown-ack";
1435 1385
1436 clocks = <&gcc GCC_MS 1386 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
1437 <&gcc GCC_BI 1387 <&gcc GCC_BIMC_MSS_Q6_AXI_CLK>,
1438 <&gcc GCC_BO 1388 <&gcc GCC_BOOT_ROM_AHB_CLK>,
1439 <&gcc GCC_MS 1389 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
1440 <&gcc GCC_MS 1390 <&gcc GCC_MSS_SNOC_AXI_CLK>,
1441 <&gcc GCC_MS 1391 <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>,
1442 <&rpmcc RPM_ 1392 <&rpmcc RPM_SMD_QDSS_CLK>,
1443 <&rpmcc RPM_ 1393 <&rpmcc RPM_SMD_XO_CLK_SRC>;
1444 clock-names = "iface" 1394 clock-names = "iface", "bus", "mem", "gpll0_mss",
1445 "snoc_a 1395 "snoc_axi", "mnoc_axi", "qdss", "xo";
1446 1396
1447 qcom,smem-states = <& 1397 qcom,smem-states = <&modem_smp2p_out 0>;
1448 qcom,smem-state-names 1398 qcom,smem-state-names = "stop";
1449 1399
1450 resets = <&gcc GCC_MS 1400 resets = <&gcc GCC_MSS_RESTART>;
1451 reset-names = "mss_re 1401 reset-names = "mss_restart";
1452 1402
1453 qcom,halt-regs = <&tc !! 1403 qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
1454 1404
1455 power-domains = <&rpm 1405 power-domains = <&rpmpd MSM8998_VDDCX>,
1456 <&rpm 1406 <&rpmpd MSM8998_VDDMX>;
1457 power-domain-names = 1407 power-domain-names = "cx", "mx";
1458 1408
1459 status = "disabled"; 1409 status = "disabled";
1460 1410
1461 mba { 1411 mba {
1462 memory-region 1412 memory-region = <&mba_mem>;
1463 }; 1413 };
1464 1414
1465 mpss { 1415 mpss {
1466 memory-region 1416 memory-region = <&mpss_mem>;
1467 }; 1417 };
1468 1418
1469 metadata { <<
1470 memory-region <<
1471 }; <<
1472 <<
1473 glink-edge { 1419 glink-edge {
1474 interrupts = 1420 interrupts = <GIC_SPI 452 IRQ_TYPE_EDGE_RISING>;
1475 label = "mode 1421 label = "modem";
1476 qcom,remote-p 1422 qcom,remote-pid = <1>;
1477 mboxes = <&ap 1423 mboxes = <&apcs_glb 15>;
1478 }; 1424 };
1479 }; 1425 };
1480 1426
1481 adreno_gpu: gpu@5000000 { 1427 adreno_gpu: gpu@5000000 {
1482 compatible = "qcom,ad 1428 compatible = "qcom,adreno-540.1", "qcom,adreno";
1483 reg = <0x05000000 0x4 1429 reg = <0x05000000 0x40000>;
1484 reg-names = "kgsl_3d0 1430 reg-names = "kgsl_3d0_reg_memory";
1485 1431
1486 clocks = <&gcc GCC_GP 1432 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
1487 <&gpucc RBBMT 1433 <&gpucc RBBMTIMER_CLK>,
1488 <&gcc GCC_BIM 1434 <&gcc GCC_BIMC_GFX_CLK>,
1489 <&gcc GCC_GPU 1435 <&gcc GCC_GPU_BIMC_GFX_CLK>,
1490 <&gpucc RBCPR 1436 <&gpucc RBCPR_CLK>,
1491 <&gpucc GFX3D 1437 <&gpucc GFX3D_CLK>;
1492 clock-names = "iface" 1438 clock-names = "iface",
1493 "rbbmtimer", 1439 "rbbmtimer",
1494 "mem", 1440 "mem",
1495 "mem_iface", 1441 "mem_iface",
1496 "rbcpr", 1442 "rbcpr",
1497 "core"; 1443 "core";
1498 1444
1499 interrupts = <GIC_SPI !! 1445 interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
1500 iommus = <&adreno_smm 1446 iommus = <&adreno_smmu 0>;
1501 operating-points-v2 = 1447 operating-points-v2 = <&gpu_opp_table>;
1502 power-domains = <&rpm 1448 power-domains = <&rpmpd MSM8998_VDDMX>;
>> 1449 #stream-id-cells = <16>;
1503 status = "disabled"; 1450 status = "disabled";
1504 1451
1505 gpu_opp_table: opp-ta 1452 gpu_opp_table: opp-table {
1506 compatible = !! 1453 compatible = "operating-points-v2";
1507 opp-710000097 1454 opp-710000097 {
1508 opp-h 1455 opp-hz = /bits/ 64 <710000097>;
1509 opp-l 1456 opp-level = <RPM_SMD_LEVEL_TURBO>;
1510 opp-s !! 1457 opp-supported-hw = <0xFF>;
1511 }; 1458 };
1512 1459
1513 opp-670000048 1460 opp-670000048 {
1514 opp-h 1461 opp-hz = /bits/ 64 <670000048>;
1515 opp-l 1462 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
1516 opp-s !! 1463 opp-supported-hw = <0xFF>;
1517 }; 1464 };
1518 1465
1519 opp-596000097 1466 opp-596000097 {
1520 opp-h 1467 opp-hz = /bits/ 64 <596000097>;
1521 opp-l 1468 opp-level = <RPM_SMD_LEVEL_NOM>;
1522 opp-s !! 1469 opp-supported-hw = <0xFF>;
1523 }; 1470 };
1524 1471
1525 opp-515000097 1472 opp-515000097 {
1526 opp-h 1473 opp-hz = /bits/ 64 <515000097>;
1527 opp-l 1474 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
1528 opp-s !! 1475 opp-supported-hw = <0xFF>;
1529 }; 1476 };
1530 1477
1531 opp-414000000 1478 opp-414000000 {
1532 opp-h 1479 opp-hz = /bits/ 64 <414000000>;
1533 opp-l 1480 opp-level = <RPM_SMD_LEVEL_SVS>;
1534 opp-s !! 1481 opp-supported-hw = <0xFF>;
1535 }; 1482 };
1536 1483
1537 opp-342000000 1484 opp-342000000 {
1538 opp-h 1485 opp-hz = /bits/ 64 <342000000>;
1539 opp-l 1486 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
1540 opp-s !! 1487 opp-supported-hw = <0xFF>;
1541 }; 1488 };
1542 1489
1543 opp-257000000 1490 opp-257000000 {
1544 opp-h 1491 opp-hz = /bits/ 64 <257000000>;
1545 opp-l 1492 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
1546 opp-s !! 1493 opp-supported-hw = <0xFF>;
1547 }; 1494 };
1548 }; 1495 };
1549 }; 1496 };
1550 1497
1551 adreno_smmu: iommu@5040000 { 1498 adreno_smmu: iommu@5040000 {
1552 compatible = "qcom,ms 1499 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
1553 reg = <0x05040000 0x1 1500 reg = <0x05040000 0x10000>;
1554 clocks = <&gcc GCC_GP 1501 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
1555 <&gcc GCC_BI 1502 <&gcc GCC_BIMC_GFX_CLK>,
1556 <&gcc GCC_GP 1503 <&gcc GCC_GPU_BIMC_GFX_CLK>;
1557 clock-names = "iface" 1504 clock-names = "iface", "mem", "mem_iface";
1558 1505
1559 #global-interrupts = 1506 #global-interrupts = <0>;
1560 #iommu-cells = <1>; 1507 #iommu-cells = <1>;
1561 interrupts = 1508 interrupts =
1562 <GIC_SPI 329 1509 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1563 <GIC_SPI 330 1510 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
1564 <GIC_SPI 331 1511 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
1565 /* 1512 /*
1566 * GPU-GX GDSC's pare 1513 * GPU-GX GDSC's parent is GPU-CX. We need to bring up the
1567 * GPU-CX for SMMU bu 1514 * GPU-CX for SMMU but we need both of them up for Adreno.
1568 * Contemporarily, we 1515 * Contemporarily, we also need to manage the VDDMX rpmpd
1569 * domain in the Adre 1516 * domain in the Adreno driver.
1570 * Enable GPU CX/GX G 1517 * Enable GPU CX/GX GDSCs here so that we can manage the
1571 * SoC VDDMX RPM Powe 1518 * SoC VDDMX RPM Power Domain in the Adreno driver.
1572 */ 1519 */
1573 power-domains = <&gpu 1520 power-domains = <&gpucc GPU_GX_GDSC>;
>> 1521 status = "disabled";
1574 }; 1522 };
1575 1523
1576 gpucc: clock-controller@50650 1524 gpucc: clock-controller@5065000 {
1577 compatible = "qcom,ms 1525 compatible = "qcom,msm8998-gpucc";
1578 #clock-cells = <1>; 1526 #clock-cells = <1>;
1579 #reset-cells = <1>; 1527 #reset-cells = <1>;
1580 #power-domain-cells = 1528 #power-domain-cells = <1>;
1581 reg = <0x05065000 0x9 1529 reg = <0x05065000 0x9000>;
1582 1530
1583 clocks = <&rpmcc RPM_ 1531 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1584 <&gcc GCC_GP !! 1532 <&gcc GPLL0_OUT_MAIN>;
1585 clock-names = "xo", 1533 clock-names = "xo",
1586 "gpll0" 1534 "gpll0";
1587 }; 1535 };
1588 1536
1589 lpass_q6_smmu: iommu@5100000 <<
1590 compatible = "qcom,ms <<
1591 reg = <0x05100000 0x4 <<
1592 clocks = <&gcc HLOS1_ <<
1593 clock-names = "bus"; <<
1594 <<
1595 #global-interrupts = <<
1596 #iommu-cells = <1>; <<
1597 interrupts = <<
1598 <GIC_SPI 226 <<
1599 <GIC_SPI 393 <<
1600 <GIC_SPI 394 <<
1601 <GIC_SPI 395 <<
1602 <GIC_SPI 396 <<
1603 <GIC_SPI 397 <<
1604 <GIC_SPI 398 <<
1605 <GIC_SPI 399 <<
1606 <GIC_SPI 400 <<
1607 <GIC_SPI 401 <<
1608 <GIC_SPI 402 <<
1609 <GIC_SPI 403 <<
1610 <GIC_SPI 137 <<
1611 <<
1612 power-domains = <&gcc <<
1613 status = "disabled"; <<
1614 }; <<
1615 <<
1616 remoteproc_slpi: remoteproc@5 1537 remoteproc_slpi: remoteproc@5800000 {
1617 compatible = "qcom,ms 1538 compatible = "qcom,msm8998-slpi-pas";
1618 reg = <0x05800000 0x4 1539 reg = <0x05800000 0x4040>;
1619 1540
1620 interrupts-extended = 1541 interrupts-extended = <&intc GIC_SPI 390 IRQ_TYPE_EDGE_RISING>,
1621 1542 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1622 1543 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1623 1544 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1624 1545 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1625 interrupt-names = "wd 1546 interrupt-names = "wdog", "fatal", "ready",
1626 "ha 1547 "handover", "stop-ack";
1627 1548
1628 px-supply = <&vreg_lv 1549 px-supply = <&vreg_lvs2a_1p8>;
1629 1550
1630 clocks = <&rpmcc RPM_ !! 1551 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1631 clock-names = "xo"; !! 1552 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
>> 1553 clock-names = "xo", "aggre2";
1632 1554
1633 memory-region = <&slp 1555 memory-region = <&slpi_mem>;
1634 1556
1635 qcom,smem-states = <& 1557 qcom,smem-states = <&slpi_smp2p_out 0>;
1636 qcom,smem-state-names 1558 qcom,smem-state-names = "stop";
1637 1559
1638 power-domains = <&rpm 1560 power-domains = <&rpmpd MSM8998_SSCCX>;
1639 power-domain-names = 1561 power-domain-names = "ssc_cx";
1640 1562
1641 status = "disabled"; 1563 status = "disabled";
1642 1564
1643 glink-edge { 1565 glink-edge {
1644 interrupts = 1566 interrupts = <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>;
1645 label = "dsps 1567 label = "dsps";
1646 qcom,remote-p 1568 qcom,remote-pid = <3>;
1647 mboxes = <&ap 1569 mboxes = <&apcs_glb 27>;
1648 }; 1570 };
1649 }; 1571 };
1650 1572
1651 stm: stm@6002000 { 1573 stm: stm@6002000 {
1652 compatible = "arm,cor 1574 compatible = "arm,coresight-stm", "arm,primecell";
1653 reg = <0x06002000 0x1 1575 reg = <0x06002000 0x1000>,
1654 <0x16280000 0x1 1576 <0x16280000 0x180000>;
1655 reg-names = "stm-base !! 1577 reg-names = "stm-base", "stm-data-base";
1656 status = "disabled"; 1578 status = "disabled";
1657 1579
1658 clocks = <&rpmcc RPM_ 1580 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1659 clock-names = "apb_pc 1581 clock-names = "apb_pclk", "atclk";
1660 1582
1661 out-ports { 1583 out-ports {
1662 port { 1584 port {
1663 stm_o 1585 stm_out: endpoint {
1664 1586 remote-endpoint = <&funnel0_in7>;
1665 }; 1587 };
1666 }; 1588 };
1667 }; 1589 };
1668 }; 1590 };
1669 1591
1670 funnel1: funnel@6041000 { 1592 funnel1: funnel@6041000 {
1671 compatible = "arm,cor 1593 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1672 reg = <0x06041000 0x1 1594 reg = <0x06041000 0x1000>;
1673 status = "disabled"; 1595 status = "disabled";
1674 1596
1675 clocks = <&rpmcc RPM_ 1597 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1676 clock-names = "apb_pc 1598 clock-names = "apb_pclk", "atclk";
1677 1599
1678 out-ports { 1600 out-ports {
1679 port { 1601 port {
1680 funne 1602 funnel0_out: endpoint {
1681 1603 remote-endpoint =
1682 1604 <&merge_funnel_in0>;
1683 }; 1605 };
1684 }; 1606 };
1685 }; 1607 };
1686 1608
1687 in-ports { 1609 in-ports {
1688 #address-cell 1610 #address-cells = <1>;
1689 #size-cells = 1611 #size-cells = <0>;
1690 1612
1691 port@7 { 1613 port@7 {
1692 reg = 1614 reg = <7>;
1693 funne 1615 funnel0_in7: endpoint {
1694 1616 remote-endpoint = <&stm_out>;
1695 }; 1617 };
1696 }; 1618 };
1697 }; 1619 };
1698 }; 1620 };
1699 1621
1700 funnel2: funnel@6042000 { 1622 funnel2: funnel@6042000 {
1701 compatible = "arm,cor 1623 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1702 reg = <0x06042000 0x1 1624 reg = <0x06042000 0x1000>;
1703 status = "disabled"; 1625 status = "disabled";
1704 1626
1705 clocks = <&rpmcc RPM_ 1627 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1706 clock-names = "apb_pc 1628 clock-names = "apb_pclk", "atclk";
1707 1629
1708 out-ports { 1630 out-ports {
1709 port { 1631 port {
1710 funne 1632 funnel1_out: endpoint {
1711 1633 remote-endpoint =
1712 1634 <&merge_funnel_in1>;
1713 }; 1635 };
1714 }; 1636 };
1715 }; 1637 };
1716 1638
1717 in-ports { 1639 in-ports {
1718 #address-cell 1640 #address-cells = <1>;
1719 #size-cells = 1641 #size-cells = <0>;
1720 1642
1721 port@6 { 1643 port@6 {
1722 reg = 1644 reg = <6>;
1723 funne 1645 funnel1_in6: endpoint {
1724 1646 remote-endpoint =
1725 1647 <&apss_merge_funnel_out>;
1726 }; 1648 };
1727 }; 1649 };
1728 }; 1650 };
1729 }; 1651 };
1730 1652
1731 funnel3: funnel@6045000 { 1653 funnel3: funnel@6045000 {
1732 compatible = "arm,cor 1654 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1733 reg = <0x06045000 0x1 1655 reg = <0x06045000 0x1000>;
1734 status = "disabled"; 1656 status = "disabled";
1735 1657
1736 clocks = <&rpmcc RPM_ 1658 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1737 clock-names = "apb_pc 1659 clock-names = "apb_pclk", "atclk";
1738 1660
1739 out-ports { 1661 out-ports {
1740 port { 1662 port {
1741 merge 1663 merge_funnel_out: endpoint {
1742 1664 remote-endpoint =
1743 1665 <&etf_in>;
1744 }; 1666 };
1745 }; 1667 };
1746 }; 1668 };
1747 1669
1748 in-ports { 1670 in-ports {
1749 #address-cell 1671 #address-cells = <1>;
1750 #size-cells = 1672 #size-cells = <0>;
1751 1673
1752 port@0 { 1674 port@0 {
1753 reg = 1675 reg = <0>;
1754 merge 1676 merge_funnel_in0: endpoint {
1755 1677 remote-endpoint =
1756 1678 <&funnel0_out>;
1757 }; 1679 };
1758 }; 1680 };
1759 1681
1760 port@1 { 1682 port@1 {
1761 reg = 1683 reg = <1>;
1762 merge 1684 merge_funnel_in1: endpoint {
1763 1685 remote-endpoint =
1764 1686 <&funnel1_out>;
1765 }; 1687 };
1766 }; 1688 };
1767 }; 1689 };
1768 }; 1690 };
1769 1691
1770 replicator1: replicator@60460 1692 replicator1: replicator@6046000 {
1771 compatible = "arm,cor 1693 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
1772 reg = <0x06046000 0x1 1694 reg = <0x06046000 0x1000>;
1773 status = "disabled"; 1695 status = "disabled";
1774 1696
1775 clocks = <&rpmcc RPM_ 1697 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1776 clock-names = "apb_pc 1698 clock-names = "apb_pclk", "atclk";
1777 1699
1778 out-ports { 1700 out-ports {
1779 port { 1701 port {
1780 repli 1702 replicator_out: endpoint {
1781 1703 remote-endpoint = <&etr_in>;
1782 }; 1704 };
1783 }; 1705 };
1784 }; 1706 };
1785 1707
1786 in-ports { 1708 in-ports {
1787 port { 1709 port {
1788 repli 1710 replicator_in: endpoint {
1789 1711 remote-endpoint = <&etf_out>;
1790 }; 1712 };
1791 }; 1713 };
1792 }; 1714 };
1793 }; 1715 };
1794 1716
1795 etf: etf@6047000 { 1717 etf: etf@6047000 {
1796 compatible = "arm,cor 1718 compatible = "arm,coresight-tmc", "arm,primecell";
1797 reg = <0x06047000 0x1 1719 reg = <0x06047000 0x1000>;
1798 status = "disabled"; 1720 status = "disabled";
1799 1721
1800 clocks = <&rpmcc RPM_ 1722 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1801 clock-names = "apb_pc 1723 clock-names = "apb_pclk", "atclk";
1802 1724
1803 out-ports { 1725 out-ports {
1804 port { 1726 port {
1805 etf_o 1727 etf_out: endpoint {
1806 1728 remote-endpoint =
1807 1729 <&replicator_in>;
1808 }; 1730 };
1809 }; 1731 };
1810 }; 1732 };
1811 1733
1812 in-ports { 1734 in-ports {
1813 port { 1735 port {
1814 etf_i 1736 etf_in: endpoint {
1815 1737 remote-endpoint =
1816 1738 <&merge_funnel_out>;
1817 }; 1739 };
1818 }; 1740 };
1819 }; 1741 };
1820 }; 1742 };
1821 1743
1822 etr: etr@6048000 { 1744 etr: etr@6048000 {
1823 compatible = "arm,cor 1745 compatible = "arm,coresight-tmc", "arm,primecell";
1824 reg = <0x06048000 0x1 1746 reg = <0x06048000 0x1000>;
1825 status = "disabled"; 1747 status = "disabled";
1826 1748
1827 clocks = <&rpmcc RPM_ 1749 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1828 clock-names = "apb_pc 1750 clock-names = "apb_pclk", "atclk";
1829 arm,scatter-gather; 1751 arm,scatter-gather;
1830 1752
1831 in-ports { 1753 in-ports {
1832 port { 1754 port {
1833 etr_i 1755 etr_in: endpoint {
1834 1756 remote-endpoint =
1835 1757 <&replicator_out>;
1836 }; 1758 };
1837 }; 1759 };
1838 }; 1760 };
1839 }; 1761 };
1840 1762
1841 etm1: etm@7840000 { 1763 etm1: etm@7840000 {
1842 compatible = "arm,cor 1764 compatible = "arm,coresight-etm4x", "arm,primecell";
1843 reg = <0x07840000 0x1 1765 reg = <0x07840000 0x1000>;
1844 status = "disabled"; 1766 status = "disabled";
1845 1767
1846 clocks = <&rpmcc RPM_ 1768 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1847 clock-names = "apb_pc 1769 clock-names = "apb_pclk", "atclk";
1848 1770
1849 cpu = <&CPU0>; 1771 cpu = <&CPU0>;
1850 1772
1851 out-ports { 1773 out-ports {
1852 port { 1774 port {
1853 etm0_ 1775 etm0_out: endpoint {
1854 1776 remote-endpoint =
1855 1777 <&apss_funnel_in0>;
1856 }; 1778 };
1857 }; 1779 };
1858 }; 1780 };
1859 }; 1781 };
1860 1782
1861 etm2: etm@7940000 { 1783 etm2: etm@7940000 {
1862 compatible = "arm,cor 1784 compatible = "arm,coresight-etm4x", "arm,primecell";
1863 reg = <0x07940000 0x1 1785 reg = <0x07940000 0x1000>;
1864 status = "disabled"; 1786 status = "disabled";
1865 1787
1866 clocks = <&rpmcc RPM_ 1788 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1867 clock-names = "apb_pc 1789 clock-names = "apb_pclk", "atclk";
1868 1790
1869 cpu = <&CPU1>; 1791 cpu = <&CPU1>;
1870 1792
1871 out-ports { 1793 out-ports {
1872 port { 1794 port {
1873 etm1_ 1795 etm1_out: endpoint {
1874 1796 remote-endpoint =
1875 1797 <&apss_funnel_in1>;
1876 }; 1798 };
1877 }; 1799 };
1878 }; 1800 };
1879 }; 1801 };
1880 1802
1881 etm3: etm@7a40000 { 1803 etm3: etm@7a40000 {
1882 compatible = "arm,cor 1804 compatible = "arm,coresight-etm4x", "arm,primecell";
1883 reg = <0x07a40000 0x1 1805 reg = <0x07a40000 0x1000>;
1884 status = "disabled"; 1806 status = "disabled";
1885 1807
1886 clocks = <&rpmcc RPM_ 1808 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1887 clock-names = "apb_pc 1809 clock-names = "apb_pclk", "atclk";
1888 1810
1889 cpu = <&CPU2>; 1811 cpu = <&CPU2>;
1890 1812
1891 out-ports { 1813 out-ports {
1892 port { 1814 port {
1893 etm2_ 1815 etm2_out: endpoint {
1894 1816 remote-endpoint =
1895 1817 <&apss_funnel_in2>;
1896 }; 1818 };
1897 }; 1819 };
1898 }; 1820 };
1899 }; 1821 };
1900 1822
1901 etm4: etm@7b40000 { 1823 etm4: etm@7b40000 {
1902 compatible = "arm,cor 1824 compatible = "arm,coresight-etm4x", "arm,primecell";
1903 reg = <0x07b40000 0x1 1825 reg = <0x07b40000 0x1000>;
1904 status = "disabled"; 1826 status = "disabled";
1905 1827
1906 clocks = <&rpmcc RPM_ 1828 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1907 clock-names = "apb_pc 1829 clock-names = "apb_pclk", "atclk";
1908 1830
1909 cpu = <&CPU3>; 1831 cpu = <&CPU3>;
1910 1832
1911 out-ports { 1833 out-ports {
1912 port { 1834 port {
1913 etm3_ 1835 etm3_out: endpoint {
1914 1836 remote-endpoint =
1915 1837 <&apss_funnel_in3>;
1916 }; 1838 };
1917 }; 1839 };
1918 }; 1840 };
1919 }; 1841 };
1920 1842
1921 funnel4: funnel@7b60000 { /* 1843 funnel4: funnel@7b60000 { /* APSS Funnel */
1922 compatible = "arm,cor 1844 compatible = "arm,coresight-etm4x", "arm,primecell";
1923 reg = <0x07b60000 0x1 1845 reg = <0x07b60000 0x1000>;
1924 status = "disabled"; 1846 status = "disabled";
1925 1847
1926 clocks = <&rpmcc RPM_ 1848 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1927 clock-names = "apb_pc 1849 clock-names = "apb_pclk", "atclk";
1928 1850
1929 out-ports { 1851 out-ports {
1930 port { 1852 port {
1931 apss_ 1853 apss_funnel_out: endpoint {
1932 1854 remote-endpoint =
1933 1855 <&apss_merge_funnel_in>;
1934 }; 1856 };
1935 }; 1857 };
1936 }; 1858 };
1937 1859
1938 in-ports { 1860 in-ports {
1939 #address-cell 1861 #address-cells = <1>;
1940 #size-cells = 1862 #size-cells = <0>;
1941 1863
1942 port@0 { 1864 port@0 {
1943 reg = 1865 reg = <0>;
1944 apss_ 1866 apss_funnel_in0: endpoint {
1945 1867 remote-endpoint =
1946 1868 <&etm0_out>;
1947 }; 1869 };
1948 }; 1870 };
1949 1871
1950 port@1 { 1872 port@1 {
1951 reg = 1873 reg = <1>;
1952 apss_ 1874 apss_funnel_in1: endpoint {
1953 1875 remote-endpoint =
1954 1876 <&etm1_out>;
1955 }; 1877 };
1956 }; 1878 };
1957 1879
1958 port@2 { 1880 port@2 {
1959 reg = 1881 reg = <2>;
1960 apss_ 1882 apss_funnel_in2: endpoint {
1961 1883 remote-endpoint =
1962 1884 <&etm2_out>;
1963 }; 1885 };
1964 }; 1886 };
1965 1887
1966 port@3 { 1888 port@3 {
1967 reg = 1889 reg = <3>;
1968 apss_ 1890 apss_funnel_in3: endpoint {
1969 1891 remote-endpoint =
1970 1892 <&etm3_out>;
1971 }; 1893 };
1972 }; 1894 };
1973 1895
1974 port@4 { 1896 port@4 {
1975 reg = 1897 reg = <4>;
1976 apss_ 1898 apss_funnel_in4: endpoint {
1977 1899 remote-endpoint =
1978 1900 <&etm4_out>;
1979 }; 1901 };
1980 }; 1902 };
1981 1903
1982 port@5 { 1904 port@5 {
1983 reg = 1905 reg = <5>;
1984 apss_ 1906 apss_funnel_in5: endpoint {
1985 1907 remote-endpoint =
1986 1908 <&etm5_out>;
1987 }; 1909 };
1988 }; 1910 };
1989 1911
1990 port@6 { 1912 port@6 {
1991 reg = 1913 reg = <6>;
1992 apss_ 1914 apss_funnel_in6: endpoint {
1993 1915 remote-endpoint =
1994 1916 <&etm6_out>;
1995 }; 1917 };
1996 }; 1918 };
1997 1919
1998 port@7 { 1920 port@7 {
1999 reg = 1921 reg = <7>;
2000 apss_ 1922 apss_funnel_in7: endpoint {
2001 1923 remote-endpoint =
2002 1924 <&etm7_out>;
2003 }; 1925 };
2004 }; 1926 };
2005 }; 1927 };
2006 }; 1928 };
2007 1929
2008 funnel5: funnel@7b70000 { 1930 funnel5: funnel@7b70000 {
2009 compatible = "arm,cor 1931 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2010 reg = <0x07b70000 0x1 1932 reg = <0x07b70000 0x1000>;
2011 status = "disabled"; 1933 status = "disabled";
2012 1934
2013 clocks = <&rpmcc RPM_ 1935 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2014 clock-names = "apb_pc 1936 clock-names = "apb_pclk", "atclk";
2015 1937
2016 out-ports { 1938 out-ports {
2017 port { 1939 port {
2018 apss_ 1940 apss_merge_funnel_out: endpoint {
2019 1941 remote-endpoint =
2020 1942 <&funnel1_in6>;
2021 }; 1943 };
2022 }; 1944 };
2023 }; 1945 };
2024 1946
2025 in-ports { 1947 in-ports {
2026 port { 1948 port {
2027 apss_ 1949 apss_merge_funnel_in: endpoint {
2028 1950 remote-endpoint =
2029 1951 <&apss_funnel_out>;
2030 }; 1952 };
2031 }; 1953 };
2032 }; 1954 };
2033 }; 1955 };
2034 1956
2035 etm5: etm@7c40000 { 1957 etm5: etm@7c40000 {
2036 compatible = "arm,cor 1958 compatible = "arm,coresight-etm4x", "arm,primecell";
2037 reg = <0x07c40000 0x1 1959 reg = <0x07c40000 0x1000>;
2038 status = "disabled"; 1960 status = "disabled";
2039 1961
2040 clocks = <&rpmcc RPM_ 1962 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2041 clock-names = "apb_pc 1963 clock-names = "apb_pclk", "atclk";
2042 1964
2043 cpu = <&CPU4>; 1965 cpu = <&CPU4>;
2044 1966
2045 out-ports { !! 1967 port{
2046 port { !! 1968 etm4_out: endpoint {
2047 etm4_ !! 1969 remote-endpoint = <&apss_funnel_in4>;
2048 <<
2049 }; <<
2050 }; 1970 };
2051 }; 1971 };
2052 }; 1972 };
2053 1973
2054 etm6: etm@7d40000 { 1974 etm6: etm@7d40000 {
2055 compatible = "arm,cor 1975 compatible = "arm,coresight-etm4x", "arm,primecell";
2056 reg = <0x07d40000 0x1 1976 reg = <0x07d40000 0x1000>;
2057 status = "disabled"; 1977 status = "disabled";
2058 1978
2059 clocks = <&rpmcc RPM_ 1979 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2060 clock-names = "apb_pc 1980 clock-names = "apb_pclk", "atclk";
2061 1981
2062 cpu = <&CPU5>; 1982 cpu = <&CPU5>;
2063 1983
2064 out-ports { !! 1984 port{
2065 port { !! 1985 etm5_out: endpoint {
2066 etm5_ !! 1986 remote-endpoint = <&apss_funnel_in5>;
2067 <<
2068 }; <<
2069 }; 1987 };
2070 }; 1988 };
2071 }; 1989 };
2072 1990
2073 etm7: etm@7e40000 { 1991 etm7: etm@7e40000 {
2074 compatible = "arm,cor 1992 compatible = "arm,coresight-etm4x", "arm,primecell";
2075 reg = <0x07e40000 0x1 1993 reg = <0x07e40000 0x1000>;
2076 status = "disabled"; 1994 status = "disabled";
2077 1995
2078 clocks = <&rpmcc RPM_ 1996 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2079 clock-names = "apb_pc 1997 clock-names = "apb_pclk", "atclk";
2080 1998
2081 cpu = <&CPU6>; 1999 cpu = <&CPU6>;
2082 2000
2083 out-ports { !! 2001 port{
2084 port { !! 2002 etm6_out: endpoint {
2085 etm6_ !! 2003 remote-endpoint = <&apss_funnel_in6>;
2086 <<
2087 }; <<
2088 }; 2004 };
2089 }; 2005 };
2090 }; 2006 };
2091 2007
2092 etm8: etm@7f40000 { 2008 etm8: etm@7f40000 {
2093 compatible = "arm,cor 2009 compatible = "arm,coresight-etm4x", "arm,primecell";
2094 reg = <0x07f40000 0x1 2010 reg = <0x07f40000 0x1000>;
2095 status = "disabled"; 2011 status = "disabled";
2096 2012
2097 clocks = <&rpmcc RPM_ 2013 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2098 clock-names = "apb_pc 2014 clock-names = "apb_pclk", "atclk";
2099 2015
2100 cpu = <&CPU7>; 2016 cpu = <&CPU7>;
2101 2017
2102 out-ports { !! 2018 port{
2103 port { !! 2019 etm7_out: endpoint {
2104 etm7_ !! 2020 remote-endpoint = <&apss_funnel_in7>;
2105 <<
2106 }; <<
2107 }; 2021 };
2108 }; 2022 };
2109 }; 2023 };
2110 2024
2111 sram@290000 { 2025 sram@290000 {
2112 compatible = "qcom,rp 2026 compatible = "qcom,rpm-stats";
2113 reg = <0x00290000 0x1 2027 reg = <0x00290000 0x10000>;
2114 }; 2028 };
2115 2029
2116 spmi_bus: spmi@800f000 { 2030 spmi_bus: spmi@800f000 {
2117 compatible = "qcom,sp 2031 compatible = "qcom,spmi-pmic-arb";
2118 reg = <0x0800f000 0x1 !! 2032 reg = <0x0800f000 0x1000>,
2119 <0x08400000 0x1 !! 2033 <0x08400000 0x1000000>,
2120 <0x09400000 0x1 !! 2034 <0x09400000 0x1000000>,
2121 <0x0a400000 0x2 !! 2035 <0x0a400000 0x220000>,
2122 <0x0800a000 0x3 !! 2036 <0x0800a000 0x3000>;
2123 reg-names = "core", " 2037 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
2124 interrupt-names = "pe 2038 interrupt-names = "periph_irq";
2125 interrupts = <GIC_SPI 2039 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
2126 qcom,ee = <0>; 2040 qcom,ee = <0>;
2127 qcom,channel = <0>; 2041 qcom,channel = <0>;
2128 #address-cells = <2>; 2042 #address-cells = <2>;
2129 #size-cells = <0>; 2043 #size-cells = <0>;
2130 interrupt-controller; 2044 interrupt-controller;
2131 #interrupt-cells = <4 2045 #interrupt-cells = <4>;
>> 2046 cell-index = <0>;
2132 }; 2047 };
2133 2048
2134 usb3: usb@a8f8800 { 2049 usb3: usb@a8f8800 {
2135 compatible = "qcom,ms 2050 compatible = "qcom,msm8998-dwc3", "qcom,dwc3";
2136 reg = <0x0a8f8800 0x4 2051 reg = <0x0a8f8800 0x400>;
2137 status = "disabled"; 2052 status = "disabled";
2138 #address-cells = <1>; 2053 #address-cells = <1>;
2139 #size-cells = <1>; 2054 #size-cells = <1>;
2140 ranges; 2055 ranges;
2141 2056
2142 clocks = <&gcc GCC_CF 2057 clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>,
2143 <&gcc GCC_US 2058 <&gcc GCC_USB30_MASTER_CLK>,
2144 <&gcc GCC_AG 2059 <&gcc GCC_AGGRE1_USB3_AXI_CLK>,
2145 <&gcc GCC_US !! 2060 <&gcc GCC_USB30_MOCK_UTMI_CLK>,
2146 <&gcc GCC_US !! 2061 <&gcc GCC_USB30_SLEEP_CLK>;
2147 clock-names = "cfg_no !! 2062 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
2148 "core", !! 2063 "sleep";
2149 "iface" <<
2150 "sleep" <<
2151 "mock_u <<
2152 2064
2153 assigned-clocks = <&g 2065 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
2154 <&g 2066 <&gcc GCC_USB30_MASTER_CLK>;
2155 assigned-clock-rates 2067 assigned-clock-rates = <19200000>, <120000000>;
2156 2068
2157 interrupts = <GIC_SPI !! 2069 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
2158 <GIC_SPI <<
2159 <GIC_SPI 2070 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
2160 interrupt-names = "pw !! 2071 interrupt-names = "hs_phy_irq", "ss_phy_irq";
2161 "qu <<
2162 "ss <<
2163 2072
2164 power-domains = <&gcc 2073 power-domains = <&gcc USB_30_GDSC>;
2165 2074
2166 resets = <&gcc GCC_US 2075 resets = <&gcc GCC_USB_30_BCR>;
2167 2076
2168 usb3_dwc3: usb@a80000 !! 2077 usb3_dwc3: dwc3@a800000 {
2169 compatible = 2078 compatible = "snps,dwc3";
2170 reg = <0x0a80 2079 reg = <0x0a800000 0xcd00>;
2171 interrupts = 2080 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
2172 snps,dis_u2_s 2081 snps,dis_u2_susphy_quirk;
2173 snps,dis_enbl 2082 snps,dis_enblslpm_quirk;
2174 snps,parkmode !! 2083 phys = <&qusb2phy>, <&usb1_ssphy>;
2175 phys = <&qusb <<
2176 phy-names = " 2084 phy-names = "usb2-phy", "usb3-phy";
2177 snps,has-lpm- 2085 snps,has-lpm-erratum;
2178 snps,hird-thr 2086 snps,hird-threshold = /bits/ 8 <0x10>;
2179 }; 2087 };
2180 }; 2088 };
2181 2089
2182 usb3phy: phy@c010000 { 2090 usb3phy: phy@c010000 {
2183 compatible = "qcom,ms 2091 compatible = "qcom,msm8998-qmp-usb3-phy";
2184 reg = <0x0c010000 0x1 !! 2092 reg = <0x0c010000 0x18c>;
>> 2093 status = "disabled";
>> 2094 #address-cells = <1>;
>> 2095 #size-cells = <1>;
>> 2096 ranges;
2185 2097
2186 clocks = <&gcc GCC_US 2098 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
2187 <&gcc GCC_US <<
2188 <&gcc GCC_US 2099 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2189 <&gcc GCC_US !! 2100 <&gcc GCC_USB3_CLKREF_CLK>;
2190 clock-names = "aux", !! 2101 clock-names = "aux", "cfg_ahb", "ref";
2191 "ref", <<
2192 "cfg_ah <<
2193 "pipe"; <<
2194 clock-output-names = <<
2195 #clock-cells = <0>; <<
2196 #phy-cells = <0>; <<
2197 2102
2198 resets = <&gcc GCC_US 2103 resets = <&gcc GCC_USB3_PHY_BCR>,
2199 <&gcc GCC_US 2104 <&gcc GCC_USB3PHY_PHY_BCR>;
2200 reset-names = "phy", !! 2105 reset-names = "phy", "common";
2201 "phy_ph <<
2202 <<
2203 qcom,tcsr-reg = <&tcs <<
2204 2106
2205 status = "disabled"; !! 2107 usb1_ssphy: phy@c010200 {
>> 2108 reg = <0xc010200 0x128>,
>> 2109 <0xc010400 0x200>,
>> 2110 <0xc010c00 0x20c>,
>> 2111 <0xc010600 0x128>,
>> 2112 <0xc010800 0x200>;
>> 2113 #phy-cells = <0>;
>> 2114 #clock-cells = <1>;
>> 2115 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
>> 2116 clock-names = "pipe0";
>> 2117 clock-output-names = "usb3_phy_pipe_clk_src";
>> 2118 };
2206 }; 2119 };
2207 2120
2208 qusb2phy: phy@c012000 { 2121 qusb2phy: phy@c012000 {
2209 compatible = "qcom,ms 2122 compatible = "qcom,msm8998-qusb2-phy";
2210 reg = <0x0c012000 0x2 2123 reg = <0x0c012000 0x2a8>;
2211 status = "disabled"; 2124 status = "disabled";
2212 #phy-cells = <0>; 2125 #phy-cells = <0>;
2213 2126
2214 clocks = <&gcc GCC_US 2127 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2215 <&gcc GCC_RX 2128 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
2216 clock-names = "cfg_ah 2129 clock-names = "cfg_ahb", "ref";
2217 2130
2218 resets = <&gcc GCC_QU 2131 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2219 2132
2220 nvmem-cells = <&qusb2 2133 nvmem-cells = <&qusb2_hstx_trim>;
2221 }; 2134 };
2222 2135
2223 sdhc2: mmc@c0a4900 { !! 2136 sdhc2: sdhci@c0a4900 {
2224 compatible = "qcom,ms !! 2137 compatible = "qcom,sdhci-msm-v4";
2225 reg = <0x0c0a4900 0x3 2138 reg = <0x0c0a4900 0x314>, <0x0c0a4000 0x800>;
2226 reg-names = "hc", "co !! 2139 reg-names = "hc_mem", "core_mem";
2227 2140
2228 interrupts = <GIC_SPI 2141 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
2229 <GIC_SPI 2142 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
2230 interrupt-names = "hc 2143 interrupt-names = "hc_irq", "pwr_irq";
2231 2144
2232 clock-names = "iface" 2145 clock-names = "iface", "core", "xo";
2233 clocks = <&gcc GCC_SD 2146 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2234 <&gcc GCC_SD 2147 <&gcc GCC_SDCC2_APPS_CLK>,
2235 <&rpmcc RPM_ !! 2148 <&xo>;
2236 bus-width = <4>; 2149 bus-width = <4>;
2237 status = "disabled"; 2150 status = "disabled";
2238 }; 2151 };
2239 2152
2240 blsp1_dma: dma-controller@c14 2153 blsp1_dma: dma-controller@c144000 {
2241 compatible = "qcom,ba 2154 compatible = "qcom,bam-v1.7.0";
2242 reg = <0x0c144000 0x2 2155 reg = <0x0c144000 0x25000>;
2243 interrupts = <GIC_SPI 2156 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
2244 clocks = <&gcc GCC_BL 2157 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
2245 clock-names = "bam_cl 2158 clock-names = "bam_clk";
2246 #dma-cells = <1>; 2159 #dma-cells = <1>;
2247 qcom,ee = <0>; 2160 qcom,ee = <0>;
2248 qcom,controlled-remot 2161 qcom,controlled-remotely;
2249 num-channels = <18>; 2162 num-channels = <18>;
2250 qcom,num-ees = <4>; 2163 qcom,num-ees = <4>;
2251 }; 2164 };
2252 2165
2253 blsp1_uart3: serial@c171000 { 2166 blsp1_uart3: serial@c171000 {
2254 compatible = "qcom,ms 2167 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2255 reg = <0x0c171000 0x1 2168 reg = <0x0c171000 0x1000>;
2256 interrupts = <GIC_SPI 2169 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
2257 clocks = <&gcc GCC_BL 2170 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
2258 <&gcc GCC_BL 2171 <&gcc GCC_BLSP1_AHB_CLK>;
2259 clock-names = "core", 2172 clock-names = "core", "iface";
2260 dmas = <&blsp1_dma 4> 2173 dmas = <&blsp1_dma 4>, <&blsp1_dma 5>;
2261 dma-names = "tx", "rx 2174 dma-names = "tx", "rx";
2262 pinctrl-names = "defa 2175 pinctrl-names = "default";
2263 pinctrl-0 = <&blsp1_u 2176 pinctrl-0 = <&blsp1_uart3_on>;
2264 status = "disabled"; 2177 status = "disabled";
2265 }; 2178 };
2266 2179
2267 blsp1_i2c1: i2c@c175000 { 2180 blsp1_i2c1: i2c@c175000 {
2268 compatible = "qcom,i2 2181 compatible = "qcom,i2c-qup-v2.2.1";
2269 reg = <0x0c175000 0x6 2182 reg = <0x0c175000 0x600>;
2270 interrupts = <GIC_SPI 2183 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
2271 2184
2272 clocks = <&gcc GCC_BL 2185 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
2273 <&gcc GCC_BL 2186 <&gcc GCC_BLSP1_AHB_CLK>;
2274 clock-names = "core", 2187 clock-names = "core", "iface";
2275 dmas = <&blsp1_dma 6> 2188 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>;
2276 dma-names = "tx", "rx 2189 dma-names = "tx", "rx";
2277 pinctrl-names = "defa 2190 pinctrl-names = "default", "sleep";
2278 pinctrl-0 = <&blsp1_i 2191 pinctrl-0 = <&blsp1_i2c1_default>;
2279 pinctrl-1 = <&blsp1_i 2192 pinctrl-1 = <&blsp1_i2c1_sleep>;
2280 clock-frequency = <40 2193 clock-frequency = <400000>;
2281 2194
2282 status = "disabled"; 2195 status = "disabled";
2283 #address-cells = <1>; 2196 #address-cells = <1>;
2284 #size-cells = <0>; 2197 #size-cells = <0>;
2285 }; 2198 };
2286 2199
2287 blsp1_i2c2: i2c@c176000 { 2200 blsp1_i2c2: i2c@c176000 {
2288 compatible = "qcom,i2 2201 compatible = "qcom,i2c-qup-v2.2.1";
2289 reg = <0x0c176000 0x6 2202 reg = <0x0c176000 0x600>;
2290 interrupts = <GIC_SPI 2203 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
2291 2204
2292 clocks = <&gcc GCC_BL 2205 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
2293 <&gcc GCC_BL 2206 <&gcc GCC_BLSP1_AHB_CLK>;
2294 clock-names = "core", 2207 clock-names = "core", "iface";
2295 dmas = <&blsp1_dma 8> 2208 dmas = <&blsp1_dma 8>, <&blsp1_dma 9>;
2296 dma-names = "tx", "rx 2209 dma-names = "tx", "rx";
2297 pinctrl-names = "defa 2210 pinctrl-names = "default", "sleep";
2298 pinctrl-0 = <&blsp1_i 2211 pinctrl-0 = <&blsp1_i2c2_default>;
2299 pinctrl-1 = <&blsp1_i 2212 pinctrl-1 = <&blsp1_i2c2_sleep>;
2300 clock-frequency = <40 2213 clock-frequency = <400000>;
2301 2214
2302 status = "disabled"; 2215 status = "disabled";
2303 #address-cells = <1>; 2216 #address-cells = <1>;
2304 #size-cells = <0>; 2217 #size-cells = <0>;
2305 }; 2218 };
2306 2219
2307 blsp1_i2c3: i2c@c177000 { 2220 blsp1_i2c3: i2c@c177000 {
2308 compatible = "qcom,i2 2221 compatible = "qcom,i2c-qup-v2.2.1";
2309 reg = <0x0c177000 0x6 2222 reg = <0x0c177000 0x600>;
2310 interrupts = <GIC_SPI 2223 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
2311 2224
2312 clocks = <&gcc GCC_BL 2225 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
2313 <&gcc GCC_BL 2226 <&gcc GCC_BLSP1_AHB_CLK>;
2314 clock-names = "core", 2227 clock-names = "core", "iface";
2315 dmas = <&blsp1_dma 10 2228 dmas = <&blsp1_dma 10>, <&blsp1_dma 11>;
2316 dma-names = "tx", "rx 2229 dma-names = "tx", "rx";
2317 pinctrl-names = "defa 2230 pinctrl-names = "default", "sleep";
2318 pinctrl-0 = <&blsp1_i 2231 pinctrl-0 = <&blsp1_i2c3_default>;
2319 pinctrl-1 = <&blsp1_i 2232 pinctrl-1 = <&blsp1_i2c3_sleep>;
2320 clock-frequency = <40 2233 clock-frequency = <400000>;
2321 2234
2322 status = "disabled"; 2235 status = "disabled";
2323 #address-cells = <1>; 2236 #address-cells = <1>;
2324 #size-cells = <0>; 2237 #size-cells = <0>;
2325 }; 2238 };
2326 2239
2327 blsp1_i2c4: i2c@c178000 { 2240 blsp1_i2c4: i2c@c178000 {
2328 compatible = "qcom,i2 2241 compatible = "qcom,i2c-qup-v2.2.1";
2329 reg = <0x0c178000 0x6 2242 reg = <0x0c178000 0x600>;
2330 interrupts = <GIC_SPI 2243 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
2331 2244
2332 clocks = <&gcc GCC_BL 2245 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
2333 <&gcc GCC_BL 2246 <&gcc GCC_BLSP1_AHB_CLK>;
2334 clock-names = "core", 2247 clock-names = "core", "iface";
2335 dmas = <&blsp1_dma 12 2248 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
2336 dma-names = "tx", "rx 2249 dma-names = "tx", "rx";
2337 pinctrl-names = "defa 2250 pinctrl-names = "default", "sleep";
2338 pinctrl-0 = <&blsp1_i 2251 pinctrl-0 = <&blsp1_i2c4_default>;
2339 pinctrl-1 = <&blsp1_i 2252 pinctrl-1 = <&blsp1_i2c4_sleep>;
2340 clock-frequency = <40 2253 clock-frequency = <400000>;
2341 2254
2342 status = "disabled"; 2255 status = "disabled";
2343 #address-cells = <1>; 2256 #address-cells = <1>;
2344 #size-cells = <0>; 2257 #size-cells = <0>;
2345 }; 2258 };
2346 2259
2347 blsp1_i2c5: i2c@c179000 { 2260 blsp1_i2c5: i2c@c179000 {
2348 compatible = "qcom,i2 2261 compatible = "qcom,i2c-qup-v2.2.1";
2349 reg = <0x0c179000 0x6 2262 reg = <0x0c179000 0x600>;
2350 interrupts = <GIC_SPI 2263 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
2351 2264
2352 clocks = <&gcc GCC_BL 2265 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
2353 <&gcc GCC_BL 2266 <&gcc GCC_BLSP1_AHB_CLK>;
2354 clock-names = "core", 2267 clock-names = "core", "iface";
2355 dmas = <&blsp1_dma 14 2268 dmas = <&blsp1_dma 14>, <&blsp1_dma 15>;
2356 dma-names = "tx", "rx 2269 dma-names = "tx", "rx";
2357 pinctrl-names = "defa 2270 pinctrl-names = "default", "sleep";
2358 pinctrl-0 = <&blsp1_i 2271 pinctrl-0 = <&blsp1_i2c5_default>;
2359 pinctrl-1 = <&blsp1_i 2272 pinctrl-1 = <&blsp1_i2c5_sleep>;
2360 clock-frequency = <40 2273 clock-frequency = <400000>;
2361 2274
2362 status = "disabled"; 2275 status = "disabled";
2363 #address-cells = <1>; 2276 #address-cells = <1>;
2364 #size-cells = <0>; 2277 #size-cells = <0>;
2365 }; 2278 };
2366 2279
2367 blsp1_i2c6: i2c@c17a000 { 2280 blsp1_i2c6: i2c@c17a000 {
2368 compatible = "qcom,i2 2281 compatible = "qcom,i2c-qup-v2.2.1";
2369 reg = <0x0c17a000 0x6 2282 reg = <0x0c17a000 0x600>;
2370 interrupts = <GIC_SPI 2283 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
2371 2284
2372 clocks = <&gcc GCC_BL 2285 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
2373 <&gcc GCC_BL 2286 <&gcc GCC_BLSP1_AHB_CLK>;
2374 clock-names = "core", 2287 clock-names = "core", "iface";
2375 dmas = <&blsp1_dma 16 2288 dmas = <&blsp1_dma 16>, <&blsp1_dma 17>;
2376 dma-names = "tx", "rx 2289 dma-names = "tx", "rx";
2377 pinctrl-names = "defa 2290 pinctrl-names = "default", "sleep";
2378 pinctrl-0 = <&blsp1_i 2291 pinctrl-0 = <&blsp1_i2c6_default>;
2379 pinctrl-1 = <&blsp1_i 2292 pinctrl-1 = <&blsp1_i2c6_sleep>;
2380 clock-frequency = <40 2293 clock-frequency = <400000>;
2381 2294
2382 status = "disabled"; 2295 status = "disabled";
2383 #address-cells = <1>; 2296 #address-cells = <1>;
2384 #size-cells = <0>; 2297 #size-cells = <0>;
2385 }; 2298 };
2386 2299
2387 blsp1_spi1: spi@c175000 { <<
2388 compatible = "qcom,sp <<
2389 reg = <0x0c175000 0x6 <<
2390 interrupts = <GIC_SPI <<
2391 <<
2392 clocks = <&gcc GCC_BL <<
2393 <&gcc GCC_BL <<
2394 clock-names = "core", <<
2395 dmas = <&blsp1_dma 6> <<
2396 dma-names = "tx", "rx <<
2397 pinctrl-names = "defa <<
2398 pinctrl-0 = <&blsp1_s <<
2399 <<
2400 status = "disabled"; <<
2401 #address-cells = <1>; <<
2402 #size-cells = <0>; <<
2403 }; <<
2404 <<
2405 blsp1_spi2: spi@c176000 { <<
2406 compatible = "qcom,sp <<
2407 reg = <0x0c176000 0x6 <<
2408 interrupts = <GIC_SPI <<
2409 <<
2410 clocks = <&gcc GCC_BL <<
2411 <&gcc GCC_BL <<
2412 clock-names = "core", <<
2413 dmas = <&blsp1_dma 8> <<
2414 dma-names = "tx", "rx <<
2415 pinctrl-names = "defa <<
2416 pinctrl-0 = <&blsp1_s <<
2417 <<
2418 status = "disabled"; <<
2419 #address-cells = <1>; <<
2420 #size-cells = <0>; <<
2421 }; <<
2422 <<
2423 blsp1_spi3: spi@c177000 { <<
2424 compatible = "qcom,sp <<
2425 reg = <0x0c177000 0x6 <<
2426 interrupts = <GIC_SPI <<
2427 <<
2428 clocks = <&gcc GCC_BL <<
2429 <&gcc GCC_BL <<
2430 clock-names = "core", <<
2431 dmas = <&blsp1_dma 10 <<
2432 dma-names = "tx", "rx <<
2433 pinctrl-names = "defa <<
2434 pinctrl-0 = <&blsp1_s <<
2435 <<
2436 status = "disabled"; <<
2437 #address-cells = <1>; <<
2438 #size-cells = <0>; <<
2439 }; <<
2440 <<
2441 blsp1_spi4: spi@c178000 { <<
2442 compatible = "qcom,sp <<
2443 reg = <0x0c178000 0x6 <<
2444 interrupts = <GIC_SPI <<
2445 <<
2446 clocks = <&gcc GCC_BL <<
2447 <&gcc GCC_BL <<
2448 clock-names = "core", <<
2449 dmas = <&blsp1_dma 12 <<
2450 dma-names = "tx", "rx <<
2451 pinctrl-names = "defa <<
2452 pinctrl-0 = <&blsp1_s <<
2453 <<
2454 status = "disabled"; <<
2455 #address-cells = <1>; <<
2456 #size-cells = <0>; <<
2457 }; <<
2458 <<
2459 blsp1_spi5: spi@c179000 { <<
2460 compatible = "qcom,sp <<
2461 reg = <0x0c179000 0x6 <<
2462 interrupts = <GIC_SPI <<
2463 <<
2464 clocks = <&gcc GCC_BL <<
2465 <&gcc GCC_BL <<
2466 clock-names = "core", <<
2467 dmas = <&blsp1_dma 14 <<
2468 dma-names = "tx", "rx <<
2469 pinctrl-names = "defa <<
2470 pinctrl-0 = <&blsp1_s <<
2471 <<
2472 status = "disabled"; <<
2473 #address-cells = <1>; <<
2474 #size-cells = <0>; <<
2475 }; <<
2476 <<
2477 blsp1_spi6: spi@c17a000 { <<
2478 compatible = "qcom,sp <<
2479 reg = <0x0c17a000 0x6 <<
2480 interrupts = <GIC_SPI <<
2481 <<
2482 clocks = <&gcc GCC_BL <<
2483 <&gcc GCC_BL <<
2484 clock-names = "core", <<
2485 dmas = <&blsp1_dma 16 <<
2486 dma-names = "tx", "rx <<
2487 pinctrl-names = "defa <<
2488 pinctrl-0 = <&blsp1_s <<
2489 <<
2490 status = "disabled"; <<
2491 #address-cells = <1>; <<
2492 #size-cells = <0>; <<
2493 }; <<
2494 <<
2495 blsp2_dma: dma-controller@c18 2300 blsp2_dma: dma-controller@c184000 {
2496 compatible = "qcom,ba 2301 compatible = "qcom,bam-v1.7.0";
2497 reg = <0x0c184000 0x2 2302 reg = <0x0c184000 0x25000>;
2498 interrupts = <GIC_SPI 2303 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
2499 clocks = <&gcc GCC_BL 2304 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
2500 clock-names = "bam_cl 2305 clock-names = "bam_clk";
2501 #dma-cells = <1>; 2306 #dma-cells = <1>;
2502 qcom,ee = <0>; 2307 qcom,ee = <0>;
2503 qcom,controlled-remot 2308 qcom,controlled-remotely;
2504 num-channels = <18>; 2309 num-channels = <18>;
2505 qcom,num-ees = <4>; 2310 qcom,num-ees = <4>;
2506 }; 2311 };
2507 2312
2508 blsp2_uart1: serial@c1b0000 { 2313 blsp2_uart1: serial@c1b0000 {
2509 compatible = "qcom,ms 2314 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2510 reg = <0x0c1b0000 0x1 2315 reg = <0x0c1b0000 0x1000>;
2511 interrupts = <GIC_SPI 2316 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
2512 clocks = <&gcc GCC_BL 2317 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
2513 <&gcc GCC_BL 2318 <&gcc GCC_BLSP2_AHB_CLK>;
2514 clock-names = "core", 2319 clock-names = "core", "iface";
2515 status = "disabled"; 2320 status = "disabled";
2516 }; 2321 };
2517 2322
2518 blsp2_i2c1: i2c@c1b5000 { 2323 blsp2_i2c1: i2c@c1b5000 {
2519 compatible = "qcom,i2 2324 compatible = "qcom,i2c-qup-v2.2.1";
2520 reg = <0x0c1b5000 0x6 2325 reg = <0x0c1b5000 0x600>;
2521 interrupts = <GIC_SPI 2326 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
2522 2327
2523 clocks = <&gcc GCC_BL 2328 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
2524 <&gcc GCC_BL 2329 <&gcc GCC_BLSP2_AHB_CLK>;
2525 clock-names = "core", 2330 clock-names = "core", "iface";
2526 dmas = <&blsp2_dma 6> 2331 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>;
2527 dma-names = "tx", "rx 2332 dma-names = "tx", "rx";
2528 pinctrl-names = "defa 2333 pinctrl-names = "default", "sleep";
2529 pinctrl-0 = <&blsp2_i 2334 pinctrl-0 = <&blsp2_i2c1_default>;
2530 pinctrl-1 = <&blsp2_i 2335 pinctrl-1 = <&blsp2_i2c1_sleep>;
2531 clock-frequency = <40 2336 clock-frequency = <400000>;
2532 2337
2533 status = "disabled"; 2338 status = "disabled";
2534 #address-cells = <1>; 2339 #address-cells = <1>;
2535 #size-cells = <0>; 2340 #size-cells = <0>;
2536 }; 2341 };
2537 2342
2538 blsp2_i2c2: i2c@c1b6000 { 2343 blsp2_i2c2: i2c@c1b6000 {
2539 compatible = "qcom,i2 2344 compatible = "qcom,i2c-qup-v2.2.1";
2540 reg = <0x0c1b6000 0x6 2345 reg = <0x0c1b6000 0x600>;
2541 interrupts = <GIC_SPI 2346 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
2542 2347
2543 clocks = <&gcc GCC_BL 2348 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
2544 <&gcc GCC_BL 2349 <&gcc GCC_BLSP2_AHB_CLK>;
2545 clock-names = "core", 2350 clock-names = "core", "iface";
2546 dmas = <&blsp2_dma 8> 2351 dmas = <&blsp2_dma 8>, <&blsp2_dma 9>;
2547 dma-names = "tx", "rx 2352 dma-names = "tx", "rx";
2548 pinctrl-names = "defa 2353 pinctrl-names = "default", "sleep";
2549 pinctrl-0 = <&blsp2_i 2354 pinctrl-0 = <&blsp2_i2c2_default>;
2550 pinctrl-1 = <&blsp2_i 2355 pinctrl-1 = <&blsp2_i2c2_sleep>;
2551 clock-frequency = <40 2356 clock-frequency = <400000>;
2552 2357
2553 status = "disabled"; 2358 status = "disabled";
2554 #address-cells = <1>; 2359 #address-cells = <1>;
2555 #size-cells = <0>; 2360 #size-cells = <0>;
2556 }; 2361 };
2557 2362
2558 blsp2_i2c3: i2c@c1b7000 { 2363 blsp2_i2c3: i2c@c1b7000 {
2559 compatible = "qcom,i2 2364 compatible = "qcom,i2c-qup-v2.2.1";
2560 reg = <0x0c1b7000 0x6 2365 reg = <0x0c1b7000 0x600>;
2561 interrupts = <GIC_SPI 2366 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
2562 2367
2563 clocks = <&gcc GCC_BL 2368 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
2564 <&gcc GCC_BL 2369 <&gcc GCC_BLSP2_AHB_CLK>;
2565 clock-names = "core", 2370 clock-names = "core", "iface";
2566 dmas = <&blsp2_dma 10 2371 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>;
2567 dma-names = "tx", "rx 2372 dma-names = "tx", "rx";
2568 pinctrl-names = "defa 2373 pinctrl-names = "default", "sleep";
2569 pinctrl-0 = <&blsp2_i 2374 pinctrl-0 = <&blsp2_i2c3_default>;
2570 pinctrl-1 = <&blsp2_i 2375 pinctrl-1 = <&blsp2_i2c3_sleep>;
2571 clock-frequency = <40 2376 clock-frequency = <400000>;
2572 2377
2573 status = "disabled"; 2378 status = "disabled";
2574 #address-cells = <1>; 2379 #address-cells = <1>;
2575 #size-cells = <0>; 2380 #size-cells = <0>;
2576 }; 2381 };
2577 2382
2578 blsp2_i2c4: i2c@c1b8000 { 2383 blsp2_i2c4: i2c@c1b8000 {
2579 compatible = "qcom,i2 2384 compatible = "qcom,i2c-qup-v2.2.1";
2580 reg = <0x0c1b8000 0x6 2385 reg = <0x0c1b8000 0x600>;
2581 interrupts = <GIC_SPI 2386 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
2582 2387
2583 clocks = <&gcc GCC_BL 2388 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>,
2584 <&gcc GCC_BL 2389 <&gcc GCC_BLSP2_AHB_CLK>;
2585 clock-names = "core", 2390 clock-names = "core", "iface";
2586 dmas = <&blsp2_dma 12 2391 dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
2587 dma-names = "tx", "rx 2392 dma-names = "tx", "rx";
2588 pinctrl-names = "defa 2393 pinctrl-names = "default", "sleep";
2589 pinctrl-0 = <&blsp2_i 2394 pinctrl-0 = <&blsp2_i2c4_default>;
2590 pinctrl-1 = <&blsp2_i 2395 pinctrl-1 = <&blsp2_i2c4_sleep>;
2591 clock-frequency = <40 2396 clock-frequency = <400000>;
2592 2397
2593 status = "disabled"; 2398 status = "disabled";
2594 #address-cells = <1>; 2399 #address-cells = <1>;
2595 #size-cells = <0>; 2400 #size-cells = <0>;
2596 }; 2401 };
2597 2402
2598 blsp2_i2c5: i2c@c1b9000 { 2403 blsp2_i2c5: i2c@c1b9000 {
2599 compatible = "qcom,i2 2404 compatible = "qcom,i2c-qup-v2.2.1";
2600 reg = <0x0c1b9000 0x6 2405 reg = <0x0c1b9000 0x600>;
2601 interrupts = <GIC_SPI 2406 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
2602 2407
2603 clocks = <&gcc GCC_BL 2408 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,
2604 <&gcc GCC_BL 2409 <&gcc GCC_BLSP2_AHB_CLK>;
2605 clock-names = "core", 2410 clock-names = "core", "iface";
2606 dmas = <&blsp2_dma 14 2411 dmas = <&blsp2_dma 14>, <&blsp2_dma 15>;
2607 dma-names = "tx", "rx 2412 dma-names = "tx", "rx";
2608 pinctrl-names = "defa 2413 pinctrl-names = "default", "sleep";
2609 pinctrl-0 = <&blsp2_i 2414 pinctrl-0 = <&blsp2_i2c5_default>;
2610 pinctrl-1 = <&blsp2_i 2415 pinctrl-1 = <&blsp2_i2c5_sleep>;
2611 clock-frequency = <40 2416 clock-frequency = <400000>;
2612 2417
2613 status = "disabled"; 2418 status = "disabled";
2614 #address-cells = <1>; 2419 #address-cells = <1>;
2615 #size-cells = <0>; 2420 #size-cells = <0>;
2616 }; 2421 };
2617 2422
2618 blsp2_i2c6: i2c@c1ba000 { 2423 blsp2_i2c6: i2c@c1ba000 {
2619 compatible = "qcom,i2 2424 compatible = "qcom,i2c-qup-v2.2.1";
2620 reg = <0x0c1ba000 0x6 2425 reg = <0x0c1ba000 0x600>;
2621 interrupts = <GIC_SPI 2426 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
2622 2427
2623 clocks = <&gcc GCC_BL 2428 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>,
2624 <&gcc GCC_BL 2429 <&gcc GCC_BLSP2_AHB_CLK>;
2625 clock-names = "core", 2430 clock-names = "core", "iface";
2626 dmas = <&blsp2_dma 16 2431 dmas = <&blsp2_dma 16>, <&blsp2_dma 17>;
2627 dma-names = "tx", "rx 2432 dma-names = "tx", "rx";
2628 pinctrl-names = "defa 2433 pinctrl-names = "default", "sleep";
2629 pinctrl-0 = <&blsp2_i 2434 pinctrl-0 = <&blsp2_i2c6_default>;
2630 pinctrl-1 = <&blsp2_i 2435 pinctrl-1 = <&blsp2_i2c6_sleep>;
2631 clock-frequency = <40 2436 clock-frequency = <400000>;
2632 2437
2633 status = "disabled"; 2438 status = "disabled";
2634 #address-cells = <1>; 2439 #address-cells = <1>;
2635 #size-cells = <0>; 2440 #size-cells = <0>;
2636 }; 2441 };
2637 2442
2638 blsp2_spi1: spi@c1b5000 { <<
2639 compatible = "qcom,sp <<
2640 reg = <0x0c1b5000 0x6 <<
2641 interrupts = <GIC_SPI <<
2642 <<
2643 clocks = <&gcc GCC_BL <<
2644 <&gcc GCC_BL <<
2645 clock-names = "core", <<
2646 dmas = <&blsp2_dma 6> <<
2647 dma-names = "tx", "rx <<
2648 pinctrl-names = "defa <<
2649 pinctrl-0 = <&blsp2_s <<
2650 <<
2651 status = "disabled"; <<
2652 #address-cells = <1>; <<
2653 #size-cells = <0>; <<
2654 }; <<
2655 <<
2656 blsp2_spi2: spi@c1b6000 { <<
2657 compatible = "qcom,sp <<
2658 reg = <0x0c1b6000 0x6 <<
2659 interrupts = <GIC_SPI <<
2660 <<
2661 clocks = <&gcc GCC_BL <<
2662 <&gcc GCC_BL <<
2663 clock-names = "core", <<
2664 dmas = <&blsp2_dma 8> <<
2665 dma-names = "tx", "rx <<
2666 pinctrl-names = "defa <<
2667 pinctrl-0 = <&blsp2_s <<
2668 <<
2669 status = "disabled"; <<
2670 #address-cells = <1>; <<
2671 #size-cells = <0>; <<
2672 }; <<
2673 <<
2674 blsp2_spi3: spi@c1b7000 { <<
2675 compatible = "qcom,sp <<
2676 reg = <0x0c1b7000 0x6 <<
2677 interrupts = <GIC_SPI <<
2678 <<
2679 clocks = <&gcc GCC_BL <<
2680 <&gcc GCC_BL <<
2681 clock-names = "core", <<
2682 dmas = <&blsp2_dma 10 <<
2683 dma-names = "tx", "rx <<
2684 pinctrl-names = "defa <<
2685 pinctrl-0 = <&blsp2_s <<
2686 <<
2687 status = "disabled"; <<
2688 #address-cells = <1>; <<
2689 #size-cells = <0>; <<
2690 }; <<
2691 <<
2692 blsp2_spi4: spi@c1b8000 { <<
2693 compatible = "qcom,sp <<
2694 reg = <0x0c1b8000 0x6 <<
2695 interrupts = <GIC_SPI <<
2696 <<
2697 clocks = <&gcc GCC_BL <<
2698 <&gcc GCC_BL <<
2699 clock-names = "core", <<
2700 dmas = <&blsp2_dma 12 <<
2701 dma-names = "tx", "rx <<
2702 pinctrl-names = "defa <<
2703 pinctrl-0 = <&blsp2_s <<
2704 <<
2705 status = "disabled"; <<
2706 #address-cells = <1>; <<
2707 #size-cells = <0>; <<
2708 }; <<
2709 <<
2710 blsp2_spi5: spi@c1b9000 { <<
2711 compatible = "qcom,sp <<
2712 reg = <0x0c1b9000 0x6 <<
2713 interrupts = <GIC_SPI <<
2714 <<
2715 clocks = <&gcc GCC_BL <<
2716 <&gcc GCC_BL <<
2717 clock-names = "core", <<
2718 dmas = <&blsp2_dma 14 <<
2719 dma-names = "tx", "rx <<
2720 pinctrl-names = "defa <<
2721 pinctrl-0 = <&blsp2_s <<
2722 <<
2723 status = "disabled"; <<
2724 #address-cells = <1>; <<
2725 #size-cells = <0>; <<
2726 }; <<
2727 <<
2728 blsp2_spi6: spi@c1ba000 { <<
2729 compatible = "qcom,sp <<
2730 reg = <0x0c1ba000 0x6 <<
2731 interrupts = <GIC_SPI <<
2732 <<
2733 clocks = <&gcc GCC_BL <<
2734 <&gcc GCC_BL <<
2735 clock-names = "core", <<
2736 dmas = <&blsp2_dma 16 <<
2737 dma-names = "tx", "rx <<
2738 pinctrl-names = "defa <<
2739 pinctrl-0 = <&blsp2_s <<
2740 <<
2741 status = "disabled"; <<
2742 #address-cells = <1>; <<
2743 #size-cells = <0>; <<
2744 }; <<
2745 <<
2746 mmcc: clock-controller@c8c000 2443 mmcc: clock-controller@c8c0000 {
2747 compatible = "qcom,mm 2444 compatible = "qcom,mmcc-msm8998";
2748 #clock-cells = <1>; 2445 #clock-cells = <1>;
2749 #reset-cells = <1>; 2446 #reset-cells = <1>;
2750 #power-domain-cells = 2447 #power-domain-cells = <1>;
2751 reg = <0xc8c0000 0x40 2448 reg = <0xc8c0000 0x40000>;
>> 2449 status = "disabled";
2752 2450
2753 clock-names = "xo", 2451 clock-names = "xo",
2754 "gpll0" 2452 "gpll0",
2755 "dsi0ds 2453 "dsi0dsi",
2756 "dsi0by 2454 "dsi0byte",
2757 "dsi1ds 2455 "dsi1dsi",
2758 "dsi1by 2456 "dsi1byte",
2759 "hdmipl 2457 "hdmipll",
2760 "dplink 2458 "dplink",
2761 "dpvco" 2459 "dpvco",
2762 "gpll0_ !! 2460 "core_bi_pll_test_se";
2763 clocks = <&rpmcc RPM_ 2461 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
2764 <&gcc GCC_MM 2462 <&gcc GCC_MMSS_GPLL0_CLK>,
2765 <&mdss_dsi0_ <<
2766 <&mdss_dsi0_ <<
2767 <&mdss_dsi1_ <<
2768 <&mdss_dsi1_ <<
2769 <0>, 2463 <0>,
2770 <0>, 2464 <0>,
2771 <0>, 2465 <0>,
2772 <&gcc GCC_MM !! 2466 <0>,
2773 }; !! 2467 <0>,
2774 !! 2468 <0>,
2775 mdss: display-subsystem@c9000 !! 2469 <0>,
2776 compatible = "qcom,ms !! 2470 <0>;
2777 reg = <0x0c900000 0x1 <<
2778 reg-names = "mdss"; <<
2779 <<
2780 interrupts = <GIC_SPI <<
2781 interrupt-controller; <<
2782 #interrupt-cells = <1 <<
2783 <<
2784 clocks = <&mmcc MDSS_ <<
2785 <&mmcc MDSS_ <<
2786 <&mmcc MDSS_ <<
2787 clock-names = "iface" <<
2788 "bus", <<
2789 "core"; <<
2790 <<
2791 power-domains = <&mmc <<
2792 iommus = <&mmss_smmu <<
2793 <<
2794 #address-cells = <1>; <<
2795 #size-cells = <1>; <<
2796 ranges; <<
2797 <<
2798 status = "disabled"; <<
2799 <<
2800 mdss_mdp: display-con <<
2801 compatible = <<
2802 reg = <0x0c90 <<
2803 <0x0c9a <<
2804 <0x0c9b <<
2805 <0x0c9b <<
2806 reg-names = " <<
2807 " <<
2808 " <<
2809 " <<
2810 <<
2811 interrupt-par <<
2812 interrupts = <<
2813 <<
2814 clocks = <&mm <<
2815 <&mm <<
2816 <&mm <<
2817 <&mm <<
2818 <&mm <<
2819 clock-names = <<
2820 <<
2821 <<
2822 <<
2823 <<
2824 <<
2825 assigned-cloc <<
2826 assigned-cloc <<
2827 <<
2828 operating-poi <<
2829 power-domains <<
2830 <<
2831 mdp_opp_table <<
2832 compa <<
2833 <<
2834 opp-1 <<
2835 <<
2836 <<
2837 }; <<
2838 <<
2839 opp-2 <<
2840 <<
2841 <<
2842 }; <<
2843 <<
2844 opp-3 <<
2845 <<
2846 <<
2847 }; <<
2848 <<
2849 opp-4 <<
2850 <<
2851 <<
2852 }; <<
2853 }; <<
2854 <<
2855 ports { <<
2856 #addr <<
2857 #size <<
2858 <<
2859 port@ <<
2860 <<
2861 <<
2862 <<
2863 <<
2864 <<
2865 }; <<
2866 <<
2867 port@ <<
2868 <<
2869 <<
2870 <<
2871 <<
2872 <<
2873 }; <<
2874 }; <<
2875 }; <<
2876 <<
2877 mdss_dsi0: dsi@c99400 <<
2878 compatible = <<
2879 reg = <0x0c99 <<
2880 reg-names = " <<
2881 <<
2882 interrupt-par <<
2883 interrupts = <<
2884 <<
2885 clocks = <&mm <<
2886 <&mm <<
2887 <&mm <<
2888 <&mm <<
2889 <&mm <<
2890 <&mm <<
2891 clock-names = <<
2892 <<
2893 <<
2894 <<
2895 <<
2896 <<
2897 assigned-cloc <<
2898 <<
2899 assigned-cloc <<
2900 <<
2901 <<
2902 operating-poi <<
2903 power-domains <<
2904 <<
2905 phys = <&mdss <<
2906 phy-names = " <<
2907 <<
2908 #address-cell <<
2909 #size-cells = <<
2910 <<
2911 status = "dis <<
2912 <<
2913 ports { <<
2914 #addr <<
2915 #size <<
2916 <<
2917 port@ <<
2918 <<
2919 <<
2920 <<
2921 <<
2922 <<
2923 }; <<
2924 <<
2925 port@ <<
2926 <<
2927 <<
2928 <<
2929 <<
2930 }; <<
2931 }; <<
2932 }; <<
2933 <<
2934 mdss_dsi0_phy: phy@c9 <<
2935 compatible = <<
2936 reg = <0x0c99 <<
2937 <0x0c99 <<
2938 <0x0c99 <<
2939 reg-names = " <<
2940 " <<
2941 " <<
2942 <<
2943 clocks = <&mm <<
2944 <&rp <<
2945 clock-names = <<
2946 <<
2947 #clock-cells <<
2948 #phy-cells = <<
2949 <<
2950 status = "dis <<
2951 }; <<
2952 <<
2953 mdss_dsi1: dsi@c99600 <<
2954 compatible = <<
2955 reg = <0x0c99 <<
2956 reg-names = " <<
2957 <<
2958 interrupt-par <<
2959 interrupts = <<
2960 <<
2961 clocks = <&mm <<
2962 <&mm <<
2963 <&mm <<
2964 <&mm <<
2965 <&mm <<
2966 <&mm <<
2967 clock-names = <<
2968 <<
2969 <<
2970 <<
2971 <<
2972 <<
2973 assigned-cloc <<
2974 <<
2975 assigned-cloc <<
2976 <<
2977 <<
2978 operating-poi <<
2979 power-domains <<
2980 <<
2981 phys = <&mdss <<
2982 phy-names = " <<
2983 <<
2984 #address-cell <<
2985 #size-cells = <<
2986 <<
2987 status = "dis <<
2988 <<
2989 ports { <<
2990 #addr <<
2991 #size <<
2992 <<
2993 port@ <<
2994 <<
2995 <<
2996 <<
2997 <<
2998 <<
2999 }; <<
3000 <<
3001 port@ <<
3002 <<
3003 <<
3004 <<
3005 <<
3006 }; <<
3007 }; <<
3008 }; <<
3009 <<
3010 mdss_dsi1_phy: phy@c9 <<
3011 compatible = <<
3012 reg = <0x0c99 <<
3013 <0x0c99 <<
3014 <0x0c99 <<
3015 reg-names = " <<
3016 " <<
3017 " <<
3018 <<
3019 clocks = <&mm <<
3020 <&rp <<
3021 clock-names = <<
3022 <<
3023 <<
3024 #clock-cells <<
3025 #phy-cells = <<
3026 <<
3027 status = "dis <<
3028 }; <<
3029 }; <<
3030 <<
3031 venus: video-codec@cc00000 { <<
3032 compatible = "qcom,ms <<
3033 reg = <0x0cc00000 0xf <<
3034 interrupts = <GIC_SPI <<
3035 power-domains = <&mmc <<
3036 clocks = <&mmcc VIDEO <<
3037 <&mmcc VIDEO <<
3038 <&mmcc VIDEO <<
3039 <&mmcc VIDEO <<
3040 clock-names = "core", <<
3041 iommus = <&mmss_smmu <<
3042 <&mmss_smmu <<
3043 <&mmss_smmu <<
3044 <&mmss_smmu <<
3045 <&mmss_smmu <<
3046 <&mmss_smmu <<
3047 <&mmss_smmu <<
3048 <&mmss_smmu <<
3049 <&mmss_smmu <<
3050 <&mmss_smmu <<
3051 <&mmss_smmu <<
3052 <&mmss_smmu <<
3053 <&mmss_smmu <<
3054 <&mmss_smmu <<
3055 <&mmss_smmu <<
3056 <&mmss_smmu <<
3057 <&mmss_smmu <<
3058 <&mmss_smmu <<
3059 <&mmss_smmu <<
3060 <&mmss_smmu <<
3061 memory-region = <&ven <<
3062 status = "disabled"; <<
3063 <<
3064 video-decoder { <<
3065 compatible = <<
3066 clocks = <&mm <<
3067 clock-names = <<
3068 power-domains <<
3069 }; <<
3070 <<
3071 video-encoder { <<
3072 compatible = <<
3073 clocks = <&mm <<
3074 clock-names = <<
3075 power-domains <<
3076 }; <<
3077 }; 2471 };
3078 2472
3079 mmss_smmu: iommu@cd00000 { 2473 mmss_smmu: iommu@cd00000 {
3080 compatible = "qcom,ms 2474 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
3081 reg = <0x0cd00000 0x4 2475 reg = <0x0cd00000 0x40000>;
3082 #iommu-cells = <1>; 2476 #iommu-cells = <1>;
3083 2477
3084 clocks = <&mmcc MNOC_ 2478 clocks = <&mmcc MNOC_AHB_CLK>,
3085 <&mmcc BIMC_ 2479 <&mmcc BIMC_SMMU_AHB_CLK>,
>> 2480 <&rpmcc RPM_SMD_MMAXI_CLK>,
3086 <&mmcc BIMC_ 2481 <&mmcc BIMC_SMMU_AXI_CLK>;
3087 clock-names = "iface- !! 2482 clock-names = "iface-mm", "iface-smmu",
3088 "iface- !! 2483 "bus-mm", "bus-smmu";
3089 "bus-sm !! 2484 status = "disabled";
3090 2485
3091 #global-interrupts = 2486 #global-interrupts = <0>;
3092 interrupts = 2487 interrupts =
3093 <GIC_SPI 263 2488 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
3094 <GIC_SPI 266 2489 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
3095 <GIC_SPI 267 2490 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
3096 <GIC_SPI 268 2491 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
3097 <GIC_SPI 244 2492 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
3098 <GIC_SPI 245 2493 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
3099 <GIC_SPI 247 2494 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
3100 <GIC_SPI 248 2495 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
3101 <GIC_SPI 249 2496 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
3102 <GIC_SPI 250 2497 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
3103 <GIC_SPI 251 2498 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
3104 <GIC_SPI 252 2499 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
3105 <GIC_SPI 253 2500 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
3106 <GIC_SPI 254 2501 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
3107 <GIC_SPI 255 2502 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
3108 <GIC_SPI 256 2503 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
3109 <GIC_SPI 260 2504 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
3110 <GIC_SPI 261 2505 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
3111 <GIC_SPI 262 2506 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
3112 <GIC_SPI 272 2507 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
3113 <<
3114 power-domains = <&mmc <<
3115 }; 2508 };
3116 2509
3117 remoteproc_adsp: remoteproc@1 2510 remoteproc_adsp: remoteproc@17300000 {
3118 compatible = "qcom,ms 2511 compatible = "qcom,msm8998-adsp-pas";
3119 reg = <0x17300000 0x4 2512 reg = <0x17300000 0x4040>;
3120 2513
3121 interrupts-extended = 2514 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
3122 2515 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3123 2516 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3124 2517 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3125 2518 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
3126 interrupt-names = "wd 2519 interrupt-names = "wdog", "fatal", "ready",
3127 "ha 2520 "handover", "stop-ack";
3128 2521
3129 clocks = <&rpmcc RPM_ 2522 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
3130 clock-names = "xo"; 2523 clock-names = "xo";
3131 2524
3132 memory-region = <&ads 2525 memory-region = <&adsp_mem>;
3133 2526
3134 qcom,smem-states = <& 2527 qcom,smem-states = <&adsp_smp2p_out 0>;
3135 qcom,smem-state-names 2528 qcom,smem-state-names = "stop";
3136 2529
3137 power-domains = <&rpm 2530 power-domains = <&rpmpd MSM8998_VDDCX>;
3138 power-domain-names = 2531 power-domain-names = "cx";
3139 2532
3140 status = "disabled"; 2533 status = "disabled";
3141 2534
3142 glink-edge { 2535 glink-edge {
3143 interrupts = 2536 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
3144 label = "lpas 2537 label = "lpass";
3145 qcom,remote-p 2538 qcom,remote-pid = <2>;
3146 mboxes = <&ap 2539 mboxes = <&apcs_glb 9>;
3147 }; 2540 };
3148 }; 2541 };
3149 2542
3150 apcs_glb: mailbox@17911000 { 2543 apcs_glb: mailbox@17911000 {
3151 compatible = "qcom,ms !! 2544 compatible = "qcom,msm8998-apcs-hmss-global";
3152 "qcom,ms <<
3153 reg = <0x17911000 0x1 2545 reg = <0x17911000 0x1000>;
3154 2546
3155 #mbox-cells = <1>; 2547 #mbox-cells = <1>;
3156 }; 2548 };
3157 2549
3158 timer@17920000 { 2550 timer@17920000 {
3159 #address-cells = <1>; 2551 #address-cells = <1>;
3160 #size-cells = <1>; 2552 #size-cells = <1>;
3161 ranges; 2553 ranges;
3162 compatible = "arm,arm 2554 compatible = "arm,armv7-timer-mem";
3163 reg = <0x17920000 0x1 2555 reg = <0x17920000 0x1000>;
3164 2556
3165 frame@17921000 { 2557 frame@17921000 {
3166 frame-number 2558 frame-number = <0>;
3167 interrupts = 2559 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
3168 2560 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
3169 reg = <0x1792 2561 reg = <0x17921000 0x1000>,
3170 <0x1792 2562 <0x17922000 0x1000>;
3171 }; 2563 };
3172 2564
3173 frame@17923000 { 2565 frame@17923000 {
3174 frame-number 2566 frame-number = <1>;
3175 interrupts = 2567 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
3176 reg = <0x1792 2568 reg = <0x17923000 0x1000>;
3177 status = "dis 2569 status = "disabled";
3178 }; 2570 };
3179 2571
3180 frame@17924000 { 2572 frame@17924000 {
3181 frame-number 2573 frame-number = <2>;
3182 interrupts = 2574 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
3183 reg = <0x1792 2575 reg = <0x17924000 0x1000>;
3184 status = "dis 2576 status = "disabled";
3185 }; 2577 };
3186 2578
3187 frame@17925000 { 2579 frame@17925000 {
3188 frame-number 2580 frame-number = <3>;
3189 interrupts = 2581 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3190 reg = <0x1792 2582 reg = <0x17925000 0x1000>;
3191 status = "dis 2583 status = "disabled";
3192 }; 2584 };
3193 2585
3194 frame@17926000 { 2586 frame@17926000 {
3195 frame-number 2587 frame-number = <4>;
3196 interrupts = 2588 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3197 reg = <0x1792 2589 reg = <0x17926000 0x1000>;
3198 status = "dis 2590 status = "disabled";
3199 }; 2591 };
3200 2592
3201 frame@17927000 { 2593 frame@17927000 {
3202 frame-number 2594 frame-number = <5>;
3203 interrupts = 2595 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3204 reg = <0x1792 2596 reg = <0x17927000 0x1000>;
3205 status = "dis 2597 status = "disabled";
3206 }; 2598 };
3207 2599
3208 frame@17928000 { 2600 frame@17928000 {
3209 frame-number 2601 frame-number = <6>;
3210 interrupts = 2602 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
3211 reg = <0x1792 2603 reg = <0x17928000 0x1000>;
3212 status = "dis 2604 status = "disabled";
3213 }; 2605 };
3214 }; 2606 };
3215 2607
3216 intc: interrupt-controller@17 2608 intc: interrupt-controller@17a00000 {
3217 compatible = "arm,gic 2609 compatible = "arm,gic-v3";
3218 reg = <0x17a00000 0x1 2610 reg = <0x17a00000 0x10000>, /* GICD */
3219 <0x17b00000 0x1 2611 <0x17b00000 0x100000>; /* GICR * 8 */
3220 #interrupt-cells = <3 2612 #interrupt-cells = <3>;
3221 #address-cells = <1>; 2613 #address-cells = <1>;
3222 #size-cells = <1>; 2614 #size-cells = <1>;
3223 ranges; 2615 ranges;
3224 interrupt-controller; 2616 interrupt-controller;
3225 #redistributor-region 2617 #redistributor-regions = <1>;
3226 redistributor-stride 2618 redistributor-stride = <0x0 0x20000>;
3227 interrupts = <GIC_PPI 2619 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3228 }; 2620 };
3229 2621
3230 wifi: wifi@18800000 { 2622 wifi: wifi@18800000 {
3231 compatible = "qcom,wc 2623 compatible = "qcom,wcn3990-wifi";
3232 status = "disabled"; 2624 status = "disabled";
3233 reg = <0x18800000 0x8 2625 reg = <0x18800000 0x800000>;
3234 reg-names = "membase" 2626 reg-names = "membase";
3235 memory-region = <&wla 2627 memory-region = <&wlan_msa_mem>;
3236 clocks = <&rpmcc RPM_ 2628 clocks = <&rpmcc RPM_SMD_RF_CLK2_PIN>;
3237 clock-names = "cxo_re 2629 clock-names = "cxo_ref_clk_pin";
3238 interrupts = 2630 interrupts =
3239 <GIC_SPI 413 2631 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
3240 <GIC_SPI 414 2632 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
3241 <GIC_SPI 415 2633 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
3242 <GIC_SPI 416 2634 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
3243 <GIC_SPI 417 2635 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
3244 <GIC_SPI 418 2636 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
3245 <GIC_SPI 420 2637 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
3246 <GIC_SPI 421 2638 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
3247 <GIC_SPI 422 2639 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
3248 <GIC_SPI 423 2640 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
3249 <GIC_SPI 424 2641 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
3250 <GIC_SPI 425 2642 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
3251 iommus = <&anoc2_smmu 2643 iommus = <&anoc2_smmu 0x1900>,
3252 <&anoc2_smmu 2644 <&anoc2_smmu 0x1901>;
3253 qcom,snoc-host-cap-8b 2645 qcom,snoc-host-cap-8bit-quirk;
3254 qcom,no-msa-ready-ind <<
3255 }; 2646 };
3256 }; 2647 };
3257 }; 2648 };
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