1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2016, The Linux Foundation. A 2 /* Copyright (c) 2016, The Linux Foundation. All rights reserved. */
3 3
4 #include <dt-bindings/interrupt-controller/arm 4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-msm8998.h 5 #include <dt-bindings/clock/qcom,gcc-msm8998.h>
6 #include <dt-bindings/clock/qcom,gpucc-msm8998 6 #include <dt-bindings/clock/qcom,gpucc-msm8998.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8998. 7 #include <dt-bindings/clock/qcom,mmcc-msm8998.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h> 8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/firmware/qcom,scm.h> <<
10 #include <dt-bindings/power/qcom-rpmpd.h> 9 #include <dt-bindings/power/qcom-rpmpd.h>
11 #include <dt-bindings/gpio/gpio.h> 10 #include <dt-bindings/gpio/gpio.h>
12 11
13 / { 12 / {
14 interrupt-parent = <&intc>; 13 interrupt-parent = <&intc>;
15 14
16 qcom,msm-id = <292 0x0>; 15 qcom,msm-id = <292 0x0>;
17 16
18 #address-cells = <2>; 17 #address-cells = <2>;
19 #size-cells = <2>; 18 #size-cells = <2>;
20 19
21 chosen { }; 20 chosen { };
22 21
23 memory@80000000 { 22 memory@80000000 {
24 device_type = "memory"; 23 device_type = "memory";
25 /* We expect the bootloader to 24 /* We expect the bootloader to fill in the reg */
26 reg = <0x0 0x80000000 0x0 0x0> 25 reg = <0x0 0x80000000 0x0 0x0>;
27 }; 26 };
28 27
29 reserved-memory { 28 reserved-memory {
30 #address-cells = <2>; 29 #address-cells = <2>;
31 #size-cells = <2>; 30 #size-cells = <2>;
32 ranges; 31 ranges;
33 32
34 hyp_mem: memory@85800000 { 33 hyp_mem: memory@85800000 {
35 reg = <0x0 0x85800000 34 reg = <0x0 0x85800000 0x0 0x600000>;
36 no-map; 35 no-map;
37 }; 36 };
38 37
39 xbl_mem: memory@85e00000 { 38 xbl_mem: memory@85e00000 {
40 reg = <0x0 0x85e00000 39 reg = <0x0 0x85e00000 0x0 0x100000>;
41 no-map; 40 no-map;
42 }; 41 };
43 42
44 smem_mem: smem-mem@86000000 { 43 smem_mem: smem-mem@86000000 {
45 reg = <0x0 0x86000000 44 reg = <0x0 0x86000000 0x0 0x200000>;
46 no-map; 45 no-map;
47 }; 46 };
48 47
49 tz_mem: memory@86200000 { 48 tz_mem: memory@86200000 {
50 reg = <0x0 0x86200000 49 reg = <0x0 0x86200000 0x0 0x2d00000>;
51 no-map; 50 no-map;
52 }; 51 };
53 52
54 rmtfs_mem: memory@88f00000 { 53 rmtfs_mem: memory@88f00000 {
55 compatible = "qcom,rmt 54 compatible = "qcom,rmtfs-mem";
56 reg = <0x0 0x88f00000 55 reg = <0x0 0x88f00000 0x0 0x200000>;
57 no-map; 56 no-map;
58 57
59 qcom,client-id = <1>; 58 qcom,client-id = <1>;
60 qcom,vmid = <QCOM_SCM_ !! 59 qcom,vmid = <15>;
61 }; 60 };
62 61
63 spss_mem: memory@8ab00000 { 62 spss_mem: memory@8ab00000 {
64 reg = <0x0 0x8ab00000 63 reg = <0x0 0x8ab00000 0x0 0x700000>;
65 no-map; 64 no-map;
66 }; 65 };
67 66
68 adsp_mem: memory@8b200000 { 67 adsp_mem: memory@8b200000 {
69 reg = <0x0 0x8b200000 68 reg = <0x0 0x8b200000 0x0 0x1a00000>;
70 no-map; 69 no-map;
71 }; 70 };
72 71
73 mpss_mem: memory@8cc00000 { 72 mpss_mem: memory@8cc00000 {
74 reg = <0x0 0x8cc00000 73 reg = <0x0 0x8cc00000 0x0 0x7000000>;
75 no-map; 74 no-map;
76 }; 75 };
77 76
78 venus_mem: memory@93c00000 { 77 venus_mem: memory@93c00000 {
79 reg = <0x0 0x93c00000 78 reg = <0x0 0x93c00000 0x0 0x500000>;
80 no-map; 79 no-map;
81 }; 80 };
82 81
83 mba_mem: memory@94100000 { 82 mba_mem: memory@94100000 {
84 reg = <0x0 0x94100000 83 reg = <0x0 0x94100000 0x0 0x200000>;
85 no-map; 84 no-map;
86 }; 85 };
87 86
88 slpi_mem: memory@94300000 { 87 slpi_mem: memory@94300000 {
89 reg = <0x0 0x94300000 88 reg = <0x0 0x94300000 0x0 0xf00000>;
90 no-map; 89 no-map;
91 }; 90 };
92 91
93 ipa_fw_mem: memory@95200000 { 92 ipa_fw_mem: memory@95200000 {
94 reg = <0x0 0x95200000 93 reg = <0x0 0x95200000 0x0 0x10000>;
95 no-map; 94 no-map;
96 }; 95 };
97 96
98 ipa_gsi_mem: memory@95210000 { 97 ipa_gsi_mem: memory@95210000 {
99 reg = <0x0 0x95210000 98 reg = <0x0 0x95210000 0x0 0x5000>;
100 no-map; 99 no-map;
101 }; 100 };
102 101
103 gpu_mem: memory@95600000 { 102 gpu_mem: memory@95600000 {
104 reg = <0x0 0x95600000 103 reg = <0x0 0x95600000 0x0 0x100000>;
105 no-map; 104 no-map;
106 }; 105 };
107 106
108 wlan_msa_mem: memory@95700000 107 wlan_msa_mem: memory@95700000 {
109 reg = <0x0 0x95700000 108 reg = <0x0 0x95700000 0x0 0x100000>;
110 no-map; 109 no-map;
111 }; 110 };
112 <<
113 mdata_mem: mpss-metadata { <<
114 alloc-ranges = <0x0 0x <<
115 size = <0x0 0x4000>; <<
116 no-map; <<
117 }; <<
118 }; 111 };
119 112
120 clocks { 113 clocks {
121 xo: xo-board { 114 xo: xo-board {
122 compatible = "fixed-cl 115 compatible = "fixed-clock";
123 #clock-cells = <0>; 116 #clock-cells = <0>;
124 clock-frequency = <192 117 clock-frequency = <19200000>;
125 clock-output-names = " 118 clock-output-names = "xo_board";
126 }; 119 };
127 120
128 sleep_clk: sleep-clk { 121 sleep_clk: sleep-clk {
129 compatible = "fixed-cl 122 compatible = "fixed-clock";
130 #clock-cells = <0>; 123 #clock-cells = <0>;
131 clock-frequency = <327 124 clock-frequency = <32764>;
132 }; 125 };
133 }; 126 };
134 127
135 cpus { 128 cpus {
136 #address-cells = <2>; 129 #address-cells = <2>;
137 #size-cells = <0>; 130 #size-cells = <0>;
138 131
139 CPU0: cpu@0 { 132 CPU0: cpu@0 {
140 device_type = "cpu"; 133 device_type = "cpu";
141 compatible = "qcom,kry 134 compatible = "qcom,kryo280";
142 reg = <0x0 0x0>; 135 reg = <0x0 0x0>;
143 enable-method = "psci" 136 enable-method = "psci";
144 capacity-dmips-mhz = < 137 capacity-dmips-mhz = <1024>;
145 cpu-idle-states = <&LI 138 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
146 next-level-cache = <&L 139 next-level-cache = <&L2_0>;
147 L2_0: l2-cache { 140 L2_0: l2-cache {
148 compatible = " 141 compatible = "cache";
149 cache-level = 142 cache-level = <2>;
150 cache-unified; <<
151 }; 143 };
152 }; 144 };
153 145
154 CPU1: cpu@1 { 146 CPU1: cpu@1 {
155 device_type = "cpu"; 147 device_type = "cpu";
156 compatible = "qcom,kry 148 compatible = "qcom,kryo280";
157 reg = <0x0 0x1>; 149 reg = <0x0 0x1>;
158 enable-method = "psci" 150 enable-method = "psci";
159 capacity-dmips-mhz = < 151 capacity-dmips-mhz = <1024>;
160 cpu-idle-states = <&LI 152 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
161 next-level-cache = <&L 153 next-level-cache = <&L2_0>;
162 }; 154 };
163 155
164 CPU2: cpu@2 { 156 CPU2: cpu@2 {
165 device_type = "cpu"; 157 device_type = "cpu";
166 compatible = "qcom,kry 158 compatible = "qcom,kryo280";
167 reg = <0x0 0x2>; 159 reg = <0x0 0x2>;
168 enable-method = "psci" 160 enable-method = "psci";
169 capacity-dmips-mhz = < 161 capacity-dmips-mhz = <1024>;
170 cpu-idle-states = <&LI 162 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
171 next-level-cache = <&L 163 next-level-cache = <&L2_0>;
172 }; 164 };
173 165
174 CPU3: cpu@3 { 166 CPU3: cpu@3 {
175 device_type = "cpu"; 167 device_type = "cpu";
176 compatible = "qcom,kry 168 compatible = "qcom,kryo280";
177 reg = <0x0 0x3>; 169 reg = <0x0 0x3>;
178 enable-method = "psci" 170 enable-method = "psci";
179 capacity-dmips-mhz = < 171 capacity-dmips-mhz = <1024>;
180 cpu-idle-states = <&LI 172 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
181 next-level-cache = <&L 173 next-level-cache = <&L2_0>;
182 }; 174 };
183 175
184 CPU4: cpu@100 { 176 CPU4: cpu@100 {
185 device_type = "cpu"; 177 device_type = "cpu";
186 compatible = "qcom,kry 178 compatible = "qcom,kryo280";
187 reg = <0x0 0x100>; 179 reg = <0x0 0x100>;
188 enable-method = "psci" 180 enable-method = "psci";
189 capacity-dmips-mhz = < 181 capacity-dmips-mhz = <1536>;
190 cpu-idle-states = <&BI 182 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
191 next-level-cache = <&L 183 next-level-cache = <&L2_1>;
192 L2_1: l2-cache { 184 L2_1: l2-cache {
193 compatible = " 185 compatible = "cache";
194 cache-level = 186 cache-level = <2>;
195 cache-unified; <<
196 }; 187 };
197 }; 188 };
198 189
199 CPU5: cpu@101 { 190 CPU5: cpu@101 {
200 device_type = "cpu"; 191 device_type = "cpu";
201 compatible = "qcom,kry 192 compatible = "qcom,kryo280";
202 reg = <0x0 0x101>; 193 reg = <0x0 0x101>;
203 enable-method = "psci" 194 enable-method = "psci";
204 capacity-dmips-mhz = < 195 capacity-dmips-mhz = <1536>;
205 cpu-idle-states = <&BI 196 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
206 next-level-cache = <&L 197 next-level-cache = <&L2_1>;
207 }; 198 };
208 199
209 CPU6: cpu@102 { 200 CPU6: cpu@102 {
210 device_type = "cpu"; 201 device_type = "cpu";
211 compatible = "qcom,kry 202 compatible = "qcom,kryo280";
212 reg = <0x0 0x102>; 203 reg = <0x0 0x102>;
213 enable-method = "psci" 204 enable-method = "psci";
214 capacity-dmips-mhz = < 205 capacity-dmips-mhz = <1536>;
215 cpu-idle-states = <&BI 206 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
216 next-level-cache = <&L 207 next-level-cache = <&L2_1>;
217 }; 208 };
218 209
219 CPU7: cpu@103 { 210 CPU7: cpu@103 {
220 device_type = "cpu"; 211 device_type = "cpu";
221 compatible = "qcom,kry 212 compatible = "qcom,kryo280";
222 reg = <0x0 0x103>; 213 reg = <0x0 0x103>;
223 enable-method = "psci" 214 enable-method = "psci";
224 capacity-dmips-mhz = < 215 capacity-dmips-mhz = <1536>;
225 cpu-idle-states = <&BI 216 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
226 next-level-cache = <&L 217 next-level-cache = <&L2_1>;
227 }; 218 };
228 219
229 cpu-map { 220 cpu-map {
230 cluster0 { 221 cluster0 {
231 core0 { 222 core0 {
232 cpu = 223 cpu = <&CPU0>;
233 }; 224 };
234 225
235 core1 { 226 core1 {
236 cpu = 227 cpu = <&CPU1>;
237 }; 228 };
238 229
239 core2 { 230 core2 {
240 cpu = 231 cpu = <&CPU2>;
241 }; 232 };
242 233
243 core3 { 234 core3 {
244 cpu = 235 cpu = <&CPU3>;
245 }; 236 };
246 }; 237 };
247 238
248 cluster1 { 239 cluster1 {
249 core0 { 240 core0 {
250 cpu = 241 cpu = <&CPU4>;
251 }; 242 };
252 243
253 core1 { 244 core1 {
254 cpu = 245 cpu = <&CPU5>;
255 }; 246 };
256 247
257 core2 { 248 core2 {
258 cpu = 249 cpu = <&CPU6>;
259 }; 250 };
260 251
261 core3 { 252 core3 {
262 cpu = 253 cpu = <&CPU7>;
263 }; 254 };
264 }; 255 };
265 }; 256 };
266 257
267 idle-states { 258 idle-states {
268 entry-method = "psci"; 259 entry-method = "psci";
269 260
270 LITTLE_CPU_SLEEP_0: cp 261 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
271 compatible = " 262 compatible = "arm,idle-state";
272 idle-state-nam 263 idle-state-name = "little-retention";
273 /* CPU Retenti 264 /* CPU Retention (C2D), L2 Active */
274 arm,psci-suspe 265 arm,psci-suspend-param = <0x00000002>;
275 entry-latency- 266 entry-latency-us = <81>;
276 exit-latency-u 267 exit-latency-us = <86>;
277 min-residency- 268 min-residency-us = <504>;
278 }; 269 };
279 270
280 LITTLE_CPU_SLEEP_1: cp 271 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
281 compatible = " 272 compatible = "arm,idle-state";
282 idle-state-nam 273 idle-state-name = "little-power-collapse";
283 /* CPU + L2 Po 274 /* CPU + L2 Power Collapse (C3, D4) */
284 arm,psci-suspe 275 arm,psci-suspend-param = <0x40000003>;
285 entry-latency- 276 entry-latency-us = <814>;
286 exit-latency-u 277 exit-latency-us = <4562>;
287 min-residency- 278 min-residency-us = <9183>;
288 local-timer-st 279 local-timer-stop;
289 }; 280 };
290 281
291 BIG_CPU_SLEEP_0: cpu-s 282 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
292 compatible = " 283 compatible = "arm,idle-state";
293 idle-state-nam 284 idle-state-name = "big-retention";
294 /* CPU Retenti 285 /* CPU Retention (C2D), L2 Active */
295 arm,psci-suspe 286 arm,psci-suspend-param = <0x00000002>;
296 entry-latency- 287 entry-latency-us = <79>;
297 exit-latency-u 288 exit-latency-us = <82>;
298 min-residency- 289 min-residency-us = <1302>;
299 }; 290 };
300 291
301 BIG_CPU_SLEEP_1: cpu-s 292 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
302 compatible = " 293 compatible = "arm,idle-state";
303 idle-state-nam 294 idle-state-name = "big-power-collapse";
304 /* CPU + L2 Po 295 /* CPU + L2 Power Collapse (C3, D4) */
305 arm,psci-suspe 296 arm,psci-suspend-param = <0x40000003>;
306 entry-latency- 297 entry-latency-us = <724>;
307 exit-latency-u 298 exit-latency-us = <2027>;
308 min-residency- 299 min-residency-us = <9419>;
309 local-timer-st 300 local-timer-stop;
310 }; 301 };
311 }; 302 };
312 }; 303 };
313 304
314 firmware { 305 firmware {
315 scm { 306 scm {
316 compatible = "qcom,scm 307 compatible = "qcom,scm-msm8998", "qcom,scm";
317 }; 308 };
318 }; 309 };
319 310
320 dsi_opp_table: opp-table-dsi { !! 311 tcsr_mutex: hwlock {
321 compatible = "operating-points !! 312 compatible = "qcom,tcsr-mutex";
322 !! 313 syscon = <&tcsr_mutex_regs 0 0x1000>;
323 opp-131250000 { !! 314 #hwlock-cells = <1>;
324 opp-hz = /bits/ 64 <13 <<
325 required-opps = <&rpmp <<
326 }; <<
327 <<
328 opp-210000000 { <<
329 opp-hz = /bits/ 64 <21 <<
330 required-opps = <&rpmp <<
331 }; <<
332 <<
333 opp-312500000 { <<
334 opp-hz = /bits/ 64 <31 <<
335 required-opps = <&rpmp <<
336 }; <<
337 }; 315 };
338 316
339 psci { 317 psci {
340 compatible = "arm,psci-1.0"; 318 compatible = "arm,psci-1.0";
341 method = "smc"; 319 method = "smc";
342 }; 320 };
343 321
344 rpm: remoteproc { !! 322 rpm-glink {
345 compatible = "qcom,msm8998-rpm !! 323 compatible = "qcom,glink-rpm";
>> 324
>> 325 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
>> 326 qcom,rpm-msg-ram = <&rpm_msg_ram>;
>> 327 mboxes = <&apcs_glb 0>;
>> 328
>> 329 rpm_requests: rpm-requests {
>> 330 compatible = "qcom,rpm-msm8998";
>> 331 qcom,glink-channels = "rpm_requests";
>> 332
>> 333 rpmcc: clock-controller {
>> 334 compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc";
>> 335 #clock-cells = <1>;
>> 336 };
>> 337
>> 338 rpmpd: power-controller {
>> 339 compatible = "qcom,msm8998-rpmpd";
>> 340 #power-domain-cells = <1>;
>> 341 operating-points-v2 = <&rpmpd_opp_table>;
>> 342
>> 343 rpmpd_opp_table: opp-table {
>> 344 compatible = "operating-points-v2";
>> 345
>> 346 rpmpd_opp_ret: opp1 {
>> 347 opp-level = <RPM_SMD_LEVEL_RETENTION>;
>> 348 };
>> 349
>> 350 rpmpd_opp_ret_plus: opp2 {
>> 351 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
>> 352 };
>> 353
>> 354 rpmpd_opp_min_svs: opp3 {
>> 355 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
>> 356 };
>> 357
>> 358 rpmpd_opp_low_svs: opp4 {
>> 359 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
>> 360 };
>> 361
>> 362 rpmpd_opp_svs: opp5 {
>> 363 opp-level = <RPM_SMD_LEVEL_SVS>;
>> 364 };
>> 365
>> 366 rpmpd_opp_svs_plus: opp6 {
>> 367 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
>> 368 };
>> 369
>> 370 rpmpd_opp_nom: opp7 {
>> 371 opp-level = <RPM_SMD_LEVEL_NOM>;
>> 372 };
346 373
347 glink-edge { !! 374 rpmpd_opp_nom_plus: opp8 {
348 compatible = "qcom,gli !! 375 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
>> 376 };
349 377
350 interrupts = <GIC_SPI !! 378 rpmpd_opp_turbo: opp9 {
351 qcom,rpm-msg-ram = <&r !! 379 opp-level = <RPM_SMD_LEVEL_TURBO>;
352 mboxes = <&apcs_glb 0> !! 380 };
353 !! 381
354 rpm_requests: rpm-requ !! 382 rpmpd_opp_turbo_plus: opp10 {
355 compatible = " !! 383 opp-level = <RPM_SMD_LEVEL_BINNING>;
356 qcom,glink-cha <<
357 <<
358 rpmcc: clock-c <<
359 compat <<
360 clocks <<
361 clock- <<
362 #clock <<
363 }; <<
364 <<
365 rpmpd: power-c <<
366 compat <<
367 #power <<
368 operat <<
369 <<
370 rpmpd_ <<
371 <<
372 <<
373 <<
374 <<
375 <<
376 <<
377 <<
378 <<
379 <<
380 <<
381 <<
382 <<
383 <<
384 <<
385 <<
386 <<
387 <<
388 <<
389 <<
390 <<
391 <<
392 <<
393 <<
394 <<
395 <<
396 <<
397 <<
398 <<
399 <<
400 <<
401 <<
402 <<
403 <<
404 <<
405 <<
406 <<
407 <<
408 <<
409 <<
410 <<
411 <<
412 }; 384 };
413 }; 385 };
414 }; 386 };
415 }; 387 };
416 }; 388 };
417 389
418 smem { 390 smem {
419 compatible = "qcom,smem"; 391 compatible = "qcom,smem";
420 memory-region = <&smem_mem>; 392 memory-region = <&smem_mem>;
421 hwlocks = <&tcsr_mutex 3>; 393 hwlocks = <&tcsr_mutex 3>;
422 }; 394 };
423 395
424 smp2p-lpass { 396 smp2p-lpass {
425 compatible = "qcom,smp2p"; 397 compatible = "qcom,smp2p";
426 qcom,smem = <443>, <429>; 398 qcom,smem = <443>, <429>;
427 399
428 interrupts = <GIC_SPI 158 IRQ_ 400 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
429 401
430 mboxes = <&apcs_glb 10>; 402 mboxes = <&apcs_glb 10>;
431 403
432 qcom,local-pid = <0>; 404 qcom,local-pid = <0>;
433 qcom,remote-pid = <2>; 405 qcom,remote-pid = <2>;
434 406
435 adsp_smp2p_out: master-kernel 407 adsp_smp2p_out: master-kernel {
436 qcom,entry-name = "mas 408 qcom,entry-name = "master-kernel";
437 #qcom,smem-state-cells 409 #qcom,smem-state-cells = <1>;
438 }; 410 };
439 411
440 adsp_smp2p_in: slave-kernel { 412 adsp_smp2p_in: slave-kernel {
441 qcom,entry-name = "sla 413 qcom,entry-name = "slave-kernel";
442 414
443 interrupt-controller; 415 interrupt-controller;
444 #interrupt-cells = <2> 416 #interrupt-cells = <2>;
445 }; 417 };
446 }; 418 };
447 419
448 smp2p-mpss { 420 smp2p-mpss {
449 compatible = "qcom,smp2p"; 421 compatible = "qcom,smp2p";
450 qcom,smem = <435>, <428>; 422 qcom,smem = <435>, <428>;
451 interrupts = <GIC_SPI 451 IRQ_ 423 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
452 mboxes = <&apcs_glb 14>; 424 mboxes = <&apcs_glb 14>;
453 qcom,local-pid = <0>; 425 qcom,local-pid = <0>;
454 qcom,remote-pid = <1>; 426 qcom,remote-pid = <1>;
455 427
456 modem_smp2p_out: master-kernel 428 modem_smp2p_out: master-kernel {
457 qcom,entry-name = "mas 429 qcom,entry-name = "master-kernel";
458 #qcom,smem-state-cells 430 #qcom,smem-state-cells = <1>;
459 }; 431 };
460 432
461 modem_smp2p_in: slave-kernel { 433 modem_smp2p_in: slave-kernel {
462 qcom,entry-name = "sla 434 qcom,entry-name = "slave-kernel";
463 interrupt-controller; 435 interrupt-controller;
464 #interrupt-cells = <2> 436 #interrupt-cells = <2>;
465 }; 437 };
466 }; 438 };
467 439
468 smp2p-slpi { 440 smp2p-slpi {
469 compatible = "qcom,smp2p"; 441 compatible = "qcom,smp2p";
470 qcom,smem = <481>, <430>; 442 qcom,smem = <481>, <430>;
471 interrupts = <GIC_SPI 178 IRQ_ 443 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
472 mboxes = <&apcs_glb 26>; 444 mboxes = <&apcs_glb 26>;
473 qcom,local-pid = <0>; 445 qcom,local-pid = <0>;
474 qcom,remote-pid = <3>; 446 qcom,remote-pid = <3>;
475 447
476 slpi_smp2p_out: master-kernel 448 slpi_smp2p_out: master-kernel {
477 qcom,entry-name = "mas 449 qcom,entry-name = "master-kernel";
478 #qcom,smem-state-cells 450 #qcom,smem-state-cells = <1>;
479 }; 451 };
480 452
481 slpi_smp2p_in: slave-kernel { 453 slpi_smp2p_in: slave-kernel {
482 qcom,entry-name = "sla 454 qcom,entry-name = "slave-kernel";
483 interrupt-controller; 455 interrupt-controller;
484 #interrupt-cells = <2> 456 #interrupt-cells = <2>;
485 }; 457 };
486 }; 458 };
487 459
488 thermal-zones { 460 thermal-zones {
489 cpu0-thermal { 461 cpu0-thermal {
490 polling-delay-passive 462 polling-delay-passive = <250>;
>> 463 polling-delay = <1000>;
491 464
492 thermal-sensors = <&ts 465 thermal-sensors = <&tsens0 1>;
493 466
494 trips { 467 trips {
495 cpu0_alert0: t 468 cpu0_alert0: trip-point0 {
496 temper 469 temperature = <75000>;
497 hyster 470 hysteresis = <2000>;
498 type = 471 type = "passive";
499 }; 472 };
500 473
501 cpu0_crit: cpu !! 474 cpu0_crit: cpu_crit {
502 temper 475 temperature = <110000>;
503 hyster 476 hysteresis = <2000>;
504 type = 477 type = "critical";
505 }; 478 };
506 }; 479 };
507 }; 480 };
508 481
509 cpu1-thermal { 482 cpu1-thermal {
510 polling-delay-passive 483 polling-delay-passive = <250>;
>> 484 polling-delay = <1000>;
511 485
512 thermal-sensors = <&ts 486 thermal-sensors = <&tsens0 2>;
513 487
514 trips { 488 trips {
515 cpu1_alert0: t 489 cpu1_alert0: trip-point0 {
516 temper 490 temperature = <75000>;
517 hyster 491 hysteresis = <2000>;
518 type = 492 type = "passive";
519 }; 493 };
520 494
521 cpu1_crit: cpu !! 495 cpu1_crit: cpu_crit {
522 temper 496 temperature = <110000>;
523 hyster 497 hysteresis = <2000>;
524 type = 498 type = "critical";
525 }; 499 };
526 }; 500 };
527 }; 501 };
528 502
529 cpu2-thermal { 503 cpu2-thermal {
530 polling-delay-passive 504 polling-delay-passive = <250>;
>> 505 polling-delay = <1000>;
531 506
532 thermal-sensors = <&ts 507 thermal-sensors = <&tsens0 3>;
533 508
534 trips { 509 trips {
535 cpu2_alert0: t 510 cpu2_alert0: trip-point0 {
536 temper 511 temperature = <75000>;
537 hyster 512 hysteresis = <2000>;
538 type = 513 type = "passive";
539 }; 514 };
540 515
541 cpu2_crit: cpu !! 516 cpu2_crit: cpu_crit {
542 temper 517 temperature = <110000>;
543 hyster 518 hysteresis = <2000>;
544 type = 519 type = "critical";
545 }; 520 };
546 }; 521 };
547 }; 522 };
548 523
549 cpu3-thermal { 524 cpu3-thermal {
550 polling-delay-passive 525 polling-delay-passive = <250>;
>> 526 polling-delay = <1000>;
551 527
552 thermal-sensors = <&ts 528 thermal-sensors = <&tsens0 4>;
553 529
554 trips { 530 trips {
555 cpu3_alert0: t 531 cpu3_alert0: trip-point0 {
556 temper 532 temperature = <75000>;
557 hyster 533 hysteresis = <2000>;
558 type = 534 type = "passive";
559 }; 535 };
560 536
561 cpu3_crit: cpu !! 537 cpu3_crit: cpu_crit {
562 temper 538 temperature = <110000>;
563 hyster 539 hysteresis = <2000>;
564 type = 540 type = "critical";
565 }; 541 };
566 }; 542 };
567 }; 543 };
568 544
569 cpu4-thermal { 545 cpu4-thermal {
570 polling-delay-passive 546 polling-delay-passive = <250>;
>> 547 polling-delay = <1000>;
571 548
572 thermal-sensors = <&ts 549 thermal-sensors = <&tsens0 7>;
573 550
574 trips { 551 trips {
575 cpu4_alert0: t 552 cpu4_alert0: trip-point0 {
576 temper 553 temperature = <75000>;
577 hyster 554 hysteresis = <2000>;
578 type = 555 type = "passive";
579 }; 556 };
580 557
581 cpu4_crit: cpu !! 558 cpu4_crit: cpu_crit {
582 temper 559 temperature = <110000>;
583 hyster 560 hysteresis = <2000>;
584 type = 561 type = "critical";
585 }; 562 };
586 }; 563 };
587 }; 564 };
588 565
589 cpu5-thermal { 566 cpu5-thermal {
590 polling-delay-passive 567 polling-delay-passive = <250>;
>> 568 polling-delay = <1000>;
591 569
592 thermal-sensors = <&ts 570 thermal-sensors = <&tsens0 8>;
593 571
594 trips { 572 trips {
595 cpu5_alert0: t 573 cpu5_alert0: trip-point0 {
596 temper 574 temperature = <75000>;
597 hyster 575 hysteresis = <2000>;
598 type = 576 type = "passive";
599 }; 577 };
600 578
601 cpu5_crit: cpu !! 579 cpu5_crit: cpu_crit {
602 temper 580 temperature = <110000>;
603 hyster 581 hysteresis = <2000>;
604 type = 582 type = "critical";
605 }; 583 };
606 }; 584 };
607 }; 585 };
608 586
609 cpu6-thermal { 587 cpu6-thermal {
610 polling-delay-passive 588 polling-delay-passive = <250>;
>> 589 polling-delay = <1000>;
611 590
612 thermal-sensors = <&ts 591 thermal-sensors = <&tsens0 9>;
613 592
614 trips { 593 trips {
615 cpu6_alert0: t 594 cpu6_alert0: trip-point0 {
616 temper 595 temperature = <75000>;
617 hyster 596 hysteresis = <2000>;
618 type = 597 type = "passive";
619 }; 598 };
620 599
621 cpu6_crit: cpu !! 600 cpu6_crit: cpu_crit {
622 temper 601 temperature = <110000>;
623 hyster 602 hysteresis = <2000>;
624 type = 603 type = "critical";
625 }; 604 };
626 }; 605 };
627 }; 606 };
628 607
629 cpu7-thermal { 608 cpu7-thermal {
630 polling-delay-passive 609 polling-delay-passive = <250>;
>> 610 polling-delay = <1000>;
631 611
632 thermal-sensors = <&ts 612 thermal-sensors = <&tsens0 10>;
633 613
634 trips { 614 trips {
635 cpu7_alert0: t 615 cpu7_alert0: trip-point0 {
636 temper 616 temperature = <75000>;
637 hyster 617 hysteresis = <2000>;
638 type = 618 type = "passive";
639 }; 619 };
640 620
641 cpu7_crit: cpu !! 621 cpu7_crit: cpu_crit {
642 temper 622 temperature = <110000>;
643 hyster 623 hysteresis = <2000>;
644 type = 624 type = "critical";
645 }; 625 };
646 }; 626 };
647 }; 627 };
648 628
649 gpu-bottom-thermal { 629 gpu-bottom-thermal {
650 polling-delay-passive 630 polling-delay-passive = <250>;
>> 631 polling-delay = <1000>;
651 632
652 thermal-sensors = <&ts 633 thermal-sensors = <&tsens0 12>;
653 634
654 trips { 635 trips {
655 gpu1_alert0: t 636 gpu1_alert0: trip-point0 {
656 temper 637 temperature = <90000>;
657 hyster 638 hysteresis = <2000>;
658 type = 639 type = "hot";
659 }; 640 };
660 }; 641 };
661 }; 642 };
662 643
663 gpu-top-thermal { 644 gpu-top-thermal {
664 polling-delay-passive 645 polling-delay-passive = <250>;
>> 646 polling-delay = <1000>;
665 647
666 thermal-sensors = <&ts 648 thermal-sensors = <&tsens0 13>;
667 649
668 trips { 650 trips {
669 gpu2_alert0: t 651 gpu2_alert0: trip-point0 {
670 temper 652 temperature = <90000>;
671 hyster 653 hysteresis = <2000>;
672 type = 654 type = "hot";
673 }; 655 };
674 }; 656 };
675 }; 657 };
676 658
677 clust0-mhm-thermal { 659 clust0-mhm-thermal {
678 polling-delay-passive 660 polling-delay-passive = <250>;
>> 661 polling-delay = <1000>;
679 662
680 thermal-sensors = <&ts 663 thermal-sensors = <&tsens0 5>;
681 664
682 trips { 665 trips {
683 cluster0_mhm_a 666 cluster0_mhm_alert0: trip-point0 {
684 temper 667 temperature = <90000>;
685 hyster 668 hysteresis = <2000>;
686 type = 669 type = "hot";
687 }; 670 };
688 }; 671 };
689 }; 672 };
690 673
691 clust1-mhm-thermal { 674 clust1-mhm-thermal {
692 polling-delay-passive 675 polling-delay-passive = <250>;
>> 676 polling-delay = <1000>;
693 677
694 thermal-sensors = <&ts 678 thermal-sensors = <&tsens0 6>;
695 679
696 trips { 680 trips {
697 cluster1_mhm_a 681 cluster1_mhm_alert0: trip-point0 {
698 temper 682 temperature = <90000>;
699 hyster 683 hysteresis = <2000>;
700 type = 684 type = "hot";
701 }; 685 };
702 }; 686 };
703 }; 687 };
704 688
705 cluster1-l2-thermal { 689 cluster1-l2-thermal {
706 polling-delay-passive 690 polling-delay-passive = <250>;
>> 691 polling-delay = <1000>;
707 692
708 thermal-sensors = <&ts 693 thermal-sensors = <&tsens0 11>;
709 694
710 trips { 695 trips {
711 cluster1_l2_al 696 cluster1_l2_alert0: trip-point0 {
712 temper 697 temperature = <90000>;
713 hyster 698 hysteresis = <2000>;
714 type = 699 type = "hot";
715 }; 700 };
716 }; 701 };
717 }; 702 };
718 703
719 modem-thermal { 704 modem-thermal {
720 polling-delay-passive 705 polling-delay-passive = <250>;
>> 706 polling-delay = <1000>;
721 707
722 thermal-sensors = <&ts 708 thermal-sensors = <&tsens1 1>;
723 709
724 trips { 710 trips {
725 modem_alert0: 711 modem_alert0: trip-point0 {
726 temper 712 temperature = <90000>;
727 hyster 713 hysteresis = <2000>;
728 type = 714 type = "hot";
729 }; 715 };
730 }; 716 };
731 }; 717 };
732 718
733 mem-thermal { 719 mem-thermal {
734 polling-delay-passive 720 polling-delay-passive = <250>;
>> 721 polling-delay = <1000>;
735 722
736 thermal-sensors = <&ts 723 thermal-sensors = <&tsens1 2>;
737 724
738 trips { 725 trips {
739 mem_alert0: tr 726 mem_alert0: trip-point0 {
740 temper 727 temperature = <90000>;
741 hyster 728 hysteresis = <2000>;
742 type = 729 type = "hot";
743 }; 730 };
744 }; 731 };
745 }; 732 };
746 733
747 wlan-thermal { 734 wlan-thermal {
748 polling-delay-passive 735 polling-delay-passive = <250>;
>> 736 polling-delay = <1000>;
749 737
750 thermal-sensors = <&ts 738 thermal-sensors = <&tsens1 3>;
751 739
752 trips { 740 trips {
753 wlan_alert0: t 741 wlan_alert0: trip-point0 {
754 temper 742 temperature = <90000>;
755 hyster 743 hysteresis = <2000>;
756 type = 744 type = "hot";
757 }; 745 };
758 }; 746 };
759 }; 747 };
760 748
761 q6-dsp-thermal { 749 q6-dsp-thermal {
762 polling-delay-passive 750 polling-delay-passive = <250>;
>> 751 polling-delay = <1000>;
763 752
764 thermal-sensors = <&ts 753 thermal-sensors = <&tsens1 4>;
765 754
766 trips { 755 trips {
767 q6_dsp_alert0: 756 q6_dsp_alert0: trip-point0 {
768 temper 757 temperature = <90000>;
769 hyster 758 hysteresis = <2000>;
770 type = 759 type = "hot";
771 }; 760 };
772 }; 761 };
773 }; 762 };
774 763
775 camera-thermal { 764 camera-thermal {
776 polling-delay-passive 765 polling-delay-passive = <250>;
>> 766 polling-delay = <1000>;
777 767
778 thermal-sensors = <&ts 768 thermal-sensors = <&tsens1 5>;
779 769
780 trips { 770 trips {
781 camera_alert0: 771 camera_alert0: trip-point0 {
782 temper 772 temperature = <90000>;
783 hyster 773 hysteresis = <2000>;
784 type = 774 type = "hot";
785 }; 775 };
786 }; 776 };
787 }; 777 };
788 778
789 multimedia-thermal { 779 multimedia-thermal {
790 polling-delay-passive 780 polling-delay-passive = <250>;
>> 781 polling-delay = <1000>;
791 782
792 thermal-sensors = <&ts 783 thermal-sensors = <&tsens1 6>;
793 784
794 trips { 785 trips {
795 multimedia_ale 786 multimedia_alert0: trip-point0 {
796 temper 787 temperature = <90000>;
797 hyster 788 hysteresis = <2000>;
798 type = 789 type = "hot";
799 }; 790 };
800 }; 791 };
801 }; 792 };
802 }; 793 };
803 794
804 timer { 795 timer {
805 compatible = "arm,armv8-timer" 796 compatible = "arm,armv8-timer";
806 interrupts = <GIC_PPI 1 IRQ_TY 797 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
807 <GIC_PPI 2 IRQ_TY 798 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
808 <GIC_PPI 3 IRQ_TY 799 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
809 <GIC_PPI 0 IRQ_TY 800 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
810 }; 801 };
811 802
812 soc: soc@0 { !! 803 soc: soc {
813 #address-cells = <1>; 804 #address-cells = <1>;
814 #size-cells = <1>; 805 #size-cells = <1>;
815 ranges = <0 0 0 0xffffffff>; 806 ranges = <0 0 0 0xffffffff>;
816 compatible = "simple-bus"; 807 compatible = "simple-bus";
817 808
818 gcc: clock-controller@100000 { 809 gcc: clock-controller@100000 {
819 compatible = "qcom,gcc 810 compatible = "qcom,gcc-msm8998";
820 #clock-cells = <1>; 811 #clock-cells = <1>;
821 #reset-cells = <1>; 812 #reset-cells = <1>;
822 #power-domain-cells = 813 #power-domain-cells = <1>;
823 reg = <0x00100000 0xb0 814 reg = <0x00100000 0xb0000>;
824 815
825 clock-names = "xo", "s 816 clock-names = "xo", "sleep_clk";
826 clocks = <&rpmcc RPM_S !! 817 clocks = <&xo>, <&sleep_clk>;
827 818
828 /* 819 /*
829 * The hypervisor typi 820 * The hypervisor typically configures the memory region where these clocks
830 * reside as read-only 821 * reside as read-only for the HLOS. If the HLOS tried to enable or disable
831 * these clocks on a d 822 * these clocks on a device with such configuration (e.g. because they are
832 * enabled but unused 823 * enabled but unused during boot-up), the device will most likely decide
833 * to reboot. 824 * to reboot.
834 * In light of that, w 825 * In light of that, we are conservative here and we list all such clocks
835 * as protected. The b 826 * as protected. The board dts (or a user-supplied dts) can override the
836 * list of protected c 827 * list of protected clocks if it differs from the norm, and it is in fact
837 * desired for the HLO 828 * desired for the HLOS to manage these clocks
838 */ 829 */
839 protected-clocks = <AG 830 protected-clocks = <AGGRE2_SNOC_NORTH_AXI>,
840 <SS 831 <SSC_XO>,
841 <SS 832 <SSC_CNOC_AHBS_CLK>;
842 }; 833 };
843 834
844 rpm_msg_ram: sram@778000 { 835 rpm_msg_ram: sram@778000 {
845 compatible = "qcom,rpm 836 compatible = "qcom,rpm-msg-ram";
846 reg = <0x00778000 0x70 837 reg = <0x00778000 0x7000>;
847 }; 838 };
848 839
849 qfprom: qfprom@784000 { 840 qfprom: qfprom@784000 {
850 compatible = "qcom,msm !! 841 compatible = "qcom,qfprom";
851 reg = <0x00784000 0x62 842 reg = <0x00784000 0x621c>;
852 #address-cells = <1>; 843 #address-cells = <1>;
853 #size-cells = <1>; 844 #size-cells = <1>;
854 845
855 qusb2_hstx_trim: hstx- 846 qusb2_hstx_trim: hstx-trim@23a {
856 reg = <0x23a 0 847 reg = <0x23a 0x1>;
857 bits = <0 4>; 848 bits = <0 4>;
858 }; 849 };
859 }; 850 };
860 851
861 tsens0: thermal@10ab000 { 852 tsens0: thermal@10ab000 {
862 compatible = "qcom,msm 853 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
863 reg = <0x010ab000 0x10 854 reg = <0x010ab000 0x1000>, /* TM */
864 <0x010aa000 0x10 855 <0x010aa000 0x1000>; /* SROT */
865 #qcom,sensors = <14>; 856 #qcom,sensors = <14>;
866 interrupts = <GIC_SPI 857 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
867 <GIC_SPI 858 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
868 interrupt-names = "upl 859 interrupt-names = "uplow", "critical";
869 #thermal-sensor-cells 860 #thermal-sensor-cells = <1>;
870 }; 861 };
871 862
872 tsens1: thermal@10ae000 { 863 tsens1: thermal@10ae000 {
873 compatible = "qcom,msm 864 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
874 reg = <0x010ae000 0x10 865 reg = <0x010ae000 0x1000>, /* TM */
875 <0x010ad000 0x10 866 <0x010ad000 0x1000>; /* SROT */
876 #qcom,sensors = <8>; 867 #qcom,sensors = <8>;
877 interrupts = <GIC_SPI 868 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
878 <GIC_SPI 869 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
879 interrupt-names = "upl 870 interrupt-names = "uplow", "critical";
880 #thermal-sensor-cells 871 #thermal-sensor-cells = <1>;
881 }; 872 };
882 873
883 anoc1_smmu: iommu@1680000 { 874 anoc1_smmu: iommu@1680000 {
884 compatible = "qcom,msm 875 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
885 reg = <0x01680000 0x10 876 reg = <0x01680000 0x10000>;
886 #iommu-cells = <1>; 877 #iommu-cells = <1>;
887 878
888 #global-interrupts = < 879 #global-interrupts = <0>;
889 interrupts = 880 interrupts =
890 <GIC_SPI 364 I 881 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
891 <GIC_SPI 365 I 882 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
892 <GIC_SPI 366 I 883 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
893 <GIC_SPI 367 I 884 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
894 <GIC_SPI 368 I 885 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
895 <GIC_SPI 369 I 886 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>;
896 }; 887 };
897 888
898 anoc2_smmu: iommu@16c0000 { 889 anoc2_smmu: iommu@16c0000 {
899 compatible = "qcom,msm 890 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
900 reg = <0x016c0000 0x40 891 reg = <0x016c0000 0x40000>;
901 #iommu-cells = <1>; 892 #iommu-cells = <1>;
902 893
903 #global-interrupts = < 894 #global-interrupts = <0>;
904 interrupts = 895 interrupts =
905 <GIC_SPI 373 I 896 <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>,
906 <GIC_SPI 374 I 897 <GIC_SPI 374 IRQ_TYPE_EDGE_RISING>,
907 <GIC_SPI 375 I 898 <GIC_SPI 375 IRQ_TYPE_EDGE_RISING>,
908 <GIC_SPI 376 I 899 <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>,
909 <GIC_SPI 377 I 900 <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>,
910 <GIC_SPI 378 I 901 <GIC_SPI 378 IRQ_TYPE_EDGE_RISING>,
911 <GIC_SPI 462 I 902 <GIC_SPI 462 IRQ_TYPE_EDGE_RISING>,
912 <GIC_SPI 463 I 903 <GIC_SPI 463 IRQ_TYPE_EDGE_RISING>,
913 <GIC_SPI 464 I 904 <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
914 <GIC_SPI 465 I 905 <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>;
915 }; 906 };
916 907
917 pcie0: pcie@1c00000 { !! 908 pcie0: pci@1c00000 {
918 compatible = "qcom,pci !! 909 compatible = "qcom,pcie-msm8996";
919 reg = <0x01c00000 0x20 !! 910 reg = <0x01c00000 0x2000>,
920 <0x1b000000 0xf1 !! 911 <0x1b000000 0xf1d>,
921 <0x1b000f20 0xa8 !! 912 <0x1b000f20 0xa8>,
922 <0x1b100000 0x10 !! 913 <0x1b100000 0x100000>;
923 reg-names = "parf", "d 914 reg-names = "parf", "dbi", "elbi", "config";
924 device_type = "pci"; 915 device_type = "pci";
925 linux,pci-domain = <0> 916 linux,pci-domain = <0>;
926 bus-range = <0x00 0xff 917 bus-range = <0x00 0xff>;
927 #address-cells = <3>; 918 #address-cells = <3>;
928 #size-cells = <2>; 919 #size-cells = <2>;
929 num-lanes = <1>; 920 num-lanes = <1>;
930 phys = <&pcie_phy>; !! 921 phys = <&pciephy>;
931 phy-names = "pciephy"; 922 phy-names = "pciephy";
932 status = "disabled"; 923 status = "disabled";
933 924
934 ranges = <0x01000000 0 !! 925 ranges = <0x01000000 0x0 0x1b200000 0x1b200000 0x0 0x100000>,
935 <0x02000000 0 926 <0x02000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>;
936 927
937 #interrupt-cells = <1> 928 #interrupt-cells = <1>;
938 interrupts = <GIC_SPI 929 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
939 interrupt-names = "msi 930 interrupt-names = "msi";
940 interrupt-map-mask = < 931 interrupt-map-mask = <0 0 0 0x7>;
941 interrupt-map = <0 0 0 !! 932 interrupt-map = <0 0 0 1 &intc 0 0 135 IRQ_TYPE_LEVEL_HIGH>,
942 <0 0 0 933 <0 0 0 2 &intc 0 0 136 IRQ_TYPE_LEVEL_HIGH>,
943 <0 0 0 934 <0 0 0 3 &intc 0 0 138 IRQ_TYPE_LEVEL_HIGH>,
944 <0 0 0 935 <0 0 0 4 &intc 0 0 139 IRQ_TYPE_LEVEL_HIGH>;
945 936
946 clocks = <&gcc GCC_PCI 937 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
947 <&gcc GCC_PCI <<
948 <&gcc GCC_PCI <<
949 <&gcc GCC_PCI 938 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
950 <&gcc GCC_PCI !! 939 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
951 clock-names = "pipe", !! 940 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
>> 941 <&gcc GCC_PCIE_0_AUX_CLK>;
>> 942 clock-names = "pipe", "bus_master", "bus_slave", "cfg", "aux";
952 943
953 power-domains = <&gcc 944 power-domains = <&gcc PCIE_0_GDSC>;
954 iommu-map = <0x100 &an 945 iommu-map = <0x100 &anoc1_smmu 0x1480 1>;
955 perst-gpios = <&tlmm 3 946 perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
956 <<
957 pcie@0 { <<
958 device_type = <<
959 reg = <0x0 0x0 <<
960 bus-range = <0 <<
961 <<
962 #address-cells <<
963 #size-cells = <<
964 ranges; <<
965 }; <<
966 }; 947 };
967 948
968 pcie_phy: phy@1c06000 { 949 pcie_phy: phy@1c06000 {
969 compatible = "qcom,msm 950 compatible = "qcom,msm8998-qmp-pcie-phy";
970 reg = <0x01c06000 0x10 !! 951 reg = <0x01c06000 0x18c>;
>> 952 #address-cells = <1>;
>> 953 #size-cells = <1>;
971 status = "disabled"; 954 status = "disabled";
>> 955 ranges;
972 956
973 clocks = <&gcc GCC_PCI 957 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
974 <&gcc GCC_PCI 958 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
975 <&gcc GCC_PCI !! 959 <&gcc GCC_PCIE_CLKREF_CLK>;
976 <&gcc GCC_PCI !! 960 clock-names = "aux", "cfg_ahb", "ref";
977 clock-names = "aux", <<
978 "cfg_ahb <<
979 "ref", <<
980 "pipe"; <<
981 <<
982 clock-output-names = " <<
983 #clock-cells = <0>; <<
984 <<
985 #phy-cells = <0>; <<
986 961
987 resets = <&gcc GCC_PCI 962 resets = <&gcc GCC_PCIE_0_PHY_BCR>, <&gcc GCC_PCIE_PHY_BCR>;
988 reset-names = "phy", " 963 reset-names = "phy", "common";
989 964
990 vdda-phy-supply = <&vr 965 vdda-phy-supply = <&vreg_l1a_0p875>;
991 vdda-pll-supply = <&vr 966 vdda-pll-supply = <&vreg_l2a_1p2>;
>> 967
>> 968 pciephy: phy@1c06800 {
>> 969 reg = <0x01c06200 0x128>, <0x01c06400 0x1fc>, <0x01c06800 0x20c>;
>> 970 #phy-cells = <0>;
>> 971
>> 972 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
>> 973 clock-names = "pipe0";
>> 974 clock-output-names = "pcie_0_pipe_clk_src";
>> 975 #clock-cells = <0>;
>> 976 };
992 }; 977 };
993 978
994 ufshc: ufshc@1da4000 { 979 ufshc: ufshc@1da4000 {
995 compatible = "qcom,msm 980 compatible = "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
996 reg = <0x01da4000 0x25 981 reg = <0x01da4000 0x2500>;
997 interrupts = <GIC_SPI 982 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
998 phys = <&ufsphy>; !! 983 phys = <&ufsphy_lanes>;
999 phy-names = "ufsphy"; 984 phy-names = "ufsphy";
1000 lanes-per-direction = 985 lanes-per-direction = <2>;
1001 power-domains = <&gcc 986 power-domains = <&gcc UFS_GDSC>;
1002 status = "disabled"; 987 status = "disabled";
1003 #reset-cells = <1>; 988 #reset-cells = <1>;
1004 989
1005 clock-names = 990 clock-names =
1006 "core_clk", 991 "core_clk",
1007 "bus_aggr_clk 992 "bus_aggr_clk",
1008 "iface_clk", 993 "iface_clk",
1009 "core_clk_uni 994 "core_clk_unipro",
1010 "ref_clk", 995 "ref_clk",
1011 "tx_lane0_syn 996 "tx_lane0_sync_clk",
1012 "rx_lane0_syn 997 "rx_lane0_sync_clk",
1013 "rx_lane1_syn 998 "rx_lane1_sync_clk";
1014 clocks = 999 clocks =
1015 <&gcc GCC_UFS 1000 <&gcc GCC_UFS_AXI_CLK>,
1016 <&gcc GCC_AGG 1001 <&gcc GCC_AGGRE1_UFS_AXI_CLK>,
1017 <&gcc GCC_UFS 1002 <&gcc GCC_UFS_AHB_CLK>,
1018 <&gcc GCC_UFS 1003 <&gcc GCC_UFS_UNIPRO_CORE_CLK>,
1019 <&rpmcc RPM_S 1004 <&rpmcc RPM_SMD_LN_BB_CLK1>,
1020 <&gcc GCC_UFS 1005 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
1021 <&gcc GCC_UFS 1006 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>,
1022 <&gcc GCC_UFS 1007 <&gcc GCC_UFS_RX_SYMBOL_1_CLK>;
1023 freq-table-hz = 1008 freq-table-hz =
1024 <50000000 200 1009 <50000000 200000000>,
1025 <0 0>, 1010 <0 0>,
1026 <0 0>, 1011 <0 0>,
1027 <37500000 150 1012 <37500000 150000000>,
1028 <0 0>, 1013 <0 0>,
1029 <0 0>, 1014 <0 0>,
1030 <0 0>, 1015 <0 0>,
1031 <0 0>; 1016 <0 0>;
1032 1017
1033 resets = <&gcc GCC_UF 1018 resets = <&gcc GCC_UFS_BCR>;
1034 reset-names = "rst"; 1019 reset-names = "rst";
1035 }; 1020 };
1036 1021
1037 ufsphy: phy@1da7000 { 1022 ufsphy: phy@1da7000 {
1038 compatible = "qcom,ms 1023 compatible = "qcom,msm8998-qmp-ufs-phy";
1039 reg = <0x01da7000 0x1 !! 1024 reg = <0x01da7000 0x18c>;
>> 1025 #address-cells = <1>;
>> 1026 #size-cells = <1>;
>> 1027 status = "disabled";
>> 1028 ranges;
1040 1029
1041 clocks = <&rpmcc RPM_ !! 1030 clock-names =
1042 <&gcc GCC_UF !! 1031 "ref",
1043 <&gcc GCC_UF !! 1032 "ref_aux";
1044 clock-names = "ref", !! 1033 clocks =
1045 "ref_au !! 1034 <&gcc GCC_UFS_CLKREF_CLK>,
1046 "qref"; !! 1035 <&gcc GCC_UFS_PHY_AUX_CLK>;
1047 1036
1048 reset-names = "ufsphy 1037 reset-names = "ufsphy";
1049 resets = <&ufshc 0>; 1038 resets = <&ufshc 0>;
1050 1039
1051 #phy-cells = <0>; !! 1040 ufsphy_lanes: phy@1da7400 {
1052 status = "disabled"; !! 1041 reg = <0x01da7400 0x128>,
1053 }; !! 1042 <0x01da7600 0x1fc>,
1054 !! 1043 <0x01da7c00 0x1dc>,
1055 tcsr_mutex: hwlock@1f40000 { !! 1044 <0x01da7800 0x128>,
1056 compatible = "qcom,tc !! 1045 <0x01da7a00 0x1fc>;
1057 reg = <0x01f40000 0x2 !! 1046 #phy-cells = <0>;
1058 #hwlock-cells = <1>; !! 1047 };
1059 }; <<
1060 <<
1061 tcsr_regs_1: syscon@1f60000 { <<
1062 compatible = "qcom,ms <<
1063 reg = <0x01f60000 0x2 <<
1064 }; 1048 };
1065 1049
1066 tcsr_regs_2: syscon@1fc0000 { !! 1050 tcsr_mutex_regs: syscon@1f40000 {
1067 compatible = "qcom,ms !! 1051 compatible = "syscon";
1068 reg = <0x01fc0000 0x2 !! 1052 reg = <0x01f40000 0x40000>;
1069 }; 1053 };
1070 1054
1071 tlmm: pinctrl@3400000 { 1055 tlmm: pinctrl@3400000 {
1072 compatible = "qcom,ms 1056 compatible = "qcom,msm8998-pinctrl";
1073 reg = <0x03400000 0xc 1057 reg = <0x03400000 0xc00000>;
1074 interrupts = <GIC_SPI 1058 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1075 gpio-ranges = <&tlmm <<
1076 gpio-controller; 1059 gpio-controller;
1077 #gpio-cells = <2>; !! 1060 #gpio-cells = <0x2>;
1078 interrupt-controller; 1061 interrupt-controller;
1079 #interrupt-cells = <2 !! 1062 #interrupt-cells = <0x2>;
1080 1063
1081 sdc2_on: sdc2-on-stat !! 1064 sdc2_clk_on: sdc2_clk_on {
1082 clk-pins { !! 1065 config {
1083 pins 1066 pins = "sdc2_clk";
>> 1067 bias-disable;
1084 drive 1068 drive-strength = <16>;
>> 1069 };
>> 1070 };
>> 1071
>> 1072 sdc2_clk_off: sdc2_clk_off {
>> 1073 config {
>> 1074 pins = "sdc2_clk";
1085 bias- 1075 bias-disable;
>> 1076 drive-strength = <2>;
1086 }; 1077 };
>> 1078 };
1087 1079
1088 cmd-pins { !! 1080 sdc2_cmd_on: sdc2_cmd_on {
>> 1081 config {
1089 pins 1082 pins = "sdc2_cmd";
>> 1083 bias-pull-up;
1090 drive 1084 drive-strength = <10>;
>> 1085 };
>> 1086 };
>> 1087
>> 1088 sdc2_cmd_off: sdc2_cmd_off {
>> 1089 config {
>> 1090 pins = "sdc2_cmd";
1091 bias- 1091 bias-pull-up;
>> 1092 drive-strength = <2>;
1092 }; 1093 };
>> 1094 };
1093 1095
1094 data-pins { !! 1096 sdc2_data_on: sdc2_data_on {
>> 1097 config {
1095 pins 1098 pins = "sdc2_data";
1096 drive <<
1097 bias- 1099 bias-pull-up;
>> 1100 drive-strength = <10>;
1098 }; 1101 };
1099 }; 1102 };
1100 1103
1101 sdc2_off: sdc2-off-st !! 1104 sdc2_data_off: sdc2_data_off {
1102 clk-pins { !! 1105 config {
1103 pins !! 1106 pins = "sdc2_data";
>> 1107 bias-pull-up;
1104 drive 1108 drive-strength = <2>;
1105 bias- <<
1106 }; 1109 };
>> 1110 };
1107 1111
1108 cmd-pins { !! 1112 sdc2_cd_on: sdc2_cd_on {
1109 pins !! 1113 mux {
1110 drive !! 1114 pins = "gpio95";
1111 bias- !! 1115 function = "gpio";
1112 }; 1116 };
1113 1117
1114 data-pins { !! 1118 config {
1115 pins !! 1119 pins = "gpio95";
1116 drive <<
1117 bias- 1120 bias-pull-up;
>> 1121 drive-strength = <2>;
1118 }; 1122 };
1119 }; 1123 };
1120 1124
1121 sdc2_cd: sdc2-cd-stat !! 1125 sdc2_cd_off: sdc2_cd_off {
1122 pins = "gpio9 !! 1126 mux {
1123 function = "g !! 1127 pins = "gpio95";
1124 bias-pull-up; !! 1128 function = "gpio";
1125 drive-strengt !! 1129 };
>> 1130
>> 1131 config {
>> 1132 pins = "gpio95";
>> 1133 bias-pull-up;
>> 1134 drive-strength = <2>;
>> 1135 };
1126 }; 1136 };
1127 1137
1128 blsp1_uart3_on: blsp1 !! 1138 blsp1_uart3_on: blsp1_uart3_on {
1129 tx-pins { !! 1139 tx {
1130 pins 1140 pins = "gpio45";
1131 funct 1141 function = "blsp_uart3_a";
1132 drive 1142 drive-strength = <2>;
1133 bias- 1143 bias-disable;
1134 }; 1144 };
1135 1145
1136 rx-pins { !! 1146 rx {
1137 pins 1147 pins = "gpio46";
1138 funct 1148 function = "blsp_uart3_a";
1139 drive 1149 drive-strength = <2>;
1140 bias- 1150 bias-disable;
1141 }; 1151 };
1142 1152
1143 cts-pins { !! 1153 cts {
1144 pins 1154 pins = "gpio47";
1145 funct 1155 function = "blsp_uart3_a";
1146 drive 1156 drive-strength = <2>;
1147 bias- 1157 bias-disable;
1148 }; 1158 };
1149 1159
1150 rfr-pins { !! 1160 rfr {
1151 pins 1161 pins = "gpio48";
1152 funct 1162 function = "blsp_uart3_a";
1153 drive 1163 drive-strength = <2>;
1154 bias- 1164 bias-disable;
1155 }; 1165 };
1156 }; 1166 };
1157 1167
1158 blsp1_i2c1_default: b !! 1168 blsp1_i2c1_default: blsp1-i2c1-default {
1159 pins = "gpio2 1169 pins = "gpio2", "gpio3";
1160 function = "b 1170 function = "blsp_i2c1";
1161 drive-strengt 1171 drive-strength = <2>;
1162 bias-disable; 1172 bias-disable;
1163 }; 1173 };
1164 1174
1165 blsp1_i2c1_sleep: bls !! 1175 blsp1_i2c1_sleep: blsp1-i2c1-sleep {
1166 pins = "gpio2 1176 pins = "gpio2", "gpio3";
1167 function = "b 1177 function = "blsp_i2c1";
1168 drive-strengt 1178 drive-strength = <2>;
1169 bias-pull-up; 1179 bias-pull-up;
1170 }; 1180 };
1171 1181
1172 blsp1_i2c2_default: b !! 1182 blsp1_i2c2_default: blsp1-i2c2-default {
1173 pins = "gpio3 1183 pins = "gpio32", "gpio33";
1174 function = "b 1184 function = "blsp_i2c2";
1175 drive-strengt 1185 drive-strength = <2>;
1176 bias-disable; 1186 bias-disable;
1177 }; 1187 };
1178 1188
1179 blsp1_i2c2_sleep: bls !! 1189 blsp1_i2c2_sleep: blsp1-i2c2-sleep {
1180 pins = "gpio3 1190 pins = "gpio32", "gpio33";
1181 function = "b 1191 function = "blsp_i2c2";
1182 drive-strengt 1192 drive-strength = <2>;
1183 bias-pull-up; 1193 bias-pull-up;
1184 }; 1194 };
1185 1195
1186 blsp1_i2c3_default: b !! 1196 blsp1_i2c3_default: blsp1-i2c3-default {
1187 pins = "gpio4 1197 pins = "gpio47", "gpio48";
1188 function = "b 1198 function = "blsp_i2c3";
1189 drive-strengt 1199 drive-strength = <2>;
1190 bias-disable; 1200 bias-disable;
1191 }; 1201 };
1192 1202
1193 blsp1_i2c3_sleep: bls !! 1203 blsp1_i2c3_sleep: blsp1-i2c3-sleep {
1194 pins = "gpio4 1204 pins = "gpio47", "gpio48";
1195 function = "b 1205 function = "blsp_i2c3";
1196 drive-strengt 1206 drive-strength = <2>;
1197 bias-pull-up; 1207 bias-pull-up;
1198 }; 1208 };
1199 1209
1200 blsp1_i2c4_default: b !! 1210 blsp1_i2c4_default: blsp1-i2c4-default {
1201 pins = "gpio1 1211 pins = "gpio10", "gpio11";
1202 function = "b 1212 function = "blsp_i2c4";
1203 drive-strengt 1213 drive-strength = <2>;
1204 bias-disable; 1214 bias-disable;
1205 }; 1215 };
1206 1216
1207 blsp1_i2c4_sleep: bls !! 1217 blsp1_i2c4_sleep: blsp1-i2c4-sleep {
1208 pins = "gpio1 1218 pins = "gpio10", "gpio11";
1209 function = "b 1219 function = "blsp_i2c4";
1210 drive-strengt 1220 drive-strength = <2>;
1211 bias-pull-up; 1221 bias-pull-up;
1212 }; 1222 };
1213 1223
1214 blsp1_i2c5_default: b !! 1224 blsp1_i2c5_default: blsp1-i2c5-default {
1215 pins = "gpio8 1225 pins = "gpio87", "gpio88";
1216 function = "b 1226 function = "blsp_i2c5";
1217 drive-strengt 1227 drive-strength = <2>;
1218 bias-disable; 1228 bias-disable;
1219 }; 1229 };
1220 1230
1221 blsp1_i2c5_sleep: bls !! 1231 blsp1_i2c5_sleep: blsp1-i2c5-sleep {
1222 pins = "gpio8 1232 pins = "gpio87", "gpio88";
1223 function = "b 1233 function = "blsp_i2c5";
1224 drive-strengt 1234 drive-strength = <2>;
1225 bias-pull-up; 1235 bias-pull-up;
1226 }; 1236 };
1227 1237
1228 blsp1_i2c6_default: b !! 1238 blsp1_i2c6_default: blsp1-i2c6-default {
1229 pins = "gpio4 1239 pins = "gpio43", "gpio44";
1230 function = "b 1240 function = "blsp_i2c6";
1231 drive-strengt 1241 drive-strength = <2>;
1232 bias-disable; 1242 bias-disable;
1233 }; 1243 };
1234 1244
1235 blsp1_i2c6_sleep: bls !! 1245 blsp1_i2c6_sleep: blsp1-i2c6-sleep {
1236 pins = "gpio4 1246 pins = "gpio43", "gpio44";
1237 function = "b 1247 function = "blsp_i2c6";
1238 drive-strengt 1248 drive-strength = <2>;
1239 bias-pull-up; 1249 bias-pull-up;
1240 }; 1250 };
1241 <<
1242 blsp1_spi_b_default: <<
1243 pins = "gpio2 <<
1244 function = "b <<
1245 drive-strengt <<
1246 bias-disable; <<
1247 }; <<
1248 <<
1249 blsp1_spi1_default: b <<
1250 pins = "gpio0 <<
1251 function = "b <<
1252 drive-strengt <<
1253 bias-disable; <<
1254 }; <<
1255 <<
1256 blsp1_spi2_default: b <<
1257 pins = "gpio3 <<
1258 function = "b <<
1259 drive-strengt <<
1260 bias-disable; <<
1261 }; <<
1262 <<
1263 blsp1_spi3_default: b <<
1264 pins = "gpio4 <<
1265 function = "b <<
1266 drive-strengt <<
1267 bias-disable; <<
1268 }; <<
1269 <<
1270 blsp1_spi4_default: b <<
1271 pins = "gpio8 <<
1272 function = "b <<
1273 drive-strengt <<
1274 bias-disable; <<
1275 }; <<
1276 <<
1277 blsp1_spi5_default: b <<
1278 pins = "gpio8 <<
1279 function = "b <<
1280 drive-strengt <<
1281 bias-disable; <<
1282 }; <<
1283 <<
1284 blsp1_spi6_default: b <<
1285 pins = "gpio4 <<
1286 function = "b <<
1287 drive-strengt <<
1288 bias-disable; <<
1289 }; <<
1290 <<
1291 <<
1292 /* 6 interfaces per Q 1251 /* 6 interfaces per QUP, BLSP2 indexes are numbered (n)+6 */
1293 blsp2_i2c1_default: b !! 1252 blsp2_i2c1_default: blsp2-i2c1-default {
1294 pins = "gpio5 1253 pins = "gpio55", "gpio56";
1295 function = "b 1254 function = "blsp_i2c7";
1296 drive-strengt 1255 drive-strength = <2>;
1297 bias-disable; 1256 bias-disable;
1298 }; 1257 };
1299 1258
1300 blsp2_i2c1_sleep: bls !! 1259 blsp2_i2c1_sleep: blsp2-i2c1-sleep {
1301 pins = "gpio5 1260 pins = "gpio55", "gpio56";
1302 function = "b 1261 function = "blsp_i2c7";
1303 drive-strengt 1262 drive-strength = <2>;
1304 bias-pull-up; 1263 bias-pull-up;
1305 }; 1264 };
1306 1265
1307 blsp2_i2c2_default: b !! 1266 blsp2_i2c2_default: blsp2-i2c2-default {
1308 pins = "gpio6 1267 pins = "gpio6", "gpio7";
1309 function = "b 1268 function = "blsp_i2c8";
1310 drive-strengt 1269 drive-strength = <2>;
1311 bias-disable; 1270 bias-disable;
1312 }; 1271 };
1313 1272
1314 blsp2_i2c2_sleep: bls !! 1273 blsp2_i2c2_sleep: blsp2-i2c2-sleep {
1315 pins = "gpio6 1274 pins = "gpio6", "gpio7";
1316 function = "b 1275 function = "blsp_i2c8";
1317 drive-strengt 1276 drive-strength = <2>;
1318 bias-pull-up; 1277 bias-pull-up;
1319 }; 1278 };
1320 1279
1321 blsp2_i2c3_default: b !! 1280 blsp2_i2c3_default: blsp2-i2c3-default {
1322 pins = "gpio5 1281 pins = "gpio51", "gpio52";
1323 function = "b 1282 function = "blsp_i2c9";
1324 drive-strengt 1283 drive-strength = <2>;
1325 bias-disable; 1284 bias-disable;
1326 }; 1285 };
1327 1286
1328 blsp2_i2c3_sleep: bls !! 1287 blsp2_i2c3_sleep: blsp2-i2c3-sleep {
1329 pins = "gpio5 1288 pins = "gpio51", "gpio52";
1330 function = "b 1289 function = "blsp_i2c9";
1331 drive-strengt 1290 drive-strength = <2>;
1332 bias-pull-up; 1291 bias-pull-up;
1333 }; 1292 };
1334 1293
1335 blsp2_i2c4_default: b !! 1294 blsp2_i2c4_default: blsp2-i2c4-default {
1336 pins = "gpio6 1295 pins = "gpio67", "gpio68";
1337 function = "b 1296 function = "blsp_i2c10";
1338 drive-strengt 1297 drive-strength = <2>;
1339 bias-disable; 1298 bias-disable;
1340 }; 1299 };
1341 1300
1342 blsp2_i2c4_sleep: bls !! 1301 blsp2_i2c4_sleep: blsp2-i2c4-sleep {
1343 pins = "gpio6 1302 pins = "gpio67", "gpio68";
1344 function = "b 1303 function = "blsp_i2c10";
1345 drive-strengt 1304 drive-strength = <2>;
1346 bias-pull-up; 1305 bias-pull-up;
1347 }; 1306 };
1348 1307
1349 blsp2_i2c5_default: b !! 1308 blsp2_i2c5_default: blsp2-i2c5-default {
1350 pins = "gpio6 1309 pins = "gpio60", "gpio61";
1351 function = "b 1310 function = "blsp_i2c11";
1352 drive-strengt 1311 drive-strength = <2>;
1353 bias-disable; 1312 bias-disable;
1354 }; 1313 };
1355 1314
1356 blsp2_i2c5_sleep: bls !! 1315 blsp2_i2c5_sleep: blsp2-i2c5-sleep {
1357 pins = "gpio6 1316 pins = "gpio60", "gpio61";
1358 function = "b 1317 function = "blsp_i2c11";
1359 drive-strengt 1318 drive-strength = <2>;
1360 bias-pull-up; 1319 bias-pull-up;
1361 }; 1320 };
1362 1321
1363 blsp2_i2c6_default: b !! 1322 blsp2_i2c6_default: blsp2-i2c6-default {
1364 pins = "gpio8 1323 pins = "gpio83", "gpio84";
1365 function = "b 1324 function = "blsp_i2c12";
1366 drive-strengt 1325 drive-strength = <2>;
1367 bias-disable; 1326 bias-disable;
1368 }; 1327 };
1369 1328
1370 blsp2_i2c6_sleep: bls !! 1329 blsp2_i2c6_sleep: blsp2-i2c6-sleep {
1371 pins = "gpio8 1330 pins = "gpio83", "gpio84";
1372 function = "b 1331 function = "blsp_i2c12";
1373 drive-strengt 1332 drive-strength = <2>;
1374 bias-pull-up; 1333 bias-pull-up;
1375 }; 1334 };
1376 <<
1377 blsp2_spi1_default: b <<
1378 pins = "gpio5 <<
1379 function = "b <<
1380 drive-strengt <<
1381 bias-disable; <<
1382 }; <<
1383 <<
1384 blsp2_spi2_default: b <<
1385 pins = "gpio4 <<
1386 function = "b <<
1387 drive-strengt <<
1388 bias-disable; <<
1389 }; <<
1390 <<
1391 blsp2_spi3_default: b <<
1392 pins = "gpio4 <<
1393 function = "b <<
1394 drive-strengt <<
1395 bias-disable; <<
1396 }; <<
1397 <<
1398 blsp2_spi4_default: b <<
1399 pins = "gpio6 <<
1400 function = "b <<
1401 drive-strengt <<
1402 bias-disable; <<
1403 }; <<
1404 <<
1405 blsp2_spi5_default: b <<
1406 pins = "gpio5 <<
1407 function = "b <<
1408 drive-strengt <<
1409 bias-disable; <<
1410 }; <<
1411 <<
1412 blsp2_spi6_default: b <<
1413 pins = "gpio8 <<
1414 function = "b <<
1415 drive-strengt <<
1416 bias-disable; <<
1417 }; <<
1418 }; 1335 };
1419 1336
1420 remoteproc_mss: remoteproc@40 1337 remoteproc_mss: remoteproc@4080000 {
1421 compatible = "qcom,ms 1338 compatible = "qcom,msm8998-mss-pil";
1422 reg = <0x04080000 0x1 1339 reg = <0x04080000 0x100>, <0x04180000 0x20>;
1423 reg-names = "qdsp6", 1340 reg-names = "qdsp6", "rmb";
1424 1341
1425 interrupts-extended = 1342 interrupts-extended =
1426 <&intc GIC_SP 1343 <&intc GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
1427 <&modem_smp2p 1344 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1428 <&modem_smp2p 1345 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1429 <&modem_smp2p 1346 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1430 <&modem_smp2p 1347 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
1431 <&modem_smp2p 1348 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
1432 interrupt-names = "wd 1349 interrupt-names = "wdog", "fatal", "ready",
1433 "ha 1350 "handover", "stop-ack",
1434 "sh 1351 "shutdown-ack";
1435 1352
1436 clocks = <&gcc GCC_MS 1353 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
1437 <&gcc GCC_BI 1354 <&gcc GCC_BIMC_MSS_Q6_AXI_CLK>,
1438 <&gcc GCC_BO 1355 <&gcc GCC_BOOT_ROM_AHB_CLK>,
1439 <&gcc GCC_MS 1356 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
1440 <&gcc GCC_MS 1357 <&gcc GCC_MSS_SNOC_AXI_CLK>,
1441 <&gcc GCC_MS 1358 <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>,
1442 <&rpmcc RPM_ 1359 <&rpmcc RPM_SMD_QDSS_CLK>,
1443 <&rpmcc RPM_ 1360 <&rpmcc RPM_SMD_XO_CLK_SRC>;
1444 clock-names = "iface" 1361 clock-names = "iface", "bus", "mem", "gpll0_mss",
1445 "snoc_a 1362 "snoc_axi", "mnoc_axi", "qdss", "xo";
1446 1363
1447 qcom,smem-states = <& 1364 qcom,smem-states = <&modem_smp2p_out 0>;
1448 qcom,smem-state-names 1365 qcom,smem-state-names = "stop";
1449 1366
1450 resets = <&gcc GCC_MS 1367 resets = <&gcc GCC_MSS_RESTART>;
1451 reset-names = "mss_re 1368 reset-names = "mss_restart";
1452 1369
1453 qcom,halt-regs = <&tc !! 1370 qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
1454 1371
1455 power-domains = <&rpm 1372 power-domains = <&rpmpd MSM8998_VDDCX>,
1456 <&rpm 1373 <&rpmpd MSM8998_VDDMX>;
1457 power-domain-names = 1374 power-domain-names = "cx", "mx";
1458 1375
1459 status = "disabled"; 1376 status = "disabled";
1460 1377
1461 mba { 1378 mba {
1462 memory-region 1379 memory-region = <&mba_mem>;
1463 }; 1380 };
1464 1381
1465 mpss { 1382 mpss {
1466 memory-region 1383 memory-region = <&mpss_mem>;
1467 }; 1384 };
1468 1385
1469 metadata { <<
1470 memory-region <<
1471 }; <<
1472 <<
1473 glink-edge { 1386 glink-edge {
1474 interrupts = 1387 interrupts = <GIC_SPI 452 IRQ_TYPE_EDGE_RISING>;
1475 label = "mode 1388 label = "modem";
1476 qcom,remote-p 1389 qcom,remote-pid = <1>;
1477 mboxes = <&ap 1390 mboxes = <&apcs_glb 15>;
1478 }; 1391 };
1479 }; 1392 };
1480 1393
1481 adreno_gpu: gpu@5000000 { 1394 adreno_gpu: gpu@5000000 {
1482 compatible = "qcom,ad 1395 compatible = "qcom,adreno-540.1", "qcom,adreno";
1483 reg = <0x05000000 0x4 1396 reg = <0x05000000 0x40000>;
1484 reg-names = "kgsl_3d0 1397 reg-names = "kgsl_3d0_reg_memory";
1485 1398
1486 clocks = <&gcc GCC_GP 1399 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
1487 <&gpucc RBBMT 1400 <&gpucc RBBMTIMER_CLK>,
1488 <&gcc GCC_BIM 1401 <&gcc GCC_BIMC_GFX_CLK>,
1489 <&gcc GCC_GPU 1402 <&gcc GCC_GPU_BIMC_GFX_CLK>,
1490 <&gpucc RBCPR 1403 <&gpucc RBCPR_CLK>,
1491 <&gpucc GFX3D 1404 <&gpucc GFX3D_CLK>;
1492 clock-names = "iface" 1405 clock-names = "iface",
1493 "rbbmtimer", 1406 "rbbmtimer",
1494 "mem", 1407 "mem",
1495 "mem_iface", 1408 "mem_iface",
1496 "rbcpr", 1409 "rbcpr",
1497 "core"; 1410 "core";
1498 1411
1499 interrupts = <GIC_SPI !! 1412 interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
1500 iommus = <&adreno_smm 1413 iommus = <&adreno_smmu 0>;
1501 operating-points-v2 = 1414 operating-points-v2 = <&gpu_opp_table>;
1502 power-domains = <&rpm 1415 power-domains = <&rpmpd MSM8998_VDDMX>;
1503 status = "disabled"; 1416 status = "disabled";
1504 1417
1505 gpu_opp_table: opp-ta 1418 gpu_opp_table: opp-table {
1506 compatible = !! 1419 compatible = "operating-points-v2";
1507 opp-710000097 1420 opp-710000097 {
1508 opp-h 1421 opp-hz = /bits/ 64 <710000097>;
1509 opp-l 1422 opp-level = <RPM_SMD_LEVEL_TURBO>;
1510 opp-s !! 1423 opp-supported-hw = <0xFF>;
1511 }; 1424 };
1512 1425
1513 opp-670000048 1426 opp-670000048 {
1514 opp-h 1427 opp-hz = /bits/ 64 <670000048>;
1515 opp-l 1428 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
1516 opp-s !! 1429 opp-supported-hw = <0xFF>;
1517 }; 1430 };
1518 1431
1519 opp-596000097 1432 opp-596000097 {
1520 opp-h 1433 opp-hz = /bits/ 64 <596000097>;
1521 opp-l 1434 opp-level = <RPM_SMD_LEVEL_NOM>;
1522 opp-s !! 1435 opp-supported-hw = <0xFF>;
1523 }; 1436 };
1524 1437
1525 opp-515000097 1438 opp-515000097 {
1526 opp-h 1439 opp-hz = /bits/ 64 <515000097>;
1527 opp-l 1440 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
1528 opp-s !! 1441 opp-supported-hw = <0xFF>;
1529 }; 1442 };
1530 1443
1531 opp-414000000 1444 opp-414000000 {
1532 opp-h 1445 opp-hz = /bits/ 64 <414000000>;
1533 opp-l 1446 opp-level = <RPM_SMD_LEVEL_SVS>;
1534 opp-s !! 1447 opp-supported-hw = <0xFF>;
1535 }; 1448 };
1536 1449
1537 opp-342000000 1450 opp-342000000 {
1538 opp-h 1451 opp-hz = /bits/ 64 <342000000>;
1539 opp-l 1452 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
1540 opp-s !! 1453 opp-supported-hw = <0xFF>;
1541 }; 1454 };
1542 1455
1543 opp-257000000 1456 opp-257000000 {
1544 opp-h 1457 opp-hz = /bits/ 64 <257000000>;
1545 opp-l 1458 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
1546 opp-s !! 1459 opp-supported-hw = <0xFF>;
1547 }; 1460 };
1548 }; 1461 };
1549 }; 1462 };
1550 1463
1551 adreno_smmu: iommu@5040000 { 1464 adreno_smmu: iommu@5040000 {
1552 compatible = "qcom,ms 1465 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
1553 reg = <0x05040000 0x1 1466 reg = <0x05040000 0x10000>;
1554 clocks = <&gcc GCC_GP 1467 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
1555 <&gcc GCC_BI 1468 <&gcc GCC_BIMC_GFX_CLK>,
1556 <&gcc GCC_GP 1469 <&gcc GCC_GPU_BIMC_GFX_CLK>;
1557 clock-names = "iface" 1470 clock-names = "iface", "mem", "mem_iface";
1558 1471
1559 #global-interrupts = 1472 #global-interrupts = <0>;
1560 #iommu-cells = <1>; 1473 #iommu-cells = <1>;
1561 interrupts = 1474 interrupts =
1562 <GIC_SPI 329 1475 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1563 <GIC_SPI 330 1476 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
1564 <GIC_SPI 331 1477 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
1565 /* 1478 /*
1566 * GPU-GX GDSC's pare 1479 * GPU-GX GDSC's parent is GPU-CX. We need to bring up the
1567 * GPU-CX for SMMU bu 1480 * GPU-CX for SMMU but we need both of them up for Adreno.
1568 * Contemporarily, we 1481 * Contemporarily, we also need to manage the VDDMX rpmpd
1569 * domain in the Adre 1482 * domain in the Adreno driver.
1570 * Enable GPU CX/GX G 1483 * Enable GPU CX/GX GDSCs here so that we can manage the
1571 * SoC VDDMX RPM Powe 1484 * SoC VDDMX RPM Power Domain in the Adreno driver.
1572 */ 1485 */
1573 power-domains = <&gpu 1486 power-domains = <&gpucc GPU_GX_GDSC>;
>> 1487 status = "disabled";
1574 }; 1488 };
1575 1489
1576 gpucc: clock-controller@50650 1490 gpucc: clock-controller@5065000 {
1577 compatible = "qcom,ms 1491 compatible = "qcom,msm8998-gpucc";
1578 #clock-cells = <1>; 1492 #clock-cells = <1>;
1579 #reset-cells = <1>; 1493 #reset-cells = <1>;
1580 #power-domain-cells = 1494 #power-domain-cells = <1>;
1581 reg = <0x05065000 0x9 1495 reg = <0x05065000 0x9000>;
1582 1496
1583 clocks = <&rpmcc RPM_ 1497 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1584 <&gcc GCC_GP !! 1498 <&gcc GPLL0_OUT_MAIN>;
1585 clock-names = "xo", 1499 clock-names = "xo",
1586 "gpll0" 1500 "gpll0";
1587 }; 1501 };
1588 1502
1589 lpass_q6_smmu: iommu@5100000 <<
1590 compatible = "qcom,ms <<
1591 reg = <0x05100000 0x4 <<
1592 clocks = <&gcc HLOS1_ <<
1593 clock-names = "bus"; <<
1594 <<
1595 #global-interrupts = <<
1596 #iommu-cells = <1>; <<
1597 interrupts = <<
1598 <GIC_SPI 226 <<
1599 <GIC_SPI 393 <<
1600 <GIC_SPI 394 <<
1601 <GIC_SPI 395 <<
1602 <GIC_SPI 396 <<
1603 <GIC_SPI 397 <<
1604 <GIC_SPI 398 <<
1605 <GIC_SPI 399 <<
1606 <GIC_SPI 400 <<
1607 <GIC_SPI 401 <<
1608 <GIC_SPI 402 <<
1609 <GIC_SPI 403 <<
1610 <GIC_SPI 137 <<
1611 <<
1612 power-domains = <&gcc <<
1613 status = "disabled"; <<
1614 }; <<
1615 <<
1616 remoteproc_slpi: remoteproc@5 1503 remoteproc_slpi: remoteproc@5800000 {
1617 compatible = "qcom,ms 1504 compatible = "qcom,msm8998-slpi-pas";
1618 reg = <0x05800000 0x4 1505 reg = <0x05800000 0x4040>;
1619 1506
1620 interrupts-extended = 1507 interrupts-extended = <&intc GIC_SPI 390 IRQ_TYPE_EDGE_RISING>,
1621 1508 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1622 1509 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1623 1510 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1624 1511 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1625 interrupt-names = "wd 1512 interrupt-names = "wdog", "fatal", "ready",
1626 "ha 1513 "handover", "stop-ack";
1627 1514
1628 px-supply = <&vreg_lv 1515 px-supply = <&vreg_lvs2a_1p8>;
1629 1516
1630 clocks = <&rpmcc RPM_ !! 1517 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1631 clock-names = "xo"; !! 1518 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
>> 1519 clock-names = "xo", "aggre2";
1632 1520
1633 memory-region = <&slp 1521 memory-region = <&slpi_mem>;
1634 1522
1635 qcom,smem-states = <& 1523 qcom,smem-states = <&slpi_smp2p_out 0>;
1636 qcom,smem-state-names 1524 qcom,smem-state-names = "stop";
1637 1525
1638 power-domains = <&rpm 1526 power-domains = <&rpmpd MSM8998_SSCCX>;
1639 power-domain-names = 1527 power-domain-names = "ssc_cx";
1640 1528
1641 status = "disabled"; 1529 status = "disabled";
1642 1530
1643 glink-edge { 1531 glink-edge {
1644 interrupts = 1532 interrupts = <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>;
1645 label = "dsps 1533 label = "dsps";
1646 qcom,remote-p 1534 qcom,remote-pid = <3>;
1647 mboxes = <&ap 1535 mboxes = <&apcs_glb 27>;
1648 }; 1536 };
1649 }; 1537 };
1650 1538
1651 stm: stm@6002000 { 1539 stm: stm@6002000 {
1652 compatible = "arm,cor 1540 compatible = "arm,coresight-stm", "arm,primecell";
1653 reg = <0x06002000 0x1 1541 reg = <0x06002000 0x1000>,
1654 <0x16280000 0x1 1542 <0x16280000 0x180000>;
1655 reg-names = "stm-base !! 1543 reg-names = "stm-base", "stm-data-base";
1656 status = "disabled"; 1544 status = "disabled";
1657 1545
1658 clocks = <&rpmcc RPM_ 1546 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1659 clock-names = "apb_pc 1547 clock-names = "apb_pclk", "atclk";
1660 1548
1661 out-ports { 1549 out-ports {
1662 port { 1550 port {
1663 stm_o 1551 stm_out: endpoint {
1664 1552 remote-endpoint = <&funnel0_in7>;
1665 }; 1553 };
1666 }; 1554 };
1667 }; 1555 };
1668 }; 1556 };
1669 1557
1670 funnel1: funnel@6041000 { 1558 funnel1: funnel@6041000 {
1671 compatible = "arm,cor 1559 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1672 reg = <0x06041000 0x1 1560 reg = <0x06041000 0x1000>;
1673 status = "disabled"; 1561 status = "disabled";
1674 1562
1675 clocks = <&rpmcc RPM_ 1563 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1676 clock-names = "apb_pc 1564 clock-names = "apb_pclk", "atclk";
1677 1565
1678 out-ports { 1566 out-ports {
1679 port { 1567 port {
1680 funne 1568 funnel0_out: endpoint {
1681 1569 remote-endpoint =
1682 1570 <&merge_funnel_in0>;
1683 }; 1571 };
1684 }; 1572 };
1685 }; 1573 };
1686 1574
1687 in-ports { 1575 in-ports {
1688 #address-cell 1576 #address-cells = <1>;
1689 #size-cells = 1577 #size-cells = <0>;
1690 1578
1691 port@7 { 1579 port@7 {
1692 reg = 1580 reg = <7>;
1693 funne 1581 funnel0_in7: endpoint {
1694 1582 remote-endpoint = <&stm_out>;
1695 }; 1583 };
1696 }; 1584 };
1697 }; 1585 };
1698 }; 1586 };
1699 1587
1700 funnel2: funnel@6042000 { 1588 funnel2: funnel@6042000 {
1701 compatible = "arm,cor 1589 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1702 reg = <0x06042000 0x1 1590 reg = <0x06042000 0x1000>;
1703 status = "disabled"; 1591 status = "disabled";
1704 1592
1705 clocks = <&rpmcc RPM_ 1593 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1706 clock-names = "apb_pc 1594 clock-names = "apb_pclk", "atclk";
1707 1595
1708 out-ports { 1596 out-ports {
1709 port { 1597 port {
1710 funne 1598 funnel1_out: endpoint {
1711 1599 remote-endpoint =
1712 1600 <&merge_funnel_in1>;
1713 }; 1601 };
1714 }; 1602 };
1715 }; 1603 };
1716 1604
1717 in-ports { 1605 in-ports {
1718 #address-cell 1606 #address-cells = <1>;
1719 #size-cells = 1607 #size-cells = <0>;
1720 1608
1721 port@6 { 1609 port@6 {
1722 reg = 1610 reg = <6>;
1723 funne 1611 funnel1_in6: endpoint {
1724 1612 remote-endpoint =
1725 1613 <&apss_merge_funnel_out>;
1726 }; 1614 };
1727 }; 1615 };
1728 }; 1616 };
1729 }; 1617 };
1730 1618
1731 funnel3: funnel@6045000 { 1619 funnel3: funnel@6045000 {
1732 compatible = "arm,cor 1620 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1733 reg = <0x06045000 0x1 1621 reg = <0x06045000 0x1000>;
1734 status = "disabled"; 1622 status = "disabled";
1735 1623
1736 clocks = <&rpmcc RPM_ 1624 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1737 clock-names = "apb_pc 1625 clock-names = "apb_pclk", "atclk";
1738 1626
1739 out-ports { 1627 out-ports {
1740 port { 1628 port {
1741 merge 1629 merge_funnel_out: endpoint {
1742 1630 remote-endpoint =
1743 1631 <&etf_in>;
1744 }; 1632 };
1745 }; 1633 };
1746 }; 1634 };
1747 1635
1748 in-ports { 1636 in-ports {
1749 #address-cell 1637 #address-cells = <1>;
1750 #size-cells = 1638 #size-cells = <0>;
1751 1639
1752 port@0 { 1640 port@0 {
1753 reg = 1641 reg = <0>;
1754 merge 1642 merge_funnel_in0: endpoint {
1755 1643 remote-endpoint =
1756 1644 <&funnel0_out>;
1757 }; 1645 };
1758 }; 1646 };
1759 1647
1760 port@1 { 1648 port@1 {
1761 reg = 1649 reg = <1>;
1762 merge 1650 merge_funnel_in1: endpoint {
1763 1651 remote-endpoint =
1764 1652 <&funnel1_out>;
1765 }; 1653 };
1766 }; 1654 };
1767 }; 1655 };
1768 }; 1656 };
1769 1657
1770 replicator1: replicator@60460 1658 replicator1: replicator@6046000 {
1771 compatible = "arm,cor 1659 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
1772 reg = <0x06046000 0x1 1660 reg = <0x06046000 0x1000>;
1773 status = "disabled"; 1661 status = "disabled";
1774 1662
1775 clocks = <&rpmcc RPM_ 1663 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1776 clock-names = "apb_pc 1664 clock-names = "apb_pclk", "atclk";
1777 1665
1778 out-ports { 1666 out-ports {
1779 port { 1667 port {
1780 repli 1668 replicator_out: endpoint {
1781 1669 remote-endpoint = <&etr_in>;
1782 }; 1670 };
1783 }; 1671 };
1784 }; 1672 };
1785 1673
1786 in-ports { 1674 in-ports {
1787 port { 1675 port {
1788 repli 1676 replicator_in: endpoint {
1789 1677 remote-endpoint = <&etf_out>;
1790 }; 1678 };
1791 }; 1679 };
1792 }; 1680 };
1793 }; 1681 };
1794 1682
1795 etf: etf@6047000 { 1683 etf: etf@6047000 {
1796 compatible = "arm,cor 1684 compatible = "arm,coresight-tmc", "arm,primecell";
1797 reg = <0x06047000 0x1 1685 reg = <0x06047000 0x1000>;
1798 status = "disabled"; 1686 status = "disabled";
1799 1687
1800 clocks = <&rpmcc RPM_ 1688 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1801 clock-names = "apb_pc 1689 clock-names = "apb_pclk", "atclk";
1802 1690
1803 out-ports { 1691 out-ports {
1804 port { 1692 port {
1805 etf_o 1693 etf_out: endpoint {
1806 1694 remote-endpoint =
1807 1695 <&replicator_in>;
1808 }; 1696 };
1809 }; 1697 };
1810 }; 1698 };
1811 1699
1812 in-ports { 1700 in-ports {
1813 port { 1701 port {
1814 etf_i 1702 etf_in: endpoint {
1815 1703 remote-endpoint =
1816 1704 <&merge_funnel_out>;
1817 }; 1705 };
1818 }; 1706 };
1819 }; 1707 };
1820 }; 1708 };
1821 1709
1822 etr: etr@6048000 { 1710 etr: etr@6048000 {
1823 compatible = "arm,cor 1711 compatible = "arm,coresight-tmc", "arm,primecell";
1824 reg = <0x06048000 0x1 1712 reg = <0x06048000 0x1000>;
1825 status = "disabled"; 1713 status = "disabled";
1826 1714
1827 clocks = <&rpmcc RPM_ 1715 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1828 clock-names = "apb_pc 1716 clock-names = "apb_pclk", "atclk";
1829 arm,scatter-gather; 1717 arm,scatter-gather;
1830 1718
1831 in-ports { 1719 in-ports {
1832 port { 1720 port {
1833 etr_i 1721 etr_in: endpoint {
1834 1722 remote-endpoint =
1835 1723 <&replicator_out>;
1836 }; 1724 };
1837 }; 1725 };
1838 }; 1726 };
1839 }; 1727 };
1840 1728
1841 etm1: etm@7840000 { 1729 etm1: etm@7840000 {
1842 compatible = "arm,cor 1730 compatible = "arm,coresight-etm4x", "arm,primecell";
1843 reg = <0x07840000 0x1 1731 reg = <0x07840000 0x1000>;
1844 status = "disabled"; 1732 status = "disabled";
1845 1733
1846 clocks = <&rpmcc RPM_ 1734 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1847 clock-names = "apb_pc 1735 clock-names = "apb_pclk", "atclk";
1848 1736
1849 cpu = <&CPU0>; 1737 cpu = <&CPU0>;
1850 1738
1851 out-ports { 1739 out-ports {
1852 port { 1740 port {
1853 etm0_ 1741 etm0_out: endpoint {
1854 1742 remote-endpoint =
1855 1743 <&apss_funnel_in0>;
1856 }; 1744 };
1857 }; 1745 };
1858 }; 1746 };
1859 }; 1747 };
1860 1748
1861 etm2: etm@7940000 { 1749 etm2: etm@7940000 {
1862 compatible = "arm,cor 1750 compatible = "arm,coresight-etm4x", "arm,primecell";
1863 reg = <0x07940000 0x1 1751 reg = <0x07940000 0x1000>;
1864 status = "disabled"; 1752 status = "disabled";
1865 1753
1866 clocks = <&rpmcc RPM_ 1754 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1867 clock-names = "apb_pc 1755 clock-names = "apb_pclk", "atclk";
1868 1756
1869 cpu = <&CPU1>; 1757 cpu = <&CPU1>;
1870 1758
1871 out-ports { 1759 out-ports {
1872 port { 1760 port {
1873 etm1_ 1761 etm1_out: endpoint {
1874 1762 remote-endpoint =
1875 1763 <&apss_funnel_in1>;
1876 }; 1764 };
1877 }; 1765 };
1878 }; 1766 };
1879 }; 1767 };
1880 1768
1881 etm3: etm@7a40000 { 1769 etm3: etm@7a40000 {
1882 compatible = "arm,cor 1770 compatible = "arm,coresight-etm4x", "arm,primecell";
1883 reg = <0x07a40000 0x1 1771 reg = <0x07a40000 0x1000>;
1884 status = "disabled"; 1772 status = "disabled";
1885 1773
1886 clocks = <&rpmcc RPM_ 1774 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1887 clock-names = "apb_pc 1775 clock-names = "apb_pclk", "atclk";
1888 1776
1889 cpu = <&CPU2>; 1777 cpu = <&CPU2>;
1890 1778
1891 out-ports { 1779 out-ports {
1892 port { 1780 port {
1893 etm2_ 1781 etm2_out: endpoint {
1894 1782 remote-endpoint =
1895 1783 <&apss_funnel_in2>;
1896 }; 1784 };
1897 }; 1785 };
1898 }; 1786 };
1899 }; 1787 };
1900 1788
1901 etm4: etm@7b40000 { 1789 etm4: etm@7b40000 {
1902 compatible = "arm,cor 1790 compatible = "arm,coresight-etm4x", "arm,primecell";
1903 reg = <0x07b40000 0x1 1791 reg = <0x07b40000 0x1000>;
1904 status = "disabled"; 1792 status = "disabled";
1905 1793
1906 clocks = <&rpmcc RPM_ 1794 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1907 clock-names = "apb_pc 1795 clock-names = "apb_pclk", "atclk";
1908 1796
1909 cpu = <&CPU3>; 1797 cpu = <&CPU3>;
1910 1798
1911 out-ports { 1799 out-ports {
1912 port { 1800 port {
1913 etm3_ 1801 etm3_out: endpoint {
1914 1802 remote-endpoint =
1915 1803 <&apss_funnel_in3>;
1916 }; 1804 };
1917 }; 1805 };
1918 }; 1806 };
1919 }; 1807 };
1920 1808
1921 funnel4: funnel@7b60000 { /* 1809 funnel4: funnel@7b60000 { /* APSS Funnel */
1922 compatible = "arm,cor 1810 compatible = "arm,coresight-etm4x", "arm,primecell";
1923 reg = <0x07b60000 0x1 1811 reg = <0x07b60000 0x1000>;
1924 status = "disabled"; 1812 status = "disabled";
1925 1813
1926 clocks = <&rpmcc RPM_ 1814 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1927 clock-names = "apb_pc 1815 clock-names = "apb_pclk", "atclk";
1928 1816
1929 out-ports { 1817 out-ports {
1930 port { 1818 port {
1931 apss_ 1819 apss_funnel_out: endpoint {
1932 1820 remote-endpoint =
1933 1821 <&apss_merge_funnel_in>;
1934 }; 1822 };
1935 }; 1823 };
1936 }; 1824 };
1937 1825
1938 in-ports { 1826 in-ports {
1939 #address-cell 1827 #address-cells = <1>;
1940 #size-cells = 1828 #size-cells = <0>;
1941 1829
1942 port@0 { 1830 port@0 {
1943 reg = 1831 reg = <0>;
1944 apss_ 1832 apss_funnel_in0: endpoint {
1945 1833 remote-endpoint =
1946 1834 <&etm0_out>;
1947 }; 1835 };
1948 }; 1836 };
1949 1837
1950 port@1 { 1838 port@1 {
1951 reg = 1839 reg = <1>;
1952 apss_ 1840 apss_funnel_in1: endpoint {
1953 1841 remote-endpoint =
1954 1842 <&etm1_out>;
1955 }; 1843 };
1956 }; 1844 };
1957 1845
1958 port@2 { 1846 port@2 {
1959 reg = 1847 reg = <2>;
1960 apss_ 1848 apss_funnel_in2: endpoint {
1961 1849 remote-endpoint =
1962 1850 <&etm2_out>;
1963 }; 1851 };
1964 }; 1852 };
1965 1853
1966 port@3 { 1854 port@3 {
1967 reg = 1855 reg = <3>;
1968 apss_ 1856 apss_funnel_in3: endpoint {
1969 1857 remote-endpoint =
1970 1858 <&etm3_out>;
1971 }; 1859 };
1972 }; 1860 };
1973 1861
1974 port@4 { 1862 port@4 {
1975 reg = 1863 reg = <4>;
1976 apss_ 1864 apss_funnel_in4: endpoint {
1977 1865 remote-endpoint =
1978 1866 <&etm4_out>;
1979 }; 1867 };
1980 }; 1868 };
1981 1869
1982 port@5 { 1870 port@5 {
1983 reg = 1871 reg = <5>;
1984 apss_ 1872 apss_funnel_in5: endpoint {
1985 1873 remote-endpoint =
1986 1874 <&etm5_out>;
1987 }; 1875 };
1988 }; 1876 };
1989 1877
1990 port@6 { 1878 port@6 {
1991 reg = 1879 reg = <6>;
1992 apss_ 1880 apss_funnel_in6: endpoint {
1993 1881 remote-endpoint =
1994 1882 <&etm6_out>;
1995 }; 1883 };
1996 }; 1884 };
1997 1885
1998 port@7 { 1886 port@7 {
1999 reg = 1887 reg = <7>;
2000 apss_ 1888 apss_funnel_in7: endpoint {
2001 1889 remote-endpoint =
2002 1890 <&etm7_out>;
2003 }; 1891 };
2004 }; 1892 };
2005 }; 1893 };
2006 }; 1894 };
2007 1895
2008 funnel5: funnel@7b70000 { 1896 funnel5: funnel@7b70000 {
2009 compatible = "arm,cor 1897 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2010 reg = <0x07b70000 0x1 1898 reg = <0x07b70000 0x1000>;
2011 status = "disabled"; 1899 status = "disabled";
2012 1900
2013 clocks = <&rpmcc RPM_ 1901 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2014 clock-names = "apb_pc 1902 clock-names = "apb_pclk", "atclk";
2015 1903
2016 out-ports { 1904 out-ports {
2017 port { 1905 port {
2018 apss_ 1906 apss_merge_funnel_out: endpoint {
2019 1907 remote-endpoint =
2020 1908 <&funnel1_in6>;
2021 }; 1909 };
2022 }; 1910 };
2023 }; 1911 };
2024 1912
2025 in-ports { 1913 in-ports {
2026 port { 1914 port {
2027 apss_ 1915 apss_merge_funnel_in: endpoint {
2028 1916 remote-endpoint =
2029 1917 <&apss_funnel_out>;
2030 }; 1918 };
2031 }; 1919 };
2032 }; 1920 };
2033 }; 1921 };
2034 1922
2035 etm5: etm@7c40000 { 1923 etm5: etm@7c40000 {
2036 compatible = "arm,cor 1924 compatible = "arm,coresight-etm4x", "arm,primecell";
2037 reg = <0x07c40000 0x1 1925 reg = <0x07c40000 0x1000>;
2038 status = "disabled"; 1926 status = "disabled";
2039 1927
2040 clocks = <&rpmcc RPM_ 1928 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2041 clock-names = "apb_pc 1929 clock-names = "apb_pclk", "atclk";
2042 1930
2043 cpu = <&CPU4>; 1931 cpu = <&CPU4>;
2044 1932
2045 out-ports { !! 1933 port{
2046 port { !! 1934 etm4_out: endpoint {
2047 etm4_ !! 1935 remote-endpoint = <&apss_funnel_in4>;
2048 <<
2049 }; <<
2050 }; 1936 };
2051 }; 1937 };
2052 }; 1938 };
2053 1939
2054 etm6: etm@7d40000 { 1940 etm6: etm@7d40000 {
2055 compatible = "arm,cor 1941 compatible = "arm,coresight-etm4x", "arm,primecell";
2056 reg = <0x07d40000 0x1 1942 reg = <0x07d40000 0x1000>;
2057 status = "disabled"; 1943 status = "disabled";
2058 1944
2059 clocks = <&rpmcc RPM_ 1945 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2060 clock-names = "apb_pc 1946 clock-names = "apb_pclk", "atclk";
2061 1947
2062 cpu = <&CPU5>; 1948 cpu = <&CPU5>;
2063 1949
2064 out-ports { !! 1950 port{
2065 port { !! 1951 etm5_out: endpoint {
2066 etm5_ !! 1952 remote-endpoint = <&apss_funnel_in5>;
2067 <<
2068 }; <<
2069 }; 1953 };
2070 }; 1954 };
2071 }; 1955 };
2072 1956
2073 etm7: etm@7e40000 { 1957 etm7: etm@7e40000 {
2074 compatible = "arm,cor 1958 compatible = "arm,coresight-etm4x", "arm,primecell";
2075 reg = <0x07e40000 0x1 1959 reg = <0x07e40000 0x1000>;
2076 status = "disabled"; 1960 status = "disabled";
2077 1961
2078 clocks = <&rpmcc RPM_ 1962 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2079 clock-names = "apb_pc 1963 clock-names = "apb_pclk", "atclk";
2080 1964
2081 cpu = <&CPU6>; 1965 cpu = <&CPU6>;
2082 1966
2083 out-ports { !! 1967 port{
2084 port { !! 1968 etm6_out: endpoint {
2085 etm6_ !! 1969 remote-endpoint = <&apss_funnel_in6>;
2086 <<
2087 }; <<
2088 }; 1970 };
2089 }; 1971 };
2090 }; 1972 };
2091 1973
2092 etm8: etm@7f40000 { 1974 etm8: etm@7f40000 {
2093 compatible = "arm,cor 1975 compatible = "arm,coresight-etm4x", "arm,primecell";
2094 reg = <0x07f40000 0x1 1976 reg = <0x07f40000 0x1000>;
2095 status = "disabled"; 1977 status = "disabled";
2096 1978
2097 clocks = <&rpmcc RPM_ 1979 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2098 clock-names = "apb_pc 1980 clock-names = "apb_pclk", "atclk";
2099 1981
2100 cpu = <&CPU7>; 1982 cpu = <&CPU7>;
2101 1983
2102 out-ports { !! 1984 port{
2103 port { !! 1985 etm7_out: endpoint {
2104 etm7_ !! 1986 remote-endpoint = <&apss_funnel_in7>;
2105 <<
2106 }; <<
2107 }; 1987 };
2108 }; 1988 };
2109 }; 1989 };
2110 1990
2111 sram@290000 { 1991 sram@290000 {
2112 compatible = "qcom,rp 1992 compatible = "qcom,rpm-stats";
2113 reg = <0x00290000 0x1 1993 reg = <0x00290000 0x10000>;
2114 }; 1994 };
2115 1995
2116 spmi_bus: spmi@800f000 { 1996 spmi_bus: spmi@800f000 {
2117 compatible = "qcom,sp 1997 compatible = "qcom,spmi-pmic-arb";
2118 reg = <0x0800f000 0x1 !! 1998 reg = <0x0800f000 0x1000>,
2119 <0x08400000 0x1 !! 1999 <0x08400000 0x1000000>,
2120 <0x09400000 0x1 !! 2000 <0x09400000 0x1000000>,
2121 <0x0a400000 0x2 !! 2001 <0x0a400000 0x220000>,
2122 <0x0800a000 0x3 !! 2002 <0x0800a000 0x3000>;
2123 reg-names = "core", " 2003 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
2124 interrupt-names = "pe 2004 interrupt-names = "periph_irq";
2125 interrupts = <GIC_SPI 2005 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
2126 qcom,ee = <0>; 2006 qcom,ee = <0>;
2127 qcom,channel = <0>; 2007 qcom,channel = <0>;
2128 #address-cells = <2>; 2008 #address-cells = <2>;
2129 #size-cells = <0>; 2009 #size-cells = <0>;
2130 interrupt-controller; 2010 interrupt-controller;
2131 #interrupt-cells = <4 2011 #interrupt-cells = <4>;
>> 2012 cell-index = <0>;
2132 }; 2013 };
2133 2014
2134 usb3: usb@a8f8800 { 2015 usb3: usb@a8f8800 {
2135 compatible = "qcom,ms 2016 compatible = "qcom,msm8998-dwc3", "qcom,dwc3";
2136 reg = <0x0a8f8800 0x4 2017 reg = <0x0a8f8800 0x400>;
2137 status = "disabled"; 2018 status = "disabled";
2138 #address-cells = <1>; 2019 #address-cells = <1>;
2139 #size-cells = <1>; 2020 #size-cells = <1>;
2140 ranges; 2021 ranges;
2141 2022
2142 clocks = <&gcc GCC_CF 2023 clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>,
2143 <&gcc GCC_US 2024 <&gcc GCC_USB30_MASTER_CLK>,
2144 <&gcc GCC_AG 2025 <&gcc GCC_AGGRE1_USB3_AXI_CLK>,
2145 <&gcc GCC_US 2026 <&gcc GCC_USB30_SLEEP_CLK>,
2146 <&gcc GCC_US 2027 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
2147 clock-names = "cfg_no 2028 clock-names = "cfg_noc",
2148 "core", 2029 "core",
2149 "iface" 2030 "iface",
2150 "sleep" 2031 "sleep",
2151 "mock_u 2032 "mock_utmi";
2152 2033
2153 assigned-clocks = <&g 2034 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
2154 <&g 2035 <&gcc GCC_USB30_MASTER_CLK>;
2155 assigned-clock-rates 2036 assigned-clock-rates = <19200000>, <120000000>;
2156 2037
2157 interrupts = <GIC_SPI !! 2038 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
2158 <GIC_SPI <<
2159 <GIC_SPI 2039 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
2160 interrupt-names = "pw !! 2040 interrupt-names = "hs_phy_irq", "ss_phy_irq";
2161 "qu <<
2162 "ss <<
2163 2041
2164 power-domains = <&gcc 2042 power-domains = <&gcc USB_30_GDSC>;
2165 2043
2166 resets = <&gcc GCC_US 2044 resets = <&gcc GCC_USB_30_BCR>;
2167 2045
2168 usb3_dwc3: usb@a80000 2046 usb3_dwc3: usb@a800000 {
2169 compatible = 2047 compatible = "snps,dwc3";
2170 reg = <0x0a80 2048 reg = <0x0a800000 0xcd00>;
2171 interrupts = 2049 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
2172 snps,dis_u2_s 2050 snps,dis_u2_susphy_quirk;
2173 snps,dis_enbl 2051 snps,dis_enblslpm_quirk;
2174 snps,parkmode !! 2052 phys = <&qusb2phy>, <&usb1_ssphy>;
2175 phys = <&qusb <<
2176 phy-names = " 2053 phy-names = "usb2-phy", "usb3-phy";
2177 snps,has-lpm- 2054 snps,has-lpm-erratum;
2178 snps,hird-thr 2055 snps,hird-threshold = /bits/ 8 <0x10>;
2179 }; 2056 };
2180 }; 2057 };
2181 2058
2182 usb3phy: phy@c010000 { 2059 usb3phy: phy@c010000 {
2183 compatible = "qcom,ms 2060 compatible = "qcom,msm8998-qmp-usb3-phy";
2184 reg = <0x0c010000 0x1 !! 2061 reg = <0x0c010000 0x18c>;
>> 2062 status = "disabled";
>> 2063 #address-cells = <1>;
>> 2064 #size-cells = <1>;
>> 2065 ranges;
2185 2066
2186 clocks = <&gcc GCC_US 2067 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
2187 <&gcc GCC_US <<
2188 <&gcc GCC_US 2068 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2189 <&gcc GCC_US !! 2069 <&gcc GCC_USB3_CLKREF_CLK>;
2190 clock-names = "aux", !! 2070 clock-names = "aux", "cfg_ahb", "ref";
2191 "ref", <<
2192 "cfg_ah <<
2193 "pipe"; <<
2194 clock-output-names = <<
2195 #clock-cells = <0>; <<
2196 #phy-cells = <0>; <<
2197 2071
2198 resets = <&gcc GCC_US 2072 resets = <&gcc GCC_USB3_PHY_BCR>,
2199 <&gcc GCC_US 2073 <&gcc GCC_USB3PHY_PHY_BCR>;
2200 reset-names = "phy", !! 2074 reset-names = "phy", "common";
2201 "phy_ph <<
2202 <<
2203 qcom,tcsr-reg = <&tcs <<
2204 2075
2205 status = "disabled"; !! 2076 usb1_ssphy: phy@c010200 {
>> 2077 reg = <0xc010200 0x128>,
>> 2078 <0xc010400 0x200>,
>> 2079 <0xc010c00 0x20c>,
>> 2080 <0xc010600 0x128>,
>> 2081 <0xc010800 0x200>;
>> 2082 #phy-cells = <0>;
>> 2083 #clock-cells = <1>;
>> 2084 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
>> 2085 clock-names = "pipe0";
>> 2086 clock-output-names = "usb3_phy_pipe_clk_src";
>> 2087 };
2206 }; 2088 };
2207 2089
2208 qusb2phy: phy@c012000 { 2090 qusb2phy: phy@c012000 {
2209 compatible = "qcom,ms 2091 compatible = "qcom,msm8998-qusb2-phy";
2210 reg = <0x0c012000 0x2 2092 reg = <0x0c012000 0x2a8>;
2211 status = "disabled"; 2093 status = "disabled";
2212 #phy-cells = <0>; 2094 #phy-cells = <0>;
2213 2095
2214 clocks = <&gcc GCC_US 2096 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2215 <&gcc GCC_RX 2097 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
2216 clock-names = "cfg_ah 2098 clock-names = "cfg_ahb", "ref";
2217 2099
2218 resets = <&gcc GCC_QU 2100 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2219 2101
2220 nvmem-cells = <&qusb2 2102 nvmem-cells = <&qusb2_hstx_trim>;
2221 }; 2103 };
2222 2104
2223 sdhc2: mmc@c0a4900 { !! 2105 sdhc2: sdhci@c0a4900 {
2224 compatible = "qcom,ms !! 2106 compatible = "qcom,sdhci-msm-v4";
2225 reg = <0x0c0a4900 0x3 2107 reg = <0x0c0a4900 0x314>, <0x0c0a4000 0x800>;
2226 reg-names = "hc", "co !! 2108 reg-names = "hc_mem", "core_mem";
2227 2109
2228 interrupts = <GIC_SPI 2110 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
2229 <GIC_SPI 2111 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
2230 interrupt-names = "hc 2112 interrupt-names = "hc_irq", "pwr_irq";
2231 2113
2232 clock-names = "iface" 2114 clock-names = "iface", "core", "xo";
2233 clocks = <&gcc GCC_SD 2115 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2234 <&gcc GCC_SD 2116 <&gcc GCC_SDCC2_APPS_CLK>,
2235 <&rpmcc RPM_ !! 2117 <&xo>;
2236 bus-width = <4>; 2118 bus-width = <4>;
2237 status = "disabled"; 2119 status = "disabled";
2238 }; 2120 };
2239 2121
2240 blsp1_dma: dma-controller@c14 2122 blsp1_dma: dma-controller@c144000 {
2241 compatible = "qcom,ba 2123 compatible = "qcom,bam-v1.7.0";
2242 reg = <0x0c144000 0x2 2124 reg = <0x0c144000 0x25000>;
2243 interrupts = <GIC_SPI 2125 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
2244 clocks = <&gcc GCC_BL 2126 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
2245 clock-names = "bam_cl 2127 clock-names = "bam_clk";
2246 #dma-cells = <1>; 2128 #dma-cells = <1>;
2247 qcom,ee = <0>; 2129 qcom,ee = <0>;
2248 qcom,controlled-remot 2130 qcom,controlled-remotely;
2249 num-channels = <18>; 2131 num-channels = <18>;
2250 qcom,num-ees = <4>; 2132 qcom,num-ees = <4>;
2251 }; 2133 };
2252 2134
2253 blsp1_uart3: serial@c171000 { 2135 blsp1_uart3: serial@c171000 {
2254 compatible = "qcom,ms 2136 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2255 reg = <0x0c171000 0x1 2137 reg = <0x0c171000 0x1000>;
2256 interrupts = <GIC_SPI 2138 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
2257 clocks = <&gcc GCC_BL 2139 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
2258 <&gcc GCC_BL 2140 <&gcc GCC_BLSP1_AHB_CLK>;
2259 clock-names = "core", 2141 clock-names = "core", "iface";
2260 dmas = <&blsp1_dma 4> 2142 dmas = <&blsp1_dma 4>, <&blsp1_dma 5>;
2261 dma-names = "tx", "rx 2143 dma-names = "tx", "rx";
2262 pinctrl-names = "defa 2144 pinctrl-names = "default";
2263 pinctrl-0 = <&blsp1_u 2145 pinctrl-0 = <&blsp1_uart3_on>;
2264 status = "disabled"; 2146 status = "disabled";
2265 }; 2147 };
2266 2148
2267 blsp1_i2c1: i2c@c175000 { 2149 blsp1_i2c1: i2c@c175000 {
2268 compatible = "qcom,i2 2150 compatible = "qcom,i2c-qup-v2.2.1";
2269 reg = <0x0c175000 0x6 2151 reg = <0x0c175000 0x600>;
2270 interrupts = <GIC_SPI 2152 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
2271 2153
2272 clocks = <&gcc GCC_BL 2154 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
2273 <&gcc GCC_BL 2155 <&gcc GCC_BLSP1_AHB_CLK>;
2274 clock-names = "core", 2156 clock-names = "core", "iface";
2275 dmas = <&blsp1_dma 6> 2157 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>;
2276 dma-names = "tx", "rx 2158 dma-names = "tx", "rx";
2277 pinctrl-names = "defa 2159 pinctrl-names = "default", "sleep";
2278 pinctrl-0 = <&blsp1_i 2160 pinctrl-0 = <&blsp1_i2c1_default>;
2279 pinctrl-1 = <&blsp1_i 2161 pinctrl-1 = <&blsp1_i2c1_sleep>;
2280 clock-frequency = <40 2162 clock-frequency = <400000>;
2281 2163
2282 status = "disabled"; 2164 status = "disabled";
2283 #address-cells = <1>; 2165 #address-cells = <1>;
2284 #size-cells = <0>; 2166 #size-cells = <0>;
2285 }; 2167 };
2286 2168
2287 blsp1_i2c2: i2c@c176000 { 2169 blsp1_i2c2: i2c@c176000 {
2288 compatible = "qcom,i2 2170 compatible = "qcom,i2c-qup-v2.2.1";
2289 reg = <0x0c176000 0x6 2171 reg = <0x0c176000 0x600>;
2290 interrupts = <GIC_SPI 2172 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
2291 2173
2292 clocks = <&gcc GCC_BL 2174 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
2293 <&gcc GCC_BL 2175 <&gcc GCC_BLSP1_AHB_CLK>;
2294 clock-names = "core", 2176 clock-names = "core", "iface";
2295 dmas = <&blsp1_dma 8> 2177 dmas = <&blsp1_dma 8>, <&blsp1_dma 9>;
2296 dma-names = "tx", "rx 2178 dma-names = "tx", "rx";
2297 pinctrl-names = "defa 2179 pinctrl-names = "default", "sleep";
2298 pinctrl-0 = <&blsp1_i 2180 pinctrl-0 = <&blsp1_i2c2_default>;
2299 pinctrl-1 = <&blsp1_i 2181 pinctrl-1 = <&blsp1_i2c2_sleep>;
2300 clock-frequency = <40 2182 clock-frequency = <400000>;
2301 2183
2302 status = "disabled"; 2184 status = "disabled";
2303 #address-cells = <1>; 2185 #address-cells = <1>;
2304 #size-cells = <0>; 2186 #size-cells = <0>;
2305 }; 2187 };
2306 2188
2307 blsp1_i2c3: i2c@c177000 { 2189 blsp1_i2c3: i2c@c177000 {
2308 compatible = "qcom,i2 2190 compatible = "qcom,i2c-qup-v2.2.1";
2309 reg = <0x0c177000 0x6 2191 reg = <0x0c177000 0x600>;
2310 interrupts = <GIC_SPI 2192 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
2311 2193
2312 clocks = <&gcc GCC_BL 2194 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
2313 <&gcc GCC_BL 2195 <&gcc GCC_BLSP1_AHB_CLK>;
2314 clock-names = "core", 2196 clock-names = "core", "iface";
2315 dmas = <&blsp1_dma 10 2197 dmas = <&blsp1_dma 10>, <&blsp1_dma 11>;
2316 dma-names = "tx", "rx 2198 dma-names = "tx", "rx";
2317 pinctrl-names = "defa 2199 pinctrl-names = "default", "sleep";
2318 pinctrl-0 = <&blsp1_i 2200 pinctrl-0 = <&blsp1_i2c3_default>;
2319 pinctrl-1 = <&blsp1_i 2201 pinctrl-1 = <&blsp1_i2c3_sleep>;
2320 clock-frequency = <40 2202 clock-frequency = <400000>;
2321 2203
2322 status = "disabled"; 2204 status = "disabled";
2323 #address-cells = <1>; 2205 #address-cells = <1>;
2324 #size-cells = <0>; 2206 #size-cells = <0>;
2325 }; 2207 };
2326 2208
2327 blsp1_i2c4: i2c@c178000 { 2209 blsp1_i2c4: i2c@c178000 {
2328 compatible = "qcom,i2 2210 compatible = "qcom,i2c-qup-v2.2.1";
2329 reg = <0x0c178000 0x6 2211 reg = <0x0c178000 0x600>;
2330 interrupts = <GIC_SPI 2212 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
2331 2213
2332 clocks = <&gcc GCC_BL 2214 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
2333 <&gcc GCC_BL 2215 <&gcc GCC_BLSP1_AHB_CLK>;
2334 clock-names = "core", 2216 clock-names = "core", "iface";
2335 dmas = <&blsp1_dma 12 2217 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
2336 dma-names = "tx", "rx 2218 dma-names = "tx", "rx";
2337 pinctrl-names = "defa 2219 pinctrl-names = "default", "sleep";
2338 pinctrl-0 = <&blsp1_i 2220 pinctrl-0 = <&blsp1_i2c4_default>;
2339 pinctrl-1 = <&blsp1_i 2221 pinctrl-1 = <&blsp1_i2c4_sleep>;
2340 clock-frequency = <40 2222 clock-frequency = <400000>;
2341 2223
2342 status = "disabled"; 2224 status = "disabled";
2343 #address-cells = <1>; 2225 #address-cells = <1>;
2344 #size-cells = <0>; 2226 #size-cells = <0>;
2345 }; 2227 };
2346 2228
2347 blsp1_i2c5: i2c@c179000 { 2229 blsp1_i2c5: i2c@c179000 {
2348 compatible = "qcom,i2 2230 compatible = "qcom,i2c-qup-v2.2.1";
2349 reg = <0x0c179000 0x6 2231 reg = <0x0c179000 0x600>;
2350 interrupts = <GIC_SPI 2232 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
2351 2233
2352 clocks = <&gcc GCC_BL 2234 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
2353 <&gcc GCC_BL 2235 <&gcc GCC_BLSP1_AHB_CLK>;
2354 clock-names = "core", 2236 clock-names = "core", "iface";
2355 dmas = <&blsp1_dma 14 2237 dmas = <&blsp1_dma 14>, <&blsp1_dma 15>;
2356 dma-names = "tx", "rx 2238 dma-names = "tx", "rx";
2357 pinctrl-names = "defa 2239 pinctrl-names = "default", "sleep";
2358 pinctrl-0 = <&blsp1_i 2240 pinctrl-0 = <&blsp1_i2c5_default>;
2359 pinctrl-1 = <&blsp1_i 2241 pinctrl-1 = <&blsp1_i2c5_sleep>;
2360 clock-frequency = <40 2242 clock-frequency = <400000>;
2361 2243
2362 status = "disabled"; 2244 status = "disabled";
2363 #address-cells = <1>; 2245 #address-cells = <1>;
2364 #size-cells = <0>; 2246 #size-cells = <0>;
2365 }; 2247 };
2366 2248
2367 blsp1_i2c6: i2c@c17a000 { 2249 blsp1_i2c6: i2c@c17a000 {
2368 compatible = "qcom,i2 2250 compatible = "qcom,i2c-qup-v2.2.1";
2369 reg = <0x0c17a000 0x6 2251 reg = <0x0c17a000 0x600>;
2370 interrupts = <GIC_SPI 2252 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
2371 2253
2372 clocks = <&gcc GCC_BL 2254 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
2373 <&gcc GCC_BL 2255 <&gcc GCC_BLSP1_AHB_CLK>;
2374 clock-names = "core", 2256 clock-names = "core", "iface";
2375 dmas = <&blsp1_dma 16 2257 dmas = <&blsp1_dma 16>, <&blsp1_dma 17>;
2376 dma-names = "tx", "rx 2258 dma-names = "tx", "rx";
2377 pinctrl-names = "defa 2259 pinctrl-names = "default", "sleep";
2378 pinctrl-0 = <&blsp1_i 2260 pinctrl-0 = <&blsp1_i2c6_default>;
2379 pinctrl-1 = <&blsp1_i 2261 pinctrl-1 = <&blsp1_i2c6_sleep>;
2380 clock-frequency = <40 2262 clock-frequency = <400000>;
2381 2263
2382 status = "disabled"; 2264 status = "disabled";
2383 #address-cells = <1>; 2265 #address-cells = <1>;
2384 #size-cells = <0>; 2266 #size-cells = <0>;
2385 }; 2267 };
2386 2268
2387 blsp1_spi1: spi@c175000 { <<
2388 compatible = "qcom,sp <<
2389 reg = <0x0c175000 0x6 <<
2390 interrupts = <GIC_SPI <<
2391 <<
2392 clocks = <&gcc GCC_BL <<
2393 <&gcc GCC_BL <<
2394 clock-names = "core", <<
2395 dmas = <&blsp1_dma 6> <<
2396 dma-names = "tx", "rx <<
2397 pinctrl-names = "defa <<
2398 pinctrl-0 = <&blsp1_s <<
2399 <<
2400 status = "disabled"; <<
2401 #address-cells = <1>; <<
2402 #size-cells = <0>; <<
2403 }; <<
2404 <<
2405 blsp1_spi2: spi@c176000 { <<
2406 compatible = "qcom,sp <<
2407 reg = <0x0c176000 0x6 <<
2408 interrupts = <GIC_SPI <<
2409 <<
2410 clocks = <&gcc GCC_BL <<
2411 <&gcc GCC_BL <<
2412 clock-names = "core", <<
2413 dmas = <&blsp1_dma 8> <<
2414 dma-names = "tx", "rx <<
2415 pinctrl-names = "defa <<
2416 pinctrl-0 = <&blsp1_s <<
2417 <<
2418 status = "disabled"; <<
2419 #address-cells = <1>; <<
2420 #size-cells = <0>; <<
2421 }; <<
2422 <<
2423 blsp1_spi3: spi@c177000 { <<
2424 compatible = "qcom,sp <<
2425 reg = <0x0c177000 0x6 <<
2426 interrupts = <GIC_SPI <<
2427 <<
2428 clocks = <&gcc GCC_BL <<
2429 <&gcc GCC_BL <<
2430 clock-names = "core", <<
2431 dmas = <&blsp1_dma 10 <<
2432 dma-names = "tx", "rx <<
2433 pinctrl-names = "defa <<
2434 pinctrl-0 = <&blsp1_s <<
2435 <<
2436 status = "disabled"; <<
2437 #address-cells = <1>; <<
2438 #size-cells = <0>; <<
2439 }; <<
2440 <<
2441 blsp1_spi4: spi@c178000 { <<
2442 compatible = "qcom,sp <<
2443 reg = <0x0c178000 0x6 <<
2444 interrupts = <GIC_SPI <<
2445 <<
2446 clocks = <&gcc GCC_BL <<
2447 <&gcc GCC_BL <<
2448 clock-names = "core", <<
2449 dmas = <&blsp1_dma 12 <<
2450 dma-names = "tx", "rx <<
2451 pinctrl-names = "defa <<
2452 pinctrl-0 = <&blsp1_s <<
2453 <<
2454 status = "disabled"; <<
2455 #address-cells = <1>; <<
2456 #size-cells = <0>; <<
2457 }; <<
2458 <<
2459 blsp1_spi5: spi@c179000 { <<
2460 compatible = "qcom,sp <<
2461 reg = <0x0c179000 0x6 <<
2462 interrupts = <GIC_SPI <<
2463 <<
2464 clocks = <&gcc GCC_BL <<
2465 <&gcc GCC_BL <<
2466 clock-names = "core", <<
2467 dmas = <&blsp1_dma 14 <<
2468 dma-names = "tx", "rx <<
2469 pinctrl-names = "defa <<
2470 pinctrl-0 = <&blsp1_s <<
2471 <<
2472 status = "disabled"; <<
2473 #address-cells = <1>; <<
2474 #size-cells = <0>; <<
2475 }; <<
2476 <<
2477 blsp1_spi6: spi@c17a000 { <<
2478 compatible = "qcom,sp <<
2479 reg = <0x0c17a000 0x6 <<
2480 interrupts = <GIC_SPI <<
2481 <<
2482 clocks = <&gcc GCC_BL <<
2483 <&gcc GCC_BL <<
2484 clock-names = "core", <<
2485 dmas = <&blsp1_dma 16 <<
2486 dma-names = "tx", "rx <<
2487 pinctrl-names = "defa <<
2488 pinctrl-0 = <&blsp1_s <<
2489 <<
2490 status = "disabled"; <<
2491 #address-cells = <1>; <<
2492 #size-cells = <0>; <<
2493 }; <<
2494 <<
2495 blsp2_dma: dma-controller@c18 2269 blsp2_dma: dma-controller@c184000 {
2496 compatible = "qcom,ba 2270 compatible = "qcom,bam-v1.7.0";
2497 reg = <0x0c184000 0x2 2271 reg = <0x0c184000 0x25000>;
2498 interrupts = <GIC_SPI 2272 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
2499 clocks = <&gcc GCC_BL 2273 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
2500 clock-names = "bam_cl 2274 clock-names = "bam_clk";
2501 #dma-cells = <1>; 2275 #dma-cells = <1>;
2502 qcom,ee = <0>; 2276 qcom,ee = <0>;
2503 qcom,controlled-remot 2277 qcom,controlled-remotely;
2504 num-channels = <18>; 2278 num-channels = <18>;
2505 qcom,num-ees = <4>; 2279 qcom,num-ees = <4>;
2506 }; 2280 };
2507 2281
2508 blsp2_uart1: serial@c1b0000 { 2282 blsp2_uart1: serial@c1b0000 {
2509 compatible = "qcom,ms 2283 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2510 reg = <0x0c1b0000 0x1 2284 reg = <0x0c1b0000 0x1000>;
2511 interrupts = <GIC_SPI 2285 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
2512 clocks = <&gcc GCC_BL 2286 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
2513 <&gcc GCC_BL 2287 <&gcc GCC_BLSP2_AHB_CLK>;
2514 clock-names = "core", 2288 clock-names = "core", "iface";
2515 status = "disabled"; 2289 status = "disabled";
2516 }; 2290 };
2517 2291
2518 blsp2_i2c1: i2c@c1b5000 { 2292 blsp2_i2c1: i2c@c1b5000 {
2519 compatible = "qcom,i2 2293 compatible = "qcom,i2c-qup-v2.2.1";
2520 reg = <0x0c1b5000 0x6 2294 reg = <0x0c1b5000 0x600>;
2521 interrupts = <GIC_SPI 2295 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
2522 2296
2523 clocks = <&gcc GCC_BL 2297 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
2524 <&gcc GCC_BL 2298 <&gcc GCC_BLSP2_AHB_CLK>;
2525 clock-names = "core", 2299 clock-names = "core", "iface";
2526 dmas = <&blsp2_dma 6> 2300 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>;
2527 dma-names = "tx", "rx 2301 dma-names = "tx", "rx";
2528 pinctrl-names = "defa 2302 pinctrl-names = "default", "sleep";
2529 pinctrl-0 = <&blsp2_i 2303 pinctrl-0 = <&blsp2_i2c1_default>;
2530 pinctrl-1 = <&blsp2_i 2304 pinctrl-1 = <&blsp2_i2c1_sleep>;
2531 clock-frequency = <40 2305 clock-frequency = <400000>;
2532 2306
2533 status = "disabled"; 2307 status = "disabled";
2534 #address-cells = <1>; 2308 #address-cells = <1>;
2535 #size-cells = <0>; 2309 #size-cells = <0>;
2536 }; 2310 };
2537 2311
2538 blsp2_i2c2: i2c@c1b6000 { 2312 blsp2_i2c2: i2c@c1b6000 {
2539 compatible = "qcom,i2 2313 compatible = "qcom,i2c-qup-v2.2.1";
2540 reg = <0x0c1b6000 0x6 2314 reg = <0x0c1b6000 0x600>;
2541 interrupts = <GIC_SPI 2315 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
2542 2316
2543 clocks = <&gcc GCC_BL 2317 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
2544 <&gcc GCC_BL 2318 <&gcc GCC_BLSP2_AHB_CLK>;
2545 clock-names = "core", 2319 clock-names = "core", "iface";
2546 dmas = <&blsp2_dma 8> 2320 dmas = <&blsp2_dma 8>, <&blsp2_dma 9>;
2547 dma-names = "tx", "rx 2321 dma-names = "tx", "rx";
2548 pinctrl-names = "defa 2322 pinctrl-names = "default", "sleep";
2549 pinctrl-0 = <&blsp2_i 2323 pinctrl-0 = <&blsp2_i2c2_default>;
2550 pinctrl-1 = <&blsp2_i 2324 pinctrl-1 = <&blsp2_i2c2_sleep>;
2551 clock-frequency = <40 2325 clock-frequency = <400000>;
2552 2326
2553 status = "disabled"; 2327 status = "disabled";
2554 #address-cells = <1>; 2328 #address-cells = <1>;
2555 #size-cells = <0>; 2329 #size-cells = <0>;
2556 }; 2330 };
2557 2331
2558 blsp2_i2c3: i2c@c1b7000 { 2332 blsp2_i2c3: i2c@c1b7000 {
2559 compatible = "qcom,i2 2333 compatible = "qcom,i2c-qup-v2.2.1";
2560 reg = <0x0c1b7000 0x6 2334 reg = <0x0c1b7000 0x600>;
2561 interrupts = <GIC_SPI 2335 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
2562 2336
2563 clocks = <&gcc GCC_BL 2337 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
2564 <&gcc GCC_BL 2338 <&gcc GCC_BLSP2_AHB_CLK>;
2565 clock-names = "core", 2339 clock-names = "core", "iface";
2566 dmas = <&blsp2_dma 10 2340 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>;
2567 dma-names = "tx", "rx 2341 dma-names = "tx", "rx";
2568 pinctrl-names = "defa 2342 pinctrl-names = "default", "sleep";
2569 pinctrl-0 = <&blsp2_i 2343 pinctrl-0 = <&blsp2_i2c3_default>;
2570 pinctrl-1 = <&blsp2_i 2344 pinctrl-1 = <&blsp2_i2c3_sleep>;
2571 clock-frequency = <40 2345 clock-frequency = <400000>;
2572 2346
2573 status = "disabled"; 2347 status = "disabled";
2574 #address-cells = <1>; 2348 #address-cells = <1>;
2575 #size-cells = <0>; 2349 #size-cells = <0>;
2576 }; 2350 };
2577 2351
2578 blsp2_i2c4: i2c@c1b8000 { 2352 blsp2_i2c4: i2c@c1b8000 {
2579 compatible = "qcom,i2 2353 compatible = "qcom,i2c-qup-v2.2.1";
2580 reg = <0x0c1b8000 0x6 2354 reg = <0x0c1b8000 0x600>;
2581 interrupts = <GIC_SPI 2355 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
2582 2356
2583 clocks = <&gcc GCC_BL 2357 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>,
2584 <&gcc GCC_BL 2358 <&gcc GCC_BLSP2_AHB_CLK>;
2585 clock-names = "core", 2359 clock-names = "core", "iface";
2586 dmas = <&blsp2_dma 12 2360 dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
2587 dma-names = "tx", "rx 2361 dma-names = "tx", "rx";
2588 pinctrl-names = "defa 2362 pinctrl-names = "default", "sleep";
2589 pinctrl-0 = <&blsp2_i 2363 pinctrl-0 = <&blsp2_i2c4_default>;
2590 pinctrl-1 = <&blsp2_i 2364 pinctrl-1 = <&blsp2_i2c4_sleep>;
2591 clock-frequency = <40 2365 clock-frequency = <400000>;
2592 2366
2593 status = "disabled"; 2367 status = "disabled";
2594 #address-cells = <1>; 2368 #address-cells = <1>;
2595 #size-cells = <0>; 2369 #size-cells = <0>;
2596 }; 2370 };
2597 2371
2598 blsp2_i2c5: i2c@c1b9000 { 2372 blsp2_i2c5: i2c@c1b9000 {
2599 compatible = "qcom,i2 2373 compatible = "qcom,i2c-qup-v2.2.1";
2600 reg = <0x0c1b9000 0x6 2374 reg = <0x0c1b9000 0x600>;
2601 interrupts = <GIC_SPI 2375 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
2602 2376
2603 clocks = <&gcc GCC_BL 2377 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,
2604 <&gcc GCC_BL 2378 <&gcc GCC_BLSP2_AHB_CLK>;
2605 clock-names = "core", 2379 clock-names = "core", "iface";
2606 dmas = <&blsp2_dma 14 2380 dmas = <&blsp2_dma 14>, <&blsp2_dma 15>;
2607 dma-names = "tx", "rx 2381 dma-names = "tx", "rx";
2608 pinctrl-names = "defa 2382 pinctrl-names = "default", "sleep";
2609 pinctrl-0 = <&blsp2_i 2383 pinctrl-0 = <&blsp2_i2c5_default>;
2610 pinctrl-1 = <&blsp2_i 2384 pinctrl-1 = <&blsp2_i2c5_sleep>;
2611 clock-frequency = <40 2385 clock-frequency = <400000>;
2612 2386
2613 status = "disabled"; 2387 status = "disabled";
2614 #address-cells = <1>; 2388 #address-cells = <1>;
2615 #size-cells = <0>; 2389 #size-cells = <0>;
2616 }; 2390 };
2617 2391
2618 blsp2_i2c6: i2c@c1ba000 { 2392 blsp2_i2c6: i2c@c1ba000 {
2619 compatible = "qcom,i2 2393 compatible = "qcom,i2c-qup-v2.2.1";
2620 reg = <0x0c1ba000 0x6 2394 reg = <0x0c1ba000 0x600>;
2621 interrupts = <GIC_SPI 2395 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
2622 2396
2623 clocks = <&gcc GCC_BL 2397 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>,
2624 <&gcc GCC_BL 2398 <&gcc GCC_BLSP2_AHB_CLK>;
2625 clock-names = "core", 2399 clock-names = "core", "iface";
2626 dmas = <&blsp2_dma 16 2400 dmas = <&blsp2_dma 16>, <&blsp2_dma 17>;
2627 dma-names = "tx", "rx 2401 dma-names = "tx", "rx";
2628 pinctrl-names = "defa 2402 pinctrl-names = "default", "sleep";
2629 pinctrl-0 = <&blsp2_i 2403 pinctrl-0 = <&blsp2_i2c6_default>;
2630 pinctrl-1 = <&blsp2_i 2404 pinctrl-1 = <&blsp2_i2c6_sleep>;
2631 clock-frequency = <40 2405 clock-frequency = <400000>;
2632 2406
2633 status = "disabled"; 2407 status = "disabled";
2634 #address-cells = <1>; 2408 #address-cells = <1>;
2635 #size-cells = <0>; 2409 #size-cells = <0>;
2636 }; 2410 };
2637 2411
2638 blsp2_spi1: spi@c1b5000 { <<
2639 compatible = "qcom,sp <<
2640 reg = <0x0c1b5000 0x6 <<
2641 interrupts = <GIC_SPI <<
2642 <<
2643 clocks = <&gcc GCC_BL <<
2644 <&gcc GCC_BL <<
2645 clock-names = "core", <<
2646 dmas = <&blsp2_dma 6> <<
2647 dma-names = "tx", "rx <<
2648 pinctrl-names = "defa <<
2649 pinctrl-0 = <&blsp2_s <<
2650 <<
2651 status = "disabled"; <<
2652 #address-cells = <1>; <<
2653 #size-cells = <0>; <<
2654 }; <<
2655 <<
2656 blsp2_spi2: spi@c1b6000 { <<
2657 compatible = "qcom,sp <<
2658 reg = <0x0c1b6000 0x6 <<
2659 interrupts = <GIC_SPI <<
2660 <<
2661 clocks = <&gcc GCC_BL <<
2662 <&gcc GCC_BL <<
2663 clock-names = "core", <<
2664 dmas = <&blsp2_dma 8> <<
2665 dma-names = "tx", "rx <<
2666 pinctrl-names = "defa <<
2667 pinctrl-0 = <&blsp2_s <<
2668 <<
2669 status = "disabled"; <<
2670 #address-cells = <1>; <<
2671 #size-cells = <0>; <<
2672 }; <<
2673 <<
2674 blsp2_spi3: spi@c1b7000 { <<
2675 compatible = "qcom,sp <<
2676 reg = <0x0c1b7000 0x6 <<
2677 interrupts = <GIC_SPI <<
2678 <<
2679 clocks = <&gcc GCC_BL <<
2680 <&gcc GCC_BL <<
2681 clock-names = "core", <<
2682 dmas = <&blsp2_dma 10 <<
2683 dma-names = "tx", "rx <<
2684 pinctrl-names = "defa <<
2685 pinctrl-0 = <&blsp2_s <<
2686 <<
2687 status = "disabled"; <<
2688 #address-cells = <1>; <<
2689 #size-cells = <0>; <<
2690 }; <<
2691 <<
2692 blsp2_spi4: spi@c1b8000 { <<
2693 compatible = "qcom,sp <<
2694 reg = <0x0c1b8000 0x6 <<
2695 interrupts = <GIC_SPI <<
2696 <<
2697 clocks = <&gcc GCC_BL <<
2698 <&gcc GCC_BL <<
2699 clock-names = "core", <<
2700 dmas = <&blsp2_dma 12 <<
2701 dma-names = "tx", "rx <<
2702 pinctrl-names = "defa <<
2703 pinctrl-0 = <&blsp2_s <<
2704 <<
2705 status = "disabled"; <<
2706 #address-cells = <1>; <<
2707 #size-cells = <0>; <<
2708 }; <<
2709 <<
2710 blsp2_spi5: spi@c1b9000 { <<
2711 compatible = "qcom,sp <<
2712 reg = <0x0c1b9000 0x6 <<
2713 interrupts = <GIC_SPI <<
2714 <<
2715 clocks = <&gcc GCC_BL <<
2716 <&gcc GCC_BL <<
2717 clock-names = "core", <<
2718 dmas = <&blsp2_dma 14 <<
2719 dma-names = "tx", "rx <<
2720 pinctrl-names = "defa <<
2721 pinctrl-0 = <&blsp2_s <<
2722 <<
2723 status = "disabled"; <<
2724 #address-cells = <1>; <<
2725 #size-cells = <0>; <<
2726 }; <<
2727 <<
2728 blsp2_spi6: spi@c1ba000 { <<
2729 compatible = "qcom,sp <<
2730 reg = <0x0c1ba000 0x6 <<
2731 interrupts = <GIC_SPI <<
2732 <<
2733 clocks = <&gcc GCC_BL <<
2734 <&gcc GCC_BL <<
2735 clock-names = "core", <<
2736 dmas = <&blsp2_dma 16 <<
2737 dma-names = "tx", "rx <<
2738 pinctrl-names = "defa <<
2739 pinctrl-0 = <&blsp2_s <<
2740 <<
2741 status = "disabled"; <<
2742 #address-cells = <1>; <<
2743 #size-cells = <0>; <<
2744 }; <<
2745 <<
2746 mmcc: clock-controller@c8c000 2412 mmcc: clock-controller@c8c0000 {
2747 compatible = "qcom,mm 2413 compatible = "qcom,mmcc-msm8998";
2748 #clock-cells = <1>; 2414 #clock-cells = <1>;
2749 #reset-cells = <1>; 2415 #reset-cells = <1>;
2750 #power-domain-cells = 2416 #power-domain-cells = <1>;
2751 reg = <0xc8c0000 0x40 2417 reg = <0xc8c0000 0x40000>;
>> 2418 status = "disabled";
2752 2419
2753 clock-names = "xo", 2420 clock-names = "xo",
2754 "gpll0" 2421 "gpll0",
2755 "dsi0ds 2422 "dsi0dsi",
2756 "dsi0by 2423 "dsi0byte",
2757 "dsi1ds 2424 "dsi1dsi",
2758 "dsi1by 2425 "dsi1byte",
2759 "hdmipl 2426 "hdmipll",
2760 "dplink 2427 "dplink",
2761 "dpvco" 2428 "dpvco",
2762 "gpll0_ !! 2429 "core_bi_pll_test_se";
2763 clocks = <&rpmcc RPM_ 2430 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
2764 <&gcc GCC_MM 2431 <&gcc GCC_MMSS_GPLL0_CLK>,
2765 <&mdss_dsi0_ <<
2766 <&mdss_dsi0_ <<
2767 <&mdss_dsi1_ <<
2768 <&mdss_dsi1_ <<
2769 <0>, 2432 <0>,
2770 <0>, 2433 <0>,
2771 <0>, 2434 <0>,
2772 <&gcc GCC_MM !! 2435 <0>,
2773 }; !! 2436 <0>,
2774 !! 2437 <0>,
2775 mdss: display-subsystem@c9000 !! 2438 <0>,
2776 compatible = "qcom,ms !! 2439 <0>;
2777 reg = <0x0c900000 0x1 <<
2778 reg-names = "mdss"; <<
2779 <<
2780 interrupts = <GIC_SPI <<
2781 interrupt-controller; <<
2782 #interrupt-cells = <1 <<
2783 <<
2784 clocks = <&mmcc MDSS_ <<
2785 <&mmcc MDSS_ <<
2786 <&mmcc MDSS_ <<
2787 clock-names = "iface" <<
2788 "bus", <<
2789 "core"; <<
2790 <<
2791 power-domains = <&mmc <<
2792 iommus = <&mmss_smmu <<
2793 <<
2794 #address-cells = <1>; <<
2795 #size-cells = <1>; <<
2796 ranges; <<
2797 <<
2798 status = "disabled"; <<
2799 <<
2800 mdss_mdp: display-con <<
2801 compatible = <<
2802 reg = <0x0c90 <<
2803 <0x0c9a <<
2804 <0x0c9b <<
2805 <0x0c9b <<
2806 reg-names = " <<
2807 " <<
2808 " <<
2809 " <<
2810 <<
2811 interrupt-par <<
2812 interrupts = <<
2813 <<
2814 clocks = <&mm <<
2815 <&mm <<
2816 <&mm <<
2817 <&mm <<
2818 <&mm <<
2819 clock-names = <<
2820 <<
2821 <<
2822 <<
2823 <<
2824 <<
2825 assigned-cloc <<
2826 assigned-cloc <<
2827 <<
2828 operating-poi <<
2829 power-domains <<
2830 <<
2831 mdp_opp_table <<
2832 compa <<
2833 <<
2834 opp-1 <<
2835 <<
2836 <<
2837 }; <<
2838 <<
2839 opp-2 <<
2840 <<
2841 <<
2842 }; <<
2843 <<
2844 opp-3 <<
2845 <<
2846 <<
2847 }; <<
2848 <<
2849 opp-4 <<
2850 <<
2851 <<
2852 }; <<
2853 }; <<
2854 <<
2855 ports { <<
2856 #addr <<
2857 #size <<
2858 <<
2859 port@ <<
2860 <<
2861 <<
2862 <<
2863 <<
2864 <<
2865 }; <<
2866 <<
2867 port@ <<
2868 <<
2869 <<
2870 <<
2871 <<
2872 <<
2873 }; <<
2874 }; <<
2875 }; <<
2876 <<
2877 mdss_dsi0: dsi@c99400 <<
2878 compatible = <<
2879 reg = <0x0c99 <<
2880 reg-names = " <<
2881 <<
2882 interrupt-par <<
2883 interrupts = <<
2884 <<
2885 clocks = <&mm <<
2886 <&mm <<
2887 <&mm <<
2888 <&mm <<
2889 <&mm <<
2890 <&mm <<
2891 clock-names = <<
2892 <<
2893 <<
2894 <<
2895 <<
2896 <<
2897 assigned-cloc <<
2898 <<
2899 assigned-cloc <<
2900 <<
2901 <<
2902 operating-poi <<
2903 power-domains <<
2904 <<
2905 phys = <&mdss <<
2906 phy-names = " <<
2907 <<
2908 #address-cell <<
2909 #size-cells = <<
2910 <<
2911 status = "dis <<
2912 <<
2913 ports { <<
2914 #addr <<
2915 #size <<
2916 <<
2917 port@ <<
2918 <<
2919 <<
2920 <<
2921 <<
2922 <<
2923 }; <<
2924 <<
2925 port@ <<
2926 <<
2927 <<
2928 <<
2929 <<
2930 }; <<
2931 }; <<
2932 }; <<
2933 <<
2934 mdss_dsi0_phy: phy@c9 <<
2935 compatible = <<
2936 reg = <0x0c99 <<
2937 <0x0c99 <<
2938 <0x0c99 <<
2939 reg-names = " <<
2940 " <<
2941 " <<
2942 <<
2943 clocks = <&mm <<
2944 <&rp <<
2945 clock-names = <<
2946 <<
2947 #clock-cells <<
2948 #phy-cells = <<
2949 <<
2950 status = "dis <<
2951 }; <<
2952 <<
2953 mdss_dsi1: dsi@c99600 <<
2954 compatible = <<
2955 reg = <0x0c99 <<
2956 reg-names = " <<
2957 <<
2958 interrupt-par <<
2959 interrupts = <<
2960 <<
2961 clocks = <&mm <<
2962 <&mm <<
2963 <&mm <<
2964 <&mm <<
2965 <&mm <<
2966 <&mm <<
2967 clock-names = <<
2968 <<
2969 <<
2970 <<
2971 <<
2972 <<
2973 assigned-cloc <<
2974 <<
2975 assigned-cloc <<
2976 <<
2977 <<
2978 operating-poi <<
2979 power-domains <<
2980 <<
2981 phys = <&mdss <<
2982 phy-names = " <<
2983 <<
2984 #address-cell <<
2985 #size-cells = <<
2986 <<
2987 status = "dis <<
2988 <<
2989 ports { <<
2990 #addr <<
2991 #size <<
2992 <<
2993 port@ <<
2994 <<
2995 <<
2996 <<
2997 <<
2998 <<
2999 }; <<
3000 <<
3001 port@ <<
3002 <<
3003 <<
3004 <<
3005 <<
3006 }; <<
3007 }; <<
3008 }; <<
3009 <<
3010 mdss_dsi1_phy: phy@c9 <<
3011 compatible = <<
3012 reg = <0x0c99 <<
3013 <0x0c99 <<
3014 <0x0c99 <<
3015 reg-names = " <<
3016 " <<
3017 " <<
3018 <<
3019 clocks = <&mm <<
3020 <&rp <<
3021 clock-names = <<
3022 <<
3023 <<
3024 #clock-cells <<
3025 #phy-cells = <<
3026 <<
3027 status = "dis <<
3028 }; <<
3029 }; <<
3030 <<
3031 venus: video-codec@cc00000 { <<
3032 compatible = "qcom,ms <<
3033 reg = <0x0cc00000 0xf <<
3034 interrupts = <GIC_SPI <<
3035 power-domains = <&mmc <<
3036 clocks = <&mmcc VIDEO <<
3037 <&mmcc VIDEO <<
3038 <&mmcc VIDEO <<
3039 <&mmcc VIDEO <<
3040 clock-names = "core", <<
3041 iommus = <&mmss_smmu <<
3042 <&mmss_smmu <<
3043 <&mmss_smmu <<
3044 <&mmss_smmu <<
3045 <&mmss_smmu <<
3046 <&mmss_smmu <<
3047 <&mmss_smmu <<
3048 <&mmss_smmu <<
3049 <&mmss_smmu <<
3050 <&mmss_smmu <<
3051 <&mmss_smmu <<
3052 <&mmss_smmu <<
3053 <&mmss_smmu <<
3054 <&mmss_smmu <<
3055 <&mmss_smmu <<
3056 <&mmss_smmu <<
3057 <&mmss_smmu <<
3058 <&mmss_smmu <<
3059 <&mmss_smmu <<
3060 <&mmss_smmu <<
3061 memory-region = <&ven <<
3062 status = "disabled"; <<
3063 <<
3064 video-decoder { <<
3065 compatible = <<
3066 clocks = <&mm <<
3067 clock-names = <<
3068 power-domains <<
3069 }; <<
3070 <<
3071 video-encoder { <<
3072 compatible = <<
3073 clocks = <&mm <<
3074 clock-names = <<
3075 power-domains <<
3076 }; <<
3077 }; 2440 };
3078 2441
3079 mmss_smmu: iommu@cd00000 { 2442 mmss_smmu: iommu@cd00000 {
3080 compatible = "qcom,ms 2443 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
3081 reg = <0x0cd00000 0x4 2444 reg = <0x0cd00000 0x40000>;
3082 #iommu-cells = <1>; 2445 #iommu-cells = <1>;
3083 2446
3084 clocks = <&mmcc MNOC_ 2447 clocks = <&mmcc MNOC_AHB_CLK>,
3085 <&mmcc BIMC_ 2448 <&mmcc BIMC_SMMU_AHB_CLK>,
>> 2449 <&rpmcc RPM_SMD_MMAXI_CLK>,
3086 <&mmcc BIMC_ 2450 <&mmcc BIMC_SMMU_AXI_CLK>;
3087 clock-names = "iface- !! 2451 clock-names = "iface-mm", "iface-smmu",
3088 "iface- !! 2452 "bus-mm", "bus-smmu";
3089 "bus-sm !! 2453 status = "disabled";
3090 2454
3091 #global-interrupts = 2455 #global-interrupts = <0>;
3092 interrupts = 2456 interrupts =
3093 <GIC_SPI 263 2457 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
3094 <GIC_SPI 266 2458 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
3095 <GIC_SPI 267 2459 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
3096 <GIC_SPI 268 2460 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
3097 <GIC_SPI 244 2461 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
3098 <GIC_SPI 245 2462 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
3099 <GIC_SPI 247 2463 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
3100 <GIC_SPI 248 2464 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
3101 <GIC_SPI 249 2465 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
3102 <GIC_SPI 250 2466 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
3103 <GIC_SPI 251 2467 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
3104 <GIC_SPI 252 2468 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
3105 <GIC_SPI 253 2469 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
3106 <GIC_SPI 254 2470 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
3107 <GIC_SPI 255 2471 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
3108 <GIC_SPI 256 2472 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
3109 <GIC_SPI 260 2473 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
3110 <GIC_SPI 261 2474 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
3111 <GIC_SPI 262 2475 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
3112 <GIC_SPI 272 2476 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
3113 <<
3114 power-domains = <&mmc <<
3115 }; 2477 };
3116 2478
3117 remoteproc_adsp: remoteproc@1 2479 remoteproc_adsp: remoteproc@17300000 {
3118 compatible = "qcom,ms 2480 compatible = "qcom,msm8998-adsp-pas";
3119 reg = <0x17300000 0x4 2481 reg = <0x17300000 0x4040>;
3120 2482
3121 interrupts-extended = 2483 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
3122 2484 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3123 2485 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3124 2486 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3125 2487 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
3126 interrupt-names = "wd 2488 interrupt-names = "wdog", "fatal", "ready",
3127 "ha 2489 "handover", "stop-ack";
3128 2490
3129 clocks = <&rpmcc RPM_ 2491 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
3130 clock-names = "xo"; 2492 clock-names = "xo";
3131 2493
3132 memory-region = <&ads 2494 memory-region = <&adsp_mem>;
3133 2495
3134 qcom,smem-states = <& 2496 qcom,smem-states = <&adsp_smp2p_out 0>;
3135 qcom,smem-state-names 2497 qcom,smem-state-names = "stop";
3136 2498
3137 power-domains = <&rpm 2499 power-domains = <&rpmpd MSM8998_VDDCX>;
3138 power-domain-names = 2500 power-domain-names = "cx";
3139 2501
3140 status = "disabled"; 2502 status = "disabled";
3141 2503
3142 glink-edge { 2504 glink-edge {
3143 interrupts = 2505 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
3144 label = "lpas 2506 label = "lpass";
3145 qcom,remote-p 2507 qcom,remote-pid = <2>;
3146 mboxes = <&ap 2508 mboxes = <&apcs_glb 9>;
3147 }; 2509 };
3148 }; 2510 };
3149 2511
3150 apcs_glb: mailbox@17911000 { 2512 apcs_glb: mailbox@17911000 {
3151 compatible = "qcom,ms !! 2513 compatible = "qcom,msm8998-apcs-hmss-global";
3152 "qcom,ms <<
3153 reg = <0x17911000 0x1 2514 reg = <0x17911000 0x1000>;
3154 2515
3155 #mbox-cells = <1>; 2516 #mbox-cells = <1>;
3156 }; 2517 };
3157 2518
3158 timer@17920000 { 2519 timer@17920000 {
3159 #address-cells = <1>; 2520 #address-cells = <1>;
3160 #size-cells = <1>; 2521 #size-cells = <1>;
3161 ranges; 2522 ranges;
3162 compatible = "arm,arm 2523 compatible = "arm,armv7-timer-mem";
3163 reg = <0x17920000 0x1 2524 reg = <0x17920000 0x1000>;
3164 2525
3165 frame@17921000 { 2526 frame@17921000 {
3166 frame-number 2527 frame-number = <0>;
3167 interrupts = 2528 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
3168 2529 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
3169 reg = <0x1792 2530 reg = <0x17921000 0x1000>,
3170 <0x1792 2531 <0x17922000 0x1000>;
3171 }; 2532 };
3172 2533
3173 frame@17923000 { 2534 frame@17923000 {
3174 frame-number 2535 frame-number = <1>;
3175 interrupts = 2536 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
3176 reg = <0x1792 2537 reg = <0x17923000 0x1000>;
3177 status = "dis 2538 status = "disabled";
3178 }; 2539 };
3179 2540
3180 frame@17924000 { 2541 frame@17924000 {
3181 frame-number 2542 frame-number = <2>;
3182 interrupts = 2543 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
3183 reg = <0x1792 2544 reg = <0x17924000 0x1000>;
3184 status = "dis 2545 status = "disabled";
3185 }; 2546 };
3186 2547
3187 frame@17925000 { 2548 frame@17925000 {
3188 frame-number 2549 frame-number = <3>;
3189 interrupts = 2550 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3190 reg = <0x1792 2551 reg = <0x17925000 0x1000>;
3191 status = "dis 2552 status = "disabled";
3192 }; 2553 };
3193 2554
3194 frame@17926000 { 2555 frame@17926000 {
3195 frame-number 2556 frame-number = <4>;
3196 interrupts = 2557 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3197 reg = <0x1792 2558 reg = <0x17926000 0x1000>;
3198 status = "dis 2559 status = "disabled";
3199 }; 2560 };
3200 2561
3201 frame@17927000 { 2562 frame@17927000 {
3202 frame-number 2563 frame-number = <5>;
3203 interrupts = 2564 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3204 reg = <0x1792 2565 reg = <0x17927000 0x1000>;
3205 status = "dis 2566 status = "disabled";
3206 }; 2567 };
3207 2568
3208 frame@17928000 { 2569 frame@17928000 {
3209 frame-number 2570 frame-number = <6>;
3210 interrupts = 2571 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
3211 reg = <0x1792 2572 reg = <0x17928000 0x1000>;
3212 status = "dis 2573 status = "disabled";
3213 }; 2574 };
3214 }; 2575 };
3215 2576
3216 intc: interrupt-controller@17 2577 intc: interrupt-controller@17a00000 {
3217 compatible = "arm,gic 2578 compatible = "arm,gic-v3";
3218 reg = <0x17a00000 0x1 2579 reg = <0x17a00000 0x10000>, /* GICD */
3219 <0x17b00000 0x1 2580 <0x17b00000 0x100000>; /* GICR * 8 */
3220 #interrupt-cells = <3 2581 #interrupt-cells = <3>;
3221 #address-cells = <1>; 2582 #address-cells = <1>;
3222 #size-cells = <1>; 2583 #size-cells = <1>;
3223 ranges; 2584 ranges;
3224 interrupt-controller; 2585 interrupt-controller;
3225 #redistributor-region 2586 #redistributor-regions = <1>;
3226 redistributor-stride 2587 redistributor-stride = <0x0 0x20000>;
3227 interrupts = <GIC_PPI 2588 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3228 }; 2589 };
3229 2590
3230 wifi: wifi@18800000 { 2591 wifi: wifi@18800000 {
3231 compatible = "qcom,wc 2592 compatible = "qcom,wcn3990-wifi";
3232 status = "disabled"; 2593 status = "disabled";
3233 reg = <0x18800000 0x8 2594 reg = <0x18800000 0x800000>;
3234 reg-names = "membase" 2595 reg-names = "membase";
3235 memory-region = <&wla 2596 memory-region = <&wlan_msa_mem>;
3236 clocks = <&rpmcc RPM_ 2597 clocks = <&rpmcc RPM_SMD_RF_CLK2_PIN>;
3237 clock-names = "cxo_re 2598 clock-names = "cxo_ref_clk_pin";
3238 interrupts = 2599 interrupts =
3239 <GIC_SPI 413 2600 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
3240 <GIC_SPI 414 2601 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
3241 <GIC_SPI 415 2602 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
3242 <GIC_SPI 416 2603 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
3243 <GIC_SPI 417 2604 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
3244 <GIC_SPI 418 2605 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
3245 <GIC_SPI 420 2606 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
3246 <GIC_SPI 421 2607 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
3247 <GIC_SPI 422 2608 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
3248 <GIC_SPI 423 2609 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
3249 <GIC_SPI 424 2610 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
3250 <GIC_SPI 425 2611 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
3251 iommus = <&anoc2_smmu 2612 iommus = <&anoc2_smmu 0x1900>,
3252 <&anoc2_smmu 2613 <&anoc2_smmu 0x1901>;
3253 qcom,snoc-host-cap-8b 2614 qcom,snoc-host-cap-8bit-quirk;
3254 qcom,no-msa-ready-ind <<
3255 }; 2615 };
3256 }; 2616 };
3257 }; 2617 };
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