1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2016, The Linux Foundation. A 2 /* Copyright (c) 2016, The Linux Foundation. All rights reserved. */
3 3
4 #include <dt-bindings/interrupt-controller/arm 4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-msm8998.h 5 #include <dt-bindings/clock/qcom,gcc-msm8998.h>
6 #include <dt-bindings/clock/qcom,gpucc-msm8998 <<
7 #include <dt-bindings/clock/qcom,mmcc-msm8998. <<
8 #include <dt-bindings/clock/qcom,rpmcc.h> 6 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/firmware/qcom,scm.h> <<
10 #include <dt-bindings/power/qcom-rpmpd.h> <<
11 #include <dt-bindings/gpio/gpio.h> 7 #include <dt-bindings/gpio/gpio.h>
12 8
13 / { 9 / {
14 interrupt-parent = <&intc>; 10 interrupt-parent = <&intc>;
15 11
16 qcom,msm-id = <292 0x0>; 12 qcom,msm-id = <292 0x0>;
17 13
18 #address-cells = <2>; 14 #address-cells = <2>;
19 #size-cells = <2>; 15 #size-cells = <2>;
20 16
21 chosen { }; 17 chosen { };
22 18
23 memory@80000000 { !! 19 memory {
24 device_type = "memory"; 20 device_type = "memory";
25 /* We expect the bootloader to 21 /* We expect the bootloader to fill in the reg */
26 reg = <0x0 0x80000000 0x0 0x0> !! 22 reg = <0 0 0 0>;
27 }; 23 };
28 24
29 reserved-memory { 25 reserved-memory {
30 #address-cells = <2>; 26 #address-cells = <2>;
31 #size-cells = <2>; 27 #size-cells = <2>;
32 ranges; 28 ranges;
33 29
34 hyp_mem: memory@85800000 { !! 30 memory@85800000 {
35 reg = <0x0 0x85800000 !! 31 reg = <0x0 0x85800000 0x0 0x800000>;
36 no-map; <<
37 }; <<
38 <<
39 xbl_mem: memory@85e00000 { <<
40 reg = <0x0 0x85e00000 <<
41 no-map; 32 no-map;
42 }; 33 };
43 34
44 smem_mem: smem-mem@86000000 { 35 smem_mem: smem-mem@86000000 {
45 reg = <0x0 0x86000000 36 reg = <0x0 0x86000000 0x0 0x200000>;
46 no-map; 37 no-map;
47 }; 38 };
48 39
49 tz_mem: memory@86200000 { !! 40 memory@86200000 {
50 reg = <0x0 0x86200000 41 reg = <0x0 0x86200000 0x0 0x2d00000>;
51 no-map; 42 no-map;
52 }; 43 };
53 44
54 rmtfs_mem: memory@88f00000 { !! 45 rmtfs {
55 compatible = "qcom,rmt 46 compatible = "qcom,rmtfs-mem";
56 reg = <0x0 0x88f00000 <<
57 no-map; <<
58 <<
59 qcom,client-id = <1>; <<
60 qcom,vmid = <QCOM_SCM_ <<
61 }; <<
62 <<
63 spss_mem: memory@8ab00000 { <<
64 reg = <0x0 0x8ab00000 <<
65 no-map; <<
66 }; <<
67 <<
68 adsp_mem: memory@8b200000 { <<
69 reg = <0x0 0x8b200000 <<
70 no-map; <<
71 }; <<
72 <<
73 mpss_mem: memory@8cc00000 { <<
74 reg = <0x0 0x8cc00000 <<
75 no-map; <<
76 }; <<
77 <<
78 venus_mem: memory@93c00000 { <<
79 reg = <0x0 0x93c00000 <<
80 no-map; <<
81 }; <<
82 <<
83 mba_mem: memory@94100000 { <<
84 reg = <0x0 0x94100000 <<
85 no-map; <<
86 }; <<
87 <<
88 slpi_mem: memory@94300000 { <<
89 reg = <0x0 0x94300000 <<
90 no-map; <<
91 }; <<
92 47
93 ipa_fw_mem: memory@95200000 { !! 48 size = <0x0 0x200000>;
94 reg = <0x0 0x95200000 !! 49 alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
95 no-map; 50 no-map;
96 }; <<
97 <<
98 ipa_gsi_mem: memory@95210000 { <<
99 reg = <0x0 0x95210000 <<
100 no-map; <<
101 }; <<
102 <<
103 gpu_mem: memory@95600000 { <<
104 reg = <0x0 0x95600000 <<
105 no-map; <<
106 }; <<
107 51
108 wlan_msa_mem: memory@95700000 !! 52 qcom,client-id = <1>;
109 reg = <0x0 0x95700000 !! 53 qcom,vmid = <15>;
110 no-map; <<
111 }; <<
112 <<
113 mdata_mem: mpss-metadata { <<
114 alloc-ranges = <0x0 0x <<
115 size = <0x0 0x4000>; <<
116 no-map; <<
117 }; 54 };
118 }; 55 };
119 56
120 clocks { 57 clocks {
121 xo: xo-board { 58 xo: xo-board {
122 compatible = "fixed-cl 59 compatible = "fixed-clock";
123 #clock-cells = <0>; 60 #clock-cells = <0>;
124 clock-frequency = <192 61 clock-frequency = <19200000>;
125 clock-output-names = " 62 clock-output-names = "xo_board";
126 }; 63 };
127 64
128 sleep_clk: sleep-clk { !! 65 sleep_clk {
129 compatible = "fixed-cl 66 compatible = "fixed-clock";
130 #clock-cells = <0>; 67 #clock-cells = <0>;
131 clock-frequency = <327 68 clock-frequency = <32764>;
132 }; 69 };
133 }; 70 };
134 71
135 cpus { 72 cpus {
136 #address-cells = <2>; 73 #address-cells = <2>;
137 #size-cells = <0>; 74 #size-cells = <0>;
138 75
139 CPU0: cpu@0 { 76 CPU0: cpu@0 {
140 device_type = "cpu"; 77 device_type = "cpu";
141 compatible = "qcom,kry !! 78 compatible = "arm,armv8";
142 reg = <0x0 0x0>; 79 reg = <0x0 0x0>;
143 enable-method = "psci" 80 enable-method = "psci";
144 capacity-dmips-mhz = < <<
145 cpu-idle-states = <&LI <<
146 next-level-cache = <&L 81 next-level-cache = <&L2_0>;
147 L2_0: l2-cache { 82 L2_0: l2-cache {
148 compatible = " !! 83 compatible = "arm,arch-cache";
149 cache-level = 84 cache-level = <2>;
150 cache-unified; !! 85 };
>> 86 L1_I_0: l1-icache {
>> 87 compatible = "arm,arch-cache";
>> 88 };
>> 89 L1_D_0: l1-dcache {
>> 90 compatible = "arm,arch-cache";
151 }; 91 };
152 }; 92 };
153 93
154 CPU1: cpu@1 { 94 CPU1: cpu@1 {
155 device_type = "cpu"; 95 device_type = "cpu";
156 compatible = "qcom,kry !! 96 compatible = "arm,armv8";
157 reg = <0x0 0x1>; 97 reg = <0x0 0x1>;
158 enable-method = "psci" 98 enable-method = "psci";
159 capacity-dmips-mhz = < <<
160 cpu-idle-states = <&LI <<
161 next-level-cache = <&L 99 next-level-cache = <&L2_0>;
>> 100 L1_I_1: l1-icache {
>> 101 compatible = "arm,arch-cache";
>> 102 };
>> 103 L1_D_1: l1-dcache {
>> 104 compatible = "arm,arch-cache";
>> 105 };
162 }; 106 };
163 107
164 CPU2: cpu@2 { 108 CPU2: cpu@2 {
165 device_type = "cpu"; 109 device_type = "cpu";
166 compatible = "qcom,kry !! 110 compatible = "arm,armv8";
167 reg = <0x0 0x2>; 111 reg = <0x0 0x2>;
168 enable-method = "psci" 112 enable-method = "psci";
169 capacity-dmips-mhz = < <<
170 cpu-idle-states = <&LI <<
171 next-level-cache = <&L 113 next-level-cache = <&L2_0>;
>> 114 L1_I_2: l1-icache {
>> 115 compatible = "arm,arch-cache";
>> 116 };
>> 117 L1_D_2: l1-dcache {
>> 118 compatible = "arm,arch-cache";
>> 119 };
172 }; 120 };
173 121
174 CPU3: cpu@3 { 122 CPU3: cpu@3 {
175 device_type = "cpu"; 123 device_type = "cpu";
176 compatible = "qcom,kry !! 124 compatible = "arm,armv8";
177 reg = <0x0 0x3>; 125 reg = <0x0 0x3>;
178 enable-method = "psci" 126 enable-method = "psci";
179 capacity-dmips-mhz = < <<
180 cpu-idle-states = <&LI <<
181 next-level-cache = <&L 127 next-level-cache = <&L2_0>;
>> 128 L1_I_3: l1-icache {
>> 129 compatible = "arm,arch-cache";
>> 130 };
>> 131 L1_D_3: l1-dcache {
>> 132 compatible = "arm,arch-cache";
>> 133 };
182 }; 134 };
183 135
184 CPU4: cpu@100 { 136 CPU4: cpu@100 {
185 device_type = "cpu"; 137 device_type = "cpu";
186 compatible = "qcom,kry !! 138 compatible = "arm,armv8";
187 reg = <0x0 0x100>; 139 reg = <0x0 0x100>;
188 enable-method = "psci" 140 enable-method = "psci";
189 capacity-dmips-mhz = < <<
190 cpu-idle-states = <&BI <<
191 next-level-cache = <&L 141 next-level-cache = <&L2_1>;
192 L2_1: l2-cache { 142 L2_1: l2-cache {
193 compatible = " !! 143 compatible = "arm,arch-cache";
194 cache-level = 144 cache-level = <2>;
195 cache-unified; !! 145 };
>> 146 L1_I_100: l1-icache {
>> 147 compatible = "arm,arch-cache";
>> 148 };
>> 149 L1_D_100: l1-dcache {
>> 150 compatible = "arm,arch-cache";
196 }; 151 };
197 }; 152 };
198 153
199 CPU5: cpu@101 { 154 CPU5: cpu@101 {
200 device_type = "cpu"; 155 device_type = "cpu";
201 compatible = "qcom,kry !! 156 compatible = "arm,armv8";
202 reg = <0x0 0x101>; 157 reg = <0x0 0x101>;
203 enable-method = "psci" 158 enable-method = "psci";
204 capacity-dmips-mhz = < <<
205 cpu-idle-states = <&BI <<
206 next-level-cache = <&L 159 next-level-cache = <&L2_1>;
>> 160 L1_I_101: l1-icache {
>> 161 compatible = "arm,arch-cache";
>> 162 };
>> 163 L1_D_101: l1-dcache {
>> 164 compatible = "arm,arch-cache";
>> 165 };
207 }; 166 };
208 167
209 CPU6: cpu@102 { 168 CPU6: cpu@102 {
210 device_type = "cpu"; 169 device_type = "cpu";
211 compatible = "qcom,kry !! 170 compatible = "arm,armv8";
212 reg = <0x0 0x102>; 171 reg = <0x0 0x102>;
213 enable-method = "psci" 172 enable-method = "psci";
214 capacity-dmips-mhz = < <<
215 cpu-idle-states = <&BI <<
216 next-level-cache = <&L 173 next-level-cache = <&L2_1>;
>> 174 L1_I_102: l1-icache {
>> 175 compatible = "arm,arch-cache";
>> 176 };
>> 177 L1_D_102: l1-dcache {
>> 178 compatible = "arm,arch-cache";
>> 179 };
217 }; 180 };
218 181
219 CPU7: cpu@103 { 182 CPU7: cpu@103 {
220 device_type = "cpu"; 183 device_type = "cpu";
221 compatible = "qcom,kry !! 184 compatible = "arm,armv8";
222 reg = <0x0 0x103>; 185 reg = <0x0 0x103>;
223 enable-method = "psci" 186 enable-method = "psci";
224 capacity-dmips-mhz = < <<
225 cpu-idle-states = <&BI <<
226 next-level-cache = <&L 187 next-level-cache = <&L2_1>;
>> 188 L1_I_103: l1-icache {
>> 189 compatible = "arm,arch-cache";
>> 190 };
>> 191 L1_D_103: l1-dcache {
>> 192 compatible = "arm,arch-cache";
>> 193 };
227 }; 194 };
228 195
229 cpu-map { 196 cpu-map {
230 cluster0 { 197 cluster0 {
231 core0 { 198 core0 {
232 cpu = 199 cpu = <&CPU0>;
233 }; 200 };
234 201
235 core1 { 202 core1 {
236 cpu = 203 cpu = <&CPU1>;
237 }; 204 };
238 205
239 core2 { 206 core2 {
240 cpu = 207 cpu = <&CPU2>;
241 }; 208 };
242 209
243 core3 { 210 core3 {
244 cpu = 211 cpu = <&CPU3>;
245 }; 212 };
246 }; 213 };
247 214
248 cluster1 { 215 cluster1 {
249 core0 { 216 core0 {
250 cpu = 217 cpu = <&CPU4>;
251 }; 218 };
252 219
253 core1 { 220 core1 {
254 cpu = 221 cpu = <&CPU5>;
255 }; 222 };
256 223
257 core2 { 224 core2 {
258 cpu = 225 cpu = <&CPU6>;
259 }; 226 };
260 227
261 core3 { 228 core3 {
262 cpu = 229 cpu = <&CPU7>;
263 }; 230 };
264 }; 231 };
265 }; 232 };
266 <<
267 idle-states { <<
268 entry-method = "psci"; <<
269 <<
270 LITTLE_CPU_SLEEP_0: cp <<
271 compatible = " <<
272 idle-state-nam <<
273 /* CPU Retenti <<
274 arm,psci-suspe <<
275 entry-latency- <<
276 exit-latency-u <<
277 min-residency- <<
278 }; <<
279 <<
280 LITTLE_CPU_SLEEP_1: cp <<
281 compatible = " <<
282 idle-state-nam <<
283 /* CPU + L2 Po <<
284 arm,psci-suspe <<
285 entry-latency- <<
286 exit-latency-u <<
287 min-residency- <<
288 local-timer-st <<
289 }; <<
290 <<
291 BIG_CPU_SLEEP_0: cpu-s <<
292 compatible = " <<
293 idle-state-nam <<
294 /* CPU Retenti <<
295 arm,psci-suspe <<
296 entry-latency- <<
297 exit-latency-u <<
298 min-residency- <<
299 }; <<
300 <<
301 BIG_CPU_SLEEP_1: cpu-s <<
302 compatible = " <<
303 idle-state-nam <<
304 /* CPU + L2 Po <<
305 arm,psci-suspe <<
306 entry-latency- <<
307 exit-latency-u <<
308 min-residency- <<
309 local-timer-st <<
310 }; <<
311 }; <<
312 }; 233 };
313 234
314 firmware { 235 firmware {
315 scm { 236 scm {
316 compatible = "qcom,scm 237 compatible = "qcom,scm-msm8998", "qcom,scm";
317 }; 238 };
318 }; 239 };
319 240
320 dsi_opp_table: opp-table-dsi { !! 241 tcsr_mutex: hwlock {
321 compatible = "operating-points !! 242 compatible = "qcom,tcsr-mutex";
322 !! 243 syscon = <&tcsr_mutex_regs 0 0x1000>;
323 opp-131250000 { !! 244 #hwlock-cells = <1>;
324 opp-hz = /bits/ 64 <13 <<
325 required-opps = <&rpmp <<
326 }; <<
327 <<
328 opp-210000000 { <<
329 opp-hz = /bits/ 64 <21 <<
330 required-opps = <&rpmp <<
331 }; <<
332 <<
333 opp-312500000 { <<
334 opp-hz = /bits/ 64 <31 <<
335 required-opps = <&rpmp <<
336 }; <<
337 }; 245 };
338 246
339 psci { 247 psci {
340 compatible = "arm,psci-1.0"; 248 compatible = "arm,psci-1.0";
341 method = "smc"; 249 method = "smc";
342 }; 250 };
343 251
344 rpm: remoteproc { !! 252 rpm-glink {
345 compatible = "qcom,msm8998-rpm !! 253 compatible = "qcom,glink-rpm";
346 254
347 glink-edge { !! 255 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
348 compatible = "qcom,gli !! 256 qcom,rpm-msg-ram = <&rpm_msg_ram>;
>> 257 mboxes = <&apcs_glb 0>;
>> 258
>> 259 rpm_requests: rpm-requests {
>> 260 compatible = "qcom,rpm-msm8998";
>> 261 qcom,glink-channels = "rpm_requests";
349 262
350 interrupts = <GIC_SPI !! 263 rpmcc: clock-controller {
351 qcom,rpm-msg-ram = <&r !! 264 compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc";
352 mboxes = <&apcs_glb 0> !! 265 #clock-cells = <1>;
353 <<
354 rpm_requests: rpm-requ <<
355 compatible = " <<
356 qcom,glink-cha <<
357 <<
358 rpmcc: clock-c <<
359 compat <<
360 clocks <<
361 clock- <<
362 #clock <<
363 }; <<
364 <<
365 rpmpd: power-c <<
366 compat <<
367 #power <<
368 operat <<
369 <<
370 rpmpd_ <<
371 <<
372 <<
373 <<
374 <<
375 <<
376 <<
377 <<
378 <<
379 <<
380 <<
381 <<
382 <<
383 <<
384 <<
385 <<
386 <<
387 <<
388 <<
389 <<
390 <<
391 <<
392 <<
393 <<
394 <<
395 <<
396 <<
397 <<
398 <<
399 <<
400 <<
401 <<
402 <<
403 <<
404 <<
405 <<
406 <<
407 <<
408 <<
409 <<
410 <<
411 <<
412 }; <<
413 }; <<
414 }; 266 };
415 }; 267 };
416 }; 268 };
417 269
418 smem { 270 smem {
419 compatible = "qcom,smem"; 271 compatible = "qcom,smem";
420 memory-region = <&smem_mem>; 272 memory-region = <&smem_mem>;
421 hwlocks = <&tcsr_mutex 3>; 273 hwlocks = <&tcsr_mutex 3>;
422 }; 274 };
423 275
424 smp2p-lpass { 276 smp2p-lpass {
425 compatible = "qcom,smp2p"; 277 compatible = "qcom,smp2p";
426 qcom,smem = <443>, <429>; 278 qcom,smem = <443>, <429>;
427 279
428 interrupts = <GIC_SPI 158 IRQ_ 280 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
429 281
430 mboxes = <&apcs_glb 10>; 282 mboxes = <&apcs_glb 10>;
431 283
432 qcom,local-pid = <0>; 284 qcom,local-pid = <0>;
433 qcom,remote-pid = <2>; 285 qcom,remote-pid = <2>;
434 286
435 adsp_smp2p_out: master-kernel 287 adsp_smp2p_out: master-kernel {
436 qcom,entry-name = "mas 288 qcom,entry-name = "master-kernel";
437 #qcom,smem-state-cells 289 #qcom,smem-state-cells = <1>;
438 }; 290 };
439 291
440 adsp_smp2p_in: slave-kernel { 292 adsp_smp2p_in: slave-kernel {
441 qcom,entry-name = "sla 293 qcom,entry-name = "slave-kernel";
442 294
443 interrupt-controller; 295 interrupt-controller;
444 #interrupt-cells = <2> 296 #interrupt-cells = <2>;
445 }; 297 };
446 }; 298 };
447 299
448 smp2p-mpss { 300 smp2p-mpss {
449 compatible = "qcom,smp2p"; 301 compatible = "qcom,smp2p";
450 qcom,smem = <435>, <428>; 302 qcom,smem = <435>, <428>;
451 interrupts = <GIC_SPI 451 IRQ_ 303 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
452 mboxes = <&apcs_glb 14>; 304 mboxes = <&apcs_glb 14>;
453 qcom,local-pid = <0>; 305 qcom,local-pid = <0>;
454 qcom,remote-pid = <1>; 306 qcom,remote-pid = <1>;
455 307
456 modem_smp2p_out: master-kernel 308 modem_smp2p_out: master-kernel {
457 qcom,entry-name = "mas 309 qcom,entry-name = "master-kernel";
458 #qcom,smem-state-cells 310 #qcom,smem-state-cells = <1>;
459 }; 311 };
460 312
461 modem_smp2p_in: slave-kernel { 313 modem_smp2p_in: slave-kernel {
462 qcom,entry-name = "sla 314 qcom,entry-name = "slave-kernel";
463 interrupt-controller; 315 interrupt-controller;
464 #interrupt-cells = <2> 316 #interrupt-cells = <2>;
465 }; 317 };
466 }; 318 };
467 319
468 smp2p-slpi { 320 smp2p-slpi {
469 compatible = "qcom,smp2p"; 321 compatible = "qcom,smp2p";
470 qcom,smem = <481>, <430>; 322 qcom,smem = <481>, <430>;
471 interrupts = <GIC_SPI 178 IRQ_ 323 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
472 mboxes = <&apcs_glb 26>; 324 mboxes = <&apcs_glb 26>;
473 qcom,local-pid = <0>; 325 qcom,local-pid = <0>;
474 qcom,remote-pid = <3>; 326 qcom,remote-pid = <3>;
475 327
476 slpi_smp2p_out: master-kernel 328 slpi_smp2p_out: master-kernel {
477 qcom,entry-name = "mas 329 qcom,entry-name = "master-kernel";
478 #qcom,smem-state-cells 330 #qcom,smem-state-cells = <1>;
479 }; 331 };
480 332
481 slpi_smp2p_in: slave-kernel { 333 slpi_smp2p_in: slave-kernel {
482 qcom,entry-name = "sla 334 qcom,entry-name = "slave-kernel";
483 interrupt-controller; 335 interrupt-controller;
484 #interrupt-cells = <2> 336 #interrupt-cells = <2>;
485 }; 337 };
486 }; 338 };
487 339
488 thermal-zones { 340 thermal-zones {
489 cpu0-thermal { 341 cpu0-thermal {
490 polling-delay-passive 342 polling-delay-passive = <250>;
>> 343 polling-delay = <1000>;
491 344
492 thermal-sensors = <&ts 345 thermal-sensors = <&tsens0 1>;
493 346
494 trips { 347 trips {
495 cpu0_alert0: t !! 348 cpu0_alert0: trip-point@0 {
496 temper 349 temperature = <75000>;
497 hyster 350 hysteresis = <2000>;
498 type = 351 type = "passive";
499 }; 352 };
500 353
501 cpu0_crit: cpu !! 354 cpu0_crit: cpu_crit {
502 temper 355 temperature = <110000>;
503 hyster 356 hysteresis = <2000>;
504 type = 357 type = "critical";
505 }; 358 };
506 }; 359 };
507 }; 360 };
508 361
509 cpu1-thermal { 362 cpu1-thermal {
510 polling-delay-passive 363 polling-delay-passive = <250>;
>> 364 polling-delay = <1000>;
511 365
512 thermal-sensors = <&ts 366 thermal-sensors = <&tsens0 2>;
513 367
514 trips { 368 trips {
515 cpu1_alert0: t !! 369 cpu1_alert0: trip-point@0 {
516 temper 370 temperature = <75000>;
517 hyster 371 hysteresis = <2000>;
518 type = 372 type = "passive";
519 }; 373 };
520 374
521 cpu1_crit: cpu !! 375 cpu1_crit: cpu_crit {
522 temper 376 temperature = <110000>;
523 hyster 377 hysteresis = <2000>;
524 type = 378 type = "critical";
525 }; 379 };
526 }; 380 };
527 }; 381 };
528 382
529 cpu2-thermal { 383 cpu2-thermal {
530 polling-delay-passive 384 polling-delay-passive = <250>;
>> 385 polling-delay = <1000>;
531 386
532 thermal-sensors = <&ts 387 thermal-sensors = <&tsens0 3>;
533 388
534 trips { 389 trips {
535 cpu2_alert0: t !! 390 cpu2_alert0: trip-point@0 {
536 temper 391 temperature = <75000>;
537 hyster 392 hysteresis = <2000>;
538 type = 393 type = "passive";
539 }; 394 };
540 395
541 cpu2_crit: cpu !! 396 cpu2_crit: cpu_crit {
542 temper 397 temperature = <110000>;
543 hyster 398 hysteresis = <2000>;
544 type = 399 type = "critical";
545 }; 400 };
546 }; 401 };
547 }; 402 };
548 403
549 cpu3-thermal { 404 cpu3-thermal {
550 polling-delay-passive 405 polling-delay-passive = <250>;
>> 406 polling-delay = <1000>;
551 407
552 thermal-sensors = <&ts 408 thermal-sensors = <&tsens0 4>;
553 409
554 trips { 410 trips {
555 cpu3_alert0: t !! 411 cpu3_alert0: trip-point@0 {
556 temper 412 temperature = <75000>;
557 hyster 413 hysteresis = <2000>;
558 type = 414 type = "passive";
559 }; 415 };
560 416
561 cpu3_crit: cpu !! 417 cpu3_crit: cpu_crit {
562 temper 418 temperature = <110000>;
563 hyster 419 hysteresis = <2000>;
564 type = 420 type = "critical";
565 }; 421 };
566 }; 422 };
567 }; 423 };
568 424
569 cpu4-thermal { 425 cpu4-thermal {
570 polling-delay-passive 426 polling-delay-passive = <250>;
>> 427 polling-delay = <1000>;
571 428
572 thermal-sensors = <&ts 429 thermal-sensors = <&tsens0 7>;
573 430
574 trips { 431 trips {
575 cpu4_alert0: t !! 432 cpu4_alert0: trip-point@0 {
576 temper 433 temperature = <75000>;
577 hyster 434 hysteresis = <2000>;
578 type = 435 type = "passive";
579 }; 436 };
580 437
581 cpu4_crit: cpu !! 438 cpu4_crit: cpu_crit {
582 temper 439 temperature = <110000>;
583 hyster 440 hysteresis = <2000>;
584 type = 441 type = "critical";
585 }; 442 };
586 }; 443 };
587 }; 444 };
588 445
589 cpu5-thermal { 446 cpu5-thermal {
590 polling-delay-passive 447 polling-delay-passive = <250>;
>> 448 polling-delay = <1000>;
591 449
592 thermal-sensors = <&ts 450 thermal-sensors = <&tsens0 8>;
593 451
594 trips { 452 trips {
595 cpu5_alert0: t !! 453 cpu5_alert0: trip-point@0 {
596 temper 454 temperature = <75000>;
597 hyster 455 hysteresis = <2000>;
598 type = 456 type = "passive";
599 }; 457 };
600 458
601 cpu5_crit: cpu !! 459 cpu5_crit: cpu_crit {
602 temper 460 temperature = <110000>;
603 hyster 461 hysteresis = <2000>;
604 type = 462 type = "critical";
605 }; 463 };
606 }; 464 };
607 }; 465 };
608 466
609 cpu6-thermal { 467 cpu6-thermal {
610 polling-delay-passive 468 polling-delay-passive = <250>;
>> 469 polling-delay = <1000>;
611 470
612 thermal-sensors = <&ts 471 thermal-sensors = <&tsens0 9>;
613 472
614 trips { 473 trips {
615 cpu6_alert0: t !! 474 cpu6_alert0: trip-point@0 {
616 temper 475 temperature = <75000>;
617 hyster 476 hysteresis = <2000>;
618 type = 477 type = "passive";
619 }; 478 };
620 479
621 cpu6_crit: cpu !! 480 cpu6_crit: cpu_crit {
622 temper 481 temperature = <110000>;
623 hyster 482 hysteresis = <2000>;
624 type = 483 type = "critical";
625 }; 484 };
626 }; 485 };
627 }; 486 };
628 487
629 cpu7-thermal { 488 cpu7-thermal {
630 polling-delay-passive 489 polling-delay-passive = <250>;
>> 490 polling-delay = <1000>;
631 491
632 thermal-sensors = <&ts 492 thermal-sensors = <&tsens0 10>;
633 493
634 trips { 494 trips {
635 cpu7_alert0: t !! 495 cpu7_alert0: trip-point@0 {
636 temper 496 temperature = <75000>;
637 hyster 497 hysteresis = <2000>;
638 type = 498 type = "passive";
639 }; 499 };
640 500
641 cpu7_crit: cpu !! 501 cpu7_crit: cpu_crit {
642 temper 502 temperature = <110000>;
643 hyster 503 hysteresis = <2000>;
644 type = 504 type = "critical";
645 }; 505 };
646 }; 506 };
647 }; 507 };
648 508
649 gpu-bottom-thermal { !! 509 gpu-thermal-bottom {
650 polling-delay-passive 510 polling-delay-passive = <250>;
>> 511 polling-delay = <1000>;
651 512
652 thermal-sensors = <&ts 513 thermal-sensors = <&tsens0 12>;
653 514
654 trips { 515 trips {
655 gpu1_alert0: t !! 516 gpu1_alert0: trip-point@0 {
656 temper 517 temperature = <90000>;
657 hyster 518 hysteresis = <2000>;
658 type = 519 type = "hot";
659 }; 520 };
660 }; 521 };
661 }; 522 };
662 523
663 gpu-top-thermal { !! 524 gpu-thermal-top {
664 polling-delay-passive 525 polling-delay-passive = <250>;
>> 526 polling-delay = <1000>;
665 527
666 thermal-sensors = <&ts 528 thermal-sensors = <&tsens0 13>;
667 529
668 trips { 530 trips {
669 gpu2_alert0: t !! 531 gpu2_alert0: trip-point@0 {
670 temper 532 temperature = <90000>;
671 hyster 533 hysteresis = <2000>;
672 type = 534 type = "hot";
673 }; 535 };
674 }; 536 };
675 }; 537 };
676 538
677 clust0-mhm-thermal { 539 clust0-mhm-thermal {
678 polling-delay-passive 540 polling-delay-passive = <250>;
>> 541 polling-delay = <1000>;
679 542
680 thermal-sensors = <&ts 543 thermal-sensors = <&tsens0 5>;
681 544
682 trips { 545 trips {
683 cluster0_mhm_a !! 546 cluster0_mhm_alert0: trip-point@0 {
684 temper 547 temperature = <90000>;
685 hyster 548 hysteresis = <2000>;
686 type = 549 type = "hot";
687 }; 550 };
688 }; 551 };
689 }; 552 };
690 553
691 clust1-mhm-thermal { 554 clust1-mhm-thermal {
692 polling-delay-passive 555 polling-delay-passive = <250>;
>> 556 polling-delay = <1000>;
693 557
694 thermal-sensors = <&ts 558 thermal-sensors = <&tsens0 6>;
695 559
696 trips { 560 trips {
697 cluster1_mhm_a !! 561 cluster1_mhm_alert0: trip-point@0 {
698 temper 562 temperature = <90000>;
699 hyster 563 hysteresis = <2000>;
700 type = 564 type = "hot";
701 }; 565 };
702 }; 566 };
703 }; 567 };
704 568
705 cluster1-l2-thermal { 569 cluster1-l2-thermal {
706 polling-delay-passive 570 polling-delay-passive = <250>;
>> 571 polling-delay = <1000>;
707 572
708 thermal-sensors = <&ts 573 thermal-sensors = <&tsens0 11>;
709 574
710 trips { 575 trips {
711 cluster1_l2_al !! 576 cluster1_l2_alert0: trip-point@0 {
712 temper 577 temperature = <90000>;
713 hyster 578 hysteresis = <2000>;
714 type = 579 type = "hot";
715 }; 580 };
716 }; 581 };
717 }; 582 };
718 583
719 modem-thermal { 584 modem-thermal {
720 polling-delay-passive 585 polling-delay-passive = <250>;
>> 586 polling-delay = <1000>;
721 587
722 thermal-sensors = <&ts 588 thermal-sensors = <&tsens1 1>;
723 589
724 trips { 590 trips {
725 modem_alert0: !! 591 modem_alert0: trip-point@0 {
726 temper 592 temperature = <90000>;
727 hyster 593 hysteresis = <2000>;
728 type = 594 type = "hot";
729 }; 595 };
730 }; 596 };
731 }; 597 };
732 598
733 mem-thermal { 599 mem-thermal {
734 polling-delay-passive 600 polling-delay-passive = <250>;
>> 601 polling-delay = <1000>;
735 602
736 thermal-sensors = <&ts 603 thermal-sensors = <&tsens1 2>;
737 604
738 trips { 605 trips {
739 mem_alert0: tr !! 606 mem_alert0: trip-point@0 {
740 temper 607 temperature = <90000>;
741 hyster 608 hysteresis = <2000>;
742 type = 609 type = "hot";
743 }; 610 };
744 }; 611 };
745 }; 612 };
746 613
747 wlan-thermal { 614 wlan-thermal {
748 polling-delay-passive 615 polling-delay-passive = <250>;
>> 616 polling-delay = <1000>;
749 617
750 thermal-sensors = <&ts 618 thermal-sensors = <&tsens1 3>;
751 619
752 trips { 620 trips {
753 wlan_alert0: t !! 621 wlan_alert0: trip-point@0 {
754 temper 622 temperature = <90000>;
755 hyster 623 hysteresis = <2000>;
756 type = 624 type = "hot";
757 }; 625 };
758 }; 626 };
759 }; 627 };
760 628
761 q6-dsp-thermal { 629 q6-dsp-thermal {
762 polling-delay-passive 630 polling-delay-passive = <250>;
>> 631 polling-delay = <1000>;
763 632
764 thermal-sensors = <&ts 633 thermal-sensors = <&tsens1 4>;
765 634
766 trips { 635 trips {
767 q6_dsp_alert0: !! 636 q6_dsp_alert0: trip-point@0 {
768 temper 637 temperature = <90000>;
769 hyster 638 hysteresis = <2000>;
770 type = 639 type = "hot";
771 }; 640 };
772 }; 641 };
773 }; 642 };
774 643
775 camera-thermal { 644 camera-thermal {
776 polling-delay-passive 645 polling-delay-passive = <250>;
>> 646 polling-delay = <1000>;
777 647
778 thermal-sensors = <&ts 648 thermal-sensors = <&tsens1 5>;
779 649
780 trips { 650 trips {
781 camera_alert0: !! 651 camera_alert0: trip-point@0 {
782 temper 652 temperature = <90000>;
783 hyster 653 hysteresis = <2000>;
784 type = 654 type = "hot";
785 }; 655 };
786 }; 656 };
787 }; 657 };
788 658
789 multimedia-thermal { 659 multimedia-thermal {
790 polling-delay-passive 660 polling-delay-passive = <250>;
>> 661 polling-delay = <1000>;
791 662
792 thermal-sensors = <&ts 663 thermal-sensors = <&tsens1 6>;
793 664
794 trips { 665 trips {
795 multimedia_ale !! 666 multimedia_alert0: trip-point@0 {
796 temper 667 temperature = <90000>;
797 hyster 668 hysteresis = <2000>;
798 type = 669 type = "hot";
799 }; 670 };
800 }; 671 };
801 }; 672 };
802 }; 673 };
803 674
804 timer { 675 timer {
805 compatible = "arm,armv8-timer" 676 compatible = "arm,armv8-timer";
806 interrupts = <GIC_PPI 1 IRQ_TY 677 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
807 <GIC_PPI 2 IRQ_TY 678 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
808 <GIC_PPI 3 IRQ_TY 679 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
809 <GIC_PPI 0 IRQ_TY 680 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
810 }; 681 };
811 682
812 soc: soc@0 { !! 683 soc: soc {
813 #address-cells = <1>; 684 #address-cells = <1>;
814 #size-cells = <1>; 685 #size-cells = <1>;
815 ranges = <0 0 0 0xffffffff>; 686 ranges = <0 0 0 0xffffffff>;
816 compatible = "simple-bus"; 687 compatible = "simple-bus";
817 688
818 gcc: clock-controller@100000 { !! 689 rpm_msg_ram: memory@68000 {
819 compatible = "qcom,gcc <<
820 #clock-cells = <1>; <<
821 #reset-cells = <1>; <<
822 #power-domain-cells = <<
823 reg = <0x00100000 0xb0 <<
824 <<
825 clock-names = "xo", "s <<
826 clocks = <&rpmcc RPM_S <<
827 <<
828 /* <<
829 * The hypervisor typi <<
830 * reside as read-only <<
831 * these clocks on a d <<
832 * enabled but unused <<
833 * to reboot. <<
834 * In light of that, w <<
835 * as protected. The b <<
836 * list of protected c <<
837 * desired for the HLO <<
838 */ <<
839 protected-clocks = <AG <<
840 <SS <<
841 <SS <<
842 }; <<
843 <<
844 rpm_msg_ram: sram@778000 { <<
845 compatible = "qcom,rpm 690 compatible = "qcom,rpm-msg-ram";
846 reg = <0x00778000 0x70 !! 691 reg = <0x778000 0x7000>;
847 }; 692 };
848 693
849 qfprom: qfprom@784000 { !! 694 qfprom: qfprom@780000 {
850 compatible = "qcom,msm !! 695 compatible = "qcom,qfprom";
851 reg = <0x00784000 0x62 !! 696 reg = <0x780000 0x621c>;
852 #address-cells = <1>; 697 #address-cells = <1>;
853 #size-cells = <1>; 698 #size-cells = <1>;
854 699
855 qusb2_hstx_trim: hstx- !! 700 qusb2_hstx_trim: hstx-trim@423a {
856 reg = <0x23a 0 !! 701 reg = <0x423a 0x1>;
857 bits = <0 4>; 702 bits = <0 4>;
858 }; 703 };
859 }; 704 };
860 705
861 tsens0: thermal@10ab000 { !! 706 gcc: clock-controller@100000 {
862 compatible = "qcom,msm !! 707 compatible = "qcom,gcc-msm8998";
863 reg = <0x010ab000 0x10 !! 708 #clock-cells = <1>;
864 <0x010aa000 0x10 <<
865 #qcom,sensors = <14>; <<
866 interrupts = <GIC_SPI <<
867 <GIC_SPI <<
868 interrupt-names = "upl <<
869 #thermal-sensor-cells <<
870 }; <<
871 <<
872 tsens1: thermal@10ae000 { <<
873 compatible = "qcom,msm <<
874 reg = <0x010ae000 0x10 <<
875 <0x010ad000 0x10 <<
876 #qcom,sensors = <8>; <<
877 interrupts = <GIC_SPI <<
878 <GIC_SPI <<
879 interrupt-names = "upl <<
880 #thermal-sensor-cells <<
881 }; <<
882 <<
883 anoc1_smmu: iommu@1680000 { <<
884 compatible = "qcom,msm <<
885 reg = <0x01680000 0x10 <<
886 #iommu-cells = <1>; <<
887 <<
888 #global-interrupts = < <<
889 interrupts = <<
890 <GIC_SPI 364 I <<
891 <GIC_SPI 365 I <<
892 <GIC_SPI 366 I <<
893 <GIC_SPI 367 I <<
894 <GIC_SPI 368 I <<
895 <GIC_SPI 369 I <<
896 }; <<
897 <<
898 anoc2_smmu: iommu@16c0000 { <<
899 compatible = "qcom,msm <<
900 reg = <0x016c0000 0x40 <<
901 #iommu-cells = <1>; <<
902 <<
903 #global-interrupts = < <<
904 interrupts = <<
905 <GIC_SPI 373 I <<
906 <GIC_SPI 374 I <<
907 <GIC_SPI 375 I <<
908 <GIC_SPI 376 I <<
909 <GIC_SPI 377 I <<
910 <GIC_SPI 378 I <<
911 <GIC_SPI 462 I <<
912 <GIC_SPI 463 I <<
913 <GIC_SPI 464 I <<
914 <GIC_SPI 465 I <<
915 }; <<
916 <<
917 pcie0: pcie@1c00000 { <<
918 compatible = "qcom,pci <<
919 reg = <0x01c00000 0x20 <<
920 <0x1b000000 0xf1 <<
921 <0x1b000f20 0xa8 <<
922 <0x1b100000 0x10 <<
923 reg-names = "parf", "d <<
924 device_type = "pci"; <<
925 linux,pci-domain = <0> <<
926 bus-range = <0x00 0xff <<
927 #address-cells = <3>; <<
928 #size-cells = <2>; <<
929 num-lanes = <1>; <<
930 phys = <&pcie_phy>; <<
931 phy-names = "pciephy"; <<
932 status = "disabled"; <<
933 <<
934 ranges = <0x01000000 0 <<
935 <0x02000000 0 <<
936 <<
937 #interrupt-cells = <1> <<
938 interrupts = <GIC_SPI <<
939 interrupt-names = "msi <<
940 interrupt-map-mask = < <<
941 interrupt-map = <0 0 0 <<
942 <0 0 0 <<
943 <0 0 0 <<
944 <0 0 0 <<
945 <<
946 clocks = <&gcc GCC_PCI <<
947 <&gcc GCC_PCI <<
948 <&gcc GCC_PCI <<
949 <&gcc GCC_PCI <<
950 <&gcc GCC_PCI <<
951 clock-names = "pipe", <<
952 <<
953 power-domains = <&gcc <<
954 iommu-map = <0x100 &an <<
955 perst-gpios = <&tlmm 3 <<
956 <<
957 pcie@0 { <<
958 device_type = <<
959 reg = <0x0 0x0 <<
960 bus-range = <0 <<
961 <<
962 #address-cells <<
963 #size-cells = <<
964 ranges; <<
965 }; <<
966 }; <<
967 <<
968 pcie_phy: phy@1c06000 { <<
969 compatible = "qcom,msm <<
970 reg = <0x01c06000 0x10 <<
971 status = "disabled"; <<
972 <<
973 clocks = <&gcc GCC_PCI <<
974 <&gcc GCC_PCI <<
975 <&gcc GCC_PCI <<
976 <&gcc GCC_PCI <<
977 clock-names = "aux", <<
978 "cfg_ahb <<
979 "ref", <<
980 "pipe"; <<
981 <<
982 clock-output-names = " <<
983 #clock-cells = <0>; <<
984 <<
985 #phy-cells = <0>; <<
986 <<
987 resets = <&gcc GCC_PCI <<
988 reset-names = "phy", " <<
989 <<
990 vdda-phy-supply = <&vr <<
991 vdda-pll-supply = <&vr <<
992 }; <<
993 <<
994 ufshc: ufshc@1da4000 { <<
995 compatible = "qcom,msm <<
996 reg = <0x01da4000 0x25 <<
997 interrupts = <GIC_SPI <<
998 phys = <&ufsphy>; <<
999 phy-names = "ufsphy"; <<
1000 lanes-per-direction = <<
1001 power-domains = <&gcc <<
1002 status = "disabled"; <<
1003 #reset-cells = <1>; 709 #reset-cells = <1>;
1004 !! 710 #power-domain-cells = <1>;
1005 clock-names = !! 711 reg = <0x100000 0xb0000>;
1006 "core_clk", <<
1007 "bus_aggr_clk <<
1008 "iface_clk", <<
1009 "core_clk_uni <<
1010 "ref_clk", <<
1011 "tx_lane0_syn <<
1012 "rx_lane0_syn <<
1013 "rx_lane1_syn <<
1014 clocks = <<
1015 <&gcc GCC_UFS <<
1016 <&gcc GCC_AGG <<
1017 <&gcc GCC_UFS <<
1018 <&gcc GCC_UFS <<
1019 <&rpmcc RPM_S <<
1020 <&gcc GCC_UFS <<
1021 <&gcc GCC_UFS <<
1022 <&gcc GCC_UFS <<
1023 freq-table-hz = <<
1024 <50000000 200 <<
1025 <0 0>, <<
1026 <0 0>, <<
1027 <37500000 150 <<
1028 <0 0>, <<
1029 <0 0>, <<
1030 <0 0>, <<
1031 <0 0>; <<
1032 <<
1033 resets = <&gcc GCC_UF <<
1034 reset-names = "rst"; <<
1035 }; <<
1036 <<
1037 ufsphy: phy@1da7000 { <<
1038 compatible = "qcom,ms <<
1039 reg = <0x01da7000 0x1 <<
1040 <<
1041 clocks = <&rpmcc RPM_ <<
1042 <&gcc GCC_UF <<
1043 <&gcc GCC_UF <<
1044 clock-names = "ref", <<
1045 "ref_au <<
1046 "qref"; <<
1047 <<
1048 reset-names = "ufsphy <<
1049 resets = <&ufshc 0>; <<
1050 <<
1051 #phy-cells = <0>; <<
1052 status = "disabled"; <<
1053 }; <<
1054 <<
1055 tcsr_mutex: hwlock@1f40000 { <<
1056 compatible = "qcom,tc <<
1057 reg = <0x01f40000 0x2 <<
1058 #hwlock-cells = <1>; <<
1059 }; <<
1060 <<
1061 tcsr_regs_1: syscon@1f60000 { <<
1062 compatible = "qcom,ms <<
1063 reg = <0x01f60000 0x2 <<
1064 }; <<
1065 <<
1066 tcsr_regs_2: syscon@1fc0000 { <<
1067 compatible = "qcom,ms <<
1068 reg = <0x01fc0000 0x2 <<
1069 }; 712 };
1070 713
1071 tlmm: pinctrl@3400000 { 714 tlmm: pinctrl@3400000 {
1072 compatible = "qcom,ms 715 compatible = "qcom,msm8998-pinctrl";
1073 reg = <0x03400000 0xc !! 716 reg = <0x3400000 0xc00000>;
1074 interrupts = <GIC_SPI 717 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1075 gpio-ranges = <&tlmm <<
1076 gpio-controller; 718 gpio-controller;
1077 #gpio-cells = <2>; !! 719 #gpio-cells = <0x2>;
1078 interrupt-controller; 720 interrupt-controller;
1079 #interrupt-cells = <2 !! 721 #interrupt-cells = <0x2>;
1080 <<
1081 sdc2_on: sdc2-on-stat <<
1082 clk-pins { <<
1083 pins <<
1084 drive <<
1085 bias- <<
1086 }; <<
1087 <<
1088 cmd-pins { <<
1089 pins <<
1090 drive <<
1091 bias- <<
1092 }; <<
1093 <<
1094 data-pins { <<
1095 pins <<
1096 drive <<
1097 bias- <<
1098 }; <<
1099 }; <<
1100 <<
1101 sdc2_off: sdc2-off-st <<
1102 clk-pins { <<
1103 pins <<
1104 drive <<
1105 bias- <<
1106 }; <<
1107 <<
1108 cmd-pins { <<
1109 pins <<
1110 drive <<
1111 bias- <<
1112 }; <<
1113 <<
1114 data-pins { <<
1115 pins <<
1116 drive <<
1117 bias- <<
1118 }; <<
1119 }; <<
1120 <<
1121 sdc2_cd: sdc2-cd-stat <<
1122 pins = "gpio9 <<
1123 function = "g <<
1124 bias-pull-up; <<
1125 drive-strengt <<
1126 }; <<
1127 <<
1128 blsp1_uart3_on: blsp1 <<
1129 tx-pins { <<
1130 pins <<
1131 funct <<
1132 drive <<
1133 bias- <<
1134 }; <<
1135 <<
1136 rx-pins { <<
1137 pins <<
1138 funct <<
1139 drive <<
1140 bias- <<
1141 }; <<
1142 <<
1143 cts-pins { <<
1144 pins <<
1145 funct <<
1146 drive <<
1147 bias- <<
1148 }; <<
1149 <<
1150 rfr-pins { <<
1151 pins <<
1152 funct <<
1153 drive <<
1154 bias- <<
1155 }; <<
1156 }; <<
1157 <<
1158 blsp1_i2c1_default: b <<
1159 pins = "gpio2 <<
1160 function = "b <<
1161 drive-strengt <<
1162 bias-disable; <<
1163 }; <<
1164 <<
1165 blsp1_i2c1_sleep: bls <<
1166 pins = "gpio2 <<
1167 function = "b <<
1168 drive-strengt <<
1169 bias-pull-up; <<
1170 }; <<
1171 <<
1172 blsp1_i2c2_default: b <<
1173 pins = "gpio3 <<
1174 function = "b <<
1175 drive-strengt <<
1176 bias-disable; <<
1177 }; <<
1178 <<
1179 blsp1_i2c2_sleep: bls <<
1180 pins = "gpio3 <<
1181 function = "b <<
1182 drive-strengt <<
1183 bias-pull-up; <<
1184 }; <<
1185 <<
1186 blsp1_i2c3_default: b <<
1187 pins = "gpio4 <<
1188 function = "b <<
1189 drive-strengt <<
1190 bias-disable; <<
1191 }; <<
1192 <<
1193 blsp1_i2c3_sleep: bls <<
1194 pins = "gpio4 <<
1195 function = "b <<
1196 drive-strengt <<
1197 bias-pull-up; <<
1198 }; <<
1199 <<
1200 blsp1_i2c4_default: b <<
1201 pins = "gpio1 <<
1202 function = "b <<
1203 drive-strengt <<
1204 bias-disable; <<
1205 }; <<
1206 <<
1207 blsp1_i2c4_sleep: bls <<
1208 pins = "gpio1 <<
1209 function = "b <<
1210 drive-strengt <<
1211 bias-pull-up; <<
1212 }; <<
1213 <<
1214 blsp1_i2c5_default: b <<
1215 pins = "gpio8 <<
1216 function = "b <<
1217 drive-strengt <<
1218 bias-disable; <<
1219 }; <<
1220 <<
1221 blsp1_i2c5_sleep: bls <<
1222 pins = "gpio8 <<
1223 function = "b <<
1224 drive-strengt <<
1225 bias-pull-up; <<
1226 }; <<
1227 <<
1228 blsp1_i2c6_default: b <<
1229 pins = "gpio4 <<
1230 function = "b <<
1231 drive-strengt <<
1232 bias-disable; <<
1233 }; <<
1234 <<
1235 blsp1_i2c6_sleep: bls <<
1236 pins = "gpio4 <<
1237 function = "b <<
1238 drive-strengt <<
1239 bias-pull-up; <<
1240 }; <<
1241 <<
1242 blsp1_spi_b_default: <<
1243 pins = "gpio2 <<
1244 function = "b <<
1245 drive-strengt <<
1246 bias-disable; <<
1247 }; <<
1248 <<
1249 blsp1_spi1_default: b <<
1250 pins = "gpio0 <<
1251 function = "b <<
1252 drive-strengt <<
1253 bias-disable; <<
1254 }; <<
1255 <<
1256 blsp1_spi2_default: b <<
1257 pins = "gpio3 <<
1258 function = "b <<
1259 drive-strengt <<
1260 bias-disable; <<
1261 }; <<
1262 <<
1263 blsp1_spi3_default: b <<
1264 pins = "gpio4 <<
1265 function = "b <<
1266 drive-strengt <<
1267 bias-disable; <<
1268 }; <<
1269 <<
1270 blsp1_spi4_default: b <<
1271 pins = "gpio8 <<
1272 function = "b <<
1273 drive-strengt <<
1274 bias-disable; <<
1275 }; <<
1276 <<
1277 blsp1_spi5_default: b <<
1278 pins = "gpio8 <<
1279 function = "b <<
1280 drive-strengt <<
1281 bias-disable; <<
1282 }; <<
1283 <<
1284 blsp1_spi6_default: b <<
1285 pins = "gpio4 <<
1286 function = "b <<
1287 drive-strengt <<
1288 bias-disable; <<
1289 }; <<
1290 <<
1291 <<
1292 /* 6 interfaces per Q <<
1293 blsp2_i2c1_default: b <<
1294 pins = "gpio5 <<
1295 function = "b <<
1296 drive-strengt <<
1297 bias-disable; <<
1298 }; <<
1299 <<
1300 blsp2_i2c1_sleep: bls <<
1301 pins = "gpio5 <<
1302 function = "b <<
1303 drive-strengt <<
1304 bias-pull-up; <<
1305 }; <<
1306 <<
1307 blsp2_i2c2_default: b <<
1308 pins = "gpio6 <<
1309 function = "b <<
1310 drive-strengt <<
1311 bias-disable; <<
1312 }; <<
1313 <<
1314 blsp2_i2c2_sleep: bls <<
1315 pins = "gpio6 <<
1316 function = "b <<
1317 drive-strengt <<
1318 bias-pull-up; <<
1319 }; <<
1320 <<
1321 blsp2_i2c3_default: b <<
1322 pins = "gpio5 <<
1323 function = "b <<
1324 drive-strengt <<
1325 bias-disable; <<
1326 }; <<
1327 <<
1328 blsp2_i2c3_sleep: bls <<
1329 pins = "gpio5 <<
1330 function = "b <<
1331 drive-strengt <<
1332 bias-pull-up; <<
1333 }; <<
1334 <<
1335 blsp2_i2c4_default: b <<
1336 pins = "gpio6 <<
1337 function = "b <<
1338 drive-strengt <<
1339 bias-disable; <<
1340 }; <<
1341 <<
1342 blsp2_i2c4_sleep: bls <<
1343 pins = "gpio6 <<
1344 function = "b <<
1345 drive-strengt <<
1346 bias-pull-up; <<
1347 }; <<
1348 <<
1349 blsp2_i2c5_default: b <<
1350 pins = "gpio6 <<
1351 function = "b <<
1352 drive-strengt <<
1353 bias-disable; <<
1354 }; <<
1355 <<
1356 blsp2_i2c5_sleep: bls <<
1357 pins = "gpio6 <<
1358 function = "b <<
1359 drive-strengt <<
1360 bias-pull-up; <<
1361 }; <<
1362 <<
1363 blsp2_i2c6_default: b <<
1364 pins = "gpio8 <<
1365 function = "b <<
1366 drive-strengt <<
1367 bias-disable; <<
1368 }; <<
1369 <<
1370 blsp2_i2c6_sleep: bls <<
1371 pins = "gpio8 <<
1372 function = "b <<
1373 drive-strengt <<
1374 bias-pull-up; <<
1375 }; <<
1376 <<
1377 blsp2_spi1_default: b <<
1378 pins = "gpio5 <<
1379 function = "b <<
1380 drive-strengt <<
1381 bias-disable; <<
1382 }; <<
1383 <<
1384 blsp2_spi2_default: b <<
1385 pins = "gpio4 <<
1386 function = "b <<
1387 drive-strengt <<
1388 bias-disable; <<
1389 }; <<
1390 <<
1391 blsp2_spi3_default: b <<
1392 pins = "gpio4 <<
1393 function = "b <<
1394 drive-strengt <<
1395 bias-disable; <<
1396 }; <<
1397 <<
1398 blsp2_spi4_default: b <<
1399 pins = "gpio6 <<
1400 function = "b <<
1401 drive-strengt <<
1402 bias-disable; <<
1403 }; <<
1404 <<
1405 blsp2_spi5_default: b <<
1406 pins = "gpio5 <<
1407 function = "b <<
1408 drive-strengt <<
1409 bias-disable; <<
1410 }; <<
1411 <<
1412 blsp2_spi6_default: b <<
1413 pins = "gpio8 <<
1414 function = "b <<
1415 drive-strengt <<
1416 bias-disable; <<
1417 }; <<
1418 }; <<
1419 <<
1420 remoteproc_mss: remoteproc@40 <<
1421 compatible = "qcom,ms <<
1422 reg = <0x04080000 0x1 <<
1423 reg-names = "qdsp6", <<
1424 <<
1425 interrupts-extended = <<
1426 <&intc GIC_SP <<
1427 <&modem_smp2p <<
1428 <&modem_smp2p <<
1429 <&modem_smp2p <<
1430 <&modem_smp2p <<
1431 <&modem_smp2p <<
1432 interrupt-names = "wd <<
1433 "ha <<
1434 "sh <<
1435 <<
1436 clocks = <&gcc GCC_MS <<
1437 <&gcc GCC_BI <<
1438 <&gcc GCC_BO <<
1439 <&gcc GCC_MS <<
1440 <&gcc GCC_MS <<
1441 <&gcc GCC_MS <<
1442 <&rpmcc RPM_ <<
1443 <&rpmcc RPM_ <<
1444 clock-names = "iface" <<
1445 "snoc_a <<
1446 <<
1447 qcom,smem-states = <& <<
1448 qcom,smem-state-names <<
1449 <<
1450 resets = <&gcc GCC_MS <<
1451 reset-names = "mss_re <<
1452 <<
1453 qcom,halt-regs = <&tc <<
1454 <<
1455 power-domains = <&rpm <<
1456 <&rpm <<
1457 power-domain-names = <<
1458 <<
1459 status = "disabled"; <<
1460 <<
1461 mba { <<
1462 memory-region <<
1463 }; <<
1464 <<
1465 mpss { <<
1466 memory-region <<
1467 }; <<
1468 <<
1469 metadata { <<
1470 memory-region <<
1471 }; <<
1472 <<
1473 glink-edge { <<
1474 interrupts = <<
1475 label = "mode <<
1476 qcom,remote-p <<
1477 mboxes = <&ap <<
1478 }; <<
1479 }; <<
1480 <<
1481 adreno_gpu: gpu@5000000 { <<
1482 compatible = "qcom,ad <<
1483 reg = <0x05000000 0x4 <<
1484 reg-names = "kgsl_3d0 <<
1485 <<
1486 clocks = <&gcc GCC_GP <<
1487 <&gpucc RBBMT <<
1488 <&gcc GCC_BIM <<
1489 <&gcc GCC_GPU <<
1490 <&gpucc RBCPR <<
1491 <&gpucc GFX3D <<
1492 clock-names = "iface" <<
1493 "rbbmtimer", <<
1494 "mem", <<
1495 "mem_iface", <<
1496 "rbcpr", <<
1497 "core"; <<
1498 <<
1499 interrupts = <GIC_SPI <<
1500 iommus = <&adreno_smm <<
1501 operating-points-v2 = <<
1502 power-domains = <&rpm <<
1503 status = "disabled"; <<
1504 <<
1505 gpu_opp_table: opp-ta <<
1506 compatible = <<
1507 opp-710000097 <<
1508 opp-h <<
1509 opp-l <<
1510 opp-s <<
1511 }; <<
1512 <<
1513 opp-670000048 <<
1514 opp-h <<
1515 opp-l <<
1516 opp-s <<
1517 }; <<
1518 <<
1519 opp-596000097 <<
1520 opp-h <<
1521 opp-l <<
1522 opp-s <<
1523 }; <<
1524 <<
1525 opp-515000097 <<
1526 opp-h <<
1527 opp-l <<
1528 opp-s <<
1529 }; <<
1530 <<
1531 opp-414000000 <<
1532 opp-h <<
1533 opp-l <<
1534 opp-s <<
1535 }; <<
1536 <<
1537 opp-342000000 <<
1538 opp-h <<
1539 opp-l <<
1540 opp-s <<
1541 }; <<
1542 <<
1543 opp-257000000 <<
1544 opp-h <<
1545 opp-l <<
1546 opp-s <<
1547 }; <<
1548 }; <<
1549 }; <<
1550 <<
1551 adreno_smmu: iommu@5040000 { <<
1552 compatible = "qcom,ms <<
1553 reg = <0x05040000 0x1 <<
1554 clocks = <&gcc GCC_GP <<
1555 <&gcc GCC_BI <<
1556 <&gcc GCC_GP <<
1557 clock-names = "iface" <<
1558 <<
1559 #global-interrupts = <<
1560 #iommu-cells = <1>; <<
1561 interrupts = <<
1562 <GIC_SPI 329 <<
1563 <GIC_SPI 330 <<
1564 <GIC_SPI 331 <<
1565 /* <<
1566 * GPU-GX GDSC's pare <<
1567 * GPU-CX for SMMU bu <<
1568 * Contemporarily, we <<
1569 * domain in the Adre <<
1570 * Enable GPU CX/GX G <<
1571 * SoC VDDMX RPM Powe <<
1572 */ <<
1573 power-domains = <&gpu <<
1574 }; <<
1575 <<
1576 gpucc: clock-controller@50650 <<
1577 compatible = "qcom,ms <<
1578 #clock-cells = <1>; <<
1579 #reset-cells = <1>; <<
1580 #power-domain-cells = <<
1581 reg = <0x05065000 0x9 <<
1582 <<
1583 clocks = <&rpmcc RPM_ <<
1584 <&gcc GCC_GP <<
1585 clock-names = "xo", <<
1586 "gpll0" <<
1587 }; <<
1588 <<
1589 lpass_q6_smmu: iommu@5100000 <<
1590 compatible = "qcom,ms <<
1591 reg = <0x05100000 0x4 <<
1592 clocks = <&gcc HLOS1_ <<
1593 clock-names = "bus"; <<
1594 <<
1595 #global-interrupts = <<
1596 #iommu-cells = <1>; <<
1597 interrupts = <<
1598 <GIC_SPI 226 <<
1599 <GIC_SPI 393 <<
1600 <GIC_SPI 394 <<
1601 <GIC_SPI 395 <<
1602 <GIC_SPI 396 <<
1603 <GIC_SPI 397 <<
1604 <GIC_SPI 398 <<
1605 <GIC_SPI 399 <<
1606 <GIC_SPI 400 <<
1607 <GIC_SPI 401 <<
1608 <GIC_SPI 402 <<
1609 <GIC_SPI 403 <<
1610 <GIC_SPI 137 <<
1611 <<
1612 power-domains = <&gcc <<
1613 status = "disabled"; <<
1614 }; <<
1615 <<
1616 remoteproc_slpi: remoteproc@5 <<
1617 compatible = "qcom,ms <<
1618 reg = <0x05800000 0x4 <<
1619 <<
1620 interrupts-extended = <<
1621 <<
1622 <<
1623 <<
1624 <<
1625 interrupt-names = "wd <<
1626 "ha <<
1627 <<
1628 px-supply = <&vreg_lv <<
1629 <<
1630 clocks = <&rpmcc RPM_ <<
1631 clock-names = "xo"; <<
1632 <<
1633 memory-region = <&slp <<
1634 <<
1635 qcom,smem-states = <& <<
1636 qcom,smem-state-names <<
1637 <<
1638 power-domains = <&rpm <<
1639 power-domain-names = <<
1640 <<
1641 status = "disabled"; <<
1642 <<
1643 glink-edge { <<
1644 interrupts = <<
1645 label = "dsps <<
1646 qcom,remote-p <<
1647 mboxes = <&ap <<
1648 }; <<
1649 }; <<
1650 <<
1651 stm: stm@6002000 { <<
1652 compatible = "arm,cor <<
1653 reg = <0x06002000 0x1 <<
1654 <0x16280000 0x1 <<
1655 reg-names = "stm-base <<
1656 status = "disabled"; <<
1657 <<
1658 clocks = <&rpmcc RPM_ <<
1659 clock-names = "apb_pc <<
1660 <<
1661 out-ports { <<
1662 port { <<
1663 stm_o <<
1664 <<
1665 }; <<
1666 }; <<
1667 }; <<
1668 }; <<
1669 <<
1670 funnel1: funnel@6041000 { <<
1671 compatible = "arm,cor <<
1672 reg = <0x06041000 0x1 <<
1673 status = "disabled"; <<
1674 <<
1675 clocks = <&rpmcc RPM_ <<
1676 clock-names = "apb_pc <<
1677 <<
1678 out-ports { <<
1679 port { <<
1680 funne <<
1681 <<
1682 <<
1683 }; <<
1684 }; <<
1685 }; <<
1686 <<
1687 in-ports { <<
1688 #address-cell <<
1689 #size-cells = <<
1690 <<
1691 port@7 { <<
1692 reg = <<
1693 funne <<
1694 <<
1695 }; <<
1696 }; <<
1697 }; <<
1698 }; <<
1699 <<
1700 funnel2: funnel@6042000 { <<
1701 compatible = "arm,cor <<
1702 reg = <0x06042000 0x1 <<
1703 status = "disabled"; <<
1704 <<
1705 clocks = <&rpmcc RPM_ <<
1706 clock-names = "apb_pc <<
1707 <<
1708 out-ports { <<
1709 port { <<
1710 funne <<
1711 <<
1712 <<
1713 }; <<
1714 }; <<
1715 }; <<
1716 <<
1717 in-ports { <<
1718 #address-cell <<
1719 #size-cells = <<
1720 <<
1721 port@6 { <<
1722 reg = <<
1723 funne <<
1724 <<
1725 <<
1726 }; <<
1727 }; <<
1728 }; <<
1729 }; <<
1730 <<
1731 funnel3: funnel@6045000 { <<
1732 compatible = "arm,cor <<
1733 reg = <0x06045000 0x1 <<
1734 status = "disabled"; <<
1735 <<
1736 clocks = <&rpmcc RPM_ <<
1737 clock-names = "apb_pc <<
1738 <<
1739 out-ports { <<
1740 port { <<
1741 merge <<
1742 <<
1743 <<
1744 }; <<
1745 }; <<
1746 }; <<
1747 <<
1748 in-ports { <<
1749 #address-cell <<
1750 #size-cells = <<
1751 <<
1752 port@0 { <<
1753 reg = <<
1754 merge <<
1755 <<
1756 <<
1757 }; <<
1758 }; <<
1759 <<
1760 port@1 { <<
1761 reg = <<
1762 merge <<
1763 <<
1764 <<
1765 }; <<
1766 }; <<
1767 }; <<
1768 }; <<
1769 <<
1770 replicator1: replicator@60460 <<
1771 compatible = "arm,cor <<
1772 reg = <0x06046000 0x1 <<
1773 status = "disabled"; <<
1774 <<
1775 clocks = <&rpmcc RPM_ <<
1776 clock-names = "apb_pc <<
1777 <<
1778 out-ports { <<
1779 port { <<
1780 repli <<
1781 <<
1782 }; <<
1783 }; <<
1784 }; <<
1785 <<
1786 in-ports { <<
1787 port { <<
1788 repli <<
1789 <<
1790 }; <<
1791 }; <<
1792 }; <<
1793 }; <<
1794 <<
1795 etf: etf@6047000 { <<
1796 compatible = "arm,cor <<
1797 reg = <0x06047000 0x1 <<
1798 status = "disabled"; <<
1799 <<
1800 clocks = <&rpmcc RPM_ <<
1801 clock-names = "apb_pc <<
1802 <<
1803 out-ports { <<
1804 port { <<
1805 etf_o <<
1806 <<
1807 <<
1808 }; <<
1809 }; <<
1810 }; <<
1811 <<
1812 in-ports { <<
1813 port { <<
1814 etf_i <<
1815 <<
1816 <<
1817 }; <<
1818 }; <<
1819 }; <<
1820 }; <<
1821 <<
1822 etr: etr@6048000 { <<
1823 compatible = "arm,cor <<
1824 reg = <0x06048000 0x1 <<
1825 status = "disabled"; <<
1826 <<
1827 clocks = <&rpmcc RPM_ <<
1828 clock-names = "apb_pc <<
1829 arm,scatter-gather; <<
1830 <<
1831 in-ports { <<
1832 port { <<
1833 etr_i <<
1834 <<
1835 <<
1836 }; <<
1837 }; <<
1838 }; <<
1839 }; <<
1840 <<
1841 etm1: etm@7840000 { <<
1842 compatible = "arm,cor <<
1843 reg = <0x07840000 0x1 <<
1844 status = "disabled"; <<
1845 <<
1846 clocks = <&rpmcc RPM_ <<
1847 clock-names = "apb_pc <<
1848 <<
1849 cpu = <&CPU0>; <<
1850 <<
1851 out-ports { <<
1852 port { <<
1853 etm0_ <<
1854 <<
1855 <<
1856 }; <<
1857 }; <<
1858 }; <<
1859 }; <<
1860 <<
1861 etm2: etm@7940000 { <<
1862 compatible = "arm,cor <<
1863 reg = <0x07940000 0x1 <<
1864 status = "disabled"; <<
1865 <<
1866 clocks = <&rpmcc RPM_ <<
1867 clock-names = "apb_pc <<
1868 <<
1869 cpu = <&CPU1>; <<
1870 <<
1871 out-ports { <<
1872 port { <<
1873 etm1_ <<
1874 <<
1875 <<
1876 }; <<
1877 }; <<
1878 }; <<
1879 }; <<
1880 <<
1881 etm3: etm@7a40000 { <<
1882 compatible = "arm,cor <<
1883 reg = <0x07a40000 0x1 <<
1884 status = "disabled"; <<
1885 <<
1886 clocks = <&rpmcc RPM_ <<
1887 clock-names = "apb_pc <<
1888 <<
1889 cpu = <&CPU2>; <<
1890 <<
1891 out-ports { <<
1892 port { <<
1893 etm2_ <<
1894 <<
1895 <<
1896 }; <<
1897 }; <<
1898 }; <<
1899 }; <<
1900 <<
1901 etm4: etm@7b40000 { <<
1902 compatible = "arm,cor <<
1903 reg = <0x07b40000 0x1 <<
1904 status = "disabled"; <<
1905 <<
1906 clocks = <&rpmcc RPM_ <<
1907 clock-names = "apb_pc <<
1908 <<
1909 cpu = <&CPU3>; <<
1910 <<
1911 out-ports { <<
1912 port { <<
1913 etm3_ <<
1914 <<
1915 <<
1916 }; <<
1917 }; <<
1918 }; <<
1919 }; <<
1920 <<
1921 funnel4: funnel@7b60000 { /* <<
1922 compatible = "arm,cor <<
1923 reg = <0x07b60000 0x1 <<
1924 status = "disabled"; <<
1925 <<
1926 clocks = <&rpmcc RPM_ <<
1927 clock-names = "apb_pc <<
1928 <<
1929 out-ports { <<
1930 port { <<
1931 apss_ <<
1932 <<
1933 <<
1934 }; <<
1935 }; <<
1936 }; <<
1937 <<
1938 in-ports { <<
1939 #address-cell <<
1940 #size-cells = <<
1941 <<
1942 port@0 { <<
1943 reg = <<
1944 apss_ <<
1945 <<
1946 <<
1947 }; <<
1948 }; <<
1949 <<
1950 port@1 { <<
1951 reg = <<
1952 apss_ <<
1953 <<
1954 <<
1955 }; <<
1956 }; <<
1957 <<
1958 port@2 { <<
1959 reg = <<
1960 apss_ <<
1961 <<
1962 <<
1963 }; <<
1964 }; <<
1965 <<
1966 port@3 { <<
1967 reg = <<
1968 apss_ <<
1969 <<
1970 <<
1971 }; <<
1972 }; <<
1973 <<
1974 port@4 { <<
1975 reg = <<
1976 apss_ <<
1977 <<
1978 <<
1979 }; <<
1980 }; <<
1981 <<
1982 port@5 { <<
1983 reg = <<
1984 apss_ <<
1985 <<
1986 <<
1987 }; <<
1988 }; <<
1989 <<
1990 port@6 { <<
1991 reg = <<
1992 apss_ <<
1993 <<
1994 <<
1995 }; <<
1996 }; <<
1997 <<
1998 port@7 { <<
1999 reg = <<
2000 apss_ <<
2001 <<
2002 <<
2003 }; <<
2004 }; <<
2005 }; <<
2006 }; <<
2007 <<
2008 funnel5: funnel@7b70000 { <<
2009 compatible = "arm,cor <<
2010 reg = <0x07b70000 0x1 <<
2011 status = "disabled"; <<
2012 <<
2013 clocks = <&rpmcc RPM_ <<
2014 clock-names = "apb_pc <<
2015 <<
2016 out-ports { <<
2017 port { <<
2018 apss_ <<
2019 <<
2020 <<
2021 }; <<
2022 }; <<
2023 }; <<
2024 <<
2025 in-ports { <<
2026 port { <<
2027 apss_ <<
2028 <<
2029 <<
2030 }; <<
2031 }; <<
2032 }; <<
2033 }; <<
2034 <<
2035 etm5: etm@7c40000 { <<
2036 compatible = "arm,cor <<
2037 reg = <0x07c40000 0x1 <<
2038 status = "disabled"; <<
2039 <<
2040 clocks = <&rpmcc RPM_ <<
2041 clock-names = "apb_pc <<
2042 <<
2043 cpu = <&CPU4>; <<
2044 <<
2045 out-ports { <<
2046 port { <<
2047 etm4_ <<
2048 <<
2049 }; <<
2050 }; <<
2051 }; <<
2052 }; <<
2053 <<
2054 etm6: etm@7d40000 { <<
2055 compatible = "arm,cor <<
2056 reg = <0x07d40000 0x1 <<
2057 status = "disabled"; <<
2058 <<
2059 clocks = <&rpmcc RPM_ <<
2060 clock-names = "apb_pc <<
2061 <<
2062 cpu = <&CPU5>; <<
2063 <<
2064 out-ports { <<
2065 port { <<
2066 etm5_ <<
2067 <<
2068 }; <<
2069 }; <<
2070 }; <<
2071 }; <<
2072 <<
2073 etm7: etm@7e40000 { <<
2074 compatible = "arm,cor <<
2075 reg = <0x07e40000 0x1 <<
2076 status = "disabled"; <<
2077 <<
2078 clocks = <&rpmcc RPM_ <<
2079 clock-names = "apb_pc <<
2080 <<
2081 cpu = <&CPU6>; <<
2082 <<
2083 out-ports { <<
2084 port { <<
2085 etm6_ <<
2086 <<
2087 }; <<
2088 }; <<
2089 }; <<
2090 }; <<
2091 <<
2092 etm8: etm@7f40000 { <<
2093 compatible = "arm,cor <<
2094 reg = <0x07f40000 0x1 <<
2095 status = "disabled"; <<
2096 <<
2097 clocks = <&rpmcc RPM_ <<
2098 clock-names = "apb_pc <<
2099 <<
2100 cpu = <&CPU7>; <<
2101 <<
2102 out-ports { <<
2103 port { <<
2104 etm7_ <<
2105 <<
2106 }; <<
2107 }; <<
2108 }; <<
2109 }; <<
2110 <<
2111 sram@290000 { <<
2112 compatible = "qcom,rp <<
2113 reg = <0x00290000 0x1 <<
2114 }; 722 };
2115 723
2116 spmi_bus: spmi@800f000 { 724 spmi_bus: spmi@800f000 {
2117 compatible = "qcom,sp 725 compatible = "qcom,spmi-pmic-arb";
2118 reg = <0x0800f000 0x1 !! 726 reg = <0x800f000 0x1000>,
2119 <0x08400000 0x1 !! 727 <0x8400000 0x1000000>,
2120 <0x09400000 0x1 !! 728 <0x9400000 0x1000000>,
2121 <0x0a400000 0x2 !! 729 <0xa400000 0x220000>,
2122 <0x0800a000 0x3 !! 730 <0x800a000 0x3000>;
2123 reg-names = "core", " 731 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
2124 interrupt-names = "pe 732 interrupt-names = "periph_irq";
2125 interrupts = <GIC_SPI 733 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
2126 qcom,ee = <0>; 734 qcom,ee = <0>;
2127 qcom,channel = <0>; 735 qcom,channel = <0>;
2128 #address-cells = <2>; 736 #address-cells = <2>;
2129 #size-cells = <0>; 737 #size-cells = <0>;
2130 interrupt-controller; 738 interrupt-controller;
2131 #interrupt-cells = <4 739 #interrupt-cells = <4>;
>> 740 cell-index = <0>;
>> 741 };
>> 742
>> 743 tsens0: thermal@10ab000 {
>> 744 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
>> 745 reg = <0x10ab000 0x1000>, /* TM */
>> 746 <0x10aa000 0x1000>; /* SROT */
>> 747
>> 748 #qcom,sensors = <14>;
>> 749 #thermal-sensor-cells = <1>;
>> 750 };
>> 751
>> 752 tsens1: thermal@10ae000 {
>> 753 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
>> 754 reg = <0x10ae000 0x1000>, /* TM */
>> 755 <0x10ad000 0x1000>; /* SROT */
>> 756
>> 757 #qcom,sensors = <8>;
>> 758 #thermal-sensor-cells = <1>;
>> 759 };
>> 760
>> 761 tcsr_mutex_regs: syscon@1f40000 {
>> 762 compatible = "syscon";
>> 763 reg = <0x1f40000 0x20000>;
>> 764 };
>> 765
>> 766 apcs_glb: mailbox@9820000 {
>> 767 compatible = "qcom,msm8998-apcs-hmss-global";
>> 768 reg = <0x17911000 0x1000>;
>> 769
>> 770 #mbox-cells = <1>;
2132 }; 771 };
2133 772
2134 usb3: usb@a8f8800 { 773 usb3: usb@a8f8800 {
2135 compatible = "qcom,ms 774 compatible = "qcom,msm8998-dwc3", "qcom,dwc3";
2136 reg = <0x0a8f8800 0x4 775 reg = <0x0a8f8800 0x400>;
2137 status = "disabled"; 776 status = "disabled";
2138 #address-cells = <1>; 777 #address-cells = <1>;
2139 #size-cells = <1>; 778 #size-cells = <1>;
2140 ranges; 779 ranges;
2141 780
2142 clocks = <&gcc GCC_CF 781 clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>,
2143 <&gcc GCC_US 782 <&gcc GCC_USB30_MASTER_CLK>,
2144 <&gcc GCC_AG 783 <&gcc GCC_AGGRE1_USB3_AXI_CLK>,
2145 <&gcc GCC_US !! 784 <&gcc GCC_USB30_MOCK_UTMI_CLK>,
2146 <&gcc GCC_US !! 785 <&gcc GCC_USB30_SLEEP_CLK>;
2147 clock-names = "cfg_no !! 786 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
2148 "core", !! 787 "sleep";
2149 "iface" <<
2150 "sleep" <<
2151 "mock_u <<
2152 788
2153 assigned-clocks = <&g 789 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
2154 <&g 790 <&gcc GCC_USB30_MASTER_CLK>;
2155 assigned-clock-rates 791 assigned-clock-rates = <19200000>, <120000000>;
2156 792
2157 interrupts = <GIC_SPI !! 793 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
2158 <GIC_SPI <<
2159 <GIC_SPI 794 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
2160 interrupt-names = "pw !! 795 interrupt-names = "hs_phy_irq", "ss_phy_irq";
2161 "qu <<
2162 "ss <<
2163 796
2164 power-domains = <&gcc 797 power-domains = <&gcc USB_30_GDSC>;
2165 798
2166 resets = <&gcc GCC_US 799 resets = <&gcc GCC_USB_30_BCR>;
2167 800
2168 usb3_dwc3: usb@a80000 !! 801 usb3_dwc3: dwc3@a800000 {
2169 compatible = 802 compatible = "snps,dwc3";
2170 reg = <0x0a80 803 reg = <0x0a800000 0xcd00>;
2171 interrupts = 804 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
2172 snps,dis_u2_s 805 snps,dis_u2_susphy_quirk;
2173 snps,dis_enbl 806 snps,dis_enblslpm_quirk;
2174 snps,parkmode !! 807 phys = <&qusb2phy>, <&usb1_ssphy>;
2175 phys = <&qusb <<
2176 phy-names = " 808 phy-names = "usb2-phy", "usb3-phy";
2177 snps,has-lpm- 809 snps,has-lpm-erratum;
2178 snps,hird-thr 810 snps,hird-threshold = /bits/ 8 <0x10>;
2179 }; 811 };
2180 }; 812 };
2181 813
2182 usb3phy: phy@c010000 { 814 usb3phy: phy@c010000 {
2183 compatible = "qcom,ms 815 compatible = "qcom,msm8998-qmp-usb3-phy";
2184 reg = <0x0c010000 0x1 !! 816 reg = <0x0c010000 0x18c>;
>> 817 status = "disabled";
>> 818 #clock-cells = <1>;
>> 819 #address-cells = <1>;
>> 820 #size-cells = <1>;
>> 821 ranges;
2185 822
2186 clocks = <&gcc GCC_US 823 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
2187 <&gcc GCC_US <<
2188 <&gcc GCC_US 824 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2189 <&gcc GCC_US !! 825 <&gcc GCC_USB3_CLKREF_CLK>;
2190 clock-names = "aux", !! 826 clock-names = "aux", "cfg_ahb", "ref";
2191 "ref", <<
2192 "cfg_ah <<
2193 "pipe"; <<
2194 clock-output-names = <<
2195 #clock-cells = <0>; <<
2196 #phy-cells = <0>; <<
2197 827
2198 resets = <&gcc GCC_US 828 resets = <&gcc GCC_USB3_PHY_BCR>,
2199 <&gcc GCC_US 829 <&gcc GCC_USB3PHY_PHY_BCR>;
2200 reset-names = "phy", !! 830 reset-names = "phy", "common";
2201 "phy_ph <<
2202 <<
2203 qcom,tcsr-reg = <&tcs <<
2204 831
2205 status = "disabled"; !! 832 usb1_ssphy: lane@c010200 {
>> 833 reg = <0xc010200 0x128>,
>> 834 <0xc010400 0x200>,
>> 835 <0xc010c00 0x20c>,
>> 836 <0xc010600 0x128>,
>> 837 <0xc010800 0x200>;
>> 838 #phy-cells = <0>;
>> 839 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
>> 840 clock-names = "pipe0";
>> 841 clock-output-names = "usb3_phy_pipe_clk_src";
>> 842 };
2206 }; 843 };
2207 844
2208 qusb2phy: phy@c012000 { 845 qusb2phy: phy@c012000 {
2209 compatible = "qcom,ms 846 compatible = "qcom,msm8998-qusb2-phy";
2210 reg = <0x0c012000 0x2 847 reg = <0x0c012000 0x2a8>;
2211 status = "disabled"; 848 status = "disabled";
2212 #phy-cells = <0>; 849 #phy-cells = <0>;
2213 850
2214 clocks = <&gcc GCC_US 851 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2215 <&gcc GCC_RX 852 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
2216 clock-names = "cfg_ah 853 clock-names = "cfg_ahb", "ref";
2217 854
2218 resets = <&gcc GCC_QU 855 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2219 856
2220 nvmem-cells = <&qusb2 857 nvmem-cells = <&qusb2_hstx_trim>;
2221 }; 858 };
2222 859
2223 sdhc2: mmc@c0a4900 { !! 860 sdhc2: sdhci@c0a4900 {
2224 compatible = "qcom,ms !! 861 compatible = "qcom,sdhci-msm-v4";
2225 reg = <0x0c0a4900 0x3 !! 862 reg = <0xc0a4900 0x314>, <0xc0a4000 0x800>;
2226 reg-names = "hc", "co !! 863 reg-names = "hc_mem", "core_mem";
2227 864
2228 interrupts = <GIC_SPI 865 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
2229 <GIC_SPI 866 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
2230 interrupt-names = "hc 867 interrupt-names = "hc_irq", "pwr_irq";
2231 868
2232 clock-names = "iface" 869 clock-names = "iface", "core", "xo";
2233 clocks = <&gcc GCC_SD 870 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2234 <&gcc GCC_SD 871 <&gcc GCC_SDCC2_APPS_CLK>,
2235 <&rpmcc RPM_ !! 872 <&xo>;
2236 bus-width = <4>; 873 bus-width = <4>;
2237 status = "disabled"; 874 status = "disabled";
2238 }; 875 };
2239 876
2240 blsp1_dma: dma-controller@c14 <<
2241 compatible = "qcom,ba <<
2242 reg = <0x0c144000 0x2 <<
2243 interrupts = <GIC_SPI <<
2244 clocks = <&gcc GCC_BL <<
2245 clock-names = "bam_cl <<
2246 #dma-cells = <1>; <<
2247 qcom,ee = <0>; <<
2248 qcom,controlled-remot <<
2249 num-channels = <18>; <<
2250 qcom,num-ees = <4>; <<
2251 }; <<
2252 <<
2253 blsp1_uart3: serial@c171000 { <<
2254 compatible = "qcom,ms <<
2255 reg = <0x0c171000 0x1 <<
2256 interrupts = <GIC_SPI <<
2257 clocks = <&gcc GCC_BL <<
2258 <&gcc GCC_BL <<
2259 clock-names = "core", <<
2260 dmas = <&blsp1_dma 4> <<
2261 dma-names = "tx", "rx <<
2262 pinctrl-names = "defa <<
2263 pinctrl-0 = <&blsp1_u <<
2264 status = "disabled"; <<
2265 }; <<
2266 <<
2267 blsp1_i2c1: i2c@c175000 { 877 blsp1_i2c1: i2c@c175000 {
2268 compatible = "qcom,i2 878 compatible = "qcom,i2c-qup-v2.2.1";
2269 reg = <0x0c175000 0x6 879 reg = <0x0c175000 0x600>;
2270 interrupts = <GIC_SPI 880 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
2271 881
2272 clocks = <&gcc GCC_BL 882 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
2273 <&gcc GCC_BL 883 <&gcc GCC_BLSP1_AHB_CLK>;
2274 clock-names = "core", 884 clock-names = "core", "iface";
2275 dmas = <&blsp1_dma 6> <<
2276 dma-names = "tx", "rx <<
2277 pinctrl-names = "defa <<
2278 pinctrl-0 = <&blsp1_i <<
2279 pinctrl-1 = <&blsp1_i <<
2280 clock-frequency = <40 885 clock-frequency = <400000>;
2281 886
2282 status = "disabled"; 887 status = "disabled";
2283 #address-cells = <1>; 888 #address-cells = <1>;
2284 #size-cells = <0>; 889 #size-cells = <0>;
2285 }; 890 };
2286 891
2287 blsp1_i2c2: i2c@c176000 { 892 blsp1_i2c2: i2c@c176000 {
2288 compatible = "qcom,i2 893 compatible = "qcom,i2c-qup-v2.2.1";
2289 reg = <0x0c176000 0x6 894 reg = <0x0c176000 0x600>;
2290 interrupts = <GIC_SPI 895 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
2291 896
2292 clocks = <&gcc GCC_BL 897 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
2293 <&gcc GCC_BL 898 <&gcc GCC_BLSP1_AHB_CLK>;
2294 clock-names = "core", 899 clock-names = "core", "iface";
2295 dmas = <&blsp1_dma 8> <<
2296 dma-names = "tx", "rx <<
2297 pinctrl-names = "defa <<
2298 pinctrl-0 = <&blsp1_i <<
2299 pinctrl-1 = <&blsp1_i <<
2300 clock-frequency = <40 900 clock-frequency = <400000>;
2301 901
2302 status = "disabled"; 902 status = "disabled";
2303 #address-cells = <1>; 903 #address-cells = <1>;
2304 #size-cells = <0>; 904 #size-cells = <0>;
2305 }; 905 };
2306 906
2307 blsp1_i2c3: i2c@c177000 { 907 blsp1_i2c3: i2c@c177000 {
2308 compatible = "qcom,i2 908 compatible = "qcom,i2c-qup-v2.2.1";
2309 reg = <0x0c177000 0x6 909 reg = <0x0c177000 0x600>;
2310 interrupts = <GIC_SPI 910 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
2311 911
2312 clocks = <&gcc GCC_BL 912 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
2313 <&gcc GCC_BL 913 <&gcc GCC_BLSP1_AHB_CLK>;
2314 clock-names = "core", 914 clock-names = "core", "iface";
2315 dmas = <&blsp1_dma 10 <<
2316 dma-names = "tx", "rx <<
2317 pinctrl-names = "defa <<
2318 pinctrl-0 = <&blsp1_i <<
2319 pinctrl-1 = <&blsp1_i <<
2320 clock-frequency = <40 915 clock-frequency = <400000>;
2321 916
2322 status = "disabled"; 917 status = "disabled";
2323 #address-cells = <1>; 918 #address-cells = <1>;
2324 #size-cells = <0>; 919 #size-cells = <0>;
2325 }; 920 };
2326 921
2327 blsp1_i2c4: i2c@c178000 { 922 blsp1_i2c4: i2c@c178000 {
2328 compatible = "qcom,i2 923 compatible = "qcom,i2c-qup-v2.2.1";
2329 reg = <0x0c178000 0x6 924 reg = <0x0c178000 0x600>;
2330 interrupts = <GIC_SPI 925 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
2331 926
2332 clocks = <&gcc GCC_BL 927 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
2333 <&gcc GCC_BL 928 <&gcc GCC_BLSP1_AHB_CLK>;
2334 clock-names = "core", 929 clock-names = "core", "iface";
2335 dmas = <&blsp1_dma 12 <<
2336 dma-names = "tx", "rx <<
2337 pinctrl-names = "defa <<
2338 pinctrl-0 = <&blsp1_i <<
2339 pinctrl-1 = <&blsp1_i <<
2340 clock-frequency = <40 930 clock-frequency = <400000>;
2341 931
2342 status = "disabled"; 932 status = "disabled";
2343 #address-cells = <1>; 933 #address-cells = <1>;
2344 #size-cells = <0>; 934 #size-cells = <0>;
2345 }; 935 };
2346 936
2347 blsp1_i2c5: i2c@c179000 { 937 blsp1_i2c5: i2c@c179000 {
2348 compatible = "qcom,i2 938 compatible = "qcom,i2c-qup-v2.2.1";
2349 reg = <0x0c179000 0x6 939 reg = <0x0c179000 0x600>;
2350 interrupts = <GIC_SPI 940 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
2351 941
2352 clocks = <&gcc GCC_BL 942 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
2353 <&gcc GCC_BL 943 <&gcc GCC_BLSP1_AHB_CLK>;
2354 clock-names = "core", 944 clock-names = "core", "iface";
2355 dmas = <&blsp1_dma 14 <<
2356 dma-names = "tx", "rx <<
2357 pinctrl-names = "defa <<
2358 pinctrl-0 = <&blsp1_i <<
2359 pinctrl-1 = <&blsp1_i <<
2360 clock-frequency = <40 945 clock-frequency = <400000>;
2361 946
2362 status = "disabled"; 947 status = "disabled";
2363 #address-cells = <1>; 948 #address-cells = <1>;
2364 #size-cells = <0>; 949 #size-cells = <0>;
2365 }; 950 };
2366 951
2367 blsp1_i2c6: i2c@c17a000 { 952 blsp1_i2c6: i2c@c17a000 {
2368 compatible = "qcom,i2 953 compatible = "qcom,i2c-qup-v2.2.1";
2369 reg = <0x0c17a000 0x6 954 reg = <0x0c17a000 0x600>;
2370 interrupts = <GIC_SPI 955 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
2371 956
2372 clocks = <&gcc GCC_BL 957 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
2373 <&gcc GCC_BL 958 <&gcc GCC_BLSP1_AHB_CLK>;
2374 clock-names = "core", 959 clock-names = "core", "iface";
2375 dmas = <&blsp1_dma 16 <<
2376 dma-names = "tx", "rx <<
2377 pinctrl-names = "defa <<
2378 pinctrl-0 = <&blsp1_i <<
2379 pinctrl-1 = <&blsp1_i <<
2380 clock-frequency = <40 960 clock-frequency = <400000>;
2381 961
2382 status = "disabled"; 962 status = "disabled";
2383 #address-cells = <1>; 963 #address-cells = <1>;
2384 #size-cells = <0>; 964 #size-cells = <0>;
2385 }; 965 };
2386 966
2387 blsp1_spi1: spi@c175000 { !! 967 blsp2_i2c0: i2c@c1b5000 {
2388 compatible = "qcom,sp <<
2389 reg = <0x0c175000 0x6 <<
2390 interrupts = <GIC_SPI <<
2391 <<
2392 clocks = <&gcc GCC_BL <<
2393 <&gcc GCC_BL <<
2394 clock-names = "core", <<
2395 dmas = <&blsp1_dma 6> <<
2396 dma-names = "tx", "rx <<
2397 pinctrl-names = "defa <<
2398 pinctrl-0 = <&blsp1_s <<
2399 <<
2400 status = "disabled"; <<
2401 #address-cells = <1>; <<
2402 #size-cells = <0>; <<
2403 }; <<
2404 <<
2405 blsp1_spi2: spi@c176000 { <<
2406 compatible = "qcom,sp <<
2407 reg = <0x0c176000 0x6 <<
2408 interrupts = <GIC_SPI <<
2409 <<
2410 clocks = <&gcc GCC_BL <<
2411 <&gcc GCC_BL <<
2412 clock-names = "core", <<
2413 dmas = <&blsp1_dma 8> <<
2414 dma-names = "tx", "rx <<
2415 pinctrl-names = "defa <<
2416 pinctrl-0 = <&blsp1_s <<
2417 <<
2418 status = "disabled"; <<
2419 #address-cells = <1>; <<
2420 #size-cells = <0>; <<
2421 }; <<
2422 <<
2423 blsp1_spi3: spi@c177000 { <<
2424 compatible = "qcom,sp <<
2425 reg = <0x0c177000 0x6 <<
2426 interrupts = <GIC_SPI <<
2427 <<
2428 clocks = <&gcc GCC_BL <<
2429 <&gcc GCC_BL <<
2430 clock-names = "core", <<
2431 dmas = <&blsp1_dma 10 <<
2432 dma-names = "tx", "rx <<
2433 pinctrl-names = "defa <<
2434 pinctrl-0 = <&blsp1_s <<
2435 <<
2436 status = "disabled"; <<
2437 #address-cells = <1>; <<
2438 #size-cells = <0>; <<
2439 }; <<
2440 <<
2441 blsp1_spi4: spi@c178000 { <<
2442 compatible = "qcom,sp <<
2443 reg = <0x0c178000 0x6 <<
2444 interrupts = <GIC_SPI <<
2445 <<
2446 clocks = <&gcc GCC_BL <<
2447 <&gcc GCC_BL <<
2448 clock-names = "core", <<
2449 dmas = <&blsp1_dma 12 <<
2450 dma-names = "tx", "rx <<
2451 pinctrl-names = "defa <<
2452 pinctrl-0 = <&blsp1_s <<
2453 <<
2454 status = "disabled"; <<
2455 #address-cells = <1>; <<
2456 #size-cells = <0>; <<
2457 }; <<
2458 <<
2459 blsp1_spi5: spi@c179000 { <<
2460 compatible = "qcom,sp <<
2461 reg = <0x0c179000 0x6 <<
2462 interrupts = <GIC_SPI <<
2463 <<
2464 clocks = <&gcc GCC_BL <<
2465 <&gcc GCC_BL <<
2466 clock-names = "core", <<
2467 dmas = <&blsp1_dma 14 <<
2468 dma-names = "tx", "rx <<
2469 pinctrl-names = "defa <<
2470 pinctrl-0 = <&blsp1_s <<
2471 <<
2472 status = "disabled"; <<
2473 #address-cells = <1>; <<
2474 #size-cells = <0>; <<
2475 }; <<
2476 <<
2477 blsp1_spi6: spi@c17a000 { <<
2478 compatible = "qcom,sp <<
2479 reg = <0x0c17a000 0x6 <<
2480 interrupts = <GIC_SPI <<
2481 <<
2482 clocks = <&gcc GCC_BL <<
2483 <&gcc GCC_BL <<
2484 clock-names = "core", <<
2485 dmas = <&blsp1_dma 16 <<
2486 dma-names = "tx", "rx <<
2487 pinctrl-names = "defa <<
2488 pinctrl-0 = <&blsp1_s <<
2489 <<
2490 status = "disabled"; <<
2491 #address-cells = <1>; <<
2492 #size-cells = <0>; <<
2493 }; <<
2494 <<
2495 blsp2_dma: dma-controller@c18 <<
2496 compatible = "qcom,ba <<
2497 reg = <0x0c184000 0x2 <<
2498 interrupts = <GIC_SPI <<
2499 clocks = <&gcc GCC_BL <<
2500 clock-names = "bam_cl <<
2501 #dma-cells = <1>; <<
2502 qcom,ee = <0>; <<
2503 qcom,controlled-remot <<
2504 num-channels = <18>; <<
2505 qcom,num-ees = <4>; <<
2506 }; <<
2507 <<
2508 blsp2_uart1: serial@c1b0000 { <<
2509 compatible = "qcom,ms <<
2510 reg = <0x0c1b0000 0x1 <<
2511 interrupts = <GIC_SPI <<
2512 clocks = <&gcc GCC_BL <<
2513 <&gcc GCC_BL <<
2514 clock-names = "core", <<
2515 status = "disabled"; <<
2516 }; <<
2517 <<
2518 blsp2_i2c1: i2c@c1b5000 { <<
2519 compatible = "qcom,i2 968 compatible = "qcom,i2c-qup-v2.2.1";
2520 reg = <0x0c1b5000 0x6 969 reg = <0x0c1b5000 0x600>;
2521 interrupts = <GIC_SPI 970 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
2522 971
2523 clocks = <&gcc GCC_BL 972 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
2524 <&gcc GCC_BL 973 <&gcc GCC_BLSP2_AHB_CLK>;
2525 clock-names = "core", 974 clock-names = "core", "iface";
2526 dmas = <&blsp2_dma 6> <<
2527 dma-names = "tx", "rx <<
2528 pinctrl-names = "defa <<
2529 pinctrl-0 = <&blsp2_i <<
2530 pinctrl-1 = <&blsp2_i <<
2531 clock-frequency = <40 975 clock-frequency = <400000>;
2532 976
2533 status = "disabled"; 977 status = "disabled";
2534 #address-cells = <1>; 978 #address-cells = <1>;
2535 #size-cells = <0>; 979 #size-cells = <0>;
2536 }; 980 };
2537 981
2538 blsp2_i2c2: i2c@c1b6000 { !! 982 blsp2_i2c1: i2c@c1b6000 {
2539 compatible = "qcom,i2 983 compatible = "qcom,i2c-qup-v2.2.1";
2540 reg = <0x0c1b6000 0x6 984 reg = <0x0c1b6000 0x600>;
2541 interrupts = <GIC_SPI 985 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
2542 986
2543 clocks = <&gcc GCC_BL 987 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
2544 <&gcc GCC_BL 988 <&gcc GCC_BLSP2_AHB_CLK>;
2545 clock-names = "core", 989 clock-names = "core", "iface";
2546 dmas = <&blsp2_dma 8> <<
2547 dma-names = "tx", "rx <<
2548 pinctrl-names = "defa <<
2549 pinctrl-0 = <&blsp2_i <<
2550 pinctrl-1 = <&blsp2_i <<
2551 clock-frequency = <40 990 clock-frequency = <400000>;
2552 991
2553 status = "disabled"; 992 status = "disabled";
2554 #address-cells = <1>; 993 #address-cells = <1>;
2555 #size-cells = <0>; 994 #size-cells = <0>;
2556 }; 995 };
2557 996
2558 blsp2_i2c3: i2c@c1b7000 { !! 997 blsp2_i2c2: i2c@c1b7000 {
2559 compatible = "qcom,i2 998 compatible = "qcom,i2c-qup-v2.2.1";
2560 reg = <0x0c1b7000 0x6 999 reg = <0x0c1b7000 0x600>;
2561 interrupts = <GIC_SPI 1000 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
2562 1001
2563 clocks = <&gcc GCC_BL 1002 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
2564 <&gcc GCC_BL 1003 <&gcc GCC_BLSP2_AHB_CLK>;
2565 clock-names = "core", 1004 clock-names = "core", "iface";
2566 dmas = <&blsp2_dma 10 <<
2567 dma-names = "tx", "rx <<
2568 pinctrl-names = "defa <<
2569 pinctrl-0 = <&blsp2_i <<
2570 pinctrl-1 = <&blsp2_i <<
2571 clock-frequency = <40 1005 clock-frequency = <400000>;
2572 1006
2573 status = "disabled"; 1007 status = "disabled";
2574 #address-cells = <1>; 1008 #address-cells = <1>;
2575 #size-cells = <0>; 1009 #size-cells = <0>;
2576 }; 1010 };
2577 1011
2578 blsp2_i2c4: i2c@c1b8000 { !! 1012 blsp2_i2c3: i2c@c1b8000 {
2579 compatible = "qcom,i2 1013 compatible = "qcom,i2c-qup-v2.2.1";
2580 reg = <0x0c1b8000 0x6 1014 reg = <0x0c1b8000 0x600>;
2581 interrupts = <GIC_SPI 1015 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
2582 1016
2583 clocks = <&gcc GCC_BL 1017 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>,
2584 <&gcc GCC_BL 1018 <&gcc GCC_BLSP2_AHB_CLK>;
2585 clock-names = "core", 1019 clock-names = "core", "iface";
2586 dmas = <&blsp2_dma 12 <<
2587 dma-names = "tx", "rx <<
2588 pinctrl-names = "defa <<
2589 pinctrl-0 = <&blsp2_i <<
2590 pinctrl-1 = <&blsp2_i <<
2591 clock-frequency = <40 1020 clock-frequency = <400000>;
2592 1021
2593 status = "disabled"; 1022 status = "disabled";
2594 #address-cells = <1>; 1023 #address-cells = <1>;
2595 #size-cells = <0>; 1024 #size-cells = <0>;
2596 }; 1025 };
2597 1026
2598 blsp2_i2c5: i2c@c1b9000 { !! 1027 blsp2_i2c4: i2c@c1b9000 {
2599 compatible = "qcom,i2 1028 compatible = "qcom,i2c-qup-v2.2.1";
2600 reg = <0x0c1b9000 0x6 1029 reg = <0x0c1b9000 0x600>;
2601 interrupts = <GIC_SPI 1030 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
2602 1031
2603 clocks = <&gcc GCC_BL 1032 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,
2604 <&gcc GCC_BL 1033 <&gcc GCC_BLSP2_AHB_CLK>;
2605 clock-names = "core", 1034 clock-names = "core", "iface";
2606 dmas = <&blsp2_dma 14 <<
2607 dma-names = "tx", "rx <<
2608 pinctrl-names = "defa <<
2609 pinctrl-0 = <&blsp2_i <<
2610 pinctrl-1 = <&blsp2_i <<
2611 clock-frequency = <40 1035 clock-frequency = <400000>;
2612 1036
2613 status = "disabled"; 1037 status = "disabled";
2614 #address-cells = <1>; 1038 #address-cells = <1>;
2615 #size-cells = <0>; 1039 #size-cells = <0>;
2616 }; 1040 };
2617 1041
2618 blsp2_i2c6: i2c@c1ba000 { !! 1042 blsp2_i2c5: i2c@c1ba000 {
2619 compatible = "qcom,i2 1043 compatible = "qcom,i2c-qup-v2.2.1";
2620 reg = <0x0c1ba000 0x6 1044 reg = <0x0c1ba000 0x600>;
2621 interrupts = <GIC_SPI 1045 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
2622 1046
2623 clocks = <&gcc GCC_BL 1047 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>,
2624 <&gcc GCC_BL 1048 <&gcc GCC_BLSP2_AHB_CLK>;
2625 clock-names = "core", 1049 clock-names = "core", "iface";
2626 dmas = <&blsp2_dma 16 <<
2627 dma-names = "tx", "rx <<
2628 pinctrl-names = "defa <<
2629 pinctrl-0 = <&blsp2_i <<
2630 pinctrl-1 = <&blsp2_i <<
2631 clock-frequency = <40 1050 clock-frequency = <400000>;
2632 1051
2633 status = "disabled"; 1052 status = "disabled";
2634 #address-cells = <1>; 1053 #address-cells = <1>;
2635 #size-cells = <0>; 1054 #size-cells = <0>;
2636 }; 1055 };
2637 1056
2638 blsp2_spi1: spi@c1b5000 { !! 1057 blsp2_uart1: serial@c1b0000 {
2639 compatible = "qcom,sp !! 1058 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2640 reg = <0x0c1b5000 0x6 !! 1059 reg = <0xc1b0000 0x1000>;
2641 interrupts = <GIC_SPI !! 1060 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
2642 !! 1061 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
2643 clocks = <&gcc GCC_BL <<
2644 <&gcc GCC_BL <<
2645 clock-names = "core", <<
2646 dmas = <&blsp2_dma 6> <<
2647 dma-names = "tx", "rx <<
2648 pinctrl-names = "defa <<
2649 pinctrl-0 = <&blsp2_s <<
2650 <<
2651 status = "disabled"; <<
2652 #address-cells = <1>; <<
2653 #size-cells = <0>; <<
2654 }; <<
2655 <<
2656 blsp2_spi2: spi@c1b6000 { <<
2657 compatible = "qcom,sp <<
2658 reg = <0x0c1b6000 0x6 <<
2659 interrupts = <GIC_SPI <<
2660 <<
2661 clocks = <&gcc GCC_BL <<
2662 <&gcc GCC_BL <<
2663 clock-names = "core", <<
2664 dmas = <&blsp2_dma 8> <<
2665 dma-names = "tx", "rx <<
2666 pinctrl-names = "defa <<
2667 pinctrl-0 = <&blsp2_s <<
2668 <<
2669 status = "disabled"; <<
2670 #address-cells = <1>; <<
2671 #size-cells = <0>; <<
2672 }; <<
2673 <<
2674 blsp2_spi3: spi@c1b7000 { <<
2675 compatible = "qcom,sp <<
2676 reg = <0x0c1b7000 0x6 <<
2677 interrupts = <GIC_SPI <<
2678 <<
2679 clocks = <&gcc GCC_BL <<
2680 <&gcc GCC_BL <<
2681 clock-names = "core", <<
2682 dmas = <&blsp2_dma 10 <<
2683 dma-names = "tx", "rx <<
2684 pinctrl-names = "defa <<
2685 pinctrl-0 = <&blsp2_s <<
2686 <<
2687 status = "disabled"; <<
2688 #address-cells = <1>; <<
2689 #size-cells = <0>; <<
2690 }; <<
2691 <<
2692 blsp2_spi4: spi@c1b8000 { <<
2693 compatible = "qcom,sp <<
2694 reg = <0x0c1b8000 0x6 <<
2695 interrupts = <GIC_SPI <<
2696 <<
2697 clocks = <&gcc GCC_BL <<
2698 <&gcc GCC_BL <<
2699 clock-names = "core", <<
2700 dmas = <&blsp2_dma 12 <<
2701 dma-names = "tx", "rx <<
2702 pinctrl-names = "defa <<
2703 pinctrl-0 = <&blsp2_s <<
2704 <<
2705 status = "disabled"; <<
2706 #address-cells = <1>; <<
2707 #size-cells = <0>; <<
2708 }; <<
2709 <<
2710 blsp2_spi5: spi@c1b9000 { <<
2711 compatible = "qcom,sp <<
2712 reg = <0x0c1b9000 0x6 <<
2713 interrupts = <GIC_SPI <<
2714 <<
2715 clocks = <&gcc GCC_BL <<
2716 <&gcc GCC_BL <<
2717 clock-names = "core", <<
2718 dmas = <&blsp2_dma 14 <<
2719 dma-names = "tx", "rx <<
2720 pinctrl-names = "defa <<
2721 pinctrl-0 = <&blsp2_s <<
2722 <<
2723 status = "disabled"; <<
2724 #address-cells = <1>; <<
2725 #size-cells = <0>; <<
2726 }; <<
2727 <<
2728 blsp2_spi6: spi@c1ba000 { <<
2729 compatible = "qcom,sp <<
2730 reg = <0x0c1ba000 0x6 <<
2731 interrupts = <GIC_SPI <<
2732 <<
2733 clocks = <&gcc GCC_BL <<
2734 <&gcc GCC_BL 1062 <&gcc GCC_BLSP2_AHB_CLK>;
2735 clock-names = "core", 1063 clock-names = "core", "iface";
2736 dmas = <&blsp2_dma 16 <<
2737 dma-names = "tx", "rx <<
2738 pinctrl-names = "defa <<
2739 pinctrl-0 = <&blsp2_s <<
2740 <<
2741 status = "disabled"; 1064 status = "disabled";
2742 #address-cells = <1>; <<
2743 #size-cells = <0>; <<
2744 }; <<
2745 <<
2746 mmcc: clock-controller@c8c000 <<
2747 compatible = "qcom,mm <<
2748 #clock-cells = <1>; <<
2749 #reset-cells = <1>; <<
2750 #power-domain-cells = <<
2751 reg = <0xc8c0000 0x40 <<
2752 <<
2753 clock-names = "xo", <<
2754 "gpll0" <<
2755 "dsi0ds <<
2756 "dsi0by <<
2757 "dsi1ds <<
2758 "dsi1by <<
2759 "hdmipl <<
2760 "dplink <<
2761 "dpvco" <<
2762 "gpll0_ <<
2763 clocks = <&rpmcc RPM_ <<
2764 <&gcc GCC_MM <<
2765 <&mdss_dsi0_ <<
2766 <&mdss_dsi0_ <<
2767 <&mdss_dsi1_ <<
2768 <&mdss_dsi1_ <<
2769 <0>, <<
2770 <0>, <<
2771 <0>, <<
2772 <&gcc GCC_MM <<
2773 }; <<
2774 <<
2775 mdss: display-subsystem@c9000 <<
2776 compatible = "qcom,ms <<
2777 reg = <0x0c900000 0x1 <<
2778 reg-names = "mdss"; <<
2779 <<
2780 interrupts = <GIC_SPI <<
2781 interrupt-controller; <<
2782 #interrupt-cells = <1 <<
2783 <<
2784 clocks = <&mmcc MDSS_ <<
2785 <&mmcc MDSS_ <<
2786 <&mmcc MDSS_ <<
2787 clock-names = "iface" <<
2788 "bus", <<
2789 "core"; <<
2790 <<
2791 power-domains = <&mmc <<
2792 iommus = <&mmss_smmu <<
2793 <<
2794 #address-cells = <1>; <<
2795 #size-cells = <1>; <<
2796 ranges; <<
2797 <<
2798 status = "disabled"; <<
2799 <<
2800 mdss_mdp: display-con <<
2801 compatible = <<
2802 reg = <0x0c90 <<
2803 <0x0c9a <<
2804 <0x0c9b <<
2805 <0x0c9b <<
2806 reg-names = " <<
2807 " <<
2808 " <<
2809 " <<
2810 <<
2811 interrupt-par <<
2812 interrupts = <<
2813 <<
2814 clocks = <&mm <<
2815 <&mm <<
2816 <&mm <<
2817 <&mm <<
2818 <&mm <<
2819 clock-names = <<
2820 <<
2821 <<
2822 <<
2823 <<
2824 <<
2825 assigned-cloc <<
2826 assigned-cloc <<
2827 <<
2828 operating-poi <<
2829 power-domains <<
2830 <<
2831 mdp_opp_table <<
2832 compa <<
2833 <<
2834 opp-1 <<
2835 <<
2836 <<
2837 }; <<
2838 <<
2839 opp-2 <<
2840 <<
2841 <<
2842 }; <<
2843 <<
2844 opp-3 <<
2845 <<
2846 <<
2847 }; <<
2848 <<
2849 opp-4 <<
2850 <<
2851 <<
2852 }; <<
2853 }; <<
2854 <<
2855 ports { <<
2856 #addr <<
2857 #size <<
2858 <<
2859 port@ <<
2860 <<
2861 <<
2862 <<
2863 <<
2864 <<
2865 }; <<
2866 <<
2867 port@ <<
2868 <<
2869 <<
2870 <<
2871 <<
2872 <<
2873 }; <<
2874 }; <<
2875 }; <<
2876 <<
2877 mdss_dsi0: dsi@c99400 <<
2878 compatible = <<
2879 reg = <0x0c99 <<
2880 reg-names = " <<
2881 <<
2882 interrupt-par <<
2883 interrupts = <<
2884 <<
2885 clocks = <&mm <<
2886 <&mm <<
2887 <&mm <<
2888 <&mm <<
2889 <&mm <<
2890 <&mm <<
2891 clock-names = <<
2892 <<
2893 <<
2894 <<
2895 <<
2896 <<
2897 assigned-cloc <<
2898 <<
2899 assigned-cloc <<
2900 <<
2901 <<
2902 operating-poi <<
2903 power-domains <<
2904 <<
2905 phys = <&mdss <<
2906 phy-names = " <<
2907 <<
2908 #address-cell <<
2909 #size-cells = <<
2910 <<
2911 status = "dis <<
2912 <<
2913 ports { <<
2914 #addr <<
2915 #size <<
2916 <<
2917 port@ <<
2918 <<
2919 <<
2920 <<
2921 <<
2922 <<
2923 }; <<
2924 <<
2925 port@ <<
2926 <<
2927 <<
2928 <<
2929 <<
2930 }; <<
2931 }; <<
2932 }; <<
2933 <<
2934 mdss_dsi0_phy: phy@c9 <<
2935 compatible = <<
2936 reg = <0x0c99 <<
2937 <0x0c99 <<
2938 <0x0c99 <<
2939 reg-names = " <<
2940 " <<
2941 " <<
2942 <<
2943 clocks = <&mm <<
2944 <&rp <<
2945 clock-names = <<
2946 <<
2947 #clock-cells <<
2948 #phy-cells = <<
2949 <<
2950 status = "dis <<
2951 }; <<
2952 <<
2953 mdss_dsi1: dsi@c99600 <<
2954 compatible = <<
2955 reg = <0x0c99 <<
2956 reg-names = " <<
2957 <<
2958 interrupt-par <<
2959 interrupts = <<
2960 <<
2961 clocks = <&mm <<
2962 <&mm <<
2963 <&mm <<
2964 <&mm <<
2965 <&mm <<
2966 <&mm <<
2967 clock-names = <<
2968 <<
2969 <<
2970 <<
2971 <<
2972 <<
2973 assigned-cloc <<
2974 <<
2975 assigned-cloc <<
2976 <<
2977 <<
2978 operating-poi <<
2979 power-domains <<
2980 <<
2981 phys = <&mdss <<
2982 phy-names = " <<
2983 <<
2984 #address-cell <<
2985 #size-cells = <<
2986 <<
2987 status = "dis <<
2988 <<
2989 ports { <<
2990 #addr <<
2991 #size <<
2992 <<
2993 port@ <<
2994 <<
2995 <<
2996 <<
2997 <<
2998 <<
2999 }; <<
3000 <<
3001 port@ <<
3002 <<
3003 <<
3004 <<
3005 <<
3006 }; <<
3007 }; <<
3008 }; <<
3009 <<
3010 mdss_dsi1_phy: phy@c9 <<
3011 compatible = <<
3012 reg = <0x0c99 <<
3013 <0x0c99 <<
3014 <0x0c99 <<
3015 reg-names = " <<
3016 " <<
3017 " <<
3018 <<
3019 clocks = <&mm <<
3020 <&rp <<
3021 clock-names = <<
3022 <<
3023 <<
3024 #clock-cells <<
3025 #phy-cells = <<
3026 <<
3027 status = "dis <<
3028 }; <<
3029 }; <<
3030 <<
3031 venus: video-codec@cc00000 { <<
3032 compatible = "qcom,ms <<
3033 reg = <0x0cc00000 0xf <<
3034 interrupts = <GIC_SPI <<
3035 power-domains = <&mmc <<
3036 clocks = <&mmcc VIDEO <<
3037 <&mmcc VIDEO <<
3038 <&mmcc VIDEO <<
3039 <&mmcc VIDEO <<
3040 clock-names = "core", <<
3041 iommus = <&mmss_smmu <<
3042 <&mmss_smmu <<
3043 <&mmss_smmu <<
3044 <&mmss_smmu <<
3045 <&mmss_smmu <<
3046 <&mmss_smmu <<
3047 <&mmss_smmu <<
3048 <&mmss_smmu <<
3049 <&mmss_smmu <<
3050 <&mmss_smmu <<
3051 <&mmss_smmu <<
3052 <&mmss_smmu <<
3053 <&mmss_smmu <<
3054 <&mmss_smmu <<
3055 <&mmss_smmu <<
3056 <&mmss_smmu <<
3057 <&mmss_smmu <<
3058 <&mmss_smmu <<
3059 <&mmss_smmu <<
3060 <&mmss_smmu <<
3061 memory-region = <&ven <<
3062 status = "disabled"; <<
3063 <<
3064 video-decoder { <<
3065 compatible = <<
3066 clocks = <&mm <<
3067 clock-names = <<
3068 power-domains <<
3069 }; <<
3070 <<
3071 video-encoder { <<
3072 compatible = <<
3073 clocks = <&mm <<
3074 clock-names = <<
3075 power-domains <<
3076 }; <<
3077 }; <<
3078 <<
3079 mmss_smmu: iommu@cd00000 { <<
3080 compatible = "qcom,ms <<
3081 reg = <0x0cd00000 0x4 <<
3082 #iommu-cells = <1>; <<
3083 <<
3084 clocks = <&mmcc MNOC_ <<
3085 <&mmcc BIMC_ <<
3086 <&mmcc BIMC_ <<
3087 clock-names = "iface- <<
3088 "iface- <<
3089 "bus-sm <<
3090 <<
3091 #global-interrupts = <<
3092 interrupts = <<
3093 <GIC_SPI 263 <<
3094 <GIC_SPI 266 <<
3095 <GIC_SPI 267 <<
3096 <GIC_SPI 268 <<
3097 <GIC_SPI 244 <<
3098 <GIC_SPI 245 <<
3099 <GIC_SPI 247 <<
3100 <GIC_SPI 248 <<
3101 <GIC_SPI 249 <<
3102 <GIC_SPI 250 <<
3103 <GIC_SPI 251 <<
3104 <GIC_SPI 252 <<
3105 <GIC_SPI 253 <<
3106 <GIC_SPI 254 <<
3107 <GIC_SPI 255 <<
3108 <GIC_SPI 256 <<
3109 <GIC_SPI 260 <<
3110 <GIC_SPI 261 <<
3111 <GIC_SPI 262 <<
3112 <GIC_SPI 272 <<
3113 <<
3114 power-domains = <&mmc <<
3115 }; <<
3116 <<
3117 remoteproc_adsp: remoteproc@1 <<
3118 compatible = "qcom,ms <<
3119 reg = <0x17300000 0x4 <<
3120 <<
3121 interrupts-extended = <<
3122 <<
3123 <<
3124 <<
3125 <<
3126 interrupt-names = "wd <<
3127 "ha <<
3128 <<
3129 clocks = <&rpmcc RPM_ <<
3130 clock-names = "xo"; <<
3131 <<
3132 memory-region = <&ads <<
3133 <<
3134 qcom,smem-states = <& <<
3135 qcom,smem-state-names <<
3136 <<
3137 power-domains = <&rpm <<
3138 power-domain-names = <<
3139 <<
3140 status = "disabled"; <<
3141 <<
3142 glink-edge { <<
3143 interrupts = <<
3144 label = "lpas <<
3145 qcom,remote-p <<
3146 mboxes = <&ap <<
3147 }; <<
3148 }; <<
3149 <<
3150 apcs_glb: mailbox@17911000 { <<
3151 compatible = "qcom,ms <<
3152 "qcom,ms <<
3153 reg = <0x17911000 0x1 <<
3154 <<
3155 #mbox-cells = <1>; <<
3156 }; 1065 };
3157 1066
3158 timer@17920000 { 1067 timer@17920000 {
3159 #address-cells = <1>; 1068 #address-cells = <1>;
3160 #size-cells = <1>; 1069 #size-cells = <1>;
3161 ranges; 1070 ranges;
3162 compatible = "arm,arm 1071 compatible = "arm,armv7-timer-mem";
3163 reg = <0x17920000 0x1 1072 reg = <0x17920000 0x1000>;
3164 1073
3165 frame@17921000 { 1074 frame@17921000 {
3166 frame-number 1075 frame-number = <0>;
3167 interrupts = 1076 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
3168 1077 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
3169 reg = <0x1792 1078 reg = <0x17921000 0x1000>,
3170 <0x1792 1079 <0x17922000 0x1000>;
3171 }; 1080 };
3172 1081
3173 frame@17923000 { 1082 frame@17923000 {
3174 frame-number 1083 frame-number = <1>;
3175 interrupts = 1084 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
3176 reg = <0x1792 1085 reg = <0x17923000 0x1000>;
3177 status = "dis 1086 status = "disabled";
3178 }; 1087 };
3179 1088
3180 frame@17924000 { 1089 frame@17924000 {
3181 frame-number 1090 frame-number = <2>;
3182 interrupts = 1091 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
3183 reg = <0x1792 1092 reg = <0x17924000 0x1000>;
3184 status = "dis 1093 status = "disabled";
3185 }; 1094 };
3186 1095
3187 frame@17925000 { 1096 frame@17925000 {
3188 frame-number 1097 frame-number = <3>;
3189 interrupts = 1098 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3190 reg = <0x1792 1099 reg = <0x17925000 0x1000>;
3191 status = "dis 1100 status = "disabled";
3192 }; 1101 };
3193 1102
3194 frame@17926000 { 1103 frame@17926000 {
3195 frame-number 1104 frame-number = <4>;
3196 interrupts = 1105 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3197 reg = <0x1792 1106 reg = <0x17926000 0x1000>;
3198 status = "dis 1107 status = "disabled";
3199 }; 1108 };
3200 1109
3201 frame@17927000 { 1110 frame@17927000 {
3202 frame-number 1111 frame-number = <5>;
3203 interrupts = 1112 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3204 reg = <0x1792 1113 reg = <0x17927000 0x1000>;
3205 status = "dis 1114 status = "disabled";
3206 }; 1115 };
3207 1116
3208 frame@17928000 { 1117 frame@17928000 {
3209 frame-number 1118 frame-number = <6>;
3210 interrupts = 1119 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
3211 reg = <0x1792 1120 reg = <0x17928000 0x1000>;
3212 status = "dis 1121 status = "disabled";
3213 }; 1122 };
3214 }; 1123 };
3215 1124
3216 intc: interrupt-controller@17 1125 intc: interrupt-controller@17a00000 {
3217 compatible = "arm,gic 1126 compatible = "arm,gic-v3";
3218 reg = <0x17a00000 0x1 1127 reg = <0x17a00000 0x10000>, /* GICD */
3219 <0x17b00000 0x1 1128 <0x17b00000 0x100000>; /* GICR * 8 */
3220 #interrupt-cells = <3 1129 #interrupt-cells = <3>;
3221 #address-cells = <1>; 1130 #address-cells = <1>;
3222 #size-cells = <1>; 1131 #size-cells = <1>;
3223 ranges; 1132 ranges;
3224 interrupt-controller; 1133 interrupt-controller;
3225 #redistributor-region 1134 #redistributor-regions = <1>;
3226 redistributor-stride 1135 redistributor-stride = <0x0 0x20000>;
3227 interrupts = <GIC_PPI 1136 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3228 }; 1137 };
3229 1138
3230 wifi: wifi@18800000 { !! 1139 ufshc: ufshc@1da4000 {
3231 compatible = "qcom,wc !! 1140 compatible = "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
3232 status = "disabled"; !! 1141 reg = <0x01da4000 0x2500>;
3233 reg = <0x18800000 0x8 !! 1142 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
3234 reg-names = "membase" !! 1143 phys = <&ufsphy_lanes>;
3235 memory-region = <&wla !! 1144 phy-names = "ufsphy";
3236 clocks = <&rpmcc RPM_ !! 1145 lanes-per-direction = <2>;
3237 clock-names = "cxo_re !! 1146 power-domains = <&gcc UFS_GDSC>;
3238 interrupts = !! 1147 #reset-cells = <1>;
3239 <GIC_SPI 413 !! 1148
3240 <GIC_SPI 414 !! 1149 clock-names =
3241 <GIC_SPI 415 !! 1150 "core_clk",
3242 <GIC_SPI 416 !! 1151 "bus_aggr_clk",
3243 <GIC_SPI 417 !! 1152 "iface_clk",
3244 <GIC_SPI 418 !! 1153 "core_clk_unipro",
3245 <GIC_SPI 420 !! 1154 "ref_clk",
3246 <GIC_SPI 421 !! 1155 "tx_lane0_sync_clk",
3247 <GIC_SPI 422 !! 1156 "rx_lane0_sync_clk",
3248 <GIC_SPI 423 !! 1157 "rx_lane1_sync_clk";
3249 <GIC_SPI 424 !! 1158 clocks =
3250 <GIC_SPI 425 !! 1159 <&gcc GCC_UFS_AXI_CLK>,
3251 iommus = <&anoc2_smmu !! 1160 <&gcc GCC_AGGRE1_UFS_AXI_CLK>,
3252 <&anoc2_smmu !! 1161 <&gcc GCC_UFS_AHB_CLK>,
3253 qcom,snoc-host-cap-8b !! 1162 <&gcc GCC_UFS_UNIPRO_CORE_CLK>,
3254 qcom,no-msa-ready-ind !! 1163 <&rpmcc RPM_SMD_LN_BB_CLK1>,
>> 1164 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
>> 1165 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>,
>> 1166 <&gcc GCC_UFS_RX_SYMBOL_1_CLK>;
>> 1167 freq-table-hz =
>> 1168 <50000000 200000000>,
>> 1169 <0 0>,
>> 1170 <0 0>,
>> 1171 <37500000 150000000>,
>> 1172 <0 0>,
>> 1173 <0 0>,
>> 1174 <0 0>,
>> 1175 <0 0>;
>> 1176
>> 1177 resets = <&gcc GCC_UFS_BCR>;
>> 1178 reset-names = "rst";
>> 1179 };
>> 1180
>> 1181 ufsphy: phy@1da7000 {
>> 1182 compatible = "qcom,msm8998-qmp-ufs-phy";
>> 1183 reg = <0x01da7000 0x18c>;
>> 1184 #address-cells = <1>;
>> 1185 #size-cells = <1>;
>> 1186 ranges;
>> 1187
>> 1188 clock-names =
>> 1189 "ref",
>> 1190 "ref_aux";
>> 1191 clocks =
>> 1192 <&gcc GCC_UFS_CLKREF_CLK>,
>> 1193 <&gcc GCC_UFS_PHY_AUX_CLK>;
>> 1194
>> 1195 reset-names = "ufsphy";
>> 1196 resets = <&ufshc 0>;
>> 1197
>> 1198 ufsphy_lanes: lanes@1da7400 {
>> 1199 reg = <0x01da7400 0x128>,
>> 1200 <0x01da7600 0x1fc>,
>> 1201 <0x01da7c00 0x1dc>,
>> 1202 <0x01da7800 0x128>,
>> 1203 <0x01da7a00 0x1fc>;
>> 1204 #phy-cells = <0>;
>> 1205 };
3255 }; 1206 };
3256 }; 1207 };
3257 }; 1208 };
>> 1209
>> 1210 #include "msm8998-pins.dtsi"
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