1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2016, The Linux Foundation. A 2 /* Copyright (c) 2016, The Linux Foundation. All rights reserved. */
3 3
4 #include <dt-bindings/interrupt-controller/arm 4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-msm8998.h 5 #include <dt-bindings/clock/qcom,gcc-msm8998.h>
6 #include <dt-bindings/clock/qcom,gpucc-msm8998 <<
7 #include <dt-bindings/clock/qcom,mmcc-msm8998. <<
8 #include <dt-bindings/clock/qcom,rpmcc.h> 6 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/firmware/qcom,scm.h> <<
10 #include <dt-bindings/power/qcom-rpmpd.h> 7 #include <dt-bindings/power/qcom-rpmpd.h>
11 #include <dt-bindings/gpio/gpio.h> 8 #include <dt-bindings/gpio/gpio.h>
12 9
13 / { 10 / {
14 interrupt-parent = <&intc>; 11 interrupt-parent = <&intc>;
15 12
16 qcom,msm-id = <292 0x0>; 13 qcom,msm-id = <292 0x0>;
17 14
18 #address-cells = <2>; 15 #address-cells = <2>;
19 #size-cells = <2>; 16 #size-cells = <2>;
20 17
21 chosen { }; 18 chosen { };
22 19
23 memory@80000000 { !! 20 memory {
24 device_type = "memory"; 21 device_type = "memory";
25 /* We expect the bootloader to 22 /* We expect the bootloader to fill in the reg */
26 reg = <0x0 0x80000000 0x0 0x0> !! 23 reg = <0 0 0 0>;
27 }; 24 };
28 25
29 reserved-memory { 26 reserved-memory {
30 #address-cells = <2>; 27 #address-cells = <2>;
31 #size-cells = <2>; 28 #size-cells = <2>;
32 ranges; 29 ranges;
33 30
34 hyp_mem: memory@85800000 { !! 31 memory@85800000 {
35 reg = <0x0 0x85800000 !! 32 reg = <0x0 0x85800000 0x0 0x800000>;
36 no-map; <<
37 }; <<
38 <<
39 xbl_mem: memory@85e00000 { <<
40 reg = <0x0 0x85e00000 <<
41 no-map; 33 no-map;
42 }; 34 };
43 35
44 smem_mem: smem-mem@86000000 { 36 smem_mem: smem-mem@86000000 {
45 reg = <0x0 0x86000000 37 reg = <0x0 0x86000000 0x0 0x200000>;
46 no-map; 38 no-map;
47 }; 39 };
48 40
49 tz_mem: memory@86200000 { !! 41 memory@86200000 {
50 reg = <0x0 0x86200000 42 reg = <0x0 0x86200000 0x0 0x2d00000>;
51 no-map; 43 no-map;
52 }; 44 };
53 45
54 rmtfs_mem: memory@88f00000 { !! 46 rmtfs {
55 compatible = "qcom,rmt 47 compatible = "qcom,rmtfs-mem";
56 reg = <0x0 0x88f00000 <<
57 no-map; <<
58 <<
59 qcom,client-id = <1>; <<
60 qcom,vmid = <QCOM_SCM_ <<
61 }; <<
62 <<
63 spss_mem: memory@8ab00000 { <<
64 reg = <0x0 0x8ab00000 <<
65 no-map; <<
66 }; <<
67 <<
68 adsp_mem: memory@8b200000 { <<
69 reg = <0x0 0x8b200000 <<
70 no-map; <<
71 }; <<
72 <<
73 mpss_mem: memory@8cc00000 { <<
74 reg = <0x0 0x8cc00000 <<
75 no-map; <<
76 }; <<
77 <<
78 venus_mem: memory@93c00000 { <<
79 reg = <0x0 0x93c00000 <<
80 no-map; <<
81 }; <<
82 <<
83 mba_mem: memory@94100000 { <<
84 reg = <0x0 0x94100000 <<
85 no-map; <<
86 }; <<
87 <<
88 slpi_mem: memory@94300000 { <<
89 reg = <0x0 0x94300000 <<
90 no-map; <<
91 }; <<
92 <<
93 ipa_fw_mem: memory@95200000 { <<
94 reg = <0x0 0x95200000 <<
95 no-map; <<
96 }; <<
97 48
98 ipa_gsi_mem: memory@95210000 { !! 49 size = <0x0 0x200000>;
99 reg = <0x0 0x95210000 !! 50 alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
100 no-map; 51 no-map;
101 }; <<
102 <<
103 gpu_mem: memory@95600000 { <<
104 reg = <0x0 0x95600000 <<
105 no-map; <<
106 }; <<
107 52
108 wlan_msa_mem: memory@95700000 !! 53 qcom,client-id = <1>;
109 reg = <0x0 0x95700000 !! 54 qcom,vmid = <15>;
110 no-map; <<
111 }; <<
112 <<
113 mdata_mem: mpss-metadata { <<
114 alloc-ranges = <0x0 0x <<
115 size = <0x0 0x4000>; <<
116 no-map; <<
117 }; 55 };
118 }; 56 };
119 57
120 clocks { 58 clocks {
121 xo: xo-board { 59 xo: xo-board {
122 compatible = "fixed-cl 60 compatible = "fixed-clock";
123 #clock-cells = <0>; 61 #clock-cells = <0>;
124 clock-frequency = <192 62 clock-frequency = <19200000>;
125 clock-output-names = " 63 clock-output-names = "xo_board";
126 }; 64 };
127 65
128 sleep_clk: sleep-clk { !! 66 sleep_clk {
129 compatible = "fixed-cl 67 compatible = "fixed-clock";
130 #clock-cells = <0>; 68 #clock-cells = <0>;
131 clock-frequency = <327 69 clock-frequency = <32764>;
132 }; 70 };
133 }; 71 };
134 72
135 cpus { 73 cpus {
136 #address-cells = <2>; 74 #address-cells = <2>;
137 #size-cells = <0>; 75 #size-cells = <0>;
138 76
139 CPU0: cpu@0 { 77 CPU0: cpu@0 {
140 device_type = "cpu"; 78 device_type = "cpu";
141 compatible = "qcom,kry !! 79 compatible = "arm,armv8";
142 reg = <0x0 0x0>; 80 reg = <0x0 0x0>;
143 enable-method = "psci" 81 enable-method = "psci";
144 capacity-dmips-mhz = < <<
145 cpu-idle-states = <&LI 82 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
146 next-level-cache = <&L 83 next-level-cache = <&L2_0>;
147 L2_0: l2-cache { 84 L2_0: l2-cache {
148 compatible = " !! 85 compatible = "arm,arch-cache";
149 cache-level = 86 cache-level = <2>;
150 cache-unified; !! 87 };
>> 88 L1_I_0: l1-icache {
>> 89 compatible = "arm,arch-cache";
>> 90 };
>> 91 L1_D_0: l1-dcache {
>> 92 compatible = "arm,arch-cache";
151 }; 93 };
152 }; 94 };
153 95
154 CPU1: cpu@1 { 96 CPU1: cpu@1 {
155 device_type = "cpu"; 97 device_type = "cpu";
156 compatible = "qcom,kry !! 98 compatible = "arm,armv8";
157 reg = <0x0 0x1>; 99 reg = <0x0 0x1>;
158 enable-method = "psci" 100 enable-method = "psci";
159 capacity-dmips-mhz = < <<
160 cpu-idle-states = <&LI 101 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
161 next-level-cache = <&L 102 next-level-cache = <&L2_0>;
>> 103 L1_I_1: l1-icache {
>> 104 compatible = "arm,arch-cache";
>> 105 };
>> 106 L1_D_1: l1-dcache {
>> 107 compatible = "arm,arch-cache";
>> 108 };
162 }; 109 };
163 110
164 CPU2: cpu@2 { 111 CPU2: cpu@2 {
165 device_type = "cpu"; 112 device_type = "cpu";
166 compatible = "qcom,kry !! 113 compatible = "arm,armv8";
167 reg = <0x0 0x2>; 114 reg = <0x0 0x2>;
168 enable-method = "psci" 115 enable-method = "psci";
169 capacity-dmips-mhz = < <<
170 cpu-idle-states = <&LI 116 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
171 next-level-cache = <&L 117 next-level-cache = <&L2_0>;
>> 118 L1_I_2: l1-icache {
>> 119 compatible = "arm,arch-cache";
>> 120 };
>> 121 L1_D_2: l1-dcache {
>> 122 compatible = "arm,arch-cache";
>> 123 };
172 }; 124 };
173 125
174 CPU3: cpu@3 { 126 CPU3: cpu@3 {
175 device_type = "cpu"; 127 device_type = "cpu";
176 compatible = "qcom,kry !! 128 compatible = "arm,armv8";
177 reg = <0x0 0x3>; 129 reg = <0x0 0x3>;
178 enable-method = "psci" 130 enable-method = "psci";
179 capacity-dmips-mhz = < <<
180 cpu-idle-states = <&LI 131 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
181 next-level-cache = <&L 132 next-level-cache = <&L2_0>;
>> 133 L1_I_3: l1-icache {
>> 134 compatible = "arm,arch-cache";
>> 135 };
>> 136 L1_D_3: l1-dcache {
>> 137 compatible = "arm,arch-cache";
>> 138 };
182 }; 139 };
183 140
184 CPU4: cpu@100 { 141 CPU4: cpu@100 {
185 device_type = "cpu"; 142 device_type = "cpu";
186 compatible = "qcom,kry !! 143 compatible = "arm,armv8";
187 reg = <0x0 0x100>; 144 reg = <0x0 0x100>;
188 enable-method = "psci" 145 enable-method = "psci";
189 capacity-dmips-mhz = < <<
190 cpu-idle-states = <&BI 146 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
191 next-level-cache = <&L 147 next-level-cache = <&L2_1>;
192 L2_1: l2-cache { 148 L2_1: l2-cache {
193 compatible = " !! 149 compatible = "arm,arch-cache";
194 cache-level = 150 cache-level = <2>;
195 cache-unified; !! 151 };
>> 152 L1_I_100: l1-icache {
>> 153 compatible = "arm,arch-cache";
>> 154 };
>> 155 L1_D_100: l1-dcache {
>> 156 compatible = "arm,arch-cache";
196 }; 157 };
197 }; 158 };
198 159
199 CPU5: cpu@101 { 160 CPU5: cpu@101 {
200 device_type = "cpu"; 161 device_type = "cpu";
201 compatible = "qcom,kry !! 162 compatible = "arm,armv8";
202 reg = <0x0 0x101>; 163 reg = <0x0 0x101>;
203 enable-method = "psci" 164 enable-method = "psci";
204 capacity-dmips-mhz = < <<
205 cpu-idle-states = <&BI 165 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
206 next-level-cache = <&L 166 next-level-cache = <&L2_1>;
>> 167 L1_I_101: l1-icache {
>> 168 compatible = "arm,arch-cache";
>> 169 };
>> 170 L1_D_101: l1-dcache {
>> 171 compatible = "arm,arch-cache";
>> 172 };
207 }; 173 };
208 174
209 CPU6: cpu@102 { 175 CPU6: cpu@102 {
210 device_type = "cpu"; 176 device_type = "cpu";
211 compatible = "qcom,kry !! 177 compatible = "arm,armv8";
212 reg = <0x0 0x102>; 178 reg = <0x0 0x102>;
213 enable-method = "psci" 179 enable-method = "psci";
214 capacity-dmips-mhz = < <<
215 cpu-idle-states = <&BI 180 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
216 next-level-cache = <&L 181 next-level-cache = <&L2_1>;
>> 182 L1_I_102: l1-icache {
>> 183 compatible = "arm,arch-cache";
>> 184 };
>> 185 L1_D_102: l1-dcache {
>> 186 compatible = "arm,arch-cache";
>> 187 };
217 }; 188 };
218 189
219 CPU7: cpu@103 { 190 CPU7: cpu@103 {
220 device_type = "cpu"; 191 device_type = "cpu";
221 compatible = "qcom,kry !! 192 compatible = "arm,armv8";
222 reg = <0x0 0x103>; 193 reg = <0x0 0x103>;
223 enable-method = "psci" 194 enable-method = "psci";
224 capacity-dmips-mhz = < <<
225 cpu-idle-states = <&BI 195 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
226 next-level-cache = <&L 196 next-level-cache = <&L2_1>;
>> 197 L1_I_103: l1-icache {
>> 198 compatible = "arm,arch-cache";
>> 199 };
>> 200 L1_D_103: l1-dcache {
>> 201 compatible = "arm,arch-cache";
>> 202 };
227 }; 203 };
228 204
229 cpu-map { 205 cpu-map {
230 cluster0 { 206 cluster0 {
231 core0 { 207 core0 {
232 cpu = 208 cpu = <&CPU0>;
233 }; 209 };
234 210
235 core1 { 211 core1 {
236 cpu = 212 cpu = <&CPU1>;
237 }; 213 };
238 214
239 core2 { 215 core2 {
240 cpu = 216 cpu = <&CPU2>;
241 }; 217 };
242 218
243 core3 { 219 core3 {
244 cpu = 220 cpu = <&CPU3>;
245 }; 221 };
246 }; 222 };
247 223
248 cluster1 { 224 cluster1 {
249 core0 { 225 core0 {
250 cpu = 226 cpu = <&CPU4>;
251 }; 227 };
252 228
253 core1 { 229 core1 {
254 cpu = 230 cpu = <&CPU5>;
255 }; 231 };
256 232
257 core2 { 233 core2 {
258 cpu = 234 cpu = <&CPU6>;
259 }; 235 };
260 236
261 core3 { 237 core3 {
262 cpu = 238 cpu = <&CPU7>;
263 }; 239 };
264 }; 240 };
265 }; 241 };
266 242
267 idle-states { 243 idle-states {
268 entry-method = "psci"; 244 entry-method = "psci";
269 245
270 LITTLE_CPU_SLEEP_0: cp 246 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
271 compatible = " 247 compatible = "arm,idle-state";
272 idle-state-nam 248 idle-state-name = "little-retention";
273 /* CPU Retenti 249 /* CPU Retention (C2D), L2 Active */
274 arm,psci-suspe 250 arm,psci-suspend-param = <0x00000002>;
275 entry-latency- 251 entry-latency-us = <81>;
276 exit-latency-u 252 exit-latency-us = <86>;
277 min-residency- 253 min-residency-us = <504>;
278 }; 254 };
279 255
280 LITTLE_CPU_SLEEP_1: cp 256 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
281 compatible = " 257 compatible = "arm,idle-state";
282 idle-state-nam 258 idle-state-name = "little-power-collapse";
283 /* CPU + L2 Po 259 /* CPU + L2 Power Collapse (C3, D4) */
284 arm,psci-suspe 260 arm,psci-suspend-param = <0x40000003>;
285 entry-latency- 261 entry-latency-us = <814>;
286 exit-latency-u 262 exit-latency-us = <4562>;
287 min-residency- 263 min-residency-us = <9183>;
288 local-timer-st 264 local-timer-stop;
289 }; 265 };
290 266
291 BIG_CPU_SLEEP_0: cpu-s 267 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
292 compatible = " 268 compatible = "arm,idle-state";
293 idle-state-nam 269 idle-state-name = "big-retention";
294 /* CPU Retenti 270 /* CPU Retention (C2D), L2 Active */
295 arm,psci-suspe 271 arm,psci-suspend-param = <0x00000002>;
296 entry-latency- 272 entry-latency-us = <79>;
297 exit-latency-u 273 exit-latency-us = <82>;
298 min-residency- 274 min-residency-us = <1302>;
299 }; 275 };
300 276
301 BIG_CPU_SLEEP_1: cpu-s 277 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
302 compatible = " 278 compatible = "arm,idle-state";
303 idle-state-nam 279 idle-state-name = "big-power-collapse";
304 /* CPU + L2 Po 280 /* CPU + L2 Power Collapse (C3, D4) */
305 arm,psci-suspe 281 arm,psci-suspend-param = <0x40000003>;
306 entry-latency- 282 entry-latency-us = <724>;
307 exit-latency-u 283 exit-latency-us = <2027>;
308 min-residency- 284 min-residency-us = <9419>;
309 local-timer-st 285 local-timer-stop;
310 }; 286 };
311 }; 287 };
312 }; 288 };
313 289
314 firmware { 290 firmware {
315 scm { 291 scm {
316 compatible = "qcom,scm 292 compatible = "qcom,scm-msm8998", "qcom,scm";
317 }; 293 };
318 }; 294 };
319 295
320 dsi_opp_table: opp-table-dsi { !! 296 tcsr_mutex: hwlock {
321 compatible = "operating-points !! 297 compatible = "qcom,tcsr-mutex";
322 !! 298 syscon = <&tcsr_mutex_regs 0 0x1000>;
323 opp-131250000 { !! 299 #hwlock-cells = <1>;
324 opp-hz = /bits/ 64 <13 <<
325 required-opps = <&rpmp <<
326 }; <<
327 <<
328 opp-210000000 { <<
329 opp-hz = /bits/ 64 <21 <<
330 required-opps = <&rpmp <<
331 }; <<
332 <<
333 opp-312500000 { <<
334 opp-hz = /bits/ 64 <31 <<
335 required-opps = <&rpmp <<
336 }; <<
337 }; 300 };
338 301
339 psci { 302 psci {
340 compatible = "arm,psci-1.0"; 303 compatible = "arm,psci-1.0";
341 method = "smc"; 304 method = "smc";
342 }; 305 };
343 306
344 rpm: remoteproc { !! 307 rpm-glink {
345 compatible = "qcom,msm8998-rpm !! 308 compatible = "qcom,glink-rpm";
>> 309
>> 310 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
>> 311 qcom,rpm-msg-ram = <&rpm_msg_ram>;
>> 312 mboxes = <&apcs_glb 0>;
>> 313
>> 314 rpm_requests: rpm-requests {
>> 315 compatible = "qcom,rpm-msm8998";
>> 316 qcom,glink-channels = "rpm_requests";
>> 317
>> 318 rpmcc: clock-controller {
>> 319 compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc";
>> 320 #clock-cells = <1>;
>> 321 };
>> 322
>> 323 rpmpd: power-controller {
>> 324 compatible = "qcom,msm8998-rpmpd";
>> 325 #power-domain-cells = <1>;
>> 326 operating-points-v2 = <&rpmpd_opp_table>;
346 327
347 glink-edge { !! 328 rpmpd_opp_table: opp-table {
348 compatible = "qcom,gli !! 329 compatible = "operating-points-v2";
349 330
350 interrupts = <GIC_SPI !! 331 rpmpd_opp_ret: opp1 {
351 qcom,rpm-msg-ram = <&r !! 332 opp-level = <16>;
352 mboxes = <&apcs_glb 0> !! 333 };
353 !! 334
354 rpm_requests: rpm-requ !! 335 rpmpd_opp_ret_plus: opp2 {
355 compatible = " !! 336 opp-level = <32>;
356 qcom,glink-cha !! 337 };
357 !! 338
358 rpmcc: clock-c !! 339 rpmpd_opp_min_svs: opp3 {
359 compat !! 340 opp-level = <48>;
360 clocks !! 341 };
361 clock- !! 342
362 #clock !! 343 rpmpd_opp_low_svs: opp4 {
363 }; !! 344 opp-level = <64>;
364 !! 345 };
365 rpmpd: power-c !! 346
366 compat !! 347 rpmpd_opp_svs: opp5 {
367 #power !! 348 opp-level = <128>;
368 operat !! 349 };
369 !! 350
370 rpmpd_ !! 351 rpmpd_opp_svs_plus: opp6 {
371 !! 352 opp-level = <192>;
372 !! 353 };
373 !! 354
374 !! 355 rpmpd_opp_nom: opp7 {
375 !! 356 opp-level = <256>;
376 !! 357 };
377 !! 358
378 !! 359 rpmpd_opp_nom_plus: opp8 {
379 !! 360 opp-level = <320>;
380 !! 361 };
381 !! 362
382 !! 363 rpmpd_opp_turbo: opp9 {
383 !! 364 opp-level = <384>;
384 !! 365 };
385 !! 366
386 !! 367 rpmpd_opp_turbo_plus: opp10 {
387 !! 368 opp-level = <512>;
388 <<
389 <<
390 <<
391 <<
392 <<
393 <<
394 <<
395 <<
396 <<
397 <<
398 <<
399 <<
400 <<
401 <<
402 <<
403 <<
404 <<
405 <<
406 <<
407 <<
408 <<
409 <<
410 <<
411 <<
412 }; 369 };
413 }; 370 };
414 }; 371 };
415 }; 372 };
416 }; 373 };
417 374
418 smem { 375 smem {
419 compatible = "qcom,smem"; 376 compatible = "qcom,smem";
420 memory-region = <&smem_mem>; 377 memory-region = <&smem_mem>;
421 hwlocks = <&tcsr_mutex 3>; 378 hwlocks = <&tcsr_mutex 3>;
422 }; 379 };
423 380
424 smp2p-lpass { 381 smp2p-lpass {
425 compatible = "qcom,smp2p"; 382 compatible = "qcom,smp2p";
426 qcom,smem = <443>, <429>; 383 qcom,smem = <443>, <429>;
427 384
428 interrupts = <GIC_SPI 158 IRQ_ 385 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
429 386
430 mboxes = <&apcs_glb 10>; 387 mboxes = <&apcs_glb 10>;
431 388
432 qcom,local-pid = <0>; 389 qcom,local-pid = <0>;
433 qcom,remote-pid = <2>; 390 qcom,remote-pid = <2>;
434 391
435 adsp_smp2p_out: master-kernel 392 adsp_smp2p_out: master-kernel {
436 qcom,entry-name = "mas 393 qcom,entry-name = "master-kernel";
437 #qcom,smem-state-cells 394 #qcom,smem-state-cells = <1>;
438 }; 395 };
439 396
440 adsp_smp2p_in: slave-kernel { 397 adsp_smp2p_in: slave-kernel {
441 qcom,entry-name = "sla 398 qcom,entry-name = "slave-kernel";
442 399
443 interrupt-controller; 400 interrupt-controller;
444 #interrupt-cells = <2> 401 #interrupt-cells = <2>;
445 }; 402 };
446 }; 403 };
447 404
448 smp2p-mpss { 405 smp2p-mpss {
449 compatible = "qcom,smp2p"; 406 compatible = "qcom,smp2p";
450 qcom,smem = <435>, <428>; 407 qcom,smem = <435>, <428>;
451 interrupts = <GIC_SPI 451 IRQ_ 408 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
452 mboxes = <&apcs_glb 14>; 409 mboxes = <&apcs_glb 14>;
453 qcom,local-pid = <0>; 410 qcom,local-pid = <0>;
454 qcom,remote-pid = <1>; 411 qcom,remote-pid = <1>;
455 412
456 modem_smp2p_out: master-kernel 413 modem_smp2p_out: master-kernel {
457 qcom,entry-name = "mas 414 qcom,entry-name = "master-kernel";
458 #qcom,smem-state-cells 415 #qcom,smem-state-cells = <1>;
459 }; 416 };
460 417
461 modem_smp2p_in: slave-kernel { 418 modem_smp2p_in: slave-kernel {
462 qcom,entry-name = "sla 419 qcom,entry-name = "slave-kernel";
463 interrupt-controller; 420 interrupt-controller;
464 #interrupt-cells = <2> 421 #interrupt-cells = <2>;
465 }; 422 };
466 }; 423 };
467 424
468 smp2p-slpi { 425 smp2p-slpi {
469 compatible = "qcom,smp2p"; 426 compatible = "qcom,smp2p";
470 qcom,smem = <481>, <430>; 427 qcom,smem = <481>, <430>;
471 interrupts = <GIC_SPI 178 IRQ_ 428 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
472 mboxes = <&apcs_glb 26>; 429 mboxes = <&apcs_glb 26>;
473 qcom,local-pid = <0>; 430 qcom,local-pid = <0>;
474 qcom,remote-pid = <3>; 431 qcom,remote-pid = <3>;
475 432
476 slpi_smp2p_out: master-kernel 433 slpi_smp2p_out: master-kernel {
477 qcom,entry-name = "mas 434 qcom,entry-name = "master-kernel";
478 #qcom,smem-state-cells 435 #qcom,smem-state-cells = <1>;
479 }; 436 };
480 437
481 slpi_smp2p_in: slave-kernel { 438 slpi_smp2p_in: slave-kernel {
482 qcom,entry-name = "sla 439 qcom,entry-name = "slave-kernel";
483 interrupt-controller; 440 interrupt-controller;
484 #interrupt-cells = <2> 441 #interrupt-cells = <2>;
485 }; 442 };
486 }; 443 };
487 444
488 thermal-zones { 445 thermal-zones {
489 cpu0-thermal { 446 cpu0-thermal {
490 polling-delay-passive 447 polling-delay-passive = <250>;
>> 448 polling-delay = <1000>;
491 449
492 thermal-sensors = <&ts 450 thermal-sensors = <&tsens0 1>;
493 451
494 trips { 452 trips {
495 cpu0_alert0: t !! 453 cpu0_alert0: trip-point@0 {
496 temper 454 temperature = <75000>;
497 hyster 455 hysteresis = <2000>;
498 type = 456 type = "passive";
499 }; 457 };
500 458
501 cpu0_crit: cpu !! 459 cpu0_crit: cpu_crit {
502 temper 460 temperature = <110000>;
503 hyster 461 hysteresis = <2000>;
504 type = 462 type = "critical";
505 }; 463 };
506 }; 464 };
507 }; 465 };
508 466
509 cpu1-thermal { 467 cpu1-thermal {
510 polling-delay-passive 468 polling-delay-passive = <250>;
>> 469 polling-delay = <1000>;
511 470
512 thermal-sensors = <&ts 471 thermal-sensors = <&tsens0 2>;
513 472
514 trips { 473 trips {
515 cpu1_alert0: t !! 474 cpu1_alert0: trip-point@0 {
516 temper 475 temperature = <75000>;
517 hyster 476 hysteresis = <2000>;
518 type = 477 type = "passive";
519 }; 478 };
520 479
521 cpu1_crit: cpu !! 480 cpu1_crit: cpu_crit {
522 temper 481 temperature = <110000>;
523 hyster 482 hysteresis = <2000>;
524 type = 483 type = "critical";
525 }; 484 };
526 }; 485 };
527 }; 486 };
528 487
529 cpu2-thermal { 488 cpu2-thermal {
530 polling-delay-passive 489 polling-delay-passive = <250>;
>> 490 polling-delay = <1000>;
531 491
532 thermal-sensors = <&ts 492 thermal-sensors = <&tsens0 3>;
533 493
534 trips { 494 trips {
535 cpu2_alert0: t !! 495 cpu2_alert0: trip-point@0 {
536 temper 496 temperature = <75000>;
537 hyster 497 hysteresis = <2000>;
538 type = 498 type = "passive";
539 }; 499 };
540 500
541 cpu2_crit: cpu !! 501 cpu2_crit: cpu_crit {
542 temper 502 temperature = <110000>;
543 hyster 503 hysteresis = <2000>;
544 type = 504 type = "critical";
545 }; 505 };
546 }; 506 };
547 }; 507 };
548 508
549 cpu3-thermal { 509 cpu3-thermal {
550 polling-delay-passive 510 polling-delay-passive = <250>;
>> 511 polling-delay = <1000>;
551 512
552 thermal-sensors = <&ts 513 thermal-sensors = <&tsens0 4>;
553 514
554 trips { 515 trips {
555 cpu3_alert0: t !! 516 cpu3_alert0: trip-point@0 {
556 temper 517 temperature = <75000>;
557 hyster 518 hysteresis = <2000>;
558 type = 519 type = "passive";
559 }; 520 };
560 521
561 cpu3_crit: cpu !! 522 cpu3_crit: cpu_crit {
562 temper 523 temperature = <110000>;
563 hyster 524 hysteresis = <2000>;
564 type = 525 type = "critical";
565 }; 526 };
566 }; 527 };
567 }; 528 };
568 529
569 cpu4-thermal { 530 cpu4-thermal {
570 polling-delay-passive 531 polling-delay-passive = <250>;
>> 532 polling-delay = <1000>;
571 533
572 thermal-sensors = <&ts 534 thermal-sensors = <&tsens0 7>;
573 535
574 trips { 536 trips {
575 cpu4_alert0: t !! 537 cpu4_alert0: trip-point@0 {
576 temper 538 temperature = <75000>;
577 hyster 539 hysteresis = <2000>;
578 type = 540 type = "passive";
579 }; 541 };
580 542
581 cpu4_crit: cpu !! 543 cpu4_crit: cpu_crit {
582 temper 544 temperature = <110000>;
583 hyster 545 hysteresis = <2000>;
584 type = 546 type = "critical";
585 }; 547 };
586 }; 548 };
587 }; 549 };
588 550
589 cpu5-thermal { 551 cpu5-thermal {
590 polling-delay-passive 552 polling-delay-passive = <250>;
>> 553 polling-delay = <1000>;
591 554
592 thermal-sensors = <&ts 555 thermal-sensors = <&tsens0 8>;
593 556
594 trips { 557 trips {
595 cpu5_alert0: t !! 558 cpu5_alert0: trip-point@0 {
596 temper 559 temperature = <75000>;
597 hyster 560 hysteresis = <2000>;
598 type = 561 type = "passive";
599 }; 562 };
600 563
601 cpu5_crit: cpu !! 564 cpu5_crit: cpu_crit {
602 temper 565 temperature = <110000>;
603 hyster 566 hysteresis = <2000>;
604 type = 567 type = "critical";
605 }; 568 };
606 }; 569 };
607 }; 570 };
608 571
609 cpu6-thermal { 572 cpu6-thermal {
610 polling-delay-passive 573 polling-delay-passive = <250>;
>> 574 polling-delay = <1000>;
611 575
612 thermal-sensors = <&ts 576 thermal-sensors = <&tsens0 9>;
613 577
614 trips { 578 trips {
615 cpu6_alert0: t !! 579 cpu6_alert0: trip-point@0 {
616 temper 580 temperature = <75000>;
617 hyster 581 hysteresis = <2000>;
618 type = 582 type = "passive";
619 }; 583 };
620 584
621 cpu6_crit: cpu !! 585 cpu6_crit: cpu_crit {
622 temper 586 temperature = <110000>;
623 hyster 587 hysteresis = <2000>;
624 type = 588 type = "critical";
625 }; 589 };
626 }; 590 };
627 }; 591 };
628 592
629 cpu7-thermal { 593 cpu7-thermal {
630 polling-delay-passive 594 polling-delay-passive = <250>;
>> 595 polling-delay = <1000>;
631 596
632 thermal-sensors = <&ts 597 thermal-sensors = <&tsens0 10>;
633 598
634 trips { 599 trips {
635 cpu7_alert0: t !! 600 cpu7_alert0: trip-point@0 {
636 temper 601 temperature = <75000>;
637 hyster 602 hysteresis = <2000>;
638 type = 603 type = "passive";
639 }; 604 };
640 605
641 cpu7_crit: cpu !! 606 cpu7_crit: cpu_crit {
642 temper 607 temperature = <110000>;
643 hyster 608 hysteresis = <2000>;
644 type = 609 type = "critical";
645 }; 610 };
646 }; 611 };
647 }; 612 };
648 613
649 gpu-bottom-thermal { !! 614 gpu-thermal-bottom {
650 polling-delay-passive 615 polling-delay-passive = <250>;
>> 616 polling-delay = <1000>;
651 617
652 thermal-sensors = <&ts 618 thermal-sensors = <&tsens0 12>;
653 619
654 trips { 620 trips {
655 gpu1_alert0: t !! 621 gpu1_alert0: trip-point@0 {
656 temper 622 temperature = <90000>;
657 hyster 623 hysteresis = <2000>;
658 type = 624 type = "hot";
659 }; 625 };
660 }; 626 };
661 }; 627 };
662 628
663 gpu-top-thermal { !! 629 gpu-thermal-top {
664 polling-delay-passive 630 polling-delay-passive = <250>;
>> 631 polling-delay = <1000>;
665 632
666 thermal-sensors = <&ts 633 thermal-sensors = <&tsens0 13>;
667 634
668 trips { 635 trips {
669 gpu2_alert0: t !! 636 gpu2_alert0: trip-point@0 {
670 temper 637 temperature = <90000>;
671 hyster 638 hysteresis = <2000>;
672 type = 639 type = "hot";
673 }; 640 };
674 }; 641 };
675 }; 642 };
676 643
677 clust0-mhm-thermal { 644 clust0-mhm-thermal {
678 polling-delay-passive 645 polling-delay-passive = <250>;
>> 646 polling-delay = <1000>;
679 647
680 thermal-sensors = <&ts 648 thermal-sensors = <&tsens0 5>;
681 649
682 trips { 650 trips {
683 cluster0_mhm_a !! 651 cluster0_mhm_alert0: trip-point@0 {
684 temper 652 temperature = <90000>;
685 hyster 653 hysteresis = <2000>;
686 type = 654 type = "hot";
687 }; 655 };
688 }; 656 };
689 }; 657 };
690 658
691 clust1-mhm-thermal { 659 clust1-mhm-thermal {
692 polling-delay-passive 660 polling-delay-passive = <250>;
>> 661 polling-delay = <1000>;
693 662
694 thermal-sensors = <&ts 663 thermal-sensors = <&tsens0 6>;
695 664
696 trips { 665 trips {
697 cluster1_mhm_a !! 666 cluster1_mhm_alert0: trip-point@0 {
698 temper 667 temperature = <90000>;
699 hyster 668 hysteresis = <2000>;
700 type = 669 type = "hot";
701 }; 670 };
702 }; 671 };
703 }; 672 };
704 673
705 cluster1-l2-thermal { 674 cluster1-l2-thermal {
706 polling-delay-passive 675 polling-delay-passive = <250>;
>> 676 polling-delay = <1000>;
707 677
708 thermal-sensors = <&ts 678 thermal-sensors = <&tsens0 11>;
709 679
710 trips { 680 trips {
711 cluster1_l2_al !! 681 cluster1_l2_alert0: trip-point@0 {
712 temper 682 temperature = <90000>;
713 hyster 683 hysteresis = <2000>;
714 type = 684 type = "hot";
715 }; 685 };
716 }; 686 };
717 }; 687 };
718 688
719 modem-thermal { 689 modem-thermal {
720 polling-delay-passive 690 polling-delay-passive = <250>;
>> 691 polling-delay = <1000>;
721 692
722 thermal-sensors = <&ts 693 thermal-sensors = <&tsens1 1>;
723 694
724 trips { 695 trips {
725 modem_alert0: !! 696 modem_alert0: trip-point@0 {
726 temper 697 temperature = <90000>;
727 hyster 698 hysteresis = <2000>;
728 type = 699 type = "hot";
729 }; 700 };
730 }; 701 };
731 }; 702 };
732 703
733 mem-thermal { 704 mem-thermal {
734 polling-delay-passive 705 polling-delay-passive = <250>;
>> 706 polling-delay = <1000>;
735 707
736 thermal-sensors = <&ts 708 thermal-sensors = <&tsens1 2>;
737 709
738 trips { 710 trips {
739 mem_alert0: tr !! 711 mem_alert0: trip-point@0 {
740 temper 712 temperature = <90000>;
741 hyster 713 hysteresis = <2000>;
742 type = 714 type = "hot";
743 }; 715 };
744 }; 716 };
745 }; 717 };
746 718
747 wlan-thermal { 719 wlan-thermal {
748 polling-delay-passive 720 polling-delay-passive = <250>;
>> 721 polling-delay = <1000>;
749 722
750 thermal-sensors = <&ts 723 thermal-sensors = <&tsens1 3>;
751 724
752 trips { 725 trips {
753 wlan_alert0: t !! 726 wlan_alert0: trip-point@0 {
754 temper 727 temperature = <90000>;
755 hyster 728 hysteresis = <2000>;
756 type = 729 type = "hot";
757 }; 730 };
758 }; 731 };
759 }; 732 };
760 733
761 q6-dsp-thermal { 734 q6-dsp-thermal {
762 polling-delay-passive 735 polling-delay-passive = <250>;
>> 736 polling-delay = <1000>;
763 737
764 thermal-sensors = <&ts 738 thermal-sensors = <&tsens1 4>;
765 739
766 trips { 740 trips {
767 q6_dsp_alert0: !! 741 q6_dsp_alert0: trip-point@0 {
768 temper 742 temperature = <90000>;
769 hyster 743 hysteresis = <2000>;
770 type = 744 type = "hot";
771 }; 745 };
772 }; 746 };
773 }; 747 };
774 748
775 camera-thermal { 749 camera-thermal {
776 polling-delay-passive 750 polling-delay-passive = <250>;
>> 751 polling-delay = <1000>;
777 752
778 thermal-sensors = <&ts 753 thermal-sensors = <&tsens1 5>;
779 754
780 trips { 755 trips {
781 camera_alert0: !! 756 camera_alert0: trip-point@0 {
782 temper 757 temperature = <90000>;
783 hyster 758 hysteresis = <2000>;
784 type = 759 type = "hot";
785 }; 760 };
786 }; 761 };
787 }; 762 };
788 763
789 multimedia-thermal { 764 multimedia-thermal {
790 polling-delay-passive 765 polling-delay-passive = <250>;
>> 766 polling-delay = <1000>;
791 767
792 thermal-sensors = <&ts 768 thermal-sensors = <&tsens1 6>;
793 769
794 trips { 770 trips {
795 multimedia_ale !! 771 multimedia_alert0: trip-point@0 {
796 temper 772 temperature = <90000>;
797 hyster 773 hysteresis = <2000>;
798 type = 774 type = "hot";
799 }; 775 };
800 }; 776 };
801 }; 777 };
802 }; 778 };
803 779
804 timer { 780 timer {
805 compatible = "arm,armv8-timer" 781 compatible = "arm,armv8-timer";
806 interrupts = <GIC_PPI 1 IRQ_TY 782 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
807 <GIC_PPI 2 IRQ_TY 783 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
808 <GIC_PPI 3 IRQ_TY 784 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
809 <GIC_PPI 0 IRQ_TY 785 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
810 }; 786 };
811 787
812 soc: soc@0 { !! 788 soc: soc {
813 #address-cells = <1>; 789 #address-cells = <1>;
814 #size-cells = <1>; 790 #size-cells = <1>;
815 ranges = <0 0 0 0xffffffff>; 791 ranges = <0 0 0 0xffffffff>;
816 compatible = "simple-bus"; 792 compatible = "simple-bus";
817 793
818 gcc: clock-controller@100000 { 794 gcc: clock-controller@100000 {
819 compatible = "qcom,gcc 795 compatible = "qcom,gcc-msm8998";
820 #clock-cells = <1>; 796 #clock-cells = <1>;
821 #reset-cells = <1>; 797 #reset-cells = <1>;
822 #power-domain-cells = 798 #power-domain-cells = <1>;
823 reg = <0x00100000 0xb0 799 reg = <0x00100000 0xb0000>;
824 <<
825 clock-names = "xo", "s <<
826 clocks = <&rpmcc RPM_S <<
827 <<
828 /* <<
829 * The hypervisor typi <<
830 * reside as read-only <<
831 * these clocks on a d <<
832 * enabled but unused <<
833 * to reboot. <<
834 * In light of that, w <<
835 * as protected. The b <<
836 * list of protected c <<
837 * desired for the HLO <<
838 */ <<
839 protected-clocks = <AG <<
840 <SS <<
841 <SS <<
842 }; 800 };
843 801
844 rpm_msg_ram: sram@778000 { !! 802 rpm_msg_ram: memory@778000 {
845 compatible = "qcom,rpm 803 compatible = "qcom,rpm-msg-ram";
846 reg = <0x00778000 0x70 804 reg = <0x00778000 0x7000>;
847 }; 805 };
848 806
849 qfprom: qfprom@784000 { !! 807 qfprom: qfprom@780000 {
850 compatible = "qcom,msm !! 808 compatible = "qcom,qfprom";
851 reg = <0x00784000 0x62 !! 809 reg = <0x00780000 0x621c>;
852 #address-cells = <1>; 810 #address-cells = <1>;
853 #size-cells = <1>; 811 #size-cells = <1>;
854 812
855 qusb2_hstx_trim: hstx- !! 813 qusb2_hstx_trim: hstx-trim@423a {
856 reg = <0x23a 0 !! 814 reg = <0x423a 0x1>;
857 bits = <0 4>; 815 bits = <0 4>;
858 }; 816 };
859 }; 817 };
860 818
861 tsens0: thermal@10ab000 { 819 tsens0: thermal@10ab000 {
862 compatible = "qcom,msm 820 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
863 reg = <0x010ab000 0x10 821 reg = <0x010ab000 0x1000>, /* TM */
864 <0x010aa000 0x10 822 <0x010aa000 0x1000>; /* SROT */
>> 823
865 #qcom,sensors = <14>; 824 #qcom,sensors = <14>;
866 interrupts = <GIC_SPI <<
867 <GIC_SPI <<
868 interrupt-names = "upl <<
869 #thermal-sensor-cells 825 #thermal-sensor-cells = <1>;
870 }; 826 };
871 827
872 tsens1: thermal@10ae000 { 828 tsens1: thermal@10ae000 {
873 compatible = "qcom,msm 829 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
874 reg = <0x010ae000 0x10 830 reg = <0x010ae000 0x1000>, /* TM */
875 <0x010ad000 0x10 831 <0x010ad000 0x1000>; /* SROT */
>> 832
876 #qcom,sensors = <8>; 833 #qcom,sensors = <8>;
877 interrupts = <GIC_SPI <<
878 <GIC_SPI <<
879 interrupt-names = "upl <<
880 #thermal-sensor-cells 834 #thermal-sensor-cells = <1>;
881 }; 835 };
882 836
883 anoc1_smmu: iommu@1680000 { 837 anoc1_smmu: iommu@1680000 {
884 compatible = "qcom,msm 838 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
885 reg = <0x01680000 0x10 839 reg = <0x01680000 0x10000>;
886 #iommu-cells = <1>; 840 #iommu-cells = <1>;
887 841
888 #global-interrupts = < 842 #global-interrupts = <0>;
889 interrupts = 843 interrupts =
890 <GIC_SPI 364 I 844 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
891 <GIC_SPI 365 I 845 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
892 <GIC_SPI 366 I 846 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
893 <GIC_SPI 367 I 847 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
894 <GIC_SPI 368 I 848 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
895 <GIC_SPI 369 I 849 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>;
896 }; 850 };
897 851
898 anoc2_smmu: iommu@16c0000 { !! 852 pcie0: pci@1c00000 {
899 compatible = "qcom,msm !! 853 compatible = "qcom,pcie-msm8996";
900 reg = <0x016c0000 0x40 !! 854 reg = <0x01c00000 0x2000>,
901 #iommu-cells = <1>; !! 855 <0x1b000000 0xf1d>,
902 !! 856 <0x1b000f20 0xa8>,
903 #global-interrupts = < !! 857 <0x1b100000 0x100000>;
904 interrupts = <<
905 <GIC_SPI 373 I <<
906 <GIC_SPI 374 I <<
907 <GIC_SPI 375 I <<
908 <GIC_SPI 376 I <<
909 <GIC_SPI 377 I <<
910 <GIC_SPI 378 I <<
911 <GIC_SPI 462 I <<
912 <GIC_SPI 463 I <<
913 <GIC_SPI 464 I <<
914 <GIC_SPI 465 I <<
915 }; <<
916 <<
917 pcie0: pcie@1c00000 { <<
918 compatible = "qcom,pci <<
919 reg = <0x01c00000 0x20 <<
920 <0x1b000000 0xf1 <<
921 <0x1b000f20 0xa8 <<
922 <0x1b100000 0x10 <<
923 reg-names = "parf", "d 858 reg-names = "parf", "dbi", "elbi", "config";
924 device_type = "pci"; 859 device_type = "pci";
925 linux,pci-domain = <0> 860 linux,pci-domain = <0>;
926 bus-range = <0x00 0xff 861 bus-range = <0x00 0xff>;
927 #address-cells = <3>; 862 #address-cells = <3>;
928 #size-cells = <2>; 863 #size-cells = <2>;
929 num-lanes = <1>; 864 num-lanes = <1>;
930 phys = <&pcie_phy>; !! 865 phys = <&pciephy>;
931 phy-names = "pciephy"; 866 phy-names = "pciephy";
932 status = "disabled"; <<
933 867
934 ranges = <0x01000000 0 !! 868 ranges = <0x01000000 0x0 0x1b200000 0x1b200000 0x0 0x100000>,
935 <0x02000000 0 869 <0x02000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>;
936 870
937 #interrupt-cells = <1> 871 #interrupt-cells = <1>;
938 interrupts = <GIC_SPI 872 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
939 interrupt-names = "msi 873 interrupt-names = "msi";
940 interrupt-map-mask = < 874 interrupt-map-mask = <0 0 0 0x7>;
941 interrupt-map = <0 0 0 !! 875 interrupt-map = <0 0 0 1 &intc 0 0 135 IRQ_TYPE_LEVEL_HIGH>,
942 <0 0 0 876 <0 0 0 2 &intc 0 0 136 IRQ_TYPE_LEVEL_HIGH>,
943 <0 0 0 877 <0 0 0 3 &intc 0 0 138 IRQ_TYPE_LEVEL_HIGH>,
944 <0 0 0 878 <0 0 0 4 &intc 0 0 139 IRQ_TYPE_LEVEL_HIGH>;
945 879
946 clocks = <&gcc GCC_PCI 880 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
947 <&gcc GCC_PCI <<
948 <&gcc GCC_PCI <<
949 <&gcc GCC_PCI 881 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
950 <&gcc GCC_PCI !! 882 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
951 clock-names = "pipe", !! 883 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
>> 884 <&gcc GCC_PCIE_0_AUX_CLK>;
>> 885 clock-names = "pipe", "bus_master", "bus_slave", "cfg", "aux";
952 886
953 power-domains = <&gcc 887 power-domains = <&gcc PCIE_0_GDSC>;
954 iommu-map = <0x100 &an 888 iommu-map = <0x100 &anoc1_smmu 0x1480 1>;
955 perst-gpios = <&tlmm 3 889 perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
956 <<
957 pcie@0 { <<
958 device_type = <<
959 reg = <0x0 0x0 <<
960 bus-range = <0 <<
961 <<
962 #address-cells <<
963 #size-cells = <<
964 ranges; <<
965 }; <<
966 }; 890 };
967 891
968 pcie_phy: phy@1c06000 { !! 892 phy@1c06000 {
969 compatible = "qcom,msm 893 compatible = "qcom,msm8998-qmp-pcie-phy";
970 reg = <0x01c06000 0x10 !! 894 reg = <0x01c06000 0x18c>;
971 status = "disabled"; !! 895 #address-cells = <1>;
>> 896 #size-cells = <1>;
>> 897 ranges;
972 898
973 clocks = <&gcc GCC_PCI 899 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
974 <&gcc GCC_PCI 900 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
975 <&gcc GCC_PCI !! 901 <&gcc GCC_PCIE_CLKREF_CLK>;
976 <&gcc GCC_PCI !! 902 clock-names = "aux", "cfg_ahb", "ref";
977 clock-names = "aux", <<
978 "cfg_ahb <<
979 "ref", <<
980 "pipe"; <<
981 <<
982 clock-output-names = " <<
983 #clock-cells = <0>; <<
984 <<
985 #phy-cells = <0>; <<
986 903
987 resets = <&gcc GCC_PCI 904 resets = <&gcc GCC_PCIE_0_PHY_BCR>, <&gcc GCC_PCIE_PHY_BCR>;
988 reset-names = "phy", " 905 reset-names = "phy", "common";
989 906
990 vdda-phy-supply = <&vr 907 vdda-phy-supply = <&vreg_l1a_0p875>;
991 vdda-pll-supply = <&vr 908 vdda-pll-supply = <&vreg_l2a_1p2>;
>> 909
>> 910 pciephy: lane@1c06800 {
>> 911 reg = <0x01c06200 0x128>, <0x01c06400 0x1fc>, <0x01c06800 0x20c>;
>> 912 #phy-cells = <0>;
>> 913
>> 914 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
>> 915 clock-names = "pipe0";
>> 916 clock-output-names = "pcie_0_pipe_clk_src";
>> 917 #clock-cells = <0>;
>> 918 };
992 }; 919 };
993 920
994 ufshc: ufshc@1da4000 { 921 ufshc: ufshc@1da4000 {
995 compatible = "qcom,msm 922 compatible = "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
996 reg = <0x01da4000 0x25 923 reg = <0x01da4000 0x2500>;
997 interrupts = <GIC_SPI 924 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
998 phys = <&ufsphy>; !! 925 phys = <&ufsphy_lanes>;
999 phy-names = "ufsphy"; 926 phy-names = "ufsphy";
1000 lanes-per-direction = 927 lanes-per-direction = <2>;
1001 power-domains = <&gcc 928 power-domains = <&gcc UFS_GDSC>;
1002 status = "disabled"; <<
1003 #reset-cells = <1>; 929 #reset-cells = <1>;
1004 930
1005 clock-names = 931 clock-names =
1006 "core_clk", 932 "core_clk",
1007 "bus_aggr_clk 933 "bus_aggr_clk",
1008 "iface_clk", 934 "iface_clk",
1009 "core_clk_uni 935 "core_clk_unipro",
1010 "ref_clk", 936 "ref_clk",
1011 "tx_lane0_syn 937 "tx_lane0_sync_clk",
1012 "rx_lane0_syn 938 "rx_lane0_sync_clk",
1013 "rx_lane1_syn 939 "rx_lane1_sync_clk";
1014 clocks = 940 clocks =
1015 <&gcc GCC_UFS 941 <&gcc GCC_UFS_AXI_CLK>,
1016 <&gcc GCC_AGG 942 <&gcc GCC_AGGRE1_UFS_AXI_CLK>,
1017 <&gcc GCC_UFS 943 <&gcc GCC_UFS_AHB_CLK>,
1018 <&gcc GCC_UFS 944 <&gcc GCC_UFS_UNIPRO_CORE_CLK>,
1019 <&rpmcc RPM_S 945 <&rpmcc RPM_SMD_LN_BB_CLK1>,
1020 <&gcc GCC_UFS 946 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
1021 <&gcc GCC_UFS 947 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>,
1022 <&gcc GCC_UFS 948 <&gcc GCC_UFS_RX_SYMBOL_1_CLK>;
1023 freq-table-hz = 949 freq-table-hz =
1024 <50000000 200 950 <50000000 200000000>,
1025 <0 0>, 951 <0 0>,
1026 <0 0>, 952 <0 0>,
1027 <37500000 150 953 <37500000 150000000>,
1028 <0 0>, 954 <0 0>,
1029 <0 0>, 955 <0 0>,
1030 <0 0>, 956 <0 0>,
1031 <0 0>; 957 <0 0>;
1032 958
1033 resets = <&gcc GCC_UF 959 resets = <&gcc GCC_UFS_BCR>;
1034 reset-names = "rst"; 960 reset-names = "rst";
1035 }; 961 };
1036 962
1037 ufsphy: phy@1da7000 { 963 ufsphy: phy@1da7000 {
1038 compatible = "qcom,ms 964 compatible = "qcom,msm8998-qmp-ufs-phy";
1039 reg = <0x01da7000 0x1 !! 965 reg = <0x01da7000 0x18c>;
>> 966 #address-cells = <1>;
>> 967 #size-cells = <1>;
>> 968 ranges;
1040 969
1041 clocks = <&rpmcc RPM_ !! 970 clock-names =
1042 <&gcc GCC_UF !! 971 "ref",
1043 <&gcc GCC_UF !! 972 "ref_aux";
1044 clock-names = "ref", !! 973 clocks =
1045 "ref_au !! 974 <&gcc GCC_UFS_CLKREF_CLK>,
1046 "qref"; !! 975 <&gcc GCC_UFS_PHY_AUX_CLK>;
1047 976
1048 reset-names = "ufsphy 977 reset-names = "ufsphy";
1049 resets = <&ufshc 0>; 978 resets = <&ufshc 0>;
1050 979
1051 #phy-cells = <0>; !! 980 ufsphy_lanes: lanes@1da7400 {
1052 status = "disabled"; !! 981 reg = <0x01da7400 0x128>,
1053 }; !! 982 <0x01da7600 0x1fc>,
1054 !! 983 <0x01da7c00 0x1dc>,
1055 tcsr_mutex: hwlock@1f40000 { !! 984 <0x01da7800 0x128>,
1056 compatible = "qcom,tc !! 985 <0x01da7a00 0x1fc>;
1057 reg = <0x01f40000 0x2 !! 986 #phy-cells = <0>;
1058 #hwlock-cells = <1>; !! 987 };
1059 }; <<
1060 <<
1061 tcsr_regs_1: syscon@1f60000 { <<
1062 compatible = "qcom,ms <<
1063 reg = <0x01f60000 0x2 <<
1064 }; 988 };
1065 989
1066 tcsr_regs_2: syscon@1fc0000 { !! 990 tcsr_mutex_regs: syscon@1f40000 {
1067 compatible = "qcom,ms !! 991 compatible = "syscon";
1068 reg = <0x01fc0000 0x2 !! 992 reg = <0x01f40000 0x40000>;
1069 }; 993 };
1070 994
1071 tlmm: pinctrl@3400000 { 995 tlmm: pinctrl@3400000 {
1072 compatible = "qcom,ms 996 compatible = "qcom,msm8998-pinctrl";
1073 reg = <0x03400000 0xc 997 reg = <0x03400000 0xc00000>;
1074 interrupts = <GIC_SPI 998 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1075 gpio-ranges = <&tlmm <<
1076 gpio-controller; 999 gpio-controller;
1077 #gpio-cells = <2>; !! 1000 #gpio-cells = <0x2>;
1078 interrupt-controller; 1001 interrupt-controller;
1079 #interrupt-cells = <2 !! 1002 #interrupt-cells = <0x2>;
1080 <<
1081 sdc2_on: sdc2-on-stat <<
1082 clk-pins { <<
1083 pins <<
1084 drive <<
1085 bias- <<
1086 }; <<
1087 <<
1088 cmd-pins { <<
1089 pins <<
1090 drive <<
1091 bias- <<
1092 }; <<
1093 <<
1094 data-pins { <<
1095 pins <<
1096 drive <<
1097 bias- <<
1098 }; <<
1099 }; <<
1100 <<
1101 sdc2_off: sdc2-off-st <<
1102 clk-pins { <<
1103 pins <<
1104 drive <<
1105 bias- <<
1106 }; <<
1107 <<
1108 cmd-pins { <<
1109 pins <<
1110 drive <<
1111 bias- <<
1112 }; <<
1113 <<
1114 data-pins { <<
1115 pins <<
1116 drive <<
1117 bias- <<
1118 }; <<
1119 }; <<
1120 <<
1121 sdc2_cd: sdc2-cd-stat <<
1122 pins = "gpio9 <<
1123 function = "g <<
1124 bias-pull-up; <<
1125 drive-strengt <<
1126 }; <<
1127 <<
1128 blsp1_uart3_on: blsp1 <<
1129 tx-pins { <<
1130 pins <<
1131 funct <<
1132 drive <<
1133 bias- <<
1134 }; <<
1135 <<
1136 rx-pins { <<
1137 pins <<
1138 funct <<
1139 drive <<
1140 bias- <<
1141 }; <<
1142 <<
1143 cts-pins { <<
1144 pins <<
1145 funct <<
1146 drive <<
1147 bias- <<
1148 }; <<
1149 <<
1150 rfr-pins { <<
1151 pins <<
1152 funct <<
1153 drive <<
1154 bias- <<
1155 }; <<
1156 }; <<
1157 <<
1158 blsp1_i2c1_default: b <<
1159 pins = "gpio2 <<
1160 function = "b <<
1161 drive-strengt <<
1162 bias-disable; <<
1163 }; <<
1164 <<
1165 blsp1_i2c1_sleep: bls <<
1166 pins = "gpio2 <<
1167 function = "b <<
1168 drive-strengt <<
1169 bias-pull-up; <<
1170 }; <<
1171 <<
1172 blsp1_i2c2_default: b <<
1173 pins = "gpio3 <<
1174 function = "b <<
1175 drive-strengt <<
1176 bias-disable; <<
1177 }; <<
1178 <<
1179 blsp1_i2c2_sleep: bls <<
1180 pins = "gpio3 <<
1181 function = "b <<
1182 drive-strengt <<
1183 bias-pull-up; <<
1184 }; <<
1185 <<
1186 blsp1_i2c3_default: b <<
1187 pins = "gpio4 <<
1188 function = "b <<
1189 drive-strengt <<
1190 bias-disable; <<
1191 }; <<
1192 <<
1193 blsp1_i2c3_sleep: bls <<
1194 pins = "gpio4 <<
1195 function = "b <<
1196 drive-strengt <<
1197 bias-pull-up; <<
1198 }; <<
1199 <<
1200 blsp1_i2c4_default: b <<
1201 pins = "gpio1 <<
1202 function = "b <<
1203 drive-strengt <<
1204 bias-disable; <<
1205 }; <<
1206 <<
1207 blsp1_i2c4_sleep: bls <<
1208 pins = "gpio1 <<
1209 function = "b <<
1210 drive-strengt <<
1211 bias-pull-up; <<
1212 }; <<
1213 <<
1214 blsp1_i2c5_default: b <<
1215 pins = "gpio8 <<
1216 function = "b <<
1217 drive-strengt <<
1218 bias-disable; <<
1219 }; <<
1220 <<
1221 blsp1_i2c5_sleep: bls <<
1222 pins = "gpio8 <<
1223 function = "b <<
1224 drive-strengt <<
1225 bias-pull-up; <<
1226 }; <<
1227 <<
1228 blsp1_i2c6_default: b <<
1229 pins = "gpio4 <<
1230 function = "b <<
1231 drive-strengt <<
1232 bias-disable; <<
1233 }; <<
1234 <<
1235 blsp1_i2c6_sleep: bls <<
1236 pins = "gpio4 <<
1237 function = "b <<
1238 drive-strengt <<
1239 bias-pull-up; <<
1240 }; <<
1241 <<
1242 blsp1_spi_b_default: <<
1243 pins = "gpio2 <<
1244 function = "b <<
1245 drive-strengt <<
1246 bias-disable; <<
1247 }; <<
1248 <<
1249 blsp1_spi1_default: b <<
1250 pins = "gpio0 <<
1251 function = "b <<
1252 drive-strengt <<
1253 bias-disable; <<
1254 }; <<
1255 <<
1256 blsp1_spi2_default: b <<
1257 pins = "gpio3 <<
1258 function = "b <<
1259 drive-strengt <<
1260 bias-disable; <<
1261 }; <<
1262 <<
1263 blsp1_spi3_default: b <<
1264 pins = "gpio4 <<
1265 function = "b <<
1266 drive-strengt <<
1267 bias-disable; <<
1268 }; <<
1269 <<
1270 blsp1_spi4_default: b <<
1271 pins = "gpio8 <<
1272 function = "b <<
1273 drive-strengt <<
1274 bias-disable; <<
1275 }; <<
1276 <<
1277 blsp1_spi5_default: b <<
1278 pins = "gpio8 <<
1279 function = "b <<
1280 drive-strengt <<
1281 bias-disable; <<
1282 }; <<
1283 <<
1284 blsp1_spi6_default: b <<
1285 pins = "gpio4 <<
1286 function = "b <<
1287 drive-strengt <<
1288 bias-disable; <<
1289 }; <<
1290 <<
1291 <<
1292 /* 6 interfaces per Q <<
1293 blsp2_i2c1_default: b <<
1294 pins = "gpio5 <<
1295 function = "b <<
1296 drive-strengt <<
1297 bias-disable; <<
1298 }; <<
1299 <<
1300 blsp2_i2c1_sleep: bls <<
1301 pins = "gpio5 <<
1302 function = "b <<
1303 drive-strengt <<
1304 bias-pull-up; <<
1305 }; <<
1306 <<
1307 blsp2_i2c2_default: b <<
1308 pins = "gpio6 <<
1309 function = "b <<
1310 drive-strengt <<
1311 bias-disable; <<
1312 }; <<
1313 <<
1314 blsp2_i2c2_sleep: bls <<
1315 pins = "gpio6 <<
1316 function = "b <<
1317 drive-strengt <<
1318 bias-pull-up; <<
1319 }; <<
1320 <<
1321 blsp2_i2c3_default: b <<
1322 pins = "gpio5 <<
1323 function = "b <<
1324 drive-strengt <<
1325 bias-disable; <<
1326 }; <<
1327 <<
1328 blsp2_i2c3_sleep: bls <<
1329 pins = "gpio5 <<
1330 function = "b <<
1331 drive-strengt <<
1332 bias-pull-up; <<
1333 }; <<
1334 <<
1335 blsp2_i2c4_default: b <<
1336 pins = "gpio6 <<
1337 function = "b <<
1338 drive-strengt <<
1339 bias-disable; <<
1340 }; <<
1341 <<
1342 blsp2_i2c4_sleep: bls <<
1343 pins = "gpio6 <<
1344 function = "b <<
1345 drive-strengt <<
1346 bias-pull-up; <<
1347 }; <<
1348 <<
1349 blsp2_i2c5_default: b <<
1350 pins = "gpio6 <<
1351 function = "b <<
1352 drive-strengt <<
1353 bias-disable; <<
1354 }; <<
1355 <<
1356 blsp2_i2c5_sleep: bls <<
1357 pins = "gpio6 <<
1358 function = "b <<
1359 drive-strengt <<
1360 bias-pull-up; <<
1361 }; <<
1362 <<
1363 blsp2_i2c6_default: b <<
1364 pins = "gpio8 <<
1365 function = "b <<
1366 drive-strengt <<
1367 bias-disable; <<
1368 }; <<
1369 <<
1370 blsp2_i2c6_sleep: bls <<
1371 pins = "gpio8 <<
1372 function = "b <<
1373 drive-strengt <<
1374 bias-pull-up; <<
1375 }; <<
1376 <<
1377 blsp2_spi1_default: b <<
1378 pins = "gpio5 <<
1379 function = "b <<
1380 drive-strengt <<
1381 bias-disable; <<
1382 }; <<
1383 <<
1384 blsp2_spi2_default: b <<
1385 pins = "gpio4 <<
1386 function = "b <<
1387 drive-strengt <<
1388 bias-disable; <<
1389 }; <<
1390 <<
1391 blsp2_spi3_default: b <<
1392 pins = "gpio4 <<
1393 function = "b <<
1394 drive-strengt <<
1395 bias-disable; <<
1396 }; <<
1397 <<
1398 blsp2_spi4_default: b <<
1399 pins = "gpio6 <<
1400 function = "b <<
1401 drive-strengt <<
1402 bias-disable; <<
1403 }; <<
1404 <<
1405 blsp2_spi5_default: b <<
1406 pins = "gpio5 <<
1407 function = "b <<
1408 drive-strengt <<
1409 bias-disable; <<
1410 }; <<
1411 <<
1412 blsp2_spi6_default: b <<
1413 pins = "gpio8 <<
1414 function = "b <<
1415 drive-strengt <<
1416 bias-disable; <<
1417 }; <<
1418 }; <<
1419 <<
1420 remoteproc_mss: remoteproc@40 <<
1421 compatible = "qcom,ms <<
1422 reg = <0x04080000 0x1 <<
1423 reg-names = "qdsp6", <<
1424 <<
1425 interrupts-extended = <<
1426 <&intc GIC_SP <<
1427 <&modem_smp2p <<
1428 <&modem_smp2p <<
1429 <&modem_smp2p <<
1430 <&modem_smp2p <<
1431 <&modem_smp2p <<
1432 interrupt-names = "wd <<
1433 "ha <<
1434 "sh <<
1435 <<
1436 clocks = <&gcc GCC_MS <<
1437 <&gcc GCC_BI <<
1438 <&gcc GCC_BO <<
1439 <&gcc GCC_MS <<
1440 <&gcc GCC_MS <<
1441 <&gcc GCC_MS <<
1442 <&rpmcc RPM_ <<
1443 <&rpmcc RPM_ <<
1444 clock-names = "iface" <<
1445 "snoc_a <<
1446 <<
1447 qcom,smem-states = <& <<
1448 qcom,smem-state-names <<
1449 <<
1450 resets = <&gcc GCC_MS <<
1451 reset-names = "mss_re <<
1452 <<
1453 qcom,halt-regs = <&tc <<
1454 <<
1455 power-domains = <&rpm <<
1456 <&rpm <<
1457 power-domain-names = <<
1458 <<
1459 status = "disabled"; <<
1460 <<
1461 mba { <<
1462 memory-region <<
1463 }; <<
1464 <<
1465 mpss { <<
1466 memory-region <<
1467 }; <<
1468 <<
1469 metadata { <<
1470 memory-region <<
1471 }; <<
1472 <<
1473 glink-edge { <<
1474 interrupts = <<
1475 label = "mode <<
1476 qcom,remote-p <<
1477 mboxes = <&ap <<
1478 }; <<
1479 }; <<
1480 <<
1481 adreno_gpu: gpu@5000000 { <<
1482 compatible = "qcom,ad <<
1483 reg = <0x05000000 0x4 <<
1484 reg-names = "kgsl_3d0 <<
1485 <<
1486 clocks = <&gcc GCC_GP <<
1487 <&gpucc RBBMT <<
1488 <&gcc GCC_BIM <<
1489 <&gcc GCC_GPU <<
1490 <&gpucc RBCPR <<
1491 <&gpucc GFX3D <<
1492 clock-names = "iface" <<
1493 "rbbmtimer", <<
1494 "mem", <<
1495 "mem_iface", <<
1496 "rbcpr", <<
1497 "core"; <<
1498 <<
1499 interrupts = <GIC_SPI <<
1500 iommus = <&adreno_smm <<
1501 operating-points-v2 = <<
1502 power-domains = <&rpm <<
1503 status = "disabled"; <<
1504 <<
1505 gpu_opp_table: opp-ta <<
1506 compatible = <<
1507 opp-710000097 <<
1508 opp-h <<
1509 opp-l <<
1510 opp-s <<
1511 }; <<
1512 <<
1513 opp-670000048 <<
1514 opp-h <<
1515 opp-l <<
1516 opp-s <<
1517 }; <<
1518 <<
1519 opp-596000097 <<
1520 opp-h <<
1521 opp-l <<
1522 opp-s <<
1523 }; <<
1524 <<
1525 opp-515000097 <<
1526 opp-h <<
1527 opp-l <<
1528 opp-s <<
1529 }; <<
1530 <<
1531 opp-414000000 <<
1532 opp-h <<
1533 opp-l <<
1534 opp-s <<
1535 }; <<
1536 <<
1537 opp-342000000 <<
1538 opp-h <<
1539 opp-l <<
1540 opp-s <<
1541 }; <<
1542 <<
1543 opp-257000000 <<
1544 opp-h <<
1545 opp-l <<
1546 opp-s <<
1547 }; <<
1548 }; <<
1549 }; <<
1550 <<
1551 adreno_smmu: iommu@5040000 { <<
1552 compatible = "qcom,ms <<
1553 reg = <0x05040000 0x1 <<
1554 clocks = <&gcc GCC_GP <<
1555 <&gcc GCC_BI <<
1556 <&gcc GCC_GP <<
1557 clock-names = "iface" <<
1558 <<
1559 #global-interrupts = <<
1560 #iommu-cells = <1>; <<
1561 interrupts = <<
1562 <GIC_SPI 329 <<
1563 <GIC_SPI 330 <<
1564 <GIC_SPI 331 <<
1565 /* <<
1566 * GPU-GX GDSC's pare <<
1567 * GPU-CX for SMMU bu <<
1568 * Contemporarily, we <<
1569 * domain in the Adre <<
1570 * Enable GPU CX/GX G <<
1571 * SoC VDDMX RPM Powe <<
1572 */ <<
1573 power-domains = <&gpu <<
1574 }; <<
1575 <<
1576 gpucc: clock-controller@50650 <<
1577 compatible = "qcom,ms <<
1578 #clock-cells = <1>; <<
1579 #reset-cells = <1>; <<
1580 #power-domain-cells = <<
1581 reg = <0x05065000 0x9 <<
1582 <<
1583 clocks = <&rpmcc RPM_ <<
1584 <&gcc GCC_GP <<
1585 clock-names = "xo", <<
1586 "gpll0" <<
1587 }; <<
1588 <<
1589 lpass_q6_smmu: iommu@5100000 <<
1590 compatible = "qcom,ms <<
1591 reg = <0x05100000 0x4 <<
1592 clocks = <&gcc HLOS1_ <<
1593 clock-names = "bus"; <<
1594 <<
1595 #global-interrupts = <<
1596 #iommu-cells = <1>; <<
1597 interrupts = <<
1598 <GIC_SPI 226 <<
1599 <GIC_SPI 393 <<
1600 <GIC_SPI 394 <<
1601 <GIC_SPI 395 <<
1602 <GIC_SPI 396 <<
1603 <GIC_SPI 397 <<
1604 <GIC_SPI 398 <<
1605 <GIC_SPI 399 <<
1606 <GIC_SPI 400 <<
1607 <GIC_SPI 401 <<
1608 <GIC_SPI 402 <<
1609 <GIC_SPI 403 <<
1610 <GIC_SPI 137 <<
1611 <<
1612 power-domains = <&gcc <<
1613 status = "disabled"; <<
1614 }; <<
1615 <<
1616 remoteproc_slpi: remoteproc@5 <<
1617 compatible = "qcom,ms <<
1618 reg = <0x05800000 0x4 <<
1619 <<
1620 interrupts-extended = <<
1621 <<
1622 <<
1623 <<
1624 <<
1625 interrupt-names = "wd <<
1626 "ha <<
1627 <<
1628 px-supply = <&vreg_lv <<
1629 <<
1630 clocks = <&rpmcc RPM_ <<
1631 clock-names = "xo"; <<
1632 <<
1633 memory-region = <&slp <<
1634 <<
1635 qcom,smem-states = <& <<
1636 qcom,smem-state-names <<
1637 <<
1638 power-domains = <&rpm <<
1639 power-domain-names = <<
1640 <<
1641 status = "disabled"; <<
1642 <<
1643 glink-edge { <<
1644 interrupts = <<
1645 label = "dsps <<
1646 qcom,remote-p <<
1647 mboxes = <&ap <<
1648 }; <<
1649 }; 1003 };
1650 1004
1651 stm: stm@6002000 { 1005 stm: stm@6002000 {
1652 compatible = "arm,cor 1006 compatible = "arm,coresight-stm", "arm,primecell";
1653 reg = <0x06002000 0x1 1007 reg = <0x06002000 0x1000>,
1654 <0x16280000 0x1 1008 <0x16280000 0x180000>;
1655 reg-names = "stm-base !! 1009 reg-names = "stm-base", "stm-data-base";
1656 status = "disabled"; 1010 status = "disabled";
1657 1011
1658 clocks = <&rpmcc RPM_ 1012 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1659 clock-names = "apb_pc 1013 clock-names = "apb_pclk", "atclk";
1660 1014
1661 out-ports { 1015 out-ports {
1662 port { 1016 port {
1663 stm_o 1017 stm_out: endpoint {
1664 1018 remote-endpoint = <&funnel0_in7>;
1665 }; 1019 };
1666 }; 1020 };
1667 }; 1021 };
1668 }; 1022 };
1669 1023
1670 funnel1: funnel@6041000 { 1024 funnel1: funnel@6041000 {
1671 compatible = "arm,cor 1025 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1672 reg = <0x06041000 0x1 1026 reg = <0x06041000 0x1000>;
1673 status = "disabled"; 1027 status = "disabled";
1674 1028
1675 clocks = <&rpmcc RPM_ 1029 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1676 clock-names = "apb_pc 1030 clock-names = "apb_pclk", "atclk";
1677 1031
1678 out-ports { 1032 out-ports {
1679 port { 1033 port {
1680 funne 1034 funnel0_out: endpoint {
1681 1035 remote-endpoint =
1682 1036 <&merge_funnel_in0>;
1683 }; 1037 };
1684 }; 1038 };
1685 }; 1039 };
1686 1040
1687 in-ports { 1041 in-ports {
1688 #address-cell 1042 #address-cells = <1>;
1689 #size-cells = 1043 #size-cells = <0>;
1690 1044
1691 port@7 { 1045 port@7 {
1692 reg = 1046 reg = <7>;
1693 funne 1047 funnel0_in7: endpoint {
1694 1048 remote-endpoint = <&stm_out>;
1695 }; 1049 };
1696 }; 1050 };
1697 }; 1051 };
1698 }; 1052 };
1699 1053
1700 funnel2: funnel@6042000 { 1054 funnel2: funnel@6042000 {
1701 compatible = "arm,cor 1055 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1702 reg = <0x06042000 0x1 1056 reg = <0x06042000 0x1000>;
1703 status = "disabled"; 1057 status = "disabled";
1704 1058
1705 clocks = <&rpmcc RPM_ 1059 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1706 clock-names = "apb_pc 1060 clock-names = "apb_pclk", "atclk";
1707 1061
1708 out-ports { 1062 out-ports {
1709 port { 1063 port {
1710 funne 1064 funnel1_out: endpoint {
1711 1065 remote-endpoint =
1712 1066 <&merge_funnel_in1>;
1713 }; 1067 };
1714 }; 1068 };
1715 }; 1069 };
1716 1070
1717 in-ports { 1071 in-ports {
1718 #address-cell 1072 #address-cells = <1>;
1719 #size-cells = 1073 #size-cells = <0>;
1720 1074
1721 port@6 { 1075 port@6 {
1722 reg = 1076 reg = <6>;
1723 funne 1077 funnel1_in6: endpoint {
1724 1078 remote-endpoint =
1725 1079 <&apss_merge_funnel_out>;
1726 }; 1080 };
1727 }; 1081 };
1728 }; 1082 };
1729 }; 1083 };
1730 1084
1731 funnel3: funnel@6045000 { 1085 funnel3: funnel@6045000 {
1732 compatible = "arm,cor 1086 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1733 reg = <0x06045000 0x1 1087 reg = <0x06045000 0x1000>;
1734 status = "disabled"; 1088 status = "disabled";
1735 1089
1736 clocks = <&rpmcc RPM_ 1090 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1737 clock-names = "apb_pc 1091 clock-names = "apb_pclk", "atclk";
1738 1092
1739 out-ports { 1093 out-ports {
1740 port { 1094 port {
1741 merge 1095 merge_funnel_out: endpoint {
1742 1096 remote-endpoint =
1743 1097 <&etf_in>;
1744 }; 1098 };
1745 }; 1099 };
1746 }; 1100 };
1747 1101
1748 in-ports { 1102 in-ports {
1749 #address-cell 1103 #address-cells = <1>;
1750 #size-cells = 1104 #size-cells = <0>;
1751 1105
1752 port@0 { 1106 port@0 {
1753 reg = 1107 reg = <0>;
1754 merge 1108 merge_funnel_in0: endpoint {
1755 1109 remote-endpoint =
1756 1110 <&funnel0_out>;
1757 }; 1111 };
1758 }; 1112 };
1759 1113
1760 port@1 { 1114 port@1 {
1761 reg = 1115 reg = <1>;
1762 merge 1116 merge_funnel_in1: endpoint {
1763 1117 remote-endpoint =
1764 1118 <&funnel1_out>;
1765 }; 1119 };
1766 }; 1120 };
1767 }; 1121 };
1768 }; 1122 };
1769 1123
1770 replicator1: replicator@60460 1124 replicator1: replicator@6046000 {
1771 compatible = "arm,cor 1125 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
1772 reg = <0x06046000 0x1 1126 reg = <0x06046000 0x1000>;
1773 status = "disabled"; 1127 status = "disabled";
1774 1128
1775 clocks = <&rpmcc RPM_ 1129 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1776 clock-names = "apb_pc 1130 clock-names = "apb_pclk", "atclk";
1777 1131
1778 out-ports { 1132 out-ports {
1779 port { 1133 port {
1780 repli 1134 replicator_out: endpoint {
1781 1135 remote-endpoint = <&etr_in>;
1782 }; 1136 };
1783 }; 1137 };
1784 }; 1138 };
1785 1139
1786 in-ports { 1140 in-ports {
1787 port { 1141 port {
1788 repli 1142 replicator_in: endpoint {
1789 1143 remote-endpoint = <&etf_out>;
1790 }; 1144 };
1791 }; 1145 };
1792 }; 1146 };
1793 }; 1147 };
1794 1148
1795 etf: etf@6047000 { 1149 etf: etf@6047000 {
1796 compatible = "arm,cor 1150 compatible = "arm,coresight-tmc", "arm,primecell";
1797 reg = <0x06047000 0x1 1151 reg = <0x06047000 0x1000>;
1798 status = "disabled"; 1152 status = "disabled";
1799 1153
1800 clocks = <&rpmcc RPM_ 1154 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1801 clock-names = "apb_pc 1155 clock-names = "apb_pclk", "atclk";
1802 1156
1803 out-ports { 1157 out-ports {
1804 port { 1158 port {
1805 etf_o 1159 etf_out: endpoint {
1806 1160 remote-endpoint =
1807 1161 <&replicator_in>;
1808 }; 1162 };
1809 }; 1163 };
1810 }; 1164 };
1811 1165
1812 in-ports { 1166 in-ports {
1813 port { 1167 port {
1814 etf_i 1168 etf_in: endpoint {
1815 1169 remote-endpoint =
1816 1170 <&merge_funnel_out>;
1817 }; 1171 };
1818 }; 1172 };
1819 }; 1173 };
1820 }; 1174 };
1821 1175
1822 etr: etr@6048000 { 1176 etr: etr@6048000 {
1823 compatible = "arm,cor 1177 compatible = "arm,coresight-tmc", "arm,primecell";
1824 reg = <0x06048000 0x1 1178 reg = <0x06048000 0x1000>;
1825 status = "disabled"; 1179 status = "disabled";
1826 1180
1827 clocks = <&rpmcc RPM_ 1181 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1828 clock-names = "apb_pc 1182 clock-names = "apb_pclk", "atclk";
1829 arm,scatter-gather; 1183 arm,scatter-gather;
1830 1184
1831 in-ports { 1185 in-ports {
1832 port { 1186 port {
1833 etr_i 1187 etr_in: endpoint {
1834 1188 remote-endpoint =
1835 1189 <&replicator_out>;
1836 }; 1190 };
1837 }; 1191 };
1838 }; 1192 };
1839 }; 1193 };
1840 1194
1841 etm1: etm@7840000 { 1195 etm1: etm@7840000 {
1842 compatible = "arm,cor 1196 compatible = "arm,coresight-etm4x", "arm,primecell";
1843 reg = <0x07840000 0x1 1197 reg = <0x07840000 0x1000>;
1844 status = "disabled"; 1198 status = "disabled";
1845 1199
1846 clocks = <&rpmcc RPM_ 1200 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1847 clock-names = "apb_pc 1201 clock-names = "apb_pclk", "atclk";
1848 1202
1849 cpu = <&CPU0>; 1203 cpu = <&CPU0>;
1850 1204
1851 out-ports { 1205 out-ports {
1852 port { 1206 port {
1853 etm0_ 1207 etm0_out: endpoint {
1854 1208 remote-endpoint =
1855 1209 <&apss_funnel_in0>;
1856 }; 1210 };
1857 }; 1211 };
1858 }; 1212 };
1859 }; 1213 };
1860 1214
1861 etm2: etm@7940000 { 1215 etm2: etm@7940000 {
1862 compatible = "arm,cor 1216 compatible = "arm,coresight-etm4x", "arm,primecell";
1863 reg = <0x07940000 0x1 1217 reg = <0x07940000 0x1000>;
1864 status = "disabled"; 1218 status = "disabled";
1865 1219
1866 clocks = <&rpmcc RPM_ 1220 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1867 clock-names = "apb_pc 1221 clock-names = "apb_pclk", "atclk";
1868 1222
1869 cpu = <&CPU1>; 1223 cpu = <&CPU1>;
1870 1224
1871 out-ports { 1225 out-ports {
1872 port { 1226 port {
1873 etm1_ 1227 etm1_out: endpoint {
1874 1228 remote-endpoint =
1875 1229 <&apss_funnel_in1>;
1876 }; 1230 };
1877 }; 1231 };
1878 }; 1232 };
1879 }; 1233 };
1880 1234
1881 etm3: etm@7a40000 { 1235 etm3: etm@7a40000 {
1882 compatible = "arm,cor 1236 compatible = "arm,coresight-etm4x", "arm,primecell";
1883 reg = <0x07a40000 0x1 1237 reg = <0x07a40000 0x1000>;
1884 status = "disabled"; 1238 status = "disabled";
1885 1239
1886 clocks = <&rpmcc RPM_ 1240 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1887 clock-names = "apb_pc 1241 clock-names = "apb_pclk", "atclk";
1888 1242
1889 cpu = <&CPU2>; 1243 cpu = <&CPU2>;
1890 1244
1891 out-ports { 1245 out-ports {
1892 port { 1246 port {
1893 etm2_ 1247 etm2_out: endpoint {
1894 1248 remote-endpoint =
1895 1249 <&apss_funnel_in2>;
1896 }; 1250 };
1897 }; 1251 };
1898 }; 1252 };
1899 }; 1253 };
1900 1254
1901 etm4: etm@7b40000 { 1255 etm4: etm@7b40000 {
1902 compatible = "arm,cor 1256 compatible = "arm,coresight-etm4x", "arm,primecell";
1903 reg = <0x07b40000 0x1 1257 reg = <0x07b40000 0x1000>;
1904 status = "disabled"; 1258 status = "disabled";
1905 1259
1906 clocks = <&rpmcc RPM_ 1260 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1907 clock-names = "apb_pc 1261 clock-names = "apb_pclk", "atclk";
1908 1262
1909 cpu = <&CPU3>; 1263 cpu = <&CPU3>;
1910 1264
1911 out-ports { 1265 out-ports {
1912 port { 1266 port {
1913 etm3_ 1267 etm3_out: endpoint {
1914 1268 remote-endpoint =
1915 1269 <&apss_funnel_in3>;
1916 }; 1270 };
1917 }; 1271 };
1918 }; 1272 };
1919 }; 1273 };
1920 1274
1921 funnel4: funnel@7b60000 { /* 1275 funnel4: funnel@7b60000 { /* APSS Funnel */
1922 compatible = "arm,cor 1276 compatible = "arm,coresight-etm4x", "arm,primecell";
1923 reg = <0x07b60000 0x1 1277 reg = <0x07b60000 0x1000>;
1924 status = "disabled"; 1278 status = "disabled";
1925 1279
1926 clocks = <&rpmcc RPM_ 1280 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1927 clock-names = "apb_pc 1281 clock-names = "apb_pclk", "atclk";
1928 1282
1929 out-ports { 1283 out-ports {
1930 port { 1284 port {
1931 apss_ 1285 apss_funnel_out: endpoint {
1932 1286 remote-endpoint =
1933 1287 <&apss_merge_funnel_in>;
1934 }; 1288 };
1935 }; 1289 };
1936 }; 1290 };
1937 1291
1938 in-ports { 1292 in-ports {
1939 #address-cell 1293 #address-cells = <1>;
1940 #size-cells = 1294 #size-cells = <0>;
1941 1295
1942 port@0 { 1296 port@0 {
1943 reg = 1297 reg = <0>;
1944 apss_ 1298 apss_funnel_in0: endpoint {
1945 1299 remote-endpoint =
1946 1300 <&etm0_out>;
1947 }; 1301 };
1948 }; 1302 };
1949 1303
1950 port@1 { 1304 port@1 {
1951 reg = 1305 reg = <1>;
1952 apss_ 1306 apss_funnel_in1: endpoint {
1953 1307 remote-endpoint =
1954 1308 <&etm1_out>;
1955 }; 1309 };
1956 }; 1310 };
1957 1311
1958 port@2 { 1312 port@2 {
1959 reg = 1313 reg = <2>;
1960 apss_ 1314 apss_funnel_in2: endpoint {
1961 1315 remote-endpoint =
1962 1316 <&etm2_out>;
1963 }; 1317 };
1964 }; 1318 };
1965 1319
1966 port@3 { 1320 port@3 {
1967 reg = 1321 reg = <3>;
1968 apss_ 1322 apss_funnel_in3: endpoint {
1969 1323 remote-endpoint =
1970 1324 <&etm3_out>;
1971 }; 1325 };
1972 }; 1326 };
1973 1327
1974 port@4 { 1328 port@4 {
1975 reg = 1329 reg = <4>;
1976 apss_ 1330 apss_funnel_in4: endpoint {
1977 1331 remote-endpoint =
1978 1332 <&etm4_out>;
1979 }; 1333 };
1980 }; 1334 };
1981 1335
1982 port@5 { 1336 port@5 {
1983 reg = 1337 reg = <5>;
1984 apss_ 1338 apss_funnel_in5: endpoint {
1985 1339 remote-endpoint =
1986 1340 <&etm5_out>;
1987 }; 1341 };
1988 }; 1342 };
1989 1343
1990 port@6 { 1344 port@6 {
1991 reg = 1345 reg = <6>;
1992 apss_ 1346 apss_funnel_in6: endpoint {
1993 1347 remote-endpoint =
1994 1348 <&etm6_out>;
1995 }; 1349 };
1996 }; 1350 };
1997 1351
1998 port@7 { 1352 port@7 {
1999 reg = 1353 reg = <7>;
2000 apss_ 1354 apss_funnel_in7: endpoint {
2001 1355 remote-endpoint =
2002 1356 <&etm7_out>;
2003 }; 1357 };
2004 }; 1358 };
2005 }; 1359 };
2006 }; 1360 };
2007 1361
2008 funnel5: funnel@7b70000 { 1362 funnel5: funnel@7b70000 {
2009 compatible = "arm,cor 1363 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2010 reg = <0x07b70000 0x1 1364 reg = <0x07b70000 0x1000>;
2011 status = "disabled"; 1365 status = "disabled";
2012 1366
2013 clocks = <&rpmcc RPM_ 1367 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2014 clock-names = "apb_pc 1368 clock-names = "apb_pclk", "atclk";
2015 1369
2016 out-ports { 1370 out-ports {
2017 port { 1371 port {
2018 apss_ 1372 apss_merge_funnel_out: endpoint {
2019 1373 remote-endpoint =
2020 1374 <&funnel1_in6>;
2021 }; 1375 };
2022 }; 1376 };
2023 }; 1377 };
2024 1378
2025 in-ports { 1379 in-ports {
2026 port { 1380 port {
2027 apss_ 1381 apss_merge_funnel_in: endpoint {
2028 1382 remote-endpoint =
2029 1383 <&apss_funnel_out>;
2030 }; 1384 };
2031 }; 1385 };
2032 }; 1386 };
2033 }; 1387 };
2034 1388
2035 etm5: etm@7c40000 { 1389 etm5: etm@7c40000 {
2036 compatible = "arm,cor 1390 compatible = "arm,coresight-etm4x", "arm,primecell";
2037 reg = <0x07c40000 0x1 1391 reg = <0x07c40000 0x1000>;
2038 status = "disabled"; 1392 status = "disabled";
2039 1393
2040 clocks = <&rpmcc RPM_ 1394 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2041 clock-names = "apb_pc 1395 clock-names = "apb_pclk", "atclk";
2042 1396
2043 cpu = <&CPU4>; 1397 cpu = <&CPU4>;
2044 1398
2045 out-ports { 1399 out-ports {
2046 port { !! 1400 port{
2047 etm4_ 1401 etm4_out: endpoint {
2048 1402 remote-endpoint = <&apss_funnel_in4>;
2049 }; 1403 };
2050 }; 1404 };
2051 }; 1405 };
2052 }; 1406 };
2053 1407
2054 etm6: etm@7d40000 { 1408 etm6: etm@7d40000 {
2055 compatible = "arm,cor 1409 compatible = "arm,coresight-etm4x", "arm,primecell";
2056 reg = <0x07d40000 0x1 1410 reg = <0x07d40000 0x1000>;
2057 status = "disabled"; 1411 status = "disabled";
2058 1412
2059 clocks = <&rpmcc RPM_ 1413 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2060 clock-names = "apb_pc 1414 clock-names = "apb_pclk", "atclk";
2061 1415
2062 cpu = <&CPU5>; 1416 cpu = <&CPU5>;
2063 1417
2064 out-ports { 1418 out-ports {
2065 port { !! 1419 port{
2066 etm5_ 1420 etm5_out: endpoint {
2067 1421 remote-endpoint = <&apss_funnel_in5>;
2068 }; 1422 };
2069 }; 1423 };
2070 }; 1424 };
2071 }; 1425 };
2072 1426
2073 etm7: etm@7e40000 { 1427 etm7: etm@7e40000 {
2074 compatible = "arm,cor 1428 compatible = "arm,coresight-etm4x", "arm,primecell";
2075 reg = <0x07e40000 0x1 1429 reg = <0x07e40000 0x1000>;
2076 status = "disabled"; 1430 status = "disabled";
2077 1431
2078 clocks = <&rpmcc RPM_ 1432 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2079 clock-names = "apb_pc 1433 clock-names = "apb_pclk", "atclk";
2080 1434
2081 cpu = <&CPU6>; 1435 cpu = <&CPU6>;
2082 1436
2083 out-ports { 1437 out-ports {
2084 port { !! 1438 port{
2085 etm6_ 1439 etm6_out: endpoint {
2086 1440 remote-endpoint = <&apss_funnel_in6>;
2087 }; 1441 };
2088 }; 1442 };
2089 }; 1443 };
2090 }; 1444 };
2091 1445
2092 etm8: etm@7f40000 { 1446 etm8: etm@7f40000 {
2093 compatible = "arm,cor 1447 compatible = "arm,coresight-etm4x", "arm,primecell";
2094 reg = <0x07f40000 0x1 1448 reg = <0x07f40000 0x1000>;
2095 status = "disabled"; 1449 status = "disabled";
2096 1450
2097 clocks = <&rpmcc RPM_ 1451 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2098 clock-names = "apb_pc 1452 clock-names = "apb_pclk", "atclk";
2099 1453
2100 cpu = <&CPU7>; 1454 cpu = <&CPU7>;
2101 1455
2102 out-ports { 1456 out-ports {
2103 port { !! 1457 port{
2104 etm7_ 1458 etm7_out: endpoint {
2105 1459 remote-endpoint = <&apss_funnel_in7>;
2106 }; 1460 };
2107 }; 1461 };
2108 }; 1462 };
2109 }; 1463 };
2110 1464
2111 sram@290000 { <<
2112 compatible = "qcom,rp <<
2113 reg = <0x00290000 0x1 <<
2114 }; <<
2115 <<
2116 spmi_bus: spmi@800f000 { 1465 spmi_bus: spmi@800f000 {
2117 compatible = "qcom,sp 1466 compatible = "qcom,spmi-pmic-arb";
2118 reg = <0x0800f000 0x1 !! 1467 reg = <0x0800f000 0x1000>,
2119 <0x08400000 0x1 !! 1468 <0x08400000 0x1000000>,
2120 <0x09400000 0x1 !! 1469 <0x09400000 0x1000000>,
2121 <0x0a400000 0x2 !! 1470 <0x0a400000 0x220000>,
2122 <0x0800a000 0x3 !! 1471 <0x0800a000 0x3000>;
2123 reg-names = "core", " 1472 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
2124 interrupt-names = "pe 1473 interrupt-names = "periph_irq";
2125 interrupts = <GIC_SPI 1474 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
2126 qcom,ee = <0>; 1475 qcom,ee = <0>;
2127 qcom,channel = <0>; 1476 qcom,channel = <0>;
2128 #address-cells = <2>; 1477 #address-cells = <2>;
2129 #size-cells = <0>; 1478 #size-cells = <0>;
2130 interrupt-controller; 1479 interrupt-controller;
2131 #interrupt-cells = <4 1480 #interrupt-cells = <4>;
>> 1481 cell-index = <0>;
2132 }; 1482 };
2133 1483
2134 usb3: usb@a8f8800 { 1484 usb3: usb@a8f8800 {
2135 compatible = "qcom,ms 1485 compatible = "qcom,msm8998-dwc3", "qcom,dwc3";
2136 reg = <0x0a8f8800 0x4 1486 reg = <0x0a8f8800 0x400>;
2137 status = "disabled"; 1487 status = "disabled";
2138 #address-cells = <1>; 1488 #address-cells = <1>;
2139 #size-cells = <1>; 1489 #size-cells = <1>;
2140 ranges; 1490 ranges;
2141 1491
2142 clocks = <&gcc GCC_CF 1492 clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>,
2143 <&gcc GCC_US 1493 <&gcc GCC_USB30_MASTER_CLK>,
2144 <&gcc GCC_AG 1494 <&gcc GCC_AGGRE1_USB3_AXI_CLK>,
2145 <&gcc GCC_US !! 1495 <&gcc GCC_USB30_MOCK_UTMI_CLK>,
2146 <&gcc GCC_US !! 1496 <&gcc GCC_USB30_SLEEP_CLK>;
2147 clock-names = "cfg_no !! 1497 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
2148 "core", !! 1498 "sleep";
2149 "iface" <<
2150 "sleep" <<
2151 "mock_u <<
2152 1499
2153 assigned-clocks = <&g 1500 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
2154 <&g 1501 <&gcc GCC_USB30_MASTER_CLK>;
2155 assigned-clock-rates 1502 assigned-clock-rates = <19200000>, <120000000>;
2156 1503
2157 interrupts = <GIC_SPI !! 1504 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
2158 <GIC_SPI <<
2159 <GIC_SPI 1505 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
2160 interrupt-names = "pw !! 1506 interrupt-names = "hs_phy_irq", "ss_phy_irq";
2161 "qu <<
2162 "ss <<
2163 1507
2164 power-domains = <&gcc 1508 power-domains = <&gcc USB_30_GDSC>;
2165 1509
2166 resets = <&gcc GCC_US 1510 resets = <&gcc GCC_USB_30_BCR>;
2167 1511
2168 usb3_dwc3: usb@a80000 !! 1512 usb3_dwc3: dwc3@a800000 {
2169 compatible = 1513 compatible = "snps,dwc3";
2170 reg = <0x0a80 1514 reg = <0x0a800000 0xcd00>;
2171 interrupts = 1515 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
2172 snps,dis_u2_s 1516 snps,dis_u2_susphy_quirk;
2173 snps,dis_enbl 1517 snps,dis_enblslpm_quirk;
2174 snps,parkmode !! 1518 phys = <&qusb2phy>, <&usb1_ssphy>;
2175 phys = <&qusb <<
2176 phy-names = " 1519 phy-names = "usb2-phy", "usb3-phy";
2177 snps,has-lpm- 1520 snps,has-lpm-erratum;
2178 snps,hird-thr 1521 snps,hird-threshold = /bits/ 8 <0x10>;
2179 }; 1522 };
2180 }; 1523 };
2181 1524
2182 usb3phy: phy@c010000 { 1525 usb3phy: phy@c010000 {
2183 compatible = "qcom,ms 1526 compatible = "qcom,msm8998-qmp-usb3-phy";
2184 reg = <0x0c010000 0x1 !! 1527 reg = <0x0c010000 0x18c>;
>> 1528 status = "disabled";
>> 1529 #clock-cells = <1>;
>> 1530 #address-cells = <1>;
>> 1531 #size-cells = <1>;
>> 1532 ranges;
2185 1533
2186 clocks = <&gcc GCC_US 1534 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
2187 <&gcc GCC_US <<
2188 <&gcc GCC_US 1535 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2189 <&gcc GCC_US !! 1536 <&gcc GCC_USB3_CLKREF_CLK>;
2190 clock-names = "aux", !! 1537 clock-names = "aux", "cfg_ahb", "ref";
2191 "ref", <<
2192 "cfg_ah <<
2193 "pipe"; <<
2194 clock-output-names = <<
2195 #clock-cells = <0>; <<
2196 #phy-cells = <0>; <<
2197 1538
2198 resets = <&gcc GCC_US 1539 resets = <&gcc GCC_USB3_PHY_BCR>,
2199 <&gcc GCC_US 1540 <&gcc GCC_USB3PHY_PHY_BCR>;
2200 reset-names = "phy", !! 1541 reset-names = "phy", "common";
2201 "phy_ph <<
2202 <<
2203 qcom,tcsr-reg = <&tcs <<
2204 1542
2205 status = "disabled"; !! 1543 usb1_ssphy: lane@c010200 {
>> 1544 reg = <0xc010200 0x128>,
>> 1545 <0xc010400 0x200>,
>> 1546 <0xc010c00 0x20c>,
>> 1547 <0xc010600 0x128>,
>> 1548 <0xc010800 0x200>;
>> 1549 #phy-cells = <0>;
>> 1550 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
>> 1551 clock-names = "pipe0";
>> 1552 clock-output-names = "usb3_phy_pipe_clk_src";
>> 1553 };
2206 }; 1554 };
2207 1555
2208 qusb2phy: phy@c012000 { 1556 qusb2phy: phy@c012000 {
2209 compatible = "qcom,ms 1557 compatible = "qcom,msm8998-qusb2-phy";
2210 reg = <0x0c012000 0x2 1558 reg = <0x0c012000 0x2a8>;
2211 status = "disabled"; 1559 status = "disabled";
2212 #phy-cells = <0>; 1560 #phy-cells = <0>;
2213 1561
2214 clocks = <&gcc GCC_US 1562 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2215 <&gcc GCC_RX 1563 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
2216 clock-names = "cfg_ah 1564 clock-names = "cfg_ahb", "ref";
2217 1565
2218 resets = <&gcc GCC_QU 1566 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2219 1567
2220 nvmem-cells = <&qusb2 1568 nvmem-cells = <&qusb2_hstx_trim>;
2221 }; 1569 };
2222 1570
2223 sdhc2: mmc@c0a4900 { !! 1571 sdhc2: sdhci@c0a4900 {
2224 compatible = "qcom,ms !! 1572 compatible = "qcom,sdhci-msm-v4";
2225 reg = <0x0c0a4900 0x3 1573 reg = <0x0c0a4900 0x314>, <0x0c0a4000 0x800>;
2226 reg-names = "hc", "co !! 1574 reg-names = "hc_mem", "core_mem";
2227 1575
2228 interrupts = <GIC_SPI 1576 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
2229 <GIC_SPI 1577 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
2230 interrupt-names = "hc 1578 interrupt-names = "hc_irq", "pwr_irq";
2231 1579
2232 clock-names = "iface" 1580 clock-names = "iface", "core", "xo";
2233 clocks = <&gcc GCC_SD 1581 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2234 <&gcc GCC_SD 1582 <&gcc GCC_SDCC2_APPS_CLK>,
2235 <&rpmcc RPM_ !! 1583 <&xo>;
2236 bus-width = <4>; 1584 bus-width = <4>;
2237 status = "disabled"; 1585 status = "disabled";
2238 }; 1586 };
2239 1587
2240 blsp1_dma: dma-controller@c14 <<
2241 compatible = "qcom,ba <<
2242 reg = <0x0c144000 0x2 <<
2243 interrupts = <GIC_SPI <<
2244 clocks = <&gcc GCC_BL <<
2245 clock-names = "bam_cl <<
2246 #dma-cells = <1>; <<
2247 qcom,ee = <0>; <<
2248 qcom,controlled-remot <<
2249 num-channels = <18>; <<
2250 qcom,num-ees = <4>; <<
2251 }; <<
2252 <<
2253 blsp1_uart3: serial@c171000 { <<
2254 compatible = "qcom,ms <<
2255 reg = <0x0c171000 0x1 <<
2256 interrupts = <GIC_SPI <<
2257 clocks = <&gcc GCC_BL <<
2258 <&gcc GCC_BL <<
2259 clock-names = "core", <<
2260 dmas = <&blsp1_dma 4> <<
2261 dma-names = "tx", "rx <<
2262 pinctrl-names = "defa <<
2263 pinctrl-0 = <&blsp1_u <<
2264 status = "disabled"; <<
2265 }; <<
2266 <<
2267 blsp1_i2c1: i2c@c175000 { 1588 blsp1_i2c1: i2c@c175000 {
2268 compatible = "qcom,i2 1589 compatible = "qcom,i2c-qup-v2.2.1";
2269 reg = <0x0c175000 0x6 1590 reg = <0x0c175000 0x600>;
2270 interrupts = <GIC_SPI 1591 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
2271 1592
2272 clocks = <&gcc GCC_BL 1593 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
2273 <&gcc GCC_BL 1594 <&gcc GCC_BLSP1_AHB_CLK>;
2274 clock-names = "core", 1595 clock-names = "core", "iface";
2275 dmas = <&blsp1_dma 6> <<
2276 dma-names = "tx", "rx <<
2277 pinctrl-names = "defa <<
2278 pinctrl-0 = <&blsp1_i <<
2279 pinctrl-1 = <&blsp1_i <<
2280 clock-frequency = <40 1596 clock-frequency = <400000>;
2281 1597
2282 status = "disabled"; 1598 status = "disabled";
2283 #address-cells = <1>; 1599 #address-cells = <1>;
2284 #size-cells = <0>; 1600 #size-cells = <0>;
2285 }; 1601 };
2286 1602
2287 blsp1_i2c2: i2c@c176000 { 1603 blsp1_i2c2: i2c@c176000 {
2288 compatible = "qcom,i2 1604 compatible = "qcom,i2c-qup-v2.2.1";
2289 reg = <0x0c176000 0x6 1605 reg = <0x0c176000 0x600>;
2290 interrupts = <GIC_SPI 1606 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
2291 1607
2292 clocks = <&gcc GCC_BL 1608 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
2293 <&gcc GCC_BL 1609 <&gcc GCC_BLSP1_AHB_CLK>;
2294 clock-names = "core", 1610 clock-names = "core", "iface";
2295 dmas = <&blsp1_dma 8> <<
2296 dma-names = "tx", "rx <<
2297 pinctrl-names = "defa <<
2298 pinctrl-0 = <&blsp1_i <<
2299 pinctrl-1 = <&blsp1_i <<
2300 clock-frequency = <40 1611 clock-frequency = <400000>;
2301 1612
2302 status = "disabled"; 1613 status = "disabled";
2303 #address-cells = <1>; 1614 #address-cells = <1>;
2304 #size-cells = <0>; 1615 #size-cells = <0>;
2305 }; 1616 };
2306 1617
2307 blsp1_i2c3: i2c@c177000 { 1618 blsp1_i2c3: i2c@c177000 {
2308 compatible = "qcom,i2 1619 compatible = "qcom,i2c-qup-v2.2.1";
2309 reg = <0x0c177000 0x6 1620 reg = <0x0c177000 0x600>;
2310 interrupts = <GIC_SPI 1621 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
2311 1622
2312 clocks = <&gcc GCC_BL 1623 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
2313 <&gcc GCC_BL 1624 <&gcc GCC_BLSP1_AHB_CLK>;
2314 clock-names = "core", 1625 clock-names = "core", "iface";
2315 dmas = <&blsp1_dma 10 <<
2316 dma-names = "tx", "rx <<
2317 pinctrl-names = "defa <<
2318 pinctrl-0 = <&blsp1_i <<
2319 pinctrl-1 = <&blsp1_i <<
2320 clock-frequency = <40 1626 clock-frequency = <400000>;
2321 1627
2322 status = "disabled"; 1628 status = "disabled";
2323 #address-cells = <1>; 1629 #address-cells = <1>;
2324 #size-cells = <0>; 1630 #size-cells = <0>;
2325 }; 1631 };
2326 1632
2327 blsp1_i2c4: i2c@c178000 { 1633 blsp1_i2c4: i2c@c178000 {
2328 compatible = "qcom,i2 1634 compatible = "qcom,i2c-qup-v2.2.1";
2329 reg = <0x0c178000 0x6 1635 reg = <0x0c178000 0x600>;
2330 interrupts = <GIC_SPI 1636 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
2331 1637
2332 clocks = <&gcc GCC_BL 1638 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
2333 <&gcc GCC_BL 1639 <&gcc GCC_BLSP1_AHB_CLK>;
2334 clock-names = "core", 1640 clock-names = "core", "iface";
2335 dmas = <&blsp1_dma 12 <<
2336 dma-names = "tx", "rx <<
2337 pinctrl-names = "defa <<
2338 pinctrl-0 = <&blsp1_i <<
2339 pinctrl-1 = <&blsp1_i <<
2340 clock-frequency = <40 1641 clock-frequency = <400000>;
2341 1642
2342 status = "disabled"; 1643 status = "disabled";
2343 #address-cells = <1>; 1644 #address-cells = <1>;
2344 #size-cells = <0>; 1645 #size-cells = <0>;
2345 }; 1646 };
2346 1647
2347 blsp1_i2c5: i2c@c179000 { 1648 blsp1_i2c5: i2c@c179000 {
2348 compatible = "qcom,i2 1649 compatible = "qcom,i2c-qup-v2.2.1";
2349 reg = <0x0c179000 0x6 1650 reg = <0x0c179000 0x600>;
2350 interrupts = <GIC_SPI 1651 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
2351 1652
2352 clocks = <&gcc GCC_BL 1653 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
2353 <&gcc GCC_BL 1654 <&gcc GCC_BLSP1_AHB_CLK>;
2354 clock-names = "core", 1655 clock-names = "core", "iface";
2355 dmas = <&blsp1_dma 14 <<
2356 dma-names = "tx", "rx <<
2357 pinctrl-names = "defa <<
2358 pinctrl-0 = <&blsp1_i <<
2359 pinctrl-1 = <&blsp1_i <<
2360 clock-frequency = <40 1656 clock-frequency = <400000>;
2361 1657
2362 status = "disabled"; 1658 status = "disabled";
2363 #address-cells = <1>; 1659 #address-cells = <1>;
2364 #size-cells = <0>; 1660 #size-cells = <0>;
2365 }; 1661 };
2366 1662
2367 blsp1_i2c6: i2c@c17a000 { 1663 blsp1_i2c6: i2c@c17a000 {
2368 compatible = "qcom,i2 1664 compatible = "qcom,i2c-qup-v2.2.1";
2369 reg = <0x0c17a000 0x6 1665 reg = <0x0c17a000 0x600>;
2370 interrupts = <GIC_SPI 1666 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
2371 1667
2372 clocks = <&gcc GCC_BL 1668 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
2373 <&gcc GCC_BL 1669 <&gcc GCC_BLSP1_AHB_CLK>;
2374 clock-names = "core", 1670 clock-names = "core", "iface";
2375 dmas = <&blsp1_dma 16 <<
2376 dma-names = "tx", "rx <<
2377 pinctrl-names = "defa <<
2378 pinctrl-0 = <&blsp1_i <<
2379 pinctrl-1 = <&blsp1_i <<
2380 clock-frequency = <40 1671 clock-frequency = <400000>;
2381 1672
2382 status = "disabled"; 1673 status = "disabled";
2383 #address-cells = <1>; 1674 #address-cells = <1>;
2384 #size-cells = <0>; 1675 #size-cells = <0>;
2385 }; 1676 };
2386 1677
2387 blsp1_spi1: spi@c175000 { <<
2388 compatible = "qcom,sp <<
2389 reg = <0x0c175000 0x6 <<
2390 interrupts = <GIC_SPI <<
2391 <<
2392 clocks = <&gcc GCC_BL <<
2393 <&gcc GCC_BL <<
2394 clock-names = "core", <<
2395 dmas = <&blsp1_dma 6> <<
2396 dma-names = "tx", "rx <<
2397 pinctrl-names = "defa <<
2398 pinctrl-0 = <&blsp1_s <<
2399 <<
2400 status = "disabled"; <<
2401 #address-cells = <1>; <<
2402 #size-cells = <0>; <<
2403 }; <<
2404 <<
2405 blsp1_spi2: spi@c176000 { <<
2406 compatible = "qcom,sp <<
2407 reg = <0x0c176000 0x6 <<
2408 interrupts = <GIC_SPI <<
2409 <<
2410 clocks = <&gcc GCC_BL <<
2411 <&gcc GCC_BL <<
2412 clock-names = "core", <<
2413 dmas = <&blsp1_dma 8> <<
2414 dma-names = "tx", "rx <<
2415 pinctrl-names = "defa <<
2416 pinctrl-0 = <&blsp1_s <<
2417 <<
2418 status = "disabled"; <<
2419 #address-cells = <1>; <<
2420 #size-cells = <0>; <<
2421 }; <<
2422 <<
2423 blsp1_spi3: spi@c177000 { <<
2424 compatible = "qcom,sp <<
2425 reg = <0x0c177000 0x6 <<
2426 interrupts = <GIC_SPI <<
2427 <<
2428 clocks = <&gcc GCC_BL <<
2429 <&gcc GCC_BL <<
2430 clock-names = "core", <<
2431 dmas = <&blsp1_dma 10 <<
2432 dma-names = "tx", "rx <<
2433 pinctrl-names = "defa <<
2434 pinctrl-0 = <&blsp1_s <<
2435 <<
2436 status = "disabled"; <<
2437 #address-cells = <1>; <<
2438 #size-cells = <0>; <<
2439 }; <<
2440 <<
2441 blsp1_spi4: spi@c178000 { <<
2442 compatible = "qcom,sp <<
2443 reg = <0x0c178000 0x6 <<
2444 interrupts = <GIC_SPI <<
2445 <<
2446 clocks = <&gcc GCC_BL <<
2447 <&gcc GCC_BL <<
2448 clock-names = "core", <<
2449 dmas = <&blsp1_dma 12 <<
2450 dma-names = "tx", "rx <<
2451 pinctrl-names = "defa <<
2452 pinctrl-0 = <&blsp1_s <<
2453 <<
2454 status = "disabled"; <<
2455 #address-cells = <1>; <<
2456 #size-cells = <0>; <<
2457 }; <<
2458 <<
2459 blsp1_spi5: spi@c179000 { <<
2460 compatible = "qcom,sp <<
2461 reg = <0x0c179000 0x6 <<
2462 interrupts = <GIC_SPI <<
2463 <<
2464 clocks = <&gcc GCC_BL <<
2465 <&gcc GCC_BL <<
2466 clock-names = "core", <<
2467 dmas = <&blsp1_dma 14 <<
2468 dma-names = "tx", "rx <<
2469 pinctrl-names = "defa <<
2470 pinctrl-0 = <&blsp1_s <<
2471 <<
2472 status = "disabled"; <<
2473 #address-cells = <1>; <<
2474 #size-cells = <0>; <<
2475 }; <<
2476 <<
2477 blsp1_spi6: spi@c17a000 { <<
2478 compatible = "qcom,sp <<
2479 reg = <0x0c17a000 0x6 <<
2480 interrupts = <GIC_SPI <<
2481 <<
2482 clocks = <&gcc GCC_BL <<
2483 <&gcc GCC_BL <<
2484 clock-names = "core", <<
2485 dmas = <&blsp1_dma 16 <<
2486 dma-names = "tx", "rx <<
2487 pinctrl-names = "defa <<
2488 pinctrl-0 = <&blsp1_s <<
2489 <<
2490 status = "disabled"; <<
2491 #address-cells = <1>; <<
2492 #size-cells = <0>; <<
2493 }; <<
2494 <<
2495 blsp2_dma: dma-controller@c18 <<
2496 compatible = "qcom,ba <<
2497 reg = <0x0c184000 0x2 <<
2498 interrupts = <GIC_SPI <<
2499 clocks = <&gcc GCC_BL <<
2500 clock-names = "bam_cl <<
2501 #dma-cells = <1>; <<
2502 qcom,ee = <0>; <<
2503 qcom,controlled-remot <<
2504 num-channels = <18>; <<
2505 qcom,num-ees = <4>; <<
2506 }; <<
2507 <<
2508 blsp2_uart1: serial@c1b0000 { 1678 blsp2_uart1: serial@c1b0000 {
2509 compatible = "qcom,ms 1679 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2510 reg = <0x0c1b0000 0x1 1680 reg = <0x0c1b0000 0x1000>;
2511 interrupts = <GIC_SPI 1681 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
2512 clocks = <&gcc GCC_BL 1682 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
2513 <&gcc GCC_BL 1683 <&gcc GCC_BLSP2_AHB_CLK>;
2514 clock-names = "core", 1684 clock-names = "core", "iface";
2515 status = "disabled"; 1685 status = "disabled";
2516 }; 1686 };
2517 1687
2518 blsp2_i2c1: i2c@c1b5000 { !! 1688 blsp2_i2c0: i2c@c1b5000 {
2519 compatible = "qcom,i2 1689 compatible = "qcom,i2c-qup-v2.2.1";
2520 reg = <0x0c1b5000 0x6 1690 reg = <0x0c1b5000 0x600>;
2521 interrupts = <GIC_SPI 1691 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
2522 1692
2523 clocks = <&gcc GCC_BL 1693 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
2524 <&gcc GCC_BL 1694 <&gcc GCC_BLSP2_AHB_CLK>;
2525 clock-names = "core", 1695 clock-names = "core", "iface";
2526 dmas = <&blsp2_dma 6> <<
2527 dma-names = "tx", "rx <<
2528 pinctrl-names = "defa <<
2529 pinctrl-0 = <&blsp2_i <<
2530 pinctrl-1 = <&blsp2_i <<
2531 clock-frequency = <40 1696 clock-frequency = <400000>;
2532 1697
2533 status = "disabled"; 1698 status = "disabled";
2534 #address-cells = <1>; 1699 #address-cells = <1>;
2535 #size-cells = <0>; 1700 #size-cells = <0>;
2536 }; 1701 };
2537 1702
2538 blsp2_i2c2: i2c@c1b6000 { !! 1703 blsp2_i2c1: i2c@c1b6000 {
2539 compatible = "qcom,i2 1704 compatible = "qcom,i2c-qup-v2.2.1";
2540 reg = <0x0c1b6000 0x6 1705 reg = <0x0c1b6000 0x600>;
2541 interrupts = <GIC_SPI 1706 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
2542 1707
2543 clocks = <&gcc GCC_BL 1708 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
2544 <&gcc GCC_BL 1709 <&gcc GCC_BLSP2_AHB_CLK>;
2545 clock-names = "core", 1710 clock-names = "core", "iface";
2546 dmas = <&blsp2_dma 8> <<
2547 dma-names = "tx", "rx <<
2548 pinctrl-names = "defa <<
2549 pinctrl-0 = <&blsp2_i <<
2550 pinctrl-1 = <&blsp2_i <<
2551 clock-frequency = <40 1711 clock-frequency = <400000>;
2552 1712
2553 status = "disabled"; 1713 status = "disabled";
2554 #address-cells = <1>; 1714 #address-cells = <1>;
2555 #size-cells = <0>; 1715 #size-cells = <0>;
2556 }; 1716 };
2557 1717
2558 blsp2_i2c3: i2c@c1b7000 { !! 1718 blsp2_i2c2: i2c@c1b7000 {
2559 compatible = "qcom,i2 1719 compatible = "qcom,i2c-qup-v2.2.1";
2560 reg = <0x0c1b7000 0x6 1720 reg = <0x0c1b7000 0x600>;
2561 interrupts = <GIC_SPI 1721 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
2562 1722
2563 clocks = <&gcc GCC_BL 1723 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
2564 <&gcc GCC_BL 1724 <&gcc GCC_BLSP2_AHB_CLK>;
2565 clock-names = "core", 1725 clock-names = "core", "iface";
2566 dmas = <&blsp2_dma 10 <<
2567 dma-names = "tx", "rx <<
2568 pinctrl-names = "defa <<
2569 pinctrl-0 = <&blsp2_i <<
2570 pinctrl-1 = <&blsp2_i <<
2571 clock-frequency = <40 1726 clock-frequency = <400000>;
2572 1727
2573 status = "disabled"; 1728 status = "disabled";
2574 #address-cells = <1>; 1729 #address-cells = <1>;
2575 #size-cells = <0>; 1730 #size-cells = <0>;
2576 }; 1731 };
2577 1732
2578 blsp2_i2c4: i2c@c1b8000 { !! 1733 blsp2_i2c3: i2c@c1b8000 {
2579 compatible = "qcom,i2 1734 compatible = "qcom,i2c-qup-v2.2.1";
2580 reg = <0x0c1b8000 0x6 1735 reg = <0x0c1b8000 0x600>;
2581 interrupts = <GIC_SPI 1736 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
2582 1737
2583 clocks = <&gcc GCC_BL 1738 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>,
2584 <&gcc GCC_BL 1739 <&gcc GCC_BLSP2_AHB_CLK>;
2585 clock-names = "core", 1740 clock-names = "core", "iface";
2586 dmas = <&blsp2_dma 12 <<
2587 dma-names = "tx", "rx <<
2588 pinctrl-names = "defa <<
2589 pinctrl-0 = <&blsp2_i <<
2590 pinctrl-1 = <&blsp2_i <<
2591 clock-frequency = <40 1741 clock-frequency = <400000>;
2592 1742
2593 status = "disabled"; 1743 status = "disabled";
2594 #address-cells = <1>; 1744 #address-cells = <1>;
2595 #size-cells = <0>; 1745 #size-cells = <0>;
2596 }; 1746 };
2597 1747
2598 blsp2_i2c5: i2c@c1b9000 { !! 1748 blsp2_i2c4: i2c@c1b9000 {
2599 compatible = "qcom,i2 1749 compatible = "qcom,i2c-qup-v2.2.1";
2600 reg = <0x0c1b9000 0x6 1750 reg = <0x0c1b9000 0x600>;
2601 interrupts = <GIC_SPI 1751 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
2602 1752
2603 clocks = <&gcc GCC_BL 1753 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,
2604 <&gcc GCC_BL 1754 <&gcc GCC_BLSP2_AHB_CLK>;
2605 clock-names = "core", 1755 clock-names = "core", "iface";
2606 dmas = <&blsp2_dma 14 <<
2607 dma-names = "tx", "rx <<
2608 pinctrl-names = "defa <<
2609 pinctrl-0 = <&blsp2_i <<
2610 pinctrl-1 = <&blsp2_i <<
2611 clock-frequency = <40 1756 clock-frequency = <400000>;
2612 1757
2613 status = "disabled"; 1758 status = "disabled";
2614 #address-cells = <1>; 1759 #address-cells = <1>;
2615 #size-cells = <0>; 1760 #size-cells = <0>;
2616 }; 1761 };
2617 1762
2618 blsp2_i2c6: i2c@c1ba000 { !! 1763 blsp2_i2c5: i2c@c1ba000 {
2619 compatible = "qcom,i2 1764 compatible = "qcom,i2c-qup-v2.2.1";
2620 reg = <0x0c1ba000 0x6 1765 reg = <0x0c1ba000 0x600>;
2621 interrupts = <GIC_SPI 1766 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
2622 1767
2623 clocks = <&gcc GCC_BL 1768 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>,
2624 <&gcc GCC_BL 1769 <&gcc GCC_BLSP2_AHB_CLK>;
2625 clock-names = "core", 1770 clock-names = "core", "iface";
2626 dmas = <&blsp2_dma 16 <<
2627 dma-names = "tx", "rx <<
2628 pinctrl-names = "defa <<
2629 pinctrl-0 = <&blsp2_i <<
2630 pinctrl-1 = <&blsp2_i <<
2631 clock-frequency = <40 1771 clock-frequency = <400000>;
2632 1772
2633 status = "disabled"; 1773 status = "disabled";
2634 #address-cells = <1>; 1774 #address-cells = <1>;
2635 #size-cells = <0>; 1775 #size-cells = <0>;
2636 }; 1776 };
2637 1777
2638 blsp2_spi1: spi@c1b5000 { <<
2639 compatible = "qcom,sp <<
2640 reg = <0x0c1b5000 0x6 <<
2641 interrupts = <GIC_SPI <<
2642 <<
2643 clocks = <&gcc GCC_BL <<
2644 <&gcc GCC_BL <<
2645 clock-names = "core", <<
2646 dmas = <&blsp2_dma 6> <<
2647 dma-names = "tx", "rx <<
2648 pinctrl-names = "defa <<
2649 pinctrl-0 = <&blsp2_s <<
2650 <<
2651 status = "disabled"; <<
2652 #address-cells = <1>; <<
2653 #size-cells = <0>; <<
2654 }; <<
2655 <<
2656 blsp2_spi2: spi@c1b6000 { <<
2657 compatible = "qcom,sp <<
2658 reg = <0x0c1b6000 0x6 <<
2659 interrupts = <GIC_SPI <<
2660 <<
2661 clocks = <&gcc GCC_BL <<
2662 <&gcc GCC_BL <<
2663 clock-names = "core", <<
2664 dmas = <&blsp2_dma 8> <<
2665 dma-names = "tx", "rx <<
2666 pinctrl-names = "defa <<
2667 pinctrl-0 = <&blsp2_s <<
2668 <<
2669 status = "disabled"; <<
2670 #address-cells = <1>; <<
2671 #size-cells = <0>; <<
2672 }; <<
2673 <<
2674 blsp2_spi3: spi@c1b7000 { <<
2675 compatible = "qcom,sp <<
2676 reg = <0x0c1b7000 0x6 <<
2677 interrupts = <GIC_SPI <<
2678 <<
2679 clocks = <&gcc GCC_BL <<
2680 <&gcc GCC_BL <<
2681 clock-names = "core", <<
2682 dmas = <&blsp2_dma 10 <<
2683 dma-names = "tx", "rx <<
2684 pinctrl-names = "defa <<
2685 pinctrl-0 = <&blsp2_s <<
2686 <<
2687 status = "disabled"; <<
2688 #address-cells = <1>; <<
2689 #size-cells = <0>; <<
2690 }; <<
2691 <<
2692 blsp2_spi4: spi@c1b8000 { <<
2693 compatible = "qcom,sp <<
2694 reg = <0x0c1b8000 0x6 <<
2695 interrupts = <GIC_SPI <<
2696 <<
2697 clocks = <&gcc GCC_BL <<
2698 <&gcc GCC_BL <<
2699 clock-names = "core", <<
2700 dmas = <&blsp2_dma 12 <<
2701 dma-names = "tx", "rx <<
2702 pinctrl-names = "defa <<
2703 pinctrl-0 = <&blsp2_s <<
2704 <<
2705 status = "disabled"; <<
2706 #address-cells = <1>; <<
2707 #size-cells = <0>; <<
2708 }; <<
2709 <<
2710 blsp2_spi5: spi@c1b9000 { <<
2711 compatible = "qcom,sp <<
2712 reg = <0x0c1b9000 0x6 <<
2713 interrupts = <GIC_SPI <<
2714 <<
2715 clocks = <&gcc GCC_BL <<
2716 <&gcc GCC_BL <<
2717 clock-names = "core", <<
2718 dmas = <&blsp2_dma 14 <<
2719 dma-names = "tx", "rx <<
2720 pinctrl-names = "defa <<
2721 pinctrl-0 = <&blsp2_s <<
2722 <<
2723 status = "disabled"; <<
2724 #address-cells = <1>; <<
2725 #size-cells = <0>; <<
2726 }; <<
2727 <<
2728 blsp2_spi6: spi@c1ba000 { <<
2729 compatible = "qcom,sp <<
2730 reg = <0x0c1ba000 0x6 <<
2731 interrupts = <GIC_SPI <<
2732 <<
2733 clocks = <&gcc GCC_BL <<
2734 <&gcc GCC_BL <<
2735 clock-names = "core", <<
2736 dmas = <&blsp2_dma 16 <<
2737 dma-names = "tx", "rx <<
2738 pinctrl-names = "defa <<
2739 pinctrl-0 = <&blsp2_s <<
2740 <<
2741 status = "disabled"; <<
2742 #address-cells = <1>; <<
2743 #size-cells = <0>; <<
2744 }; <<
2745 <<
2746 mmcc: clock-controller@c8c000 <<
2747 compatible = "qcom,mm <<
2748 #clock-cells = <1>; <<
2749 #reset-cells = <1>; <<
2750 #power-domain-cells = <<
2751 reg = <0xc8c0000 0x40 <<
2752 <<
2753 clock-names = "xo", <<
2754 "gpll0" <<
2755 "dsi0ds <<
2756 "dsi0by <<
2757 "dsi1ds <<
2758 "dsi1by <<
2759 "hdmipl <<
2760 "dplink <<
2761 "dpvco" <<
2762 "gpll0_ <<
2763 clocks = <&rpmcc RPM_ <<
2764 <&gcc GCC_MM <<
2765 <&mdss_dsi0_ <<
2766 <&mdss_dsi0_ <<
2767 <&mdss_dsi1_ <<
2768 <&mdss_dsi1_ <<
2769 <0>, <<
2770 <0>, <<
2771 <0>, <<
2772 <&gcc GCC_MM <<
2773 }; <<
2774 <<
2775 mdss: display-subsystem@c9000 <<
2776 compatible = "qcom,ms <<
2777 reg = <0x0c900000 0x1 <<
2778 reg-names = "mdss"; <<
2779 <<
2780 interrupts = <GIC_SPI <<
2781 interrupt-controller; <<
2782 #interrupt-cells = <1 <<
2783 <<
2784 clocks = <&mmcc MDSS_ <<
2785 <&mmcc MDSS_ <<
2786 <&mmcc MDSS_ <<
2787 clock-names = "iface" <<
2788 "bus", <<
2789 "core"; <<
2790 <<
2791 power-domains = <&mmc <<
2792 iommus = <&mmss_smmu <<
2793 <<
2794 #address-cells = <1>; <<
2795 #size-cells = <1>; <<
2796 ranges; <<
2797 <<
2798 status = "disabled"; <<
2799 <<
2800 mdss_mdp: display-con <<
2801 compatible = <<
2802 reg = <0x0c90 <<
2803 <0x0c9a <<
2804 <0x0c9b <<
2805 <0x0c9b <<
2806 reg-names = " <<
2807 " <<
2808 " <<
2809 " <<
2810 <<
2811 interrupt-par <<
2812 interrupts = <<
2813 <<
2814 clocks = <&mm <<
2815 <&mm <<
2816 <&mm <<
2817 <&mm <<
2818 <&mm <<
2819 clock-names = <<
2820 <<
2821 <<
2822 <<
2823 <<
2824 <<
2825 assigned-cloc <<
2826 assigned-cloc <<
2827 <<
2828 operating-poi <<
2829 power-domains <<
2830 <<
2831 mdp_opp_table <<
2832 compa <<
2833 <<
2834 opp-1 <<
2835 <<
2836 <<
2837 }; <<
2838 <<
2839 opp-2 <<
2840 <<
2841 <<
2842 }; <<
2843 <<
2844 opp-3 <<
2845 <<
2846 <<
2847 }; <<
2848 <<
2849 opp-4 <<
2850 <<
2851 <<
2852 }; <<
2853 }; <<
2854 <<
2855 ports { <<
2856 #addr <<
2857 #size <<
2858 <<
2859 port@ <<
2860 <<
2861 <<
2862 <<
2863 <<
2864 <<
2865 }; <<
2866 <<
2867 port@ <<
2868 <<
2869 <<
2870 <<
2871 <<
2872 <<
2873 }; <<
2874 }; <<
2875 }; <<
2876 <<
2877 mdss_dsi0: dsi@c99400 <<
2878 compatible = <<
2879 reg = <0x0c99 <<
2880 reg-names = " <<
2881 <<
2882 interrupt-par <<
2883 interrupts = <<
2884 <<
2885 clocks = <&mm <<
2886 <&mm <<
2887 <&mm <<
2888 <&mm <<
2889 <&mm <<
2890 <&mm <<
2891 clock-names = <<
2892 <<
2893 <<
2894 <<
2895 <<
2896 <<
2897 assigned-cloc <<
2898 <<
2899 assigned-cloc <<
2900 <<
2901 <<
2902 operating-poi <<
2903 power-domains <<
2904 <<
2905 phys = <&mdss <<
2906 phy-names = " <<
2907 <<
2908 #address-cell <<
2909 #size-cells = <<
2910 <<
2911 status = "dis <<
2912 <<
2913 ports { <<
2914 #addr <<
2915 #size <<
2916 <<
2917 port@ <<
2918 <<
2919 <<
2920 <<
2921 <<
2922 <<
2923 }; <<
2924 <<
2925 port@ <<
2926 <<
2927 <<
2928 <<
2929 <<
2930 }; <<
2931 }; <<
2932 }; <<
2933 <<
2934 mdss_dsi0_phy: phy@c9 <<
2935 compatible = <<
2936 reg = <0x0c99 <<
2937 <0x0c99 <<
2938 <0x0c99 <<
2939 reg-names = " <<
2940 " <<
2941 " <<
2942 <<
2943 clocks = <&mm <<
2944 <&rp <<
2945 clock-names = <<
2946 <<
2947 #clock-cells <<
2948 #phy-cells = <<
2949 <<
2950 status = "dis <<
2951 }; <<
2952 <<
2953 mdss_dsi1: dsi@c99600 <<
2954 compatible = <<
2955 reg = <0x0c99 <<
2956 reg-names = " <<
2957 <<
2958 interrupt-par <<
2959 interrupts = <<
2960 <<
2961 clocks = <&mm <<
2962 <&mm <<
2963 <&mm <<
2964 <&mm <<
2965 <&mm <<
2966 <&mm <<
2967 clock-names = <<
2968 <<
2969 <<
2970 <<
2971 <<
2972 <<
2973 assigned-cloc <<
2974 <<
2975 assigned-cloc <<
2976 <<
2977 <<
2978 operating-poi <<
2979 power-domains <<
2980 <<
2981 phys = <&mdss <<
2982 phy-names = " <<
2983 <<
2984 #address-cell <<
2985 #size-cells = <<
2986 <<
2987 status = "dis <<
2988 <<
2989 ports { <<
2990 #addr <<
2991 #size <<
2992 <<
2993 port@ <<
2994 <<
2995 <<
2996 <<
2997 <<
2998 <<
2999 }; <<
3000 <<
3001 port@ <<
3002 <<
3003 <<
3004 <<
3005 <<
3006 }; <<
3007 }; <<
3008 }; <<
3009 <<
3010 mdss_dsi1_phy: phy@c9 <<
3011 compatible = <<
3012 reg = <0x0c99 <<
3013 <0x0c99 <<
3014 <0x0c99 <<
3015 reg-names = " <<
3016 " <<
3017 " <<
3018 <<
3019 clocks = <&mm <<
3020 <&rp <<
3021 clock-names = <<
3022 <<
3023 <<
3024 #clock-cells <<
3025 #phy-cells = <<
3026 <<
3027 status = "dis <<
3028 }; <<
3029 }; <<
3030 <<
3031 venus: video-codec@cc00000 { <<
3032 compatible = "qcom,ms <<
3033 reg = <0x0cc00000 0xf <<
3034 interrupts = <GIC_SPI <<
3035 power-domains = <&mmc <<
3036 clocks = <&mmcc VIDEO <<
3037 <&mmcc VIDEO <<
3038 <&mmcc VIDEO <<
3039 <&mmcc VIDEO <<
3040 clock-names = "core", <<
3041 iommus = <&mmss_smmu <<
3042 <&mmss_smmu <<
3043 <&mmss_smmu <<
3044 <&mmss_smmu <<
3045 <&mmss_smmu <<
3046 <&mmss_smmu <<
3047 <&mmss_smmu <<
3048 <&mmss_smmu <<
3049 <&mmss_smmu <<
3050 <&mmss_smmu <<
3051 <&mmss_smmu <<
3052 <&mmss_smmu <<
3053 <&mmss_smmu <<
3054 <&mmss_smmu <<
3055 <&mmss_smmu <<
3056 <&mmss_smmu <<
3057 <&mmss_smmu <<
3058 <&mmss_smmu <<
3059 <&mmss_smmu <<
3060 <&mmss_smmu <<
3061 memory-region = <&ven <<
3062 status = "disabled"; <<
3063 <<
3064 video-decoder { <<
3065 compatible = <<
3066 clocks = <&mm <<
3067 clock-names = <<
3068 power-domains <<
3069 }; <<
3070 <<
3071 video-encoder { <<
3072 compatible = <<
3073 clocks = <&mm <<
3074 clock-names = <<
3075 power-domains <<
3076 }; <<
3077 }; <<
3078 <<
3079 mmss_smmu: iommu@cd00000 { <<
3080 compatible = "qcom,ms <<
3081 reg = <0x0cd00000 0x4 <<
3082 #iommu-cells = <1>; <<
3083 <<
3084 clocks = <&mmcc MNOC_ <<
3085 <&mmcc BIMC_ <<
3086 <&mmcc BIMC_ <<
3087 clock-names = "iface- <<
3088 "iface- <<
3089 "bus-sm <<
3090 <<
3091 #global-interrupts = <<
3092 interrupts = <<
3093 <GIC_SPI 263 <<
3094 <GIC_SPI 266 <<
3095 <GIC_SPI 267 <<
3096 <GIC_SPI 268 <<
3097 <GIC_SPI 244 <<
3098 <GIC_SPI 245 <<
3099 <GIC_SPI 247 <<
3100 <GIC_SPI 248 <<
3101 <GIC_SPI 249 <<
3102 <GIC_SPI 250 <<
3103 <GIC_SPI 251 <<
3104 <GIC_SPI 252 <<
3105 <GIC_SPI 253 <<
3106 <GIC_SPI 254 <<
3107 <GIC_SPI 255 <<
3108 <GIC_SPI 256 <<
3109 <GIC_SPI 260 <<
3110 <GIC_SPI 261 <<
3111 <GIC_SPI 262 <<
3112 <GIC_SPI 272 <<
3113 <<
3114 power-domains = <&mmc <<
3115 }; <<
3116 <<
3117 remoteproc_adsp: remoteproc@1 <<
3118 compatible = "qcom,ms <<
3119 reg = <0x17300000 0x4 <<
3120 <<
3121 interrupts-extended = <<
3122 <<
3123 <<
3124 <<
3125 <<
3126 interrupt-names = "wd <<
3127 "ha <<
3128 <<
3129 clocks = <&rpmcc RPM_ <<
3130 clock-names = "xo"; <<
3131 <<
3132 memory-region = <&ads <<
3133 <<
3134 qcom,smem-states = <& <<
3135 qcom,smem-state-names <<
3136 <<
3137 power-domains = <&rpm <<
3138 power-domain-names = <<
3139 <<
3140 status = "disabled"; <<
3141 <<
3142 glink-edge { <<
3143 interrupts = <<
3144 label = "lpas <<
3145 qcom,remote-p <<
3146 mboxes = <&ap <<
3147 }; <<
3148 }; <<
3149 <<
3150 apcs_glb: mailbox@17911000 { 1778 apcs_glb: mailbox@17911000 {
3151 compatible = "qcom,ms !! 1779 compatible = "qcom,msm8998-apcs-hmss-global";
3152 "qcom,ms <<
3153 reg = <0x17911000 0x1 1780 reg = <0x17911000 0x1000>;
3154 1781
3155 #mbox-cells = <1>; 1782 #mbox-cells = <1>;
3156 }; 1783 };
3157 1784
3158 timer@17920000 { 1785 timer@17920000 {
3159 #address-cells = <1>; 1786 #address-cells = <1>;
3160 #size-cells = <1>; 1787 #size-cells = <1>;
3161 ranges; 1788 ranges;
3162 compatible = "arm,arm 1789 compatible = "arm,armv7-timer-mem";
3163 reg = <0x17920000 0x1 1790 reg = <0x17920000 0x1000>;
3164 1791
3165 frame@17921000 { 1792 frame@17921000 {
3166 frame-number 1793 frame-number = <0>;
3167 interrupts = 1794 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
3168 1795 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
3169 reg = <0x1792 1796 reg = <0x17921000 0x1000>,
3170 <0x1792 1797 <0x17922000 0x1000>;
3171 }; 1798 };
3172 1799
3173 frame@17923000 { 1800 frame@17923000 {
3174 frame-number 1801 frame-number = <1>;
3175 interrupts = 1802 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
3176 reg = <0x1792 1803 reg = <0x17923000 0x1000>;
3177 status = "dis 1804 status = "disabled";
3178 }; 1805 };
3179 1806
3180 frame@17924000 { 1807 frame@17924000 {
3181 frame-number 1808 frame-number = <2>;
3182 interrupts = 1809 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
3183 reg = <0x1792 1810 reg = <0x17924000 0x1000>;
3184 status = "dis 1811 status = "disabled";
3185 }; 1812 };
3186 1813
3187 frame@17925000 { 1814 frame@17925000 {
3188 frame-number 1815 frame-number = <3>;
3189 interrupts = 1816 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3190 reg = <0x1792 1817 reg = <0x17925000 0x1000>;
3191 status = "dis 1818 status = "disabled";
3192 }; 1819 };
3193 1820
3194 frame@17926000 { 1821 frame@17926000 {
3195 frame-number 1822 frame-number = <4>;
3196 interrupts = 1823 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3197 reg = <0x1792 1824 reg = <0x17926000 0x1000>;
3198 status = "dis 1825 status = "disabled";
3199 }; 1826 };
3200 1827
3201 frame@17927000 { 1828 frame@17927000 {
3202 frame-number 1829 frame-number = <5>;
3203 interrupts = 1830 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3204 reg = <0x1792 1831 reg = <0x17927000 0x1000>;
3205 status = "dis 1832 status = "disabled";
3206 }; 1833 };
3207 1834
3208 frame@17928000 { 1835 frame@17928000 {
3209 frame-number 1836 frame-number = <6>;
3210 interrupts = 1837 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
3211 reg = <0x1792 1838 reg = <0x17928000 0x1000>;
3212 status = "dis 1839 status = "disabled";
3213 }; 1840 };
3214 }; 1841 };
3215 1842
3216 intc: interrupt-controller@17 1843 intc: interrupt-controller@17a00000 {
3217 compatible = "arm,gic 1844 compatible = "arm,gic-v3";
3218 reg = <0x17a00000 0x1 1845 reg = <0x17a00000 0x10000>, /* GICD */
3219 <0x17b00000 0x1 1846 <0x17b00000 0x100000>; /* GICR * 8 */
3220 #interrupt-cells = <3 1847 #interrupt-cells = <3>;
3221 #address-cells = <1>; 1848 #address-cells = <1>;
3222 #size-cells = <1>; 1849 #size-cells = <1>;
3223 ranges; 1850 ranges;
3224 interrupt-controller; 1851 interrupt-controller;
3225 #redistributor-region 1852 #redistributor-regions = <1>;
3226 redistributor-stride 1853 redistributor-stride = <0x0 0x20000>;
3227 interrupts = <GIC_PPI 1854 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3228 }; 1855 };
3229 <<
3230 wifi: wifi@18800000 { <<
3231 compatible = "qcom,wc <<
3232 status = "disabled"; <<
3233 reg = <0x18800000 0x8 <<
3234 reg-names = "membase" <<
3235 memory-region = <&wla <<
3236 clocks = <&rpmcc RPM_ <<
3237 clock-names = "cxo_re <<
3238 interrupts = <<
3239 <GIC_SPI 413 <<
3240 <GIC_SPI 414 <<
3241 <GIC_SPI 415 <<
3242 <GIC_SPI 416 <<
3243 <GIC_SPI 417 <<
3244 <GIC_SPI 418 <<
3245 <GIC_SPI 420 <<
3246 <GIC_SPI 421 <<
3247 <GIC_SPI 422 <<
3248 <GIC_SPI 423 <<
3249 <GIC_SPI 424 <<
3250 <GIC_SPI 425 <<
3251 iommus = <&anoc2_smmu <<
3252 <&anoc2_smmu <<
3253 qcom,snoc-host-cap-8b <<
3254 qcom,no-msa-ready-ind <<
3255 }; <<
3256 }; 1856 };
3257 }; 1857 };
>> 1858
>> 1859 #include "msm8998-pins.dtsi"
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