1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2016, The Linux Foundation. A 2 /* Copyright (c) 2016, The Linux Foundation. All rights reserved. */
3 3
4 #include <dt-bindings/interrupt-controller/arm 4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-msm8998.h 5 #include <dt-bindings/clock/qcom,gcc-msm8998.h>
6 #include <dt-bindings/clock/qcom,gpucc-msm8998 6 #include <dt-bindings/clock/qcom,gpucc-msm8998.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8998. <<
8 #include <dt-bindings/clock/qcom,rpmcc.h> 7 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/firmware/qcom,scm.h> <<
10 #include <dt-bindings/power/qcom-rpmpd.h> 8 #include <dt-bindings/power/qcom-rpmpd.h>
11 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/gpio/gpio.h>
12 10
13 / { 11 / {
14 interrupt-parent = <&intc>; 12 interrupt-parent = <&intc>;
15 13
16 qcom,msm-id = <292 0x0>; 14 qcom,msm-id = <292 0x0>;
17 15
18 #address-cells = <2>; 16 #address-cells = <2>;
19 #size-cells = <2>; 17 #size-cells = <2>;
20 18
21 chosen { }; 19 chosen { };
22 20
23 memory@80000000 { !! 21 memory {
24 device_type = "memory"; 22 device_type = "memory";
25 /* We expect the bootloader to 23 /* We expect the bootloader to fill in the reg */
26 reg = <0x0 0x80000000 0x0 0x0> !! 24 reg = <0 0 0 0>;
27 }; 25 };
28 26
29 reserved-memory { 27 reserved-memory {
30 #address-cells = <2>; 28 #address-cells = <2>;
31 #size-cells = <2>; 29 #size-cells = <2>;
32 ranges; 30 ranges;
33 31
34 hyp_mem: memory@85800000 { 32 hyp_mem: memory@85800000 {
35 reg = <0x0 0x85800000 33 reg = <0x0 0x85800000 0x0 0x600000>;
36 no-map; 34 no-map;
37 }; 35 };
38 36
39 xbl_mem: memory@85e00000 { 37 xbl_mem: memory@85e00000 {
40 reg = <0x0 0x85e00000 38 reg = <0x0 0x85e00000 0x0 0x100000>;
41 no-map; 39 no-map;
42 }; 40 };
43 41
44 smem_mem: smem-mem@86000000 { 42 smem_mem: smem-mem@86000000 {
45 reg = <0x0 0x86000000 43 reg = <0x0 0x86000000 0x0 0x200000>;
46 no-map; 44 no-map;
47 }; 45 };
48 46
49 tz_mem: memory@86200000 { 47 tz_mem: memory@86200000 {
50 reg = <0x0 0x86200000 48 reg = <0x0 0x86200000 0x0 0x2d00000>;
51 no-map; 49 no-map;
52 }; 50 };
53 51
54 rmtfs_mem: memory@88f00000 { 52 rmtfs_mem: memory@88f00000 {
55 compatible = "qcom,rmt 53 compatible = "qcom,rmtfs-mem";
56 reg = <0x0 0x88f00000 54 reg = <0x0 0x88f00000 0x0 0x200000>;
57 no-map; 55 no-map;
58 56
59 qcom,client-id = <1>; 57 qcom,client-id = <1>;
60 qcom,vmid = <QCOM_SCM_ !! 58 qcom,vmid = <15>;
61 }; 59 };
62 60
63 spss_mem: memory@8ab00000 { 61 spss_mem: memory@8ab00000 {
64 reg = <0x0 0x8ab00000 62 reg = <0x0 0x8ab00000 0x0 0x700000>;
65 no-map; 63 no-map;
66 }; 64 };
67 65
68 adsp_mem: memory@8b200000 { 66 adsp_mem: memory@8b200000 {
69 reg = <0x0 0x8b200000 67 reg = <0x0 0x8b200000 0x0 0x1a00000>;
70 no-map; 68 no-map;
71 }; 69 };
72 70
73 mpss_mem: memory@8cc00000 { 71 mpss_mem: memory@8cc00000 {
74 reg = <0x0 0x8cc00000 72 reg = <0x0 0x8cc00000 0x0 0x7000000>;
75 no-map; 73 no-map;
76 }; 74 };
77 75
78 venus_mem: memory@93c00000 { 76 venus_mem: memory@93c00000 {
79 reg = <0x0 0x93c00000 77 reg = <0x0 0x93c00000 0x0 0x500000>;
80 no-map; 78 no-map;
81 }; 79 };
82 80
83 mba_mem: memory@94100000 { 81 mba_mem: memory@94100000 {
84 reg = <0x0 0x94100000 82 reg = <0x0 0x94100000 0x0 0x200000>;
85 no-map; 83 no-map;
86 }; 84 };
87 85
88 slpi_mem: memory@94300000 { 86 slpi_mem: memory@94300000 {
89 reg = <0x0 0x94300000 87 reg = <0x0 0x94300000 0x0 0xf00000>;
90 no-map; 88 no-map;
91 }; 89 };
92 90
93 ipa_fw_mem: memory@95200000 { 91 ipa_fw_mem: memory@95200000 {
94 reg = <0x0 0x95200000 92 reg = <0x0 0x95200000 0x0 0x10000>;
95 no-map; 93 no-map;
96 }; 94 };
97 95
98 ipa_gsi_mem: memory@95210000 { 96 ipa_gsi_mem: memory@95210000 {
99 reg = <0x0 0x95210000 97 reg = <0x0 0x95210000 0x0 0x5000>;
100 no-map; 98 no-map;
101 }; 99 };
102 100
103 gpu_mem: memory@95600000 { 101 gpu_mem: memory@95600000 {
104 reg = <0x0 0x95600000 102 reg = <0x0 0x95600000 0x0 0x100000>;
105 no-map; 103 no-map;
106 }; 104 };
107 105
108 wlan_msa_mem: memory@95700000 106 wlan_msa_mem: memory@95700000 {
109 reg = <0x0 0x95700000 107 reg = <0x0 0x95700000 0x0 0x100000>;
110 no-map; 108 no-map;
111 }; 109 };
112 <<
113 mdata_mem: mpss-metadata { <<
114 alloc-ranges = <0x0 0x <<
115 size = <0x0 0x4000>; <<
116 no-map; <<
117 }; <<
118 }; 110 };
119 111
120 clocks { 112 clocks {
121 xo: xo-board { 113 xo: xo-board {
122 compatible = "fixed-cl 114 compatible = "fixed-clock";
123 #clock-cells = <0>; 115 #clock-cells = <0>;
124 clock-frequency = <192 116 clock-frequency = <19200000>;
125 clock-output-names = " 117 clock-output-names = "xo_board";
126 }; 118 };
127 119
128 sleep_clk: sleep-clk { !! 120 sleep_clk {
129 compatible = "fixed-cl 121 compatible = "fixed-clock";
130 #clock-cells = <0>; 122 #clock-cells = <0>;
131 clock-frequency = <327 123 clock-frequency = <32764>;
132 }; 124 };
133 }; 125 };
134 126
135 cpus { 127 cpus {
136 #address-cells = <2>; 128 #address-cells = <2>;
137 #size-cells = <0>; 129 #size-cells = <0>;
138 130
139 CPU0: cpu@0 { 131 CPU0: cpu@0 {
140 device_type = "cpu"; 132 device_type = "cpu";
141 compatible = "qcom,kry !! 133 compatible = "arm,armv8";
142 reg = <0x0 0x0>; 134 reg = <0x0 0x0>;
143 enable-method = "psci" 135 enable-method = "psci";
144 capacity-dmips-mhz = < <<
145 cpu-idle-states = <&LI 136 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
146 next-level-cache = <&L 137 next-level-cache = <&L2_0>;
147 L2_0: l2-cache { 138 L2_0: l2-cache {
148 compatible = " !! 139 compatible = "arm,arch-cache";
149 cache-level = 140 cache-level = <2>;
150 cache-unified; !! 141 };
>> 142 L1_I_0: l1-icache {
>> 143 compatible = "arm,arch-cache";
>> 144 };
>> 145 L1_D_0: l1-dcache {
>> 146 compatible = "arm,arch-cache";
151 }; 147 };
152 }; 148 };
153 149
154 CPU1: cpu@1 { 150 CPU1: cpu@1 {
155 device_type = "cpu"; 151 device_type = "cpu";
156 compatible = "qcom,kry !! 152 compatible = "arm,armv8";
157 reg = <0x0 0x1>; 153 reg = <0x0 0x1>;
158 enable-method = "psci" 154 enable-method = "psci";
159 capacity-dmips-mhz = < <<
160 cpu-idle-states = <&LI 155 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
161 next-level-cache = <&L 156 next-level-cache = <&L2_0>;
>> 157 L1_I_1: l1-icache {
>> 158 compatible = "arm,arch-cache";
>> 159 };
>> 160 L1_D_1: l1-dcache {
>> 161 compatible = "arm,arch-cache";
>> 162 };
162 }; 163 };
163 164
164 CPU2: cpu@2 { 165 CPU2: cpu@2 {
165 device_type = "cpu"; 166 device_type = "cpu";
166 compatible = "qcom,kry !! 167 compatible = "arm,armv8";
167 reg = <0x0 0x2>; 168 reg = <0x0 0x2>;
168 enable-method = "psci" 169 enable-method = "psci";
169 capacity-dmips-mhz = < <<
170 cpu-idle-states = <&LI 170 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
171 next-level-cache = <&L 171 next-level-cache = <&L2_0>;
>> 172 L1_I_2: l1-icache {
>> 173 compatible = "arm,arch-cache";
>> 174 };
>> 175 L1_D_2: l1-dcache {
>> 176 compatible = "arm,arch-cache";
>> 177 };
172 }; 178 };
173 179
174 CPU3: cpu@3 { 180 CPU3: cpu@3 {
175 device_type = "cpu"; 181 device_type = "cpu";
176 compatible = "qcom,kry !! 182 compatible = "arm,armv8";
177 reg = <0x0 0x3>; 183 reg = <0x0 0x3>;
178 enable-method = "psci" 184 enable-method = "psci";
179 capacity-dmips-mhz = < <<
180 cpu-idle-states = <&LI 185 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
181 next-level-cache = <&L 186 next-level-cache = <&L2_0>;
>> 187 L1_I_3: l1-icache {
>> 188 compatible = "arm,arch-cache";
>> 189 };
>> 190 L1_D_3: l1-dcache {
>> 191 compatible = "arm,arch-cache";
>> 192 };
182 }; 193 };
183 194
184 CPU4: cpu@100 { 195 CPU4: cpu@100 {
185 device_type = "cpu"; 196 device_type = "cpu";
186 compatible = "qcom,kry !! 197 compatible = "arm,armv8";
187 reg = <0x0 0x100>; 198 reg = <0x0 0x100>;
188 enable-method = "psci" 199 enable-method = "psci";
189 capacity-dmips-mhz = < <<
190 cpu-idle-states = <&BI 200 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
191 next-level-cache = <&L 201 next-level-cache = <&L2_1>;
192 L2_1: l2-cache { 202 L2_1: l2-cache {
193 compatible = " !! 203 compatible = "arm,arch-cache";
194 cache-level = 204 cache-level = <2>;
195 cache-unified; !! 205 };
>> 206 L1_I_100: l1-icache {
>> 207 compatible = "arm,arch-cache";
>> 208 };
>> 209 L1_D_100: l1-dcache {
>> 210 compatible = "arm,arch-cache";
196 }; 211 };
197 }; 212 };
198 213
199 CPU5: cpu@101 { 214 CPU5: cpu@101 {
200 device_type = "cpu"; 215 device_type = "cpu";
201 compatible = "qcom,kry !! 216 compatible = "arm,armv8";
202 reg = <0x0 0x101>; 217 reg = <0x0 0x101>;
203 enable-method = "psci" 218 enable-method = "psci";
204 capacity-dmips-mhz = < <<
205 cpu-idle-states = <&BI 219 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
206 next-level-cache = <&L 220 next-level-cache = <&L2_1>;
>> 221 L1_I_101: l1-icache {
>> 222 compatible = "arm,arch-cache";
>> 223 };
>> 224 L1_D_101: l1-dcache {
>> 225 compatible = "arm,arch-cache";
>> 226 };
207 }; 227 };
208 228
209 CPU6: cpu@102 { 229 CPU6: cpu@102 {
210 device_type = "cpu"; 230 device_type = "cpu";
211 compatible = "qcom,kry !! 231 compatible = "arm,armv8";
212 reg = <0x0 0x102>; 232 reg = <0x0 0x102>;
213 enable-method = "psci" 233 enable-method = "psci";
214 capacity-dmips-mhz = < <<
215 cpu-idle-states = <&BI 234 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
216 next-level-cache = <&L 235 next-level-cache = <&L2_1>;
>> 236 L1_I_102: l1-icache {
>> 237 compatible = "arm,arch-cache";
>> 238 };
>> 239 L1_D_102: l1-dcache {
>> 240 compatible = "arm,arch-cache";
>> 241 };
217 }; 242 };
218 243
219 CPU7: cpu@103 { 244 CPU7: cpu@103 {
220 device_type = "cpu"; 245 device_type = "cpu";
221 compatible = "qcom,kry !! 246 compatible = "arm,armv8";
222 reg = <0x0 0x103>; 247 reg = <0x0 0x103>;
223 enable-method = "psci" 248 enable-method = "psci";
224 capacity-dmips-mhz = < <<
225 cpu-idle-states = <&BI 249 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
226 next-level-cache = <&L 250 next-level-cache = <&L2_1>;
>> 251 L1_I_103: l1-icache {
>> 252 compatible = "arm,arch-cache";
>> 253 };
>> 254 L1_D_103: l1-dcache {
>> 255 compatible = "arm,arch-cache";
>> 256 };
227 }; 257 };
228 258
229 cpu-map { 259 cpu-map {
230 cluster0 { 260 cluster0 {
231 core0 { 261 core0 {
232 cpu = 262 cpu = <&CPU0>;
233 }; 263 };
234 264
235 core1 { 265 core1 {
236 cpu = 266 cpu = <&CPU1>;
237 }; 267 };
238 268
239 core2 { 269 core2 {
240 cpu = 270 cpu = <&CPU2>;
241 }; 271 };
242 272
243 core3 { 273 core3 {
244 cpu = 274 cpu = <&CPU3>;
245 }; 275 };
246 }; 276 };
247 277
248 cluster1 { 278 cluster1 {
249 core0 { 279 core0 {
250 cpu = 280 cpu = <&CPU4>;
251 }; 281 };
252 282
253 core1 { 283 core1 {
254 cpu = 284 cpu = <&CPU5>;
255 }; 285 };
256 286
257 core2 { 287 core2 {
258 cpu = 288 cpu = <&CPU6>;
259 }; 289 };
260 290
261 core3 { 291 core3 {
262 cpu = 292 cpu = <&CPU7>;
263 }; 293 };
264 }; 294 };
265 }; 295 };
266 296
267 idle-states { 297 idle-states {
268 entry-method = "psci"; 298 entry-method = "psci";
269 299
270 LITTLE_CPU_SLEEP_0: cp 300 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
271 compatible = " 301 compatible = "arm,idle-state";
272 idle-state-nam 302 idle-state-name = "little-retention";
273 /* CPU Retenti <<
274 arm,psci-suspe 303 arm,psci-suspend-param = <0x00000002>;
275 entry-latency- 304 entry-latency-us = <81>;
276 exit-latency-u 305 exit-latency-us = <86>;
277 min-residency- !! 306 min-residency-us = <200>;
278 }; 307 };
279 308
280 LITTLE_CPU_SLEEP_1: cp 309 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
281 compatible = " 310 compatible = "arm,idle-state";
282 idle-state-nam 311 idle-state-name = "little-power-collapse";
283 /* CPU + L2 Po <<
284 arm,psci-suspe 312 arm,psci-suspend-param = <0x40000003>;
285 entry-latency- !! 313 entry-latency-us = <273>;
286 exit-latency-u !! 314 exit-latency-us = <612>;
287 min-residency- !! 315 min-residency-us = <1000>;
288 local-timer-st 316 local-timer-stop;
289 }; 317 };
290 318
291 BIG_CPU_SLEEP_0: cpu-s 319 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
292 compatible = " 320 compatible = "arm,idle-state";
293 idle-state-nam 321 idle-state-name = "big-retention";
294 /* CPU Retenti <<
295 arm,psci-suspe 322 arm,psci-suspend-param = <0x00000002>;
296 entry-latency- 323 entry-latency-us = <79>;
297 exit-latency-u 324 exit-latency-us = <82>;
298 min-residency- !! 325 min-residency-us = <200>;
299 }; 326 };
300 327
301 BIG_CPU_SLEEP_1: cpu-s 328 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
302 compatible = " 329 compatible = "arm,idle-state";
303 idle-state-nam 330 idle-state-name = "big-power-collapse";
304 /* CPU + L2 Po <<
305 arm,psci-suspe 331 arm,psci-suspend-param = <0x40000003>;
306 entry-latency- !! 332 entry-latency-us = <336>;
307 exit-latency-u !! 333 exit-latency-us = <525>;
308 min-residency- !! 334 min-residency-us = <1000>;
309 local-timer-st 335 local-timer-stop;
310 }; 336 };
311 }; 337 };
312 }; 338 };
313 339
314 firmware { 340 firmware {
315 scm { 341 scm {
316 compatible = "qcom,scm 342 compatible = "qcom,scm-msm8998", "qcom,scm";
317 }; 343 };
318 }; 344 };
319 345
320 dsi_opp_table: opp-table-dsi { !! 346 tcsr_mutex: hwlock {
321 compatible = "operating-points !! 347 compatible = "qcom,tcsr-mutex";
322 !! 348 syscon = <&tcsr_mutex_regs 0 0x1000>;
323 opp-131250000 { !! 349 #hwlock-cells = <1>;
324 opp-hz = /bits/ 64 <13 <<
325 required-opps = <&rpmp <<
326 }; <<
327 <<
328 opp-210000000 { <<
329 opp-hz = /bits/ 64 <21 <<
330 required-opps = <&rpmp <<
331 }; <<
332 <<
333 opp-312500000 { <<
334 opp-hz = /bits/ 64 <31 <<
335 required-opps = <&rpmp <<
336 }; <<
337 }; 350 };
338 351
339 psci { 352 psci {
340 compatible = "arm,psci-1.0"; 353 compatible = "arm,psci-1.0";
341 method = "smc"; 354 method = "smc";
342 }; 355 };
343 356
344 rpm: remoteproc { !! 357 rpm-glink {
345 compatible = "qcom,msm8998-rpm !! 358 compatible = "qcom,glink-rpm";
>> 359
>> 360 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
>> 361 qcom,rpm-msg-ram = <&rpm_msg_ram>;
>> 362 mboxes = <&apcs_glb 0>;
>> 363
>> 364 rpm_requests: rpm-requests {
>> 365 compatible = "qcom,rpm-msm8998";
>> 366 qcom,glink-channels = "rpm_requests";
>> 367
>> 368 rpmcc: clock-controller {
>> 369 compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc";
>> 370 #clock-cells = <1>;
>> 371 };
>> 372
>> 373 rpmpd: power-controller {
>> 374 compatible = "qcom,msm8998-rpmpd";
>> 375 #power-domain-cells = <1>;
>> 376 operating-points-v2 = <&rpmpd_opp_table>;
>> 377
>> 378 rpmpd_opp_table: opp-table {
>> 379 compatible = "operating-points-v2";
>> 380
>> 381 rpmpd_opp_ret: opp1 {
>> 382 opp-level = <16>;
>> 383 };
>> 384
>> 385 rpmpd_opp_ret_plus: opp2 {
>> 386 opp-level = <32>;
>> 387 };
346 388
347 glink-edge { !! 389 rpmpd_opp_min_svs: opp3 {
348 compatible = "qcom,gli !! 390 opp-level = <48>;
>> 391 };
>> 392
>> 393 rpmpd_opp_low_svs: opp4 {
>> 394 opp-level = <64>;
>> 395 };
>> 396
>> 397 rpmpd_opp_svs: opp5 {
>> 398 opp-level = <128>;
>> 399 };
>> 400
>> 401 rpmpd_opp_svs_plus: opp6 {
>> 402 opp-level = <192>;
>> 403 };
349 404
350 interrupts = <GIC_SPI !! 405 rpmpd_opp_nom: opp7 {
351 qcom,rpm-msg-ram = <&r !! 406 opp-level = <256>;
352 mboxes = <&apcs_glb 0> !! 407 };
353 !! 408
354 rpm_requests: rpm-requ !! 409 rpmpd_opp_nom_plus: opp8 {
355 compatible = " !! 410 opp-level = <320>;
356 qcom,glink-cha !! 411 };
357 !! 412
358 rpmcc: clock-c !! 413 rpmpd_opp_turbo: opp9 {
359 compat !! 414 opp-level = <384>;
360 clocks !! 415 };
361 clock- !! 416
362 #clock !! 417 rpmpd_opp_turbo_plus: opp10 {
363 }; !! 418 opp-level = <512>;
364 <<
365 rpmpd: power-c <<
366 compat <<
367 #power <<
368 operat <<
369 <<
370 rpmpd_ <<
371 <<
372 <<
373 <<
374 <<
375 <<
376 <<
377 <<
378 <<
379 <<
380 <<
381 <<
382 <<
383 <<
384 <<
385 <<
386 <<
387 <<
388 <<
389 <<
390 <<
391 <<
392 <<
393 <<
394 <<
395 <<
396 <<
397 <<
398 <<
399 <<
400 <<
401 <<
402 <<
403 <<
404 <<
405 <<
406 <<
407 <<
408 <<
409 <<
410 <<
411 <<
412 }; 419 };
413 }; 420 };
414 }; 421 };
415 }; 422 };
416 }; 423 };
417 424
418 smem { 425 smem {
419 compatible = "qcom,smem"; 426 compatible = "qcom,smem";
420 memory-region = <&smem_mem>; 427 memory-region = <&smem_mem>;
421 hwlocks = <&tcsr_mutex 3>; 428 hwlocks = <&tcsr_mutex 3>;
422 }; 429 };
423 430
424 smp2p-lpass { 431 smp2p-lpass {
425 compatible = "qcom,smp2p"; 432 compatible = "qcom,smp2p";
426 qcom,smem = <443>, <429>; 433 qcom,smem = <443>, <429>;
427 434
428 interrupts = <GIC_SPI 158 IRQ_ 435 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
429 436
430 mboxes = <&apcs_glb 10>; 437 mboxes = <&apcs_glb 10>;
431 438
432 qcom,local-pid = <0>; 439 qcom,local-pid = <0>;
433 qcom,remote-pid = <2>; 440 qcom,remote-pid = <2>;
434 441
435 adsp_smp2p_out: master-kernel 442 adsp_smp2p_out: master-kernel {
436 qcom,entry-name = "mas 443 qcom,entry-name = "master-kernel";
437 #qcom,smem-state-cells 444 #qcom,smem-state-cells = <1>;
438 }; 445 };
439 446
440 adsp_smp2p_in: slave-kernel { 447 adsp_smp2p_in: slave-kernel {
441 qcom,entry-name = "sla 448 qcom,entry-name = "slave-kernel";
442 449
443 interrupt-controller; 450 interrupt-controller;
444 #interrupt-cells = <2> 451 #interrupt-cells = <2>;
445 }; 452 };
446 }; 453 };
447 454
448 smp2p-mpss { 455 smp2p-mpss {
449 compatible = "qcom,smp2p"; 456 compatible = "qcom,smp2p";
450 qcom,smem = <435>, <428>; 457 qcom,smem = <435>, <428>;
451 interrupts = <GIC_SPI 451 IRQ_ 458 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
452 mboxes = <&apcs_glb 14>; 459 mboxes = <&apcs_glb 14>;
453 qcom,local-pid = <0>; 460 qcom,local-pid = <0>;
454 qcom,remote-pid = <1>; 461 qcom,remote-pid = <1>;
455 462
456 modem_smp2p_out: master-kernel 463 modem_smp2p_out: master-kernel {
457 qcom,entry-name = "mas 464 qcom,entry-name = "master-kernel";
458 #qcom,smem-state-cells 465 #qcom,smem-state-cells = <1>;
459 }; 466 };
460 467
461 modem_smp2p_in: slave-kernel { 468 modem_smp2p_in: slave-kernel {
462 qcom,entry-name = "sla 469 qcom,entry-name = "slave-kernel";
463 interrupt-controller; 470 interrupt-controller;
464 #interrupt-cells = <2> 471 #interrupt-cells = <2>;
465 }; 472 };
466 }; 473 };
467 474
468 smp2p-slpi { 475 smp2p-slpi {
469 compatible = "qcom,smp2p"; 476 compatible = "qcom,smp2p";
470 qcom,smem = <481>, <430>; 477 qcom,smem = <481>, <430>;
471 interrupts = <GIC_SPI 178 IRQ_ 478 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
472 mboxes = <&apcs_glb 26>; 479 mboxes = <&apcs_glb 26>;
473 qcom,local-pid = <0>; 480 qcom,local-pid = <0>;
474 qcom,remote-pid = <3>; 481 qcom,remote-pid = <3>;
475 482
476 slpi_smp2p_out: master-kernel 483 slpi_smp2p_out: master-kernel {
477 qcom,entry-name = "mas 484 qcom,entry-name = "master-kernel";
478 #qcom,smem-state-cells 485 #qcom,smem-state-cells = <1>;
479 }; 486 };
480 487
481 slpi_smp2p_in: slave-kernel { 488 slpi_smp2p_in: slave-kernel {
482 qcom,entry-name = "sla 489 qcom,entry-name = "slave-kernel";
483 interrupt-controller; 490 interrupt-controller;
484 #interrupt-cells = <2> 491 #interrupt-cells = <2>;
485 }; 492 };
486 }; 493 };
487 494
488 thermal-zones { 495 thermal-zones {
489 cpu0-thermal { 496 cpu0-thermal {
490 polling-delay-passive 497 polling-delay-passive = <250>;
>> 498 polling-delay = <1000>;
491 499
492 thermal-sensors = <&ts 500 thermal-sensors = <&tsens0 1>;
493 501
494 trips { 502 trips {
495 cpu0_alert0: t !! 503 cpu0_alert0: trip-point@0 {
496 temper 504 temperature = <75000>;
497 hyster 505 hysteresis = <2000>;
498 type = 506 type = "passive";
499 }; 507 };
500 508
501 cpu0_crit: cpu !! 509 cpu0_crit: cpu_crit {
502 temper 510 temperature = <110000>;
503 hyster 511 hysteresis = <2000>;
504 type = 512 type = "critical";
505 }; 513 };
506 }; 514 };
507 }; 515 };
508 516
509 cpu1-thermal { 517 cpu1-thermal {
510 polling-delay-passive 518 polling-delay-passive = <250>;
>> 519 polling-delay = <1000>;
511 520
512 thermal-sensors = <&ts 521 thermal-sensors = <&tsens0 2>;
513 522
514 trips { 523 trips {
515 cpu1_alert0: t !! 524 cpu1_alert0: trip-point@0 {
516 temper 525 temperature = <75000>;
517 hyster 526 hysteresis = <2000>;
518 type = 527 type = "passive";
519 }; 528 };
520 529
521 cpu1_crit: cpu !! 530 cpu1_crit: cpu_crit {
522 temper 531 temperature = <110000>;
523 hyster 532 hysteresis = <2000>;
524 type = 533 type = "critical";
525 }; 534 };
526 }; 535 };
527 }; 536 };
528 537
529 cpu2-thermal { 538 cpu2-thermal {
530 polling-delay-passive 539 polling-delay-passive = <250>;
>> 540 polling-delay = <1000>;
531 541
532 thermal-sensors = <&ts 542 thermal-sensors = <&tsens0 3>;
533 543
534 trips { 544 trips {
535 cpu2_alert0: t !! 545 cpu2_alert0: trip-point@0 {
536 temper 546 temperature = <75000>;
537 hyster 547 hysteresis = <2000>;
538 type = 548 type = "passive";
539 }; 549 };
540 550
541 cpu2_crit: cpu !! 551 cpu2_crit: cpu_crit {
542 temper 552 temperature = <110000>;
543 hyster 553 hysteresis = <2000>;
544 type = 554 type = "critical";
545 }; 555 };
546 }; 556 };
547 }; 557 };
548 558
549 cpu3-thermal { 559 cpu3-thermal {
550 polling-delay-passive 560 polling-delay-passive = <250>;
>> 561 polling-delay = <1000>;
551 562
552 thermal-sensors = <&ts 563 thermal-sensors = <&tsens0 4>;
553 564
554 trips { 565 trips {
555 cpu3_alert0: t !! 566 cpu3_alert0: trip-point@0 {
556 temper 567 temperature = <75000>;
557 hyster 568 hysteresis = <2000>;
558 type = 569 type = "passive";
559 }; 570 };
560 571
561 cpu3_crit: cpu !! 572 cpu3_crit: cpu_crit {
562 temper 573 temperature = <110000>;
563 hyster 574 hysteresis = <2000>;
564 type = 575 type = "critical";
565 }; 576 };
566 }; 577 };
567 }; 578 };
568 579
569 cpu4-thermal { 580 cpu4-thermal {
570 polling-delay-passive 581 polling-delay-passive = <250>;
>> 582 polling-delay = <1000>;
571 583
572 thermal-sensors = <&ts 584 thermal-sensors = <&tsens0 7>;
573 585
574 trips { 586 trips {
575 cpu4_alert0: t !! 587 cpu4_alert0: trip-point@0 {
576 temper 588 temperature = <75000>;
577 hyster 589 hysteresis = <2000>;
578 type = 590 type = "passive";
579 }; 591 };
580 592
581 cpu4_crit: cpu !! 593 cpu4_crit: cpu_crit {
582 temper 594 temperature = <110000>;
583 hyster 595 hysteresis = <2000>;
584 type = 596 type = "critical";
585 }; 597 };
586 }; 598 };
587 }; 599 };
588 600
589 cpu5-thermal { 601 cpu5-thermal {
590 polling-delay-passive 602 polling-delay-passive = <250>;
>> 603 polling-delay = <1000>;
591 604
592 thermal-sensors = <&ts 605 thermal-sensors = <&tsens0 8>;
593 606
594 trips { 607 trips {
595 cpu5_alert0: t !! 608 cpu5_alert0: trip-point@0 {
596 temper 609 temperature = <75000>;
597 hyster 610 hysteresis = <2000>;
598 type = 611 type = "passive";
599 }; 612 };
600 613
601 cpu5_crit: cpu !! 614 cpu5_crit: cpu_crit {
602 temper 615 temperature = <110000>;
603 hyster 616 hysteresis = <2000>;
604 type = 617 type = "critical";
605 }; 618 };
606 }; 619 };
607 }; 620 };
608 621
609 cpu6-thermal { 622 cpu6-thermal {
610 polling-delay-passive 623 polling-delay-passive = <250>;
>> 624 polling-delay = <1000>;
611 625
612 thermal-sensors = <&ts 626 thermal-sensors = <&tsens0 9>;
613 627
614 trips { 628 trips {
615 cpu6_alert0: t !! 629 cpu6_alert0: trip-point@0 {
616 temper 630 temperature = <75000>;
617 hyster 631 hysteresis = <2000>;
618 type = 632 type = "passive";
619 }; 633 };
620 634
621 cpu6_crit: cpu !! 635 cpu6_crit: cpu_crit {
622 temper 636 temperature = <110000>;
623 hyster 637 hysteresis = <2000>;
624 type = 638 type = "critical";
625 }; 639 };
626 }; 640 };
627 }; 641 };
628 642
629 cpu7-thermal { 643 cpu7-thermal {
630 polling-delay-passive 644 polling-delay-passive = <250>;
>> 645 polling-delay = <1000>;
631 646
632 thermal-sensors = <&ts 647 thermal-sensors = <&tsens0 10>;
633 648
634 trips { 649 trips {
635 cpu7_alert0: t !! 650 cpu7_alert0: trip-point@0 {
636 temper 651 temperature = <75000>;
637 hyster 652 hysteresis = <2000>;
638 type = 653 type = "passive";
639 }; 654 };
640 655
641 cpu7_crit: cpu !! 656 cpu7_crit: cpu_crit {
642 temper 657 temperature = <110000>;
643 hyster 658 hysteresis = <2000>;
644 type = 659 type = "critical";
645 }; 660 };
646 }; 661 };
647 }; 662 };
648 663
649 gpu-bottom-thermal { !! 664 gpu-thermal-bottom {
650 polling-delay-passive 665 polling-delay-passive = <250>;
>> 666 polling-delay = <1000>;
651 667
652 thermal-sensors = <&ts 668 thermal-sensors = <&tsens0 12>;
653 669
654 trips { 670 trips {
655 gpu1_alert0: t !! 671 gpu1_alert0: trip-point@0 {
656 temper 672 temperature = <90000>;
657 hyster 673 hysteresis = <2000>;
658 type = 674 type = "hot";
659 }; 675 };
660 }; 676 };
661 }; 677 };
662 678
663 gpu-top-thermal { !! 679 gpu-thermal-top {
664 polling-delay-passive 680 polling-delay-passive = <250>;
>> 681 polling-delay = <1000>;
665 682
666 thermal-sensors = <&ts 683 thermal-sensors = <&tsens0 13>;
667 684
668 trips { 685 trips {
669 gpu2_alert0: t !! 686 gpu2_alert0: trip-point@0 {
670 temper 687 temperature = <90000>;
671 hyster 688 hysteresis = <2000>;
672 type = 689 type = "hot";
673 }; 690 };
674 }; 691 };
675 }; 692 };
676 693
677 clust0-mhm-thermal { 694 clust0-mhm-thermal {
678 polling-delay-passive 695 polling-delay-passive = <250>;
>> 696 polling-delay = <1000>;
679 697
680 thermal-sensors = <&ts 698 thermal-sensors = <&tsens0 5>;
681 699
682 trips { 700 trips {
683 cluster0_mhm_a !! 701 cluster0_mhm_alert0: trip-point@0 {
684 temper 702 temperature = <90000>;
685 hyster 703 hysteresis = <2000>;
686 type = 704 type = "hot";
687 }; 705 };
688 }; 706 };
689 }; 707 };
690 708
691 clust1-mhm-thermal { 709 clust1-mhm-thermal {
692 polling-delay-passive 710 polling-delay-passive = <250>;
>> 711 polling-delay = <1000>;
693 712
694 thermal-sensors = <&ts 713 thermal-sensors = <&tsens0 6>;
695 714
696 trips { 715 trips {
697 cluster1_mhm_a !! 716 cluster1_mhm_alert0: trip-point@0 {
698 temper 717 temperature = <90000>;
699 hyster 718 hysteresis = <2000>;
700 type = 719 type = "hot";
701 }; 720 };
702 }; 721 };
703 }; 722 };
704 723
705 cluster1-l2-thermal { 724 cluster1-l2-thermal {
706 polling-delay-passive 725 polling-delay-passive = <250>;
>> 726 polling-delay = <1000>;
707 727
708 thermal-sensors = <&ts 728 thermal-sensors = <&tsens0 11>;
709 729
710 trips { 730 trips {
711 cluster1_l2_al !! 731 cluster1_l2_alert0: trip-point@0 {
712 temper 732 temperature = <90000>;
713 hyster 733 hysteresis = <2000>;
714 type = 734 type = "hot";
715 }; 735 };
716 }; 736 };
717 }; 737 };
718 738
719 modem-thermal { 739 modem-thermal {
720 polling-delay-passive 740 polling-delay-passive = <250>;
>> 741 polling-delay = <1000>;
721 742
722 thermal-sensors = <&ts 743 thermal-sensors = <&tsens1 1>;
723 744
724 trips { 745 trips {
725 modem_alert0: !! 746 modem_alert0: trip-point@0 {
726 temper 747 temperature = <90000>;
727 hyster 748 hysteresis = <2000>;
728 type = 749 type = "hot";
729 }; 750 };
730 }; 751 };
731 }; 752 };
732 753
733 mem-thermal { 754 mem-thermal {
734 polling-delay-passive 755 polling-delay-passive = <250>;
>> 756 polling-delay = <1000>;
735 757
736 thermal-sensors = <&ts 758 thermal-sensors = <&tsens1 2>;
737 759
738 trips { 760 trips {
739 mem_alert0: tr !! 761 mem_alert0: trip-point@0 {
740 temper 762 temperature = <90000>;
741 hyster 763 hysteresis = <2000>;
742 type = 764 type = "hot";
743 }; 765 };
744 }; 766 };
745 }; 767 };
746 768
747 wlan-thermal { 769 wlan-thermal {
748 polling-delay-passive 770 polling-delay-passive = <250>;
>> 771 polling-delay = <1000>;
749 772
750 thermal-sensors = <&ts 773 thermal-sensors = <&tsens1 3>;
751 774
752 trips { 775 trips {
753 wlan_alert0: t !! 776 wlan_alert0: trip-point@0 {
754 temper 777 temperature = <90000>;
755 hyster 778 hysteresis = <2000>;
756 type = 779 type = "hot";
757 }; 780 };
758 }; 781 };
759 }; 782 };
760 783
761 q6-dsp-thermal { 784 q6-dsp-thermal {
762 polling-delay-passive 785 polling-delay-passive = <250>;
>> 786 polling-delay = <1000>;
763 787
764 thermal-sensors = <&ts 788 thermal-sensors = <&tsens1 4>;
765 789
766 trips { 790 trips {
767 q6_dsp_alert0: !! 791 q6_dsp_alert0: trip-point@0 {
768 temper 792 temperature = <90000>;
769 hyster 793 hysteresis = <2000>;
770 type = 794 type = "hot";
771 }; 795 };
772 }; 796 };
773 }; 797 };
774 798
775 camera-thermal { 799 camera-thermal {
776 polling-delay-passive 800 polling-delay-passive = <250>;
>> 801 polling-delay = <1000>;
777 802
778 thermal-sensors = <&ts 803 thermal-sensors = <&tsens1 5>;
779 804
780 trips { 805 trips {
781 camera_alert0: !! 806 camera_alert0: trip-point@0 {
782 temper 807 temperature = <90000>;
783 hyster 808 hysteresis = <2000>;
784 type = 809 type = "hot";
785 }; 810 };
786 }; 811 };
787 }; 812 };
788 813
789 multimedia-thermal { 814 multimedia-thermal {
790 polling-delay-passive 815 polling-delay-passive = <250>;
>> 816 polling-delay = <1000>;
791 817
792 thermal-sensors = <&ts 818 thermal-sensors = <&tsens1 6>;
793 819
794 trips { 820 trips {
795 multimedia_ale !! 821 multimedia_alert0: trip-point@0 {
796 temper 822 temperature = <90000>;
797 hyster 823 hysteresis = <2000>;
798 type = 824 type = "hot";
799 }; 825 };
800 }; 826 };
801 }; 827 };
802 }; 828 };
803 829
804 timer { 830 timer {
805 compatible = "arm,armv8-timer" 831 compatible = "arm,armv8-timer";
806 interrupts = <GIC_PPI 1 IRQ_TY 832 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
807 <GIC_PPI 2 IRQ_TY 833 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
808 <GIC_PPI 3 IRQ_TY 834 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
809 <GIC_PPI 0 IRQ_TY 835 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
810 }; 836 };
811 837
812 soc: soc@0 { !! 838 soc: soc {
813 #address-cells = <1>; 839 #address-cells = <1>;
814 #size-cells = <1>; 840 #size-cells = <1>;
815 ranges = <0 0 0 0xffffffff>; 841 ranges = <0 0 0 0xffffffff>;
816 compatible = "simple-bus"; 842 compatible = "simple-bus";
817 843
818 gcc: clock-controller@100000 { 844 gcc: clock-controller@100000 {
819 compatible = "qcom,gcc 845 compatible = "qcom,gcc-msm8998";
820 #clock-cells = <1>; 846 #clock-cells = <1>;
821 #reset-cells = <1>; 847 #reset-cells = <1>;
822 #power-domain-cells = 848 #power-domain-cells = <1>;
823 reg = <0x00100000 0xb0 849 reg = <0x00100000 0xb0000>;
824 <<
825 clock-names = "xo", "s <<
826 clocks = <&rpmcc RPM_S <<
827 <<
828 /* <<
829 * The hypervisor typi <<
830 * reside as read-only <<
831 * these clocks on a d <<
832 * enabled but unused <<
833 * to reboot. <<
834 * In light of that, w <<
835 * as protected. The b <<
836 * list of protected c <<
837 * desired for the HLO <<
838 */ <<
839 protected-clocks = <AG <<
840 <SS <<
841 <SS <<
842 }; 850 };
843 851
844 rpm_msg_ram: sram@778000 { !! 852 rpm_msg_ram: memory@778000 {
845 compatible = "qcom,rpm 853 compatible = "qcom,rpm-msg-ram";
846 reg = <0x00778000 0x70 854 reg = <0x00778000 0x7000>;
847 }; 855 };
848 856
849 qfprom: qfprom@784000 { !! 857 qfprom: qfprom@780000 {
850 compatible = "qcom,msm !! 858 compatible = "qcom,qfprom";
851 reg = <0x00784000 0x62 !! 859 reg = <0x00780000 0x621c>;
852 #address-cells = <1>; 860 #address-cells = <1>;
853 #size-cells = <1>; 861 #size-cells = <1>;
854 862
855 qusb2_hstx_trim: hstx- !! 863 qusb2_hstx_trim: hstx-trim@423a {
856 reg = <0x23a 0 !! 864 reg = <0x423a 0x1>;
857 bits = <0 4>; 865 bits = <0 4>;
858 }; 866 };
859 }; 867 };
860 868
861 tsens0: thermal@10ab000 { 869 tsens0: thermal@10ab000 {
862 compatible = "qcom,msm 870 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
863 reg = <0x010ab000 0x10 871 reg = <0x010ab000 0x1000>, /* TM */
864 <0x010aa000 0x10 872 <0x010aa000 0x1000>; /* SROT */
865 #qcom,sensors = <14>; 873 #qcom,sensors = <14>;
866 interrupts = <GIC_SPI 874 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
867 <GIC_SPI 875 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
868 interrupt-names = "upl 876 interrupt-names = "uplow", "critical";
869 #thermal-sensor-cells 877 #thermal-sensor-cells = <1>;
870 }; 878 };
871 879
872 tsens1: thermal@10ae000 { 880 tsens1: thermal@10ae000 {
873 compatible = "qcom,msm 881 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
874 reg = <0x010ae000 0x10 882 reg = <0x010ae000 0x1000>, /* TM */
875 <0x010ad000 0x10 883 <0x010ad000 0x1000>; /* SROT */
876 #qcom,sensors = <8>; 884 #qcom,sensors = <8>;
877 interrupts = <GIC_SPI 885 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
878 <GIC_SPI 886 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
879 interrupt-names = "upl 887 interrupt-names = "uplow", "critical";
880 #thermal-sensor-cells 888 #thermal-sensor-cells = <1>;
881 }; 889 };
882 890
883 anoc1_smmu: iommu@1680000 { 891 anoc1_smmu: iommu@1680000 {
884 compatible = "qcom,msm 892 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
885 reg = <0x01680000 0x10 893 reg = <0x01680000 0x10000>;
886 #iommu-cells = <1>; 894 #iommu-cells = <1>;
887 895
888 #global-interrupts = < 896 #global-interrupts = <0>;
889 interrupts = 897 interrupts =
890 <GIC_SPI 364 I 898 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
891 <GIC_SPI 365 I 899 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
892 <GIC_SPI 366 I 900 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
893 <GIC_SPI 367 I 901 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
894 <GIC_SPI 368 I 902 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
895 <GIC_SPI 369 I 903 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>;
896 }; 904 };
897 905
898 anoc2_smmu: iommu@16c0000 { 906 anoc2_smmu: iommu@16c0000 {
899 compatible = "qcom,msm 907 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
900 reg = <0x016c0000 0x40 908 reg = <0x016c0000 0x40000>;
901 #iommu-cells = <1>; 909 #iommu-cells = <1>;
902 910
903 #global-interrupts = < 911 #global-interrupts = <0>;
904 interrupts = 912 interrupts =
905 <GIC_SPI 373 I 913 <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>,
906 <GIC_SPI 374 I 914 <GIC_SPI 374 IRQ_TYPE_EDGE_RISING>,
907 <GIC_SPI 375 I 915 <GIC_SPI 375 IRQ_TYPE_EDGE_RISING>,
908 <GIC_SPI 376 I 916 <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>,
909 <GIC_SPI 377 I 917 <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>,
910 <GIC_SPI 378 I 918 <GIC_SPI 378 IRQ_TYPE_EDGE_RISING>,
911 <GIC_SPI 462 I 919 <GIC_SPI 462 IRQ_TYPE_EDGE_RISING>,
912 <GIC_SPI 463 I 920 <GIC_SPI 463 IRQ_TYPE_EDGE_RISING>,
913 <GIC_SPI 464 I 921 <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
914 <GIC_SPI 465 I 922 <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>;
915 }; 923 };
916 924
917 pcie0: pcie@1c00000 { !! 925 pcie0: pci@1c00000 {
918 compatible = "qcom,pci !! 926 compatible = "qcom,pcie-msm8996";
919 reg = <0x01c00000 0x20 !! 927 reg = <0x01c00000 0x2000>,
920 <0x1b000000 0xf1 !! 928 <0x1b000000 0xf1d>,
921 <0x1b000f20 0xa8 !! 929 <0x1b000f20 0xa8>,
922 <0x1b100000 0x10 !! 930 <0x1b100000 0x100000>;
923 reg-names = "parf", "d 931 reg-names = "parf", "dbi", "elbi", "config";
924 device_type = "pci"; 932 device_type = "pci";
925 linux,pci-domain = <0> 933 linux,pci-domain = <0>;
926 bus-range = <0x00 0xff 934 bus-range = <0x00 0xff>;
927 #address-cells = <3>; 935 #address-cells = <3>;
928 #size-cells = <2>; 936 #size-cells = <2>;
929 num-lanes = <1>; 937 num-lanes = <1>;
930 phys = <&pcie_phy>; !! 938 phys = <&pciephy>;
931 phy-names = "pciephy"; 939 phy-names = "pciephy";
932 status = "disabled"; <<
933 940
934 ranges = <0x01000000 0 !! 941 ranges = <0x01000000 0x0 0x1b200000 0x1b200000 0x0 0x100000>,
935 <0x02000000 0 942 <0x02000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>;
936 943
937 #interrupt-cells = <1> 944 #interrupt-cells = <1>;
938 interrupts = <GIC_SPI 945 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
939 interrupt-names = "msi 946 interrupt-names = "msi";
940 interrupt-map-mask = < 947 interrupt-map-mask = <0 0 0 0x7>;
941 interrupt-map = <0 0 0 !! 948 interrupt-map = <0 0 0 1 &intc 0 135 IRQ_TYPE_LEVEL_HIGH>,
942 <0 0 0 !! 949 <0 0 0 2 &intc 0 136 IRQ_TYPE_LEVEL_HIGH>,
943 <0 0 0 !! 950 <0 0 0 3 &intc 0 138 IRQ_TYPE_LEVEL_HIGH>,
944 <0 0 0 !! 951 <0 0 0 4 &intc 0 139 IRQ_TYPE_LEVEL_HIGH>;
945 952
946 clocks = <&gcc GCC_PCI 953 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
947 <&gcc GCC_PCI <<
948 <&gcc GCC_PCI <<
949 <&gcc GCC_PCI 954 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
950 <&gcc GCC_PCI !! 955 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
951 clock-names = "pipe", !! 956 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
>> 957 <&gcc GCC_PCIE_0_AUX_CLK>;
>> 958 clock-names = "pipe", "bus_master", "bus_slave", "cfg", "aux";
952 959
953 power-domains = <&gcc 960 power-domains = <&gcc PCIE_0_GDSC>;
954 iommu-map = <0x100 &an 961 iommu-map = <0x100 &anoc1_smmu 0x1480 1>;
955 perst-gpios = <&tlmm 3 962 perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
956 <<
957 pcie@0 { <<
958 device_type = <<
959 reg = <0x0 0x0 <<
960 bus-range = <0 <<
961 <<
962 #address-cells <<
963 #size-cells = <<
964 ranges; <<
965 }; <<
966 }; 963 };
967 964
968 pcie_phy: phy@1c06000 { !! 965 phy@1c06000 {
969 compatible = "qcom,msm 966 compatible = "qcom,msm8998-qmp-pcie-phy";
970 reg = <0x01c06000 0x10 !! 967 reg = <0x01c06000 0x18c>;
971 status = "disabled"; !! 968 #address-cells = <1>;
>> 969 #size-cells = <1>;
>> 970 ranges;
972 971
973 clocks = <&gcc GCC_PCI 972 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
974 <&gcc GCC_PCI 973 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
975 <&gcc GCC_PCI !! 974 <&gcc GCC_PCIE_CLKREF_CLK>;
976 <&gcc GCC_PCI !! 975 clock-names = "aux", "cfg_ahb", "ref";
977 clock-names = "aux", <<
978 "cfg_ahb <<
979 "ref", <<
980 "pipe"; <<
981 <<
982 clock-output-names = " <<
983 #clock-cells = <0>; <<
984 <<
985 #phy-cells = <0>; <<
986 976
987 resets = <&gcc GCC_PCI 977 resets = <&gcc GCC_PCIE_0_PHY_BCR>, <&gcc GCC_PCIE_PHY_BCR>;
988 reset-names = "phy", " 978 reset-names = "phy", "common";
989 979
990 vdda-phy-supply = <&vr 980 vdda-phy-supply = <&vreg_l1a_0p875>;
991 vdda-pll-supply = <&vr 981 vdda-pll-supply = <&vreg_l2a_1p2>;
>> 982
>> 983 pciephy: lane@1c06800 {
>> 984 reg = <0x01c06200 0x128>, <0x01c06400 0x1fc>, <0x01c06800 0x20c>;
>> 985 #phy-cells = <0>;
>> 986
>> 987 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
>> 988 clock-names = "pipe0";
>> 989 clock-output-names = "pcie_0_pipe_clk_src";
>> 990 #clock-cells = <0>;
>> 991 };
992 }; 992 };
993 993
994 ufshc: ufshc@1da4000 { 994 ufshc: ufshc@1da4000 {
995 compatible = "qcom,msm 995 compatible = "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
996 reg = <0x01da4000 0x25 996 reg = <0x01da4000 0x2500>;
997 interrupts = <GIC_SPI 997 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
998 phys = <&ufsphy>; !! 998 phys = <&ufsphy_lanes>;
999 phy-names = "ufsphy"; 999 phy-names = "ufsphy";
1000 lanes-per-direction = 1000 lanes-per-direction = <2>;
1001 power-domains = <&gcc 1001 power-domains = <&gcc UFS_GDSC>;
1002 status = "disabled"; <<
1003 #reset-cells = <1>; 1002 #reset-cells = <1>;
1004 1003
1005 clock-names = 1004 clock-names =
1006 "core_clk", 1005 "core_clk",
1007 "bus_aggr_clk 1006 "bus_aggr_clk",
1008 "iface_clk", 1007 "iface_clk",
1009 "core_clk_uni 1008 "core_clk_unipro",
1010 "ref_clk", 1009 "ref_clk",
1011 "tx_lane0_syn 1010 "tx_lane0_sync_clk",
1012 "rx_lane0_syn 1011 "rx_lane0_sync_clk",
1013 "rx_lane1_syn 1012 "rx_lane1_sync_clk";
1014 clocks = 1013 clocks =
1015 <&gcc GCC_UFS 1014 <&gcc GCC_UFS_AXI_CLK>,
1016 <&gcc GCC_AGG 1015 <&gcc GCC_AGGRE1_UFS_AXI_CLK>,
1017 <&gcc GCC_UFS 1016 <&gcc GCC_UFS_AHB_CLK>,
1018 <&gcc GCC_UFS 1017 <&gcc GCC_UFS_UNIPRO_CORE_CLK>,
1019 <&rpmcc RPM_S 1018 <&rpmcc RPM_SMD_LN_BB_CLK1>,
1020 <&gcc GCC_UFS 1019 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
1021 <&gcc GCC_UFS 1020 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>,
1022 <&gcc GCC_UFS 1021 <&gcc GCC_UFS_RX_SYMBOL_1_CLK>;
1023 freq-table-hz = 1022 freq-table-hz =
1024 <50000000 200 1023 <50000000 200000000>,
1025 <0 0>, 1024 <0 0>,
1026 <0 0>, 1025 <0 0>,
1027 <37500000 150 1026 <37500000 150000000>,
1028 <0 0>, 1027 <0 0>,
1029 <0 0>, 1028 <0 0>,
1030 <0 0>, 1029 <0 0>,
1031 <0 0>; 1030 <0 0>;
1032 1031
1033 resets = <&gcc GCC_UF 1032 resets = <&gcc GCC_UFS_BCR>;
1034 reset-names = "rst"; 1033 reset-names = "rst";
1035 }; 1034 };
1036 1035
1037 ufsphy: phy@1da7000 { 1036 ufsphy: phy@1da7000 {
1038 compatible = "qcom,ms 1037 compatible = "qcom,msm8998-qmp-ufs-phy";
1039 reg = <0x01da7000 0x1 !! 1038 reg = <0x01da7000 0x18c>;
>> 1039 #address-cells = <1>;
>> 1040 #size-cells = <1>;
>> 1041 ranges;
1040 1042
1041 clocks = <&rpmcc RPM_ !! 1043 clock-names =
1042 <&gcc GCC_UF !! 1044 "ref",
1043 <&gcc GCC_UF !! 1045 "ref_aux";
1044 clock-names = "ref", !! 1046 clocks =
1045 "ref_au !! 1047 <&gcc GCC_UFS_CLKREF_CLK>,
1046 "qref"; !! 1048 <&gcc GCC_UFS_PHY_AUX_CLK>;
1047 1049
1048 reset-names = "ufsphy 1050 reset-names = "ufsphy";
1049 resets = <&ufshc 0>; 1051 resets = <&ufshc 0>;
1050 1052
1051 #phy-cells = <0>; !! 1053 ufsphy_lanes: lanes@1da7400 {
1052 status = "disabled"; !! 1054 reg = <0x01da7400 0x128>,
1053 }; !! 1055 <0x01da7600 0x1fc>,
1054 !! 1056 <0x01da7c00 0x1dc>,
1055 tcsr_mutex: hwlock@1f40000 { !! 1057 <0x01da7800 0x128>,
1056 compatible = "qcom,tc !! 1058 <0x01da7a00 0x1fc>;
1057 reg = <0x01f40000 0x2 !! 1059 #phy-cells = <0>;
1058 #hwlock-cells = <1>; !! 1060 };
1059 }; <<
1060 <<
1061 tcsr_regs_1: syscon@1f60000 { <<
1062 compatible = "qcom,ms <<
1063 reg = <0x01f60000 0x2 <<
1064 }; 1061 };
1065 1062
1066 tcsr_regs_2: syscon@1fc0000 { !! 1063 tcsr_mutex_regs: syscon@1f40000 {
1067 compatible = "qcom,ms !! 1064 compatible = "syscon";
1068 reg = <0x01fc0000 0x2 !! 1065 reg = <0x01f40000 0x40000>;
1069 }; 1066 };
1070 1067
1071 tlmm: pinctrl@3400000 { 1068 tlmm: pinctrl@3400000 {
1072 compatible = "qcom,ms 1069 compatible = "qcom,msm8998-pinctrl";
1073 reg = <0x03400000 0xc 1070 reg = <0x03400000 0xc00000>;
1074 interrupts = <GIC_SPI 1071 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1075 gpio-ranges = <&tlmm <<
1076 gpio-controller; 1072 gpio-controller;
1077 #gpio-cells = <2>; !! 1073 #gpio-cells = <0x2>;
1078 interrupt-controller; 1074 interrupt-controller;
1079 #interrupt-cells = <2 !! 1075 #interrupt-cells = <0x2>;
1080 <<
1081 sdc2_on: sdc2-on-stat <<
1082 clk-pins { <<
1083 pins <<
1084 drive <<
1085 bias- <<
1086 }; <<
1087 <<
1088 cmd-pins { <<
1089 pins <<
1090 drive <<
1091 bias- <<
1092 }; <<
1093 <<
1094 data-pins { <<
1095 pins <<
1096 drive <<
1097 bias- <<
1098 }; <<
1099 }; <<
1100 <<
1101 sdc2_off: sdc2-off-st <<
1102 clk-pins { <<
1103 pins <<
1104 drive <<
1105 bias- <<
1106 }; <<
1107 <<
1108 cmd-pins { <<
1109 pins <<
1110 drive <<
1111 bias- <<
1112 }; <<
1113 <<
1114 data-pins { <<
1115 pins <<
1116 drive <<
1117 bias- <<
1118 }; <<
1119 }; <<
1120 <<
1121 sdc2_cd: sdc2-cd-stat <<
1122 pins = "gpio9 <<
1123 function = "g <<
1124 bias-pull-up; <<
1125 drive-strengt <<
1126 }; <<
1127 <<
1128 blsp1_uart3_on: blsp1 <<
1129 tx-pins { <<
1130 pins <<
1131 funct <<
1132 drive <<
1133 bias- <<
1134 }; <<
1135 <<
1136 rx-pins { <<
1137 pins <<
1138 funct <<
1139 drive <<
1140 bias- <<
1141 }; <<
1142 <<
1143 cts-pins { <<
1144 pins <<
1145 funct <<
1146 drive <<
1147 bias- <<
1148 }; <<
1149 <<
1150 rfr-pins { <<
1151 pins <<
1152 funct <<
1153 drive <<
1154 bias- <<
1155 }; <<
1156 }; <<
1157 <<
1158 blsp1_i2c1_default: b <<
1159 pins = "gpio2 <<
1160 function = "b <<
1161 drive-strengt <<
1162 bias-disable; <<
1163 }; <<
1164 <<
1165 blsp1_i2c1_sleep: bls <<
1166 pins = "gpio2 <<
1167 function = "b <<
1168 drive-strengt <<
1169 bias-pull-up; <<
1170 }; <<
1171 <<
1172 blsp1_i2c2_default: b <<
1173 pins = "gpio3 <<
1174 function = "b <<
1175 drive-strengt <<
1176 bias-disable; <<
1177 }; <<
1178 <<
1179 blsp1_i2c2_sleep: bls <<
1180 pins = "gpio3 <<
1181 function = "b <<
1182 drive-strengt <<
1183 bias-pull-up; <<
1184 }; <<
1185 <<
1186 blsp1_i2c3_default: b <<
1187 pins = "gpio4 <<
1188 function = "b <<
1189 drive-strengt <<
1190 bias-disable; <<
1191 }; <<
1192 <<
1193 blsp1_i2c3_sleep: bls <<
1194 pins = "gpio4 <<
1195 function = "b <<
1196 drive-strengt <<
1197 bias-pull-up; <<
1198 }; <<
1199 <<
1200 blsp1_i2c4_default: b <<
1201 pins = "gpio1 <<
1202 function = "b <<
1203 drive-strengt <<
1204 bias-disable; <<
1205 }; <<
1206 <<
1207 blsp1_i2c4_sleep: bls <<
1208 pins = "gpio1 <<
1209 function = "b <<
1210 drive-strengt <<
1211 bias-pull-up; <<
1212 }; <<
1213 <<
1214 blsp1_i2c5_default: b <<
1215 pins = "gpio8 <<
1216 function = "b <<
1217 drive-strengt <<
1218 bias-disable; <<
1219 }; <<
1220 <<
1221 blsp1_i2c5_sleep: bls <<
1222 pins = "gpio8 <<
1223 function = "b <<
1224 drive-strengt <<
1225 bias-pull-up; <<
1226 }; <<
1227 <<
1228 blsp1_i2c6_default: b <<
1229 pins = "gpio4 <<
1230 function = "b <<
1231 drive-strengt <<
1232 bias-disable; <<
1233 }; <<
1234 <<
1235 blsp1_i2c6_sleep: bls <<
1236 pins = "gpio4 <<
1237 function = "b <<
1238 drive-strengt <<
1239 bias-pull-up; <<
1240 }; <<
1241 <<
1242 blsp1_spi_b_default: <<
1243 pins = "gpio2 <<
1244 function = "b <<
1245 drive-strengt <<
1246 bias-disable; <<
1247 }; <<
1248 <<
1249 blsp1_spi1_default: b <<
1250 pins = "gpio0 <<
1251 function = "b <<
1252 drive-strengt <<
1253 bias-disable; <<
1254 }; <<
1255 <<
1256 blsp1_spi2_default: b <<
1257 pins = "gpio3 <<
1258 function = "b <<
1259 drive-strengt <<
1260 bias-disable; <<
1261 }; <<
1262 <<
1263 blsp1_spi3_default: b <<
1264 pins = "gpio4 <<
1265 function = "b <<
1266 drive-strengt <<
1267 bias-disable; <<
1268 }; <<
1269 <<
1270 blsp1_spi4_default: b <<
1271 pins = "gpio8 <<
1272 function = "b <<
1273 drive-strengt <<
1274 bias-disable; <<
1275 }; <<
1276 <<
1277 blsp1_spi5_default: b <<
1278 pins = "gpio8 <<
1279 function = "b <<
1280 drive-strengt <<
1281 bias-disable; <<
1282 }; <<
1283 <<
1284 blsp1_spi6_default: b <<
1285 pins = "gpio4 <<
1286 function = "b <<
1287 drive-strengt <<
1288 bias-disable; <<
1289 }; <<
1290 <<
1291 <<
1292 /* 6 interfaces per Q <<
1293 blsp2_i2c1_default: b <<
1294 pins = "gpio5 <<
1295 function = "b <<
1296 drive-strengt <<
1297 bias-disable; <<
1298 }; <<
1299 <<
1300 blsp2_i2c1_sleep: bls <<
1301 pins = "gpio5 <<
1302 function = "b <<
1303 drive-strengt <<
1304 bias-pull-up; <<
1305 }; <<
1306 <<
1307 blsp2_i2c2_default: b <<
1308 pins = "gpio6 <<
1309 function = "b <<
1310 drive-strengt <<
1311 bias-disable; <<
1312 }; <<
1313 <<
1314 blsp2_i2c2_sleep: bls <<
1315 pins = "gpio6 <<
1316 function = "b <<
1317 drive-strengt <<
1318 bias-pull-up; <<
1319 }; <<
1320 <<
1321 blsp2_i2c3_default: b <<
1322 pins = "gpio5 <<
1323 function = "b <<
1324 drive-strengt <<
1325 bias-disable; <<
1326 }; <<
1327 <<
1328 blsp2_i2c3_sleep: bls <<
1329 pins = "gpio5 <<
1330 function = "b <<
1331 drive-strengt <<
1332 bias-pull-up; <<
1333 }; <<
1334 <<
1335 blsp2_i2c4_default: b <<
1336 pins = "gpio6 <<
1337 function = "b <<
1338 drive-strengt <<
1339 bias-disable; <<
1340 }; <<
1341 <<
1342 blsp2_i2c4_sleep: bls <<
1343 pins = "gpio6 <<
1344 function = "b <<
1345 drive-strengt <<
1346 bias-pull-up; <<
1347 }; <<
1348 <<
1349 blsp2_i2c5_default: b <<
1350 pins = "gpio6 <<
1351 function = "b <<
1352 drive-strengt <<
1353 bias-disable; <<
1354 }; <<
1355 <<
1356 blsp2_i2c5_sleep: bls <<
1357 pins = "gpio6 <<
1358 function = "b <<
1359 drive-strengt <<
1360 bias-pull-up; <<
1361 }; <<
1362 <<
1363 blsp2_i2c6_default: b <<
1364 pins = "gpio8 <<
1365 function = "b <<
1366 drive-strengt <<
1367 bias-disable; <<
1368 }; <<
1369 <<
1370 blsp2_i2c6_sleep: bls <<
1371 pins = "gpio8 <<
1372 function = "b <<
1373 drive-strengt <<
1374 bias-pull-up; <<
1375 }; <<
1376 <<
1377 blsp2_spi1_default: b <<
1378 pins = "gpio5 <<
1379 function = "b <<
1380 drive-strengt <<
1381 bias-disable; <<
1382 }; <<
1383 <<
1384 blsp2_spi2_default: b <<
1385 pins = "gpio4 <<
1386 function = "b <<
1387 drive-strengt <<
1388 bias-disable; <<
1389 }; <<
1390 <<
1391 blsp2_spi3_default: b <<
1392 pins = "gpio4 <<
1393 function = "b <<
1394 drive-strengt <<
1395 bias-disable; <<
1396 }; <<
1397 <<
1398 blsp2_spi4_default: b <<
1399 pins = "gpio6 <<
1400 function = "b <<
1401 drive-strengt <<
1402 bias-disable; <<
1403 }; <<
1404 <<
1405 blsp2_spi5_default: b <<
1406 pins = "gpio5 <<
1407 function = "b <<
1408 drive-strengt <<
1409 bias-disable; <<
1410 }; <<
1411 <<
1412 blsp2_spi6_default: b <<
1413 pins = "gpio8 <<
1414 function = "b <<
1415 drive-strengt <<
1416 bias-disable; <<
1417 }; <<
1418 }; 1076 };
1419 1077
1420 remoteproc_mss: remoteproc@40 1078 remoteproc_mss: remoteproc@4080000 {
1421 compatible = "qcom,ms 1079 compatible = "qcom,msm8998-mss-pil";
1422 reg = <0x04080000 0x1 1080 reg = <0x04080000 0x100>, <0x04180000 0x20>;
1423 reg-names = "qdsp6", 1081 reg-names = "qdsp6", "rmb";
1424 1082
1425 interrupts-extended = 1083 interrupts-extended =
1426 <&intc GIC_SP 1084 <&intc GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
1427 <&modem_smp2p 1085 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1428 <&modem_smp2p 1086 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1429 <&modem_smp2p 1087 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1430 <&modem_smp2p 1088 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
1431 <&modem_smp2p 1089 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
1432 interrupt-names = "wd 1090 interrupt-names = "wdog", "fatal", "ready",
1433 "ha 1091 "handover", "stop-ack",
1434 "sh 1092 "shutdown-ack";
1435 1093
1436 clocks = <&gcc GCC_MS 1094 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
1437 <&gcc GCC_BI 1095 <&gcc GCC_BIMC_MSS_Q6_AXI_CLK>,
1438 <&gcc GCC_BO 1096 <&gcc GCC_BOOT_ROM_AHB_CLK>,
1439 <&gcc GCC_MS 1097 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
1440 <&gcc GCC_MS 1098 <&gcc GCC_MSS_SNOC_AXI_CLK>,
1441 <&gcc GCC_MS 1099 <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>,
1442 <&rpmcc RPM_ 1100 <&rpmcc RPM_SMD_QDSS_CLK>,
1443 <&rpmcc RPM_ 1101 <&rpmcc RPM_SMD_XO_CLK_SRC>;
1444 clock-names = "iface" 1102 clock-names = "iface", "bus", "mem", "gpll0_mss",
1445 "snoc_a 1103 "snoc_axi", "mnoc_axi", "qdss", "xo";
1446 1104
1447 qcom,smem-states = <& 1105 qcom,smem-states = <&modem_smp2p_out 0>;
1448 qcom,smem-state-names 1106 qcom,smem-state-names = "stop";
1449 1107
1450 resets = <&gcc GCC_MS 1108 resets = <&gcc GCC_MSS_RESTART>;
1451 reset-names = "mss_re 1109 reset-names = "mss_restart";
1452 1110
1453 qcom,halt-regs = <&tc !! 1111 qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
1454 1112
1455 power-domains = <&rpm 1113 power-domains = <&rpmpd MSM8998_VDDCX>,
1456 <&rpm 1114 <&rpmpd MSM8998_VDDMX>;
1457 power-domain-names = 1115 power-domain-names = "cx", "mx";
1458 1116
1459 status = "disabled"; <<
1460 <<
1461 mba { 1117 mba {
1462 memory-region 1118 memory-region = <&mba_mem>;
1463 }; 1119 };
1464 1120
1465 mpss { 1121 mpss {
1466 memory-region 1122 memory-region = <&mpss_mem>;
1467 }; 1123 };
1468 1124
1469 metadata { <<
1470 memory-region <<
1471 }; <<
1472 <<
1473 glink-edge { 1125 glink-edge {
1474 interrupts = 1126 interrupts = <GIC_SPI 452 IRQ_TYPE_EDGE_RISING>;
1475 label = "mode 1127 label = "modem";
1476 qcom,remote-p 1128 qcom,remote-pid = <1>;
1477 mboxes = <&ap 1129 mboxes = <&apcs_glb 15>;
1478 }; 1130 };
1479 }; 1131 };
1480 1132
1481 adreno_gpu: gpu@5000000 { <<
1482 compatible = "qcom,ad <<
1483 reg = <0x05000000 0x4 <<
1484 reg-names = "kgsl_3d0 <<
1485 <<
1486 clocks = <&gcc GCC_GP <<
1487 <&gpucc RBBMT <<
1488 <&gcc GCC_BIM <<
1489 <&gcc GCC_GPU <<
1490 <&gpucc RBCPR <<
1491 <&gpucc GFX3D <<
1492 clock-names = "iface" <<
1493 "rbbmtimer", <<
1494 "mem", <<
1495 "mem_iface", <<
1496 "rbcpr", <<
1497 "core"; <<
1498 <<
1499 interrupts = <GIC_SPI <<
1500 iommus = <&adreno_smm <<
1501 operating-points-v2 = <<
1502 power-domains = <&rpm <<
1503 status = "disabled"; <<
1504 <<
1505 gpu_opp_table: opp-ta <<
1506 compatible = <<
1507 opp-710000097 <<
1508 opp-h <<
1509 opp-l <<
1510 opp-s <<
1511 }; <<
1512 <<
1513 opp-670000048 <<
1514 opp-h <<
1515 opp-l <<
1516 opp-s <<
1517 }; <<
1518 <<
1519 opp-596000097 <<
1520 opp-h <<
1521 opp-l <<
1522 opp-s <<
1523 }; <<
1524 <<
1525 opp-515000097 <<
1526 opp-h <<
1527 opp-l <<
1528 opp-s <<
1529 }; <<
1530 <<
1531 opp-414000000 <<
1532 opp-h <<
1533 opp-l <<
1534 opp-s <<
1535 }; <<
1536 <<
1537 opp-342000000 <<
1538 opp-h <<
1539 opp-l <<
1540 opp-s <<
1541 }; <<
1542 <<
1543 opp-257000000 <<
1544 opp-h <<
1545 opp-l <<
1546 opp-s <<
1547 }; <<
1548 }; <<
1549 }; <<
1550 <<
1551 adreno_smmu: iommu@5040000 { <<
1552 compatible = "qcom,ms <<
1553 reg = <0x05040000 0x1 <<
1554 clocks = <&gcc GCC_GP <<
1555 <&gcc GCC_BI <<
1556 <&gcc GCC_GP <<
1557 clock-names = "iface" <<
1558 <<
1559 #global-interrupts = <<
1560 #iommu-cells = <1>; <<
1561 interrupts = <<
1562 <GIC_SPI 329 <<
1563 <GIC_SPI 330 <<
1564 <GIC_SPI 331 <<
1565 /* <<
1566 * GPU-GX GDSC's pare <<
1567 * GPU-CX for SMMU bu <<
1568 * Contemporarily, we <<
1569 * domain in the Adre <<
1570 * Enable GPU CX/GX G <<
1571 * SoC VDDMX RPM Powe <<
1572 */ <<
1573 power-domains = <&gpu <<
1574 }; <<
1575 <<
1576 gpucc: clock-controller@50650 1133 gpucc: clock-controller@5065000 {
1577 compatible = "qcom,ms 1134 compatible = "qcom,msm8998-gpucc";
1578 #clock-cells = <1>; 1135 #clock-cells = <1>;
1579 #reset-cells = <1>; 1136 #reset-cells = <1>;
1580 #power-domain-cells = 1137 #power-domain-cells = <1>;
1581 reg = <0x05065000 0x9 1138 reg = <0x05065000 0x9000>;
1582 1139
1583 clocks = <&rpmcc RPM_ 1140 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1584 <&gcc GCC_GP !! 1141 <&gcc GPLL0_OUT_MAIN>;
1585 clock-names = "xo", 1142 clock-names = "xo",
1586 "gpll0" 1143 "gpll0";
1587 }; 1144 };
1588 1145
1589 lpass_q6_smmu: iommu@5100000 <<
1590 compatible = "qcom,ms <<
1591 reg = <0x05100000 0x4 <<
1592 clocks = <&gcc HLOS1_ <<
1593 clock-names = "bus"; <<
1594 <<
1595 #global-interrupts = <<
1596 #iommu-cells = <1>; <<
1597 interrupts = <<
1598 <GIC_SPI 226 <<
1599 <GIC_SPI 393 <<
1600 <GIC_SPI 394 <<
1601 <GIC_SPI 395 <<
1602 <GIC_SPI 396 <<
1603 <GIC_SPI 397 <<
1604 <GIC_SPI 398 <<
1605 <GIC_SPI 399 <<
1606 <GIC_SPI 400 <<
1607 <GIC_SPI 401 <<
1608 <GIC_SPI 402 <<
1609 <GIC_SPI 403 <<
1610 <GIC_SPI 137 <<
1611 <<
1612 power-domains = <&gcc <<
1613 status = "disabled"; <<
1614 }; <<
1615 <<
1616 remoteproc_slpi: remoteproc@5 1146 remoteproc_slpi: remoteproc@5800000 {
1617 compatible = "qcom,ms 1147 compatible = "qcom,msm8998-slpi-pas";
1618 reg = <0x05800000 0x4 1148 reg = <0x05800000 0x4040>;
1619 1149
1620 interrupts-extended = 1150 interrupts-extended = <&intc GIC_SPI 390 IRQ_TYPE_EDGE_RISING>,
1621 1151 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1622 1152 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1623 1153 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1624 1154 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1625 interrupt-names = "wd 1155 interrupt-names = "wdog", "fatal", "ready",
1626 "ha 1156 "handover", "stop-ack";
1627 1157
1628 px-supply = <&vreg_lv 1158 px-supply = <&vreg_lvs2a_1p8>;
1629 1159
1630 clocks = <&rpmcc RPM_ !! 1160 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1631 clock-names = "xo"; !! 1161 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
>> 1162 clock-names = "xo", "aggre2";
1632 1163
1633 memory-region = <&slp 1164 memory-region = <&slpi_mem>;
1634 1165
1635 qcom,smem-states = <& 1166 qcom,smem-states = <&slpi_smp2p_out 0>;
1636 qcom,smem-state-names 1167 qcom,smem-state-names = "stop";
1637 1168
1638 power-domains = <&rpm 1169 power-domains = <&rpmpd MSM8998_SSCCX>;
1639 power-domain-names = 1170 power-domain-names = "ssc_cx";
1640 1171
1641 status = "disabled"; 1172 status = "disabled";
1642 1173
1643 glink-edge { 1174 glink-edge {
1644 interrupts = 1175 interrupts = <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>;
1645 label = "dsps 1176 label = "dsps";
1646 qcom,remote-p 1177 qcom,remote-pid = <3>;
1647 mboxes = <&ap 1178 mboxes = <&apcs_glb 27>;
1648 }; 1179 };
1649 }; 1180 };
1650 1181
1651 stm: stm@6002000 { 1182 stm: stm@6002000 {
1652 compatible = "arm,cor 1183 compatible = "arm,coresight-stm", "arm,primecell";
1653 reg = <0x06002000 0x1 1184 reg = <0x06002000 0x1000>,
1654 <0x16280000 0x1 1185 <0x16280000 0x180000>;
1655 reg-names = "stm-base !! 1186 reg-names = "stm-base", "stm-data-base";
1656 status = "disabled"; 1187 status = "disabled";
1657 1188
1658 clocks = <&rpmcc RPM_ 1189 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1659 clock-names = "apb_pc 1190 clock-names = "apb_pclk", "atclk";
1660 1191
1661 out-ports { 1192 out-ports {
1662 port { 1193 port {
1663 stm_o 1194 stm_out: endpoint {
1664 1195 remote-endpoint = <&funnel0_in7>;
1665 }; 1196 };
1666 }; 1197 };
1667 }; 1198 };
1668 }; 1199 };
1669 1200
1670 funnel1: funnel@6041000 { 1201 funnel1: funnel@6041000 {
1671 compatible = "arm,cor 1202 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1672 reg = <0x06041000 0x1 1203 reg = <0x06041000 0x1000>;
1673 status = "disabled"; 1204 status = "disabled";
1674 1205
1675 clocks = <&rpmcc RPM_ 1206 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1676 clock-names = "apb_pc 1207 clock-names = "apb_pclk", "atclk";
1677 1208
1678 out-ports { 1209 out-ports {
1679 port { 1210 port {
1680 funne 1211 funnel0_out: endpoint {
1681 1212 remote-endpoint =
1682 1213 <&merge_funnel_in0>;
1683 }; 1214 };
1684 }; 1215 };
1685 }; 1216 };
1686 1217
1687 in-ports { 1218 in-ports {
1688 #address-cell 1219 #address-cells = <1>;
1689 #size-cells = 1220 #size-cells = <0>;
1690 1221
1691 port@7 { 1222 port@7 {
1692 reg = 1223 reg = <7>;
1693 funne 1224 funnel0_in7: endpoint {
1694 1225 remote-endpoint = <&stm_out>;
1695 }; 1226 };
1696 }; 1227 };
1697 }; 1228 };
1698 }; 1229 };
1699 1230
1700 funnel2: funnel@6042000 { 1231 funnel2: funnel@6042000 {
1701 compatible = "arm,cor 1232 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1702 reg = <0x06042000 0x1 1233 reg = <0x06042000 0x1000>;
1703 status = "disabled"; 1234 status = "disabled";
1704 1235
1705 clocks = <&rpmcc RPM_ 1236 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1706 clock-names = "apb_pc 1237 clock-names = "apb_pclk", "atclk";
1707 1238
1708 out-ports { 1239 out-ports {
1709 port { 1240 port {
1710 funne 1241 funnel1_out: endpoint {
1711 1242 remote-endpoint =
1712 1243 <&merge_funnel_in1>;
1713 }; 1244 };
1714 }; 1245 };
1715 }; 1246 };
1716 1247
1717 in-ports { 1248 in-ports {
1718 #address-cell 1249 #address-cells = <1>;
1719 #size-cells = 1250 #size-cells = <0>;
1720 1251
1721 port@6 { 1252 port@6 {
1722 reg = 1253 reg = <6>;
1723 funne 1254 funnel1_in6: endpoint {
1724 1255 remote-endpoint =
1725 1256 <&apss_merge_funnel_out>;
1726 }; 1257 };
1727 }; 1258 };
1728 }; 1259 };
1729 }; 1260 };
1730 1261
1731 funnel3: funnel@6045000 { 1262 funnel3: funnel@6045000 {
1732 compatible = "arm,cor 1263 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1733 reg = <0x06045000 0x1 1264 reg = <0x06045000 0x1000>;
1734 status = "disabled"; 1265 status = "disabled";
1735 1266
1736 clocks = <&rpmcc RPM_ 1267 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1737 clock-names = "apb_pc 1268 clock-names = "apb_pclk", "atclk";
1738 1269
1739 out-ports { 1270 out-ports {
1740 port { 1271 port {
1741 merge 1272 merge_funnel_out: endpoint {
1742 1273 remote-endpoint =
1743 1274 <&etf_in>;
1744 }; 1275 };
1745 }; 1276 };
1746 }; 1277 };
1747 1278
1748 in-ports { 1279 in-ports {
1749 #address-cell 1280 #address-cells = <1>;
1750 #size-cells = 1281 #size-cells = <0>;
1751 1282
1752 port@0 { 1283 port@0 {
1753 reg = 1284 reg = <0>;
1754 merge 1285 merge_funnel_in0: endpoint {
1755 1286 remote-endpoint =
1756 1287 <&funnel0_out>;
1757 }; 1288 };
1758 }; 1289 };
1759 1290
1760 port@1 { 1291 port@1 {
1761 reg = 1292 reg = <1>;
1762 merge 1293 merge_funnel_in1: endpoint {
1763 1294 remote-endpoint =
1764 1295 <&funnel1_out>;
1765 }; 1296 };
1766 }; 1297 };
1767 }; 1298 };
1768 }; 1299 };
1769 1300
1770 replicator1: replicator@60460 1301 replicator1: replicator@6046000 {
1771 compatible = "arm,cor 1302 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
1772 reg = <0x06046000 0x1 1303 reg = <0x06046000 0x1000>;
1773 status = "disabled"; 1304 status = "disabled";
1774 1305
1775 clocks = <&rpmcc RPM_ 1306 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1776 clock-names = "apb_pc 1307 clock-names = "apb_pclk", "atclk";
1777 1308
1778 out-ports { 1309 out-ports {
1779 port { 1310 port {
1780 repli 1311 replicator_out: endpoint {
1781 1312 remote-endpoint = <&etr_in>;
1782 }; 1313 };
1783 }; 1314 };
1784 }; 1315 };
1785 1316
1786 in-ports { 1317 in-ports {
1787 port { 1318 port {
1788 repli 1319 replicator_in: endpoint {
1789 1320 remote-endpoint = <&etf_out>;
1790 }; 1321 };
1791 }; 1322 };
1792 }; 1323 };
1793 }; 1324 };
1794 1325
1795 etf: etf@6047000 { 1326 etf: etf@6047000 {
1796 compatible = "arm,cor 1327 compatible = "arm,coresight-tmc", "arm,primecell";
1797 reg = <0x06047000 0x1 1328 reg = <0x06047000 0x1000>;
1798 status = "disabled"; 1329 status = "disabled";
1799 1330
1800 clocks = <&rpmcc RPM_ 1331 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1801 clock-names = "apb_pc 1332 clock-names = "apb_pclk", "atclk";
1802 1333
1803 out-ports { 1334 out-ports {
1804 port { 1335 port {
1805 etf_o 1336 etf_out: endpoint {
1806 1337 remote-endpoint =
1807 1338 <&replicator_in>;
1808 }; 1339 };
1809 }; 1340 };
1810 }; 1341 };
1811 1342
1812 in-ports { 1343 in-ports {
1813 port { 1344 port {
1814 etf_i 1345 etf_in: endpoint {
1815 1346 remote-endpoint =
1816 1347 <&merge_funnel_out>;
1817 }; 1348 };
1818 }; 1349 };
1819 }; 1350 };
1820 }; 1351 };
1821 1352
1822 etr: etr@6048000 { 1353 etr: etr@6048000 {
1823 compatible = "arm,cor 1354 compatible = "arm,coresight-tmc", "arm,primecell";
1824 reg = <0x06048000 0x1 1355 reg = <0x06048000 0x1000>;
1825 status = "disabled"; 1356 status = "disabled";
1826 1357
1827 clocks = <&rpmcc RPM_ 1358 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1828 clock-names = "apb_pc 1359 clock-names = "apb_pclk", "atclk";
1829 arm,scatter-gather; 1360 arm,scatter-gather;
1830 1361
1831 in-ports { 1362 in-ports {
1832 port { 1363 port {
1833 etr_i 1364 etr_in: endpoint {
1834 1365 remote-endpoint =
1835 1366 <&replicator_out>;
1836 }; 1367 };
1837 }; 1368 };
1838 }; 1369 };
1839 }; 1370 };
1840 1371
1841 etm1: etm@7840000 { 1372 etm1: etm@7840000 {
1842 compatible = "arm,cor 1373 compatible = "arm,coresight-etm4x", "arm,primecell";
1843 reg = <0x07840000 0x1 1374 reg = <0x07840000 0x1000>;
1844 status = "disabled"; 1375 status = "disabled";
1845 1376
1846 clocks = <&rpmcc RPM_ 1377 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1847 clock-names = "apb_pc 1378 clock-names = "apb_pclk", "atclk";
1848 1379
1849 cpu = <&CPU0>; 1380 cpu = <&CPU0>;
1850 1381
1851 out-ports { 1382 out-ports {
1852 port { 1383 port {
1853 etm0_ 1384 etm0_out: endpoint {
1854 1385 remote-endpoint =
1855 1386 <&apss_funnel_in0>;
1856 }; 1387 };
1857 }; 1388 };
1858 }; 1389 };
1859 }; 1390 };
1860 1391
1861 etm2: etm@7940000 { 1392 etm2: etm@7940000 {
1862 compatible = "arm,cor 1393 compatible = "arm,coresight-etm4x", "arm,primecell";
1863 reg = <0x07940000 0x1 1394 reg = <0x07940000 0x1000>;
1864 status = "disabled"; 1395 status = "disabled";
1865 1396
1866 clocks = <&rpmcc RPM_ 1397 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1867 clock-names = "apb_pc 1398 clock-names = "apb_pclk", "atclk";
1868 1399
1869 cpu = <&CPU1>; 1400 cpu = <&CPU1>;
1870 1401
1871 out-ports { 1402 out-ports {
1872 port { 1403 port {
1873 etm1_ 1404 etm1_out: endpoint {
1874 1405 remote-endpoint =
1875 1406 <&apss_funnel_in1>;
1876 }; 1407 };
1877 }; 1408 };
1878 }; 1409 };
1879 }; 1410 };
1880 1411
1881 etm3: etm@7a40000 { 1412 etm3: etm@7a40000 {
1882 compatible = "arm,cor 1413 compatible = "arm,coresight-etm4x", "arm,primecell";
1883 reg = <0x07a40000 0x1 1414 reg = <0x07a40000 0x1000>;
1884 status = "disabled"; 1415 status = "disabled";
1885 1416
1886 clocks = <&rpmcc RPM_ 1417 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1887 clock-names = "apb_pc 1418 clock-names = "apb_pclk", "atclk";
1888 1419
1889 cpu = <&CPU2>; 1420 cpu = <&CPU2>;
1890 1421
1891 out-ports { 1422 out-ports {
1892 port { 1423 port {
1893 etm2_ 1424 etm2_out: endpoint {
1894 1425 remote-endpoint =
1895 1426 <&apss_funnel_in2>;
1896 }; 1427 };
1897 }; 1428 };
1898 }; 1429 };
1899 }; 1430 };
1900 1431
1901 etm4: etm@7b40000 { 1432 etm4: etm@7b40000 {
1902 compatible = "arm,cor 1433 compatible = "arm,coresight-etm4x", "arm,primecell";
1903 reg = <0x07b40000 0x1 1434 reg = <0x07b40000 0x1000>;
1904 status = "disabled"; 1435 status = "disabled";
1905 1436
1906 clocks = <&rpmcc RPM_ 1437 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1907 clock-names = "apb_pc 1438 clock-names = "apb_pclk", "atclk";
1908 1439
1909 cpu = <&CPU3>; 1440 cpu = <&CPU3>;
1910 1441
1911 out-ports { 1442 out-ports {
1912 port { 1443 port {
1913 etm3_ 1444 etm3_out: endpoint {
1914 1445 remote-endpoint =
1915 1446 <&apss_funnel_in3>;
1916 }; 1447 };
1917 }; 1448 };
1918 }; 1449 };
1919 }; 1450 };
1920 1451
1921 funnel4: funnel@7b60000 { /* 1452 funnel4: funnel@7b60000 { /* APSS Funnel */
1922 compatible = "arm,cor 1453 compatible = "arm,coresight-etm4x", "arm,primecell";
1923 reg = <0x07b60000 0x1 1454 reg = <0x07b60000 0x1000>;
1924 status = "disabled"; 1455 status = "disabled";
1925 1456
1926 clocks = <&rpmcc RPM_ 1457 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1927 clock-names = "apb_pc 1458 clock-names = "apb_pclk", "atclk";
1928 1459
1929 out-ports { 1460 out-ports {
1930 port { 1461 port {
1931 apss_ 1462 apss_funnel_out: endpoint {
1932 1463 remote-endpoint =
1933 1464 <&apss_merge_funnel_in>;
1934 }; 1465 };
1935 }; 1466 };
1936 }; 1467 };
1937 1468
1938 in-ports { 1469 in-ports {
1939 #address-cell 1470 #address-cells = <1>;
1940 #size-cells = 1471 #size-cells = <0>;
1941 1472
1942 port@0 { 1473 port@0 {
1943 reg = 1474 reg = <0>;
1944 apss_ 1475 apss_funnel_in0: endpoint {
1945 1476 remote-endpoint =
1946 1477 <&etm0_out>;
1947 }; 1478 };
1948 }; 1479 };
1949 1480
1950 port@1 { 1481 port@1 {
1951 reg = 1482 reg = <1>;
1952 apss_ 1483 apss_funnel_in1: endpoint {
1953 1484 remote-endpoint =
1954 1485 <&etm1_out>;
1955 }; 1486 };
1956 }; 1487 };
1957 1488
1958 port@2 { 1489 port@2 {
1959 reg = 1490 reg = <2>;
1960 apss_ 1491 apss_funnel_in2: endpoint {
1961 1492 remote-endpoint =
1962 1493 <&etm2_out>;
1963 }; 1494 };
1964 }; 1495 };
1965 1496
1966 port@3 { 1497 port@3 {
1967 reg = 1498 reg = <3>;
1968 apss_ 1499 apss_funnel_in3: endpoint {
1969 1500 remote-endpoint =
1970 1501 <&etm3_out>;
1971 }; 1502 };
1972 }; 1503 };
1973 1504
1974 port@4 { 1505 port@4 {
1975 reg = 1506 reg = <4>;
1976 apss_ 1507 apss_funnel_in4: endpoint {
1977 1508 remote-endpoint =
1978 1509 <&etm4_out>;
1979 }; 1510 };
1980 }; 1511 };
1981 1512
1982 port@5 { 1513 port@5 {
1983 reg = 1514 reg = <5>;
1984 apss_ 1515 apss_funnel_in5: endpoint {
1985 1516 remote-endpoint =
1986 1517 <&etm5_out>;
1987 }; 1518 };
1988 }; 1519 };
1989 1520
1990 port@6 { 1521 port@6 {
1991 reg = 1522 reg = <6>;
1992 apss_ 1523 apss_funnel_in6: endpoint {
1993 1524 remote-endpoint =
1994 1525 <&etm6_out>;
1995 }; 1526 };
1996 }; 1527 };
1997 1528
1998 port@7 { 1529 port@7 {
1999 reg = 1530 reg = <7>;
2000 apss_ 1531 apss_funnel_in7: endpoint {
2001 1532 remote-endpoint =
2002 1533 <&etm7_out>;
2003 }; 1534 };
2004 }; 1535 };
2005 }; 1536 };
2006 }; 1537 };
2007 1538
2008 funnel5: funnel@7b70000 { 1539 funnel5: funnel@7b70000 {
2009 compatible = "arm,cor 1540 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2010 reg = <0x07b70000 0x1 1541 reg = <0x07b70000 0x1000>;
2011 status = "disabled"; 1542 status = "disabled";
2012 1543
2013 clocks = <&rpmcc RPM_ 1544 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2014 clock-names = "apb_pc 1545 clock-names = "apb_pclk", "atclk";
2015 1546
2016 out-ports { 1547 out-ports {
2017 port { 1548 port {
2018 apss_ 1549 apss_merge_funnel_out: endpoint {
2019 1550 remote-endpoint =
2020 1551 <&funnel1_in6>;
2021 }; 1552 };
2022 }; 1553 };
2023 }; 1554 };
2024 1555
2025 in-ports { 1556 in-ports {
2026 port { 1557 port {
2027 apss_ 1558 apss_merge_funnel_in: endpoint {
2028 1559 remote-endpoint =
2029 1560 <&apss_funnel_out>;
2030 }; 1561 };
2031 }; 1562 };
2032 }; 1563 };
2033 }; 1564 };
2034 1565
2035 etm5: etm@7c40000 { 1566 etm5: etm@7c40000 {
2036 compatible = "arm,cor 1567 compatible = "arm,coresight-etm4x", "arm,primecell";
2037 reg = <0x07c40000 0x1 1568 reg = <0x07c40000 0x1000>;
2038 status = "disabled"; 1569 status = "disabled";
2039 1570
2040 clocks = <&rpmcc RPM_ 1571 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2041 clock-names = "apb_pc 1572 clock-names = "apb_pclk", "atclk";
2042 1573
2043 cpu = <&CPU4>; 1574 cpu = <&CPU4>;
2044 1575
2045 out-ports { !! 1576 port{
2046 port { !! 1577 etm4_out: endpoint {
2047 etm4_ !! 1578 remote-endpoint = <&apss_funnel_in4>;
2048 <<
2049 }; <<
2050 }; 1579 };
2051 }; 1580 };
2052 }; 1581 };
2053 1582
2054 etm6: etm@7d40000 { 1583 etm6: etm@7d40000 {
2055 compatible = "arm,cor 1584 compatible = "arm,coresight-etm4x", "arm,primecell";
2056 reg = <0x07d40000 0x1 1585 reg = <0x07d40000 0x1000>;
2057 status = "disabled"; 1586 status = "disabled";
2058 1587
2059 clocks = <&rpmcc RPM_ 1588 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2060 clock-names = "apb_pc 1589 clock-names = "apb_pclk", "atclk";
2061 1590
2062 cpu = <&CPU5>; 1591 cpu = <&CPU5>;
2063 1592
2064 out-ports { !! 1593 port{
2065 port { !! 1594 etm5_out: endpoint {
2066 etm5_ !! 1595 remote-endpoint = <&apss_funnel_in5>;
2067 <<
2068 }; <<
2069 }; 1596 };
2070 }; 1597 };
2071 }; 1598 };
2072 1599
2073 etm7: etm@7e40000 { 1600 etm7: etm@7e40000 {
2074 compatible = "arm,cor 1601 compatible = "arm,coresight-etm4x", "arm,primecell";
2075 reg = <0x07e40000 0x1 1602 reg = <0x07e40000 0x1000>;
2076 status = "disabled"; 1603 status = "disabled";
2077 1604
2078 clocks = <&rpmcc RPM_ 1605 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2079 clock-names = "apb_pc 1606 clock-names = "apb_pclk", "atclk";
2080 1607
2081 cpu = <&CPU6>; 1608 cpu = <&CPU6>;
2082 1609
2083 out-ports { !! 1610 port{
2084 port { !! 1611 etm6_out: endpoint {
2085 etm6_ !! 1612 remote-endpoint = <&apss_funnel_in6>;
2086 <<
2087 }; <<
2088 }; 1613 };
2089 }; 1614 };
2090 }; 1615 };
2091 1616
2092 etm8: etm@7f40000 { 1617 etm8: etm@7f40000 {
2093 compatible = "arm,cor 1618 compatible = "arm,coresight-etm4x", "arm,primecell";
2094 reg = <0x07f40000 0x1 1619 reg = <0x07f40000 0x1000>;
2095 status = "disabled"; 1620 status = "disabled";
2096 1621
2097 clocks = <&rpmcc RPM_ 1622 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2098 clock-names = "apb_pc 1623 clock-names = "apb_pclk", "atclk";
2099 1624
2100 cpu = <&CPU7>; 1625 cpu = <&CPU7>;
2101 1626
2102 out-ports { !! 1627 port{
2103 port { !! 1628 etm7_out: endpoint {
2104 etm7_ !! 1629 remote-endpoint = <&apss_funnel_in7>;
2105 <<
2106 }; <<
2107 }; 1630 };
2108 }; 1631 };
2109 }; 1632 };
2110 1633
2111 sram@290000 { <<
2112 compatible = "qcom,rp <<
2113 reg = <0x00290000 0x1 <<
2114 }; <<
2115 <<
2116 spmi_bus: spmi@800f000 { 1634 spmi_bus: spmi@800f000 {
2117 compatible = "qcom,sp 1635 compatible = "qcom,spmi-pmic-arb";
2118 reg = <0x0800f000 0x1 !! 1636 reg = <0x0800f000 0x1000>,
2119 <0x08400000 0x1 !! 1637 <0x08400000 0x1000000>,
2120 <0x09400000 0x1 !! 1638 <0x09400000 0x1000000>,
2121 <0x0a400000 0x2 !! 1639 <0x0a400000 0x220000>,
2122 <0x0800a000 0x3 !! 1640 <0x0800a000 0x3000>;
2123 reg-names = "core", " 1641 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
2124 interrupt-names = "pe 1642 interrupt-names = "periph_irq";
2125 interrupts = <GIC_SPI 1643 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
2126 qcom,ee = <0>; 1644 qcom,ee = <0>;
2127 qcom,channel = <0>; 1645 qcom,channel = <0>;
2128 #address-cells = <2>; 1646 #address-cells = <2>;
2129 #size-cells = <0>; 1647 #size-cells = <0>;
2130 interrupt-controller; 1648 interrupt-controller;
2131 #interrupt-cells = <4 1649 #interrupt-cells = <4>;
>> 1650 cell-index = <0>;
2132 }; 1651 };
2133 1652
2134 usb3: usb@a8f8800 { 1653 usb3: usb@a8f8800 {
2135 compatible = "qcom,ms 1654 compatible = "qcom,msm8998-dwc3", "qcom,dwc3";
2136 reg = <0x0a8f8800 0x4 1655 reg = <0x0a8f8800 0x400>;
2137 status = "disabled"; 1656 status = "disabled";
2138 #address-cells = <1>; 1657 #address-cells = <1>;
2139 #size-cells = <1>; 1658 #size-cells = <1>;
2140 ranges; 1659 ranges;
2141 1660
2142 clocks = <&gcc GCC_CF 1661 clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>,
2143 <&gcc GCC_US 1662 <&gcc GCC_USB30_MASTER_CLK>,
2144 <&gcc GCC_AG 1663 <&gcc GCC_AGGRE1_USB3_AXI_CLK>,
2145 <&gcc GCC_US !! 1664 <&gcc GCC_USB30_MOCK_UTMI_CLK>,
2146 <&gcc GCC_US !! 1665 <&gcc GCC_USB30_SLEEP_CLK>;
2147 clock-names = "cfg_no !! 1666 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
2148 "core", !! 1667 "sleep";
2149 "iface" <<
2150 "sleep" <<
2151 "mock_u <<
2152 1668
2153 assigned-clocks = <&g 1669 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
2154 <&g 1670 <&gcc GCC_USB30_MASTER_CLK>;
2155 assigned-clock-rates 1671 assigned-clock-rates = <19200000>, <120000000>;
2156 1672
2157 interrupts = <GIC_SPI !! 1673 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
2158 <GIC_SPI <<
2159 <GIC_SPI 1674 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
2160 interrupt-names = "pw !! 1675 interrupt-names = "hs_phy_irq", "ss_phy_irq";
2161 "qu <<
2162 "ss <<
2163 1676
2164 power-domains = <&gcc 1677 power-domains = <&gcc USB_30_GDSC>;
2165 1678
2166 resets = <&gcc GCC_US 1679 resets = <&gcc GCC_USB_30_BCR>;
2167 1680
2168 usb3_dwc3: usb@a80000 !! 1681 usb3_dwc3: dwc3@a800000 {
2169 compatible = 1682 compatible = "snps,dwc3";
2170 reg = <0x0a80 1683 reg = <0x0a800000 0xcd00>;
2171 interrupts = 1684 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
2172 snps,dis_u2_s 1685 snps,dis_u2_susphy_quirk;
2173 snps,dis_enbl 1686 snps,dis_enblslpm_quirk;
2174 snps,parkmode !! 1687 phys = <&qusb2phy>, <&usb1_ssphy>;
2175 phys = <&qusb <<
2176 phy-names = " 1688 phy-names = "usb2-phy", "usb3-phy";
2177 snps,has-lpm- 1689 snps,has-lpm-erratum;
2178 snps,hird-thr 1690 snps,hird-threshold = /bits/ 8 <0x10>;
2179 }; 1691 };
2180 }; 1692 };
2181 1693
2182 usb3phy: phy@c010000 { 1694 usb3phy: phy@c010000 {
2183 compatible = "qcom,ms 1695 compatible = "qcom,msm8998-qmp-usb3-phy";
2184 reg = <0x0c010000 0x1 !! 1696 reg = <0x0c010000 0x18c>;
>> 1697 status = "disabled";
>> 1698 #clock-cells = <1>;
>> 1699 #address-cells = <1>;
>> 1700 #size-cells = <1>;
>> 1701 ranges;
2185 1702
2186 clocks = <&gcc GCC_US 1703 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
2187 <&gcc GCC_US <<
2188 <&gcc GCC_US 1704 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2189 <&gcc GCC_US !! 1705 <&gcc GCC_USB3_CLKREF_CLK>;
2190 clock-names = "aux", !! 1706 clock-names = "aux", "cfg_ahb", "ref";
2191 "ref", <<
2192 "cfg_ah <<
2193 "pipe"; <<
2194 clock-output-names = <<
2195 #clock-cells = <0>; <<
2196 #phy-cells = <0>; <<
2197 1707
2198 resets = <&gcc GCC_US 1708 resets = <&gcc GCC_USB3_PHY_BCR>,
2199 <&gcc GCC_US 1709 <&gcc GCC_USB3PHY_PHY_BCR>;
2200 reset-names = "phy", !! 1710 reset-names = "phy", "common";
2201 "phy_ph <<
2202 <<
2203 qcom,tcsr-reg = <&tcs <<
2204 1711
2205 status = "disabled"; !! 1712 usb1_ssphy: lane@c010200 {
>> 1713 reg = <0xc010200 0x128>,
>> 1714 <0xc010400 0x200>,
>> 1715 <0xc010c00 0x20c>,
>> 1716 <0xc010600 0x128>,
>> 1717 <0xc010800 0x200>;
>> 1718 #phy-cells = <0>;
>> 1719 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
>> 1720 clock-names = "pipe0";
>> 1721 clock-output-names = "usb3_phy_pipe_clk_src";
>> 1722 };
2206 }; 1723 };
2207 1724
2208 qusb2phy: phy@c012000 { 1725 qusb2phy: phy@c012000 {
2209 compatible = "qcom,ms 1726 compatible = "qcom,msm8998-qusb2-phy";
2210 reg = <0x0c012000 0x2 1727 reg = <0x0c012000 0x2a8>;
2211 status = "disabled"; 1728 status = "disabled";
2212 #phy-cells = <0>; 1729 #phy-cells = <0>;
2213 1730
2214 clocks = <&gcc GCC_US 1731 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2215 <&gcc GCC_RX 1732 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
2216 clock-names = "cfg_ah 1733 clock-names = "cfg_ahb", "ref";
2217 1734
2218 resets = <&gcc GCC_QU 1735 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2219 1736
2220 nvmem-cells = <&qusb2 1737 nvmem-cells = <&qusb2_hstx_trim>;
2221 }; 1738 };
2222 1739
2223 sdhc2: mmc@c0a4900 { !! 1740 sdhc2: sdhci@c0a4900 {
2224 compatible = "qcom,ms !! 1741 compatible = "qcom,sdhci-msm-v4";
2225 reg = <0x0c0a4900 0x3 1742 reg = <0x0c0a4900 0x314>, <0x0c0a4000 0x800>;
2226 reg-names = "hc", "co !! 1743 reg-names = "hc_mem", "core_mem";
2227 1744
2228 interrupts = <GIC_SPI 1745 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
2229 <GIC_SPI 1746 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
2230 interrupt-names = "hc 1747 interrupt-names = "hc_irq", "pwr_irq";
2231 1748
2232 clock-names = "iface" 1749 clock-names = "iface", "core", "xo";
2233 clocks = <&gcc GCC_SD 1750 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2234 <&gcc GCC_SD 1751 <&gcc GCC_SDCC2_APPS_CLK>,
2235 <&rpmcc RPM_ !! 1752 <&xo>;
2236 bus-width = <4>; 1753 bus-width = <4>;
2237 status = "disabled"; 1754 status = "disabled";
2238 }; 1755 };
2239 1756
2240 blsp1_dma: dma-controller@c14 !! 1757 blsp1_dma: dma@c144000 {
2241 compatible = "qcom,ba 1758 compatible = "qcom,bam-v1.7.0";
2242 reg = <0x0c144000 0x2 1759 reg = <0x0c144000 0x25000>;
2243 interrupts = <GIC_SPI 1760 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
2244 clocks = <&gcc GCC_BL 1761 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
2245 clock-names = "bam_cl 1762 clock-names = "bam_clk";
2246 #dma-cells = <1>; 1763 #dma-cells = <1>;
2247 qcom,ee = <0>; 1764 qcom,ee = <0>;
2248 qcom,controlled-remot 1765 qcom,controlled-remotely;
2249 num-channels = <18>; 1766 num-channels = <18>;
2250 qcom,num-ees = <4>; 1767 qcom,num-ees = <4>;
2251 }; 1768 };
2252 1769
2253 blsp1_uart3: serial@c171000 { 1770 blsp1_uart3: serial@c171000 {
2254 compatible = "qcom,ms 1771 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2255 reg = <0x0c171000 0x1 1772 reg = <0x0c171000 0x1000>;
2256 interrupts = <GIC_SPI 1773 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
2257 clocks = <&gcc GCC_BL 1774 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
2258 <&gcc GCC_BL 1775 <&gcc GCC_BLSP1_AHB_CLK>;
2259 clock-names = "core", 1776 clock-names = "core", "iface";
2260 dmas = <&blsp1_dma 4> 1777 dmas = <&blsp1_dma 4>, <&blsp1_dma 5>;
2261 dma-names = "tx", "rx 1778 dma-names = "tx", "rx";
2262 pinctrl-names = "defa 1779 pinctrl-names = "default";
2263 pinctrl-0 = <&blsp1_u 1780 pinctrl-0 = <&blsp1_uart3_on>;
2264 status = "disabled"; 1781 status = "disabled";
2265 }; 1782 };
2266 1783
2267 blsp1_i2c1: i2c@c175000 { 1784 blsp1_i2c1: i2c@c175000 {
2268 compatible = "qcom,i2 1785 compatible = "qcom,i2c-qup-v2.2.1";
2269 reg = <0x0c175000 0x6 1786 reg = <0x0c175000 0x600>;
2270 interrupts = <GIC_SPI 1787 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
2271 1788
2272 clocks = <&gcc GCC_BL 1789 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
2273 <&gcc GCC_BL 1790 <&gcc GCC_BLSP1_AHB_CLK>;
2274 clock-names = "core", 1791 clock-names = "core", "iface";
2275 dmas = <&blsp1_dma 6> <<
2276 dma-names = "tx", "rx <<
2277 pinctrl-names = "defa <<
2278 pinctrl-0 = <&blsp1_i <<
2279 pinctrl-1 = <&blsp1_i <<
2280 clock-frequency = <40 1792 clock-frequency = <400000>;
2281 1793
2282 status = "disabled"; 1794 status = "disabled";
2283 #address-cells = <1>; 1795 #address-cells = <1>;
2284 #size-cells = <0>; 1796 #size-cells = <0>;
2285 }; 1797 };
2286 1798
2287 blsp1_i2c2: i2c@c176000 { 1799 blsp1_i2c2: i2c@c176000 {
2288 compatible = "qcom,i2 1800 compatible = "qcom,i2c-qup-v2.2.1";
2289 reg = <0x0c176000 0x6 1801 reg = <0x0c176000 0x600>;
2290 interrupts = <GIC_SPI 1802 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
2291 1803
2292 clocks = <&gcc GCC_BL 1804 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
2293 <&gcc GCC_BL 1805 <&gcc GCC_BLSP1_AHB_CLK>;
2294 clock-names = "core", 1806 clock-names = "core", "iface";
2295 dmas = <&blsp1_dma 8> <<
2296 dma-names = "tx", "rx <<
2297 pinctrl-names = "defa <<
2298 pinctrl-0 = <&blsp1_i <<
2299 pinctrl-1 = <&blsp1_i <<
2300 clock-frequency = <40 1807 clock-frequency = <400000>;
2301 1808
2302 status = "disabled"; 1809 status = "disabled";
2303 #address-cells = <1>; 1810 #address-cells = <1>;
2304 #size-cells = <0>; 1811 #size-cells = <0>;
2305 }; 1812 };
2306 1813
2307 blsp1_i2c3: i2c@c177000 { 1814 blsp1_i2c3: i2c@c177000 {
2308 compatible = "qcom,i2 1815 compatible = "qcom,i2c-qup-v2.2.1";
2309 reg = <0x0c177000 0x6 1816 reg = <0x0c177000 0x600>;
2310 interrupts = <GIC_SPI 1817 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
2311 1818
2312 clocks = <&gcc GCC_BL 1819 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
2313 <&gcc GCC_BL 1820 <&gcc GCC_BLSP1_AHB_CLK>;
2314 clock-names = "core", 1821 clock-names = "core", "iface";
2315 dmas = <&blsp1_dma 10 <<
2316 dma-names = "tx", "rx <<
2317 pinctrl-names = "defa <<
2318 pinctrl-0 = <&blsp1_i <<
2319 pinctrl-1 = <&blsp1_i <<
2320 clock-frequency = <40 1822 clock-frequency = <400000>;
2321 1823
2322 status = "disabled"; 1824 status = "disabled";
2323 #address-cells = <1>; 1825 #address-cells = <1>;
2324 #size-cells = <0>; 1826 #size-cells = <0>;
2325 }; 1827 };
2326 1828
2327 blsp1_i2c4: i2c@c178000 { 1829 blsp1_i2c4: i2c@c178000 {
2328 compatible = "qcom,i2 1830 compatible = "qcom,i2c-qup-v2.2.1";
2329 reg = <0x0c178000 0x6 1831 reg = <0x0c178000 0x600>;
2330 interrupts = <GIC_SPI 1832 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
2331 1833
2332 clocks = <&gcc GCC_BL 1834 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
2333 <&gcc GCC_BL 1835 <&gcc GCC_BLSP1_AHB_CLK>;
2334 clock-names = "core", 1836 clock-names = "core", "iface";
2335 dmas = <&blsp1_dma 12 <<
2336 dma-names = "tx", "rx <<
2337 pinctrl-names = "defa <<
2338 pinctrl-0 = <&blsp1_i <<
2339 pinctrl-1 = <&blsp1_i <<
2340 clock-frequency = <40 1837 clock-frequency = <400000>;
2341 1838
2342 status = "disabled"; 1839 status = "disabled";
2343 #address-cells = <1>; 1840 #address-cells = <1>;
2344 #size-cells = <0>; 1841 #size-cells = <0>;
2345 }; 1842 };
2346 1843
2347 blsp1_i2c5: i2c@c179000 { 1844 blsp1_i2c5: i2c@c179000 {
2348 compatible = "qcom,i2 1845 compatible = "qcom,i2c-qup-v2.2.1";
2349 reg = <0x0c179000 0x6 1846 reg = <0x0c179000 0x600>;
2350 interrupts = <GIC_SPI 1847 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
2351 1848
2352 clocks = <&gcc GCC_BL 1849 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
2353 <&gcc GCC_BL 1850 <&gcc GCC_BLSP1_AHB_CLK>;
2354 clock-names = "core", 1851 clock-names = "core", "iface";
2355 dmas = <&blsp1_dma 14 <<
2356 dma-names = "tx", "rx <<
2357 pinctrl-names = "defa <<
2358 pinctrl-0 = <&blsp1_i <<
2359 pinctrl-1 = <&blsp1_i <<
2360 clock-frequency = <40 1852 clock-frequency = <400000>;
2361 1853
2362 status = "disabled"; 1854 status = "disabled";
2363 #address-cells = <1>; 1855 #address-cells = <1>;
2364 #size-cells = <0>; 1856 #size-cells = <0>;
2365 }; 1857 };
2366 1858
2367 blsp1_i2c6: i2c@c17a000 { 1859 blsp1_i2c6: i2c@c17a000 {
2368 compatible = "qcom,i2 1860 compatible = "qcom,i2c-qup-v2.2.1";
2369 reg = <0x0c17a000 0x6 1861 reg = <0x0c17a000 0x600>;
2370 interrupts = <GIC_SPI 1862 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
2371 1863
2372 clocks = <&gcc GCC_BL 1864 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
2373 <&gcc GCC_BL 1865 <&gcc GCC_BLSP1_AHB_CLK>;
2374 clock-names = "core", 1866 clock-names = "core", "iface";
2375 dmas = <&blsp1_dma 16 <<
2376 dma-names = "tx", "rx <<
2377 pinctrl-names = "defa <<
2378 pinctrl-0 = <&blsp1_i <<
2379 pinctrl-1 = <&blsp1_i <<
2380 clock-frequency = <40 1867 clock-frequency = <400000>;
2381 1868
2382 status = "disabled"; 1869 status = "disabled";
2383 #address-cells = <1>; 1870 #address-cells = <1>;
2384 #size-cells = <0>; 1871 #size-cells = <0>;
2385 }; 1872 };
2386 1873
2387 blsp1_spi1: spi@c175000 { <<
2388 compatible = "qcom,sp <<
2389 reg = <0x0c175000 0x6 <<
2390 interrupts = <GIC_SPI <<
2391 <<
2392 clocks = <&gcc GCC_BL <<
2393 <&gcc GCC_BL <<
2394 clock-names = "core", <<
2395 dmas = <&blsp1_dma 6> <<
2396 dma-names = "tx", "rx <<
2397 pinctrl-names = "defa <<
2398 pinctrl-0 = <&blsp1_s <<
2399 <<
2400 status = "disabled"; <<
2401 #address-cells = <1>; <<
2402 #size-cells = <0>; <<
2403 }; <<
2404 <<
2405 blsp1_spi2: spi@c176000 { <<
2406 compatible = "qcom,sp <<
2407 reg = <0x0c176000 0x6 <<
2408 interrupts = <GIC_SPI <<
2409 <<
2410 clocks = <&gcc GCC_BL <<
2411 <&gcc GCC_BL <<
2412 clock-names = "core", <<
2413 dmas = <&blsp1_dma 8> <<
2414 dma-names = "tx", "rx <<
2415 pinctrl-names = "defa <<
2416 pinctrl-0 = <&blsp1_s <<
2417 <<
2418 status = "disabled"; <<
2419 #address-cells = <1>; <<
2420 #size-cells = <0>; <<
2421 }; <<
2422 <<
2423 blsp1_spi3: spi@c177000 { <<
2424 compatible = "qcom,sp <<
2425 reg = <0x0c177000 0x6 <<
2426 interrupts = <GIC_SPI <<
2427 <<
2428 clocks = <&gcc GCC_BL <<
2429 <&gcc GCC_BL <<
2430 clock-names = "core", <<
2431 dmas = <&blsp1_dma 10 <<
2432 dma-names = "tx", "rx <<
2433 pinctrl-names = "defa <<
2434 pinctrl-0 = <&blsp1_s <<
2435 <<
2436 status = "disabled"; <<
2437 #address-cells = <1>; <<
2438 #size-cells = <0>; <<
2439 }; <<
2440 <<
2441 blsp1_spi4: spi@c178000 { <<
2442 compatible = "qcom,sp <<
2443 reg = <0x0c178000 0x6 <<
2444 interrupts = <GIC_SPI <<
2445 <<
2446 clocks = <&gcc GCC_BL <<
2447 <&gcc GCC_BL <<
2448 clock-names = "core", <<
2449 dmas = <&blsp1_dma 12 <<
2450 dma-names = "tx", "rx <<
2451 pinctrl-names = "defa <<
2452 pinctrl-0 = <&blsp1_s <<
2453 <<
2454 status = "disabled"; <<
2455 #address-cells = <1>; <<
2456 #size-cells = <0>; <<
2457 }; <<
2458 <<
2459 blsp1_spi5: spi@c179000 { <<
2460 compatible = "qcom,sp <<
2461 reg = <0x0c179000 0x6 <<
2462 interrupts = <GIC_SPI <<
2463 <<
2464 clocks = <&gcc GCC_BL <<
2465 <&gcc GCC_BL <<
2466 clock-names = "core", <<
2467 dmas = <&blsp1_dma 14 <<
2468 dma-names = "tx", "rx <<
2469 pinctrl-names = "defa <<
2470 pinctrl-0 = <&blsp1_s <<
2471 <<
2472 status = "disabled"; <<
2473 #address-cells = <1>; <<
2474 #size-cells = <0>; <<
2475 }; <<
2476 <<
2477 blsp1_spi6: spi@c17a000 { <<
2478 compatible = "qcom,sp <<
2479 reg = <0x0c17a000 0x6 <<
2480 interrupts = <GIC_SPI <<
2481 <<
2482 clocks = <&gcc GCC_BL <<
2483 <&gcc GCC_BL <<
2484 clock-names = "core", <<
2485 dmas = <&blsp1_dma 16 <<
2486 dma-names = "tx", "rx <<
2487 pinctrl-names = "defa <<
2488 pinctrl-0 = <&blsp1_s <<
2489 <<
2490 status = "disabled"; <<
2491 #address-cells = <1>; <<
2492 #size-cells = <0>; <<
2493 }; <<
2494 <<
2495 blsp2_dma: dma-controller@c18 <<
2496 compatible = "qcom,ba <<
2497 reg = <0x0c184000 0x2 <<
2498 interrupts = <GIC_SPI <<
2499 clocks = <&gcc GCC_BL <<
2500 clock-names = "bam_cl <<
2501 #dma-cells = <1>; <<
2502 qcom,ee = <0>; <<
2503 qcom,controlled-remot <<
2504 num-channels = <18>; <<
2505 qcom,num-ees = <4>; <<
2506 }; <<
2507 <<
2508 blsp2_uart1: serial@c1b0000 { 1874 blsp2_uart1: serial@c1b0000 {
2509 compatible = "qcom,ms 1875 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2510 reg = <0x0c1b0000 0x1 1876 reg = <0x0c1b0000 0x1000>;
2511 interrupts = <GIC_SPI 1877 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
2512 clocks = <&gcc GCC_BL 1878 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
2513 <&gcc GCC_BL 1879 <&gcc GCC_BLSP2_AHB_CLK>;
2514 clock-names = "core", 1880 clock-names = "core", "iface";
2515 status = "disabled"; 1881 status = "disabled";
2516 }; 1882 };
2517 1883
2518 blsp2_i2c1: i2c@c1b5000 { !! 1884 blsp2_i2c0: i2c@c1b5000 {
2519 compatible = "qcom,i2 1885 compatible = "qcom,i2c-qup-v2.2.1";
2520 reg = <0x0c1b5000 0x6 1886 reg = <0x0c1b5000 0x600>;
2521 interrupts = <GIC_SPI 1887 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
2522 1888
2523 clocks = <&gcc GCC_BL 1889 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
2524 <&gcc GCC_BL 1890 <&gcc GCC_BLSP2_AHB_CLK>;
2525 clock-names = "core", 1891 clock-names = "core", "iface";
2526 dmas = <&blsp2_dma 6> <<
2527 dma-names = "tx", "rx <<
2528 pinctrl-names = "defa <<
2529 pinctrl-0 = <&blsp2_i <<
2530 pinctrl-1 = <&blsp2_i <<
2531 clock-frequency = <40 1892 clock-frequency = <400000>;
2532 1893
2533 status = "disabled"; 1894 status = "disabled";
2534 #address-cells = <1>; 1895 #address-cells = <1>;
2535 #size-cells = <0>; 1896 #size-cells = <0>;
2536 }; 1897 };
2537 1898
2538 blsp2_i2c2: i2c@c1b6000 { !! 1899 blsp2_i2c1: i2c@c1b6000 {
2539 compatible = "qcom,i2 1900 compatible = "qcom,i2c-qup-v2.2.1";
2540 reg = <0x0c1b6000 0x6 1901 reg = <0x0c1b6000 0x600>;
2541 interrupts = <GIC_SPI 1902 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
2542 1903
2543 clocks = <&gcc GCC_BL 1904 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
2544 <&gcc GCC_BL 1905 <&gcc GCC_BLSP2_AHB_CLK>;
2545 clock-names = "core", 1906 clock-names = "core", "iface";
2546 dmas = <&blsp2_dma 8> <<
2547 dma-names = "tx", "rx <<
2548 pinctrl-names = "defa <<
2549 pinctrl-0 = <&blsp2_i <<
2550 pinctrl-1 = <&blsp2_i <<
2551 clock-frequency = <40 1907 clock-frequency = <400000>;
2552 1908
2553 status = "disabled"; 1909 status = "disabled";
2554 #address-cells = <1>; 1910 #address-cells = <1>;
2555 #size-cells = <0>; 1911 #size-cells = <0>;
2556 }; 1912 };
2557 1913
2558 blsp2_i2c3: i2c@c1b7000 { !! 1914 blsp2_i2c2: i2c@c1b7000 {
2559 compatible = "qcom,i2 1915 compatible = "qcom,i2c-qup-v2.2.1";
2560 reg = <0x0c1b7000 0x6 1916 reg = <0x0c1b7000 0x600>;
2561 interrupts = <GIC_SPI 1917 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
2562 1918
2563 clocks = <&gcc GCC_BL 1919 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
2564 <&gcc GCC_BL 1920 <&gcc GCC_BLSP2_AHB_CLK>;
2565 clock-names = "core", 1921 clock-names = "core", "iface";
2566 dmas = <&blsp2_dma 10 <<
2567 dma-names = "tx", "rx <<
2568 pinctrl-names = "defa <<
2569 pinctrl-0 = <&blsp2_i <<
2570 pinctrl-1 = <&blsp2_i <<
2571 clock-frequency = <40 1922 clock-frequency = <400000>;
2572 1923
2573 status = "disabled"; 1924 status = "disabled";
2574 #address-cells = <1>; 1925 #address-cells = <1>;
2575 #size-cells = <0>; 1926 #size-cells = <0>;
2576 }; 1927 };
2577 1928
2578 blsp2_i2c4: i2c@c1b8000 { !! 1929 blsp2_i2c3: i2c@c1b8000 {
2579 compatible = "qcom,i2 1930 compatible = "qcom,i2c-qup-v2.2.1";
2580 reg = <0x0c1b8000 0x6 1931 reg = <0x0c1b8000 0x600>;
2581 interrupts = <GIC_SPI 1932 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
2582 1933
2583 clocks = <&gcc GCC_BL 1934 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>,
2584 <&gcc GCC_BL 1935 <&gcc GCC_BLSP2_AHB_CLK>;
2585 clock-names = "core", 1936 clock-names = "core", "iface";
2586 dmas = <&blsp2_dma 12 <<
2587 dma-names = "tx", "rx <<
2588 pinctrl-names = "defa <<
2589 pinctrl-0 = <&blsp2_i <<
2590 pinctrl-1 = <&blsp2_i <<
2591 clock-frequency = <40 1937 clock-frequency = <400000>;
2592 1938
2593 status = "disabled"; 1939 status = "disabled";
2594 #address-cells = <1>; 1940 #address-cells = <1>;
2595 #size-cells = <0>; 1941 #size-cells = <0>;
2596 }; 1942 };
2597 1943
2598 blsp2_i2c5: i2c@c1b9000 { !! 1944 blsp2_i2c4: i2c@c1b9000 {
2599 compatible = "qcom,i2 1945 compatible = "qcom,i2c-qup-v2.2.1";
2600 reg = <0x0c1b9000 0x6 1946 reg = <0x0c1b9000 0x600>;
2601 interrupts = <GIC_SPI 1947 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
2602 1948
2603 clocks = <&gcc GCC_BL 1949 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,
2604 <&gcc GCC_BL 1950 <&gcc GCC_BLSP2_AHB_CLK>;
2605 clock-names = "core", 1951 clock-names = "core", "iface";
2606 dmas = <&blsp2_dma 14 <<
2607 dma-names = "tx", "rx <<
2608 pinctrl-names = "defa <<
2609 pinctrl-0 = <&blsp2_i <<
2610 pinctrl-1 = <&blsp2_i <<
2611 clock-frequency = <40 1952 clock-frequency = <400000>;
2612 1953
2613 status = "disabled"; 1954 status = "disabled";
2614 #address-cells = <1>; 1955 #address-cells = <1>;
2615 #size-cells = <0>; 1956 #size-cells = <0>;
2616 }; 1957 };
2617 1958
2618 blsp2_i2c6: i2c@c1ba000 { !! 1959 blsp2_i2c5: i2c@c1ba000 {
2619 compatible = "qcom,i2 1960 compatible = "qcom,i2c-qup-v2.2.1";
2620 reg = <0x0c1ba000 0x6 1961 reg = <0x0c1ba000 0x600>;
2621 interrupts = <GIC_SPI 1962 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
2622 1963
2623 clocks = <&gcc GCC_BL 1964 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>,
2624 <&gcc GCC_BL 1965 <&gcc GCC_BLSP2_AHB_CLK>;
2625 clock-names = "core", 1966 clock-names = "core", "iface";
2626 dmas = <&blsp2_dma 16 <<
2627 dma-names = "tx", "rx <<
2628 pinctrl-names = "defa <<
2629 pinctrl-0 = <&blsp2_i <<
2630 pinctrl-1 = <&blsp2_i <<
2631 clock-frequency = <40 1967 clock-frequency = <400000>;
2632 1968
2633 status = "disabled"; 1969 status = "disabled";
2634 #address-cells = <1>; 1970 #address-cells = <1>;
2635 #size-cells = <0>; 1971 #size-cells = <0>;
2636 }; 1972 };
2637 1973
2638 blsp2_spi1: spi@c1b5000 { <<
2639 compatible = "qcom,sp <<
2640 reg = <0x0c1b5000 0x6 <<
2641 interrupts = <GIC_SPI <<
2642 <<
2643 clocks = <&gcc GCC_BL <<
2644 <&gcc GCC_BL <<
2645 clock-names = "core", <<
2646 dmas = <&blsp2_dma 6> <<
2647 dma-names = "tx", "rx <<
2648 pinctrl-names = "defa <<
2649 pinctrl-0 = <&blsp2_s <<
2650 <<
2651 status = "disabled"; <<
2652 #address-cells = <1>; <<
2653 #size-cells = <0>; <<
2654 }; <<
2655 <<
2656 blsp2_spi2: spi@c1b6000 { <<
2657 compatible = "qcom,sp <<
2658 reg = <0x0c1b6000 0x6 <<
2659 interrupts = <GIC_SPI <<
2660 <<
2661 clocks = <&gcc GCC_BL <<
2662 <&gcc GCC_BL <<
2663 clock-names = "core", <<
2664 dmas = <&blsp2_dma 8> <<
2665 dma-names = "tx", "rx <<
2666 pinctrl-names = "defa <<
2667 pinctrl-0 = <&blsp2_s <<
2668 <<
2669 status = "disabled"; <<
2670 #address-cells = <1>; <<
2671 #size-cells = <0>; <<
2672 }; <<
2673 <<
2674 blsp2_spi3: spi@c1b7000 { <<
2675 compatible = "qcom,sp <<
2676 reg = <0x0c1b7000 0x6 <<
2677 interrupts = <GIC_SPI <<
2678 <<
2679 clocks = <&gcc GCC_BL <<
2680 <&gcc GCC_BL <<
2681 clock-names = "core", <<
2682 dmas = <&blsp2_dma 10 <<
2683 dma-names = "tx", "rx <<
2684 pinctrl-names = "defa <<
2685 pinctrl-0 = <&blsp2_s <<
2686 <<
2687 status = "disabled"; <<
2688 #address-cells = <1>; <<
2689 #size-cells = <0>; <<
2690 }; <<
2691 <<
2692 blsp2_spi4: spi@c1b8000 { <<
2693 compatible = "qcom,sp <<
2694 reg = <0x0c1b8000 0x6 <<
2695 interrupts = <GIC_SPI <<
2696 <<
2697 clocks = <&gcc GCC_BL <<
2698 <&gcc GCC_BL <<
2699 clock-names = "core", <<
2700 dmas = <&blsp2_dma 12 <<
2701 dma-names = "tx", "rx <<
2702 pinctrl-names = "defa <<
2703 pinctrl-0 = <&blsp2_s <<
2704 <<
2705 status = "disabled"; <<
2706 #address-cells = <1>; <<
2707 #size-cells = <0>; <<
2708 }; <<
2709 <<
2710 blsp2_spi5: spi@c1b9000 { <<
2711 compatible = "qcom,sp <<
2712 reg = <0x0c1b9000 0x6 <<
2713 interrupts = <GIC_SPI <<
2714 <<
2715 clocks = <&gcc GCC_BL <<
2716 <&gcc GCC_BL <<
2717 clock-names = "core", <<
2718 dmas = <&blsp2_dma 14 <<
2719 dma-names = "tx", "rx <<
2720 pinctrl-names = "defa <<
2721 pinctrl-0 = <&blsp2_s <<
2722 <<
2723 status = "disabled"; <<
2724 #address-cells = <1>; <<
2725 #size-cells = <0>; <<
2726 }; <<
2727 <<
2728 blsp2_spi6: spi@c1ba000 { <<
2729 compatible = "qcom,sp <<
2730 reg = <0x0c1ba000 0x6 <<
2731 interrupts = <GIC_SPI <<
2732 <<
2733 clocks = <&gcc GCC_BL <<
2734 <&gcc GCC_BL <<
2735 clock-names = "core", <<
2736 dmas = <&blsp2_dma 16 <<
2737 dma-names = "tx", "rx <<
2738 pinctrl-names = "defa <<
2739 pinctrl-0 = <&blsp2_s <<
2740 <<
2741 status = "disabled"; <<
2742 #address-cells = <1>; <<
2743 #size-cells = <0>; <<
2744 }; <<
2745 <<
2746 mmcc: clock-controller@c8c000 <<
2747 compatible = "qcom,mm <<
2748 #clock-cells = <1>; <<
2749 #reset-cells = <1>; <<
2750 #power-domain-cells = <<
2751 reg = <0xc8c0000 0x40 <<
2752 <<
2753 clock-names = "xo", <<
2754 "gpll0" <<
2755 "dsi0ds <<
2756 "dsi0by <<
2757 "dsi1ds <<
2758 "dsi1by <<
2759 "hdmipl <<
2760 "dplink <<
2761 "dpvco" <<
2762 "gpll0_ <<
2763 clocks = <&rpmcc RPM_ <<
2764 <&gcc GCC_MM <<
2765 <&mdss_dsi0_ <<
2766 <&mdss_dsi0_ <<
2767 <&mdss_dsi1_ <<
2768 <&mdss_dsi1_ <<
2769 <0>, <<
2770 <0>, <<
2771 <0>, <<
2772 <&gcc GCC_MM <<
2773 }; <<
2774 <<
2775 mdss: display-subsystem@c9000 <<
2776 compatible = "qcom,ms <<
2777 reg = <0x0c900000 0x1 <<
2778 reg-names = "mdss"; <<
2779 <<
2780 interrupts = <GIC_SPI <<
2781 interrupt-controller; <<
2782 #interrupt-cells = <1 <<
2783 <<
2784 clocks = <&mmcc MDSS_ <<
2785 <&mmcc MDSS_ <<
2786 <&mmcc MDSS_ <<
2787 clock-names = "iface" <<
2788 "bus", <<
2789 "core"; <<
2790 <<
2791 power-domains = <&mmc <<
2792 iommus = <&mmss_smmu <<
2793 <<
2794 #address-cells = <1>; <<
2795 #size-cells = <1>; <<
2796 ranges; <<
2797 <<
2798 status = "disabled"; <<
2799 <<
2800 mdss_mdp: display-con <<
2801 compatible = <<
2802 reg = <0x0c90 <<
2803 <0x0c9a <<
2804 <0x0c9b <<
2805 <0x0c9b <<
2806 reg-names = " <<
2807 " <<
2808 " <<
2809 " <<
2810 <<
2811 interrupt-par <<
2812 interrupts = <<
2813 <<
2814 clocks = <&mm <<
2815 <&mm <<
2816 <&mm <<
2817 <&mm <<
2818 <&mm <<
2819 clock-names = <<
2820 <<
2821 <<
2822 <<
2823 <<
2824 <<
2825 assigned-cloc <<
2826 assigned-cloc <<
2827 <<
2828 operating-poi <<
2829 power-domains <<
2830 <<
2831 mdp_opp_table <<
2832 compa <<
2833 <<
2834 opp-1 <<
2835 <<
2836 <<
2837 }; <<
2838 <<
2839 opp-2 <<
2840 <<
2841 <<
2842 }; <<
2843 <<
2844 opp-3 <<
2845 <<
2846 <<
2847 }; <<
2848 <<
2849 opp-4 <<
2850 <<
2851 <<
2852 }; <<
2853 }; <<
2854 <<
2855 ports { <<
2856 #addr <<
2857 #size <<
2858 <<
2859 port@ <<
2860 <<
2861 <<
2862 <<
2863 <<
2864 <<
2865 }; <<
2866 <<
2867 port@ <<
2868 <<
2869 <<
2870 <<
2871 <<
2872 <<
2873 }; <<
2874 }; <<
2875 }; <<
2876 <<
2877 mdss_dsi0: dsi@c99400 <<
2878 compatible = <<
2879 reg = <0x0c99 <<
2880 reg-names = " <<
2881 <<
2882 interrupt-par <<
2883 interrupts = <<
2884 <<
2885 clocks = <&mm <<
2886 <&mm <<
2887 <&mm <<
2888 <&mm <<
2889 <&mm <<
2890 <&mm <<
2891 clock-names = <<
2892 <<
2893 <<
2894 <<
2895 <<
2896 <<
2897 assigned-cloc <<
2898 <<
2899 assigned-cloc <<
2900 <<
2901 <<
2902 operating-poi <<
2903 power-domains <<
2904 <<
2905 phys = <&mdss <<
2906 phy-names = " <<
2907 <<
2908 #address-cell <<
2909 #size-cells = <<
2910 <<
2911 status = "dis <<
2912 <<
2913 ports { <<
2914 #addr <<
2915 #size <<
2916 <<
2917 port@ <<
2918 <<
2919 <<
2920 <<
2921 <<
2922 <<
2923 }; <<
2924 <<
2925 port@ <<
2926 <<
2927 <<
2928 <<
2929 <<
2930 }; <<
2931 }; <<
2932 }; <<
2933 <<
2934 mdss_dsi0_phy: phy@c9 <<
2935 compatible = <<
2936 reg = <0x0c99 <<
2937 <0x0c99 <<
2938 <0x0c99 <<
2939 reg-names = " <<
2940 " <<
2941 " <<
2942 <<
2943 clocks = <&mm <<
2944 <&rp <<
2945 clock-names = <<
2946 <<
2947 #clock-cells <<
2948 #phy-cells = <<
2949 <<
2950 status = "dis <<
2951 }; <<
2952 <<
2953 mdss_dsi1: dsi@c99600 <<
2954 compatible = <<
2955 reg = <0x0c99 <<
2956 reg-names = " <<
2957 <<
2958 interrupt-par <<
2959 interrupts = <<
2960 <<
2961 clocks = <&mm <<
2962 <&mm <<
2963 <&mm <<
2964 <&mm <<
2965 <&mm <<
2966 <&mm <<
2967 clock-names = <<
2968 <<
2969 <<
2970 <<
2971 <<
2972 <<
2973 assigned-cloc <<
2974 <<
2975 assigned-cloc <<
2976 <<
2977 <<
2978 operating-poi <<
2979 power-domains <<
2980 <<
2981 phys = <&mdss <<
2982 phy-names = " <<
2983 <<
2984 #address-cell <<
2985 #size-cells = <<
2986 <<
2987 status = "dis <<
2988 <<
2989 ports { <<
2990 #addr <<
2991 #size <<
2992 <<
2993 port@ <<
2994 <<
2995 <<
2996 <<
2997 <<
2998 <<
2999 }; <<
3000 <<
3001 port@ <<
3002 <<
3003 <<
3004 <<
3005 <<
3006 }; <<
3007 }; <<
3008 }; <<
3009 <<
3010 mdss_dsi1_phy: phy@c9 <<
3011 compatible = <<
3012 reg = <0x0c99 <<
3013 <0x0c99 <<
3014 <0x0c99 <<
3015 reg-names = " <<
3016 " <<
3017 " <<
3018 <<
3019 clocks = <&mm <<
3020 <&rp <<
3021 clock-names = <<
3022 <<
3023 <<
3024 #clock-cells <<
3025 #phy-cells = <<
3026 <<
3027 status = "dis <<
3028 }; <<
3029 }; <<
3030 <<
3031 venus: video-codec@cc00000 { <<
3032 compatible = "qcom,ms <<
3033 reg = <0x0cc00000 0xf <<
3034 interrupts = <GIC_SPI <<
3035 power-domains = <&mmc <<
3036 clocks = <&mmcc VIDEO <<
3037 <&mmcc VIDEO <<
3038 <&mmcc VIDEO <<
3039 <&mmcc VIDEO <<
3040 clock-names = "core", <<
3041 iommus = <&mmss_smmu <<
3042 <&mmss_smmu <<
3043 <&mmss_smmu <<
3044 <&mmss_smmu <<
3045 <&mmss_smmu <<
3046 <&mmss_smmu <<
3047 <&mmss_smmu <<
3048 <&mmss_smmu <<
3049 <&mmss_smmu <<
3050 <&mmss_smmu <<
3051 <&mmss_smmu <<
3052 <&mmss_smmu <<
3053 <&mmss_smmu <<
3054 <&mmss_smmu <<
3055 <&mmss_smmu <<
3056 <&mmss_smmu <<
3057 <&mmss_smmu <<
3058 <&mmss_smmu <<
3059 <&mmss_smmu <<
3060 <&mmss_smmu <<
3061 memory-region = <&ven <<
3062 status = "disabled"; <<
3063 <<
3064 video-decoder { <<
3065 compatible = <<
3066 clocks = <&mm <<
3067 clock-names = <<
3068 power-domains <<
3069 }; <<
3070 <<
3071 video-encoder { <<
3072 compatible = <<
3073 clocks = <&mm <<
3074 clock-names = <<
3075 power-domains <<
3076 }; <<
3077 }; <<
3078 <<
3079 mmss_smmu: iommu@cd00000 { <<
3080 compatible = "qcom,ms <<
3081 reg = <0x0cd00000 0x4 <<
3082 #iommu-cells = <1>; <<
3083 <<
3084 clocks = <&mmcc MNOC_ <<
3085 <&mmcc BIMC_ <<
3086 <&mmcc BIMC_ <<
3087 clock-names = "iface- <<
3088 "iface- <<
3089 "bus-sm <<
3090 <<
3091 #global-interrupts = <<
3092 interrupts = <<
3093 <GIC_SPI 263 <<
3094 <GIC_SPI 266 <<
3095 <GIC_SPI 267 <<
3096 <GIC_SPI 268 <<
3097 <GIC_SPI 244 <<
3098 <GIC_SPI 245 <<
3099 <GIC_SPI 247 <<
3100 <GIC_SPI 248 <<
3101 <GIC_SPI 249 <<
3102 <GIC_SPI 250 <<
3103 <GIC_SPI 251 <<
3104 <GIC_SPI 252 <<
3105 <GIC_SPI 253 <<
3106 <GIC_SPI 254 <<
3107 <GIC_SPI 255 <<
3108 <GIC_SPI 256 <<
3109 <GIC_SPI 260 <<
3110 <GIC_SPI 261 <<
3111 <GIC_SPI 262 <<
3112 <GIC_SPI 272 <<
3113 <<
3114 power-domains = <&mmc <<
3115 }; <<
3116 <<
3117 remoteproc_adsp: remoteproc@1 1974 remoteproc_adsp: remoteproc@17300000 {
3118 compatible = "qcom,ms 1975 compatible = "qcom,msm8998-adsp-pas";
3119 reg = <0x17300000 0x4 1976 reg = <0x17300000 0x4040>;
3120 1977
3121 interrupts-extended = 1978 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
3122 1979 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3123 1980 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3124 1981 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3125 1982 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
3126 interrupt-names = "wd 1983 interrupt-names = "wdog", "fatal", "ready",
3127 "ha 1984 "handover", "stop-ack";
3128 1985
3129 clocks = <&rpmcc RPM_ 1986 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
3130 clock-names = "xo"; 1987 clock-names = "xo";
3131 1988
3132 memory-region = <&ads 1989 memory-region = <&adsp_mem>;
3133 1990
3134 qcom,smem-states = <& 1991 qcom,smem-states = <&adsp_smp2p_out 0>;
3135 qcom,smem-state-names 1992 qcom,smem-state-names = "stop";
3136 1993
3137 power-domains = <&rpm 1994 power-domains = <&rpmpd MSM8998_VDDCX>;
3138 power-domain-names = 1995 power-domain-names = "cx";
3139 1996
3140 status = "disabled"; 1997 status = "disabled";
3141 1998
3142 glink-edge { 1999 glink-edge {
3143 interrupts = 2000 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
3144 label = "lpas 2001 label = "lpass";
3145 qcom,remote-p 2002 qcom,remote-pid = <2>;
3146 mboxes = <&ap 2003 mboxes = <&apcs_glb 9>;
3147 }; 2004 };
3148 }; 2005 };
3149 2006
3150 apcs_glb: mailbox@17911000 { 2007 apcs_glb: mailbox@17911000 {
3151 compatible = "qcom,ms !! 2008 compatible = "qcom,msm8998-apcs-hmss-global";
3152 "qcom,ms <<
3153 reg = <0x17911000 0x1 2009 reg = <0x17911000 0x1000>;
3154 2010
3155 #mbox-cells = <1>; 2011 #mbox-cells = <1>;
3156 }; 2012 };
3157 2013
3158 timer@17920000 { 2014 timer@17920000 {
3159 #address-cells = <1>; 2015 #address-cells = <1>;
3160 #size-cells = <1>; 2016 #size-cells = <1>;
3161 ranges; 2017 ranges;
3162 compatible = "arm,arm 2018 compatible = "arm,armv7-timer-mem";
3163 reg = <0x17920000 0x1 2019 reg = <0x17920000 0x1000>;
3164 2020
3165 frame@17921000 { 2021 frame@17921000 {
3166 frame-number 2022 frame-number = <0>;
3167 interrupts = 2023 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
3168 2024 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
3169 reg = <0x1792 2025 reg = <0x17921000 0x1000>,
3170 <0x1792 2026 <0x17922000 0x1000>;
3171 }; 2027 };
3172 2028
3173 frame@17923000 { 2029 frame@17923000 {
3174 frame-number 2030 frame-number = <1>;
3175 interrupts = 2031 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
3176 reg = <0x1792 2032 reg = <0x17923000 0x1000>;
3177 status = "dis 2033 status = "disabled";
3178 }; 2034 };
3179 2035
3180 frame@17924000 { 2036 frame@17924000 {
3181 frame-number 2037 frame-number = <2>;
3182 interrupts = 2038 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
3183 reg = <0x1792 2039 reg = <0x17924000 0x1000>;
3184 status = "dis 2040 status = "disabled";
3185 }; 2041 };
3186 2042
3187 frame@17925000 { 2043 frame@17925000 {
3188 frame-number 2044 frame-number = <3>;
3189 interrupts = 2045 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3190 reg = <0x1792 2046 reg = <0x17925000 0x1000>;
3191 status = "dis 2047 status = "disabled";
3192 }; 2048 };
3193 2049
3194 frame@17926000 { 2050 frame@17926000 {
3195 frame-number 2051 frame-number = <4>;
3196 interrupts = 2052 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3197 reg = <0x1792 2053 reg = <0x17926000 0x1000>;
3198 status = "dis 2054 status = "disabled";
3199 }; 2055 };
3200 2056
3201 frame@17927000 { 2057 frame@17927000 {
3202 frame-number 2058 frame-number = <5>;
3203 interrupts = 2059 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3204 reg = <0x1792 2060 reg = <0x17927000 0x1000>;
3205 status = "dis 2061 status = "disabled";
3206 }; 2062 };
3207 2063
3208 frame@17928000 { 2064 frame@17928000 {
3209 frame-number 2065 frame-number = <6>;
3210 interrupts = 2066 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
3211 reg = <0x1792 2067 reg = <0x17928000 0x1000>;
3212 status = "dis 2068 status = "disabled";
3213 }; 2069 };
3214 }; 2070 };
3215 2071
3216 intc: interrupt-controller@17 2072 intc: interrupt-controller@17a00000 {
3217 compatible = "arm,gic 2073 compatible = "arm,gic-v3";
3218 reg = <0x17a00000 0x1 2074 reg = <0x17a00000 0x10000>, /* GICD */
3219 <0x17b00000 0x1 2075 <0x17b00000 0x100000>; /* GICR * 8 */
3220 #interrupt-cells = <3 2076 #interrupt-cells = <3>;
3221 #address-cells = <1>; 2077 #address-cells = <1>;
3222 #size-cells = <1>; 2078 #size-cells = <1>;
3223 ranges; 2079 ranges;
3224 interrupt-controller; 2080 interrupt-controller;
3225 #redistributor-region 2081 #redistributor-regions = <1>;
3226 redistributor-stride 2082 redistributor-stride = <0x0 0x20000>;
3227 interrupts = <GIC_PPI 2083 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3228 }; 2084 };
3229 2085
3230 wifi: wifi@18800000 { 2086 wifi: wifi@18800000 {
3231 compatible = "qcom,wc 2087 compatible = "qcom,wcn3990-wifi";
3232 status = "disabled"; 2088 status = "disabled";
3233 reg = <0x18800000 0x8 2089 reg = <0x18800000 0x800000>;
3234 reg-names = "membase" 2090 reg-names = "membase";
3235 memory-region = <&wla 2091 memory-region = <&wlan_msa_mem>;
3236 clocks = <&rpmcc RPM_ 2092 clocks = <&rpmcc RPM_SMD_RF_CLK2_PIN>;
3237 clock-names = "cxo_re 2093 clock-names = "cxo_ref_clk_pin";
3238 interrupts = 2094 interrupts =
3239 <GIC_SPI 413 2095 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
3240 <GIC_SPI 414 2096 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
3241 <GIC_SPI 415 2097 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
3242 <GIC_SPI 416 2098 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
3243 <GIC_SPI 417 2099 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
3244 <GIC_SPI 418 2100 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
3245 <GIC_SPI 420 2101 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
3246 <GIC_SPI 421 2102 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
3247 <GIC_SPI 422 2103 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
3248 <GIC_SPI 423 2104 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
3249 <GIC_SPI 424 2105 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
3250 <GIC_SPI 425 2106 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
3251 iommus = <&anoc2_smmu 2107 iommus = <&anoc2_smmu 0x1900>,
3252 <&anoc2_smmu 2108 <&anoc2_smmu 0x1901>;
3253 qcom,snoc-host-cap-8b 2109 qcom,snoc-host-cap-8bit-quirk;
3254 qcom,no-msa-ready-ind <<
3255 }; 2110 };
3256 }; 2111 };
3257 }; 2112 };
>> 2113
>> 2114 #include "msm8998-pins.dtsi"
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