1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2016, The Linux Foundation. A 2 /* Copyright (c) 2016, The Linux Foundation. All rights reserved. */
3 3
4 #include <dt-bindings/interrupt-controller/arm 4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-msm8998.h 5 #include <dt-bindings/clock/qcom,gcc-msm8998.h>
6 #include <dt-bindings/clock/qcom,gpucc-msm8998 6 #include <dt-bindings/clock/qcom,gpucc-msm8998.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8998. 7 #include <dt-bindings/clock/qcom,mmcc-msm8998.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h> 8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/firmware/qcom,scm.h> 9 #include <dt-bindings/firmware/qcom,scm.h>
10 #include <dt-bindings/power/qcom-rpmpd.h> 10 #include <dt-bindings/power/qcom-rpmpd.h>
11 #include <dt-bindings/gpio/gpio.h> 11 #include <dt-bindings/gpio/gpio.h>
12 12
13 / { 13 / {
14 interrupt-parent = <&intc>; 14 interrupt-parent = <&intc>;
15 15
16 qcom,msm-id = <292 0x0>; 16 qcom,msm-id = <292 0x0>;
17 17
18 #address-cells = <2>; 18 #address-cells = <2>;
19 #size-cells = <2>; 19 #size-cells = <2>;
20 20
21 chosen { }; 21 chosen { };
22 22
23 memory@80000000 { 23 memory@80000000 {
24 device_type = "memory"; 24 device_type = "memory";
25 /* We expect the bootloader to 25 /* We expect the bootloader to fill in the reg */
26 reg = <0x0 0x80000000 0x0 0x0> 26 reg = <0x0 0x80000000 0x0 0x0>;
27 }; 27 };
28 28
29 reserved-memory { 29 reserved-memory {
30 #address-cells = <2>; 30 #address-cells = <2>;
31 #size-cells = <2>; 31 #size-cells = <2>;
32 ranges; 32 ranges;
33 33
34 hyp_mem: memory@85800000 { 34 hyp_mem: memory@85800000 {
35 reg = <0x0 0x85800000 35 reg = <0x0 0x85800000 0x0 0x600000>;
36 no-map; 36 no-map;
37 }; 37 };
38 38
39 xbl_mem: memory@85e00000 { 39 xbl_mem: memory@85e00000 {
40 reg = <0x0 0x85e00000 40 reg = <0x0 0x85e00000 0x0 0x100000>;
41 no-map; 41 no-map;
42 }; 42 };
43 43
44 smem_mem: smem-mem@86000000 { 44 smem_mem: smem-mem@86000000 {
45 reg = <0x0 0x86000000 45 reg = <0x0 0x86000000 0x0 0x200000>;
46 no-map; 46 no-map;
47 }; 47 };
48 48
49 tz_mem: memory@86200000 { 49 tz_mem: memory@86200000 {
50 reg = <0x0 0x86200000 50 reg = <0x0 0x86200000 0x0 0x2d00000>;
51 no-map; 51 no-map;
52 }; 52 };
53 53
54 rmtfs_mem: memory@88f00000 { 54 rmtfs_mem: memory@88f00000 {
55 compatible = "qcom,rmt 55 compatible = "qcom,rmtfs-mem";
56 reg = <0x0 0x88f00000 56 reg = <0x0 0x88f00000 0x0 0x200000>;
57 no-map; 57 no-map;
58 58
59 qcom,client-id = <1>; 59 qcom,client-id = <1>;
60 qcom,vmid = <QCOM_SCM_ 60 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>;
61 }; 61 };
62 62
63 spss_mem: memory@8ab00000 { 63 spss_mem: memory@8ab00000 {
64 reg = <0x0 0x8ab00000 64 reg = <0x0 0x8ab00000 0x0 0x700000>;
65 no-map; 65 no-map;
66 }; 66 };
67 67
68 adsp_mem: memory@8b200000 { 68 adsp_mem: memory@8b200000 {
69 reg = <0x0 0x8b200000 69 reg = <0x0 0x8b200000 0x0 0x1a00000>;
70 no-map; 70 no-map;
71 }; 71 };
72 72
73 mpss_mem: memory@8cc00000 { 73 mpss_mem: memory@8cc00000 {
74 reg = <0x0 0x8cc00000 74 reg = <0x0 0x8cc00000 0x0 0x7000000>;
75 no-map; 75 no-map;
76 }; 76 };
77 77
78 venus_mem: memory@93c00000 { 78 venus_mem: memory@93c00000 {
79 reg = <0x0 0x93c00000 79 reg = <0x0 0x93c00000 0x0 0x500000>;
80 no-map; 80 no-map;
81 }; 81 };
82 82
83 mba_mem: memory@94100000 { 83 mba_mem: memory@94100000 {
84 reg = <0x0 0x94100000 84 reg = <0x0 0x94100000 0x0 0x200000>;
85 no-map; 85 no-map;
86 }; 86 };
87 87
88 slpi_mem: memory@94300000 { 88 slpi_mem: memory@94300000 {
89 reg = <0x0 0x94300000 89 reg = <0x0 0x94300000 0x0 0xf00000>;
90 no-map; 90 no-map;
91 }; 91 };
92 92
93 ipa_fw_mem: memory@95200000 { 93 ipa_fw_mem: memory@95200000 {
94 reg = <0x0 0x95200000 94 reg = <0x0 0x95200000 0x0 0x10000>;
95 no-map; 95 no-map;
96 }; 96 };
97 97
98 ipa_gsi_mem: memory@95210000 { 98 ipa_gsi_mem: memory@95210000 {
99 reg = <0x0 0x95210000 99 reg = <0x0 0x95210000 0x0 0x5000>;
100 no-map; 100 no-map;
101 }; 101 };
102 102
103 gpu_mem: memory@95600000 { 103 gpu_mem: memory@95600000 {
104 reg = <0x0 0x95600000 104 reg = <0x0 0x95600000 0x0 0x100000>;
105 no-map; 105 no-map;
106 }; 106 };
107 107
108 wlan_msa_mem: memory@95700000 108 wlan_msa_mem: memory@95700000 {
109 reg = <0x0 0x95700000 109 reg = <0x0 0x95700000 0x0 0x100000>;
110 no-map; 110 no-map;
111 }; 111 };
112 112
113 mdata_mem: mpss-metadata { 113 mdata_mem: mpss-metadata {
114 alloc-ranges = <0x0 0x 114 alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>;
115 size = <0x0 0x4000>; 115 size = <0x0 0x4000>;
116 no-map; 116 no-map;
117 }; 117 };
118 }; 118 };
119 119
120 clocks { 120 clocks {
121 xo: xo-board { 121 xo: xo-board {
122 compatible = "fixed-cl 122 compatible = "fixed-clock";
123 #clock-cells = <0>; 123 #clock-cells = <0>;
124 clock-frequency = <192 124 clock-frequency = <19200000>;
125 clock-output-names = " 125 clock-output-names = "xo_board";
126 }; 126 };
127 127
128 sleep_clk: sleep-clk { 128 sleep_clk: sleep-clk {
129 compatible = "fixed-cl 129 compatible = "fixed-clock";
130 #clock-cells = <0>; 130 #clock-cells = <0>;
131 clock-frequency = <327 131 clock-frequency = <32764>;
132 }; 132 };
133 }; 133 };
134 134
135 cpus { 135 cpus {
136 #address-cells = <2>; 136 #address-cells = <2>;
137 #size-cells = <0>; 137 #size-cells = <0>;
138 138
139 CPU0: cpu@0 { 139 CPU0: cpu@0 {
140 device_type = "cpu"; 140 device_type = "cpu";
141 compatible = "qcom,kry 141 compatible = "qcom,kryo280";
142 reg = <0x0 0x0>; 142 reg = <0x0 0x0>;
143 enable-method = "psci" 143 enable-method = "psci";
144 capacity-dmips-mhz = < 144 capacity-dmips-mhz = <1024>;
145 cpu-idle-states = <&LI 145 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
146 next-level-cache = <&L 146 next-level-cache = <&L2_0>;
147 L2_0: l2-cache { 147 L2_0: l2-cache {
148 compatible = " 148 compatible = "cache";
149 cache-level = 149 cache-level = <2>;
150 cache-unified; 150 cache-unified;
151 }; 151 };
152 }; 152 };
153 153
154 CPU1: cpu@1 { 154 CPU1: cpu@1 {
155 device_type = "cpu"; 155 device_type = "cpu";
156 compatible = "qcom,kry 156 compatible = "qcom,kryo280";
157 reg = <0x0 0x1>; 157 reg = <0x0 0x1>;
158 enable-method = "psci" 158 enable-method = "psci";
159 capacity-dmips-mhz = < 159 capacity-dmips-mhz = <1024>;
160 cpu-idle-states = <&LI 160 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
161 next-level-cache = <&L 161 next-level-cache = <&L2_0>;
162 }; 162 };
163 163
164 CPU2: cpu@2 { 164 CPU2: cpu@2 {
165 device_type = "cpu"; 165 device_type = "cpu";
166 compatible = "qcom,kry 166 compatible = "qcom,kryo280";
167 reg = <0x0 0x2>; 167 reg = <0x0 0x2>;
168 enable-method = "psci" 168 enable-method = "psci";
169 capacity-dmips-mhz = < 169 capacity-dmips-mhz = <1024>;
170 cpu-idle-states = <&LI 170 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
171 next-level-cache = <&L 171 next-level-cache = <&L2_0>;
172 }; 172 };
173 173
174 CPU3: cpu@3 { 174 CPU3: cpu@3 {
175 device_type = "cpu"; 175 device_type = "cpu";
176 compatible = "qcom,kry 176 compatible = "qcom,kryo280";
177 reg = <0x0 0x3>; 177 reg = <0x0 0x3>;
178 enable-method = "psci" 178 enable-method = "psci";
179 capacity-dmips-mhz = < 179 capacity-dmips-mhz = <1024>;
180 cpu-idle-states = <&LI 180 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
181 next-level-cache = <&L 181 next-level-cache = <&L2_0>;
182 }; 182 };
183 183
184 CPU4: cpu@100 { 184 CPU4: cpu@100 {
185 device_type = "cpu"; 185 device_type = "cpu";
186 compatible = "qcom,kry 186 compatible = "qcom,kryo280";
187 reg = <0x0 0x100>; 187 reg = <0x0 0x100>;
188 enable-method = "psci" 188 enable-method = "psci";
189 capacity-dmips-mhz = < 189 capacity-dmips-mhz = <1536>;
190 cpu-idle-states = <&BI 190 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
191 next-level-cache = <&L 191 next-level-cache = <&L2_1>;
192 L2_1: l2-cache { 192 L2_1: l2-cache {
193 compatible = " 193 compatible = "cache";
194 cache-level = 194 cache-level = <2>;
195 cache-unified; 195 cache-unified;
196 }; 196 };
197 }; 197 };
198 198
199 CPU5: cpu@101 { 199 CPU5: cpu@101 {
200 device_type = "cpu"; 200 device_type = "cpu";
201 compatible = "qcom,kry 201 compatible = "qcom,kryo280";
202 reg = <0x0 0x101>; 202 reg = <0x0 0x101>;
203 enable-method = "psci" 203 enable-method = "psci";
204 capacity-dmips-mhz = < 204 capacity-dmips-mhz = <1536>;
205 cpu-idle-states = <&BI 205 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
206 next-level-cache = <&L 206 next-level-cache = <&L2_1>;
207 }; 207 };
208 208
209 CPU6: cpu@102 { 209 CPU6: cpu@102 {
210 device_type = "cpu"; 210 device_type = "cpu";
211 compatible = "qcom,kry 211 compatible = "qcom,kryo280";
212 reg = <0x0 0x102>; 212 reg = <0x0 0x102>;
213 enable-method = "psci" 213 enable-method = "psci";
214 capacity-dmips-mhz = < 214 capacity-dmips-mhz = <1536>;
215 cpu-idle-states = <&BI 215 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
216 next-level-cache = <&L 216 next-level-cache = <&L2_1>;
217 }; 217 };
218 218
219 CPU7: cpu@103 { 219 CPU7: cpu@103 {
220 device_type = "cpu"; 220 device_type = "cpu";
221 compatible = "qcom,kry 221 compatible = "qcom,kryo280";
222 reg = <0x0 0x103>; 222 reg = <0x0 0x103>;
223 enable-method = "psci" 223 enable-method = "psci";
224 capacity-dmips-mhz = < 224 capacity-dmips-mhz = <1536>;
225 cpu-idle-states = <&BI 225 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
226 next-level-cache = <&L 226 next-level-cache = <&L2_1>;
227 }; 227 };
228 228
229 cpu-map { 229 cpu-map {
230 cluster0 { 230 cluster0 {
231 core0 { 231 core0 {
232 cpu = 232 cpu = <&CPU0>;
233 }; 233 };
234 234
235 core1 { 235 core1 {
236 cpu = 236 cpu = <&CPU1>;
237 }; 237 };
238 238
239 core2 { 239 core2 {
240 cpu = 240 cpu = <&CPU2>;
241 }; 241 };
242 242
243 core3 { 243 core3 {
244 cpu = 244 cpu = <&CPU3>;
245 }; 245 };
246 }; 246 };
247 247
248 cluster1 { 248 cluster1 {
249 core0 { 249 core0 {
250 cpu = 250 cpu = <&CPU4>;
251 }; 251 };
252 252
253 core1 { 253 core1 {
254 cpu = 254 cpu = <&CPU5>;
255 }; 255 };
256 256
257 core2 { 257 core2 {
258 cpu = 258 cpu = <&CPU6>;
259 }; 259 };
260 260
261 core3 { 261 core3 {
262 cpu = 262 cpu = <&CPU7>;
263 }; 263 };
264 }; 264 };
265 }; 265 };
266 266
267 idle-states { 267 idle-states {
268 entry-method = "psci"; 268 entry-method = "psci";
269 269
270 LITTLE_CPU_SLEEP_0: cp 270 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
271 compatible = " 271 compatible = "arm,idle-state";
272 idle-state-nam 272 idle-state-name = "little-retention";
273 /* CPU Retenti 273 /* CPU Retention (C2D), L2 Active */
274 arm,psci-suspe 274 arm,psci-suspend-param = <0x00000002>;
275 entry-latency- 275 entry-latency-us = <81>;
276 exit-latency-u 276 exit-latency-us = <86>;
277 min-residency- 277 min-residency-us = <504>;
278 }; 278 };
279 279
280 LITTLE_CPU_SLEEP_1: cp 280 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
281 compatible = " 281 compatible = "arm,idle-state";
282 idle-state-nam 282 idle-state-name = "little-power-collapse";
283 /* CPU + L2 Po 283 /* CPU + L2 Power Collapse (C3, D4) */
284 arm,psci-suspe 284 arm,psci-suspend-param = <0x40000003>;
285 entry-latency- 285 entry-latency-us = <814>;
286 exit-latency-u 286 exit-latency-us = <4562>;
287 min-residency- 287 min-residency-us = <9183>;
288 local-timer-st 288 local-timer-stop;
289 }; 289 };
290 290
291 BIG_CPU_SLEEP_0: cpu-s 291 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
292 compatible = " 292 compatible = "arm,idle-state";
293 idle-state-nam 293 idle-state-name = "big-retention";
294 /* CPU Retenti 294 /* CPU Retention (C2D), L2 Active */
295 arm,psci-suspe 295 arm,psci-suspend-param = <0x00000002>;
296 entry-latency- 296 entry-latency-us = <79>;
297 exit-latency-u 297 exit-latency-us = <82>;
298 min-residency- 298 min-residency-us = <1302>;
299 }; 299 };
300 300
301 BIG_CPU_SLEEP_1: cpu-s 301 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
302 compatible = " 302 compatible = "arm,idle-state";
303 idle-state-nam 303 idle-state-name = "big-power-collapse";
304 /* CPU + L2 Po 304 /* CPU + L2 Power Collapse (C3, D4) */
305 arm,psci-suspe 305 arm,psci-suspend-param = <0x40000003>;
306 entry-latency- 306 entry-latency-us = <724>;
307 exit-latency-u 307 exit-latency-us = <2027>;
308 min-residency- 308 min-residency-us = <9419>;
309 local-timer-st 309 local-timer-stop;
310 }; 310 };
311 }; 311 };
312 }; 312 };
313 313
314 firmware { 314 firmware {
315 scm { 315 scm {
316 compatible = "qcom,scm 316 compatible = "qcom,scm-msm8998", "qcom,scm";
317 }; 317 };
318 }; 318 };
319 319
320 dsi_opp_table: opp-table-dsi { 320 dsi_opp_table: opp-table-dsi {
321 compatible = "operating-points 321 compatible = "operating-points-v2";
322 322
323 opp-131250000 { 323 opp-131250000 {
324 opp-hz = /bits/ 64 <13 324 opp-hz = /bits/ 64 <131250000>;
325 required-opps = <&rpmp 325 required-opps = <&rpmpd_opp_low_svs>;
326 }; 326 };
327 327
328 opp-210000000 { 328 opp-210000000 {
329 opp-hz = /bits/ 64 <21 329 opp-hz = /bits/ 64 <210000000>;
330 required-opps = <&rpmp 330 required-opps = <&rpmpd_opp_svs>;
331 }; 331 };
332 332
333 opp-312500000 { 333 opp-312500000 {
334 opp-hz = /bits/ 64 <31 334 opp-hz = /bits/ 64 <312500000>;
335 required-opps = <&rpmp 335 required-opps = <&rpmpd_opp_nom>;
336 }; 336 };
337 }; 337 };
338 338
339 psci { 339 psci {
340 compatible = "arm,psci-1.0"; 340 compatible = "arm,psci-1.0";
341 method = "smc"; 341 method = "smc";
342 }; 342 };
343 343
344 rpm: remoteproc { 344 rpm: remoteproc {
345 compatible = "qcom,msm8998-rpm 345 compatible = "qcom,msm8998-rpm-proc", "qcom,rpm-proc";
346 346
347 glink-edge { 347 glink-edge {
348 compatible = "qcom,gli 348 compatible = "qcom,glink-rpm";
349 349
350 interrupts = <GIC_SPI 350 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
351 qcom,rpm-msg-ram = <&r 351 qcom,rpm-msg-ram = <&rpm_msg_ram>;
352 mboxes = <&apcs_glb 0> 352 mboxes = <&apcs_glb 0>;
353 353
354 rpm_requests: rpm-requ 354 rpm_requests: rpm-requests {
355 compatible = " !! 355 compatible = "qcom,rpm-msm8998";
356 qcom,glink-cha 356 qcom,glink-channels = "rpm_requests";
357 357
358 rpmcc: clock-c 358 rpmcc: clock-controller {
359 compat 359 compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc";
360 clocks 360 clocks = <&xo>;
361 clock- 361 clock-names = "xo";
362 #clock 362 #clock-cells = <1>;
363 }; 363 };
364 364
365 rpmpd: power-c 365 rpmpd: power-controller {
366 compat 366 compatible = "qcom,msm8998-rpmpd";
367 #power 367 #power-domain-cells = <1>;
368 operat 368 operating-points-v2 = <&rpmpd_opp_table>;
369 369
370 rpmpd_ 370 rpmpd_opp_table: opp-table {
371 371 compatible = "operating-points-v2";
372 372
373 373 rpmpd_opp_ret: opp1 {
374 374 opp-level = <RPM_SMD_LEVEL_RETENTION>;
375 375 };
376 376
377 377 rpmpd_opp_ret_plus: opp2 {
378 378 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
379 379 };
380 380
381 381 rpmpd_opp_min_svs: opp3 {
382 382 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
383 383 };
384 384
385 385 rpmpd_opp_low_svs: opp4 {
386 386 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
387 387 };
388 388
389 389 rpmpd_opp_svs: opp5 {
390 390 opp-level = <RPM_SMD_LEVEL_SVS>;
391 391 };
392 392
393 393 rpmpd_opp_svs_plus: opp6 {
394 394 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
395 395 };
396 396
397 397 rpmpd_opp_nom: opp7 {
398 398 opp-level = <RPM_SMD_LEVEL_NOM>;
399 399 };
400 400
401 401 rpmpd_opp_nom_plus: opp8 {
402 402 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
403 403 };
404 404
405 405 rpmpd_opp_turbo: opp9 {
406 406 opp-level = <RPM_SMD_LEVEL_TURBO>;
407 407 };
408 408
409 409 rpmpd_opp_turbo_plus: opp10 {
410 410 opp-level = <RPM_SMD_LEVEL_BINNING>;
411 411 };
412 }; 412 };
413 }; 413 };
414 }; 414 };
415 }; 415 };
416 }; 416 };
417 417
418 smem { 418 smem {
419 compatible = "qcom,smem"; 419 compatible = "qcom,smem";
420 memory-region = <&smem_mem>; 420 memory-region = <&smem_mem>;
421 hwlocks = <&tcsr_mutex 3>; 421 hwlocks = <&tcsr_mutex 3>;
422 }; 422 };
423 423
424 smp2p-lpass { 424 smp2p-lpass {
425 compatible = "qcom,smp2p"; 425 compatible = "qcom,smp2p";
426 qcom,smem = <443>, <429>; 426 qcom,smem = <443>, <429>;
427 427
428 interrupts = <GIC_SPI 158 IRQ_ 428 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
429 429
430 mboxes = <&apcs_glb 10>; 430 mboxes = <&apcs_glb 10>;
431 431
432 qcom,local-pid = <0>; 432 qcom,local-pid = <0>;
433 qcom,remote-pid = <2>; 433 qcom,remote-pid = <2>;
434 434
435 adsp_smp2p_out: master-kernel 435 adsp_smp2p_out: master-kernel {
436 qcom,entry-name = "mas 436 qcom,entry-name = "master-kernel";
437 #qcom,smem-state-cells 437 #qcom,smem-state-cells = <1>;
438 }; 438 };
439 439
440 adsp_smp2p_in: slave-kernel { 440 adsp_smp2p_in: slave-kernel {
441 qcom,entry-name = "sla 441 qcom,entry-name = "slave-kernel";
442 442
443 interrupt-controller; 443 interrupt-controller;
444 #interrupt-cells = <2> 444 #interrupt-cells = <2>;
445 }; 445 };
446 }; 446 };
447 447
448 smp2p-mpss { 448 smp2p-mpss {
449 compatible = "qcom,smp2p"; 449 compatible = "qcom,smp2p";
450 qcom,smem = <435>, <428>; 450 qcom,smem = <435>, <428>;
451 interrupts = <GIC_SPI 451 IRQ_ 451 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
452 mboxes = <&apcs_glb 14>; 452 mboxes = <&apcs_glb 14>;
453 qcom,local-pid = <0>; 453 qcom,local-pid = <0>;
454 qcom,remote-pid = <1>; 454 qcom,remote-pid = <1>;
455 455
456 modem_smp2p_out: master-kernel 456 modem_smp2p_out: master-kernel {
457 qcom,entry-name = "mas 457 qcom,entry-name = "master-kernel";
458 #qcom,smem-state-cells 458 #qcom,smem-state-cells = <1>;
459 }; 459 };
460 460
461 modem_smp2p_in: slave-kernel { 461 modem_smp2p_in: slave-kernel {
462 qcom,entry-name = "sla 462 qcom,entry-name = "slave-kernel";
463 interrupt-controller; 463 interrupt-controller;
464 #interrupt-cells = <2> 464 #interrupt-cells = <2>;
465 }; 465 };
466 }; 466 };
467 467
468 smp2p-slpi { 468 smp2p-slpi {
469 compatible = "qcom,smp2p"; 469 compatible = "qcom,smp2p";
470 qcom,smem = <481>, <430>; 470 qcom,smem = <481>, <430>;
471 interrupts = <GIC_SPI 178 IRQ_ 471 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
472 mboxes = <&apcs_glb 26>; 472 mboxes = <&apcs_glb 26>;
473 qcom,local-pid = <0>; 473 qcom,local-pid = <0>;
474 qcom,remote-pid = <3>; 474 qcom,remote-pid = <3>;
475 475
476 slpi_smp2p_out: master-kernel 476 slpi_smp2p_out: master-kernel {
477 qcom,entry-name = "mas 477 qcom,entry-name = "master-kernel";
478 #qcom,smem-state-cells 478 #qcom,smem-state-cells = <1>;
479 }; 479 };
480 480
481 slpi_smp2p_in: slave-kernel { 481 slpi_smp2p_in: slave-kernel {
482 qcom,entry-name = "sla 482 qcom,entry-name = "slave-kernel";
483 interrupt-controller; 483 interrupt-controller;
484 #interrupt-cells = <2> 484 #interrupt-cells = <2>;
485 }; 485 };
486 }; 486 };
487 487
488 thermal-zones { 488 thermal-zones {
489 cpu0-thermal { 489 cpu0-thermal {
490 polling-delay-passive 490 polling-delay-passive = <250>;
>> 491 polling-delay = <1000>;
491 492
492 thermal-sensors = <&ts 493 thermal-sensors = <&tsens0 1>;
493 494
494 trips { 495 trips {
495 cpu0_alert0: t 496 cpu0_alert0: trip-point0 {
496 temper 497 temperature = <75000>;
497 hyster 498 hysteresis = <2000>;
498 type = 499 type = "passive";
499 }; 500 };
500 501
501 cpu0_crit: cpu 502 cpu0_crit: cpu-crit {
502 temper 503 temperature = <110000>;
503 hyster 504 hysteresis = <2000>;
504 type = 505 type = "critical";
505 }; 506 };
506 }; 507 };
507 }; 508 };
508 509
509 cpu1-thermal { 510 cpu1-thermal {
510 polling-delay-passive 511 polling-delay-passive = <250>;
>> 512 polling-delay = <1000>;
511 513
512 thermal-sensors = <&ts 514 thermal-sensors = <&tsens0 2>;
513 515
514 trips { 516 trips {
515 cpu1_alert0: t 517 cpu1_alert0: trip-point0 {
516 temper 518 temperature = <75000>;
517 hyster 519 hysteresis = <2000>;
518 type = 520 type = "passive";
519 }; 521 };
520 522
521 cpu1_crit: cpu 523 cpu1_crit: cpu-crit {
522 temper 524 temperature = <110000>;
523 hyster 525 hysteresis = <2000>;
524 type = 526 type = "critical";
525 }; 527 };
526 }; 528 };
527 }; 529 };
528 530
529 cpu2-thermal { 531 cpu2-thermal {
530 polling-delay-passive 532 polling-delay-passive = <250>;
>> 533 polling-delay = <1000>;
531 534
532 thermal-sensors = <&ts 535 thermal-sensors = <&tsens0 3>;
533 536
534 trips { 537 trips {
535 cpu2_alert0: t 538 cpu2_alert0: trip-point0 {
536 temper 539 temperature = <75000>;
537 hyster 540 hysteresis = <2000>;
538 type = 541 type = "passive";
539 }; 542 };
540 543
541 cpu2_crit: cpu 544 cpu2_crit: cpu-crit {
542 temper 545 temperature = <110000>;
543 hyster 546 hysteresis = <2000>;
544 type = 547 type = "critical";
545 }; 548 };
546 }; 549 };
547 }; 550 };
548 551
549 cpu3-thermal { 552 cpu3-thermal {
550 polling-delay-passive 553 polling-delay-passive = <250>;
>> 554 polling-delay = <1000>;
551 555
552 thermal-sensors = <&ts 556 thermal-sensors = <&tsens0 4>;
553 557
554 trips { 558 trips {
555 cpu3_alert0: t 559 cpu3_alert0: trip-point0 {
556 temper 560 temperature = <75000>;
557 hyster 561 hysteresis = <2000>;
558 type = 562 type = "passive";
559 }; 563 };
560 564
561 cpu3_crit: cpu 565 cpu3_crit: cpu-crit {
562 temper 566 temperature = <110000>;
563 hyster 567 hysteresis = <2000>;
564 type = 568 type = "critical";
565 }; 569 };
566 }; 570 };
567 }; 571 };
568 572
569 cpu4-thermal { 573 cpu4-thermal {
570 polling-delay-passive 574 polling-delay-passive = <250>;
>> 575 polling-delay = <1000>;
571 576
572 thermal-sensors = <&ts 577 thermal-sensors = <&tsens0 7>;
573 578
574 trips { 579 trips {
575 cpu4_alert0: t 580 cpu4_alert0: trip-point0 {
576 temper 581 temperature = <75000>;
577 hyster 582 hysteresis = <2000>;
578 type = 583 type = "passive";
579 }; 584 };
580 585
581 cpu4_crit: cpu 586 cpu4_crit: cpu-crit {
582 temper 587 temperature = <110000>;
583 hyster 588 hysteresis = <2000>;
584 type = 589 type = "critical";
585 }; 590 };
586 }; 591 };
587 }; 592 };
588 593
589 cpu5-thermal { 594 cpu5-thermal {
590 polling-delay-passive 595 polling-delay-passive = <250>;
>> 596 polling-delay = <1000>;
591 597
592 thermal-sensors = <&ts 598 thermal-sensors = <&tsens0 8>;
593 599
594 trips { 600 trips {
595 cpu5_alert0: t 601 cpu5_alert0: trip-point0 {
596 temper 602 temperature = <75000>;
597 hyster 603 hysteresis = <2000>;
598 type = 604 type = "passive";
599 }; 605 };
600 606
601 cpu5_crit: cpu 607 cpu5_crit: cpu-crit {
602 temper 608 temperature = <110000>;
603 hyster 609 hysteresis = <2000>;
604 type = 610 type = "critical";
605 }; 611 };
606 }; 612 };
607 }; 613 };
608 614
609 cpu6-thermal { 615 cpu6-thermal {
610 polling-delay-passive 616 polling-delay-passive = <250>;
>> 617 polling-delay = <1000>;
611 618
612 thermal-sensors = <&ts 619 thermal-sensors = <&tsens0 9>;
613 620
614 trips { 621 trips {
615 cpu6_alert0: t 622 cpu6_alert0: trip-point0 {
616 temper 623 temperature = <75000>;
617 hyster 624 hysteresis = <2000>;
618 type = 625 type = "passive";
619 }; 626 };
620 627
621 cpu6_crit: cpu 628 cpu6_crit: cpu-crit {
622 temper 629 temperature = <110000>;
623 hyster 630 hysteresis = <2000>;
624 type = 631 type = "critical";
625 }; 632 };
626 }; 633 };
627 }; 634 };
628 635
629 cpu7-thermal { 636 cpu7-thermal {
630 polling-delay-passive 637 polling-delay-passive = <250>;
>> 638 polling-delay = <1000>;
631 639
632 thermal-sensors = <&ts 640 thermal-sensors = <&tsens0 10>;
633 641
634 trips { 642 trips {
635 cpu7_alert0: t 643 cpu7_alert0: trip-point0 {
636 temper 644 temperature = <75000>;
637 hyster 645 hysteresis = <2000>;
638 type = 646 type = "passive";
639 }; 647 };
640 648
641 cpu7_crit: cpu 649 cpu7_crit: cpu-crit {
642 temper 650 temperature = <110000>;
643 hyster 651 hysteresis = <2000>;
644 type = 652 type = "critical";
645 }; 653 };
646 }; 654 };
647 }; 655 };
648 656
649 gpu-bottom-thermal { 657 gpu-bottom-thermal {
650 polling-delay-passive 658 polling-delay-passive = <250>;
>> 659 polling-delay = <1000>;
651 660
652 thermal-sensors = <&ts 661 thermal-sensors = <&tsens0 12>;
653 662
654 trips { 663 trips {
655 gpu1_alert0: t 664 gpu1_alert0: trip-point0 {
656 temper 665 temperature = <90000>;
657 hyster 666 hysteresis = <2000>;
658 type = 667 type = "hot";
659 }; 668 };
660 }; 669 };
661 }; 670 };
662 671
663 gpu-top-thermal { 672 gpu-top-thermal {
664 polling-delay-passive 673 polling-delay-passive = <250>;
>> 674 polling-delay = <1000>;
665 675
666 thermal-sensors = <&ts 676 thermal-sensors = <&tsens0 13>;
667 677
668 trips { 678 trips {
669 gpu2_alert0: t 679 gpu2_alert0: trip-point0 {
670 temper 680 temperature = <90000>;
671 hyster 681 hysteresis = <2000>;
672 type = 682 type = "hot";
673 }; 683 };
674 }; 684 };
675 }; 685 };
676 686
677 clust0-mhm-thermal { 687 clust0-mhm-thermal {
678 polling-delay-passive 688 polling-delay-passive = <250>;
>> 689 polling-delay = <1000>;
679 690
680 thermal-sensors = <&ts 691 thermal-sensors = <&tsens0 5>;
681 692
682 trips { 693 trips {
683 cluster0_mhm_a 694 cluster0_mhm_alert0: trip-point0 {
684 temper 695 temperature = <90000>;
685 hyster 696 hysteresis = <2000>;
686 type = 697 type = "hot";
687 }; 698 };
688 }; 699 };
689 }; 700 };
690 701
691 clust1-mhm-thermal { 702 clust1-mhm-thermal {
692 polling-delay-passive 703 polling-delay-passive = <250>;
>> 704 polling-delay = <1000>;
693 705
694 thermal-sensors = <&ts 706 thermal-sensors = <&tsens0 6>;
695 707
696 trips { 708 trips {
697 cluster1_mhm_a 709 cluster1_mhm_alert0: trip-point0 {
698 temper 710 temperature = <90000>;
699 hyster 711 hysteresis = <2000>;
700 type = 712 type = "hot";
701 }; 713 };
702 }; 714 };
703 }; 715 };
704 716
705 cluster1-l2-thermal { 717 cluster1-l2-thermal {
706 polling-delay-passive 718 polling-delay-passive = <250>;
>> 719 polling-delay = <1000>;
707 720
708 thermal-sensors = <&ts 721 thermal-sensors = <&tsens0 11>;
709 722
710 trips { 723 trips {
711 cluster1_l2_al 724 cluster1_l2_alert0: trip-point0 {
712 temper 725 temperature = <90000>;
713 hyster 726 hysteresis = <2000>;
714 type = 727 type = "hot";
715 }; 728 };
716 }; 729 };
717 }; 730 };
718 731
719 modem-thermal { 732 modem-thermal {
720 polling-delay-passive 733 polling-delay-passive = <250>;
>> 734 polling-delay = <1000>;
721 735
722 thermal-sensors = <&ts 736 thermal-sensors = <&tsens1 1>;
723 737
724 trips { 738 trips {
725 modem_alert0: 739 modem_alert0: trip-point0 {
726 temper 740 temperature = <90000>;
727 hyster 741 hysteresis = <2000>;
728 type = 742 type = "hot";
729 }; 743 };
730 }; 744 };
731 }; 745 };
732 746
733 mem-thermal { 747 mem-thermal {
734 polling-delay-passive 748 polling-delay-passive = <250>;
>> 749 polling-delay = <1000>;
735 750
736 thermal-sensors = <&ts 751 thermal-sensors = <&tsens1 2>;
737 752
738 trips { 753 trips {
739 mem_alert0: tr 754 mem_alert0: trip-point0 {
740 temper 755 temperature = <90000>;
741 hyster 756 hysteresis = <2000>;
742 type = 757 type = "hot";
743 }; 758 };
744 }; 759 };
745 }; 760 };
746 761
747 wlan-thermal { 762 wlan-thermal {
748 polling-delay-passive 763 polling-delay-passive = <250>;
>> 764 polling-delay = <1000>;
749 765
750 thermal-sensors = <&ts 766 thermal-sensors = <&tsens1 3>;
751 767
752 trips { 768 trips {
753 wlan_alert0: t 769 wlan_alert0: trip-point0 {
754 temper 770 temperature = <90000>;
755 hyster 771 hysteresis = <2000>;
756 type = 772 type = "hot";
757 }; 773 };
758 }; 774 };
759 }; 775 };
760 776
761 q6-dsp-thermal { 777 q6-dsp-thermal {
762 polling-delay-passive 778 polling-delay-passive = <250>;
>> 779 polling-delay = <1000>;
763 780
764 thermal-sensors = <&ts 781 thermal-sensors = <&tsens1 4>;
765 782
766 trips { 783 trips {
767 q6_dsp_alert0: 784 q6_dsp_alert0: trip-point0 {
768 temper 785 temperature = <90000>;
769 hyster 786 hysteresis = <2000>;
770 type = 787 type = "hot";
771 }; 788 };
772 }; 789 };
773 }; 790 };
774 791
775 camera-thermal { 792 camera-thermal {
776 polling-delay-passive 793 polling-delay-passive = <250>;
>> 794 polling-delay = <1000>;
777 795
778 thermal-sensors = <&ts 796 thermal-sensors = <&tsens1 5>;
779 797
780 trips { 798 trips {
781 camera_alert0: 799 camera_alert0: trip-point0 {
782 temper 800 temperature = <90000>;
783 hyster 801 hysteresis = <2000>;
784 type = 802 type = "hot";
785 }; 803 };
786 }; 804 };
787 }; 805 };
788 806
789 multimedia-thermal { 807 multimedia-thermal {
790 polling-delay-passive 808 polling-delay-passive = <250>;
>> 809 polling-delay = <1000>;
791 810
792 thermal-sensors = <&ts 811 thermal-sensors = <&tsens1 6>;
793 812
794 trips { 813 trips {
795 multimedia_ale 814 multimedia_alert0: trip-point0 {
796 temper 815 temperature = <90000>;
797 hyster 816 hysteresis = <2000>;
798 type = 817 type = "hot";
799 }; 818 };
800 }; 819 };
801 }; 820 };
802 }; 821 };
803 822
804 timer { 823 timer {
805 compatible = "arm,armv8-timer" 824 compatible = "arm,armv8-timer";
806 interrupts = <GIC_PPI 1 IRQ_TY 825 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
807 <GIC_PPI 2 IRQ_TY 826 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
808 <GIC_PPI 3 IRQ_TY 827 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
809 <GIC_PPI 0 IRQ_TY 828 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
810 }; 829 };
811 830
812 soc: soc@0 { 831 soc: soc@0 {
813 #address-cells = <1>; 832 #address-cells = <1>;
814 #size-cells = <1>; 833 #size-cells = <1>;
815 ranges = <0 0 0 0xffffffff>; 834 ranges = <0 0 0 0xffffffff>;
816 compatible = "simple-bus"; 835 compatible = "simple-bus";
817 836
818 gcc: clock-controller@100000 { 837 gcc: clock-controller@100000 {
819 compatible = "qcom,gcc 838 compatible = "qcom,gcc-msm8998";
820 #clock-cells = <1>; 839 #clock-cells = <1>;
821 #reset-cells = <1>; 840 #reset-cells = <1>;
822 #power-domain-cells = 841 #power-domain-cells = <1>;
823 reg = <0x00100000 0xb0 842 reg = <0x00100000 0xb0000>;
824 843
825 clock-names = "xo", "s 844 clock-names = "xo", "sleep_clk";
826 clocks = <&rpmcc RPM_S 845 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>;
827 846
828 /* 847 /*
829 * The hypervisor typi 848 * The hypervisor typically configures the memory region where these clocks
830 * reside as read-only 849 * reside as read-only for the HLOS. If the HLOS tried to enable or disable
831 * these clocks on a d 850 * these clocks on a device with such configuration (e.g. because they are
832 * enabled but unused 851 * enabled but unused during boot-up), the device will most likely decide
833 * to reboot. 852 * to reboot.
834 * In light of that, w 853 * In light of that, we are conservative here and we list all such clocks
835 * as protected. The b 854 * as protected. The board dts (or a user-supplied dts) can override the
836 * list of protected c 855 * list of protected clocks if it differs from the norm, and it is in fact
837 * desired for the HLO 856 * desired for the HLOS to manage these clocks
838 */ 857 */
839 protected-clocks = <AG 858 protected-clocks = <AGGRE2_SNOC_NORTH_AXI>,
840 <SS 859 <SSC_XO>,
841 <SS 860 <SSC_CNOC_AHBS_CLK>;
842 }; 861 };
843 862
844 rpm_msg_ram: sram@778000 { 863 rpm_msg_ram: sram@778000 {
845 compatible = "qcom,rpm 864 compatible = "qcom,rpm-msg-ram";
846 reg = <0x00778000 0x70 865 reg = <0x00778000 0x7000>;
847 }; 866 };
848 867
849 qfprom: qfprom@784000 { 868 qfprom: qfprom@784000 {
850 compatible = "qcom,msm 869 compatible = "qcom,msm8998-qfprom", "qcom,qfprom";
851 reg = <0x00784000 0x62 870 reg = <0x00784000 0x621c>;
852 #address-cells = <1>; 871 #address-cells = <1>;
853 #size-cells = <1>; 872 #size-cells = <1>;
854 873
855 qusb2_hstx_trim: hstx- 874 qusb2_hstx_trim: hstx-trim@23a {
856 reg = <0x23a 0 875 reg = <0x23a 0x1>;
857 bits = <0 4>; 876 bits = <0 4>;
858 }; 877 };
859 }; 878 };
860 879
861 tsens0: thermal@10ab000 { 880 tsens0: thermal@10ab000 {
862 compatible = "qcom,msm 881 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
863 reg = <0x010ab000 0x10 882 reg = <0x010ab000 0x1000>, /* TM */
864 <0x010aa000 0x10 883 <0x010aa000 0x1000>; /* SROT */
865 #qcom,sensors = <14>; 884 #qcom,sensors = <14>;
866 interrupts = <GIC_SPI 885 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
867 <GIC_SPI 886 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
868 interrupt-names = "upl 887 interrupt-names = "uplow", "critical";
869 #thermal-sensor-cells 888 #thermal-sensor-cells = <1>;
870 }; 889 };
871 890
872 tsens1: thermal@10ae000 { 891 tsens1: thermal@10ae000 {
873 compatible = "qcom,msm 892 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
874 reg = <0x010ae000 0x10 893 reg = <0x010ae000 0x1000>, /* TM */
875 <0x010ad000 0x10 894 <0x010ad000 0x1000>; /* SROT */
876 #qcom,sensors = <8>; 895 #qcom,sensors = <8>;
877 interrupts = <GIC_SPI 896 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
878 <GIC_SPI 897 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
879 interrupt-names = "upl 898 interrupt-names = "uplow", "critical";
880 #thermal-sensor-cells 899 #thermal-sensor-cells = <1>;
881 }; 900 };
882 901
883 anoc1_smmu: iommu@1680000 { 902 anoc1_smmu: iommu@1680000 {
884 compatible = "qcom,msm 903 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
885 reg = <0x01680000 0x10 904 reg = <0x01680000 0x10000>;
886 #iommu-cells = <1>; 905 #iommu-cells = <1>;
887 906
888 #global-interrupts = < 907 #global-interrupts = <0>;
889 interrupts = 908 interrupts =
890 <GIC_SPI 364 I 909 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
891 <GIC_SPI 365 I 910 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
892 <GIC_SPI 366 I 911 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
893 <GIC_SPI 367 I 912 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
894 <GIC_SPI 368 I 913 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
895 <GIC_SPI 369 I 914 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>;
896 }; 915 };
897 916
898 anoc2_smmu: iommu@16c0000 { 917 anoc2_smmu: iommu@16c0000 {
899 compatible = "qcom,msm 918 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
900 reg = <0x016c0000 0x40 919 reg = <0x016c0000 0x40000>;
901 #iommu-cells = <1>; 920 #iommu-cells = <1>;
902 921
903 #global-interrupts = < 922 #global-interrupts = <0>;
904 interrupts = 923 interrupts =
905 <GIC_SPI 373 I 924 <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>,
906 <GIC_SPI 374 I 925 <GIC_SPI 374 IRQ_TYPE_EDGE_RISING>,
907 <GIC_SPI 375 I 926 <GIC_SPI 375 IRQ_TYPE_EDGE_RISING>,
908 <GIC_SPI 376 I 927 <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>,
909 <GIC_SPI 377 I 928 <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>,
910 <GIC_SPI 378 I 929 <GIC_SPI 378 IRQ_TYPE_EDGE_RISING>,
911 <GIC_SPI 462 I 930 <GIC_SPI 462 IRQ_TYPE_EDGE_RISING>,
912 <GIC_SPI 463 I 931 <GIC_SPI 463 IRQ_TYPE_EDGE_RISING>,
913 <GIC_SPI 464 I 932 <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
914 <GIC_SPI 465 I 933 <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>;
915 }; 934 };
916 935
917 pcie0: pcie@1c00000 { 936 pcie0: pcie@1c00000 {
918 compatible = "qcom,pci 937 compatible = "qcom,pcie-msm8998", "qcom,pcie-msm8996";
919 reg = <0x01c00000 0x20 938 reg = <0x01c00000 0x2000>,
920 <0x1b000000 0xf1 939 <0x1b000000 0xf1d>,
921 <0x1b000f20 0xa8 940 <0x1b000f20 0xa8>,
922 <0x1b100000 0x10 941 <0x1b100000 0x100000>;
923 reg-names = "parf", "d 942 reg-names = "parf", "dbi", "elbi", "config";
924 device_type = "pci"; 943 device_type = "pci";
925 linux,pci-domain = <0> 944 linux,pci-domain = <0>;
926 bus-range = <0x00 0xff 945 bus-range = <0x00 0xff>;
927 #address-cells = <3>; 946 #address-cells = <3>;
928 #size-cells = <2>; 947 #size-cells = <2>;
929 num-lanes = <1>; 948 num-lanes = <1>;
930 phys = <&pcie_phy>; 949 phys = <&pcie_phy>;
931 phy-names = "pciephy"; 950 phy-names = "pciephy";
932 status = "disabled"; 951 status = "disabled";
933 952
934 ranges = <0x01000000 0 953 ranges = <0x01000000 0x0 0x00000000 0x1b200000 0x0 0x100000>,
935 <0x02000000 0 954 <0x02000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>;
936 955
937 #interrupt-cells = <1> 956 #interrupt-cells = <1>;
938 interrupts = <GIC_SPI 957 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
939 interrupt-names = "msi 958 interrupt-names = "msi";
940 interrupt-map-mask = < 959 interrupt-map-mask = <0 0 0 0x7>;
941 interrupt-map = <0 0 0 960 interrupt-map = <0 0 0 1 &intc 0 0 135 IRQ_TYPE_LEVEL_HIGH>,
942 <0 0 0 961 <0 0 0 2 &intc 0 0 136 IRQ_TYPE_LEVEL_HIGH>,
943 <0 0 0 962 <0 0 0 3 &intc 0 0 138 IRQ_TYPE_LEVEL_HIGH>,
944 <0 0 0 963 <0 0 0 4 &intc 0 0 139 IRQ_TYPE_LEVEL_HIGH>;
945 964
946 clocks = <&gcc GCC_PCI 965 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
947 <&gcc GCC_PCI 966 <&gcc GCC_PCIE_0_AUX_CLK>,
948 <&gcc GCC_PCI 967 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
949 <&gcc GCC_PCI 968 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
950 <&gcc GCC_PCI 969 <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
951 clock-names = "pipe", 970 clock-names = "pipe", "aux", "cfg", "bus_master", "bus_slave";
952 971
953 power-domains = <&gcc 972 power-domains = <&gcc PCIE_0_GDSC>;
954 iommu-map = <0x100 &an 973 iommu-map = <0x100 &anoc1_smmu 0x1480 1>;
955 perst-gpios = <&tlmm 3 974 perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
956 975
957 pcie@0 { 976 pcie@0 {
958 device_type = 977 device_type = "pci";
959 reg = <0x0 0x0 978 reg = <0x0 0x0 0x0 0x0 0x0>;
960 bus-range = <0 979 bus-range = <0x01 0xff>;
961 980
962 #address-cells 981 #address-cells = <3>;
963 #size-cells = 982 #size-cells = <2>;
964 ranges; 983 ranges;
965 }; 984 };
966 }; 985 };
967 986
968 pcie_phy: phy@1c06000 { 987 pcie_phy: phy@1c06000 {
969 compatible = "qcom,msm 988 compatible = "qcom,msm8998-qmp-pcie-phy";
970 reg = <0x01c06000 0x10 989 reg = <0x01c06000 0x1000>;
971 status = "disabled"; 990 status = "disabled";
972 991
973 clocks = <&gcc GCC_PCI 992 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
974 <&gcc GCC_PCI 993 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
975 <&gcc GCC_PCI 994 <&gcc GCC_PCIE_CLKREF_CLK>,
976 <&gcc GCC_PCI 995 <&gcc GCC_PCIE_0_PIPE_CLK>;
977 clock-names = "aux", 996 clock-names = "aux",
978 "cfg_ahb 997 "cfg_ahb",
979 "ref", 998 "ref",
980 "pipe"; 999 "pipe";
981 1000
982 clock-output-names = " 1001 clock-output-names = "pcie_0_pipe_clk_src";
983 #clock-cells = <0>; 1002 #clock-cells = <0>;
984 1003
985 #phy-cells = <0>; 1004 #phy-cells = <0>;
986 1005
987 resets = <&gcc GCC_PCI 1006 resets = <&gcc GCC_PCIE_0_PHY_BCR>, <&gcc GCC_PCIE_PHY_BCR>;
988 reset-names = "phy", " 1007 reset-names = "phy", "common";
989 1008
990 vdda-phy-supply = <&vr 1009 vdda-phy-supply = <&vreg_l1a_0p875>;
991 vdda-pll-supply = <&vr 1010 vdda-pll-supply = <&vreg_l2a_1p2>;
992 }; 1011 };
993 1012
994 ufshc: ufshc@1da4000 { 1013 ufshc: ufshc@1da4000 {
995 compatible = "qcom,msm 1014 compatible = "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
996 reg = <0x01da4000 0x25 1015 reg = <0x01da4000 0x2500>;
997 interrupts = <GIC_SPI 1016 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
998 phys = <&ufsphy>; 1017 phys = <&ufsphy>;
999 phy-names = "ufsphy"; 1018 phy-names = "ufsphy";
1000 lanes-per-direction = 1019 lanes-per-direction = <2>;
1001 power-domains = <&gcc 1020 power-domains = <&gcc UFS_GDSC>;
1002 status = "disabled"; 1021 status = "disabled";
1003 #reset-cells = <1>; 1022 #reset-cells = <1>;
1004 1023
1005 clock-names = 1024 clock-names =
1006 "core_clk", 1025 "core_clk",
1007 "bus_aggr_clk 1026 "bus_aggr_clk",
1008 "iface_clk", 1027 "iface_clk",
1009 "core_clk_uni 1028 "core_clk_unipro",
1010 "ref_clk", 1029 "ref_clk",
1011 "tx_lane0_syn 1030 "tx_lane0_sync_clk",
1012 "rx_lane0_syn 1031 "rx_lane0_sync_clk",
1013 "rx_lane1_syn 1032 "rx_lane1_sync_clk";
1014 clocks = 1033 clocks =
1015 <&gcc GCC_UFS 1034 <&gcc GCC_UFS_AXI_CLK>,
1016 <&gcc GCC_AGG 1035 <&gcc GCC_AGGRE1_UFS_AXI_CLK>,
1017 <&gcc GCC_UFS 1036 <&gcc GCC_UFS_AHB_CLK>,
1018 <&gcc GCC_UFS 1037 <&gcc GCC_UFS_UNIPRO_CORE_CLK>,
1019 <&rpmcc RPM_S 1038 <&rpmcc RPM_SMD_LN_BB_CLK1>,
1020 <&gcc GCC_UFS 1039 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
1021 <&gcc GCC_UFS 1040 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>,
1022 <&gcc GCC_UFS 1041 <&gcc GCC_UFS_RX_SYMBOL_1_CLK>;
1023 freq-table-hz = 1042 freq-table-hz =
1024 <50000000 200 1043 <50000000 200000000>,
1025 <0 0>, 1044 <0 0>,
1026 <0 0>, 1045 <0 0>,
1027 <37500000 150 1046 <37500000 150000000>,
1028 <0 0>, 1047 <0 0>,
1029 <0 0>, 1048 <0 0>,
1030 <0 0>, 1049 <0 0>,
1031 <0 0>; 1050 <0 0>;
1032 1051
1033 resets = <&gcc GCC_UF 1052 resets = <&gcc GCC_UFS_BCR>;
1034 reset-names = "rst"; 1053 reset-names = "rst";
1035 }; 1054 };
1036 1055
1037 ufsphy: phy@1da7000 { 1056 ufsphy: phy@1da7000 {
1038 compatible = "qcom,ms 1057 compatible = "qcom,msm8998-qmp-ufs-phy";
1039 reg = <0x01da7000 0x1 1058 reg = <0x01da7000 0x1000>;
1040 1059
1041 clocks = <&rpmcc RPM_ 1060 clocks = <&rpmcc RPM_SMD_LN_BB_CLK1>,
1042 <&gcc GCC_UF 1061 <&gcc GCC_UFS_PHY_AUX_CLK>,
1043 <&gcc GCC_UF 1062 <&gcc GCC_UFS_CLKREF_CLK>;
1044 clock-names = "ref", 1063 clock-names = "ref",
1045 "ref_au 1064 "ref_aux",
1046 "qref"; 1065 "qref";
1047 1066
1048 reset-names = "ufsphy 1067 reset-names = "ufsphy";
1049 resets = <&ufshc 0>; 1068 resets = <&ufshc 0>;
1050 1069
1051 #phy-cells = <0>; 1070 #phy-cells = <0>;
1052 status = "disabled"; 1071 status = "disabled";
1053 }; 1072 };
1054 1073
1055 tcsr_mutex: hwlock@1f40000 { 1074 tcsr_mutex: hwlock@1f40000 {
1056 compatible = "qcom,tc 1075 compatible = "qcom,tcsr-mutex";
1057 reg = <0x01f40000 0x2 1076 reg = <0x01f40000 0x20000>;
1058 #hwlock-cells = <1>; 1077 #hwlock-cells = <1>;
1059 }; 1078 };
1060 1079
1061 tcsr_regs_1: syscon@1f60000 { 1080 tcsr_regs_1: syscon@1f60000 {
1062 compatible = "qcom,ms 1081 compatible = "qcom,msm8998-tcsr", "syscon";
1063 reg = <0x01f60000 0x2 1082 reg = <0x01f60000 0x20000>;
1064 }; 1083 };
1065 1084
1066 tcsr_regs_2: syscon@1fc0000 { 1085 tcsr_regs_2: syscon@1fc0000 {
1067 compatible = "qcom,ms 1086 compatible = "qcom,msm8998-tcsr", "syscon";
1068 reg = <0x01fc0000 0x2 1087 reg = <0x01fc0000 0x26000>;
1069 }; 1088 };
1070 1089
1071 tlmm: pinctrl@3400000 { 1090 tlmm: pinctrl@3400000 {
1072 compatible = "qcom,ms 1091 compatible = "qcom,msm8998-pinctrl";
1073 reg = <0x03400000 0xc 1092 reg = <0x03400000 0xc00000>;
1074 interrupts = <GIC_SPI 1093 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1075 gpio-ranges = <&tlmm 1094 gpio-ranges = <&tlmm 0 0 150>;
1076 gpio-controller; 1095 gpio-controller;
1077 #gpio-cells = <2>; 1096 #gpio-cells = <2>;
1078 interrupt-controller; 1097 interrupt-controller;
1079 #interrupt-cells = <2 1098 #interrupt-cells = <2>;
1080 1099
1081 sdc2_on: sdc2-on-stat 1100 sdc2_on: sdc2-on-state {
1082 clk-pins { 1101 clk-pins {
1083 pins 1102 pins = "sdc2_clk";
1084 drive 1103 drive-strength = <16>;
1085 bias- 1104 bias-disable;
1086 }; 1105 };
1087 1106
1088 cmd-pins { 1107 cmd-pins {
1089 pins 1108 pins = "sdc2_cmd";
1090 drive 1109 drive-strength = <10>;
1091 bias- 1110 bias-pull-up;
1092 }; 1111 };
1093 1112
1094 data-pins { 1113 data-pins {
1095 pins 1114 pins = "sdc2_data";
1096 drive 1115 drive-strength = <10>;
1097 bias- 1116 bias-pull-up;
1098 }; 1117 };
1099 }; 1118 };
1100 1119
1101 sdc2_off: sdc2-off-st 1120 sdc2_off: sdc2-off-state {
1102 clk-pins { 1121 clk-pins {
1103 pins 1122 pins = "sdc2_clk";
1104 drive 1123 drive-strength = <2>;
1105 bias- 1124 bias-disable;
1106 }; 1125 };
1107 1126
1108 cmd-pins { 1127 cmd-pins {
1109 pins 1128 pins = "sdc2_cmd";
1110 drive 1129 drive-strength = <2>;
1111 bias- 1130 bias-pull-up;
1112 }; 1131 };
1113 1132
1114 data-pins { 1133 data-pins {
1115 pins 1134 pins = "sdc2_data";
1116 drive 1135 drive-strength = <2>;
1117 bias- 1136 bias-pull-up;
1118 }; 1137 };
1119 }; 1138 };
1120 1139
1121 sdc2_cd: sdc2-cd-stat 1140 sdc2_cd: sdc2-cd-state {
1122 pins = "gpio9 1141 pins = "gpio95";
1123 function = "g 1142 function = "gpio";
1124 bias-pull-up; 1143 bias-pull-up;
1125 drive-strengt 1144 drive-strength = <2>;
1126 }; 1145 };
1127 1146
1128 blsp1_uart3_on: blsp1 1147 blsp1_uart3_on: blsp1-uart3-on-state {
1129 tx-pins { 1148 tx-pins {
1130 pins 1149 pins = "gpio45";
1131 funct 1150 function = "blsp_uart3_a";
1132 drive 1151 drive-strength = <2>;
1133 bias- 1152 bias-disable;
1134 }; 1153 };
1135 1154
1136 rx-pins { 1155 rx-pins {
1137 pins 1156 pins = "gpio46";
1138 funct 1157 function = "blsp_uart3_a";
1139 drive 1158 drive-strength = <2>;
1140 bias- 1159 bias-disable;
1141 }; 1160 };
1142 1161
1143 cts-pins { 1162 cts-pins {
1144 pins 1163 pins = "gpio47";
1145 funct 1164 function = "blsp_uart3_a";
1146 drive 1165 drive-strength = <2>;
1147 bias- 1166 bias-disable;
1148 }; 1167 };
1149 1168
1150 rfr-pins { 1169 rfr-pins {
1151 pins 1170 pins = "gpio48";
1152 funct 1171 function = "blsp_uart3_a";
1153 drive 1172 drive-strength = <2>;
1154 bias- 1173 bias-disable;
1155 }; 1174 };
1156 }; 1175 };
1157 1176
1158 blsp1_i2c1_default: b 1177 blsp1_i2c1_default: blsp1-i2c1-default-state {
1159 pins = "gpio2 1178 pins = "gpio2", "gpio3";
1160 function = "b 1179 function = "blsp_i2c1";
1161 drive-strengt 1180 drive-strength = <2>;
1162 bias-disable; 1181 bias-disable;
1163 }; 1182 };
1164 1183
1165 blsp1_i2c1_sleep: bls 1184 blsp1_i2c1_sleep: blsp1-i2c1-sleep-state-state {
1166 pins = "gpio2 1185 pins = "gpio2", "gpio3";
1167 function = "b 1186 function = "blsp_i2c1";
1168 drive-strengt 1187 drive-strength = <2>;
1169 bias-pull-up; 1188 bias-pull-up;
1170 }; 1189 };
1171 1190
1172 blsp1_i2c2_default: b 1191 blsp1_i2c2_default: blsp1-i2c2-default-state {
1173 pins = "gpio3 1192 pins = "gpio32", "gpio33";
1174 function = "b 1193 function = "blsp_i2c2";
1175 drive-strengt 1194 drive-strength = <2>;
1176 bias-disable; 1195 bias-disable;
1177 }; 1196 };
1178 1197
1179 blsp1_i2c2_sleep: bls 1198 blsp1_i2c2_sleep: blsp1-i2c2-sleep-state-state {
1180 pins = "gpio3 1199 pins = "gpio32", "gpio33";
1181 function = "b 1200 function = "blsp_i2c2";
1182 drive-strengt 1201 drive-strength = <2>;
1183 bias-pull-up; 1202 bias-pull-up;
1184 }; 1203 };
1185 1204
1186 blsp1_i2c3_default: b 1205 blsp1_i2c3_default: blsp1-i2c3-default-state {
1187 pins = "gpio4 1206 pins = "gpio47", "gpio48";
1188 function = "b 1207 function = "blsp_i2c3";
1189 drive-strengt 1208 drive-strength = <2>;
1190 bias-disable; 1209 bias-disable;
1191 }; 1210 };
1192 1211
1193 blsp1_i2c3_sleep: bls 1212 blsp1_i2c3_sleep: blsp1-i2c3-sleep-state {
1194 pins = "gpio4 1213 pins = "gpio47", "gpio48";
1195 function = "b 1214 function = "blsp_i2c3";
1196 drive-strengt 1215 drive-strength = <2>;
1197 bias-pull-up; 1216 bias-pull-up;
1198 }; 1217 };
1199 1218
1200 blsp1_i2c4_default: b 1219 blsp1_i2c4_default: blsp1-i2c4-default-state {
1201 pins = "gpio1 1220 pins = "gpio10", "gpio11";
1202 function = "b 1221 function = "blsp_i2c4";
1203 drive-strengt 1222 drive-strength = <2>;
1204 bias-disable; 1223 bias-disable;
1205 }; 1224 };
1206 1225
1207 blsp1_i2c4_sleep: bls 1226 blsp1_i2c4_sleep: blsp1-i2c4-sleep-state {
1208 pins = "gpio1 1227 pins = "gpio10", "gpio11";
1209 function = "b 1228 function = "blsp_i2c4";
1210 drive-strengt 1229 drive-strength = <2>;
1211 bias-pull-up; 1230 bias-pull-up;
1212 }; 1231 };
1213 1232
1214 blsp1_i2c5_default: b 1233 blsp1_i2c5_default: blsp1-i2c5-default-state {
1215 pins = "gpio8 1234 pins = "gpio87", "gpio88";
1216 function = "b 1235 function = "blsp_i2c5";
1217 drive-strengt 1236 drive-strength = <2>;
1218 bias-disable; 1237 bias-disable;
1219 }; 1238 };
1220 1239
1221 blsp1_i2c5_sleep: bls 1240 blsp1_i2c5_sleep: blsp1-i2c5-sleep-state {
1222 pins = "gpio8 1241 pins = "gpio87", "gpio88";
1223 function = "b 1242 function = "blsp_i2c5";
1224 drive-strengt 1243 drive-strength = <2>;
1225 bias-pull-up; 1244 bias-pull-up;
1226 }; 1245 };
1227 1246
1228 blsp1_i2c6_default: b 1247 blsp1_i2c6_default: blsp1-i2c6-default-state {
1229 pins = "gpio4 1248 pins = "gpio43", "gpio44";
1230 function = "b 1249 function = "blsp_i2c6";
1231 drive-strengt 1250 drive-strength = <2>;
1232 bias-disable; 1251 bias-disable;
1233 }; 1252 };
1234 1253
1235 blsp1_i2c6_sleep: bls 1254 blsp1_i2c6_sleep: blsp1-i2c6-sleep-state {
1236 pins = "gpio4 1255 pins = "gpio43", "gpio44";
1237 function = "b 1256 function = "blsp_i2c6";
1238 drive-strengt 1257 drive-strength = <2>;
1239 bias-pull-up; 1258 bias-pull-up;
1240 }; 1259 };
1241 1260
1242 blsp1_spi_b_default: 1261 blsp1_spi_b_default: blsp1-spi-b-default-state {
1243 pins = "gpio2 1262 pins = "gpio23", "gpio28";
1244 function = "b 1263 function = "blsp1_spi_b";
1245 drive-strengt 1264 drive-strength = <6>;
1246 bias-disable; 1265 bias-disable;
1247 }; 1266 };
1248 1267
1249 blsp1_spi1_default: b 1268 blsp1_spi1_default: blsp1-spi1-default-state {
1250 pins = "gpio0 1269 pins = "gpio0", "gpio1", "gpio2", "gpio3";
1251 function = "b 1270 function = "blsp_spi1";
1252 drive-strengt 1271 drive-strength = <6>;
1253 bias-disable; 1272 bias-disable;
1254 }; 1273 };
1255 1274
1256 blsp1_spi2_default: b 1275 blsp1_spi2_default: blsp1-spi2-default-state {
1257 pins = "gpio3 1276 pins = "gpio31", "gpio34", "gpio32", "gpio33";
1258 function = "b 1277 function = "blsp_spi2";
1259 drive-strengt 1278 drive-strength = <6>;
1260 bias-disable; 1279 bias-disable;
1261 }; 1280 };
1262 1281
1263 blsp1_spi3_default: b 1282 blsp1_spi3_default: blsp1-spi3-default-state {
1264 pins = "gpio4 1283 pins = "gpio45", "gpio46", "gpio47", "gpio48";
1265 function = "b 1284 function = "blsp_spi2";
1266 drive-strengt 1285 drive-strength = <6>;
1267 bias-disable; 1286 bias-disable;
1268 }; 1287 };
1269 1288
1270 blsp1_spi4_default: b 1289 blsp1_spi4_default: blsp1-spi4-default-state {
1271 pins = "gpio8 1290 pins = "gpio8", "gpio9", "gpio10", "gpio11";
1272 function = "b 1291 function = "blsp_spi4";
1273 drive-strengt 1292 drive-strength = <6>;
1274 bias-disable; 1293 bias-disable;
1275 }; 1294 };
1276 1295
1277 blsp1_spi5_default: b 1296 blsp1_spi5_default: blsp1-spi5-default-state {
1278 pins = "gpio8 1297 pins = "gpio85", "gpio86", "gpio87", "gpio88";
1279 function = "b 1298 function = "blsp_spi5";
1280 drive-strengt 1299 drive-strength = <6>;
1281 bias-disable; 1300 bias-disable;
1282 }; 1301 };
1283 1302
1284 blsp1_spi6_default: b 1303 blsp1_spi6_default: blsp1-spi6-default-state {
1285 pins = "gpio4 1304 pins = "gpio41", "gpio42", "gpio43", "gpio44";
1286 function = "b 1305 function = "blsp_spi6";
1287 drive-strengt 1306 drive-strength = <6>;
1288 bias-disable; 1307 bias-disable;
1289 }; 1308 };
1290 1309
1291 1310
1292 /* 6 interfaces per Q 1311 /* 6 interfaces per QUP, BLSP2 indexes are numbered (n)+6 */
1293 blsp2_i2c1_default: b 1312 blsp2_i2c1_default: blsp2-i2c1-default-state {
1294 pins = "gpio5 1313 pins = "gpio55", "gpio56";
1295 function = "b 1314 function = "blsp_i2c7";
1296 drive-strengt 1315 drive-strength = <2>;
1297 bias-disable; 1316 bias-disable;
1298 }; 1317 };
1299 1318
1300 blsp2_i2c1_sleep: bls 1319 blsp2_i2c1_sleep: blsp2-i2c1-sleep-state {
1301 pins = "gpio5 1320 pins = "gpio55", "gpio56";
1302 function = "b 1321 function = "blsp_i2c7";
1303 drive-strengt 1322 drive-strength = <2>;
1304 bias-pull-up; 1323 bias-pull-up;
1305 }; 1324 };
1306 1325
1307 blsp2_i2c2_default: b 1326 blsp2_i2c2_default: blsp2-i2c2-default-state {
1308 pins = "gpio6 1327 pins = "gpio6", "gpio7";
1309 function = "b 1328 function = "blsp_i2c8";
1310 drive-strengt 1329 drive-strength = <2>;
1311 bias-disable; 1330 bias-disable;
1312 }; 1331 };
1313 1332
1314 blsp2_i2c2_sleep: bls 1333 blsp2_i2c2_sleep: blsp2-i2c2-sleep-state {
1315 pins = "gpio6 1334 pins = "gpio6", "gpio7";
1316 function = "b 1335 function = "blsp_i2c8";
1317 drive-strengt 1336 drive-strength = <2>;
1318 bias-pull-up; 1337 bias-pull-up;
1319 }; 1338 };
1320 1339
1321 blsp2_i2c3_default: b 1340 blsp2_i2c3_default: blsp2-i2c3-default-state {
1322 pins = "gpio5 1341 pins = "gpio51", "gpio52";
1323 function = "b 1342 function = "blsp_i2c9";
1324 drive-strengt 1343 drive-strength = <2>;
1325 bias-disable; 1344 bias-disable;
1326 }; 1345 };
1327 1346
1328 blsp2_i2c3_sleep: bls 1347 blsp2_i2c3_sleep: blsp2-i2c3-sleep-state {
1329 pins = "gpio5 1348 pins = "gpio51", "gpio52";
1330 function = "b 1349 function = "blsp_i2c9";
1331 drive-strengt 1350 drive-strength = <2>;
1332 bias-pull-up; 1351 bias-pull-up;
1333 }; 1352 };
1334 1353
1335 blsp2_i2c4_default: b 1354 blsp2_i2c4_default: blsp2-i2c4-default-state {
1336 pins = "gpio6 1355 pins = "gpio67", "gpio68";
1337 function = "b 1356 function = "blsp_i2c10";
1338 drive-strengt 1357 drive-strength = <2>;
1339 bias-disable; 1358 bias-disable;
1340 }; 1359 };
1341 1360
1342 blsp2_i2c4_sleep: bls 1361 blsp2_i2c4_sleep: blsp2-i2c4-sleep-state {
1343 pins = "gpio6 1362 pins = "gpio67", "gpio68";
1344 function = "b 1363 function = "blsp_i2c10";
1345 drive-strengt 1364 drive-strength = <2>;
1346 bias-pull-up; 1365 bias-pull-up;
1347 }; 1366 };
1348 1367
1349 blsp2_i2c5_default: b 1368 blsp2_i2c5_default: blsp2-i2c5-default-state {
1350 pins = "gpio6 1369 pins = "gpio60", "gpio61";
1351 function = "b 1370 function = "blsp_i2c11";
1352 drive-strengt 1371 drive-strength = <2>;
1353 bias-disable; 1372 bias-disable;
1354 }; 1373 };
1355 1374
1356 blsp2_i2c5_sleep: bls 1375 blsp2_i2c5_sleep: blsp2-i2c5-sleep-state {
1357 pins = "gpio6 1376 pins = "gpio60", "gpio61";
1358 function = "b 1377 function = "blsp_i2c11";
1359 drive-strengt 1378 drive-strength = <2>;
1360 bias-pull-up; 1379 bias-pull-up;
1361 }; 1380 };
1362 1381
1363 blsp2_i2c6_default: b 1382 blsp2_i2c6_default: blsp2-i2c6-default-state {
1364 pins = "gpio8 1383 pins = "gpio83", "gpio84";
1365 function = "b 1384 function = "blsp_i2c12";
1366 drive-strengt 1385 drive-strength = <2>;
1367 bias-disable; 1386 bias-disable;
1368 }; 1387 };
1369 1388
1370 blsp2_i2c6_sleep: bls 1389 blsp2_i2c6_sleep: blsp2-i2c6-sleep-state {
1371 pins = "gpio8 1390 pins = "gpio83", "gpio84";
1372 function = "b 1391 function = "blsp_i2c12";
1373 drive-strengt 1392 drive-strength = <2>;
1374 bias-pull-up; 1393 bias-pull-up;
1375 }; 1394 };
1376 1395
1377 blsp2_spi1_default: b 1396 blsp2_spi1_default: blsp2-spi1-default-state {
1378 pins = "gpio5 1397 pins = "gpio53", "gpio54", "gpio55", "gpio56";
1379 function = "b 1398 function = "blsp_spi7";
1380 drive-strengt 1399 drive-strength = <6>;
1381 bias-disable; 1400 bias-disable;
1382 }; 1401 };
1383 1402
1384 blsp2_spi2_default: b 1403 blsp2_spi2_default: blsp2-spi2-default-state {
1385 pins = "gpio4 1404 pins = "gpio4", "gpio5", "gpio6", "gpio7";
1386 function = "b 1405 function = "blsp_spi8";
1387 drive-strengt 1406 drive-strength = <6>;
1388 bias-disable; 1407 bias-disable;
1389 }; 1408 };
1390 1409
1391 blsp2_spi3_default: b 1410 blsp2_spi3_default: blsp2-spi3-default-state {
1392 pins = "gpio4 1411 pins = "gpio49", "gpio50", "gpio51", "gpio52";
1393 function = "b 1412 function = "blsp_spi9";
1394 drive-strengt 1413 drive-strength = <6>;
1395 bias-disable; 1414 bias-disable;
1396 }; 1415 };
1397 1416
1398 blsp2_spi4_default: b 1417 blsp2_spi4_default: blsp2-spi4-default-state {
1399 pins = "gpio6 1418 pins = "gpio65", "gpio66", "gpio67", "gpio68";
1400 function = "b 1419 function = "blsp_spi10";
1401 drive-strengt 1420 drive-strength = <6>;
1402 bias-disable; 1421 bias-disable;
1403 }; 1422 };
1404 1423
1405 blsp2_spi5_default: b 1424 blsp2_spi5_default: blsp2-spi5-default-state {
1406 pins = "gpio5 1425 pins = "gpio58", "gpio59", "gpio60", "gpio61";
1407 function = "b 1426 function = "blsp_spi11";
1408 drive-strengt 1427 drive-strength = <6>;
1409 bias-disable; 1428 bias-disable;
1410 }; 1429 };
1411 1430
1412 blsp2_spi6_default: b 1431 blsp2_spi6_default: blsp2-spi6-default-state {
1413 pins = "gpio8 1432 pins = "gpio81", "gpio82", "gpio83", "gpio84";
1414 function = "b 1433 function = "blsp_spi12";
1415 drive-strengt 1434 drive-strength = <6>;
1416 bias-disable; 1435 bias-disable;
1417 }; 1436 };
1418 }; 1437 };
1419 1438
1420 remoteproc_mss: remoteproc@40 1439 remoteproc_mss: remoteproc@4080000 {
1421 compatible = "qcom,ms 1440 compatible = "qcom,msm8998-mss-pil";
1422 reg = <0x04080000 0x1 1441 reg = <0x04080000 0x100>, <0x04180000 0x20>;
1423 reg-names = "qdsp6", 1442 reg-names = "qdsp6", "rmb";
1424 1443
1425 interrupts-extended = 1444 interrupts-extended =
1426 <&intc GIC_SP 1445 <&intc GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
1427 <&modem_smp2p 1446 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1428 <&modem_smp2p 1447 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1429 <&modem_smp2p 1448 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1430 <&modem_smp2p 1449 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
1431 <&modem_smp2p 1450 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
1432 interrupt-names = "wd 1451 interrupt-names = "wdog", "fatal", "ready",
1433 "ha 1452 "handover", "stop-ack",
1434 "sh 1453 "shutdown-ack";
1435 1454
1436 clocks = <&gcc GCC_MS 1455 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
1437 <&gcc GCC_BI 1456 <&gcc GCC_BIMC_MSS_Q6_AXI_CLK>,
1438 <&gcc GCC_BO 1457 <&gcc GCC_BOOT_ROM_AHB_CLK>,
1439 <&gcc GCC_MS 1458 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
1440 <&gcc GCC_MS 1459 <&gcc GCC_MSS_SNOC_AXI_CLK>,
1441 <&gcc GCC_MS 1460 <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>,
1442 <&rpmcc RPM_ 1461 <&rpmcc RPM_SMD_QDSS_CLK>,
1443 <&rpmcc RPM_ 1462 <&rpmcc RPM_SMD_XO_CLK_SRC>;
1444 clock-names = "iface" 1463 clock-names = "iface", "bus", "mem", "gpll0_mss",
1445 "snoc_a 1464 "snoc_axi", "mnoc_axi", "qdss", "xo";
1446 1465
1447 qcom,smem-states = <& 1466 qcom,smem-states = <&modem_smp2p_out 0>;
1448 qcom,smem-state-names 1467 qcom,smem-state-names = "stop";
1449 1468
1450 resets = <&gcc GCC_MS 1469 resets = <&gcc GCC_MSS_RESTART>;
1451 reset-names = "mss_re 1470 reset-names = "mss_restart";
1452 1471
1453 qcom,halt-regs = <&tc 1472 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>;
1454 1473
1455 power-domains = <&rpm 1474 power-domains = <&rpmpd MSM8998_VDDCX>,
1456 <&rpm 1475 <&rpmpd MSM8998_VDDMX>;
1457 power-domain-names = 1476 power-domain-names = "cx", "mx";
1458 1477
1459 status = "disabled"; 1478 status = "disabled";
1460 1479
1461 mba { 1480 mba {
1462 memory-region 1481 memory-region = <&mba_mem>;
1463 }; 1482 };
1464 1483
1465 mpss { 1484 mpss {
1466 memory-region 1485 memory-region = <&mpss_mem>;
1467 }; 1486 };
1468 1487
1469 metadata { 1488 metadata {
1470 memory-region 1489 memory-region = <&mdata_mem>;
1471 }; 1490 };
1472 1491
1473 glink-edge { 1492 glink-edge {
1474 interrupts = 1493 interrupts = <GIC_SPI 452 IRQ_TYPE_EDGE_RISING>;
1475 label = "mode 1494 label = "modem";
1476 qcom,remote-p 1495 qcom,remote-pid = <1>;
1477 mboxes = <&ap 1496 mboxes = <&apcs_glb 15>;
1478 }; 1497 };
1479 }; 1498 };
1480 1499
1481 adreno_gpu: gpu@5000000 { 1500 adreno_gpu: gpu@5000000 {
1482 compatible = "qcom,ad 1501 compatible = "qcom,adreno-540.1", "qcom,adreno";
1483 reg = <0x05000000 0x4 1502 reg = <0x05000000 0x40000>;
1484 reg-names = "kgsl_3d0 1503 reg-names = "kgsl_3d0_reg_memory";
1485 1504
1486 clocks = <&gcc GCC_GP 1505 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
1487 <&gpucc RBBMT 1506 <&gpucc RBBMTIMER_CLK>,
1488 <&gcc GCC_BIM 1507 <&gcc GCC_BIMC_GFX_CLK>,
1489 <&gcc GCC_GPU 1508 <&gcc GCC_GPU_BIMC_GFX_CLK>,
1490 <&gpucc RBCPR 1509 <&gpucc RBCPR_CLK>,
1491 <&gpucc GFX3D 1510 <&gpucc GFX3D_CLK>;
1492 clock-names = "iface" 1511 clock-names = "iface",
1493 "rbbmtimer", 1512 "rbbmtimer",
1494 "mem", 1513 "mem",
1495 "mem_iface", 1514 "mem_iface",
1496 "rbcpr", 1515 "rbcpr",
1497 "core"; 1516 "core";
1498 1517
1499 interrupts = <GIC_SPI 1518 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
1500 iommus = <&adreno_smm 1519 iommus = <&adreno_smmu 0>;
1501 operating-points-v2 = 1520 operating-points-v2 = <&gpu_opp_table>;
1502 power-domains = <&rpm 1521 power-domains = <&rpmpd MSM8998_VDDMX>;
1503 status = "disabled"; 1522 status = "disabled";
1504 1523
1505 gpu_opp_table: opp-ta 1524 gpu_opp_table: opp-table {
1506 compatible = 1525 compatible = "operating-points-v2";
1507 opp-710000097 1526 opp-710000097 {
1508 opp-h 1527 opp-hz = /bits/ 64 <710000097>;
1509 opp-l 1528 opp-level = <RPM_SMD_LEVEL_TURBO>;
1510 opp-s 1529 opp-supported-hw = <0xff>;
1511 }; 1530 };
1512 1531
1513 opp-670000048 1532 opp-670000048 {
1514 opp-h 1533 opp-hz = /bits/ 64 <670000048>;
1515 opp-l 1534 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
1516 opp-s 1535 opp-supported-hw = <0xff>;
1517 }; 1536 };
1518 1537
1519 opp-596000097 1538 opp-596000097 {
1520 opp-h 1539 opp-hz = /bits/ 64 <596000097>;
1521 opp-l 1540 opp-level = <RPM_SMD_LEVEL_NOM>;
1522 opp-s 1541 opp-supported-hw = <0xff>;
1523 }; 1542 };
1524 1543
1525 opp-515000097 1544 opp-515000097 {
1526 opp-h 1545 opp-hz = /bits/ 64 <515000097>;
1527 opp-l 1546 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
1528 opp-s 1547 opp-supported-hw = <0xff>;
1529 }; 1548 };
1530 1549
1531 opp-414000000 1550 opp-414000000 {
1532 opp-h 1551 opp-hz = /bits/ 64 <414000000>;
1533 opp-l 1552 opp-level = <RPM_SMD_LEVEL_SVS>;
1534 opp-s 1553 opp-supported-hw = <0xff>;
1535 }; 1554 };
1536 1555
1537 opp-342000000 1556 opp-342000000 {
1538 opp-h 1557 opp-hz = /bits/ 64 <342000000>;
1539 opp-l 1558 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
1540 opp-s 1559 opp-supported-hw = <0xff>;
1541 }; 1560 };
1542 1561
1543 opp-257000000 1562 opp-257000000 {
1544 opp-h 1563 opp-hz = /bits/ 64 <257000000>;
1545 opp-l 1564 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
1546 opp-s 1565 opp-supported-hw = <0xff>;
1547 }; 1566 };
1548 }; 1567 };
1549 }; 1568 };
1550 1569
1551 adreno_smmu: iommu@5040000 { 1570 adreno_smmu: iommu@5040000 {
1552 compatible = "qcom,ms 1571 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
1553 reg = <0x05040000 0x1 1572 reg = <0x05040000 0x10000>;
1554 clocks = <&gcc GCC_GP 1573 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
1555 <&gcc GCC_BI 1574 <&gcc GCC_BIMC_GFX_CLK>,
1556 <&gcc GCC_GP 1575 <&gcc GCC_GPU_BIMC_GFX_CLK>;
1557 clock-names = "iface" 1576 clock-names = "iface", "mem", "mem_iface";
1558 1577
1559 #global-interrupts = 1578 #global-interrupts = <0>;
1560 #iommu-cells = <1>; 1579 #iommu-cells = <1>;
1561 interrupts = 1580 interrupts =
1562 <GIC_SPI 329 1581 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1563 <GIC_SPI 330 1582 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
1564 <GIC_SPI 331 1583 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
1565 /* 1584 /*
1566 * GPU-GX GDSC's pare 1585 * GPU-GX GDSC's parent is GPU-CX. We need to bring up the
1567 * GPU-CX for SMMU bu 1586 * GPU-CX for SMMU but we need both of them up for Adreno.
1568 * Contemporarily, we 1587 * Contemporarily, we also need to manage the VDDMX rpmpd
1569 * domain in the Adre 1588 * domain in the Adreno driver.
1570 * Enable GPU CX/GX G 1589 * Enable GPU CX/GX GDSCs here so that we can manage the
1571 * SoC VDDMX RPM Powe 1590 * SoC VDDMX RPM Power Domain in the Adreno driver.
1572 */ 1591 */
1573 power-domains = <&gpu 1592 power-domains = <&gpucc GPU_GX_GDSC>;
1574 }; 1593 };
1575 1594
1576 gpucc: clock-controller@50650 1595 gpucc: clock-controller@5065000 {
1577 compatible = "qcom,ms 1596 compatible = "qcom,msm8998-gpucc";
1578 #clock-cells = <1>; 1597 #clock-cells = <1>;
1579 #reset-cells = <1>; 1598 #reset-cells = <1>;
1580 #power-domain-cells = 1599 #power-domain-cells = <1>;
1581 reg = <0x05065000 0x9 1600 reg = <0x05065000 0x9000>;
1582 1601
1583 clocks = <&rpmcc RPM_ 1602 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1584 <&gcc GCC_GP 1603 <&gcc GCC_GPU_GPLL0_CLK>;
1585 clock-names = "xo", 1604 clock-names = "xo",
1586 "gpll0" 1605 "gpll0";
1587 }; 1606 };
1588 1607
1589 lpass_q6_smmu: iommu@5100000 <<
1590 compatible = "qcom,ms <<
1591 reg = <0x05100000 0x4 <<
1592 clocks = <&gcc HLOS1_ <<
1593 clock-names = "bus"; <<
1594 <<
1595 #global-interrupts = <<
1596 #iommu-cells = <1>; <<
1597 interrupts = <<
1598 <GIC_SPI 226 <<
1599 <GIC_SPI 393 <<
1600 <GIC_SPI 394 <<
1601 <GIC_SPI 395 <<
1602 <GIC_SPI 396 <<
1603 <GIC_SPI 397 <<
1604 <GIC_SPI 398 <<
1605 <GIC_SPI 399 <<
1606 <GIC_SPI 400 <<
1607 <GIC_SPI 401 <<
1608 <GIC_SPI 402 <<
1609 <GIC_SPI 403 <<
1610 <GIC_SPI 137 <<
1611 <<
1612 power-domains = <&gcc <<
1613 status = "disabled"; <<
1614 }; <<
1615 <<
1616 remoteproc_slpi: remoteproc@5 1608 remoteproc_slpi: remoteproc@5800000 {
1617 compatible = "qcom,ms 1609 compatible = "qcom,msm8998-slpi-pas";
1618 reg = <0x05800000 0x4 1610 reg = <0x05800000 0x4040>;
1619 1611
1620 interrupts-extended = 1612 interrupts-extended = <&intc GIC_SPI 390 IRQ_TYPE_EDGE_RISING>,
1621 1613 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1622 1614 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1623 1615 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1624 1616 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1625 interrupt-names = "wd 1617 interrupt-names = "wdog", "fatal", "ready",
1626 "ha 1618 "handover", "stop-ack";
1627 1619
1628 px-supply = <&vreg_lv 1620 px-supply = <&vreg_lvs2a_1p8>;
1629 1621
1630 clocks = <&rpmcc RPM_ 1622 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
1631 clock-names = "xo"; 1623 clock-names = "xo";
1632 1624
1633 memory-region = <&slp 1625 memory-region = <&slpi_mem>;
1634 1626
1635 qcom,smem-states = <& 1627 qcom,smem-states = <&slpi_smp2p_out 0>;
1636 qcom,smem-state-names 1628 qcom,smem-state-names = "stop";
1637 1629
1638 power-domains = <&rpm 1630 power-domains = <&rpmpd MSM8998_SSCCX>;
1639 power-domain-names = 1631 power-domain-names = "ssc_cx";
1640 1632
1641 status = "disabled"; 1633 status = "disabled";
1642 1634
1643 glink-edge { 1635 glink-edge {
1644 interrupts = 1636 interrupts = <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>;
1645 label = "dsps 1637 label = "dsps";
1646 qcom,remote-p 1638 qcom,remote-pid = <3>;
1647 mboxes = <&ap 1639 mboxes = <&apcs_glb 27>;
1648 }; 1640 };
1649 }; 1641 };
1650 1642
1651 stm: stm@6002000 { 1643 stm: stm@6002000 {
1652 compatible = "arm,cor 1644 compatible = "arm,coresight-stm", "arm,primecell";
1653 reg = <0x06002000 0x1 1645 reg = <0x06002000 0x1000>,
1654 <0x16280000 0x1 1646 <0x16280000 0x180000>;
1655 reg-names = "stm-base 1647 reg-names = "stm-base", "stm-stimulus-base";
1656 status = "disabled"; 1648 status = "disabled";
1657 1649
1658 clocks = <&rpmcc RPM_ 1650 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1659 clock-names = "apb_pc 1651 clock-names = "apb_pclk", "atclk";
1660 1652
1661 out-ports { 1653 out-ports {
1662 port { 1654 port {
1663 stm_o 1655 stm_out: endpoint {
1664 1656 remote-endpoint = <&funnel0_in7>;
1665 }; 1657 };
1666 }; 1658 };
1667 }; 1659 };
1668 }; 1660 };
1669 1661
1670 funnel1: funnel@6041000 { 1662 funnel1: funnel@6041000 {
1671 compatible = "arm,cor 1663 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1672 reg = <0x06041000 0x1 1664 reg = <0x06041000 0x1000>;
1673 status = "disabled"; 1665 status = "disabled";
1674 1666
1675 clocks = <&rpmcc RPM_ 1667 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1676 clock-names = "apb_pc 1668 clock-names = "apb_pclk", "atclk";
1677 1669
1678 out-ports { 1670 out-ports {
1679 port { 1671 port {
1680 funne 1672 funnel0_out: endpoint {
1681 1673 remote-endpoint =
1682 1674 <&merge_funnel_in0>;
1683 }; 1675 };
1684 }; 1676 };
1685 }; 1677 };
1686 1678
1687 in-ports { 1679 in-ports {
1688 #address-cell 1680 #address-cells = <1>;
1689 #size-cells = 1681 #size-cells = <0>;
1690 1682
1691 port@7 { 1683 port@7 {
1692 reg = 1684 reg = <7>;
1693 funne 1685 funnel0_in7: endpoint {
1694 1686 remote-endpoint = <&stm_out>;
1695 }; 1687 };
1696 }; 1688 };
1697 }; 1689 };
1698 }; 1690 };
1699 1691
1700 funnel2: funnel@6042000 { 1692 funnel2: funnel@6042000 {
1701 compatible = "arm,cor 1693 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1702 reg = <0x06042000 0x1 1694 reg = <0x06042000 0x1000>;
1703 status = "disabled"; 1695 status = "disabled";
1704 1696
1705 clocks = <&rpmcc RPM_ 1697 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1706 clock-names = "apb_pc 1698 clock-names = "apb_pclk", "atclk";
1707 1699
1708 out-ports { 1700 out-ports {
1709 port { 1701 port {
1710 funne 1702 funnel1_out: endpoint {
1711 1703 remote-endpoint =
1712 1704 <&merge_funnel_in1>;
1713 }; 1705 };
1714 }; 1706 };
1715 }; 1707 };
1716 1708
1717 in-ports { 1709 in-ports {
1718 #address-cell 1710 #address-cells = <1>;
1719 #size-cells = 1711 #size-cells = <0>;
1720 1712
1721 port@6 { 1713 port@6 {
1722 reg = 1714 reg = <6>;
1723 funne 1715 funnel1_in6: endpoint {
1724 1716 remote-endpoint =
1725 1717 <&apss_merge_funnel_out>;
1726 }; 1718 };
1727 }; 1719 };
1728 }; 1720 };
1729 }; 1721 };
1730 1722
1731 funnel3: funnel@6045000 { 1723 funnel3: funnel@6045000 {
1732 compatible = "arm,cor 1724 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1733 reg = <0x06045000 0x1 1725 reg = <0x06045000 0x1000>;
1734 status = "disabled"; 1726 status = "disabled";
1735 1727
1736 clocks = <&rpmcc RPM_ 1728 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1737 clock-names = "apb_pc 1729 clock-names = "apb_pclk", "atclk";
1738 1730
1739 out-ports { 1731 out-ports {
1740 port { 1732 port {
1741 merge 1733 merge_funnel_out: endpoint {
1742 1734 remote-endpoint =
1743 1735 <&etf_in>;
1744 }; 1736 };
1745 }; 1737 };
1746 }; 1738 };
1747 1739
1748 in-ports { 1740 in-ports {
1749 #address-cell 1741 #address-cells = <1>;
1750 #size-cells = 1742 #size-cells = <0>;
1751 1743
1752 port@0 { 1744 port@0 {
1753 reg = 1745 reg = <0>;
1754 merge 1746 merge_funnel_in0: endpoint {
1755 1747 remote-endpoint =
1756 1748 <&funnel0_out>;
1757 }; 1749 };
1758 }; 1750 };
1759 1751
1760 port@1 { 1752 port@1 {
1761 reg = 1753 reg = <1>;
1762 merge 1754 merge_funnel_in1: endpoint {
1763 1755 remote-endpoint =
1764 1756 <&funnel1_out>;
1765 }; 1757 };
1766 }; 1758 };
1767 }; 1759 };
1768 }; 1760 };
1769 1761
1770 replicator1: replicator@60460 1762 replicator1: replicator@6046000 {
1771 compatible = "arm,cor 1763 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
1772 reg = <0x06046000 0x1 1764 reg = <0x06046000 0x1000>;
1773 status = "disabled"; 1765 status = "disabled";
1774 1766
1775 clocks = <&rpmcc RPM_ 1767 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1776 clock-names = "apb_pc 1768 clock-names = "apb_pclk", "atclk";
1777 1769
1778 out-ports { 1770 out-ports {
1779 port { 1771 port {
1780 repli 1772 replicator_out: endpoint {
1781 1773 remote-endpoint = <&etr_in>;
1782 }; 1774 };
1783 }; 1775 };
1784 }; 1776 };
1785 1777
1786 in-ports { 1778 in-ports {
1787 port { 1779 port {
1788 repli 1780 replicator_in: endpoint {
1789 1781 remote-endpoint = <&etf_out>;
1790 }; 1782 };
1791 }; 1783 };
1792 }; 1784 };
1793 }; 1785 };
1794 1786
1795 etf: etf@6047000 { 1787 etf: etf@6047000 {
1796 compatible = "arm,cor 1788 compatible = "arm,coresight-tmc", "arm,primecell";
1797 reg = <0x06047000 0x1 1789 reg = <0x06047000 0x1000>;
1798 status = "disabled"; 1790 status = "disabled";
1799 1791
1800 clocks = <&rpmcc RPM_ 1792 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1801 clock-names = "apb_pc 1793 clock-names = "apb_pclk", "atclk";
1802 1794
1803 out-ports { 1795 out-ports {
1804 port { 1796 port {
1805 etf_o 1797 etf_out: endpoint {
1806 1798 remote-endpoint =
1807 1799 <&replicator_in>;
1808 }; 1800 };
1809 }; 1801 };
1810 }; 1802 };
1811 1803
1812 in-ports { 1804 in-ports {
1813 port { 1805 port {
1814 etf_i 1806 etf_in: endpoint {
1815 1807 remote-endpoint =
1816 1808 <&merge_funnel_out>;
1817 }; 1809 };
1818 }; 1810 };
1819 }; 1811 };
1820 }; 1812 };
1821 1813
1822 etr: etr@6048000 { 1814 etr: etr@6048000 {
1823 compatible = "arm,cor 1815 compatible = "arm,coresight-tmc", "arm,primecell";
1824 reg = <0x06048000 0x1 1816 reg = <0x06048000 0x1000>;
1825 status = "disabled"; 1817 status = "disabled";
1826 1818
1827 clocks = <&rpmcc RPM_ 1819 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1828 clock-names = "apb_pc 1820 clock-names = "apb_pclk", "atclk";
1829 arm,scatter-gather; 1821 arm,scatter-gather;
1830 1822
1831 in-ports { 1823 in-ports {
1832 port { 1824 port {
1833 etr_i 1825 etr_in: endpoint {
1834 1826 remote-endpoint =
1835 1827 <&replicator_out>;
1836 }; 1828 };
1837 }; 1829 };
1838 }; 1830 };
1839 }; 1831 };
1840 1832
1841 etm1: etm@7840000 { 1833 etm1: etm@7840000 {
1842 compatible = "arm,cor 1834 compatible = "arm,coresight-etm4x", "arm,primecell";
1843 reg = <0x07840000 0x1 1835 reg = <0x07840000 0x1000>;
1844 status = "disabled"; 1836 status = "disabled";
1845 1837
1846 clocks = <&rpmcc RPM_ 1838 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1847 clock-names = "apb_pc 1839 clock-names = "apb_pclk", "atclk";
1848 1840
1849 cpu = <&CPU0>; 1841 cpu = <&CPU0>;
1850 1842
1851 out-ports { 1843 out-ports {
1852 port { 1844 port {
1853 etm0_ 1845 etm0_out: endpoint {
1854 1846 remote-endpoint =
1855 1847 <&apss_funnel_in0>;
1856 }; 1848 };
1857 }; 1849 };
1858 }; 1850 };
1859 }; 1851 };
1860 1852
1861 etm2: etm@7940000 { 1853 etm2: etm@7940000 {
1862 compatible = "arm,cor 1854 compatible = "arm,coresight-etm4x", "arm,primecell";
1863 reg = <0x07940000 0x1 1855 reg = <0x07940000 0x1000>;
1864 status = "disabled"; 1856 status = "disabled";
1865 1857
1866 clocks = <&rpmcc RPM_ 1858 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1867 clock-names = "apb_pc 1859 clock-names = "apb_pclk", "atclk";
1868 1860
1869 cpu = <&CPU1>; 1861 cpu = <&CPU1>;
1870 1862
1871 out-ports { 1863 out-ports {
1872 port { 1864 port {
1873 etm1_ 1865 etm1_out: endpoint {
1874 1866 remote-endpoint =
1875 1867 <&apss_funnel_in1>;
1876 }; 1868 };
1877 }; 1869 };
1878 }; 1870 };
1879 }; 1871 };
1880 1872
1881 etm3: etm@7a40000 { 1873 etm3: etm@7a40000 {
1882 compatible = "arm,cor 1874 compatible = "arm,coresight-etm4x", "arm,primecell";
1883 reg = <0x07a40000 0x1 1875 reg = <0x07a40000 0x1000>;
1884 status = "disabled"; 1876 status = "disabled";
1885 1877
1886 clocks = <&rpmcc RPM_ 1878 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1887 clock-names = "apb_pc 1879 clock-names = "apb_pclk", "atclk";
1888 1880
1889 cpu = <&CPU2>; 1881 cpu = <&CPU2>;
1890 1882
1891 out-ports { 1883 out-ports {
1892 port { 1884 port {
1893 etm2_ 1885 etm2_out: endpoint {
1894 1886 remote-endpoint =
1895 1887 <&apss_funnel_in2>;
1896 }; 1888 };
1897 }; 1889 };
1898 }; 1890 };
1899 }; 1891 };
1900 1892
1901 etm4: etm@7b40000 { 1893 etm4: etm@7b40000 {
1902 compatible = "arm,cor 1894 compatible = "arm,coresight-etm4x", "arm,primecell";
1903 reg = <0x07b40000 0x1 1895 reg = <0x07b40000 0x1000>;
1904 status = "disabled"; 1896 status = "disabled";
1905 1897
1906 clocks = <&rpmcc RPM_ 1898 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1907 clock-names = "apb_pc 1899 clock-names = "apb_pclk", "atclk";
1908 1900
1909 cpu = <&CPU3>; 1901 cpu = <&CPU3>;
1910 1902
1911 out-ports { 1903 out-ports {
1912 port { 1904 port {
1913 etm3_ 1905 etm3_out: endpoint {
1914 1906 remote-endpoint =
1915 1907 <&apss_funnel_in3>;
1916 }; 1908 };
1917 }; 1909 };
1918 }; 1910 };
1919 }; 1911 };
1920 1912
1921 funnel4: funnel@7b60000 { /* 1913 funnel4: funnel@7b60000 { /* APSS Funnel */
1922 compatible = "arm,cor 1914 compatible = "arm,coresight-etm4x", "arm,primecell";
1923 reg = <0x07b60000 0x1 1915 reg = <0x07b60000 0x1000>;
1924 status = "disabled"; 1916 status = "disabled";
1925 1917
1926 clocks = <&rpmcc RPM_ 1918 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1927 clock-names = "apb_pc 1919 clock-names = "apb_pclk", "atclk";
1928 1920
1929 out-ports { 1921 out-ports {
1930 port { 1922 port {
1931 apss_ 1923 apss_funnel_out: endpoint {
1932 1924 remote-endpoint =
1933 1925 <&apss_merge_funnel_in>;
1934 }; 1926 };
1935 }; 1927 };
1936 }; 1928 };
1937 1929
1938 in-ports { 1930 in-ports {
1939 #address-cell 1931 #address-cells = <1>;
1940 #size-cells = 1932 #size-cells = <0>;
1941 1933
1942 port@0 { 1934 port@0 {
1943 reg = 1935 reg = <0>;
1944 apss_ 1936 apss_funnel_in0: endpoint {
1945 1937 remote-endpoint =
1946 1938 <&etm0_out>;
1947 }; 1939 };
1948 }; 1940 };
1949 1941
1950 port@1 { 1942 port@1 {
1951 reg = 1943 reg = <1>;
1952 apss_ 1944 apss_funnel_in1: endpoint {
1953 1945 remote-endpoint =
1954 1946 <&etm1_out>;
1955 }; 1947 };
1956 }; 1948 };
1957 1949
1958 port@2 { 1950 port@2 {
1959 reg = 1951 reg = <2>;
1960 apss_ 1952 apss_funnel_in2: endpoint {
1961 1953 remote-endpoint =
1962 1954 <&etm2_out>;
1963 }; 1955 };
1964 }; 1956 };
1965 1957
1966 port@3 { 1958 port@3 {
1967 reg = 1959 reg = <3>;
1968 apss_ 1960 apss_funnel_in3: endpoint {
1969 1961 remote-endpoint =
1970 1962 <&etm3_out>;
1971 }; 1963 };
1972 }; 1964 };
1973 1965
1974 port@4 { 1966 port@4 {
1975 reg = 1967 reg = <4>;
1976 apss_ 1968 apss_funnel_in4: endpoint {
1977 1969 remote-endpoint =
1978 1970 <&etm4_out>;
1979 }; 1971 };
1980 }; 1972 };
1981 1973
1982 port@5 { 1974 port@5 {
1983 reg = 1975 reg = <5>;
1984 apss_ 1976 apss_funnel_in5: endpoint {
1985 1977 remote-endpoint =
1986 1978 <&etm5_out>;
1987 }; 1979 };
1988 }; 1980 };
1989 1981
1990 port@6 { 1982 port@6 {
1991 reg = 1983 reg = <6>;
1992 apss_ 1984 apss_funnel_in6: endpoint {
1993 1985 remote-endpoint =
1994 1986 <&etm6_out>;
1995 }; 1987 };
1996 }; 1988 };
1997 1989
1998 port@7 { 1990 port@7 {
1999 reg = 1991 reg = <7>;
2000 apss_ 1992 apss_funnel_in7: endpoint {
2001 1993 remote-endpoint =
2002 1994 <&etm7_out>;
2003 }; 1995 };
2004 }; 1996 };
2005 }; 1997 };
2006 }; 1998 };
2007 1999
2008 funnel5: funnel@7b70000 { 2000 funnel5: funnel@7b70000 {
2009 compatible = "arm,cor 2001 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2010 reg = <0x07b70000 0x1 2002 reg = <0x07b70000 0x1000>;
2011 status = "disabled"; 2003 status = "disabled";
2012 2004
2013 clocks = <&rpmcc RPM_ 2005 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2014 clock-names = "apb_pc 2006 clock-names = "apb_pclk", "atclk";
2015 2007
2016 out-ports { 2008 out-ports {
2017 port { 2009 port {
2018 apss_ 2010 apss_merge_funnel_out: endpoint {
2019 2011 remote-endpoint =
2020 2012 <&funnel1_in6>;
2021 }; 2013 };
2022 }; 2014 };
2023 }; 2015 };
2024 2016
2025 in-ports { 2017 in-ports {
2026 port { 2018 port {
2027 apss_ 2019 apss_merge_funnel_in: endpoint {
2028 2020 remote-endpoint =
2029 2021 <&apss_funnel_out>;
2030 }; 2022 };
2031 }; 2023 };
2032 }; 2024 };
2033 }; 2025 };
2034 2026
2035 etm5: etm@7c40000 { 2027 etm5: etm@7c40000 {
2036 compatible = "arm,cor 2028 compatible = "arm,coresight-etm4x", "arm,primecell";
2037 reg = <0x07c40000 0x1 2029 reg = <0x07c40000 0x1000>;
2038 status = "disabled"; 2030 status = "disabled";
2039 2031
2040 clocks = <&rpmcc RPM_ 2032 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2041 clock-names = "apb_pc 2033 clock-names = "apb_pclk", "atclk";
2042 2034
2043 cpu = <&CPU4>; 2035 cpu = <&CPU4>;
2044 2036
2045 out-ports { 2037 out-ports {
2046 port { 2038 port {
2047 etm4_ 2039 etm4_out: endpoint {
2048 2040 remote-endpoint = <&apss_funnel_in4>;
2049 }; 2041 };
2050 }; 2042 };
2051 }; 2043 };
2052 }; 2044 };
2053 2045
2054 etm6: etm@7d40000 { 2046 etm6: etm@7d40000 {
2055 compatible = "arm,cor 2047 compatible = "arm,coresight-etm4x", "arm,primecell";
2056 reg = <0x07d40000 0x1 2048 reg = <0x07d40000 0x1000>;
2057 status = "disabled"; 2049 status = "disabled";
2058 2050
2059 clocks = <&rpmcc RPM_ 2051 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2060 clock-names = "apb_pc 2052 clock-names = "apb_pclk", "atclk";
2061 2053
2062 cpu = <&CPU5>; 2054 cpu = <&CPU5>;
2063 2055
2064 out-ports { 2056 out-ports {
2065 port { 2057 port {
2066 etm5_ 2058 etm5_out: endpoint {
2067 2059 remote-endpoint = <&apss_funnel_in5>;
2068 }; 2060 };
2069 }; 2061 };
2070 }; 2062 };
2071 }; 2063 };
2072 2064
2073 etm7: etm@7e40000 { 2065 etm7: etm@7e40000 {
2074 compatible = "arm,cor 2066 compatible = "arm,coresight-etm4x", "arm,primecell";
2075 reg = <0x07e40000 0x1 2067 reg = <0x07e40000 0x1000>;
2076 status = "disabled"; 2068 status = "disabled";
2077 2069
2078 clocks = <&rpmcc RPM_ 2070 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2079 clock-names = "apb_pc 2071 clock-names = "apb_pclk", "atclk";
2080 2072
2081 cpu = <&CPU6>; 2073 cpu = <&CPU6>;
2082 2074
2083 out-ports { 2075 out-ports {
2084 port { 2076 port {
2085 etm6_ 2077 etm6_out: endpoint {
2086 2078 remote-endpoint = <&apss_funnel_in6>;
2087 }; 2079 };
2088 }; 2080 };
2089 }; 2081 };
2090 }; 2082 };
2091 2083
2092 etm8: etm@7f40000 { 2084 etm8: etm@7f40000 {
2093 compatible = "arm,cor 2085 compatible = "arm,coresight-etm4x", "arm,primecell";
2094 reg = <0x07f40000 0x1 2086 reg = <0x07f40000 0x1000>;
2095 status = "disabled"; 2087 status = "disabled";
2096 2088
2097 clocks = <&rpmcc RPM_ 2089 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2098 clock-names = "apb_pc 2090 clock-names = "apb_pclk", "atclk";
2099 2091
2100 cpu = <&CPU7>; 2092 cpu = <&CPU7>;
2101 2093
2102 out-ports { 2094 out-ports {
2103 port { 2095 port {
2104 etm7_ 2096 etm7_out: endpoint {
2105 2097 remote-endpoint = <&apss_funnel_in7>;
2106 }; 2098 };
2107 }; 2099 };
2108 }; 2100 };
2109 }; 2101 };
2110 2102
2111 sram@290000 { 2103 sram@290000 {
2112 compatible = "qcom,rp 2104 compatible = "qcom,rpm-stats";
2113 reg = <0x00290000 0x1 2105 reg = <0x00290000 0x10000>;
2114 }; 2106 };
2115 2107
2116 spmi_bus: spmi@800f000 { 2108 spmi_bus: spmi@800f000 {
2117 compatible = "qcom,sp 2109 compatible = "qcom,spmi-pmic-arb";
2118 reg = <0x0800f000 0x1 2110 reg = <0x0800f000 0x1000>,
2119 <0x08400000 0x1 2111 <0x08400000 0x1000000>,
2120 <0x09400000 0x1 2112 <0x09400000 0x1000000>,
2121 <0x0a400000 0x2 2113 <0x0a400000 0x220000>,
2122 <0x0800a000 0x3 2114 <0x0800a000 0x3000>;
2123 reg-names = "core", " 2115 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
2124 interrupt-names = "pe 2116 interrupt-names = "periph_irq";
2125 interrupts = <GIC_SPI 2117 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
2126 qcom,ee = <0>; 2118 qcom,ee = <0>;
2127 qcom,channel = <0>; 2119 qcom,channel = <0>;
2128 #address-cells = <2>; 2120 #address-cells = <2>;
2129 #size-cells = <0>; 2121 #size-cells = <0>;
2130 interrupt-controller; 2122 interrupt-controller;
2131 #interrupt-cells = <4 2123 #interrupt-cells = <4>;
2132 }; 2124 };
2133 2125
2134 usb3: usb@a8f8800 { 2126 usb3: usb@a8f8800 {
2135 compatible = "qcom,ms 2127 compatible = "qcom,msm8998-dwc3", "qcom,dwc3";
2136 reg = <0x0a8f8800 0x4 2128 reg = <0x0a8f8800 0x400>;
2137 status = "disabled"; 2129 status = "disabled";
2138 #address-cells = <1>; 2130 #address-cells = <1>;
2139 #size-cells = <1>; 2131 #size-cells = <1>;
2140 ranges; 2132 ranges;
2141 2133
2142 clocks = <&gcc GCC_CF 2134 clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>,
2143 <&gcc GCC_US 2135 <&gcc GCC_USB30_MASTER_CLK>,
2144 <&gcc GCC_AG 2136 <&gcc GCC_AGGRE1_USB3_AXI_CLK>,
2145 <&gcc GCC_US 2137 <&gcc GCC_USB30_SLEEP_CLK>,
2146 <&gcc GCC_US 2138 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
2147 clock-names = "cfg_no 2139 clock-names = "cfg_noc",
2148 "core", 2140 "core",
2149 "iface" 2141 "iface",
2150 "sleep" 2142 "sleep",
2151 "mock_u 2143 "mock_utmi";
2152 2144
2153 assigned-clocks = <&g 2145 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
2154 <&g 2146 <&gcc GCC_USB30_MASTER_CLK>;
2155 assigned-clock-rates 2147 assigned-clock-rates = <19200000>, <120000000>;
2156 2148
2157 interrupts = <GIC_SPI 2149 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
2158 <GIC_SPI 2150 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
2159 <GIC_SPI 2151 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
2160 interrupt-names = "pw 2152 interrupt-names = "pwr_event",
2161 "qu 2153 "qusb2_phy",
2162 "ss 2154 "ss_phy_irq";
2163 2155
2164 power-domains = <&gcc 2156 power-domains = <&gcc USB_30_GDSC>;
2165 2157
2166 resets = <&gcc GCC_US 2158 resets = <&gcc GCC_USB_30_BCR>;
2167 2159
2168 usb3_dwc3: usb@a80000 2160 usb3_dwc3: usb@a800000 {
2169 compatible = 2161 compatible = "snps,dwc3";
2170 reg = <0x0a80 2162 reg = <0x0a800000 0xcd00>;
2171 interrupts = 2163 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
2172 snps,dis_u2_s 2164 snps,dis_u2_susphy_quirk;
2173 snps,dis_enbl 2165 snps,dis_enblslpm_quirk;
2174 snps,parkmode 2166 snps,parkmode-disable-ss-quirk;
2175 phys = <&qusb 2167 phys = <&qusb2phy>, <&usb3phy>;
2176 phy-names = " 2168 phy-names = "usb2-phy", "usb3-phy";
2177 snps,has-lpm- 2169 snps,has-lpm-erratum;
2178 snps,hird-thr 2170 snps,hird-threshold = /bits/ 8 <0x10>;
2179 }; 2171 };
2180 }; 2172 };
2181 2173
2182 usb3phy: phy@c010000 { 2174 usb3phy: phy@c010000 {
2183 compatible = "qcom,ms 2175 compatible = "qcom,msm8998-qmp-usb3-phy";
2184 reg = <0x0c010000 0x1 2176 reg = <0x0c010000 0x1000>;
2185 2177
2186 clocks = <&gcc GCC_US 2178 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
2187 <&gcc GCC_US 2179 <&gcc GCC_USB3_CLKREF_CLK>,
2188 <&gcc GCC_US 2180 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2189 <&gcc GCC_US 2181 <&gcc GCC_USB3_PHY_PIPE_CLK>;
2190 clock-names = "aux", 2182 clock-names = "aux",
2191 "ref", 2183 "ref",
2192 "cfg_ah 2184 "cfg_ahb",
2193 "pipe"; 2185 "pipe";
2194 clock-output-names = 2186 clock-output-names = "usb3_phy_pipe_clk_src";
2195 #clock-cells = <0>; 2187 #clock-cells = <0>;
2196 #phy-cells = <0>; 2188 #phy-cells = <0>;
2197 2189
2198 resets = <&gcc GCC_US 2190 resets = <&gcc GCC_USB3_PHY_BCR>,
2199 <&gcc GCC_US 2191 <&gcc GCC_USB3PHY_PHY_BCR>;
2200 reset-names = "phy", 2192 reset-names = "phy",
2201 "phy_ph 2193 "phy_phy";
2202 2194
2203 qcom,tcsr-reg = <&tcs 2195 qcom,tcsr-reg = <&tcsr_regs_2 0xb244>;
2204 2196
2205 status = "disabled"; 2197 status = "disabled";
2206 }; 2198 };
2207 2199
2208 qusb2phy: phy@c012000 { 2200 qusb2phy: phy@c012000 {
2209 compatible = "qcom,ms 2201 compatible = "qcom,msm8998-qusb2-phy";
2210 reg = <0x0c012000 0x2 2202 reg = <0x0c012000 0x2a8>;
2211 status = "disabled"; 2203 status = "disabled";
2212 #phy-cells = <0>; 2204 #phy-cells = <0>;
2213 2205
2214 clocks = <&gcc GCC_US 2206 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2215 <&gcc GCC_RX 2207 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
2216 clock-names = "cfg_ah 2208 clock-names = "cfg_ahb", "ref";
2217 2209
2218 resets = <&gcc GCC_QU 2210 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2219 2211
2220 nvmem-cells = <&qusb2 2212 nvmem-cells = <&qusb2_hstx_trim>;
2221 }; 2213 };
2222 2214
2223 sdhc2: mmc@c0a4900 { 2215 sdhc2: mmc@c0a4900 {
2224 compatible = "qcom,ms 2216 compatible = "qcom,msm8998-sdhci", "qcom,sdhci-msm-v4";
2225 reg = <0x0c0a4900 0x3 2217 reg = <0x0c0a4900 0x314>, <0x0c0a4000 0x800>;
2226 reg-names = "hc", "co 2218 reg-names = "hc", "core";
2227 2219
2228 interrupts = <GIC_SPI 2220 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
2229 <GIC_SPI 2221 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
2230 interrupt-names = "hc 2222 interrupt-names = "hc_irq", "pwr_irq";
2231 2223
2232 clock-names = "iface" 2224 clock-names = "iface", "core", "xo";
2233 clocks = <&gcc GCC_SD 2225 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2234 <&gcc GCC_SD 2226 <&gcc GCC_SDCC2_APPS_CLK>,
2235 <&rpmcc RPM_ 2227 <&rpmcc RPM_SMD_XO_CLK_SRC>;
2236 bus-width = <4>; 2228 bus-width = <4>;
2237 status = "disabled"; 2229 status = "disabled";
2238 }; 2230 };
2239 2231
2240 blsp1_dma: dma-controller@c14 2232 blsp1_dma: dma-controller@c144000 {
2241 compatible = "qcom,ba 2233 compatible = "qcom,bam-v1.7.0";
2242 reg = <0x0c144000 0x2 2234 reg = <0x0c144000 0x25000>;
2243 interrupts = <GIC_SPI 2235 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
2244 clocks = <&gcc GCC_BL 2236 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
2245 clock-names = "bam_cl 2237 clock-names = "bam_clk";
2246 #dma-cells = <1>; 2238 #dma-cells = <1>;
2247 qcom,ee = <0>; 2239 qcom,ee = <0>;
2248 qcom,controlled-remot 2240 qcom,controlled-remotely;
2249 num-channels = <18>; 2241 num-channels = <18>;
2250 qcom,num-ees = <4>; 2242 qcom,num-ees = <4>;
2251 }; 2243 };
2252 2244
2253 blsp1_uart3: serial@c171000 { 2245 blsp1_uart3: serial@c171000 {
2254 compatible = "qcom,ms 2246 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2255 reg = <0x0c171000 0x1 2247 reg = <0x0c171000 0x1000>;
2256 interrupts = <GIC_SPI 2248 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
2257 clocks = <&gcc GCC_BL 2249 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
2258 <&gcc GCC_BL 2250 <&gcc GCC_BLSP1_AHB_CLK>;
2259 clock-names = "core", 2251 clock-names = "core", "iface";
2260 dmas = <&blsp1_dma 4> 2252 dmas = <&blsp1_dma 4>, <&blsp1_dma 5>;
2261 dma-names = "tx", "rx 2253 dma-names = "tx", "rx";
2262 pinctrl-names = "defa 2254 pinctrl-names = "default";
2263 pinctrl-0 = <&blsp1_u 2255 pinctrl-0 = <&blsp1_uart3_on>;
2264 status = "disabled"; 2256 status = "disabled";
2265 }; 2257 };
2266 2258
2267 blsp1_i2c1: i2c@c175000 { 2259 blsp1_i2c1: i2c@c175000 {
2268 compatible = "qcom,i2 2260 compatible = "qcom,i2c-qup-v2.2.1";
2269 reg = <0x0c175000 0x6 2261 reg = <0x0c175000 0x600>;
2270 interrupts = <GIC_SPI 2262 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
2271 2263
2272 clocks = <&gcc GCC_BL 2264 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
2273 <&gcc GCC_BL 2265 <&gcc GCC_BLSP1_AHB_CLK>;
2274 clock-names = "core", 2266 clock-names = "core", "iface";
2275 dmas = <&blsp1_dma 6> 2267 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>;
2276 dma-names = "tx", "rx 2268 dma-names = "tx", "rx";
2277 pinctrl-names = "defa 2269 pinctrl-names = "default", "sleep";
2278 pinctrl-0 = <&blsp1_i 2270 pinctrl-0 = <&blsp1_i2c1_default>;
2279 pinctrl-1 = <&blsp1_i 2271 pinctrl-1 = <&blsp1_i2c1_sleep>;
2280 clock-frequency = <40 2272 clock-frequency = <400000>;
2281 2273
2282 status = "disabled"; 2274 status = "disabled";
2283 #address-cells = <1>; 2275 #address-cells = <1>;
2284 #size-cells = <0>; 2276 #size-cells = <0>;
2285 }; 2277 };
2286 2278
2287 blsp1_i2c2: i2c@c176000 { 2279 blsp1_i2c2: i2c@c176000 {
2288 compatible = "qcom,i2 2280 compatible = "qcom,i2c-qup-v2.2.1";
2289 reg = <0x0c176000 0x6 2281 reg = <0x0c176000 0x600>;
2290 interrupts = <GIC_SPI 2282 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
2291 2283
2292 clocks = <&gcc GCC_BL 2284 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
2293 <&gcc GCC_BL 2285 <&gcc GCC_BLSP1_AHB_CLK>;
2294 clock-names = "core", 2286 clock-names = "core", "iface";
2295 dmas = <&blsp1_dma 8> 2287 dmas = <&blsp1_dma 8>, <&blsp1_dma 9>;
2296 dma-names = "tx", "rx 2288 dma-names = "tx", "rx";
2297 pinctrl-names = "defa 2289 pinctrl-names = "default", "sleep";
2298 pinctrl-0 = <&blsp1_i 2290 pinctrl-0 = <&blsp1_i2c2_default>;
2299 pinctrl-1 = <&blsp1_i 2291 pinctrl-1 = <&blsp1_i2c2_sleep>;
2300 clock-frequency = <40 2292 clock-frequency = <400000>;
2301 2293
2302 status = "disabled"; 2294 status = "disabled";
2303 #address-cells = <1>; 2295 #address-cells = <1>;
2304 #size-cells = <0>; 2296 #size-cells = <0>;
2305 }; 2297 };
2306 2298
2307 blsp1_i2c3: i2c@c177000 { 2299 blsp1_i2c3: i2c@c177000 {
2308 compatible = "qcom,i2 2300 compatible = "qcom,i2c-qup-v2.2.1";
2309 reg = <0x0c177000 0x6 2301 reg = <0x0c177000 0x600>;
2310 interrupts = <GIC_SPI 2302 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
2311 2303
2312 clocks = <&gcc GCC_BL 2304 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
2313 <&gcc GCC_BL 2305 <&gcc GCC_BLSP1_AHB_CLK>;
2314 clock-names = "core", 2306 clock-names = "core", "iface";
2315 dmas = <&blsp1_dma 10 2307 dmas = <&blsp1_dma 10>, <&blsp1_dma 11>;
2316 dma-names = "tx", "rx 2308 dma-names = "tx", "rx";
2317 pinctrl-names = "defa 2309 pinctrl-names = "default", "sleep";
2318 pinctrl-0 = <&blsp1_i 2310 pinctrl-0 = <&blsp1_i2c3_default>;
2319 pinctrl-1 = <&blsp1_i 2311 pinctrl-1 = <&blsp1_i2c3_sleep>;
2320 clock-frequency = <40 2312 clock-frequency = <400000>;
2321 2313
2322 status = "disabled"; 2314 status = "disabled";
2323 #address-cells = <1>; 2315 #address-cells = <1>;
2324 #size-cells = <0>; 2316 #size-cells = <0>;
2325 }; 2317 };
2326 2318
2327 blsp1_i2c4: i2c@c178000 { 2319 blsp1_i2c4: i2c@c178000 {
2328 compatible = "qcom,i2 2320 compatible = "qcom,i2c-qup-v2.2.1";
2329 reg = <0x0c178000 0x6 2321 reg = <0x0c178000 0x600>;
2330 interrupts = <GIC_SPI 2322 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
2331 2323
2332 clocks = <&gcc GCC_BL 2324 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
2333 <&gcc GCC_BL 2325 <&gcc GCC_BLSP1_AHB_CLK>;
2334 clock-names = "core", 2326 clock-names = "core", "iface";
2335 dmas = <&blsp1_dma 12 2327 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
2336 dma-names = "tx", "rx 2328 dma-names = "tx", "rx";
2337 pinctrl-names = "defa 2329 pinctrl-names = "default", "sleep";
2338 pinctrl-0 = <&blsp1_i 2330 pinctrl-0 = <&blsp1_i2c4_default>;
2339 pinctrl-1 = <&blsp1_i 2331 pinctrl-1 = <&blsp1_i2c4_sleep>;
2340 clock-frequency = <40 2332 clock-frequency = <400000>;
2341 2333
2342 status = "disabled"; 2334 status = "disabled";
2343 #address-cells = <1>; 2335 #address-cells = <1>;
2344 #size-cells = <0>; 2336 #size-cells = <0>;
2345 }; 2337 };
2346 2338
2347 blsp1_i2c5: i2c@c179000 { 2339 blsp1_i2c5: i2c@c179000 {
2348 compatible = "qcom,i2 2340 compatible = "qcom,i2c-qup-v2.2.1";
2349 reg = <0x0c179000 0x6 2341 reg = <0x0c179000 0x600>;
2350 interrupts = <GIC_SPI 2342 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
2351 2343
2352 clocks = <&gcc GCC_BL 2344 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
2353 <&gcc GCC_BL 2345 <&gcc GCC_BLSP1_AHB_CLK>;
2354 clock-names = "core", 2346 clock-names = "core", "iface";
2355 dmas = <&blsp1_dma 14 2347 dmas = <&blsp1_dma 14>, <&blsp1_dma 15>;
2356 dma-names = "tx", "rx 2348 dma-names = "tx", "rx";
2357 pinctrl-names = "defa 2349 pinctrl-names = "default", "sleep";
2358 pinctrl-0 = <&blsp1_i 2350 pinctrl-0 = <&blsp1_i2c5_default>;
2359 pinctrl-1 = <&blsp1_i 2351 pinctrl-1 = <&blsp1_i2c5_sleep>;
2360 clock-frequency = <40 2352 clock-frequency = <400000>;
2361 2353
2362 status = "disabled"; 2354 status = "disabled";
2363 #address-cells = <1>; 2355 #address-cells = <1>;
2364 #size-cells = <0>; 2356 #size-cells = <0>;
2365 }; 2357 };
2366 2358
2367 blsp1_i2c6: i2c@c17a000 { 2359 blsp1_i2c6: i2c@c17a000 {
2368 compatible = "qcom,i2 2360 compatible = "qcom,i2c-qup-v2.2.1";
2369 reg = <0x0c17a000 0x6 2361 reg = <0x0c17a000 0x600>;
2370 interrupts = <GIC_SPI 2362 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
2371 2363
2372 clocks = <&gcc GCC_BL 2364 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
2373 <&gcc GCC_BL 2365 <&gcc GCC_BLSP1_AHB_CLK>;
2374 clock-names = "core", 2366 clock-names = "core", "iface";
2375 dmas = <&blsp1_dma 16 2367 dmas = <&blsp1_dma 16>, <&blsp1_dma 17>;
2376 dma-names = "tx", "rx 2368 dma-names = "tx", "rx";
2377 pinctrl-names = "defa 2369 pinctrl-names = "default", "sleep";
2378 pinctrl-0 = <&blsp1_i 2370 pinctrl-0 = <&blsp1_i2c6_default>;
2379 pinctrl-1 = <&blsp1_i 2371 pinctrl-1 = <&blsp1_i2c6_sleep>;
2380 clock-frequency = <40 2372 clock-frequency = <400000>;
2381 2373
2382 status = "disabled"; 2374 status = "disabled";
2383 #address-cells = <1>; 2375 #address-cells = <1>;
2384 #size-cells = <0>; 2376 #size-cells = <0>;
2385 }; 2377 };
2386 2378
2387 blsp1_spi1: spi@c175000 { 2379 blsp1_spi1: spi@c175000 {
2388 compatible = "qcom,sp 2380 compatible = "qcom,spi-qup-v2.2.1";
2389 reg = <0x0c175000 0x6 2381 reg = <0x0c175000 0x600>;
2390 interrupts = <GIC_SPI 2382 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
2391 2383
2392 clocks = <&gcc GCC_BL 2384 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
2393 <&gcc GCC_BL 2385 <&gcc GCC_BLSP1_AHB_CLK>;
2394 clock-names = "core", 2386 clock-names = "core", "iface";
2395 dmas = <&blsp1_dma 6> 2387 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>;
2396 dma-names = "tx", "rx 2388 dma-names = "tx", "rx";
2397 pinctrl-names = "defa 2389 pinctrl-names = "default";
2398 pinctrl-0 = <&blsp1_s 2390 pinctrl-0 = <&blsp1_spi1_default>;
2399 2391
2400 status = "disabled"; 2392 status = "disabled";
2401 #address-cells = <1>; 2393 #address-cells = <1>;
2402 #size-cells = <0>; 2394 #size-cells = <0>;
2403 }; 2395 };
2404 2396
2405 blsp1_spi2: spi@c176000 { 2397 blsp1_spi2: spi@c176000 {
2406 compatible = "qcom,sp 2398 compatible = "qcom,spi-qup-v2.2.1";
2407 reg = <0x0c176000 0x6 2399 reg = <0x0c176000 0x600>;
2408 interrupts = <GIC_SPI 2400 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
2409 2401
2410 clocks = <&gcc GCC_BL 2402 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
2411 <&gcc GCC_BL 2403 <&gcc GCC_BLSP1_AHB_CLK>;
2412 clock-names = "core", 2404 clock-names = "core", "iface";
2413 dmas = <&blsp1_dma 8> 2405 dmas = <&blsp1_dma 8>, <&blsp1_dma 9>;
2414 dma-names = "tx", "rx 2406 dma-names = "tx", "rx";
2415 pinctrl-names = "defa 2407 pinctrl-names = "default";
2416 pinctrl-0 = <&blsp1_s 2408 pinctrl-0 = <&blsp1_spi2_default>;
2417 2409
2418 status = "disabled"; 2410 status = "disabled";
2419 #address-cells = <1>; 2411 #address-cells = <1>;
2420 #size-cells = <0>; 2412 #size-cells = <0>;
2421 }; 2413 };
2422 2414
2423 blsp1_spi3: spi@c177000 { 2415 blsp1_spi3: spi@c177000 {
2424 compatible = "qcom,sp 2416 compatible = "qcom,spi-qup-v2.2.1";
2425 reg = <0x0c177000 0x6 2417 reg = <0x0c177000 0x600>;
2426 interrupts = <GIC_SPI 2418 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
2427 2419
2428 clocks = <&gcc GCC_BL 2420 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
2429 <&gcc GCC_BL 2421 <&gcc GCC_BLSP1_AHB_CLK>;
2430 clock-names = "core", 2422 clock-names = "core", "iface";
2431 dmas = <&blsp1_dma 10 2423 dmas = <&blsp1_dma 10>, <&blsp1_dma 11>;
2432 dma-names = "tx", "rx 2424 dma-names = "tx", "rx";
2433 pinctrl-names = "defa 2425 pinctrl-names = "default";
2434 pinctrl-0 = <&blsp1_s 2426 pinctrl-0 = <&blsp1_spi3_default>;
2435 2427
2436 status = "disabled"; 2428 status = "disabled";
2437 #address-cells = <1>; 2429 #address-cells = <1>;
2438 #size-cells = <0>; 2430 #size-cells = <0>;
2439 }; 2431 };
2440 2432
2441 blsp1_spi4: spi@c178000 { 2433 blsp1_spi4: spi@c178000 {
2442 compatible = "qcom,sp 2434 compatible = "qcom,spi-qup-v2.2.1";
2443 reg = <0x0c178000 0x6 2435 reg = <0x0c178000 0x600>;
2444 interrupts = <GIC_SPI 2436 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
2445 2437
2446 clocks = <&gcc GCC_BL 2438 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
2447 <&gcc GCC_BL 2439 <&gcc GCC_BLSP1_AHB_CLK>;
2448 clock-names = "core", 2440 clock-names = "core", "iface";
2449 dmas = <&blsp1_dma 12 2441 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
2450 dma-names = "tx", "rx 2442 dma-names = "tx", "rx";
2451 pinctrl-names = "defa 2443 pinctrl-names = "default";
2452 pinctrl-0 = <&blsp1_s 2444 pinctrl-0 = <&blsp1_spi4_default>;
2453 2445
2454 status = "disabled"; 2446 status = "disabled";
2455 #address-cells = <1>; 2447 #address-cells = <1>;
2456 #size-cells = <0>; 2448 #size-cells = <0>;
2457 }; 2449 };
2458 2450
2459 blsp1_spi5: spi@c179000 { 2451 blsp1_spi5: spi@c179000 {
2460 compatible = "qcom,sp 2452 compatible = "qcom,spi-qup-v2.2.1";
2461 reg = <0x0c179000 0x6 2453 reg = <0x0c179000 0x600>;
2462 interrupts = <GIC_SPI 2454 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
2463 2455
2464 clocks = <&gcc GCC_BL 2456 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
2465 <&gcc GCC_BL 2457 <&gcc GCC_BLSP1_AHB_CLK>;
2466 clock-names = "core", 2458 clock-names = "core", "iface";
2467 dmas = <&blsp1_dma 14 2459 dmas = <&blsp1_dma 14>, <&blsp1_dma 15>;
2468 dma-names = "tx", "rx 2460 dma-names = "tx", "rx";
2469 pinctrl-names = "defa 2461 pinctrl-names = "default";
2470 pinctrl-0 = <&blsp1_s 2462 pinctrl-0 = <&blsp1_spi5_default>;
2471 2463
2472 status = "disabled"; 2464 status = "disabled";
2473 #address-cells = <1>; 2465 #address-cells = <1>;
2474 #size-cells = <0>; 2466 #size-cells = <0>;
2475 }; 2467 };
2476 2468
2477 blsp1_spi6: spi@c17a000 { 2469 blsp1_spi6: spi@c17a000 {
2478 compatible = "qcom,sp 2470 compatible = "qcom,spi-qup-v2.2.1";
2479 reg = <0x0c17a000 0x6 2471 reg = <0x0c17a000 0x600>;
2480 interrupts = <GIC_SPI 2472 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
2481 2473
2482 clocks = <&gcc GCC_BL 2474 clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
2483 <&gcc GCC_BL 2475 <&gcc GCC_BLSP1_AHB_CLK>;
2484 clock-names = "core", 2476 clock-names = "core", "iface";
2485 dmas = <&blsp1_dma 16 2477 dmas = <&blsp1_dma 16>, <&blsp1_dma 17>;
2486 dma-names = "tx", "rx 2478 dma-names = "tx", "rx";
2487 pinctrl-names = "defa 2479 pinctrl-names = "default";
2488 pinctrl-0 = <&blsp1_s 2480 pinctrl-0 = <&blsp1_spi6_default>;
2489 2481
2490 status = "disabled"; 2482 status = "disabled";
2491 #address-cells = <1>; 2483 #address-cells = <1>;
2492 #size-cells = <0>; 2484 #size-cells = <0>;
2493 }; 2485 };
2494 2486
2495 blsp2_dma: dma-controller@c18 2487 blsp2_dma: dma-controller@c184000 {
2496 compatible = "qcom,ba 2488 compatible = "qcom,bam-v1.7.0";
2497 reg = <0x0c184000 0x2 2489 reg = <0x0c184000 0x25000>;
2498 interrupts = <GIC_SPI 2490 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
2499 clocks = <&gcc GCC_BL 2491 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
2500 clock-names = "bam_cl 2492 clock-names = "bam_clk";
2501 #dma-cells = <1>; 2493 #dma-cells = <1>;
2502 qcom,ee = <0>; 2494 qcom,ee = <0>;
2503 qcom,controlled-remot 2495 qcom,controlled-remotely;
2504 num-channels = <18>; 2496 num-channels = <18>;
2505 qcom,num-ees = <4>; 2497 qcom,num-ees = <4>;
2506 }; 2498 };
2507 2499
2508 blsp2_uart1: serial@c1b0000 { 2500 blsp2_uart1: serial@c1b0000 {
2509 compatible = "qcom,ms 2501 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2510 reg = <0x0c1b0000 0x1 2502 reg = <0x0c1b0000 0x1000>;
2511 interrupts = <GIC_SPI 2503 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
2512 clocks = <&gcc GCC_BL 2504 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
2513 <&gcc GCC_BL 2505 <&gcc GCC_BLSP2_AHB_CLK>;
2514 clock-names = "core", 2506 clock-names = "core", "iface";
2515 status = "disabled"; 2507 status = "disabled";
2516 }; 2508 };
2517 2509
2518 blsp2_i2c1: i2c@c1b5000 { 2510 blsp2_i2c1: i2c@c1b5000 {
2519 compatible = "qcom,i2 2511 compatible = "qcom,i2c-qup-v2.2.1";
2520 reg = <0x0c1b5000 0x6 2512 reg = <0x0c1b5000 0x600>;
2521 interrupts = <GIC_SPI 2513 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
2522 2514
2523 clocks = <&gcc GCC_BL 2515 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
2524 <&gcc GCC_BL 2516 <&gcc GCC_BLSP2_AHB_CLK>;
2525 clock-names = "core", 2517 clock-names = "core", "iface";
2526 dmas = <&blsp2_dma 6> 2518 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>;
2527 dma-names = "tx", "rx 2519 dma-names = "tx", "rx";
2528 pinctrl-names = "defa 2520 pinctrl-names = "default", "sleep";
2529 pinctrl-0 = <&blsp2_i 2521 pinctrl-0 = <&blsp2_i2c1_default>;
2530 pinctrl-1 = <&blsp2_i 2522 pinctrl-1 = <&blsp2_i2c1_sleep>;
2531 clock-frequency = <40 2523 clock-frequency = <400000>;
2532 2524
2533 status = "disabled"; 2525 status = "disabled";
2534 #address-cells = <1>; 2526 #address-cells = <1>;
2535 #size-cells = <0>; 2527 #size-cells = <0>;
2536 }; 2528 };
2537 2529
2538 blsp2_i2c2: i2c@c1b6000 { 2530 blsp2_i2c2: i2c@c1b6000 {
2539 compatible = "qcom,i2 2531 compatible = "qcom,i2c-qup-v2.2.1";
2540 reg = <0x0c1b6000 0x6 2532 reg = <0x0c1b6000 0x600>;
2541 interrupts = <GIC_SPI 2533 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
2542 2534
2543 clocks = <&gcc GCC_BL 2535 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
2544 <&gcc GCC_BL 2536 <&gcc GCC_BLSP2_AHB_CLK>;
2545 clock-names = "core", 2537 clock-names = "core", "iface";
2546 dmas = <&blsp2_dma 8> 2538 dmas = <&blsp2_dma 8>, <&blsp2_dma 9>;
2547 dma-names = "tx", "rx 2539 dma-names = "tx", "rx";
2548 pinctrl-names = "defa 2540 pinctrl-names = "default", "sleep";
2549 pinctrl-0 = <&blsp2_i 2541 pinctrl-0 = <&blsp2_i2c2_default>;
2550 pinctrl-1 = <&blsp2_i 2542 pinctrl-1 = <&blsp2_i2c2_sleep>;
2551 clock-frequency = <40 2543 clock-frequency = <400000>;
2552 2544
2553 status = "disabled"; 2545 status = "disabled";
2554 #address-cells = <1>; 2546 #address-cells = <1>;
2555 #size-cells = <0>; 2547 #size-cells = <0>;
2556 }; 2548 };
2557 2549
2558 blsp2_i2c3: i2c@c1b7000 { 2550 blsp2_i2c3: i2c@c1b7000 {
2559 compatible = "qcom,i2 2551 compatible = "qcom,i2c-qup-v2.2.1";
2560 reg = <0x0c1b7000 0x6 2552 reg = <0x0c1b7000 0x600>;
2561 interrupts = <GIC_SPI 2553 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
2562 2554
2563 clocks = <&gcc GCC_BL 2555 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
2564 <&gcc GCC_BL 2556 <&gcc GCC_BLSP2_AHB_CLK>;
2565 clock-names = "core", 2557 clock-names = "core", "iface";
2566 dmas = <&blsp2_dma 10 2558 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>;
2567 dma-names = "tx", "rx 2559 dma-names = "tx", "rx";
2568 pinctrl-names = "defa 2560 pinctrl-names = "default", "sleep";
2569 pinctrl-0 = <&blsp2_i 2561 pinctrl-0 = <&blsp2_i2c3_default>;
2570 pinctrl-1 = <&blsp2_i 2562 pinctrl-1 = <&blsp2_i2c3_sleep>;
2571 clock-frequency = <40 2563 clock-frequency = <400000>;
2572 2564
2573 status = "disabled"; 2565 status = "disabled";
2574 #address-cells = <1>; 2566 #address-cells = <1>;
2575 #size-cells = <0>; 2567 #size-cells = <0>;
2576 }; 2568 };
2577 2569
2578 blsp2_i2c4: i2c@c1b8000 { 2570 blsp2_i2c4: i2c@c1b8000 {
2579 compatible = "qcom,i2 2571 compatible = "qcom,i2c-qup-v2.2.1";
2580 reg = <0x0c1b8000 0x6 2572 reg = <0x0c1b8000 0x600>;
2581 interrupts = <GIC_SPI 2573 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
2582 2574
2583 clocks = <&gcc GCC_BL 2575 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>,
2584 <&gcc GCC_BL 2576 <&gcc GCC_BLSP2_AHB_CLK>;
2585 clock-names = "core", 2577 clock-names = "core", "iface";
2586 dmas = <&blsp2_dma 12 2578 dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
2587 dma-names = "tx", "rx 2579 dma-names = "tx", "rx";
2588 pinctrl-names = "defa 2580 pinctrl-names = "default", "sleep";
2589 pinctrl-0 = <&blsp2_i 2581 pinctrl-0 = <&blsp2_i2c4_default>;
2590 pinctrl-1 = <&blsp2_i 2582 pinctrl-1 = <&blsp2_i2c4_sleep>;
2591 clock-frequency = <40 2583 clock-frequency = <400000>;
2592 2584
2593 status = "disabled"; 2585 status = "disabled";
2594 #address-cells = <1>; 2586 #address-cells = <1>;
2595 #size-cells = <0>; 2587 #size-cells = <0>;
2596 }; 2588 };
2597 2589
2598 blsp2_i2c5: i2c@c1b9000 { 2590 blsp2_i2c5: i2c@c1b9000 {
2599 compatible = "qcom,i2 2591 compatible = "qcom,i2c-qup-v2.2.1";
2600 reg = <0x0c1b9000 0x6 2592 reg = <0x0c1b9000 0x600>;
2601 interrupts = <GIC_SPI 2593 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
2602 2594
2603 clocks = <&gcc GCC_BL 2595 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,
2604 <&gcc GCC_BL 2596 <&gcc GCC_BLSP2_AHB_CLK>;
2605 clock-names = "core", 2597 clock-names = "core", "iface";
2606 dmas = <&blsp2_dma 14 2598 dmas = <&blsp2_dma 14>, <&blsp2_dma 15>;
2607 dma-names = "tx", "rx 2599 dma-names = "tx", "rx";
2608 pinctrl-names = "defa 2600 pinctrl-names = "default", "sleep";
2609 pinctrl-0 = <&blsp2_i 2601 pinctrl-0 = <&blsp2_i2c5_default>;
2610 pinctrl-1 = <&blsp2_i 2602 pinctrl-1 = <&blsp2_i2c5_sleep>;
2611 clock-frequency = <40 2603 clock-frequency = <400000>;
2612 2604
2613 status = "disabled"; 2605 status = "disabled";
2614 #address-cells = <1>; 2606 #address-cells = <1>;
2615 #size-cells = <0>; 2607 #size-cells = <0>;
2616 }; 2608 };
2617 2609
2618 blsp2_i2c6: i2c@c1ba000 { 2610 blsp2_i2c6: i2c@c1ba000 {
2619 compatible = "qcom,i2 2611 compatible = "qcom,i2c-qup-v2.2.1";
2620 reg = <0x0c1ba000 0x6 2612 reg = <0x0c1ba000 0x600>;
2621 interrupts = <GIC_SPI 2613 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
2622 2614
2623 clocks = <&gcc GCC_BL 2615 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>,
2624 <&gcc GCC_BL 2616 <&gcc GCC_BLSP2_AHB_CLK>;
2625 clock-names = "core", 2617 clock-names = "core", "iface";
2626 dmas = <&blsp2_dma 16 2618 dmas = <&blsp2_dma 16>, <&blsp2_dma 17>;
2627 dma-names = "tx", "rx 2619 dma-names = "tx", "rx";
2628 pinctrl-names = "defa 2620 pinctrl-names = "default", "sleep";
2629 pinctrl-0 = <&blsp2_i 2621 pinctrl-0 = <&blsp2_i2c6_default>;
2630 pinctrl-1 = <&blsp2_i 2622 pinctrl-1 = <&blsp2_i2c6_sleep>;
2631 clock-frequency = <40 2623 clock-frequency = <400000>;
2632 2624
2633 status = "disabled"; 2625 status = "disabled";
2634 #address-cells = <1>; 2626 #address-cells = <1>;
2635 #size-cells = <0>; 2627 #size-cells = <0>;
2636 }; 2628 };
2637 2629
2638 blsp2_spi1: spi@c1b5000 { 2630 blsp2_spi1: spi@c1b5000 {
2639 compatible = "qcom,sp 2631 compatible = "qcom,spi-qup-v2.2.1";
2640 reg = <0x0c1b5000 0x6 2632 reg = <0x0c1b5000 0x600>;
2641 interrupts = <GIC_SPI 2633 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
2642 2634
2643 clocks = <&gcc GCC_BL 2635 clocks = <&gcc GCC_BLSP2_QUP1_SPI_APPS_CLK>,
2644 <&gcc GCC_BL 2636 <&gcc GCC_BLSP2_AHB_CLK>;
2645 clock-names = "core", 2637 clock-names = "core", "iface";
2646 dmas = <&blsp2_dma 6> 2638 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>;
2647 dma-names = "tx", "rx 2639 dma-names = "tx", "rx";
2648 pinctrl-names = "defa 2640 pinctrl-names = "default";
2649 pinctrl-0 = <&blsp2_s 2641 pinctrl-0 = <&blsp2_spi1_default>;
2650 2642
2651 status = "disabled"; 2643 status = "disabled";
2652 #address-cells = <1>; 2644 #address-cells = <1>;
2653 #size-cells = <0>; 2645 #size-cells = <0>;
2654 }; 2646 };
2655 2647
2656 blsp2_spi2: spi@c1b6000 { 2648 blsp2_spi2: spi@c1b6000 {
2657 compatible = "qcom,sp 2649 compatible = "qcom,spi-qup-v2.2.1";
2658 reg = <0x0c1b6000 0x6 2650 reg = <0x0c1b6000 0x600>;
2659 interrupts = <GIC_SPI 2651 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
2660 2652
2661 clocks = <&gcc GCC_BL 2653 clocks = <&gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>,
2662 <&gcc GCC_BL 2654 <&gcc GCC_BLSP2_AHB_CLK>;
2663 clock-names = "core", 2655 clock-names = "core", "iface";
2664 dmas = <&blsp2_dma 8> 2656 dmas = <&blsp2_dma 8>, <&blsp2_dma 9>;
2665 dma-names = "tx", "rx 2657 dma-names = "tx", "rx";
2666 pinctrl-names = "defa 2658 pinctrl-names = "default";
2667 pinctrl-0 = <&blsp2_s 2659 pinctrl-0 = <&blsp2_spi2_default>;
2668 2660
2669 status = "disabled"; 2661 status = "disabled";
2670 #address-cells = <1>; 2662 #address-cells = <1>;
2671 #size-cells = <0>; 2663 #size-cells = <0>;
2672 }; 2664 };
2673 2665
2674 blsp2_spi3: spi@c1b7000 { 2666 blsp2_spi3: spi@c1b7000 {
2675 compatible = "qcom,sp 2667 compatible = "qcom,spi-qup-v2.2.1";
2676 reg = <0x0c1b7000 0x6 2668 reg = <0x0c1b7000 0x600>;
2677 interrupts = <GIC_SPI 2669 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
2678 2670
2679 clocks = <&gcc GCC_BL 2671 clocks = <&gcc GCC_BLSP2_QUP3_SPI_APPS_CLK>,
2680 <&gcc GCC_BL 2672 <&gcc GCC_BLSP2_AHB_CLK>;
2681 clock-names = "core", 2673 clock-names = "core", "iface";
2682 dmas = <&blsp2_dma 10 2674 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>;
2683 dma-names = "tx", "rx 2675 dma-names = "tx", "rx";
2684 pinctrl-names = "defa 2676 pinctrl-names = "default";
2685 pinctrl-0 = <&blsp2_s 2677 pinctrl-0 = <&blsp2_spi3_default>;
2686 2678
2687 status = "disabled"; 2679 status = "disabled";
2688 #address-cells = <1>; 2680 #address-cells = <1>;
2689 #size-cells = <0>; 2681 #size-cells = <0>;
2690 }; 2682 };
2691 2683
2692 blsp2_spi4: spi@c1b8000 { 2684 blsp2_spi4: spi@c1b8000 {
2693 compatible = "qcom,sp 2685 compatible = "qcom,spi-qup-v2.2.1";
2694 reg = <0x0c1b8000 0x6 2686 reg = <0x0c1b8000 0x600>;
2695 interrupts = <GIC_SPI 2687 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
2696 2688
2697 clocks = <&gcc GCC_BL 2689 clocks = <&gcc GCC_BLSP2_QUP4_SPI_APPS_CLK>,
2698 <&gcc GCC_BL 2690 <&gcc GCC_BLSP2_AHB_CLK>;
2699 clock-names = "core", 2691 clock-names = "core", "iface";
2700 dmas = <&blsp2_dma 12 2692 dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
2701 dma-names = "tx", "rx 2693 dma-names = "tx", "rx";
2702 pinctrl-names = "defa 2694 pinctrl-names = "default";
2703 pinctrl-0 = <&blsp2_s 2695 pinctrl-0 = <&blsp2_spi4_default>;
2704 2696
2705 status = "disabled"; 2697 status = "disabled";
2706 #address-cells = <1>; 2698 #address-cells = <1>;
2707 #size-cells = <0>; 2699 #size-cells = <0>;
2708 }; 2700 };
2709 2701
2710 blsp2_spi5: spi@c1b9000 { 2702 blsp2_spi5: spi@c1b9000 {
2711 compatible = "qcom,sp 2703 compatible = "qcom,spi-qup-v2.2.1";
2712 reg = <0x0c1b9000 0x6 2704 reg = <0x0c1b9000 0x600>;
2713 interrupts = <GIC_SPI 2705 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
2714 2706
2715 clocks = <&gcc GCC_BL 2707 clocks = <&gcc GCC_BLSP2_QUP5_SPI_APPS_CLK>,
2716 <&gcc GCC_BL 2708 <&gcc GCC_BLSP2_AHB_CLK>;
2717 clock-names = "core", 2709 clock-names = "core", "iface";
2718 dmas = <&blsp2_dma 14 2710 dmas = <&blsp2_dma 14>, <&blsp2_dma 15>;
2719 dma-names = "tx", "rx 2711 dma-names = "tx", "rx";
2720 pinctrl-names = "defa 2712 pinctrl-names = "default";
2721 pinctrl-0 = <&blsp2_s 2713 pinctrl-0 = <&blsp2_spi5_default>;
2722 2714
2723 status = "disabled"; 2715 status = "disabled";
2724 #address-cells = <1>; 2716 #address-cells = <1>;
2725 #size-cells = <0>; 2717 #size-cells = <0>;
2726 }; 2718 };
2727 2719
2728 blsp2_spi6: spi@c1ba000 { 2720 blsp2_spi6: spi@c1ba000 {
2729 compatible = "qcom,sp 2721 compatible = "qcom,spi-qup-v2.2.1";
2730 reg = <0x0c1ba000 0x6 2722 reg = <0x0c1ba000 0x600>;
2731 interrupts = <GIC_SPI 2723 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
2732 2724
2733 clocks = <&gcc GCC_BL 2725 clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>,
2734 <&gcc GCC_BL 2726 <&gcc GCC_BLSP2_AHB_CLK>;
2735 clock-names = "core", 2727 clock-names = "core", "iface";
2736 dmas = <&blsp2_dma 16 2728 dmas = <&blsp2_dma 16>, <&blsp2_dma 17>;
2737 dma-names = "tx", "rx 2729 dma-names = "tx", "rx";
2738 pinctrl-names = "defa 2730 pinctrl-names = "default";
2739 pinctrl-0 = <&blsp2_s 2731 pinctrl-0 = <&blsp2_spi6_default>;
2740 2732
2741 status = "disabled"; 2733 status = "disabled";
2742 #address-cells = <1>; 2734 #address-cells = <1>;
2743 #size-cells = <0>; 2735 #size-cells = <0>;
2744 }; 2736 };
2745 2737
2746 mmcc: clock-controller@c8c000 2738 mmcc: clock-controller@c8c0000 {
2747 compatible = "qcom,mm 2739 compatible = "qcom,mmcc-msm8998";
2748 #clock-cells = <1>; 2740 #clock-cells = <1>;
2749 #reset-cells = <1>; 2741 #reset-cells = <1>;
2750 #power-domain-cells = 2742 #power-domain-cells = <1>;
2751 reg = <0xc8c0000 0x40 2743 reg = <0xc8c0000 0x40000>;
2752 2744
2753 clock-names = "xo", 2745 clock-names = "xo",
2754 "gpll0" 2746 "gpll0",
2755 "dsi0ds 2747 "dsi0dsi",
2756 "dsi0by 2748 "dsi0byte",
2757 "dsi1ds 2749 "dsi1dsi",
2758 "dsi1by 2750 "dsi1byte",
2759 "hdmipl 2751 "hdmipll",
2760 "dplink 2752 "dplink",
2761 "dpvco" 2753 "dpvco",
2762 "gpll0_ 2754 "gpll0_div";
2763 clocks = <&rpmcc RPM_ 2755 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
2764 <&gcc GCC_MM 2756 <&gcc GCC_MMSS_GPLL0_CLK>,
2765 <&mdss_dsi0_ 2757 <&mdss_dsi0_phy 1>,
2766 <&mdss_dsi0_ 2758 <&mdss_dsi0_phy 0>,
2767 <&mdss_dsi1_ 2759 <&mdss_dsi1_phy 1>,
2768 <&mdss_dsi1_ 2760 <&mdss_dsi1_phy 0>,
2769 <0>, 2761 <0>,
2770 <0>, 2762 <0>,
2771 <0>, 2763 <0>,
2772 <&gcc GCC_MM 2764 <&gcc GCC_MMSS_GPLL0_DIV_CLK>;
2773 }; 2765 };
2774 2766
2775 mdss: display-subsystem@c9000 2767 mdss: display-subsystem@c900000 {
2776 compatible = "qcom,ms 2768 compatible = "qcom,msm8998-mdss";
2777 reg = <0x0c900000 0x1 2769 reg = <0x0c900000 0x1000>;
2778 reg-names = "mdss"; 2770 reg-names = "mdss";
2779 2771
2780 interrupts = <GIC_SPI 2772 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
2781 interrupt-controller; 2773 interrupt-controller;
2782 #interrupt-cells = <1 2774 #interrupt-cells = <1>;
2783 2775
2784 clocks = <&mmcc MDSS_ 2776 clocks = <&mmcc MDSS_AHB_CLK>,
2785 <&mmcc MDSS_ 2777 <&mmcc MDSS_AXI_CLK>,
2786 <&mmcc MDSS_ 2778 <&mmcc MDSS_MDP_CLK>;
2787 clock-names = "iface" 2779 clock-names = "iface",
2788 "bus", 2780 "bus",
2789 "core"; 2781 "core";
2790 2782
2791 power-domains = <&mmc 2783 power-domains = <&mmcc MDSS_GDSC>;
2792 iommus = <&mmss_smmu 2784 iommus = <&mmss_smmu 0>;
2793 2785
2794 #address-cells = <1>; 2786 #address-cells = <1>;
2795 #size-cells = <1>; 2787 #size-cells = <1>;
2796 ranges; 2788 ranges;
2797 2789
2798 status = "disabled"; 2790 status = "disabled";
2799 2791
2800 mdss_mdp: display-con 2792 mdss_mdp: display-controller@c901000 {
2801 compatible = 2793 compatible = "qcom,msm8998-dpu";
2802 reg = <0x0c90 2794 reg = <0x0c901000 0x8f000>,
2803 <0x0c9a 2795 <0x0c9a8e00 0xf0>,
2804 <0x0c9b 2796 <0x0c9b0000 0x2008>,
2805 <0x0c9b 2797 <0x0c9b8000 0x1040>;
2806 reg-names = " 2798 reg-names = "mdp",
2807 " 2799 "regdma",
2808 " 2800 "vbif",
2809 " 2801 "vbif_nrt";
2810 2802
2811 interrupt-par 2803 interrupt-parent = <&mdss>;
2812 interrupts = 2804 interrupts = <0>;
2813 2805
2814 clocks = <&mm 2806 clocks = <&mmcc MDSS_AHB_CLK>,
2815 <&mm 2807 <&mmcc MDSS_AXI_CLK>,
2816 <&mm 2808 <&mmcc MNOC_AHB_CLK>,
2817 <&mm 2809 <&mmcc MDSS_MDP_CLK>,
2818 <&mm 2810 <&mmcc MDSS_VSYNC_CLK>;
2819 clock-names = 2811 clock-names = "iface",
2820 2812 "bus",
2821 2813 "mnoc",
2822 2814 "core",
2823 2815 "vsync";
2824 2816
2825 assigned-cloc 2817 assigned-clocks = <&mmcc MDSS_VSYNC_CLK>;
2826 assigned-cloc 2818 assigned-clock-rates = <19200000>;
2827 2819
2828 operating-poi 2820 operating-points-v2 = <&mdp_opp_table>;
2829 power-domains 2821 power-domains = <&rpmpd MSM8998_VDDMX>;
2830 2822
2831 mdp_opp_table 2823 mdp_opp_table: opp-table {
2832 compa 2824 compatible = "operating-points-v2";
2833 2825
2834 opp-1 2826 opp-171430000 {
2835 2827 opp-hz = /bits/ 64 <171430000>;
2836 2828 required-opps = <&rpmpd_opp_low_svs>;
2837 }; 2829 };
2838 2830
2839 opp-2 2831 opp-275000000 {
2840 2832 opp-hz = /bits/ 64 <275000000>;
2841 2833 required-opps = <&rpmpd_opp_svs>;
2842 }; 2834 };
2843 2835
2844 opp-3 2836 opp-330000000 {
2845 2837 opp-hz = /bits/ 64 <330000000>;
2846 2838 required-opps = <&rpmpd_opp_nom>;
2847 }; 2839 };
2848 2840
2849 opp-4 2841 opp-412500000 {
2850 2842 opp-hz = /bits/ 64 <412500000>;
2851 2843 required-opps = <&rpmpd_opp_turbo>;
2852 }; 2844 };
2853 }; 2845 };
2854 2846
2855 ports { 2847 ports {
2856 #addr 2848 #address-cells = <1>;
2857 #size 2849 #size-cells = <0>;
2858 2850
2859 port@ 2851 port@0 {
2860 2852 reg = <0>;
2861 2853
2862 2854 dpu_intf1_out: endpoint {
2863 2855 remote-endpoint = <&mdss_dsi0_in>;
2864 2856 };
2865 }; 2857 };
2866 2858
2867 port@ 2859 port@1 {
2868 2860 reg = <1>;
2869 2861
2870 2862 dpu_intf2_out: endpoint {
2871 2863 remote-endpoint = <&mdss_dsi1_in>;
2872 2864 };
2873 }; 2865 };
2874 }; 2866 };
2875 }; 2867 };
2876 2868
2877 mdss_dsi0: dsi@c99400 2869 mdss_dsi0: dsi@c994000 {
2878 compatible = 2870 compatible = "qcom,msm8998-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2879 reg = <0x0c99 2871 reg = <0x0c994000 0x400>;
2880 reg-names = " 2872 reg-names = "dsi_ctrl";
2881 2873
2882 interrupt-par 2874 interrupt-parent = <&mdss>;
2883 interrupts = 2875 interrupts = <4>;
2884 2876
2885 clocks = <&mm 2877 clocks = <&mmcc MDSS_BYTE0_CLK>,
2886 <&mm 2878 <&mmcc MDSS_BYTE0_INTF_CLK>,
2887 <&mm 2879 <&mmcc MDSS_PCLK0_CLK>,
2888 <&mm 2880 <&mmcc MDSS_ESC0_CLK>,
2889 <&mm 2881 <&mmcc MDSS_AHB_CLK>,
2890 <&mm 2882 <&mmcc MDSS_AXI_CLK>;
2891 clock-names = 2883 clock-names = "byte",
2892 2884 "byte_intf",
2893 2885 "pixel",
2894 2886 "core",
2895 2887 "iface",
2896 2888 "bus";
2897 assigned-cloc 2889 assigned-clocks = <&mmcc BYTE0_CLK_SRC>,
2898 2890 <&mmcc PCLK0_CLK_SRC>;
2899 assigned-cloc 2891 assigned-clock-parents = <&mdss_dsi0_phy 0>,
2900 2892 <&mdss_dsi0_phy 1>;
2901 2893
2902 operating-poi 2894 operating-points-v2 = <&dsi_opp_table>;
2903 power-domains 2895 power-domains = <&rpmpd MSM8998_VDDCX>;
2904 2896
2905 phys = <&mdss 2897 phys = <&mdss_dsi0_phy>;
2906 phy-names = " 2898 phy-names = "dsi";
2907 2899
2908 #address-cell 2900 #address-cells = <1>;
2909 #size-cells = 2901 #size-cells = <0>;
2910 2902
2911 status = "dis 2903 status = "disabled";
2912 2904
2913 ports { 2905 ports {
2914 #addr 2906 #address-cells = <1>;
2915 #size 2907 #size-cells = <0>;
2916 2908
2917 port@ 2909 port@0 {
2918 2910 reg = <0>;
2919 2911
2920 2912 mdss_dsi0_in: endpoint {
2921 2913 remote-endpoint = <&dpu_intf1_out>;
2922 2914 };
2923 }; 2915 };
2924 2916
2925 port@ 2917 port@1 {
2926 2918 reg = <1>;
2927 2919
2928 2920 mdss_dsi0_out: endpoint {
2929 2921 };
2930 }; 2922 };
2931 }; 2923 };
2932 }; 2924 };
2933 2925
2934 mdss_dsi0_phy: phy@c9 2926 mdss_dsi0_phy: phy@c994400 {
2935 compatible = 2927 compatible = "qcom,dsi-phy-10nm-8998";
2936 reg = <0x0c99 2928 reg = <0x0c994400 0x200>,
2937 <0x0c99 2929 <0x0c994600 0x280>,
2938 <0x0c99 2930 <0x0c994a00 0x1e0>;
2939 reg-names = " 2931 reg-names = "dsi_phy",
2940 " 2932 "dsi_phy_lane",
2941 " 2933 "dsi_pll";
2942 2934
2943 clocks = <&mm 2935 clocks = <&mmcc MDSS_AHB_CLK>,
2944 <&rp 2936 <&rpmcc RPM_SMD_XO_CLK_SRC>;
2945 clock-names = 2937 clock-names = "iface", "ref";
2946 2938
2947 #clock-cells 2939 #clock-cells = <1>;
2948 #phy-cells = 2940 #phy-cells = <0>;
2949 2941
2950 status = "dis 2942 status = "disabled";
2951 }; 2943 };
2952 2944
2953 mdss_dsi1: dsi@c99600 2945 mdss_dsi1: dsi@c996000 {
2954 compatible = 2946 compatible = "qcom,msm8998-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2955 reg = <0x0c99 2947 reg = <0x0c996000 0x400>;
2956 reg-names = " 2948 reg-names = "dsi_ctrl";
2957 2949
2958 interrupt-par 2950 interrupt-parent = <&mdss>;
2959 interrupts = 2951 interrupts = <5>;
2960 2952
2961 clocks = <&mm 2953 clocks = <&mmcc MDSS_BYTE1_CLK>,
2962 <&mm 2954 <&mmcc MDSS_BYTE1_INTF_CLK>,
2963 <&mm 2955 <&mmcc MDSS_PCLK1_CLK>,
2964 <&mm 2956 <&mmcc MDSS_ESC1_CLK>,
2965 <&mm 2957 <&mmcc MDSS_AHB_CLK>,
2966 <&mm 2958 <&mmcc MDSS_AXI_CLK>;
2967 clock-names = 2959 clock-names = "byte",
2968 2960 "byte_intf",
2969 2961 "pixel",
2970 2962 "core",
2971 2963 "iface",
2972 2964 "bus";
2973 assigned-cloc 2965 assigned-clocks = <&mmcc BYTE1_CLK_SRC>,
2974 2966 <&mmcc PCLK1_CLK_SRC>;
2975 assigned-cloc 2967 assigned-clock-parents = <&mdss_dsi1_phy 0>,
2976 2968 <&mdss_dsi1_phy 1>;
2977 2969
2978 operating-poi 2970 operating-points-v2 = <&dsi_opp_table>;
2979 power-domains 2971 power-domains = <&rpmpd MSM8998_VDDCX>;
2980 2972
2981 phys = <&mdss 2973 phys = <&mdss_dsi1_phy>;
2982 phy-names = " 2974 phy-names = "dsi";
2983 2975
2984 #address-cell 2976 #address-cells = <1>;
2985 #size-cells = 2977 #size-cells = <0>;
2986 2978
2987 status = "dis 2979 status = "disabled";
2988 2980
2989 ports { 2981 ports {
2990 #addr 2982 #address-cells = <1>;
2991 #size 2983 #size-cells = <0>;
2992 2984
2993 port@ 2985 port@0 {
2994 2986 reg = <0>;
2995 2987
2996 2988 mdss_dsi1_in: endpoint {
2997 2989 remote-endpoint = <&dpu_intf2_out>;
2998 2990 };
2999 }; 2991 };
3000 2992
3001 port@ 2993 port@1 {
3002 2994 reg = <1>;
3003 2995
3004 2996 mdss_dsi1_out: endpoint {
3005 2997 };
3006 }; 2998 };
3007 }; 2999 };
3008 }; 3000 };
3009 3001
3010 mdss_dsi1_phy: phy@c9 3002 mdss_dsi1_phy: phy@c996400 {
3011 compatible = 3003 compatible = "qcom,dsi-phy-10nm-8998";
3012 reg = <0x0c99 3004 reg = <0x0c996400 0x200>,
3013 <0x0c99 3005 <0x0c996600 0x280>,
3014 <0x0c99 3006 <0x0c996a00 0x10e>;
3015 reg-names = " 3007 reg-names = "dsi_phy",
3016 " 3008 "dsi_phy_lane",
3017 " 3009 "dsi_pll";
3018 3010
3019 clocks = <&mm 3011 clocks = <&mmcc MDSS_AHB_CLK>,
3020 <&rp 3012 <&rpmcc RPM_SMD_XO_CLK_SRC>;
3021 clock-names = 3013 clock-names = "iface",
3022 3014 "ref";
3023 3015
3024 #clock-cells 3016 #clock-cells = <1>;
3025 #phy-cells = 3017 #phy-cells = <0>;
3026 3018
3027 status = "dis 3019 status = "disabled";
3028 }; 3020 };
3029 }; 3021 };
3030 3022
3031 venus: video-codec@cc00000 { <<
3032 compatible = "qcom,ms <<
3033 reg = <0x0cc00000 0xf <<
3034 interrupts = <GIC_SPI <<
3035 power-domains = <&mmc <<
3036 clocks = <&mmcc VIDEO <<
3037 <&mmcc VIDEO <<
3038 <&mmcc VIDEO <<
3039 <&mmcc VIDEO <<
3040 clock-names = "core", <<
3041 iommus = <&mmss_smmu <<
3042 <&mmss_smmu <<
3043 <&mmss_smmu <<
3044 <&mmss_smmu <<
3045 <&mmss_smmu <<
3046 <&mmss_smmu <<
3047 <&mmss_smmu <<
3048 <&mmss_smmu <<
3049 <&mmss_smmu <<
3050 <&mmss_smmu <<
3051 <&mmss_smmu <<
3052 <&mmss_smmu <<
3053 <&mmss_smmu <<
3054 <&mmss_smmu <<
3055 <&mmss_smmu <<
3056 <&mmss_smmu <<
3057 <&mmss_smmu <<
3058 <&mmss_smmu <<
3059 <&mmss_smmu <<
3060 <&mmss_smmu <<
3061 memory-region = <&ven <<
3062 status = "disabled"; <<
3063 <<
3064 video-decoder { <<
3065 compatible = <<
3066 clocks = <&mm <<
3067 clock-names = <<
3068 power-domains <<
3069 }; <<
3070 <<
3071 video-encoder { <<
3072 compatible = <<
3073 clocks = <&mm <<
3074 clock-names = <<
3075 power-domains <<
3076 }; <<
3077 }; <<
3078 <<
3079 mmss_smmu: iommu@cd00000 { 3023 mmss_smmu: iommu@cd00000 {
3080 compatible = "qcom,ms 3024 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
3081 reg = <0x0cd00000 0x4 3025 reg = <0x0cd00000 0x40000>;
3082 #iommu-cells = <1>; 3026 #iommu-cells = <1>;
3083 3027
3084 clocks = <&mmcc MNOC_ 3028 clocks = <&mmcc MNOC_AHB_CLK>,
3085 <&mmcc BIMC_ 3029 <&mmcc BIMC_SMMU_AHB_CLK>,
3086 <&mmcc BIMC_ 3030 <&mmcc BIMC_SMMU_AXI_CLK>;
3087 clock-names = "iface- 3031 clock-names = "iface-mm",
3088 "iface- 3032 "iface-smmu",
3089 "bus-sm 3033 "bus-smmu";
3090 3034
3091 #global-interrupts = 3035 #global-interrupts = <0>;
3092 interrupts = 3036 interrupts =
3093 <GIC_SPI 263 3037 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
3094 <GIC_SPI 266 3038 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
3095 <GIC_SPI 267 3039 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
3096 <GIC_SPI 268 3040 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
3097 <GIC_SPI 244 3041 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
3098 <GIC_SPI 245 3042 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
3099 <GIC_SPI 247 3043 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
3100 <GIC_SPI 248 3044 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
3101 <GIC_SPI 249 3045 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
3102 <GIC_SPI 250 3046 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
3103 <GIC_SPI 251 3047 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
3104 <GIC_SPI 252 3048 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
3105 <GIC_SPI 253 3049 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
3106 <GIC_SPI 254 3050 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
3107 <GIC_SPI 255 3051 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
3108 <GIC_SPI 256 3052 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
3109 <GIC_SPI 260 3053 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
3110 <GIC_SPI 261 3054 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
3111 <GIC_SPI 262 3055 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
3112 <GIC_SPI 272 3056 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
3113 3057
3114 power-domains = <&mmc 3058 power-domains = <&mmcc BIMC_SMMU_GDSC>;
3115 }; 3059 };
3116 3060
3117 remoteproc_adsp: remoteproc@1 3061 remoteproc_adsp: remoteproc@17300000 {
3118 compatible = "qcom,ms 3062 compatible = "qcom,msm8998-adsp-pas";
3119 reg = <0x17300000 0x4 3063 reg = <0x17300000 0x4040>;
3120 3064
3121 interrupts-extended = 3065 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
3122 3066 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3123 3067 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3124 3068 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3125 3069 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
3126 interrupt-names = "wd 3070 interrupt-names = "wdog", "fatal", "ready",
3127 "ha 3071 "handover", "stop-ack";
3128 3072
3129 clocks = <&rpmcc RPM_ 3073 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
3130 clock-names = "xo"; 3074 clock-names = "xo";
3131 3075
3132 memory-region = <&ads 3076 memory-region = <&adsp_mem>;
3133 3077
3134 qcom,smem-states = <& 3078 qcom,smem-states = <&adsp_smp2p_out 0>;
3135 qcom,smem-state-names 3079 qcom,smem-state-names = "stop";
3136 3080
3137 power-domains = <&rpm 3081 power-domains = <&rpmpd MSM8998_VDDCX>;
3138 power-domain-names = 3082 power-domain-names = "cx";
3139 3083
3140 status = "disabled"; 3084 status = "disabled";
3141 3085
3142 glink-edge { 3086 glink-edge {
3143 interrupts = 3087 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
3144 label = "lpas 3088 label = "lpass";
3145 qcom,remote-p 3089 qcom,remote-pid = <2>;
3146 mboxes = <&ap 3090 mboxes = <&apcs_glb 9>;
3147 }; 3091 };
3148 }; 3092 };
3149 3093
3150 apcs_glb: mailbox@17911000 { 3094 apcs_glb: mailbox@17911000 {
3151 compatible = "qcom,ms 3095 compatible = "qcom,msm8998-apcs-hmss-global",
3152 "qcom,ms 3096 "qcom,msm8994-apcs-kpss-global";
3153 reg = <0x17911000 0x1 3097 reg = <0x17911000 0x1000>;
3154 3098
3155 #mbox-cells = <1>; 3099 #mbox-cells = <1>;
3156 }; 3100 };
3157 3101
3158 timer@17920000 { 3102 timer@17920000 {
3159 #address-cells = <1>; 3103 #address-cells = <1>;
3160 #size-cells = <1>; 3104 #size-cells = <1>;
3161 ranges; 3105 ranges;
3162 compatible = "arm,arm 3106 compatible = "arm,armv7-timer-mem";
3163 reg = <0x17920000 0x1 3107 reg = <0x17920000 0x1000>;
3164 3108
3165 frame@17921000 { 3109 frame@17921000 {
3166 frame-number 3110 frame-number = <0>;
3167 interrupts = 3111 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
3168 3112 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
3169 reg = <0x1792 3113 reg = <0x17921000 0x1000>,
3170 <0x1792 3114 <0x17922000 0x1000>;
3171 }; 3115 };
3172 3116
3173 frame@17923000 { 3117 frame@17923000 {
3174 frame-number 3118 frame-number = <1>;
3175 interrupts = 3119 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
3176 reg = <0x1792 3120 reg = <0x17923000 0x1000>;
3177 status = "dis 3121 status = "disabled";
3178 }; 3122 };
3179 3123
3180 frame@17924000 { 3124 frame@17924000 {
3181 frame-number 3125 frame-number = <2>;
3182 interrupts = 3126 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
3183 reg = <0x1792 3127 reg = <0x17924000 0x1000>;
3184 status = "dis 3128 status = "disabled";
3185 }; 3129 };
3186 3130
3187 frame@17925000 { 3131 frame@17925000 {
3188 frame-number 3132 frame-number = <3>;
3189 interrupts = 3133 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3190 reg = <0x1792 3134 reg = <0x17925000 0x1000>;
3191 status = "dis 3135 status = "disabled";
3192 }; 3136 };
3193 3137
3194 frame@17926000 { 3138 frame@17926000 {
3195 frame-number 3139 frame-number = <4>;
3196 interrupts = 3140 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3197 reg = <0x1792 3141 reg = <0x17926000 0x1000>;
3198 status = "dis 3142 status = "disabled";
3199 }; 3143 };
3200 3144
3201 frame@17927000 { 3145 frame@17927000 {
3202 frame-number 3146 frame-number = <5>;
3203 interrupts = 3147 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3204 reg = <0x1792 3148 reg = <0x17927000 0x1000>;
3205 status = "dis 3149 status = "disabled";
3206 }; 3150 };
3207 3151
3208 frame@17928000 { 3152 frame@17928000 {
3209 frame-number 3153 frame-number = <6>;
3210 interrupts = 3154 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
3211 reg = <0x1792 3155 reg = <0x17928000 0x1000>;
3212 status = "dis 3156 status = "disabled";
3213 }; 3157 };
3214 }; 3158 };
3215 3159
3216 intc: interrupt-controller@17 3160 intc: interrupt-controller@17a00000 {
3217 compatible = "arm,gic 3161 compatible = "arm,gic-v3";
3218 reg = <0x17a00000 0x1 3162 reg = <0x17a00000 0x10000>, /* GICD */
3219 <0x17b00000 0x1 3163 <0x17b00000 0x100000>; /* GICR * 8 */
3220 #interrupt-cells = <3 3164 #interrupt-cells = <3>;
3221 #address-cells = <1>; 3165 #address-cells = <1>;
3222 #size-cells = <1>; 3166 #size-cells = <1>;
3223 ranges; 3167 ranges;
3224 interrupt-controller; 3168 interrupt-controller;
3225 #redistributor-region 3169 #redistributor-regions = <1>;
3226 redistributor-stride 3170 redistributor-stride = <0x0 0x20000>;
3227 interrupts = <GIC_PPI 3171 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3228 }; 3172 };
3229 3173
3230 wifi: wifi@18800000 { 3174 wifi: wifi@18800000 {
3231 compatible = "qcom,wc 3175 compatible = "qcom,wcn3990-wifi";
3232 status = "disabled"; 3176 status = "disabled";
3233 reg = <0x18800000 0x8 3177 reg = <0x18800000 0x800000>;
3234 reg-names = "membase" 3178 reg-names = "membase";
3235 memory-region = <&wla 3179 memory-region = <&wlan_msa_mem>;
3236 clocks = <&rpmcc RPM_ 3180 clocks = <&rpmcc RPM_SMD_RF_CLK2_PIN>;
3237 clock-names = "cxo_re 3181 clock-names = "cxo_ref_clk_pin";
3238 interrupts = 3182 interrupts =
3239 <GIC_SPI 413 3183 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
3240 <GIC_SPI 414 3184 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
3241 <GIC_SPI 415 3185 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
3242 <GIC_SPI 416 3186 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
3243 <GIC_SPI 417 3187 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
3244 <GIC_SPI 418 3188 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
3245 <GIC_SPI 420 3189 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
3246 <GIC_SPI 421 3190 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
3247 <GIC_SPI 422 3191 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
3248 <GIC_SPI 423 3192 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
3249 <GIC_SPI 424 3193 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
3250 <GIC_SPI 425 3194 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
3251 iommus = <&anoc2_smmu 3195 iommus = <&anoc2_smmu 0x1900>,
3252 <&anoc2_smmu 3196 <&anoc2_smmu 0x1901>;
3253 qcom,snoc-host-cap-8b 3197 qcom,snoc-host-cap-8bit-quirk;
3254 qcom,no-msa-ready-ind <<
3255 }; 3198 };
3256 }; 3199 };
3257 }; 3200 };
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