1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2016, The Linux Foundation. A 2 /* Copyright (c) 2016, The Linux Foundation. All rights reserved. */
3 3
4 #include <dt-bindings/interrupt-controller/arm 4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-msm8998.h 5 #include <dt-bindings/clock/qcom,gcc-msm8998.h>
6 #include <dt-bindings/clock/qcom,gpucc-msm8998 6 #include <dt-bindings/clock/qcom,gpucc-msm8998.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8998. 7 #include <dt-bindings/clock/qcom,mmcc-msm8998.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h> 8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/firmware/qcom,scm.h> 9 #include <dt-bindings/firmware/qcom,scm.h>
10 #include <dt-bindings/power/qcom-rpmpd.h> 10 #include <dt-bindings/power/qcom-rpmpd.h>
11 #include <dt-bindings/gpio/gpio.h> 11 #include <dt-bindings/gpio/gpio.h>
12 12
13 / { 13 / {
14 interrupt-parent = <&intc>; 14 interrupt-parent = <&intc>;
15 15
16 qcom,msm-id = <292 0x0>; 16 qcom,msm-id = <292 0x0>;
17 17
18 #address-cells = <2>; 18 #address-cells = <2>;
19 #size-cells = <2>; 19 #size-cells = <2>;
20 20
21 chosen { }; 21 chosen { };
22 22
23 memory@80000000 { 23 memory@80000000 {
24 device_type = "memory"; 24 device_type = "memory";
25 /* We expect the bootloader to 25 /* We expect the bootloader to fill in the reg */
26 reg = <0x0 0x80000000 0x0 0x0> 26 reg = <0x0 0x80000000 0x0 0x0>;
27 }; 27 };
28 28
29 reserved-memory { 29 reserved-memory {
30 #address-cells = <2>; 30 #address-cells = <2>;
31 #size-cells = <2>; 31 #size-cells = <2>;
32 ranges; 32 ranges;
33 33
34 hyp_mem: memory@85800000 { 34 hyp_mem: memory@85800000 {
35 reg = <0x0 0x85800000 35 reg = <0x0 0x85800000 0x0 0x600000>;
36 no-map; 36 no-map;
37 }; 37 };
38 38
39 xbl_mem: memory@85e00000 { 39 xbl_mem: memory@85e00000 {
40 reg = <0x0 0x85e00000 40 reg = <0x0 0x85e00000 0x0 0x100000>;
41 no-map; 41 no-map;
42 }; 42 };
43 43
44 smem_mem: smem-mem@86000000 { 44 smem_mem: smem-mem@86000000 {
45 reg = <0x0 0x86000000 45 reg = <0x0 0x86000000 0x0 0x200000>;
46 no-map; 46 no-map;
47 }; 47 };
48 48
49 tz_mem: memory@86200000 { 49 tz_mem: memory@86200000 {
50 reg = <0x0 0x86200000 50 reg = <0x0 0x86200000 0x0 0x2d00000>;
51 no-map; 51 no-map;
52 }; 52 };
53 53
54 rmtfs_mem: memory@88f00000 { 54 rmtfs_mem: memory@88f00000 {
55 compatible = "qcom,rmt 55 compatible = "qcom,rmtfs-mem";
56 reg = <0x0 0x88f00000 56 reg = <0x0 0x88f00000 0x0 0x200000>;
57 no-map; 57 no-map;
58 58
59 qcom,client-id = <1>; 59 qcom,client-id = <1>;
60 qcom,vmid = <QCOM_SCM_ 60 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>;
61 }; 61 };
62 62
63 spss_mem: memory@8ab00000 { 63 spss_mem: memory@8ab00000 {
64 reg = <0x0 0x8ab00000 64 reg = <0x0 0x8ab00000 0x0 0x700000>;
65 no-map; 65 no-map;
66 }; 66 };
67 67
68 adsp_mem: memory@8b200000 { 68 adsp_mem: memory@8b200000 {
69 reg = <0x0 0x8b200000 69 reg = <0x0 0x8b200000 0x0 0x1a00000>;
70 no-map; 70 no-map;
71 }; 71 };
72 72
73 mpss_mem: memory@8cc00000 { 73 mpss_mem: memory@8cc00000 {
74 reg = <0x0 0x8cc00000 74 reg = <0x0 0x8cc00000 0x0 0x7000000>;
75 no-map; 75 no-map;
76 }; 76 };
77 77
78 venus_mem: memory@93c00000 { 78 venus_mem: memory@93c00000 {
79 reg = <0x0 0x93c00000 79 reg = <0x0 0x93c00000 0x0 0x500000>;
80 no-map; 80 no-map;
81 }; 81 };
82 82
83 mba_mem: memory@94100000 { 83 mba_mem: memory@94100000 {
84 reg = <0x0 0x94100000 84 reg = <0x0 0x94100000 0x0 0x200000>;
85 no-map; 85 no-map;
86 }; 86 };
87 87
88 slpi_mem: memory@94300000 { 88 slpi_mem: memory@94300000 {
89 reg = <0x0 0x94300000 89 reg = <0x0 0x94300000 0x0 0xf00000>;
90 no-map; 90 no-map;
91 }; 91 };
92 92
93 ipa_fw_mem: memory@95200000 { 93 ipa_fw_mem: memory@95200000 {
94 reg = <0x0 0x95200000 94 reg = <0x0 0x95200000 0x0 0x10000>;
95 no-map; 95 no-map;
96 }; 96 };
97 97
98 ipa_gsi_mem: memory@95210000 { 98 ipa_gsi_mem: memory@95210000 {
99 reg = <0x0 0x95210000 99 reg = <0x0 0x95210000 0x0 0x5000>;
100 no-map; 100 no-map;
101 }; 101 };
102 102
103 gpu_mem: memory@95600000 { 103 gpu_mem: memory@95600000 {
104 reg = <0x0 0x95600000 104 reg = <0x0 0x95600000 0x0 0x100000>;
105 no-map; 105 no-map;
106 }; 106 };
107 107
108 wlan_msa_mem: memory@95700000 108 wlan_msa_mem: memory@95700000 {
109 reg = <0x0 0x95700000 109 reg = <0x0 0x95700000 0x0 0x100000>;
110 no-map; 110 no-map;
111 }; 111 };
112 112
113 mdata_mem: mpss-metadata { 113 mdata_mem: mpss-metadata {
114 alloc-ranges = <0x0 0x 114 alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>;
115 size = <0x0 0x4000>; 115 size = <0x0 0x4000>;
116 no-map; 116 no-map;
117 }; 117 };
118 }; 118 };
119 119
120 clocks { 120 clocks {
121 xo: xo-board { 121 xo: xo-board {
122 compatible = "fixed-cl 122 compatible = "fixed-clock";
123 #clock-cells = <0>; 123 #clock-cells = <0>;
124 clock-frequency = <192 124 clock-frequency = <19200000>;
125 clock-output-names = " 125 clock-output-names = "xo_board";
126 }; 126 };
127 127
128 sleep_clk: sleep-clk { 128 sleep_clk: sleep-clk {
129 compatible = "fixed-cl 129 compatible = "fixed-clock";
130 #clock-cells = <0>; 130 #clock-cells = <0>;
131 clock-frequency = <327 131 clock-frequency = <32764>;
132 }; 132 };
133 }; 133 };
134 134
135 cpus { 135 cpus {
136 #address-cells = <2>; 136 #address-cells = <2>;
137 #size-cells = <0>; 137 #size-cells = <0>;
138 138
139 CPU0: cpu@0 { 139 CPU0: cpu@0 {
140 device_type = "cpu"; 140 device_type = "cpu";
141 compatible = "qcom,kry 141 compatible = "qcom,kryo280";
142 reg = <0x0 0x0>; 142 reg = <0x0 0x0>;
143 enable-method = "psci" 143 enable-method = "psci";
144 capacity-dmips-mhz = < 144 capacity-dmips-mhz = <1024>;
145 cpu-idle-states = <&LI 145 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
146 next-level-cache = <&L 146 next-level-cache = <&L2_0>;
147 L2_0: l2-cache { 147 L2_0: l2-cache {
148 compatible = " 148 compatible = "cache";
149 cache-level = 149 cache-level = <2>;
150 cache-unified; 150 cache-unified;
151 }; 151 };
152 }; 152 };
153 153
154 CPU1: cpu@1 { 154 CPU1: cpu@1 {
155 device_type = "cpu"; 155 device_type = "cpu";
156 compatible = "qcom,kry 156 compatible = "qcom,kryo280";
157 reg = <0x0 0x1>; 157 reg = <0x0 0x1>;
158 enable-method = "psci" 158 enable-method = "psci";
159 capacity-dmips-mhz = < 159 capacity-dmips-mhz = <1024>;
160 cpu-idle-states = <&LI 160 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
161 next-level-cache = <&L 161 next-level-cache = <&L2_0>;
162 }; 162 };
163 163
164 CPU2: cpu@2 { 164 CPU2: cpu@2 {
165 device_type = "cpu"; 165 device_type = "cpu";
166 compatible = "qcom,kry 166 compatible = "qcom,kryo280";
167 reg = <0x0 0x2>; 167 reg = <0x0 0x2>;
168 enable-method = "psci" 168 enable-method = "psci";
169 capacity-dmips-mhz = < 169 capacity-dmips-mhz = <1024>;
170 cpu-idle-states = <&LI 170 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
171 next-level-cache = <&L 171 next-level-cache = <&L2_0>;
172 }; 172 };
173 173
174 CPU3: cpu@3 { 174 CPU3: cpu@3 {
175 device_type = "cpu"; 175 device_type = "cpu";
176 compatible = "qcom,kry 176 compatible = "qcom,kryo280";
177 reg = <0x0 0x3>; 177 reg = <0x0 0x3>;
178 enable-method = "psci" 178 enable-method = "psci";
179 capacity-dmips-mhz = < 179 capacity-dmips-mhz = <1024>;
180 cpu-idle-states = <&LI 180 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
181 next-level-cache = <&L 181 next-level-cache = <&L2_0>;
182 }; 182 };
183 183
184 CPU4: cpu@100 { 184 CPU4: cpu@100 {
185 device_type = "cpu"; 185 device_type = "cpu";
186 compatible = "qcom,kry 186 compatible = "qcom,kryo280";
187 reg = <0x0 0x100>; 187 reg = <0x0 0x100>;
188 enable-method = "psci" 188 enable-method = "psci";
189 capacity-dmips-mhz = < 189 capacity-dmips-mhz = <1536>;
190 cpu-idle-states = <&BI 190 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
191 next-level-cache = <&L 191 next-level-cache = <&L2_1>;
192 L2_1: l2-cache { 192 L2_1: l2-cache {
193 compatible = " 193 compatible = "cache";
194 cache-level = 194 cache-level = <2>;
195 cache-unified; 195 cache-unified;
196 }; 196 };
197 }; 197 };
198 198
199 CPU5: cpu@101 { 199 CPU5: cpu@101 {
200 device_type = "cpu"; 200 device_type = "cpu";
201 compatible = "qcom,kry 201 compatible = "qcom,kryo280";
202 reg = <0x0 0x101>; 202 reg = <0x0 0x101>;
203 enable-method = "psci" 203 enable-method = "psci";
204 capacity-dmips-mhz = < 204 capacity-dmips-mhz = <1536>;
205 cpu-idle-states = <&BI 205 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
206 next-level-cache = <&L 206 next-level-cache = <&L2_1>;
207 }; 207 };
208 208
209 CPU6: cpu@102 { 209 CPU6: cpu@102 {
210 device_type = "cpu"; 210 device_type = "cpu";
211 compatible = "qcom,kry 211 compatible = "qcom,kryo280";
212 reg = <0x0 0x102>; 212 reg = <0x0 0x102>;
213 enable-method = "psci" 213 enable-method = "psci";
214 capacity-dmips-mhz = < 214 capacity-dmips-mhz = <1536>;
215 cpu-idle-states = <&BI 215 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
216 next-level-cache = <&L 216 next-level-cache = <&L2_1>;
217 }; 217 };
218 218
219 CPU7: cpu@103 { 219 CPU7: cpu@103 {
220 device_type = "cpu"; 220 device_type = "cpu";
221 compatible = "qcom,kry 221 compatible = "qcom,kryo280";
222 reg = <0x0 0x103>; 222 reg = <0x0 0x103>;
223 enable-method = "psci" 223 enable-method = "psci";
224 capacity-dmips-mhz = < 224 capacity-dmips-mhz = <1536>;
225 cpu-idle-states = <&BI 225 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
226 next-level-cache = <&L 226 next-level-cache = <&L2_1>;
227 }; 227 };
228 228
229 cpu-map { 229 cpu-map {
230 cluster0 { 230 cluster0 {
231 core0 { 231 core0 {
232 cpu = 232 cpu = <&CPU0>;
233 }; 233 };
234 234
235 core1 { 235 core1 {
236 cpu = 236 cpu = <&CPU1>;
237 }; 237 };
238 238
239 core2 { 239 core2 {
240 cpu = 240 cpu = <&CPU2>;
241 }; 241 };
242 242
243 core3 { 243 core3 {
244 cpu = 244 cpu = <&CPU3>;
245 }; 245 };
246 }; 246 };
247 247
248 cluster1 { 248 cluster1 {
249 core0 { 249 core0 {
250 cpu = 250 cpu = <&CPU4>;
251 }; 251 };
252 252
253 core1 { 253 core1 {
254 cpu = 254 cpu = <&CPU5>;
255 }; 255 };
256 256
257 core2 { 257 core2 {
258 cpu = 258 cpu = <&CPU6>;
259 }; 259 };
260 260
261 core3 { 261 core3 {
262 cpu = 262 cpu = <&CPU7>;
263 }; 263 };
264 }; 264 };
265 }; 265 };
266 266
267 idle-states { 267 idle-states {
268 entry-method = "psci"; 268 entry-method = "psci";
269 269
270 LITTLE_CPU_SLEEP_0: cp 270 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
271 compatible = " 271 compatible = "arm,idle-state";
272 idle-state-nam 272 idle-state-name = "little-retention";
273 /* CPU Retenti 273 /* CPU Retention (C2D), L2 Active */
274 arm,psci-suspe 274 arm,psci-suspend-param = <0x00000002>;
275 entry-latency- 275 entry-latency-us = <81>;
276 exit-latency-u 276 exit-latency-us = <86>;
277 min-residency- 277 min-residency-us = <504>;
278 }; 278 };
279 279
280 LITTLE_CPU_SLEEP_1: cp 280 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
281 compatible = " 281 compatible = "arm,idle-state";
282 idle-state-nam 282 idle-state-name = "little-power-collapse";
283 /* CPU + L2 Po 283 /* CPU + L2 Power Collapse (C3, D4) */
284 arm,psci-suspe 284 arm,psci-suspend-param = <0x40000003>;
285 entry-latency- 285 entry-latency-us = <814>;
286 exit-latency-u 286 exit-latency-us = <4562>;
287 min-residency- 287 min-residency-us = <9183>;
288 local-timer-st 288 local-timer-stop;
289 }; 289 };
290 290
291 BIG_CPU_SLEEP_0: cpu-s 291 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
292 compatible = " 292 compatible = "arm,idle-state";
293 idle-state-nam 293 idle-state-name = "big-retention";
294 /* CPU Retenti 294 /* CPU Retention (C2D), L2 Active */
295 arm,psci-suspe 295 arm,psci-suspend-param = <0x00000002>;
296 entry-latency- 296 entry-latency-us = <79>;
297 exit-latency-u 297 exit-latency-us = <82>;
298 min-residency- 298 min-residency-us = <1302>;
299 }; 299 };
300 300
301 BIG_CPU_SLEEP_1: cpu-s 301 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
302 compatible = " 302 compatible = "arm,idle-state";
303 idle-state-nam 303 idle-state-name = "big-power-collapse";
304 /* CPU + L2 Po 304 /* CPU + L2 Power Collapse (C3, D4) */
305 arm,psci-suspe 305 arm,psci-suspend-param = <0x40000003>;
306 entry-latency- 306 entry-latency-us = <724>;
307 exit-latency-u 307 exit-latency-us = <2027>;
308 min-residency- 308 min-residency-us = <9419>;
309 local-timer-st 309 local-timer-stop;
310 }; 310 };
311 }; 311 };
312 }; 312 };
313 313
314 firmware { 314 firmware {
315 scm { 315 scm {
316 compatible = "qcom,scm 316 compatible = "qcom,scm-msm8998", "qcom,scm";
317 }; 317 };
318 }; 318 };
319 319
320 dsi_opp_table: opp-table-dsi { 320 dsi_opp_table: opp-table-dsi {
321 compatible = "operating-points 321 compatible = "operating-points-v2";
322 322
323 opp-131250000 { 323 opp-131250000 {
324 opp-hz = /bits/ 64 <13 324 opp-hz = /bits/ 64 <131250000>;
325 required-opps = <&rpmp 325 required-opps = <&rpmpd_opp_low_svs>;
326 }; 326 };
327 327
328 opp-210000000 { 328 opp-210000000 {
329 opp-hz = /bits/ 64 <21 329 opp-hz = /bits/ 64 <210000000>;
330 required-opps = <&rpmp 330 required-opps = <&rpmpd_opp_svs>;
331 }; 331 };
332 332
333 opp-312500000 { 333 opp-312500000 {
334 opp-hz = /bits/ 64 <31 334 opp-hz = /bits/ 64 <312500000>;
335 required-opps = <&rpmp 335 required-opps = <&rpmpd_opp_nom>;
336 }; 336 };
337 }; 337 };
338 338
339 psci { 339 psci {
340 compatible = "arm,psci-1.0"; 340 compatible = "arm,psci-1.0";
341 method = "smc"; 341 method = "smc";
342 }; 342 };
343 343
344 rpm: remoteproc { 344 rpm: remoteproc {
345 compatible = "qcom,msm8998-rpm 345 compatible = "qcom,msm8998-rpm-proc", "qcom,rpm-proc";
346 346
347 glink-edge { 347 glink-edge {
348 compatible = "qcom,gli 348 compatible = "qcom,glink-rpm";
349 349
350 interrupts = <GIC_SPI 350 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
351 qcom,rpm-msg-ram = <&r 351 qcom,rpm-msg-ram = <&rpm_msg_ram>;
352 mboxes = <&apcs_glb 0> 352 mboxes = <&apcs_glb 0>;
353 353
354 rpm_requests: rpm-requ 354 rpm_requests: rpm-requests {
355 compatible = " !! 355 compatible = "qcom,rpm-msm8998";
356 qcom,glink-cha 356 qcom,glink-channels = "rpm_requests";
357 357
358 rpmcc: clock-c 358 rpmcc: clock-controller {
359 compat 359 compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc";
360 clocks 360 clocks = <&xo>;
361 clock- 361 clock-names = "xo";
362 #clock 362 #clock-cells = <1>;
363 }; 363 };
364 364
365 rpmpd: power-c 365 rpmpd: power-controller {
366 compat 366 compatible = "qcom,msm8998-rpmpd";
367 #power 367 #power-domain-cells = <1>;
368 operat 368 operating-points-v2 = <&rpmpd_opp_table>;
369 369
370 rpmpd_ 370 rpmpd_opp_table: opp-table {
371 371 compatible = "operating-points-v2";
372 372
373 373 rpmpd_opp_ret: opp1 {
374 374 opp-level = <RPM_SMD_LEVEL_RETENTION>;
375 375 };
376 376
377 377 rpmpd_opp_ret_plus: opp2 {
378 378 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
379 379 };
380 380
381 381 rpmpd_opp_min_svs: opp3 {
382 382 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
383 383 };
384 384
385 385 rpmpd_opp_low_svs: opp4 {
386 386 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
387 387 };
388 388
389 389 rpmpd_opp_svs: opp5 {
390 390 opp-level = <RPM_SMD_LEVEL_SVS>;
391 391 };
392 392
393 393 rpmpd_opp_svs_plus: opp6 {
394 394 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
395 395 };
396 396
397 397 rpmpd_opp_nom: opp7 {
398 398 opp-level = <RPM_SMD_LEVEL_NOM>;
399 399 };
400 400
401 401 rpmpd_opp_nom_plus: opp8 {
402 402 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
403 403 };
404 404
405 405 rpmpd_opp_turbo: opp9 {
406 406 opp-level = <RPM_SMD_LEVEL_TURBO>;
407 407 };
408 408
409 409 rpmpd_opp_turbo_plus: opp10 {
410 410 opp-level = <RPM_SMD_LEVEL_BINNING>;
411 411 };
412 }; 412 };
413 }; 413 };
414 }; 414 };
415 }; 415 };
416 }; 416 };
417 417
418 smem { 418 smem {
419 compatible = "qcom,smem"; 419 compatible = "qcom,smem";
420 memory-region = <&smem_mem>; 420 memory-region = <&smem_mem>;
421 hwlocks = <&tcsr_mutex 3>; 421 hwlocks = <&tcsr_mutex 3>;
422 }; 422 };
423 423
424 smp2p-lpass { 424 smp2p-lpass {
425 compatible = "qcom,smp2p"; 425 compatible = "qcom,smp2p";
426 qcom,smem = <443>, <429>; 426 qcom,smem = <443>, <429>;
427 427
428 interrupts = <GIC_SPI 158 IRQ_ 428 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
429 429
430 mboxes = <&apcs_glb 10>; 430 mboxes = <&apcs_glb 10>;
431 431
432 qcom,local-pid = <0>; 432 qcom,local-pid = <0>;
433 qcom,remote-pid = <2>; 433 qcom,remote-pid = <2>;
434 434
435 adsp_smp2p_out: master-kernel 435 adsp_smp2p_out: master-kernel {
436 qcom,entry-name = "mas 436 qcom,entry-name = "master-kernel";
437 #qcom,smem-state-cells 437 #qcom,smem-state-cells = <1>;
438 }; 438 };
439 439
440 adsp_smp2p_in: slave-kernel { 440 adsp_smp2p_in: slave-kernel {
441 qcom,entry-name = "sla 441 qcom,entry-name = "slave-kernel";
442 442
443 interrupt-controller; 443 interrupt-controller;
444 #interrupt-cells = <2> 444 #interrupt-cells = <2>;
445 }; 445 };
446 }; 446 };
447 447
448 smp2p-mpss { 448 smp2p-mpss {
449 compatible = "qcom,smp2p"; 449 compatible = "qcom,smp2p";
450 qcom,smem = <435>, <428>; 450 qcom,smem = <435>, <428>;
451 interrupts = <GIC_SPI 451 IRQ_ 451 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
452 mboxes = <&apcs_glb 14>; 452 mboxes = <&apcs_glb 14>;
453 qcom,local-pid = <0>; 453 qcom,local-pid = <0>;
454 qcom,remote-pid = <1>; 454 qcom,remote-pid = <1>;
455 455
456 modem_smp2p_out: master-kernel 456 modem_smp2p_out: master-kernel {
457 qcom,entry-name = "mas 457 qcom,entry-name = "master-kernel";
458 #qcom,smem-state-cells 458 #qcom,smem-state-cells = <1>;
459 }; 459 };
460 460
461 modem_smp2p_in: slave-kernel { 461 modem_smp2p_in: slave-kernel {
462 qcom,entry-name = "sla 462 qcom,entry-name = "slave-kernel";
463 interrupt-controller; 463 interrupt-controller;
464 #interrupt-cells = <2> 464 #interrupt-cells = <2>;
465 }; 465 };
466 }; 466 };
467 467
468 smp2p-slpi { 468 smp2p-slpi {
469 compatible = "qcom,smp2p"; 469 compatible = "qcom,smp2p";
470 qcom,smem = <481>, <430>; 470 qcom,smem = <481>, <430>;
471 interrupts = <GIC_SPI 178 IRQ_ 471 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
472 mboxes = <&apcs_glb 26>; 472 mboxes = <&apcs_glb 26>;
473 qcom,local-pid = <0>; 473 qcom,local-pid = <0>;
474 qcom,remote-pid = <3>; 474 qcom,remote-pid = <3>;
475 475
476 slpi_smp2p_out: master-kernel 476 slpi_smp2p_out: master-kernel {
477 qcom,entry-name = "mas 477 qcom,entry-name = "master-kernel";
478 #qcom,smem-state-cells 478 #qcom,smem-state-cells = <1>;
479 }; 479 };
480 480
481 slpi_smp2p_in: slave-kernel { 481 slpi_smp2p_in: slave-kernel {
482 qcom,entry-name = "sla 482 qcom,entry-name = "slave-kernel";
483 interrupt-controller; 483 interrupt-controller;
484 #interrupt-cells = <2> 484 #interrupt-cells = <2>;
485 }; 485 };
486 }; 486 };
487 487
488 thermal-zones { 488 thermal-zones {
489 cpu0-thermal { 489 cpu0-thermal {
490 polling-delay-passive 490 polling-delay-passive = <250>;
491 491
492 thermal-sensors = <&ts 492 thermal-sensors = <&tsens0 1>;
493 493
494 trips { 494 trips {
495 cpu0_alert0: t 495 cpu0_alert0: trip-point0 {
496 temper 496 temperature = <75000>;
497 hyster 497 hysteresis = <2000>;
498 type = 498 type = "passive";
499 }; 499 };
500 500
501 cpu0_crit: cpu 501 cpu0_crit: cpu-crit {
502 temper 502 temperature = <110000>;
503 hyster 503 hysteresis = <2000>;
504 type = 504 type = "critical";
505 }; 505 };
506 }; 506 };
507 }; 507 };
508 508
509 cpu1-thermal { 509 cpu1-thermal {
510 polling-delay-passive 510 polling-delay-passive = <250>;
511 511
512 thermal-sensors = <&ts 512 thermal-sensors = <&tsens0 2>;
513 513
514 trips { 514 trips {
515 cpu1_alert0: t 515 cpu1_alert0: trip-point0 {
516 temper 516 temperature = <75000>;
517 hyster 517 hysteresis = <2000>;
518 type = 518 type = "passive";
519 }; 519 };
520 520
521 cpu1_crit: cpu 521 cpu1_crit: cpu-crit {
522 temper 522 temperature = <110000>;
523 hyster 523 hysteresis = <2000>;
524 type = 524 type = "critical";
525 }; 525 };
526 }; 526 };
527 }; 527 };
528 528
529 cpu2-thermal { 529 cpu2-thermal {
530 polling-delay-passive 530 polling-delay-passive = <250>;
531 531
532 thermal-sensors = <&ts 532 thermal-sensors = <&tsens0 3>;
533 533
534 trips { 534 trips {
535 cpu2_alert0: t 535 cpu2_alert0: trip-point0 {
536 temper 536 temperature = <75000>;
537 hyster 537 hysteresis = <2000>;
538 type = 538 type = "passive";
539 }; 539 };
540 540
541 cpu2_crit: cpu 541 cpu2_crit: cpu-crit {
542 temper 542 temperature = <110000>;
543 hyster 543 hysteresis = <2000>;
544 type = 544 type = "critical";
545 }; 545 };
546 }; 546 };
547 }; 547 };
548 548
549 cpu3-thermal { 549 cpu3-thermal {
550 polling-delay-passive 550 polling-delay-passive = <250>;
551 551
552 thermal-sensors = <&ts 552 thermal-sensors = <&tsens0 4>;
553 553
554 trips { 554 trips {
555 cpu3_alert0: t 555 cpu3_alert0: trip-point0 {
556 temper 556 temperature = <75000>;
557 hyster 557 hysteresis = <2000>;
558 type = 558 type = "passive";
559 }; 559 };
560 560
561 cpu3_crit: cpu 561 cpu3_crit: cpu-crit {
562 temper 562 temperature = <110000>;
563 hyster 563 hysteresis = <2000>;
564 type = 564 type = "critical";
565 }; 565 };
566 }; 566 };
567 }; 567 };
568 568
569 cpu4-thermal { 569 cpu4-thermal {
570 polling-delay-passive 570 polling-delay-passive = <250>;
571 571
572 thermal-sensors = <&ts 572 thermal-sensors = <&tsens0 7>;
573 573
574 trips { 574 trips {
575 cpu4_alert0: t 575 cpu4_alert0: trip-point0 {
576 temper 576 temperature = <75000>;
577 hyster 577 hysteresis = <2000>;
578 type = 578 type = "passive";
579 }; 579 };
580 580
581 cpu4_crit: cpu 581 cpu4_crit: cpu-crit {
582 temper 582 temperature = <110000>;
583 hyster 583 hysteresis = <2000>;
584 type = 584 type = "critical";
585 }; 585 };
586 }; 586 };
587 }; 587 };
588 588
589 cpu5-thermal { 589 cpu5-thermal {
590 polling-delay-passive 590 polling-delay-passive = <250>;
591 591
592 thermal-sensors = <&ts 592 thermal-sensors = <&tsens0 8>;
593 593
594 trips { 594 trips {
595 cpu5_alert0: t 595 cpu5_alert0: trip-point0 {
596 temper 596 temperature = <75000>;
597 hyster 597 hysteresis = <2000>;
598 type = 598 type = "passive";
599 }; 599 };
600 600
601 cpu5_crit: cpu 601 cpu5_crit: cpu-crit {
602 temper 602 temperature = <110000>;
603 hyster 603 hysteresis = <2000>;
604 type = 604 type = "critical";
605 }; 605 };
606 }; 606 };
607 }; 607 };
608 608
609 cpu6-thermal { 609 cpu6-thermal {
610 polling-delay-passive 610 polling-delay-passive = <250>;
611 611
612 thermal-sensors = <&ts 612 thermal-sensors = <&tsens0 9>;
613 613
614 trips { 614 trips {
615 cpu6_alert0: t 615 cpu6_alert0: trip-point0 {
616 temper 616 temperature = <75000>;
617 hyster 617 hysteresis = <2000>;
618 type = 618 type = "passive";
619 }; 619 };
620 620
621 cpu6_crit: cpu 621 cpu6_crit: cpu-crit {
622 temper 622 temperature = <110000>;
623 hyster 623 hysteresis = <2000>;
624 type = 624 type = "critical";
625 }; 625 };
626 }; 626 };
627 }; 627 };
628 628
629 cpu7-thermal { 629 cpu7-thermal {
630 polling-delay-passive 630 polling-delay-passive = <250>;
631 631
632 thermal-sensors = <&ts 632 thermal-sensors = <&tsens0 10>;
633 633
634 trips { 634 trips {
635 cpu7_alert0: t 635 cpu7_alert0: trip-point0 {
636 temper 636 temperature = <75000>;
637 hyster 637 hysteresis = <2000>;
638 type = 638 type = "passive";
639 }; 639 };
640 640
641 cpu7_crit: cpu 641 cpu7_crit: cpu-crit {
642 temper 642 temperature = <110000>;
643 hyster 643 hysteresis = <2000>;
644 type = 644 type = "critical";
645 }; 645 };
646 }; 646 };
647 }; 647 };
648 648
649 gpu-bottom-thermal { 649 gpu-bottom-thermal {
650 polling-delay-passive 650 polling-delay-passive = <250>;
651 651
652 thermal-sensors = <&ts 652 thermal-sensors = <&tsens0 12>;
653 653
654 trips { 654 trips {
655 gpu1_alert0: t 655 gpu1_alert0: trip-point0 {
656 temper 656 temperature = <90000>;
657 hyster 657 hysteresis = <2000>;
658 type = 658 type = "hot";
659 }; 659 };
660 }; 660 };
661 }; 661 };
662 662
663 gpu-top-thermal { 663 gpu-top-thermal {
664 polling-delay-passive 664 polling-delay-passive = <250>;
665 665
666 thermal-sensors = <&ts 666 thermal-sensors = <&tsens0 13>;
667 667
668 trips { 668 trips {
669 gpu2_alert0: t 669 gpu2_alert0: trip-point0 {
670 temper 670 temperature = <90000>;
671 hyster 671 hysteresis = <2000>;
672 type = 672 type = "hot";
673 }; 673 };
674 }; 674 };
675 }; 675 };
676 676
677 clust0-mhm-thermal { 677 clust0-mhm-thermal {
678 polling-delay-passive 678 polling-delay-passive = <250>;
679 679
680 thermal-sensors = <&ts 680 thermal-sensors = <&tsens0 5>;
681 681
682 trips { 682 trips {
683 cluster0_mhm_a 683 cluster0_mhm_alert0: trip-point0 {
684 temper 684 temperature = <90000>;
685 hyster 685 hysteresis = <2000>;
686 type = 686 type = "hot";
687 }; 687 };
688 }; 688 };
689 }; 689 };
690 690
691 clust1-mhm-thermal { 691 clust1-mhm-thermal {
692 polling-delay-passive 692 polling-delay-passive = <250>;
693 693
694 thermal-sensors = <&ts 694 thermal-sensors = <&tsens0 6>;
695 695
696 trips { 696 trips {
697 cluster1_mhm_a 697 cluster1_mhm_alert0: trip-point0 {
698 temper 698 temperature = <90000>;
699 hyster 699 hysteresis = <2000>;
700 type = 700 type = "hot";
701 }; 701 };
702 }; 702 };
703 }; 703 };
704 704
705 cluster1-l2-thermal { 705 cluster1-l2-thermal {
706 polling-delay-passive 706 polling-delay-passive = <250>;
707 707
708 thermal-sensors = <&ts 708 thermal-sensors = <&tsens0 11>;
709 709
710 trips { 710 trips {
711 cluster1_l2_al 711 cluster1_l2_alert0: trip-point0 {
712 temper 712 temperature = <90000>;
713 hyster 713 hysteresis = <2000>;
714 type = 714 type = "hot";
715 }; 715 };
716 }; 716 };
717 }; 717 };
718 718
719 modem-thermal { 719 modem-thermal {
720 polling-delay-passive 720 polling-delay-passive = <250>;
721 721
722 thermal-sensors = <&ts 722 thermal-sensors = <&tsens1 1>;
723 723
724 trips { 724 trips {
725 modem_alert0: 725 modem_alert0: trip-point0 {
726 temper 726 temperature = <90000>;
727 hyster 727 hysteresis = <2000>;
728 type = 728 type = "hot";
729 }; 729 };
730 }; 730 };
731 }; 731 };
732 732
733 mem-thermal { 733 mem-thermal {
734 polling-delay-passive 734 polling-delay-passive = <250>;
735 735
736 thermal-sensors = <&ts 736 thermal-sensors = <&tsens1 2>;
737 737
738 trips { 738 trips {
739 mem_alert0: tr 739 mem_alert0: trip-point0 {
740 temper 740 temperature = <90000>;
741 hyster 741 hysteresis = <2000>;
742 type = 742 type = "hot";
743 }; 743 };
744 }; 744 };
745 }; 745 };
746 746
747 wlan-thermal { 747 wlan-thermal {
748 polling-delay-passive 748 polling-delay-passive = <250>;
749 749
750 thermal-sensors = <&ts 750 thermal-sensors = <&tsens1 3>;
751 751
752 trips { 752 trips {
753 wlan_alert0: t 753 wlan_alert0: trip-point0 {
754 temper 754 temperature = <90000>;
755 hyster 755 hysteresis = <2000>;
756 type = 756 type = "hot";
757 }; 757 };
758 }; 758 };
759 }; 759 };
760 760
761 q6-dsp-thermal { 761 q6-dsp-thermal {
762 polling-delay-passive 762 polling-delay-passive = <250>;
763 763
764 thermal-sensors = <&ts 764 thermal-sensors = <&tsens1 4>;
765 765
766 trips { 766 trips {
767 q6_dsp_alert0: 767 q6_dsp_alert0: trip-point0 {
768 temper 768 temperature = <90000>;
769 hyster 769 hysteresis = <2000>;
770 type = 770 type = "hot";
771 }; 771 };
772 }; 772 };
773 }; 773 };
774 774
775 camera-thermal { 775 camera-thermal {
776 polling-delay-passive 776 polling-delay-passive = <250>;
777 777
778 thermal-sensors = <&ts 778 thermal-sensors = <&tsens1 5>;
779 779
780 trips { 780 trips {
781 camera_alert0: 781 camera_alert0: trip-point0 {
782 temper 782 temperature = <90000>;
783 hyster 783 hysteresis = <2000>;
784 type = 784 type = "hot";
785 }; 785 };
786 }; 786 };
787 }; 787 };
788 788
789 multimedia-thermal { 789 multimedia-thermal {
790 polling-delay-passive 790 polling-delay-passive = <250>;
791 791
792 thermal-sensors = <&ts 792 thermal-sensors = <&tsens1 6>;
793 793
794 trips { 794 trips {
795 multimedia_ale 795 multimedia_alert0: trip-point0 {
796 temper 796 temperature = <90000>;
797 hyster 797 hysteresis = <2000>;
798 type = 798 type = "hot";
799 }; 799 };
800 }; 800 };
801 }; 801 };
802 }; 802 };
803 803
804 timer { 804 timer {
805 compatible = "arm,armv8-timer" 805 compatible = "arm,armv8-timer";
806 interrupts = <GIC_PPI 1 IRQ_TY 806 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
807 <GIC_PPI 2 IRQ_TY 807 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
808 <GIC_PPI 3 IRQ_TY 808 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
809 <GIC_PPI 0 IRQ_TY 809 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
810 }; 810 };
811 811
812 soc: soc@0 { 812 soc: soc@0 {
813 #address-cells = <1>; 813 #address-cells = <1>;
814 #size-cells = <1>; 814 #size-cells = <1>;
815 ranges = <0 0 0 0xffffffff>; 815 ranges = <0 0 0 0xffffffff>;
816 compatible = "simple-bus"; 816 compatible = "simple-bus";
817 817
818 gcc: clock-controller@100000 { 818 gcc: clock-controller@100000 {
819 compatible = "qcom,gcc 819 compatible = "qcom,gcc-msm8998";
820 #clock-cells = <1>; 820 #clock-cells = <1>;
821 #reset-cells = <1>; 821 #reset-cells = <1>;
822 #power-domain-cells = 822 #power-domain-cells = <1>;
823 reg = <0x00100000 0xb0 823 reg = <0x00100000 0xb0000>;
824 824
825 clock-names = "xo", "s 825 clock-names = "xo", "sleep_clk";
826 clocks = <&rpmcc RPM_S 826 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>;
827 827
828 /* 828 /*
829 * The hypervisor typi 829 * The hypervisor typically configures the memory region where these clocks
830 * reside as read-only 830 * reside as read-only for the HLOS. If the HLOS tried to enable or disable
831 * these clocks on a d 831 * these clocks on a device with such configuration (e.g. because they are
832 * enabled but unused 832 * enabled but unused during boot-up), the device will most likely decide
833 * to reboot. 833 * to reboot.
834 * In light of that, w 834 * In light of that, we are conservative here and we list all such clocks
835 * as protected. The b 835 * as protected. The board dts (or a user-supplied dts) can override the
836 * list of protected c 836 * list of protected clocks if it differs from the norm, and it is in fact
837 * desired for the HLO 837 * desired for the HLOS to manage these clocks
838 */ 838 */
839 protected-clocks = <AG 839 protected-clocks = <AGGRE2_SNOC_NORTH_AXI>,
840 <SS 840 <SSC_XO>,
841 <SS 841 <SSC_CNOC_AHBS_CLK>;
842 }; 842 };
843 843
844 rpm_msg_ram: sram@778000 { 844 rpm_msg_ram: sram@778000 {
845 compatible = "qcom,rpm 845 compatible = "qcom,rpm-msg-ram";
846 reg = <0x00778000 0x70 846 reg = <0x00778000 0x7000>;
847 }; 847 };
848 848
849 qfprom: qfprom@784000 { 849 qfprom: qfprom@784000 {
850 compatible = "qcom,msm 850 compatible = "qcom,msm8998-qfprom", "qcom,qfprom";
851 reg = <0x00784000 0x62 851 reg = <0x00784000 0x621c>;
852 #address-cells = <1>; 852 #address-cells = <1>;
853 #size-cells = <1>; 853 #size-cells = <1>;
854 854
855 qusb2_hstx_trim: hstx- 855 qusb2_hstx_trim: hstx-trim@23a {
856 reg = <0x23a 0 856 reg = <0x23a 0x1>;
857 bits = <0 4>; 857 bits = <0 4>;
858 }; 858 };
859 }; 859 };
860 860
861 tsens0: thermal@10ab000 { 861 tsens0: thermal@10ab000 {
862 compatible = "qcom,msm 862 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
863 reg = <0x010ab000 0x10 863 reg = <0x010ab000 0x1000>, /* TM */
864 <0x010aa000 0x10 864 <0x010aa000 0x1000>; /* SROT */
865 #qcom,sensors = <14>; 865 #qcom,sensors = <14>;
866 interrupts = <GIC_SPI 866 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
867 <GIC_SPI 867 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
868 interrupt-names = "upl 868 interrupt-names = "uplow", "critical";
869 #thermal-sensor-cells 869 #thermal-sensor-cells = <1>;
870 }; 870 };
871 871
872 tsens1: thermal@10ae000 { 872 tsens1: thermal@10ae000 {
873 compatible = "qcom,msm 873 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
874 reg = <0x010ae000 0x10 874 reg = <0x010ae000 0x1000>, /* TM */
875 <0x010ad000 0x10 875 <0x010ad000 0x1000>; /* SROT */
876 #qcom,sensors = <8>; 876 #qcom,sensors = <8>;
877 interrupts = <GIC_SPI 877 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
878 <GIC_SPI 878 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
879 interrupt-names = "upl 879 interrupt-names = "uplow", "critical";
880 #thermal-sensor-cells 880 #thermal-sensor-cells = <1>;
881 }; 881 };
882 882
883 anoc1_smmu: iommu@1680000 { 883 anoc1_smmu: iommu@1680000 {
884 compatible = "qcom,msm 884 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
885 reg = <0x01680000 0x10 885 reg = <0x01680000 0x10000>;
886 #iommu-cells = <1>; 886 #iommu-cells = <1>;
887 887
888 #global-interrupts = < 888 #global-interrupts = <0>;
889 interrupts = 889 interrupts =
890 <GIC_SPI 364 I 890 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
891 <GIC_SPI 365 I 891 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
892 <GIC_SPI 366 I 892 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
893 <GIC_SPI 367 I 893 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
894 <GIC_SPI 368 I 894 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
895 <GIC_SPI 369 I 895 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>;
896 }; 896 };
897 897
898 anoc2_smmu: iommu@16c0000 { 898 anoc2_smmu: iommu@16c0000 {
899 compatible = "qcom,msm 899 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
900 reg = <0x016c0000 0x40 900 reg = <0x016c0000 0x40000>;
901 #iommu-cells = <1>; 901 #iommu-cells = <1>;
902 902
903 #global-interrupts = < 903 #global-interrupts = <0>;
904 interrupts = 904 interrupts =
905 <GIC_SPI 373 I 905 <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>,
906 <GIC_SPI 374 I 906 <GIC_SPI 374 IRQ_TYPE_EDGE_RISING>,
907 <GIC_SPI 375 I 907 <GIC_SPI 375 IRQ_TYPE_EDGE_RISING>,
908 <GIC_SPI 376 I 908 <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>,
909 <GIC_SPI 377 I 909 <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>,
910 <GIC_SPI 378 I 910 <GIC_SPI 378 IRQ_TYPE_EDGE_RISING>,
911 <GIC_SPI 462 I 911 <GIC_SPI 462 IRQ_TYPE_EDGE_RISING>,
912 <GIC_SPI 463 I 912 <GIC_SPI 463 IRQ_TYPE_EDGE_RISING>,
913 <GIC_SPI 464 I 913 <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
914 <GIC_SPI 465 I 914 <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>;
915 }; 915 };
916 916
917 pcie0: pcie@1c00000 { 917 pcie0: pcie@1c00000 {
918 compatible = "qcom,pci 918 compatible = "qcom,pcie-msm8998", "qcom,pcie-msm8996";
919 reg = <0x01c00000 0x20 919 reg = <0x01c00000 0x2000>,
920 <0x1b000000 0xf1 920 <0x1b000000 0xf1d>,
921 <0x1b000f20 0xa8 921 <0x1b000f20 0xa8>,
922 <0x1b100000 0x10 922 <0x1b100000 0x100000>;
923 reg-names = "parf", "d 923 reg-names = "parf", "dbi", "elbi", "config";
924 device_type = "pci"; 924 device_type = "pci";
925 linux,pci-domain = <0> 925 linux,pci-domain = <0>;
926 bus-range = <0x00 0xff 926 bus-range = <0x00 0xff>;
927 #address-cells = <3>; 927 #address-cells = <3>;
928 #size-cells = <2>; 928 #size-cells = <2>;
929 num-lanes = <1>; 929 num-lanes = <1>;
930 phys = <&pcie_phy>; 930 phys = <&pcie_phy>;
931 phy-names = "pciephy"; 931 phy-names = "pciephy";
932 status = "disabled"; 932 status = "disabled";
933 933
934 ranges = <0x01000000 0 934 ranges = <0x01000000 0x0 0x00000000 0x1b200000 0x0 0x100000>,
935 <0x02000000 0 935 <0x02000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>;
936 936
937 #interrupt-cells = <1> 937 #interrupt-cells = <1>;
938 interrupts = <GIC_SPI 938 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
939 interrupt-names = "msi 939 interrupt-names = "msi";
940 interrupt-map-mask = < 940 interrupt-map-mask = <0 0 0 0x7>;
941 interrupt-map = <0 0 0 941 interrupt-map = <0 0 0 1 &intc 0 0 135 IRQ_TYPE_LEVEL_HIGH>,
942 <0 0 0 942 <0 0 0 2 &intc 0 0 136 IRQ_TYPE_LEVEL_HIGH>,
943 <0 0 0 943 <0 0 0 3 &intc 0 0 138 IRQ_TYPE_LEVEL_HIGH>,
944 <0 0 0 944 <0 0 0 4 &intc 0 0 139 IRQ_TYPE_LEVEL_HIGH>;
945 945
946 clocks = <&gcc GCC_PCI 946 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
947 <&gcc GCC_PCI 947 <&gcc GCC_PCIE_0_AUX_CLK>,
948 <&gcc GCC_PCI 948 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
949 <&gcc GCC_PCI 949 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
950 <&gcc GCC_PCI 950 <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
951 clock-names = "pipe", 951 clock-names = "pipe", "aux", "cfg", "bus_master", "bus_slave";
952 952
953 power-domains = <&gcc 953 power-domains = <&gcc PCIE_0_GDSC>;
954 iommu-map = <0x100 &an 954 iommu-map = <0x100 &anoc1_smmu 0x1480 1>;
955 perst-gpios = <&tlmm 3 955 perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
956 956
957 pcie@0 { 957 pcie@0 {
958 device_type = 958 device_type = "pci";
959 reg = <0x0 0x0 959 reg = <0x0 0x0 0x0 0x0 0x0>;
960 bus-range = <0 960 bus-range = <0x01 0xff>;
961 961
962 #address-cells 962 #address-cells = <3>;
963 #size-cells = 963 #size-cells = <2>;
964 ranges; 964 ranges;
965 }; 965 };
966 }; 966 };
967 967
968 pcie_phy: phy@1c06000 { 968 pcie_phy: phy@1c06000 {
969 compatible = "qcom,msm 969 compatible = "qcom,msm8998-qmp-pcie-phy";
970 reg = <0x01c06000 0x10 970 reg = <0x01c06000 0x1000>;
971 status = "disabled"; 971 status = "disabled";
972 972
973 clocks = <&gcc GCC_PCI 973 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
974 <&gcc GCC_PCI 974 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
975 <&gcc GCC_PCI 975 <&gcc GCC_PCIE_CLKREF_CLK>,
976 <&gcc GCC_PCI 976 <&gcc GCC_PCIE_0_PIPE_CLK>;
977 clock-names = "aux", 977 clock-names = "aux",
978 "cfg_ahb 978 "cfg_ahb",
979 "ref", 979 "ref",
980 "pipe"; 980 "pipe";
981 981
982 clock-output-names = " 982 clock-output-names = "pcie_0_pipe_clk_src";
983 #clock-cells = <0>; 983 #clock-cells = <0>;
984 984
985 #phy-cells = <0>; 985 #phy-cells = <0>;
986 986
987 resets = <&gcc GCC_PCI 987 resets = <&gcc GCC_PCIE_0_PHY_BCR>, <&gcc GCC_PCIE_PHY_BCR>;
988 reset-names = "phy", " 988 reset-names = "phy", "common";
989 989
990 vdda-phy-supply = <&vr 990 vdda-phy-supply = <&vreg_l1a_0p875>;
991 vdda-pll-supply = <&vr 991 vdda-pll-supply = <&vreg_l2a_1p2>;
992 }; 992 };
993 993
994 ufshc: ufshc@1da4000 { 994 ufshc: ufshc@1da4000 {
995 compatible = "qcom,msm 995 compatible = "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
996 reg = <0x01da4000 0x25 996 reg = <0x01da4000 0x2500>;
997 interrupts = <GIC_SPI 997 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
998 phys = <&ufsphy>; 998 phys = <&ufsphy>;
999 phy-names = "ufsphy"; 999 phy-names = "ufsphy";
1000 lanes-per-direction = 1000 lanes-per-direction = <2>;
1001 power-domains = <&gcc 1001 power-domains = <&gcc UFS_GDSC>;
1002 status = "disabled"; 1002 status = "disabled";
1003 #reset-cells = <1>; 1003 #reset-cells = <1>;
1004 1004
1005 clock-names = 1005 clock-names =
1006 "core_clk", 1006 "core_clk",
1007 "bus_aggr_clk 1007 "bus_aggr_clk",
1008 "iface_clk", 1008 "iface_clk",
1009 "core_clk_uni 1009 "core_clk_unipro",
1010 "ref_clk", 1010 "ref_clk",
1011 "tx_lane0_syn 1011 "tx_lane0_sync_clk",
1012 "rx_lane0_syn 1012 "rx_lane0_sync_clk",
1013 "rx_lane1_syn 1013 "rx_lane1_sync_clk";
1014 clocks = 1014 clocks =
1015 <&gcc GCC_UFS 1015 <&gcc GCC_UFS_AXI_CLK>,
1016 <&gcc GCC_AGG 1016 <&gcc GCC_AGGRE1_UFS_AXI_CLK>,
1017 <&gcc GCC_UFS 1017 <&gcc GCC_UFS_AHB_CLK>,
1018 <&gcc GCC_UFS 1018 <&gcc GCC_UFS_UNIPRO_CORE_CLK>,
1019 <&rpmcc RPM_S 1019 <&rpmcc RPM_SMD_LN_BB_CLK1>,
1020 <&gcc GCC_UFS 1020 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
1021 <&gcc GCC_UFS 1021 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>,
1022 <&gcc GCC_UFS 1022 <&gcc GCC_UFS_RX_SYMBOL_1_CLK>;
1023 freq-table-hz = 1023 freq-table-hz =
1024 <50000000 200 1024 <50000000 200000000>,
1025 <0 0>, 1025 <0 0>,
1026 <0 0>, 1026 <0 0>,
1027 <37500000 150 1027 <37500000 150000000>,
1028 <0 0>, 1028 <0 0>,
1029 <0 0>, 1029 <0 0>,
1030 <0 0>, 1030 <0 0>,
1031 <0 0>; 1031 <0 0>;
1032 1032
1033 resets = <&gcc GCC_UF 1033 resets = <&gcc GCC_UFS_BCR>;
1034 reset-names = "rst"; 1034 reset-names = "rst";
1035 }; 1035 };
1036 1036
1037 ufsphy: phy@1da7000 { 1037 ufsphy: phy@1da7000 {
1038 compatible = "qcom,ms 1038 compatible = "qcom,msm8998-qmp-ufs-phy";
1039 reg = <0x01da7000 0x1 1039 reg = <0x01da7000 0x1000>;
1040 1040
1041 clocks = <&rpmcc RPM_ 1041 clocks = <&rpmcc RPM_SMD_LN_BB_CLK1>,
1042 <&gcc GCC_UF 1042 <&gcc GCC_UFS_PHY_AUX_CLK>,
1043 <&gcc GCC_UF 1043 <&gcc GCC_UFS_CLKREF_CLK>;
1044 clock-names = "ref", 1044 clock-names = "ref",
1045 "ref_au 1045 "ref_aux",
1046 "qref"; 1046 "qref";
1047 1047
1048 reset-names = "ufsphy 1048 reset-names = "ufsphy";
1049 resets = <&ufshc 0>; 1049 resets = <&ufshc 0>;
1050 1050
1051 #phy-cells = <0>; 1051 #phy-cells = <0>;
1052 status = "disabled"; 1052 status = "disabled";
1053 }; 1053 };
1054 1054
1055 tcsr_mutex: hwlock@1f40000 { 1055 tcsr_mutex: hwlock@1f40000 {
1056 compatible = "qcom,tc 1056 compatible = "qcom,tcsr-mutex";
1057 reg = <0x01f40000 0x2 1057 reg = <0x01f40000 0x20000>;
1058 #hwlock-cells = <1>; 1058 #hwlock-cells = <1>;
1059 }; 1059 };
1060 1060
1061 tcsr_regs_1: syscon@1f60000 { 1061 tcsr_regs_1: syscon@1f60000 {
1062 compatible = "qcom,ms 1062 compatible = "qcom,msm8998-tcsr", "syscon";
1063 reg = <0x01f60000 0x2 1063 reg = <0x01f60000 0x20000>;
1064 }; 1064 };
1065 1065
1066 tcsr_regs_2: syscon@1fc0000 { 1066 tcsr_regs_2: syscon@1fc0000 {
1067 compatible = "qcom,ms 1067 compatible = "qcom,msm8998-tcsr", "syscon";
1068 reg = <0x01fc0000 0x2 1068 reg = <0x01fc0000 0x26000>;
1069 }; 1069 };
1070 1070
1071 tlmm: pinctrl@3400000 { 1071 tlmm: pinctrl@3400000 {
1072 compatible = "qcom,ms 1072 compatible = "qcom,msm8998-pinctrl";
1073 reg = <0x03400000 0xc 1073 reg = <0x03400000 0xc00000>;
1074 interrupts = <GIC_SPI 1074 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1075 gpio-ranges = <&tlmm 1075 gpio-ranges = <&tlmm 0 0 150>;
1076 gpio-controller; 1076 gpio-controller;
1077 #gpio-cells = <2>; 1077 #gpio-cells = <2>;
1078 interrupt-controller; 1078 interrupt-controller;
1079 #interrupt-cells = <2 1079 #interrupt-cells = <2>;
1080 1080
1081 sdc2_on: sdc2-on-stat 1081 sdc2_on: sdc2-on-state {
1082 clk-pins { 1082 clk-pins {
1083 pins 1083 pins = "sdc2_clk";
1084 drive 1084 drive-strength = <16>;
1085 bias- 1085 bias-disable;
1086 }; 1086 };
1087 1087
1088 cmd-pins { 1088 cmd-pins {
1089 pins 1089 pins = "sdc2_cmd";
1090 drive 1090 drive-strength = <10>;
1091 bias- 1091 bias-pull-up;
1092 }; 1092 };
1093 1093
1094 data-pins { 1094 data-pins {
1095 pins 1095 pins = "sdc2_data";
1096 drive 1096 drive-strength = <10>;
1097 bias- 1097 bias-pull-up;
1098 }; 1098 };
1099 }; 1099 };
1100 1100
1101 sdc2_off: sdc2-off-st 1101 sdc2_off: sdc2-off-state {
1102 clk-pins { 1102 clk-pins {
1103 pins 1103 pins = "sdc2_clk";
1104 drive 1104 drive-strength = <2>;
1105 bias- 1105 bias-disable;
1106 }; 1106 };
1107 1107
1108 cmd-pins { 1108 cmd-pins {
1109 pins 1109 pins = "sdc2_cmd";
1110 drive 1110 drive-strength = <2>;
1111 bias- 1111 bias-pull-up;
1112 }; 1112 };
1113 1113
1114 data-pins { 1114 data-pins {
1115 pins 1115 pins = "sdc2_data";
1116 drive 1116 drive-strength = <2>;
1117 bias- 1117 bias-pull-up;
1118 }; 1118 };
1119 }; 1119 };
1120 1120
1121 sdc2_cd: sdc2-cd-stat 1121 sdc2_cd: sdc2-cd-state {
1122 pins = "gpio9 1122 pins = "gpio95";
1123 function = "g 1123 function = "gpio";
1124 bias-pull-up; 1124 bias-pull-up;
1125 drive-strengt 1125 drive-strength = <2>;
1126 }; 1126 };
1127 1127
1128 blsp1_uart3_on: blsp1 1128 blsp1_uart3_on: blsp1-uart3-on-state {
1129 tx-pins { 1129 tx-pins {
1130 pins 1130 pins = "gpio45";
1131 funct 1131 function = "blsp_uart3_a";
1132 drive 1132 drive-strength = <2>;
1133 bias- 1133 bias-disable;
1134 }; 1134 };
1135 1135
1136 rx-pins { 1136 rx-pins {
1137 pins 1137 pins = "gpio46";
1138 funct 1138 function = "blsp_uart3_a";
1139 drive 1139 drive-strength = <2>;
1140 bias- 1140 bias-disable;
1141 }; 1141 };
1142 1142
1143 cts-pins { 1143 cts-pins {
1144 pins 1144 pins = "gpio47";
1145 funct 1145 function = "blsp_uart3_a";
1146 drive 1146 drive-strength = <2>;
1147 bias- 1147 bias-disable;
1148 }; 1148 };
1149 1149
1150 rfr-pins { 1150 rfr-pins {
1151 pins 1151 pins = "gpio48";
1152 funct 1152 function = "blsp_uart3_a";
1153 drive 1153 drive-strength = <2>;
1154 bias- 1154 bias-disable;
1155 }; 1155 };
1156 }; 1156 };
1157 1157
1158 blsp1_i2c1_default: b 1158 blsp1_i2c1_default: blsp1-i2c1-default-state {
1159 pins = "gpio2 1159 pins = "gpio2", "gpio3";
1160 function = "b 1160 function = "blsp_i2c1";
1161 drive-strengt 1161 drive-strength = <2>;
1162 bias-disable; 1162 bias-disable;
1163 }; 1163 };
1164 1164
1165 blsp1_i2c1_sleep: bls 1165 blsp1_i2c1_sleep: blsp1-i2c1-sleep-state-state {
1166 pins = "gpio2 1166 pins = "gpio2", "gpio3";
1167 function = "b 1167 function = "blsp_i2c1";
1168 drive-strengt 1168 drive-strength = <2>;
1169 bias-pull-up; 1169 bias-pull-up;
1170 }; 1170 };
1171 1171
1172 blsp1_i2c2_default: b 1172 blsp1_i2c2_default: blsp1-i2c2-default-state {
1173 pins = "gpio3 1173 pins = "gpio32", "gpio33";
1174 function = "b 1174 function = "blsp_i2c2";
1175 drive-strengt 1175 drive-strength = <2>;
1176 bias-disable; 1176 bias-disable;
1177 }; 1177 };
1178 1178
1179 blsp1_i2c2_sleep: bls 1179 blsp1_i2c2_sleep: blsp1-i2c2-sleep-state-state {
1180 pins = "gpio3 1180 pins = "gpio32", "gpio33";
1181 function = "b 1181 function = "blsp_i2c2";
1182 drive-strengt 1182 drive-strength = <2>;
1183 bias-pull-up; 1183 bias-pull-up;
1184 }; 1184 };
1185 1185
1186 blsp1_i2c3_default: b 1186 blsp1_i2c3_default: blsp1-i2c3-default-state {
1187 pins = "gpio4 1187 pins = "gpio47", "gpio48";
1188 function = "b 1188 function = "blsp_i2c3";
1189 drive-strengt 1189 drive-strength = <2>;
1190 bias-disable; 1190 bias-disable;
1191 }; 1191 };
1192 1192
1193 blsp1_i2c3_sleep: bls 1193 blsp1_i2c3_sleep: blsp1-i2c3-sleep-state {
1194 pins = "gpio4 1194 pins = "gpio47", "gpio48";
1195 function = "b 1195 function = "blsp_i2c3";
1196 drive-strengt 1196 drive-strength = <2>;
1197 bias-pull-up; 1197 bias-pull-up;
1198 }; 1198 };
1199 1199
1200 blsp1_i2c4_default: b 1200 blsp1_i2c4_default: blsp1-i2c4-default-state {
1201 pins = "gpio1 1201 pins = "gpio10", "gpio11";
1202 function = "b 1202 function = "blsp_i2c4";
1203 drive-strengt 1203 drive-strength = <2>;
1204 bias-disable; 1204 bias-disable;
1205 }; 1205 };
1206 1206
1207 blsp1_i2c4_sleep: bls 1207 blsp1_i2c4_sleep: blsp1-i2c4-sleep-state {
1208 pins = "gpio1 1208 pins = "gpio10", "gpio11";
1209 function = "b 1209 function = "blsp_i2c4";
1210 drive-strengt 1210 drive-strength = <2>;
1211 bias-pull-up; 1211 bias-pull-up;
1212 }; 1212 };
1213 1213
1214 blsp1_i2c5_default: b 1214 blsp1_i2c5_default: blsp1-i2c5-default-state {
1215 pins = "gpio8 1215 pins = "gpio87", "gpio88";
1216 function = "b 1216 function = "blsp_i2c5";
1217 drive-strengt 1217 drive-strength = <2>;
1218 bias-disable; 1218 bias-disable;
1219 }; 1219 };
1220 1220
1221 blsp1_i2c5_sleep: bls 1221 blsp1_i2c5_sleep: blsp1-i2c5-sleep-state {
1222 pins = "gpio8 1222 pins = "gpio87", "gpio88";
1223 function = "b 1223 function = "blsp_i2c5";
1224 drive-strengt 1224 drive-strength = <2>;
1225 bias-pull-up; 1225 bias-pull-up;
1226 }; 1226 };
1227 1227
1228 blsp1_i2c6_default: b 1228 blsp1_i2c6_default: blsp1-i2c6-default-state {
1229 pins = "gpio4 1229 pins = "gpio43", "gpio44";
1230 function = "b 1230 function = "blsp_i2c6";
1231 drive-strengt 1231 drive-strength = <2>;
1232 bias-disable; 1232 bias-disable;
1233 }; 1233 };
1234 1234
1235 blsp1_i2c6_sleep: bls 1235 blsp1_i2c6_sleep: blsp1-i2c6-sleep-state {
1236 pins = "gpio4 1236 pins = "gpio43", "gpio44";
1237 function = "b 1237 function = "blsp_i2c6";
1238 drive-strengt 1238 drive-strength = <2>;
1239 bias-pull-up; 1239 bias-pull-up;
1240 }; 1240 };
1241 1241
1242 blsp1_spi_b_default: 1242 blsp1_spi_b_default: blsp1-spi-b-default-state {
1243 pins = "gpio2 1243 pins = "gpio23", "gpio28";
1244 function = "b 1244 function = "blsp1_spi_b";
1245 drive-strengt 1245 drive-strength = <6>;
1246 bias-disable; 1246 bias-disable;
1247 }; 1247 };
1248 1248
1249 blsp1_spi1_default: b 1249 blsp1_spi1_default: blsp1-spi1-default-state {
1250 pins = "gpio0 1250 pins = "gpio0", "gpio1", "gpio2", "gpio3";
1251 function = "b 1251 function = "blsp_spi1";
1252 drive-strengt 1252 drive-strength = <6>;
1253 bias-disable; 1253 bias-disable;
1254 }; 1254 };
1255 1255
1256 blsp1_spi2_default: b 1256 blsp1_spi2_default: blsp1-spi2-default-state {
1257 pins = "gpio3 1257 pins = "gpio31", "gpio34", "gpio32", "gpio33";
1258 function = "b 1258 function = "blsp_spi2";
1259 drive-strengt 1259 drive-strength = <6>;
1260 bias-disable; 1260 bias-disable;
1261 }; 1261 };
1262 1262
1263 blsp1_spi3_default: b 1263 blsp1_spi3_default: blsp1-spi3-default-state {
1264 pins = "gpio4 1264 pins = "gpio45", "gpio46", "gpio47", "gpio48";
1265 function = "b 1265 function = "blsp_spi2";
1266 drive-strengt 1266 drive-strength = <6>;
1267 bias-disable; 1267 bias-disable;
1268 }; 1268 };
1269 1269
1270 blsp1_spi4_default: b 1270 blsp1_spi4_default: blsp1-spi4-default-state {
1271 pins = "gpio8 1271 pins = "gpio8", "gpio9", "gpio10", "gpio11";
1272 function = "b 1272 function = "blsp_spi4";
1273 drive-strengt 1273 drive-strength = <6>;
1274 bias-disable; 1274 bias-disable;
1275 }; 1275 };
1276 1276
1277 blsp1_spi5_default: b 1277 blsp1_spi5_default: blsp1-spi5-default-state {
1278 pins = "gpio8 1278 pins = "gpio85", "gpio86", "gpio87", "gpio88";
1279 function = "b 1279 function = "blsp_spi5";
1280 drive-strengt 1280 drive-strength = <6>;
1281 bias-disable; 1281 bias-disable;
1282 }; 1282 };
1283 1283
1284 blsp1_spi6_default: b 1284 blsp1_spi6_default: blsp1-spi6-default-state {
1285 pins = "gpio4 1285 pins = "gpio41", "gpio42", "gpio43", "gpio44";
1286 function = "b 1286 function = "blsp_spi6";
1287 drive-strengt 1287 drive-strength = <6>;
1288 bias-disable; 1288 bias-disable;
1289 }; 1289 };
1290 1290
1291 1291
1292 /* 6 interfaces per Q 1292 /* 6 interfaces per QUP, BLSP2 indexes are numbered (n)+6 */
1293 blsp2_i2c1_default: b 1293 blsp2_i2c1_default: blsp2-i2c1-default-state {
1294 pins = "gpio5 1294 pins = "gpio55", "gpio56";
1295 function = "b 1295 function = "blsp_i2c7";
1296 drive-strengt 1296 drive-strength = <2>;
1297 bias-disable; 1297 bias-disable;
1298 }; 1298 };
1299 1299
1300 blsp2_i2c1_sleep: bls 1300 blsp2_i2c1_sleep: blsp2-i2c1-sleep-state {
1301 pins = "gpio5 1301 pins = "gpio55", "gpio56";
1302 function = "b 1302 function = "blsp_i2c7";
1303 drive-strengt 1303 drive-strength = <2>;
1304 bias-pull-up; 1304 bias-pull-up;
1305 }; 1305 };
1306 1306
1307 blsp2_i2c2_default: b 1307 blsp2_i2c2_default: blsp2-i2c2-default-state {
1308 pins = "gpio6 1308 pins = "gpio6", "gpio7";
1309 function = "b 1309 function = "blsp_i2c8";
1310 drive-strengt 1310 drive-strength = <2>;
1311 bias-disable; 1311 bias-disable;
1312 }; 1312 };
1313 1313
1314 blsp2_i2c2_sleep: bls 1314 blsp2_i2c2_sleep: blsp2-i2c2-sleep-state {
1315 pins = "gpio6 1315 pins = "gpio6", "gpio7";
1316 function = "b 1316 function = "blsp_i2c8";
1317 drive-strengt 1317 drive-strength = <2>;
1318 bias-pull-up; 1318 bias-pull-up;
1319 }; 1319 };
1320 1320
1321 blsp2_i2c3_default: b 1321 blsp2_i2c3_default: blsp2-i2c3-default-state {
1322 pins = "gpio5 1322 pins = "gpio51", "gpio52";
1323 function = "b 1323 function = "blsp_i2c9";
1324 drive-strengt 1324 drive-strength = <2>;
1325 bias-disable; 1325 bias-disable;
1326 }; 1326 };
1327 1327
1328 blsp2_i2c3_sleep: bls 1328 blsp2_i2c3_sleep: blsp2-i2c3-sleep-state {
1329 pins = "gpio5 1329 pins = "gpio51", "gpio52";
1330 function = "b 1330 function = "blsp_i2c9";
1331 drive-strengt 1331 drive-strength = <2>;
1332 bias-pull-up; 1332 bias-pull-up;
1333 }; 1333 };
1334 1334
1335 blsp2_i2c4_default: b 1335 blsp2_i2c4_default: blsp2-i2c4-default-state {
1336 pins = "gpio6 1336 pins = "gpio67", "gpio68";
1337 function = "b 1337 function = "blsp_i2c10";
1338 drive-strengt 1338 drive-strength = <2>;
1339 bias-disable; 1339 bias-disable;
1340 }; 1340 };
1341 1341
1342 blsp2_i2c4_sleep: bls 1342 blsp2_i2c4_sleep: blsp2-i2c4-sleep-state {
1343 pins = "gpio6 1343 pins = "gpio67", "gpio68";
1344 function = "b 1344 function = "blsp_i2c10";
1345 drive-strengt 1345 drive-strength = <2>;
1346 bias-pull-up; 1346 bias-pull-up;
1347 }; 1347 };
1348 1348
1349 blsp2_i2c5_default: b 1349 blsp2_i2c5_default: blsp2-i2c5-default-state {
1350 pins = "gpio6 1350 pins = "gpio60", "gpio61";
1351 function = "b 1351 function = "blsp_i2c11";
1352 drive-strengt 1352 drive-strength = <2>;
1353 bias-disable; 1353 bias-disable;
1354 }; 1354 };
1355 1355
1356 blsp2_i2c5_sleep: bls 1356 blsp2_i2c5_sleep: blsp2-i2c5-sleep-state {
1357 pins = "gpio6 1357 pins = "gpio60", "gpio61";
1358 function = "b 1358 function = "blsp_i2c11";
1359 drive-strengt 1359 drive-strength = <2>;
1360 bias-pull-up; 1360 bias-pull-up;
1361 }; 1361 };
1362 1362
1363 blsp2_i2c6_default: b 1363 blsp2_i2c6_default: blsp2-i2c6-default-state {
1364 pins = "gpio8 1364 pins = "gpio83", "gpio84";
1365 function = "b 1365 function = "blsp_i2c12";
1366 drive-strengt 1366 drive-strength = <2>;
1367 bias-disable; 1367 bias-disable;
1368 }; 1368 };
1369 1369
1370 blsp2_i2c6_sleep: bls 1370 blsp2_i2c6_sleep: blsp2-i2c6-sleep-state {
1371 pins = "gpio8 1371 pins = "gpio83", "gpio84";
1372 function = "b 1372 function = "blsp_i2c12";
1373 drive-strengt 1373 drive-strength = <2>;
1374 bias-pull-up; 1374 bias-pull-up;
1375 }; 1375 };
1376 1376
1377 blsp2_spi1_default: b 1377 blsp2_spi1_default: blsp2-spi1-default-state {
1378 pins = "gpio5 1378 pins = "gpio53", "gpio54", "gpio55", "gpio56";
1379 function = "b 1379 function = "blsp_spi7";
1380 drive-strengt 1380 drive-strength = <6>;
1381 bias-disable; 1381 bias-disable;
1382 }; 1382 };
1383 1383
1384 blsp2_spi2_default: b 1384 blsp2_spi2_default: blsp2-spi2-default-state {
1385 pins = "gpio4 1385 pins = "gpio4", "gpio5", "gpio6", "gpio7";
1386 function = "b 1386 function = "blsp_spi8";
1387 drive-strengt 1387 drive-strength = <6>;
1388 bias-disable; 1388 bias-disable;
1389 }; 1389 };
1390 1390
1391 blsp2_spi3_default: b 1391 blsp2_spi3_default: blsp2-spi3-default-state {
1392 pins = "gpio4 1392 pins = "gpio49", "gpio50", "gpio51", "gpio52";
1393 function = "b 1393 function = "blsp_spi9";
1394 drive-strengt 1394 drive-strength = <6>;
1395 bias-disable; 1395 bias-disable;
1396 }; 1396 };
1397 1397
1398 blsp2_spi4_default: b 1398 blsp2_spi4_default: blsp2-spi4-default-state {
1399 pins = "gpio6 1399 pins = "gpio65", "gpio66", "gpio67", "gpio68";
1400 function = "b 1400 function = "blsp_spi10";
1401 drive-strengt 1401 drive-strength = <6>;
1402 bias-disable; 1402 bias-disable;
1403 }; 1403 };
1404 1404
1405 blsp2_spi5_default: b 1405 blsp2_spi5_default: blsp2-spi5-default-state {
1406 pins = "gpio5 1406 pins = "gpio58", "gpio59", "gpio60", "gpio61";
1407 function = "b 1407 function = "blsp_spi11";
1408 drive-strengt 1408 drive-strength = <6>;
1409 bias-disable; 1409 bias-disable;
1410 }; 1410 };
1411 1411
1412 blsp2_spi6_default: b 1412 blsp2_spi6_default: blsp2-spi6-default-state {
1413 pins = "gpio8 1413 pins = "gpio81", "gpio82", "gpio83", "gpio84";
1414 function = "b 1414 function = "blsp_spi12";
1415 drive-strengt 1415 drive-strength = <6>;
1416 bias-disable; 1416 bias-disable;
1417 }; 1417 };
1418 }; 1418 };
1419 1419
1420 remoteproc_mss: remoteproc@40 1420 remoteproc_mss: remoteproc@4080000 {
1421 compatible = "qcom,ms 1421 compatible = "qcom,msm8998-mss-pil";
1422 reg = <0x04080000 0x1 1422 reg = <0x04080000 0x100>, <0x04180000 0x20>;
1423 reg-names = "qdsp6", 1423 reg-names = "qdsp6", "rmb";
1424 1424
1425 interrupts-extended = 1425 interrupts-extended =
1426 <&intc GIC_SP 1426 <&intc GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
1427 <&modem_smp2p 1427 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1428 <&modem_smp2p 1428 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1429 <&modem_smp2p 1429 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1430 <&modem_smp2p 1430 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
1431 <&modem_smp2p 1431 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
1432 interrupt-names = "wd 1432 interrupt-names = "wdog", "fatal", "ready",
1433 "ha 1433 "handover", "stop-ack",
1434 "sh 1434 "shutdown-ack";
1435 1435
1436 clocks = <&gcc GCC_MS 1436 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
1437 <&gcc GCC_BI 1437 <&gcc GCC_BIMC_MSS_Q6_AXI_CLK>,
1438 <&gcc GCC_BO 1438 <&gcc GCC_BOOT_ROM_AHB_CLK>,
1439 <&gcc GCC_MS 1439 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
1440 <&gcc GCC_MS 1440 <&gcc GCC_MSS_SNOC_AXI_CLK>,
1441 <&gcc GCC_MS 1441 <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>,
1442 <&rpmcc RPM_ 1442 <&rpmcc RPM_SMD_QDSS_CLK>,
1443 <&rpmcc RPM_ 1443 <&rpmcc RPM_SMD_XO_CLK_SRC>;
1444 clock-names = "iface" 1444 clock-names = "iface", "bus", "mem", "gpll0_mss",
1445 "snoc_a 1445 "snoc_axi", "mnoc_axi", "qdss", "xo";
1446 1446
1447 qcom,smem-states = <& 1447 qcom,smem-states = <&modem_smp2p_out 0>;
1448 qcom,smem-state-names 1448 qcom,smem-state-names = "stop";
1449 1449
1450 resets = <&gcc GCC_MS 1450 resets = <&gcc GCC_MSS_RESTART>;
1451 reset-names = "mss_re 1451 reset-names = "mss_restart";
1452 1452
1453 qcom,halt-regs = <&tc 1453 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>;
1454 1454
1455 power-domains = <&rpm 1455 power-domains = <&rpmpd MSM8998_VDDCX>,
1456 <&rpm 1456 <&rpmpd MSM8998_VDDMX>;
1457 power-domain-names = 1457 power-domain-names = "cx", "mx";
1458 1458
1459 status = "disabled"; 1459 status = "disabled";
1460 1460
1461 mba { 1461 mba {
1462 memory-region 1462 memory-region = <&mba_mem>;
1463 }; 1463 };
1464 1464
1465 mpss { 1465 mpss {
1466 memory-region 1466 memory-region = <&mpss_mem>;
1467 }; 1467 };
1468 1468
1469 metadata { 1469 metadata {
1470 memory-region 1470 memory-region = <&mdata_mem>;
1471 }; 1471 };
1472 1472
1473 glink-edge { 1473 glink-edge {
1474 interrupts = 1474 interrupts = <GIC_SPI 452 IRQ_TYPE_EDGE_RISING>;
1475 label = "mode 1475 label = "modem";
1476 qcom,remote-p 1476 qcom,remote-pid = <1>;
1477 mboxes = <&ap 1477 mboxes = <&apcs_glb 15>;
1478 }; 1478 };
1479 }; 1479 };
1480 1480
1481 adreno_gpu: gpu@5000000 { 1481 adreno_gpu: gpu@5000000 {
1482 compatible = "qcom,ad 1482 compatible = "qcom,adreno-540.1", "qcom,adreno";
1483 reg = <0x05000000 0x4 1483 reg = <0x05000000 0x40000>;
1484 reg-names = "kgsl_3d0 1484 reg-names = "kgsl_3d0_reg_memory";
1485 1485
1486 clocks = <&gcc GCC_GP 1486 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
1487 <&gpucc RBBMT 1487 <&gpucc RBBMTIMER_CLK>,
1488 <&gcc GCC_BIM 1488 <&gcc GCC_BIMC_GFX_CLK>,
1489 <&gcc GCC_GPU 1489 <&gcc GCC_GPU_BIMC_GFX_CLK>,
1490 <&gpucc RBCPR 1490 <&gpucc RBCPR_CLK>,
1491 <&gpucc GFX3D 1491 <&gpucc GFX3D_CLK>;
1492 clock-names = "iface" 1492 clock-names = "iface",
1493 "rbbmtimer", 1493 "rbbmtimer",
1494 "mem", 1494 "mem",
1495 "mem_iface", 1495 "mem_iface",
1496 "rbcpr", 1496 "rbcpr",
1497 "core"; 1497 "core";
1498 1498
1499 interrupts = <GIC_SPI 1499 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
1500 iommus = <&adreno_smm 1500 iommus = <&adreno_smmu 0>;
1501 operating-points-v2 = 1501 operating-points-v2 = <&gpu_opp_table>;
1502 power-domains = <&rpm 1502 power-domains = <&rpmpd MSM8998_VDDMX>;
1503 status = "disabled"; 1503 status = "disabled";
1504 1504
1505 gpu_opp_table: opp-ta 1505 gpu_opp_table: opp-table {
1506 compatible = 1506 compatible = "operating-points-v2";
1507 opp-710000097 1507 opp-710000097 {
1508 opp-h 1508 opp-hz = /bits/ 64 <710000097>;
1509 opp-l 1509 opp-level = <RPM_SMD_LEVEL_TURBO>;
1510 opp-s 1510 opp-supported-hw = <0xff>;
1511 }; 1511 };
1512 1512
1513 opp-670000048 1513 opp-670000048 {
1514 opp-h 1514 opp-hz = /bits/ 64 <670000048>;
1515 opp-l 1515 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
1516 opp-s 1516 opp-supported-hw = <0xff>;
1517 }; 1517 };
1518 1518
1519 opp-596000097 1519 opp-596000097 {
1520 opp-h 1520 opp-hz = /bits/ 64 <596000097>;
1521 opp-l 1521 opp-level = <RPM_SMD_LEVEL_NOM>;
1522 opp-s 1522 opp-supported-hw = <0xff>;
1523 }; 1523 };
1524 1524
1525 opp-515000097 1525 opp-515000097 {
1526 opp-h 1526 opp-hz = /bits/ 64 <515000097>;
1527 opp-l 1527 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
1528 opp-s 1528 opp-supported-hw = <0xff>;
1529 }; 1529 };
1530 1530
1531 opp-414000000 1531 opp-414000000 {
1532 opp-h 1532 opp-hz = /bits/ 64 <414000000>;
1533 opp-l 1533 opp-level = <RPM_SMD_LEVEL_SVS>;
1534 opp-s 1534 opp-supported-hw = <0xff>;
1535 }; 1535 };
1536 1536
1537 opp-342000000 1537 opp-342000000 {
1538 opp-h 1538 opp-hz = /bits/ 64 <342000000>;
1539 opp-l 1539 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
1540 opp-s 1540 opp-supported-hw = <0xff>;
1541 }; 1541 };
1542 1542
1543 opp-257000000 1543 opp-257000000 {
1544 opp-h 1544 opp-hz = /bits/ 64 <257000000>;
1545 opp-l 1545 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
1546 opp-s 1546 opp-supported-hw = <0xff>;
1547 }; 1547 };
1548 }; 1548 };
1549 }; 1549 };
1550 1550
1551 adreno_smmu: iommu@5040000 { 1551 adreno_smmu: iommu@5040000 {
1552 compatible = "qcom,ms 1552 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
1553 reg = <0x05040000 0x1 1553 reg = <0x05040000 0x10000>;
1554 clocks = <&gcc GCC_GP 1554 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
1555 <&gcc GCC_BI 1555 <&gcc GCC_BIMC_GFX_CLK>,
1556 <&gcc GCC_GP 1556 <&gcc GCC_GPU_BIMC_GFX_CLK>;
1557 clock-names = "iface" 1557 clock-names = "iface", "mem", "mem_iface";
1558 1558
1559 #global-interrupts = 1559 #global-interrupts = <0>;
1560 #iommu-cells = <1>; 1560 #iommu-cells = <1>;
1561 interrupts = 1561 interrupts =
1562 <GIC_SPI 329 1562 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1563 <GIC_SPI 330 1563 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
1564 <GIC_SPI 331 1564 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
1565 /* 1565 /*
1566 * GPU-GX GDSC's pare 1566 * GPU-GX GDSC's parent is GPU-CX. We need to bring up the
1567 * GPU-CX for SMMU bu 1567 * GPU-CX for SMMU but we need both of them up for Adreno.
1568 * Contemporarily, we 1568 * Contemporarily, we also need to manage the VDDMX rpmpd
1569 * domain in the Adre 1569 * domain in the Adreno driver.
1570 * Enable GPU CX/GX G 1570 * Enable GPU CX/GX GDSCs here so that we can manage the
1571 * SoC VDDMX RPM Powe 1571 * SoC VDDMX RPM Power Domain in the Adreno driver.
1572 */ 1572 */
1573 power-domains = <&gpu 1573 power-domains = <&gpucc GPU_GX_GDSC>;
1574 }; 1574 };
1575 1575
1576 gpucc: clock-controller@50650 1576 gpucc: clock-controller@5065000 {
1577 compatible = "qcom,ms 1577 compatible = "qcom,msm8998-gpucc";
1578 #clock-cells = <1>; 1578 #clock-cells = <1>;
1579 #reset-cells = <1>; 1579 #reset-cells = <1>;
1580 #power-domain-cells = 1580 #power-domain-cells = <1>;
1581 reg = <0x05065000 0x9 1581 reg = <0x05065000 0x9000>;
1582 1582
1583 clocks = <&rpmcc RPM_ 1583 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1584 <&gcc GCC_GP 1584 <&gcc GCC_GPU_GPLL0_CLK>;
1585 clock-names = "xo", 1585 clock-names = "xo",
1586 "gpll0" 1586 "gpll0";
1587 }; <<
1588 <<
1589 lpass_q6_smmu: iommu@5100000 <<
1590 compatible = "qcom,ms <<
1591 reg = <0x05100000 0x4 <<
1592 clocks = <&gcc HLOS1_ <<
1593 clock-names = "bus"; <<
1594 <<
1595 #global-interrupts = <<
1596 #iommu-cells = <1>; <<
1597 interrupts = <<
1598 <GIC_SPI 226 <<
1599 <GIC_SPI 393 <<
1600 <GIC_SPI 394 <<
1601 <GIC_SPI 395 <<
1602 <GIC_SPI 396 <<
1603 <GIC_SPI 397 <<
1604 <GIC_SPI 398 <<
1605 <GIC_SPI 399 <<
1606 <GIC_SPI 400 <<
1607 <GIC_SPI 401 <<
1608 <GIC_SPI 402 <<
1609 <GIC_SPI 403 <<
1610 <GIC_SPI 137 <<
1611 <<
1612 power-domains = <&gcc <<
1613 status = "disabled"; <<
1614 }; 1587 };
1615 1588
1616 remoteproc_slpi: remoteproc@5 1589 remoteproc_slpi: remoteproc@5800000 {
1617 compatible = "qcom,ms 1590 compatible = "qcom,msm8998-slpi-pas";
1618 reg = <0x05800000 0x4 1591 reg = <0x05800000 0x4040>;
1619 1592
1620 interrupts-extended = 1593 interrupts-extended = <&intc GIC_SPI 390 IRQ_TYPE_EDGE_RISING>,
1621 1594 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1622 1595 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1623 1596 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1624 1597 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1625 interrupt-names = "wd 1598 interrupt-names = "wdog", "fatal", "ready",
1626 "ha 1599 "handover", "stop-ack";
1627 1600
1628 px-supply = <&vreg_lv 1601 px-supply = <&vreg_lvs2a_1p8>;
1629 1602
1630 clocks = <&rpmcc RPM_ 1603 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
1631 clock-names = "xo"; 1604 clock-names = "xo";
1632 1605
1633 memory-region = <&slp 1606 memory-region = <&slpi_mem>;
1634 1607
1635 qcom,smem-states = <& 1608 qcom,smem-states = <&slpi_smp2p_out 0>;
1636 qcom,smem-state-names 1609 qcom,smem-state-names = "stop";
1637 1610
1638 power-domains = <&rpm 1611 power-domains = <&rpmpd MSM8998_SSCCX>;
1639 power-domain-names = 1612 power-domain-names = "ssc_cx";
1640 1613
1641 status = "disabled"; 1614 status = "disabled";
1642 1615
1643 glink-edge { 1616 glink-edge {
1644 interrupts = 1617 interrupts = <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>;
1645 label = "dsps 1618 label = "dsps";
1646 qcom,remote-p 1619 qcom,remote-pid = <3>;
1647 mboxes = <&ap 1620 mboxes = <&apcs_glb 27>;
1648 }; 1621 };
1649 }; 1622 };
1650 1623
1651 stm: stm@6002000 { 1624 stm: stm@6002000 {
1652 compatible = "arm,cor 1625 compatible = "arm,coresight-stm", "arm,primecell";
1653 reg = <0x06002000 0x1 1626 reg = <0x06002000 0x1000>,
1654 <0x16280000 0x1 1627 <0x16280000 0x180000>;
1655 reg-names = "stm-base 1628 reg-names = "stm-base", "stm-stimulus-base";
1656 status = "disabled"; 1629 status = "disabled";
1657 1630
1658 clocks = <&rpmcc RPM_ 1631 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1659 clock-names = "apb_pc 1632 clock-names = "apb_pclk", "atclk";
1660 1633
1661 out-ports { 1634 out-ports {
1662 port { 1635 port {
1663 stm_o 1636 stm_out: endpoint {
1664 1637 remote-endpoint = <&funnel0_in7>;
1665 }; 1638 };
1666 }; 1639 };
1667 }; 1640 };
1668 }; 1641 };
1669 1642
1670 funnel1: funnel@6041000 { 1643 funnel1: funnel@6041000 {
1671 compatible = "arm,cor 1644 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1672 reg = <0x06041000 0x1 1645 reg = <0x06041000 0x1000>;
1673 status = "disabled"; 1646 status = "disabled";
1674 1647
1675 clocks = <&rpmcc RPM_ 1648 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1676 clock-names = "apb_pc 1649 clock-names = "apb_pclk", "atclk";
1677 1650
1678 out-ports { 1651 out-ports {
1679 port { 1652 port {
1680 funne 1653 funnel0_out: endpoint {
1681 1654 remote-endpoint =
1682 1655 <&merge_funnel_in0>;
1683 }; 1656 };
1684 }; 1657 };
1685 }; 1658 };
1686 1659
1687 in-ports { 1660 in-ports {
1688 #address-cell 1661 #address-cells = <1>;
1689 #size-cells = 1662 #size-cells = <0>;
1690 1663
1691 port@7 { 1664 port@7 {
1692 reg = 1665 reg = <7>;
1693 funne 1666 funnel0_in7: endpoint {
1694 1667 remote-endpoint = <&stm_out>;
1695 }; 1668 };
1696 }; 1669 };
1697 }; 1670 };
1698 }; 1671 };
1699 1672
1700 funnel2: funnel@6042000 { 1673 funnel2: funnel@6042000 {
1701 compatible = "arm,cor 1674 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1702 reg = <0x06042000 0x1 1675 reg = <0x06042000 0x1000>;
1703 status = "disabled"; 1676 status = "disabled";
1704 1677
1705 clocks = <&rpmcc RPM_ 1678 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1706 clock-names = "apb_pc 1679 clock-names = "apb_pclk", "atclk";
1707 1680
1708 out-ports { 1681 out-ports {
1709 port { 1682 port {
1710 funne 1683 funnel1_out: endpoint {
1711 1684 remote-endpoint =
1712 1685 <&merge_funnel_in1>;
1713 }; 1686 };
1714 }; 1687 };
1715 }; 1688 };
1716 1689
1717 in-ports { 1690 in-ports {
1718 #address-cell 1691 #address-cells = <1>;
1719 #size-cells = 1692 #size-cells = <0>;
1720 1693
1721 port@6 { 1694 port@6 {
1722 reg = 1695 reg = <6>;
1723 funne 1696 funnel1_in6: endpoint {
1724 1697 remote-endpoint =
1725 1698 <&apss_merge_funnel_out>;
1726 }; 1699 };
1727 }; 1700 };
1728 }; 1701 };
1729 }; 1702 };
1730 1703
1731 funnel3: funnel@6045000 { 1704 funnel3: funnel@6045000 {
1732 compatible = "arm,cor 1705 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1733 reg = <0x06045000 0x1 1706 reg = <0x06045000 0x1000>;
1734 status = "disabled"; 1707 status = "disabled";
1735 1708
1736 clocks = <&rpmcc RPM_ 1709 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1737 clock-names = "apb_pc 1710 clock-names = "apb_pclk", "atclk";
1738 1711
1739 out-ports { 1712 out-ports {
1740 port { 1713 port {
1741 merge 1714 merge_funnel_out: endpoint {
1742 1715 remote-endpoint =
1743 1716 <&etf_in>;
1744 }; 1717 };
1745 }; 1718 };
1746 }; 1719 };
1747 1720
1748 in-ports { 1721 in-ports {
1749 #address-cell 1722 #address-cells = <1>;
1750 #size-cells = 1723 #size-cells = <0>;
1751 1724
1752 port@0 { 1725 port@0 {
1753 reg = 1726 reg = <0>;
1754 merge 1727 merge_funnel_in0: endpoint {
1755 1728 remote-endpoint =
1756 1729 <&funnel0_out>;
1757 }; 1730 };
1758 }; 1731 };
1759 1732
1760 port@1 { 1733 port@1 {
1761 reg = 1734 reg = <1>;
1762 merge 1735 merge_funnel_in1: endpoint {
1763 1736 remote-endpoint =
1764 1737 <&funnel1_out>;
1765 }; 1738 };
1766 }; 1739 };
1767 }; 1740 };
1768 }; 1741 };
1769 1742
1770 replicator1: replicator@60460 1743 replicator1: replicator@6046000 {
1771 compatible = "arm,cor 1744 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
1772 reg = <0x06046000 0x1 1745 reg = <0x06046000 0x1000>;
1773 status = "disabled"; 1746 status = "disabled";
1774 1747
1775 clocks = <&rpmcc RPM_ 1748 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1776 clock-names = "apb_pc 1749 clock-names = "apb_pclk", "atclk";
1777 1750
1778 out-ports { 1751 out-ports {
1779 port { 1752 port {
1780 repli 1753 replicator_out: endpoint {
1781 1754 remote-endpoint = <&etr_in>;
1782 }; 1755 };
1783 }; 1756 };
1784 }; 1757 };
1785 1758
1786 in-ports { 1759 in-ports {
1787 port { 1760 port {
1788 repli 1761 replicator_in: endpoint {
1789 1762 remote-endpoint = <&etf_out>;
1790 }; 1763 };
1791 }; 1764 };
1792 }; 1765 };
1793 }; 1766 };
1794 1767
1795 etf: etf@6047000 { 1768 etf: etf@6047000 {
1796 compatible = "arm,cor 1769 compatible = "arm,coresight-tmc", "arm,primecell";
1797 reg = <0x06047000 0x1 1770 reg = <0x06047000 0x1000>;
1798 status = "disabled"; 1771 status = "disabled";
1799 1772
1800 clocks = <&rpmcc RPM_ 1773 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1801 clock-names = "apb_pc 1774 clock-names = "apb_pclk", "atclk";
1802 1775
1803 out-ports { 1776 out-ports {
1804 port { 1777 port {
1805 etf_o 1778 etf_out: endpoint {
1806 1779 remote-endpoint =
1807 1780 <&replicator_in>;
1808 }; 1781 };
1809 }; 1782 };
1810 }; 1783 };
1811 1784
1812 in-ports { 1785 in-ports {
1813 port { 1786 port {
1814 etf_i 1787 etf_in: endpoint {
1815 1788 remote-endpoint =
1816 1789 <&merge_funnel_out>;
1817 }; 1790 };
1818 }; 1791 };
1819 }; 1792 };
1820 }; 1793 };
1821 1794
1822 etr: etr@6048000 { 1795 etr: etr@6048000 {
1823 compatible = "arm,cor 1796 compatible = "arm,coresight-tmc", "arm,primecell";
1824 reg = <0x06048000 0x1 1797 reg = <0x06048000 0x1000>;
1825 status = "disabled"; 1798 status = "disabled";
1826 1799
1827 clocks = <&rpmcc RPM_ 1800 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1828 clock-names = "apb_pc 1801 clock-names = "apb_pclk", "atclk";
1829 arm,scatter-gather; 1802 arm,scatter-gather;
1830 1803
1831 in-ports { 1804 in-ports {
1832 port { 1805 port {
1833 etr_i 1806 etr_in: endpoint {
1834 1807 remote-endpoint =
1835 1808 <&replicator_out>;
1836 }; 1809 };
1837 }; 1810 };
1838 }; 1811 };
1839 }; 1812 };
1840 1813
1841 etm1: etm@7840000 { 1814 etm1: etm@7840000 {
1842 compatible = "arm,cor 1815 compatible = "arm,coresight-etm4x", "arm,primecell";
1843 reg = <0x07840000 0x1 1816 reg = <0x07840000 0x1000>;
1844 status = "disabled"; 1817 status = "disabled";
1845 1818
1846 clocks = <&rpmcc RPM_ 1819 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1847 clock-names = "apb_pc 1820 clock-names = "apb_pclk", "atclk";
1848 1821
1849 cpu = <&CPU0>; 1822 cpu = <&CPU0>;
1850 1823
1851 out-ports { 1824 out-ports {
1852 port { 1825 port {
1853 etm0_ 1826 etm0_out: endpoint {
1854 1827 remote-endpoint =
1855 1828 <&apss_funnel_in0>;
1856 }; 1829 };
1857 }; 1830 };
1858 }; 1831 };
1859 }; 1832 };
1860 1833
1861 etm2: etm@7940000 { 1834 etm2: etm@7940000 {
1862 compatible = "arm,cor 1835 compatible = "arm,coresight-etm4x", "arm,primecell";
1863 reg = <0x07940000 0x1 1836 reg = <0x07940000 0x1000>;
1864 status = "disabled"; 1837 status = "disabled";
1865 1838
1866 clocks = <&rpmcc RPM_ 1839 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1867 clock-names = "apb_pc 1840 clock-names = "apb_pclk", "atclk";
1868 1841
1869 cpu = <&CPU1>; 1842 cpu = <&CPU1>;
1870 1843
1871 out-ports { 1844 out-ports {
1872 port { 1845 port {
1873 etm1_ 1846 etm1_out: endpoint {
1874 1847 remote-endpoint =
1875 1848 <&apss_funnel_in1>;
1876 }; 1849 };
1877 }; 1850 };
1878 }; 1851 };
1879 }; 1852 };
1880 1853
1881 etm3: etm@7a40000 { 1854 etm3: etm@7a40000 {
1882 compatible = "arm,cor 1855 compatible = "arm,coresight-etm4x", "arm,primecell";
1883 reg = <0x07a40000 0x1 1856 reg = <0x07a40000 0x1000>;
1884 status = "disabled"; 1857 status = "disabled";
1885 1858
1886 clocks = <&rpmcc RPM_ 1859 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1887 clock-names = "apb_pc 1860 clock-names = "apb_pclk", "atclk";
1888 1861
1889 cpu = <&CPU2>; 1862 cpu = <&CPU2>;
1890 1863
1891 out-ports { 1864 out-ports {
1892 port { 1865 port {
1893 etm2_ 1866 etm2_out: endpoint {
1894 1867 remote-endpoint =
1895 1868 <&apss_funnel_in2>;
1896 }; 1869 };
1897 }; 1870 };
1898 }; 1871 };
1899 }; 1872 };
1900 1873
1901 etm4: etm@7b40000 { 1874 etm4: etm@7b40000 {
1902 compatible = "arm,cor 1875 compatible = "arm,coresight-etm4x", "arm,primecell";
1903 reg = <0x07b40000 0x1 1876 reg = <0x07b40000 0x1000>;
1904 status = "disabled"; 1877 status = "disabled";
1905 1878
1906 clocks = <&rpmcc RPM_ 1879 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1907 clock-names = "apb_pc 1880 clock-names = "apb_pclk", "atclk";
1908 1881
1909 cpu = <&CPU3>; 1882 cpu = <&CPU3>;
1910 1883
1911 out-ports { 1884 out-ports {
1912 port { 1885 port {
1913 etm3_ 1886 etm3_out: endpoint {
1914 1887 remote-endpoint =
1915 1888 <&apss_funnel_in3>;
1916 }; 1889 };
1917 }; 1890 };
1918 }; 1891 };
1919 }; 1892 };
1920 1893
1921 funnel4: funnel@7b60000 { /* 1894 funnel4: funnel@7b60000 { /* APSS Funnel */
1922 compatible = "arm,cor 1895 compatible = "arm,coresight-etm4x", "arm,primecell";
1923 reg = <0x07b60000 0x1 1896 reg = <0x07b60000 0x1000>;
1924 status = "disabled"; 1897 status = "disabled";
1925 1898
1926 clocks = <&rpmcc RPM_ 1899 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1927 clock-names = "apb_pc 1900 clock-names = "apb_pclk", "atclk";
1928 1901
1929 out-ports { 1902 out-ports {
1930 port { 1903 port {
1931 apss_ 1904 apss_funnel_out: endpoint {
1932 1905 remote-endpoint =
1933 1906 <&apss_merge_funnel_in>;
1934 }; 1907 };
1935 }; 1908 };
1936 }; 1909 };
1937 1910
1938 in-ports { 1911 in-ports {
1939 #address-cell 1912 #address-cells = <1>;
1940 #size-cells = 1913 #size-cells = <0>;
1941 1914
1942 port@0 { 1915 port@0 {
1943 reg = 1916 reg = <0>;
1944 apss_ 1917 apss_funnel_in0: endpoint {
1945 1918 remote-endpoint =
1946 1919 <&etm0_out>;
1947 }; 1920 };
1948 }; 1921 };
1949 1922
1950 port@1 { 1923 port@1 {
1951 reg = 1924 reg = <1>;
1952 apss_ 1925 apss_funnel_in1: endpoint {
1953 1926 remote-endpoint =
1954 1927 <&etm1_out>;
1955 }; 1928 };
1956 }; 1929 };
1957 1930
1958 port@2 { 1931 port@2 {
1959 reg = 1932 reg = <2>;
1960 apss_ 1933 apss_funnel_in2: endpoint {
1961 1934 remote-endpoint =
1962 1935 <&etm2_out>;
1963 }; 1936 };
1964 }; 1937 };
1965 1938
1966 port@3 { 1939 port@3 {
1967 reg = 1940 reg = <3>;
1968 apss_ 1941 apss_funnel_in3: endpoint {
1969 1942 remote-endpoint =
1970 1943 <&etm3_out>;
1971 }; 1944 };
1972 }; 1945 };
1973 1946
1974 port@4 { 1947 port@4 {
1975 reg = 1948 reg = <4>;
1976 apss_ 1949 apss_funnel_in4: endpoint {
1977 1950 remote-endpoint =
1978 1951 <&etm4_out>;
1979 }; 1952 };
1980 }; 1953 };
1981 1954
1982 port@5 { 1955 port@5 {
1983 reg = 1956 reg = <5>;
1984 apss_ 1957 apss_funnel_in5: endpoint {
1985 1958 remote-endpoint =
1986 1959 <&etm5_out>;
1987 }; 1960 };
1988 }; 1961 };
1989 1962
1990 port@6 { 1963 port@6 {
1991 reg = 1964 reg = <6>;
1992 apss_ 1965 apss_funnel_in6: endpoint {
1993 1966 remote-endpoint =
1994 1967 <&etm6_out>;
1995 }; 1968 };
1996 }; 1969 };
1997 1970
1998 port@7 { 1971 port@7 {
1999 reg = 1972 reg = <7>;
2000 apss_ 1973 apss_funnel_in7: endpoint {
2001 1974 remote-endpoint =
2002 1975 <&etm7_out>;
2003 }; 1976 };
2004 }; 1977 };
2005 }; 1978 };
2006 }; 1979 };
2007 1980
2008 funnel5: funnel@7b70000 { 1981 funnel5: funnel@7b70000 {
2009 compatible = "arm,cor 1982 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2010 reg = <0x07b70000 0x1 1983 reg = <0x07b70000 0x1000>;
2011 status = "disabled"; 1984 status = "disabled";
2012 1985
2013 clocks = <&rpmcc RPM_ 1986 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2014 clock-names = "apb_pc 1987 clock-names = "apb_pclk", "atclk";
2015 1988
2016 out-ports { 1989 out-ports {
2017 port { 1990 port {
2018 apss_ 1991 apss_merge_funnel_out: endpoint {
2019 1992 remote-endpoint =
2020 1993 <&funnel1_in6>;
2021 }; 1994 };
2022 }; 1995 };
2023 }; 1996 };
2024 1997
2025 in-ports { 1998 in-ports {
2026 port { 1999 port {
2027 apss_ 2000 apss_merge_funnel_in: endpoint {
2028 2001 remote-endpoint =
2029 2002 <&apss_funnel_out>;
2030 }; 2003 };
2031 }; 2004 };
2032 }; 2005 };
2033 }; 2006 };
2034 2007
2035 etm5: etm@7c40000 { 2008 etm5: etm@7c40000 {
2036 compatible = "arm,cor 2009 compatible = "arm,coresight-etm4x", "arm,primecell";
2037 reg = <0x07c40000 0x1 2010 reg = <0x07c40000 0x1000>;
2038 status = "disabled"; 2011 status = "disabled";
2039 2012
2040 clocks = <&rpmcc RPM_ 2013 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2041 clock-names = "apb_pc 2014 clock-names = "apb_pclk", "atclk";
2042 2015
2043 cpu = <&CPU4>; 2016 cpu = <&CPU4>;
2044 2017
2045 out-ports { 2018 out-ports {
2046 port { 2019 port {
2047 etm4_ 2020 etm4_out: endpoint {
2048 2021 remote-endpoint = <&apss_funnel_in4>;
2049 }; 2022 };
2050 }; 2023 };
2051 }; 2024 };
2052 }; 2025 };
2053 2026
2054 etm6: etm@7d40000 { 2027 etm6: etm@7d40000 {
2055 compatible = "arm,cor 2028 compatible = "arm,coresight-etm4x", "arm,primecell";
2056 reg = <0x07d40000 0x1 2029 reg = <0x07d40000 0x1000>;
2057 status = "disabled"; 2030 status = "disabled";
2058 2031
2059 clocks = <&rpmcc RPM_ 2032 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2060 clock-names = "apb_pc 2033 clock-names = "apb_pclk", "atclk";
2061 2034
2062 cpu = <&CPU5>; 2035 cpu = <&CPU5>;
2063 2036
2064 out-ports { 2037 out-ports {
2065 port { 2038 port {
2066 etm5_ 2039 etm5_out: endpoint {
2067 2040 remote-endpoint = <&apss_funnel_in5>;
2068 }; 2041 };
2069 }; 2042 };
2070 }; 2043 };
2071 }; 2044 };
2072 2045
2073 etm7: etm@7e40000 { 2046 etm7: etm@7e40000 {
2074 compatible = "arm,cor 2047 compatible = "arm,coresight-etm4x", "arm,primecell";
2075 reg = <0x07e40000 0x1 2048 reg = <0x07e40000 0x1000>;
2076 status = "disabled"; 2049 status = "disabled";
2077 2050
2078 clocks = <&rpmcc RPM_ 2051 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2079 clock-names = "apb_pc 2052 clock-names = "apb_pclk", "atclk";
2080 2053
2081 cpu = <&CPU6>; 2054 cpu = <&CPU6>;
2082 2055
2083 out-ports { 2056 out-ports {
2084 port { 2057 port {
2085 etm6_ 2058 etm6_out: endpoint {
2086 2059 remote-endpoint = <&apss_funnel_in6>;
2087 }; 2060 };
2088 }; 2061 };
2089 }; 2062 };
2090 }; 2063 };
2091 2064
2092 etm8: etm@7f40000 { 2065 etm8: etm@7f40000 {
2093 compatible = "arm,cor 2066 compatible = "arm,coresight-etm4x", "arm,primecell";
2094 reg = <0x07f40000 0x1 2067 reg = <0x07f40000 0x1000>;
2095 status = "disabled"; 2068 status = "disabled";
2096 2069
2097 clocks = <&rpmcc RPM_ 2070 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2098 clock-names = "apb_pc 2071 clock-names = "apb_pclk", "atclk";
2099 2072
2100 cpu = <&CPU7>; 2073 cpu = <&CPU7>;
2101 2074
2102 out-ports { 2075 out-ports {
2103 port { 2076 port {
2104 etm7_ 2077 etm7_out: endpoint {
2105 2078 remote-endpoint = <&apss_funnel_in7>;
2106 }; 2079 };
2107 }; 2080 };
2108 }; 2081 };
2109 }; 2082 };
2110 2083
2111 sram@290000 { 2084 sram@290000 {
2112 compatible = "qcom,rp 2085 compatible = "qcom,rpm-stats";
2113 reg = <0x00290000 0x1 2086 reg = <0x00290000 0x10000>;
2114 }; 2087 };
2115 2088
2116 spmi_bus: spmi@800f000 { 2089 spmi_bus: spmi@800f000 {
2117 compatible = "qcom,sp 2090 compatible = "qcom,spmi-pmic-arb";
2118 reg = <0x0800f000 0x1 2091 reg = <0x0800f000 0x1000>,
2119 <0x08400000 0x1 2092 <0x08400000 0x1000000>,
2120 <0x09400000 0x1 2093 <0x09400000 0x1000000>,
2121 <0x0a400000 0x2 2094 <0x0a400000 0x220000>,
2122 <0x0800a000 0x3 2095 <0x0800a000 0x3000>;
2123 reg-names = "core", " 2096 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
2124 interrupt-names = "pe 2097 interrupt-names = "periph_irq";
2125 interrupts = <GIC_SPI 2098 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
2126 qcom,ee = <0>; 2099 qcom,ee = <0>;
2127 qcom,channel = <0>; 2100 qcom,channel = <0>;
2128 #address-cells = <2>; 2101 #address-cells = <2>;
2129 #size-cells = <0>; 2102 #size-cells = <0>;
2130 interrupt-controller; 2103 interrupt-controller;
2131 #interrupt-cells = <4 2104 #interrupt-cells = <4>;
2132 }; 2105 };
2133 2106
2134 usb3: usb@a8f8800 { 2107 usb3: usb@a8f8800 {
2135 compatible = "qcom,ms 2108 compatible = "qcom,msm8998-dwc3", "qcom,dwc3";
2136 reg = <0x0a8f8800 0x4 2109 reg = <0x0a8f8800 0x400>;
2137 status = "disabled"; 2110 status = "disabled";
2138 #address-cells = <1>; 2111 #address-cells = <1>;
2139 #size-cells = <1>; 2112 #size-cells = <1>;
2140 ranges; 2113 ranges;
2141 2114
2142 clocks = <&gcc GCC_CF 2115 clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>,
2143 <&gcc GCC_US 2116 <&gcc GCC_USB30_MASTER_CLK>,
2144 <&gcc GCC_AG 2117 <&gcc GCC_AGGRE1_USB3_AXI_CLK>,
2145 <&gcc GCC_US 2118 <&gcc GCC_USB30_SLEEP_CLK>,
2146 <&gcc GCC_US 2119 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
2147 clock-names = "cfg_no 2120 clock-names = "cfg_noc",
2148 "core", 2121 "core",
2149 "iface" 2122 "iface",
2150 "sleep" 2123 "sleep",
2151 "mock_u 2124 "mock_utmi";
2152 2125
2153 assigned-clocks = <&g 2126 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
2154 <&g 2127 <&gcc GCC_USB30_MASTER_CLK>;
2155 assigned-clock-rates 2128 assigned-clock-rates = <19200000>, <120000000>;
2156 2129
2157 interrupts = <GIC_SPI 2130 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
2158 <GIC_SPI 2131 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
2159 <GIC_SPI 2132 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
2160 interrupt-names = "pw 2133 interrupt-names = "pwr_event",
2161 "qu 2134 "qusb2_phy",
2162 "ss 2135 "ss_phy_irq";
2163 2136
2164 power-domains = <&gcc 2137 power-domains = <&gcc USB_30_GDSC>;
2165 2138
2166 resets = <&gcc GCC_US 2139 resets = <&gcc GCC_USB_30_BCR>;
2167 2140
2168 usb3_dwc3: usb@a80000 2141 usb3_dwc3: usb@a800000 {
2169 compatible = 2142 compatible = "snps,dwc3";
2170 reg = <0x0a80 2143 reg = <0x0a800000 0xcd00>;
2171 interrupts = 2144 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
2172 snps,dis_u2_s 2145 snps,dis_u2_susphy_quirk;
2173 snps,dis_enbl 2146 snps,dis_enblslpm_quirk;
2174 snps,parkmode 2147 snps,parkmode-disable-ss-quirk;
2175 phys = <&qusb 2148 phys = <&qusb2phy>, <&usb3phy>;
2176 phy-names = " 2149 phy-names = "usb2-phy", "usb3-phy";
2177 snps,has-lpm- 2150 snps,has-lpm-erratum;
2178 snps,hird-thr 2151 snps,hird-threshold = /bits/ 8 <0x10>;
2179 }; 2152 };
2180 }; 2153 };
2181 2154
2182 usb3phy: phy@c010000 { 2155 usb3phy: phy@c010000 {
2183 compatible = "qcom,ms 2156 compatible = "qcom,msm8998-qmp-usb3-phy";
2184 reg = <0x0c010000 0x1 2157 reg = <0x0c010000 0x1000>;
2185 2158
2186 clocks = <&gcc GCC_US 2159 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
2187 <&gcc GCC_US 2160 <&gcc GCC_USB3_CLKREF_CLK>,
2188 <&gcc GCC_US 2161 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2189 <&gcc GCC_US 2162 <&gcc GCC_USB3_PHY_PIPE_CLK>;
2190 clock-names = "aux", 2163 clock-names = "aux",
2191 "ref", 2164 "ref",
2192 "cfg_ah 2165 "cfg_ahb",
2193 "pipe"; 2166 "pipe";
2194 clock-output-names = 2167 clock-output-names = "usb3_phy_pipe_clk_src";
2195 #clock-cells = <0>; 2168 #clock-cells = <0>;
2196 #phy-cells = <0>; 2169 #phy-cells = <0>;
2197 2170
2198 resets = <&gcc GCC_US 2171 resets = <&gcc GCC_USB3_PHY_BCR>,
2199 <&gcc GCC_US 2172 <&gcc GCC_USB3PHY_PHY_BCR>;
2200 reset-names = "phy", 2173 reset-names = "phy",
2201 "phy_ph 2174 "phy_phy";
2202 2175
2203 qcom,tcsr-reg = <&tcs 2176 qcom,tcsr-reg = <&tcsr_regs_2 0xb244>;
2204 2177
2205 status = "disabled"; 2178 status = "disabled";
2206 }; 2179 };
2207 2180
2208 qusb2phy: phy@c012000 { 2181 qusb2phy: phy@c012000 {
2209 compatible = "qcom,ms 2182 compatible = "qcom,msm8998-qusb2-phy";
2210 reg = <0x0c012000 0x2 2183 reg = <0x0c012000 0x2a8>;
2211 status = "disabled"; 2184 status = "disabled";
2212 #phy-cells = <0>; 2185 #phy-cells = <0>;
2213 2186
2214 clocks = <&gcc GCC_US 2187 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2215 <&gcc GCC_RX 2188 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
2216 clock-names = "cfg_ah 2189 clock-names = "cfg_ahb", "ref";
2217 2190
2218 resets = <&gcc GCC_QU 2191 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2219 2192
2220 nvmem-cells = <&qusb2 2193 nvmem-cells = <&qusb2_hstx_trim>;
2221 }; 2194 };
2222 2195
2223 sdhc2: mmc@c0a4900 { 2196 sdhc2: mmc@c0a4900 {
2224 compatible = "qcom,ms 2197 compatible = "qcom,msm8998-sdhci", "qcom,sdhci-msm-v4";
2225 reg = <0x0c0a4900 0x3 2198 reg = <0x0c0a4900 0x314>, <0x0c0a4000 0x800>;
2226 reg-names = "hc", "co 2199 reg-names = "hc", "core";
2227 2200
2228 interrupts = <GIC_SPI 2201 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
2229 <GIC_SPI 2202 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
2230 interrupt-names = "hc 2203 interrupt-names = "hc_irq", "pwr_irq";
2231 2204
2232 clock-names = "iface" 2205 clock-names = "iface", "core", "xo";
2233 clocks = <&gcc GCC_SD 2206 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2234 <&gcc GCC_SD 2207 <&gcc GCC_SDCC2_APPS_CLK>,
2235 <&rpmcc RPM_ 2208 <&rpmcc RPM_SMD_XO_CLK_SRC>;
2236 bus-width = <4>; 2209 bus-width = <4>;
2237 status = "disabled"; 2210 status = "disabled";
2238 }; 2211 };
2239 2212
2240 blsp1_dma: dma-controller@c14 2213 blsp1_dma: dma-controller@c144000 {
2241 compatible = "qcom,ba 2214 compatible = "qcom,bam-v1.7.0";
2242 reg = <0x0c144000 0x2 2215 reg = <0x0c144000 0x25000>;
2243 interrupts = <GIC_SPI 2216 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
2244 clocks = <&gcc GCC_BL 2217 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
2245 clock-names = "bam_cl 2218 clock-names = "bam_clk";
2246 #dma-cells = <1>; 2219 #dma-cells = <1>;
2247 qcom,ee = <0>; 2220 qcom,ee = <0>;
2248 qcom,controlled-remot 2221 qcom,controlled-remotely;
2249 num-channels = <18>; 2222 num-channels = <18>;
2250 qcom,num-ees = <4>; 2223 qcom,num-ees = <4>;
2251 }; 2224 };
2252 2225
2253 blsp1_uart3: serial@c171000 { 2226 blsp1_uart3: serial@c171000 {
2254 compatible = "qcom,ms 2227 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2255 reg = <0x0c171000 0x1 2228 reg = <0x0c171000 0x1000>;
2256 interrupts = <GIC_SPI 2229 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
2257 clocks = <&gcc GCC_BL 2230 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
2258 <&gcc GCC_BL 2231 <&gcc GCC_BLSP1_AHB_CLK>;
2259 clock-names = "core", 2232 clock-names = "core", "iface";
2260 dmas = <&blsp1_dma 4> 2233 dmas = <&blsp1_dma 4>, <&blsp1_dma 5>;
2261 dma-names = "tx", "rx 2234 dma-names = "tx", "rx";
2262 pinctrl-names = "defa 2235 pinctrl-names = "default";
2263 pinctrl-0 = <&blsp1_u 2236 pinctrl-0 = <&blsp1_uart3_on>;
2264 status = "disabled"; 2237 status = "disabled";
2265 }; 2238 };
2266 2239
2267 blsp1_i2c1: i2c@c175000 { 2240 blsp1_i2c1: i2c@c175000 {
2268 compatible = "qcom,i2 2241 compatible = "qcom,i2c-qup-v2.2.1";
2269 reg = <0x0c175000 0x6 2242 reg = <0x0c175000 0x600>;
2270 interrupts = <GIC_SPI 2243 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
2271 2244
2272 clocks = <&gcc GCC_BL 2245 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
2273 <&gcc GCC_BL 2246 <&gcc GCC_BLSP1_AHB_CLK>;
2274 clock-names = "core", 2247 clock-names = "core", "iface";
2275 dmas = <&blsp1_dma 6> 2248 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>;
2276 dma-names = "tx", "rx 2249 dma-names = "tx", "rx";
2277 pinctrl-names = "defa 2250 pinctrl-names = "default", "sleep";
2278 pinctrl-0 = <&blsp1_i 2251 pinctrl-0 = <&blsp1_i2c1_default>;
2279 pinctrl-1 = <&blsp1_i 2252 pinctrl-1 = <&blsp1_i2c1_sleep>;
2280 clock-frequency = <40 2253 clock-frequency = <400000>;
2281 2254
2282 status = "disabled"; 2255 status = "disabled";
2283 #address-cells = <1>; 2256 #address-cells = <1>;
2284 #size-cells = <0>; 2257 #size-cells = <0>;
2285 }; 2258 };
2286 2259
2287 blsp1_i2c2: i2c@c176000 { 2260 blsp1_i2c2: i2c@c176000 {
2288 compatible = "qcom,i2 2261 compatible = "qcom,i2c-qup-v2.2.1";
2289 reg = <0x0c176000 0x6 2262 reg = <0x0c176000 0x600>;
2290 interrupts = <GIC_SPI 2263 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
2291 2264
2292 clocks = <&gcc GCC_BL 2265 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
2293 <&gcc GCC_BL 2266 <&gcc GCC_BLSP1_AHB_CLK>;
2294 clock-names = "core", 2267 clock-names = "core", "iface";
2295 dmas = <&blsp1_dma 8> 2268 dmas = <&blsp1_dma 8>, <&blsp1_dma 9>;
2296 dma-names = "tx", "rx 2269 dma-names = "tx", "rx";
2297 pinctrl-names = "defa 2270 pinctrl-names = "default", "sleep";
2298 pinctrl-0 = <&blsp1_i 2271 pinctrl-0 = <&blsp1_i2c2_default>;
2299 pinctrl-1 = <&blsp1_i 2272 pinctrl-1 = <&blsp1_i2c2_sleep>;
2300 clock-frequency = <40 2273 clock-frequency = <400000>;
2301 2274
2302 status = "disabled"; 2275 status = "disabled";
2303 #address-cells = <1>; 2276 #address-cells = <1>;
2304 #size-cells = <0>; 2277 #size-cells = <0>;
2305 }; 2278 };
2306 2279
2307 blsp1_i2c3: i2c@c177000 { 2280 blsp1_i2c3: i2c@c177000 {
2308 compatible = "qcom,i2 2281 compatible = "qcom,i2c-qup-v2.2.1";
2309 reg = <0x0c177000 0x6 2282 reg = <0x0c177000 0x600>;
2310 interrupts = <GIC_SPI 2283 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
2311 2284
2312 clocks = <&gcc GCC_BL 2285 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
2313 <&gcc GCC_BL 2286 <&gcc GCC_BLSP1_AHB_CLK>;
2314 clock-names = "core", 2287 clock-names = "core", "iface";
2315 dmas = <&blsp1_dma 10 2288 dmas = <&blsp1_dma 10>, <&blsp1_dma 11>;
2316 dma-names = "tx", "rx 2289 dma-names = "tx", "rx";
2317 pinctrl-names = "defa 2290 pinctrl-names = "default", "sleep";
2318 pinctrl-0 = <&blsp1_i 2291 pinctrl-0 = <&blsp1_i2c3_default>;
2319 pinctrl-1 = <&blsp1_i 2292 pinctrl-1 = <&blsp1_i2c3_sleep>;
2320 clock-frequency = <40 2293 clock-frequency = <400000>;
2321 2294
2322 status = "disabled"; 2295 status = "disabled";
2323 #address-cells = <1>; 2296 #address-cells = <1>;
2324 #size-cells = <0>; 2297 #size-cells = <0>;
2325 }; 2298 };
2326 2299
2327 blsp1_i2c4: i2c@c178000 { 2300 blsp1_i2c4: i2c@c178000 {
2328 compatible = "qcom,i2 2301 compatible = "qcom,i2c-qup-v2.2.1";
2329 reg = <0x0c178000 0x6 2302 reg = <0x0c178000 0x600>;
2330 interrupts = <GIC_SPI 2303 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
2331 2304
2332 clocks = <&gcc GCC_BL 2305 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
2333 <&gcc GCC_BL 2306 <&gcc GCC_BLSP1_AHB_CLK>;
2334 clock-names = "core", 2307 clock-names = "core", "iface";
2335 dmas = <&blsp1_dma 12 2308 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
2336 dma-names = "tx", "rx 2309 dma-names = "tx", "rx";
2337 pinctrl-names = "defa 2310 pinctrl-names = "default", "sleep";
2338 pinctrl-0 = <&blsp1_i 2311 pinctrl-0 = <&blsp1_i2c4_default>;
2339 pinctrl-1 = <&blsp1_i 2312 pinctrl-1 = <&blsp1_i2c4_sleep>;
2340 clock-frequency = <40 2313 clock-frequency = <400000>;
2341 2314
2342 status = "disabled"; 2315 status = "disabled";
2343 #address-cells = <1>; 2316 #address-cells = <1>;
2344 #size-cells = <0>; 2317 #size-cells = <0>;
2345 }; 2318 };
2346 2319
2347 blsp1_i2c5: i2c@c179000 { 2320 blsp1_i2c5: i2c@c179000 {
2348 compatible = "qcom,i2 2321 compatible = "qcom,i2c-qup-v2.2.1";
2349 reg = <0x0c179000 0x6 2322 reg = <0x0c179000 0x600>;
2350 interrupts = <GIC_SPI 2323 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
2351 2324
2352 clocks = <&gcc GCC_BL 2325 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
2353 <&gcc GCC_BL 2326 <&gcc GCC_BLSP1_AHB_CLK>;
2354 clock-names = "core", 2327 clock-names = "core", "iface";
2355 dmas = <&blsp1_dma 14 2328 dmas = <&blsp1_dma 14>, <&blsp1_dma 15>;
2356 dma-names = "tx", "rx 2329 dma-names = "tx", "rx";
2357 pinctrl-names = "defa 2330 pinctrl-names = "default", "sleep";
2358 pinctrl-0 = <&blsp1_i 2331 pinctrl-0 = <&blsp1_i2c5_default>;
2359 pinctrl-1 = <&blsp1_i 2332 pinctrl-1 = <&blsp1_i2c5_sleep>;
2360 clock-frequency = <40 2333 clock-frequency = <400000>;
2361 2334
2362 status = "disabled"; 2335 status = "disabled";
2363 #address-cells = <1>; 2336 #address-cells = <1>;
2364 #size-cells = <0>; 2337 #size-cells = <0>;
2365 }; 2338 };
2366 2339
2367 blsp1_i2c6: i2c@c17a000 { 2340 blsp1_i2c6: i2c@c17a000 {
2368 compatible = "qcom,i2 2341 compatible = "qcom,i2c-qup-v2.2.1";
2369 reg = <0x0c17a000 0x6 2342 reg = <0x0c17a000 0x600>;
2370 interrupts = <GIC_SPI 2343 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
2371 2344
2372 clocks = <&gcc GCC_BL 2345 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
2373 <&gcc GCC_BL 2346 <&gcc GCC_BLSP1_AHB_CLK>;
2374 clock-names = "core", 2347 clock-names = "core", "iface";
2375 dmas = <&blsp1_dma 16 2348 dmas = <&blsp1_dma 16>, <&blsp1_dma 17>;
2376 dma-names = "tx", "rx 2349 dma-names = "tx", "rx";
2377 pinctrl-names = "defa 2350 pinctrl-names = "default", "sleep";
2378 pinctrl-0 = <&blsp1_i 2351 pinctrl-0 = <&blsp1_i2c6_default>;
2379 pinctrl-1 = <&blsp1_i 2352 pinctrl-1 = <&blsp1_i2c6_sleep>;
2380 clock-frequency = <40 2353 clock-frequency = <400000>;
2381 2354
2382 status = "disabled"; 2355 status = "disabled";
2383 #address-cells = <1>; 2356 #address-cells = <1>;
2384 #size-cells = <0>; 2357 #size-cells = <0>;
2385 }; 2358 };
2386 2359
2387 blsp1_spi1: spi@c175000 { 2360 blsp1_spi1: spi@c175000 {
2388 compatible = "qcom,sp 2361 compatible = "qcom,spi-qup-v2.2.1";
2389 reg = <0x0c175000 0x6 2362 reg = <0x0c175000 0x600>;
2390 interrupts = <GIC_SPI 2363 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
2391 2364
2392 clocks = <&gcc GCC_BL 2365 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
2393 <&gcc GCC_BL 2366 <&gcc GCC_BLSP1_AHB_CLK>;
2394 clock-names = "core", 2367 clock-names = "core", "iface";
2395 dmas = <&blsp1_dma 6> 2368 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>;
2396 dma-names = "tx", "rx 2369 dma-names = "tx", "rx";
2397 pinctrl-names = "defa 2370 pinctrl-names = "default";
2398 pinctrl-0 = <&blsp1_s 2371 pinctrl-0 = <&blsp1_spi1_default>;
2399 2372
2400 status = "disabled"; 2373 status = "disabled";
2401 #address-cells = <1>; 2374 #address-cells = <1>;
2402 #size-cells = <0>; 2375 #size-cells = <0>;
2403 }; 2376 };
2404 2377
2405 blsp1_spi2: spi@c176000 { 2378 blsp1_spi2: spi@c176000 {
2406 compatible = "qcom,sp 2379 compatible = "qcom,spi-qup-v2.2.1";
2407 reg = <0x0c176000 0x6 2380 reg = <0x0c176000 0x600>;
2408 interrupts = <GIC_SPI 2381 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
2409 2382
2410 clocks = <&gcc GCC_BL 2383 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
2411 <&gcc GCC_BL 2384 <&gcc GCC_BLSP1_AHB_CLK>;
2412 clock-names = "core", 2385 clock-names = "core", "iface";
2413 dmas = <&blsp1_dma 8> 2386 dmas = <&blsp1_dma 8>, <&blsp1_dma 9>;
2414 dma-names = "tx", "rx 2387 dma-names = "tx", "rx";
2415 pinctrl-names = "defa 2388 pinctrl-names = "default";
2416 pinctrl-0 = <&blsp1_s 2389 pinctrl-0 = <&blsp1_spi2_default>;
2417 2390
2418 status = "disabled"; 2391 status = "disabled";
2419 #address-cells = <1>; 2392 #address-cells = <1>;
2420 #size-cells = <0>; 2393 #size-cells = <0>;
2421 }; 2394 };
2422 2395
2423 blsp1_spi3: spi@c177000 { 2396 blsp1_spi3: spi@c177000 {
2424 compatible = "qcom,sp 2397 compatible = "qcom,spi-qup-v2.2.1";
2425 reg = <0x0c177000 0x6 2398 reg = <0x0c177000 0x600>;
2426 interrupts = <GIC_SPI 2399 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
2427 2400
2428 clocks = <&gcc GCC_BL 2401 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
2429 <&gcc GCC_BL 2402 <&gcc GCC_BLSP1_AHB_CLK>;
2430 clock-names = "core", 2403 clock-names = "core", "iface";
2431 dmas = <&blsp1_dma 10 2404 dmas = <&blsp1_dma 10>, <&blsp1_dma 11>;
2432 dma-names = "tx", "rx 2405 dma-names = "tx", "rx";
2433 pinctrl-names = "defa 2406 pinctrl-names = "default";
2434 pinctrl-0 = <&blsp1_s 2407 pinctrl-0 = <&blsp1_spi3_default>;
2435 2408
2436 status = "disabled"; 2409 status = "disabled";
2437 #address-cells = <1>; 2410 #address-cells = <1>;
2438 #size-cells = <0>; 2411 #size-cells = <0>;
2439 }; 2412 };
2440 2413
2441 blsp1_spi4: spi@c178000 { 2414 blsp1_spi4: spi@c178000 {
2442 compatible = "qcom,sp 2415 compatible = "qcom,spi-qup-v2.2.1";
2443 reg = <0x0c178000 0x6 2416 reg = <0x0c178000 0x600>;
2444 interrupts = <GIC_SPI 2417 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
2445 2418
2446 clocks = <&gcc GCC_BL 2419 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
2447 <&gcc GCC_BL 2420 <&gcc GCC_BLSP1_AHB_CLK>;
2448 clock-names = "core", 2421 clock-names = "core", "iface";
2449 dmas = <&blsp1_dma 12 2422 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
2450 dma-names = "tx", "rx 2423 dma-names = "tx", "rx";
2451 pinctrl-names = "defa 2424 pinctrl-names = "default";
2452 pinctrl-0 = <&blsp1_s 2425 pinctrl-0 = <&blsp1_spi4_default>;
2453 2426
2454 status = "disabled"; 2427 status = "disabled";
2455 #address-cells = <1>; 2428 #address-cells = <1>;
2456 #size-cells = <0>; 2429 #size-cells = <0>;
2457 }; 2430 };
2458 2431
2459 blsp1_spi5: spi@c179000 { 2432 blsp1_spi5: spi@c179000 {
2460 compatible = "qcom,sp 2433 compatible = "qcom,spi-qup-v2.2.1";
2461 reg = <0x0c179000 0x6 2434 reg = <0x0c179000 0x600>;
2462 interrupts = <GIC_SPI 2435 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
2463 2436
2464 clocks = <&gcc GCC_BL 2437 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
2465 <&gcc GCC_BL 2438 <&gcc GCC_BLSP1_AHB_CLK>;
2466 clock-names = "core", 2439 clock-names = "core", "iface";
2467 dmas = <&blsp1_dma 14 2440 dmas = <&blsp1_dma 14>, <&blsp1_dma 15>;
2468 dma-names = "tx", "rx 2441 dma-names = "tx", "rx";
2469 pinctrl-names = "defa 2442 pinctrl-names = "default";
2470 pinctrl-0 = <&blsp1_s 2443 pinctrl-0 = <&blsp1_spi5_default>;
2471 2444
2472 status = "disabled"; 2445 status = "disabled";
2473 #address-cells = <1>; 2446 #address-cells = <1>;
2474 #size-cells = <0>; 2447 #size-cells = <0>;
2475 }; 2448 };
2476 2449
2477 blsp1_spi6: spi@c17a000 { 2450 blsp1_spi6: spi@c17a000 {
2478 compatible = "qcom,sp 2451 compatible = "qcom,spi-qup-v2.2.1";
2479 reg = <0x0c17a000 0x6 2452 reg = <0x0c17a000 0x600>;
2480 interrupts = <GIC_SPI 2453 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
2481 2454
2482 clocks = <&gcc GCC_BL 2455 clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
2483 <&gcc GCC_BL 2456 <&gcc GCC_BLSP1_AHB_CLK>;
2484 clock-names = "core", 2457 clock-names = "core", "iface";
2485 dmas = <&blsp1_dma 16 2458 dmas = <&blsp1_dma 16>, <&blsp1_dma 17>;
2486 dma-names = "tx", "rx 2459 dma-names = "tx", "rx";
2487 pinctrl-names = "defa 2460 pinctrl-names = "default";
2488 pinctrl-0 = <&blsp1_s 2461 pinctrl-0 = <&blsp1_spi6_default>;
2489 2462
2490 status = "disabled"; 2463 status = "disabled";
2491 #address-cells = <1>; 2464 #address-cells = <1>;
2492 #size-cells = <0>; 2465 #size-cells = <0>;
2493 }; 2466 };
2494 2467
2495 blsp2_dma: dma-controller@c18 2468 blsp2_dma: dma-controller@c184000 {
2496 compatible = "qcom,ba 2469 compatible = "qcom,bam-v1.7.0";
2497 reg = <0x0c184000 0x2 2470 reg = <0x0c184000 0x25000>;
2498 interrupts = <GIC_SPI 2471 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
2499 clocks = <&gcc GCC_BL 2472 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
2500 clock-names = "bam_cl 2473 clock-names = "bam_clk";
2501 #dma-cells = <1>; 2474 #dma-cells = <1>;
2502 qcom,ee = <0>; 2475 qcom,ee = <0>;
2503 qcom,controlled-remot 2476 qcom,controlled-remotely;
2504 num-channels = <18>; 2477 num-channels = <18>;
2505 qcom,num-ees = <4>; 2478 qcom,num-ees = <4>;
2506 }; 2479 };
2507 2480
2508 blsp2_uart1: serial@c1b0000 { 2481 blsp2_uart1: serial@c1b0000 {
2509 compatible = "qcom,ms 2482 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2510 reg = <0x0c1b0000 0x1 2483 reg = <0x0c1b0000 0x1000>;
2511 interrupts = <GIC_SPI 2484 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
2512 clocks = <&gcc GCC_BL 2485 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
2513 <&gcc GCC_BL 2486 <&gcc GCC_BLSP2_AHB_CLK>;
2514 clock-names = "core", 2487 clock-names = "core", "iface";
2515 status = "disabled"; 2488 status = "disabled";
2516 }; 2489 };
2517 2490
2518 blsp2_i2c1: i2c@c1b5000 { 2491 blsp2_i2c1: i2c@c1b5000 {
2519 compatible = "qcom,i2 2492 compatible = "qcom,i2c-qup-v2.2.1";
2520 reg = <0x0c1b5000 0x6 2493 reg = <0x0c1b5000 0x600>;
2521 interrupts = <GIC_SPI 2494 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
2522 2495
2523 clocks = <&gcc GCC_BL 2496 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
2524 <&gcc GCC_BL 2497 <&gcc GCC_BLSP2_AHB_CLK>;
2525 clock-names = "core", 2498 clock-names = "core", "iface";
2526 dmas = <&blsp2_dma 6> 2499 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>;
2527 dma-names = "tx", "rx 2500 dma-names = "tx", "rx";
2528 pinctrl-names = "defa 2501 pinctrl-names = "default", "sleep";
2529 pinctrl-0 = <&blsp2_i 2502 pinctrl-0 = <&blsp2_i2c1_default>;
2530 pinctrl-1 = <&blsp2_i 2503 pinctrl-1 = <&blsp2_i2c1_sleep>;
2531 clock-frequency = <40 2504 clock-frequency = <400000>;
2532 2505
2533 status = "disabled"; 2506 status = "disabled";
2534 #address-cells = <1>; 2507 #address-cells = <1>;
2535 #size-cells = <0>; 2508 #size-cells = <0>;
2536 }; 2509 };
2537 2510
2538 blsp2_i2c2: i2c@c1b6000 { 2511 blsp2_i2c2: i2c@c1b6000 {
2539 compatible = "qcom,i2 2512 compatible = "qcom,i2c-qup-v2.2.1";
2540 reg = <0x0c1b6000 0x6 2513 reg = <0x0c1b6000 0x600>;
2541 interrupts = <GIC_SPI 2514 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
2542 2515
2543 clocks = <&gcc GCC_BL 2516 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
2544 <&gcc GCC_BL 2517 <&gcc GCC_BLSP2_AHB_CLK>;
2545 clock-names = "core", 2518 clock-names = "core", "iface";
2546 dmas = <&blsp2_dma 8> 2519 dmas = <&blsp2_dma 8>, <&blsp2_dma 9>;
2547 dma-names = "tx", "rx 2520 dma-names = "tx", "rx";
2548 pinctrl-names = "defa 2521 pinctrl-names = "default", "sleep";
2549 pinctrl-0 = <&blsp2_i 2522 pinctrl-0 = <&blsp2_i2c2_default>;
2550 pinctrl-1 = <&blsp2_i 2523 pinctrl-1 = <&blsp2_i2c2_sleep>;
2551 clock-frequency = <40 2524 clock-frequency = <400000>;
2552 2525
2553 status = "disabled"; 2526 status = "disabled";
2554 #address-cells = <1>; 2527 #address-cells = <1>;
2555 #size-cells = <0>; 2528 #size-cells = <0>;
2556 }; 2529 };
2557 2530
2558 blsp2_i2c3: i2c@c1b7000 { 2531 blsp2_i2c3: i2c@c1b7000 {
2559 compatible = "qcom,i2 2532 compatible = "qcom,i2c-qup-v2.2.1";
2560 reg = <0x0c1b7000 0x6 2533 reg = <0x0c1b7000 0x600>;
2561 interrupts = <GIC_SPI 2534 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
2562 2535
2563 clocks = <&gcc GCC_BL 2536 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
2564 <&gcc GCC_BL 2537 <&gcc GCC_BLSP2_AHB_CLK>;
2565 clock-names = "core", 2538 clock-names = "core", "iface";
2566 dmas = <&blsp2_dma 10 2539 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>;
2567 dma-names = "tx", "rx 2540 dma-names = "tx", "rx";
2568 pinctrl-names = "defa 2541 pinctrl-names = "default", "sleep";
2569 pinctrl-0 = <&blsp2_i 2542 pinctrl-0 = <&blsp2_i2c3_default>;
2570 pinctrl-1 = <&blsp2_i 2543 pinctrl-1 = <&blsp2_i2c3_sleep>;
2571 clock-frequency = <40 2544 clock-frequency = <400000>;
2572 2545
2573 status = "disabled"; 2546 status = "disabled";
2574 #address-cells = <1>; 2547 #address-cells = <1>;
2575 #size-cells = <0>; 2548 #size-cells = <0>;
2576 }; 2549 };
2577 2550
2578 blsp2_i2c4: i2c@c1b8000 { 2551 blsp2_i2c4: i2c@c1b8000 {
2579 compatible = "qcom,i2 2552 compatible = "qcom,i2c-qup-v2.2.1";
2580 reg = <0x0c1b8000 0x6 2553 reg = <0x0c1b8000 0x600>;
2581 interrupts = <GIC_SPI 2554 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
2582 2555
2583 clocks = <&gcc GCC_BL 2556 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>,
2584 <&gcc GCC_BL 2557 <&gcc GCC_BLSP2_AHB_CLK>;
2585 clock-names = "core", 2558 clock-names = "core", "iface";
2586 dmas = <&blsp2_dma 12 2559 dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
2587 dma-names = "tx", "rx 2560 dma-names = "tx", "rx";
2588 pinctrl-names = "defa 2561 pinctrl-names = "default", "sleep";
2589 pinctrl-0 = <&blsp2_i 2562 pinctrl-0 = <&blsp2_i2c4_default>;
2590 pinctrl-1 = <&blsp2_i 2563 pinctrl-1 = <&blsp2_i2c4_sleep>;
2591 clock-frequency = <40 2564 clock-frequency = <400000>;
2592 2565
2593 status = "disabled"; 2566 status = "disabled";
2594 #address-cells = <1>; 2567 #address-cells = <1>;
2595 #size-cells = <0>; 2568 #size-cells = <0>;
2596 }; 2569 };
2597 2570
2598 blsp2_i2c5: i2c@c1b9000 { 2571 blsp2_i2c5: i2c@c1b9000 {
2599 compatible = "qcom,i2 2572 compatible = "qcom,i2c-qup-v2.2.1";
2600 reg = <0x0c1b9000 0x6 2573 reg = <0x0c1b9000 0x600>;
2601 interrupts = <GIC_SPI 2574 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
2602 2575
2603 clocks = <&gcc GCC_BL 2576 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,
2604 <&gcc GCC_BL 2577 <&gcc GCC_BLSP2_AHB_CLK>;
2605 clock-names = "core", 2578 clock-names = "core", "iface";
2606 dmas = <&blsp2_dma 14 2579 dmas = <&blsp2_dma 14>, <&blsp2_dma 15>;
2607 dma-names = "tx", "rx 2580 dma-names = "tx", "rx";
2608 pinctrl-names = "defa 2581 pinctrl-names = "default", "sleep";
2609 pinctrl-0 = <&blsp2_i 2582 pinctrl-0 = <&blsp2_i2c5_default>;
2610 pinctrl-1 = <&blsp2_i 2583 pinctrl-1 = <&blsp2_i2c5_sleep>;
2611 clock-frequency = <40 2584 clock-frequency = <400000>;
2612 2585
2613 status = "disabled"; 2586 status = "disabled";
2614 #address-cells = <1>; 2587 #address-cells = <1>;
2615 #size-cells = <0>; 2588 #size-cells = <0>;
2616 }; 2589 };
2617 2590
2618 blsp2_i2c6: i2c@c1ba000 { 2591 blsp2_i2c6: i2c@c1ba000 {
2619 compatible = "qcom,i2 2592 compatible = "qcom,i2c-qup-v2.2.1";
2620 reg = <0x0c1ba000 0x6 2593 reg = <0x0c1ba000 0x600>;
2621 interrupts = <GIC_SPI 2594 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
2622 2595
2623 clocks = <&gcc GCC_BL 2596 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>,
2624 <&gcc GCC_BL 2597 <&gcc GCC_BLSP2_AHB_CLK>;
2625 clock-names = "core", 2598 clock-names = "core", "iface";
2626 dmas = <&blsp2_dma 16 2599 dmas = <&blsp2_dma 16>, <&blsp2_dma 17>;
2627 dma-names = "tx", "rx 2600 dma-names = "tx", "rx";
2628 pinctrl-names = "defa 2601 pinctrl-names = "default", "sleep";
2629 pinctrl-0 = <&blsp2_i 2602 pinctrl-0 = <&blsp2_i2c6_default>;
2630 pinctrl-1 = <&blsp2_i 2603 pinctrl-1 = <&blsp2_i2c6_sleep>;
2631 clock-frequency = <40 2604 clock-frequency = <400000>;
2632 2605
2633 status = "disabled"; 2606 status = "disabled";
2634 #address-cells = <1>; 2607 #address-cells = <1>;
2635 #size-cells = <0>; 2608 #size-cells = <0>;
2636 }; 2609 };
2637 2610
2638 blsp2_spi1: spi@c1b5000 { 2611 blsp2_spi1: spi@c1b5000 {
2639 compatible = "qcom,sp 2612 compatible = "qcom,spi-qup-v2.2.1";
2640 reg = <0x0c1b5000 0x6 2613 reg = <0x0c1b5000 0x600>;
2641 interrupts = <GIC_SPI 2614 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
2642 2615
2643 clocks = <&gcc GCC_BL 2616 clocks = <&gcc GCC_BLSP2_QUP1_SPI_APPS_CLK>,
2644 <&gcc GCC_BL 2617 <&gcc GCC_BLSP2_AHB_CLK>;
2645 clock-names = "core", 2618 clock-names = "core", "iface";
2646 dmas = <&blsp2_dma 6> 2619 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>;
2647 dma-names = "tx", "rx 2620 dma-names = "tx", "rx";
2648 pinctrl-names = "defa 2621 pinctrl-names = "default";
2649 pinctrl-0 = <&blsp2_s 2622 pinctrl-0 = <&blsp2_spi1_default>;
2650 2623
2651 status = "disabled"; 2624 status = "disabled";
2652 #address-cells = <1>; 2625 #address-cells = <1>;
2653 #size-cells = <0>; 2626 #size-cells = <0>;
2654 }; 2627 };
2655 2628
2656 blsp2_spi2: spi@c1b6000 { 2629 blsp2_spi2: spi@c1b6000 {
2657 compatible = "qcom,sp 2630 compatible = "qcom,spi-qup-v2.2.1";
2658 reg = <0x0c1b6000 0x6 2631 reg = <0x0c1b6000 0x600>;
2659 interrupts = <GIC_SPI 2632 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
2660 2633
2661 clocks = <&gcc GCC_BL 2634 clocks = <&gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>,
2662 <&gcc GCC_BL 2635 <&gcc GCC_BLSP2_AHB_CLK>;
2663 clock-names = "core", 2636 clock-names = "core", "iface";
2664 dmas = <&blsp2_dma 8> 2637 dmas = <&blsp2_dma 8>, <&blsp2_dma 9>;
2665 dma-names = "tx", "rx 2638 dma-names = "tx", "rx";
2666 pinctrl-names = "defa 2639 pinctrl-names = "default";
2667 pinctrl-0 = <&blsp2_s 2640 pinctrl-0 = <&blsp2_spi2_default>;
2668 2641
2669 status = "disabled"; 2642 status = "disabled";
2670 #address-cells = <1>; 2643 #address-cells = <1>;
2671 #size-cells = <0>; 2644 #size-cells = <0>;
2672 }; 2645 };
2673 2646
2674 blsp2_spi3: spi@c1b7000 { 2647 blsp2_spi3: spi@c1b7000 {
2675 compatible = "qcom,sp 2648 compatible = "qcom,spi-qup-v2.2.1";
2676 reg = <0x0c1b7000 0x6 2649 reg = <0x0c1b7000 0x600>;
2677 interrupts = <GIC_SPI 2650 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
2678 2651
2679 clocks = <&gcc GCC_BL 2652 clocks = <&gcc GCC_BLSP2_QUP3_SPI_APPS_CLK>,
2680 <&gcc GCC_BL 2653 <&gcc GCC_BLSP2_AHB_CLK>;
2681 clock-names = "core", 2654 clock-names = "core", "iface";
2682 dmas = <&blsp2_dma 10 2655 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>;
2683 dma-names = "tx", "rx 2656 dma-names = "tx", "rx";
2684 pinctrl-names = "defa 2657 pinctrl-names = "default";
2685 pinctrl-0 = <&blsp2_s 2658 pinctrl-0 = <&blsp2_spi3_default>;
2686 2659
2687 status = "disabled"; 2660 status = "disabled";
2688 #address-cells = <1>; 2661 #address-cells = <1>;
2689 #size-cells = <0>; 2662 #size-cells = <0>;
2690 }; 2663 };
2691 2664
2692 blsp2_spi4: spi@c1b8000 { 2665 blsp2_spi4: spi@c1b8000 {
2693 compatible = "qcom,sp 2666 compatible = "qcom,spi-qup-v2.2.1";
2694 reg = <0x0c1b8000 0x6 2667 reg = <0x0c1b8000 0x600>;
2695 interrupts = <GIC_SPI 2668 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
2696 2669
2697 clocks = <&gcc GCC_BL 2670 clocks = <&gcc GCC_BLSP2_QUP4_SPI_APPS_CLK>,
2698 <&gcc GCC_BL 2671 <&gcc GCC_BLSP2_AHB_CLK>;
2699 clock-names = "core", 2672 clock-names = "core", "iface";
2700 dmas = <&blsp2_dma 12 2673 dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
2701 dma-names = "tx", "rx 2674 dma-names = "tx", "rx";
2702 pinctrl-names = "defa 2675 pinctrl-names = "default";
2703 pinctrl-0 = <&blsp2_s 2676 pinctrl-0 = <&blsp2_spi4_default>;
2704 2677
2705 status = "disabled"; 2678 status = "disabled";
2706 #address-cells = <1>; 2679 #address-cells = <1>;
2707 #size-cells = <0>; 2680 #size-cells = <0>;
2708 }; 2681 };
2709 2682
2710 blsp2_spi5: spi@c1b9000 { 2683 blsp2_spi5: spi@c1b9000 {
2711 compatible = "qcom,sp 2684 compatible = "qcom,spi-qup-v2.2.1";
2712 reg = <0x0c1b9000 0x6 2685 reg = <0x0c1b9000 0x600>;
2713 interrupts = <GIC_SPI 2686 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
2714 2687
2715 clocks = <&gcc GCC_BL 2688 clocks = <&gcc GCC_BLSP2_QUP5_SPI_APPS_CLK>,
2716 <&gcc GCC_BL 2689 <&gcc GCC_BLSP2_AHB_CLK>;
2717 clock-names = "core", 2690 clock-names = "core", "iface";
2718 dmas = <&blsp2_dma 14 2691 dmas = <&blsp2_dma 14>, <&blsp2_dma 15>;
2719 dma-names = "tx", "rx 2692 dma-names = "tx", "rx";
2720 pinctrl-names = "defa 2693 pinctrl-names = "default";
2721 pinctrl-0 = <&blsp2_s 2694 pinctrl-0 = <&blsp2_spi5_default>;
2722 2695
2723 status = "disabled"; 2696 status = "disabled";
2724 #address-cells = <1>; 2697 #address-cells = <1>;
2725 #size-cells = <0>; 2698 #size-cells = <0>;
2726 }; 2699 };
2727 2700
2728 blsp2_spi6: spi@c1ba000 { 2701 blsp2_spi6: spi@c1ba000 {
2729 compatible = "qcom,sp 2702 compatible = "qcom,spi-qup-v2.2.1";
2730 reg = <0x0c1ba000 0x6 2703 reg = <0x0c1ba000 0x600>;
2731 interrupts = <GIC_SPI 2704 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
2732 2705
2733 clocks = <&gcc GCC_BL 2706 clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>,
2734 <&gcc GCC_BL 2707 <&gcc GCC_BLSP2_AHB_CLK>;
2735 clock-names = "core", 2708 clock-names = "core", "iface";
2736 dmas = <&blsp2_dma 16 2709 dmas = <&blsp2_dma 16>, <&blsp2_dma 17>;
2737 dma-names = "tx", "rx 2710 dma-names = "tx", "rx";
2738 pinctrl-names = "defa 2711 pinctrl-names = "default";
2739 pinctrl-0 = <&blsp2_s 2712 pinctrl-0 = <&blsp2_spi6_default>;
2740 2713
2741 status = "disabled"; 2714 status = "disabled";
2742 #address-cells = <1>; 2715 #address-cells = <1>;
2743 #size-cells = <0>; 2716 #size-cells = <0>;
2744 }; 2717 };
2745 2718
2746 mmcc: clock-controller@c8c000 2719 mmcc: clock-controller@c8c0000 {
2747 compatible = "qcom,mm 2720 compatible = "qcom,mmcc-msm8998";
2748 #clock-cells = <1>; 2721 #clock-cells = <1>;
2749 #reset-cells = <1>; 2722 #reset-cells = <1>;
2750 #power-domain-cells = 2723 #power-domain-cells = <1>;
2751 reg = <0xc8c0000 0x40 2724 reg = <0xc8c0000 0x40000>;
2752 2725
2753 clock-names = "xo", 2726 clock-names = "xo",
2754 "gpll0" 2727 "gpll0",
2755 "dsi0ds 2728 "dsi0dsi",
2756 "dsi0by 2729 "dsi0byte",
2757 "dsi1ds 2730 "dsi1dsi",
2758 "dsi1by 2731 "dsi1byte",
2759 "hdmipl 2732 "hdmipll",
2760 "dplink 2733 "dplink",
2761 "dpvco" 2734 "dpvco",
2762 "gpll0_ 2735 "gpll0_div";
2763 clocks = <&rpmcc RPM_ 2736 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
2764 <&gcc GCC_MM 2737 <&gcc GCC_MMSS_GPLL0_CLK>,
2765 <&mdss_dsi0_ 2738 <&mdss_dsi0_phy 1>,
2766 <&mdss_dsi0_ 2739 <&mdss_dsi0_phy 0>,
2767 <&mdss_dsi1_ 2740 <&mdss_dsi1_phy 1>,
2768 <&mdss_dsi1_ 2741 <&mdss_dsi1_phy 0>,
2769 <0>, 2742 <0>,
2770 <0>, 2743 <0>,
2771 <0>, 2744 <0>,
2772 <&gcc GCC_MM 2745 <&gcc GCC_MMSS_GPLL0_DIV_CLK>;
2773 }; 2746 };
2774 2747
2775 mdss: display-subsystem@c9000 2748 mdss: display-subsystem@c900000 {
2776 compatible = "qcom,ms 2749 compatible = "qcom,msm8998-mdss";
2777 reg = <0x0c900000 0x1 2750 reg = <0x0c900000 0x1000>;
2778 reg-names = "mdss"; 2751 reg-names = "mdss";
2779 2752
2780 interrupts = <GIC_SPI 2753 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
2781 interrupt-controller; 2754 interrupt-controller;
2782 #interrupt-cells = <1 2755 #interrupt-cells = <1>;
2783 2756
2784 clocks = <&mmcc MDSS_ 2757 clocks = <&mmcc MDSS_AHB_CLK>,
2785 <&mmcc MDSS_ 2758 <&mmcc MDSS_AXI_CLK>,
2786 <&mmcc MDSS_ 2759 <&mmcc MDSS_MDP_CLK>;
2787 clock-names = "iface" 2760 clock-names = "iface",
2788 "bus", 2761 "bus",
2789 "core"; 2762 "core";
2790 2763
2791 power-domains = <&mmc 2764 power-domains = <&mmcc MDSS_GDSC>;
2792 iommus = <&mmss_smmu 2765 iommus = <&mmss_smmu 0>;
2793 2766
2794 #address-cells = <1>; 2767 #address-cells = <1>;
2795 #size-cells = <1>; 2768 #size-cells = <1>;
2796 ranges; 2769 ranges;
2797 2770
2798 status = "disabled"; 2771 status = "disabled";
2799 2772
2800 mdss_mdp: display-con 2773 mdss_mdp: display-controller@c901000 {
2801 compatible = 2774 compatible = "qcom,msm8998-dpu";
2802 reg = <0x0c90 2775 reg = <0x0c901000 0x8f000>,
2803 <0x0c9a 2776 <0x0c9a8e00 0xf0>,
2804 <0x0c9b 2777 <0x0c9b0000 0x2008>,
2805 <0x0c9b 2778 <0x0c9b8000 0x1040>;
2806 reg-names = " 2779 reg-names = "mdp",
2807 " 2780 "regdma",
2808 " 2781 "vbif",
2809 " 2782 "vbif_nrt";
2810 2783
2811 interrupt-par 2784 interrupt-parent = <&mdss>;
2812 interrupts = 2785 interrupts = <0>;
2813 2786
2814 clocks = <&mm 2787 clocks = <&mmcc MDSS_AHB_CLK>,
2815 <&mm 2788 <&mmcc MDSS_AXI_CLK>,
2816 <&mm 2789 <&mmcc MNOC_AHB_CLK>,
2817 <&mm 2790 <&mmcc MDSS_MDP_CLK>,
2818 <&mm 2791 <&mmcc MDSS_VSYNC_CLK>;
2819 clock-names = 2792 clock-names = "iface",
2820 2793 "bus",
2821 2794 "mnoc",
2822 2795 "core",
2823 2796 "vsync";
2824 2797
2825 assigned-cloc 2798 assigned-clocks = <&mmcc MDSS_VSYNC_CLK>;
2826 assigned-cloc 2799 assigned-clock-rates = <19200000>;
2827 2800
2828 operating-poi 2801 operating-points-v2 = <&mdp_opp_table>;
2829 power-domains 2802 power-domains = <&rpmpd MSM8998_VDDMX>;
2830 2803
2831 mdp_opp_table 2804 mdp_opp_table: opp-table {
2832 compa 2805 compatible = "operating-points-v2";
2833 2806
2834 opp-1 2807 opp-171430000 {
2835 2808 opp-hz = /bits/ 64 <171430000>;
2836 2809 required-opps = <&rpmpd_opp_low_svs>;
2837 }; 2810 };
2838 2811
2839 opp-2 2812 opp-275000000 {
2840 2813 opp-hz = /bits/ 64 <275000000>;
2841 2814 required-opps = <&rpmpd_opp_svs>;
2842 }; 2815 };
2843 2816
2844 opp-3 2817 opp-330000000 {
2845 2818 opp-hz = /bits/ 64 <330000000>;
2846 2819 required-opps = <&rpmpd_opp_nom>;
2847 }; 2820 };
2848 2821
2849 opp-4 2822 opp-412500000 {
2850 2823 opp-hz = /bits/ 64 <412500000>;
2851 2824 required-opps = <&rpmpd_opp_turbo>;
2852 }; 2825 };
2853 }; 2826 };
2854 2827
2855 ports { 2828 ports {
2856 #addr 2829 #address-cells = <1>;
2857 #size 2830 #size-cells = <0>;
2858 2831
2859 port@ 2832 port@0 {
2860 2833 reg = <0>;
2861 2834
2862 2835 dpu_intf1_out: endpoint {
2863 2836 remote-endpoint = <&mdss_dsi0_in>;
2864 2837 };
2865 }; 2838 };
2866 2839
2867 port@ 2840 port@1 {
2868 2841 reg = <1>;
2869 2842
2870 2843 dpu_intf2_out: endpoint {
2871 2844 remote-endpoint = <&mdss_dsi1_in>;
2872 2845 };
2873 }; 2846 };
2874 }; 2847 };
2875 }; 2848 };
2876 2849
2877 mdss_dsi0: dsi@c99400 2850 mdss_dsi0: dsi@c994000 {
2878 compatible = 2851 compatible = "qcom,msm8998-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2879 reg = <0x0c99 2852 reg = <0x0c994000 0x400>;
2880 reg-names = " 2853 reg-names = "dsi_ctrl";
2881 2854
2882 interrupt-par 2855 interrupt-parent = <&mdss>;
2883 interrupts = 2856 interrupts = <4>;
2884 2857
2885 clocks = <&mm 2858 clocks = <&mmcc MDSS_BYTE0_CLK>,
2886 <&mm 2859 <&mmcc MDSS_BYTE0_INTF_CLK>,
2887 <&mm 2860 <&mmcc MDSS_PCLK0_CLK>,
2888 <&mm 2861 <&mmcc MDSS_ESC0_CLK>,
2889 <&mm 2862 <&mmcc MDSS_AHB_CLK>,
2890 <&mm 2863 <&mmcc MDSS_AXI_CLK>;
2891 clock-names = 2864 clock-names = "byte",
2892 2865 "byte_intf",
2893 2866 "pixel",
2894 2867 "core",
2895 2868 "iface",
2896 2869 "bus";
2897 assigned-cloc 2870 assigned-clocks = <&mmcc BYTE0_CLK_SRC>,
2898 2871 <&mmcc PCLK0_CLK_SRC>;
2899 assigned-cloc 2872 assigned-clock-parents = <&mdss_dsi0_phy 0>,
2900 2873 <&mdss_dsi0_phy 1>;
2901 2874
2902 operating-poi 2875 operating-points-v2 = <&dsi_opp_table>;
2903 power-domains 2876 power-domains = <&rpmpd MSM8998_VDDCX>;
2904 2877
2905 phys = <&mdss 2878 phys = <&mdss_dsi0_phy>;
2906 phy-names = " 2879 phy-names = "dsi";
2907 2880
2908 #address-cell 2881 #address-cells = <1>;
2909 #size-cells = 2882 #size-cells = <0>;
2910 2883
2911 status = "dis 2884 status = "disabled";
2912 2885
2913 ports { 2886 ports {
2914 #addr 2887 #address-cells = <1>;
2915 #size 2888 #size-cells = <0>;
2916 2889
2917 port@ 2890 port@0 {
2918 2891 reg = <0>;
2919 2892
2920 2893 mdss_dsi0_in: endpoint {
2921 2894 remote-endpoint = <&dpu_intf1_out>;
2922 2895 };
2923 }; 2896 };
2924 2897
2925 port@ 2898 port@1 {
2926 2899 reg = <1>;
2927 2900
2928 2901 mdss_dsi0_out: endpoint {
2929 2902 };
2930 }; 2903 };
2931 }; 2904 };
2932 }; 2905 };
2933 2906
2934 mdss_dsi0_phy: phy@c9 2907 mdss_dsi0_phy: phy@c994400 {
2935 compatible = 2908 compatible = "qcom,dsi-phy-10nm-8998";
2936 reg = <0x0c99 2909 reg = <0x0c994400 0x200>,
2937 <0x0c99 2910 <0x0c994600 0x280>,
2938 <0x0c99 2911 <0x0c994a00 0x1e0>;
2939 reg-names = " 2912 reg-names = "dsi_phy",
2940 " 2913 "dsi_phy_lane",
2941 " 2914 "dsi_pll";
2942 2915
2943 clocks = <&mm 2916 clocks = <&mmcc MDSS_AHB_CLK>,
2944 <&rp 2917 <&rpmcc RPM_SMD_XO_CLK_SRC>;
2945 clock-names = 2918 clock-names = "iface", "ref";
2946 2919
2947 #clock-cells 2920 #clock-cells = <1>;
2948 #phy-cells = 2921 #phy-cells = <0>;
2949 2922
2950 status = "dis 2923 status = "disabled";
2951 }; 2924 };
2952 2925
2953 mdss_dsi1: dsi@c99600 2926 mdss_dsi1: dsi@c996000 {
2954 compatible = 2927 compatible = "qcom,msm8998-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2955 reg = <0x0c99 2928 reg = <0x0c996000 0x400>;
2956 reg-names = " 2929 reg-names = "dsi_ctrl";
2957 2930
2958 interrupt-par 2931 interrupt-parent = <&mdss>;
2959 interrupts = 2932 interrupts = <5>;
2960 2933
2961 clocks = <&mm 2934 clocks = <&mmcc MDSS_BYTE1_CLK>,
2962 <&mm 2935 <&mmcc MDSS_BYTE1_INTF_CLK>,
2963 <&mm 2936 <&mmcc MDSS_PCLK1_CLK>,
2964 <&mm 2937 <&mmcc MDSS_ESC1_CLK>,
2965 <&mm 2938 <&mmcc MDSS_AHB_CLK>,
2966 <&mm 2939 <&mmcc MDSS_AXI_CLK>;
2967 clock-names = 2940 clock-names = "byte",
2968 2941 "byte_intf",
2969 2942 "pixel",
2970 2943 "core",
2971 2944 "iface",
2972 2945 "bus";
2973 assigned-cloc 2946 assigned-clocks = <&mmcc BYTE1_CLK_SRC>,
2974 2947 <&mmcc PCLK1_CLK_SRC>;
2975 assigned-cloc 2948 assigned-clock-parents = <&mdss_dsi1_phy 0>,
2976 2949 <&mdss_dsi1_phy 1>;
2977 2950
2978 operating-poi 2951 operating-points-v2 = <&dsi_opp_table>;
2979 power-domains 2952 power-domains = <&rpmpd MSM8998_VDDCX>;
2980 2953
2981 phys = <&mdss 2954 phys = <&mdss_dsi1_phy>;
2982 phy-names = " 2955 phy-names = "dsi";
2983 2956
2984 #address-cell 2957 #address-cells = <1>;
2985 #size-cells = 2958 #size-cells = <0>;
2986 2959
2987 status = "dis 2960 status = "disabled";
2988 2961
2989 ports { 2962 ports {
2990 #addr 2963 #address-cells = <1>;
2991 #size 2964 #size-cells = <0>;
2992 2965
2993 port@ 2966 port@0 {
2994 2967 reg = <0>;
2995 2968
2996 2969 mdss_dsi1_in: endpoint {
2997 2970 remote-endpoint = <&dpu_intf2_out>;
2998 2971 };
2999 }; 2972 };
3000 2973
3001 port@ 2974 port@1 {
3002 2975 reg = <1>;
3003 2976
3004 2977 mdss_dsi1_out: endpoint {
3005 2978 };
3006 }; 2979 };
3007 }; 2980 };
3008 }; 2981 };
3009 2982
3010 mdss_dsi1_phy: phy@c9 2983 mdss_dsi1_phy: phy@c996400 {
3011 compatible = 2984 compatible = "qcom,dsi-phy-10nm-8998";
3012 reg = <0x0c99 2985 reg = <0x0c996400 0x200>,
3013 <0x0c99 2986 <0x0c996600 0x280>,
3014 <0x0c99 2987 <0x0c996a00 0x10e>;
3015 reg-names = " 2988 reg-names = "dsi_phy",
3016 " 2989 "dsi_phy_lane",
3017 " 2990 "dsi_pll";
3018 2991
3019 clocks = <&mm 2992 clocks = <&mmcc MDSS_AHB_CLK>,
3020 <&rp 2993 <&rpmcc RPM_SMD_XO_CLK_SRC>;
3021 clock-names = 2994 clock-names = "iface",
3022 2995 "ref";
3023 2996
3024 #clock-cells 2997 #clock-cells = <1>;
3025 #phy-cells = 2998 #phy-cells = <0>;
3026 2999
3027 status = "dis 3000 status = "disabled";
3028 }; 3001 };
3029 }; 3002 };
3030 3003
3031 venus: video-codec@cc00000 { 3004 venus: video-codec@cc00000 {
3032 compatible = "qcom,ms 3005 compatible = "qcom,msm8998-venus";
3033 reg = <0x0cc00000 0xf 3006 reg = <0x0cc00000 0xff000>;
3034 interrupts = <GIC_SPI 3007 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
3035 power-domains = <&mmc 3008 power-domains = <&mmcc VIDEO_TOP_GDSC>;
3036 clocks = <&mmcc VIDEO 3009 clocks = <&mmcc VIDEO_CORE_CLK>,
3037 <&mmcc VIDEO 3010 <&mmcc VIDEO_AHB_CLK>,
3038 <&mmcc VIDEO 3011 <&mmcc VIDEO_AXI_CLK>,
3039 <&mmcc VIDEO 3012 <&mmcc VIDEO_MAXI_CLK>;
3040 clock-names = "core", 3013 clock-names = "core", "iface", "bus", "mbus";
3041 iommus = <&mmss_smmu 3014 iommus = <&mmss_smmu 0x400>,
3042 <&mmss_smmu 3015 <&mmss_smmu 0x401>,
3043 <&mmss_smmu 3016 <&mmss_smmu 0x40a>,
3044 <&mmss_smmu 3017 <&mmss_smmu 0x407>,
3045 <&mmss_smmu 3018 <&mmss_smmu 0x40e>,
3046 <&mmss_smmu 3019 <&mmss_smmu 0x40f>,
3047 <&mmss_smmu 3020 <&mmss_smmu 0x408>,
3048 <&mmss_smmu 3021 <&mmss_smmu 0x409>,
3049 <&mmss_smmu 3022 <&mmss_smmu 0x40b>,
3050 <&mmss_smmu 3023 <&mmss_smmu 0x40c>,
3051 <&mmss_smmu 3024 <&mmss_smmu 0x40d>,
3052 <&mmss_smmu 3025 <&mmss_smmu 0x410>,
3053 <&mmss_smmu 3026 <&mmss_smmu 0x421>,
3054 <&mmss_smmu 3027 <&mmss_smmu 0x428>,
3055 <&mmss_smmu 3028 <&mmss_smmu 0x429>,
3056 <&mmss_smmu 3029 <&mmss_smmu 0x42b>,
3057 <&mmss_smmu 3030 <&mmss_smmu 0x42c>,
3058 <&mmss_smmu 3031 <&mmss_smmu 0x42d>,
3059 <&mmss_smmu 3032 <&mmss_smmu 0x411>,
3060 <&mmss_smmu 3033 <&mmss_smmu 0x431>;
3061 memory-region = <&ven 3034 memory-region = <&venus_mem>;
3062 status = "disabled"; 3035 status = "disabled";
3063 3036
3064 video-decoder { 3037 video-decoder {
3065 compatible = 3038 compatible = "venus-decoder";
3066 clocks = <&mm 3039 clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
3067 clock-names = 3040 clock-names = "core";
3068 power-domains 3041 power-domains = <&mmcc VIDEO_SUBCORE0_GDSC>;
3069 }; 3042 };
3070 3043
3071 video-encoder { 3044 video-encoder {
3072 compatible = 3045 compatible = "venus-encoder";
3073 clocks = <&mm 3046 clocks = <&mmcc VIDEO_SUBCORE1_CLK>;
3074 clock-names = 3047 clock-names = "core";
3075 power-domains 3048 power-domains = <&mmcc VIDEO_SUBCORE1_GDSC>;
3076 }; 3049 };
3077 }; 3050 };
3078 3051
3079 mmss_smmu: iommu@cd00000 { 3052 mmss_smmu: iommu@cd00000 {
3080 compatible = "qcom,ms 3053 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
3081 reg = <0x0cd00000 0x4 3054 reg = <0x0cd00000 0x40000>;
3082 #iommu-cells = <1>; 3055 #iommu-cells = <1>;
3083 3056
3084 clocks = <&mmcc MNOC_ 3057 clocks = <&mmcc MNOC_AHB_CLK>,
3085 <&mmcc BIMC_ 3058 <&mmcc BIMC_SMMU_AHB_CLK>,
3086 <&mmcc BIMC_ 3059 <&mmcc BIMC_SMMU_AXI_CLK>;
3087 clock-names = "iface- 3060 clock-names = "iface-mm",
3088 "iface- 3061 "iface-smmu",
3089 "bus-sm 3062 "bus-smmu";
3090 3063
3091 #global-interrupts = 3064 #global-interrupts = <0>;
3092 interrupts = 3065 interrupts =
3093 <GIC_SPI 263 3066 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
3094 <GIC_SPI 266 3067 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
3095 <GIC_SPI 267 3068 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
3096 <GIC_SPI 268 3069 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
3097 <GIC_SPI 244 3070 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
3098 <GIC_SPI 245 3071 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
3099 <GIC_SPI 247 3072 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
3100 <GIC_SPI 248 3073 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
3101 <GIC_SPI 249 3074 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
3102 <GIC_SPI 250 3075 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
3103 <GIC_SPI 251 3076 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
3104 <GIC_SPI 252 3077 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
3105 <GIC_SPI 253 3078 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
3106 <GIC_SPI 254 3079 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
3107 <GIC_SPI 255 3080 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
3108 <GIC_SPI 256 3081 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
3109 <GIC_SPI 260 3082 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
3110 <GIC_SPI 261 3083 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
3111 <GIC_SPI 262 3084 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
3112 <GIC_SPI 272 3085 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
3113 3086
3114 power-domains = <&mmc 3087 power-domains = <&mmcc BIMC_SMMU_GDSC>;
3115 }; 3088 };
3116 3089
3117 remoteproc_adsp: remoteproc@1 3090 remoteproc_adsp: remoteproc@17300000 {
3118 compatible = "qcom,ms 3091 compatible = "qcom,msm8998-adsp-pas";
3119 reg = <0x17300000 0x4 3092 reg = <0x17300000 0x4040>;
3120 3093
3121 interrupts-extended = 3094 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
3122 3095 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3123 3096 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3124 3097 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3125 3098 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
3126 interrupt-names = "wd 3099 interrupt-names = "wdog", "fatal", "ready",
3127 "ha 3100 "handover", "stop-ack";
3128 3101
3129 clocks = <&rpmcc RPM_ 3102 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
3130 clock-names = "xo"; 3103 clock-names = "xo";
3131 3104
3132 memory-region = <&ads 3105 memory-region = <&adsp_mem>;
3133 3106
3134 qcom,smem-states = <& 3107 qcom,smem-states = <&adsp_smp2p_out 0>;
3135 qcom,smem-state-names 3108 qcom,smem-state-names = "stop";
3136 3109
3137 power-domains = <&rpm 3110 power-domains = <&rpmpd MSM8998_VDDCX>;
3138 power-domain-names = 3111 power-domain-names = "cx";
3139 3112
3140 status = "disabled"; 3113 status = "disabled";
3141 3114
3142 glink-edge { 3115 glink-edge {
3143 interrupts = 3116 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
3144 label = "lpas 3117 label = "lpass";
3145 qcom,remote-p 3118 qcom,remote-pid = <2>;
3146 mboxes = <&ap 3119 mboxes = <&apcs_glb 9>;
3147 }; 3120 };
3148 }; 3121 };
3149 3122
3150 apcs_glb: mailbox@17911000 { 3123 apcs_glb: mailbox@17911000 {
3151 compatible = "qcom,ms 3124 compatible = "qcom,msm8998-apcs-hmss-global",
3152 "qcom,ms 3125 "qcom,msm8994-apcs-kpss-global";
3153 reg = <0x17911000 0x1 3126 reg = <0x17911000 0x1000>;
3154 3127
3155 #mbox-cells = <1>; 3128 #mbox-cells = <1>;
3156 }; 3129 };
3157 3130
3158 timer@17920000 { 3131 timer@17920000 {
3159 #address-cells = <1>; 3132 #address-cells = <1>;
3160 #size-cells = <1>; 3133 #size-cells = <1>;
3161 ranges; 3134 ranges;
3162 compatible = "arm,arm 3135 compatible = "arm,armv7-timer-mem";
3163 reg = <0x17920000 0x1 3136 reg = <0x17920000 0x1000>;
3164 3137
3165 frame@17921000 { 3138 frame@17921000 {
3166 frame-number 3139 frame-number = <0>;
3167 interrupts = 3140 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
3168 3141 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
3169 reg = <0x1792 3142 reg = <0x17921000 0x1000>,
3170 <0x1792 3143 <0x17922000 0x1000>;
3171 }; 3144 };
3172 3145
3173 frame@17923000 { 3146 frame@17923000 {
3174 frame-number 3147 frame-number = <1>;
3175 interrupts = 3148 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
3176 reg = <0x1792 3149 reg = <0x17923000 0x1000>;
3177 status = "dis 3150 status = "disabled";
3178 }; 3151 };
3179 3152
3180 frame@17924000 { 3153 frame@17924000 {
3181 frame-number 3154 frame-number = <2>;
3182 interrupts = 3155 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
3183 reg = <0x1792 3156 reg = <0x17924000 0x1000>;
3184 status = "dis 3157 status = "disabled";
3185 }; 3158 };
3186 3159
3187 frame@17925000 { 3160 frame@17925000 {
3188 frame-number 3161 frame-number = <3>;
3189 interrupts = 3162 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3190 reg = <0x1792 3163 reg = <0x17925000 0x1000>;
3191 status = "dis 3164 status = "disabled";
3192 }; 3165 };
3193 3166
3194 frame@17926000 { 3167 frame@17926000 {
3195 frame-number 3168 frame-number = <4>;
3196 interrupts = 3169 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3197 reg = <0x1792 3170 reg = <0x17926000 0x1000>;
3198 status = "dis 3171 status = "disabled";
3199 }; 3172 };
3200 3173
3201 frame@17927000 { 3174 frame@17927000 {
3202 frame-number 3175 frame-number = <5>;
3203 interrupts = 3176 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3204 reg = <0x1792 3177 reg = <0x17927000 0x1000>;
3205 status = "dis 3178 status = "disabled";
3206 }; 3179 };
3207 3180
3208 frame@17928000 { 3181 frame@17928000 {
3209 frame-number 3182 frame-number = <6>;
3210 interrupts = 3183 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
3211 reg = <0x1792 3184 reg = <0x17928000 0x1000>;
3212 status = "dis 3185 status = "disabled";
3213 }; 3186 };
3214 }; 3187 };
3215 3188
3216 intc: interrupt-controller@17 3189 intc: interrupt-controller@17a00000 {
3217 compatible = "arm,gic 3190 compatible = "arm,gic-v3";
3218 reg = <0x17a00000 0x1 3191 reg = <0x17a00000 0x10000>, /* GICD */
3219 <0x17b00000 0x1 3192 <0x17b00000 0x100000>; /* GICR * 8 */
3220 #interrupt-cells = <3 3193 #interrupt-cells = <3>;
3221 #address-cells = <1>; 3194 #address-cells = <1>;
3222 #size-cells = <1>; 3195 #size-cells = <1>;
3223 ranges; 3196 ranges;
3224 interrupt-controller; 3197 interrupt-controller;
3225 #redistributor-region 3198 #redistributor-regions = <1>;
3226 redistributor-stride 3199 redistributor-stride = <0x0 0x20000>;
3227 interrupts = <GIC_PPI 3200 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3228 }; 3201 };
3229 3202
3230 wifi: wifi@18800000 { 3203 wifi: wifi@18800000 {
3231 compatible = "qcom,wc 3204 compatible = "qcom,wcn3990-wifi";
3232 status = "disabled"; 3205 status = "disabled";
3233 reg = <0x18800000 0x8 3206 reg = <0x18800000 0x800000>;
3234 reg-names = "membase" 3207 reg-names = "membase";
3235 memory-region = <&wla 3208 memory-region = <&wlan_msa_mem>;
3236 clocks = <&rpmcc RPM_ 3209 clocks = <&rpmcc RPM_SMD_RF_CLK2_PIN>;
3237 clock-names = "cxo_re 3210 clock-names = "cxo_ref_clk_pin";
3238 interrupts = 3211 interrupts =
3239 <GIC_SPI 413 3212 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
3240 <GIC_SPI 414 3213 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
3241 <GIC_SPI 415 3214 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
3242 <GIC_SPI 416 3215 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
3243 <GIC_SPI 417 3216 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
3244 <GIC_SPI 418 3217 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
3245 <GIC_SPI 420 3218 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
3246 <GIC_SPI 421 3219 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
3247 <GIC_SPI 422 3220 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
3248 <GIC_SPI 423 3221 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
3249 <GIC_SPI 424 3222 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
3250 <GIC_SPI 425 3223 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
3251 iommus = <&anoc2_smmu 3224 iommus = <&anoc2_smmu 0x1900>,
3252 <&anoc2_smmu 3225 <&anoc2_smmu 0x1901>;
3253 qcom,snoc-host-cap-8b 3226 qcom,snoc-host-cap-8bit-quirk;
3254 qcom,no-msa-ready-ind 3227 qcom,no-msa-ready-indicator;
3255 }; 3228 };
3256 }; 3229 };
3257 }; 3230 };
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