1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2016, The Linux Foundation. A 2 /* Copyright (c) 2016, The Linux Foundation. All rights reserved. */
3 3
4 #include <dt-bindings/interrupt-controller/arm 4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-msm8998.h 5 #include <dt-bindings/clock/qcom,gcc-msm8998.h>
6 #include <dt-bindings/clock/qcom,gpucc-msm8998 6 #include <dt-bindings/clock/qcom,gpucc-msm8998.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8998. 7 #include <dt-bindings/clock/qcom,mmcc-msm8998.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h> 8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/firmware/qcom,scm.h> <<
10 #include <dt-bindings/power/qcom-rpmpd.h> 9 #include <dt-bindings/power/qcom-rpmpd.h>
11 #include <dt-bindings/gpio/gpio.h> 10 #include <dt-bindings/gpio/gpio.h>
12 11
13 / { 12 / {
14 interrupt-parent = <&intc>; 13 interrupt-parent = <&intc>;
15 14
16 qcom,msm-id = <292 0x0>; 15 qcom,msm-id = <292 0x0>;
17 16
18 #address-cells = <2>; 17 #address-cells = <2>;
19 #size-cells = <2>; 18 #size-cells = <2>;
20 19
21 chosen { }; 20 chosen { };
22 21
23 memory@80000000 { 22 memory@80000000 {
24 device_type = "memory"; 23 device_type = "memory";
25 /* We expect the bootloader to 24 /* We expect the bootloader to fill in the reg */
26 reg = <0x0 0x80000000 0x0 0x0> 25 reg = <0x0 0x80000000 0x0 0x0>;
27 }; 26 };
28 27
29 reserved-memory { 28 reserved-memory {
30 #address-cells = <2>; 29 #address-cells = <2>;
31 #size-cells = <2>; 30 #size-cells = <2>;
32 ranges; 31 ranges;
33 32
34 hyp_mem: memory@85800000 { 33 hyp_mem: memory@85800000 {
35 reg = <0x0 0x85800000 34 reg = <0x0 0x85800000 0x0 0x600000>;
36 no-map; 35 no-map;
37 }; 36 };
38 37
39 xbl_mem: memory@85e00000 { 38 xbl_mem: memory@85e00000 {
40 reg = <0x0 0x85e00000 39 reg = <0x0 0x85e00000 0x0 0x100000>;
41 no-map; 40 no-map;
42 }; 41 };
43 42
44 smem_mem: smem-mem@86000000 { 43 smem_mem: smem-mem@86000000 {
45 reg = <0x0 0x86000000 44 reg = <0x0 0x86000000 0x0 0x200000>;
46 no-map; 45 no-map;
47 }; 46 };
48 47
49 tz_mem: memory@86200000 { 48 tz_mem: memory@86200000 {
50 reg = <0x0 0x86200000 49 reg = <0x0 0x86200000 0x0 0x2d00000>;
51 no-map; 50 no-map;
52 }; 51 };
53 52
54 rmtfs_mem: memory@88f00000 { 53 rmtfs_mem: memory@88f00000 {
55 compatible = "qcom,rmt 54 compatible = "qcom,rmtfs-mem";
56 reg = <0x0 0x88f00000 55 reg = <0x0 0x88f00000 0x0 0x200000>;
57 no-map; 56 no-map;
58 57
59 qcom,client-id = <1>; 58 qcom,client-id = <1>;
60 qcom,vmid = <QCOM_SCM_ !! 59 qcom,vmid = <15>;
61 }; 60 };
62 61
63 spss_mem: memory@8ab00000 { 62 spss_mem: memory@8ab00000 {
64 reg = <0x0 0x8ab00000 63 reg = <0x0 0x8ab00000 0x0 0x700000>;
65 no-map; 64 no-map;
66 }; 65 };
67 66
68 adsp_mem: memory@8b200000 { 67 adsp_mem: memory@8b200000 {
69 reg = <0x0 0x8b200000 68 reg = <0x0 0x8b200000 0x0 0x1a00000>;
70 no-map; 69 no-map;
71 }; 70 };
72 71
73 mpss_mem: memory@8cc00000 { 72 mpss_mem: memory@8cc00000 {
74 reg = <0x0 0x8cc00000 73 reg = <0x0 0x8cc00000 0x0 0x7000000>;
75 no-map; 74 no-map;
76 }; 75 };
77 76
78 venus_mem: memory@93c00000 { 77 venus_mem: memory@93c00000 {
79 reg = <0x0 0x93c00000 78 reg = <0x0 0x93c00000 0x0 0x500000>;
80 no-map; 79 no-map;
81 }; 80 };
82 81
83 mba_mem: memory@94100000 { 82 mba_mem: memory@94100000 {
84 reg = <0x0 0x94100000 83 reg = <0x0 0x94100000 0x0 0x200000>;
85 no-map; 84 no-map;
86 }; 85 };
87 86
88 slpi_mem: memory@94300000 { 87 slpi_mem: memory@94300000 {
89 reg = <0x0 0x94300000 88 reg = <0x0 0x94300000 0x0 0xf00000>;
90 no-map; 89 no-map;
91 }; 90 };
92 91
93 ipa_fw_mem: memory@95200000 { 92 ipa_fw_mem: memory@95200000 {
94 reg = <0x0 0x95200000 93 reg = <0x0 0x95200000 0x0 0x10000>;
95 no-map; 94 no-map;
96 }; 95 };
97 96
98 ipa_gsi_mem: memory@95210000 { 97 ipa_gsi_mem: memory@95210000 {
99 reg = <0x0 0x95210000 98 reg = <0x0 0x95210000 0x0 0x5000>;
100 no-map; 99 no-map;
101 }; 100 };
102 101
103 gpu_mem: memory@95600000 { 102 gpu_mem: memory@95600000 {
104 reg = <0x0 0x95600000 103 reg = <0x0 0x95600000 0x0 0x100000>;
105 no-map; 104 no-map;
106 }; 105 };
107 106
108 wlan_msa_mem: memory@95700000 107 wlan_msa_mem: memory@95700000 {
109 reg = <0x0 0x95700000 108 reg = <0x0 0x95700000 0x0 0x100000>;
110 no-map; 109 no-map;
111 }; 110 };
112 <<
113 mdata_mem: mpss-metadata { <<
114 alloc-ranges = <0x0 0x <<
115 size = <0x0 0x4000>; <<
116 no-map; <<
117 }; <<
118 }; 111 };
119 112
120 clocks { 113 clocks {
121 xo: xo-board { 114 xo: xo-board {
122 compatible = "fixed-cl 115 compatible = "fixed-clock";
123 #clock-cells = <0>; 116 #clock-cells = <0>;
124 clock-frequency = <192 117 clock-frequency = <19200000>;
125 clock-output-names = " 118 clock-output-names = "xo_board";
126 }; 119 };
127 120
128 sleep_clk: sleep-clk { 121 sleep_clk: sleep-clk {
129 compatible = "fixed-cl 122 compatible = "fixed-clock";
130 #clock-cells = <0>; 123 #clock-cells = <0>;
131 clock-frequency = <327 124 clock-frequency = <32764>;
132 }; 125 };
133 }; 126 };
134 127
135 cpus { 128 cpus {
136 #address-cells = <2>; 129 #address-cells = <2>;
137 #size-cells = <0>; 130 #size-cells = <0>;
138 131
139 CPU0: cpu@0 { 132 CPU0: cpu@0 {
140 device_type = "cpu"; 133 device_type = "cpu";
141 compatible = "qcom,kry 134 compatible = "qcom,kryo280";
142 reg = <0x0 0x0>; 135 reg = <0x0 0x0>;
143 enable-method = "psci" 136 enable-method = "psci";
144 capacity-dmips-mhz = < 137 capacity-dmips-mhz = <1024>;
145 cpu-idle-states = <&LI 138 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
146 next-level-cache = <&L 139 next-level-cache = <&L2_0>;
147 L2_0: l2-cache { 140 L2_0: l2-cache {
148 compatible = " 141 compatible = "cache";
149 cache-level = 142 cache-level = <2>;
150 cache-unified; <<
151 }; 143 };
152 }; 144 };
153 145
154 CPU1: cpu@1 { 146 CPU1: cpu@1 {
155 device_type = "cpu"; 147 device_type = "cpu";
156 compatible = "qcom,kry 148 compatible = "qcom,kryo280";
157 reg = <0x0 0x1>; 149 reg = <0x0 0x1>;
158 enable-method = "psci" 150 enable-method = "psci";
159 capacity-dmips-mhz = < 151 capacity-dmips-mhz = <1024>;
160 cpu-idle-states = <&LI 152 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
161 next-level-cache = <&L 153 next-level-cache = <&L2_0>;
162 }; 154 };
163 155
164 CPU2: cpu@2 { 156 CPU2: cpu@2 {
165 device_type = "cpu"; 157 device_type = "cpu";
166 compatible = "qcom,kry 158 compatible = "qcom,kryo280";
167 reg = <0x0 0x2>; 159 reg = <0x0 0x2>;
168 enable-method = "psci" 160 enable-method = "psci";
169 capacity-dmips-mhz = < 161 capacity-dmips-mhz = <1024>;
170 cpu-idle-states = <&LI 162 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
171 next-level-cache = <&L 163 next-level-cache = <&L2_0>;
172 }; 164 };
173 165
174 CPU3: cpu@3 { 166 CPU3: cpu@3 {
175 device_type = "cpu"; 167 device_type = "cpu";
176 compatible = "qcom,kry 168 compatible = "qcom,kryo280";
177 reg = <0x0 0x3>; 169 reg = <0x0 0x3>;
178 enable-method = "psci" 170 enable-method = "psci";
179 capacity-dmips-mhz = < 171 capacity-dmips-mhz = <1024>;
180 cpu-idle-states = <&LI 172 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
181 next-level-cache = <&L 173 next-level-cache = <&L2_0>;
182 }; 174 };
183 175
184 CPU4: cpu@100 { 176 CPU4: cpu@100 {
185 device_type = "cpu"; 177 device_type = "cpu";
186 compatible = "qcom,kry 178 compatible = "qcom,kryo280";
187 reg = <0x0 0x100>; 179 reg = <0x0 0x100>;
188 enable-method = "psci" 180 enable-method = "psci";
189 capacity-dmips-mhz = < 181 capacity-dmips-mhz = <1536>;
190 cpu-idle-states = <&BI 182 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
191 next-level-cache = <&L 183 next-level-cache = <&L2_1>;
192 L2_1: l2-cache { 184 L2_1: l2-cache {
193 compatible = " 185 compatible = "cache";
194 cache-level = 186 cache-level = <2>;
195 cache-unified; <<
196 }; 187 };
197 }; 188 };
198 189
199 CPU5: cpu@101 { 190 CPU5: cpu@101 {
200 device_type = "cpu"; 191 device_type = "cpu";
201 compatible = "qcom,kry 192 compatible = "qcom,kryo280";
202 reg = <0x0 0x101>; 193 reg = <0x0 0x101>;
203 enable-method = "psci" 194 enable-method = "psci";
204 capacity-dmips-mhz = < 195 capacity-dmips-mhz = <1536>;
205 cpu-idle-states = <&BI 196 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
206 next-level-cache = <&L 197 next-level-cache = <&L2_1>;
207 }; 198 };
208 199
209 CPU6: cpu@102 { 200 CPU6: cpu@102 {
210 device_type = "cpu"; 201 device_type = "cpu";
211 compatible = "qcom,kry 202 compatible = "qcom,kryo280";
212 reg = <0x0 0x102>; 203 reg = <0x0 0x102>;
213 enable-method = "psci" 204 enable-method = "psci";
214 capacity-dmips-mhz = < 205 capacity-dmips-mhz = <1536>;
215 cpu-idle-states = <&BI 206 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
216 next-level-cache = <&L 207 next-level-cache = <&L2_1>;
217 }; 208 };
218 209
219 CPU7: cpu@103 { 210 CPU7: cpu@103 {
220 device_type = "cpu"; 211 device_type = "cpu";
221 compatible = "qcom,kry 212 compatible = "qcom,kryo280";
222 reg = <0x0 0x103>; 213 reg = <0x0 0x103>;
223 enable-method = "psci" 214 enable-method = "psci";
224 capacity-dmips-mhz = < 215 capacity-dmips-mhz = <1536>;
225 cpu-idle-states = <&BI 216 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
226 next-level-cache = <&L 217 next-level-cache = <&L2_1>;
227 }; 218 };
228 219
229 cpu-map { 220 cpu-map {
230 cluster0 { 221 cluster0 {
231 core0 { 222 core0 {
232 cpu = 223 cpu = <&CPU0>;
233 }; 224 };
234 225
235 core1 { 226 core1 {
236 cpu = 227 cpu = <&CPU1>;
237 }; 228 };
238 229
239 core2 { 230 core2 {
240 cpu = 231 cpu = <&CPU2>;
241 }; 232 };
242 233
243 core3 { 234 core3 {
244 cpu = 235 cpu = <&CPU3>;
245 }; 236 };
246 }; 237 };
247 238
248 cluster1 { 239 cluster1 {
249 core0 { 240 core0 {
250 cpu = 241 cpu = <&CPU4>;
251 }; 242 };
252 243
253 core1 { 244 core1 {
254 cpu = 245 cpu = <&CPU5>;
255 }; 246 };
256 247
257 core2 { 248 core2 {
258 cpu = 249 cpu = <&CPU6>;
259 }; 250 };
260 251
261 core3 { 252 core3 {
262 cpu = 253 cpu = <&CPU7>;
263 }; 254 };
264 }; 255 };
265 }; 256 };
266 257
267 idle-states { 258 idle-states {
268 entry-method = "psci"; 259 entry-method = "psci";
269 260
270 LITTLE_CPU_SLEEP_0: cp 261 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
271 compatible = " 262 compatible = "arm,idle-state";
272 idle-state-nam 263 idle-state-name = "little-retention";
273 /* CPU Retenti 264 /* CPU Retention (C2D), L2 Active */
274 arm,psci-suspe 265 arm,psci-suspend-param = <0x00000002>;
275 entry-latency- 266 entry-latency-us = <81>;
276 exit-latency-u 267 exit-latency-us = <86>;
277 min-residency- 268 min-residency-us = <504>;
278 }; 269 };
279 270
280 LITTLE_CPU_SLEEP_1: cp 271 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
281 compatible = " 272 compatible = "arm,idle-state";
282 idle-state-nam 273 idle-state-name = "little-power-collapse";
283 /* CPU + L2 Po 274 /* CPU + L2 Power Collapse (C3, D4) */
284 arm,psci-suspe 275 arm,psci-suspend-param = <0x40000003>;
285 entry-latency- 276 entry-latency-us = <814>;
286 exit-latency-u 277 exit-latency-us = <4562>;
287 min-residency- 278 min-residency-us = <9183>;
288 local-timer-st 279 local-timer-stop;
289 }; 280 };
290 281
291 BIG_CPU_SLEEP_0: cpu-s 282 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
292 compatible = " 283 compatible = "arm,idle-state";
293 idle-state-nam 284 idle-state-name = "big-retention";
294 /* CPU Retenti 285 /* CPU Retention (C2D), L2 Active */
295 arm,psci-suspe 286 arm,psci-suspend-param = <0x00000002>;
296 entry-latency- 287 entry-latency-us = <79>;
297 exit-latency-u 288 exit-latency-us = <82>;
298 min-residency- 289 min-residency-us = <1302>;
299 }; 290 };
300 291
301 BIG_CPU_SLEEP_1: cpu-s 292 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
302 compatible = " 293 compatible = "arm,idle-state";
303 idle-state-nam 294 idle-state-name = "big-power-collapse";
304 /* CPU + L2 Po 295 /* CPU + L2 Power Collapse (C3, D4) */
305 arm,psci-suspe 296 arm,psci-suspend-param = <0x40000003>;
306 entry-latency- 297 entry-latency-us = <724>;
307 exit-latency-u 298 exit-latency-us = <2027>;
308 min-residency- 299 min-residency-us = <9419>;
309 local-timer-st 300 local-timer-stop;
310 }; 301 };
311 }; 302 };
312 }; 303 };
313 304
314 firmware { 305 firmware {
315 scm { 306 scm {
316 compatible = "qcom,scm 307 compatible = "qcom,scm-msm8998", "qcom,scm";
317 }; 308 };
318 }; 309 };
319 310
320 dsi_opp_table: opp-table-dsi { <<
321 compatible = "operating-points <<
322 <<
323 opp-131250000 { <<
324 opp-hz = /bits/ 64 <13 <<
325 required-opps = <&rpmp <<
326 }; <<
327 <<
328 opp-210000000 { <<
329 opp-hz = /bits/ 64 <21 <<
330 required-opps = <&rpmp <<
331 }; <<
332 <<
333 opp-312500000 { <<
334 opp-hz = /bits/ 64 <31 <<
335 required-opps = <&rpmp <<
336 }; <<
337 }; <<
338 <<
339 psci { 311 psci {
340 compatible = "arm,psci-1.0"; 312 compatible = "arm,psci-1.0";
341 method = "smc"; 313 method = "smc";
342 }; 314 };
343 315
344 rpm: remoteproc { !! 316 rpm-glink {
345 compatible = "qcom,msm8998-rpm !! 317 compatible = "qcom,glink-rpm";
>> 318
>> 319 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
>> 320 qcom,rpm-msg-ram = <&rpm_msg_ram>;
>> 321 mboxes = <&apcs_glb 0>;
>> 322
>> 323 rpm_requests: rpm-requests {
>> 324 compatible = "qcom,rpm-msm8998";
>> 325 qcom,glink-channels = "rpm_requests";
>> 326
>> 327 rpmcc: clock-controller {
>> 328 compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc";
>> 329 #clock-cells = <1>;
>> 330 };
346 331
347 glink-edge { !! 332 rpmpd: power-controller {
348 compatible = "qcom,gli !! 333 compatible = "qcom,msm8998-rpmpd";
>> 334 #power-domain-cells = <1>;
>> 335 operating-points-v2 = <&rpmpd_opp_table>;
>> 336
>> 337 rpmpd_opp_table: opp-table {
>> 338 compatible = "operating-points-v2";
349 339
350 interrupts = <GIC_SPI !! 340 rpmpd_opp_ret: opp1 {
351 qcom,rpm-msg-ram = <&r !! 341 opp-level = <RPM_SMD_LEVEL_RETENTION>;
352 mboxes = <&apcs_glb 0> !! 342 };
353 !! 343
354 rpm_requests: rpm-requ !! 344 rpmpd_opp_ret_plus: opp2 {
355 compatible = " !! 345 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
356 qcom,glink-cha !! 346 };
357 !! 347
358 rpmcc: clock-c !! 348 rpmpd_opp_min_svs: opp3 {
359 compat !! 349 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
360 clocks !! 350 };
361 clock- !! 351
362 #clock !! 352 rpmpd_opp_low_svs: opp4 {
363 }; !! 353 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
364 !! 354 };
365 rpmpd: power-c !! 355
366 compat !! 356 rpmpd_opp_svs: opp5 {
367 #power !! 357 opp-level = <RPM_SMD_LEVEL_SVS>;
368 operat !! 358 };
369 !! 359
370 rpmpd_ !! 360 rpmpd_opp_svs_plus: opp6 {
371 !! 361 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
372 !! 362 };
373 !! 363
374 !! 364 rpmpd_opp_nom: opp7 {
375 !! 365 opp-level = <RPM_SMD_LEVEL_NOM>;
376 !! 366 };
377 !! 367
378 !! 368 rpmpd_opp_nom_plus: opp8 {
379 !! 369 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
380 !! 370 };
381 !! 371
382 !! 372 rpmpd_opp_turbo: opp9 {
383 !! 373 opp-level = <RPM_SMD_LEVEL_TURBO>;
384 !! 374 };
385 !! 375
386 !! 376 rpmpd_opp_turbo_plus: opp10 {
387 !! 377 opp-level = <RPM_SMD_LEVEL_BINNING>;
388 <<
389 <<
390 <<
391 <<
392 <<
393 <<
394 <<
395 <<
396 <<
397 <<
398 <<
399 <<
400 <<
401 <<
402 <<
403 <<
404 <<
405 <<
406 <<
407 <<
408 <<
409 <<
410 <<
411 <<
412 }; 378 };
413 }; 379 };
414 }; 380 };
415 }; 381 };
416 }; 382 };
417 383
418 smem { 384 smem {
419 compatible = "qcom,smem"; 385 compatible = "qcom,smem";
420 memory-region = <&smem_mem>; 386 memory-region = <&smem_mem>;
421 hwlocks = <&tcsr_mutex 3>; 387 hwlocks = <&tcsr_mutex 3>;
422 }; 388 };
423 389
424 smp2p-lpass { 390 smp2p-lpass {
425 compatible = "qcom,smp2p"; 391 compatible = "qcom,smp2p";
426 qcom,smem = <443>, <429>; 392 qcom,smem = <443>, <429>;
427 393
428 interrupts = <GIC_SPI 158 IRQ_ 394 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
429 395
430 mboxes = <&apcs_glb 10>; 396 mboxes = <&apcs_glb 10>;
431 397
432 qcom,local-pid = <0>; 398 qcom,local-pid = <0>;
433 qcom,remote-pid = <2>; 399 qcom,remote-pid = <2>;
434 400
435 adsp_smp2p_out: master-kernel 401 adsp_smp2p_out: master-kernel {
436 qcom,entry-name = "mas 402 qcom,entry-name = "master-kernel";
437 #qcom,smem-state-cells 403 #qcom,smem-state-cells = <1>;
438 }; 404 };
439 405
440 adsp_smp2p_in: slave-kernel { 406 adsp_smp2p_in: slave-kernel {
441 qcom,entry-name = "sla 407 qcom,entry-name = "slave-kernel";
442 408
443 interrupt-controller; 409 interrupt-controller;
444 #interrupt-cells = <2> 410 #interrupt-cells = <2>;
445 }; 411 };
446 }; 412 };
447 413
448 smp2p-mpss { 414 smp2p-mpss {
449 compatible = "qcom,smp2p"; 415 compatible = "qcom,smp2p";
450 qcom,smem = <435>, <428>; 416 qcom,smem = <435>, <428>;
451 interrupts = <GIC_SPI 451 IRQ_ 417 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
452 mboxes = <&apcs_glb 14>; 418 mboxes = <&apcs_glb 14>;
453 qcom,local-pid = <0>; 419 qcom,local-pid = <0>;
454 qcom,remote-pid = <1>; 420 qcom,remote-pid = <1>;
455 421
456 modem_smp2p_out: master-kernel 422 modem_smp2p_out: master-kernel {
457 qcom,entry-name = "mas 423 qcom,entry-name = "master-kernel";
458 #qcom,smem-state-cells 424 #qcom,smem-state-cells = <1>;
459 }; 425 };
460 426
461 modem_smp2p_in: slave-kernel { 427 modem_smp2p_in: slave-kernel {
462 qcom,entry-name = "sla 428 qcom,entry-name = "slave-kernel";
463 interrupt-controller; 429 interrupt-controller;
464 #interrupt-cells = <2> 430 #interrupt-cells = <2>;
465 }; 431 };
466 }; 432 };
467 433
468 smp2p-slpi { 434 smp2p-slpi {
469 compatible = "qcom,smp2p"; 435 compatible = "qcom,smp2p";
470 qcom,smem = <481>, <430>; 436 qcom,smem = <481>, <430>;
471 interrupts = <GIC_SPI 178 IRQ_ 437 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
472 mboxes = <&apcs_glb 26>; 438 mboxes = <&apcs_glb 26>;
473 qcom,local-pid = <0>; 439 qcom,local-pid = <0>;
474 qcom,remote-pid = <3>; 440 qcom,remote-pid = <3>;
475 441
476 slpi_smp2p_out: master-kernel 442 slpi_smp2p_out: master-kernel {
477 qcom,entry-name = "mas 443 qcom,entry-name = "master-kernel";
478 #qcom,smem-state-cells 444 #qcom,smem-state-cells = <1>;
479 }; 445 };
480 446
481 slpi_smp2p_in: slave-kernel { 447 slpi_smp2p_in: slave-kernel {
482 qcom,entry-name = "sla 448 qcom,entry-name = "slave-kernel";
483 interrupt-controller; 449 interrupt-controller;
484 #interrupt-cells = <2> 450 #interrupt-cells = <2>;
485 }; 451 };
486 }; 452 };
487 453
488 thermal-zones { 454 thermal-zones {
489 cpu0-thermal { 455 cpu0-thermal {
490 polling-delay-passive 456 polling-delay-passive = <250>;
>> 457 polling-delay = <1000>;
491 458
492 thermal-sensors = <&ts 459 thermal-sensors = <&tsens0 1>;
493 460
494 trips { 461 trips {
495 cpu0_alert0: t 462 cpu0_alert0: trip-point0 {
496 temper 463 temperature = <75000>;
497 hyster 464 hysteresis = <2000>;
498 type = 465 type = "passive";
499 }; 466 };
500 467
501 cpu0_crit: cpu !! 468 cpu0_crit: cpu_crit {
502 temper 469 temperature = <110000>;
503 hyster 470 hysteresis = <2000>;
504 type = 471 type = "critical";
505 }; 472 };
506 }; 473 };
507 }; 474 };
508 475
509 cpu1-thermal { 476 cpu1-thermal {
510 polling-delay-passive 477 polling-delay-passive = <250>;
>> 478 polling-delay = <1000>;
511 479
512 thermal-sensors = <&ts 480 thermal-sensors = <&tsens0 2>;
513 481
514 trips { 482 trips {
515 cpu1_alert0: t 483 cpu1_alert0: trip-point0 {
516 temper 484 temperature = <75000>;
517 hyster 485 hysteresis = <2000>;
518 type = 486 type = "passive";
519 }; 487 };
520 488
521 cpu1_crit: cpu !! 489 cpu1_crit: cpu_crit {
522 temper 490 temperature = <110000>;
523 hyster 491 hysteresis = <2000>;
524 type = 492 type = "critical";
525 }; 493 };
526 }; 494 };
527 }; 495 };
528 496
529 cpu2-thermal { 497 cpu2-thermal {
530 polling-delay-passive 498 polling-delay-passive = <250>;
>> 499 polling-delay = <1000>;
531 500
532 thermal-sensors = <&ts 501 thermal-sensors = <&tsens0 3>;
533 502
534 trips { 503 trips {
535 cpu2_alert0: t 504 cpu2_alert0: trip-point0 {
536 temper 505 temperature = <75000>;
537 hyster 506 hysteresis = <2000>;
538 type = 507 type = "passive";
539 }; 508 };
540 509
541 cpu2_crit: cpu !! 510 cpu2_crit: cpu_crit {
542 temper 511 temperature = <110000>;
543 hyster 512 hysteresis = <2000>;
544 type = 513 type = "critical";
545 }; 514 };
546 }; 515 };
547 }; 516 };
548 517
549 cpu3-thermal { 518 cpu3-thermal {
550 polling-delay-passive 519 polling-delay-passive = <250>;
>> 520 polling-delay = <1000>;
551 521
552 thermal-sensors = <&ts 522 thermal-sensors = <&tsens0 4>;
553 523
554 trips { 524 trips {
555 cpu3_alert0: t 525 cpu3_alert0: trip-point0 {
556 temper 526 temperature = <75000>;
557 hyster 527 hysteresis = <2000>;
558 type = 528 type = "passive";
559 }; 529 };
560 530
561 cpu3_crit: cpu !! 531 cpu3_crit: cpu_crit {
562 temper 532 temperature = <110000>;
563 hyster 533 hysteresis = <2000>;
564 type = 534 type = "critical";
565 }; 535 };
566 }; 536 };
567 }; 537 };
568 538
569 cpu4-thermal { 539 cpu4-thermal {
570 polling-delay-passive 540 polling-delay-passive = <250>;
>> 541 polling-delay = <1000>;
571 542
572 thermal-sensors = <&ts 543 thermal-sensors = <&tsens0 7>;
573 544
574 trips { 545 trips {
575 cpu4_alert0: t 546 cpu4_alert0: trip-point0 {
576 temper 547 temperature = <75000>;
577 hyster 548 hysteresis = <2000>;
578 type = 549 type = "passive";
579 }; 550 };
580 551
581 cpu4_crit: cpu !! 552 cpu4_crit: cpu_crit {
582 temper 553 temperature = <110000>;
583 hyster 554 hysteresis = <2000>;
584 type = 555 type = "critical";
585 }; 556 };
586 }; 557 };
587 }; 558 };
588 559
589 cpu5-thermal { 560 cpu5-thermal {
590 polling-delay-passive 561 polling-delay-passive = <250>;
>> 562 polling-delay = <1000>;
591 563
592 thermal-sensors = <&ts 564 thermal-sensors = <&tsens0 8>;
593 565
594 trips { 566 trips {
595 cpu5_alert0: t 567 cpu5_alert0: trip-point0 {
596 temper 568 temperature = <75000>;
597 hyster 569 hysteresis = <2000>;
598 type = 570 type = "passive";
599 }; 571 };
600 572
601 cpu5_crit: cpu !! 573 cpu5_crit: cpu_crit {
602 temper 574 temperature = <110000>;
603 hyster 575 hysteresis = <2000>;
604 type = 576 type = "critical";
605 }; 577 };
606 }; 578 };
607 }; 579 };
608 580
609 cpu6-thermal { 581 cpu6-thermal {
610 polling-delay-passive 582 polling-delay-passive = <250>;
>> 583 polling-delay = <1000>;
611 584
612 thermal-sensors = <&ts 585 thermal-sensors = <&tsens0 9>;
613 586
614 trips { 587 trips {
615 cpu6_alert0: t 588 cpu6_alert0: trip-point0 {
616 temper 589 temperature = <75000>;
617 hyster 590 hysteresis = <2000>;
618 type = 591 type = "passive";
619 }; 592 };
620 593
621 cpu6_crit: cpu !! 594 cpu6_crit: cpu_crit {
622 temper 595 temperature = <110000>;
623 hyster 596 hysteresis = <2000>;
624 type = 597 type = "critical";
625 }; 598 };
626 }; 599 };
627 }; 600 };
628 601
629 cpu7-thermal { 602 cpu7-thermal {
630 polling-delay-passive 603 polling-delay-passive = <250>;
>> 604 polling-delay = <1000>;
631 605
632 thermal-sensors = <&ts 606 thermal-sensors = <&tsens0 10>;
633 607
634 trips { 608 trips {
635 cpu7_alert0: t 609 cpu7_alert0: trip-point0 {
636 temper 610 temperature = <75000>;
637 hyster 611 hysteresis = <2000>;
638 type = 612 type = "passive";
639 }; 613 };
640 614
641 cpu7_crit: cpu !! 615 cpu7_crit: cpu_crit {
642 temper 616 temperature = <110000>;
643 hyster 617 hysteresis = <2000>;
644 type = 618 type = "critical";
645 }; 619 };
646 }; 620 };
647 }; 621 };
648 622
649 gpu-bottom-thermal { 623 gpu-bottom-thermal {
650 polling-delay-passive 624 polling-delay-passive = <250>;
>> 625 polling-delay = <1000>;
651 626
652 thermal-sensors = <&ts 627 thermal-sensors = <&tsens0 12>;
653 628
654 trips { 629 trips {
655 gpu1_alert0: t 630 gpu1_alert0: trip-point0 {
656 temper 631 temperature = <90000>;
657 hyster 632 hysteresis = <2000>;
658 type = 633 type = "hot";
659 }; 634 };
660 }; 635 };
661 }; 636 };
662 637
663 gpu-top-thermal { 638 gpu-top-thermal {
664 polling-delay-passive 639 polling-delay-passive = <250>;
>> 640 polling-delay = <1000>;
665 641
666 thermal-sensors = <&ts 642 thermal-sensors = <&tsens0 13>;
667 643
668 trips { 644 trips {
669 gpu2_alert0: t 645 gpu2_alert0: trip-point0 {
670 temper 646 temperature = <90000>;
671 hyster 647 hysteresis = <2000>;
672 type = 648 type = "hot";
673 }; 649 };
674 }; 650 };
675 }; 651 };
676 652
677 clust0-mhm-thermal { 653 clust0-mhm-thermal {
678 polling-delay-passive 654 polling-delay-passive = <250>;
>> 655 polling-delay = <1000>;
679 656
680 thermal-sensors = <&ts 657 thermal-sensors = <&tsens0 5>;
681 658
682 trips { 659 trips {
683 cluster0_mhm_a 660 cluster0_mhm_alert0: trip-point0 {
684 temper 661 temperature = <90000>;
685 hyster 662 hysteresis = <2000>;
686 type = 663 type = "hot";
687 }; 664 };
688 }; 665 };
689 }; 666 };
690 667
691 clust1-mhm-thermal { 668 clust1-mhm-thermal {
692 polling-delay-passive 669 polling-delay-passive = <250>;
>> 670 polling-delay = <1000>;
693 671
694 thermal-sensors = <&ts 672 thermal-sensors = <&tsens0 6>;
695 673
696 trips { 674 trips {
697 cluster1_mhm_a 675 cluster1_mhm_alert0: trip-point0 {
698 temper 676 temperature = <90000>;
699 hyster 677 hysteresis = <2000>;
700 type = 678 type = "hot";
701 }; 679 };
702 }; 680 };
703 }; 681 };
704 682
705 cluster1-l2-thermal { 683 cluster1-l2-thermal {
706 polling-delay-passive 684 polling-delay-passive = <250>;
>> 685 polling-delay = <1000>;
707 686
708 thermal-sensors = <&ts 687 thermal-sensors = <&tsens0 11>;
709 688
710 trips { 689 trips {
711 cluster1_l2_al 690 cluster1_l2_alert0: trip-point0 {
712 temper 691 temperature = <90000>;
713 hyster 692 hysteresis = <2000>;
714 type = 693 type = "hot";
715 }; 694 };
716 }; 695 };
717 }; 696 };
718 697
719 modem-thermal { 698 modem-thermal {
720 polling-delay-passive 699 polling-delay-passive = <250>;
>> 700 polling-delay = <1000>;
721 701
722 thermal-sensors = <&ts 702 thermal-sensors = <&tsens1 1>;
723 703
724 trips { 704 trips {
725 modem_alert0: 705 modem_alert0: trip-point0 {
726 temper 706 temperature = <90000>;
727 hyster 707 hysteresis = <2000>;
728 type = 708 type = "hot";
729 }; 709 };
730 }; 710 };
731 }; 711 };
732 712
733 mem-thermal { 713 mem-thermal {
734 polling-delay-passive 714 polling-delay-passive = <250>;
>> 715 polling-delay = <1000>;
735 716
736 thermal-sensors = <&ts 717 thermal-sensors = <&tsens1 2>;
737 718
738 trips { 719 trips {
739 mem_alert0: tr 720 mem_alert0: trip-point0 {
740 temper 721 temperature = <90000>;
741 hyster 722 hysteresis = <2000>;
742 type = 723 type = "hot";
743 }; 724 };
744 }; 725 };
745 }; 726 };
746 727
747 wlan-thermal { 728 wlan-thermal {
748 polling-delay-passive 729 polling-delay-passive = <250>;
>> 730 polling-delay = <1000>;
749 731
750 thermal-sensors = <&ts 732 thermal-sensors = <&tsens1 3>;
751 733
752 trips { 734 trips {
753 wlan_alert0: t 735 wlan_alert0: trip-point0 {
754 temper 736 temperature = <90000>;
755 hyster 737 hysteresis = <2000>;
756 type = 738 type = "hot";
757 }; 739 };
758 }; 740 };
759 }; 741 };
760 742
761 q6-dsp-thermal { 743 q6-dsp-thermal {
762 polling-delay-passive 744 polling-delay-passive = <250>;
>> 745 polling-delay = <1000>;
763 746
764 thermal-sensors = <&ts 747 thermal-sensors = <&tsens1 4>;
765 748
766 trips { 749 trips {
767 q6_dsp_alert0: 750 q6_dsp_alert0: trip-point0 {
768 temper 751 temperature = <90000>;
769 hyster 752 hysteresis = <2000>;
770 type = 753 type = "hot";
771 }; 754 };
772 }; 755 };
773 }; 756 };
774 757
775 camera-thermal { 758 camera-thermal {
776 polling-delay-passive 759 polling-delay-passive = <250>;
>> 760 polling-delay = <1000>;
777 761
778 thermal-sensors = <&ts 762 thermal-sensors = <&tsens1 5>;
779 763
780 trips { 764 trips {
781 camera_alert0: 765 camera_alert0: trip-point0 {
782 temper 766 temperature = <90000>;
783 hyster 767 hysteresis = <2000>;
784 type = 768 type = "hot";
785 }; 769 };
786 }; 770 };
787 }; 771 };
788 772
789 multimedia-thermal { 773 multimedia-thermal {
790 polling-delay-passive 774 polling-delay-passive = <250>;
>> 775 polling-delay = <1000>;
791 776
792 thermal-sensors = <&ts 777 thermal-sensors = <&tsens1 6>;
793 778
794 trips { 779 trips {
795 multimedia_ale 780 multimedia_alert0: trip-point0 {
796 temper 781 temperature = <90000>;
797 hyster 782 hysteresis = <2000>;
798 type = 783 type = "hot";
799 }; 784 };
800 }; 785 };
801 }; 786 };
802 }; 787 };
803 788
804 timer { 789 timer {
805 compatible = "arm,armv8-timer" 790 compatible = "arm,armv8-timer";
806 interrupts = <GIC_PPI 1 IRQ_TY 791 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
807 <GIC_PPI 2 IRQ_TY 792 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
808 <GIC_PPI 3 IRQ_TY 793 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
809 <GIC_PPI 0 IRQ_TY 794 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
810 }; 795 };
811 796
812 soc: soc@0 { !! 797 soc: soc {
813 #address-cells = <1>; 798 #address-cells = <1>;
814 #size-cells = <1>; 799 #size-cells = <1>;
815 ranges = <0 0 0 0xffffffff>; 800 ranges = <0 0 0 0xffffffff>;
816 compatible = "simple-bus"; 801 compatible = "simple-bus";
817 802
818 gcc: clock-controller@100000 { 803 gcc: clock-controller@100000 {
819 compatible = "qcom,gcc 804 compatible = "qcom,gcc-msm8998";
820 #clock-cells = <1>; 805 #clock-cells = <1>;
821 #reset-cells = <1>; 806 #reset-cells = <1>;
822 #power-domain-cells = 807 #power-domain-cells = <1>;
823 reg = <0x00100000 0xb0 808 reg = <0x00100000 0xb0000>;
824 809
825 clock-names = "xo", "s 810 clock-names = "xo", "sleep_clk";
826 clocks = <&rpmcc RPM_S !! 811 clocks = <&xo>, <&sleep_clk>;
827 812
828 /* 813 /*
829 * The hypervisor typi 814 * The hypervisor typically configures the memory region where these clocks
830 * reside as read-only 815 * reside as read-only for the HLOS. If the HLOS tried to enable or disable
831 * these clocks on a d 816 * these clocks on a device with such configuration (e.g. because they are
832 * enabled but unused 817 * enabled but unused during boot-up), the device will most likely decide
833 * to reboot. 818 * to reboot.
834 * In light of that, w 819 * In light of that, we are conservative here and we list all such clocks
835 * as protected. The b 820 * as protected. The board dts (or a user-supplied dts) can override the
836 * list of protected c 821 * list of protected clocks if it differs from the norm, and it is in fact
837 * desired for the HLO 822 * desired for the HLOS to manage these clocks
838 */ 823 */
839 protected-clocks = <AG 824 protected-clocks = <AGGRE2_SNOC_NORTH_AXI>,
840 <SS 825 <SSC_XO>,
841 <SS 826 <SSC_CNOC_AHBS_CLK>;
842 }; 827 };
843 828
844 rpm_msg_ram: sram@778000 { 829 rpm_msg_ram: sram@778000 {
845 compatible = "qcom,rpm 830 compatible = "qcom,rpm-msg-ram";
846 reg = <0x00778000 0x70 831 reg = <0x00778000 0x7000>;
847 }; 832 };
848 833
849 qfprom: qfprom@784000 { 834 qfprom: qfprom@784000 {
850 compatible = "qcom,msm 835 compatible = "qcom,msm8998-qfprom", "qcom,qfprom";
851 reg = <0x00784000 0x62 836 reg = <0x00784000 0x621c>;
852 #address-cells = <1>; 837 #address-cells = <1>;
853 #size-cells = <1>; 838 #size-cells = <1>;
854 839
855 qusb2_hstx_trim: hstx- 840 qusb2_hstx_trim: hstx-trim@23a {
856 reg = <0x23a 0 841 reg = <0x23a 0x1>;
857 bits = <0 4>; 842 bits = <0 4>;
858 }; 843 };
859 }; 844 };
860 845
861 tsens0: thermal@10ab000 { 846 tsens0: thermal@10ab000 {
862 compatible = "qcom,msm 847 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
863 reg = <0x010ab000 0x10 848 reg = <0x010ab000 0x1000>, /* TM */
864 <0x010aa000 0x10 849 <0x010aa000 0x1000>; /* SROT */
865 #qcom,sensors = <14>; 850 #qcom,sensors = <14>;
866 interrupts = <GIC_SPI 851 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
867 <GIC_SPI 852 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
868 interrupt-names = "upl 853 interrupt-names = "uplow", "critical";
869 #thermal-sensor-cells 854 #thermal-sensor-cells = <1>;
870 }; 855 };
871 856
872 tsens1: thermal@10ae000 { 857 tsens1: thermal@10ae000 {
873 compatible = "qcom,msm 858 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
874 reg = <0x010ae000 0x10 859 reg = <0x010ae000 0x1000>, /* TM */
875 <0x010ad000 0x10 860 <0x010ad000 0x1000>; /* SROT */
876 #qcom,sensors = <8>; 861 #qcom,sensors = <8>;
877 interrupts = <GIC_SPI 862 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
878 <GIC_SPI 863 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
879 interrupt-names = "upl 864 interrupt-names = "uplow", "critical";
880 #thermal-sensor-cells 865 #thermal-sensor-cells = <1>;
881 }; 866 };
882 867
883 anoc1_smmu: iommu@1680000 { 868 anoc1_smmu: iommu@1680000 {
884 compatible = "qcom,msm 869 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
885 reg = <0x01680000 0x10 870 reg = <0x01680000 0x10000>;
886 #iommu-cells = <1>; 871 #iommu-cells = <1>;
887 872
888 #global-interrupts = < 873 #global-interrupts = <0>;
889 interrupts = 874 interrupts =
890 <GIC_SPI 364 I 875 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
891 <GIC_SPI 365 I 876 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
892 <GIC_SPI 366 I 877 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
893 <GIC_SPI 367 I 878 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
894 <GIC_SPI 368 I 879 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
895 <GIC_SPI 369 I 880 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>;
896 }; 881 };
897 882
898 anoc2_smmu: iommu@16c0000 { 883 anoc2_smmu: iommu@16c0000 {
899 compatible = "qcom,msm 884 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
900 reg = <0x016c0000 0x40 885 reg = <0x016c0000 0x40000>;
901 #iommu-cells = <1>; 886 #iommu-cells = <1>;
902 887
903 #global-interrupts = < 888 #global-interrupts = <0>;
904 interrupts = 889 interrupts =
905 <GIC_SPI 373 I 890 <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>,
906 <GIC_SPI 374 I 891 <GIC_SPI 374 IRQ_TYPE_EDGE_RISING>,
907 <GIC_SPI 375 I 892 <GIC_SPI 375 IRQ_TYPE_EDGE_RISING>,
908 <GIC_SPI 376 I 893 <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>,
909 <GIC_SPI 377 I 894 <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>,
910 <GIC_SPI 378 I 895 <GIC_SPI 378 IRQ_TYPE_EDGE_RISING>,
911 <GIC_SPI 462 I 896 <GIC_SPI 462 IRQ_TYPE_EDGE_RISING>,
912 <GIC_SPI 463 I 897 <GIC_SPI 463 IRQ_TYPE_EDGE_RISING>,
913 <GIC_SPI 464 I 898 <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
914 <GIC_SPI 465 I 899 <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>;
915 }; 900 };
916 901
917 pcie0: pcie@1c00000 { !! 902 pcie0: pci@1c00000 {
918 compatible = "qcom,pci 903 compatible = "qcom,pcie-msm8998", "qcom,pcie-msm8996";
919 reg = <0x01c00000 0x20 !! 904 reg = <0x01c00000 0x2000>,
920 <0x1b000000 0xf1 !! 905 <0x1b000000 0xf1d>,
921 <0x1b000f20 0xa8 !! 906 <0x1b000f20 0xa8>,
922 <0x1b100000 0x10 !! 907 <0x1b100000 0x100000>;
923 reg-names = "parf", "d 908 reg-names = "parf", "dbi", "elbi", "config";
924 device_type = "pci"; 909 device_type = "pci";
925 linux,pci-domain = <0> 910 linux,pci-domain = <0>;
926 bus-range = <0x00 0xff 911 bus-range = <0x00 0xff>;
927 #address-cells = <3>; 912 #address-cells = <3>;
928 #size-cells = <2>; 913 #size-cells = <2>;
929 num-lanes = <1>; 914 num-lanes = <1>;
930 phys = <&pcie_phy>; !! 915 phys = <&pciephy>;
931 phy-names = "pciephy"; 916 phy-names = "pciephy";
932 status = "disabled"; 917 status = "disabled";
933 918
934 ranges = <0x01000000 0 919 ranges = <0x01000000 0x0 0x00000000 0x1b200000 0x0 0x100000>,
935 <0x02000000 0 920 <0x02000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>;
936 921
937 #interrupt-cells = <1> 922 #interrupt-cells = <1>;
938 interrupts = <GIC_SPI 923 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
939 interrupt-names = "msi 924 interrupt-names = "msi";
940 interrupt-map-mask = < 925 interrupt-map-mask = <0 0 0 0x7>;
941 interrupt-map = <0 0 0 926 interrupt-map = <0 0 0 1 &intc 0 0 135 IRQ_TYPE_LEVEL_HIGH>,
942 <0 0 0 927 <0 0 0 2 &intc 0 0 136 IRQ_TYPE_LEVEL_HIGH>,
943 <0 0 0 928 <0 0 0 3 &intc 0 0 138 IRQ_TYPE_LEVEL_HIGH>,
944 <0 0 0 929 <0 0 0 4 &intc 0 0 139 IRQ_TYPE_LEVEL_HIGH>;
945 930
946 clocks = <&gcc GCC_PCI 931 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
947 <&gcc GCC_PCI 932 <&gcc GCC_PCIE_0_AUX_CLK>,
948 <&gcc GCC_PCI 933 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
949 <&gcc GCC_PCI 934 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
950 <&gcc GCC_PCI 935 <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
951 clock-names = "pipe", 936 clock-names = "pipe", "aux", "cfg", "bus_master", "bus_slave";
952 937
953 power-domains = <&gcc 938 power-domains = <&gcc PCIE_0_GDSC>;
954 iommu-map = <0x100 &an 939 iommu-map = <0x100 &anoc1_smmu 0x1480 1>;
955 perst-gpios = <&tlmm 3 940 perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
956 <<
957 pcie@0 { <<
958 device_type = <<
959 reg = <0x0 0x0 <<
960 bus-range = <0 <<
961 <<
962 #address-cells <<
963 #size-cells = <<
964 ranges; <<
965 }; <<
966 }; 941 };
967 942
968 pcie_phy: phy@1c06000 { 943 pcie_phy: phy@1c06000 {
969 compatible = "qcom,msm 944 compatible = "qcom,msm8998-qmp-pcie-phy";
970 reg = <0x01c06000 0x10 !! 945 reg = <0x01c06000 0x18c>;
>> 946 #address-cells = <1>;
>> 947 #size-cells = <1>;
971 status = "disabled"; 948 status = "disabled";
>> 949 ranges;
972 950
973 clocks = <&gcc GCC_PCI 951 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
974 <&gcc GCC_PCI 952 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
975 <&gcc GCC_PCI !! 953 <&gcc GCC_PCIE_CLKREF_CLK>;
976 <&gcc GCC_PCI !! 954 clock-names = "aux", "cfg_ahb", "ref";
977 clock-names = "aux", <<
978 "cfg_ahb <<
979 "ref", <<
980 "pipe"; <<
981 <<
982 clock-output-names = " <<
983 #clock-cells = <0>; <<
984 <<
985 #phy-cells = <0>; <<
986 955
987 resets = <&gcc GCC_PCI 956 resets = <&gcc GCC_PCIE_0_PHY_BCR>, <&gcc GCC_PCIE_PHY_BCR>;
988 reset-names = "phy", " 957 reset-names = "phy", "common";
989 958
990 vdda-phy-supply = <&vr 959 vdda-phy-supply = <&vreg_l1a_0p875>;
991 vdda-pll-supply = <&vr 960 vdda-pll-supply = <&vreg_l2a_1p2>;
>> 961
>> 962 pciephy: phy@1c06800 {
>> 963 reg = <0x01c06200 0x128>, <0x01c06400 0x1fc>, <0x01c06800 0x20c>;
>> 964 #phy-cells = <0>;
>> 965
>> 966 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
>> 967 clock-names = "pipe0";
>> 968 clock-output-names = "pcie_0_pipe_clk_src";
>> 969 #clock-cells = <0>;
>> 970 };
992 }; 971 };
993 972
994 ufshc: ufshc@1da4000 { 973 ufshc: ufshc@1da4000 {
995 compatible = "qcom,msm 974 compatible = "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
996 reg = <0x01da4000 0x25 975 reg = <0x01da4000 0x2500>;
997 interrupts = <GIC_SPI 976 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
998 phys = <&ufsphy>; !! 977 phys = <&ufsphy_lanes>;
999 phy-names = "ufsphy"; 978 phy-names = "ufsphy";
1000 lanes-per-direction = 979 lanes-per-direction = <2>;
1001 power-domains = <&gcc 980 power-domains = <&gcc UFS_GDSC>;
1002 status = "disabled"; 981 status = "disabled";
1003 #reset-cells = <1>; 982 #reset-cells = <1>;
1004 983
1005 clock-names = 984 clock-names =
1006 "core_clk", 985 "core_clk",
1007 "bus_aggr_clk 986 "bus_aggr_clk",
1008 "iface_clk", 987 "iface_clk",
1009 "core_clk_uni 988 "core_clk_unipro",
1010 "ref_clk", 989 "ref_clk",
1011 "tx_lane0_syn 990 "tx_lane0_sync_clk",
1012 "rx_lane0_syn 991 "rx_lane0_sync_clk",
1013 "rx_lane1_syn 992 "rx_lane1_sync_clk";
1014 clocks = 993 clocks =
1015 <&gcc GCC_UFS 994 <&gcc GCC_UFS_AXI_CLK>,
1016 <&gcc GCC_AGG 995 <&gcc GCC_AGGRE1_UFS_AXI_CLK>,
1017 <&gcc GCC_UFS 996 <&gcc GCC_UFS_AHB_CLK>,
1018 <&gcc GCC_UFS 997 <&gcc GCC_UFS_UNIPRO_CORE_CLK>,
1019 <&rpmcc RPM_S 998 <&rpmcc RPM_SMD_LN_BB_CLK1>,
1020 <&gcc GCC_UFS 999 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
1021 <&gcc GCC_UFS 1000 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>,
1022 <&gcc GCC_UFS 1001 <&gcc GCC_UFS_RX_SYMBOL_1_CLK>;
1023 freq-table-hz = 1002 freq-table-hz =
1024 <50000000 200 1003 <50000000 200000000>,
1025 <0 0>, 1004 <0 0>,
1026 <0 0>, 1005 <0 0>,
1027 <37500000 150 1006 <37500000 150000000>,
1028 <0 0>, 1007 <0 0>,
1029 <0 0>, 1008 <0 0>,
1030 <0 0>, 1009 <0 0>,
1031 <0 0>; 1010 <0 0>;
1032 1011
1033 resets = <&gcc GCC_UF 1012 resets = <&gcc GCC_UFS_BCR>;
1034 reset-names = "rst"; 1013 reset-names = "rst";
1035 }; 1014 };
1036 1015
1037 ufsphy: phy@1da7000 { 1016 ufsphy: phy@1da7000 {
1038 compatible = "qcom,ms 1017 compatible = "qcom,msm8998-qmp-ufs-phy";
1039 reg = <0x01da7000 0x1 !! 1018 reg = <0x01da7000 0x18c>;
>> 1019 #address-cells = <1>;
>> 1020 #size-cells = <1>;
>> 1021 status = "disabled";
>> 1022 ranges;
1040 1023
1041 clocks = <&rpmcc RPM_ !! 1024 clock-names =
1042 <&gcc GCC_UF !! 1025 "ref",
1043 <&gcc GCC_UF !! 1026 "ref_aux";
1044 clock-names = "ref", !! 1027 clocks =
1045 "ref_au !! 1028 <&gcc GCC_UFS_CLKREF_CLK>,
1046 "qref"; !! 1029 <&gcc GCC_UFS_PHY_AUX_CLK>;
1047 1030
1048 reset-names = "ufsphy 1031 reset-names = "ufsphy";
1049 resets = <&ufshc 0>; 1032 resets = <&ufshc 0>;
1050 1033
1051 #phy-cells = <0>; !! 1034 ufsphy_lanes: phy@1da7400 {
1052 status = "disabled"; !! 1035 reg = <0x01da7400 0x128>,
>> 1036 <0x01da7600 0x1fc>,
>> 1037 <0x01da7c00 0x1dc>,
>> 1038 <0x01da7800 0x128>,
>> 1039 <0x01da7a00 0x1fc>;
>> 1040 #phy-cells = <0>;
>> 1041 };
1053 }; 1042 };
1054 1043
1055 tcsr_mutex: hwlock@1f40000 { 1044 tcsr_mutex: hwlock@1f40000 {
1056 compatible = "qcom,tc 1045 compatible = "qcom,tcsr-mutex";
1057 reg = <0x01f40000 0x2 1046 reg = <0x01f40000 0x20000>;
1058 #hwlock-cells = <1>; 1047 #hwlock-cells = <1>;
1059 }; 1048 };
1060 1049
1061 tcsr_regs_1: syscon@1f60000 { 1050 tcsr_regs_1: syscon@1f60000 {
1062 compatible = "qcom,ms 1051 compatible = "qcom,msm8998-tcsr", "syscon";
1063 reg = <0x01f60000 0x2 1052 reg = <0x01f60000 0x20000>;
1064 }; 1053 };
1065 1054
1066 tcsr_regs_2: syscon@1fc0000 { <<
1067 compatible = "qcom,ms <<
1068 reg = <0x01fc0000 0x2 <<
1069 }; <<
1070 <<
1071 tlmm: pinctrl@3400000 { 1055 tlmm: pinctrl@3400000 {
1072 compatible = "qcom,ms 1056 compatible = "qcom,msm8998-pinctrl";
1073 reg = <0x03400000 0xc 1057 reg = <0x03400000 0xc00000>;
1074 interrupts = <GIC_SPI 1058 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1075 gpio-ranges = <&tlmm 1059 gpio-ranges = <&tlmm 0 0 150>;
1076 gpio-controller; 1060 gpio-controller;
1077 #gpio-cells = <2>; 1061 #gpio-cells = <2>;
1078 interrupt-controller; 1062 interrupt-controller;
1079 #interrupt-cells = <2 1063 #interrupt-cells = <2>;
1080 1064
1081 sdc2_on: sdc2-on-stat 1065 sdc2_on: sdc2-on-state {
1082 clk-pins { 1066 clk-pins {
1083 pins 1067 pins = "sdc2_clk";
1084 drive 1068 drive-strength = <16>;
1085 bias- 1069 bias-disable;
1086 }; 1070 };
1087 1071
1088 cmd-pins { 1072 cmd-pins {
1089 pins 1073 pins = "sdc2_cmd";
1090 drive 1074 drive-strength = <10>;
1091 bias- 1075 bias-pull-up;
1092 }; 1076 };
1093 1077
1094 data-pins { 1078 data-pins {
1095 pins 1079 pins = "sdc2_data";
1096 drive 1080 drive-strength = <10>;
1097 bias- 1081 bias-pull-up;
1098 }; 1082 };
1099 }; 1083 };
1100 1084
1101 sdc2_off: sdc2-off-st 1085 sdc2_off: sdc2-off-state {
1102 clk-pins { 1086 clk-pins {
1103 pins 1087 pins = "sdc2_clk";
1104 drive 1088 drive-strength = <2>;
1105 bias- 1089 bias-disable;
1106 }; 1090 };
1107 1091
1108 cmd-pins { 1092 cmd-pins {
1109 pins 1093 pins = "sdc2_cmd";
1110 drive 1094 drive-strength = <2>;
1111 bias- 1095 bias-pull-up;
1112 }; 1096 };
1113 1097
1114 data-pins { 1098 data-pins {
1115 pins 1099 pins = "sdc2_data";
1116 drive 1100 drive-strength = <2>;
1117 bias- 1101 bias-pull-up;
1118 }; 1102 };
1119 }; 1103 };
1120 1104
1121 sdc2_cd: sdc2-cd-stat 1105 sdc2_cd: sdc2-cd-state {
1122 pins = "gpio9 1106 pins = "gpio95";
1123 function = "g 1107 function = "gpio";
1124 bias-pull-up; 1108 bias-pull-up;
1125 drive-strengt 1109 drive-strength = <2>;
1126 }; 1110 };
1127 1111
1128 blsp1_uart3_on: blsp1 1112 blsp1_uart3_on: blsp1-uart3-on-state {
1129 tx-pins { 1113 tx-pins {
1130 pins 1114 pins = "gpio45";
1131 funct 1115 function = "blsp_uart3_a";
1132 drive 1116 drive-strength = <2>;
1133 bias- 1117 bias-disable;
1134 }; 1118 };
1135 1119
1136 rx-pins { 1120 rx-pins {
1137 pins 1121 pins = "gpio46";
1138 funct 1122 function = "blsp_uart3_a";
1139 drive 1123 drive-strength = <2>;
1140 bias- 1124 bias-disable;
1141 }; 1125 };
1142 1126
1143 cts-pins { 1127 cts-pins {
1144 pins 1128 pins = "gpio47";
1145 funct 1129 function = "blsp_uart3_a";
1146 drive 1130 drive-strength = <2>;
1147 bias- 1131 bias-disable;
1148 }; 1132 };
1149 1133
1150 rfr-pins { 1134 rfr-pins {
1151 pins 1135 pins = "gpio48";
1152 funct 1136 function = "blsp_uart3_a";
1153 drive 1137 drive-strength = <2>;
1154 bias- 1138 bias-disable;
1155 }; 1139 };
1156 }; 1140 };
1157 1141
1158 blsp1_i2c1_default: b 1142 blsp1_i2c1_default: blsp1-i2c1-default-state {
1159 pins = "gpio2 1143 pins = "gpio2", "gpio3";
1160 function = "b 1144 function = "blsp_i2c1";
1161 drive-strengt 1145 drive-strength = <2>;
1162 bias-disable; 1146 bias-disable;
1163 }; 1147 };
1164 1148
1165 blsp1_i2c1_sleep: bls 1149 blsp1_i2c1_sleep: blsp1-i2c1-sleep-state-state {
1166 pins = "gpio2 1150 pins = "gpio2", "gpio3";
1167 function = "b 1151 function = "blsp_i2c1";
1168 drive-strengt 1152 drive-strength = <2>;
1169 bias-pull-up; 1153 bias-pull-up;
1170 }; 1154 };
1171 1155
1172 blsp1_i2c2_default: b 1156 blsp1_i2c2_default: blsp1-i2c2-default-state {
1173 pins = "gpio3 1157 pins = "gpio32", "gpio33";
1174 function = "b 1158 function = "blsp_i2c2";
1175 drive-strengt 1159 drive-strength = <2>;
1176 bias-disable; 1160 bias-disable;
1177 }; 1161 };
1178 1162
1179 blsp1_i2c2_sleep: bls 1163 blsp1_i2c2_sleep: blsp1-i2c2-sleep-state-state {
1180 pins = "gpio3 1164 pins = "gpio32", "gpio33";
1181 function = "b 1165 function = "blsp_i2c2";
1182 drive-strengt 1166 drive-strength = <2>;
1183 bias-pull-up; 1167 bias-pull-up;
1184 }; 1168 };
1185 1169
1186 blsp1_i2c3_default: b 1170 blsp1_i2c3_default: blsp1-i2c3-default-state {
1187 pins = "gpio4 1171 pins = "gpio47", "gpio48";
1188 function = "b 1172 function = "blsp_i2c3";
1189 drive-strengt 1173 drive-strength = <2>;
1190 bias-disable; 1174 bias-disable;
1191 }; 1175 };
1192 1176
1193 blsp1_i2c3_sleep: bls 1177 blsp1_i2c3_sleep: blsp1-i2c3-sleep-state {
1194 pins = "gpio4 1178 pins = "gpio47", "gpio48";
1195 function = "b 1179 function = "blsp_i2c3";
1196 drive-strengt 1180 drive-strength = <2>;
1197 bias-pull-up; 1181 bias-pull-up;
1198 }; 1182 };
1199 1183
1200 blsp1_i2c4_default: b 1184 blsp1_i2c4_default: blsp1-i2c4-default-state {
1201 pins = "gpio1 1185 pins = "gpio10", "gpio11";
1202 function = "b 1186 function = "blsp_i2c4";
1203 drive-strengt 1187 drive-strength = <2>;
1204 bias-disable; 1188 bias-disable;
1205 }; 1189 };
1206 1190
1207 blsp1_i2c4_sleep: bls 1191 blsp1_i2c4_sleep: blsp1-i2c4-sleep-state {
1208 pins = "gpio1 1192 pins = "gpio10", "gpio11";
1209 function = "b 1193 function = "blsp_i2c4";
1210 drive-strengt 1194 drive-strength = <2>;
1211 bias-pull-up; 1195 bias-pull-up;
1212 }; 1196 };
1213 1197
1214 blsp1_i2c5_default: b 1198 blsp1_i2c5_default: blsp1-i2c5-default-state {
1215 pins = "gpio8 1199 pins = "gpio87", "gpio88";
1216 function = "b 1200 function = "blsp_i2c5";
1217 drive-strengt 1201 drive-strength = <2>;
1218 bias-disable; 1202 bias-disable;
1219 }; 1203 };
1220 1204
1221 blsp1_i2c5_sleep: bls 1205 blsp1_i2c5_sleep: blsp1-i2c5-sleep-state {
1222 pins = "gpio8 1206 pins = "gpio87", "gpio88";
1223 function = "b 1207 function = "blsp_i2c5";
1224 drive-strengt 1208 drive-strength = <2>;
1225 bias-pull-up; 1209 bias-pull-up;
1226 }; 1210 };
1227 1211
1228 blsp1_i2c6_default: b 1212 blsp1_i2c6_default: blsp1-i2c6-default-state {
1229 pins = "gpio4 1213 pins = "gpio43", "gpio44";
1230 function = "b 1214 function = "blsp_i2c6";
1231 drive-strengt 1215 drive-strength = <2>;
1232 bias-disable; 1216 bias-disable;
1233 }; 1217 };
1234 1218
1235 blsp1_i2c6_sleep: bls 1219 blsp1_i2c6_sleep: blsp1-i2c6-sleep-state {
1236 pins = "gpio4 1220 pins = "gpio43", "gpio44";
1237 function = "b 1221 function = "blsp_i2c6";
1238 drive-strengt 1222 drive-strength = <2>;
1239 bias-pull-up; 1223 bias-pull-up;
1240 }; 1224 };
1241 <<
1242 blsp1_spi_b_default: <<
1243 pins = "gpio2 <<
1244 function = "b <<
1245 drive-strengt <<
1246 bias-disable; <<
1247 }; <<
1248 <<
1249 blsp1_spi1_default: b <<
1250 pins = "gpio0 <<
1251 function = "b <<
1252 drive-strengt <<
1253 bias-disable; <<
1254 }; <<
1255 <<
1256 blsp1_spi2_default: b <<
1257 pins = "gpio3 <<
1258 function = "b <<
1259 drive-strengt <<
1260 bias-disable; <<
1261 }; <<
1262 <<
1263 blsp1_spi3_default: b <<
1264 pins = "gpio4 <<
1265 function = "b <<
1266 drive-strengt <<
1267 bias-disable; <<
1268 }; <<
1269 <<
1270 blsp1_spi4_default: b <<
1271 pins = "gpio8 <<
1272 function = "b <<
1273 drive-strengt <<
1274 bias-disable; <<
1275 }; <<
1276 <<
1277 blsp1_spi5_default: b <<
1278 pins = "gpio8 <<
1279 function = "b <<
1280 drive-strengt <<
1281 bias-disable; <<
1282 }; <<
1283 <<
1284 blsp1_spi6_default: b <<
1285 pins = "gpio4 <<
1286 function = "b <<
1287 drive-strengt <<
1288 bias-disable; <<
1289 }; <<
1290 <<
1291 <<
1292 /* 6 interfaces per Q 1225 /* 6 interfaces per QUP, BLSP2 indexes are numbered (n)+6 */
1293 blsp2_i2c1_default: b 1226 blsp2_i2c1_default: blsp2-i2c1-default-state {
1294 pins = "gpio5 1227 pins = "gpio55", "gpio56";
1295 function = "b 1228 function = "blsp_i2c7";
1296 drive-strengt 1229 drive-strength = <2>;
1297 bias-disable; 1230 bias-disable;
1298 }; 1231 };
1299 1232
1300 blsp2_i2c1_sleep: bls 1233 blsp2_i2c1_sleep: blsp2-i2c1-sleep-state {
1301 pins = "gpio5 1234 pins = "gpio55", "gpio56";
1302 function = "b 1235 function = "blsp_i2c7";
1303 drive-strengt 1236 drive-strength = <2>;
1304 bias-pull-up; 1237 bias-pull-up;
1305 }; 1238 };
1306 1239
1307 blsp2_i2c2_default: b 1240 blsp2_i2c2_default: blsp2-i2c2-default-state {
1308 pins = "gpio6 1241 pins = "gpio6", "gpio7";
1309 function = "b 1242 function = "blsp_i2c8";
1310 drive-strengt 1243 drive-strength = <2>;
1311 bias-disable; 1244 bias-disable;
1312 }; 1245 };
1313 1246
1314 blsp2_i2c2_sleep: bls 1247 blsp2_i2c2_sleep: blsp2-i2c2-sleep-state {
1315 pins = "gpio6 1248 pins = "gpio6", "gpio7";
1316 function = "b 1249 function = "blsp_i2c8";
1317 drive-strengt 1250 drive-strength = <2>;
1318 bias-pull-up; 1251 bias-pull-up;
1319 }; 1252 };
1320 1253
1321 blsp2_i2c3_default: b 1254 blsp2_i2c3_default: blsp2-i2c3-default-state {
1322 pins = "gpio5 1255 pins = "gpio51", "gpio52";
1323 function = "b 1256 function = "blsp_i2c9";
1324 drive-strengt 1257 drive-strength = <2>;
1325 bias-disable; 1258 bias-disable;
1326 }; 1259 };
1327 1260
1328 blsp2_i2c3_sleep: bls 1261 blsp2_i2c3_sleep: blsp2-i2c3-sleep-state {
1329 pins = "gpio5 1262 pins = "gpio51", "gpio52";
1330 function = "b 1263 function = "blsp_i2c9";
1331 drive-strengt 1264 drive-strength = <2>;
1332 bias-pull-up; 1265 bias-pull-up;
1333 }; 1266 };
1334 1267
1335 blsp2_i2c4_default: b 1268 blsp2_i2c4_default: blsp2-i2c4-default-state {
1336 pins = "gpio6 1269 pins = "gpio67", "gpio68";
1337 function = "b 1270 function = "blsp_i2c10";
1338 drive-strengt 1271 drive-strength = <2>;
1339 bias-disable; 1272 bias-disable;
1340 }; 1273 };
1341 1274
1342 blsp2_i2c4_sleep: bls 1275 blsp2_i2c4_sleep: blsp2-i2c4-sleep-state {
1343 pins = "gpio6 1276 pins = "gpio67", "gpio68";
1344 function = "b 1277 function = "blsp_i2c10";
1345 drive-strengt 1278 drive-strength = <2>;
1346 bias-pull-up; 1279 bias-pull-up;
1347 }; 1280 };
1348 1281
1349 blsp2_i2c5_default: b 1282 blsp2_i2c5_default: blsp2-i2c5-default-state {
1350 pins = "gpio6 1283 pins = "gpio60", "gpio61";
1351 function = "b 1284 function = "blsp_i2c11";
1352 drive-strengt 1285 drive-strength = <2>;
1353 bias-disable; 1286 bias-disable;
1354 }; 1287 };
1355 1288
1356 blsp2_i2c5_sleep: bls 1289 blsp2_i2c5_sleep: blsp2-i2c5-sleep-state {
1357 pins = "gpio6 1290 pins = "gpio60", "gpio61";
1358 function = "b 1291 function = "blsp_i2c11";
1359 drive-strengt 1292 drive-strength = <2>;
1360 bias-pull-up; 1293 bias-pull-up;
1361 }; 1294 };
1362 1295
1363 blsp2_i2c6_default: b 1296 blsp2_i2c6_default: blsp2-i2c6-default-state {
1364 pins = "gpio8 1297 pins = "gpio83", "gpio84";
1365 function = "b 1298 function = "blsp_i2c12";
1366 drive-strengt 1299 drive-strength = <2>;
1367 bias-disable; 1300 bias-disable;
1368 }; 1301 };
1369 1302
1370 blsp2_i2c6_sleep: bls 1303 blsp2_i2c6_sleep: blsp2-i2c6-sleep-state {
1371 pins = "gpio8 1304 pins = "gpio83", "gpio84";
1372 function = "b 1305 function = "blsp_i2c12";
1373 drive-strengt 1306 drive-strength = <2>;
1374 bias-pull-up; 1307 bias-pull-up;
1375 }; 1308 };
1376 <<
1377 blsp2_spi1_default: b <<
1378 pins = "gpio5 <<
1379 function = "b <<
1380 drive-strengt <<
1381 bias-disable; <<
1382 }; <<
1383 <<
1384 blsp2_spi2_default: b <<
1385 pins = "gpio4 <<
1386 function = "b <<
1387 drive-strengt <<
1388 bias-disable; <<
1389 }; <<
1390 <<
1391 blsp2_spi3_default: b <<
1392 pins = "gpio4 <<
1393 function = "b <<
1394 drive-strengt <<
1395 bias-disable; <<
1396 }; <<
1397 <<
1398 blsp2_spi4_default: b <<
1399 pins = "gpio6 <<
1400 function = "b <<
1401 drive-strengt <<
1402 bias-disable; <<
1403 }; <<
1404 <<
1405 blsp2_spi5_default: b <<
1406 pins = "gpio5 <<
1407 function = "b <<
1408 drive-strengt <<
1409 bias-disable; <<
1410 }; <<
1411 <<
1412 blsp2_spi6_default: b <<
1413 pins = "gpio8 <<
1414 function = "b <<
1415 drive-strengt <<
1416 bias-disable; <<
1417 }; <<
1418 }; 1309 };
1419 1310
1420 remoteproc_mss: remoteproc@40 1311 remoteproc_mss: remoteproc@4080000 {
1421 compatible = "qcom,ms 1312 compatible = "qcom,msm8998-mss-pil";
1422 reg = <0x04080000 0x1 1313 reg = <0x04080000 0x100>, <0x04180000 0x20>;
1423 reg-names = "qdsp6", 1314 reg-names = "qdsp6", "rmb";
1424 1315
1425 interrupts-extended = 1316 interrupts-extended =
1426 <&intc GIC_SP 1317 <&intc GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
1427 <&modem_smp2p 1318 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1428 <&modem_smp2p 1319 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1429 <&modem_smp2p 1320 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1430 <&modem_smp2p 1321 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
1431 <&modem_smp2p 1322 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
1432 interrupt-names = "wd 1323 interrupt-names = "wdog", "fatal", "ready",
1433 "ha 1324 "handover", "stop-ack",
1434 "sh 1325 "shutdown-ack";
1435 1326
1436 clocks = <&gcc GCC_MS 1327 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
1437 <&gcc GCC_BI 1328 <&gcc GCC_BIMC_MSS_Q6_AXI_CLK>,
1438 <&gcc GCC_BO 1329 <&gcc GCC_BOOT_ROM_AHB_CLK>,
1439 <&gcc GCC_MS 1330 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
1440 <&gcc GCC_MS 1331 <&gcc GCC_MSS_SNOC_AXI_CLK>,
1441 <&gcc GCC_MS 1332 <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>,
1442 <&rpmcc RPM_ 1333 <&rpmcc RPM_SMD_QDSS_CLK>,
1443 <&rpmcc RPM_ 1334 <&rpmcc RPM_SMD_XO_CLK_SRC>;
1444 clock-names = "iface" 1335 clock-names = "iface", "bus", "mem", "gpll0_mss",
1445 "snoc_a 1336 "snoc_axi", "mnoc_axi", "qdss", "xo";
1446 1337
1447 qcom,smem-states = <& 1338 qcom,smem-states = <&modem_smp2p_out 0>;
1448 qcom,smem-state-names 1339 qcom,smem-state-names = "stop";
1449 1340
1450 resets = <&gcc GCC_MS 1341 resets = <&gcc GCC_MSS_RESTART>;
1451 reset-names = "mss_re 1342 reset-names = "mss_restart";
1452 1343
1453 qcom,halt-regs = <&tc 1344 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>;
1454 1345
1455 power-domains = <&rpm 1346 power-domains = <&rpmpd MSM8998_VDDCX>,
1456 <&rpm 1347 <&rpmpd MSM8998_VDDMX>;
1457 power-domain-names = 1348 power-domain-names = "cx", "mx";
1458 1349
1459 status = "disabled"; 1350 status = "disabled";
1460 1351
1461 mba { 1352 mba {
1462 memory-region 1353 memory-region = <&mba_mem>;
1463 }; 1354 };
1464 1355
1465 mpss { 1356 mpss {
1466 memory-region 1357 memory-region = <&mpss_mem>;
1467 }; 1358 };
1468 1359
1469 metadata { <<
1470 memory-region <<
1471 }; <<
1472 <<
1473 glink-edge { 1360 glink-edge {
1474 interrupts = 1361 interrupts = <GIC_SPI 452 IRQ_TYPE_EDGE_RISING>;
1475 label = "mode 1362 label = "modem";
1476 qcom,remote-p 1363 qcom,remote-pid = <1>;
1477 mboxes = <&ap 1364 mboxes = <&apcs_glb 15>;
1478 }; 1365 };
1479 }; 1366 };
1480 1367
1481 adreno_gpu: gpu@5000000 { 1368 adreno_gpu: gpu@5000000 {
1482 compatible = "qcom,ad 1369 compatible = "qcom,adreno-540.1", "qcom,adreno";
1483 reg = <0x05000000 0x4 1370 reg = <0x05000000 0x40000>;
1484 reg-names = "kgsl_3d0 1371 reg-names = "kgsl_3d0_reg_memory";
1485 1372
1486 clocks = <&gcc GCC_GP 1373 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
1487 <&gpucc RBBMT 1374 <&gpucc RBBMTIMER_CLK>,
1488 <&gcc GCC_BIM 1375 <&gcc GCC_BIMC_GFX_CLK>,
1489 <&gcc GCC_GPU 1376 <&gcc GCC_GPU_BIMC_GFX_CLK>,
1490 <&gpucc RBCPR 1377 <&gpucc RBCPR_CLK>,
1491 <&gpucc GFX3D 1378 <&gpucc GFX3D_CLK>;
1492 clock-names = "iface" 1379 clock-names = "iface",
1493 "rbbmtimer", 1380 "rbbmtimer",
1494 "mem", 1381 "mem",
1495 "mem_iface", 1382 "mem_iface",
1496 "rbcpr", 1383 "rbcpr",
1497 "core"; 1384 "core";
1498 1385
1499 interrupts = <GIC_SPI !! 1386 interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
1500 iommus = <&adreno_smm 1387 iommus = <&adreno_smmu 0>;
1501 operating-points-v2 = 1388 operating-points-v2 = <&gpu_opp_table>;
1502 power-domains = <&rpm 1389 power-domains = <&rpmpd MSM8998_VDDMX>;
1503 status = "disabled"; 1390 status = "disabled";
1504 1391
1505 gpu_opp_table: opp-ta 1392 gpu_opp_table: opp-table {
1506 compatible = 1393 compatible = "operating-points-v2";
1507 opp-710000097 1394 opp-710000097 {
1508 opp-h 1395 opp-hz = /bits/ 64 <710000097>;
1509 opp-l 1396 opp-level = <RPM_SMD_LEVEL_TURBO>;
1510 opp-s !! 1397 opp-supported-hw = <0xFF>;
1511 }; 1398 };
1512 1399
1513 opp-670000048 1400 opp-670000048 {
1514 opp-h 1401 opp-hz = /bits/ 64 <670000048>;
1515 opp-l 1402 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
1516 opp-s !! 1403 opp-supported-hw = <0xFF>;
1517 }; 1404 };
1518 1405
1519 opp-596000097 1406 opp-596000097 {
1520 opp-h 1407 opp-hz = /bits/ 64 <596000097>;
1521 opp-l 1408 opp-level = <RPM_SMD_LEVEL_NOM>;
1522 opp-s !! 1409 opp-supported-hw = <0xFF>;
1523 }; 1410 };
1524 1411
1525 opp-515000097 1412 opp-515000097 {
1526 opp-h 1413 opp-hz = /bits/ 64 <515000097>;
1527 opp-l 1414 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
1528 opp-s !! 1415 opp-supported-hw = <0xFF>;
1529 }; 1416 };
1530 1417
1531 opp-414000000 1418 opp-414000000 {
1532 opp-h 1419 opp-hz = /bits/ 64 <414000000>;
1533 opp-l 1420 opp-level = <RPM_SMD_LEVEL_SVS>;
1534 opp-s !! 1421 opp-supported-hw = <0xFF>;
1535 }; 1422 };
1536 1423
1537 opp-342000000 1424 opp-342000000 {
1538 opp-h 1425 opp-hz = /bits/ 64 <342000000>;
1539 opp-l 1426 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
1540 opp-s !! 1427 opp-supported-hw = <0xFF>;
1541 }; 1428 };
1542 1429
1543 opp-257000000 1430 opp-257000000 {
1544 opp-h 1431 opp-hz = /bits/ 64 <257000000>;
1545 opp-l 1432 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
1546 opp-s !! 1433 opp-supported-hw = <0xFF>;
1547 }; 1434 };
1548 }; 1435 };
1549 }; 1436 };
1550 1437
1551 adreno_smmu: iommu@5040000 { 1438 adreno_smmu: iommu@5040000 {
1552 compatible = "qcom,ms 1439 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
1553 reg = <0x05040000 0x1 1440 reg = <0x05040000 0x10000>;
1554 clocks = <&gcc GCC_GP 1441 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
1555 <&gcc GCC_BI 1442 <&gcc GCC_BIMC_GFX_CLK>,
1556 <&gcc GCC_GP 1443 <&gcc GCC_GPU_BIMC_GFX_CLK>;
1557 clock-names = "iface" 1444 clock-names = "iface", "mem", "mem_iface";
1558 1445
1559 #global-interrupts = 1446 #global-interrupts = <0>;
1560 #iommu-cells = <1>; 1447 #iommu-cells = <1>;
1561 interrupts = 1448 interrupts =
1562 <GIC_SPI 329 1449 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1563 <GIC_SPI 330 1450 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
1564 <GIC_SPI 331 1451 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
1565 /* 1452 /*
1566 * GPU-GX GDSC's pare 1453 * GPU-GX GDSC's parent is GPU-CX. We need to bring up the
1567 * GPU-CX for SMMU bu 1454 * GPU-CX for SMMU but we need both of them up for Adreno.
1568 * Contemporarily, we 1455 * Contemporarily, we also need to manage the VDDMX rpmpd
1569 * domain in the Adre 1456 * domain in the Adreno driver.
1570 * Enable GPU CX/GX G 1457 * Enable GPU CX/GX GDSCs here so that we can manage the
1571 * SoC VDDMX RPM Powe 1458 * SoC VDDMX RPM Power Domain in the Adreno driver.
1572 */ 1459 */
1573 power-domains = <&gpu 1460 power-domains = <&gpucc GPU_GX_GDSC>;
>> 1461 status = "disabled";
1574 }; 1462 };
1575 1463
1576 gpucc: clock-controller@50650 1464 gpucc: clock-controller@5065000 {
1577 compatible = "qcom,ms 1465 compatible = "qcom,msm8998-gpucc";
1578 #clock-cells = <1>; 1466 #clock-cells = <1>;
1579 #reset-cells = <1>; 1467 #reset-cells = <1>;
1580 #power-domain-cells = 1468 #power-domain-cells = <1>;
1581 reg = <0x05065000 0x9 1469 reg = <0x05065000 0x9000>;
1582 1470
1583 clocks = <&rpmcc RPM_ 1471 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1584 <&gcc GCC_GP !! 1472 <&gcc GPLL0_OUT_MAIN>;
1585 clock-names = "xo", 1473 clock-names = "xo",
1586 "gpll0" 1474 "gpll0";
1587 }; 1475 };
1588 1476
1589 lpass_q6_smmu: iommu@5100000 <<
1590 compatible = "qcom,ms <<
1591 reg = <0x05100000 0x4 <<
1592 clocks = <&gcc HLOS1_ <<
1593 clock-names = "bus"; <<
1594 <<
1595 #global-interrupts = <<
1596 #iommu-cells = <1>; <<
1597 interrupts = <<
1598 <GIC_SPI 226 <<
1599 <GIC_SPI 393 <<
1600 <GIC_SPI 394 <<
1601 <GIC_SPI 395 <<
1602 <GIC_SPI 396 <<
1603 <GIC_SPI 397 <<
1604 <GIC_SPI 398 <<
1605 <GIC_SPI 399 <<
1606 <GIC_SPI 400 <<
1607 <GIC_SPI 401 <<
1608 <GIC_SPI 402 <<
1609 <GIC_SPI 403 <<
1610 <GIC_SPI 137 <<
1611 <<
1612 power-domains = <&gcc <<
1613 status = "disabled"; <<
1614 }; <<
1615 <<
1616 remoteproc_slpi: remoteproc@5 1477 remoteproc_slpi: remoteproc@5800000 {
1617 compatible = "qcom,ms 1478 compatible = "qcom,msm8998-slpi-pas";
1618 reg = <0x05800000 0x4 1479 reg = <0x05800000 0x4040>;
1619 1480
1620 interrupts-extended = 1481 interrupts-extended = <&intc GIC_SPI 390 IRQ_TYPE_EDGE_RISING>,
1621 1482 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1622 1483 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1623 1484 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1624 1485 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1625 interrupt-names = "wd 1486 interrupt-names = "wdog", "fatal", "ready",
1626 "ha 1487 "handover", "stop-ack";
1627 1488
1628 px-supply = <&vreg_lv 1489 px-supply = <&vreg_lvs2a_1p8>;
1629 1490
1630 clocks = <&rpmcc RPM_ !! 1491 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1631 clock-names = "xo"; !! 1492 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
>> 1493 clock-names = "xo", "aggre2";
1632 1494
1633 memory-region = <&slp 1495 memory-region = <&slpi_mem>;
1634 1496
1635 qcom,smem-states = <& 1497 qcom,smem-states = <&slpi_smp2p_out 0>;
1636 qcom,smem-state-names 1498 qcom,smem-state-names = "stop";
1637 1499
1638 power-domains = <&rpm 1500 power-domains = <&rpmpd MSM8998_SSCCX>;
1639 power-domain-names = 1501 power-domain-names = "ssc_cx";
1640 1502
1641 status = "disabled"; 1503 status = "disabled";
1642 1504
1643 glink-edge { 1505 glink-edge {
1644 interrupts = 1506 interrupts = <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>;
1645 label = "dsps 1507 label = "dsps";
1646 qcom,remote-p 1508 qcom,remote-pid = <3>;
1647 mboxes = <&ap 1509 mboxes = <&apcs_glb 27>;
1648 }; 1510 };
1649 }; 1511 };
1650 1512
1651 stm: stm@6002000 { 1513 stm: stm@6002000 {
1652 compatible = "arm,cor 1514 compatible = "arm,coresight-stm", "arm,primecell";
1653 reg = <0x06002000 0x1 1515 reg = <0x06002000 0x1000>,
1654 <0x16280000 0x1 1516 <0x16280000 0x180000>;
1655 reg-names = "stm-base 1517 reg-names = "stm-base", "stm-stimulus-base";
1656 status = "disabled"; 1518 status = "disabled";
1657 1519
1658 clocks = <&rpmcc RPM_ 1520 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1659 clock-names = "apb_pc 1521 clock-names = "apb_pclk", "atclk";
1660 1522
1661 out-ports { 1523 out-ports {
1662 port { 1524 port {
1663 stm_o 1525 stm_out: endpoint {
1664 1526 remote-endpoint = <&funnel0_in7>;
1665 }; 1527 };
1666 }; 1528 };
1667 }; 1529 };
1668 }; 1530 };
1669 1531
1670 funnel1: funnel@6041000 { 1532 funnel1: funnel@6041000 {
1671 compatible = "arm,cor 1533 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1672 reg = <0x06041000 0x1 1534 reg = <0x06041000 0x1000>;
1673 status = "disabled"; 1535 status = "disabled";
1674 1536
1675 clocks = <&rpmcc RPM_ 1537 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1676 clock-names = "apb_pc 1538 clock-names = "apb_pclk", "atclk";
1677 1539
1678 out-ports { 1540 out-ports {
1679 port { 1541 port {
1680 funne 1542 funnel0_out: endpoint {
1681 1543 remote-endpoint =
1682 1544 <&merge_funnel_in0>;
1683 }; 1545 };
1684 }; 1546 };
1685 }; 1547 };
1686 1548
1687 in-ports { 1549 in-ports {
1688 #address-cell 1550 #address-cells = <1>;
1689 #size-cells = 1551 #size-cells = <0>;
1690 1552
1691 port@7 { 1553 port@7 {
1692 reg = 1554 reg = <7>;
1693 funne 1555 funnel0_in7: endpoint {
1694 1556 remote-endpoint = <&stm_out>;
1695 }; 1557 };
1696 }; 1558 };
1697 }; 1559 };
1698 }; 1560 };
1699 1561
1700 funnel2: funnel@6042000 { 1562 funnel2: funnel@6042000 {
1701 compatible = "arm,cor 1563 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1702 reg = <0x06042000 0x1 1564 reg = <0x06042000 0x1000>;
1703 status = "disabled"; 1565 status = "disabled";
1704 1566
1705 clocks = <&rpmcc RPM_ 1567 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1706 clock-names = "apb_pc 1568 clock-names = "apb_pclk", "atclk";
1707 1569
1708 out-ports { 1570 out-ports {
1709 port { 1571 port {
1710 funne 1572 funnel1_out: endpoint {
1711 1573 remote-endpoint =
1712 1574 <&merge_funnel_in1>;
1713 }; 1575 };
1714 }; 1576 };
1715 }; 1577 };
1716 1578
1717 in-ports { 1579 in-ports {
1718 #address-cell 1580 #address-cells = <1>;
1719 #size-cells = 1581 #size-cells = <0>;
1720 1582
1721 port@6 { 1583 port@6 {
1722 reg = 1584 reg = <6>;
1723 funne 1585 funnel1_in6: endpoint {
1724 1586 remote-endpoint =
1725 1587 <&apss_merge_funnel_out>;
1726 }; 1588 };
1727 }; 1589 };
1728 }; 1590 };
1729 }; 1591 };
1730 1592
1731 funnel3: funnel@6045000 { 1593 funnel3: funnel@6045000 {
1732 compatible = "arm,cor 1594 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1733 reg = <0x06045000 0x1 1595 reg = <0x06045000 0x1000>;
1734 status = "disabled"; 1596 status = "disabled";
1735 1597
1736 clocks = <&rpmcc RPM_ 1598 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1737 clock-names = "apb_pc 1599 clock-names = "apb_pclk", "atclk";
1738 1600
1739 out-ports { 1601 out-ports {
1740 port { 1602 port {
1741 merge 1603 merge_funnel_out: endpoint {
1742 1604 remote-endpoint =
1743 1605 <&etf_in>;
1744 }; 1606 };
1745 }; 1607 };
1746 }; 1608 };
1747 1609
1748 in-ports { 1610 in-ports {
1749 #address-cell 1611 #address-cells = <1>;
1750 #size-cells = 1612 #size-cells = <0>;
1751 1613
1752 port@0 { 1614 port@0 {
1753 reg = 1615 reg = <0>;
1754 merge 1616 merge_funnel_in0: endpoint {
1755 1617 remote-endpoint =
1756 1618 <&funnel0_out>;
1757 }; 1619 };
1758 }; 1620 };
1759 1621
1760 port@1 { 1622 port@1 {
1761 reg = 1623 reg = <1>;
1762 merge 1624 merge_funnel_in1: endpoint {
1763 1625 remote-endpoint =
1764 1626 <&funnel1_out>;
1765 }; 1627 };
1766 }; 1628 };
1767 }; 1629 };
1768 }; 1630 };
1769 1631
1770 replicator1: replicator@60460 1632 replicator1: replicator@6046000 {
1771 compatible = "arm,cor 1633 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
1772 reg = <0x06046000 0x1 1634 reg = <0x06046000 0x1000>;
1773 status = "disabled"; 1635 status = "disabled";
1774 1636
1775 clocks = <&rpmcc RPM_ 1637 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1776 clock-names = "apb_pc 1638 clock-names = "apb_pclk", "atclk";
1777 1639
1778 out-ports { 1640 out-ports {
1779 port { 1641 port {
1780 repli 1642 replicator_out: endpoint {
1781 1643 remote-endpoint = <&etr_in>;
1782 }; 1644 };
1783 }; 1645 };
1784 }; 1646 };
1785 1647
1786 in-ports { 1648 in-ports {
1787 port { 1649 port {
1788 repli 1650 replicator_in: endpoint {
1789 1651 remote-endpoint = <&etf_out>;
1790 }; 1652 };
1791 }; 1653 };
1792 }; 1654 };
1793 }; 1655 };
1794 1656
1795 etf: etf@6047000 { 1657 etf: etf@6047000 {
1796 compatible = "arm,cor 1658 compatible = "arm,coresight-tmc", "arm,primecell";
1797 reg = <0x06047000 0x1 1659 reg = <0x06047000 0x1000>;
1798 status = "disabled"; 1660 status = "disabled";
1799 1661
1800 clocks = <&rpmcc RPM_ 1662 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1801 clock-names = "apb_pc 1663 clock-names = "apb_pclk", "atclk";
1802 1664
1803 out-ports { 1665 out-ports {
1804 port { 1666 port {
1805 etf_o 1667 etf_out: endpoint {
1806 1668 remote-endpoint =
1807 1669 <&replicator_in>;
1808 }; 1670 };
1809 }; 1671 };
1810 }; 1672 };
1811 1673
1812 in-ports { 1674 in-ports {
1813 port { 1675 port {
1814 etf_i 1676 etf_in: endpoint {
1815 1677 remote-endpoint =
1816 1678 <&merge_funnel_out>;
1817 }; 1679 };
1818 }; 1680 };
1819 }; 1681 };
1820 }; 1682 };
1821 1683
1822 etr: etr@6048000 { 1684 etr: etr@6048000 {
1823 compatible = "arm,cor 1685 compatible = "arm,coresight-tmc", "arm,primecell";
1824 reg = <0x06048000 0x1 1686 reg = <0x06048000 0x1000>;
1825 status = "disabled"; 1687 status = "disabled";
1826 1688
1827 clocks = <&rpmcc RPM_ 1689 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1828 clock-names = "apb_pc 1690 clock-names = "apb_pclk", "atclk";
1829 arm,scatter-gather; 1691 arm,scatter-gather;
1830 1692
1831 in-ports { 1693 in-ports {
1832 port { 1694 port {
1833 etr_i 1695 etr_in: endpoint {
1834 1696 remote-endpoint =
1835 1697 <&replicator_out>;
1836 }; 1698 };
1837 }; 1699 };
1838 }; 1700 };
1839 }; 1701 };
1840 1702
1841 etm1: etm@7840000 { 1703 etm1: etm@7840000 {
1842 compatible = "arm,cor 1704 compatible = "arm,coresight-etm4x", "arm,primecell";
1843 reg = <0x07840000 0x1 1705 reg = <0x07840000 0x1000>;
1844 status = "disabled"; 1706 status = "disabled";
1845 1707
1846 clocks = <&rpmcc RPM_ 1708 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1847 clock-names = "apb_pc 1709 clock-names = "apb_pclk", "atclk";
1848 1710
1849 cpu = <&CPU0>; 1711 cpu = <&CPU0>;
1850 1712
1851 out-ports { 1713 out-ports {
1852 port { 1714 port {
1853 etm0_ 1715 etm0_out: endpoint {
1854 1716 remote-endpoint =
1855 1717 <&apss_funnel_in0>;
1856 }; 1718 };
1857 }; 1719 };
1858 }; 1720 };
1859 }; 1721 };
1860 1722
1861 etm2: etm@7940000 { 1723 etm2: etm@7940000 {
1862 compatible = "arm,cor 1724 compatible = "arm,coresight-etm4x", "arm,primecell";
1863 reg = <0x07940000 0x1 1725 reg = <0x07940000 0x1000>;
1864 status = "disabled"; 1726 status = "disabled";
1865 1727
1866 clocks = <&rpmcc RPM_ 1728 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1867 clock-names = "apb_pc 1729 clock-names = "apb_pclk", "atclk";
1868 1730
1869 cpu = <&CPU1>; 1731 cpu = <&CPU1>;
1870 1732
1871 out-ports { 1733 out-ports {
1872 port { 1734 port {
1873 etm1_ 1735 etm1_out: endpoint {
1874 1736 remote-endpoint =
1875 1737 <&apss_funnel_in1>;
1876 }; 1738 };
1877 }; 1739 };
1878 }; 1740 };
1879 }; 1741 };
1880 1742
1881 etm3: etm@7a40000 { 1743 etm3: etm@7a40000 {
1882 compatible = "arm,cor 1744 compatible = "arm,coresight-etm4x", "arm,primecell";
1883 reg = <0x07a40000 0x1 1745 reg = <0x07a40000 0x1000>;
1884 status = "disabled"; 1746 status = "disabled";
1885 1747
1886 clocks = <&rpmcc RPM_ 1748 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1887 clock-names = "apb_pc 1749 clock-names = "apb_pclk", "atclk";
1888 1750
1889 cpu = <&CPU2>; 1751 cpu = <&CPU2>;
1890 1752
1891 out-ports { 1753 out-ports {
1892 port { 1754 port {
1893 etm2_ 1755 etm2_out: endpoint {
1894 1756 remote-endpoint =
1895 1757 <&apss_funnel_in2>;
1896 }; 1758 };
1897 }; 1759 };
1898 }; 1760 };
1899 }; 1761 };
1900 1762
1901 etm4: etm@7b40000 { 1763 etm4: etm@7b40000 {
1902 compatible = "arm,cor 1764 compatible = "arm,coresight-etm4x", "arm,primecell";
1903 reg = <0x07b40000 0x1 1765 reg = <0x07b40000 0x1000>;
1904 status = "disabled"; 1766 status = "disabled";
1905 1767
1906 clocks = <&rpmcc RPM_ 1768 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1907 clock-names = "apb_pc 1769 clock-names = "apb_pclk", "atclk";
1908 1770
1909 cpu = <&CPU3>; 1771 cpu = <&CPU3>;
1910 1772
1911 out-ports { 1773 out-ports {
1912 port { 1774 port {
1913 etm3_ 1775 etm3_out: endpoint {
1914 1776 remote-endpoint =
1915 1777 <&apss_funnel_in3>;
1916 }; 1778 };
1917 }; 1779 };
1918 }; 1780 };
1919 }; 1781 };
1920 1782
1921 funnel4: funnel@7b60000 { /* 1783 funnel4: funnel@7b60000 { /* APSS Funnel */
1922 compatible = "arm,cor 1784 compatible = "arm,coresight-etm4x", "arm,primecell";
1923 reg = <0x07b60000 0x1 1785 reg = <0x07b60000 0x1000>;
1924 status = "disabled"; 1786 status = "disabled";
1925 1787
1926 clocks = <&rpmcc RPM_ 1788 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1927 clock-names = "apb_pc 1789 clock-names = "apb_pclk", "atclk";
1928 1790
1929 out-ports { 1791 out-ports {
1930 port { 1792 port {
1931 apss_ 1793 apss_funnel_out: endpoint {
1932 1794 remote-endpoint =
1933 1795 <&apss_merge_funnel_in>;
1934 }; 1796 };
1935 }; 1797 };
1936 }; 1798 };
1937 1799
1938 in-ports { 1800 in-ports {
1939 #address-cell 1801 #address-cells = <1>;
1940 #size-cells = 1802 #size-cells = <0>;
1941 1803
1942 port@0 { 1804 port@0 {
1943 reg = 1805 reg = <0>;
1944 apss_ 1806 apss_funnel_in0: endpoint {
1945 1807 remote-endpoint =
1946 1808 <&etm0_out>;
1947 }; 1809 };
1948 }; 1810 };
1949 1811
1950 port@1 { 1812 port@1 {
1951 reg = 1813 reg = <1>;
1952 apss_ 1814 apss_funnel_in1: endpoint {
1953 1815 remote-endpoint =
1954 1816 <&etm1_out>;
1955 }; 1817 };
1956 }; 1818 };
1957 1819
1958 port@2 { 1820 port@2 {
1959 reg = 1821 reg = <2>;
1960 apss_ 1822 apss_funnel_in2: endpoint {
1961 1823 remote-endpoint =
1962 1824 <&etm2_out>;
1963 }; 1825 };
1964 }; 1826 };
1965 1827
1966 port@3 { 1828 port@3 {
1967 reg = 1829 reg = <3>;
1968 apss_ 1830 apss_funnel_in3: endpoint {
1969 1831 remote-endpoint =
1970 1832 <&etm3_out>;
1971 }; 1833 };
1972 }; 1834 };
1973 1835
1974 port@4 { 1836 port@4 {
1975 reg = 1837 reg = <4>;
1976 apss_ 1838 apss_funnel_in4: endpoint {
1977 1839 remote-endpoint =
1978 1840 <&etm4_out>;
1979 }; 1841 };
1980 }; 1842 };
1981 1843
1982 port@5 { 1844 port@5 {
1983 reg = 1845 reg = <5>;
1984 apss_ 1846 apss_funnel_in5: endpoint {
1985 1847 remote-endpoint =
1986 1848 <&etm5_out>;
1987 }; 1849 };
1988 }; 1850 };
1989 1851
1990 port@6 { 1852 port@6 {
1991 reg = 1853 reg = <6>;
1992 apss_ 1854 apss_funnel_in6: endpoint {
1993 1855 remote-endpoint =
1994 1856 <&etm6_out>;
1995 }; 1857 };
1996 }; 1858 };
1997 1859
1998 port@7 { 1860 port@7 {
1999 reg = 1861 reg = <7>;
2000 apss_ 1862 apss_funnel_in7: endpoint {
2001 1863 remote-endpoint =
2002 1864 <&etm7_out>;
2003 }; 1865 };
2004 }; 1866 };
2005 }; 1867 };
2006 }; 1868 };
2007 1869
2008 funnel5: funnel@7b70000 { 1870 funnel5: funnel@7b70000 {
2009 compatible = "arm,cor 1871 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2010 reg = <0x07b70000 0x1 1872 reg = <0x07b70000 0x1000>;
2011 status = "disabled"; 1873 status = "disabled";
2012 1874
2013 clocks = <&rpmcc RPM_ 1875 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2014 clock-names = "apb_pc 1876 clock-names = "apb_pclk", "atclk";
2015 1877
2016 out-ports { 1878 out-ports {
2017 port { 1879 port {
2018 apss_ 1880 apss_merge_funnel_out: endpoint {
2019 1881 remote-endpoint =
2020 1882 <&funnel1_in6>;
2021 }; 1883 };
2022 }; 1884 };
2023 }; 1885 };
2024 1886
2025 in-ports { 1887 in-ports {
2026 port { 1888 port {
2027 apss_ 1889 apss_merge_funnel_in: endpoint {
2028 1890 remote-endpoint =
2029 1891 <&apss_funnel_out>;
2030 }; 1892 };
2031 }; 1893 };
2032 }; 1894 };
2033 }; 1895 };
2034 1896
2035 etm5: etm@7c40000 { 1897 etm5: etm@7c40000 {
2036 compatible = "arm,cor 1898 compatible = "arm,coresight-etm4x", "arm,primecell";
2037 reg = <0x07c40000 0x1 1899 reg = <0x07c40000 0x1000>;
2038 status = "disabled"; 1900 status = "disabled";
2039 1901
2040 clocks = <&rpmcc RPM_ 1902 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2041 clock-names = "apb_pc 1903 clock-names = "apb_pclk", "atclk";
2042 1904
2043 cpu = <&CPU4>; 1905 cpu = <&CPU4>;
2044 1906
2045 out-ports { !! 1907 port {
2046 port { !! 1908 etm4_out: endpoint {
2047 etm4_ !! 1909 remote-endpoint = <&apss_funnel_in4>;
2048 <<
2049 }; <<
2050 }; 1910 };
2051 }; 1911 };
2052 }; 1912 };
2053 1913
2054 etm6: etm@7d40000 { 1914 etm6: etm@7d40000 {
2055 compatible = "arm,cor 1915 compatible = "arm,coresight-etm4x", "arm,primecell";
2056 reg = <0x07d40000 0x1 1916 reg = <0x07d40000 0x1000>;
2057 status = "disabled"; 1917 status = "disabled";
2058 1918
2059 clocks = <&rpmcc RPM_ 1919 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2060 clock-names = "apb_pc 1920 clock-names = "apb_pclk", "atclk";
2061 1921
2062 cpu = <&CPU5>; 1922 cpu = <&CPU5>;
2063 1923
2064 out-ports { !! 1924 port {
2065 port { !! 1925 etm5_out: endpoint {
2066 etm5_ !! 1926 remote-endpoint = <&apss_funnel_in5>;
2067 <<
2068 }; <<
2069 }; 1927 };
2070 }; 1928 };
2071 }; 1929 };
2072 1930
2073 etm7: etm@7e40000 { 1931 etm7: etm@7e40000 {
2074 compatible = "arm,cor 1932 compatible = "arm,coresight-etm4x", "arm,primecell";
2075 reg = <0x07e40000 0x1 1933 reg = <0x07e40000 0x1000>;
2076 status = "disabled"; 1934 status = "disabled";
2077 1935
2078 clocks = <&rpmcc RPM_ 1936 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2079 clock-names = "apb_pc 1937 clock-names = "apb_pclk", "atclk";
2080 1938
2081 cpu = <&CPU6>; 1939 cpu = <&CPU6>;
2082 1940
2083 out-ports { !! 1941 port {
2084 port { !! 1942 etm6_out: endpoint {
2085 etm6_ !! 1943 remote-endpoint = <&apss_funnel_in6>;
2086 <<
2087 }; <<
2088 }; 1944 };
2089 }; 1945 };
2090 }; 1946 };
2091 1947
2092 etm8: etm@7f40000 { 1948 etm8: etm@7f40000 {
2093 compatible = "arm,cor 1949 compatible = "arm,coresight-etm4x", "arm,primecell";
2094 reg = <0x07f40000 0x1 1950 reg = <0x07f40000 0x1000>;
2095 status = "disabled"; 1951 status = "disabled";
2096 1952
2097 clocks = <&rpmcc RPM_ 1953 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2098 clock-names = "apb_pc 1954 clock-names = "apb_pclk", "atclk";
2099 1955
2100 cpu = <&CPU7>; 1956 cpu = <&CPU7>;
2101 1957
2102 out-ports { !! 1958 port {
2103 port { !! 1959 etm7_out: endpoint {
2104 etm7_ !! 1960 remote-endpoint = <&apss_funnel_in7>;
2105 <<
2106 }; <<
2107 }; 1961 };
2108 }; 1962 };
2109 }; 1963 };
2110 1964
2111 sram@290000 { 1965 sram@290000 {
2112 compatible = "qcom,rp 1966 compatible = "qcom,rpm-stats";
2113 reg = <0x00290000 0x1 1967 reg = <0x00290000 0x10000>;
2114 }; 1968 };
2115 1969
2116 spmi_bus: spmi@800f000 { 1970 spmi_bus: spmi@800f000 {
2117 compatible = "qcom,sp 1971 compatible = "qcom,spmi-pmic-arb";
2118 reg = <0x0800f000 0x1 !! 1972 reg = <0x0800f000 0x1000>,
2119 <0x08400000 0x1 !! 1973 <0x08400000 0x1000000>,
2120 <0x09400000 0x1 !! 1974 <0x09400000 0x1000000>,
2121 <0x0a400000 0x2 !! 1975 <0x0a400000 0x220000>,
2122 <0x0800a000 0x3 !! 1976 <0x0800a000 0x3000>;
2123 reg-names = "core", " 1977 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
2124 interrupt-names = "pe 1978 interrupt-names = "periph_irq";
2125 interrupts = <GIC_SPI 1979 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
2126 qcom,ee = <0>; 1980 qcom,ee = <0>;
2127 qcom,channel = <0>; 1981 qcom,channel = <0>;
2128 #address-cells = <2>; 1982 #address-cells = <2>;
2129 #size-cells = <0>; 1983 #size-cells = <0>;
2130 interrupt-controller; 1984 interrupt-controller;
2131 #interrupt-cells = <4 1985 #interrupt-cells = <4>;
>> 1986 cell-index = <0>;
2132 }; 1987 };
2133 1988
2134 usb3: usb@a8f8800 { 1989 usb3: usb@a8f8800 {
2135 compatible = "qcom,ms 1990 compatible = "qcom,msm8998-dwc3", "qcom,dwc3";
2136 reg = <0x0a8f8800 0x4 1991 reg = <0x0a8f8800 0x400>;
2137 status = "disabled"; 1992 status = "disabled";
2138 #address-cells = <1>; 1993 #address-cells = <1>;
2139 #size-cells = <1>; 1994 #size-cells = <1>;
2140 ranges; 1995 ranges;
2141 1996
2142 clocks = <&gcc GCC_CF 1997 clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>,
2143 <&gcc GCC_US 1998 <&gcc GCC_USB30_MASTER_CLK>,
2144 <&gcc GCC_AG 1999 <&gcc GCC_AGGRE1_USB3_AXI_CLK>,
2145 <&gcc GCC_US 2000 <&gcc GCC_USB30_SLEEP_CLK>,
2146 <&gcc GCC_US 2001 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
2147 clock-names = "cfg_no 2002 clock-names = "cfg_noc",
2148 "core", 2003 "core",
2149 "iface" 2004 "iface",
2150 "sleep" 2005 "sleep",
2151 "mock_u 2006 "mock_utmi";
2152 2007
2153 assigned-clocks = <&g 2008 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
2154 <&g 2009 <&gcc GCC_USB30_MASTER_CLK>;
2155 assigned-clock-rates 2010 assigned-clock-rates = <19200000>, <120000000>;
2156 2011
2157 interrupts = <GIC_SPI !! 2012 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
2158 <GIC_SPI <<
2159 <GIC_SPI 2013 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
2160 interrupt-names = "pw !! 2014 interrupt-names = "hs_phy_irq", "ss_phy_irq";
2161 "qu <<
2162 "ss <<
2163 2015
2164 power-domains = <&gcc 2016 power-domains = <&gcc USB_30_GDSC>;
2165 2017
2166 resets = <&gcc GCC_US 2018 resets = <&gcc GCC_USB_30_BCR>;
2167 2019
2168 usb3_dwc3: usb@a80000 2020 usb3_dwc3: usb@a800000 {
2169 compatible = 2021 compatible = "snps,dwc3";
2170 reg = <0x0a80 2022 reg = <0x0a800000 0xcd00>;
2171 interrupts = 2023 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
2172 snps,dis_u2_s 2024 snps,dis_u2_susphy_quirk;
2173 snps,dis_enbl 2025 snps,dis_enblslpm_quirk;
2174 snps,parkmode !! 2026 phys = <&qusb2phy>, <&usb1_ssphy>;
2175 phys = <&qusb <<
2176 phy-names = " 2027 phy-names = "usb2-phy", "usb3-phy";
2177 snps,has-lpm- 2028 snps,has-lpm-erratum;
2178 snps,hird-thr 2029 snps,hird-threshold = /bits/ 8 <0x10>;
2179 }; 2030 };
2180 }; 2031 };
2181 2032
2182 usb3phy: phy@c010000 { 2033 usb3phy: phy@c010000 {
2183 compatible = "qcom,ms 2034 compatible = "qcom,msm8998-qmp-usb3-phy";
2184 reg = <0x0c010000 0x1 !! 2035 reg = <0x0c010000 0x18c>;
>> 2036 status = "disabled";
>> 2037 #address-cells = <1>;
>> 2038 #size-cells = <1>;
>> 2039 ranges;
2185 2040
2186 clocks = <&gcc GCC_US 2041 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
2187 <&gcc GCC_US <<
2188 <&gcc GCC_US 2042 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2189 <&gcc GCC_US !! 2043 <&gcc GCC_USB3_CLKREF_CLK>;
2190 clock-names = "aux", !! 2044 clock-names = "aux", "cfg_ahb", "ref";
2191 "ref", <<
2192 "cfg_ah <<
2193 "pipe"; <<
2194 clock-output-names = <<
2195 #clock-cells = <0>; <<
2196 #phy-cells = <0>; <<
2197 2045
2198 resets = <&gcc GCC_US 2046 resets = <&gcc GCC_USB3_PHY_BCR>,
2199 <&gcc GCC_US 2047 <&gcc GCC_USB3PHY_PHY_BCR>;
2200 reset-names = "phy", !! 2048 reset-names = "phy", "common";
2201 "phy_ph <<
2202 <<
2203 qcom,tcsr-reg = <&tcs <<
2204 2049
2205 status = "disabled"; !! 2050 usb1_ssphy: phy@c010200 {
>> 2051 reg = <0xc010200 0x128>,
>> 2052 <0xc010400 0x200>,
>> 2053 <0xc010c00 0x20c>,
>> 2054 <0xc010600 0x128>,
>> 2055 <0xc010800 0x200>;
>> 2056 #phy-cells = <0>;
>> 2057 #clock-cells = <0>;
>> 2058 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
>> 2059 clock-names = "pipe0";
>> 2060 clock-output-names = "usb3_phy_pipe_clk_src";
>> 2061 };
2206 }; 2062 };
2207 2063
2208 qusb2phy: phy@c012000 { 2064 qusb2phy: phy@c012000 {
2209 compatible = "qcom,ms 2065 compatible = "qcom,msm8998-qusb2-phy";
2210 reg = <0x0c012000 0x2 2066 reg = <0x0c012000 0x2a8>;
2211 status = "disabled"; 2067 status = "disabled";
2212 #phy-cells = <0>; 2068 #phy-cells = <0>;
2213 2069
2214 clocks = <&gcc GCC_US 2070 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2215 <&gcc GCC_RX 2071 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
2216 clock-names = "cfg_ah 2072 clock-names = "cfg_ahb", "ref";
2217 2073
2218 resets = <&gcc GCC_QU 2074 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2219 2075
2220 nvmem-cells = <&qusb2 2076 nvmem-cells = <&qusb2_hstx_trim>;
2221 }; 2077 };
2222 2078
2223 sdhc2: mmc@c0a4900 { 2079 sdhc2: mmc@c0a4900 {
2224 compatible = "qcom,ms 2080 compatible = "qcom,msm8998-sdhci", "qcom,sdhci-msm-v4";
2225 reg = <0x0c0a4900 0x3 2081 reg = <0x0c0a4900 0x314>, <0x0c0a4000 0x800>;
2226 reg-names = "hc", "co 2082 reg-names = "hc", "core";
2227 2083
2228 interrupts = <GIC_SPI 2084 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
2229 <GIC_SPI 2085 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
2230 interrupt-names = "hc 2086 interrupt-names = "hc_irq", "pwr_irq";
2231 2087
2232 clock-names = "iface" 2088 clock-names = "iface", "core", "xo";
2233 clocks = <&gcc GCC_SD 2089 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2234 <&gcc GCC_SD 2090 <&gcc GCC_SDCC2_APPS_CLK>,
2235 <&rpmcc RPM_ !! 2091 <&xo>;
2236 bus-width = <4>; 2092 bus-width = <4>;
2237 status = "disabled"; 2093 status = "disabled";
2238 }; 2094 };
2239 2095
2240 blsp1_dma: dma-controller@c14 2096 blsp1_dma: dma-controller@c144000 {
2241 compatible = "qcom,ba 2097 compatible = "qcom,bam-v1.7.0";
2242 reg = <0x0c144000 0x2 2098 reg = <0x0c144000 0x25000>;
2243 interrupts = <GIC_SPI 2099 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
2244 clocks = <&gcc GCC_BL 2100 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
2245 clock-names = "bam_cl 2101 clock-names = "bam_clk";
2246 #dma-cells = <1>; 2102 #dma-cells = <1>;
2247 qcom,ee = <0>; 2103 qcom,ee = <0>;
2248 qcom,controlled-remot 2104 qcom,controlled-remotely;
2249 num-channels = <18>; 2105 num-channels = <18>;
2250 qcom,num-ees = <4>; 2106 qcom,num-ees = <4>;
2251 }; 2107 };
2252 2108
2253 blsp1_uart3: serial@c171000 { 2109 blsp1_uart3: serial@c171000 {
2254 compatible = "qcom,ms 2110 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2255 reg = <0x0c171000 0x1 2111 reg = <0x0c171000 0x1000>;
2256 interrupts = <GIC_SPI 2112 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
2257 clocks = <&gcc GCC_BL 2113 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
2258 <&gcc GCC_BL 2114 <&gcc GCC_BLSP1_AHB_CLK>;
2259 clock-names = "core", 2115 clock-names = "core", "iface";
2260 dmas = <&blsp1_dma 4> 2116 dmas = <&blsp1_dma 4>, <&blsp1_dma 5>;
2261 dma-names = "tx", "rx 2117 dma-names = "tx", "rx";
2262 pinctrl-names = "defa 2118 pinctrl-names = "default";
2263 pinctrl-0 = <&blsp1_u 2119 pinctrl-0 = <&blsp1_uart3_on>;
2264 status = "disabled"; 2120 status = "disabled";
2265 }; 2121 };
2266 2122
2267 blsp1_i2c1: i2c@c175000 { 2123 blsp1_i2c1: i2c@c175000 {
2268 compatible = "qcom,i2 2124 compatible = "qcom,i2c-qup-v2.2.1";
2269 reg = <0x0c175000 0x6 2125 reg = <0x0c175000 0x600>;
2270 interrupts = <GIC_SPI 2126 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
2271 2127
2272 clocks = <&gcc GCC_BL 2128 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
2273 <&gcc GCC_BL 2129 <&gcc GCC_BLSP1_AHB_CLK>;
2274 clock-names = "core", 2130 clock-names = "core", "iface";
2275 dmas = <&blsp1_dma 6> 2131 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>;
2276 dma-names = "tx", "rx 2132 dma-names = "tx", "rx";
2277 pinctrl-names = "defa 2133 pinctrl-names = "default", "sleep";
2278 pinctrl-0 = <&blsp1_i 2134 pinctrl-0 = <&blsp1_i2c1_default>;
2279 pinctrl-1 = <&blsp1_i 2135 pinctrl-1 = <&blsp1_i2c1_sleep>;
2280 clock-frequency = <40 2136 clock-frequency = <400000>;
2281 2137
2282 status = "disabled"; 2138 status = "disabled";
2283 #address-cells = <1>; 2139 #address-cells = <1>;
2284 #size-cells = <0>; 2140 #size-cells = <0>;
2285 }; 2141 };
2286 2142
2287 blsp1_i2c2: i2c@c176000 { 2143 blsp1_i2c2: i2c@c176000 {
2288 compatible = "qcom,i2 2144 compatible = "qcom,i2c-qup-v2.2.1";
2289 reg = <0x0c176000 0x6 2145 reg = <0x0c176000 0x600>;
2290 interrupts = <GIC_SPI 2146 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
2291 2147
2292 clocks = <&gcc GCC_BL 2148 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
2293 <&gcc GCC_BL 2149 <&gcc GCC_BLSP1_AHB_CLK>;
2294 clock-names = "core", 2150 clock-names = "core", "iface";
2295 dmas = <&blsp1_dma 8> 2151 dmas = <&blsp1_dma 8>, <&blsp1_dma 9>;
2296 dma-names = "tx", "rx 2152 dma-names = "tx", "rx";
2297 pinctrl-names = "defa 2153 pinctrl-names = "default", "sleep";
2298 pinctrl-0 = <&blsp1_i 2154 pinctrl-0 = <&blsp1_i2c2_default>;
2299 pinctrl-1 = <&blsp1_i 2155 pinctrl-1 = <&blsp1_i2c2_sleep>;
2300 clock-frequency = <40 2156 clock-frequency = <400000>;
2301 2157
2302 status = "disabled"; 2158 status = "disabled";
2303 #address-cells = <1>; 2159 #address-cells = <1>;
2304 #size-cells = <0>; 2160 #size-cells = <0>;
2305 }; 2161 };
2306 2162
2307 blsp1_i2c3: i2c@c177000 { 2163 blsp1_i2c3: i2c@c177000 {
2308 compatible = "qcom,i2 2164 compatible = "qcom,i2c-qup-v2.2.1";
2309 reg = <0x0c177000 0x6 2165 reg = <0x0c177000 0x600>;
2310 interrupts = <GIC_SPI 2166 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
2311 2167
2312 clocks = <&gcc GCC_BL 2168 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
2313 <&gcc GCC_BL 2169 <&gcc GCC_BLSP1_AHB_CLK>;
2314 clock-names = "core", 2170 clock-names = "core", "iface";
2315 dmas = <&blsp1_dma 10 2171 dmas = <&blsp1_dma 10>, <&blsp1_dma 11>;
2316 dma-names = "tx", "rx 2172 dma-names = "tx", "rx";
2317 pinctrl-names = "defa 2173 pinctrl-names = "default", "sleep";
2318 pinctrl-0 = <&blsp1_i 2174 pinctrl-0 = <&blsp1_i2c3_default>;
2319 pinctrl-1 = <&blsp1_i 2175 pinctrl-1 = <&blsp1_i2c3_sleep>;
2320 clock-frequency = <40 2176 clock-frequency = <400000>;
2321 2177
2322 status = "disabled"; 2178 status = "disabled";
2323 #address-cells = <1>; 2179 #address-cells = <1>;
2324 #size-cells = <0>; 2180 #size-cells = <0>;
2325 }; 2181 };
2326 2182
2327 blsp1_i2c4: i2c@c178000 { 2183 blsp1_i2c4: i2c@c178000 {
2328 compatible = "qcom,i2 2184 compatible = "qcom,i2c-qup-v2.2.1";
2329 reg = <0x0c178000 0x6 2185 reg = <0x0c178000 0x600>;
2330 interrupts = <GIC_SPI 2186 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
2331 2187
2332 clocks = <&gcc GCC_BL 2188 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
2333 <&gcc GCC_BL 2189 <&gcc GCC_BLSP1_AHB_CLK>;
2334 clock-names = "core", 2190 clock-names = "core", "iface";
2335 dmas = <&blsp1_dma 12 2191 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
2336 dma-names = "tx", "rx 2192 dma-names = "tx", "rx";
2337 pinctrl-names = "defa 2193 pinctrl-names = "default", "sleep";
2338 pinctrl-0 = <&blsp1_i 2194 pinctrl-0 = <&blsp1_i2c4_default>;
2339 pinctrl-1 = <&blsp1_i 2195 pinctrl-1 = <&blsp1_i2c4_sleep>;
2340 clock-frequency = <40 2196 clock-frequency = <400000>;
2341 2197
2342 status = "disabled"; 2198 status = "disabled";
2343 #address-cells = <1>; 2199 #address-cells = <1>;
2344 #size-cells = <0>; 2200 #size-cells = <0>;
2345 }; 2201 };
2346 2202
2347 blsp1_i2c5: i2c@c179000 { 2203 blsp1_i2c5: i2c@c179000 {
2348 compatible = "qcom,i2 2204 compatible = "qcom,i2c-qup-v2.2.1";
2349 reg = <0x0c179000 0x6 2205 reg = <0x0c179000 0x600>;
2350 interrupts = <GIC_SPI 2206 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
2351 2207
2352 clocks = <&gcc GCC_BL 2208 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
2353 <&gcc GCC_BL 2209 <&gcc GCC_BLSP1_AHB_CLK>;
2354 clock-names = "core", 2210 clock-names = "core", "iface";
2355 dmas = <&blsp1_dma 14 2211 dmas = <&blsp1_dma 14>, <&blsp1_dma 15>;
2356 dma-names = "tx", "rx 2212 dma-names = "tx", "rx";
2357 pinctrl-names = "defa 2213 pinctrl-names = "default", "sleep";
2358 pinctrl-0 = <&blsp1_i 2214 pinctrl-0 = <&blsp1_i2c5_default>;
2359 pinctrl-1 = <&blsp1_i 2215 pinctrl-1 = <&blsp1_i2c5_sleep>;
2360 clock-frequency = <40 2216 clock-frequency = <400000>;
2361 2217
2362 status = "disabled"; 2218 status = "disabled";
2363 #address-cells = <1>; 2219 #address-cells = <1>;
2364 #size-cells = <0>; 2220 #size-cells = <0>;
2365 }; 2221 };
2366 2222
2367 blsp1_i2c6: i2c@c17a000 { 2223 blsp1_i2c6: i2c@c17a000 {
2368 compatible = "qcom,i2 2224 compatible = "qcom,i2c-qup-v2.2.1";
2369 reg = <0x0c17a000 0x6 2225 reg = <0x0c17a000 0x600>;
2370 interrupts = <GIC_SPI 2226 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
2371 2227
2372 clocks = <&gcc GCC_BL 2228 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
2373 <&gcc GCC_BL 2229 <&gcc GCC_BLSP1_AHB_CLK>;
2374 clock-names = "core", 2230 clock-names = "core", "iface";
2375 dmas = <&blsp1_dma 16 2231 dmas = <&blsp1_dma 16>, <&blsp1_dma 17>;
2376 dma-names = "tx", "rx 2232 dma-names = "tx", "rx";
2377 pinctrl-names = "defa 2233 pinctrl-names = "default", "sleep";
2378 pinctrl-0 = <&blsp1_i 2234 pinctrl-0 = <&blsp1_i2c6_default>;
2379 pinctrl-1 = <&blsp1_i 2235 pinctrl-1 = <&blsp1_i2c6_sleep>;
2380 clock-frequency = <40 2236 clock-frequency = <400000>;
2381 2237
2382 status = "disabled"; 2238 status = "disabled";
2383 #address-cells = <1>; 2239 #address-cells = <1>;
2384 #size-cells = <0>; 2240 #size-cells = <0>;
2385 }; 2241 };
2386 2242
2387 blsp1_spi1: spi@c175000 { <<
2388 compatible = "qcom,sp <<
2389 reg = <0x0c175000 0x6 <<
2390 interrupts = <GIC_SPI <<
2391 <<
2392 clocks = <&gcc GCC_BL <<
2393 <&gcc GCC_BL <<
2394 clock-names = "core", <<
2395 dmas = <&blsp1_dma 6> <<
2396 dma-names = "tx", "rx <<
2397 pinctrl-names = "defa <<
2398 pinctrl-0 = <&blsp1_s <<
2399 <<
2400 status = "disabled"; <<
2401 #address-cells = <1>; <<
2402 #size-cells = <0>; <<
2403 }; <<
2404 <<
2405 blsp1_spi2: spi@c176000 { <<
2406 compatible = "qcom,sp <<
2407 reg = <0x0c176000 0x6 <<
2408 interrupts = <GIC_SPI <<
2409 <<
2410 clocks = <&gcc GCC_BL <<
2411 <&gcc GCC_BL <<
2412 clock-names = "core", <<
2413 dmas = <&blsp1_dma 8> <<
2414 dma-names = "tx", "rx <<
2415 pinctrl-names = "defa <<
2416 pinctrl-0 = <&blsp1_s <<
2417 <<
2418 status = "disabled"; <<
2419 #address-cells = <1>; <<
2420 #size-cells = <0>; <<
2421 }; <<
2422 <<
2423 blsp1_spi3: spi@c177000 { <<
2424 compatible = "qcom,sp <<
2425 reg = <0x0c177000 0x6 <<
2426 interrupts = <GIC_SPI <<
2427 <<
2428 clocks = <&gcc GCC_BL <<
2429 <&gcc GCC_BL <<
2430 clock-names = "core", <<
2431 dmas = <&blsp1_dma 10 <<
2432 dma-names = "tx", "rx <<
2433 pinctrl-names = "defa <<
2434 pinctrl-0 = <&blsp1_s <<
2435 <<
2436 status = "disabled"; <<
2437 #address-cells = <1>; <<
2438 #size-cells = <0>; <<
2439 }; <<
2440 <<
2441 blsp1_spi4: spi@c178000 { <<
2442 compatible = "qcom,sp <<
2443 reg = <0x0c178000 0x6 <<
2444 interrupts = <GIC_SPI <<
2445 <<
2446 clocks = <&gcc GCC_BL <<
2447 <&gcc GCC_BL <<
2448 clock-names = "core", <<
2449 dmas = <&blsp1_dma 12 <<
2450 dma-names = "tx", "rx <<
2451 pinctrl-names = "defa <<
2452 pinctrl-0 = <&blsp1_s <<
2453 <<
2454 status = "disabled"; <<
2455 #address-cells = <1>; <<
2456 #size-cells = <0>; <<
2457 }; <<
2458 <<
2459 blsp1_spi5: spi@c179000 { <<
2460 compatible = "qcom,sp <<
2461 reg = <0x0c179000 0x6 <<
2462 interrupts = <GIC_SPI <<
2463 <<
2464 clocks = <&gcc GCC_BL <<
2465 <&gcc GCC_BL <<
2466 clock-names = "core", <<
2467 dmas = <&blsp1_dma 14 <<
2468 dma-names = "tx", "rx <<
2469 pinctrl-names = "defa <<
2470 pinctrl-0 = <&blsp1_s <<
2471 <<
2472 status = "disabled"; <<
2473 #address-cells = <1>; <<
2474 #size-cells = <0>; <<
2475 }; <<
2476 <<
2477 blsp1_spi6: spi@c17a000 { <<
2478 compatible = "qcom,sp <<
2479 reg = <0x0c17a000 0x6 <<
2480 interrupts = <GIC_SPI <<
2481 <<
2482 clocks = <&gcc GCC_BL <<
2483 <&gcc GCC_BL <<
2484 clock-names = "core", <<
2485 dmas = <&blsp1_dma 16 <<
2486 dma-names = "tx", "rx <<
2487 pinctrl-names = "defa <<
2488 pinctrl-0 = <&blsp1_s <<
2489 <<
2490 status = "disabled"; <<
2491 #address-cells = <1>; <<
2492 #size-cells = <0>; <<
2493 }; <<
2494 <<
2495 blsp2_dma: dma-controller@c18 2243 blsp2_dma: dma-controller@c184000 {
2496 compatible = "qcom,ba 2244 compatible = "qcom,bam-v1.7.0";
2497 reg = <0x0c184000 0x2 2245 reg = <0x0c184000 0x25000>;
2498 interrupts = <GIC_SPI 2246 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
2499 clocks = <&gcc GCC_BL 2247 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
2500 clock-names = "bam_cl 2248 clock-names = "bam_clk";
2501 #dma-cells = <1>; 2249 #dma-cells = <1>;
2502 qcom,ee = <0>; 2250 qcom,ee = <0>;
2503 qcom,controlled-remot 2251 qcom,controlled-remotely;
2504 num-channels = <18>; 2252 num-channels = <18>;
2505 qcom,num-ees = <4>; 2253 qcom,num-ees = <4>;
2506 }; 2254 };
2507 2255
2508 blsp2_uart1: serial@c1b0000 { 2256 blsp2_uart1: serial@c1b0000 {
2509 compatible = "qcom,ms 2257 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2510 reg = <0x0c1b0000 0x1 2258 reg = <0x0c1b0000 0x1000>;
2511 interrupts = <GIC_SPI 2259 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
2512 clocks = <&gcc GCC_BL 2260 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
2513 <&gcc GCC_BL 2261 <&gcc GCC_BLSP2_AHB_CLK>;
2514 clock-names = "core", 2262 clock-names = "core", "iface";
2515 status = "disabled"; 2263 status = "disabled";
2516 }; 2264 };
2517 2265
2518 blsp2_i2c1: i2c@c1b5000 { 2266 blsp2_i2c1: i2c@c1b5000 {
2519 compatible = "qcom,i2 2267 compatible = "qcom,i2c-qup-v2.2.1";
2520 reg = <0x0c1b5000 0x6 2268 reg = <0x0c1b5000 0x600>;
2521 interrupts = <GIC_SPI 2269 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
2522 2270
2523 clocks = <&gcc GCC_BL 2271 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
2524 <&gcc GCC_BL 2272 <&gcc GCC_BLSP2_AHB_CLK>;
2525 clock-names = "core", 2273 clock-names = "core", "iface";
2526 dmas = <&blsp2_dma 6> 2274 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>;
2527 dma-names = "tx", "rx 2275 dma-names = "tx", "rx";
2528 pinctrl-names = "defa 2276 pinctrl-names = "default", "sleep";
2529 pinctrl-0 = <&blsp2_i 2277 pinctrl-0 = <&blsp2_i2c1_default>;
2530 pinctrl-1 = <&blsp2_i 2278 pinctrl-1 = <&blsp2_i2c1_sleep>;
2531 clock-frequency = <40 2279 clock-frequency = <400000>;
2532 2280
2533 status = "disabled"; 2281 status = "disabled";
2534 #address-cells = <1>; 2282 #address-cells = <1>;
2535 #size-cells = <0>; 2283 #size-cells = <0>;
2536 }; 2284 };
2537 2285
2538 blsp2_i2c2: i2c@c1b6000 { 2286 blsp2_i2c2: i2c@c1b6000 {
2539 compatible = "qcom,i2 2287 compatible = "qcom,i2c-qup-v2.2.1";
2540 reg = <0x0c1b6000 0x6 2288 reg = <0x0c1b6000 0x600>;
2541 interrupts = <GIC_SPI 2289 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
2542 2290
2543 clocks = <&gcc GCC_BL 2291 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
2544 <&gcc GCC_BL 2292 <&gcc GCC_BLSP2_AHB_CLK>;
2545 clock-names = "core", 2293 clock-names = "core", "iface";
2546 dmas = <&blsp2_dma 8> 2294 dmas = <&blsp2_dma 8>, <&blsp2_dma 9>;
2547 dma-names = "tx", "rx 2295 dma-names = "tx", "rx";
2548 pinctrl-names = "defa 2296 pinctrl-names = "default", "sleep";
2549 pinctrl-0 = <&blsp2_i 2297 pinctrl-0 = <&blsp2_i2c2_default>;
2550 pinctrl-1 = <&blsp2_i 2298 pinctrl-1 = <&blsp2_i2c2_sleep>;
2551 clock-frequency = <40 2299 clock-frequency = <400000>;
2552 2300
2553 status = "disabled"; 2301 status = "disabled";
2554 #address-cells = <1>; 2302 #address-cells = <1>;
2555 #size-cells = <0>; 2303 #size-cells = <0>;
2556 }; 2304 };
2557 2305
2558 blsp2_i2c3: i2c@c1b7000 { 2306 blsp2_i2c3: i2c@c1b7000 {
2559 compatible = "qcom,i2 2307 compatible = "qcom,i2c-qup-v2.2.1";
2560 reg = <0x0c1b7000 0x6 2308 reg = <0x0c1b7000 0x600>;
2561 interrupts = <GIC_SPI 2309 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
2562 2310
2563 clocks = <&gcc GCC_BL 2311 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
2564 <&gcc GCC_BL 2312 <&gcc GCC_BLSP2_AHB_CLK>;
2565 clock-names = "core", 2313 clock-names = "core", "iface";
2566 dmas = <&blsp2_dma 10 2314 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>;
2567 dma-names = "tx", "rx 2315 dma-names = "tx", "rx";
2568 pinctrl-names = "defa 2316 pinctrl-names = "default", "sleep";
2569 pinctrl-0 = <&blsp2_i 2317 pinctrl-0 = <&blsp2_i2c3_default>;
2570 pinctrl-1 = <&blsp2_i 2318 pinctrl-1 = <&blsp2_i2c3_sleep>;
2571 clock-frequency = <40 2319 clock-frequency = <400000>;
2572 2320
2573 status = "disabled"; 2321 status = "disabled";
2574 #address-cells = <1>; 2322 #address-cells = <1>;
2575 #size-cells = <0>; 2323 #size-cells = <0>;
2576 }; 2324 };
2577 2325
2578 blsp2_i2c4: i2c@c1b8000 { 2326 blsp2_i2c4: i2c@c1b8000 {
2579 compatible = "qcom,i2 2327 compatible = "qcom,i2c-qup-v2.2.1";
2580 reg = <0x0c1b8000 0x6 2328 reg = <0x0c1b8000 0x600>;
2581 interrupts = <GIC_SPI 2329 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
2582 2330
2583 clocks = <&gcc GCC_BL 2331 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>,
2584 <&gcc GCC_BL 2332 <&gcc GCC_BLSP2_AHB_CLK>;
2585 clock-names = "core", 2333 clock-names = "core", "iface";
2586 dmas = <&blsp2_dma 12 2334 dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
2587 dma-names = "tx", "rx 2335 dma-names = "tx", "rx";
2588 pinctrl-names = "defa 2336 pinctrl-names = "default", "sleep";
2589 pinctrl-0 = <&blsp2_i 2337 pinctrl-0 = <&blsp2_i2c4_default>;
2590 pinctrl-1 = <&blsp2_i 2338 pinctrl-1 = <&blsp2_i2c4_sleep>;
2591 clock-frequency = <40 2339 clock-frequency = <400000>;
2592 2340
2593 status = "disabled"; 2341 status = "disabled";
2594 #address-cells = <1>; 2342 #address-cells = <1>;
2595 #size-cells = <0>; 2343 #size-cells = <0>;
2596 }; 2344 };
2597 2345
2598 blsp2_i2c5: i2c@c1b9000 { 2346 blsp2_i2c5: i2c@c1b9000 {
2599 compatible = "qcom,i2 2347 compatible = "qcom,i2c-qup-v2.2.1";
2600 reg = <0x0c1b9000 0x6 2348 reg = <0x0c1b9000 0x600>;
2601 interrupts = <GIC_SPI 2349 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
2602 2350
2603 clocks = <&gcc GCC_BL 2351 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,
2604 <&gcc GCC_BL 2352 <&gcc GCC_BLSP2_AHB_CLK>;
2605 clock-names = "core", 2353 clock-names = "core", "iface";
2606 dmas = <&blsp2_dma 14 2354 dmas = <&blsp2_dma 14>, <&blsp2_dma 15>;
2607 dma-names = "tx", "rx 2355 dma-names = "tx", "rx";
2608 pinctrl-names = "defa 2356 pinctrl-names = "default", "sleep";
2609 pinctrl-0 = <&blsp2_i 2357 pinctrl-0 = <&blsp2_i2c5_default>;
2610 pinctrl-1 = <&blsp2_i 2358 pinctrl-1 = <&blsp2_i2c5_sleep>;
2611 clock-frequency = <40 2359 clock-frequency = <400000>;
2612 2360
2613 status = "disabled"; 2361 status = "disabled";
2614 #address-cells = <1>; 2362 #address-cells = <1>;
2615 #size-cells = <0>; 2363 #size-cells = <0>;
2616 }; 2364 };
2617 2365
2618 blsp2_i2c6: i2c@c1ba000 { 2366 blsp2_i2c6: i2c@c1ba000 {
2619 compatible = "qcom,i2 2367 compatible = "qcom,i2c-qup-v2.2.1";
2620 reg = <0x0c1ba000 0x6 2368 reg = <0x0c1ba000 0x600>;
2621 interrupts = <GIC_SPI 2369 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
2622 2370
2623 clocks = <&gcc GCC_BL 2371 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>,
2624 <&gcc GCC_BL 2372 <&gcc GCC_BLSP2_AHB_CLK>;
2625 clock-names = "core", 2373 clock-names = "core", "iface";
2626 dmas = <&blsp2_dma 16 2374 dmas = <&blsp2_dma 16>, <&blsp2_dma 17>;
2627 dma-names = "tx", "rx 2375 dma-names = "tx", "rx";
2628 pinctrl-names = "defa 2376 pinctrl-names = "default", "sleep";
2629 pinctrl-0 = <&blsp2_i 2377 pinctrl-0 = <&blsp2_i2c6_default>;
2630 pinctrl-1 = <&blsp2_i 2378 pinctrl-1 = <&blsp2_i2c6_sleep>;
2631 clock-frequency = <40 2379 clock-frequency = <400000>;
2632 2380
2633 status = "disabled"; 2381 status = "disabled";
2634 #address-cells = <1>; 2382 #address-cells = <1>;
2635 #size-cells = <0>; 2383 #size-cells = <0>;
2636 }; 2384 };
2637 2385
2638 blsp2_spi1: spi@c1b5000 { <<
2639 compatible = "qcom,sp <<
2640 reg = <0x0c1b5000 0x6 <<
2641 interrupts = <GIC_SPI <<
2642 <<
2643 clocks = <&gcc GCC_BL <<
2644 <&gcc GCC_BL <<
2645 clock-names = "core", <<
2646 dmas = <&blsp2_dma 6> <<
2647 dma-names = "tx", "rx <<
2648 pinctrl-names = "defa <<
2649 pinctrl-0 = <&blsp2_s <<
2650 <<
2651 status = "disabled"; <<
2652 #address-cells = <1>; <<
2653 #size-cells = <0>; <<
2654 }; <<
2655 <<
2656 blsp2_spi2: spi@c1b6000 { <<
2657 compatible = "qcom,sp <<
2658 reg = <0x0c1b6000 0x6 <<
2659 interrupts = <GIC_SPI <<
2660 <<
2661 clocks = <&gcc GCC_BL <<
2662 <&gcc GCC_BL <<
2663 clock-names = "core", <<
2664 dmas = <&blsp2_dma 8> <<
2665 dma-names = "tx", "rx <<
2666 pinctrl-names = "defa <<
2667 pinctrl-0 = <&blsp2_s <<
2668 <<
2669 status = "disabled"; <<
2670 #address-cells = <1>; <<
2671 #size-cells = <0>; <<
2672 }; <<
2673 <<
2674 blsp2_spi3: spi@c1b7000 { <<
2675 compatible = "qcom,sp <<
2676 reg = <0x0c1b7000 0x6 <<
2677 interrupts = <GIC_SPI <<
2678 <<
2679 clocks = <&gcc GCC_BL <<
2680 <&gcc GCC_BL <<
2681 clock-names = "core", <<
2682 dmas = <&blsp2_dma 10 <<
2683 dma-names = "tx", "rx <<
2684 pinctrl-names = "defa <<
2685 pinctrl-0 = <&blsp2_s <<
2686 <<
2687 status = "disabled"; <<
2688 #address-cells = <1>; <<
2689 #size-cells = <0>; <<
2690 }; <<
2691 <<
2692 blsp2_spi4: spi@c1b8000 { <<
2693 compatible = "qcom,sp <<
2694 reg = <0x0c1b8000 0x6 <<
2695 interrupts = <GIC_SPI <<
2696 <<
2697 clocks = <&gcc GCC_BL <<
2698 <&gcc GCC_BL <<
2699 clock-names = "core", <<
2700 dmas = <&blsp2_dma 12 <<
2701 dma-names = "tx", "rx <<
2702 pinctrl-names = "defa <<
2703 pinctrl-0 = <&blsp2_s <<
2704 <<
2705 status = "disabled"; <<
2706 #address-cells = <1>; <<
2707 #size-cells = <0>; <<
2708 }; <<
2709 <<
2710 blsp2_spi5: spi@c1b9000 { <<
2711 compatible = "qcom,sp <<
2712 reg = <0x0c1b9000 0x6 <<
2713 interrupts = <GIC_SPI <<
2714 <<
2715 clocks = <&gcc GCC_BL <<
2716 <&gcc GCC_BL <<
2717 clock-names = "core", <<
2718 dmas = <&blsp2_dma 14 <<
2719 dma-names = "tx", "rx <<
2720 pinctrl-names = "defa <<
2721 pinctrl-0 = <&blsp2_s <<
2722 <<
2723 status = "disabled"; <<
2724 #address-cells = <1>; <<
2725 #size-cells = <0>; <<
2726 }; <<
2727 <<
2728 blsp2_spi6: spi@c1ba000 { <<
2729 compatible = "qcom,sp <<
2730 reg = <0x0c1ba000 0x6 <<
2731 interrupts = <GIC_SPI <<
2732 <<
2733 clocks = <&gcc GCC_BL <<
2734 <&gcc GCC_BL <<
2735 clock-names = "core", <<
2736 dmas = <&blsp2_dma 16 <<
2737 dma-names = "tx", "rx <<
2738 pinctrl-names = "defa <<
2739 pinctrl-0 = <&blsp2_s <<
2740 <<
2741 status = "disabled"; <<
2742 #address-cells = <1>; <<
2743 #size-cells = <0>; <<
2744 }; <<
2745 <<
2746 mmcc: clock-controller@c8c000 2386 mmcc: clock-controller@c8c0000 {
2747 compatible = "qcom,mm 2387 compatible = "qcom,mmcc-msm8998";
2748 #clock-cells = <1>; 2388 #clock-cells = <1>;
2749 #reset-cells = <1>; 2389 #reset-cells = <1>;
2750 #power-domain-cells = 2390 #power-domain-cells = <1>;
2751 reg = <0xc8c0000 0x40 2391 reg = <0xc8c0000 0x40000>;
2752 2392
2753 clock-names = "xo", 2393 clock-names = "xo",
2754 "gpll0" 2394 "gpll0",
2755 "dsi0ds 2395 "dsi0dsi",
2756 "dsi0by 2396 "dsi0byte",
2757 "dsi1ds 2397 "dsi1dsi",
2758 "dsi1by 2398 "dsi1byte",
2759 "hdmipl 2399 "hdmipll",
2760 "dplink 2400 "dplink",
2761 "dpvco" 2401 "dpvco",
2762 "gpll0_ !! 2402 "core_bi_pll_test_se";
2763 clocks = <&rpmcc RPM_ 2403 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
2764 <&gcc GCC_MM 2404 <&gcc GCC_MMSS_GPLL0_CLK>,
2765 <&mdss_dsi0_ <<
2766 <&mdss_dsi0_ <<
2767 <&mdss_dsi1_ <<
2768 <&mdss_dsi1_ <<
2769 <0>, 2405 <0>,
2770 <0>, 2406 <0>,
2771 <0>, 2407 <0>,
2772 <&gcc GCC_MM !! 2408 <0>,
2773 }; !! 2409 <0>,
2774 !! 2410 <0>,
2775 mdss: display-subsystem@c9000 !! 2411 <0>,
2776 compatible = "qcom,ms !! 2412 <0>;
2777 reg = <0x0c900000 0x1 <<
2778 reg-names = "mdss"; <<
2779 <<
2780 interrupts = <GIC_SPI <<
2781 interrupt-controller; <<
2782 #interrupt-cells = <1 <<
2783 <<
2784 clocks = <&mmcc MDSS_ <<
2785 <&mmcc MDSS_ <<
2786 <&mmcc MDSS_ <<
2787 clock-names = "iface" <<
2788 "bus", <<
2789 "core"; <<
2790 <<
2791 power-domains = <&mmc <<
2792 iommus = <&mmss_smmu <<
2793 <<
2794 #address-cells = <1>; <<
2795 #size-cells = <1>; <<
2796 ranges; <<
2797 <<
2798 status = "disabled"; <<
2799 <<
2800 mdss_mdp: display-con <<
2801 compatible = <<
2802 reg = <0x0c90 <<
2803 <0x0c9a <<
2804 <0x0c9b <<
2805 <0x0c9b <<
2806 reg-names = " <<
2807 " <<
2808 " <<
2809 " <<
2810 <<
2811 interrupt-par <<
2812 interrupts = <<
2813 <<
2814 clocks = <&mm <<
2815 <&mm <<
2816 <&mm <<
2817 <&mm <<
2818 <&mm <<
2819 clock-names = <<
2820 <<
2821 <<
2822 <<
2823 <<
2824 <<
2825 assigned-cloc <<
2826 assigned-cloc <<
2827 <<
2828 operating-poi <<
2829 power-domains <<
2830 <<
2831 mdp_opp_table <<
2832 compa <<
2833 <<
2834 opp-1 <<
2835 <<
2836 <<
2837 }; <<
2838 <<
2839 opp-2 <<
2840 <<
2841 <<
2842 }; <<
2843 <<
2844 opp-3 <<
2845 <<
2846 <<
2847 }; <<
2848 <<
2849 opp-4 <<
2850 <<
2851 <<
2852 }; <<
2853 }; <<
2854 <<
2855 ports { <<
2856 #addr <<
2857 #size <<
2858 <<
2859 port@ <<
2860 <<
2861 <<
2862 <<
2863 <<
2864 <<
2865 }; <<
2866 <<
2867 port@ <<
2868 <<
2869 <<
2870 <<
2871 <<
2872 <<
2873 }; <<
2874 }; <<
2875 }; <<
2876 <<
2877 mdss_dsi0: dsi@c99400 <<
2878 compatible = <<
2879 reg = <0x0c99 <<
2880 reg-names = " <<
2881 <<
2882 interrupt-par <<
2883 interrupts = <<
2884 <<
2885 clocks = <&mm <<
2886 <&mm <<
2887 <&mm <<
2888 <&mm <<
2889 <&mm <<
2890 <&mm <<
2891 clock-names = <<
2892 <<
2893 <<
2894 <<
2895 <<
2896 <<
2897 assigned-cloc <<
2898 <<
2899 assigned-cloc <<
2900 <<
2901 <<
2902 operating-poi <<
2903 power-domains <<
2904 <<
2905 phys = <&mdss <<
2906 phy-names = " <<
2907 <<
2908 #address-cell <<
2909 #size-cells = <<
2910 <<
2911 status = "dis <<
2912 <<
2913 ports { <<
2914 #addr <<
2915 #size <<
2916 <<
2917 port@ <<
2918 <<
2919 <<
2920 <<
2921 <<
2922 <<
2923 }; <<
2924 <<
2925 port@ <<
2926 <<
2927 <<
2928 <<
2929 <<
2930 }; <<
2931 }; <<
2932 }; <<
2933 <<
2934 mdss_dsi0_phy: phy@c9 <<
2935 compatible = <<
2936 reg = <0x0c99 <<
2937 <0x0c99 <<
2938 <0x0c99 <<
2939 reg-names = " <<
2940 " <<
2941 " <<
2942 <<
2943 clocks = <&mm <<
2944 <&rp <<
2945 clock-names = <<
2946 <<
2947 #clock-cells <<
2948 #phy-cells = <<
2949 <<
2950 status = "dis <<
2951 }; <<
2952 <<
2953 mdss_dsi1: dsi@c99600 <<
2954 compatible = <<
2955 reg = <0x0c99 <<
2956 reg-names = " <<
2957 <<
2958 interrupt-par <<
2959 interrupts = <<
2960 <<
2961 clocks = <&mm <<
2962 <&mm <<
2963 <&mm <<
2964 <&mm <<
2965 <&mm <<
2966 <&mm <<
2967 clock-names = <<
2968 <<
2969 <<
2970 <<
2971 <<
2972 <<
2973 assigned-cloc <<
2974 <<
2975 assigned-cloc <<
2976 <<
2977 <<
2978 operating-poi <<
2979 power-domains <<
2980 <<
2981 phys = <&mdss <<
2982 phy-names = " <<
2983 <<
2984 #address-cell <<
2985 #size-cells = <<
2986 <<
2987 status = "dis <<
2988 <<
2989 ports { <<
2990 #addr <<
2991 #size <<
2992 <<
2993 port@ <<
2994 <<
2995 <<
2996 <<
2997 <<
2998 <<
2999 }; <<
3000 <<
3001 port@ <<
3002 <<
3003 <<
3004 <<
3005 <<
3006 }; <<
3007 }; <<
3008 }; <<
3009 <<
3010 mdss_dsi1_phy: phy@c9 <<
3011 compatible = <<
3012 reg = <0x0c99 <<
3013 <0x0c99 <<
3014 <0x0c99 <<
3015 reg-names = " <<
3016 " <<
3017 " <<
3018 <<
3019 clocks = <&mm <<
3020 <&rp <<
3021 clock-names = <<
3022 <<
3023 <<
3024 #clock-cells <<
3025 #phy-cells = <<
3026 <<
3027 status = "dis <<
3028 }; <<
3029 }; <<
3030 <<
3031 venus: video-codec@cc00000 { <<
3032 compatible = "qcom,ms <<
3033 reg = <0x0cc00000 0xf <<
3034 interrupts = <GIC_SPI <<
3035 power-domains = <&mmc <<
3036 clocks = <&mmcc VIDEO <<
3037 <&mmcc VIDEO <<
3038 <&mmcc VIDEO <<
3039 <&mmcc VIDEO <<
3040 clock-names = "core", <<
3041 iommus = <&mmss_smmu <<
3042 <&mmss_smmu <<
3043 <&mmss_smmu <<
3044 <&mmss_smmu <<
3045 <&mmss_smmu <<
3046 <&mmss_smmu <<
3047 <&mmss_smmu <<
3048 <&mmss_smmu <<
3049 <&mmss_smmu <<
3050 <&mmss_smmu <<
3051 <&mmss_smmu <<
3052 <&mmss_smmu <<
3053 <&mmss_smmu <<
3054 <&mmss_smmu <<
3055 <&mmss_smmu <<
3056 <&mmss_smmu <<
3057 <&mmss_smmu <<
3058 <&mmss_smmu <<
3059 <&mmss_smmu <<
3060 <&mmss_smmu <<
3061 memory-region = <&ven <<
3062 status = "disabled"; <<
3063 <<
3064 video-decoder { <<
3065 compatible = <<
3066 clocks = <&mm <<
3067 clock-names = <<
3068 power-domains <<
3069 }; <<
3070 <<
3071 video-encoder { <<
3072 compatible = <<
3073 clocks = <&mm <<
3074 clock-names = <<
3075 power-domains <<
3076 }; <<
3077 }; 2413 };
3078 2414
3079 mmss_smmu: iommu@cd00000 { 2415 mmss_smmu: iommu@cd00000 {
3080 compatible = "qcom,ms 2416 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
3081 reg = <0x0cd00000 0x4 2417 reg = <0x0cd00000 0x40000>;
3082 #iommu-cells = <1>; 2418 #iommu-cells = <1>;
3083 2419
3084 clocks = <&mmcc MNOC_ 2420 clocks = <&mmcc MNOC_AHB_CLK>,
3085 <&mmcc BIMC_ 2421 <&mmcc BIMC_SMMU_AHB_CLK>,
>> 2422 <&rpmcc RPM_SMD_MMAXI_CLK>,
3086 <&mmcc BIMC_ 2423 <&mmcc BIMC_SMMU_AXI_CLK>;
3087 clock-names = "iface- !! 2424 clock-names = "iface-mm", "iface-smmu",
3088 "iface- !! 2425 "bus-mm", "bus-smmu";
3089 "bus-sm <<
3090 2426
3091 #global-interrupts = 2427 #global-interrupts = <0>;
3092 interrupts = 2428 interrupts =
3093 <GIC_SPI 263 2429 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
3094 <GIC_SPI 266 2430 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
3095 <GIC_SPI 267 2431 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
3096 <GIC_SPI 268 2432 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
3097 <GIC_SPI 244 2433 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
3098 <GIC_SPI 245 2434 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
3099 <GIC_SPI 247 2435 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
3100 <GIC_SPI 248 2436 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
3101 <GIC_SPI 249 2437 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
3102 <GIC_SPI 250 2438 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
3103 <GIC_SPI 251 2439 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
3104 <GIC_SPI 252 2440 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
3105 <GIC_SPI 253 2441 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
3106 <GIC_SPI 254 2442 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
3107 <GIC_SPI 255 2443 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
3108 <GIC_SPI 256 2444 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
3109 <GIC_SPI 260 2445 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
3110 <GIC_SPI 261 2446 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
3111 <GIC_SPI 262 2447 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
3112 <GIC_SPI 272 2448 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
3113 <<
3114 power-domains = <&mmc <<
3115 }; 2449 };
3116 2450
3117 remoteproc_adsp: remoteproc@1 2451 remoteproc_adsp: remoteproc@17300000 {
3118 compatible = "qcom,ms 2452 compatible = "qcom,msm8998-adsp-pas";
3119 reg = <0x17300000 0x4 2453 reg = <0x17300000 0x4040>;
3120 2454
3121 interrupts-extended = 2455 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
3122 2456 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3123 2457 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3124 2458 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3125 2459 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
3126 interrupt-names = "wd 2460 interrupt-names = "wdog", "fatal", "ready",
3127 "ha 2461 "handover", "stop-ack";
3128 2462
3129 clocks = <&rpmcc RPM_ 2463 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
3130 clock-names = "xo"; 2464 clock-names = "xo";
3131 2465
3132 memory-region = <&ads 2466 memory-region = <&adsp_mem>;
3133 2467
3134 qcom,smem-states = <& 2468 qcom,smem-states = <&adsp_smp2p_out 0>;
3135 qcom,smem-state-names 2469 qcom,smem-state-names = "stop";
3136 2470
3137 power-domains = <&rpm 2471 power-domains = <&rpmpd MSM8998_VDDCX>;
3138 power-domain-names = 2472 power-domain-names = "cx";
3139 2473
3140 status = "disabled"; 2474 status = "disabled";
3141 2475
3142 glink-edge { 2476 glink-edge {
3143 interrupts = 2477 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
3144 label = "lpas 2478 label = "lpass";
3145 qcom,remote-p 2479 qcom,remote-pid = <2>;
3146 mboxes = <&ap 2480 mboxes = <&apcs_glb 9>;
3147 }; 2481 };
3148 }; 2482 };
3149 2483
3150 apcs_glb: mailbox@17911000 { 2484 apcs_glb: mailbox@17911000 {
3151 compatible = "qcom,ms !! 2485 compatible = "qcom,msm8998-apcs-hmss-global";
3152 "qcom,ms <<
3153 reg = <0x17911000 0x1 2486 reg = <0x17911000 0x1000>;
3154 2487
3155 #mbox-cells = <1>; 2488 #mbox-cells = <1>;
3156 }; 2489 };
3157 2490
3158 timer@17920000 { 2491 timer@17920000 {
3159 #address-cells = <1>; 2492 #address-cells = <1>;
3160 #size-cells = <1>; 2493 #size-cells = <1>;
3161 ranges; 2494 ranges;
3162 compatible = "arm,arm 2495 compatible = "arm,armv7-timer-mem";
3163 reg = <0x17920000 0x1 2496 reg = <0x17920000 0x1000>;
3164 2497
3165 frame@17921000 { 2498 frame@17921000 {
3166 frame-number 2499 frame-number = <0>;
3167 interrupts = 2500 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
3168 2501 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
3169 reg = <0x1792 2502 reg = <0x17921000 0x1000>,
3170 <0x1792 2503 <0x17922000 0x1000>;
3171 }; 2504 };
3172 2505
3173 frame@17923000 { 2506 frame@17923000 {
3174 frame-number 2507 frame-number = <1>;
3175 interrupts = 2508 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
3176 reg = <0x1792 2509 reg = <0x17923000 0x1000>;
3177 status = "dis 2510 status = "disabled";
3178 }; 2511 };
3179 2512
3180 frame@17924000 { 2513 frame@17924000 {
3181 frame-number 2514 frame-number = <2>;
3182 interrupts = 2515 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
3183 reg = <0x1792 2516 reg = <0x17924000 0x1000>;
3184 status = "dis 2517 status = "disabled";
3185 }; 2518 };
3186 2519
3187 frame@17925000 { 2520 frame@17925000 {
3188 frame-number 2521 frame-number = <3>;
3189 interrupts = 2522 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3190 reg = <0x1792 2523 reg = <0x17925000 0x1000>;
3191 status = "dis 2524 status = "disabled";
3192 }; 2525 };
3193 2526
3194 frame@17926000 { 2527 frame@17926000 {
3195 frame-number 2528 frame-number = <4>;
3196 interrupts = 2529 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3197 reg = <0x1792 2530 reg = <0x17926000 0x1000>;
3198 status = "dis 2531 status = "disabled";
3199 }; 2532 };
3200 2533
3201 frame@17927000 { 2534 frame@17927000 {
3202 frame-number 2535 frame-number = <5>;
3203 interrupts = 2536 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3204 reg = <0x1792 2537 reg = <0x17927000 0x1000>;
3205 status = "dis 2538 status = "disabled";
3206 }; 2539 };
3207 2540
3208 frame@17928000 { 2541 frame@17928000 {
3209 frame-number 2542 frame-number = <6>;
3210 interrupts = 2543 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
3211 reg = <0x1792 2544 reg = <0x17928000 0x1000>;
3212 status = "dis 2545 status = "disabled";
3213 }; 2546 };
3214 }; 2547 };
3215 2548
3216 intc: interrupt-controller@17 2549 intc: interrupt-controller@17a00000 {
3217 compatible = "arm,gic 2550 compatible = "arm,gic-v3";
3218 reg = <0x17a00000 0x1 2551 reg = <0x17a00000 0x10000>, /* GICD */
3219 <0x17b00000 0x1 2552 <0x17b00000 0x100000>; /* GICR * 8 */
3220 #interrupt-cells = <3 2553 #interrupt-cells = <3>;
3221 #address-cells = <1>; 2554 #address-cells = <1>;
3222 #size-cells = <1>; 2555 #size-cells = <1>;
3223 ranges; 2556 ranges;
3224 interrupt-controller; 2557 interrupt-controller;
3225 #redistributor-region 2558 #redistributor-regions = <1>;
3226 redistributor-stride 2559 redistributor-stride = <0x0 0x20000>;
3227 interrupts = <GIC_PPI 2560 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3228 }; 2561 };
3229 2562
3230 wifi: wifi@18800000 { 2563 wifi: wifi@18800000 {
3231 compatible = "qcom,wc 2564 compatible = "qcom,wcn3990-wifi";
3232 status = "disabled"; 2565 status = "disabled";
3233 reg = <0x18800000 0x8 2566 reg = <0x18800000 0x800000>;
3234 reg-names = "membase" 2567 reg-names = "membase";
3235 memory-region = <&wla 2568 memory-region = <&wlan_msa_mem>;
3236 clocks = <&rpmcc RPM_ 2569 clocks = <&rpmcc RPM_SMD_RF_CLK2_PIN>;
3237 clock-names = "cxo_re 2570 clock-names = "cxo_ref_clk_pin";
3238 interrupts = 2571 interrupts =
3239 <GIC_SPI 413 2572 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
3240 <GIC_SPI 414 2573 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
3241 <GIC_SPI 415 2574 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
3242 <GIC_SPI 416 2575 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
3243 <GIC_SPI 417 2576 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
3244 <GIC_SPI 418 2577 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
3245 <GIC_SPI 420 2578 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
3246 <GIC_SPI 421 2579 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
3247 <GIC_SPI 422 2580 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
3248 <GIC_SPI 423 2581 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
3249 <GIC_SPI 424 2582 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
3250 <GIC_SPI 425 2583 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
3251 iommus = <&anoc2_smmu 2584 iommus = <&anoc2_smmu 0x1900>,
3252 <&anoc2_smmu 2585 <&anoc2_smmu 0x1901>;
3253 qcom,snoc-host-cap-8b 2586 qcom,snoc-host-cap-8bit-quirk;
3254 qcom,no-msa-ready-ind <<
3255 }; 2587 };
3256 }; 2588 };
3257 }; 2589 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.