1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2016, The Linux Foundation. A 2 /* Copyright (c) 2016, The Linux Foundation. All rights reserved. */
3 3
4 #include <dt-bindings/interrupt-controller/arm 4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-msm8998.h 5 #include <dt-bindings/clock/qcom,gcc-msm8998.h>
6 #include <dt-bindings/clock/qcom,gpucc-msm8998 6 #include <dt-bindings/clock/qcom,gpucc-msm8998.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8998. 7 #include <dt-bindings/clock/qcom,mmcc-msm8998.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h> 8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/firmware/qcom,scm.h> <<
10 #include <dt-bindings/power/qcom-rpmpd.h> 9 #include <dt-bindings/power/qcom-rpmpd.h>
11 #include <dt-bindings/gpio/gpio.h> 10 #include <dt-bindings/gpio/gpio.h>
12 11
13 / { 12 / {
14 interrupt-parent = <&intc>; 13 interrupt-parent = <&intc>;
15 14
16 qcom,msm-id = <292 0x0>; 15 qcom,msm-id = <292 0x0>;
17 16
18 #address-cells = <2>; 17 #address-cells = <2>;
19 #size-cells = <2>; 18 #size-cells = <2>;
20 19
21 chosen { }; 20 chosen { };
22 21
23 memory@80000000 { 22 memory@80000000 {
24 device_type = "memory"; 23 device_type = "memory";
25 /* We expect the bootloader to 24 /* We expect the bootloader to fill in the reg */
26 reg = <0x0 0x80000000 0x0 0x0> 25 reg = <0x0 0x80000000 0x0 0x0>;
27 }; 26 };
28 27
29 reserved-memory { 28 reserved-memory {
30 #address-cells = <2>; 29 #address-cells = <2>;
31 #size-cells = <2>; 30 #size-cells = <2>;
32 ranges; 31 ranges;
33 32
34 hyp_mem: memory@85800000 { 33 hyp_mem: memory@85800000 {
35 reg = <0x0 0x85800000 34 reg = <0x0 0x85800000 0x0 0x600000>;
36 no-map; 35 no-map;
37 }; 36 };
38 37
39 xbl_mem: memory@85e00000 { 38 xbl_mem: memory@85e00000 {
40 reg = <0x0 0x85e00000 39 reg = <0x0 0x85e00000 0x0 0x100000>;
41 no-map; 40 no-map;
42 }; 41 };
43 42
44 smem_mem: smem-mem@86000000 { 43 smem_mem: smem-mem@86000000 {
45 reg = <0x0 0x86000000 44 reg = <0x0 0x86000000 0x0 0x200000>;
46 no-map; 45 no-map;
47 }; 46 };
48 47
49 tz_mem: memory@86200000 { 48 tz_mem: memory@86200000 {
50 reg = <0x0 0x86200000 49 reg = <0x0 0x86200000 0x0 0x2d00000>;
51 no-map; 50 no-map;
52 }; 51 };
53 52
54 rmtfs_mem: memory@88f00000 { 53 rmtfs_mem: memory@88f00000 {
55 compatible = "qcom,rmt 54 compatible = "qcom,rmtfs-mem";
56 reg = <0x0 0x88f00000 55 reg = <0x0 0x88f00000 0x0 0x200000>;
57 no-map; 56 no-map;
58 57
59 qcom,client-id = <1>; 58 qcom,client-id = <1>;
60 qcom,vmid = <QCOM_SCM_ !! 59 qcom,vmid = <15>;
61 }; 60 };
62 61
63 spss_mem: memory@8ab00000 { 62 spss_mem: memory@8ab00000 {
64 reg = <0x0 0x8ab00000 63 reg = <0x0 0x8ab00000 0x0 0x700000>;
65 no-map; 64 no-map;
66 }; 65 };
67 66
68 adsp_mem: memory@8b200000 { 67 adsp_mem: memory@8b200000 {
69 reg = <0x0 0x8b200000 68 reg = <0x0 0x8b200000 0x0 0x1a00000>;
70 no-map; 69 no-map;
71 }; 70 };
72 71
73 mpss_mem: memory@8cc00000 { 72 mpss_mem: memory@8cc00000 {
74 reg = <0x0 0x8cc00000 73 reg = <0x0 0x8cc00000 0x0 0x7000000>;
75 no-map; 74 no-map;
76 }; 75 };
77 76
78 venus_mem: memory@93c00000 { 77 venus_mem: memory@93c00000 {
79 reg = <0x0 0x93c00000 78 reg = <0x0 0x93c00000 0x0 0x500000>;
80 no-map; 79 no-map;
81 }; 80 };
82 81
83 mba_mem: memory@94100000 { 82 mba_mem: memory@94100000 {
84 reg = <0x0 0x94100000 83 reg = <0x0 0x94100000 0x0 0x200000>;
85 no-map; 84 no-map;
86 }; 85 };
87 86
88 slpi_mem: memory@94300000 { 87 slpi_mem: memory@94300000 {
89 reg = <0x0 0x94300000 88 reg = <0x0 0x94300000 0x0 0xf00000>;
90 no-map; 89 no-map;
91 }; 90 };
92 91
93 ipa_fw_mem: memory@95200000 { 92 ipa_fw_mem: memory@95200000 {
94 reg = <0x0 0x95200000 93 reg = <0x0 0x95200000 0x0 0x10000>;
95 no-map; 94 no-map;
96 }; 95 };
97 96
98 ipa_gsi_mem: memory@95210000 { 97 ipa_gsi_mem: memory@95210000 {
99 reg = <0x0 0x95210000 98 reg = <0x0 0x95210000 0x0 0x5000>;
100 no-map; 99 no-map;
101 }; 100 };
102 101
103 gpu_mem: memory@95600000 { 102 gpu_mem: memory@95600000 {
104 reg = <0x0 0x95600000 103 reg = <0x0 0x95600000 0x0 0x100000>;
105 no-map; 104 no-map;
106 }; 105 };
107 106
108 wlan_msa_mem: memory@95700000 107 wlan_msa_mem: memory@95700000 {
109 reg = <0x0 0x95700000 108 reg = <0x0 0x95700000 0x0 0x100000>;
110 no-map; 109 no-map;
111 }; 110 };
112 111
113 mdata_mem: mpss-metadata { 112 mdata_mem: mpss-metadata {
114 alloc-ranges = <0x0 0x 113 alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>;
115 size = <0x0 0x4000>; 114 size = <0x0 0x4000>;
116 no-map; 115 no-map;
117 }; 116 };
118 }; 117 };
119 118
120 clocks { 119 clocks {
121 xo: xo-board { 120 xo: xo-board {
122 compatible = "fixed-cl 121 compatible = "fixed-clock";
123 #clock-cells = <0>; 122 #clock-cells = <0>;
124 clock-frequency = <192 123 clock-frequency = <19200000>;
125 clock-output-names = " 124 clock-output-names = "xo_board";
126 }; 125 };
127 126
128 sleep_clk: sleep-clk { 127 sleep_clk: sleep-clk {
129 compatible = "fixed-cl 128 compatible = "fixed-clock";
130 #clock-cells = <0>; 129 #clock-cells = <0>;
131 clock-frequency = <327 130 clock-frequency = <32764>;
132 }; 131 };
133 }; 132 };
134 133
135 cpus { 134 cpus {
136 #address-cells = <2>; 135 #address-cells = <2>;
137 #size-cells = <0>; 136 #size-cells = <0>;
138 137
139 CPU0: cpu@0 { 138 CPU0: cpu@0 {
140 device_type = "cpu"; 139 device_type = "cpu";
141 compatible = "qcom,kry 140 compatible = "qcom,kryo280";
142 reg = <0x0 0x0>; 141 reg = <0x0 0x0>;
143 enable-method = "psci" 142 enable-method = "psci";
144 capacity-dmips-mhz = < 143 capacity-dmips-mhz = <1024>;
145 cpu-idle-states = <&LI 144 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
146 next-level-cache = <&L 145 next-level-cache = <&L2_0>;
147 L2_0: l2-cache { 146 L2_0: l2-cache {
148 compatible = " 147 compatible = "cache";
149 cache-level = 148 cache-level = <2>;
150 cache-unified; 149 cache-unified;
151 }; 150 };
152 }; 151 };
153 152
154 CPU1: cpu@1 { 153 CPU1: cpu@1 {
155 device_type = "cpu"; 154 device_type = "cpu";
156 compatible = "qcom,kry 155 compatible = "qcom,kryo280";
157 reg = <0x0 0x1>; 156 reg = <0x0 0x1>;
158 enable-method = "psci" 157 enable-method = "psci";
159 capacity-dmips-mhz = < 158 capacity-dmips-mhz = <1024>;
160 cpu-idle-states = <&LI 159 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
161 next-level-cache = <&L 160 next-level-cache = <&L2_0>;
162 }; 161 };
163 162
164 CPU2: cpu@2 { 163 CPU2: cpu@2 {
165 device_type = "cpu"; 164 device_type = "cpu";
166 compatible = "qcom,kry 165 compatible = "qcom,kryo280";
167 reg = <0x0 0x2>; 166 reg = <0x0 0x2>;
168 enable-method = "psci" 167 enable-method = "psci";
169 capacity-dmips-mhz = < 168 capacity-dmips-mhz = <1024>;
170 cpu-idle-states = <&LI 169 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
171 next-level-cache = <&L 170 next-level-cache = <&L2_0>;
172 }; 171 };
173 172
174 CPU3: cpu@3 { 173 CPU3: cpu@3 {
175 device_type = "cpu"; 174 device_type = "cpu";
176 compatible = "qcom,kry 175 compatible = "qcom,kryo280";
177 reg = <0x0 0x3>; 176 reg = <0x0 0x3>;
178 enable-method = "psci" 177 enable-method = "psci";
179 capacity-dmips-mhz = < 178 capacity-dmips-mhz = <1024>;
180 cpu-idle-states = <&LI 179 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
181 next-level-cache = <&L 180 next-level-cache = <&L2_0>;
182 }; 181 };
183 182
184 CPU4: cpu@100 { 183 CPU4: cpu@100 {
185 device_type = "cpu"; 184 device_type = "cpu";
186 compatible = "qcom,kry 185 compatible = "qcom,kryo280";
187 reg = <0x0 0x100>; 186 reg = <0x0 0x100>;
188 enable-method = "psci" 187 enable-method = "psci";
189 capacity-dmips-mhz = < 188 capacity-dmips-mhz = <1536>;
190 cpu-idle-states = <&BI 189 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
191 next-level-cache = <&L 190 next-level-cache = <&L2_1>;
192 L2_1: l2-cache { 191 L2_1: l2-cache {
193 compatible = " 192 compatible = "cache";
194 cache-level = 193 cache-level = <2>;
195 cache-unified; 194 cache-unified;
196 }; 195 };
197 }; 196 };
198 197
199 CPU5: cpu@101 { 198 CPU5: cpu@101 {
200 device_type = "cpu"; 199 device_type = "cpu";
201 compatible = "qcom,kry 200 compatible = "qcom,kryo280";
202 reg = <0x0 0x101>; 201 reg = <0x0 0x101>;
203 enable-method = "psci" 202 enable-method = "psci";
204 capacity-dmips-mhz = < 203 capacity-dmips-mhz = <1536>;
205 cpu-idle-states = <&BI 204 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
206 next-level-cache = <&L 205 next-level-cache = <&L2_1>;
207 }; 206 };
208 207
209 CPU6: cpu@102 { 208 CPU6: cpu@102 {
210 device_type = "cpu"; 209 device_type = "cpu";
211 compatible = "qcom,kry 210 compatible = "qcom,kryo280";
212 reg = <0x0 0x102>; 211 reg = <0x0 0x102>;
213 enable-method = "psci" 212 enable-method = "psci";
214 capacity-dmips-mhz = < 213 capacity-dmips-mhz = <1536>;
215 cpu-idle-states = <&BI 214 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
216 next-level-cache = <&L 215 next-level-cache = <&L2_1>;
217 }; 216 };
218 217
219 CPU7: cpu@103 { 218 CPU7: cpu@103 {
220 device_type = "cpu"; 219 device_type = "cpu";
221 compatible = "qcom,kry 220 compatible = "qcom,kryo280";
222 reg = <0x0 0x103>; 221 reg = <0x0 0x103>;
223 enable-method = "psci" 222 enable-method = "psci";
224 capacity-dmips-mhz = < 223 capacity-dmips-mhz = <1536>;
225 cpu-idle-states = <&BI 224 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
226 next-level-cache = <&L 225 next-level-cache = <&L2_1>;
227 }; 226 };
228 227
229 cpu-map { 228 cpu-map {
230 cluster0 { 229 cluster0 {
231 core0 { 230 core0 {
232 cpu = 231 cpu = <&CPU0>;
233 }; 232 };
234 233
235 core1 { 234 core1 {
236 cpu = 235 cpu = <&CPU1>;
237 }; 236 };
238 237
239 core2 { 238 core2 {
240 cpu = 239 cpu = <&CPU2>;
241 }; 240 };
242 241
243 core3 { 242 core3 {
244 cpu = 243 cpu = <&CPU3>;
245 }; 244 };
246 }; 245 };
247 246
248 cluster1 { 247 cluster1 {
249 core0 { 248 core0 {
250 cpu = 249 cpu = <&CPU4>;
251 }; 250 };
252 251
253 core1 { 252 core1 {
254 cpu = 253 cpu = <&CPU5>;
255 }; 254 };
256 255
257 core2 { 256 core2 {
258 cpu = 257 cpu = <&CPU6>;
259 }; 258 };
260 259
261 core3 { 260 core3 {
262 cpu = 261 cpu = <&CPU7>;
263 }; 262 };
264 }; 263 };
265 }; 264 };
266 265
267 idle-states { 266 idle-states {
268 entry-method = "psci"; 267 entry-method = "psci";
269 268
270 LITTLE_CPU_SLEEP_0: cp 269 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
271 compatible = " 270 compatible = "arm,idle-state";
272 idle-state-nam 271 idle-state-name = "little-retention";
273 /* CPU Retenti 272 /* CPU Retention (C2D), L2 Active */
274 arm,psci-suspe 273 arm,psci-suspend-param = <0x00000002>;
275 entry-latency- 274 entry-latency-us = <81>;
276 exit-latency-u 275 exit-latency-us = <86>;
277 min-residency- 276 min-residency-us = <504>;
278 }; 277 };
279 278
280 LITTLE_CPU_SLEEP_1: cp 279 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
281 compatible = " 280 compatible = "arm,idle-state";
282 idle-state-nam 281 idle-state-name = "little-power-collapse";
283 /* CPU + L2 Po 282 /* CPU + L2 Power Collapse (C3, D4) */
284 arm,psci-suspe 283 arm,psci-suspend-param = <0x40000003>;
285 entry-latency- 284 entry-latency-us = <814>;
286 exit-latency-u 285 exit-latency-us = <4562>;
287 min-residency- 286 min-residency-us = <9183>;
288 local-timer-st 287 local-timer-stop;
289 }; 288 };
290 289
291 BIG_CPU_SLEEP_0: cpu-s 290 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
292 compatible = " 291 compatible = "arm,idle-state";
293 idle-state-nam 292 idle-state-name = "big-retention";
294 /* CPU Retenti 293 /* CPU Retention (C2D), L2 Active */
295 arm,psci-suspe 294 arm,psci-suspend-param = <0x00000002>;
296 entry-latency- 295 entry-latency-us = <79>;
297 exit-latency-u 296 exit-latency-us = <82>;
298 min-residency- 297 min-residency-us = <1302>;
299 }; 298 };
300 299
301 BIG_CPU_SLEEP_1: cpu-s 300 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
302 compatible = " 301 compatible = "arm,idle-state";
303 idle-state-nam 302 idle-state-name = "big-power-collapse";
304 /* CPU + L2 Po 303 /* CPU + L2 Power Collapse (C3, D4) */
305 arm,psci-suspe 304 arm,psci-suspend-param = <0x40000003>;
306 entry-latency- 305 entry-latency-us = <724>;
307 exit-latency-u 306 exit-latency-us = <2027>;
308 min-residency- 307 min-residency-us = <9419>;
309 local-timer-st 308 local-timer-stop;
310 }; 309 };
311 }; 310 };
312 }; 311 };
313 312
314 firmware { 313 firmware {
315 scm { 314 scm {
316 compatible = "qcom,scm 315 compatible = "qcom,scm-msm8998", "qcom,scm";
317 }; 316 };
318 }; 317 };
319 318
320 dsi_opp_table: opp-table-dsi { <<
321 compatible = "operating-points <<
322 <<
323 opp-131250000 { <<
324 opp-hz = /bits/ 64 <13 <<
325 required-opps = <&rpmp <<
326 }; <<
327 <<
328 opp-210000000 { <<
329 opp-hz = /bits/ 64 <21 <<
330 required-opps = <&rpmp <<
331 }; <<
332 <<
333 opp-312500000 { <<
334 opp-hz = /bits/ 64 <31 <<
335 required-opps = <&rpmp <<
336 }; <<
337 }; <<
338 <<
339 psci { 319 psci {
340 compatible = "arm,psci-1.0"; 320 compatible = "arm,psci-1.0";
341 method = "smc"; 321 method = "smc";
342 }; 322 };
343 323
344 rpm: remoteproc { !! 324 rpm-glink {
345 compatible = "qcom,msm8998-rpm !! 325 compatible = "qcom,glink-rpm";
>> 326
>> 327 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
>> 328 qcom,rpm-msg-ram = <&rpm_msg_ram>;
>> 329 mboxes = <&apcs_glb 0>;
>> 330
>> 331 rpm_requests: rpm-requests {
>> 332 compatible = "qcom,rpm-msm8998";
>> 333 qcom,glink-channels = "rpm_requests";
>> 334
>> 335 rpmcc: clock-controller {
>> 336 compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc";
>> 337 #clock-cells = <1>;
>> 338 };
>> 339
>> 340 rpmpd: power-controller {
>> 341 compatible = "qcom,msm8998-rpmpd";
>> 342 #power-domain-cells = <1>;
>> 343 operating-points-v2 = <&rpmpd_opp_table>;
>> 344
>> 345 rpmpd_opp_table: opp-table {
>> 346 compatible = "operating-points-v2";
>> 347
>> 348 rpmpd_opp_ret: opp1 {
>> 349 opp-level = <RPM_SMD_LEVEL_RETENTION>;
>> 350 };
>> 351
>> 352 rpmpd_opp_ret_plus: opp2 {
>> 353 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
>> 354 };
>> 355
>> 356 rpmpd_opp_min_svs: opp3 {
>> 357 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
>> 358 };
>> 359
>> 360 rpmpd_opp_low_svs: opp4 {
>> 361 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
>> 362 };
>> 363
>> 364 rpmpd_opp_svs: opp5 {
>> 365 opp-level = <RPM_SMD_LEVEL_SVS>;
>> 366 };
>> 367
>> 368 rpmpd_opp_svs_plus: opp6 {
>> 369 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
>> 370 };
>> 371
>> 372 rpmpd_opp_nom: opp7 {
>> 373 opp-level = <RPM_SMD_LEVEL_NOM>;
>> 374 };
>> 375
>> 376 rpmpd_opp_nom_plus: opp8 {
>> 377 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
>> 378 };
346 379
347 glink-edge { !! 380 rpmpd_opp_turbo: opp9 {
348 compatible = "qcom,gli !! 381 opp-level = <RPM_SMD_LEVEL_TURBO>;
>> 382 };
349 383
350 interrupts = <GIC_SPI !! 384 rpmpd_opp_turbo_plus: opp10 {
351 qcom,rpm-msg-ram = <&r !! 385 opp-level = <RPM_SMD_LEVEL_BINNING>;
352 mboxes = <&apcs_glb 0> <<
353 <<
354 rpm_requests: rpm-requ <<
355 compatible = " <<
356 qcom,glink-cha <<
357 <<
358 rpmcc: clock-c <<
359 compat <<
360 clocks <<
361 clock- <<
362 #clock <<
363 }; <<
364 <<
365 rpmpd: power-c <<
366 compat <<
367 #power <<
368 operat <<
369 <<
370 rpmpd_ <<
371 <<
372 <<
373 <<
374 <<
375 <<
376 <<
377 <<
378 <<
379 <<
380 <<
381 <<
382 <<
383 <<
384 <<
385 <<
386 <<
387 <<
388 <<
389 <<
390 <<
391 <<
392 <<
393 <<
394 <<
395 <<
396 <<
397 <<
398 <<
399 <<
400 <<
401 <<
402 <<
403 <<
404 <<
405 <<
406 <<
407 <<
408 <<
409 <<
410 <<
411 <<
412 }; 386 };
413 }; 387 };
414 }; 388 };
415 }; 389 };
416 }; 390 };
417 391
418 smem { 392 smem {
419 compatible = "qcom,smem"; 393 compatible = "qcom,smem";
420 memory-region = <&smem_mem>; 394 memory-region = <&smem_mem>;
421 hwlocks = <&tcsr_mutex 3>; 395 hwlocks = <&tcsr_mutex 3>;
422 }; 396 };
423 397
424 smp2p-lpass { 398 smp2p-lpass {
425 compatible = "qcom,smp2p"; 399 compatible = "qcom,smp2p";
426 qcom,smem = <443>, <429>; 400 qcom,smem = <443>, <429>;
427 401
428 interrupts = <GIC_SPI 158 IRQ_ 402 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
429 403
430 mboxes = <&apcs_glb 10>; 404 mboxes = <&apcs_glb 10>;
431 405
432 qcom,local-pid = <0>; 406 qcom,local-pid = <0>;
433 qcom,remote-pid = <2>; 407 qcom,remote-pid = <2>;
434 408
435 adsp_smp2p_out: master-kernel 409 adsp_smp2p_out: master-kernel {
436 qcom,entry-name = "mas 410 qcom,entry-name = "master-kernel";
437 #qcom,smem-state-cells 411 #qcom,smem-state-cells = <1>;
438 }; 412 };
439 413
440 adsp_smp2p_in: slave-kernel { 414 adsp_smp2p_in: slave-kernel {
441 qcom,entry-name = "sla 415 qcom,entry-name = "slave-kernel";
442 416
443 interrupt-controller; 417 interrupt-controller;
444 #interrupt-cells = <2> 418 #interrupt-cells = <2>;
445 }; 419 };
446 }; 420 };
447 421
448 smp2p-mpss { 422 smp2p-mpss {
449 compatible = "qcom,smp2p"; 423 compatible = "qcom,smp2p";
450 qcom,smem = <435>, <428>; 424 qcom,smem = <435>, <428>;
451 interrupts = <GIC_SPI 451 IRQ_ 425 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
452 mboxes = <&apcs_glb 14>; 426 mboxes = <&apcs_glb 14>;
453 qcom,local-pid = <0>; 427 qcom,local-pid = <0>;
454 qcom,remote-pid = <1>; 428 qcom,remote-pid = <1>;
455 429
456 modem_smp2p_out: master-kernel 430 modem_smp2p_out: master-kernel {
457 qcom,entry-name = "mas 431 qcom,entry-name = "master-kernel";
458 #qcom,smem-state-cells 432 #qcom,smem-state-cells = <1>;
459 }; 433 };
460 434
461 modem_smp2p_in: slave-kernel { 435 modem_smp2p_in: slave-kernel {
462 qcom,entry-name = "sla 436 qcom,entry-name = "slave-kernel";
463 interrupt-controller; 437 interrupt-controller;
464 #interrupt-cells = <2> 438 #interrupt-cells = <2>;
465 }; 439 };
466 }; 440 };
467 441
468 smp2p-slpi { 442 smp2p-slpi {
469 compatible = "qcom,smp2p"; 443 compatible = "qcom,smp2p";
470 qcom,smem = <481>, <430>; 444 qcom,smem = <481>, <430>;
471 interrupts = <GIC_SPI 178 IRQ_ 445 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
472 mboxes = <&apcs_glb 26>; 446 mboxes = <&apcs_glb 26>;
473 qcom,local-pid = <0>; 447 qcom,local-pid = <0>;
474 qcom,remote-pid = <3>; 448 qcom,remote-pid = <3>;
475 449
476 slpi_smp2p_out: master-kernel 450 slpi_smp2p_out: master-kernel {
477 qcom,entry-name = "mas 451 qcom,entry-name = "master-kernel";
478 #qcom,smem-state-cells 452 #qcom,smem-state-cells = <1>;
479 }; 453 };
480 454
481 slpi_smp2p_in: slave-kernel { 455 slpi_smp2p_in: slave-kernel {
482 qcom,entry-name = "sla 456 qcom,entry-name = "slave-kernel";
483 interrupt-controller; 457 interrupt-controller;
484 #interrupt-cells = <2> 458 #interrupt-cells = <2>;
485 }; 459 };
486 }; 460 };
487 461
488 thermal-zones { 462 thermal-zones {
489 cpu0-thermal { 463 cpu0-thermal {
490 polling-delay-passive 464 polling-delay-passive = <250>;
>> 465 polling-delay = <1000>;
491 466
492 thermal-sensors = <&ts 467 thermal-sensors = <&tsens0 1>;
493 468
494 trips { 469 trips {
495 cpu0_alert0: t 470 cpu0_alert0: trip-point0 {
496 temper 471 temperature = <75000>;
497 hyster 472 hysteresis = <2000>;
498 type = 473 type = "passive";
499 }; 474 };
500 475
501 cpu0_crit: cpu 476 cpu0_crit: cpu-crit {
502 temper 477 temperature = <110000>;
503 hyster 478 hysteresis = <2000>;
504 type = 479 type = "critical";
505 }; 480 };
506 }; 481 };
507 }; 482 };
508 483
509 cpu1-thermal { 484 cpu1-thermal {
510 polling-delay-passive 485 polling-delay-passive = <250>;
>> 486 polling-delay = <1000>;
511 487
512 thermal-sensors = <&ts 488 thermal-sensors = <&tsens0 2>;
513 489
514 trips { 490 trips {
515 cpu1_alert0: t 491 cpu1_alert0: trip-point0 {
516 temper 492 temperature = <75000>;
517 hyster 493 hysteresis = <2000>;
518 type = 494 type = "passive";
519 }; 495 };
520 496
521 cpu1_crit: cpu 497 cpu1_crit: cpu-crit {
522 temper 498 temperature = <110000>;
523 hyster 499 hysteresis = <2000>;
524 type = 500 type = "critical";
525 }; 501 };
526 }; 502 };
527 }; 503 };
528 504
529 cpu2-thermal { 505 cpu2-thermal {
530 polling-delay-passive 506 polling-delay-passive = <250>;
>> 507 polling-delay = <1000>;
531 508
532 thermal-sensors = <&ts 509 thermal-sensors = <&tsens0 3>;
533 510
534 trips { 511 trips {
535 cpu2_alert0: t 512 cpu2_alert0: trip-point0 {
536 temper 513 temperature = <75000>;
537 hyster 514 hysteresis = <2000>;
538 type = 515 type = "passive";
539 }; 516 };
540 517
541 cpu2_crit: cpu 518 cpu2_crit: cpu-crit {
542 temper 519 temperature = <110000>;
543 hyster 520 hysteresis = <2000>;
544 type = 521 type = "critical";
545 }; 522 };
546 }; 523 };
547 }; 524 };
548 525
549 cpu3-thermal { 526 cpu3-thermal {
550 polling-delay-passive 527 polling-delay-passive = <250>;
>> 528 polling-delay = <1000>;
551 529
552 thermal-sensors = <&ts 530 thermal-sensors = <&tsens0 4>;
553 531
554 trips { 532 trips {
555 cpu3_alert0: t 533 cpu3_alert0: trip-point0 {
556 temper 534 temperature = <75000>;
557 hyster 535 hysteresis = <2000>;
558 type = 536 type = "passive";
559 }; 537 };
560 538
561 cpu3_crit: cpu 539 cpu3_crit: cpu-crit {
562 temper 540 temperature = <110000>;
563 hyster 541 hysteresis = <2000>;
564 type = 542 type = "critical";
565 }; 543 };
566 }; 544 };
567 }; 545 };
568 546
569 cpu4-thermal { 547 cpu4-thermal {
570 polling-delay-passive 548 polling-delay-passive = <250>;
>> 549 polling-delay = <1000>;
571 550
572 thermal-sensors = <&ts 551 thermal-sensors = <&tsens0 7>;
573 552
574 trips { 553 trips {
575 cpu4_alert0: t 554 cpu4_alert0: trip-point0 {
576 temper 555 temperature = <75000>;
577 hyster 556 hysteresis = <2000>;
578 type = 557 type = "passive";
579 }; 558 };
580 559
581 cpu4_crit: cpu 560 cpu4_crit: cpu-crit {
582 temper 561 temperature = <110000>;
583 hyster 562 hysteresis = <2000>;
584 type = 563 type = "critical";
585 }; 564 };
586 }; 565 };
587 }; 566 };
588 567
589 cpu5-thermal { 568 cpu5-thermal {
590 polling-delay-passive 569 polling-delay-passive = <250>;
>> 570 polling-delay = <1000>;
591 571
592 thermal-sensors = <&ts 572 thermal-sensors = <&tsens0 8>;
593 573
594 trips { 574 trips {
595 cpu5_alert0: t 575 cpu5_alert0: trip-point0 {
596 temper 576 temperature = <75000>;
597 hyster 577 hysteresis = <2000>;
598 type = 578 type = "passive";
599 }; 579 };
600 580
601 cpu5_crit: cpu 581 cpu5_crit: cpu-crit {
602 temper 582 temperature = <110000>;
603 hyster 583 hysteresis = <2000>;
604 type = 584 type = "critical";
605 }; 585 };
606 }; 586 };
607 }; 587 };
608 588
609 cpu6-thermal { 589 cpu6-thermal {
610 polling-delay-passive 590 polling-delay-passive = <250>;
>> 591 polling-delay = <1000>;
611 592
612 thermal-sensors = <&ts 593 thermal-sensors = <&tsens0 9>;
613 594
614 trips { 595 trips {
615 cpu6_alert0: t 596 cpu6_alert0: trip-point0 {
616 temper 597 temperature = <75000>;
617 hyster 598 hysteresis = <2000>;
618 type = 599 type = "passive";
619 }; 600 };
620 601
621 cpu6_crit: cpu 602 cpu6_crit: cpu-crit {
622 temper 603 temperature = <110000>;
623 hyster 604 hysteresis = <2000>;
624 type = 605 type = "critical";
625 }; 606 };
626 }; 607 };
627 }; 608 };
628 609
629 cpu7-thermal { 610 cpu7-thermal {
630 polling-delay-passive 611 polling-delay-passive = <250>;
>> 612 polling-delay = <1000>;
631 613
632 thermal-sensors = <&ts 614 thermal-sensors = <&tsens0 10>;
633 615
634 trips { 616 trips {
635 cpu7_alert0: t 617 cpu7_alert0: trip-point0 {
636 temper 618 temperature = <75000>;
637 hyster 619 hysteresis = <2000>;
638 type = 620 type = "passive";
639 }; 621 };
640 622
641 cpu7_crit: cpu 623 cpu7_crit: cpu-crit {
642 temper 624 temperature = <110000>;
643 hyster 625 hysteresis = <2000>;
644 type = 626 type = "critical";
645 }; 627 };
646 }; 628 };
647 }; 629 };
648 630
649 gpu-bottom-thermal { 631 gpu-bottom-thermal {
650 polling-delay-passive 632 polling-delay-passive = <250>;
>> 633 polling-delay = <1000>;
651 634
652 thermal-sensors = <&ts 635 thermal-sensors = <&tsens0 12>;
653 636
654 trips { 637 trips {
655 gpu1_alert0: t 638 gpu1_alert0: trip-point0 {
656 temper 639 temperature = <90000>;
657 hyster 640 hysteresis = <2000>;
658 type = 641 type = "hot";
659 }; 642 };
660 }; 643 };
661 }; 644 };
662 645
663 gpu-top-thermal { 646 gpu-top-thermal {
664 polling-delay-passive 647 polling-delay-passive = <250>;
>> 648 polling-delay = <1000>;
665 649
666 thermal-sensors = <&ts 650 thermal-sensors = <&tsens0 13>;
667 651
668 trips { 652 trips {
669 gpu2_alert0: t 653 gpu2_alert0: trip-point0 {
670 temper 654 temperature = <90000>;
671 hyster 655 hysteresis = <2000>;
672 type = 656 type = "hot";
673 }; 657 };
674 }; 658 };
675 }; 659 };
676 660
677 clust0-mhm-thermal { 661 clust0-mhm-thermal {
678 polling-delay-passive 662 polling-delay-passive = <250>;
>> 663 polling-delay = <1000>;
679 664
680 thermal-sensors = <&ts 665 thermal-sensors = <&tsens0 5>;
681 666
682 trips { 667 trips {
683 cluster0_mhm_a 668 cluster0_mhm_alert0: trip-point0 {
684 temper 669 temperature = <90000>;
685 hyster 670 hysteresis = <2000>;
686 type = 671 type = "hot";
687 }; 672 };
688 }; 673 };
689 }; 674 };
690 675
691 clust1-mhm-thermal { 676 clust1-mhm-thermal {
692 polling-delay-passive 677 polling-delay-passive = <250>;
>> 678 polling-delay = <1000>;
693 679
694 thermal-sensors = <&ts 680 thermal-sensors = <&tsens0 6>;
695 681
696 trips { 682 trips {
697 cluster1_mhm_a 683 cluster1_mhm_alert0: trip-point0 {
698 temper 684 temperature = <90000>;
699 hyster 685 hysteresis = <2000>;
700 type = 686 type = "hot";
701 }; 687 };
702 }; 688 };
703 }; 689 };
704 690
705 cluster1-l2-thermal { 691 cluster1-l2-thermal {
706 polling-delay-passive 692 polling-delay-passive = <250>;
>> 693 polling-delay = <1000>;
707 694
708 thermal-sensors = <&ts 695 thermal-sensors = <&tsens0 11>;
709 696
710 trips { 697 trips {
711 cluster1_l2_al 698 cluster1_l2_alert0: trip-point0 {
712 temper 699 temperature = <90000>;
713 hyster 700 hysteresis = <2000>;
714 type = 701 type = "hot";
715 }; 702 };
716 }; 703 };
717 }; 704 };
718 705
719 modem-thermal { 706 modem-thermal {
720 polling-delay-passive 707 polling-delay-passive = <250>;
>> 708 polling-delay = <1000>;
721 709
722 thermal-sensors = <&ts 710 thermal-sensors = <&tsens1 1>;
723 711
724 trips { 712 trips {
725 modem_alert0: 713 modem_alert0: trip-point0 {
726 temper 714 temperature = <90000>;
727 hyster 715 hysteresis = <2000>;
728 type = 716 type = "hot";
729 }; 717 };
730 }; 718 };
731 }; 719 };
732 720
733 mem-thermal { 721 mem-thermal {
734 polling-delay-passive 722 polling-delay-passive = <250>;
>> 723 polling-delay = <1000>;
735 724
736 thermal-sensors = <&ts 725 thermal-sensors = <&tsens1 2>;
737 726
738 trips { 727 trips {
739 mem_alert0: tr 728 mem_alert0: trip-point0 {
740 temper 729 temperature = <90000>;
741 hyster 730 hysteresis = <2000>;
742 type = 731 type = "hot";
743 }; 732 };
744 }; 733 };
745 }; 734 };
746 735
747 wlan-thermal { 736 wlan-thermal {
748 polling-delay-passive 737 polling-delay-passive = <250>;
>> 738 polling-delay = <1000>;
749 739
750 thermal-sensors = <&ts 740 thermal-sensors = <&tsens1 3>;
751 741
752 trips { 742 trips {
753 wlan_alert0: t 743 wlan_alert0: trip-point0 {
754 temper 744 temperature = <90000>;
755 hyster 745 hysteresis = <2000>;
756 type = 746 type = "hot";
757 }; 747 };
758 }; 748 };
759 }; 749 };
760 750
761 q6-dsp-thermal { 751 q6-dsp-thermal {
762 polling-delay-passive 752 polling-delay-passive = <250>;
>> 753 polling-delay = <1000>;
763 754
764 thermal-sensors = <&ts 755 thermal-sensors = <&tsens1 4>;
765 756
766 trips { 757 trips {
767 q6_dsp_alert0: 758 q6_dsp_alert0: trip-point0 {
768 temper 759 temperature = <90000>;
769 hyster 760 hysteresis = <2000>;
770 type = 761 type = "hot";
771 }; 762 };
772 }; 763 };
773 }; 764 };
774 765
775 camera-thermal { 766 camera-thermal {
776 polling-delay-passive 767 polling-delay-passive = <250>;
>> 768 polling-delay = <1000>;
777 769
778 thermal-sensors = <&ts 770 thermal-sensors = <&tsens1 5>;
779 771
780 trips { 772 trips {
781 camera_alert0: 773 camera_alert0: trip-point0 {
782 temper 774 temperature = <90000>;
783 hyster 775 hysteresis = <2000>;
784 type = 776 type = "hot";
785 }; 777 };
786 }; 778 };
787 }; 779 };
788 780
789 multimedia-thermal { 781 multimedia-thermal {
790 polling-delay-passive 782 polling-delay-passive = <250>;
>> 783 polling-delay = <1000>;
791 784
792 thermal-sensors = <&ts 785 thermal-sensors = <&tsens1 6>;
793 786
794 trips { 787 trips {
795 multimedia_ale 788 multimedia_alert0: trip-point0 {
796 temper 789 temperature = <90000>;
797 hyster 790 hysteresis = <2000>;
798 type = 791 type = "hot";
799 }; 792 };
800 }; 793 };
801 }; 794 };
802 }; 795 };
803 796
804 timer { 797 timer {
805 compatible = "arm,armv8-timer" 798 compatible = "arm,armv8-timer";
806 interrupts = <GIC_PPI 1 IRQ_TY 799 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
807 <GIC_PPI 2 IRQ_TY 800 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
808 <GIC_PPI 3 IRQ_TY 801 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
809 <GIC_PPI 0 IRQ_TY 802 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
810 }; 803 };
811 804
812 soc: soc@0 { 805 soc: soc@0 {
813 #address-cells = <1>; 806 #address-cells = <1>;
814 #size-cells = <1>; 807 #size-cells = <1>;
815 ranges = <0 0 0 0xffffffff>; 808 ranges = <0 0 0 0xffffffff>;
816 compatible = "simple-bus"; 809 compatible = "simple-bus";
817 810
818 gcc: clock-controller@100000 { 811 gcc: clock-controller@100000 {
819 compatible = "qcom,gcc 812 compatible = "qcom,gcc-msm8998";
820 #clock-cells = <1>; 813 #clock-cells = <1>;
821 #reset-cells = <1>; 814 #reset-cells = <1>;
822 #power-domain-cells = 815 #power-domain-cells = <1>;
823 reg = <0x00100000 0xb0 816 reg = <0x00100000 0xb0000>;
824 817
825 clock-names = "xo", "s 818 clock-names = "xo", "sleep_clk";
826 clocks = <&rpmcc RPM_S 819 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>;
827 820
828 /* 821 /*
829 * The hypervisor typi 822 * The hypervisor typically configures the memory region where these clocks
830 * reside as read-only 823 * reside as read-only for the HLOS. If the HLOS tried to enable or disable
831 * these clocks on a d 824 * these clocks on a device with such configuration (e.g. because they are
832 * enabled but unused 825 * enabled but unused during boot-up), the device will most likely decide
833 * to reboot. 826 * to reboot.
834 * In light of that, w 827 * In light of that, we are conservative here and we list all such clocks
835 * as protected. The b 828 * as protected. The board dts (or a user-supplied dts) can override the
836 * list of protected c 829 * list of protected clocks if it differs from the norm, and it is in fact
837 * desired for the HLO 830 * desired for the HLOS to manage these clocks
838 */ 831 */
839 protected-clocks = <AG 832 protected-clocks = <AGGRE2_SNOC_NORTH_AXI>,
840 <SS 833 <SSC_XO>,
841 <SS 834 <SSC_CNOC_AHBS_CLK>;
842 }; 835 };
843 836
844 rpm_msg_ram: sram@778000 { 837 rpm_msg_ram: sram@778000 {
845 compatible = "qcom,rpm 838 compatible = "qcom,rpm-msg-ram";
846 reg = <0x00778000 0x70 839 reg = <0x00778000 0x7000>;
847 }; 840 };
848 841
849 qfprom: qfprom@784000 { 842 qfprom: qfprom@784000 {
850 compatible = "qcom,msm 843 compatible = "qcom,msm8998-qfprom", "qcom,qfprom";
851 reg = <0x00784000 0x62 844 reg = <0x00784000 0x621c>;
852 #address-cells = <1>; 845 #address-cells = <1>;
853 #size-cells = <1>; 846 #size-cells = <1>;
854 847
855 qusb2_hstx_trim: hstx- 848 qusb2_hstx_trim: hstx-trim@23a {
856 reg = <0x23a 0 849 reg = <0x23a 0x1>;
857 bits = <0 4>; 850 bits = <0 4>;
858 }; 851 };
859 }; 852 };
860 853
861 tsens0: thermal@10ab000 { 854 tsens0: thermal@10ab000 {
862 compatible = "qcom,msm 855 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
863 reg = <0x010ab000 0x10 856 reg = <0x010ab000 0x1000>, /* TM */
864 <0x010aa000 0x10 857 <0x010aa000 0x1000>; /* SROT */
865 #qcom,sensors = <14>; 858 #qcom,sensors = <14>;
866 interrupts = <GIC_SPI 859 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
867 <GIC_SPI 860 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
868 interrupt-names = "upl 861 interrupt-names = "uplow", "critical";
869 #thermal-sensor-cells 862 #thermal-sensor-cells = <1>;
870 }; 863 };
871 864
872 tsens1: thermal@10ae000 { 865 tsens1: thermal@10ae000 {
873 compatible = "qcom,msm 866 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
874 reg = <0x010ae000 0x10 867 reg = <0x010ae000 0x1000>, /* TM */
875 <0x010ad000 0x10 868 <0x010ad000 0x1000>; /* SROT */
876 #qcom,sensors = <8>; 869 #qcom,sensors = <8>;
877 interrupts = <GIC_SPI 870 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
878 <GIC_SPI 871 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
879 interrupt-names = "upl 872 interrupt-names = "uplow", "critical";
880 #thermal-sensor-cells 873 #thermal-sensor-cells = <1>;
881 }; 874 };
882 875
883 anoc1_smmu: iommu@1680000 { 876 anoc1_smmu: iommu@1680000 {
884 compatible = "qcom,msm 877 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
885 reg = <0x01680000 0x10 878 reg = <0x01680000 0x10000>;
886 #iommu-cells = <1>; 879 #iommu-cells = <1>;
887 880
888 #global-interrupts = < 881 #global-interrupts = <0>;
889 interrupts = 882 interrupts =
890 <GIC_SPI 364 I 883 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
891 <GIC_SPI 365 I 884 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
892 <GIC_SPI 366 I 885 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
893 <GIC_SPI 367 I 886 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
894 <GIC_SPI 368 I 887 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
895 <GIC_SPI 369 I 888 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>;
896 }; 889 };
897 890
898 anoc2_smmu: iommu@16c0000 { 891 anoc2_smmu: iommu@16c0000 {
899 compatible = "qcom,msm 892 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
900 reg = <0x016c0000 0x40 893 reg = <0x016c0000 0x40000>;
901 #iommu-cells = <1>; 894 #iommu-cells = <1>;
902 895
903 #global-interrupts = < 896 #global-interrupts = <0>;
904 interrupts = 897 interrupts =
905 <GIC_SPI 373 I 898 <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>,
906 <GIC_SPI 374 I 899 <GIC_SPI 374 IRQ_TYPE_EDGE_RISING>,
907 <GIC_SPI 375 I 900 <GIC_SPI 375 IRQ_TYPE_EDGE_RISING>,
908 <GIC_SPI 376 I 901 <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>,
909 <GIC_SPI 377 I 902 <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>,
910 <GIC_SPI 378 I 903 <GIC_SPI 378 IRQ_TYPE_EDGE_RISING>,
911 <GIC_SPI 462 I 904 <GIC_SPI 462 IRQ_TYPE_EDGE_RISING>,
912 <GIC_SPI 463 I 905 <GIC_SPI 463 IRQ_TYPE_EDGE_RISING>,
913 <GIC_SPI 464 I 906 <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
914 <GIC_SPI 465 I 907 <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>;
915 }; 908 };
916 909
917 pcie0: pcie@1c00000 { !! 910 pcie0: pci@1c00000 {
918 compatible = "qcom,pci 911 compatible = "qcom,pcie-msm8998", "qcom,pcie-msm8996";
919 reg = <0x01c00000 0x20 912 reg = <0x01c00000 0x2000>,
920 <0x1b000000 0xf1 913 <0x1b000000 0xf1d>,
921 <0x1b000f20 0xa8 914 <0x1b000f20 0xa8>,
922 <0x1b100000 0x10 915 <0x1b100000 0x100000>;
923 reg-names = "parf", "d 916 reg-names = "parf", "dbi", "elbi", "config";
924 device_type = "pci"; 917 device_type = "pci";
925 linux,pci-domain = <0> 918 linux,pci-domain = <0>;
926 bus-range = <0x00 0xff 919 bus-range = <0x00 0xff>;
927 #address-cells = <3>; 920 #address-cells = <3>;
928 #size-cells = <2>; 921 #size-cells = <2>;
929 num-lanes = <1>; 922 num-lanes = <1>;
930 phys = <&pcie_phy>; !! 923 phys = <&pciephy>;
931 phy-names = "pciephy"; 924 phy-names = "pciephy";
932 status = "disabled"; 925 status = "disabled";
933 926
934 ranges = <0x01000000 0 927 ranges = <0x01000000 0x0 0x00000000 0x1b200000 0x0 0x100000>,
935 <0x02000000 0 928 <0x02000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>;
936 929
937 #interrupt-cells = <1> 930 #interrupt-cells = <1>;
938 interrupts = <GIC_SPI 931 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
939 interrupt-names = "msi 932 interrupt-names = "msi";
940 interrupt-map-mask = < 933 interrupt-map-mask = <0 0 0 0x7>;
941 interrupt-map = <0 0 0 934 interrupt-map = <0 0 0 1 &intc 0 0 135 IRQ_TYPE_LEVEL_HIGH>,
942 <0 0 0 935 <0 0 0 2 &intc 0 0 136 IRQ_TYPE_LEVEL_HIGH>,
943 <0 0 0 936 <0 0 0 3 &intc 0 0 138 IRQ_TYPE_LEVEL_HIGH>,
944 <0 0 0 937 <0 0 0 4 &intc 0 0 139 IRQ_TYPE_LEVEL_HIGH>;
945 938
946 clocks = <&gcc GCC_PCI 939 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
947 <&gcc GCC_PCI 940 <&gcc GCC_PCIE_0_AUX_CLK>,
948 <&gcc GCC_PCI 941 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
949 <&gcc GCC_PCI 942 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
950 <&gcc GCC_PCI 943 <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
951 clock-names = "pipe", 944 clock-names = "pipe", "aux", "cfg", "bus_master", "bus_slave";
952 945
953 power-domains = <&gcc 946 power-domains = <&gcc PCIE_0_GDSC>;
954 iommu-map = <0x100 &an 947 iommu-map = <0x100 &anoc1_smmu 0x1480 1>;
955 perst-gpios = <&tlmm 3 948 perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
956 <<
957 pcie@0 { <<
958 device_type = <<
959 reg = <0x0 0x0 <<
960 bus-range = <0 <<
961 <<
962 #address-cells <<
963 #size-cells = <<
964 ranges; <<
965 }; <<
966 }; 949 };
967 950
968 pcie_phy: phy@1c06000 { 951 pcie_phy: phy@1c06000 {
969 compatible = "qcom,msm 952 compatible = "qcom,msm8998-qmp-pcie-phy";
970 reg = <0x01c06000 0x10 !! 953 reg = <0x01c06000 0x18c>;
>> 954 #address-cells = <1>;
>> 955 #size-cells = <1>;
971 status = "disabled"; 956 status = "disabled";
>> 957 ranges;
972 958
973 clocks = <&gcc GCC_PCI 959 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
974 <&gcc GCC_PCI 960 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
975 <&gcc GCC_PCI !! 961 <&gcc GCC_PCIE_CLKREF_CLK>;
976 <&gcc GCC_PCI !! 962 clock-names = "aux", "cfg_ahb", "ref";
977 clock-names = "aux", <<
978 "cfg_ahb <<
979 "ref", <<
980 "pipe"; <<
981 <<
982 clock-output-names = " <<
983 #clock-cells = <0>; <<
984 <<
985 #phy-cells = <0>; <<
986 963
987 resets = <&gcc GCC_PCI 964 resets = <&gcc GCC_PCIE_0_PHY_BCR>, <&gcc GCC_PCIE_PHY_BCR>;
988 reset-names = "phy", " 965 reset-names = "phy", "common";
989 966
990 vdda-phy-supply = <&vr 967 vdda-phy-supply = <&vreg_l1a_0p875>;
991 vdda-pll-supply = <&vr 968 vdda-pll-supply = <&vreg_l2a_1p2>;
>> 969
>> 970 pciephy: phy@1c06800 {
>> 971 reg = <0x01c06200 0x128>, <0x01c06400 0x1fc>, <0x01c06800 0x20c>;
>> 972 #phy-cells = <0>;
>> 973
>> 974 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
>> 975 clock-names = "pipe0";
>> 976 clock-output-names = "pcie_0_pipe_clk_src";
>> 977 #clock-cells = <0>;
>> 978 };
992 }; 979 };
993 980
994 ufshc: ufshc@1da4000 { 981 ufshc: ufshc@1da4000 {
995 compatible = "qcom,msm 982 compatible = "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
996 reg = <0x01da4000 0x25 983 reg = <0x01da4000 0x2500>;
997 interrupts = <GIC_SPI 984 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
998 phys = <&ufsphy>; !! 985 phys = <&ufsphy_lanes>;
999 phy-names = "ufsphy"; 986 phy-names = "ufsphy";
1000 lanes-per-direction = 987 lanes-per-direction = <2>;
1001 power-domains = <&gcc 988 power-domains = <&gcc UFS_GDSC>;
1002 status = "disabled"; 989 status = "disabled";
1003 #reset-cells = <1>; 990 #reset-cells = <1>;
1004 991
1005 clock-names = 992 clock-names =
1006 "core_clk", 993 "core_clk",
1007 "bus_aggr_clk 994 "bus_aggr_clk",
1008 "iface_clk", 995 "iface_clk",
1009 "core_clk_uni 996 "core_clk_unipro",
1010 "ref_clk", 997 "ref_clk",
1011 "tx_lane0_syn 998 "tx_lane0_sync_clk",
1012 "rx_lane0_syn 999 "rx_lane0_sync_clk",
1013 "rx_lane1_syn 1000 "rx_lane1_sync_clk";
1014 clocks = 1001 clocks =
1015 <&gcc GCC_UFS 1002 <&gcc GCC_UFS_AXI_CLK>,
1016 <&gcc GCC_AGG 1003 <&gcc GCC_AGGRE1_UFS_AXI_CLK>,
1017 <&gcc GCC_UFS 1004 <&gcc GCC_UFS_AHB_CLK>,
1018 <&gcc GCC_UFS 1005 <&gcc GCC_UFS_UNIPRO_CORE_CLK>,
1019 <&rpmcc RPM_S 1006 <&rpmcc RPM_SMD_LN_BB_CLK1>,
1020 <&gcc GCC_UFS 1007 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
1021 <&gcc GCC_UFS 1008 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>,
1022 <&gcc GCC_UFS 1009 <&gcc GCC_UFS_RX_SYMBOL_1_CLK>;
1023 freq-table-hz = 1010 freq-table-hz =
1024 <50000000 200 1011 <50000000 200000000>,
1025 <0 0>, 1012 <0 0>,
1026 <0 0>, 1013 <0 0>,
1027 <37500000 150 1014 <37500000 150000000>,
1028 <0 0>, 1015 <0 0>,
1029 <0 0>, 1016 <0 0>,
1030 <0 0>, 1017 <0 0>,
1031 <0 0>; 1018 <0 0>;
1032 1019
1033 resets = <&gcc GCC_UF 1020 resets = <&gcc GCC_UFS_BCR>;
1034 reset-names = "rst"; 1021 reset-names = "rst";
1035 }; 1022 };
1036 1023
1037 ufsphy: phy@1da7000 { 1024 ufsphy: phy@1da7000 {
1038 compatible = "qcom,ms 1025 compatible = "qcom,msm8998-qmp-ufs-phy";
1039 reg = <0x01da7000 0x1 !! 1026 reg = <0x01da7000 0x18c>;
>> 1027 #address-cells = <1>;
>> 1028 #size-cells = <1>;
>> 1029 status = "disabled";
>> 1030 ranges;
1040 1031
1041 clocks = <&rpmcc RPM_ !! 1032 clock-names =
1042 <&gcc GCC_UF !! 1033 "ref",
1043 <&gcc GCC_UF !! 1034 "ref_aux";
1044 clock-names = "ref", !! 1035 clocks =
1045 "ref_au !! 1036 <&gcc GCC_UFS_CLKREF_CLK>,
1046 "qref"; !! 1037 <&gcc GCC_UFS_PHY_AUX_CLK>;
1047 1038
1048 reset-names = "ufsphy 1039 reset-names = "ufsphy";
1049 resets = <&ufshc 0>; 1040 resets = <&ufshc 0>;
1050 1041
1051 #phy-cells = <0>; !! 1042 ufsphy_lanes: phy@1da7400 {
1052 status = "disabled"; !! 1043 reg = <0x01da7400 0x128>,
>> 1044 <0x01da7600 0x1fc>,
>> 1045 <0x01da7c00 0x1dc>,
>> 1046 <0x01da7800 0x128>,
>> 1047 <0x01da7a00 0x1fc>;
>> 1048 #phy-cells = <0>;
>> 1049 };
1053 }; 1050 };
1054 1051
1055 tcsr_mutex: hwlock@1f40000 { 1052 tcsr_mutex: hwlock@1f40000 {
1056 compatible = "qcom,tc 1053 compatible = "qcom,tcsr-mutex";
1057 reg = <0x01f40000 0x2 1054 reg = <0x01f40000 0x20000>;
1058 #hwlock-cells = <1>; 1055 #hwlock-cells = <1>;
1059 }; 1056 };
1060 1057
1061 tcsr_regs_1: syscon@1f60000 { 1058 tcsr_regs_1: syscon@1f60000 {
1062 compatible = "qcom,ms 1059 compatible = "qcom,msm8998-tcsr", "syscon";
1063 reg = <0x01f60000 0x2 1060 reg = <0x01f60000 0x20000>;
1064 }; 1061 };
1065 1062
1066 tcsr_regs_2: syscon@1fc0000 { <<
1067 compatible = "qcom,ms <<
1068 reg = <0x01fc0000 0x2 <<
1069 }; <<
1070 <<
1071 tlmm: pinctrl@3400000 { 1063 tlmm: pinctrl@3400000 {
1072 compatible = "qcom,ms 1064 compatible = "qcom,msm8998-pinctrl";
1073 reg = <0x03400000 0xc 1065 reg = <0x03400000 0xc00000>;
1074 interrupts = <GIC_SPI 1066 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1075 gpio-ranges = <&tlmm 1067 gpio-ranges = <&tlmm 0 0 150>;
1076 gpio-controller; 1068 gpio-controller;
1077 #gpio-cells = <2>; 1069 #gpio-cells = <2>;
1078 interrupt-controller; 1070 interrupt-controller;
1079 #interrupt-cells = <2 1071 #interrupt-cells = <2>;
1080 1072
1081 sdc2_on: sdc2-on-stat 1073 sdc2_on: sdc2-on-state {
1082 clk-pins { 1074 clk-pins {
1083 pins 1075 pins = "sdc2_clk";
1084 drive 1076 drive-strength = <16>;
1085 bias- 1077 bias-disable;
1086 }; 1078 };
1087 1079
1088 cmd-pins { 1080 cmd-pins {
1089 pins 1081 pins = "sdc2_cmd";
1090 drive 1082 drive-strength = <10>;
1091 bias- 1083 bias-pull-up;
1092 }; 1084 };
1093 1085
1094 data-pins { 1086 data-pins {
1095 pins 1087 pins = "sdc2_data";
1096 drive 1088 drive-strength = <10>;
1097 bias- 1089 bias-pull-up;
1098 }; 1090 };
1099 }; 1091 };
1100 1092
1101 sdc2_off: sdc2-off-st 1093 sdc2_off: sdc2-off-state {
1102 clk-pins { 1094 clk-pins {
1103 pins 1095 pins = "sdc2_clk";
1104 drive 1096 drive-strength = <2>;
1105 bias- 1097 bias-disable;
1106 }; 1098 };
1107 1099
1108 cmd-pins { 1100 cmd-pins {
1109 pins 1101 pins = "sdc2_cmd";
1110 drive 1102 drive-strength = <2>;
1111 bias- 1103 bias-pull-up;
1112 }; 1104 };
1113 1105
1114 data-pins { 1106 data-pins {
1115 pins 1107 pins = "sdc2_data";
1116 drive 1108 drive-strength = <2>;
1117 bias- 1109 bias-pull-up;
1118 }; 1110 };
1119 }; 1111 };
1120 1112
1121 sdc2_cd: sdc2-cd-stat 1113 sdc2_cd: sdc2-cd-state {
1122 pins = "gpio9 1114 pins = "gpio95";
1123 function = "g 1115 function = "gpio";
1124 bias-pull-up; 1116 bias-pull-up;
1125 drive-strengt 1117 drive-strength = <2>;
1126 }; 1118 };
1127 1119
1128 blsp1_uart3_on: blsp1 1120 blsp1_uart3_on: blsp1-uart3-on-state {
1129 tx-pins { 1121 tx-pins {
1130 pins 1122 pins = "gpio45";
1131 funct 1123 function = "blsp_uart3_a";
1132 drive 1124 drive-strength = <2>;
1133 bias- 1125 bias-disable;
1134 }; 1126 };
1135 1127
1136 rx-pins { 1128 rx-pins {
1137 pins 1129 pins = "gpio46";
1138 funct 1130 function = "blsp_uart3_a";
1139 drive 1131 drive-strength = <2>;
1140 bias- 1132 bias-disable;
1141 }; 1133 };
1142 1134
1143 cts-pins { 1135 cts-pins {
1144 pins 1136 pins = "gpio47";
1145 funct 1137 function = "blsp_uart3_a";
1146 drive 1138 drive-strength = <2>;
1147 bias- 1139 bias-disable;
1148 }; 1140 };
1149 1141
1150 rfr-pins { 1142 rfr-pins {
1151 pins 1143 pins = "gpio48";
1152 funct 1144 function = "blsp_uart3_a";
1153 drive 1145 drive-strength = <2>;
1154 bias- 1146 bias-disable;
1155 }; 1147 };
1156 }; 1148 };
1157 1149
1158 blsp1_i2c1_default: b 1150 blsp1_i2c1_default: blsp1-i2c1-default-state {
1159 pins = "gpio2 1151 pins = "gpio2", "gpio3";
1160 function = "b 1152 function = "blsp_i2c1";
1161 drive-strengt 1153 drive-strength = <2>;
1162 bias-disable; 1154 bias-disable;
1163 }; 1155 };
1164 1156
1165 blsp1_i2c1_sleep: bls 1157 blsp1_i2c1_sleep: blsp1-i2c1-sleep-state-state {
1166 pins = "gpio2 1158 pins = "gpio2", "gpio3";
1167 function = "b 1159 function = "blsp_i2c1";
1168 drive-strengt 1160 drive-strength = <2>;
1169 bias-pull-up; 1161 bias-pull-up;
1170 }; 1162 };
1171 1163
1172 blsp1_i2c2_default: b 1164 blsp1_i2c2_default: blsp1-i2c2-default-state {
1173 pins = "gpio3 1165 pins = "gpio32", "gpio33";
1174 function = "b 1166 function = "blsp_i2c2";
1175 drive-strengt 1167 drive-strength = <2>;
1176 bias-disable; 1168 bias-disable;
1177 }; 1169 };
1178 1170
1179 blsp1_i2c2_sleep: bls 1171 blsp1_i2c2_sleep: blsp1-i2c2-sleep-state-state {
1180 pins = "gpio3 1172 pins = "gpio32", "gpio33";
1181 function = "b 1173 function = "blsp_i2c2";
1182 drive-strengt 1174 drive-strength = <2>;
1183 bias-pull-up; 1175 bias-pull-up;
1184 }; 1176 };
1185 1177
1186 blsp1_i2c3_default: b 1178 blsp1_i2c3_default: blsp1-i2c3-default-state {
1187 pins = "gpio4 1179 pins = "gpio47", "gpio48";
1188 function = "b 1180 function = "blsp_i2c3";
1189 drive-strengt 1181 drive-strength = <2>;
1190 bias-disable; 1182 bias-disable;
1191 }; 1183 };
1192 1184
1193 blsp1_i2c3_sleep: bls 1185 blsp1_i2c3_sleep: blsp1-i2c3-sleep-state {
1194 pins = "gpio4 1186 pins = "gpio47", "gpio48";
1195 function = "b 1187 function = "blsp_i2c3";
1196 drive-strengt 1188 drive-strength = <2>;
1197 bias-pull-up; 1189 bias-pull-up;
1198 }; 1190 };
1199 1191
1200 blsp1_i2c4_default: b 1192 blsp1_i2c4_default: blsp1-i2c4-default-state {
1201 pins = "gpio1 1193 pins = "gpio10", "gpio11";
1202 function = "b 1194 function = "blsp_i2c4";
1203 drive-strengt 1195 drive-strength = <2>;
1204 bias-disable; 1196 bias-disable;
1205 }; 1197 };
1206 1198
1207 blsp1_i2c4_sleep: bls 1199 blsp1_i2c4_sleep: blsp1-i2c4-sleep-state {
1208 pins = "gpio1 1200 pins = "gpio10", "gpio11";
1209 function = "b 1201 function = "blsp_i2c4";
1210 drive-strengt 1202 drive-strength = <2>;
1211 bias-pull-up; 1203 bias-pull-up;
1212 }; 1204 };
1213 1205
1214 blsp1_i2c5_default: b 1206 blsp1_i2c5_default: blsp1-i2c5-default-state {
1215 pins = "gpio8 1207 pins = "gpio87", "gpio88";
1216 function = "b 1208 function = "blsp_i2c5";
1217 drive-strengt 1209 drive-strength = <2>;
1218 bias-disable; 1210 bias-disable;
1219 }; 1211 };
1220 1212
1221 blsp1_i2c5_sleep: bls 1213 blsp1_i2c5_sleep: blsp1-i2c5-sleep-state {
1222 pins = "gpio8 1214 pins = "gpio87", "gpio88";
1223 function = "b 1215 function = "blsp_i2c5";
1224 drive-strengt 1216 drive-strength = <2>;
1225 bias-pull-up; 1217 bias-pull-up;
1226 }; 1218 };
1227 1219
1228 blsp1_i2c6_default: b 1220 blsp1_i2c6_default: blsp1-i2c6-default-state {
1229 pins = "gpio4 1221 pins = "gpio43", "gpio44";
1230 function = "b 1222 function = "blsp_i2c6";
1231 drive-strengt 1223 drive-strength = <2>;
1232 bias-disable; 1224 bias-disable;
1233 }; 1225 };
1234 1226
1235 blsp1_i2c6_sleep: bls 1227 blsp1_i2c6_sleep: blsp1-i2c6-sleep-state {
1236 pins = "gpio4 1228 pins = "gpio43", "gpio44";
1237 function = "b 1229 function = "blsp_i2c6";
1238 drive-strengt 1230 drive-strength = <2>;
1239 bias-pull-up; 1231 bias-pull-up;
1240 }; 1232 };
1241 1233
1242 blsp1_spi_b_default: 1234 blsp1_spi_b_default: blsp1-spi-b-default-state {
1243 pins = "gpio2 1235 pins = "gpio23", "gpio28";
1244 function = "b 1236 function = "blsp1_spi_b";
1245 drive-strengt 1237 drive-strength = <6>;
1246 bias-disable; 1238 bias-disable;
1247 }; 1239 };
1248 1240
1249 blsp1_spi1_default: b 1241 blsp1_spi1_default: blsp1-spi1-default-state {
1250 pins = "gpio0 1242 pins = "gpio0", "gpio1", "gpio2", "gpio3";
1251 function = "b 1243 function = "blsp_spi1";
1252 drive-strengt 1244 drive-strength = <6>;
1253 bias-disable; 1245 bias-disable;
1254 }; 1246 };
1255 1247
1256 blsp1_spi2_default: b 1248 blsp1_spi2_default: blsp1-spi2-default-state {
1257 pins = "gpio3 1249 pins = "gpio31", "gpio34", "gpio32", "gpio33";
1258 function = "b 1250 function = "blsp_spi2";
1259 drive-strengt 1251 drive-strength = <6>;
1260 bias-disable; 1252 bias-disable;
1261 }; 1253 };
1262 1254
1263 blsp1_spi3_default: b 1255 blsp1_spi3_default: blsp1-spi3-default-state {
1264 pins = "gpio4 1256 pins = "gpio45", "gpio46", "gpio47", "gpio48";
1265 function = "b 1257 function = "blsp_spi2";
1266 drive-strengt 1258 drive-strength = <6>;
1267 bias-disable; 1259 bias-disable;
1268 }; 1260 };
1269 1261
1270 blsp1_spi4_default: b 1262 blsp1_spi4_default: blsp1-spi4-default-state {
1271 pins = "gpio8 1263 pins = "gpio8", "gpio9", "gpio10", "gpio11";
1272 function = "b 1264 function = "blsp_spi4";
1273 drive-strengt 1265 drive-strength = <6>;
1274 bias-disable; 1266 bias-disable;
1275 }; 1267 };
1276 1268
1277 blsp1_spi5_default: b 1269 blsp1_spi5_default: blsp1-spi5-default-state {
1278 pins = "gpio8 1270 pins = "gpio85", "gpio86", "gpio87", "gpio88";
1279 function = "b 1271 function = "blsp_spi5";
1280 drive-strengt 1272 drive-strength = <6>;
1281 bias-disable; 1273 bias-disable;
1282 }; 1274 };
1283 1275
1284 blsp1_spi6_default: b 1276 blsp1_spi6_default: blsp1-spi6-default-state {
1285 pins = "gpio4 1277 pins = "gpio41", "gpio42", "gpio43", "gpio44";
1286 function = "b 1278 function = "blsp_spi6";
1287 drive-strengt 1279 drive-strength = <6>;
1288 bias-disable; 1280 bias-disable;
1289 }; 1281 };
1290 1282
1291 1283
1292 /* 6 interfaces per Q 1284 /* 6 interfaces per QUP, BLSP2 indexes are numbered (n)+6 */
1293 blsp2_i2c1_default: b 1285 blsp2_i2c1_default: blsp2-i2c1-default-state {
1294 pins = "gpio5 1286 pins = "gpio55", "gpio56";
1295 function = "b 1287 function = "blsp_i2c7";
1296 drive-strengt 1288 drive-strength = <2>;
1297 bias-disable; 1289 bias-disable;
1298 }; 1290 };
1299 1291
1300 blsp2_i2c1_sleep: bls 1292 blsp2_i2c1_sleep: blsp2-i2c1-sleep-state {
1301 pins = "gpio5 1293 pins = "gpio55", "gpio56";
1302 function = "b 1294 function = "blsp_i2c7";
1303 drive-strengt 1295 drive-strength = <2>;
1304 bias-pull-up; 1296 bias-pull-up;
1305 }; 1297 };
1306 1298
1307 blsp2_i2c2_default: b 1299 blsp2_i2c2_default: blsp2-i2c2-default-state {
1308 pins = "gpio6 1300 pins = "gpio6", "gpio7";
1309 function = "b 1301 function = "blsp_i2c8";
1310 drive-strengt 1302 drive-strength = <2>;
1311 bias-disable; 1303 bias-disable;
1312 }; 1304 };
1313 1305
1314 blsp2_i2c2_sleep: bls 1306 blsp2_i2c2_sleep: blsp2-i2c2-sleep-state {
1315 pins = "gpio6 1307 pins = "gpio6", "gpio7";
1316 function = "b 1308 function = "blsp_i2c8";
1317 drive-strengt 1309 drive-strength = <2>;
1318 bias-pull-up; 1310 bias-pull-up;
1319 }; 1311 };
1320 1312
1321 blsp2_i2c3_default: b 1313 blsp2_i2c3_default: blsp2-i2c3-default-state {
1322 pins = "gpio5 1314 pins = "gpio51", "gpio52";
1323 function = "b 1315 function = "blsp_i2c9";
1324 drive-strengt 1316 drive-strength = <2>;
1325 bias-disable; 1317 bias-disable;
1326 }; 1318 };
1327 1319
1328 blsp2_i2c3_sleep: bls 1320 blsp2_i2c3_sleep: blsp2-i2c3-sleep-state {
1329 pins = "gpio5 1321 pins = "gpio51", "gpio52";
1330 function = "b 1322 function = "blsp_i2c9";
1331 drive-strengt 1323 drive-strength = <2>;
1332 bias-pull-up; 1324 bias-pull-up;
1333 }; 1325 };
1334 1326
1335 blsp2_i2c4_default: b 1327 blsp2_i2c4_default: blsp2-i2c4-default-state {
1336 pins = "gpio6 1328 pins = "gpio67", "gpio68";
1337 function = "b 1329 function = "blsp_i2c10";
1338 drive-strengt 1330 drive-strength = <2>;
1339 bias-disable; 1331 bias-disable;
1340 }; 1332 };
1341 1333
1342 blsp2_i2c4_sleep: bls 1334 blsp2_i2c4_sleep: blsp2-i2c4-sleep-state {
1343 pins = "gpio6 1335 pins = "gpio67", "gpio68";
1344 function = "b 1336 function = "blsp_i2c10";
1345 drive-strengt 1337 drive-strength = <2>;
1346 bias-pull-up; 1338 bias-pull-up;
1347 }; 1339 };
1348 1340
1349 blsp2_i2c5_default: b 1341 blsp2_i2c5_default: blsp2-i2c5-default-state {
1350 pins = "gpio6 1342 pins = "gpio60", "gpio61";
1351 function = "b 1343 function = "blsp_i2c11";
1352 drive-strengt 1344 drive-strength = <2>;
1353 bias-disable; 1345 bias-disable;
1354 }; 1346 };
1355 1347
1356 blsp2_i2c5_sleep: bls 1348 blsp2_i2c5_sleep: blsp2-i2c5-sleep-state {
1357 pins = "gpio6 1349 pins = "gpio60", "gpio61";
1358 function = "b 1350 function = "blsp_i2c11";
1359 drive-strengt 1351 drive-strength = <2>;
1360 bias-pull-up; 1352 bias-pull-up;
1361 }; 1353 };
1362 1354
1363 blsp2_i2c6_default: b 1355 blsp2_i2c6_default: blsp2-i2c6-default-state {
1364 pins = "gpio8 1356 pins = "gpio83", "gpio84";
1365 function = "b 1357 function = "blsp_i2c12";
1366 drive-strengt 1358 drive-strength = <2>;
1367 bias-disable; 1359 bias-disable;
1368 }; 1360 };
1369 1361
1370 blsp2_i2c6_sleep: bls 1362 blsp2_i2c6_sleep: blsp2-i2c6-sleep-state {
1371 pins = "gpio8 1363 pins = "gpio83", "gpio84";
1372 function = "b 1364 function = "blsp_i2c12";
1373 drive-strengt 1365 drive-strength = <2>;
1374 bias-pull-up; 1366 bias-pull-up;
1375 }; 1367 };
1376 1368
1377 blsp2_spi1_default: b 1369 blsp2_spi1_default: blsp2-spi1-default-state {
1378 pins = "gpio5 1370 pins = "gpio53", "gpio54", "gpio55", "gpio56";
1379 function = "b 1371 function = "blsp_spi7";
1380 drive-strengt 1372 drive-strength = <6>;
1381 bias-disable; 1373 bias-disable;
1382 }; 1374 };
1383 1375
1384 blsp2_spi2_default: b 1376 blsp2_spi2_default: blsp2-spi2-default-state {
1385 pins = "gpio4 1377 pins = "gpio4", "gpio5", "gpio6", "gpio7";
1386 function = "b 1378 function = "blsp_spi8";
1387 drive-strengt 1379 drive-strength = <6>;
1388 bias-disable; 1380 bias-disable;
1389 }; 1381 };
1390 1382
1391 blsp2_spi3_default: b 1383 blsp2_spi3_default: blsp2-spi3-default-state {
1392 pins = "gpio4 1384 pins = "gpio49", "gpio50", "gpio51", "gpio52";
1393 function = "b 1385 function = "blsp_spi9";
1394 drive-strengt 1386 drive-strength = <6>;
1395 bias-disable; 1387 bias-disable;
1396 }; 1388 };
1397 1389
1398 blsp2_spi4_default: b 1390 blsp2_spi4_default: blsp2-spi4-default-state {
1399 pins = "gpio6 1391 pins = "gpio65", "gpio66", "gpio67", "gpio68";
1400 function = "b 1392 function = "blsp_spi10";
1401 drive-strengt 1393 drive-strength = <6>;
1402 bias-disable; 1394 bias-disable;
1403 }; 1395 };
1404 1396
1405 blsp2_spi5_default: b 1397 blsp2_spi5_default: blsp2-spi5-default-state {
1406 pins = "gpio5 1398 pins = "gpio58", "gpio59", "gpio60", "gpio61";
1407 function = "b 1399 function = "blsp_spi11";
1408 drive-strengt 1400 drive-strength = <6>;
1409 bias-disable; 1401 bias-disable;
1410 }; 1402 };
1411 1403
1412 blsp2_spi6_default: b 1404 blsp2_spi6_default: blsp2-spi6-default-state {
1413 pins = "gpio8 1405 pins = "gpio81", "gpio82", "gpio83", "gpio84";
1414 function = "b 1406 function = "blsp_spi12";
1415 drive-strengt 1407 drive-strength = <6>;
1416 bias-disable; 1408 bias-disable;
1417 }; 1409 };
1418 }; 1410 };
1419 1411
1420 remoteproc_mss: remoteproc@40 1412 remoteproc_mss: remoteproc@4080000 {
1421 compatible = "qcom,ms 1413 compatible = "qcom,msm8998-mss-pil";
1422 reg = <0x04080000 0x1 1414 reg = <0x04080000 0x100>, <0x04180000 0x20>;
1423 reg-names = "qdsp6", 1415 reg-names = "qdsp6", "rmb";
1424 1416
1425 interrupts-extended = 1417 interrupts-extended =
1426 <&intc GIC_SP 1418 <&intc GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
1427 <&modem_smp2p 1419 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1428 <&modem_smp2p 1420 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1429 <&modem_smp2p 1421 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1430 <&modem_smp2p 1422 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
1431 <&modem_smp2p 1423 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
1432 interrupt-names = "wd 1424 interrupt-names = "wdog", "fatal", "ready",
1433 "ha 1425 "handover", "stop-ack",
1434 "sh 1426 "shutdown-ack";
1435 1427
1436 clocks = <&gcc GCC_MS 1428 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
1437 <&gcc GCC_BI 1429 <&gcc GCC_BIMC_MSS_Q6_AXI_CLK>,
1438 <&gcc GCC_BO 1430 <&gcc GCC_BOOT_ROM_AHB_CLK>,
1439 <&gcc GCC_MS 1431 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
1440 <&gcc GCC_MS 1432 <&gcc GCC_MSS_SNOC_AXI_CLK>,
1441 <&gcc GCC_MS 1433 <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>,
1442 <&rpmcc RPM_ 1434 <&rpmcc RPM_SMD_QDSS_CLK>,
1443 <&rpmcc RPM_ 1435 <&rpmcc RPM_SMD_XO_CLK_SRC>;
1444 clock-names = "iface" 1436 clock-names = "iface", "bus", "mem", "gpll0_mss",
1445 "snoc_a 1437 "snoc_axi", "mnoc_axi", "qdss", "xo";
1446 1438
1447 qcom,smem-states = <& 1439 qcom,smem-states = <&modem_smp2p_out 0>;
1448 qcom,smem-state-names 1440 qcom,smem-state-names = "stop";
1449 1441
1450 resets = <&gcc GCC_MS 1442 resets = <&gcc GCC_MSS_RESTART>;
1451 reset-names = "mss_re 1443 reset-names = "mss_restart";
1452 1444
1453 qcom,halt-regs = <&tc 1445 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>;
1454 1446
1455 power-domains = <&rpm 1447 power-domains = <&rpmpd MSM8998_VDDCX>,
1456 <&rpm 1448 <&rpmpd MSM8998_VDDMX>;
1457 power-domain-names = 1449 power-domain-names = "cx", "mx";
1458 1450
1459 status = "disabled"; 1451 status = "disabled";
1460 1452
1461 mba { 1453 mba {
1462 memory-region 1454 memory-region = <&mba_mem>;
1463 }; 1455 };
1464 1456
1465 mpss { 1457 mpss {
1466 memory-region 1458 memory-region = <&mpss_mem>;
1467 }; 1459 };
1468 1460
1469 metadata { 1461 metadata {
1470 memory-region 1462 memory-region = <&mdata_mem>;
1471 }; 1463 };
1472 1464
1473 glink-edge { 1465 glink-edge {
1474 interrupts = 1466 interrupts = <GIC_SPI 452 IRQ_TYPE_EDGE_RISING>;
1475 label = "mode 1467 label = "modem";
1476 qcom,remote-p 1468 qcom,remote-pid = <1>;
1477 mboxes = <&ap 1469 mboxes = <&apcs_glb 15>;
1478 }; 1470 };
1479 }; 1471 };
1480 1472
1481 adreno_gpu: gpu@5000000 { 1473 adreno_gpu: gpu@5000000 {
1482 compatible = "qcom,ad 1474 compatible = "qcom,adreno-540.1", "qcom,adreno";
1483 reg = <0x05000000 0x4 1475 reg = <0x05000000 0x40000>;
1484 reg-names = "kgsl_3d0 1476 reg-names = "kgsl_3d0_reg_memory";
1485 1477
1486 clocks = <&gcc GCC_GP 1478 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
1487 <&gpucc RBBMT 1479 <&gpucc RBBMTIMER_CLK>,
1488 <&gcc GCC_BIM 1480 <&gcc GCC_BIMC_GFX_CLK>,
1489 <&gcc GCC_GPU 1481 <&gcc GCC_GPU_BIMC_GFX_CLK>,
1490 <&gpucc RBCPR 1482 <&gpucc RBCPR_CLK>,
1491 <&gpucc GFX3D 1483 <&gpucc GFX3D_CLK>;
1492 clock-names = "iface" 1484 clock-names = "iface",
1493 "rbbmtimer", 1485 "rbbmtimer",
1494 "mem", 1486 "mem",
1495 "mem_iface", 1487 "mem_iface",
1496 "rbcpr", 1488 "rbcpr",
1497 "core"; 1489 "core";
1498 1490
1499 interrupts = <GIC_SPI !! 1491 interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
1500 iommus = <&adreno_smm 1492 iommus = <&adreno_smmu 0>;
1501 operating-points-v2 = 1493 operating-points-v2 = <&gpu_opp_table>;
1502 power-domains = <&rpm 1494 power-domains = <&rpmpd MSM8998_VDDMX>;
1503 status = "disabled"; 1495 status = "disabled";
1504 1496
1505 gpu_opp_table: opp-ta 1497 gpu_opp_table: opp-table {
1506 compatible = 1498 compatible = "operating-points-v2";
1507 opp-710000097 1499 opp-710000097 {
1508 opp-h 1500 opp-hz = /bits/ 64 <710000097>;
1509 opp-l 1501 opp-level = <RPM_SMD_LEVEL_TURBO>;
1510 opp-s 1502 opp-supported-hw = <0xff>;
1511 }; 1503 };
1512 1504
1513 opp-670000048 1505 opp-670000048 {
1514 opp-h 1506 opp-hz = /bits/ 64 <670000048>;
1515 opp-l 1507 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
1516 opp-s 1508 opp-supported-hw = <0xff>;
1517 }; 1509 };
1518 1510
1519 opp-596000097 1511 opp-596000097 {
1520 opp-h 1512 opp-hz = /bits/ 64 <596000097>;
1521 opp-l 1513 opp-level = <RPM_SMD_LEVEL_NOM>;
1522 opp-s 1514 opp-supported-hw = <0xff>;
1523 }; 1515 };
1524 1516
1525 opp-515000097 1517 opp-515000097 {
1526 opp-h 1518 opp-hz = /bits/ 64 <515000097>;
1527 opp-l 1519 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
1528 opp-s 1520 opp-supported-hw = <0xff>;
1529 }; 1521 };
1530 1522
1531 opp-414000000 1523 opp-414000000 {
1532 opp-h 1524 opp-hz = /bits/ 64 <414000000>;
1533 opp-l 1525 opp-level = <RPM_SMD_LEVEL_SVS>;
1534 opp-s 1526 opp-supported-hw = <0xff>;
1535 }; 1527 };
1536 1528
1537 opp-342000000 1529 opp-342000000 {
1538 opp-h 1530 opp-hz = /bits/ 64 <342000000>;
1539 opp-l 1531 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
1540 opp-s 1532 opp-supported-hw = <0xff>;
1541 }; 1533 };
1542 1534
1543 opp-257000000 1535 opp-257000000 {
1544 opp-h 1536 opp-hz = /bits/ 64 <257000000>;
1545 opp-l 1537 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
1546 opp-s 1538 opp-supported-hw = <0xff>;
1547 }; 1539 };
1548 }; 1540 };
1549 }; 1541 };
1550 1542
1551 adreno_smmu: iommu@5040000 { 1543 adreno_smmu: iommu@5040000 {
1552 compatible = "qcom,ms 1544 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
1553 reg = <0x05040000 0x1 1545 reg = <0x05040000 0x10000>;
1554 clocks = <&gcc GCC_GP 1546 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
1555 <&gcc GCC_BI 1547 <&gcc GCC_BIMC_GFX_CLK>,
1556 <&gcc GCC_GP 1548 <&gcc GCC_GPU_BIMC_GFX_CLK>;
1557 clock-names = "iface" 1549 clock-names = "iface", "mem", "mem_iface";
1558 1550
1559 #global-interrupts = 1551 #global-interrupts = <0>;
1560 #iommu-cells = <1>; 1552 #iommu-cells = <1>;
1561 interrupts = 1553 interrupts =
1562 <GIC_SPI 329 1554 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1563 <GIC_SPI 330 1555 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
1564 <GIC_SPI 331 1556 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
1565 /* 1557 /*
1566 * GPU-GX GDSC's pare 1558 * GPU-GX GDSC's parent is GPU-CX. We need to bring up the
1567 * GPU-CX for SMMU bu 1559 * GPU-CX for SMMU but we need both of them up for Adreno.
1568 * Contemporarily, we 1560 * Contemporarily, we also need to manage the VDDMX rpmpd
1569 * domain in the Adre 1561 * domain in the Adreno driver.
1570 * Enable GPU CX/GX G 1562 * Enable GPU CX/GX GDSCs here so that we can manage the
1571 * SoC VDDMX RPM Powe 1563 * SoC VDDMX RPM Power Domain in the Adreno driver.
1572 */ 1564 */
1573 power-domains = <&gpu 1565 power-domains = <&gpucc GPU_GX_GDSC>;
>> 1566 status = "disabled";
1574 }; 1567 };
1575 1568
1576 gpucc: clock-controller@50650 1569 gpucc: clock-controller@5065000 {
1577 compatible = "qcom,ms 1570 compatible = "qcom,msm8998-gpucc";
1578 #clock-cells = <1>; 1571 #clock-cells = <1>;
1579 #reset-cells = <1>; 1572 #reset-cells = <1>;
1580 #power-domain-cells = 1573 #power-domain-cells = <1>;
1581 reg = <0x05065000 0x9 1574 reg = <0x05065000 0x9000>;
1582 1575
1583 clocks = <&rpmcc RPM_ 1576 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1584 <&gcc GCC_GP !! 1577 <&gcc GPLL0_OUT_MAIN>;
1585 clock-names = "xo", 1578 clock-names = "xo",
1586 "gpll0" 1579 "gpll0";
1587 }; 1580 };
1588 1581
1589 lpass_q6_smmu: iommu@5100000 <<
1590 compatible = "qcom,ms <<
1591 reg = <0x05100000 0x4 <<
1592 clocks = <&gcc HLOS1_ <<
1593 clock-names = "bus"; <<
1594 <<
1595 #global-interrupts = <<
1596 #iommu-cells = <1>; <<
1597 interrupts = <<
1598 <GIC_SPI 226 <<
1599 <GIC_SPI 393 <<
1600 <GIC_SPI 394 <<
1601 <GIC_SPI 395 <<
1602 <GIC_SPI 396 <<
1603 <GIC_SPI 397 <<
1604 <GIC_SPI 398 <<
1605 <GIC_SPI 399 <<
1606 <GIC_SPI 400 <<
1607 <GIC_SPI 401 <<
1608 <GIC_SPI 402 <<
1609 <GIC_SPI 403 <<
1610 <GIC_SPI 137 <<
1611 <<
1612 power-domains = <&gcc <<
1613 status = "disabled"; <<
1614 }; <<
1615 <<
1616 remoteproc_slpi: remoteproc@5 1582 remoteproc_slpi: remoteproc@5800000 {
1617 compatible = "qcom,ms 1583 compatible = "qcom,msm8998-slpi-pas";
1618 reg = <0x05800000 0x4 1584 reg = <0x05800000 0x4040>;
1619 1585
1620 interrupts-extended = 1586 interrupts-extended = <&intc GIC_SPI 390 IRQ_TYPE_EDGE_RISING>,
1621 1587 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1622 1588 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1623 1589 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1624 1590 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1625 interrupt-names = "wd 1591 interrupt-names = "wdog", "fatal", "ready",
1626 "ha 1592 "handover", "stop-ack";
1627 1593
1628 px-supply = <&vreg_lv 1594 px-supply = <&vreg_lvs2a_1p8>;
1629 1595
1630 clocks = <&rpmcc RPM_ !! 1596 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1631 clock-names = "xo"; !! 1597 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
>> 1598 clock-names = "xo", "aggre2";
1632 1599
1633 memory-region = <&slp 1600 memory-region = <&slpi_mem>;
1634 1601
1635 qcom,smem-states = <& 1602 qcom,smem-states = <&slpi_smp2p_out 0>;
1636 qcom,smem-state-names 1603 qcom,smem-state-names = "stop";
1637 1604
1638 power-domains = <&rpm 1605 power-domains = <&rpmpd MSM8998_SSCCX>;
1639 power-domain-names = 1606 power-domain-names = "ssc_cx";
1640 1607
1641 status = "disabled"; 1608 status = "disabled";
1642 1609
1643 glink-edge { 1610 glink-edge {
1644 interrupts = 1611 interrupts = <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>;
1645 label = "dsps 1612 label = "dsps";
1646 qcom,remote-p 1613 qcom,remote-pid = <3>;
1647 mboxes = <&ap 1614 mboxes = <&apcs_glb 27>;
1648 }; 1615 };
1649 }; 1616 };
1650 1617
1651 stm: stm@6002000 { 1618 stm: stm@6002000 {
1652 compatible = "arm,cor 1619 compatible = "arm,coresight-stm", "arm,primecell";
1653 reg = <0x06002000 0x1 1620 reg = <0x06002000 0x1000>,
1654 <0x16280000 0x1 1621 <0x16280000 0x180000>;
1655 reg-names = "stm-base 1622 reg-names = "stm-base", "stm-stimulus-base";
1656 status = "disabled"; 1623 status = "disabled";
1657 1624
1658 clocks = <&rpmcc RPM_ 1625 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1659 clock-names = "apb_pc 1626 clock-names = "apb_pclk", "atclk";
1660 1627
1661 out-ports { 1628 out-ports {
1662 port { 1629 port {
1663 stm_o 1630 stm_out: endpoint {
1664 1631 remote-endpoint = <&funnel0_in7>;
1665 }; 1632 };
1666 }; 1633 };
1667 }; 1634 };
1668 }; 1635 };
1669 1636
1670 funnel1: funnel@6041000 { 1637 funnel1: funnel@6041000 {
1671 compatible = "arm,cor 1638 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1672 reg = <0x06041000 0x1 1639 reg = <0x06041000 0x1000>;
1673 status = "disabled"; 1640 status = "disabled";
1674 1641
1675 clocks = <&rpmcc RPM_ 1642 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1676 clock-names = "apb_pc 1643 clock-names = "apb_pclk", "atclk";
1677 1644
1678 out-ports { 1645 out-ports {
1679 port { 1646 port {
1680 funne 1647 funnel0_out: endpoint {
1681 1648 remote-endpoint =
1682 1649 <&merge_funnel_in0>;
1683 }; 1650 };
1684 }; 1651 };
1685 }; 1652 };
1686 1653
1687 in-ports { 1654 in-ports {
1688 #address-cell 1655 #address-cells = <1>;
1689 #size-cells = 1656 #size-cells = <0>;
1690 1657
1691 port@7 { 1658 port@7 {
1692 reg = 1659 reg = <7>;
1693 funne 1660 funnel0_in7: endpoint {
1694 1661 remote-endpoint = <&stm_out>;
1695 }; 1662 };
1696 }; 1663 };
1697 }; 1664 };
1698 }; 1665 };
1699 1666
1700 funnel2: funnel@6042000 { 1667 funnel2: funnel@6042000 {
1701 compatible = "arm,cor 1668 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1702 reg = <0x06042000 0x1 1669 reg = <0x06042000 0x1000>;
1703 status = "disabled"; 1670 status = "disabled";
1704 1671
1705 clocks = <&rpmcc RPM_ 1672 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1706 clock-names = "apb_pc 1673 clock-names = "apb_pclk", "atclk";
1707 1674
1708 out-ports { 1675 out-ports {
1709 port { 1676 port {
1710 funne 1677 funnel1_out: endpoint {
1711 1678 remote-endpoint =
1712 1679 <&merge_funnel_in1>;
1713 }; 1680 };
1714 }; 1681 };
1715 }; 1682 };
1716 1683
1717 in-ports { 1684 in-ports {
1718 #address-cell 1685 #address-cells = <1>;
1719 #size-cells = 1686 #size-cells = <0>;
1720 1687
1721 port@6 { 1688 port@6 {
1722 reg = 1689 reg = <6>;
1723 funne 1690 funnel1_in6: endpoint {
1724 1691 remote-endpoint =
1725 1692 <&apss_merge_funnel_out>;
1726 }; 1693 };
1727 }; 1694 };
1728 }; 1695 };
1729 }; 1696 };
1730 1697
1731 funnel3: funnel@6045000 { 1698 funnel3: funnel@6045000 {
1732 compatible = "arm,cor 1699 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1733 reg = <0x06045000 0x1 1700 reg = <0x06045000 0x1000>;
1734 status = "disabled"; 1701 status = "disabled";
1735 1702
1736 clocks = <&rpmcc RPM_ 1703 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1737 clock-names = "apb_pc 1704 clock-names = "apb_pclk", "atclk";
1738 1705
1739 out-ports { 1706 out-ports {
1740 port { 1707 port {
1741 merge 1708 merge_funnel_out: endpoint {
1742 1709 remote-endpoint =
1743 1710 <&etf_in>;
1744 }; 1711 };
1745 }; 1712 };
1746 }; 1713 };
1747 1714
1748 in-ports { 1715 in-ports {
1749 #address-cell 1716 #address-cells = <1>;
1750 #size-cells = 1717 #size-cells = <0>;
1751 1718
1752 port@0 { 1719 port@0 {
1753 reg = 1720 reg = <0>;
1754 merge 1721 merge_funnel_in0: endpoint {
1755 1722 remote-endpoint =
1756 1723 <&funnel0_out>;
1757 }; 1724 };
1758 }; 1725 };
1759 1726
1760 port@1 { 1727 port@1 {
1761 reg = 1728 reg = <1>;
1762 merge 1729 merge_funnel_in1: endpoint {
1763 1730 remote-endpoint =
1764 1731 <&funnel1_out>;
1765 }; 1732 };
1766 }; 1733 };
1767 }; 1734 };
1768 }; 1735 };
1769 1736
1770 replicator1: replicator@60460 1737 replicator1: replicator@6046000 {
1771 compatible = "arm,cor 1738 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
1772 reg = <0x06046000 0x1 1739 reg = <0x06046000 0x1000>;
1773 status = "disabled"; 1740 status = "disabled";
1774 1741
1775 clocks = <&rpmcc RPM_ 1742 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1776 clock-names = "apb_pc 1743 clock-names = "apb_pclk", "atclk";
1777 1744
1778 out-ports { 1745 out-ports {
1779 port { 1746 port {
1780 repli 1747 replicator_out: endpoint {
1781 1748 remote-endpoint = <&etr_in>;
1782 }; 1749 };
1783 }; 1750 };
1784 }; 1751 };
1785 1752
1786 in-ports { 1753 in-ports {
1787 port { 1754 port {
1788 repli 1755 replicator_in: endpoint {
1789 1756 remote-endpoint = <&etf_out>;
1790 }; 1757 };
1791 }; 1758 };
1792 }; 1759 };
1793 }; 1760 };
1794 1761
1795 etf: etf@6047000 { 1762 etf: etf@6047000 {
1796 compatible = "arm,cor 1763 compatible = "arm,coresight-tmc", "arm,primecell";
1797 reg = <0x06047000 0x1 1764 reg = <0x06047000 0x1000>;
1798 status = "disabled"; 1765 status = "disabled";
1799 1766
1800 clocks = <&rpmcc RPM_ 1767 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1801 clock-names = "apb_pc 1768 clock-names = "apb_pclk", "atclk";
1802 1769
1803 out-ports { 1770 out-ports {
1804 port { 1771 port {
1805 etf_o 1772 etf_out: endpoint {
1806 1773 remote-endpoint =
1807 1774 <&replicator_in>;
1808 }; 1775 };
1809 }; 1776 };
1810 }; 1777 };
1811 1778
1812 in-ports { 1779 in-ports {
1813 port { 1780 port {
1814 etf_i 1781 etf_in: endpoint {
1815 1782 remote-endpoint =
1816 1783 <&merge_funnel_out>;
1817 }; 1784 };
1818 }; 1785 };
1819 }; 1786 };
1820 }; 1787 };
1821 1788
1822 etr: etr@6048000 { 1789 etr: etr@6048000 {
1823 compatible = "arm,cor 1790 compatible = "arm,coresight-tmc", "arm,primecell";
1824 reg = <0x06048000 0x1 1791 reg = <0x06048000 0x1000>;
1825 status = "disabled"; 1792 status = "disabled";
1826 1793
1827 clocks = <&rpmcc RPM_ 1794 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1828 clock-names = "apb_pc 1795 clock-names = "apb_pclk", "atclk";
1829 arm,scatter-gather; 1796 arm,scatter-gather;
1830 1797
1831 in-ports { 1798 in-ports {
1832 port { 1799 port {
1833 etr_i 1800 etr_in: endpoint {
1834 1801 remote-endpoint =
1835 1802 <&replicator_out>;
1836 }; 1803 };
1837 }; 1804 };
1838 }; 1805 };
1839 }; 1806 };
1840 1807
1841 etm1: etm@7840000 { 1808 etm1: etm@7840000 {
1842 compatible = "arm,cor 1809 compatible = "arm,coresight-etm4x", "arm,primecell";
1843 reg = <0x07840000 0x1 1810 reg = <0x07840000 0x1000>;
1844 status = "disabled"; 1811 status = "disabled";
1845 1812
1846 clocks = <&rpmcc RPM_ 1813 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1847 clock-names = "apb_pc 1814 clock-names = "apb_pclk", "atclk";
1848 1815
1849 cpu = <&CPU0>; 1816 cpu = <&CPU0>;
1850 1817
1851 out-ports { 1818 out-ports {
1852 port { 1819 port {
1853 etm0_ 1820 etm0_out: endpoint {
1854 1821 remote-endpoint =
1855 1822 <&apss_funnel_in0>;
1856 }; 1823 };
1857 }; 1824 };
1858 }; 1825 };
1859 }; 1826 };
1860 1827
1861 etm2: etm@7940000 { 1828 etm2: etm@7940000 {
1862 compatible = "arm,cor 1829 compatible = "arm,coresight-etm4x", "arm,primecell";
1863 reg = <0x07940000 0x1 1830 reg = <0x07940000 0x1000>;
1864 status = "disabled"; 1831 status = "disabled";
1865 1832
1866 clocks = <&rpmcc RPM_ 1833 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1867 clock-names = "apb_pc 1834 clock-names = "apb_pclk", "atclk";
1868 1835
1869 cpu = <&CPU1>; 1836 cpu = <&CPU1>;
1870 1837
1871 out-ports { 1838 out-ports {
1872 port { 1839 port {
1873 etm1_ 1840 etm1_out: endpoint {
1874 1841 remote-endpoint =
1875 1842 <&apss_funnel_in1>;
1876 }; 1843 };
1877 }; 1844 };
1878 }; 1845 };
1879 }; 1846 };
1880 1847
1881 etm3: etm@7a40000 { 1848 etm3: etm@7a40000 {
1882 compatible = "arm,cor 1849 compatible = "arm,coresight-etm4x", "arm,primecell";
1883 reg = <0x07a40000 0x1 1850 reg = <0x07a40000 0x1000>;
1884 status = "disabled"; 1851 status = "disabled";
1885 1852
1886 clocks = <&rpmcc RPM_ 1853 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1887 clock-names = "apb_pc 1854 clock-names = "apb_pclk", "atclk";
1888 1855
1889 cpu = <&CPU2>; 1856 cpu = <&CPU2>;
1890 1857
1891 out-ports { 1858 out-ports {
1892 port { 1859 port {
1893 etm2_ 1860 etm2_out: endpoint {
1894 1861 remote-endpoint =
1895 1862 <&apss_funnel_in2>;
1896 }; 1863 };
1897 }; 1864 };
1898 }; 1865 };
1899 }; 1866 };
1900 1867
1901 etm4: etm@7b40000 { 1868 etm4: etm@7b40000 {
1902 compatible = "arm,cor 1869 compatible = "arm,coresight-etm4x", "arm,primecell";
1903 reg = <0x07b40000 0x1 1870 reg = <0x07b40000 0x1000>;
1904 status = "disabled"; 1871 status = "disabled";
1905 1872
1906 clocks = <&rpmcc RPM_ 1873 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1907 clock-names = "apb_pc 1874 clock-names = "apb_pclk", "atclk";
1908 1875
1909 cpu = <&CPU3>; 1876 cpu = <&CPU3>;
1910 1877
1911 out-ports { 1878 out-ports {
1912 port { 1879 port {
1913 etm3_ 1880 etm3_out: endpoint {
1914 1881 remote-endpoint =
1915 1882 <&apss_funnel_in3>;
1916 }; 1883 };
1917 }; 1884 };
1918 }; 1885 };
1919 }; 1886 };
1920 1887
1921 funnel4: funnel@7b60000 { /* 1888 funnel4: funnel@7b60000 { /* APSS Funnel */
1922 compatible = "arm,cor 1889 compatible = "arm,coresight-etm4x", "arm,primecell";
1923 reg = <0x07b60000 0x1 1890 reg = <0x07b60000 0x1000>;
1924 status = "disabled"; 1891 status = "disabled";
1925 1892
1926 clocks = <&rpmcc RPM_ 1893 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1927 clock-names = "apb_pc 1894 clock-names = "apb_pclk", "atclk";
1928 1895
1929 out-ports { 1896 out-ports {
1930 port { 1897 port {
1931 apss_ 1898 apss_funnel_out: endpoint {
1932 1899 remote-endpoint =
1933 1900 <&apss_merge_funnel_in>;
1934 }; 1901 };
1935 }; 1902 };
1936 }; 1903 };
1937 1904
1938 in-ports { 1905 in-ports {
1939 #address-cell 1906 #address-cells = <1>;
1940 #size-cells = 1907 #size-cells = <0>;
1941 1908
1942 port@0 { 1909 port@0 {
1943 reg = 1910 reg = <0>;
1944 apss_ 1911 apss_funnel_in0: endpoint {
1945 1912 remote-endpoint =
1946 1913 <&etm0_out>;
1947 }; 1914 };
1948 }; 1915 };
1949 1916
1950 port@1 { 1917 port@1 {
1951 reg = 1918 reg = <1>;
1952 apss_ 1919 apss_funnel_in1: endpoint {
1953 1920 remote-endpoint =
1954 1921 <&etm1_out>;
1955 }; 1922 };
1956 }; 1923 };
1957 1924
1958 port@2 { 1925 port@2 {
1959 reg = 1926 reg = <2>;
1960 apss_ 1927 apss_funnel_in2: endpoint {
1961 1928 remote-endpoint =
1962 1929 <&etm2_out>;
1963 }; 1930 };
1964 }; 1931 };
1965 1932
1966 port@3 { 1933 port@3 {
1967 reg = 1934 reg = <3>;
1968 apss_ 1935 apss_funnel_in3: endpoint {
1969 1936 remote-endpoint =
1970 1937 <&etm3_out>;
1971 }; 1938 };
1972 }; 1939 };
1973 1940
1974 port@4 { 1941 port@4 {
1975 reg = 1942 reg = <4>;
1976 apss_ 1943 apss_funnel_in4: endpoint {
1977 1944 remote-endpoint =
1978 1945 <&etm4_out>;
1979 }; 1946 };
1980 }; 1947 };
1981 1948
1982 port@5 { 1949 port@5 {
1983 reg = 1950 reg = <5>;
1984 apss_ 1951 apss_funnel_in5: endpoint {
1985 1952 remote-endpoint =
1986 1953 <&etm5_out>;
1987 }; 1954 };
1988 }; 1955 };
1989 1956
1990 port@6 { 1957 port@6 {
1991 reg = 1958 reg = <6>;
1992 apss_ 1959 apss_funnel_in6: endpoint {
1993 1960 remote-endpoint =
1994 1961 <&etm6_out>;
1995 }; 1962 };
1996 }; 1963 };
1997 1964
1998 port@7 { 1965 port@7 {
1999 reg = 1966 reg = <7>;
2000 apss_ 1967 apss_funnel_in7: endpoint {
2001 1968 remote-endpoint =
2002 1969 <&etm7_out>;
2003 }; 1970 };
2004 }; 1971 };
2005 }; 1972 };
2006 }; 1973 };
2007 1974
2008 funnel5: funnel@7b70000 { 1975 funnel5: funnel@7b70000 {
2009 compatible = "arm,cor 1976 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2010 reg = <0x07b70000 0x1 1977 reg = <0x07b70000 0x1000>;
2011 status = "disabled"; 1978 status = "disabled";
2012 1979
2013 clocks = <&rpmcc RPM_ 1980 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2014 clock-names = "apb_pc 1981 clock-names = "apb_pclk", "atclk";
2015 1982
2016 out-ports { 1983 out-ports {
2017 port { 1984 port {
2018 apss_ 1985 apss_merge_funnel_out: endpoint {
2019 1986 remote-endpoint =
2020 1987 <&funnel1_in6>;
2021 }; 1988 };
2022 }; 1989 };
2023 }; 1990 };
2024 1991
2025 in-ports { 1992 in-ports {
2026 port { 1993 port {
2027 apss_ 1994 apss_merge_funnel_in: endpoint {
2028 1995 remote-endpoint =
2029 1996 <&apss_funnel_out>;
2030 }; 1997 };
2031 }; 1998 };
2032 }; 1999 };
2033 }; 2000 };
2034 2001
2035 etm5: etm@7c40000 { 2002 etm5: etm@7c40000 {
2036 compatible = "arm,cor 2003 compatible = "arm,coresight-etm4x", "arm,primecell";
2037 reg = <0x07c40000 0x1 2004 reg = <0x07c40000 0x1000>;
2038 status = "disabled"; 2005 status = "disabled";
2039 2006
2040 clocks = <&rpmcc RPM_ 2007 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2041 clock-names = "apb_pc 2008 clock-names = "apb_pclk", "atclk";
2042 2009
2043 cpu = <&CPU4>; 2010 cpu = <&CPU4>;
2044 2011
2045 out-ports { !! 2012 port {
2046 port { !! 2013 etm4_out: endpoint {
2047 etm4_ !! 2014 remote-endpoint = <&apss_funnel_in4>;
2048 <<
2049 }; <<
2050 }; 2015 };
2051 }; 2016 };
2052 }; 2017 };
2053 2018
2054 etm6: etm@7d40000 { 2019 etm6: etm@7d40000 {
2055 compatible = "arm,cor 2020 compatible = "arm,coresight-etm4x", "arm,primecell";
2056 reg = <0x07d40000 0x1 2021 reg = <0x07d40000 0x1000>;
2057 status = "disabled"; 2022 status = "disabled";
2058 2023
2059 clocks = <&rpmcc RPM_ 2024 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2060 clock-names = "apb_pc 2025 clock-names = "apb_pclk", "atclk";
2061 2026
2062 cpu = <&CPU5>; 2027 cpu = <&CPU5>;
2063 2028
2064 out-ports { !! 2029 port {
2065 port { !! 2030 etm5_out: endpoint {
2066 etm5_ !! 2031 remote-endpoint = <&apss_funnel_in5>;
2067 <<
2068 }; <<
2069 }; 2032 };
2070 }; 2033 };
2071 }; 2034 };
2072 2035
2073 etm7: etm@7e40000 { 2036 etm7: etm@7e40000 {
2074 compatible = "arm,cor 2037 compatible = "arm,coresight-etm4x", "arm,primecell";
2075 reg = <0x07e40000 0x1 2038 reg = <0x07e40000 0x1000>;
2076 status = "disabled"; 2039 status = "disabled";
2077 2040
2078 clocks = <&rpmcc RPM_ 2041 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2079 clock-names = "apb_pc 2042 clock-names = "apb_pclk", "atclk";
2080 2043
2081 cpu = <&CPU6>; 2044 cpu = <&CPU6>;
2082 2045
2083 out-ports { !! 2046 port {
2084 port { !! 2047 etm6_out: endpoint {
2085 etm6_ !! 2048 remote-endpoint = <&apss_funnel_in6>;
2086 <<
2087 }; <<
2088 }; 2049 };
2089 }; 2050 };
2090 }; 2051 };
2091 2052
2092 etm8: etm@7f40000 { 2053 etm8: etm@7f40000 {
2093 compatible = "arm,cor 2054 compatible = "arm,coresight-etm4x", "arm,primecell";
2094 reg = <0x07f40000 0x1 2055 reg = <0x07f40000 0x1000>;
2095 status = "disabled"; 2056 status = "disabled";
2096 2057
2097 clocks = <&rpmcc RPM_ 2058 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2098 clock-names = "apb_pc 2059 clock-names = "apb_pclk", "atclk";
2099 2060
2100 cpu = <&CPU7>; 2061 cpu = <&CPU7>;
2101 2062
2102 out-ports { !! 2063 port {
2103 port { !! 2064 etm7_out: endpoint {
2104 etm7_ !! 2065 remote-endpoint = <&apss_funnel_in7>;
2105 <<
2106 }; <<
2107 }; 2066 };
2108 }; 2067 };
2109 }; 2068 };
2110 2069
2111 sram@290000 { 2070 sram@290000 {
2112 compatible = "qcom,rp 2071 compatible = "qcom,rpm-stats";
2113 reg = <0x00290000 0x1 2072 reg = <0x00290000 0x10000>;
2114 }; 2073 };
2115 2074
2116 spmi_bus: spmi@800f000 { 2075 spmi_bus: spmi@800f000 {
2117 compatible = "qcom,sp 2076 compatible = "qcom,spmi-pmic-arb";
2118 reg = <0x0800f000 0x1 2077 reg = <0x0800f000 0x1000>,
2119 <0x08400000 0x1 2078 <0x08400000 0x1000000>,
2120 <0x09400000 0x1 2079 <0x09400000 0x1000000>,
2121 <0x0a400000 0x2 2080 <0x0a400000 0x220000>,
2122 <0x0800a000 0x3 2081 <0x0800a000 0x3000>;
2123 reg-names = "core", " 2082 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
2124 interrupt-names = "pe 2083 interrupt-names = "periph_irq";
2125 interrupts = <GIC_SPI 2084 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
2126 qcom,ee = <0>; 2085 qcom,ee = <0>;
2127 qcom,channel = <0>; 2086 qcom,channel = <0>;
2128 #address-cells = <2>; 2087 #address-cells = <2>;
2129 #size-cells = <0>; 2088 #size-cells = <0>;
2130 interrupt-controller; 2089 interrupt-controller;
2131 #interrupt-cells = <4 2090 #interrupt-cells = <4>;
2132 }; 2091 };
2133 2092
2134 usb3: usb@a8f8800 { 2093 usb3: usb@a8f8800 {
2135 compatible = "qcom,ms 2094 compatible = "qcom,msm8998-dwc3", "qcom,dwc3";
2136 reg = <0x0a8f8800 0x4 2095 reg = <0x0a8f8800 0x400>;
2137 status = "disabled"; 2096 status = "disabled";
2138 #address-cells = <1>; 2097 #address-cells = <1>;
2139 #size-cells = <1>; 2098 #size-cells = <1>;
2140 ranges; 2099 ranges;
2141 2100
2142 clocks = <&gcc GCC_CF 2101 clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>,
2143 <&gcc GCC_US 2102 <&gcc GCC_USB30_MASTER_CLK>,
2144 <&gcc GCC_AG 2103 <&gcc GCC_AGGRE1_USB3_AXI_CLK>,
2145 <&gcc GCC_US 2104 <&gcc GCC_USB30_SLEEP_CLK>,
2146 <&gcc GCC_US 2105 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
2147 clock-names = "cfg_no 2106 clock-names = "cfg_noc",
2148 "core", 2107 "core",
2149 "iface" 2108 "iface",
2150 "sleep" 2109 "sleep",
2151 "mock_u 2110 "mock_utmi";
2152 2111
2153 assigned-clocks = <&g 2112 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
2154 <&g 2113 <&gcc GCC_USB30_MASTER_CLK>;
2155 assigned-clock-rates 2114 assigned-clock-rates = <19200000>, <120000000>;
2156 2115
2157 interrupts = <GIC_SPI !! 2116 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
2158 <GIC_SPI <<
2159 <GIC_SPI 2117 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
2160 interrupt-names = "pw !! 2118 interrupt-names = "hs_phy_irq", "ss_phy_irq";
2161 "qu <<
2162 "ss <<
2163 2119
2164 power-domains = <&gcc 2120 power-domains = <&gcc USB_30_GDSC>;
2165 2121
2166 resets = <&gcc GCC_US 2122 resets = <&gcc GCC_USB_30_BCR>;
2167 2123
2168 usb3_dwc3: usb@a80000 2124 usb3_dwc3: usb@a800000 {
2169 compatible = 2125 compatible = "snps,dwc3";
2170 reg = <0x0a80 2126 reg = <0x0a800000 0xcd00>;
2171 interrupts = 2127 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
2172 snps,dis_u2_s 2128 snps,dis_u2_susphy_quirk;
2173 snps,dis_enbl 2129 snps,dis_enblslpm_quirk;
2174 snps,parkmode !! 2130 phys = <&qusb2phy>, <&usb1_ssphy>;
2175 phys = <&qusb <<
2176 phy-names = " 2131 phy-names = "usb2-phy", "usb3-phy";
2177 snps,has-lpm- 2132 snps,has-lpm-erratum;
2178 snps,hird-thr 2133 snps,hird-threshold = /bits/ 8 <0x10>;
2179 }; 2134 };
2180 }; 2135 };
2181 2136
2182 usb3phy: phy@c010000 { 2137 usb3phy: phy@c010000 {
2183 compatible = "qcom,ms 2138 compatible = "qcom,msm8998-qmp-usb3-phy";
2184 reg = <0x0c010000 0x1 !! 2139 reg = <0x0c010000 0x18c>;
>> 2140 status = "disabled";
>> 2141 #address-cells = <1>;
>> 2142 #size-cells = <1>;
>> 2143 ranges;
2185 2144
2186 clocks = <&gcc GCC_US 2145 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
2187 <&gcc GCC_US <<
2188 <&gcc GCC_US 2146 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2189 <&gcc GCC_US !! 2147 <&gcc GCC_USB3_CLKREF_CLK>;
2190 clock-names = "aux", !! 2148 clock-names = "aux", "cfg_ahb", "ref";
2191 "ref", <<
2192 "cfg_ah <<
2193 "pipe"; <<
2194 clock-output-names = <<
2195 #clock-cells = <0>; <<
2196 #phy-cells = <0>; <<
2197 2149
2198 resets = <&gcc GCC_US 2150 resets = <&gcc GCC_USB3_PHY_BCR>,
2199 <&gcc GCC_US 2151 <&gcc GCC_USB3PHY_PHY_BCR>;
2200 reset-names = "phy", !! 2152 reset-names = "phy", "common";
2201 "phy_ph <<
2202 <<
2203 qcom,tcsr-reg = <&tcs <<
2204 2153
2205 status = "disabled"; !! 2154 usb1_ssphy: phy@c010200 {
>> 2155 reg = <0xc010200 0x128>,
>> 2156 <0xc010400 0x200>,
>> 2157 <0xc010c00 0x20c>,
>> 2158 <0xc010600 0x128>,
>> 2159 <0xc010800 0x200>;
>> 2160 #phy-cells = <0>;
>> 2161 #clock-cells = <0>;
>> 2162 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
>> 2163 clock-names = "pipe0";
>> 2164 clock-output-names = "usb3_phy_pipe_clk_src";
>> 2165 };
2206 }; 2166 };
2207 2167
2208 qusb2phy: phy@c012000 { 2168 qusb2phy: phy@c012000 {
2209 compatible = "qcom,ms 2169 compatible = "qcom,msm8998-qusb2-phy";
2210 reg = <0x0c012000 0x2 2170 reg = <0x0c012000 0x2a8>;
2211 status = "disabled"; 2171 status = "disabled";
2212 #phy-cells = <0>; 2172 #phy-cells = <0>;
2213 2173
2214 clocks = <&gcc GCC_US 2174 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2215 <&gcc GCC_RX 2175 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
2216 clock-names = "cfg_ah 2176 clock-names = "cfg_ahb", "ref";
2217 2177
2218 resets = <&gcc GCC_QU 2178 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2219 2179
2220 nvmem-cells = <&qusb2 2180 nvmem-cells = <&qusb2_hstx_trim>;
2221 }; 2181 };
2222 2182
2223 sdhc2: mmc@c0a4900 { 2183 sdhc2: mmc@c0a4900 {
2224 compatible = "qcom,ms 2184 compatible = "qcom,msm8998-sdhci", "qcom,sdhci-msm-v4";
2225 reg = <0x0c0a4900 0x3 2185 reg = <0x0c0a4900 0x314>, <0x0c0a4000 0x800>;
2226 reg-names = "hc", "co 2186 reg-names = "hc", "core";
2227 2187
2228 interrupts = <GIC_SPI 2188 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
2229 <GIC_SPI 2189 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
2230 interrupt-names = "hc 2190 interrupt-names = "hc_irq", "pwr_irq";
2231 2191
2232 clock-names = "iface" 2192 clock-names = "iface", "core", "xo";
2233 clocks = <&gcc GCC_SD 2193 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2234 <&gcc GCC_SD 2194 <&gcc GCC_SDCC2_APPS_CLK>,
2235 <&rpmcc RPM_ 2195 <&rpmcc RPM_SMD_XO_CLK_SRC>;
2236 bus-width = <4>; 2196 bus-width = <4>;
2237 status = "disabled"; 2197 status = "disabled";
2238 }; 2198 };
2239 2199
2240 blsp1_dma: dma-controller@c14 2200 blsp1_dma: dma-controller@c144000 {
2241 compatible = "qcom,ba 2201 compatible = "qcom,bam-v1.7.0";
2242 reg = <0x0c144000 0x2 2202 reg = <0x0c144000 0x25000>;
2243 interrupts = <GIC_SPI 2203 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
2244 clocks = <&gcc GCC_BL 2204 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
2245 clock-names = "bam_cl 2205 clock-names = "bam_clk";
2246 #dma-cells = <1>; 2206 #dma-cells = <1>;
2247 qcom,ee = <0>; 2207 qcom,ee = <0>;
2248 qcom,controlled-remot 2208 qcom,controlled-remotely;
2249 num-channels = <18>; 2209 num-channels = <18>;
2250 qcom,num-ees = <4>; 2210 qcom,num-ees = <4>;
2251 }; 2211 };
2252 2212
2253 blsp1_uart3: serial@c171000 { 2213 blsp1_uart3: serial@c171000 {
2254 compatible = "qcom,ms 2214 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2255 reg = <0x0c171000 0x1 2215 reg = <0x0c171000 0x1000>;
2256 interrupts = <GIC_SPI 2216 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
2257 clocks = <&gcc GCC_BL 2217 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
2258 <&gcc GCC_BL 2218 <&gcc GCC_BLSP1_AHB_CLK>;
2259 clock-names = "core", 2219 clock-names = "core", "iface";
2260 dmas = <&blsp1_dma 4> 2220 dmas = <&blsp1_dma 4>, <&blsp1_dma 5>;
2261 dma-names = "tx", "rx 2221 dma-names = "tx", "rx";
2262 pinctrl-names = "defa 2222 pinctrl-names = "default";
2263 pinctrl-0 = <&blsp1_u 2223 pinctrl-0 = <&blsp1_uart3_on>;
2264 status = "disabled"; 2224 status = "disabled";
2265 }; 2225 };
2266 2226
2267 blsp1_i2c1: i2c@c175000 { 2227 blsp1_i2c1: i2c@c175000 {
2268 compatible = "qcom,i2 2228 compatible = "qcom,i2c-qup-v2.2.1";
2269 reg = <0x0c175000 0x6 2229 reg = <0x0c175000 0x600>;
2270 interrupts = <GIC_SPI 2230 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
2271 2231
2272 clocks = <&gcc GCC_BL 2232 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
2273 <&gcc GCC_BL 2233 <&gcc GCC_BLSP1_AHB_CLK>;
2274 clock-names = "core", 2234 clock-names = "core", "iface";
2275 dmas = <&blsp1_dma 6> 2235 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>;
2276 dma-names = "tx", "rx 2236 dma-names = "tx", "rx";
2277 pinctrl-names = "defa 2237 pinctrl-names = "default", "sleep";
2278 pinctrl-0 = <&blsp1_i 2238 pinctrl-0 = <&blsp1_i2c1_default>;
2279 pinctrl-1 = <&blsp1_i 2239 pinctrl-1 = <&blsp1_i2c1_sleep>;
2280 clock-frequency = <40 2240 clock-frequency = <400000>;
2281 2241
2282 status = "disabled"; 2242 status = "disabled";
2283 #address-cells = <1>; 2243 #address-cells = <1>;
2284 #size-cells = <0>; 2244 #size-cells = <0>;
2285 }; 2245 };
2286 2246
2287 blsp1_i2c2: i2c@c176000 { 2247 blsp1_i2c2: i2c@c176000 {
2288 compatible = "qcom,i2 2248 compatible = "qcom,i2c-qup-v2.2.1";
2289 reg = <0x0c176000 0x6 2249 reg = <0x0c176000 0x600>;
2290 interrupts = <GIC_SPI 2250 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
2291 2251
2292 clocks = <&gcc GCC_BL 2252 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
2293 <&gcc GCC_BL 2253 <&gcc GCC_BLSP1_AHB_CLK>;
2294 clock-names = "core", 2254 clock-names = "core", "iface";
2295 dmas = <&blsp1_dma 8> 2255 dmas = <&blsp1_dma 8>, <&blsp1_dma 9>;
2296 dma-names = "tx", "rx 2256 dma-names = "tx", "rx";
2297 pinctrl-names = "defa 2257 pinctrl-names = "default", "sleep";
2298 pinctrl-0 = <&blsp1_i 2258 pinctrl-0 = <&blsp1_i2c2_default>;
2299 pinctrl-1 = <&blsp1_i 2259 pinctrl-1 = <&blsp1_i2c2_sleep>;
2300 clock-frequency = <40 2260 clock-frequency = <400000>;
2301 2261
2302 status = "disabled"; 2262 status = "disabled";
2303 #address-cells = <1>; 2263 #address-cells = <1>;
2304 #size-cells = <0>; 2264 #size-cells = <0>;
2305 }; 2265 };
2306 2266
2307 blsp1_i2c3: i2c@c177000 { 2267 blsp1_i2c3: i2c@c177000 {
2308 compatible = "qcom,i2 2268 compatible = "qcom,i2c-qup-v2.2.1";
2309 reg = <0x0c177000 0x6 2269 reg = <0x0c177000 0x600>;
2310 interrupts = <GIC_SPI 2270 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
2311 2271
2312 clocks = <&gcc GCC_BL 2272 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
2313 <&gcc GCC_BL 2273 <&gcc GCC_BLSP1_AHB_CLK>;
2314 clock-names = "core", 2274 clock-names = "core", "iface";
2315 dmas = <&blsp1_dma 10 2275 dmas = <&blsp1_dma 10>, <&blsp1_dma 11>;
2316 dma-names = "tx", "rx 2276 dma-names = "tx", "rx";
2317 pinctrl-names = "defa 2277 pinctrl-names = "default", "sleep";
2318 pinctrl-0 = <&blsp1_i 2278 pinctrl-0 = <&blsp1_i2c3_default>;
2319 pinctrl-1 = <&blsp1_i 2279 pinctrl-1 = <&blsp1_i2c3_sleep>;
2320 clock-frequency = <40 2280 clock-frequency = <400000>;
2321 2281
2322 status = "disabled"; 2282 status = "disabled";
2323 #address-cells = <1>; 2283 #address-cells = <1>;
2324 #size-cells = <0>; 2284 #size-cells = <0>;
2325 }; 2285 };
2326 2286
2327 blsp1_i2c4: i2c@c178000 { 2287 blsp1_i2c4: i2c@c178000 {
2328 compatible = "qcom,i2 2288 compatible = "qcom,i2c-qup-v2.2.1";
2329 reg = <0x0c178000 0x6 2289 reg = <0x0c178000 0x600>;
2330 interrupts = <GIC_SPI 2290 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
2331 2291
2332 clocks = <&gcc GCC_BL 2292 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
2333 <&gcc GCC_BL 2293 <&gcc GCC_BLSP1_AHB_CLK>;
2334 clock-names = "core", 2294 clock-names = "core", "iface";
2335 dmas = <&blsp1_dma 12 2295 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
2336 dma-names = "tx", "rx 2296 dma-names = "tx", "rx";
2337 pinctrl-names = "defa 2297 pinctrl-names = "default", "sleep";
2338 pinctrl-0 = <&blsp1_i 2298 pinctrl-0 = <&blsp1_i2c4_default>;
2339 pinctrl-1 = <&blsp1_i 2299 pinctrl-1 = <&blsp1_i2c4_sleep>;
2340 clock-frequency = <40 2300 clock-frequency = <400000>;
2341 2301
2342 status = "disabled"; 2302 status = "disabled";
2343 #address-cells = <1>; 2303 #address-cells = <1>;
2344 #size-cells = <0>; 2304 #size-cells = <0>;
2345 }; 2305 };
2346 2306
2347 blsp1_i2c5: i2c@c179000 { 2307 blsp1_i2c5: i2c@c179000 {
2348 compatible = "qcom,i2 2308 compatible = "qcom,i2c-qup-v2.2.1";
2349 reg = <0x0c179000 0x6 2309 reg = <0x0c179000 0x600>;
2350 interrupts = <GIC_SPI 2310 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
2351 2311
2352 clocks = <&gcc GCC_BL 2312 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
2353 <&gcc GCC_BL 2313 <&gcc GCC_BLSP1_AHB_CLK>;
2354 clock-names = "core", 2314 clock-names = "core", "iface";
2355 dmas = <&blsp1_dma 14 2315 dmas = <&blsp1_dma 14>, <&blsp1_dma 15>;
2356 dma-names = "tx", "rx 2316 dma-names = "tx", "rx";
2357 pinctrl-names = "defa 2317 pinctrl-names = "default", "sleep";
2358 pinctrl-0 = <&blsp1_i 2318 pinctrl-0 = <&blsp1_i2c5_default>;
2359 pinctrl-1 = <&blsp1_i 2319 pinctrl-1 = <&blsp1_i2c5_sleep>;
2360 clock-frequency = <40 2320 clock-frequency = <400000>;
2361 2321
2362 status = "disabled"; 2322 status = "disabled";
2363 #address-cells = <1>; 2323 #address-cells = <1>;
2364 #size-cells = <0>; 2324 #size-cells = <0>;
2365 }; 2325 };
2366 2326
2367 blsp1_i2c6: i2c@c17a000 { 2327 blsp1_i2c6: i2c@c17a000 {
2368 compatible = "qcom,i2 2328 compatible = "qcom,i2c-qup-v2.2.1";
2369 reg = <0x0c17a000 0x6 2329 reg = <0x0c17a000 0x600>;
2370 interrupts = <GIC_SPI 2330 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
2371 2331
2372 clocks = <&gcc GCC_BL 2332 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
2373 <&gcc GCC_BL 2333 <&gcc GCC_BLSP1_AHB_CLK>;
2374 clock-names = "core", 2334 clock-names = "core", "iface";
2375 dmas = <&blsp1_dma 16 2335 dmas = <&blsp1_dma 16>, <&blsp1_dma 17>;
2376 dma-names = "tx", "rx 2336 dma-names = "tx", "rx";
2377 pinctrl-names = "defa 2337 pinctrl-names = "default", "sleep";
2378 pinctrl-0 = <&blsp1_i 2338 pinctrl-0 = <&blsp1_i2c6_default>;
2379 pinctrl-1 = <&blsp1_i 2339 pinctrl-1 = <&blsp1_i2c6_sleep>;
2380 clock-frequency = <40 2340 clock-frequency = <400000>;
2381 2341
2382 status = "disabled"; 2342 status = "disabled";
2383 #address-cells = <1>; 2343 #address-cells = <1>;
2384 #size-cells = <0>; 2344 #size-cells = <0>;
2385 }; 2345 };
2386 2346
2387 blsp1_spi1: spi@c175000 { 2347 blsp1_spi1: spi@c175000 {
2388 compatible = "qcom,sp 2348 compatible = "qcom,spi-qup-v2.2.1";
2389 reg = <0x0c175000 0x6 2349 reg = <0x0c175000 0x600>;
2390 interrupts = <GIC_SPI 2350 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
2391 2351
2392 clocks = <&gcc GCC_BL 2352 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
2393 <&gcc GCC_BL 2353 <&gcc GCC_BLSP1_AHB_CLK>;
2394 clock-names = "core", 2354 clock-names = "core", "iface";
2395 dmas = <&blsp1_dma 6> 2355 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>;
2396 dma-names = "tx", "rx 2356 dma-names = "tx", "rx";
2397 pinctrl-names = "defa 2357 pinctrl-names = "default";
2398 pinctrl-0 = <&blsp1_s 2358 pinctrl-0 = <&blsp1_spi1_default>;
2399 2359
2400 status = "disabled"; 2360 status = "disabled";
2401 #address-cells = <1>; 2361 #address-cells = <1>;
2402 #size-cells = <0>; 2362 #size-cells = <0>;
2403 }; 2363 };
2404 2364
2405 blsp1_spi2: spi@c176000 { 2365 blsp1_spi2: spi@c176000 {
2406 compatible = "qcom,sp 2366 compatible = "qcom,spi-qup-v2.2.1";
2407 reg = <0x0c176000 0x6 2367 reg = <0x0c176000 0x600>;
2408 interrupts = <GIC_SPI 2368 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
2409 2369
2410 clocks = <&gcc GCC_BL 2370 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
2411 <&gcc GCC_BL 2371 <&gcc GCC_BLSP1_AHB_CLK>;
2412 clock-names = "core", 2372 clock-names = "core", "iface";
2413 dmas = <&blsp1_dma 8> 2373 dmas = <&blsp1_dma 8>, <&blsp1_dma 9>;
2414 dma-names = "tx", "rx 2374 dma-names = "tx", "rx";
2415 pinctrl-names = "defa 2375 pinctrl-names = "default";
2416 pinctrl-0 = <&blsp1_s 2376 pinctrl-0 = <&blsp1_spi2_default>;
2417 2377
2418 status = "disabled"; 2378 status = "disabled";
2419 #address-cells = <1>; 2379 #address-cells = <1>;
2420 #size-cells = <0>; 2380 #size-cells = <0>;
2421 }; 2381 };
2422 2382
2423 blsp1_spi3: spi@c177000 { 2383 blsp1_spi3: spi@c177000 {
2424 compatible = "qcom,sp 2384 compatible = "qcom,spi-qup-v2.2.1";
2425 reg = <0x0c177000 0x6 2385 reg = <0x0c177000 0x600>;
2426 interrupts = <GIC_SPI 2386 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
2427 2387
2428 clocks = <&gcc GCC_BL 2388 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
2429 <&gcc GCC_BL 2389 <&gcc GCC_BLSP1_AHB_CLK>;
2430 clock-names = "core", 2390 clock-names = "core", "iface";
2431 dmas = <&blsp1_dma 10 2391 dmas = <&blsp1_dma 10>, <&blsp1_dma 11>;
2432 dma-names = "tx", "rx 2392 dma-names = "tx", "rx";
2433 pinctrl-names = "defa 2393 pinctrl-names = "default";
2434 pinctrl-0 = <&blsp1_s 2394 pinctrl-0 = <&blsp1_spi3_default>;
2435 2395
2436 status = "disabled"; 2396 status = "disabled";
2437 #address-cells = <1>; 2397 #address-cells = <1>;
2438 #size-cells = <0>; 2398 #size-cells = <0>;
2439 }; 2399 };
2440 2400
2441 blsp1_spi4: spi@c178000 { 2401 blsp1_spi4: spi@c178000 {
2442 compatible = "qcom,sp 2402 compatible = "qcom,spi-qup-v2.2.1";
2443 reg = <0x0c178000 0x6 2403 reg = <0x0c178000 0x600>;
2444 interrupts = <GIC_SPI 2404 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
2445 2405
2446 clocks = <&gcc GCC_BL 2406 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
2447 <&gcc GCC_BL 2407 <&gcc GCC_BLSP1_AHB_CLK>;
2448 clock-names = "core", 2408 clock-names = "core", "iface";
2449 dmas = <&blsp1_dma 12 2409 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
2450 dma-names = "tx", "rx 2410 dma-names = "tx", "rx";
2451 pinctrl-names = "defa 2411 pinctrl-names = "default";
2452 pinctrl-0 = <&blsp1_s 2412 pinctrl-0 = <&blsp1_spi4_default>;
2453 2413
2454 status = "disabled"; 2414 status = "disabled";
2455 #address-cells = <1>; 2415 #address-cells = <1>;
2456 #size-cells = <0>; 2416 #size-cells = <0>;
2457 }; 2417 };
2458 2418
2459 blsp1_spi5: spi@c179000 { 2419 blsp1_spi5: spi@c179000 {
2460 compatible = "qcom,sp 2420 compatible = "qcom,spi-qup-v2.2.1";
2461 reg = <0x0c179000 0x6 2421 reg = <0x0c179000 0x600>;
2462 interrupts = <GIC_SPI 2422 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
2463 2423
2464 clocks = <&gcc GCC_BL 2424 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
2465 <&gcc GCC_BL 2425 <&gcc GCC_BLSP1_AHB_CLK>;
2466 clock-names = "core", 2426 clock-names = "core", "iface";
2467 dmas = <&blsp1_dma 14 2427 dmas = <&blsp1_dma 14>, <&blsp1_dma 15>;
2468 dma-names = "tx", "rx 2428 dma-names = "tx", "rx";
2469 pinctrl-names = "defa 2429 pinctrl-names = "default";
2470 pinctrl-0 = <&blsp1_s 2430 pinctrl-0 = <&blsp1_spi5_default>;
2471 2431
2472 status = "disabled"; 2432 status = "disabled";
2473 #address-cells = <1>; 2433 #address-cells = <1>;
2474 #size-cells = <0>; 2434 #size-cells = <0>;
2475 }; 2435 };
2476 2436
2477 blsp1_spi6: spi@c17a000 { 2437 blsp1_spi6: spi@c17a000 {
2478 compatible = "qcom,sp 2438 compatible = "qcom,spi-qup-v2.2.1";
2479 reg = <0x0c17a000 0x6 2439 reg = <0x0c17a000 0x600>;
2480 interrupts = <GIC_SPI 2440 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
2481 2441
2482 clocks = <&gcc GCC_BL 2442 clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
2483 <&gcc GCC_BL 2443 <&gcc GCC_BLSP1_AHB_CLK>;
2484 clock-names = "core", 2444 clock-names = "core", "iface";
2485 dmas = <&blsp1_dma 16 2445 dmas = <&blsp1_dma 16>, <&blsp1_dma 17>;
2486 dma-names = "tx", "rx 2446 dma-names = "tx", "rx";
2487 pinctrl-names = "defa 2447 pinctrl-names = "default";
2488 pinctrl-0 = <&blsp1_s 2448 pinctrl-0 = <&blsp1_spi6_default>;
2489 2449
2490 status = "disabled"; 2450 status = "disabled";
2491 #address-cells = <1>; 2451 #address-cells = <1>;
2492 #size-cells = <0>; 2452 #size-cells = <0>;
2493 }; 2453 };
2494 2454
2495 blsp2_dma: dma-controller@c18 2455 blsp2_dma: dma-controller@c184000 {
2496 compatible = "qcom,ba 2456 compatible = "qcom,bam-v1.7.0";
2497 reg = <0x0c184000 0x2 2457 reg = <0x0c184000 0x25000>;
2498 interrupts = <GIC_SPI 2458 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
2499 clocks = <&gcc GCC_BL 2459 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
2500 clock-names = "bam_cl 2460 clock-names = "bam_clk";
2501 #dma-cells = <1>; 2461 #dma-cells = <1>;
2502 qcom,ee = <0>; 2462 qcom,ee = <0>;
2503 qcom,controlled-remot 2463 qcom,controlled-remotely;
2504 num-channels = <18>; 2464 num-channels = <18>;
2505 qcom,num-ees = <4>; 2465 qcom,num-ees = <4>;
2506 }; 2466 };
2507 2467
2508 blsp2_uart1: serial@c1b0000 { 2468 blsp2_uart1: serial@c1b0000 {
2509 compatible = "qcom,ms 2469 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2510 reg = <0x0c1b0000 0x1 2470 reg = <0x0c1b0000 0x1000>;
2511 interrupts = <GIC_SPI 2471 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
2512 clocks = <&gcc GCC_BL 2472 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
2513 <&gcc GCC_BL 2473 <&gcc GCC_BLSP2_AHB_CLK>;
2514 clock-names = "core", 2474 clock-names = "core", "iface";
2515 status = "disabled"; 2475 status = "disabled";
2516 }; 2476 };
2517 2477
2518 blsp2_i2c1: i2c@c1b5000 { 2478 blsp2_i2c1: i2c@c1b5000 {
2519 compatible = "qcom,i2 2479 compatible = "qcom,i2c-qup-v2.2.1";
2520 reg = <0x0c1b5000 0x6 2480 reg = <0x0c1b5000 0x600>;
2521 interrupts = <GIC_SPI 2481 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
2522 2482
2523 clocks = <&gcc GCC_BL 2483 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
2524 <&gcc GCC_BL 2484 <&gcc GCC_BLSP2_AHB_CLK>;
2525 clock-names = "core", 2485 clock-names = "core", "iface";
2526 dmas = <&blsp2_dma 6> 2486 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>;
2527 dma-names = "tx", "rx 2487 dma-names = "tx", "rx";
2528 pinctrl-names = "defa 2488 pinctrl-names = "default", "sleep";
2529 pinctrl-0 = <&blsp2_i 2489 pinctrl-0 = <&blsp2_i2c1_default>;
2530 pinctrl-1 = <&blsp2_i 2490 pinctrl-1 = <&blsp2_i2c1_sleep>;
2531 clock-frequency = <40 2491 clock-frequency = <400000>;
2532 2492
2533 status = "disabled"; 2493 status = "disabled";
2534 #address-cells = <1>; 2494 #address-cells = <1>;
2535 #size-cells = <0>; 2495 #size-cells = <0>;
2536 }; 2496 };
2537 2497
2538 blsp2_i2c2: i2c@c1b6000 { 2498 blsp2_i2c2: i2c@c1b6000 {
2539 compatible = "qcom,i2 2499 compatible = "qcom,i2c-qup-v2.2.1";
2540 reg = <0x0c1b6000 0x6 2500 reg = <0x0c1b6000 0x600>;
2541 interrupts = <GIC_SPI 2501 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
2542 2502
2543 clocks = <&gcc GCC_BL 2503 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
2544 <&gcc GCC_BL 2504 <&gcc GCC_BLSP2_AHB_CLK>;
2545 clock-names = "core", 2505 clock-names = "core", "iface";
2546 dmas = <&blsp2_dma 8> 2506 dmas = <&blsp2_dma 8>, <&blsp2_dma 9>;
2547 dma-names = "tx", "rx 2507 dma-names = "tx", "rx";
2548 pinctrl-names = "defa 2508 pinctrl-names = "default", "sleep";
2549 pinctrl-0 = <&blsp2_i 2509 pinctrl-0 = <&blsp2_i2c2_default>;
2550 pinctrl-1 = <&blsp2_i 2510 pinctrl-1 = <&blsp2_i2c2_sleep>;
2551 clock-frequency = <40 2511 clock-frequency = <400000>;
2552 2512
2553 status = "disabled"; 2513 status = "disabled";
2554 #address-cells = <1>; 2514 #address-cells = <1>;
2555 #size-cells = <0>; 2515 #size-cells = <0>;
2556 }; 2516 };
2557 2517
2558 blsp2_i2c3: i2c@c1b7000 { 2518 blsp2_i2c3: i2c@c1b7000 {
2559 compatible = "qcom,i2 2519 compatible = "qcom,i2c-qup-v2.2.1";
2560 reg = <0x0c1b7000 0x6 2520 reg = <0x0c1b7000 0x600>;
2561 interrupts = <GIC_SPI 2521 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
2562 2522
2563 clocks = <&gcc GCC_BL 2523 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
2564 <&gcc GCC_BL 2524 <&gcc GCC_BLSP2_AHB_CLK>;
2565 clock-names = "core", 2525 clock-names = "core", "iface";
2566 dmas = <&blsp2_dma 10 2526 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>;
2567 dma-names = "tx", "rx 2527 dma-names = "tx", "rx";
2568 pinctrl-names = "defa 2528 pinctrl-names = "default", "sleep";
2569 pinctrl-0 = <&blsp2_i 2529 pinctrl-0 = <&blsp2_i2c3_default>;
2570 pinctrl-1 = <&blsp2_i 2530 pinctrl-1 = <&blsp2_i2c3_sleep>;
2571 clock-frequency = <40 2531 clock-frequency = <400000>;
2572 2532
2573 status = "disabled"; 2533 status = "disabled";
2574 #address-cells = <1>; 2534 #address-cells = <1>;
2575 #size-cells = <0>; 2535 #size-cells = <0>;
2576 }; 2536 };
2577 2537
2578 blsp2_i2c4: i2c@c1b8000 { 2538 blsp2_i2c4: i2c@c1b8000 {
2579 compatible = "qcom,i2 2539 compatible = "qcom,i2c-qup-v2.2.1";
2580 reg = <0x0c1b8000 0x6 2540 reg = <0x0c1b8000 0x600>;
2581 interrupts = <GIC_SPI 2541 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
2582 2542
2583 clocks = <&gcc GCC_BL 2543 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>,
2584 <&gcc GCC_BL 2544 <&gcc GCC_BLSP2_AHB_CLK>;
2585 clock-names = "core", 2545 clock-names = "core", "iface";
2586 dmas = <&blsp2_dma 12 2546 dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
2587 dma-names = "tx", "rx 2547 dma-names = "tx", "rx";
2588 pinctrl-names = "defa 2548 pinctrl-names = "default", "sleep";
2589 pinctrl-0 = <&blsp2_i 2549 pinctrl-0 = <&blsp2_i2c4_default>;
2590 pinctrl-1 = <&blsp2_i 2550 pinctrl-1 = <&blsp2_i2c4_sleep>;
2591 clock-frequency = <40 2551 clock-frequency = <400000>;
2592 2552
2593 status = "disabled"; 2553 status = "disabled";
2594 #address-cells = <1>; 2554 #address-cells = <1>;
2595 #size-cells = <0>; 2555 #size-cells = <0>;
2596 }; 2556 };
2597 2557
2598 blsp2_i2c5: i2c@c1b9000 { 2558 blsp2_i2c5: i2c@c1b9000 {
2599 compatible = "qcom,i2 2559 compatible = "qcom,i2c-qup-v2.2.1";
2600 reg = <0x0c1b9000 0x6 2560 reg = <0x0c1b9000 0x600>;
2601 interrupts = <GIC_SPI 2561 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
2602 2562
2603 clocks = <&gcc GCC_BL 2563 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,
2604 <&gcc GCC_BL 2564 <&gcc GCC_BLSP2_AHB_CLK>;
2605 clock-names = "core", 2565 clock-names = "core", "iface";
2606 dmas = <&blsp2_dma 14 2566 dmas = <&blsp2_dma 14>, <&blsp2_dma 15>;
2607 dma-names = "tx", "rx 2567 dma-names = "tx", "rx";
2608 pinctrl-names = "defa 2568 pinctrl-names = "default", "sleep";
2609 pinctrl-0 = <&blsp2_i 2569 pinctrl-0 = <&blsp2_i2c5_default>;
2610 pinctrl-1 = <&blsp2_i 2570 pinctrl-1 = <&blsp2_i2c5_sleep>;
2611 clock-frequency = <40 2571 clock-frequency = <400000>;
2612 2572
2613 status = "disabled"; 2573 status = "disabled";
2614 #address-cells = <1>; 2574 #address-cells = <1>;
2615 #size-cells = <0>; 2575 #size-cells = <0>;
2616 }; 2576 };
2617 2577
2618 blsp2_i2c6: i2c@c1ba000 { 2578 blsp2_i2c6: i2c@c1ba000 {
2619 compatible = "qcom,i2 2579 compatible = "qcom,i2c-qup-v2.2.1";
2620 reg = <0x0c1ba000 0x6 2580 reg = <0x0c1ba000 0x600>;
2621 interrupts = <GIC_SPI 2581 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
2622 2582
2623 clocks = <&gcc GCC_BL 2583 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>,
2624 <&gcc GCC_BL 2584 <&gcc GCC_BLSP2_AHB_CLK>;
2625 clock-names = "core", 2585 clock-names = "core", "iface";
2626 dmas = <&blsp2_dma 16 2586 dmas = <&blsp2_dma 16>, <&blsp2_dma 17>;
2627 dma-names = "tx", "rx 2587 dma-names = "tx", "rx";
2628 pinctrl-names = "defa 2588 pinctrl-names = "default", "sleep";
2629 pinctrl-0 = <&blsp2_i 2589 pinctrl-0 = <&blsp2_i2c6_default>;
2630 pinctrl-1 = <&blsp2_i 2590 pinctrl-1 = <&blsp2_i2c6_sleep>;
2631 clock-frequency = <40 2591 clock-frequency = <400000>;
2632 2592
2633 status = "disabled"; 2593 status = "disabled";
2634 #address-cells = <1>; 2594 #address-cells = <1>;
2635 #size-cells = <0>; 2595 #size-cells = <0>;
2636 }; 2596 };
2637 2597
2638 blsp2_spi1: spi@c1b5000 { 2598 blsp2_spi1: spi@c1b5000 {
2639 compatible = "qcom,sp 2599 compatible = "qcom,spi-qup-v2.2.1";
2640 reg = <0x0c1b5000 0x6 2600 reg = <0x0c1b5000 0x600>;
2641 interrupts = <GIC_SPI 2601 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
2642 2602
2643 clocks = <&gcc GCC_BL 2603 clocks = <&gcc GCC_BLSP2_QUP1_SPI_APPS_CLK>,
2644 <&gcc GCC_BL 2604 <&gcc GCC_BLSP2_AHB_CLK>;
2645 clock-names = "core", 2605 clock-names = "core", "iface";
2646 dmas = <&blsp2_dma 6> 2606 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>;
2647 dma-names = "tx", "rx 2607 dma-names = "tx", "rx";
2648 pinctrl-names = "defa 2608 pinctrl-names = "default";
2649 pinctrl-0 = <&blsp2_s 2609 pinctrl-0 = <&blsp2_spi1_default>;
2650 2610
2651 status = "disabled"; 2611 status = "disabled";
2652 #address-cells = <1>; 2612 #address-cells = <1>;
2653 #size-cells = <0>; 2613 #size-cells = <0>;
2654 }; 2614 };
2655 2615
2656 blsp2_spi2: spi@c1b6000 { 2616 blsp2_spi2: spi@c1b6000 {
2657 compatible = "qcom,sp 2617 compatible = "qcom,spi-qup-v2.2.1";
2658 reg = <0x0c1b6000 0x6 2618 reg = <0x0c1b6000 0x600>;
2659 interrupts = <GIC_SPI 2619 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
2660 2620
2661 clocks = <&gcc GCC_BL 2621 clocks = <&gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>,
2662 <&gcc GCC_BL 2622 <&gcc GCC_BLSP2_AHB_CLK>;
2663 clock-names = "core", 2623 clock-names = "core", "iface";
2664 dmas = <&blsp2_dma 8> 2624 dmas = <&blsp2_dma 8>, <&blsp2_dma 9>;
2665 dma-names = "tx", "rx 2625 dma-names = "tx", "rx";
2666 pinctrl-names = "defa 2626 pinctrl-names = "default";
2667 pinctrl-0 = <&blsp2_s 2627 pinctrl-0 = <&blsp2_spi2_default>;
2668 2628
2669 status = "disabled"; 2629 status = "disabled";
2670 #address-cells = <1>; 2630 #address-cells = <1>;
2671 #size-cells = <0>; 2631 #size-cells = <0>;
2672 }; 2632 };
2673 2633
2674 blsp2_spi3: spi@c1b7000 { 2634 blsp2_spi3: spi@c1b7000 {
2675 compatible = "qcom,sp 2635 compatible = "qcom,spi-qup-v2.2.1";
2676 reg = <0x0c1b7000 0x6 2636 reg = <0x0c1b7000 0x600>;
2677 interrupts = <GIC_SPI 2637 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
2678 2638
2679 clocks = <&gcc GCC_BL 2639 clocks = <&gcc GCC_BLSP2_QUP3_SPI_APPS_CLK>,
2680 <&gcc GCC_BL 2640 <&gcc GCC_BLSP2_AHB_CLK>;
2681 clock-names = "core", 2641 clock-names = "core", "iface";
2682 dmas = <&blsp2_dma 10 2642 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>;
2683 dma-names = "tx", "rx 2643 dma-names = "tx", "rx";
2684 pinctrl-names = "defa 2644 pinctrl-names = "default";
2685 pinctrl-0 = <&blsp2_s 2645 pinctrl-0 = <&blsp2_spi3_default>;
2686 2646
2687 status = "disabled"; 2647 status = "disabled";
2688 #address-cells = <1>; 2648 #address-cells = <1>;
2689 #size-cells = <0>; 2649 #size-cells = <0>;
2690 }; 2650 };
2691 2651
2692 blsp2_spi4: spi@c1b8000 { 2652 blsp2_spi4: spi@c1b8000 {
2693 compatible = "qcom,sp 2653 compatible = "qcom,spi-qup-v2.2.1";
2694 reg = <0x0c1b8000 0x6 2654 reg = <0x0c1b8000 0x600>;
2695 interrupts = <GIC_SPI 2655 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
2696 2656
2697 clocks = <&gcc GCC_BL 2657 clocks = <&gcc GCC_BLSP2_QUP4_SPI_APPS_CLK>,
2698 <&gcc GCC_BL 2658 <&gcc GCC_BLSP2_AHB_CLK>;
2699 clock-names = "core", 2659 clock-names = "core", "iface";
2700 dmas = <&blsp2_dma 12 2660 dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
2701 dma-names = "tx", "rx 2661 dma-names = "tx", "rx";
2702 pinctrl-names = "defa 2662 pinctrl-names = "default";
2703 pinctrl-0 = <&blsp2_s 2663 pinctrl-0 = <&blsp2_spi4_default>;
2704 2664
2705 status = "disabled"; 2665 status = "disabled";
2706 #address-cells = <1>; 2666 #address-cells = <1>;
2707 #size-cells = <0>; 2667 #size-cells = <0>;
2708 }; 2668 };
2709 2669
2710 blsp2_spi5: spi@c1b9000 { 2670 blsp2_spi5: spi@c1b9000 {
2711 compatible = "qcom,sp 2671 compatible = "qcom,spi-qup-v2.2.1";
2712 reg = <0x0c1b9000 0x6 2672 reg = <0x0c1b9000 0x600>;
2713 interrupts = <GIC_SPI 2673 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
2714 2674
2715 clocks = <&gcc GCC_BL 2675 clocks = <&gcc GCC_BLSP2_QUP5_SPI_APPS_CLK>,
2716 <&gcc GCC_BL 2676 <&gcc GCC_BLSP2_AHB_CLK>;
2717 clock-names = "core", 2677 clock-names = "core", "iface";
2718 dmas = <&blsp2_dma 14 2678 dmas = <&blsp2_dma 14>, <&blsp2_dma 15>;
2719 dma-names = "tx", "rx 2679 dma-names = "tx", "rx";
2720 pinctrl-names = "defa 2680 pinctrl-names = "default";
2721 pinctrl-0 = <&blsp2_s 2681 pinctrl-0 = <&blsp2_spi5_default>;
2722 2682
2723 status = "disabled"; 2683 status = "disabled";
2724 #address-cells = <1>; 2684 #address-cells = <1>;
2725 #size-cells = <0>; 2685 #size-cells = <0>;
2726 }; 2686 };
2727 2687
2728 blsp2_spi6: spi@c1ba000 { 2688 blsp2_spi6: spi@c1ba000 {
2729 compatible = "qcom,sp 2689 compatible = "qcom,spi-qup-v2.2.1";
2730 reg = <0x0c1ba000 0x6 2690 reg = <0x0c1ba000 0x600>;
2731 interrupts = <GIC_SPI 2691 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
2732 2692
2733 clocks = <&gcc GCC_BL 2693 clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>,
2734 <&gcc GCC_BL 2694 <&gcc GCC_BLSP2_AHB_CLK>;
2735 clock-names = "core", 2695 clock-names = "core", "iface";
2736 dmas = <&blsp2_dma 16 2696 dmas = <&blsp2_dma 16>, <&blsp2_dma 17>;
2737 dma-names = "tx", "rx 2697 dma-names = "tx", "rx";
2738 pinctrl-names = "defa 2698 pinctrl-names = "default";
2739 pinctrl-0 = <&blsp2_s 2699 pinctrl-0 = <&blsp2_spi6_default>;
2740 2700
2741 status = "disabled"; 2701 status = "disabled";
2742 #address-cells = <1>; 2702 #address-cells = <1>;
2743 #size-cells = <0>; 2703 #size-cells = <0>;
2744 }; 2704 };
2745 2705
2746 mmcc: clock-controller@c8c000 2706 mmcc: clock-controller@c8c0000 {
2747 compatible = "qcom,mm 2707 compatible = "qcom,mmcc-msm8998";
2748 #clock-cells = <1>; 2708 #clock-cells = <1>;
2749 #reset-cells = <1>; 2709 #reset-cells = <1>;
2750 #power-domain-cells = 2710 #power-domain-cells = <1>;
2751 reg = <0xc8c0000 0x40 2711 reg = <0xc8c0000 0x40000>;
2752 2712
2753 clock-names = "xo", 2713 clock-names = "xo",
2754 "gpll0" 2714 "gpll0",
2755 "dsi0ds 2715 "dsi0dsi",
2756 "dsi0by 2716 "dsi0byte",
2757 "dsi1ds 2717 "dsi1dsi",
2758 "dsi1by 2718 "dsi1byte",
2759 "hdmipl 2719 "hdmipll",
2760 "dplink 2720 "dplink",
2761 "dpvco" !! 2721 "dpvco";
2762 "gpll0_ <<
2763 clocks = <&rpmcc RPM_ 2722 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
2764 <&gcc GCC_MM 2723 <&gcc GCC_MMSS_GPLL0_CLK>,
2765 <&mdss_dsi0_ <<
2766 <&mdss_dsi0_ <<
2767 <&mdss_dsi1_ <<
2768 <&mdss_dsi1_ <<
2769 <0>, 2724 <0>,
2770 <0>, 2725 <0>,
2771 <0>, 2726 <0>,
2772 <&gcc GCC_MM !! 2727 <0>,
2773 }; !! 2728 <0>,
2774 !! 2729 <0>,
2775 mdss: display-subsystem@c9000 !! 2730 <0>;
2776 compatible = "qcom,ms <<
2777 reg = <0x0c900000 0x1 <<
2778 reg-names = "mdss"; <<
2779 <<
2780 interrupts = <GIC_SPI <<
2781 interrupt-controller; <<
2782 #interrupt-cells = <1 <<
2783 <<
2784 clocks = <&mmcc MDSS_ <<
2785 <&mmcc MDSS_ <<
2786 <&mmcc MDSS_ <<
2787 clock-names = "iface" <<
2788 "bus", <<
2789 "core"; <<
2790 <<
2791 power-domains = <&mmc <<
2792 iommus = <&mmss_smmu <<
2793 <<
2794 #address-cells = <1>; <<
2795 #size-cells = <1>; <<
2796 ranges; <<
2797 <<
2798 status = "disabled"; <<
2799 <<
2800 mdss_mdp: display-con <<
2801 compatible = <<
2802 reg = <0x0c90 <<
2803 <0x0c9a <<
2804 <0x0c9b <<
2805 <0x0c9b <<
2806 reg-names = " <<
2807 " <<
2808 " <<
2809 " <<
2810 <<
2811 interrupt-par <<
2812 interrupts = <<
2813 <<
2814 clocks = <&mm <<
2815 <&mm <<
2816 <&mm <<
2817 <&mm <<
2818 <&mm <<
2819 clock-names = <<
2820 <<
2821 <<
2822 <<
2823 <<
2824 <<
2825 assigned-cloc <<
2826 assigned-cloc <<
2827 <<
2828 operating-poi <<
2829 power-domains <<
2830 <<
2831 mdp_opp_table <<
2832 compa <<
2833 <<
2834 opp-1 <<
2835 <<
2836 <<
2837 }; <<
2838 <<
2839 opp-2 <<
2840 <<
2841 <<
2842 }; <<
2843 <<
2844 opp-3 <<
2845 <<
2846 <<
2847 }; <<
2848 <<
2849 opp-4 <<
2850 <<
2851 <<
2852 }; <<
2853 }; <<
2854 <<
2855 ports { <<
2856 #addr <<
2857 #size <<
2858 <<
2859 port@ <<
2860 <<
2861 <<
2862 <<
2863 <<
2864 <<
2865 }; <<
2866 <<
2867 port@ <<
2868 <<
2869 <<
2870 <<
2871 <<
2872 <<
2873 }; <<
2874 }; <<
2875 }; <<
2876 <<
2877 mdss_dsi0: dsi@c99400 <<
2878 compatible = <<
2879 reg = <0x0c99 <<
2880 reg-names = " <<
2881 <<
2882 interrupt-par <<
2883 interrupts = <<
2884 <<
2885 clocks = <&mm <<
2886 <&mm <<
2887 <&mm <<
2888 <&mm <<
2889 <&mm <<
2890 <&mm <<
2891 clock-names = <<
2892 <<
2893 <<
2894 <<
2895 <<
2896 <<
2897 assigned-cloc <<
2898 <<
2899 assigned-cloc <<
2900 <<
2901 <<
2902 operating-poi <<
2903 power-domains <<
2904 <<
2905 phys = <&mdss <<
2906 phy-names = " <<
2907 <<
2908 #address-cell <<
2909 #size-cells = <<
2910 <<
2911 status = "dis <<
2912 <<
2913 ports { <<
2914 #addr <<
2915 #size <<
2916 <<
2917 port@ <<
2918 <<
2919 <<
2920 <<
2921 <<
2922 <<
2923 }; <<
2924 <<
2925 port@ <<
2926 <<
2927 <<
2928 <<
2929 <<
2930 }; <<
2931 }; <<
2932 }; <<
2933 <<
2934 mdss_dsi0_phy: phy@c9 <<
2935 compatible = <<
2936 reg = <0x0c99 <<
2937 <0x0c99 <<
2938 <0x0c99 <<
2939 reg-names = " <<
2940 " <<
2941 " <<
2942 <<
2943 clocks = <&mm <<
2944 <&rp <<
2945 clock-names = <<
2946 <<
2947 #clock-cells <<
2948 #phy-cells = <<
2949 <<
2950 status = "dis <<
2951 }; <<
2952 <<
2953 mdss_dsi1: dsi@c99600 <<
2954 compatible = <<
2955 reg = <0x0c99 <<
2956 reg-names = " <<
2957 <<
2958 interrupt-par <<
2959 interrupts = <<
2960 <<
2961 clocks = <&mm <<
2962 <&mm <<
2963 <&mm <<
2964 <&mm <<
2965 <&mm <<
2966 <&mm <<
2967 clock-names = <<
2968 <<
2969 <<
2970 <<
2971 <<
2972 <<
2973 assigned-cloc <<
2974 <<
2975 assigned-cloc <<
2976 <<
2977 <<
2978 operating-poi <<
2979 power-domains <<
2980 <<
2981 phys = <&mdss <<
2982 phy-names = " <<
2983 <<
2984 #address-cell <<
2985 #size-cells = <<
2986 <<
2987 status = "dis <<
2988 <<
2989 ports { <<
2990 #addr <<
2991 #size <<
2992 <<
2993 port@ <<
2994 <<
2995 <<
2996 <<
2997 <<
2998 <<
2999 }; <<
3000 <<
3001 port@ <<
3002 <<
3003 <<
3004 <<
3005 <<
3006 }; <<
3007 }; <<
3008 }; <<
3009 <<
3010 mdss_dsi1_phy: phy@c9 <<
3011 compatible = <<
3012 reg = <0x0c99 <<
3013 <0x0c99 <<
3014 <0x0c99 <<
3015 reg-names = " <<
3016 " <<
3017 " <<
3018 <<
3019 clocks = <&mm <<
3020 <&rp <<
3021 clock-names = <<
3022 <<
3023 <<
3024 #clock-cells <<
3025 #phy-cells = <<
3026 <<
3027 status = "dis <<
3028 }; <<
3029 }; <<
3030 <<
3031 venus: video-codec@cc00000 { <<
3032 compatible = "qcom,ms <<
3033 reg = <0x0cc00000 0xf <<
3034 interrupts = <GIC_SPI <<
3035 power-domains = <&mmc <<
3036 clocks = <&mmcc VIDEO <<
3037 <&mmcc VIDEO <<
3038 <&mmcc VIDEO <<
3039 <&mmcc VIDEO <<
3040 clock-names = "core", <<
3041 iommus = <&mmss_smmu <<
3042 <&mmss_smmu <<
3043 <&mmss_smmu <<
3044 <&mmss_smmu <<
3045 <&mmss_smmu <<
3046 <&mmss_smmu <<
3047 <&mmss_smmu <<
3048 <&mmss_smmu <<
3049 <&mmss_smmu <<
3050 <&mmss_smmu <<
3051 <&mmss_smmu <<
3052 <&mmss_smmu <<
3053 <&mmss_smmu <<
3054 <&mmss_smmu <<
3055 <&mmss_smmu <<
3056 <&mmss_smmu <<
3057 <&mmss_smmu <<
3058 <&mmss_smmu <<
3059 <&mmss_smmu <<
3060 <&mmss_smmu <<
3061 memory-region = <&ven <<
3062 status = "disabled"; <<
3063 <<
3064 video-decoder { <<
3065 compatible = <<
3066 clocks = <&mm <<
3067 clock-names = <<
3068 power-domains <<
3069 }; <<
3070 <<
3071 video-encoder { <<
3072 compatible = <<
3073 clocks = <&mm <<
3074 clock-names = <<
3075 power-domains <<
3076 }; <<
3077 }; 2731 };
3078 2732
3079 mmss_smmu: iommu@cd00000 { 2733 mmss_smmu: iommu@cd00000 {
3080 compatible = "qcom,ms 2734 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
3081 reg = <0x0cd00000 0x4 2735 reg = <0x0cd00000 0x40000>;
3082 #iommu-cells = <1>; 2736 #iommu-cells = <1>;
3083 2737
3084 clocks = <&mmcc MNOC_ 2738 clocks = <&mmcc MNOC_AHB_CLK>,
3085 <&mmcc BIMC_ 2739 <&mmcc BIMC_SMMU_AHB_CLK>,
3086 <&mmcc BIMC_ 2740 <&mmcc BIMC_SMMU_AXI_CLK>;
3087 clock-names = "iface- 2741 clock-names = "iface-mm",
3088 "iface- 2742 "iface-smmu",
3089 "bus-sm 2743 "bus-smmu";
3090 2744
3091 #global-interrupts = 2745 #global-interrupts = <0>;
3092 interrupts = 2746 interrupts =
3093 <GIC_SPI 263 2747 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
3094 <GIC_SPI 266 2748 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
3095 <GIC_SPI 267 2749 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
3096 <GIC_SPI 268 2750 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
3097 <GIC_SPI 244 2751 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
3098 <GIC_SPI 245 2752 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
3099 <GIC_SPI 247 2753 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
3100 <GIC_SPI 248 2754 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
3101 <GIC_SPI 249 2755 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
3102 <GIC_SPI 250 2756 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
3103 <GIC_SPI 251 2757 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
3104 <GIC_SPI 252 2758 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
3105 <GIC_SPI 253 2759 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
3106 <GIC_SPI 254 2760 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
3107 <GIC_SPI 255 2761 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
3108 <GIC_SPI 256 2762 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
3109 <GIC_SPI 260 2763 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
3110 <GIC_SPI 261 2764 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
3111 <GIC_SPI 262 2765 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
3112 <GIC_SPI 272 2766 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
3113 2767
3114 power-domains = <&mmc 2768 power-domains = <&mmcc BIMC_SMMU_GDSC>;
3115 }; 2769 };
3116 2770
3117 remoteproc_adsp: remoteproc@1 2771 remoteproc_adsp: remoteproc@17300000 {
3118 compatible = "qcom,ms 2772 compatible = "qcom,msm8998-adsp-pas";
3119 reg = <0x17300000 0x4 2773 reg = <0x17300000 0x4040>;
3120 2774
3121 interrupts-extended = 2775 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
3122 2776 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3123 2777 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3124 2778 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3125 2779 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
3126 interrupt-names = "wd 2780 interrupt-names = "wdog", "fatal", "ready",
3127 "ha 2781 "handover", "stop-ack";
3128 2782
3129 clocks = <&rpmcc RPM_ 2783 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
3130 clock-names = "xo"; 2784 clock-names = "xo";
3131 2785
3132 memory-region = <&ads 2786 memory-region = <&adsp_mem>;
3133 2787
3134 qcom,smem-states = <& 2788 qcom,smem-states = <&adsp_smp2p_out 0>;
3135 qcom,smem-state-names 2789 qcom,smem-state-names = "stop";
3136 2790
3137 power-domains = <&rpm 2791 power-domains = <&rpmpd MSM8998_VDDCX>;
3138 power-domain-names = 2792 power-domain-names = "cx";
3139 2793
3140 status = "disabled"; 2794 status = "disabled";
3141 2795
3142 glink-edge { 2796 glink-edge {
3143 interrupts = 2797 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
3144 label = "lpas 2798 label = "lpass";
3145 qcom,remote-p 2799 qcom,remote-pid = <2>;
3146 mboxes = <&ap 2800 mboxes = <&apcs_glb 9>;
3147 }; 2801 };
3148 }; 2802 };
3149 2803
3150 apcs_glb: mailbox@17911000 { 2804 apcs_glb: mailbox@17911000 {
3151 compatible = "qcom,ms 2805 compatible = "qcom,msm8998-apcs-hmss-global",
3152 "qcom,ms 2806 "qcom,msm8994-apcs-kpss-global";
3153 reg = <0x17911000 0x1 2807 reg = <0x17911000 0x1000>;
3154 2808
3155 #mbox-cells = <1>; 2809 #mbox-cells = <1>;
3156 }; 2810 };
3157 2811
3158 timer@17920000 { 2812 timer@17920000 {
3159 #address-cells = <1>; 2813 #address-cells = <1>;
3160 #size-cells = <1>; 2814 #size-cells = <1>;
3161 ranges; 2815 ranges;
3162 compatible = "arm,arm 2816 compatible = "arm,armv7-timer-mem";
3163 reg = <0x17920000 0x1 2817 reg = <0x17920000 0x1000>;
3164 2818
3165 frame@17921000 { 2819 frame@17921000 {
3166 frame-number 2820 frame-number = <0>;
3167 interrupts = 2821 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
3168 2822 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
3169 reg = <0x1792 2823 reg = <0x17921000 0x1000>,
3170 <0x1792 2824 <0x17922000 0x1000>;
3171 }; 2825 };
3172 2826
3173 frame@17923000 { 2827 frame@17923000 {
3174 frame-number 2828 frame-number = <1>;
3175 interrupts = 2829 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
3176 reg = <0x1792 2830 reg = <0x17923000 0x1000>;
3177 status = "dis 2831 status = "disabled";
3178 }; 2832 };
3179 2833
3180 frame@17924000 { 2834 frame@17924000 {
3181 frame-number 2835 frame-number = <2>;
3182 interrupts = 2836 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
3183 reg = <0x1792 2837 reg = <0x17924000 0x1000>;
3184 status = "dis 2838 status = "disabled";
3185 }; 2839 };
3186 2840
3187 frame@17925000 { 2841 frame@17925000 {
3188 frame-number 2842 frame-number = <3>;
3189 interrupts = 2843 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3190 reg = <0x1792 2844 reg = <0x17925000 0x1000>;
3191 status = "dis 2845 status = "disabled";
3192 }; 2846 };
3193 2847
3194 frame@17926000 { 2848 frame@17926000 {
3195 frame-number 2849 frame-number = <4>;
3196 interrupts = 2850 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3197 reg = <0x1792 2851 reg = <0x17926000 0x1000>;
3198 status = "dis 2852 status = "disabled";
3199 }; 2853 };
3200 2854
3201 frame@17927000 { 2855 frame@17927000 {
3202 frame-number 2856 frame-number = <5>;
3203 interrupts = 2857 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3204 reg = <0x1792 2858 reg = <0x17927000 0x1000>;
3205 status = "dis 2859 status = "disabled";
3206 }; 2860 };
3207 2861
3208 frame@17928000 { 2862 frame@17928000 {
3209 frame-number 2863 frame-number = <6>;
3210 interrupts = 2864 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
3211 reg = <0x1792 2865 reg = <0x17928000 0x1000>;
3212 status = "dis 2866 status = "disabled";
3213 }; 2867 };
3214 }; 2868 };
3215 2869
3216 intc: interrupt-controller@17 2870 intc: interrupt-controller@17a00000 {
3217 compatible = "arm,gic 2871 compatible = "arm,gic-v3";
3218 reg = <0x17a00000 0x1 2872 reg = <0x17a00000 0x10000>, /* GICD */
3219 <0x17b00000 0x1 2873 <0x17b00000 0x100000>; /* GICR * 8 */
3220 #interrupt-cells = <3 2874 #interrupt-cells = <3>;
3221 #address-cells = <1>; 2875 #address-cells = <1>;
3222 #size-cells = <1>; 2876 #size-cells = <1>;
3223 ranges; 2877 ranges;
3224 interrupt-controller; 2878 interrupt-controller;
3225 #redistributor-region 2879 #redistributor-regions = <1>;
3226 redistributor-stride 2880 redistributor-stride = <0x0 0x20000>;
3227 interrupts = <GIC_PPI 2881 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3228 }; 2882 };
3229 2883
3230 wifi: wifi@18800000 { 2884 wifi: wifi@18800000 {
3231 compatible = "qcom,wc 2885 compatible = "qcom,wcn3990-wifi";
3232 status = "disabled"; 2886 status = "disabled";
3233 reg = <0x18800000 0x8 2887 reg = <0x18800000 0x800000>;
3234 reg-names = "membase" 2888 reg-names = "membase";
3235 memory-region = <&wla 2889 memory-region = <&wlan_msa_mem>;
3236 clocks = <&rpmcc RPM_ 2890 clocks = <&rpmcc RPM_SMD_RF_CLK2_PIN>;
3237 clock-names = "cxo_re 2891 clock-names = "cxo_ref_clk_pin";
3238 interrupts = 2892 interrupts =
3239 <GIC_SPI 413 2893 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
3240 <GIC_SPI 414 2894 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
3241 <GIC_SPI 415 2895 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
3242 <GIC_SPI 416 2896 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
3243 <GIC_SPI 417 2897 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
3244 <GIC_SPI 418 2898 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
3245 <GIC_SPI 420 2899 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
3246 <GIC_SPI 421 2900 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
3247 <GIC_SPI 422 2901 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
3248 <GIC_SPI 423 2902 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
3249 <GIC_SPI 424 2903 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
3250 <GIC_SPI 425 2904 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
3251 iommus = <&anoc2_smmu 2905 iommus = <&anoc2_smmu 0x1900>,
3252 <&anoc2_smmu 2906 <&anoc2_smmu 0x1901>;
3253 qcom,snoc-host-cap-8b 2907 qcom,snoc-host-cap-8bit-quirk;
3254 qcom,no-msa-ready-ind <<
3255 }; 2908 };
3256 }; 2909 };
3257 }; 2910 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.