1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2016, The Linux Foundation. A 2 /* Copyright (c) 2016, The Linux Foundation. All rights reserved. */
3 3
4 #include <dt-bindings/interrupt-controller/arm 4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-msm8998.h 5 #include <dt-bindings/clock/qcom,gcc-msm8998.h>
6 #include <dt-bindings/clock/qcom,gpucc-msm8998 6 #include <dt-bindings/clock/qcom,gpucc-msm8998.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8998. 7 #include <dt-bindings/clock/qcom,mmcc-msm8998.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h> 8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/firmware/qcom,scm.h> <<
10 #include <dt-bindings/power/qcom-rpmpd.h> 9 #include <dt-bindings/power/qcom-rpmpd.h>
11 #include <dt-bindings/gpio/gpio.h> 10 #include <dt-bindings/gpio/gpio.h>
12 11
13 / { 12 / {
14 interrupt-parent = <&intc>; 13 interrupt-parent = <&intc>;
15 14
16 qcom,msm-id = <292 0x0>; 15 qcom,msm-id = <292 0x0>;
17 16
18 #address-cells = <2>; 17 #address-cells = <2>;
19 #size-cells = <2>; 18 #size-cells = <2>;
20 19
21 chosen { }; 20 chosen { };
22 21
23 memory@80000000 { 22 memory@80000000 {
24 device_type = "memory"; 23 device_type = "memory";
25 /* We expect the bootloader to 24 /* We expect the bootloader to fill in the reg */
26 reg = <0x0 0x80000000 0x0 0x0> 25 reg = <0x0 0x80000000 0x0 0x0>;
27 }; 26 };
28 27
29 reserved-memory { 28 reserved-memory {
30 #address-cells = <2>; 29 #address-cells = <2>;
31 #size-cells = <2>; 30 #size-cells = <2>;
32 ranges; 31 ranges;
33 32
34 hyp_mem: memory@85800000 { 33 hyp_mem: memory@85800000 {
35 reg = <0x0 0x85800000 34 reg = <0x0 0x85800000 0x0 0x600000>;
36 no-map; 35 no-map;
37 }; 36 };
38 37
39 xbl_mem: memory@85e00000 { 38 xbl_mem: memory@85e00000 {
40 reg = <0x0 0x85e00000 39 reg = <0x0 0x85e00000 0x0 0x100000>;
41 no-map; 40 no-map;
42 }; 41 };
43 42
44 smem_mem: smem-mem@86000000 { 43 smem_mem: smem-mem@86000000 {
45 reg = <0x0 0x86000000 44 reg = <0x0 0x86000000 0x0 0x200000>;
46 no-map; 45 no-map;
47 }; 46 };
48 47
49 tz_mem: memory@86200000 { 48 tz_mem: memory@86200000 {
50 reg = <0x0 0x86200000 49 reg = <0x0 0x86200000 0x0 0x2d00000>;
51 no-map; 50 no-map;
52 }; 51 };
53 52
54 rmtfs_mem: memory@88f00000 { 53 rmtfs_mem: memory@88f00000 {
55 compatible = "qcom,rmt 54 compatible = "qcom,rmtfs-mem";
56 reg = <0x0 0x88f00000 55 reg = <0x0 0x88f00000 0x0 0x200000>;
57 no-map; 56 no-map;
58 57
59 qcom,client-id = <1>; 58 qcom,client-id = <1>;
60 qcom,vmid = <QCOM_SCM_ !! 59 qcom,vmid = <15>;
61 }; 60 };
62 61
63 spss_mem: memory@8ab00000 { 62 spss_mem: memory@8ab00000 {
64 reg = <0x0 0x8ab00000 63 reg = <0x0 0x8ab00000 0x0 0x700000>;
65 no-map; 64 no-map;
66 }; 65 };
67 66
68 adsp_mem: memory@8b200000 { 67 adsp_mem: memory@8b200000 {
69 reg = <0x0 0x8b200000 68 reg = <0x0 0x8b200000 0x0 0x1a00000>;
70 no-map; 69 no-map;
71 }; 70 };
72 71
73 mpss_mem: memory@8cc00000 { 72 mpss_mem: memory@8cc00000 {
74 reg = <0x0 0x8cc00000 73 reg = <0x0 0x8cc00000 0x0 0x7000000>;
75 no-map; 74 no-map;
76 }; 75 };
77 76
78 venus_mem: memory@93c00000 { 77 venus_mem: memory@93c00000 {
79 reg = <0x0 0x93c00000 78 reg = <0x0 0x93c00000 0x0 0x500000>;
80 no-map; 79 no-map;
81 }; 80 };
82 81
83 mba_mem: memory@94100000 { 82 mba_mem: memory@94100000 {
84 reg = <0x0 0x94100000 83 reg = <0x0 0x94100000 0x0 0x200000>;
85 no-map; 84 no-map;
86 }; 85 };
87 86
88 slpi_mem: memory@94300000 { 87 slpi_mem: memory@94300000 {
89 reg = <0x0 0x94300000 88 reg = <0x0 0x94300000 0x0 0xf00000>;
90 no-map; 89 no-map;
91 }; 90 };
92 91
93 ipa_fw_mem: memory@95200000 { 92 ipa_fw_mem: memory@95200000 {
94 reg = <0x0 0x95200000 93 reg = <0x0 0x95200000 0x0 0x10000>;
95 no-map; 94 no-map;
96 }; 95 };
97 96
98 ipa_gsi_mem: memory@95210000 { 97 ipa_gsi_mem: memory@95210000 {
99 reg = <0x0 0x95210000 98 reg = <0x0 0x95210000 0x0 0x5000>;
100 no-map; 99 no-map;
101 }; 100 };
102 101
103 gpu_mem: memory@95600000 { 102 gpu_mem: memory@95600000 {
104 reg = <0x0 0x95600000 103 reg = <0x0 0x95600000 0x0 0x100000>;
105 no-map; 104 no-map;
106 }; 105 };
107 106
108 wlan_msa_mem: memory@95700000 107 wlan_msa_mem: memory@95700000 {
109 reg = <0x0 0x95700000 108 reg = <0x0 0x95700000 0x0 0x100000>;
110 no-map; 109 no-map;
111 }; 110 };
112 111
113 mdata_mem: mpss-metadata { 112 mdata_mem: mpss-metadata {
114 alloc-ranges = <0x0 0x 113 alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>;
115 size = <0x0 0x4000>; 114 size = <0x0 0x4000>;
116 no-map; 115 no-map;
117 }; 116 };
118 }; 117 };
119 118
120 clocks { 119 clocks {
121 xo: xo-board { 120 xo: xo-board {
122 compatible = "fixed-cl 121 compatible = "fixed-clock";
123 #clock-cells = <0>; 122 #clock-cells = <0>;
124 clock-frequency = <192 123 clock-frequency = <19200000>;
125 clock-output-names = " 124 clock-output-names = "xo_board";
126 }; 125 };
127 126
128 sleep_clk: sleep-clk { 127 sleep_clk: sleep-clk {
129 compatible = "fixed-cl 128 compatible = "fixed-clock";
130 #clock-cells = <0>; 129 #clock-cells = <0>;
131 clock-frequency = <327 130 clock-frequency = <32764>;
132 }; 131 };
133 }; 132 };
134 133
135 cpus { 134 cpus {
136 #address-cells = <2>; 135 #address-cells = <2>;
137 #size-cells = <0>; 136 #size-cells = <0>;
138 137
139 CPU0: cpu@0 { 138 CPU0: cpu@0 {
140 device_type = "cpu"; 139 device_type = "cpu";
141 compatible = "qcom,kry 140 compatible = "qcom,kryo280";
142 reg = <0x0 0x0>; 141 reg = <0x0 0x0>;
143 enable-method = "psci" 142 enable-method = "psci";
144 capacity-dmips-mhz = < 143 capacity-dmips-mhz = <1024>;
145 cpu-idle-states = <&LI 144 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
146 next-level-cache = <&L 145 next-level-cache = <&L2_0>;
147 L2_0: l2-cache { 146 L2_0: l2-cache {
148 compatible = " 147 compatible = "cache";
149 cache-level = 148 cache-level = <2>;
150 cache-unified; 149 cache-unified;
151 }; 150 };
152 }; 151 };
153 152
154 CPU1: cpu@1 { 153 CPU1: cpu@1 {
155 device_type = "cpu"; 154 device_type = "cpu";
156 compatible = "qcom,kry 155 compatible = "qcom,kryo280";
157 reg = <0x0 0x1>; 156 reg = <0x0 0x1>;
158 enable-method = "psci" 157 enable-method = "psci";
159 capacity-dmips-mhz = < 158 capacity-dmips-mhz = <1024>;
160 cpu-idle-states = <&LI 159 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
161 next-level-cache = <&L 160 next-level-cache = <&L2_0>;
162 }; 161 };
163 162
164 CPU2: cpu@2 { 163 CPU2: cpu@2 {
165 device_type = "cpu"; 164 device_type = "cpu";
166 compatible = "qcom,kry 165 compatible = "qcom,kryo280";
167 reg = <0x0 0x2>; 166 reg = <0x0 0x2>;
168 enable-method = "psci" 167 enable-method = "psci";
169 capacity-dmips-mhz = < 168 capacity-dmips-mhz = <1024>;
170 cpu-idle-states = <&LI 169 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
171 next-level-cache = <&L 170 next-level-cache = <&L2_0>;
172 }; 171 };
173 172
174 CPU3: cpu@3 { 173 CPU3: cpu@3 {
175 device_type = "cpu"; 174 device_type = "cpu";
176 compatible = "qcom,kry 175 compatible = "qcom,kryo280";
177 reg = <0x0 0x3>; 176 reg = <0x0 0x3>;
178 enable-method = "psci" 177 enable-method = "psci";
179 capacity-dmips-mhz = < 178 capacity-dmips-mhz = <1024>;
180 cpu-idle-states = <&LI 179 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
181 next-level-cache = <&L 180 next-level-cache = <&L2_0>;
182 }; 181 };
183 182
184 CPU4: cpu@100 { 183 CPU4: cpu@100 {
185 device_type = "cpu"; 184 device_type = "cpu";
186 compatible = "qcom,kry 185 compatible = "qcom,kryo280";
187 reg = <0x0 0x100>; 186 reg = <0x0 0x100>;
188 enable-method = "psci" 187 enable-method = "psci";
189 capacity-dmips-mhz = < 188 capacity-dmips-mhz = <1536>;
190 cpu-idle-states = <&BI 189 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
191 next-level-cache = <&L 190 next-level-cache = <&L2_1>;
192 L2_1: l2-cache { 191 L2_1: l2-cache {
193 compatible = " 192 compatible = "cache";
194 cache-level = 193 cache-level = <2>;
195 cache-unified; 194 cache-unified;
196 }; 195 };
197 }; 196 };
198 197
199 CPU5: cpu@101 { 198 CPU5: cpu@101 {
200 device_type = "cpu"; 199 device_type = "cpu";
201 compatible = "qcom,kry 200 compatible = "qcom,kryo280";
202 reg = <0x0 0x101>; 201 reg = <0x0 0x101>;
203 enable-method = "psci" 202 enable-method = "psci";
204 capacity-dmips-mhz = < 203 capacity-dmips-mhz = <1536>;
205 cpu-idle-states = <&BI 204 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
206 next-level-cache = <&L 205 next-level-cache = <&L2_1>;
207 }; 206 };
208 207
209 CPU6: cpu@102 { 208 CPU6: cpu@102 {
210 device_type = "cpu"; 209 device_type = "cpu";
211 compatible = "qcom,kry 210 compatible = "qcom,kryo280";
212 reg = <0x0 0x102>; 211 reg = <0x0 0x102>;
213 enable-method = "psci" 212 enable-method = "psci";
214 capacity-dmips-mhz = < 213 capacity-dmips-mhz = <1536>;
215 cpu-idle-states = <&BI 214 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
216 next-level-cache = <&L 215 next-level-cache = <&L2_1>;
217 }; 216 };
218 217
219 CPU7: cpu@103 { 218 CPU7: cpu@103 {
220 device_type = "cpu"; 219 device_type = "cpu";
221 compatible = "qcom,kry 220 compatible = "qcom,kryo280";
222 reg = <0x0 0x103>; 221 reg = <0x0 0x103>;
223 enable-method = "psci" 222 enable-method = "psci";
224 capacity-dmips-mhz = < 223 capacity-dmips-mhz = <1536>;
225 cpu-idle-states = <&BI 224 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
226 next-level-cache = <&L 225 next-level-cache = <&L2_1>;
227 }; 226 };
228 227
229 cpu-map { 228 cpu-map {
230 cluster0 { 229 cluster0 {
231 core0 { 230 core0 {
232 cpu = 231 cpu = <&CPU0>;
233 }; 232 };
234 233
235 core1 { 234 core1 {
236 cpu = 235 cpu = <&CPU1>;
237 }; 236 };
238 237
239 core2 { 238 core2 {
240 cpu = 239 cpu = <&CPU2>;
241 }; 240 };
242 241
243 core3 { 242 core3 {
244 cpu = 243 cpu = <&CPU3>;
245 }; 244 };
246 }; 245 };
247 246
248 cluster1 { 247 cluster1 {
249 core0 { 248 core0 {
250 cpu = 249 cpu = <&CPU4>;
251 }; 250 };
252 251
253 core1 { 252 core1 {
254 cpu = 253 cpu = <&CPU5>;
255 }; 254 };
256 255
257 core2 { 256 core2 {
258 cpu = 257 cpu = <&CPU6>;
259 }; 258 };
260 259
261 core3 { 260 core3 {
262 cpu = 261 cpu = <&CPU7>;
263 }; 262 };
264 }; 263 };
265 }; 264 };
266 265
267 idle-states { 266 idle-states {
268 entry-method = "psci"; 267 entry-method = "psci";
269 268
270 LITTLE_CPU_SLEEP_0: cp 269 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
271 compatible = " 270 compatible = "arm,idle-state";
272 idle-state-nam 271 idle-state-name = "little-retention";
273 /* CPU Retenti 272 /* CPU Retention (C2D), L2 Active */
274 arm,psci-suspe 273 arm,psci-suspend-param = <0x00000002>;
275 entry-latency- 274 entry-latency-us = <81>;
276 exit-latency-u 275 exit-latency-us = <86>;
277 min-residency- 276 min-residency-us = <504>;
278 }; 277 };
279 278
280 LITTLE_CPU_SLEEP_1: cp 279 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
281 compatible = " 280 compatible = "arm,idle-state";
282 idle-state-nam 281 idle-state-name = "little-power-collapse";
283 /* CPU + L2 Po 282 /* CPU + L2 Power Collapse (C3, D4) */
284 arm,psci-suspe 283 arm,psci-suspend-param = <0x40000003>;
285 entry-latency- 284 entry-latency-us = <814>;
286 exit-latency-u 285 exit-latency-us = <4562>;
287 min-residency- 286 min-residency-us = <9183>;
288 local-timer-st 287 local-timer-stop;
289 }; 288 };
290 289
291 BIG_CPU_SLEEP_0: cpu-s 290 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
292 compatible = " 291 compatible = "arm,idle-state";
293 idle-state-nam 292 idle-state-name = "big-retention";
294 /* CPU Retenti 293 /* CPU Retention (C2D), L2 Active */
295 arm,psci-suspe 294 arm,psci-suspend-param = <0x00000002>;
296 entry-latency- 295 entry-latency-us = <79>;
297 exit-latency-u 296 exit-latency-us = <82>;
298 min-residency- 297 min-residency-us = <1302>;
299 }; 298 };
300 299
301 BIG_CPU_SLEEP_1: cpu-s 300 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
302 compatible = " 301 compatible = "arm,idle-state";
303 idle-state-nam 302 idle-state-name = "big-power-collapse";
304 /* CPU + L2 Po 303 /* CPU + L2 Power Collapse (C3, D4) */
305 arm,psci-suspe 304 arm,psci-suspend-param = <0x40000003>;
306 entry-latency- 305 entry-latency-us = <724>;
307 exit-latency-u 306 exit-latency-us = <2027>;
308 min-residency- 307 min-residency-us = <9419>;
309 local-timer-st 308 local-timer-stop;
310 }; 309 };
311 }; 310 };
312 }; 311 };
313 312
314 firmware { 313 firmware {
315 scm { 314 scm {
316 compatible = "qcom,scm 315 compatible = "qcom,scm-msm8998", "qcom,scm";
317 }; 316 };
318 }; 317 };
319 318
320 dsi_opp_table: opp-table-dsi { 319 dsi_opp_table: opp-table-dsi {
321 compatible = "operating-points 320 compatible = "operating-points-v2";
322 321
323 opp-131250000 { 322 opp-131250000 {
324 opp-hz = /bits/ 64 <13 323 opp-hz = /bits/ 64 <131250000>;
325 required-opps = <&rpmp 324 required-opps = <&rpmpd_opp_low_svs>;
326 }; 325 };
327 326
328 opp-210000000 { 327 opp-210000000 {
329 opp-hz = /bits/ 64 <21 328 opp-hz = /bits/ 64 <210000000>;
330 required-opps = <&rpmp 329 required-opps = <&rpmpd_opp_svs>;
331 }; 330 };
332 331
333 opp-312500000 { 332 opp-312500000 {
334 opp-hz = /bits/ 64 <31 333 opp-hz = /bits/ 64 <312500000>;
335 required-opps = <&rpmp 334 required-opps = <&rpmpd_opp_nom>;
336 }; 335 };
337 }; 336 };
338 337
339 psci { 338 psci {
340 compatible = "arm,psci-1.0"; 339 compatible = "arm,psci-1.0";
341 method = "smc"; 340 method = "smc";
342 }; 341 };
343 342
344 rpm: remoteproc { 343 rpm: remoteproc {
345 compatible = "qcom,msm8998-rpm 344 compatible = "qcom,msm8998-rpm-proc", "qcom,rpm-proc";
346 345
347 glink-edge { 346 glink-edge {
348 compatible = "qcom,gli 347 compatible = "qcom,glink-rpm";
349 348
350 interrupts = <GIC_SPI 349 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
351 qcom,rpm-msg-ram = <&r 350 qcom,rpm-msg-ram = <&rpm_msg_ram>;
352 mboxes = <&apcs_glb 0> 351 mboxes = <&apcs_glb 0>;
353 352
354 rpm_requests: rpm-requ 353 rpm_requests: rpm-requests {
355 compatible = " !! 354 compatible = "qcom,rpm-msm8998";
356 qcom,glink-cha 355 qcom,glink-channels = "rpm_requests";
357 356
358 rpmcc: clock-c 357 rpmcc: clock-controller {
359 compat 358 compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc";
360 clocks 359 clocks = <&xo>;
361 clock- 360 clock-names = "xo";
362 #clock 361 #clock-cells = <1>;
363 }; 362 };
364 363
365 rpmpd: power-c 364 rpmpd: power-controller {
366 compat 365 compatible = "qcom,msm8998-rpmpd";
367 #power 366 #power-domain-cells = <1>;
368 operat 367 operating-points-v2 = <&rpmpd_opp_table>;
369 368
370 rpmpd_ 369 rpmpd_opp_table: opp-table {
371 370 compatible = "operating-points-v2";
372 371
373 372 rpmpd_opp_ret: opp1 {
374 373 opp-level = <RPM_SMD_LEVEL_RETENTION>;
375 374 };
376 375
377 376 rpmpd_opp_ret_plus: opp2 {
378 377 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
379 378 };
380 379
381 380 rpmpd_opp_min_svs: opp3 {
382 381 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
383 382 };
384 383
385 384 rpmpd_opp_low_svs: opp4 {
386 385 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
387 386 };
388 387
389 388 rpmpd_opp_svs: opp5 {
390 389 opp-level = <RPM_SMD_LEVEL_SVS>;
391 390 };
392 391
393 392 rpmpd_opp_svs_plus: opp6 {
394 393 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
395 394 };
396 395
397 396 rpmpd_opp_nom: opp7 {
398 397 opp-level = <RPM_SMD_LEVEL_NOM>;
399 398 };
400 399
401 400 rpmpd_opp_nom_plus: opp8 {
402 401 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
403 402 };
404 403
405 404 rpmpd_opp_turbo: opp9 {
406 405 opp-level = <RPM_SMD_LEVEL_TURBO>;
407 406 };
408 407
409 408 rpmpd_opp_turbo_plus: opp10 {
410 409 opp-level = <RPM_SMD_LEVEL_BINNING>;
411 410 };
412 }; 411 };
413 }; 412 };
414 }; 413 };
415 }; 414 };
416 }; 415 };
417 416
418 smem { 417 smem {
419 compatible = "qcom,smem"; 418 compatible = "qcom,smem";
420 memory-region = <&smem_mem>; 419 memory-region = <&smem_mem>;
421 hwlocks = <&tcsr_mutex 3>; 420 hwlocks = <&tcsr_mutex 3>;
422 }; 421 };
423 422
424 smp2p-lpass { 423 smp2p-lpass {
425 compatible = "qcom,smp2p"; 424 compatible = "qcom,smp2p";
426 qcom,smem = <443>, <429>; 425 qcom,smem = <443>, <429>;
427 426
428 interrupts = <GIC_SPI 158 IRQ_ 427 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
429 428
430 mboxes = <&apcs_glb 10>; 429 mboxes = <&apcs_glb 10>;
431 430
432 qcom,local-pid = <0>; 431 qcom,local-pid = <0>;
433 qcom,remote-pid = <2>; 432 qcom,remote-pid = <2>;
434 433
435 adsp_smp2p_out: master-kernel 434 adsp_smp2p_out: master-kernel {
436 qcom,entry-name = "mas 435 qcom,entry-name = "master-kernel";
437 #qcom,smem-state-cells 436 #qcom,smem-state-cells = <1>;
438 }; 437 };
439 438
440 adsp_smp2p_in: slave-kernel { 439 adsp_smp2p_in: slave-kernel {
441 qcom,entry-name = "sla 440 qcom,entry-name = "slave-kernel";
442 441
443 interrupt-controller; 442 interrupt-controller;
444 #interrupt-cells = <2> 443 #interrupt-cells = <2>;
445 }; 444 };
446 }; 445 };
447 446
448 smp2p-mpss { 447 smp2p-mpss {
449 compatible = "qcom,smp2p"; 448 compatible = "qcom,smp2p";
450 qcom,smem = <435>, <428>; 449 qcom,smem = <435>, <428>;
451 interrupts = <GIC_SPI 451 IRQ_ 450 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
452 mboxes = <&apcs_glb 14>; 451 mboxes = <&apcs_glb 14>;
453 qcom,local-pid = <0>; 452 qcom,local-pid = <0>;
454 qcom,remote-pid = <1>; 453 qcom,remote-pid = <1>;
455 454
456 modem_smp2p_out: master-kernel 455 modem_smp2p_out: master-kernel {
457 qcom,entry-name = "mas 456 qcom,entry-name = "master-kernel";
458 #qcom,smem-state-cells 457 #qcom,smem-state-cells = <1>;
459 }; 458 };
460 459
461 modem_smp2p_in: slave-kernel { 460 modem_smp2p_in: slave-kernel {
462 qcom,entry-name = "sla 461 qcom,entry-name = "slave-kernel";
463 interrupt-controller; 462 interrupt-controller;
464 #interrupt-cells = <2> 463 #interrupt-cells = <2>;
465 }; 464 };
466 }; 465 };
467 466
468 smp2p-slpi { 467 smp2p-slpi {
469 compatible = "qcom,smp2p"; 468 compatible = "qcom,smp2p";
470 qcom,smem = <481>, <430>; 469 qcom,smem = <481>, <430>;
471 interrupts = <GIC_SPI 178 IRQ_ 470 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
472 mboxes = <&apcs_glb 26>; 471 mboxes = <&apcs_glb 26>;
473 qcom,local-pid = <0>; 472 qcom,local-pid = <0>;
474 qcom,remote-pid = <3>; 473 qcom,remote-pid = <3>;
475 474
476 slpi_smp2p_out: master-kernel 475 slpi_smp2p_out: master-kernel {
477 qcom,entry-name = "mas 476 qcom,entry-name = "master-kernel";
478 #qcom,smem-state-cells 477 #qcom,smem-state-cells = <1>;
479 }; 478 };
480 479
481 slpi_smp2p_in: slave-kernel { 480 slpi_smp2p_in: slave-kernel {
482 qcom,entry-name = "sla 481 qcom,entry-name = "slave-kernel";
483 interrupt-controller; 482 interrupt-controller;
484 #interrupt-cells = <2> 483 #interrupt-cells = <2>;
485 }; 484 };
486 }; 485 };
487 486
488 thermal-zones { 487 thermal-zones {
489 cpu0-thermal { 488 cpu0-thermal {
490 polling-delay-passive 489 polling-delay-passive = <250>;
>> 490 polling-delay = <1000>;
491 491
492 thermal-sensors = <&ts 492 thermal-sensors = <&tsens0 1>;
493 493
494 trips { 494 trips {
495 cpu0_alert0: t 495 cpu0_alert0: trip-point0 {
496 temper 496 temperature = <75000>;
497 hyster 497 hysteresis = <2000>;
498 type = 498 type = "passive";
499 }; 499 };
500 500
501 cpu0_crit: cpu 501 cpu0_crit: cpu-crit {
502 temper 502 temperature = <110000>;
503 hyster 503 hysteresis = <2000>;
504 type = 504 type = "critical";
505 }; 505 };
506 }; 506 };
507 }; 507 };
508 508
509 cpu1-thermal { 509 cpu1-thermal {
510 polling-delay-passive 510 polling-delay-passive = <250>;
>> 511 polling-delay = <1000>;
511 512
512 thermal-sensors = <&ts 513 thermal-sensors = <&tsens0 2>;
513 514
514 trips { 515 trips {
515 cpu1_alert0: t 516 cpu1_alert0: trip-point0 {
516 temper 517 temperature = <75000>;
517 hyster 518 hysteresis = <2000>;
518 type = 519 type = "passive";
519 }; 520 };
520 521
521 cpu1_crit: cpu 522 cpu1_crit: cpu-crit {
522 temper 523 temperature = <110000>;
523 hyster 524 hysteresis = <2000>;
524 type = 525 type = "critical";
525 }; 526 };
526 }; 527 };
527 }; 528 };
528 529
529 cpu2-thermal { 530 cpu2-thermal {
530 polling-delay-passive 531 polling-delay-passive = <250>;
>> 532 polling-delay = <1000>;
531 533
532 thermal-sensors = <&ts 534 thermal-sensors = <&tsens0 3>;
533 535
534 trips { 536 trips {
535 cpu2_alert0: t 537 cpu2_alert0: trip-point0 {
536 temper 538 temperature = <75000>;
537 hyster 539 hysteresis = <2000>;
538 type = 540 type = "passive";
539 }; 541 };
540 542
541 cpu2_crit: cpu 543 cpu2_crit: cpu-crit {
542 temper 544 temperature = <110000>;
543 hyster 545 hysteresis = <2000>;
544 type = 546 type = "critical";
545 }; 547 };
546 }; 548 };
547 }; 549 };
548 550
549 cpu3-thermal { 551 cpu3-thermal {
550 polling-delay-passive 552 polling-delay-passive = <250>;
>> 553 polling-delay = <1000>;
551 554
552 thermal-sensors = <&ts 555 thermal-sensors = <&tsens0 4>;
553 556
554 trips { 557 trips {
555 cpu3_alert0: t 558 cpu3_alert0: trip-point0 {
556 temper 559 temperature = <75000>;
557 hyster 560 hysteresis = <2000>;
558 type = 561 type = "passive";
559 }; 562 };
560 563
561 cpu3_crit: cpu 564 cpu3_crit: cpu-crit {
562 temper 565 temperature = <110000>;
563 hyster 566 hysteresis = <2000>;
564 type = 567 type = "critical";
565 }; 568 };
566 }; 569 };
567 }; 570 };
568 571
569 cpu4-thermal { 572 cpu4-thermal {
570 polling-delay-passive 573 polling-delay-passive = <250>;
>> 574 polling-delay = <1000>;
571 575
572 thermal-sensors = <&ts 576 thermal-sensors = <&tsens0 7>;
573 577
574 trips { 578 trips {
575 cpu4_alert0: t 579 cpu4_alert0: trip-point0 {
576 temper 580 temperature = <75000>;
577 hyster 581 hysteresis = <2000>;
578 type = 582 type = "passive";
579 }; 583 };
580 584
581 cpu4_crit: cpu 585 cpu4_crit: cpu-crit {
582 temper 586 temperature = <110000>;
583 hyster 587 hysteresis = <2000>;
584 type = 588 type = "critical";
585 }; 589 };
586 }; 590 };
587 }; 591 };
588 592
589 cpu5-thermal { 593 cpu5-thermal {
590 polling-delay-passive 594 polling-delay-passive = <250>;
>> 595 polling-delay = <1000>;
591 596
592 thermal-sensors = <&ts 597 thermal-sensors = <&tsens0 8>;
593 598
594 trips { 599 trips {
595 cpu5_alert0: t 600 cpu5_alert0: trip-point0 {
596 temper 601 temperature = <75000>;
597 hyster 602 hysteresis = <2000>;
598 type = 603 type = "passive";
599 }; 604 };
600 605
601 cpu5_crit: cpu 606 cpu5_crit: cpu-crit {
602 temper 607 temperature = <110000>;
603 hyster 608 hysteresis = <2000>;
604 type = 609 type = "critical";
605 }; 610 };
606 }; 611 };
607 }; 612 };
608 613
609 cpu6-thermal { 614 cpu6-thermal {
610 polling-delay-passive 615 polling-delay-passive = <250>;
>> 616 polling-delay = <1000>;
611 617
612 thermal-sensors = <&ts 618 thermal-sensors = <&tsens0 9>;
613 619
614 trips { 620 trips {
615 cpu6_alert0: t 621 cpu6_alert0: trip-point0 {
616 temper 622 temperature = <75000>;
617 hyster 623 hysteresis = <2000>;
618 type = 624 type = "passive";
619 }; 625 };
620 626
621 cpu6_crit: cpu 627 cpu6_crit: cpu-crit {
622 temper 628 temperature = <110000>;
623 hyster 629 hysteresis = <2000>;
624 type = 630 type = "critical";
625 }; 631 };
626 }; 632 };
627 }; 633 };
628 634
629 cpu7-thermal { 635 cpu7-thermal {
630 polling-delay-passive 636 polling-delay-passive = <250>;
>> 637 polling-delay = <1000>;
631 638
632 thermal-sensors = <&ts 639 thermal-sensors = <&tsens0 10>;
633 640
634 trips { 641 trips {
635 cpu7_alert0: t 642 cpu7_alert0: trip-point0 {
636 temper 643 temperature = <75000>;
637 hyster 644 hysteresis = <2000>;
638 type = 645 type = "passive";
639 }; 646 };
640 647
641 cpu7_crit: cpu 648 cpu7_crit: cpu-crit {
642 temper 649 temperature = <110000>;
643 hyster 650 hysteresis = <2000>;
644 type = 651 type = "critical";
645 }; 652 };
646 }; 653 };
647 }; 654 };
648 655
649 gpu-bottom-thermal { 656 gpu-bottom-thermal {
650 polling-delay-passive 657 polling-delay-passive = <250>;
>> 658 polling-delay = <1000>;
651 659
652 thermal-sensors = <&ts 660 thermal-sensors = <&tsens0 12>;
653 661
654 trips { 662 trips {
655 gpu1_alert0: t 663 gpu1_alert0: trip-point0 {
656 temper 664 temperature = <90000>;
657 hyster 665 hysteresis = <2000>;
658 type = 666 type = "hot";
659 }; 667 };
660 }; 668 };
661 }; 669 };
662 670
663 gpu-top-thermal { 671 gpu-top-thermal {
664 polling-delay-passive 672 polling-delay-passive = <250>;
>> 673 polling-delay = <1000>;
665 674
666 thermal-sensors = <&ts 675 thermal-sensors = <&tsens0 13>;
667 676
668 trips { 677 trips {
669 gpu2_alert0: t 678 gpu2_alert0: trip-point0 {
670 temper 679 temperature = <90000>;
671 hyster 680 hysteresis = <2000>;
672 type = 681 type = "hot";
673 }; 682 };
674 }; 683 };
675 }; 684 };
676 685
677 clust0-mhm-thermal { 686 clust0-mhm-thermal {
678 polling-delay-passive 687 polling-delay-passive = <250>;
>> 688 polling-delay = <1000>;
679 689
680 thermal-sensors = <&ts 690 thermal-sensors = <&tsens0 5>;
681 691
682 trips { 692 trips {
683 cluster0_mhm_a 693 cluster0_mhm_alert0: trip-point0 {
684 temper 694 temperature = <90000>;
685 hyster 695 hysteresis = <2000>;
686 type = 696 type = "hot";
687 }; 697 };
688 }; 698 };
689 }; 699 };
690 700
691 clust1-mhm-thermal { 701 clust1-mhm-thermal {
692 polling-delay-passive 702 polling-delay-passive = <250>;
>> 703 polling-delay = <1000>;
693 704
694 thermal-sensors = <&ts 705 thermal-sensors = <&tsens0 6>;
695 706
696 trips { 707 trips {
697 cluster1_mhm_a 708 cluster1_mhm_alert0: trip-point0 {
698 temper 709 temperature = <90000>;
699 hyster 710 hysteresis = <2000>;
700 type = 711 type = "hot";
701 }; 712 };
702 }; 713 };
703 }; 714 };
704 715
705 cluster1-l2-thermal { 716 cluster1-l2-thermal {
706 polling-delay-passive 717 polling-delay-passive = <250>;
>> 718 polling-delay = <1000>;
707 719
708 thermal-sensors = <&ts 720 thermal-sensors = <&tsens0 11>;
709 721
710 trips { 722 trips {
711 cluster1_l2_al 723 cluster1_l2_alert0: trip-point0 {
712 temper 724 temperature = <90000>;
713 hyster 725 hysteresis = <2000>;
714 type = 726 type = "hot";
715 }; 727 };
716 }; 728 };
717 }; 729 };
718 730
719 modem-thermal { 731 modem-thermal {
720 polling-delay-passive 732 polling-delay-passive = <250>;
>> 733 polling-delay = <1000>;
721 734
722 thermal-sensors = <&ts 735 thermal-sensors = <&tsens1 1>;
723 736
724 trips { 737 trips {
725 modem_alert0: 738 modem_alert0: trip-point0 {
726 temper 739 temperature = <90000>;
727 hyster 740 hysteresis = <2000>;
728 type = 741 type = "hot";
729 }; 742 };
730 }; 743 };
731 }; 744 };
732 745
733 mem-thermal { 746 mem-thermal {
734 polling-delay-passive 747 polling-delay-passive = <250>;
>> 748 polling-delay = <1000>;
735 749
736 thermal-sensors = <&ts 750 thermal-sensors = <&tsens1 2>;
737 751
738 trips { 752 trips {
739 mem_alert0: tr 753 mem_alert0: trip-point0 {
740 temper 754 temperature = <90000>;
741 hyster 755 hysteresis = <2000>;
742 type = 756 type = "hot";
743 }; 757 };
744 }; 758 };
745 }; 759 };
746 760
747 wlan-thermal { 761 wlan-thermal {
748 polling-delay-passive 762 polling-delay-passive = <250>;
>> 763 polling-delay = <1000>;
749 764
750 thermal-sensors = <&ts 765 thermal-sensors = <&tsens1 3>;
751 766
752 trips { 767 trips {
753 wlan_alert0: t 768 wlan_alert0: trip-point0 {
754 temper 769 temperature = <90000>;
755 hyster 770 hysteresis = <2000>;
756 type = 771 type = "hot";
757 }; 772 };
758 }; 773 };
759 }; 774 };
760 775
761 q6-dsp-thermal { 776 q6-dsp-thermal {
762 polling-delay-passive 777 polling-delay-passive = <250>;
>> 778 polling-delay = <1000>;
763 779
764 thermal-sensors = <&ts 780 thermal-sensors = <&tsens1 4>;
765 781
766 trips { 782 trips {
767 q6_dsp_alert0: 783 q6_dsp_alert0: trip-point0 {
768 temper 784 temperature = <90000>;
769 hyster 785 hysteresis = <2000>;
770 type = 786 type = "hot";
771 }; 787 };
772 }; 788 };
773 }; 789 };
774 790
775 camera-thermal { 791 camera-thermal {
776 polling-delay-passive 792 polling-delay-passive = <250>;
>> 793 polling-delay = <1000>;
777 794
778 thermal-sensors = <&ts 795 thermal-sensors = <&tsens1 5>;
779 796
780 trips { 797 trips {
781 camera_alert0: 798 camera_alert0: trip-point0 {
782 temper 799 temperature = <90000>;
783 hyster 800 hysteresis = <2000>;
784 type = 801 type = "hot";
785 }; 802 };
786 }; 803 };
787 }; 804 };
788 805
789 multimedia-thermal { 806 multimedia-thermal {
790 polling-delay-passive 807 polling-delay-passive = <250>;
>> 808 polling-delay = <1000>;
791 809
792 thermal-sensors = <&ts 810 thermal-sensors = <&tsens1 6>;
793 811
794 trips { 812 trips {
795 multimedia_ale 813 multimedia_alert0: trip-point0 {
796 temper 814 temperature = <90000>;
797 hyster 815 hysteresis = <2000>;
798 type = 816 type = "hot";
799 }; 817 };
800 }; 818 };
801 }; 819 };
802 }; 820 };
803 821
804 timer { 822 timer {
805 compatible = "arm,armv8-timer" 823 compatible = "arm,armv8-timer";
806 interrupts = <GIC_PPI 1 IRQ_TY 824 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
807 <GIC_PPI 2 IRQ_TY 825 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
808 <GIC_PPI 3 IRQ_TY 826 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
809 <GIC_PPI 0 IRQ_TY 827 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
810 }; 828 };
811 829
812 soc: soc@0 { 830 soc: soc@0 {
813 #address-cells = <1>; 831 #address-cells = <1>;
814 #size-cells = <1>; 832 #size-cells = <1>;
815 ranges = <0 0 0 0xffffffff>; 833 ranges = <0 0 0 0xffffffff>;
816 compatible = "simple-bus"; 834 compatible = "simple-bus";
817 835
818 gcc: clock-controller@100000 { 836 gcc: clock-controller@100000 {
819 compatible = "qcom,gcc 837 compatible = "qcom,gcc-msm8998";
820 #clock-cells = <1>; 838 #clock-cells = <1>;
821 #reset-cells = <1>; 839 #reset-cells = <1>;
822 #power-domain-cells = 840 #power-domain-cells = <1>;
823 reg = <0x00100000 0xb0 841 reg = <0x00100000 0xb0000>;
824 842
825 clock-names = "xo", "s 843 clock-names = "xo", "sleep_clk";
826 clocks = <&rpmcc RPM_S 844 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>;
827 845
828 /* 846 /*
829 * The hypervisor typi 847 * The hypervisor typically configures the memory region where these clocks
830 * reside as read-only 848 * reside as read-only for the HLOS. If the HLOS tried to enable or disable
831 * these clocks on a d 849 * these clocks on a device with such configuration (e.g. because they are
832 * enabled but unused 850 * enabled but unused during boot-up), the device will most likely decide
833 * to reboot. 851 * to reboot.
834 * In light of that, w 852 * In light of that, we are conservative here and we list all such clocks
835 * as protected. The b 853 * as protected. The board dts (or a user-supplied dts) can override the
836 * list of protected c 854 * list of protected clocks if it differs from the norm, and it is in fact
837 * desired for the HLO 855 * desired for the HLOS to manage these clocks
838 */ 856 */
839 protected-clocks = <AG 857 protected-clocks = <AGGRE2_SNOC_NORTH_AXI>,
840 <SS 858 <SSC_XO>,
841 <SS 859 <SSC_CNOC_AHBS_CLK>;
842 }; 860 };
843 861
844 rpm_msg_ram: sram@778000 { 862 rpm_msg_ram: sram@778000 {
845 compatible = "qcom,rpm 863 compatible = "qcom,rpm-msg-ram";
846 reg = <0x00778000 0x70 864 reg = <0x00778000 0x7000>;
847 }; 865 };
848 866
849 qfprom: qfprom@784000 { 867 qfprom: qfprom@784000 {
850 compatible = "qcom,msm 868 compatible = "qcom,msm8998-qfprom", "qcom,qfprom";
851 reg = <0x00784000 0x62 869 reg = <0x00784000 0x621c>;
852 #address-cells = <1>; 870 #address-cells = <1>;
853 #size-cells = <1>; 871 #size-cells = <1>;
854 872
855 qusb2_hstx_trim: hstx- 873 qusb2_hstx_trim: hstx-trim@23a {
856 reg = <0x23a 0 874 reg = <0x23a 0x1>;
857 bits = <0 4>; 875 bits = <0 4>;
858 }; 876 };
859 }; 877 };
860 878
861 tsens0: thermal@10ab000 { 879 tsens0: thermal@10ab000 {
862 compatible = "qcom,msm 880 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
863 reg = <0x010ab000 0x10 881 reg = <0x010ab000 0x1000>, /* TM */
864 <0x010aa000 0x10 882 <0x010aa000 0x1000>; /* SROT */
865 #qcom,sensors = <14>; 883 #qcom,sensors = <14>;
866 interrupts = <GIC_SPI 884 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
867 <GIC_SPI 885 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
868 interrupt-names = "upl 886 interrupt-names = "uplow", "critical";
869 #thermal-sensor-cells 887 #thermal-sensor-cells = <1>;
870 }; 888 };
871 889
872 tsens1: thermal@10ae000 { 890 tsens1: thermal@10ae000 {
873 compatible = "qcom,msm 891 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
874 reg = <0x010ae000 0x10 892 reg = <0x010ae000 0x1000>, /* TM */
875 <0x010ad000 0x10 893 <0x010ad000 0x1000>; /* SROT */
876 #qcom,sensors = <8>; 894 #qcom,sensors = <8>;
877 interrupts = <GIC_SPI 895 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
878 <GIC_SPI 896 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
879 interrupt-names = "upl 897 interrupt-names = "uplow", "critical";
880 #thermal-sensor-cells 898 #thermal-sensor-cells = <1>;
881 }; 899 };
882 900
883 anoc1_smmu: iommu@1680000 { 901 anoc1_smmu: iommu@1680000 {
884 compatible = "qcom,msm 902 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
885 reg = <0x01680000 0x10 903 reg = <0x01680000 0x10000>;
886 #iommu-cells = <1>; 904 #iommu-cells = <1>;
887 905
888 #global-interrupts = < 906 #global-interrupts = <0>;
889 interrupts = 907 interrupts =
890 <GIC_SPI 364 I 908 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
891 <GIC_SPI 365 I 909 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
892 <GIC_SPI 366 I 910 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
893 <GIC_SPI 367 I 911 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
894 <GIC_SPI 368 I 912 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
895 <GIC_SPI 369 I 913 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>;
896 }; 914 };
897 915
898 anoc2_smmu: iommu@16c0000 { 916 anoc2_smmu: iommu@16c0000 {
899 compatible = "qcom,msm 917 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
900 reg = <0x016c0000 0x40 918 reg = <0x016c0000 0x40000>;
901 #iommu-cells = <1>; 919 #iommu-cells = <1>;
902 920
903 #global-interrupts = < 921 #global-interrupts = <0>;
904 interrupts = 922 interrupts =
905 <GIC_SPI 373 I 923 <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>,
906 <GIC_SPI 374 I 924 <GIC_SPI 374 IRQ_TYPE_EDGE_RISING>,
907 <GIC_SPI 375 I 925 <GIC_SPI 375 IRQ_TYPE_EDGE_RISING>,
908 <GIC_SPI 376 I 926 <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>,
909 <GIC_SPI 377 I 927 <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>,
910 <GIC_SPI 378 I 928 <GIC_SPI 378 IRQ_TYPE_EDGE_RISING>,
911 <GIC_SPI 462 I 929 <GIC_SPI 462 IRQ_TYPE_EDGE_RISING>,
912 <GIC_SPI 463 I 930 <GIC_SPI 463 IRQ_TYPE_EDGE_RISING>,
913 <GIC_SPI 464 I 931 <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
914 <GIC_SPI 465 I 932 <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>;
915 }; 933 };
916 934
917 pcie0: pcie@1c00000 { !! 935 pcie0: pci@1c00000 {
918 compatible = "qcom,pci 936 compatible = "qcom,pcie-msm8998", "qcom,pcie-msm8996";
919 reg = <0x01c00000 0x20 937 reg = <0x01c00000 0x2000>,
920 <0x1b000000 0xf1 938 <0x1b000000 0xf1d>,
921 <0x1b000f20 0xa8 939 <0x1b000f20 0xa8>,
922 <0x1b100000 0x10 940 <0x1b100000 0x100000>;
923 reg-names = "parf", "d 941 reg-names = "parf", "dbi", "elbi", "config";
924 device_type = "pci"; 942 device_type = "pci";
925 linux,pci-domain = <0> 943 linux,pci-domain = <0>;
926 bus-range = <0x00 0xff 944 bus-range = <0x00 0xff>;
927 #address-cells = <3>; 945 #address-cells = <3>;
928 #size-cells = <2>; 946 #size-cells = <2>;
929 num-lanes = <1>; 947 num-lanes = <1>;
930 phys = <&pcie_phy>; !! 948 phys = <&pciephy>;
931 phy-names = "pciephy"; 949 phy-names = "pciephy";
932 status = "disabled"; 950 status = "disabled";
933 951
934 ranges = <0x01000000 0 952 ranges = <0x01000000 0x0 0x00000000 0x1b200000 0x0 0x100000>,
935 <0x02000000 0 953 <0x02000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>;
936 954
937 #interrupt-cells = <1> 955 #interrupt-cells = <1>;
938 interrupts = <GIC_SPI 956 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
939 interrupt-names = "msi 957 interrupt-names = "msi";
940 interrupt-map-mask = < 958 interrupt-map-mask = <0 0 0 0x7>;
941 interrupt-map = <0 0 0 959 interrupt-map = <0 0 0 1 &intc 0 0 135 IRQ_TYPE_LEVEL_HIGH>,
942 <0 0 0 960 <0 0 0 2 &intc 0 0 136 IRQ_TYPE_LEVEL_HIGH>,
943 <0 0 0 961 <0 0 0 3 &intc 0 0 138 IRQ_TYPE_LEVEL_HIGH>,
944 <0 0 0 962 <0 0 0 4 &intc 0 0 139 IRQ_TYPE_LEVEL_HIGH>;
945 963
946 clocks = <&gcc GCC_PCI 964 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
947 <&gcc GCC_PCI 965 <&gcc GCC_PCIE_0_AUX_CLK>,
948 <&gcc GCC_PCI 966 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
949 <&gcc GCC_PCI 967 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
950 <&gcc GCC_PCI 968 <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
951 clock-names = "pipe", 969 clock-names = "pipe", "aux", "cfg", "bus_master", "bus_slave";
952 970
953 power-domains = <&gcc 971 power-domains = <&gcc PCIE_0_GDSC>;
954 iommu-map = <0x100 &an 972 iommu-map = <0x100 &anoc1_smmu 0x1480 1>;
955 perst-gpios = <&tlmm 3 973 perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
956 <<
957 pcie@0 { <<
958 device_type = <<
959 reg = <0x0 0x0 <<
960 bus-range = <0 <<
961 <<
962 #address-cells <<
963 #size-cells = <<
964 ranges; <<
965 }; <<
966 }; 974 };
967 975
968 pcie_phy: phy@1c06000 { 976 pcie_phy: phy@1c06000 {
969 compatible = "qcom,msm 977 compatible = "qcom,msm8998-qmp-pcie-phy";
970 reg = <0x01c06000 0x10 !! 978 reg = <0x01c06000 0x18c>;
>> 979 #address-cells = <1>;
>> 980 #size-cells = <1>;
971 status = "disabled"; 981 status = "disabled";
>> 982 ranges;
972 983
973 clocks = <&gcc GCC_PCI 984 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
974 <&gcc GCC_PCI 985 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
975 <&gcc GCC_PCI !! 986 <&gcc GCC_PCIE_CLKREF_CLK>;
976 <&gcc GCC_PCI !! 987 clock-names = "aux", "cfg_ahb", "ref";
977 clock-names = "aux", <<
978 "cfg_ahb <<
979 "ref", <<
980 "pipe"; <<
981 <<
982 clock-output-names = " <<
983 #clock-cells = <0>; <<
984 <<
985 #phy-cells = <0>; <<
986 988
987 resets = <&gcc GCC_PCI 989 resets = <&gcc GCC_PCIE_0_PHY_BCR>, <&gcc GCC_PCIE_PHY_BCR>;
988 reset-names = "phy", " 990 reset-names = "phy", "common";
989 991
990 vdda-phy-supply = <&vr 992 vdda-phy-supply = <&vreg_l1a_0p875>;
991 vdda-pll-supply = <&vr 993 vdda-pll-supply = <&vreg_l2a_1p2>;
>> 994
>> 995 pciephy: phy@1c06800 {
>> 996 reg = <0x01c06200 0x128>, <0x01c06400 0x1fc>, <0x01c06800 0x20c>;
>> 997 #phy-cells = <0>;
>> 998
>> 999 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
>> 1000 clock-names = "pipe0";
>> 1001 clock-output-names = "pcie_0_pipe_clk_src";
>> 1002 #clock-cells = <0>;
>> 1003 };
992 }; 1004 };
993 1005
994 ufshc: ufshc@1da4000 { 1006 ufshc: ufshc@1da4000 {
995 compatible = "qcom,msm 1007 compatible = "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
996 reg = <0x01da4000 0x25 1008 reg = <0x01da4000 0x2500>;
997 interrupts = <GIC_SPI 1009 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
998 phys = <&ufsphy>; !! 1010 phys = <&ufsphy_lanes>;
999 phy-names = "ufsphy"; 1011 phy-names = "ufsphy";
1000 lanes-per-direction = 1012 lanes-per-direction = <2>;
1001 power-domains = <&gcc 1013 power-domains = <&gcc UFS_GDSC>;
1002 status = "disabled"; 1014 status = "disabled";
1003 #reset-cells = <1>; 1015 #reset-cells = <1>;
1004 1016
1005 clock-names = 1017 clock-names =
1006 "core_clk", 1018 "core_clk",
1007 "bus_aggr_clk 1019 "bus_aggr_clk",
1008 "iface_clk", 1020 "iface_clk",
1009 "core_clk_uni 1021 "core_clk_unipro",
1010 "ref_clk", 1022 "ref_clk",
1011 "tx_lane0_syn 1023 "tx_lane0_sync_clk",
1012 "rx_lane0_syn 1024 "rx_lane0_sync_clk",
1013 "rx_lane1_syn 1025 "rx_lane1_sync_clk";
1014 clocks = 1026 clocks =
1015 <&gcc GCC_UFS 1027 <&gcc GCC_UFS_AXI_CLK>,
1016 <&gcc GCC_AGG 1028 <&gcc GCC_AGGRE1_UFS_AXI_CLK>,
1017 <&gcc GCC_UFS 1029 <&gcc GCC_UFS_AHB_CLK>,
1018 <&gcc GCC_UFS 1030 <&gcc GCC_UFS_UNIPRO_CORE_CLK>,
1019 <&rpmcc RPM_S 1031 <&rpmcc RPM_SMD_LN_BB_CLK1>,
1020 <&gcc GCC_UFS 1032 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
1021 <&gcc GCC_UFS 1033 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>,
1022 <&gcc GCC_UFS 1034 <&gcc GCC_UFS_RX_SYMBOL_1_CLK>;
1023 freq-table-hz = 1035 freq-table-hz =
1024 <50000000 200 1036 <50000000 200000000>,
1025 <0 0>, 1037 <0 0>,
1026 <0 0>, 1038 <0 0>,
1027 <37500000 150 1039 <37500000 150000000>,
1028 <0 0>, 1040 <0 0>,
1029 <0 0>, 1041 <0 0>,
1030 <0 0>, 1042 <0 0>,
1031 <0 0>; 1043 <0 0>;
1032 1044
1033 resets = <&gcc GCC_UF 1045 resets = <&gcc GCC_UFS_BCR>;
1034 reset-names = "rst"; 1046 reset-names = "rst";
1035 }; 1047 };
1036 1048
1037 ufsphy: phy@1da7000 { 1049 ufsphy: phy@1da7000 {
1038 compatible = "qcom,ms 1050 compatible = "qcom,msm8998-qmp-ufs-phy";
1039 reg = <0x01da7000 0x1 !! 1051 reg = <0x01da7000 0x18c>;
>> 1052 #address-cells = <1>;
>> 1053 #size-cells = <1>;
>> 1054 status = "disabled";
>> 1055 ranges;
1040 1056
1041 clocks = <&rpmcc RPM_ !! 1057 clock-names =
1042 <&gcc GCC_UF !! 1058 "ref",
1043 <&gcc GCC_UF !! 1059 "ref_aux";
1044 clock-names = "ref", !! 1060 clocks =
1045 "ref_au !! 1061 <&gcc GCC_UFS_CLKREF_CLK>,
1046 "qref"; !! 1062 <&gcc GCC_UFS_PHY_AUX_CLK>;
1047 1063
1048 reset-names = "ufsphy 1064 reset-names = "ufsphy";
1049 resets = <&ufshc 0>; 1065 resets = <&ufshc 0>;
1050 1066
1051 #phy-cells = <0>; !! 1067 ufsphy_lanes: phy@1da7400 {
1052 status = "disabled"; !! 1068 reg = <0x01da7400 0x128>,
>> 1069 <0x01da7600 0x1fc>,
>> 1070 <0x01da7c00 0x1dc>,
>> 1071 <0x01da7800 0x128>,
>> 1072 <0x01da7a00 0x1fc>;
>> 1073 #phy-cells = <0>;
>> 1074 };
1053 }; 1075 };
1054 1076
1055 tcsr_mutex: hwlock@1f40000 { 1077 tcsr_mutex: hwlock@1f40000 {
1056 compatible = "qcom,tc 1078 compatible = "qcom,tcsr-mutex";
1057 reg = <0x01f40000 0x2 1079 reg = <0x01f40000 0x20000>;
1058 #hwlock-cells = <1>; 1080 #hwlock-cells = <1>;
1059 }; 1081 };
1060 1082
1061 tcsr_regs_1: syscon@1f60000 { 1083 tcsr_regs_1: syscon@1f60000 {
1062 compatible = "qcom,ms 1084 compatible = "qcom,msm8998-tcsr", "syscon";
1063 reg = <0x01f60000 0x2 1085 reg = <0x01f60000 0x20000>;
1064 }; 1086 };
1065 1087
1066 tcsr_regs_2: syscon@1fc0000 { <<
1067 compatible = "qcom,ms <<
1068 reg = <0x01fc0000 0x2 <<
1069 }; <<
1070 <<
1071 tlmm: pinctrl@3400000 { 1088 tlmm: pinctrl@3400000 {
1072 compatible = "qcom,ms 1089 compatible = "qcom,msm8998-pinctrl";
1073 reg = <0x03400000 0xc 1090 reg = <0x03400000 0xc00000>;
1074 interrupts = <GIC_SPI 1091 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1075 gpio-ranges = <&tlmm 1092 gpio-ranges = <&tlmm 0 0 150>;
1076 gpio-controller; 1093 gpio-controller;
1077 #gpio-cells = <2>; 1094 #gpio-cells = <2>;
1078 interrupt-controller; 1095 interrupt-controller;
1079 #interrupt-cells = <2 1096 #interrupt-cells = <2>;
1080 1097
1081 sdc2_on: sdc2-on-stat 1098 sdc2_on: sdc2-on-state {
1082 clk-pins { 1099 clk-pins {
1083 pins 1100 pins = "sdc2_clk";
1084 drive 1101 drive-strength = <16>;
1085 bias- 1102 bias-disable;
1086 }; 1103 };
1087 1104
1088 cmd-pins { 1105 cmd-pins {
1089 pins 1106 pins = "sdc2_cmd";
1090 drive 1107 drive-strength = <10>;
1091 bias- 1108 bias-pull-up;
1092 }; 1109 };
1093 1110
1094 data-pins { 1111 data-pins {
1095 pins 1112 pins = "sdc2_data";
1096 drive 1113 drive-strength = <10>;
1097 bias- 1114 bias-pull-up;
1098 }; 1115 };
1099 }; 1116 };
1100 1117
1101 sdc2_off: sdc2-off-st 1118 sdc2_off: sdc2-off-state {
1102 clk-pins { 1119 clk-pins {
1103 pins 1120 pins = "sdc2_clk";
1104 drive 1121 drive-strength = <2>;
1105 bias- 1122 bias-disable;
1106 }; 1123 };
1107 1124
1108 cmd-pins { 1125 cmd-pins {
1109 pins 1126 pins = "sdc2_cmd";
1110 drive 1127 drive-strength = <2>;
1111 bias- 1128 bias-pull-up;
1112 }; 1129 };
1113 1130
1114 data-pins { 1131 data-pins {
1115 pins 1132 pins = "sdc2_data";
1116 drive 1133 drive-strength = <2>;
1117 bias- 1134 bias-pull-up;
1118 }; 1135 };
1119 }; 1136 };
1120 1137
1121 sdc2_cd: sdc2-cd-stat 1138 sdc2_cd: sdc2-cd-state {
1122 pins = "gpio9 1139 pins = "gpio95";
1123 function = "g 1140 function = "gpio";
1124 bias-pull-up; 1141 bias-pull-up;
1125 drive-strengt 1142 drive-strength = <2>;
1126 }; 1143 };
1127 1144
1128 blsp1_uart3_on: blsp1 1145 blsp1_uart3_on: blsp1-uart3-on-state {
1129 tx-pins { 1146 tx-pins {
1130 pins 1147 pins = "gpio45";
1131 funct 1148 function = "blsp_uart3_a";
1132 drive 1149 drive-strength = <2>;
1133 bias- 1150 bias-disable;
1134 }; 1151 };
1135 1152
1136 rx-pins { 1153 rx-pins {
1137 pins 1154 pins = "gpio46";
1138 funct 1155 function = "blsp_uart3_a";
1139 drive 1156 drive-strength = <2>;
1140 bias- 1157 bias-disable;
1141 }; 1158 };
1142 1159
1143 cts-pins { 1160 cts-pins {
1144 pins 1161 pins = "gpio47";
1145 funct 1162 function = "blsp_uart3_a";
1146 drive 1163 drive-strength = <2>;
1147 bias- 1164 bias-disable;
1148 }; 1165 };
1149 1166
1150 rfr-pins { 1167 rfr-pins {
1151 pins 1168 pins = "gpio48";
1152 funct 1169 function = "blsp_uart3_a";
1153 drive 1170 drive-strength = <2>;
1154 bias- 1171 bias-disable;
1155 }; 1172 };
1156 }; 1173 };
1157 1174
1158 blsp1_i2c1_default: b 1175 blsp1_i2c1_default: blsp1-i2c1-default-state {
1159 pins = "gpio2 1176 pins = "gpio2", "gpio3";
1160 function = "b 1177 function = "blsp_i2c1";
1161 drive-strengt 1178 drive-strength = <2>;
1162 bias-disable; 1179 bias-disable;
1163 }; 1180 };
1164 1181
1165 blsp1_i2c1_sleep: bls 1182 blsp1_i2c1_sleep: blsp1-i2c1-sleep-state-state {
1166 pins = "gpio2 1183 pins = "gpio2", "gpio3";
1167 function = "b 1184 function = "blsp_i2c1";
1168 drive-strengt 1185 drive-strength = <2>;
1169 bias-pull-up; 1186 bias-pull-up;
1170 }; 1187 };
1171 1188
1172 blsp1_i2c2_default: b 1189 blsp1_i2c2_default: blsp1-i2c2-default-state {
1173 pins = "gpio3 1190 pins = "gpio32", "gpio33";
1174 function = "b 1191 function = "blsp_i2c2";
1175 drive-strengt 1192 drive-strength = <2>;
1176 bias-disable; 1193 bias-disable;
1177 }; 1194 };
1178 1195
1179 blsp1_i2c2_sleep: bls 1196 blsp1_i2c2_sleep: blsp1-i2c2-sleep-state-state {
1180 pins = "gpio3 1197 pins = "gpio32", "gpio33";
1181 function = "b 1198 function = "blsp_i2c2";
1182 drive-strengt 1199 drive-strength = <2>;
1183 bias-pull-up; 1200 bias-pull-up;
1184 }; 1201 };
1185 1202
1186 blsp1_i2c3_default: b 1203 blsp1_i2c3_default: blsp1-i2c3-default-state {
1187 pins = "gpio4 1204 pins = "gpio47", "gpio48";
1188 function = "b 1205 function = "blsp_i2c3";
1189 drive-strengt 1206 drive-strength = <2>;
1190 bias-disable; 1207 bias-disable;
1191 }; 1208 };
1192 1209
1193 blsp1_i2c3_sleep: bls 1210 blsp1_i2c3_sleep: blsp1-i2c3-sleep-state {
1194 pins = "gpio4 1211 pins = "gpio47", "gpio48";
1195 function = "b 1212 function = "blsp_i2c3";
1196 drive-strengt 1213 drive-strength = <2>;
1197 bias-pull-up; 1214 bias-pull-up;
1198 }; 1215 };
1199 1216
1200 blsp1_i2c4_default: b 1217 blsp1_i2c4_default: blsp1-i2c4-default-state {
1201 pins = "gpio1 1218 pins = "gpio10", "gpio11";
1202 function = "b 1219 function = "blsp_i2c4";
1203 drive-strengt 1220 drive-strength = <2>;
1204 bias-disable; 1221 bias-disable;
1205 }; 1222 };
1206 1223
1207 blsp1_i2c4_sleep: bls 1224 blsp1_i2c4_sleep: blsp1-i2c4-sleep-state {
1208 pins = "gpio1 1225 pins = "gpio10", "gpio11";
1209 function = "b 1226 function = "blsp_i2c4";
1210 drive-strengt 1227 drive-strength = <2>;
1211 bias-pull-up; 1228 bias-pull-up;
1212 }; 1229 };
1213 1230
1214 blsp1_i2c5_default: b 1231 blsp1_i2c5_default: blsp1-i2c5-default-state {
1215 pins = "gpio8 1232 pins = "gpio87", "gpio88";
1216 function = "b 1233 function = "blsp_i2c5";
1217 drive-strengt 1234 drive-strength = <2>;
1218 bias-disable; 1235 bias-disable;
1219 }; 1236 };
1220 1237
1221 blsp1_i2c5_sleep: bls 1238 blsp1_i2c5_sleep: blsp1-i2c5-sleep-state {
1222 pins = "gpio8 1239 pins = "gpio87", "gpio88";
1223 function = "b 1240 function = "blsp_i2c5";
1224 drive-strengt 1241 drive-strength = <2>;
1225 bias-pull-up; 1242 bias-pull-up;
1226 }; 1243 };
1227 1244
1228 blsp1_i2c6_default: b 1245 blsp1_i2c6_default: blsp1-i2c6-default-state {
1229 pins = "gpio4 1246 pins = "gpio43", "gpio44";
1230 function = "b 1247 function = "blsp_i2c6";
1231 drive-strengt 1248 drive-strength = <2>;
1232 bias-disable; 1249 bias-disable;
1233 }; 1250 };
1234 1251
1235 blsp1_i2c6_sleep: bls 1252 blsp1_i2c6_sleep: blsp1-i2c6-sleep-state {
1236 pins = "gpio4 1253 pins = "gpio43", "gpio44";
1237 function = "b 1254 function = "blsp_i2c6";
1238 drive-strengt 1255 drive-strength = <2>;
1239 bias-pull-up; 1256 bias-pull-up;
1240 }; 1257 };
1241 1258
1242 blsp1_spi_b_default: 1259 blsp1_spi_b_default: blsp1-spi-b-default-state {
1243 pins = "gpio2 1260 pins = "gpio23", "gpio28";
1244 function = "b 1261 function = "blsp1_spi_b";
1245 drive-strengt 1262 drive-strength = <6>;
1246 bias-disable; 1263 bias-disable;
1247 }; 1264 };
1248 1265
1249 blsp1_spi1_default: b 1266 blsp1_spi1_default: blsp1-spi1-default-state {
1250 pins = "gpio0 1267 pins = "gpio0", "gpio1", "gpio2", "gpio3";
1251 function = "b 1268 function = "blsp_spi1";
1252 drive-strengt 1269 drive-strength = <6>;
1253 bias-disable; 1270 bias-disable;
1254 }; 1271 };
1255 1272
1256 blsp1_spi2_default: b 1273 blsp1_spi2_default: blsp1-spi2-default-state {
1257 pins = "gpio3 1274 pins = "gpio31", "gpio34", "gpio32", "gpio33";
1258 function = "b 1275 function = "blsp_spi2";
1259 drive-strengt 1276 drive-strength = <6>;
1260 bias-disable; 1277 bias-disable;
1261 }; 1278 };
1262 1279
1263 blsp1_spi3_default: b 1280 blsp1_spi3_default: blsp1-spi3-default-state {
1264 pins = "gpio4 1281 pins = "gpio45", "gpio46", "gpio47", "gpio48";
1265 function = "b 1282 function = "blsp_spi2";
1266 drive-strengt 1283 drive-strength = <6>;
1267 bias-disable; 1284 bias-disable;
1268 }; 1285 };
1269 1286
1270 blsp1_spi4_default: b 1287 blsp1_spi4_default: blsp1-spi4-default-state {
1271 pins = "gpio8 1288 pins = "gpio8", "gpio9", "gpio10", "gpio11";
1272 function = "b 1289 function = "blsp_spi4";
1273 drive-strengt 1290 drive-strength = <6>;
1274 bias-disable; 1291 bias-disable;
1275 }; 1292 };
1276 1293
1277 blsp1_spi5_default: b 1294 blsp1_spi5_default: blsp1-spi5-default-state {
1278 pins = "gpio8 1295 pins = "gpio85", "gpio86", "gpio87", "gpio88";
1279 function = "b 1296 function = "blsp_spi5";
1280 drive-strengt 1297 drive-strength = <6>;
1281 bias-disable; 1298 bias-disable;
1282 }; 1299 };
1283 1300
1284 blsp1_spi6_default: b 1301 blsp1_spi6_default: blsp1-spi6-default-state {
1285 pins = "gpio4 1302 pins = "gpio41", "gpio42", "gpio43", "gpio44";
1286 function = "b 1303 function = "blsp_spi6";
1287 drive-strengt 1304 drive-strength = <6>;
1288 bias-disable; 1305 bias-disable;
1289 }; 1306 };
1290 1307
1291 1308
1292 /* 6 interfaces per Q 1309 /* 6 interfaces per QUP, BLSP2 indexes are numbered (n)+6 */
1293 blsp2_i2c1_default: b 1310 blsp2_i2c1_default: blsp2-i2c1-default-state {
1294 pins = "gpio5 1311 pins = "gpio55", "gpio56";
1295 function = "b 1312 function = "blsp_i2c7";
1296 drive-strengt 1313 drive-strength = <2>;
1297 bias-disable; 1314 bias-disable;
1298 }; 1315 };
1299 1316
1300 blsp2_i2c1_sleep: bls 1317 blsp2_i2c1_sleep: blsp2-i2c1-sleep-state {
1301 pins = "gpio5 1318 pins = "gpio55", "gpio56";
1302 function = "b 1319 function = "blsp_i2c7";
1303 drive-strengt 1320 drive-strength = <2>;
1304 bias-pull-up; 1321 bias-pull-up;
1305 }; 1322 };
1306 1323
1307 blsp2_i2c2_default: b 1324 blsp2_i2c2_default: blsp2-i2c2-default-state {
1308 pins = "gpio6 1325 pins = "gpio6", "gpio7";
1309 function = "b 1326 function = "blsp_i2c8";
1310 drive-strengt 1327 drive-strength = <2>;
1311 bias-disable; 1328 bias-disable;
1312 }; 1329 };
1313 1330
1314 blsp2_i2c2_sleep: bls 1331 blsp2_i2c2_sleep: blsp2-i2c2-sleep-state {
1315 pins = "gpio6 1332 pins = "gpio6", "gpio7";
1316 function = "b 1333 function = "blsp_i2c8";
1317 drive-strengt 1334 drive-strength = <2>;
1318 bias-pull-up; 1335 bias-pull-up;
1319 }; 1336 };
1320 1337
1321 blsp2_i2c3_default: b 1338 blsp2_i2c3_default: blsp2-i2c3-default-state {
1322 pins = "gpio5 1339 pins = "gpio51", "gpio52";
1323 function = "b 1340 function = "blsp_i2c9";
1324 drive-strengt 1341 drive-strength = <2>;
1325 bias-disable; 1342 bias-disable;
1326 }; 1343 };
1327 1344
1328 blsp2_i2c3_sleep: bls 1345 blsp2_i2c3_sleep: blsp2-i2c3-sleep-state {
1329 pins = "gpio5 1346 pins = "gpio51", "gpio52";
1330 function = "b 1347 function = "blsp_i2c9";
1331 drive-strengt 1348 drive-strength = <2>;
1332 bias-pull-up; 1349 bias-pull-up;
1333 }; 1350 };
1334 1351
1335 blsp2_i2c4_default: b 1352 blsp2_i2c4_default: blsp2-i2c4-default-state {
1336 pins = "gpio6 1353 pins = "gpio67", "gpio68";
1337 function = "b 1354 function = "blsp_i2c10";
1338 drive-strengt 1355 drive-strength = <2>;
1339 bias-disable; 1356 bias-disable;
1340 }; 1357 };
1341 1358
1342 blsp2_i2c4_sleep: bls 1359 blsp2_i2c4_sleep: blsp2-i2c4-sleep-state {
1343 pins = "gpio6 1360 pins = "gpio67", "gpio68";
1344 function = "b 1361 function = "blsp_i2c10";
1345 drive-strengt 1362 drive-strength = <2>;
1346 bias-pull-up; 1363 bias-pull-up;
1347 }; 1364 };
1348 1365
1349 blsp2_i2c5_default: b 1366 blsp2_i2c5_default: blsp2-i2c5-default-state {
1350 pins = "gpio6 1367 pins = "gpio60", "gpio61";
1351 function = "b 1368 function = "blsp_i2c11";
1352 drive-strengt 1369 drive-strength = <2>;
1353 bias-disable; 1370 bias-disable;
1354 }; 1371 };
1355 1372
1356 blsp2_i2c5_sleep: bls 1373 blsp2_i2c5_sleep: blsp2-i2c5-sleep-state {
1357 pins = "gpio6 1374 pins = "gpio60", "gpio61";
1358 function = "b 1375 function = "blsp_i2c11";
1359 drive-strengt 1376 drive-strength = <2>;
1360 bias-pull-up; 1377 bias-pull-up;
1361 }; 1378 };
1362 1379
1363 blsp2_i2c6_default: b 1380 blsp2_i2c6_default: blsp2-i2c6-default-state {
1364 pins = "gpio8 1381 pins = "gpio83", "gpio84";
1365 function = "b 1382 function = "blsp_i2c12";
1366 drive-strengt 1383 drive-strength = <2>;
1367 bias-disable; 1384 bias-disable;
1368 }; 1385 };
1369 1386
1370 blsp2_i2c6_sleep: bls 1387 blsp2_i2c6_sleep: blsp2-i2c6-sleep-state {
1371 pins = "gpio8 1388 pins = "gpio83", "gpio84";
1372 function = "b 1389 function = "blsp_i2c12";
1373 drive-strengt 1390 drive-strength = <2>;
1374 bias-pull-up; 1391 bias-pull-up;
1375 }; 1392 };
1376 1393
1377 blsp2_spi1_default: b 1394 blsp2_spi1_default: blsp2-spi1-default-state {
1378 pins = "gpio5 1395 pins = "gpio53", "gpio54", "gpio55", "gpio56";
1379 function = "b 1396 function = "blsp_spi7";
1380 drive-strengt 1397 drive-strength = <6>;
1381 bias-disable; 1398 bias-disable;
1382 }; 1399 };
1383 1400
1384 blsp2_spi2_default: b 1401 blsp2_spi2_default: blsp2-spi2-default-state {
1385 pins = "gpio4 1402 pins = "gpio4", "gpio5", "gpio6", "gpio7";
1386 function = "b 1403 function = "blsp_spi8";
1387 drive-strengt 1404 drive-strength = <6>;
1388 bias-disable; 1405 bias-disable;
1389 }; 1406 };
1390 1407
1391 blsp2_spi3_default: b 1408 blsp2_spi3_default: blsp2-spi3-default-state {
1392 pins = "gpio4 1409 pins = "gpio49", "gpio50", "gpio51", "gpio52";
1393 function = "b 1410 function = "blsp_spi9";
1394 drive-strengt 1411 drive-strength = <6>;
1395 bias-disable; 1412 bias-disable;
1396 }; 1413 };
1397 1414
1398 blsp2_spi4_default: b 1415 blsp2_spi4_default: blsp2-spi4-default-state {
1399 pins = "gpio6 1416 pins = "gpio65", "gpio66", "gpio67", "gpio68";
1400 function = "b 1417 function = "blsp_spi10";
1401 drive-strengt 1418 drive-strength = <6>;
1402 bias-disable; 1419 bias-disable;
1403 }; 1420 };
1404 1421
1405 blsp2_spi5_default: b 1422 blsp2_spi5_default: blsp2-spi5-default-state {
1406 pins = "gpio5 1423 pins = "gpio58", "gpio59", "gpio60", "gpio61";
1407 function = "b 1424 function = "blsp_spi11";
1408 drive-strengt 1425 drive-strength = <6>;
1409 bias-disable; 1426 bias-disable;
1410 }; 1427 };
1411 1428
1412 blsp2_spi6_default: b 1429 blsp2_spi6_default: blsp2-spi6-default-state {
1413 pins = "gpio8 1430 pins = "gpio81", "gpio82", "gpio83", "gpio84";
1414 function = "b 1431 function = "blsp_spi12";
1415 drive-strengt 1432 drive-strength = <6>;
1416 bias-disable; 1433 bias-disable;
1417 }; 1434 };
1418 }; 1435 };
1419 1436
1420 remoteproc_mss: remoteproc@40 1437 remoteproc_mss: remoteproc@4080000 {
1421 compatible = "qcom,ms 1438 compatible = "qcom,msm8998-mss-pil";
1422 reg = <0x04080000 0x1 1439 reg = <0x04080000 0x100>, <0x04180000 0x20>;
1423 reg-names = "qdsp6", 1440 reg-names = "qdsp6", "rmb";
1424 1441
1425 interrupts-extended = 1442 interrupts-extended =
1426 <&intc GIC_SP 1443 <&intc GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
1427 <&modem_smp2p 1444 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1428 <&modem_smp2p 1445 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1429 <&modem_smp2p 1446 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1430 <&modem_smp2p 1447 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
1431 <&modem_smp2p 1448 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
1432 interrupt-names = "wd 1449 interrupt-names = "wdog", "fatal", "ready",
1433 "ha 1450 "handover", "stop-ack",
1434 "sh 1451 "shutdown-ack";
1435 1452
1436 clocks = <&gcc GCC_MS 1453 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
1437 <&gcc GCC_BI 1454 <&gcc GCC_BIMC_MSS_Q6_AXI_CLK>,
1438 <&gcc GCC_BO 1455 <&gcc GCC_BOOT_ROM_AHB_CLK>,
1439 <&gcc GCC_MS 1456 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
1440 <&gcc GCC_MS 1457 <&gcc GCC_MSS_SNOC_AXI_CLK>,
1441 <&gcc GCC_MS 1458 <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>,
1442 <&rpmcc RPM_ 1459 <&rpmcc RPM_SMD_QDSS_CLK>,
1443 <&rpmcc RPM_ 1460 <&rpmcc RPM_SMD_XO_CLK_SRC>;
1444 clock-names = "iface" 1461 clock-names = "iface", "bus", "mem", "gpll0_mss",
1445 "snoc_a 1462 "snoc_axi", "mnoc_axi", "qdss", "xo";
1446 1463
1447 qcom,smem-states = <& 1464 qcom,smem-states = <&modem_smp2p_out 0>;
1448 qcom,smem-state-names 1465 qcom,smem-state-names = "stop";
1449 1466
1450 resets = <&gcc GCC_MS 1467 resets = <&gcc GCC_MSS_RESTART>;
1451 reset-names = "mss_re 1468 reset-names = "mss_restart";
1452 1469
1453 qcom,halt-regs = <&tc 1470 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>;
1454 1471
1455 power-domains = <&rpm 1472 power-domains = <&rpmpd MSM8998_VDDCX>,
1456 <&rpm 1473 <&rpmpd MSM8998_VDDMX>;
1457 power-domain-names = 1474 power-domain-names = "cx", "mx";
1458 1475
1459 status = "disabled"; 1476 status = "disabled";
1460 1477
1461 mba { 1478 mba {
1462 memory-region 1479 memory-region = <&mba_mem>;
1463 }; 1480 };
1464 1481
1465 mpss { 1482 mpss {
1466 memory-region 1483 memory-region = <&mpss_mem>;
1467 }; 1484 };
1468 1485
1469 metadata { 1486 metadata {
1470 memory-region 1487 memory-region = <&mdata_mem>;
1471 }; 1488 };
1472 1489
1473 glink-edge { 1490 glink-edge {
1474 interrupts = 1491 interrupts = <GIC_SPI 452 IRQ_TYPE_EDGE_RISING>;
1475 label = "mode 1492 label = "modem";
1476 qcom,remote-p 1493 qcom,remote-pid = <1>;
1477 mboxes = <&ap 1494 mboxes = <&apcs_glb 15>;
1478 }; 1495 };
1479 }; 1496 };
1480 1497
1481 adreno_gpu: gpu@5000000 { 1498 adreno_gpu: gpu@5000000 {
1482 compatible = "qcom,ad 1499 compatible = "qcom,adreno-540.1", "qcom,adreno";
1483 reg = <0x05000000 0x4 1500 reg = <0x05000000 0x40000>;
1484 reg-names = "kgsl_3d0 1501 reg-names = "kgsl_3d0_reg_memory";
1485 1502
1486 clocks = <&gcc GCC_GP 1503 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
1487 <&gpucc RBBMT 1504 <&gpucc RBBMTIMER_CLK>,
1488 <&gcc GCC_BIM 1505 <&gcc GCC_BIMC_GFX_CLK>,
1489 <&gcc GCC_GPU 1506 <&gcc GCC_GPU_BIMC_GFX_CLK>,
1490 <&gpucc RBCPR 1507 <&gpucc RBCPR_CLK>,
1491 <&gpucc GFX3D 1508 <&gpucc GFX3D_CLK>;
1492 clock-names = "iface" 1509 clock-names = "iface",
1493 "rbbmtimer", 1510 "rbbmtimer",
1494 "mem", 1511 "mem",
1495 "mem_iface", 1512 "mem_iface",
1496 "rbcpr", 1513 "rbcpr",
1497 "core"; 1514 "core";
1498 1515
1499 interrupts = <GIC_SPI 1516 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
1500 iommus = <&adreno_smm 1517 iommus = <&adreno_smmu 0>;
1501 operating-points-v2 = 1518 operating-points-v2 = <&gpu_opp_table>;
1502 power-domains = <&rpm 1519 power-domains = <&rpmpd MSM8998_VDDMX>;
1503 status = "disabled"; 1520 status = "disabled";
1504 1521
1505 gpu_opp_table: opp-ta 1522 gpu_opp_table: opp-table {
1506 compatible = 1523 compatible = "operating-points-v2";
1507 opp-710000097 1524 opp-710000097 {
1508 opp-h 1525 opp-hz = /bits/ 64 <710000097>;
1509 opp-l 1526 opp-level = <RPM_SMD_LEVEL_TURBO>;
1510 opp-s 1527 opp-supported-hw = <0xff>;
1511 }; 1528 };
1512 1529
1513 opp-670000048 1530 opp-670000048 {
1514 opp-h 1531 opp-hz = /bits/ 64 <670000048>;
1515 opp-l 1532 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
1516 opp-s 1533 opp-supported-hw = <0xff>;
1517 }; 1534 };
1518 1535
1519 opp-596000097 1536 opp-596000097 {
1520 opp-h 1537 opp-hz = /bits/ 64 <596000097>;
1521 opp-l 1538 opp-level = <RPM_SMD_LEVEL_NOM>;
1522 opp-s 1539 opp-supported-hw = <0xff>;
1523 }; 1540 };
1524 1541
1525 opp-515000097 1542 opp-515000097 {
1526 opp-h 1543 opp-hz = /bits/ 64 <515000097>;
1527 opp-l 1544 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
1528 opp-s 1545 opp-supported-hw = <0xff>;
1529 }; 1546 };
1530 1547
1531 opp-414000000 1548 opp-414000000 {
1532 opp-h 1549 opp-hz = /bits/ 64 <414000000>;
1533 opp-l 1550 opp-level = <RPM_SMD_LEVEL_SVS>;
1534 opp-s 1551 opp-supported-hw = <0xff>;
1535 }; 1552 };
1536 1553
1537 opp-342000000 1554 opp-342000000 {
1538 opp-h 1555 opp-hz = /bits/ 64 <342000000>;
1539 opp-l 1556 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
1540 opp-s 1557 opp-supported-hw = <0xff>;
1541 }; 1558 };
1542 1559
1543 opp-257000000 1560 opp-257000000 {
1544 opp-h 1561 opp-hz = /bits/ 64 <257000000>;
1545 opp-l 1562 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
1546 opp-s 1563 opp-supported-hw = <0xff>;
1547 }; 1564 };
1548 }; 1565 };
1549 }; 1566 };
1550 1567
1551 adreno_smmu: iommu@5040000 { 1568 adreno_smmu: iommu@5040000 {
1552 compatible = "qcom,ms 1569 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
1553 reg = <0x05040000 0x1 1570 reg = <0x05040000 0x10000>;
1554 clocks = <&gcc GCC_GP 1571 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
1555 <&gcc GCC_BI 1572 <&gcc GCC_BIMC_GFX_CLK>,
1556 <&gcc GCC_GP 1573 <&gcc GCC_GPU_BIMC_GFX_CLK>;
1557 clock-names = "iface" 1574 clock-names = "iface", "mem", "mem_iface";
1558 1575
1559 #global-interrupts = 1576 #global-interrupts = <0>;
1560 #iommu-cells = <1>; 1577 #iommu-cells = <1>;
1561 interrupts = 1578 interrupts =
1562 <GIC_SPI 329 1579 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1563 <GIC_SPI 330 1580 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
1564 <GIC_SPI 331 1581 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
1565 /* 1582 /*
1566 * GPU-GX GDSC's pare 1583 * GPU-GX GDSC's parent is GPU-CX. We need to bring up the
1567 * GPU-CX for SMMU bu 1584 * GPU-CX for SMMU but we need both of them up for Adreno.
1568 * Contemporarily, we 1585 * Contemporarily, we also need to manage the VDDMX rpmpd
1569 * domain in the Adre 1586 * domain in the Adreno driver.
1570 * Enable GPU CX/GX G 1587 * Enable GPU CX/GX GDSCs here so that we can manage the
1571 * SoC VDDMX RPM Powe 1588 * SoC VDDMX RPM Power Domain in the Adreno driver.
1572 */ 1589 */
1573 power-domains = <&gpu 1590 power-domains = <&gpucc GPU_GX_GDSC>;
1574 }; 1591 };
1575 1592
1576 gpucc: clock-controller@50650 1593 gpucc: clock-controller@5065000 {
1577 compatible = "qcom,ms 1594 compatible = "qcom,msm8998-gpucc";
1578 #clock-cells = <1>; 1595 #clock-cells = <1>;
1579 #reset-cells = <1>; 1596 #reset-cells = <1>;
1580 #power-domain-cells = 1597 #power-domain-cells = <1>;
1581 reg = <0x05065000 0x9 1598 reg = <0x05065000 0x9000>;
1582 1599
1583 clocks = <&rpmcc RPM_ 1600 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1584 <&gcc GCC_GP 1601 <&gcc GCC_GPU_GPLL0_CLK>;
1585 clock-names = "xo", 1602 clock-names = "xo",
1586 "gpll0" 1603 "gpll0";
1587 }; 1604 };
1588 1605
1589 lpass_q6_smmu: iommu@5100000 <<
1590 compatible = "qcom,ms <<
1591 reg = <0x05100000 0x4 <<
1592 clocks = <&gcc HLOS1_ <<
1593 clock-names = "bus"; <<
1594 <<
1595 #global-interrupts = <<
1596 #iommu-cells = <1>; <<
1597 interrupts = <<
1598 <GIC_SPI 226 <<
1599 <GIC_SPI 393 <<
1600 <GIC_SPI 394 <<
1601 <GIC_SPI 395 <<
1602 <GIC_SPI 396 <<
1603 <GIC_SPI 397 <<
1604 <GIC_SPI 398 <<
1605 <GIC_SPI 399 <<
1606 <GIC_SPI 400 <<
1607 <GIC_SPI 401 <<
1608 <GIC_SPI 402 <<
1609 <GIC_SPI 403 <<
1610 <GIC_SPI 137 <<
1611 <<
1612 power-domains = <&gcc <<
1613 status = "disabled"; <<
1614 }; <<
1615 <<
1616 remoteproc_slpi: remoteproc@5 1606 remoteproc_slpi: remoteproc@5800000 {
1617 compatible = "qcom,ms 1607 compatible = "qcom,msm8998-slpi-pas";
1618 reg = <0x05800000 0x4 1608 reg = <0x05800000 0x4040>;
1619 1609
1620 interrupts-extended = 1610 interrupts-extended = <&intc GIC_SPI 390 IRQ_TYPE_EDGE_RISING>,
1621 1611 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1622 1612 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1623 1613 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1624 1614 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1625 interrupt-names = "wd 1615 interrupt-names = "wdog", "fatal", "ready",
1626 "ha 1616 "handover", "stop-ack";
1627 1617
1628 px-supply = <&vreg_lv 1618 px-supply = <&vreg_lvs2a_1p8>;
1629 1619
1630 clocks = <&rpmcc RPM_ !! 1620 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1631 clock-names = "xo"; !! 1621 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
>> 1622 clock-names = "xo", "aggre2";
1632 1623
1633 memory-region = <&slp 1624 memory-region = <&slpi_mem>;
1634 1625
1635 qcom,smem-states = <& 1626 qcom,smem-states = <&slpi_smp2p_out 0>;
1636 qcom,smem-state-names 1627 qcom,smem-state-names = "stop";
1637 1628
1638 power-domains = <&rpm 1629 power-domains = <&rpmpd MSM8998_SSCCX>;
1639 power-domain-names = 1630 power-domain-names = "ssc_cx";
1640 1631
1641 status = "disabled"; 1632 status = "disabled";
1642 1633
1643 glink-edge { 1634 glink-edge {
1644 interrupts = 1635 interrupts = <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>;
1645 label = "dsps 1636 label = "dsps";
1646 qcom,remote-p 1637 qcom,remote-pid = <3>;
1647 mboxes = <&ap 1638 mboxes = <&apcs_glb 27>;
1648 }; 1639 };
1649 }; 1640 };
1650 1641
1651 stm: stm@6002000 { 1642 stm: stm@6002000 {
1652 compatible = "arm,cor 1643 compatible = "arm,coresight-stm", "arm,primecell";
1653 reg = <0x06002000 0x1 1644 reg = <0x06002000 0x1000>,
1654 <0x16280000 0x1 1645 <0x16280000 0x180000>;
1655 reg-names = "stm-base 1646 reg-names = "stm-base", "stm-stimulus-base";
1656 status = "disabled"; 1647 status = "disabled";
1657 1648
1658 clocks = <&rpmcc RPM_ 1649 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1659 clock-names = "apb_pc 1650 clock-names = "apb_pclk", "atclk";
1660 1651
1661 out-ports { 1652 out-ports {
1662 port { 1653 port {
1663 stm_o 1654 stm_out: endpoint {
1664 1655 remote-endpoint = <&funnel0_in7>;
1665 }; 1656 };
1666 }; 1657 };
1667 }; 1658 };
1668 }; 1659 };
1669 1660
1670 funnel1: funnel@6041000 { 1661 funnel1: funnel@6041000 {
1671 compatible = "arm,cor 1662 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1672 reg = <0x06041000 0x1 1663 reg = <0x06041000 0x1000>;
1673 status = "disabled"; 1664 status = "disabled";
1674 1665
1675 clocks = <&rpmcc RPM_ 1666 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1676 clock-names = "apb_pc 1667 clock-names = "apb_pclk", "atclk";
1677 1668
1678 out-ports { 1669 out-ports {
1679 port { 1670 port {
1680 funne 1671 funnel0_out: endpoint {
1681 1672 remote-endpoint =
1682 1673 <&merge_funnel_in0>;
1683 }; 1674 };
1684 }; 1675 };
1685 }; 1676 };
1686 1677
1687 in-ports { 1678 in-ports {
1688 #address-cell 1679 #address-cells = <1>;
1689 #size-cells = 1680 #size-cells = <0>;
1690 1681
1691 port@7 { 1682 port@7 {
1692 reg = 1683 reg = <7>;
1693 funne 1684 funnel0_in7: endpoint {
1694 1685 remote-endpoint = <&stm_out>;
1695 }; 1686 };
1696 }; 1687 };
1697 }; 1688 };
1698 }; 1689 };
1699 1690
1700 funnel2: funnel@6042000 { 1691 funnel2: funnel@6042000 {
1701 compatible = "arm,cor 1692 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1702 reg = <0x06042000 0x1 1693 reg = <0x06042000 0x1000>;
1703 status = "disabled"; 1694 status = "disabled";
1704 1695
1705 clocks = <&rpmcc RPM_ 1696 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1706 clock-names = "apb_pc 1697 clock-names = "apb_pclk", "atclk";
1707 1698
1708 out-ports { 1699 out-ports {
1709 port { 1700 port {
1710 funne 1701 funnel1_out: endpoint {
1711 1702 remote-endpoint =
1712 1703 <&merge_funnel_in1>;
1713 }; 1704 };
1714 }; 1705 };
1715 }; 1706 };
1716 1707
1717 in-ports { 1708 in-ports {
1718 #address-cell 1709 #address-cells = <1>;
1719 #size-cells = 1710 #size-cells = <0>;
1720 1711
1721 port@6 { 1712 port@6 {
1722 reg = 1713 reg = <6>;
1723 funne 1714 funnel1_in6: endpoint {
1724 1715 remote-endpoint =
1725 1716 <&apss_merge_funnel_out>;
1726 }; 1717 };
1727 }; 1718 };
1728 }; 1719 };
1729 }; 1720 };
1730 1721
1731 funnel3: funnel@6045000 { 1722 funnel3: funnel@6045000 {
1732 compatible = "arm,cor 1723 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1733 reg = <0x06045000 0x1 1724 reg = <0x06045000 0x1000>;
1734 status = "disabled"; 1725 status = "disabled";
1735 1726
1736 clocks = <&rpmcc RPM_ 1727 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1737 clock-names = "apb_pc 1728 clock-names = "apb_pclk", "atclk";
1738 1729
1739 out-ports { 1730 out-ports {
1740 port { 1731 port {
1741 merge 1732 merge_funnel_out: endpoint {
1742 1733 remote-endpoint =
1743 1734 <&etf_in>;
1744 }; 1735 };
1745 }; 1736 };
1746 }; 1737 };
1747 1738
1748 in-ports { 1739 in-ports {
1749 #address-cell 1740 #address-cells = <1>;
1750 #size-cells = 1741 #size-cells = <0>;
1751 1742
1752 port@0 { 1743 port@0 {
1753 reg = 1744 reg = <0>;
1754 merge 1745 merge_funnel_in0: endpoint {
1755 1746 remote-endpoint =
1756 1747 <&funnel0_out>;
1757 }; 1748 };
1758 }; 1749 };
1759 1750
1760 port@1 { 1751 port@1 {
1761 reg = 1752 reg = <1>;
1762 merge 1753 merge_funnel_in1: endpoint {
1763 1754 remote-endpoint =
1764 1755 <&funnel1_out>;
1765 }; 1756 };
1766 }; 1757 };
1767 }; 1758 };
1768 }; 1759 };
1769 1760
1770 replicator1: replicator@60460 1761 replicator1: replicator@6046000 {
1771 compatible = "arm,cor 1762 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
1772 reg = <0x06046000 0x1 1763 reg = <0x06046000 0x1000>;
1773 status = "disabled"; 1764 status = "disabled";
1774 1765
1775 clocks = <&rpmcc RPM_ 1766 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1776 clock-names = "apb_pc 1767 clock-names = "apb_pclk", "atclk";
1777 1768
1778 out-ports { 1769 out-ports {
1779 port { 1770 port {
1780 repli 1771 replicator_out: endpoint {
1781 1772 remote-endpoint = <&etr_in>;
1782 }; 1773 };
1783 }; 1774 };
1784 }; 1775 };
1785 1776
1786 in-ports { 1777 in-ports {
1787 port { 1778 port {
1788 repli 1779 replicator_in: endpoint {
1789 1780 remote-endpoint = <&etf_out>;
1790 }; 1781 };
1791 }; 1782 };
1792 }; 1783 };
1793 }; 1784 };
1794 1785
1795 etf: etf@6047000 { 1786 etf: etf@6047000 {
1796 compatible = "arm,cor 1787 compatible = "arm,coresight-tmc", "arm,primecell";
1797 reg = <0x06047000 0x1 1788 reg = <0x06047000 0x1000>;
1798 status = "disabled"; 1789 status = "disabled";
1799 1790
1800 clocks = <&rpmcc RPM_ 1791 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1801 clock-names = "apb_pc 1792 clock-names = "apb_pclk", "atclk";
1802 1793
1803 out-ports { 1794 out-ports {
1804 port { 1795 port {
1805 etf_o 1796 etf_out: endpoint {
1806 1797 remote-endpoint =
1807 1798 <&replicator_in>;
1808 }; 1799 };
1809 }; 1800 };
1810 }; 1801 };
1811 1802
1812 in-ports { 1803 in-ports {
1813 port { 1804 port {
1814 etf_i 1805 etf_in: endpoint {
1815 1806 remote-endpoint =
1816 1807 <&merge_funnel_out>;
1817 }; 1808 };
1818 }; 1809 };
1819 }; 1810 };
1820 }; 1811 };
1821 1812
1822 etr: etr@6048000 { 1813 etr: etr@6048000 {
1823 compatible = "arm,cor 1814 compatible = "arm,coresight-tmc", "arm,primecell";
1824 reg = <0x06048000 0x1 1815 reg = <0x06048000 0x1000>;
1825 status = "disabled"; 1816 status = "disabled";
1826 1817
1827 clocks = <&rpmcc RPM_ 1818 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1828 clock-names = "apb_pc 1819 clock-names = "apb_pclk", "atclk";
1829 arm,scatter-gather; 1820 arm,scatter-gather;
1830 1821
1831 in-ports { 1822 in-ports {
1832 port { 1823 port {
1833 etr_i 1824 etr_in: endpoint {
1834 1825 remote-endpoint =
1835 1826 <&replicator_out>;
1836 }; 1827 };
1837 }; 1828 };
1838 }; 1829 };
1839 }; 1830 };
1840 1831
1841 etm1: etm@7840000 { 1832 etm1: etm@7840000 {
1842 compatible = "arm,cor 1833 compatible = "arm,coresight-etm4x", "arm,primecell";
1843 reg = <0x07840000 0x1 1834 reg = <0x07840000 0x1000>;
1844 status = "disabled"; 1835 status = "disabled";
1845 1836
1846 clocks = <&rpmcc RPM_ 1837 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1847 clock-names = "apb_pc 1838 clock-names = "apb_pclk", "atclk";
1848 1839
1849 cpu = <&CPU0>; 1840 cpu = <&CPU0>;
1850 1841
1851 out-ports { 1842 out-ports {
1852 port { 1843 port {
1853 etm0_ 1844 etm0_out: endpoint {
1854 1845 remote-endpoint =
1855 1846 <&apss_funnel_in0>;
1856 }; 1847 };
1857 }; 1848 };
1858 }; 1849 };
1859 }; 1850 };
1860 1851
1861 etm2: etm@7940000 { 1852 etm2: etm@7940000 {
1862 compatible = "arm,cor 1853 compatible = "arm,coresight-etm4x", "arm,primecell";
1863 reg = <0x07940000 0x1 1854 reg = <0x07940000 0x1000>;
1864 status = "disabled"; 1855 status = "disabled";
1865 1856
1866 clocks = <&rpmcc RPM_ 1857 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1867 clock-names = "apb_pc 1858 clock-names = "apb_pclk", "atclk";
1868 1859
1869 cpu = <&CPU1>; 1860 cpu = <&CPU1>;
1870 1861
1871 out-ports { 1862 out-ports {
1872 port { 1863 port {
1873 etm1_ 1864 etm1_out: endpoint {
1874 1865 remote-endpoint =
1875 1866 <&apss_funnel_in1>;
1876 }; 1867 };
1877 }; 1868 };
1878 }; 1869 };
1879 }; 1870 };
1880 1871
1881 etm3: etm@7a40000 { 1872 etm3: etm@7a40000 {
1882 compatible = "arm,cor 1873 compatible = "arm,coresight-etm4x", "arm,primecell";
1883 reg = <0x07a40000 0x1 1874 reg = <0x07a40000 0x1000>;
1884 status = "disabled"; 1875 status = "disabled";
1885 1876
1886 clocks = <&rpmcc RPM_ 1877 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1887 clock-names = "apb_pc 1878 clock-names = "apb_pclk", "atclk";
1888 1879
1889 cpu = <&CPU2>; 1880 cpu = <&CPU2>;
1890 1881
1891 out-ports { 1882 out-ports {
1892 port { 1883 port {
1893 etm2_ 1884 etm2_out: endpoint {
1894 1885 remote-endpoint =
1895 1886 <&apss_funnel_in2>;
1896 }; 1887 };
1897 }; 1888 };
1898 }; 1889 };
1899 }; 1890 };
1900 1891
1901 etm4: etm@7b40000 { 1892 etm4: etm@7b40000 {
1902 compatible = "arm,cor 1893 compatible = "arm,coresight-etm4x", "arm,primecell";
1903 reg = <0x07b40000 0x1 1894 reg = <0x07b40000 0x1000>;
1904 status = "disabled"; 1895 status = "disabled";
1905 1896
1906 clocks = <&rpmcc RPM_ 1897 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1907 clock-names = "apb_pc 1898 clock-names = "apb_pclk", "atclk";
1908 1899
1909 cpu = <&CPU3>; 1900 cpu = <&CPU3>;
1910 1901
1911 out-ports { 1902 out-ports {
1912 port { 1903 port {
1913 etm3_ 1904 etm3_out: endpoint {
1914 1905 remote-endpoint =
1915 1906 <&apss_funnel_in3>;
1916 }; 1907 };
1917 }; 1908 };
1918 }; 1909 };
1919 }; 1910 };
1920 1911
1921 funnel4: funnel@7b60000 { /* 1912 funnel4: funnel@7b60000 { /* APSS Funnel */
1922 compatible = "arm,cor 1913 compatible = "arm,coresight-etm4x", "arm,primecell";
1923 reg = <0x07b60000 0x1 1914 reg = <0x07b60000 0x1000>;
1924 status = "disabled"; 1915 status = "disabled";
1925 1916
1926 clocks = <&rpmcc RPM_ 1917 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1927 clock-names = "apb_pc 1918 clock-names = "apb_pclk", "atclk";
1928 1919
1929 out-ports { 1920 out-ports {
1930 port { 1921 port {
1931 apss_ 1922 apss_funnel_out: endpoint {
1932 1923 remote-endpoint =
1933 1924 <&apss_merge_funnel_in>;
1934 }; 1925 };
1935 }; 1926 };
1936 }; 1927 };
1937 1928
1938 in-ports { 1929 in-ports {
1939 #address-cell 1930 #address-cells = <1>;
1940 #size-cells = 1931 #size-cells = <0>;
1941 1932
1942 port@0 { 1933 port@0 {
1943 reg = 1934 reg = <0>;
1944 apss_ 1935 apss_funnel_in0: endpoint {
1945 1936 remote-endpoint =
1946 1937 <&etm0_out>;
1947 }; 1938 };
1948 }; 1939 };
1949 1940
1950 port@1 { 1941 port@1 {
1951 reg = 1942 reg = <1>;
1952 apss_ 1943 apss_funnel_in1: endpoint {
1953 1944 remote-endpoint =
1954 1945 <&etm1_out>;
1955 }; 1946 };
1956 }; 1947 };
1957 1948
1958 port@2 { 1949 port@2 {
1959 reg = 1950 reg = <2>;
1960 apss_ 1951 apss_funnel_in2: endpoint {
1961 1952 remote-endpoint =
1962 1953 <&etm2_out>;
1963 }; 1954 };
1964 }; 1955 };
1965 1956
1966 port@3 { 1957 port@3 {
1967 reg = 1958 reg = <3>;
1968 apss_ 1959 apss_funnel_in3: endpoint {
1969 1960 remote-endpoint =
1970 1961 <&etm3_out>;
1971 }; 1962 };
1972 }; 1963 };
1973 1964
1974 port@4 { 1965 port@4 {
1975 reg = 1966 reg = <4>;
1976 apss_ 1967 apss_funnel_in4: endpoint {
1977 1968 remote-endpoint =
1978 1969 <&etm4_out>;
1979 }; 1970 };
1980 }; 1971 };
1981 1972
1982 port@5 { 1973 port@5 {
1983 reg = 1974 reg = <5>;
1984 apss_ 1975 apss_funnel_in5: endpoint {
1985 1976 remote-endpoint =
1986 1977 <&etm5_out>;
1987 }; 1978 };
1988 }; 1979 };
1989 1980
1990 port@6 { 1981 port@6 {
1991 reg = 1982 reg = <6>;
1992 apss_ 1983 apss_funnel_in6: endpoint {
1993 1984 remote-endpoint =
1994 1985 <&etm6_out>;
1995 }; 1986 };
1996 }; 1987 };
1997 1988
1998 port@7 { 1989 port@7 {
1999 reg = 1990 reg = <7>;
2000 apss_ 1991 apss_funnel_in7: endpoint {
2001 1992 remote-endpoint =
2002 1993 <&etm7_out>;
2003 }; 1994 };
2004 }; 1995 };
2005 }; 1996 };
2006 }; 1997 };
2007 1998
2008 funnel5: funnel@7b70000 { 1999 funnel5: funnel@7b70000 {
2009 compatible = "arm,cor 2000 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2010 reg = <0x07b70000 0x1 2001 reg = <0x07b70000 0x1000>;
2011 status = "disabled"; 2002 status = "disabled";
2012 2003
2013 clocks = <&rpmcc RPM_ 2004 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2014 clock-names = "apb_pc 2005 clock-names = "apb_pclk", "atclk";
2015 2006
2016 out-ports { 2007 out-ports {
2017 port { 2008 port {
2018 apss_ 2009 apss_merge_funnel_out: endpoint {
2019 2010 remote-endpoint =
2020 2011 <&funnel1_in6>;
2021 }; 2012 };
2022 }; 2013 };
2023 }; 2014 };
2024 2015
2025 in-ports { 2016 in-ports {
2026 port { 2017 port {
2027 apss_ 2018 apss_merge_funnel_in: endpoint {
2028 2019 remote-endpoint =
2029 2020 <&apss_funnel_out>;
2030 }; 2021 };
2031 }; 2022 };
2032 }; 2023 };
2033 }; 2024 };
2034 2025
2035 etm5: etm@7c40000 { 2026 etm5: etm@7c40000 {
2036 compatible = "arm,cor 2027 compatible = "arm,coresight-etm4x", "arm,primecell";
2037 reg = <0x07c40000 0x1 2028 reg = <0x07c40000 0x1000>;
2038 status = "disabled"; 2029 status = "disabled";
2039 2030
2040 clocks = <&rpmcc RPM_ 2031 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2041 clock-names = "apb_pc 2032 clock-names = "apb_pclk", "atclk";
2042 2033
2043 cpu = <&CPU4>; 2034 cpu = <&CPU4>;
2044 2035
2045 out-ports { 2036 out-ports {
2046 port { 2037 port {
2047 etm4_ 2038 etm4_out: endpoint {
2048 2039 remote-endpoint = <&apss_funnel_in4>;
2049 }; 2040 };
2050 }; 2041 };
2051 }; 2042 };
2052 }; 2043 };
2053 2044
2054 etm6: etm@7d40000 { 2045 etm6: etm@7d40000 {
2055 compatible = "arm,cor 2046 compatible = "arm,coresight-etm4x", "arm,primecell";
2056 reg = <0x07d40000 0x1 2047 reg = <0x07d40000 0x1000>;
2057 status = "disabled"; 2048 status = "disabled";
2058 2049
2059 clocks = <&rpmcc RPM_ 2050 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2060 clock-names = "apb_pc 2051 clock-names = "apb_pclk", "atclk";
2061 2052
2062 cpu = <&CPU5>; 2053 cpu = <&CPU5>;
2063 2054
2064 out-ports { 2055 out-ports {
2065 port { 2056 port {
2066 etm5_ 2057 etm5_out: endpoint {
2067 2058 remote-endpoint = <&apss_funnel_in5>;
2068 }; 2059 };
2069 }; 2060 };
2070 }; 2061 };
2071 }; 2062 };
2072 2063
2073 etm7: etm@7e40000 { 2064 etm7: etm@7e40000 {
2074 compatible = "arm,cor 2065 compatible = "arm,coresight-etm4x", "arm,primecell";
2075 reg = <0x07e40000 0x1 2066 reg = <0x07e40000 0x1000>;
2076 status = "disabled"; 2067 status = "disabled";
2077 2068
2078 clocks = <&rpmcc RPM_ 2069 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2079 clock-names = "apb_pc 2070 clock-names = "apb_pclk", "atclk";
2080 2071
2081 cpu = <&CPU6>; 2072 cpu = <&CPU6>;
2082 2073
2083 out-ports { 2074 out-ports {
2084 port { 2075 port {
2085 etm6_ 2076 etm6_out: endpoint {
2086 2077 remote-endpoint = <&apss_funnel_in6>;
2087 }; 2078 };
2088 }; 2079 };
2089 }; 2080 };
2090 }; 2081 };
2091 2082
2092 etm8: etm@7f40000 { 2083 etm8: etm@7f40000 {
2093 compatible = "arm,cor 2084 compatible = "arm,coresight-etm4x", "arm,primecell";
2094 reg = <0x07f40000 0x1 2085 reg = <0x07f40000 0x1000>;
2095 status = "disabled"; 2086 status = "disabled";
2096 2087
2097 clocks = <&rpmcc RPM_ 2088 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2098 clock-names = "apb_pc 2089 clock-names = "apb_pclk", "atclk";
2099 2090
2100 cpu = <&CPU7>; 2091 cpu = <&CPU7>;
2101 2092
2102 out-ports { 2093 out-ports {
2103 port { 2094 port {
2104 etm7_ 2095 etm7_out: endpoint {
2105 2096 remote-endpoint = <&apss_funnel_in7>;
2106 }; 2097 };
2107 }; 2098 };
2108 }; 2099 };
2109 }; 2100 };
2110 2101
2111 sram@290000 { 2102 sram@290000 {
2112 compatible = "qcom,rp 2103 compatible = "qcom,rpm-stats";
2113 reg = <0x00290000 0x1 2104 reg = <0x00290000 0x10000>;
2114 }; 2105 };
2115 2106
2116 spmi_bus: spmi@800f000 { 2107 spmi_bus: spmi@800f000 {
2117 compatible = "qcom,sp 2108 compatible = "qcom,spmi-pmic-arb";
2118 reg = <0x0800f000 0x1 2109 reg = <0x0800f000 0x1000>,
2119 <0x08400000 0x1 2110 <0x08400000 0x1000000>,
2120 <0x09400000 0x1 2111 <0x09400000 0x1000000>,
2121 <0x0a400000 0x2 2112 <0x0a400000 0x220000>,
2122 <0x0800a000 0x3 2113 <0x0800a000 0x3000>;
2123 reg-names = "core", " 2114 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
2124 interrupt-names = "pe 2115 interrupt-names = "periph_irq";
2125 interrupts = <GIC_SPI 2116 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
2126 qcom,ee = <0>; 2117 qcom,ee = <0>;
2127 qcom,channel = <0>; 2118 qcom,channel = <0>;
2128 #address-cells = <2>; 2119 #address-cells = <2>;
2129 #size-cells = <0>; 2120 #size-cells = <0>;
2130 interrupt-controller; 2121 interrupt-controller;
2131 #interrupt-cells = <4 2122 #interrupt-cells = <4>;
2132 }; 2123 };
2133 2124
2134 usb3: usb@a8f8800 { 2125 usb3: usb@a8f8800 {
2135 compatible = "qcom,ms 2126 compatible = "qcom,msm8998-dwc3", "qcom,dwc3";
2136 reg = <0x0a8f8800 0x4 2127 reg = <0x0a8f8800 0x400>;
2137 status = "disabled"; 2128 status = "disabled";
2138 #address-cells = <1>; 2129 #address-cells = <1>;
2139 #size-cells = <1>; 2130 #size-cells = <1>;
2140 ranges; 2131 ranges;
2141 2132
2142 clocks = <&gcc GCC_CF 2133 clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>,
2143 <&gcc GCC_US 2134 <&gcc GCC_USB30_MASTER_CLK>,
2144 <&gcc GCC_AG 2135 <&gcc GCC_AGGRE1_USB3_AXI_CLK>,
2145 <&gcc GCC_US 2136 <&gcc GCC_USB30_SLEEP_CLK>,
2146 <&gcc GCC_US 2137 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
2147 clock-names = "cfg_no 2138 clock-names = "cfg_noc",
2148 "core", 2139 "core",
2149 "iface" 2140 "iface",
2150 "sleep" 2141 "sleep",
2151 "mock_u 2142 "mock_utmi";
2152 2143
2153 assigned-clocks = <&g 2144 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
2154 <&g 2145 <&gcc GCC_USB30_MASTER_CLK>;
2155 assigned-clock-rates 2146 assigned-clock-rates = <19200000>, <120000000>;
2156 2147
2157 interrupts = <GIC_SPI !! 2148 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
2158 <GIC_SPI <<
2159 <GIC_SPI 2149 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
2160 interrupt-names = "pw !! 2150 interrupt-names = "hs_phy_irq", "ss_phy_irq";
2161 "qu <<
2162 "ss <<
2163 2151
2164 power-domains = <&gcc 2152 power-domains = <&gcc USB_30_GDSC>;
2165 2153
2166 resets = <&gcc GCC_US 2154 resets = <&gcc GCC_USB_30_BCR>;
2167 2155
2168 usb3_dwc3: usb@a80000 2156 usb3_dwc3: usb@a800000 {
2169 compatible = 2157 compatible = "snps,dwc3";
2170 reg = <0x0a80 2158 reg = <0x0a800000 0xcd00>;
2171 interrupts = 2159 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
2172 snps,dis_u2_s 2160 snps,dis_u2_susphy_quirk;
2173 snps,dis_enbl 2161 snps,dis_enblslpm_quirk;
2174 snps,parkmode 2162 snps,parkmode-disable-ss-quirk;
2175 phys = <&qusb 2163 phys = <&qusb2phy>, <&usb3phy>;
2176 phy-names = " 2164 phy-names = "usb2-phy", "usb3-phy";
2177 snps,has-lpm- 2165 snps,has-lpm-erratum;
2178 snps,hird-thr 2166 snps,hird-threshold = /bits/ 8 <0x10>;
2179 }; 2167 };
2180 }; 2168 };
2181 2169
2182 usb3phy: phy@c010000 { 2170 usb3phy: phy@c010000 {
2183 compatible = "qcom,ms 2171 compatible = "qcom,msm8998-qmp-usb3-phy";
2184 reg = <0x0c010000 0x1 2172 reg = <0x0c010000 0x1000>;
2185 2173
2186 clocks = <&gcc GCC_US 2174 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
2187 <&gcc GCC_US 2175 <&gcc GCC_USB3_CLKREF_CLK>,
2188 <&gcc GCC_US 2176 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2189 <&gcc GCC_US 2177 <&gcc GCC_USB3_PHY_PIPE_CLK>;
2190 clock-names = "aux", 2178 clock-names = "aux",
2191 "ref", 2179 "ref",
2192 "cfg_ah 2180 "cfg_ahb",
2193 "pipe"; 2181 "pipe";
2194 clock-output-names = 2182 clock-output-names = "usb3_phy_pipe_clk_src";
2195 #clock-cells = <0>; 2183 #clock-cells = <0>;
2196 #phy-cells = <0>; 2184 #phy-cells = <0>;
2197 2185
2198 resets = <&gcc GCC_US 2186 resets = <&gcc GCC_USB3_PHY_BCR>,
2199 <&gcc GCC_US 2187 <&gcc GCC_USB3PHY_PHY_BCR>;
2200 reset-names = "phy", 2188 reset-names = "phy",
2201 "phy_ph 2189 "phy_phy";
2202 2190
2203 qcom,tcsr-reg = <&tcs <<
2204 <<
2205 status = "disabled"; 2191 status = "disabled";
2206 }; 2192 };
2207 2193
2208 qusb2phy: phy@c012000 { 2194 qusb2phy: phy@c012000 {
2209 compatible = "qcom,ms 2195 compatible = "qcom,msm8998-qusb2-phy";
2210 reg = <0x0c012000 0x2 2196 reg = <0x0c012000 0x2a8>;
2211 status = "disabled"; 2197 status = "disabled";
2212 #phy-cells = <0>; 2198 #phy-cells = <0>;
2213 2199
2214 clocks = <&gcc GCC_US 2200 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2215 <&gcc GCC_RX 2201 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
2216 clock-names = "cfg_ah 2202 clock-names = "cfg_ahb", "ref";
2217 2203
2218 resets = <&gcc GCC_QU 2204 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2219 2205
2220 nvmem-cells = <&qusb2 2206 nvmem-cells = <&qusb2_hstx_trim>;
2221 }; 2207 };
2222 2208
2223 sdhc2: mmc@c0a4900 { 2209 sdhc2: mmc@c0a4900 {
2224 compatible = "qcom,ms 2210 compatible = "qcom,msm8998-sdhci", "qcom,sdhci-msm-v4";
2225 reg = <0x0c0a4900 0x3 2211 reg = <0x0c0a4900 0x314>, <0x0c0a4000 0x800>;
2226 reg-names = "hc", "co 2212 reg-names = "hc", "core";
2227 2213
2228 interrupts = <GIC_SPI 2214 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
2229 <GIC_SPI 2215 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
2230 interrupt-names = "hc 2216 interrupt-names = "hc_irq", "pwr_irq";
2231 2217
2232 clock-names = "iface" 2218 clock-names = "iface", "core", "xo";
2233 clocks = <&gcc GCC_SD 2219 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2234 <&gcc GCC_SD 2220 <&gcc GCC_SDCC2_APPS_CLK>,
2235 <&rpmcc RPM_ 2221 <&rpmcc RPM_SMD_XO_CLK_SRC>;
2236 bus-width = <4>; 2222 bus-width = <4>;
2237 status = "disabled"; 2223 status = "disabled";
2238 }; 2224 };
2239 2225
2240 blsp1_dma: dma-controller@c14 2226 blsp1_dma: dma-controller@c144000 {
2241 compatible = "qcom,ba 2227 compatible = "qcom,bam-v1.7.0";
2242 reg = <0x0c144000 0x2 2228 reg = <0x0c144000 0x25000>;
2243 interrupts = <GIC_SPI 2229 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
2244 clocks = <&gcc GCC_BL 2230 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
2245 clock-names = "bam_cl 2231 clock-names = "bam_clk";
2246 #dma-cells = <1>; 2232 #dma-cells = <1>;
2247 qcom,ee = <0>; 2233 qcom,ee = <0>;
2248 qcom,controlled-remot 2234 qcom,controlled-remotely;
2249 num-channels = <18>; 2235 num-channels = <18>;
2250 qcom,num-ees = <4>; 2236 qcom,num-ees = <4>;
2251 }; 2237 };
2252 2238
2253 blsp1_uart3: serial@c171000 { 2239 blsp1_uart3: serial@c171000 {
2254 compatible = "qcom,ms 2240 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2255 reg = <0x0c171000 0x1 2241 reg = <0x0c171000 0x1000>;
2256 interrupts = <GIC_SPI 2242 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
2257 clocks = <&gcc GCC_BL 2243 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
2258 <&gcc GCC_BL 2244 <&gcc GCC_BLSP1_AHB_CLK>;
2259 clock-names = "core", 2245 clock-names = "core", "iface";
2260 dmas = <&blsp1_dma 4> 2246 dmas = <&blsp1_dma 4>, <&blsp1_dma 5>;
2261 dma-names = "tx", "rx 2247 dma-names = "tx", "rx";
2262 pinctrl-names = "defa 2248 pinctrl-names = "default";
2263 pinctrl-0 = <&blsp1_u 2249 pinctrl-0 = <&blsp1_uart3_on>;
2264 status = "disabled"; 2250 status = "disabled";
2265 }; 2251 };
2266 2252
2267 blsp1_i2c1: i2c@c175000 { 2253 blsp1_i2c1: i2c@c175000 {
2268 compatible = "qcom,i2 2254 compatible = "qcom,i2c-qup-v2.2.1";
2269 reg = <0x0c175000 0x6 2255 reg = <0x0c175000 0x600>;
2270 interrupts = <GIC_SPI 2256 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
2271 2257
2272 clocks = <&gcc GCC_BL 2258 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
2273 <&gcc GCC_BL 2259 <&gcc GCC_BLSP1_AHB_CLK>;
2274 clock-names = "core", 2260 clock-names = "core", "iface";
2275 dmas = <&blsp1_dma 6> 2261 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>;
2276 dma-names = "tx", "rx 2262 dma-names = "tx", "rx";
2277 pinctrl-names = "defa 2263 pinctrl-names = "default", "sleep";
2278 pinctrl-0 = <&blsp1_i 2264 pinctrl-0 = <&blsp1_i2c1_default>;
2279 pinctrl-1 = <&blsp1_i 2265 pinctrl-1 = <&blsp1_i2c1_sleep>;
2280 clock-frequency = <40 2266 clock-frequency = <400000>;
2281 2267
2282 status = "disabled"; 2268 status = "disabled";
2283 #address-cells = <1>; 2269 #address-cells = <1>;
2284 #size-cells = <0>; 2270 #size-cells = <0>;
2285 }; 2271 };
2286 2272
2287 blsp1_i2c2: i2c@c176000 { 2273 blsp1_i2c2: i2c@c176000 {
2288 compatible = "qcom,i2 2274 compatible = "qcom,i2c-qup-v2.2.1";
2289 reg = <0x0c176000 0x6 2275 reg = <0x0c176000 0x600>;
2290 interrupts = <GIC_SPI 2276 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
2291 2277
2292 clocks = <&gcc GCC_BL 2278 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
2293 <&gcc GCC_BL 2279 <&gcc GCC_BLSP1_AHB_CLK>;
2294 clock-names = "core", 2280 clock-names = "core", "iface";
2295 dmas = <&blsp1_dma 8> 2281 dmas = <&blsp1_dma 8>, <&blsp1_dma 9>;
2296 dma-names = "tx", "rx 2282 dma-names = "tx", "rx";
2297 pinctrl-names = "defa 2283 pinctrl-names = "default", "sleep";
2298 pinctrl-0 = <&blsp1_i 2284 pinctrl-0 = <&blsp1_i2c2_default>;
2299 pinctrl-1 = <&blsp1_i 2285 pinctrl-1 = <&blsp1_i2c2_sleep>;
2300 clock-frequency = <40 2286 clock-frequency = <400000>;
2301 2287
2302 status = "disabled"; 2288 status = "disabled";
2303 #address-cells = <1>; 2289 #address-cells = <1>;
2304 #size-cells = <0>; 2290 #size-cells = <0>;
2305 }; 2291 };
2306 2292
2307 blsp1_i2c3: i2c@c177000 { 2293 blsp1_i2c3: i2c@c177000 {
2308 compatible = "qcom,i2 2294 compatible = "qcom,i2c-qup-v2.2.1";
2309 reg = <0x0c177000 0x6 2295 reg = <0x0c177000 0x600>;
2310 interrupts = <GIC_SPI 2296 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
2311 2297
2312 clocks = <&gcc GCC_BL 2298 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
2313 <&gcc GCC_BL 2299 <&gcc GCC_BLSP1_AHB_CLK>;
2314 clock-names = "core", 2300 clock-names = "core", "iface";
2315 dmas = <&blsp1_dma 10 2301 dmas = <&blsp1_dma 10>, <&blsp1_dma 11>;
2316 dma-names = "tx", "rx 2302 dma-names = "tx", "rx";
2317 pinctrl-names = "defa 2303 pinctrl-names = "default", "sleep";
2318 pinctrl-0 = <&blsp1_i 2304 pinctrl-0 = <&blsp1_i2c3_default>;
2319 pinctrl-1 = <&blsp1_i 2305 pinctrl-1 = <&blsp1_i2c3_sleep>;
2320 clock-frequency = <40 2306 clock-frequency = <400000>;
2321 2307
2322 status = "disabled"; 2308 status = "disabled";
2323 #address-cells = <1>; 2309 #address-cells = <1>;
2324 #size-cells = <0>; 2310 #size-cells = <0>;
2325 }; 2311 };
2326 2312
2327 blsp1_i2c4: i2c@c178000 { 2313 blsp1_i2c4: i2c@c178000 {
2328 compatible = "qcom,i2 2314 compatible = "qcom,i2c-qup-v2.2.1";
2329 reg = <0x0c178000 0x6 2315 reg = <0x0c178000 0x600>;
2330 interrupts = <GIC_SPI 2316 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
2331 2317
2332 clocks = <&gcc GCC_BL 2318 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
2333 <&gcc GCC_BL 2319 <&gcc GCC_BLSP1_AHB_CLK>;
2334 clock-names = "core", 2320 clock-names = "core", "iface";
2335 dmas = <&blsp1_dma 12 2321 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
2336 dma-names = "tx", "rx 2322 dma-names = "tx", "rx";
2337 pinctrl-names = "defa 2323 pinctrl-names = "default", "sleep";
2338 pinctrl-0 = <&blsp1_i 2324 pinctrl-0 = <&blsp1_i2c4_default>;
2339 pinctrl-1 = <&blsp1_i 2325 pinctrl-1 = <&blsp1_i2c4_sleep>;
2340 clock-frequency = <40 2326 clock-frequency = <400000>;
2341 2327
2342 status = "disabled"; 2328 status = "disabled";
2343 #address-cells = <1>; 2329 #address-cells = <1>;
2344 #size-cells = <0>; 2330 #size-cells = <0>;
2345 }; 2331 };
2346 2332
2347 blsp1_i2c5: i2c@c179000 { 2333 blsp1_i2c5: i2c@c179000 {
2348 compatible = "qcom,i2 2334 compatible = "qcom,i2c-qup-v2.2.1";
2349 reg = <0x0c179000 0x6 2335 reg = <0x0c179000 0x600>;
2350 interrupts = <GIC_SPI 2336 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
2351 2337
2352 clocks = <&gcc GCC_BL 2338 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
2353 <&gcc GCC_BL 2339 <&gcc GCC_BLSP1_AHB_CLK>;
2354 clock-names = "core", 2340 clock-names = "core", "iface";
2355 dmas = <&blsp1_dma 14 2341 dmas = <&blsp1_dma 14>, <&blsp1_dma 15>;
2356 dma-names = "tx", "rx 2342 dma-names = "tx", "rx";
2357 pinctrl-names = "defa 2343 pinctrl-names = "default", "sleep";
2358 pinctrl-0 = <&blsp1_i 2344 pinctrl-0 = <&blsp1_i2c5_default>;
2359 pinctrl-1 = <&blsp1_i 2345 pinctrl-1 = <&blsp1_i2c5_sleep>;
2360 clock-frequency = <40 2346 clock-frequency = <400000>;
2361 2347
2362 status = "disabled"; 2348 status = "disabled";
2363 #address-cells = <1>; 2349 #address-cells = <1>;
2364 #size-cells = <0>; 2350 #size-cells = <0>;
2365 }; 2351 };
2366 2352
2367 blsp1_i2c6: i2c@c17a000 { 2353 blsp1_i2c6: i2c@c17a000 {
2368 compatible = "qcom,i2 2354 compatible = "qcom,i2c-qup-v2.2.1";
2369 reg = <0x0c17a000 0x6 2355 reg = <0x0c17a000 0x600>;
2370 interrupts = <GIC_SPI 2356 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
2371 2357
2372 clocks = <&gcc GCC_BL 2358 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
2373 <&gcc GCC_BL 2359 <&gcc GCC_BLSP1_AHB_CLK>;
2374 clock-names = "core", 2360 clock-names = "core", "iface";
2375 dmas = <&blsp1_dma 16 2361 dmas = <&blsp1_dma 16>, <&blsp1_dma 17>;
2376 dma-names = "tx", "rx 2362 dma-names = "tx", "rx";
2377 pinctrl-names = "defa 2363 pinctrl-names = "default", "sleep";
2378 pinctrl-0 = <&blsp1_i 2364 pinctrl-0 = <&blsp1_i2c6_default>;
2379 pinctrl-1 = <&blsp1_i 2365 pinctrl-1 = <&blsp1_i2c6_sleep>;
2380 clock-frequency = <40 2366 clock-frequency = <400000>;
2381 2367
2382 status = "disabled"; 2368 status = "disabled";
2383 #address-cells = <1>; 2369 #address-cells = <1>;
2384 #size-cells = <0>; 2370 #size-cells = <0>;
2385 }; 2371 };
2386 2372
2387 blsp1_spi1: spi@c175000 { 2373 blsp1_spi1: spi@c175000 {
2388 compatible = "qcom,sp 2374 compatible = "qcom,spi-qup-v2.2.1";
2389 reg = <0x0c175000 0x6 2375 reg = <0x0c175000 0x600>;
2390 interrupts = <GIC_SPI 2376 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
2391 2377
2392 clocks = <&gcc GCC_BL 2378 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
2393 <&gcc GCC_BL 2379 <&gcc GCC_BLSP1_AHB_CLK>;
2394 clock-names = "core", 2380 clock-names = "core", "iface";
2395 dmas = <&blsp1_dma 6> 2381 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>;
2396 dma-names = "tx", "rx 2382 dma-names = "tx", "rx";
2397 pinctrl-names = "defa 2383 pinctrl-names = "default";
2398 pinctrl-0 = <&blsp1_s 2384 pinctrl-0 = <&blsp1_spi1_default>;
2399 2385
2400 status = "disabled"; 2386 status = "disabled";
2401 #address-cells = <1>; 2387 #address-cells = <1>;
2402 #size-cells = <0>; 2388 #size-cells = <0>;
2403 }; 2389 };
2404 2390
2405 blsp1_spi2: spi@c176000 { 2391 blsp1_spi2: spi@c176000 {
2406 compatible = "qcom,sp 2392 compatible = "qcom,spi-qup-v2.2.1";
2407 reg = <0x0c176000 0x6 2393 reg = <0x0c176000 0x600>;
2408 interrupts = <GIC_SPI 2394 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
2409 2395
2410 clocks = <&gcc GCC_BL 2396 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
2411 <&gcc GCC_BL 2397 <&gcc GCC_BLSP1_AHB_CLK>;
2412 clock-names = "core", 2398 clock-names = "core", "iface";
2413 dmas = <&blsp1_dma 8> 2399 dmas = <&blsp1_dma 8>, <&blsp1_dma 9>;
2414 dma-names = "tx", "rx 2400 dma-names = "tx", "rx";
2415 pinctrl-names = "defa 2401 pinctrl-names = "default";
2416 pinctrl-0 = <&blsp1_s 2402 pinctrl-0 = <&blsp1_spi2_default>;
2417 2403
2418 status = "disabled"; 2404 status = "disabled";
2419 #address-cells = <1>; 2405 #address-cells = <1>;
2420 #size-cells = <0>; 2406 #size-cells = <0>;
2421 }; 2407 };
2422 2408
2423 blsp1_spi3: spi@c177000 { 2409 blsp1_spi3: spi@c177000 {
2424 compatible = "qcom,sp 2410 compatible = "qcom,spi-qup-v2.2.1";
2425 reg = <0x0c177000 0x6 2411 reg = <0x0c177000 0x600>;
2426 interrupts = <GIC_SPI 2412 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
2427 2413
2428 clocks = <&gcc GCC_BL 2414 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
2429 <&gcc GCC_BL 2415 <&gcc GCC_BLSP1_AHB_CLK>;
2430 clock-names = "core", 2416 clock-names = "core", "iface";
2431 dmas = <&blsp1_dma 10 2417 dmas = <&blsp1_dma 10>, <&blsp1_dma 11>;
2432 dma-names = "tx", "rx 2418 dma-names = "tx", "rx";
2433 pinctrl-names = "defa 2419 pinctrl-names = "default";
2434 pinctrl-0 = <&blsp1_s 2420 pinctrl-0 = <&blsp1_spi3_default>;
2435 2421
2436 status = "disabled"; 2422 status = "disabled";
2437 #address-cells = <1>; 2423 #address-cells = <1>;
2438 #size-cells = <0>; 2424 #size-cells = <0>;
2439 }; 2425 };
2440 2426
2441 blsp1_spi4: spi@c178000 { 2427 blsp1_spi4: spi@c178000 {
2442 compatible = "qcom,sp 2428 compatible = "qcom,spi-qup-v2.2.1";
2443 reg = <0x0c178000 0x6 2429 reg = <0x0c178000 0x600>;
2444 interrupts = <GIC_SPI 2430 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
2445 2431
2446 clocks = <&gcc GCC_BL 2432 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
2447 <&gcc GCC_BL 2433 <&gcc GCC_BLSP1_AHB_CLK>;
2448 clock-names = "core", 2434 clock-names = "core", "iface";
2449 dmas = <&blsp1_dma 12 2435 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
2450 dma-names = "tx", "rx 2436 dma-names = "tx", "rx";
2451 pinctrl-names = "defa 2437 pinctrl-names = "default";
2452 pinctrl-0 = <&blsp1_s 2438 pinctrl-0 = <&blsp1_spi4_default>;
2453 2439
2454 status = "disabled"; 2440 status = "disabled";
2455 #address-cells = <1>; 2441 #address-cells = <1>;
2456 #size-cells = <0>; 2442 #size-cells = <0>;
2457 }; 2443 };
2458 2444
2459 blsp1_spi5: spi@c179000 { 2445 blsp1_spi5: spi@c179000 {
2460 compatible = "qcom,sp 2446 compatible = "qcom,spi-qup-v2.2.1";
2461 reg = <0x0c179000 0x6 2447 reg = <0x0c179000 0x600>;
2462 interrupts = <GIC_SPI 2448 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
2463 2449
2464 clocks = <&gcc GCC_BL 2450 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
2465 <&gcc GCC_BL 2451 <&gcc GCC_BLSP1_AHB_CLK>;
2466 clock-names = "core", 2452 clock-names = "core", "iface";
2467 dmas = <&blsp1_dma 14 2453 dmas = <&blsp1_dma 14>, <&blsp1_dma 15>;
2468 dma-names = "tx", "rx 2454 dma-names = "tx", "rx";
2469 pinctrl-names = "defa 2455 pinctrl-names = "default";
2470 pinctrl-0 = <&blsp1_s 2456 pinctrl-0 = <&blsp1_spi5_default>;
2471 2457
2472 status = "disabled"; 2458 status = "disabled";
2473 #address-cells = <1>; 2459 #address-cells = <1>;
2474 #size-cells = <0>; 2460 #size-cells = <0>;
2475 }; 2461 };
2476 2462
2477 blsp1_spi6: spi@c17a000 { 2463 blsp1_spi6: spi@c17a000 {
2478 compatible = "qcom,sp 2464 compatible = "qcom,spi-qup-v2.2.1";
2479 reg = <0x0c17a000 0x6 2465 reg = <0x0c17a000 0x600>;
2480 interrupts = <GIC_SPI 2466 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
2481 2467
2482 clocks = <&gcc GCC_BL 2468 clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
2483 <&gcc GCC_BL 2469 <&gcc GCC_BLSP1_AHB_CLK>;
2484 clock-names = "core", 2470 clock-names = "core", "iface";
2485 dmas = <&blsp1_dma 16 2471 dmas = <&blsp1_dma 16>, <&blsp1_dma 17>;
2486 dma-names = "tx", "rx 2472 dma-names = "tx", "rx";
2487 pinctrl-names = "defa 2473 pinctrl-names = "default";
2488 pinctrl-0 = <&blsp1_s 2474 pinctrl-0 = <&blsp1_spi6_default>;
2489 2475
2490 status = "disabled"; 2476 status = "disabled";
2491 #address-cells = <1>; 2477 #address-cells = <1>;
2492 #size-cells = <0>; 2478 #size-cells = <0>;
2493 }; 2479 };
2494 2480
2495 blsp2_dma: dma-controller@c18 2481 blsp2_dma: dma-controller@c184000 {
2496 compatible = "qcom,ba 2482 compatible = "qcom,bam-v1.7.0";
2497 reg = <0x0c184000 0x2 2483 reg = <0x0c184000 0x25000>;
2498 interrupts = <GIC_SPI 2484 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
2499 clocks = <&gcc GCC_BL 2485 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
2500 clock-names = "bam_cl 2486 clock-names = "bam_clk";
2501 #dma-cells = <1>; 2487 #dma-cells = <1>;
2502 qcom,ee = <0>; 2488 qcom,ee = <0>;
2503 qcom,controlled-remot 2489 qcom,controlled-remotely;
2504 num-channels = <18>; 2490 num-channels = <18>;
2505 qcom,num-ees = <4>; 2491 qcom,num-ees = <4>;
2506 }; 2492 };
2507 2493
2508 blsp2_uart1: serial@c1b0000 { 2494 blsp2_uart1: serial@c1b0000 {
2509 compatible = "qcom,ms 2495 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2510 reg = <0x0c1b0000 0x1 2496 reg = <0x0c1b0000 0x1000>;
2511 interrupts = <GIC_SPI 2497 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
2512 clocks = <&gcc GCC_BL 2498 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
2513 <&gcc GCC_BL 2499 <&gcc GCC_BLSP2_AHB_CLK>;
2514 clock-names = "core", 2500 clock-names = "core", "iface";
2515 status = "disabled"; 2501 status = "disabled";
2516 }; 2502 };
2517 2503
2518 blsp2_i2c1: i2c@c1b5000 { 2504 blsp2_i2c1: i2c@c1b5000 {
2519 compatible = "qcom,i2 2505 compatible = "qcom,i2c-qup-v2.2.1";
2520 reg = <0x0c1b5000 0x6 2506 reg = <0x0c1b5000 0x600>;
2521 interrupts = <GIC_SPI 2507 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
2522 2508
2523 clocks = <&gcc GCC_BL 2509 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
2524 <&gcc GCC_BL 2510 <&gcc GCC_BLSP2_AHB_CLK>;
2525 clock-names = "core", 2511 clock-names = "core", "iface";
2526 dmas = <&blsp2_dma 6> 2512 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>;
2527 dma-names = "tx", "rx 2513 dma-names = "tx", "rx";
2528 pinctrl-names = "defa 2514 pinctrl-names = "default", "sleep";
2529 pinctrl-0 = <&blsp2_i 2515 pinctrl-0 = <&blsp2_i2c1_default>;
2530 pinctrl-1 = <&blsp2_i 2516 pinctrl-1 = <&blsp2_i2c1_sleep>;
2531 clock-frequency = <40 2517 clock-frequency = <400000>;
2532 2518
2533 status = "disabled"; 2519 status = "disabled";
2534 #address-cells = <1>; 2520 #address-cells = <1>;
2535 #size-cells = <0>; 2521 #size-cells = <0>;
2536 }; 2522 };
2537 2523
2538 blsp2_i2c2: i2c@c1b6000 { 2524 blsp2_i2c2: i2c@c1b6000 {
2539 compatible = "qcom,i2 2525 compatible = "qcom,i2c-qup-v2.2.1";
2540 reg = <0x0c1b6000 0x6 2526 reg = <0x0c1b6000 0x600>;
2541 interrupts = <GIC_SPI 2527 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
2542 2528
2543 clocks = <&gcc GCC_BL 2529 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
2544 <&gcc GCC_BL 2530 <&gcc GCC_BLSP2_AHB_CLK>;
2545 clock-names = "core", 2531 clock-names = "core", "iface";
2546 dmas = <&blsp2_dma 8> 2532 dmas = <&blsp2_dma 8>, <&blsp2_dma 9>;
2547 dma-names = "tx", "rx 2533 dma-names = "tx", "rx";
2548 pinctrl-names = "defa 2534 pinctrl-names = "default", "sleep";
2549 pinctrl-0 = <&blsp2_i 2535 pinctrl-0 = <&blsp2_i2c2_default>;
2550 pinctrl-1 = <&blsp2_i 2536 pinctrl-1 = <&blsp2_i2c2_sleep>;
2551 clock-frequency = <40 2537 clock-frequency = <400000>;
2552 2538
2553 status = "disabled"; 2539 status = "disabled";
2554 #address-cells = <1>; 2540 #address-cells = <1>;
2555 #size-cells = <0>; 2541 #size-cells = <0>;
2556 }; 2542 };
2557 2543
2558 blsp2_i2c3: i2c@c1b7000 { 2544 blsp2_i2c3: i2c@c1b7000 {
2559 compatible = "qcom,i2 2545 compatible = "qcom,i2c-qup-v2.2.1";
2560 reg = <0x0c1b7000 0x6 2546 reg = <0x0c1b7000 0x600>;
2561 interrupts = <GIC_SPI 2547 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
2562 2548
2563 clocks = <&gcc GCC_BL 2549 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
2564 <&gcc GCC_BL 2550 <&gcc GCC_BLSP2_AHB_CLK>;
2565 clock-names = "core", 2551 clock-names = "core", "iface";
2566 dmas = <&blsp2_dma 10 2552 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>;
2567 dma-names = "tx", "rx 2553 dma-names = "tx", "rx";
2568 pinctrl-names = "defa 2554 pinctrl-names = "default", "sleep";
2569 pinctrl-0 = <&blsp2_i 2555 pinctrl-0 = <&blsp2_i2c3_default>;
2570 pinctrl-1 = <&blsp2_i 2556 pinctrl-1 = <&blsp2_i2c3_sleep>;
2571 clock-frequency = <40 2557 clock-frequency = <400000>;
2572 2558
2573 status = "disabled"; 2559 status = "disabled";
2574 #address-cells = <1>; 2560 #address-cells = <1>;
2575 #size-cells = <0>; 2561 #size-cells = <0>;
2576 }; 2562 };
2577 2563
2578 blsp2_i2c4: i2c@c1b8000 { 2564 blsp2_i2c4: i2c@c1b8000 {
2579 compatible = "qcom,i2 2565 compatible = "qcom,i2c-qup-v2.2.1";
2580 reg = <0x0c1b8000 0x6 2566 reg = <0x0c1b8000 0x600>;
2581 interrupts = <GIC_SPI 2567 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
2582 2568
2583 clocks = <&gcc GCC_BL 2569 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>,
2584 <&gcc GCC_BL 2570 <&gcc GCC_BLSP2_AHB_CLK>;
2585 clock-names = "core", 2571 clock-names = "core", "iface";
2586 dmas = <&blsp2_dma 12 2572 dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
2587 dma-names = "tx", "rx 2573 dma-names = "tx", "rx";
2588 pinctrl-names = "defa 2574 pinctrl-names = "default", "sleep";
2589 pinctrl-0 = <&blsp2_i 2575 pinctrl-0 = <&blsp2_i2c4_default>;
2590 pinctrl-1 = <&blsp2_i 2576 pinctrl-1 = <&blsp2_i2c4_sleep>;
2591 clock-frequency = <40 2577 clock-frequency = <400000>;
2592 2578
2593 status = "disabled"; 2579 status = "disabled";
2594 #address-cells = <1>; 2580 #address-cells = <1>;
2595 #size-cells = <0>; 2581 #size-cells = <0>;
2596 }; 2582 };
2597 2583
2598 blsp2_i2c5: i2c@c1b9000 { 2584 blsp2_i2c5: i2c@c1b9000 {
2599 compatible = "qcom,i2 2585 compatible = "qcom,i2c-qup-v2.2.1";
2600 reg = <0x0c1b9000 0x6 2586 reg = <0x0c1b9000 0x600>;
2601 interrupts = <GIC_SPI 2587 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
2602 2588
2603 clocks = <&gcc GCC_BL 2589 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,
2604 <&gcc GCC_BL 2590 <&gcc GCC_BLSP2_AHB_CLK>;
2605 clock-names = "core", 2591 clock-names = "core", "iface";
2606 dmas = <&blsp2_dma 14 2592 dmas = <&blsp2_dma 14>, <&blsp2_dma 15>;
2607 dma-names = "tx", "rx 2593 dma-names = "tx", "rx";
2608 pinctrl-names = "defa 2594 pinctrl-names = "default", "sleep";
2609 pinctrl-0 = <&blsp2_i 2595 pinctrl-0 = <&blsp2_i2c5_default>;
2610 pinctrl-1 = <&blsp2_i 2596 pinctrl-1 = <&blsp2_i2c5_sleep>;
2611 clock-frequency = <40 2597 clock-frequency = <400000>;
2612 2598
2613 status = "disabled"; 2599 status = "disabled";
2614 #address-cells = <1>; 2600 #address-cells = <1>;
2615 #size-cells = <0>; 2601 #size-cells = <0>;
2616 }; 2602 };
2617 2603
2618 blsp2_i2c6: i2c@c1ba000 { 2604 blsp2_i2c6: i2c@c1ba000 {
2619 compatible = "qcom,i2 2605 compatible = "qcom,i2c-qup-v2.2.1";
2620 reg = <0x0c1ba000 0x6 2606 reg = <0x0c1ba000 0x600>;
2621 interrupts = <GIC_SPI 2607 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
2622 2608
2623 clocks = <&gcc GCC_BL 2609 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>,
2624 <&gcc GCC_BL 2610 <&gcc GCC_BLSP2_AHB_CLK>;
2625 clock-names = "core", 2611 clock-names = "core", "iface";
2626 dmas = <&blsp2_dma 16 2612 dmas = <&blsp2_dma 16>, <&blsp2_dma 17>;
2627 dma-names = "tx", "rx 2613 dma-names = "tx", "rx";
2628 pinctrl-names = "defa 2614 pinctrl-names = "default", "sleep";
2629 pinctrl-0 = <&blsp2_i 2615 pinctrl-0 = <&blsp2_i2c6_default>;
2630 pinctrl-1 = <&blsp2_i 2616 pinctrl-1 = <&blsp2_i2c6_sleep>;
2631 clock-frequency = <40 2617 clock-frequency = <400000>;
2632 2618
2633 status = "disabled"; 2619 status = "disabled";
2634 #address-cells = <1>; 2620 #address-cells = <1>;
2635 #size-cells = <0>; 2621 #size-cells = <0>;
2636 }; 2622 };
2637 2623
2638 blsp2_spi1: spi@c1b5000 { 2624 blsp2_spi1: spi@c1b5000 {
2639 compatible = "qcom,sp 2625 compatible = "qcom,spi-qup-v2.2.1";
2640 reg = <0x0c1b5000 0x6 2626 reg = <0x0c1b5000 0x600>;
2641 interrupts = <GIC_SPI 2627 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
2642 2628
2643 clocks = <&gcc GCC_BL 2629 clocks = <&gcc GCC_BLSP2_QUP1_SPI_APPS_CLK>,
2644 <&gcc GCC_BL 2630 <&gcc GCC_BLSP2_AHB_CLK>;
2645 clock-names = "core", 2631 clock-names = "core", "iface";
2646 dmas = <&blsp2_dma 6> 2632 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>;
2647 dma-names = "tx", "rx 2633 dma-names = "tx", "rx";
2648 pinctrl-names = "defa 2634 pinctrl-names = "default";
2649 pinctrl-0 = <&blsp2_s 2635 pinctrl-0 = <&blsp2_spi1_default>;
2650 2636
2651 status = "disabled"; 2637 status = "disabled";
2652 #address-cells = <1>; 2638 #address-cells = <1>;
2653 #size-cells = <0>; 2639 #size-cells = <0>;
2654 }; 2640 };
2655 2641
2656 blsp2_spi2: spi@c1b6000 { 2642 blsp2_spi2: spi@c1b6000 {
2657 compatible = "qcom,sp 2643 compatible = "qcom,spi-qup-v2.2.1";
2658 reg = <0x0c1b6000 0x6 2644 reg = <0x0c1b6000 0x600>;
2659 interrupts = <GIC_SPI 2645 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
2660 2646
2661 clocks = <&gcc GCC_BL 2647 clocks = <&gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>,
2662 <&gcc GCC_BL 2648 <&gcc GCC_BLSP2_AHB_CLK>;
2663 clock-names = "core", 2649 clock-names = "core", "iface";
2664 dmas = <&blsp2_dma 8> 2650 dmas = <&blsp2_dma 8>, <&blsp2_dma 9>;
2665 dma-names = "tx", "rx 2651 dma-names = "tx", "rx";
2666 pinctrl-names = "defa 2652 pinctrl-names = "default";
2667 pinctrl-0 = <&blsp2_s 2653 pinctrl-0 = <&blsp2_spi2_default>;
2668 2654
2669 status = "disabled"; 2655 status = "disabled";
2670 #address-cells = <1>; 2656 #address-cells = <1>;
2671 #size-cells = <0>; 2657 #size-cells = <0>;
2672 }; 2658 };
2673 2659
2674 blsp2_spi3: spi@c1b7000 { 2660 blsp2_spi3: spi@c1b7000 {
2675 compatible = "qcom,sp 2661 compatible = "qcom,spi-qup-v2.2.1";
2676 reg = <0x0c1b7000 0x6 2662 reg = <0x0c1b7000 0x600>;
2677 interrupts = <GIC_SPI 2663 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
2678 2664
2679 clocks = <&gcc GCC_BL 2665 clocks = <&gcc GCC_BLSP2_QUP3_SPI_APPS_CLK>,
2680 <&gcc GCC_BL 2666 <&gcc GCC_BLSP2_AHB_CLK>;
2681 clock-names = "core", 2667 clock-names = "core", "iface";
2682 dmas = <&blsp2_dma 10 2668 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>;
2683 dma-names = "tx", "rx 2669 dma-names = "tx", "rx";
2684 pinctrl-names = "defa 2670 pinctrl-names = "default";
2685 pinctrl-0 = <&blsp2_s 2671 pinctrl-0 = <&blsp2_spi3_default>;
2686 2672
2687 status = "disabled"; 2673 status = "disabled";
2688 #address-cells = <1>; 2674 #address-cells = <1>;
2689 #size-cells = <0>; 2675 #size-cells = <0>;
2690 }; 2676 };
2691 2677
2692 blsp2_spi4: spi@c1b8000 { 2678 blsp2_spi4: spi@c1b8000 {
2693 compatible = "qcom,sp 2679 compatible = "qcom,spi-qup-v2.2.1";
2694 reg = <0x0c1b8000 0x6 2680 reg = <0x0c1b8000 0x600>;
2695 interrupts = <GIC_SPI 2681 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
2696 2682
2697 clocks = <&gcc GCC_BL 2683 clocks = <&gcc GCC_BLSP2_QUP4_SPI_APPS_CLK>,
2698 <&gcc GCC_BL 2684 <&gcc GCC_BLSP2_AHB_CLK>;
2699 clock-names = "core", 2685 clock-names = "core", "iface";
2700 dmas = <&blsp2_dma 12 2686 dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
2701 dma-names = "tx", "rx 2687 dma-names = "tx", "rx";
2702 pinctrl-names = "defa 2688 pinctrl-names = "default";
2703 pinctrl-0 = <&blsp2_s 2689 pinctrl-0 = <&blsp2_spi4_default>;
2704 2690
2705 status = "disabled"; 2691 status = "disabled";
2706 #address-cells = <1>; 2692 #address-cells = <1>;
2707 #size-cells = <0>; 2693 #size-cells = <0>;
2708 }; 2694 };
2709 2695
2710 blsp2_spi5: spi@c1b9000 { 2696 blsp2_spi5: spi@c1b9000 {
2711 compatible = "qcom,sp 2697 compatible = "qcom,spi-qup-v2.2.1";
2712 reg = <0x0c1b9000 0x6 2698 reg = <0x0c1b9000 0x600>;
2713 interrupts = <GIC_SPI 2699 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
2714 2700
2715 clocks = <&gcc GCC_BL 2701 clocks = <&gcc GCC_BLSP2_QUP5_SPI_APPS_CLK>,
2716 <&gcc GCC_BL 2702 <&gcc GCC_BLSP2_AHB_CLK>;
2717 clock-names = "core", 2703 clock-names = "core", "iface";
2718 dmas = <&blsp2_dma 14 2704 dmas = <&blsp2_dma 14>, <&blsp2_dma 15>;
2719 dma-names = "tx", "rx 2705 dma-names = "tx", "rx";
2720 pinctrl-names = "defa 2706 pinctrl-names = "default";
2721 pinctrl-0 = <&blsp2_s 2707 pinctrl-0 = <&blsp2_spi5_default>;
2722 2708
2723 status = "disabled"; 2709 status = "disabled";
2724 #address-cells = <1>; 2710 #address-cells = <1>;
2725 #size-cells = <0>; 2711 #size-cells = <0>;
2726 }; 2712 };
2727 2713
2728 blsp2_spi6: spi@c1ba000 { 2714 blsp2_spi6: spi@c1ba000 {
2729 compatible = "qcom,sp 2715 compatible = "qcom,spi-qup-v2.2.1";
2730 reg = <0x0c1ba000 0x6 2716 reg = <0x0c1ba000 0x600>;
2731 interrupts = <GIC_SPI 2717 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
2732 2718
2733 clocks = <&gcc GCC_BL 2719 clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>,
2734 <&gcc GCC_BL 2720 <&gcc GCC_BLSP2_AHB_CLK>;
2735 clock-names = "core", 2721 clock-names = "core", "iface";
2736 dmas = <&blsp2_dma 16 2722 dmas = <&blsp2_dma 16>, <&blsp2_dma 17>;
2737 dma-names = "tx", "rx 2723 dma-names = "tx", "rx";
2738 pinctrl-names = "defa 2724 pinctrl-names = "default";
2739 pinctrl-0 = <&blsp2_s 2725 pinctrl-0 = <&blsp2_spi6_default>;
2740 2726
2741 status = "disabled"; 2727 status = "disabled";
2742 #address-cells = <1>; 2728 #address-cells = <1>;
2743 #size-cells = <0>; 2729 #size-cells = <0>;
2744 }; 2730 };
2745 2731
2746 mmcc: clock-controller@c8c000 2732 mmcc: clock-controller@c8c0000 {
2747 compatible = "qcom,mm 2733 compatible = "qcom,mmcc-msm8998";
2748 #clock-cells = <1>; 2734 #clock-cells = <1>;
2749 #reset-cells = <1>; 2735 #reset-cells = <1>;
2750 #power-domain-cells = 2736 #power-domain-cells = <1>;
2751 reg = <0xc8c0000 0x40 2737 reg = <0xc8c0000 0x40000>;
2752 2738
2753 clock-names = "xo", 2739 clock-names = "xo",
2754 "gpll0" 2740 "gpll0",
2755 "dsi0ds 2741 "dsi0dsi",
2756 "dsi0by 2742 "dsi0byte",
2757 "dsi1ds 2743 "dsi1dsi",
2758 "dsi1by 2744 "dsi1byte",
2759 "hdmipl 2745 "hdmipll",
2760 "dplink 2746 "dplink",
2761 "dpvco" 2747 "dpvco",
2762 "gpll0_ 2748 "gpll0_div";
2763 clocks = <&rpmcc RPM_ 2749 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
2764 <&gcc GCC_MM 2750 <&gcc GCC_MMSS_GPLL0_CLK>,
2765 <&mdss_dsi0_ 2751 <&mdss_dsi0_phy 1>,
2766 <&mdss_dsi0_ 2752 <&mdss_dsi0_phy 0>,
2767 <&mdss_dsi1_ 2753 <&mdss_dsi1_phy 1>,
2768 <&mdss_dsi1_ 2754 <&mdss_dsi1_phy 0>,
2769 <0>, 2755 <0>,
2770 <0>, 2756 <0>,
2771 <0>, 2757 <0>,
2772 <&gcc GCC_MM 2758 <&gcc GCC_MMSS_GPLL0_DIV_CLK>;
2773 }; 2759 };
2774 2760
2775 mdss: display-subsystem@c9000 2761 mdss: display-subsystem@c900000 {
2776 compatible = "qcom,ms 2762 compatible = "qcom,msm8998-mdss";
2777 reg = <0x0c900000 0x1 2763 reg = <0x0c900000 0x1000>;
2778 reg-names = "mdss"; 2764 reg-names = "mdss";
2779 2765
2780 interrupts = <GIC_SPI 2766 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
2781 interrupt-controller; 2767 interrupt-controller;
2782 #interrupt-cells = <1 2768 #interrupt-cells = <1>;
2783 2769
2784 clocks = <&mmcc MDSS_ 2770 clocks = <&mmcc MDSS_AHB_CLK>,
2785 <&mmcc MDSS_ 2771 <&mmcc MDSS_AXI_CLK>,
2786 <&mmcc MDSS_ 2772 <&mmcc MDSS_MDP_CLK>;
2787 clock-names = "iface" 2773 clock-names = "iface",
2788 "bus", 2774 "bus",
2789 "core"; 2775 "core";
2790 2776
2791 power-domains = <&mmc 2777 power-domains = <&mmcc MDSS_GDSC>;
2792 iommus = <&mmss_smmu 2778 iommus = <&mmss_smmu 0>;
2793 2779
2794 #address-cells = <1>; 2780 #address-cells = <1>;
2795 #size-cells = <1>; 2781 #size-cells = <1>;
2796 ranges; 2782 ranges;
2797 2783
2798 status = "disabled"; 2784 status = "disabled";
2799 2785
2800 mdss_mdp: display-con 2786 mdss_mdp: display-controller@c901000 {
2801 compatible = 2787 compatible = "qcom,msm8998-dpu";
2802 reg = <0x0c90 2788 reg = <0x0c901000 0x8f000>,
2803 <0x0c9a 2789 <0x0c9a8e00 0xf0>,
2804 <0x0c9b 2790 <0x0c9b0000 0x2008>,
2805 <0x0c9b 2791 <0x0c9b8000 0x1040>;
2806 reg-names = " 2792 reg-names = "mdp",
2807 " 2793 "regdma",
2808 " 2794 "vbif",
2809 " 2795 "vbif_nrt";
2810 2796
2811 interrupt-par 2797 interrupt-parent = <&mdss>;
2812 interrupts = 2798 interrupts = <0>;
2813 2799
2814 clocks = <&mm 2800 clocks = <&mmcc MDSS_AHB_CLK>,
2815 <&mm 2801 <&mmcc MDSS_AXI_CLK>,
2816 <&mm 2802 <&mmcc MNOC_AHB_CLK>,
2817 <&mm 2803 <&mmcc MDSS_MDP_CLK>,
2818 <&mm 2804 <&mmcc MDSS_VSYNC_CLK>;
2819 clock-names = 2805 clock-names = "iface",
2820 2806 "bus",
2821 2807 "mnoc",
2822 2808 "core",
2823 2809 "vsync";
2824 2810
2825 assigned-cloc 2811 assigned-clocks = <&mmcc MDSS_VSYNC_CLK>;
2826 assigned-cloc 2812 assigned-clock-rates = <19200000>;
2827 2813
2828 operating-poi 2814 operating-points-v2 = <&mdp_opp_table>;
2829 power-domains 2815 power-domains = <&rpmpd MSM8998_VDDMX>;
2830 2816
2831 mdp_opp_table 2817 mdp_opp_table: opp-table {
2832 compa 2818 compatible = "operating-points-v2";
2833 2819
2834 opp-1 2820 opp-171430000 {
2835 2821 opp-hz = /bits/ 64 <171430000>;
2836 2822 required-opps = <&rpmpd_opp_low_svs>;
2837 }; 2823 };
2838 2824
2839 opp-2 2825 opp-275000000 {
2840 2826 opp-hz = /bits/ 64 <275000000>;
2841 2827 required-opps = <&rpmpd_opp_svs>;
2842 }; 2828 };
2843 2829
2844 opp-3 2830 opp-330000000 {
2845 2831 opp-hz = /bits/ 64 <330000000>;
2846 2832 required-opps = <&rpmpd_opp_nom>;
2847 }; 2833 };
2848 2834
2849 opp-4 2835 opp-412500000 {
2850 2836 opp-hz = /bits/ 64 <412500000>;
2851 2837 required-opps = <&rpmpd_opp_turbo>;
2852 }; 2838 };
2853 }; 2839 };
2854 2840
2855 ports { 2841 ports {
2856 #addr 2842 #address-cells = <1>;
2857 #size 2843 #size-cells = <0>;
2858 2844
2859 port@ 2845 port@0 {
2860 2846 reg = <0>;
2861 2847
2862 2848 dpu_intf1_out: endpoint {
2863 2849 remote-endpoint = <&mdss_dsi0_in>;
2864 2850 };
2865 }; 2851 };
2866 2852
2867 port@ 2853 port@1 {
2868 2854 reg = <1>;
2869 2855
2870 2856 dpu_intf2_out: endpoint {
2871 2857 remote-endpoint = <&mdss_dsi1_in>;
2872 2858 };
2873 }; 2859 };
2874 }; 2860 };
2875 }; 2861 };
2876 2862
2877 mdss_dsi0: dsi@c99400 2863 mdss_dsi0: dsi@c994000 {
2878 compatible = 2864 compatible = "qcom,msm8998-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2879 reg = <0x0c99 2865 reg = <0x0c994000 0x400>;
2880 reg-names = " 2866 reg-names = "dsi_ctrl";
2881 2867
2882 interrupt-par 2868 interrupt-parent = <&mdss>;
2883 interrupts = 2869 interrupts = <4>;
2884 2870
2885 clocks = <&mm 2871 clocks = <&mmcc MDSS_BYTE0_CLK>,
2886 <&mm 2872 <&mmcc MDSS_BYTE0_INTF_CLK>,
2887 <&mm 2873 <&mmcc MDSS_PCLK0_CLK>,
2888 <&mm 2874 <&mmcc MDSS_ESC0_CLK>,
2889 <&mm 2875 <&mmcc MDSS_AHB_CLK>,
2890 <&mm 2876 <&mmcc MDSS_AXI_CLK>;
2891 clock-names = 2877 clock-names = "byte",
2892 2878 "byte_intf",
2893 2879 "pixel",
2894 2880 "core",
2895 2881 "iface",
2896 2882 "bus";
2897 assigned-cloc 2883 assigned-clocks = <&mmcc BYTE0_CLK_SRC>,
2898 2884 <&mmcc PCLK0_CLK_SRC>;
2899 assigned-cloc 2885 assigned-clock-parents = <&mdss_dsi0_phy 0>,
2900 2886 <&mdss_dsi0_phy 1>;
2901 2887
2902 operating-poi 2888 operating-points-v2 = <&dsi_opp_table>;
2903 power-domains 2889 power-domains = <&rpmpd MSM8998_VDDCX>;
2904 2890
2905 phys = <&mdss 2891 phys = <&mdss_dsi0_phy>;
2906 phy-names = " 2892 phy-names = "dsi";
2907 2893
2908 #address-cell 2894 #address-cells = <1>;
2909 #size-cells = 2895 #size-cells = <0>;
2910 2896
2911 status = "dis 2897 status = "disabled";
2912 2898
2913 ports { 2899 ports {
2914 #addr 2900 #address-cells = <1>;
2915 #size 2901 #size-cells = <0>;
2916 2902
2917 port@ 2903 port@0 {
2918 2904 reg = <0>;
2919 2905
2920 2906 mdss_dsi0_in: endpoint {
2921 2907 remote-endpoint = <&dpu_intf1_out>;
2922 2908 };
2923 }; 2909 };
2924 2910
2925 port@ 2911 port@1 {
2926 2912 reg = <1>;
2927 2913
2928 2914 mdss_dsi0_out: endpoint {
2929 2915 };
2930 }; 2916 };
2931 }; 2917 };
2932 }; 2918 };
2933 2919
2934 mdss_dsi0_phy: phy@c9 2920 mdss_dsi0_phy: phy@c994400 {
2935 compatible = 2921 compatible = "qcom,dsi-phy-10nm-8998";
2936 reg = <0x0c99 2922 reg = <0x0c994400 0x200>,
2937 <0x0c99 2923 <0x0c994600 0x280>,
2938 <0x0c99 2924 <0x0c994a00 0x1e0>;
2939 reg-names = " 2925 reg-names = "dsi_phy",
2940 " 2926 "dsi_phy_lane",
2941 " 2927 "dsi_pll";
2942 2928
2943 clocks = <&mm 2929 clocks = <&mmcc MDSS_AHB_CLK>,
2944 <&rp 2930 <&rpmcc RPM_SMD_XO_CLK_SRC>;
2945 clock-names = 2931 clock-names = "iface", "ref";
2946 2932
2947 #clock-cells 2933 #clock-cells = <1>;
2948 #phy-cells = 2934 #phy-cells = <0>;
2949 2935
2950 status = "dis 2936 status = "disabled";
2951 }; 2937 };
2952 2938
2953 mdss_dsi1: dsi@c99600 2939 mdss_dsi1: dsi@c996000 {
2954 compatible = 2940 compatible = "qcom,msm8998-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2955 reg = <0x0c99 2941 reg = <0x0c996000 0x400>;
2956 reg-names = " 2942 reg-names = "dsi_ctrl";
2957 2943
2958 interrupt-par 2944 interrupt-parent = <&mdss>;
2959 interrupts = 2945 interrupts = <5>;
2960 2946
2961 clocks = <&mm 2947 clocks = <&mmcc MDSS_BYTE1_CLK>,
2962 <&mm 2948 <&mmcc MDSS_BYTE1_INTF_CLK>,
2963 <&mm 2949 <&mmcc MDSS_PCLK1_CLK>,
2964 <&mm 2950 <&mmcc MDSS_ESC1_CLK>,
2965 <&mm 2951 <&mmcc MDSS_AHB_CLK>,
2966 <&mm 2952 <&mmcc MDSS_AXI_CLK>;
2967 clock-names = 2953 clock-names = "byte",
2968 2954 "byte_intf",
2969 2955 "pixel",
2970 2956 "core",
2971 2957 "iface",
2972 2958 "bus";
2973 assigned-cloc 2959 assigned-clocks = <&mmcc BYTE1_CLK_SRC>,
2974 2960 <&mmcc PCLK1_CLK_SRC>;
2975 assigned-cloc 2961 assigned-clock-parents = <&mdss_dsi1_phy 0>,
2976 2962 <&mdss_dsi1_phy 1>;
2977 2963
2978 operating-poi 2964 operating-points-v2 = <&dsi_opp_table>;
2979 power-domains 2965 power-domains = <&rpmpd MSM8998_VDDCX>;
2980 2966
2981 phys = <&mdss 2967 phys = <&mdss_dsi1_phy>;
2982 phy-names = " 2968 phy-names = "dsi";
2983 2969
2984 #address-cell 2970 #address-cells = <1>;
2985 #size-cells = 2971 #size-cells = <0>;
2986 2972
2987 status = "dis 2973 status = "disabled";
2988 2974
2989 ports { 2975 ports {
2990 #addr 2976 #address-cells = <1>;
2991 #size 2977 #size-cells = <0>;
2992 2978
2993 port@ 2979 port@0 {
2994 2980 reg = <0>;
2995 2981
2996 2982 mdss_dsi1_in: endpoint {
2997 2983 remote-endpoint = <&dpu_intf2_out>;
2998 2984 };
2999 }; 2985 };
3000 2986
3001 port@ 2987 port@1 {
3002 2988 reg = <1>;
3003 2989
3004 2990 mdss_dsi1_out: endpoint {
3005 2991 };
3006 }; 2992 };
3007 }; 2993 };
3008 }; 2994 };
3009 2995
3010 mdss_dsi1_phy: phy@c9 2996 mdss_dsi1_phy: phy@c996400 {
3011 compatible = 2997 compatible = "qcom,dsi-phy-10nm-8998";
3012 reg = <0x0c99 2998 reg = <0x0c996400 0x200>,
3013 <0x0c99 2999 <0x0c996600 0x280>,
3014 <0x0c99 3000 <0x0c996a00 0x10e>;
3015 reg-names = " 3001 reg-names = "dsi_phy",
3016 " 3002 "dsi_phy_lane",
3017 " 3003 "dsi_pll";
3018 3004
3019 clocks = <&mm 3005 clocks = <&mmcc MDSS_AHB_CLK>,
3020 <&rp 3006 <&rpmcc RPM_SMD_XO_CLK_SRC>;
3021 clock-names = 3007 clock-names = "iface",
3022 3008 "ref";
3023 3009
3024 #clock-cells 3010 #clock-cells = <1>;
3025 #phy-cells = 3011 #phy-cells = <0>;
3026 3012
3027 status = "dis 3013 status = "disabled";
3028 }; 3014 };
3029 }; 3015 };
3030 3016
3031 venus: video-codec@cc00000 { <<
3032 compatible = "qcom,ms <<
3033 reg = <0x0cc00000 0xf <<
3034 interrupts = <GIC_SPI <<
3035 power-domains = <&mmc <<
3036 clocks = <&mmcc VIDEO <<
3037 <&mmcc VIDEO <<
3038 <&mmcc VIDEO <<
3039 <&mmcc VIDEO <<
3040 clock-names = "core", <<
3041 iommus = <&mmss_smmu <<
3042 <&mmss_smmu <<
3043 <&mmss_smmu <<
3044 <&mmss_smmu <<
3045 <&mmss_smmu <<
3046 <&mmss_smmu <<
3047 <&mmss_smmu <<
3048 <&mmss_smmu <<
3049 <&mmss_smmu <<
3050 <&mmss_smmu <<
3051 <&mmss_smmu <<
3052 <&mmss_smmu <<
3053 <&mmss_smmu <<
3054 <&mmss_smmu <<
3055 <&mmss_smmu <<
3056 <&mmss_smmu <<
3057 <&mmss_smmu <<
3058 <&mmss_smmu <<
3059 <&mmss_smmu <<
3060 <&mmss_smmu <<
3061 memory-region = <&ven <<
3062 status = "disabled"; <<
3063 <<
3064 video-decoder { <<
3065 compatible = <<
3066 clocks = <&mm <<
3067 clock-names = <<
3068 power-domains <<
3069 }; <<
3070 <<
3071 video-encoder { <<
3072 compatible = <<
3073 clocks = <&mm <<
3074 clock-names = <<
3075 power-domains <<
3076 }; <<
3077 }; <<
3078 <<
3079 mmss_smmu: iommu@cd00000 { 3017 mmss_smmu: iommu@cd00000 {
3080 compatible = "qcom,ms 3018 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
3081 reg = <0x0cd00000 0x4 3019 reg = <0x0cd00000 0x40000>;
3082 #iommu-cells = <1>; 3020 #iommu-cells = <1>;
3083 3021
3084 clocks = <&mmcc MNOC_ 3022 clocks = <&mmcc MNOC_AHB_CLK>,
3085 <&mmcc BIMC_ 3023 <&mmcc BIMC_SMMU_AHB_CLK>,
3086 <&mmcc BIMC_ 3024 <&mmcc BIMC_SMMU_AXI_CLK>;
3087 clock-names = "iface- 3025 clock-names = "iface-mm",
3088 "iface- 3026 "iface-smmu",
3089 "bus-sm 3027 "bus-smmu";
3090 3028
3091 #global-interrupts = 3029 #global-interrupts = <0>;
3092 interrupts = 3030 interrupts =
3093 <GIC_SPI 263 3031 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
3094 <GIC_SPI 266 3032 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
3095 <GIC_SPI 267 3033 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
3096 <GIC_SPI 268 3034 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
3097 <GIC_SPI 244 3035 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
3098 <GIC_SPI 245 3036 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
3099 <GIC_SPI 247 3037 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
3100 <GIC_SPI 248 3038 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
3101 <GIC_SPI 249 3039 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
3102 <GIC_SPI 250 3040 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
3103 <GIC_SPI 251 3041 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
3104 <GIC_SPI 252 3042 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
3105 <GIC_SPI 253 3043 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
3106 <GIC_SPI 254 3044 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
3107 <GIC_SPI 255 3045 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
3108 <GIC_SPI 256 3046 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
3109 <GIC_SPI 260 3047 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
3110 <GIC_SPI 261 3048 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
3111 <GIC_SPI 262 3049 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
3112 <GIC_SPI 272 3050 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
3113 3051
3114 power-domains = <&mmc 3052 power-domains = <&mmcc BIMC_SMMU_GDSC>;
3115 }; 3053 };
3116 3054
3117 remoteproc_adsp: remoteproc@1 3055 remoteproc_adsp: remoteproc@17300000 {
3118 compatible = "qcom,ms 3056 compatible = "qcom,msm8998-adsp-pas";
3119 reg = <0x17300000 0x4 3057 reg = <0x17300000 0x4040>;
3120 3058
3121 interrupts-extended = 3059 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
3122 3060 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3123 3061 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3124 3062 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3125 3063 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
3126 interrupt-names = "wd 3064 interrupt-names = "wdog", "fatal", "ready",
3127 "ha 3065 "handover", "stop-ack";
3128 3066
3129 clocks = <&rpmcc RPM_ 3067 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
3130 clock-names = "xo"; 3068 clock-names = "xo";
3131 3069
3132 memory-region = <&ads 3070 memory-region = <&adsp_mem>;
3133 3071
3134 qcom,smem-states = <& 3072 qcom,smem-states = <&adsp_smp2p_out 0>;
3135 qcom,smem-state-names 3073 qcom,smem-state-names = "stop";
3136 3074
3137 power-domains = <&rpm 3075 power-domains = <&rpmpd MSM8998_VDDCX>;
3138 power-domain-names = 3076 power-domain-names = "cx";
3139 3077
3140 status = "disabled"; 3078 status = "disabled";
3141 3079
3142 glink-edge { 3080 glink-edge {
3143 interrupts = 3081 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
3144 label = "lpas 3082 label = "lpass";
3145 qcom,remote-p 3083 qcom,remote-pid = <2>;
3146 mboxes = <&ap 3084 mboxes = <&apcs_glb 9>;
3147 }; 3085 };
3148 }; 3086 };
3149 3087
3150 apcs_glb: mailbox@17911000 { 3088 apcs_glb: mailbox@17911000 {
3151 compatible = "qcom,ms 3089 compatible = "qcom,msm8998-apcs-hmss-global",
3152 "qcom,ms 3090 "qcom,msm8994-apcs-kpss-global";
3153 reg = <0x17911000 0x1 3091 reg = <0x17911000 0x1000>;
3154 3092
3155 #mbox-cells = <1>; 3093 #mbox-cells = <1>;
3156 }; 3094 };
3157 3095
3158 timer@17920000 { 3096 timer@17920000 {
3159 #address-cells = <1>; 3097 #address-cells = <1>;
3160 #size-cells = <1>; 3098 #size-cells = <1>;
3161 ranges; 3099 ranges;
3162 compatible = "arm,arm 3100 compatible = "arm,armv7-timer-mem";
3163 reg = <0x17920000 0x1 3101 reg = <0x17920000 0x1000>;
3164 3102
3165 frame@17921000 { 3103 frame@17921000 {
3166 frame-number 3104 frame-number = <0>;
3167 interrupts = 3105 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
3168 3106 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
3169 reg = <0x1792 3107 reg = <0x17921000 0x1000>,
3170 <0x1792 3108 <0x17922000 0x1000>;
3171 }; 3109 };
3172 3110
3173 frame@17923000 { 3111 frame@17923000 {
3174 frame-number 3112 frame-number = <1>;
3175 interrupts = 3113 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
3176 reg = <0x1792 3114 reg = <0x17923000 0x1000>;
3177 status = "dis 3115 status = "disabled";
3178 }; 3116 };
3179 3117
3180 frame@17924000 { 3118 frame@17924000 {
3181 frame-number 3119 frame-number = <2>;
3182 interrupts = 3120 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
3183 reg = <0x1792 3121 reg = <0x17924000 0x1000>;
3184 status = "dis 3122 status = "disabled";
3185 }; 3123 };
3186 3124
3187 frame@17925000 { 3125 frame@17925000 {
3188 frame-number 3126 frame-number = <3>;
3189 interrupts = 3127 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3190 reg = <0x1792 3128 reg = <0x17925000 0x1000>;
3191 status = "dis 3129 status = "disabled";
3192 }; 3130 };
3193 3131
3194 frame@17926000 { 3132 frame@17926000 {
3195 frame-number 3133 frame-number = <4>;
3196 interrupts = 3134 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3197 reg = <0x1792 3135 reg = <0x17926000 0x1000>;
3198 status = "dis 3136 status = "disabled";
3199 }; 3137 };
3200 3138
3201 frame@17927000 { 3139 frame@17927000 {
3202 frame-number 3140 frame-number = <5>;
3203 interrupts = 3141 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3204 reg = <0x1792 3142 reg = <0x17927000 0x1000>;
3205 status = "dis 3143 status = "disabled";
3206 }; 3144 };
3207 3145
3208 frame@17928000 { 3146 frame@17928000 {
3209 frame-number 3147 frame-number = <6>;
3210 interrupts = 3148 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
3211 reg = <0x1792 3149 reg = <0x17928000 0x1000>;
3212 status = "dis 3150 status = "disabled";
3213 }; 3151 };
3214 }; 3152 };
3215 3153
3216 intc: interrupt-controller@17 3154 intc: interrupt-controller@17a00000 {
3217 compatible = "arm,gic 3155 compatible = "arm,gic-v3";
3218 reg = <0x17a00000 0x1 3156 reg = <0x17a00000 0x10000>, /* GICD */
3219 <0x17b00000 0x1 3157 <0x17b00000 0x100000>; /* GICR * 8 */
3220 #interrupt-cells = <3 3158 #interrupt-cells = <3>;
3221 #address-cells = <1>; 3159 #address-cells = <1>;
3222 #size-cells = <1>; 3160 #size-cells = <1>;
3223 ranges; 3161 ranges;
3224 interrupt-controller; 3162 interrupt-controller;
3225 #redistributor-region 3163 #redistributor-regions = <1>;
3226 redistributor-stride 3164 redistributor-stride = <0x0 0x20000>;
3227 interrupts = <GIC_PPI 3165 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3228 }; 3166 };
3229 3167
3230 wifi: wifi@18800000 { 3168 wifi: wifi@18800000 {
3231 compatible = "qcom,wc 3169 compatible = "qcom,wcn3990-wifi";
3232 status = "disabled"; 3170 status = "disabled";
3233 reg = <0x18800000 0x8 3171 reg = <0x18800000 0x800000>;
3234 reg-names = "membase" 3172 reg-names = "membase";
3235 memory-region = <&wla 3173 memory-region = <&wlan_msa_mem>;
3236 clocks = <&rpmcc RPM_ 3174 clocks = <&rpmcc RPM_SMD_RF_CLK2_PIN>;
3237 clock-names = "cxo_re 3175 clock-names = "cxo_ref_clk_pin";
3238 interrupts = 3176 interrupts =
3239 <GIC_SPI 413 3177 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
3240 <GIC_SPI 414 3178 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
3241 <GIC_SPI 415 3179 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
3242 <GIC_SPI 416 3180 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
3243 <GIC_SPI 417 3181 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
3244 <GIC_SPI 418 3182 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
3245 <GIC_SPI 420 3183 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
3246 <GIC_SPI 421 3184 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
3247 <GIC_SPI 422 3185 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
3248 <GIC_SPI 423 3186 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
3249 <GIC_SPI 424 3187 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
3250 <GIC_SPI 425 3188 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
3251 iommus = <&anoc2_smmu 3189 iommus = <&anoc2_smmu 0x1900>,
3252 <&anoc2_smmu 3190 <&anoc2_smmu 0x1901>;
3253 qcom,snoc-host-cap-8b 3191 qcom,snoc-host-cap-8bit-quirk;
3254 qcom,no-msa-ready-ind <<
3255 }; 3192 };
3256 }; 3193 };
3257 }; 3194 };
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