1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3
2 /*
3 * Copyright (c) 2023, Linaro Ltd
4 *
5 * Based on sm6115.dtsi and previous efforts b
6 */
7
8 #include <dt-bindings/clock/qcom,dispcc-qcm229
9 #include <dt-bindings/clock/qcom,gcc-qcm2290.h
10 #include <dt-bindings/clock/qcom,qcm2290-gpucc
11 #include <dt-bindings/clock/qcom,rpmcc.h>
12 #include <dt-bindings/dma/qcom-gpi.h>
13 #include <dt-bindings/firmware/qcom,scm.h>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/interrupt-controller/arm
16 #include <dt-bindings/interconnect/qcom,qcm229
17 #include <dt-bindings/interconnect/qcom,rpm-ic
18 #include <dt-bindings/power/qcom-rpmpd.h>
19
20 / {
21 interrupt-parent = <&intc>;
22
23 #address-cells = <2>;
24 #size-cells = <2>;
25
26 chosen { };
27
28 clocks {
29 xo_board: xo-board {
30 compatible = "fixed-cl
31 #clock-cells = <0>;
32 };
33
34 sleep_clk: sleep-clk {
35 compatible = "fixed-cl
36 clock-frequency = <327
37 #clock-cells = <0>;
38 };
39 };
40
41 cpus {
42 #address-cells = <2>;
43 #size-cells = <0>;
44
45 CPU0: cpu@0 {
46 device_type = "cpu";
47 compatible = "arm,cort
48 reg = <0x0 0x0>;
49 clocks = <&cpufreq_hw
50 capacity-dmips-mhz = <
51 dynamic-power-coeffici
52 enable-method = "psci"
53 next-level-cache = <&L
54 qcom,freq-domain = <&c
55 power-domains = <&CPU_
56 power-domain-names = "
57 L2_0: l2-cache {
58 compatible = "
59 cache-level =
60 cache-unified;
61 };
62 };
63
64 CPU1: cpu@1 {
65 device_type = "cpu";
66 compatible = "arm,cort
67 reg = <0x0 0x1>;
68 clocks = <&cpufreq_hw
69 capacity-dmips-mhz = <
70 dynamic-power-coeffici
71 enable-method = "psci"
72 next-level-cache = <&L
73 qcom,freq-domain = <&c
74 power-domains = <&CPU_
75 power-domain-names = "
76 };
77
78 CPU2: cpu@2 {
79 device_type = "cpu";
80 compatible = "arm,cort
81 reg = <0x0 0x2>;
82 clocks = <&cpufreq_hw
83 capacity-dmips-mhz = <
84 dynamic-power-coeffici
85 enable-method = "psci"
86 next-level-cache = <&L
87 qcom,freq-domain = <&c
88 power-domains = <&CPU_
89 power-domain-names = "
90 };
91
92 CPU3: cpu@3 {
93 device_type = "cpu";
94 compatible = "arm,cort
95 reg = <0x0 0x3>;
96 clocks = <&cpufreq_hw
97 capacity-dmips-mhz = <
98 dynamic-power-coeffici
99 enable-method = "psci"
100 next-level-cache = <&L
101 qcom,freq-domain = <&c
102 power-domains = <&CPU_
103 power-domain-names = "
104 };
105
106 cpu-map {
107 cluster0 {
108 core0 {
109 cpu =
110 };
111
112 core1 {
113 cpu =
114 };
115
116 core2 {
117 cpu =
118 };
119
120 core3 {
121 cpu =
122 };
123 };
124 };
125
126 domain-idle-states {
127 CLUSTER_SLEEP: cluster
128 compatible = "
129 arm,psci-suspe
130 entry-latency-
131 exit-latency-u
132 min-residency-
133 };
134 };
135
136 idle-states {
137 entry-method = "psci";
138
139 CPU_SLEEP: cpu-sleep-0
140 compatible = "
141 idle-state-nam
142 arm,psci-suspe
143 entry-latency-
144 exit-latency-u
145 min-residency-
146 local-timer-st
147 };
148 };
149 };
150
151 firmware {
152 scm: scm {
153 compatible = "qcom,scm
154 clocks = <&rpmcc RPM_S
155 clock-names = "core";
156 #reset-cells = <1>;
157 interconnects = <&syst
158 &bimc
159 };
160 };
161
162 memory@40000000 {
163 device_type = "memory";
164 /* We expect the bootloader to
165 reg = <0 0x40000000 0 0>;
166 };
167
168 pmu {
169 compatible = "arm,cortex-a53-p
170 interrupts = <GIC_PPI 6 IRQ_TY
171 };
172
173 psci {
174 compatible = "arm,psci-1.0";
175 method = "smc";
176
177 CPU_PD0: power-domain-cpu0 {
178 #power-domain-cells =
179 power-domains = <&CLUS
180 domain-idle-states = <
181 };
182
183 CPU_PD1: power-domain-cpu1 {
184 #power-domain-cells =
185 power-domains = <&CLUS
186 domain-idle-states = <
187 };
188
189 CPU_PD2: power-domain-cpu2 {
190 #power-domain-cells =
191 power-domains = <&CLUS
192 domain-idle-states = <
193 };
194
195 CPU_PD3: power-domain-cpu3 {
196 #power-domain-cells =
197 power-domains = <&CLUS
198 domain-idle-states = <
199 };
200
201 CLUSTER_PD: power-domain-cpu-c
202 #power-domain-cells =
203 power-domains = <&mpm>
204 domain-idle-states = <
205 };
206 };
207
208 rpm: remoteproc {
209 compatible = "qcom,qcm2290-rpm
210
211 glink-edge {
212 compatible = "qcom,gli
213 interrupts = <GIC_SPI
214 qcom,rpm-msg-ram = <&r
215 mboxes = <&apcs_glb 0>
216
217 rpm_requests: rpm-requ
218 compatible = "
219 qcom,glink-cha
220
221 rpmcc: clock-c
222 compat
223 clocks
224 clock-
225 #clock
226 };
227
228 rpmpd: power-c
229 compat
230 #power
231 operat
232
233 rpmpd_
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267 };
268 };
269 };
270 };
271
272 mpm: interrupt-controller {
273 compatible = "qcom,mpm
274 qcom,rpm-msg-ram = <&a
275 interrupts = <GIC_SPI
276 mboxes = <&apcs_glb 1>
277 interrupt-controller;
278 #interrupt-cells = <2>
279 #power-domain-cells =
280 interrupt-parent = <&i
281 qcom,mpm-pin-count = <
282 qcom,mpm-pin-map = <2
283 <5
284 <12
285 <24
286 <86
287 <90
288 };
289 };
290
291 reserved_memory: reserved-memory {
292 #address-cells = <2>;
293 #size-cells = <2>;
294 ranges;
295
296 hyp_mem: hyp@45700000 {
297 reg = <0x0 0x45700000
298 no-map;
299 };
300
301 xbl_aop_mem: xbl-aop@45e00000
302 reg = <0x0 0x45e00000
303 no-map;
304 };
305
306 sec_apps_mem: sec-apps@45fff00
307 reg = <0x0 0x45fff000
308 no-map;
309 };
310
311 smem_mem: smem@46000000 {
312 compatible = "qcom,sme
313 reg = <0x0 0x46000000
314 no-map;
315
316 hwlocks = <&tcsr_mutex
317 qcom,rpm-msg-ram = <&r
318 };
319
320 pil_modem_mem: modem@4ab00000
321 reg = <0x0 0x4ab00000
322 no-map;
323 };
324
325 pil_video_mem: video@51400000
326 reg = <0x0 0x51400000
327 no-map;
328 };
329
330 wlan_msa_mem: wlan-msa@5190000
331 reg = <0x0 0x51900000
332 no-map;
333 };
334
335 pil_adsp_mem: adsp@51a00000 {
336 reg = <0x0 0x51a00000
337 no-map;
338 };
339
340 pil_ipa_fw_mem: ipa-fw@5360000
341 reg = <0x0 0x53600000
342 no-map;
343 };
344
345 pil_ipa_gsi_mem: ipa-gsi@53610
346 reg = <0x0 0x53610000
347 no-map;
348 };
349
350 pil_gpu_mem: zap@53615000 {
351 compatible = "shared-d
352 reg = <0x0 0x53615000
353 no-map;
354 };
355
356 cont_splash_memory: framebuffe
357 reg = <0x0 0x5c000000
358 no-map;
359 };
360
361 dfps_data_memory: dpfs-data@5c
362 reg = <0x0 0x5cf00000
363 no-map;
364 };
365
366 removed_mem: reserved@60000000
367 reg = <0x0 0x60000000
368 no-map;
369 };
370
371 rmtfs_mem: memory@89b01000 {
372 compatible = "qcom,rmt
373 reg = <0x0 0x89b01000
374 no-map;
375
376 qcom,client-id = <1>;
377 qcom,vmid = <QCOM_SCM_
378 };
379 };
380
381 smp2p-adsp {
382 compatible = "qcom,smp2p";
383 qcom,smem = <443>, <429>;
384
385 interrupts = <GIC_SPI 279 IRQ_
386
387 mboxes = <&apcs_glb 10>;
388
389 qcom,local-pid = <0>;
390 qcom,remote-pid = <2>;
391
392 adsp_smp2p_out: master-kernel
393 qcom,entry-name = "mas
394 #qcom,smem-state-cells
395 };
396
397 adsp_smp2p_in: slave-kernel {
398 qcom,entry-name = "sla
399 interrupt-controller;
400 #interrupt-cells = <2>
401 };
402 };
403
404 smp2p-mpss {
405 compatible = "qcom,smp2p";
406 qcom,smem = <435>, <428>;
407
408 interrupts = <GIC_SPI 70 IRQ_T
409
410 mboxes = <&apcs_glb 14>;
411
412 qcom,local-pid = <0>;
413 qcom,remote-pid = <1>;
414
415 modem_smp2p_out: master-kernel
416 qcom,entry-name = "mas
417 #qcom,smem-state-cells
418 };
419
420 modem_smp2p_in: slave-kernel {
421 qcom,entry-name = "sla
422 interrupt-controller;
423 #interrupt-cells = <2>
424 };
425
426 wlan_smp2p_in: wlan-wpss-to-ap
427 qcom,entry-name = "wla
428 interrupt-controller;
429 #interrupt-cells = <2>
430 };
431 };
432
433 soc: soc@0 {
434 compatible = "simple-bus";
435 #address-cells = <2>;
436 #size-cells = <2>;
437 ranges = <0 0 0 0 0x10 0>;
438 dma-ranges = <0 0 0 0 0x10 0>;
439
440 tcsr_mutex: hwlock@340000 {
441 compatible = "qcom,tcs
442 reg = <0x0 0x00340000
443 #hwlock-cells = <1>;
444 };
445
446 tcsr_regs: syscon@3c0000 {
447 compatible = "qcom,qcm
448 reg = <0x0 0x003c0000
449 };
450
451 tlmm: pinctrl@500000 {
452 compatible = "qcom,qcm
453 reg = <0x0 0x00500000
454 interrupts = <GIC_SPI
455 gpio-controller;
456 gpio-ranges = <&tlmm 0
457 wakeup-parent = <&mpm>
458 #gpio-cells = <2>;
459 interrupt-controller;
460 #interrupt-cells = <2>
461
462 qup_i2c0_default: qup-
463 pins = "gpio0"
464 function = "qu
465 drive-strength
466 bias-pull-up;
467 };
468
469 qup_i2c1_default: qup-
470 pins = "gpio4"
471 function = "qu
472 drive-strength
473 bias-pull-up;
474 };
475
476 qup_i2c2_default: qup-
477 pins = "gpio6"
478 function = "qu
479 drive-strength
480 bias-pull-up;
481 };
482
483 qup_i2c3_default: qup-
484 pins = "gpio8"
485 function = "qu
486 drive-strength
487 bias-pull-up;
488 };
489
490 qup_i2c4_default: qup-
491 pins = "gpio12
492 function = "qu
493 drive-strength
494 bias-pull-up;
495 };
496
497 qup_i2c5_default: qup-
498 pins = "gpio14
499 function = "qu
500 drive-strength
501 bias-pull-up;
502 };
503
504 qup_spi0_default: qup-
505 pins = "gpio0"
506 function = "qu
507 drive-strength
508 bias-pull-up;
509 };
510
511 qup_spi1_default: qup-
512 pins = "gpio4"
513 function = "qu
514 drive-strength
515 bias-pull-up;
516 };
517
518 qup_spi2_default: qup-
519 pins = "gpio6"
520 function = "qu
521 drive-strength
522 bias-pull-up;
523 };
524
525 qup_spi3_default: qup-
526 pins = "gpio8"
527 function = "qu
528 drive-strength
529 bias-pull-up;
530 };
531
532 qup_spi4_default: qup-
533 pins = "gpio12
534 function = "qu
535 drive-strength
536 bias-pull-up;
537 };
538
539 qup_spi5_default: qup-
540 pins = "gpio14
541 function = "qu
542 drive-strength
543 bias-pull-up;
544 };
545
546 qup_uart0_default: qup
547 pins = "gpio0"
548 function = "qu
549 drive-strength
550 bias-disable;
551 };
552
553 qup_uart4_default: qup
554 pins = "gpio12
555 function = "qu
556 drive-strength
557 bias-disable;
558 };
559
560 sdc1_state_on: sdc1-on
561 clk-pins {
562 pins =
563 drive-
564 bias-d
565 };
566
567 cmd-pins {
568 pins =
569 drive-
570 bias-p
571 };
572
573 data-pins {
574 pins =
575 drive-
576 bias-p
577 };
578
579 rclk-pins {
580 pins =
581 bias-p
582 };
583 };
584
585 sdc1_state_off: sdc1-o
586 clk-pins {
587 pins =
588 drive-
589 bias-d
590 };
591
592 cmd-pins {
593 pins =
594 drive-
595 bias-p
596 };
597
598 data-pins {
599 pins =
600 drive-
601 bias-p
602 };
603
604 rclk-pins {
605 pins =
606 bias-p
607 };
608 };
609
610 sdc2_state_on: sdc2-on
611 clk-pins {
612 pins =
613 drive-
614 bias-d
615 };
616
617 cmd-pins {
618 pins =
619 drive-
620 bias-p
621 };
622
623 data-pins {
624 pins =
625 drive-
626 bias-p
627 };
628 };
629
630 sdc2_state_off: sdc2-o
631 clk-pins {
632 pins =
633 drive-
634 bias-d
635 };
636
637 cmd-pins {
638 pins =
639 drive-
640 bias-p
641 };
642
643 data-pins {
644 pins =
645 drive-
646 bias-p
647 };
648 };
649 };
650
651 gcc: clock-controller@1400000
652 compatible = "qcom,gcc
653 reg = <0x0 0x01400000
654 clocks = <&rpmcc RPM_S
655 clock-names = "bi_tcxo
656 #clock-cells = <1>;
657 #reset-cells = <1>;
658 #power-domain-cells =
659 };
660
661 usb_hsphy: phy@1613000 {
662 compatible = "qcom,qcm
663 reg = <0x0 0x01613000
664
665 clocks = <&gcc GCC_AHB
666 <&rpmcc RPM_S
667 clock-names = "cfg_ahb
668
669 resets = <&gcc GCC_QUS
670 nvmem-cells = <&qusb2_
671 #phy-cells = <0>;
672
673 status = "disabled";
674 };
675
676 usb_qmpphy: phy@1615000 {
677 compatible = "qcom,qcm
678 reg = <0x0 0x01615000
679
680 clocks = <&gcc GCC_AHB
681 <&gcc GCC_USB
682 <&gcc GCC_USB
683 <&gcc GCC_USB
684 clock-names = "cfg_ahb
685 "ref",
686 "com_aux
687 "pipe";
688
689 resets = <&gcc GCC_USB
690 <&gcc GCC_USB
691 reset-names = "phy",
692 "phy_phy
693
694 #clock-cells = <0>;
695 clock-output-names = "
696
697 #phy-cells = <0>;
698 orientation-switch;
699
700 qcom,tcsr-reg = <&tcsr
701
702 status = "disabled";
703
704 ports {
705 #address-cells
706 #size-cells =
707
708 port@0 {
709 reg =
710
711 usb_qm
712 };
713 };
714
715 port@1 {
716 reg =
717
718 usb_qm
719
720 };
721 };
722 };
723 };
724
725 system_noc: interconnect@18800
726 compatible = "qcom,qcm
727 reg = <0x0 0x01880000
728 #interconnect-cells =
729
730 qup_virt: interconnect
731 compatible = "
732 #interconnect-
733 };
734
735 mmnrt_virt: interconne
736 compatible = "
737 #interconnect-
738 };
739
740 mmrt_virt: interconnec
741 compatible = "
742 #interconnect-
743 };
744 };
745
746 config_noc: interconnect@19000
747 compatible = "qcom,qcm
748 reg = <0x0 0x01900000
749 #interconnect-cells =
750 };
751
752 qfprom@1b44000 {
753 compatible = "qcom,qcm
754 reg = <0x0 0x01b44000
755 #address-cells = <1>;
756 #size-cells = <1>;
757
758 qusb2_hstx_trim: hstx-
759 reg = <0x25b 0
760 bits = <1 4>;
761 };
762
763 gpu_speed_bin: gpu-spe
764 reg = <0x2006
765 bits = <5 8>;
766 };
767 };
768
769 pmu@1b8e300 {
770 compatible = "qcom,qcm
771 reg = <0x0 0x01b8e300
772 interrupts = <GIC_SPI
773
774 operating-points-v2 =
775 interconnects = <&bimc
776 &bimc
777
778 cpu_bwmon_opp_table: o
779 compatible = "
780
781 opp-0 {
782 opp-pe
783 };
784
785 opp-1 {
786 opp-pe
787 };
788
789 opp-2 {
790 opp-pe
791 };
792
793 opp-3 {
794 opp-pe
795 };
796
797 opp-4 {
798 opp-pe
799 };
800
801 opp-5 {
802 opp-pe
803 };
804
805 opp-6 {
806 opp-pe
807 };
808
809 opp-7 {
810 opp-pe
811 };
812
813 opp-8 {
814 opp-pe
815 };
816
817 opp-9 {
818 opp-pe
819 };
820 };
821 };
822
823 spmi_bus: spmi@1c40000 {
824 compatible = "qcom,spm
825 reg = <0x0 0x01c40000
826 <0x0 0x01e00000
827 <0x0 0x03e00000
828 <0x0 0x03f00000
829 <0x0 0x01c0a000
830 reg-names = "core",
831 "chnls",
832 "obsrvr",
833 "intr",
834 "cnfg";
835 interrupts-extended =
836 interrupt-names = "per
837 qcom,ee = <0>;
838 qcom,channel = <0>;
839 #address-cells = <2>;
840 #size-cells = <0>;
841 interrupt-controller;
842 #interrupt-cells = <4>
843 };
844
845 tsens0: thermal-sensor@4411000
846 compatible = "qcom,qcm
847 reg = <0x0 0x04411000
848 <0x0 0x04410000
849 #qcom,sensors = <10>;
850 interrupts-extended =
851
852 interrupt-names = "upl
853 #thermal-sensor-cells
854 };
855
856 rng: rng@4453000 {
857 compatible = "qcom,prn
858 reg = <0x0 0x04453000
859 clocks = <&rpmcc RPM_S
860 clock-names = "core";
861 };
862
863 bimc: interconnect@4480000 {
864 compatible = "qcom,qcm
865 reg = <0x0 0x04480000
866 #interconnect-cells =
867 };
868
869 rpm_msg_ram: sram@45f0000 {
870 compatible = "qcom,rpm
871 reg = <0x0 0x045f0000
872 #address-cells = <1>;
873 #size-cells = <1>;
874 ranges = <0 0x0 0x045f
875
876 apss_mpm: sram@1b8 {
877 reg = <0x1b8 0
878 };
879 };
880
881 sram@4690000 {
882 compatible = "qcom,rpm
883 reg = <0x0 0x04690000
884 };
885
886 sdhc_1: mmc@4744000 {
887 compatible = "qcom,qcm
888 reg = <0x0 0x04744000
889 <0x0 0x04745000
890 <0x0 0x04748000
891 reg-names = "hc",
892 "cqhci",
893 "ice";
894
895 interrupts = <GIC_SPI
896 <GIC_SPI
897 interrupt-names = "hc_
898
899 clocks = <&gcc GCC_SDC
900 <&gcc GCC_SDC
901 <&rpmcc RPM_S
902 <&gcc GCC_SDC
903 clock-names = "iface",
904 "core",
905 "xo",
906 "ice";
907
908 resets = <&gcc GCC_SDC
909
910 power-domains = <&rpmp
911 operating-points-v2 =
912 iommus = <&apps_smmu 0
913 interconnects = <&syst
914 &bimc
915 <&bimc
916 &conf
917 interconnect-names = "
918 "
919
920 qcom,dll-config = <0x0
921 qcom,ddr-config = <0x8
922 bus-width = <8>;
923
924 status = "disabled";
925
926 sdhc1_opp_table: opp-t
927 compatible = "
928
929 opp-100000000
930 opp-hz
931 requir
932 opp-pe
933 opp-av
934 };
935
936 opp-192000000
937 opp-hz
938 requir
939 opp-pe
940 opp-av
941 };
942
943 opp-384000000
944 opp-hz
945 requir
946 opp-pe
947 opp-av
948 };
949 };
950 };
951
952 sdhc_2: mmc@4784000 {
953 compatible = "qcom,qcm
954 reg = <0x0 0x04784000
955 reg-names = "hc";
956
957 interrupts = <GIC_SPI
958 <GIC_SPI
959 interrupt-names = "hc_
960
961 clocks = <&gcc GCC_SDC
962 <&gcc GCC_SDC
963 <&rpmcc RPM_S
964 clock-names = "iface",
965 "core",
966 "xo";
967
968 resets = <&gcc GCC_SDC
969
970 power-domains = <&rpmp
971 operating-points-v2 =
972 iommus = <&apps_smmu 0
973 interconnects = <&syst
974 &bimc
975 <&bimc
976 &conf
977 interconnect-names = "
978 "
979
980 qcom,dll-config = <0x0
981 qcom,ddr-config = <0x8
982 bus-width = <4>;
983
984 status = "disabled";
985
986 sdhc2_opp_table: opp-t
987 compatible = "
988
989 opp-100000000
990 opp-hz
991 requir
992 opp-pe
993 opp-av
994 };
995
996 opp-202000000
997 opp-hz
998 requir
999 opp-pe
1000 opp-a
1001 };
1002 };
1003 };
1004
1005 gpi_dma0: dma-controller@4a00
1006 compatible = "qcom,qc
1007 reg = <0x0 0x04a00000
1008 interrupts = <GIC_SPI
1009 <GIC_SPI
1010 <GIC_SPI
1011 <GIC_SPI
1012 <GIC_SPI
1013 <GIC_SPI
1014 <GIC_SPI
1015 <GIC_SPI
1016 <GIC_SPI
1017 <GIC_SPI
1018 dma-channels = <10>;
1019 dma-channel-mask = <0
1020 iommus = <&apps_smmu
1021 #dma-cells = <3>;
1022 status = "disabled";
1023 };
1024
1025 qupv3_id_0: geniqup@4ac0000 {
1026 compatible = "qcom,ge
1027 reg = <0x0 0x04ac0000
1028 clocks = <&gcc GCC_QU
1029 <&gcc GCC_QU
1030 clock-names = "m-ahb"
1031 iommus = <&apps_smmu
1032 #address-cells = <2>;
1033 #size-cells = <2>;
1034 ranges;
1035 status = "disabled";
1036
1037 i2c0: i2c@4a80000 {
1038 compatible =
1039 reg = <0x0 0x
1040 interrupts =
1041 clocks = <&gc
1042 clock-names =
1043 pinctrl-0 = <
1044 pinctrl-names
1045 dmas = <&gpi_
1046 <&gpi_
1047 dma-names = "
1048 interconnects
1049
1050
1051
1052
1053
1054 interconnect-
1055
1056
1057 #address-cell
1058 #size-cells =
1059 status = "dis
1060 };
1061
1062 spi0: spi@4a80000 {
1063 compatible =
1064 reg = <0x0 0x
1065 interrupts =
1066 clocks = <&gc
1067 clock-names =
1068 pinctrl-0 = <
1069 pinctrl-names
1070 dmas = <&gpi_
1071 <&gpi_
1072 dma-names = "
1073 interconnects
1074
1075
1076
1077 interconnect-
1078
1079 #address-cell
1080 #size-cells =
1081 status = "dis
1082 };
1083
1084 uart0: serial@4a80000
1085 compatible =
1086 reg = <0x0 0x
1087 interrupts =
1088 clocks = <&gc
1089 clock-names =
1090 pinctrl-0 = <
1091 pinctrl-names
1092 interconnects
1093
1094
1095
1096 interconnect-
1097
1098 status = "dis
1099 };
1100
1101 i2c1: i2c@4a84000 {
1102 compatible =
1103 reg = <0x0 0x
1104 interrupts =
1105 clocks = <&gc
1106 clock-names =
1107 pinctrl-0 = <
1108 pinctrl-names
1109 dmas = <&gpi_
1110 <&gpi_
1111 dma-names = "
1112 interconnects
1113
1114
1115
1116
1117
1118 interconnect-
1119
1120
1121 #address-cell
1122 #size-cells =
1123 status = "dis
1124 };
1125
1126 spi1: spi@4a84000 {
1127 compatible =
1128 reg = <0x0 0x
1129 interrupts =
1130 clocks = <&gc
1131 clock-names =
1132 pinctrl-0 = <
1133 pinctrl-names
1134 dmas = <&gpi_
1135 <&gpi_
1136 dma-names = "
1137 interconnects
1138
1139
1140
1141 interconnect-
1142
1143 #address-cell
1144 #size-cells =
1145 status = "dis
1146 };
1147
1148 i2c2: i2c@4a88000 {
1149 compatible =
1150 reg = <0x0 0x
1151 interrupts =
1152 clocks = <&gc
1153 clock-names =
1154 pinctrl-0 = <
1155 pinctrl-names
1156 dmas = <&gpi_
1157 <&gpi_
1158 dma-names = "
1159 interconnects
1160
1161
1162
1163
1164
1165 interconnect-
1166
1167
1168 #address-cell
1169 #size-cells =
1170 status = "dis
1171 };
1172
1173 spi2: spi@4a88000 {
1174 compatible =
1175 reg = <0x0 0x
1176 interrupts =
1177 clocks = <&gc
1178 clock-names =
1179 pinctrl-0 = <
1180 pinctrl-names
1181 dmas = <&gpi_
1182 <&gpi_
1183 dma-names = "
1184 interconnects
1185
1186
1187
1188 interconnect-
1189
1190 #address-cell
1191 #size-cells =
1192 status = "dis
1193 };
1194
1195 i2c3: i2c@4a8c000 {
1196 compatible =
1197 reg = <0x0 0x
1198 interrupts =
1199 clocks = <&gc
1200 clock-names =
1201 pinctrl-0 = <
1202 pinctrl-names
1203 dmas = <&gpi_
1204 <&gpi_
1205 dma-names = "
1206 interconnects
1207
1208
1209
1210
1211
1212 interconnect-
1213
1214
1215 #address-cell
1216 #size-cells =
1217 status = "dis
1218 };
1219
1220 spi3: spi@4a8c000 {
1221 compatible =
1222 reg = <0x0 0x
1223 interrupts =
1224 clocks = <&gc
1225 clock-names =
1226 pinctrl-0 = <
1227 pinctrl-names
1228 dmas = <&gpi_
1229 <&gpi_
1230 dma-names = "
1231 interconnects
1232
1233
1234
1235 interconnect-
1236
1237 #address-cell
1238 #size-cells =
1239 status = "dis
1240 };
1241
1242 i2c4: i2c@4a90000 {
1243 compatible =
1244 reg = <0x0 0x
1245 interrupts =
1246 clocks = <&gc
1247 clock-names =
1248 pinctrl-0 = <
1249 pinctrl-names
1250 dmas = <&gpi_
1251 <&gpi_
1252 dma-names = "
1253 interconnects
1254
1255
1256
1257
1258
1259 interconnect-
1260
1261
1262 #address-cell
1263 #size-cells =
1264 status = "dis
1265 };
1266
1267 spi4: spi@4a90000 {
1268 compatible =
1269 reg = <0x0 0x
1270 interrupts =
1271 clock-names =
1272 clocks = <&gc
1273 pinctrl-names
1274 pinctrl-0 = <
1275 dmas = <&gpi_
1276 <&gpi_
1277 dma-names = "
1278 interconnects
1279
1280
1281
1282 interconnect-
1283
1284 #address-cell
1285 #size-cells =
1286 status = "dis
1287 };
1288
1289 uart4: serial@4a90000
1290 compatible =
1291 reg = <0x0 0x
1292 interrupts =
1293 clocks = <&gc
1294 clock-names =
1295 pinctrl-0 = <
1296 pinctrl-names
1297 interconnects
1298
1299
1300
1301 interconnect-
1302
1303 status = "dis
1304 };
1305
1306 i2c5: i2c@4a94000 {
1307 compatible =
1308 reg = <0x0 0x
1309 interrupts =
1310 clocks = <&gc
1311 clock-names =
1312 pinctrl-0 = <
1313 pinctrl-names
1314 dmas = <&gpi_
1315 <&gpi_
1316 dma-names = "
1317 interconnects
1318
1319
1320
1321
1322
1323 interconnect-
1324
1325
1326 #address-cell
1327 #size-cells =
1328 status = "dis
1329 };
1330
1331 spi5: spi@4a94000 {
1332 compatible =
1333 reg = <0x0 0x
1334 interrupts =
1335 clocks = <&gc
1336 clock-names =
1337 pinctrl-0 = <
1338 pinctrl-names
1339 dmas = <&gpi_
1340 <&gpi_
1341 dma-names = "
1342 interconnects
1343
1344
1345
1346 interconnect-
1347
1348 #address-cell
1349 #size-cells =
1350 status = "dis
1351 };
1352 };
1353
1354 usb: usb@4ef8800 {
1355 compatible = "qcom,qc
1356 reg = <0x0 0x04ef8800
1357 interrupts-extended =
1358
1359 interrupt-names = "hs
1360 "ss
1361
1362 clocks = <&gcc GCC_CF
1363 <&gcc GCC_US
1364 <&gcc GCC_SY
1365 <&gcc GCC_US
1366 <&gcc GCC_US
1367 <&gcc GCC_US
1368 clock-names = "cfg_no
1369 "core",
1370 "iface"
1371 "sleep"
1372 "mock_u
1373 "xo";
1374
1375 assigned-clocks = <&g
1376 <&g
1377 assigned-clock-rates
1378
1379 resets = <&gcc GCC_US
1380 power-domains = <&gcc
1381 /* TODO: USB<->IPA pa
1382 interconnects = <&sys
1383 &bim
1384 <&bim
1385 &con
1386 interconnect-names =
1387
1388 wakeup-source;
1389
1390 #address-cells = <2>;
1391 #size-cells = <2>;
1392 ranges;
1393
1394 status = "disabled";
1395
1396 usb_dwc3: usb@4e00000
1397 compatible =
1398 reg = <0x0 0x
1399 interrupts =
1400 phys = <&usb_
1401 phy-names = "
1402 iommus = <&ap
1403 snps,dis_u2_s
1404 snps,dis_enbl
1405 snps,has-lpm-
1406 snps,hird-thr
1407 snps,usb3_lpm
1408 maximum-speed
1409 dr_mode = "ot
1410 usb-role-swit
1411
1412 ports {
1413 #addr
1414 #size
1415
1416 port@
1417
1418
1419
1420
1421 };
1422
1423 port@
1424
1425
1426
1427
1428
1429 };
1430 };
1431 };
1432 };
1433
1434 gpu: gpu@5900000 {
1435 compatible = "qcom,ad
1436 reg = <0x0 0x05900000
1437 reg-names = "kgsl_3d0
1438
1439 interrupts = <GIC_SPI
1440
1441 clocks = <&gpucc GPU_
1442 <&gpucc GPU_
1443 <&gcc GCC_BI
1444 <&gcc GCC_GP
1445 <&gpucc GPU_
1446 <&gpucc GPU_
1447 clock-names = "core",
1448 "iface"
1449 "mem_if
1450 "alt_me
1451 "gmu",
1452 "xo";
1453
1454 interconnects = <&bim
1455 &bim
1456 interconnect-names =
1457
1458 iommus = <&adreno_smm
1459 <&adreno_smm
1460 operating-points-v2 =
1461 power-domains = <&rpm
1462 qcom,gmu = <&gmu_wrap
1463
1464 nvmem-cells = <&gpu_s
1465 nvmem-cell-names = "s
1466 #cooling-cells = <2>;
1467
1468 status = "disabled";
1469
1470 zap-shader {
1471 memory-region
1472 };
1473
1474 gpu_opp_table: opp-ta
1475 compatible =
1476
1477 /* TODO: Scal
1478 opp-112320000
1479 opp-h
1480 requi
1481 opp-p
1482 opp-s
1483 turbo
1484 };
1485
1486 opp-101760000
1487 opp-h
1488 requi
1489 opp-p
1490 opp-s
1491 turbo
1492 };
1493
1494 opp-921600000
1495 opp-h
1496 requi
1497 opp-p
1498 opp-s
1499 };
1500
1501 opp-844800000
1502 opp-h
1503 requi
1504 opp-p
1505 opp-s
1506 };
1507
1508 opp-672000000
1509 opp-h
1510 requi
1511 opp-p
1512 opp-s
1513 };
1514
1515 opp-537600000
1516 opp-h
1517 requi
1518 opp-p
1519 opp-s
1520 };
1521
1522 opp-355200000
1523 opp-h
1524 requi
1525 opp-p
1526 opp-s
1527 };
1528 };
1529 };
1530
1531 gmu_wrapper: gmu@596a000 {
1532 compatible = "qcom,ad
1533 reg = <0x0 0x0596a000
1534 reg-names = "gmu";
1535 power-domains = <&gpu
1536 <&gpu
1537 power-domain-names =
1538
1539 };
1540
1541 gpucc: clock-controller@59900
1542 compatible = "qcom,qc
1543 reg = <0x0 0x05990000
1544 clocks = <&gcc GCC_GP
1545 <&rpmcc RPM_
1546 <&gcc GCC_GP
1547 <&gcc GCC_GP
1548 power-domains = <&rpm
1549 required-opps = <&rpm
1550 #clock-cells = <1>;
1551 #reset-cells = <1>;
1552 #power-domain-cells =
1553 };
1554
1555 adreno_smmu: iommu@59a0000 {
1556 compatible = "qcom,qc
1557 "qcom,sm
1558 reg = <0x0 0x059a0000
1559 interrupts = <GIC_SPI
1560 <GIC_SPI
1561 <GIC_SPI
1562 <GIC_SPI
1563 <GIC_SPI
1564 <GIC_SPI
1565 <GIC_SPI
1566 <GIC_SPI
1567 <GIC_SPI
1568
1569 clocks = <&gcc GCC_GP
1570 <&gpucc GPU_
1571 <&gcc GCC_GP
1572 clock-names = "mem",
1573 "hlos",
1574 "iface"
1575
1576 power-domains = <&gpu
1577
1578 #global-interrupts =
1579 #iommu-cells = <2>;
1580 };
1581
1582 mdss: display-subsystem@5e000
1583 compatible = "qcom,qc
1584 reg = <0x0 0x05e00000
1585 reg-names = "mdss";
1586 interrupts = <GIC_SPI
1587 interrupt-controller;
1588 #interrupt-cells = <1
1589
1590 clocks = <&gcc GCC_DI
1591 <&gcc GCC_DI
1592 <&dispcc DIS
1593 clock-names = "iface"
1594 "bus",
1595 "core";
1596
1597 resets = <&dispcc DIS
1598
1599 power-domains = <&dis
1600
1601 iommus = <&apps_smmu
1602 <&apps_smmu
1603 interconnects = <&mmr
1604 &bim
1605 <&bim
1606 &con
1607 interconnect-names =
1608
1609
1610 #address-cells = <2>;
1611 #size-cells = <2>;
1612 ranges;
1613
1614 status = "disabled";
1615
1616 mdp: display-controll
1617 compatible =
1618 reg = <0x0 0x
1619 <0x0 0x
1620 reg-names = "
1621 "
1622
1623 interrupt-par
1624 interrupts =
1625
1626 clocks = <&gc
1627 <&di
1628 <&di
1629 <&di
1630 <&di
1631 clock-names =
1632
1633
1634
1635
1636
1637 operating-poi
1638 power-domains
1639
1640 ports {
1641 #addr
1642 #size
1643
1644 port@
1645
1646
1647
1648
1649 };
1650 };
1651
1652 mdp_opp_table
1653 compa
1654
1655 opp-1
1656
1657
1658 };
1659
1660 opp-1
1661
1662
1663 };
1664
1665 opp-2
1666
1667
1668 };
1669
1670 opp-3
1671
1672
1673 };
1674
1675 opp-3
1676
1677
1678 };
1679 };
1680 };
1681
1682 mdss_dsi0: dsi@5e9400
1683 compatible =
1684 reg = <0x0 0x
1685 reg-names = "
1686
1687 interrupt-par
1688 interrupts =
1689
1690 clocks = <&di
1691 <&di
1692 <&di
1693 <&di
1694 <&di
1695 <&gc
1696 clock-names =
1697
1698
1699
1700
1701
1702
1703 assigned-cloc
1704
1705 assigned-cloc
1706
1707
1708 operating-poi
1709 power-domains
1710 phys = <&mdss
1711
1712 #address-cell
1713 #size-cells =
1714
1715 status = "dis
1716
1717 dsi_opp_table
1718 compa
1719
1720 opp-1
1721
1722
1723 };
1724
1725 opp-1
1726
1727
1728 };
1729
1730 opp-1
1731
1732
1733 };
1734 };
1735
1736 ports {
1737 #addr
1738 #size
1739
1740 port@
1741
1742
1743
1744
1745
1746 };
1747
1748 port@
1749
1750
1751
1752
1753 };
1754 };
1755 };
1756
1757 mdss_dsi0_phy: phy@5e
1758 compatible =
1759 reg = <0x0 0x
1760 <0x0 0x
1761 <0x0 0x
1762 reg-names = "
1763 "
1764 "
1765
1766 clocks = <&di
1767 <&rp
1768 clock-names =
1769
1770
1771 power-domains
1772 required-opps
1773
1774 #clock-cells
1775 #phy-cells =
1776
1777 status = "dis
1778 };
1779 };
1780
1781 dispcc: clock-controller@5f00
1782 compatible = "qcom,qc
1783 reg = <0x0 0x05f00000
1784 clocks = <&rpmcc RPM_
1785 <&rpmcc RPM_
1786 <&gcc GCC_DI
1787 <&gcc GCC_DI
1788 <&mdss_dsi0_
1789 <&mdss_dsi0_
1790 clock-names = "bi_tcx
1791 "bi_tcx
1792 "gcc_di
1793 "gcc_di
1794 "dsi0_p
1795 "dsi0_p
1796 #power-domain-cells =
1797 #clock-cells = <1>;
1798 #reset-cells = <1>;
1799 };
1800
1801 remoteproc_mpss: remoteproc@6
1802 compatible = "qcom,qc
1803 reg = <0x0 0x06080000
1804
1805 interrupts-extended =
1806
1807
1808
1809
1810
1811 interrupt-names = "wd
1812 "fa
1813 "re
1814 "ha
1815 "st
1816 "sh
1817
1818 clocks = <&rpmcc RPM_
1819 clock-names = "xo";
1820
1821 power-domains = <&rpm
1822
1823 memory-region = <&pil
1824
1825 qcom,smem-states = <&
1826 qcom,smem-state-names
1827
1828 status = "disabled";
1829
1830 glink-edge {
1831 interrupts =
1832 label = "mpss
1833 qcom,remote-p
1834 mboxes = <&ap
1835 };
1836 };
1837
1838 remoteproc_adsp: remoteproc@a
1839 compatible = "qcom,qc
1840 reg = <0x0 0x0ab00000
1841
1842 interrupts-extended =
1843
1844
1845
1846
1847 interrupt-names = "wd
1848 "fa
1849 "re
1850 "ha
1851 "st
1852
1853 clocks = <&rpmcc RPM_
1854 clock-names = "xo";
1855
1856 power-domains = <&rpm
1857 <&rpm
1858
1859 memory-region = <&pil
1860
1861 qcom,smem-states = <&
1862 qcom,smem-state-names
1863
1864 status = "disabled";
1865
1866 glink-edge {
1867 interrupts =
1868 label = "lpas
1869 qcom,remote-p
1870 mboxes = <&ap
1871 };
1872 };
1873
1874 apps_smmu: iommu@c600000 {
1875 compatible = "qcom,qc
1876 reg = <0x0 0x0c600000
1877 #iommu-cells = <2>;
1878 #global-interrupts =
1879
1880 interrupts = <GIC_SPI
1881 <GIC_SPI
1882 <GIC_SPI
1883 <GIC_SPI
1884 <GIC_SPI
1885 <GIC_SPI
1886 <GIC_SPI
1887 <GIC_SPI
1888 <GIC_SPI
1889 <GIC_SPI
1890 <GIC_SPI
1891 <GIC_SPI
1892 <GIC_SPI
1893 <GIC_SPI
1894 <GIC_SPI
1895 <GIC_SPI
1896 <GIC_SPI
1897 <GIC_SPI
1898 <GIC_SPI
1899 <GIC_SPI
1900 <GIC_SPI
1901 <GIC_SPI
1902 <GIC_SPI
1903 <GIC_SPI
1904 <GIC_SPI
1905 <GIC_SPI
1906 <GIC_SPI
1907 <GIC_SPI
1908 <GIC_SPI
1909 <GIC_SPI
1910 <GIC_SPI
1911 <GIC_SPI
1912 <GIC_SPI
1913 <GIC_SPI
1914 <GIC_SPI
1915 <GIC_SPI
1916 <GIC_SPI
1917 <GIC_SPI
1918 <GIC_SPI
1919 <GIC_SPI
1920 <GIC_SPI
1921 <GIC_SPI
1922 <GIC_SPI
1923 <GIC_SPI
1924 <GIC_SPI
1925 <GIC_SPI
1926 <GIC_SPI
1927 <GIC_SPI
1928 <GIC_SPI
1929 <GIC_SPI
1930 <GIC_SPI
1931 <GIC_SPI
1932 <GIC_SPI
1933 <GIC_SPI
1934 <GIC_SPI
1935 <GIC_SPI
1936 <GIC_SPI
1937 <GIC_SPI
1938 <GIC_SPI
1939 <GIC_SPI
1940 <GIC_SPI
1941 <GIC_SPI
1942 <GIC_SPI
1943 <GIC_SPI
1944 <GIC_SPI
1945 };
1946
1947 wifi: wifi@c800000 {
1948 compatible = "qcom,wc
1949 reg = <0x0 0x0c800000
1950 reg-names = "membase"
1951 memory-region = <&wla
1952 interrupts = <GIC_SPI
1953 <GIC_SPI
1954 <GIC_SPI
1955 <GIC_SPI
1956 <GIC_SPI
1957 <GIC_SPI
1958 <GIC_SPI
1959 <GIC_SPI
1960 <GIC_SPI
1961 <GIC_SPI
1962 <GIC_SPI
1963 <GIC_SPI
1964 iommus = <&apps_smmu
1965 qcom,msa-fixed-perm;
1966 status = "disabled";
1967 };
1968
1969 watchdog@f017000 {
1970 compatible = "qcom,ap
1971 reg = <0x0 0x0f017000
1972 interrupts = <GIC_SPI
1973 <GIC_SPI
1974 clocks = <&sleep_clk>
1975 };
1976
1977 apcs_glb: mailbox@f111000 {
1978 compatible = "qcom,qc
1979 reg = <0x0 0x0f111000
1980 #mbox-cells = <1>;
1981 };
1982
1983 timer@f120000 {
1984 compatible = "arm,arm
1985 reg = <0x0 0x0f120000
1986 #address-cells = <1>;
1987 #size-cells = <1>;
1988 ranges = <0 0x0 0x0f1
1989
1990 frame@0 {
1991 reg = <0x0 0x
1992 <0x1000
1993 interrupts =
1994
1995 frame-number
1996 };
1997
1998 frame@2000 {
1999 reg = <0x2000
2000 interrupts =
2001 frame-number
2002 status = "dis
2003 };
2004
2005 frame@3000 {
2006 reg = <0x3000
2007 interrupts =
2008 frame-number
2009 status = "dis
2010 };
2011
2012 frame@4000 {
2013 reg = <0x4000
2014 interrupts =
2015 frame-number
2016 status = "dis
2017 };
2018
2019 frame@5000 {
2020 reg = <0x5000
2021 interrupts =
2022 frame-number
2023 status = "dis
2024 };
2025
2026 frame@6000 {
2027 reg = <0x6000
2028 interrupts =
2029 frame-number
2030 status = "dis
2031 };
2032
2033 frame@7000 {
2034 reg = <0x7000
2035 interrupts =
2036 frame-number
2037 status = "dis
2038 };
2039 };
2040
2041 intc: interrupt-controller@f2
2042 compatible = "arm,gic
2043 reg = <0x0 0x0f200000
2044 <0x0 0x0f300000
2045 interrupts = <GIC_PPI
2046 #interrupt-cells = <3
2047 interrupt-controller;
2048 interrupt-parent = <&
2049 #redistributor-region
2050 redistributor-stride
2051 };
2052
2053 cpufreq_hw: cpufreq@f521000 {
2054 compatible = "qcom,qc
2055 reg = <0x0 0x0f521000
2056 reg-names = "freq-dom
2057 interrupts-extended =
2058 interrupt-names = "dc
2059 clocks = <&rpmcc RPM_
2060 clock-names = "xo", "
2061
2062 #freq-domain-cells =
2063 #clock-cells = <1>;
2064 };
2065
2066 lmh_cluster: lmh@f550800 {
2067 compatible = "qcom,qc
2068 reg = <0x0 0x0f550800
2069 interrupts = <GIC_SPI
2070 cpus = <&CPU0>;
2071 qcom,lmh-temp-arm-mil
2072 qcom,lmh-temp-low-mil
2073 qcom,lmh-temp-high-mi
2074 interrupt-controller;
2075 #interrupt-cells = <1
2076 };
2077 };
2078
2079 thermal-zones {
2080 mapss-thermal {
2081 thermal-sensors = <&t
2082
2083 trips {
2084 mapss_alert0:
2085 tempe
2086 hyste
2087 type
2088 };
2089
2090 mapss_alert1:
2091 tempe
2092 hyste
2093 type
2094 };
2095
2096 mapss_crit: m
2097 tempe
2098 hyste
2099 type
2100 };
2101 };
2102 };
2103
2104 video-thermal {
2105 thermal-sensors = <&t
2106
2107 trips {
2108 video_alert0:
2109 tempe
2110 hyste
2111 type
2112 };
2113
2114 video_alert1:
2115 tempe
2116 hyste
2117 type
2118 };
2119
2120 video_crit: v
2121 tempe
2122 hyste
2123 type
2124 };
2125 };
2126 };
2127
2128 wlan-thermal {
2129 thermal-sensors = <&t
2130
2131 trips {
2132 wlan_alert0:
2133 tempe
2134 hyste
2135 type
2136 };
2137
2138 wlan_alert1:
2139 tempe
2140 hyste
2141 type
2142 };
2143
2144 wlan_crit: wl
2145 tempe
2146 hyste
2147 type
2148 };
2149 };
2150 };
2151
2152 cpuss0-thermal {
2153 thermal-sensors = <&t
2154
2155 trips {
2156 cpuss0_alert0
2157 tempe
2158 hyste
2159 type
2160 };
2161
2162 cpuss0_alert1
2163 tempe
2164 hyste
2165 type
2166 };
2167
2168 cpuss0_crit:
2169 tempe
2170 hyste
2171 type
2172 };
2173 };
2174 };
2175
2176 cpuss1-thermal {
2177 thermal-sensors = <&t
2178
2179 trips {
2180 cpuss1_alert0
2181 tempe
2182 hyste
2183 type
2184 };
2185
2186 cpuss1_alert1
2187 tempe
2188 hyste
2189 type
2190 };
2191
2192 cpuss1_crit:
2193 tempe
2194 hyste
2195 type
2196 };
2197 };
2198 };
2199
2200 mdm0-thermal {
2201 thermal-sensors = <&t
2202
2203 trips {
2204 mdm0_alert0:
2205 tempe
2206 hyste
2207 type
2208 };
2209
2210 mdm0_alert1:
2211 tempe
2212 hyste
2213 type
2214 };
2215
2216 mdm0_crit: md
2217 tempe
2218 hyste
2219 type
2220 };
2221 };
2222 };
2223
2224 mdm1-thermal {
2225 thermal-sensors = <&t
2226
2227 trips {
2228 mdm1_alert0:
2229 tempe
2230 hyste
2231 type
2232 };
2233
2234 mdm1_alert1:
2235 tempe
2236 hyste
2237 type
2238 };
2239
2240 mdm1_crit: md
2241 tempe
2242 hyste
2243 type
2244 };
2245 };
2246 };
2247
2248 gpu-thermal {
2249 thermal-sensors = <&t
2250
2251 trips {
2252 gpu_alert0: t
2253 tempe
2254 hyste
2255 type
2256 };
2257
2258 gpu_alert1: t
2259 tempe
2260 hyste
2261 type
2262 };
2263
2264 gpu_crit: gpu
2265 tempe
2266 hyste
2267 type
2268 };
2269 };
2270 };
2271
2272 hm-center-thermal {
2273 thermal-sensors = <&t
2274
2275 trips {
2276 hm_center_ale
2277 tempe
2278 hyste
2279 type
2280 };
2281
2282 hm_center_ale
2283 tempe
2284 hyste
2285 type
2286 };
2287
2288 hm_center_cri
2289 tempe
2290 hyste
2291 type
2292 };
2293 };
2294 };
2295
2296 camera-thermal {
2297 thermal-sensors = <&t
2298
2299 trips {
2300 camera_alert0
2301 tempe
2302 hyste
2303 type
2304 };
2305
2306 camera_alert1
2307 tempe
2308 hyste
2309 type
2310 };
2311
2312 camera_crit:
2313 tempe
2314 hyste
2315 type
2316 };
2317 };
2318 };
2319 };
2320
2321 timer {
2322 compatible = "arm,armv8-timer
2323 interrupts = <GIC_PPI 1 (GIC_
2324 <GIC_PPI 2 (GIC_
2325 <GIC_PPI 3 (GIC_
2326 <GIC_PPI 0 (GIC_
2327 };
2328 };
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