1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3 1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2 /* 2 /*
3 * Copyright (c) 2023, Linaro Ltd 3 * Copyright (c) 2023, Linaro Ltd
4 * 4 *
5 * Based on sm6115.dtsi and previous efforts b 5 * Based on sm6115.dtsi and previous efforts by Shawn Guo & Loic Poulain.
6 */ 6 */
7 7
8 #include <dt-bindings/clock/qcom,dispcc-qcm229 8 #include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
9 #include <dt-bindings/clock/qcom,gcc-qcm2290.h 9 #include <dt-bindings/clock/qcom,gcc-qcm2290.h>
10 #include <dt-bindings/clock/qcom,qcm2290-gpucc <<
11 #include <dt-bindings/clock/qcom,rpmcc.h> 10 #include <dt-bindings/clock/qcom,rpmcc.h>
12 #include <dt-bindings/dma/qcom-gpi.h> 11 #include <dt-bindings/dma/qcom-gpi.h>
13 #include <dt-bindings/firmware/qcom,scm.h> 12 #include <dt-bindings/firmware/qcom,scm.h>
14 #include <dt-bindings/gpio/gpio.h> 13 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/interrupt-controller/arm 14 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/interconnect/qcom,qcm229 15 #include <dt-bindings/interconnect/qcom,qcm2290.h>
17 #include <dt-bindings/interconnect/qcom,rpm-ic 16 #include <dt-bindings/interconnect/qcom,rpm-icc.h>
18 #include <dt-bindings/power/qcom-rpmpd.h> 17 #include <dt-bindings/power/qcom-rpmpd.h>
19 18
20 / { 19 / {
21 interrupt-parent = <&intc>; 20 interrupt-parent = <&intc>;
22 21
23 #address-cells = <2>; 22 #address-cells = <2>;
24 #size-cells = <2>; 23 #size-cells = <2>;
25 24
26 chosen { }; 25 chosen { };
27 26
28 clocks { 27 clocks {
29 xo_board: xo-board { 28 xo_board: xo-board {
30 compatible = "fixed-cl 29 compatible = "fixed-clock";
31 #clock-cells = <0>; 30 #clock-cells = <0>;
32 }; 31 };
33 32
34 sleep_clk: sleep-clk { 33 sleep_clk: sleep-clk {
35 compatible = "fixed-cl 34 compatible = "fixed-clock";
36 clock-frequency = <327 35 clock-frequency = <32764>;
37 #clock-cells = <0>; 36 #clock-cells = <0>;
38 }; 37 };
39 }; 38 };
40 39
41 cpus { 40 cpus {
42 #address-cells = <2>; 41 #address-cells = <2>;
43 #size-cells = <0>; 42 #size-cells = <0>;
44 43
45 CPU0: cpu@0 { 44 CPU0: cpu@0 {
46 device_type = "cpu"; 45 device_type = "cpu";
47 compatible = "arm,cort 46 compatible = "arm,cortex-a53";
48 reg = <0x0 0x0>; 47 reg = <0x0 0x0>;
49 clocks = <&cpufreq_hw 48 clocks = <&cpufreq_hw 0>;
50 capacity-dmips-mhz = < 49 capacity-dmips-mhz = <1024>;
51 dynamic-power-coeffici 50 dynamic-power-coefficient = <100>;
52 enable-method = "psci" 51 enable-method = "psci";
53 next-level-cache = <&L 52 next-level-cache = <&L2_0>;
54 qcom,freq-domain = <&c 53 qcom,freq-domain = <&cpufreq_hw 0>;
55 power-domains = <&CPU_ 54 power-domains = <&CPU_PD0>;
56 power-domain-names = " 55 power-domain-names = "psci";
57 L2_0: l2-cache { 56 L2_0: l2-cache {
58 compatible = " 57 compatible = "cache";
59 cache-level = 58 cache-level = <2>;
60 cache-unified; 59 cache-unified;
61 }; 60 };
62 }; 61 };
63 62
64 CPU1: cpu@1 { 63 CPU1: cpu@1 {
65 device_type = "cpu"; 64 device_type = "cpu";
66 compatible = "arm,cort 65 compatible = "arm,cortex-a53";
67 reg = <0x0 0x1>; 66 reg = <0x0 0x1>;
68 clocks = <&cpufreq_hw 67 clocks = <&cpufreq_hw 0>;
69 capacity-dmips-mhz = < 68 capacity-dmips-mhz = <1024>;
70 dynamic-power-coeffici 69 dynamic-power-coefficient = <100>;
71 enable-method = "psci" 70 enable-method = "psci";
72 next-level-cache = <&L 71 next-level-cache = <&L2_0>;
73 qcom,freq-domain = <&c 72 qcom,freq-domain = <&cpufreq_hw 0>;
74 power-domains = <&CPU_ 73 power-domains = <&CPU_PD1>;
75 power-domain-names = " 74 power-domain-names = "psci";
76 }; 75 };
77 76
78 CPU2: cpu@2 { 77 CPU2: cpu@2 {
79 device_type = "cpu"; 78 device_type = "cpu";
80 compatible = "arm,cort 79 compatible = "arm,cortex-a53";
81 reg = <0x0 0x2>; 80 reg = <0x0 0x2>;
82 clocks = <&cpufreq_hw 81 clocks = <&cpufreq_hw 0>;
83 capacity-dmips-mhz = < 82 capacity-dmips-mhz = <1024>;
84 dynamic-power-coeffici 83 dynamic-power-coefficient = <100>;
85 enable-method = "psci" 84 enable-method = "psci";
86 next-level-cache = <&L 85 next-level-cache = <&L2_0>;
87 qcom,freq-domain = <&c 86 qcom,freq-domain = <&cpufreq_hw 0>;
88 power-domains = <&CPU_ 87 power-domains = <&CPU_PD2>;
89 power-domain-names = " 88 power-domain-names = "psci";
90 }; 89 };
91 90
92 CPU3: cpu@3 { 91 CPU3: cpu@3 {
93 device_type = "cpu"; 92 device_type = "cpu";
94 compatible = "arm,cort 93 compatible = "arm,cortex-a53";
95 reg = <0x0 0x3>; 94 reg = <0x0 0x3>;
96 clocks = <&cpufreq_hw 95 clocks = <&cpufreq_hw 0>;
97 capacity-dmips-mhz = < 96 capacity-dmips-mhz = <1024>;
98 dynamic-power-coeffici 97 dynamic-power-coefficient = <100>;
99 enable-method = "psci" 98 enable-method = "psci";
100 next-level-cache = <&L 99 next-level-cache = <&L2_0>;
101 qcom,freq-domain = <&c 100 qcom,freq-domain = <&cpufreq_hw 0>;
102 power-domains = <&CPU_ 101 power-domains = <&CPU_PD3>;
103 power-domain-names = " 102 power-domain-names = "psci";
104 }; 103 };
105 104
106 cpu-map { 105 cpu-map {
107 cluster0 { 106 cluster0 {
108 core0 { 107 core0 {
109 cpu = 108 cpu = <&CPU0>;
110 }; 109 };
111 110
112 core1 { 111 core1 {
113 cpu = 112 cpu = <&CPU1>;
114 }; 113 };
115 114
116 core2 { 115 core2 {
117 cpu = 116 cpu = <&CPU2>;
118 }; 117 };
119 118
120 core3 { 119 core3 {
121 cpu = 120 cpu = <&CPU3>;
122 }; 121 };
123 }; 122 };
124 }; 123 };
125 124
126 domain-idle-states { 125 domain-idle-states {
127 CLUSTER_SLEEP: cluster 126 CLUSTER_SLEEP: cluster-sleep-0 {
128 compatible = " 127 compatible = "domain-idle-state";
129 arm,psci-suspe 128 arm,psci-suspend-param = <0x41000043>;
130 entry-latency- 129 entry-latency-us = <800>;
131 exit-latency-u 130 exit-latency-us = <2118>;
132 min-residency- 131 min-residency-us = <7376>;
133 }; 132 };
134 }; 133 };
135 134
136 idle-states { 135 idle-states {
137 entry-method = "psci"; 136 entry-method = "psci";
138 137
139 CPU_SLEEP: cpu-sleep-0 138 CPU_SLEEP: cpu-sleep-0 {
140 compatible = " 139 compatible = "arm,idle-state";
141 idle-state-nam 140 idle-state-name = "power-collapse";
142 arm,psci-suspe 141 arm,psci-suspend-param = <0x40000003>;
143 entry-latency- 142 entry-latency-us = <290>;
144 exit-latency-u 143 exit-latency-us = <376>;
145 min-residency- 144 min-residency-us = <1182>;
146 local-timer-st 145 local-timer-stop;
147 }; 146 };
148 }; 147 };
149 }; 148 };
150 149
151 firmware { 150 firmware {
152 scm: scm { 151 scm: scm {
153 compatible = "qcom,scm 152 compatible = "qcom,scm-qcm2290", "qcom,scm";
154 clocks = <&rpmcc RPM_S 153 clocks = <&rpmcc RPM_SMD_CE1_CLK>;
155 clock-names = "core"; 154 clock-names = "core";
156 #reset-cells = <1>; 155 #reset-cells = <1>;
157 interconnects = <&syst 156 interconnects = <&system_noc MASTER_CRYPTO_CORE0 RPM_ALWAYS_TAG
158 &bimc 157 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>;
159 }; 158 };
160 }; 159 };
161 160
162 memory@40000000 { 161 memory@40000000 {
163 device_type = "memory"; 162 device_type = "memory";
164 /* We expect the bootloader to 163 /* We expect the bootloader to fill in the size */
165 reg = <0 0x40000000 0 0>; 164 reg = <0 0x40000000 0 0>;
166 }; 165 };
167 166
168 pmu { 167 pmu {
169 compatible = "arm,cortex-a53-p 168 compatible = "arm,cortex-a53-pmu";
170 interrupts = <GIC_PPI 6 IRQ_TY 169 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>;
171 }; 170 };
172 171
173 psci { 172 psci {
174 compatible = "arm,psci-1.0"; 173 compatible = "arm,psci-1.0";
175 method = "smc"; 174 method = "smc";
176 175
177 CPU_PD0: power-domain-cpu0 { 176 CPU_PD0: power-domain-cpu0 {
178 #power-domain-cells = 177 #power-domain-cells = <0>;
179 power-domains = <&CLUS 178 power-domains = <&CLUSTER_PD>;
180 domain-idle-states = < 179 domain-idle-states = <&CPU_SLEEP>;
181 }; 180 };
182 181
183 CPU_PD1: power-domain-cpu1 { 182 CPU_PD1: power-domain-cpu1 {
184 #power-domain-cells = 183 #power-domain-cells = <0>;
185 power-domains = <&CLUS 184 power-domains = <&CLUSTER_PD>;
186 domain-idle-states = < 185 domain-idle-states = <&CPU_SLEEP>;
187 }; 186 };
188 187
189 CPU_PD2: power-domain-cpu2 { 188 CPU_PD2: power-domain-cpu2 {
190 #power-domain-cells = 189 #power-domain-cells = <0>;
191 power-domains = <&CLUS 190 power-domains = <&CLUSTER_PD>;
192 domain-idle-states = < 191 domain-idle-states = <&CPU_SLEEP>;
193 }; 192 };
194 193
195 CPU_PD3: power-domain-cpu3 { 194 CPU_PD3: power-domain-cpu3 {
196 #power-domain-cells = 195 #power-domain-cells = <0>;
197 power-domains = <&CLUS 196 power-domains = <&CLUSTER_PD>;
198 domain-idle-states = < 197 domain-idle-states = <&CPU_SLEEP>;
199 }; 198 };
200 199
201 CLUSTER_PD: power-domain-cpu-c 200 CLUSTER_PD: power-domain-cpu-cluster {
202 #power-domain-cells = 201 #power-domain-cells = <0>;
203 power-domains = <&mpm> 202 power-domains = <&mpm>;
204 domain-idle-states = < 203 domain-idle-states = <&CLUSTER_SLEEP>;
205 }; 204 };
206 }; 205 };
207 206
208 rpm: remoteproc { 207 rpm: remoteproc {
209 compatible = "qcom,qcm2290-rpm 208 compatible = "qcom,qcm2290-rpm-proc", "qcom,rpm-proc";
210 209
211 glink-edge { 210 glink-edge {
212 compatible = "qcom,gli 211 compatible = "qcom,glink-rpm";
213 interrupts = <GIC_SPI 212 interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>;
214 qcom,rpm-msg-ram = <&r 213 qcom,rpm-msg-ram = <&rpm_msg_ram>;
215 mboxes = <&apcs_glb 0> 214 mboxes = <&apcs_glb 0>;
216 215
217 rpm_requests: rpm-requ 216 rpm_requests: rpm-requests {
218 compatible = " !! 217 compatible = "qcom,rpm-qcm2290";
219 qcom,glink-cha 218 qcom,glink-channels = "rpm_requests";
220 219
221 rpmcc: clock-c 220 rpmcc: clock-controller {
222 compat 221 compatible = "qcom,rpmcc-qcm2290", "qcom,rpmcc";
223 clocks 222 clocks = <&xo_board>;
224 clock- 223 clock-names = "xo";
225 #clock 224 #clock-cells = <1>;
226 }; 225 };
227 226
228 rpmpd: power-c 227 rpmpd: power-controller {
229 compat 228 compatible = "qcom,qcm2290-rpmpd";
230 #power 229 #power-domain-cells = <1>;
231 operat 230 operating-points-v2 = <&rpmpd_opp_table>;
232 231
233 rpmpd_ 232 rpmpd_opp_table: opp-table {
234 233 compatible = "operating-points-v2";
235 234
236 235 rpmpd_opp_min_svs: opp1 {
237 236 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
238 237 };
239 238
240 239 rpmpd_opp_low_svs: opp2 {
241 240 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
242 241 };
243 242
244 243 rpmpd_opp_svs: opp3 {
245 244 opp-level = <RPM_SMD_LEVEL_SVS>;
246 245 };
247 246
248 247 rpmpd_opp_svs_plus: opp4 {
249 248 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
250 249 };
251 250
252 251 rpmpd_opp_nom: opp5 {
253 252 opp-level = <RPM_SMD_LEVEL_NOM>;
254 253 };
255 254
256 255 rpmpd_opp_nom_plus: opp6 {
257 256 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
258 257 };
259 258
260 259 rpmpd_opp_turbo: opp7 {
261 260 opp-level = <RPM_SMD_LEVEL_TURBO>;
262 261 };
263 262
264 263 rpmpd_opp_turbo_plus: opp8 {
265 264 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>;
266 265 };
267 }; 266 };
268 }; 267 };
269 }; 268 };
270 }; 269 };
271 270
272 mpm: interrupt-controller { 271 mpm: interrupt-controller {
273 compatible = "qcom,mpm 272 compatible = "qcom,mpm";
274 qcom,rpm-msg-ram = <&a 273 qcom,rpm-msg-ram = <&apss_mpm>;
275 interrupts = <GIC_SPI 274 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
276 mboxes = <&apcs_glb 1> 275 mboxes = <&apcs_glb 1>;
277 interrupt-controller; 276 interrupt-controller;
278 #interrupt-cells = <2> 277 #interrupt-cells = <2>;
279 #power-domain-cells = 278 #power-domain-cells = <0>;
280 interrupt-parent = <&i 279 interrupt-parent = <&intc>;
281 qcom,mpm-pin-count = < 280 qcom,mpm-pin-count = <96>;
282 qcom,mpm-pin-map = <2 281 qcom,mpm-pin-map = <2 275>, /* TSENS0 uplow */
283 <5 282 <5 296>, /* Soundwire master_irq */
284 <12 283 <12 422>, /* DWC3 ss_phy_irq */
285 <24 284 <24 79>, /* Soundwire wake_irq */
286 <86 285 <86 183>, /* MPM wake, SPMI */
287 <90 286 <90 260>; /* QUSB2_PHY DP+DM */
288 }; 287 };
289 }; 288 };
290 289
291 reserved_memory: reserved-memory { 290 reserved_memory: reserved-memory {
292 #address-cells = <2>; 291 #address-cells = <2>;
293 #size-cells = <2>; 292 #size-cells = <2>;
294 ranges; 293 ranges;
295 294
296 hyp_mem: hyp@45700000 { 295 hyp_mem: hyp@45700000 {
297 reg = <0x0 0x45700000 296 reg = <0x0 0x45700000 0x0 0x600000>;
298 no-map; 297 no-map;
299 }; 298 };
300 299
301 xbl_aop_mem: xbl-aop@45e00000 300 xbl_aop_mem: xbl-aop@45e00000 {
302 reg = <0x0 0x45e00000 301 reg = <0x0 0x45e00000 0x0 0x140000>;
303 no-map; 302 no-map;
304 }; 303 };
305 304
306 sec_apps_mem: sec-apps@45fff00 305 sec_apps_mem: sec-apps@45fff000 {
307 reg = <0x0 0x45fff000 306 reg = <0x0 0x45fff000 0x0 0x1000>;
308 no-map; 307 no-map;
309 }; 308 };
310 309
311 smem_mem: smem@46000000 { 310 smem_mem: smem@46000000 {
312 compatible = "qcom,sme 311 compatible = "qcom,smem";
313 reg = <0x0 0x46000000 312 reg = <0x0 0x46000000 0x0 0x200000>;
314 no-map; 313 no-map;
315 314
316 hwlocks = <&tcsr_mutex 315 hwlocks = <&tcsr_mutex 3>;
317 qcom,rpm-msg-ram = <&r 316 qcom,rpm-msg-ram = <&rpm_msg_ram>;
318 }; 317 };
319 318
320 pil_modem_mem: modem@4ab00000 319 pil_modem_mem: modem@4ab00000 {
321 reg = <0x0 0x4ab00000 320 reg = <0x0 0x4ab00000 0x0 0x6900000>;
322 no-map; 321 no-map;
323 }; 322 };
324 323
325 pil_video_mem: video@51400000 324 pil_video_mem: video@51400000 {
326 reg = <0x0 0x51400000 325 reg = <0x0 0x51400000 0x0 0x500000>;
327 no-map; 326 no-map;
328 }; 327 };
329 328
330 wlan_msa_mem: wlan-msa@5190000 329 wlan_msa_mem: wlan-msa@51900000 {
331 reg = <0x0 0x51900000 330 reg = <0x0 0x51900000 0x0 0x100000>;
332 no-map; 331 no-map;
333 }; 332 };
334 333
335 pil_adsp_mem: adsp@51a00000 { 334 pil_adsp_mem: adsp@51a00000 {
336 reg = <0x0 0x51a00000 335 reg = <0x0 0x51a00000 0x0 0x1c00000>;
337 no-map; 336 no-map;
338 }; 337 };
339 338
340 pil_ipa_fw_mem: ipa-fw@5360000 339 pil_ipa_fw_mem: ipa-fw@53600000 {
341 reg = <0x0 0x53600000 340 reg = <0x0 0x53600000 0x0 0x10000>;
342 no-map; 341 no-map;
343 }; 342 };
344 343
345 pil_ipa_gsi_mem: ipa-gsi@53610 344 pil_ipa_gsi_mem: ipa-gsi@53610000 {
346 reg = <0x0 0x53610000 345 reg = <0x0 0x53610000 0x0 0x5000>;
347 no-map; 346 no-map;
348 }; 347 };
349 348
350 pil_gpu_mem: zap@53615000 { 349 pil_gpu_mem: zap@53615000 {
351 compatible = "shared-d 350 compatible = "shared-dma-pool";
352 reg = <0x0 0x53615000 351 reg = <0x0 0x53615000 0x0 0x2000>;
353 no-map; 352 no-map;
354 }; 353 };
355 354
356 cont_splash_memory: framebuffe 355 cont_splash_memory: framebuffer@5c000000 {
357 reg = <0x0 0x5c000000 356 reg = <0x0 0x5c000000 0x0 0x00f00000>;
358 no-map; 357 no-map;
359 }; 358 };
360 359
361 dfps_data_memory: dpfs-data@5c 360 dfps_data_memory: dpfs-data@5cf00000 {
362 reg = <0x0 0x5cf00000 361 reg = <0x0 0x5cf00000 0x0 0x0100000>;
363 no-map; 362 no-map;
364 }; 363 };
365 364
366 removed_mem: reserved@60000000 365 removed_mem: reserved@60000000 {
367 reg = <0x0 0x60000000 366 reg = <0x0 0x60000000 0x0 0x3900000>;
368 no-map; 367 no-map;
369 }; 368 };
370 369
371 rmtfs_mem: memory@89b01000 { 370 rmtfs_mem: memory@89b01000 {
372 compatible = "qcom,rmt 371 compatible = "qcom,rmtfs-mem";
373 reg = <0x0 0x89b01000 372 reg = <0x0 0x89b01000 0x0 0x200000>;
374 no-map; 373 no-map;
375 374
376 qcom,client-id = <1>; 375 qcom,client-id = <1>;
377 qcom,vmid = <QCOM_SCM_ 376 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA QCOM_SCM_VMID_NAV>;
378 }; 377 };
379 }; 378 };
380 379
381 smp2p-adsp { 380 smp2p-adsp {
382 compatible = "qcom,smp2p"; 381 compatible = "qcom,smp2p";
383 qcom,smem = <443>, <429>; 382 qcom,smem = <443>, <429>;
384 383
385 interrupts = <GIC_SPI 279 IRQ_ 384 interrupts = <GIC_SPI 279 IRQ_TYPE_EDGE_RISING>;
386 385
387 mboxes = <&apcs_glb 10>; 386 mboxes = <&apcs_glb 10>;
388 387
389 qcom,local-pid = <0>; 388 qcom,local-pid = <0>;
390 qcom,remote-pid = <2>; 389 qcom,remote-pid = <2>;
391 390
392 adsp_smp2p_out: master-kernel 391 adsp_smp2p_out: master-kernel {
393 qcom,entry-name = "mas 392 qcom,entry-name = "master-kernel";
394 #qcom,smem-state-cells 393 #qcom,smem-state-cells = <1>;
395 }; 394 };
396 395
397 adsp_smp2p_in: slave-kernel { 396 adsp_smp2p_in: slave-kernel {
398 qcom,entry-name = "sla 397 qcom,entry-name = "slave-kernel";
399 interrupt-controller; 398 interrupt-controller;
400 #interrupt-cells = <2> 399 #interrupt-cells = <2>;
401 }; 400 };
402 }; 401 };
403 402
404 smp2p-mpss { 403 smp2p-mpss {
405 compatible = "qcom,smp2p"; 404 compatible = "qcom,smp2p";
406 qcom,smem = <435>, <428>; 405 qcom,smem = <435>, <428>;
407 406
408 interrupts = <GIC_SPI 70 IRQ_T 407 interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>;
409 408
410 mboxes = <&apcs_glb 14>; 409 mboxes = <&apcs_glb 14>;
411 410
412 qcom,local-pid = <0>; 411 qcom,local-pid = <0>;
413 qcom,remote-pid = <1>; 412 qcom,remote-pid = <1>;
414 413
415 modem_smp2p_out: master-kernel 414 modem_smp2p_out: master-kernel {
416 qcom,entry-name = "mas 415 qcom,entry-name = "master-kernel";
417 #qcom,smem-state-cells 416 #qcom,smem-state-cells = <1>;
418 }; 417 };
419 418
420 modem_smp2p_in: slave-kernel { 419 modem_smp2p_in: slave-kernel {
421 qcom,entry-name = "sla 420 qcom,entry-name = "slave-kernel";
422 interrupt-controller; 421 interrupt-controller;
423 #interrupt-cells = <2> 422 #interrupt-cells = <2>;
424 }; 423 };
425 424
426 wlan_smp2p_in: wlan-wpss-to-ap 425 wlan_smp2p_in: wlan-wpss-to-ap {
427 qcom,entry-name = "wla 426 qcom,entry-name = "wlan";
428 interrupt-controller; 427 interrupt-controller;
429 #interrupt-cells = <2> 428 #interrupt-cells = <2>;
430 }; 429 };
431 }; 430 };
432 431
433 soc: soc@0 { 432 soc: soc@0 {
434 compatible = "simple-bus"; 433 compatible = "simple-bus";
435 #address-cells = <2>; 434 #address-cells = <2>;
436 #size-cells = <2>; 435 #size-cells = <2>;
437 ranges = <0 0 0 0 0x10 0>; 436 ranges = <0 0 0 0 0x10 0>;
438 dma-ranges = <0 0 0 0 0x10 0>; 437 dma-ranges = <0 0 0 0 0x10 0>;
439 438
440 tcsr_mutex: hwlock@340000 { 439 tcsr_mutex: hwlock@340000 {
441 compatible = "qcom,tcs 440 compatible = "qcom,tcsr-mutex";
442 reg = <0x0 0x00340000 441 reg = <0x0 0x00340000 0x0 0x20000>;
443 #hwlock-cells = <1>; 442 #hwlock-cells = <1>;
444 }; 443 };
445 444
446 tcsr_regs: syscon@3c0000 { 445 tcsr_regs: syscon@3c0000 {
447 compatible = "qcom,qcm 446 compatible = "qcom,qcm2290-tcsr", "syscon";
448 reg = <0x0 0x003c0000 447 reg = <0x0 0x003c0000 0x0 0x40000>;
449 }; 448 };
450 449
451 tlmm: pinctrl@500000 { 450 tlmm: pinctrl@500000 {
452 compatible = "qcom,qcm 451 compatible = "qcom,qcm2290-tlmm";
453 reg = <0x0 0x00500000 452 reg = <0x0 0x00500000 0x0 0x300000>;
454 interrupts = <GIC_SPI 453 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
455 gpio-controller; 454 gpio-controller;
456 gpio-ranges = <&tlmm 0 455 gpio-ranges = <&tlmm 0 0 127>;
457 wakeup-parent = <&mpm> 456 wakeup-parent = <&mpm>;
458 #gpio-cells = <2>; 457 #gpio-cells = <2>;
459 interrupt-controller; 458 interrupt-controller;
460 #interrupt-cells = <2> 459 #interrupt-cells = <2>;
461 460
462 qup_i2c0_default: qup- 461 qup_i2c0_default: qup-i2c0-default-state {
463 pins = "gpio0" 462 pins = "gpio0", "gpio1";
464 function = "qu 463 function = "qup0";
465 drive-strength 464 drive-strength = <2>;
466 bias-pull-up; 465 bias-pull-up;
467 }; 466 };
468 467
469 qup_i2c1_default: qup- 468 qup_i2c1_default: qup-i2c1-default-state {
470 pins = "gpio4" 469 pins = "gpio4", "gpio5";
471 function = "qu 470 function = "qup1";
472 drive-strength 471 drive-strength = <2>;
473 bias-pull-up; 472 bias-pull-up;
474 }; 473 };
475 474
476 qup_i2c2_default: qup- 475 qup_i2c2_default: qup-i2c2-default-state {
477 pins = "gpio6" 476 pins = "gpio6", "gpio7";
478 function = "qu 477 function = "qup2";
479 drive-strength 478 drive-strength = <2>;
480 bias-pull-up; 479 bias-pull-up;
481 }; 480 };
482 481
483 qup_i2c3_default: qup- 482 qup_i2c3_default: qup-i2c3-default-state {
484 pins = "gpio8" 483 pins = "gpio8", "gpio9";
485 function = "qu 484 function = "qup3";
486 drive-strength 485 drive-strength = <2>;
487 bias-pull-up; 486 bias-pull-up;
488 }; 487 };
489 488
490 qup_i2c4_default: qup- 489 qup_i2c4_default: qup-i2c4-default-state {
491 pins = "gpio12 490 pins = "gpio12", "gpio13";
492 function = "qu 491 function = "qup4";
493 drive-strength 492 drive-strength = <2>;
494 bias-pull-up; 493 bias-pull-up;
495 }; 494 };
496 495
497 qup_i2c5_default: qup- 496 qup_i2c5_default: qup-i2c5-default-state {
498 pins = "gpio14 497 pins = "gpio14", "gpio15";
499 function = "qu 498 function = "qup5";
500 drive-strength 499 drive-strength = <2>;
501 bias-pull-up; 500 bias-pull-up;
502 }; 501 };
503 502
504 qup_spi0_default: qup- 503 qup_spi0_default: qup-spi0-default-state {
505 pins = "gpio0" 504 pins = "gpio0", "gpio1","gpio2", "gpio3";
506 function = "qu 505 function = "qup0";
507 drive-strength 506 drive-strength = <2>;
508 bias-pull-up; 507 bias-pull-up;
509 }; 508 };
510 509
511 qup_spi1_default: qup- 510 qup_spi1_default: qup-spi1-default-state {
512 pins = "gpio4" 511 pins = "gpio4", "gpio5", "gpio69", "gpio70";
513 function = "qu 512 function = "qup1";
514 drive-strength 513 drive-strength = <2>;
515 bias-pull-up; 514 bias-pull-up;
516 }; 515 };
517 516
518 qup_spi2_default: qup- 517 qup_spi2_default: qup-spi2-default-state {
519 pins = "gpio6" 518 pins = "gpio6", "gpio7", "gpio71", "gpio80";
520 function = "qu 519 function = "qup2";
521 drive-strength 520 drive-strength = <2>;
522 bias-pull-up; 521 bias-pull-up;
523 }; 522 };
524 523
525 qup_spi3_default: qup- 524 qup_spi3_default: qup-spi3-default-state {
526 pins = "gpio8" 525 pins = "gpio8", "gpio9", "gpio10", "gpio11";
527 function = "qu 526 function = "qup3";
528 drive-strength 527 drive-strength = <2>;
529 bias-pull-up; 528 bias-pull-up;
530 }; 529 };
531 530
532 qup_spi4_default: qup- 531 qup_spi4_default: qup-spi4-default-state {
533 pins = "gpio12 532 pins = "gpio12", "gpio13", "gpio96", "gpio97";
534 function = "qu 533 function = "qup4";
535 drive-strength 534 drive-strength = <2>;
536 bias-pull-up; 535 bias-pull-up;
537 }; 536 };
538 537
539 qup_spi5_default: qup- 538 qup_spi5_default: qup-spi5-default-state {
540 pins = "gpio14 539 pins = "gpio14", "gpio15", "gpio16", "gpio17";
541 function = "qu 540 function = "qup5";
542 drive-strength 541 drive-strength = <2>;
543 bias-pull-up; 542 bias-pull-up;
544 }; 543 };
545 544
546 qup_uart0_default: qup 545 qup_uart0_default: qup-uart0-default-state {
547 pins = "gpio0" 546 pins = "gpio0", "gpio1", "gpio2", "gpio3";
548 function = "qu 547 function = "qup0";
549 drive-strength 548 drive-strength = <2>;
550 bias-disable; 549 bias-disable;
551 }; 550 };
552 551
553 qup_uart4_default: qup 552 qup_uart4_default: qup-uart4-default-state {
554 pins = "gpio12 553 pins = "gpio12", "gpio13";
555 function = "qu 554 function = "qup4";
556 drive-strength 555 drive-strength = <2>;
557 bias-disable; 556 bias-disable;
558 }; 557 };
559 558
560 sdc1_state_on: sdc1-on 559 sdc1_state_on: sdc1-on-state {
561 clk-pins { 560 clk-pins {
562 pins = 561 pins = "sdc1_clk";
563 drive- 562 drive-strength = <16>;
564 bias-d 563 bias-disable;
565 }; 564 };
566 565
567 cmd-pins { 566 cmd-pins {
568 pins = 567 pins = "sdc1_cmd";
569 drive- 568 drive-strength = <10>;
570 bias-p 569 bias-pull-up;
571 }; 570 };
572 571
573 data-pins { 572 data-pins {
574 pins = 573 pins = "sdc1_data";
575 drive- 574 drive-strength = <10>;
576 bias-p 575 bias-pull-up;
577 }; 576 };
578 577
579 rclk-pins { 578 rclk-pins {
580 pins = 579 pins = "sdc1_rclk";
581 bias-p 580 bias-pull-down;
582 }; 581 };
583 }; 582 };
584 583
585 sdc1_state_off: sdc1-o 584 sdc1_state_off: sdc1-off-state {
586 clk-pins { 585 clk-pins {
587 pins = 586 pins = "sdc1_clk";
588 drive- 587 drive-strength = <2>;
589 bias-d 588 bias-disable;
590 }; 589 };
591 590
592 cmd-pins { 591 cmd-pins {
593 pins = 592 pins = "sdc1_cmd";
594 drive- 593 drive-strength = <2>;
595 bias-p 594 bias-pull-up;
596 }; 595 };
597 596
598 data-pins { 597 data-pins {
599 pins = 598 pins = "sdc1_data";
600 drive- 599 drive-strength = <2>;
601 bias-p 600 bias-pull-up;
602 }; 601 };
603 602
604 rclk-pins { 603 rclk-pins {
605 pins = 604 pins = "sdc1_rclk";
606 bias-p 605 bias-pull-down;
607 }; 606 };
608 }; 607 };
609 608
610 sdc2_state_on: sdc2-on 609 sdc2_state_on: sdc2-on-state {
611 clk-pins { 610 clk-pins {
612 pins = 611 pins = "sdc2_clk";
613 drive- 612 drive-strength = <16>;
614 bias-d 613 bias-disable;
615 }; 614 };
616 615
617 cmd-pins { 616 cmd-pins {
618 pins = 617 pins = "sdc2_cmd";
619 drive- 618 drive-strength = <10>;
620 bias-p 619 bias-pull-up;
621 }; 620 };
622 621
623 data-pins { 622 data-pins {
624 pins = 623 pins = "sdc2_data";
625 drive- 624 drive-strength = <10>;
626 bias-p 625 bias-pull-up;
627 }; 626 };
628 }; 627 };
629 628
630 sdc2_state_off: sdc2-o 629 sdc2_state_off: sdc2-off-state {
631 clk-pins { 630 clk-pins {
632 pins = 631 pins = "sdc2_clk";
633 drive- 632 drive-strength = <2>;
634 bias-d 633 bias-disable;
635 }; 634 };
636 635
637 cmd-pins { 636 cmd-pins {
638 pins = 637 pins = "sdc2_cmd";
639 drive- 638 drive-strength = <2>;
640 bias-p 639 bias-pull-up;
641 }; 640 };
642 641
643 data-pins { 642 data-pins {
644 pins = 643 pins = "sdc2_data";
645 drive- 644 drive-strength = <2>;
646 bias-p 645 bias-pull-up;
647 }; 646 };
648 }; 647 };
649 }; 648 };
650 649
651 gcc: clock-controller@1400000 650 gcc: clock-controller@1400000 {
652 compatible = "qcom,gcc 651 compatible = "qcom,gcc-qcm2290";
653 reg = <0x0 0x01400000 652 reg = <0x0 0x01400000 0x0 0x1f0000>;
654 clocks = <&rpmcc RPM_S 653 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>;
655 clock-names = "bi_tcxo 654 clock-names = "bi_tcxo", "sleep_clk";
656 #clock-cells = <1>; 655 #clock-cells = <1>;
657 #reset-cells = <1>; 656 #reset-cells = <1>;
658 #power-domain-cells = 657 #power-domain-cells = <1>;
659 }; 658 };
660 659
661 usb_hsphy: phy@1613000 { 660 usb_hsphy: phy@1613000 {
662 compatible = "qcom,qcm 661 compatible = "qcom,qcm2290-qusb2-phy";
663 reg = <0x0 0x01613000 662 reg = <0x0 0x01613000 0x0 0x180>;
664 663
665 clocks = <&gcc GCC_AHB 664 clocks = <&gcc GCC_AHB2PHY_USB_CLK>,
666 <&rpmcc RPM_S 665 <&rpmcc RPM_SMD_XO_CLK_SRC>;
667 clock-names = "cfg_ahb 666 clock-names = "cfg_ahb", "ref";
668 667
669 resets = <&gcc GCC_QUS 668 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
670 nvmem-cells = <&qusb2_ 669 nvmem-cells = <&qusb2_hstx_trim>;
671 #phy-cells = <0>; 670 #phy-cells = <0>;
672 671
673 status = "disabled"; 672 status = "disabled";
674 }; 673 };
675 674
676 usb_qmpphy: phy@1615000 { 675 usb_qmpphy: phy@1615000 {
677 compatible = "qcom,qcm 676 compatible = "qcom,qcm2290-qmp-usb3-phy";
678 reg = <0x0 0x01615000 677 reg = <0x0 0x01615000 0x0 0x1000>;
679 678
680 clocks = <&gcc GCC_AHB 679 clocks = <&gcc GCC_AHB2PHY_USB_CLK>,
681 <&gcc GCC_USB 680 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
682 <&gcc GCC_USB 681 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
683 <&gcc GCC_USB 682 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
684 clock-names = "cfg_ahb 683 clock-names = "cfg_ahb",
685 "ref", 684 "ref",
686 "com_aux 685 "com_aux",
687 "pipe"; 686 "pipe";
688 687
689 resets = <&gcc GCC_USB 688 resets = <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>,
690 <&gcc GCC_USB 689 <&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>;
691 reset-names = "phy", 690 reset-names = "phy",
692 "phy_phy 691 "phy_phy";
693 692
694 #clock-cells = <0>; 693 #clock-cells = <0>;
695 clock-output-names = " 694 clock-output-names = "usb3_phy_pipe_clk_src";
696 695
697 #phy-cells = <0>; 696 #phy-cells = <0>;
698 orientation-switch; 697 orientation-switch;
699 698
700 qcom,tcsr-reg = <&tcsr 699 qcom,tcsr-reg = <&tcsr_regs 0xb244>;
701 700
702 status = "disabled"; 701 status = "disabled";
703 702
704 ports { 703 ports {
705 #address-cells 704 #address-cells = <1>;
706 #size-cells = 705 #size-cells = <0>;
707 706
708 port@0 { 707 port@0 {
709 reg = 708 reg = <0>;
710 709
711 usb_qm 710 usb_qmpphy_out: endpoint {
712 }; 711 };
713 }; 712 };
714 713
715 port@1 { 714 port@1 {
716 reg = 715 reg = <1>;
717 716
718 usb_qm 717 usb_qmpphy_usb_ss_in: endpoint {
719 718 remote-endpoint = <&usb_dwc3_ss>;
720 }; 719 };
721 }; 720 };
722 }; 721 };
723 }; 722 };
724 723
725 system_noc: interconnect@18800 724 system_noc: interconnect@1880000 {
726 compatible = "qcom,qcm 725 compatible = "qcom,qcm2290-snoc";
727 reg = <0x0 0x01880000 726 reg = <0x0 0x01880000 0x0 0x60200>;
728 #interconnect-cells = 727 #interconnect-cells = <2>;
729 728
730 qup_virt: interconnect 729 qup_virt: interconnect-qup {
731 compatible = " 730 compatible = "qcom,qcm2290-qup-virt";
732 #interconnect- 731 #interconnect-cells = <2>;
733 }; 732 };
734 733
735 mmnrt_virt: interconne 734 mmnrt_virt: interconnect-mmnrt {
736 compatible = " 735 compatible = "qcom,qcm2290-mmnrt-virt";
737 #interconnect- 736 #interconnect-cells = <2>;
738 }; 737 };
739 738
740 mmrt_virt: interconnec 739 mmrt_virt: interconnect-mmrt {
741 compatible = " 740 compatible = "qcom,qcm2290-mmrt-virt";
742 #interconnect- 741 #interconnect-cells = <2>;
743 }; 742 };
744 }; 743 };
745 744
746 config_noc: interconnect@19000 745 config_noc: interconnect@1900000 {
747 compatible = "qcom,qcm 746 compatible = "qcom,qcm2290-cnoc";
748 reg = <0x0 0x01900000 747 reg = <0x0 0x01900000 0x0 0x8200>;
749 #interconnect-cells = 748 #interconnect-cells = <2>;
750 }; 749 };
751 750
752 qfprom@1b44000 { 751 qfprom@1b44000 {
753 compatible = "qcom,qcm 752 compatible = "qcom,qcm2290-qfprom", "qcom,qfprom";
754 reg = <0x0 0x01b44000 753 reg = <0x0 0x01b44000 0x0 0x3000>;
755 #address-cells = <1>; 754 #address-cells = <1>;
756 #size-cells = <1>; 755 #size-cells = <1>;
757 756
758 qusb2_hstx_trim: hstx- 757 qusb2_hstx_trim: hstx-trim@25b {
759 reg = <0x25b 0 758 reg = <0x25b 0x1>;
760 bits = <1 4>; 759 bits = <1 4>;
761 }; 760 };
762 <<
763 gpu_speed_bin: gpu-spe <<
764 reg = <0x2006 <<
765 bits = <5 8>; <<
766 }; <<
767 }; 761 };
768 762
769 pmu@1b8e300 { 763 pmu@1b8e300 {
770 compatible = "qcom,qcm 764 compatible = "qcom,qcm2290-cpu-bwmon", "qcom,sdm845-bwmon";
771 reg = <0x0 0x01b8e300 765 reg = <0x0 0x01b8e300 0x0 0x600>;
772 interrupts = <GIC_SPI 766 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
773 767
774 operating-points-v2 = 768 operating-points-v2 = <&cpu_bwmon_opp_table>;
775 interconnects = <&bimc 769 interconnects = <&bimc MASTER_APPSS_PROC RPM_ACTIVE_TAG
776 &bimc 770 &bimc SLAVE_EBI1 RPM_ACTIVE_TAG>;
777 771
778 cpu_bwmon_opp_table: o 772 cpu_bwmon_opp_table: opp-table {
779 compatible = " 773 compatible = "operating-points-v2";
780 774
781 opp-0 { 775 opp-0 {
782 opp-pe 776 opp-peak-kBps = <(200 * 4 * 1000)>;
783 }; 777 };
784 778
785 opp-1 { 779 opp-1 {
786 opp-pe 780 opp-peak-kBps = <(300 * 4 * 1000)>;
787 }; 781 };
788 782
789 opp-2 { 783 opp-2 {
790 opp-pe 784 opp-peak-kBps = <(451 * 4 * 1000)>;
791 }; 785 };
792 786
793 opp-3 { 787 opp-3 {
794 opp-pe 788 opp-peak-kBps = <(547 * 4 * 1000)>;
795 }; 789 };
796 790
797 opp-4 { 791 opp-4 {
798 opp-pe 792 opp-peak-kBps = <(681 * 4 * 1000)>;
799 }; 793 };
800 794
801 opp-5 { 795 opp-5 {
802 opp-pe 796 opp-peak-kBps = <(768 * 4 * 1000)>;
803 }; 797 };
804 798
805 opp-6 { 799 opp-6 {
806 opp-pe 800 opp-peak-kBps = <(1017 * 4 * 1000)>;
807 }; 801 };
808 802
809 opp-7 { 803 opp-7 {
810 opp-pe 804 opp-peak-kBps = <(1353 * 4 * 1000)>;
811 }; 805 };
812 806
813 opp-8 { 807 opp-8 {
814 opp-pe 808 opp-peak-kBps = <(1555 * 4 * 1000)>;
815 }; 809 };
816 810
817 opp-9 { 811 opp-9 {
818 opp-pe 812 opp-peak-kBps = <(1804 * 4 * 1000)>;
819 }; 813 };
820 }; 814 };
821 }; 815 };
822 816
823 spmi_bus: spmi@1c40000 { 817 spmi_bus: spmi@1c40000 {
824 compatible = "qcom,spm 818 compatible = "qcom,spmi-pmic-arb";
825 reg = <0x0 0x01c40000 819 reg = <0x0 0x01c40000 0x0 0x1100>,
826 <0x0 0x01e00000 820 <0x0 0x01e00000 0x0 0x2000000>,
827 <0x0 0x03e00000 821 <0x0 0x03e00000 0x0 0x100000>,
828 <0x0 0x03f00000 822 <0x0 0x03f00000 0x0 0xa0000>,
829 <0x0 0x01c0a000 823 <0x0 0x01c0a000 0x0 0x26000>;
830 reg-names = "core", 824 reg-names = "core",
831 "chnls", 825 "chnls",
832 "obsrvr", 826 "obsrvr",
833 "intr", 827 "intr",
834 "cnfg"; 828 "cnfg";
835 interrupts-extended = 829 interrupts-extended = <&mpm 86 IRQ_TYPE_LEVEL_HIGH>;
836 interrupt-names = "per 830 interrupt-names = "periph_irq";
837 qcom,ee = <0>; 831 qcom,ee = <0>;
838 qcom,channel = <0>; 832 qcom,channel = <0>;
839 #address-cells = <2>; 833 #address-cells = <2>;
840 #size-cells = <0>; 834 #size-cells = <0>;
841 interrupt-controller; 835 interrupt-controller;
842 #interrupt-cells = <4> 836 #interrupt-cells = <4>;
843 }; 837 };
844 838
845 tsens0: thermal-sensor@4411000 839 tsens0: thermal-sensor@4411000 {
846 compatible = "qcom,qcm 840 compatible = "qcom,qcm2290-tsens", "qcom,tsens-v2";
847 reg = <0x0 0x04411000 841 reg = <0x0 0x04411000 0x0 0x1ff>,
848 <0x0 0x04410000 842 <0x0 0x04410000 0x0 0x8>;
849 #qcom,sensors = <10>; 843 #qcom,sensors = <10>;
850 interrupts-extended = 844 interrupts-extended = <&mpm 2 IRQ_TYPE_LEVEL_HIGH>,
851 845 <&intc GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
852 interrupt-names = "upl 846 interrupt-names = "uplow", "critical";
853 #thermal-sensor-cells 847 #thermal-sensor-cells = <1>;
854 }; 848 };
855 849
856 rng: rng@4453000 { 850 rng: rng@4453000 {
857 compatible = "qcom,prn 851 compatible = "qcom,prng-ee";
858 reg = <0x0 0x04453000 852 reg = <0x0 0x04453000 0x0 0x1000>;
859 clocks = <&rpmcc RPM_S 853 clocks = <&rpmcc RPM_SMD_HWKM_CLK>;
860 clock-names = "core"; 854 clock-names = "core";
861 }; 855 };
862 856
863 bimc: interconnect@4480000 { 857 bimc: interconnect@4480000 {
864 compatible = "qcom,qcm 858 compatible = "qcom,qcm2290-bimc";
865 reg = <0x0 0x04480000 859 reg = <0x0 0x04480000 0x0 0x80000>;
866 #interconnect-cells = 860 #interconnect-cells = <2>;
867 }; 861 };
868 862
869 rpm_msg_ram: sram@45f0000 { 863 rpm_msg_ram: sram@45f0000 {
870 compatible = "qcom,rpm 864 compatible = "qcom,rpm-msg-ram", "mmio-sram";
871 reg = <0x0 0x045f0000 865 reg = <0x0 0x045f0000 0x0 0x7000>;
872 #address-cells = <1>; 866 #address-cells = <1>;
873 #size-cells = <1>; 867 #size-cells = <1>;
874 ranges = <0 0x0 0x045f 868 ranges = <0 0x0 0x045f0000 0x7000>;
875 869
876 apss_mpm: sram@1b8 { 870 apss_mpm: sram@1b8 {
877 reg = <0x1b8 0 871 reg = <0x1b8 0x48>;
878 }; 872 };
879 }; 873 };
880 874
881 sram@4690000 { 875 sram@4690000 {
882 compatible = "qcom,rpm 876 compatible = "qcom,rpm-stats";
883 reg = <0x0 0x04690000 877 reg = <0x0 0x04690000 0x0 0x10000>;
884 }; 878 };
885 879
886 sdhc_1: mmc@4744000 { 880 sdhc_1: mmc@4744000 {
887 compatible = "qcom,qcm 881 compatible = "qcom,qcm2290-sdhci", "qcom,sdhci-msm-v5";
888 reg = <0x0 0x04744000 882 reg = <0x0 0x04744000 0x0 0x1000>,
889 <0x0 0x04745000 883 <0x0 0x04745000 0x0 0x1000>,
890 <0x0 0x04748000 884 <0x0 0x04748000 0x0 0x8000>;
891 reg-names = "hc", 885 reg-names = "hc",
892 "cqhci", 886 "cqhci",
893 "ice"; 887 "ice";
894 888
895 interrupts = <GIC_SPI 889 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
896 <GIC_SPI 890 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
897 interrupt-names = "hc_ 891 interrupt-names = "hc_irq", "pwr_irq";
898 892
899 clocks = <&gcc GCC_SDC 893 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
900 <&gcc GCC_SDC 894 <&gcc GCC_SDCC1_APPS_CLK>,
901 <&rpmcc RPM_S 895 <&rpmcc RPM_SMD_XO_CLK_SRC>,
902 <&gcc GCC_SDC 896 <&gcc GCC_SDCC1_ICE_CORE_CLK>;
903 clock-names = "iface", 897 clock-names = "iface",
904 "core", 898 "core",
905 "xo", 899 "xo",
906 "ice"; 900 "ice";
907 901
908 resets = <&gcc GCC_SDC 902 resets = <&gcc GCC_SDCC1_BCR>;
909 903
910 power-domains = <&rpmp 904 power-domains = <&rpmpd QCM2290_VDDCX>;
911 operating-points-v2 = 905 operating-points-v2 = <&sdhc1_opp_table>;
912 iommus = <&apps_smmu 0 906 iommus = <&apps_smmu 0xc0 0x0>;
913 interconnects = <&syst 907 interconnects = <&system_noc MASTER_SDCC_1 RPM_ALWAYS_TAG
914 &bimc 908 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>,
915 <&bimc 909 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
916 &conf 910 &config_noc SLAVE_SDCC_1 RPM_ALWAYS_TAG>;
917 interconnect-names = " 911 interconnect-names = "sdhc-ddr",
918 " 912 "cpu-sdhc";
919 913
920 qcom,dll-config = <0x0 914 qcom,dll-config = <0x000f642c>;
921 qcom,ddr-config = <0x8 915 qcom,ddr-config = <0x80040868>;
922 bus-width = <8>; 916 bus-width = <8>;
923 917
924 status = "disabled"; 918 status = "disabled";
925 919
926 sdhc1_opp_table: opp-t 920 sdhc1_opp_table: opp-table {
927 compatible = " 921 compatible = "operating-points-v2";
928 922
929 opp-100000000 923 opp-100000000 {
930 opp-hz 924 opp-hz = /bits/ 64 <100000000>;
931 requir 925 required-opps = <&rpmpd_opp_low_svs>;
932 opp-pe 926 opp-peak-kBps = <250000 133320>;
933 opp-av 927 opp-avg-kBps = <102400 65000>;
934 }; 928 };
935 929
936 opp-192000000 930 opp-192000000 {
937 opp-hz 931 opp-hz = /bits/ 64 <192000000>;
938 requir 932 required-opps = <&rpmpd_opp_low_svs>;
939 opp-pe 933 opp-peak-kBps = <800000 300000>;
940 opp-av 934 opp-avg-kBps = <204800 200000>;
941 }; 935 };
942 936
943 opp-384000000 937 opp-384000000 {
944 opp-hz 938 opp-hz = /bits/ 64 <384000000>;
945 requir 939 required-opps = <&rpmpd_opp_svs_plus>;
946 opp-pe 940 opp-peak-kBps = <800000 300000>;
947 opp-av 941 opp-avg-kBps = <204800 200000>;
948 }; 942 };
949 }; 943 };
950 }; 944 };
951 945
952 sdhc_2: mmc@4784000 { 946 sdhc_2: mmc@4784000 {
953 compatible = "qcom,qcm 947 compatible = "qcom,qcm2290-sdhci", "qcom,sdhci-msm-v5";
954 reg = <0x0 0x04784000 948 reg = <0x0 0x04784000 0x0 0x1000>;
955 reg-names = "hc"; 949 reg-names = "hc";
956 950
957 interrupts = <GIC_SPI 951 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
958 <GIC_SPI 952 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
959 interrupt-names = "hc_ 953 interrupt-names = "hc_irq", "pwr_irq";
960 954
961 clocks = <&gcc GCC_SDC 955 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
962 <&gcc GCC_SDC 956 <&gcc GCC_SDCC2_APPS_CLK>,
963 <&rpmcc RPM_S 957 <&rpmcc RPM_SMD_XO_CLK_SRC>;
964 clock-names = "iface", 958 clock-names = "iface",
965 "core", 959 "core",
966 "xo"; 960 "xo";
967 961
968 resets = <&gcc GCC_SDC 962 resets = <&gcc GCC_SDCC2_BCR>;
969 963
970 power-domains = <&rpmp 964 power-domains = <&rpmpd QCM2290_VDDCX>;
971 operating-points-v2 = 965 operating-points-v2 = <&sdhc2_opp_table>;
972 iommus = <&apps_smmu 0 966 iommus = <&apps_smmu 0xa0 0x0>;
973 interconnects = <&syst 967 interconnects = <&system_noc MASTER_SDCC_2 RPM_ALWAYS_TAG
974 &bimc 968 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>,
975 <&bimc 969 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
976 &conf 970 &config_noc SLAVE_SDCC_2 RPM_ALWAYS_TAG>;
977 interconnect-names = " 971 interconnect-names = "sdhc-ddr",
978 " 972 "cpu-sdhc";
979 973
980 qcom,dll-config = <0x0 974 qcom,dll-config = <0x0007642c>;
981 qcom,ddr-config = <0x8 975 qcom,ddr-config = <0x80040868>;
982 bus-width = <4>; 976 bus-width = <4>;
983 977
984 status = "disabled"; 978 status = "disabled";
985 979
986 sdhc2_opp_table: opp-t 980 sdhc2_opp_table: opp-table {
987 compatible = " 981 compatible = "operating-points-v2";
988 982
989 opp-100000000 983 opp-100000000 {
990 opp-hz 984 opp-hz = /bits/ 64 <100000000>;
991 requir 985 required-opps = <&rpmpd_opp_low_svs>;
992 opp-pe 986 opp-peak-kBps = <250000 133320>;
993 opp-av 987 opp-avg-kBps = <261438 150000>;
994 }; 988 };
995 989
996 opp-202000000 990 opp-202000000 {
997 opp-hz 991 opp-hz = /bits/ 64 <202000000>;
998 requir 992 required-opps = <&rpmpd_opp_svs_plus>;
999 opp-pe 993 opp-peak-kBps = <800000 300000>;
1000 opp-a 994 opp-avg-kBps = <261438 300000>;
1001 }; 995 };
1002 }; 996 };
1003 }; 997 };
1004 998
1005 gpi_dma0: dma-controller@4a00 999 gpi_dma0: dma-controller@4a00000 {
1006 compatible = "qcom,qc 1000 compatible = "qcom,qcm2290-gpi-dma", "qcom,sm6350-gpi-dma";
1007 reg = <0x0 0x04a00000 1001 reg = <0x0 0x04a00000 0x0 0x60000>;
1008 interrupts = <GIC_SPI 1002 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1009 <GIC_SPI 1003 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1010 <GIC_SPI 1004 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
1011 <GIC_SPI 1005 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
1012 <GIC_SPI 1006 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
1013 <GIC_SPI 1007 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
1014 <GIC_SPI 1008 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
1015 <GIC_SPI 1009 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
1016 <GIC_SPI 1010 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
1017 <GIC_SPI 1011 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1018 dma-channels = <10>; 1012 dma-channels = <10>;
1019 dma-channel-mask = <0 1013 dma-channel-mask = <0x1f>;
1020 iommus = <&apps_smmu 1014 iommus = <&apps_smmu 0xf6 0x0>;
1021 #dma-cells = <3>; 1015 #dma-cells = <3>;
1022 status = "disabled"; 1016 status = "disabled";
1023 }; 1017 };
1024 1018
1025 qupv3_id_0: geniqup@4ac0000 { 1019 qupv3_id_0: geniqup@4ac0000 {
1026 compatible = "qcom,ge 1020 compatible = "qcom,geni-se-qup";
1027 reg = <0x0 0x04ac0000 1021 reg = <0x0 0x04ac0000 0x0 0x2000>;
1028 clocks = <&gcc GCC_QU 1022 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1029 <&gcc GCC_QU 1023 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1030 clock-names = "m-ahb" 1024 clock-names = "m-ahb", "s-ahb";
1031 iommus = <&apps_smmu 1025 iommus = <&apps_smmu 0xe3 0x0>;
1032 #address-cells = <2>; 1026 #address-cells = <2>;
1033 #size-cells = <2>; 1027 #size-cells = <2>;
1034 ranges; 1028 ranges;
1035 status = "disabled"; 1029 status = "disabled";
1036 1030
1037 i2c0: i2c@4a80000 { 1031 i2c0: i2c@4a80000 {
1038 compatible = 1032 compatible = "qcom,geni-i2c";
1039 reg = <0x0 0x 1033 reg = <0x0 0x04a80000 0x0 0x4000>;
1040 interrupts = 1034 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
1041 clocks = <&gc 1035 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1042 clock-names = 1036 clock-names = "se";
1043 pinctrl-0 = < 1037 pinctrl-0 = <&qup_i2c0_default>;
1044 pinctrl-names 1038 pinctrl-names = "default";
1045 dmas = <&gpi_ 1039 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1046 <&gpi_ 1040 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1047 dma-names = " 1041 dma-names = "tx", "rx";
1048 interconnects 1042 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1049 1043 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1050 1044 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
1051 1045 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
1052 1046 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
1053 1047 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>;
1054 interconnect- 1048 interconnect-names = "qup-core",
1055 1049 "qup-config",
1056 1050 "qup-memory";
1057 #address-cell 1051 #address-cells = <1>;
1058 #size-cells = 1052 #size-cells = <0>;
1059 status = "dis 1053 status = "disabled";
1060 }; 1054 };
1061 1055
1062 spi0: spi@4a80000 { 1056 spi0: spi@4a80000 {
1063 compatible = 1057 compatible = "qcom,geni-spi";
1064 reg = <0x0 0x 1058 reg = <0x0 0x04a80000 0x0 0x4000>;
1065 interrupts = 1059 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
1066 clocks = <&gc 1060 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1067 clock-names = 1061 clock-names = "se";
1068 pinctrl-0 = < 1062 pinctrl-0 = <&qup_spi0_default>;
1069 pinctrl-names 1063 pinctrl-names = "default";
1070 dmas = <&gpi_ 1064 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1071 <&gpi_ 1065 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1072 dma-names = " 1066 dma-names = "tx", "rx";
1073 interconnects 1067 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1074 1068 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1075 1069 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
1076 1070 &config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>;
1077 interconnect- 1071 interconnect-names = "qup-core",
1078 1072 "qup-config";
1079 #address-cell 1073 #address-cells = <1>;
1080 #size-cells = 1074 #size-cells = <0>;
1081 status = "dis 1075 status = "disabled";
1082 }; 1076 };
1083 1077
1084 uart0: serial@4a80000 1078 uart0: serial@4a80000 {
1085 compatible = 1079 compatible = "qcom,geni-uart";
1086 reg = <0x0 0x 1080 reg = <0x0 0x04a80000 0x0 0x4000>;
1087 interrupts = 1081 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
1088 clocks = <&gc 1082 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1089 clock-names = 1083 clock-names = "se";
1090 pinctrl-0 = < 1084 pinctrl-0 = <&qup_uart0_default>;
1091 pinctrl-names 1085 pinctrl-names = "default";
1092 interconnects 1086 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1093 1087 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1094 1088 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
1095 1089 &config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>;
1096 interconnect- 1090 interconnect-names = "qup-core",
1097 1091 "qup-config";
1098 status = "dis 1092 status = "disabled";
1099 }; 1093 };
1100 1094
1101 i2c1: i2c@4a84000 { 1095 i2c1: i2c@4a84000 {
1102 compatible = 1096 compatible = "qcom,geni-i2c";
1103 reg = <0x0 0x 1097 reg = <0x0 0x04a84000 0x0 0x4000>;
1104 interrupts = 1098 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
1105 clocks = <&gc 1099 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1106 clock-names = 1100 clock-names = "se";
1107 pinctrl-0 = < 1101 pinctrl-0 = <&qup_i2c1_default>;
1108 pinctrl-names 1102 pinctrl-names = "default";
1109 dmas = <&gpi_ 1103 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1110 <&gpi_ 1104 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1111 dma-names = " 1105 dma-names = "tx", "rx";
1112 interconnects 1106 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1113 1107 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1114 1108 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
1115 1109 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
1116 1110 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
1117 1111 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>;
1118 interconnect- 1112 interconnect-names = "qup-core",
1119 1113 "qup-config",
1120 1114 "qup-memory";
1121 #address-cell 1115 #address-cells = <1>;
1122 #size-cells = 1116 #size-cells = <0>;
1123 status = "dis 1117 status = "disabled";
1124 }; 1118 };
1125 1119
1126 spi1: spi@4a84000 { 1120 spi1: spi@4a84000 {
1127 compatible = 1121 compatible = "qcom,geni-spi";
1128 reg = <0x0 0x 1122 reg = <0x0 0x04a84000 0x0 0x4000>;
1129 interrupts = 1123 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
1130 clocks = <&gc 1124 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1131 clock-names = 1125 clock-names = "se";
1132 pinctrl-0 = < 1126 pinctrl-0 = <&qup_spi1_default>;
1133 pinctrl-names 1127 pinctrl-names = "default";
1134 dmas = <&gpi_ 1128 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1135 <&gpi_ 1129 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1136 dma-names = " 1130 dma-names = "tx", "rx";
1137 interconnects 1131 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1138 1132 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1139 1133 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
1140 1134 &config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>;
1141 interconnect- 1135 interconnect-names = "qup-core",
1142 1136 "qup-config";
1143 #address-cell 1137 #address-cells = <1>;
1144 #size-cells = 1138 #size-cells = <0>;
1145 status = "dis 1139 status = "disabled";
1146 }; 1140 };
1147 1141
1148 i2c2: i2c@4a88000 { 1142 i2c2: i2c@4a88000 {
1149 compatible = 1143 compatible = "qcom,geni-i2c";
1150 reg = <0x0 0x 1144 reg = <0x0 0x04a88000 0x0 0x4000>;
1151 interrupts = 1145 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
1152 clocks = <&gc 1146 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1153 clock-names = 1147 clock-names = "se";
1154 pinctrl-0 = < 1148 pinctrl-0 = <&qup_i2c2_default>;
1155 pinctrl-names 1149 pinctrl-names = "default";
1156 dmas = <&gpi_ 1150 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1157 <&gpi_ 1151 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1158 dma-names = " 1152 dma-names = "tx", "rx";
1159 interconnects 1153 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1160 1154 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1161 1155 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
1162 1156 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
1163 1157 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
1164 1158 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>;
1165 interconnect- 1159 interconnect-names = "qup-core",
1166 1160 "qup-config",
1167 1161 "qup-memory";
1168 #address-cell 1162 #address-cells = <1>;
1169 #size-cells = 1163 #size-cells = <0>;
1170 status = "dis 1164 status = "disabled";
1171 }; 1165 };
1172 1166
1173 spi2: spi@4a88000 { 1167 spi2: spi@4a88000 {
1174 compatible = 1168 compatible = "qcom,geni-spi";
1175 reg = <0x0 0x 1169 reg = <0x0 0x04a88000 0x0 0x4000>;
1176 interrupts = 1170 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
1177 clocks = <&gc 1171 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1178 clock-names = 1172 clock-names = "se";
1179 pinctrl-0 = < 1173 pinctrl-0 = <&qup_spi2_default>;
1180 pinctrl-names 1174 pinctrl-names = "default";
1181 dmas = <&gpi_ 1175 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1182 <&gpi_ 1176 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1183 dma-names = " 1177 dma-names = "tx", "rx";
1184 interconnects 1178 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1185 1179 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1186 1180 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
1187 1181 &config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>;
1188 interconnect- 1182 interconnect-names = "qup-core",
1189 1183 "qup-config";
1190 #address-cell 1184 #address-cells = <1>;
1191 #size-cells = 1185 #size-cells = <0>;
1192 status = "dis 1186 status = "disabled";
1193 }; 1187 };
1194 1188
1195 i2c3: i2c@4a8c000 { 1189 i2c3: i2c@4a8c000 {
1196 compatible = 1190 compatible = "qcom,geni-i2c";
1197 reg = <0x0 0x 1191 reg = <0x0 0x04a8c000 0x0 0x4000>;
1198 interrupts = 1192 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
1199 clocks = <&gc 1193 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1200 clock-names = 1194 clock-names = "se";
1201 pinctrl-0 = < 1195 pinctrl-0 = <&qup_i2c3_default>;
1202 pinctrl-names 1196 pinctrl-names = "default";
1203 dmas = <&gpi_ 1197 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1204 <&gpi_ 1198 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1205 dma-names = " 1199 dma-names = "tx", "rx";
1206 interconnects 1200 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1207 1201 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1208 1202 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
1209 1203 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
1210 1204 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
1211 1205 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>;
1212 interconnect- 1206 interconnect-names = "qup-core",
1213 1207 "qup-config",
1214 1208 "qup-memory";
1215 #address-cell 1209 #address-cells = <1>;
1216 #size-cells = 1210 #size-cells = <0>;
1217 status = "dis 1211 status = "disabled";
1218 }; 1212 };
1219 1213
1220 spi3: spi@4a8c000 { 1214 spi3: spi@4a8c000 {
1221 compatible = 1215 compatible = "qcom,geni-spi";
1222 reg = <0x0 0x 1216 reg = <0x0 0x04a8c000 0x0 0x4000>;
1223 interrupts = 1217 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
1224 clocks = <&gc 1218 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1225 clock-names = 1219 clock-names = "se";
1226 pinctrl-0 = < 1220 pinctrl-0 = <&qup_spi3_default>;
1227 pinctrl-names 1221 pinctrl-names = "default";
1228 dmas = <&gpi_ 1222 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1229 <&gpi_ 1223 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1230 dma-names = " 1224 dma-names = "tx", "rx";
1231 interconnects 1225 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1232 1226 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1233 1227 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
1234 1228 &config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>;
1235 interconnect- 1229 interconnect-names = "qup-core",
1236 1230 "qup-config";
1237 #address-cell 1231 #address-cells = <1>;
1238 #size-cells = 1232 #size-cells = <0>;
1239 status = "dis 1233 status = "disabled";
1240 }; 1234 };
1241 1235
1242 i2c4: i2c@4a90000 { 1236 i2c4: i2c@4a90000 {
1243 compatible = 1237 compatible = "qcom,geni-i2c";
1244 reg = <0x0 0x 1238 reg = <0x0 0x04a90000 0x0 0x4000>;
1245 interrupts = 1239 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
1246 clocks = <&gc 1240 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1247 clock-names = 1241 clock-names = "se";
1248 pinctrl-0 = < 1242 pinctrl-0 = <&qup_i2c4_default>;
1249 pinctrl-names 1243 pinctrl-names = "default";
1250 dmas = <&gpi_ 1244 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1251 <&gpi_ 1245 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1252 dma-names = " 1246 dma-names = "tx", "rx";
1253 interconnects 1247 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1254 1248 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1255 1249 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
1256 1250 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
1257 1251 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
1258 1252 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>;
1259 interconnect- 1253 interconnect-names = "qup-core",
1260 1254 "qup-config",
1261 1255 "qup-memory";
1262 #address-cell 1256 #address-cells = <1>;
1263 #size-cells = 1257 #size-cells = <0>;
1264 status = "dis 1258 status = "disabled";
1265 }; 1259 };
1266 1260
1267 spi4: spi@4a90000 { 1261 spi4: spi@4a90000 {
1268 compatible = 1262 compatible = "qcom,geni-spi";
1269 reg = <0x0 0x 1263 reg = <0x0 0x04a90000 0x0 0x4000>;
1270 interrupts = 1264 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
1271 clock-names = 1265 clock-names = "se";
1272 clocks = <&gc 1266 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1273 pinctrl-names 1267 pinctrl-names = "default";
1274 pinctrl-0 = < 1268 pinctrl-0 = <&qup_spi4_default>;
1275 dmas = <&gpi_ 1269 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1276 <&gpi_ 1270 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1277 dma-names = " 1271 dma-names = "tx", "rx";
1278 interconnects 1272 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1279 1273 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1280 1274 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
1281 1275 &config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>;
1282 interconnect- 1276 interconnect-names = "qup-core",
1283 1277 "qup-config";
1284 #address-cell 1278 #address-cells = <1>;
1285 #size-cells = 1279 #size-cells = <0>;
1286 status = "dis 1280 status = "disabled";
1287 }; 1281 };
1288 1282
1289 uart4: serial@4a90000 1283 uart4: serial@4a90000 {
1290 compatible = 1284 compatible = "qcom,geni-uart";
1291 reg = <0x0 0x 1285 reg = <0x0 0x04a90000 0x0 0x4000>;
1292 interrupts = 1286 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
1293 clocks = <&gc 1287 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1294 clock-names = 1288 clock-names = "se";
1295 pinctrl-0 = < 1289 pinctrl-0 = <&qup_uart4_default>;
1296 pinctrl-names 1290 pinctrl-names = "default";
1297 interconnects 1291 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1298 1292 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1299 1293 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
1300 1294 &config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>;
1301 interconnect- 1295 interconnect-names = "qup-core",
1302 1296 "qup-config";
1303 status = "dis 1297 status = "disabled";
1304 }; 1298 };
1305 1299
1306 i2c5: i2c@4a94000 { 1300 i2c5: i2c@4a94000 {
1307 compatible = 1301 compatible = "qcom,geni-i2c";
1308 reg = <0x0 0x 1302 reg = <0x0 0x04a94000 0x0 0x4000>;
1309 interrupts = 1303 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
1310 clocks = <&gc 1304 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1311 clock-names = 1305 clock-names = "se";
1312 pinctrl-0 = < 1306 pinctrl-0 = <&qup_i2c5_default>;
1313 pinctrl-names 1307 pinctrl-names = "default";
1314 dmas = <&gpi_ 1308 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1315 <&gpi_ 1309 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1316 dma-names = " 1310 dma-names = "tx", "rx";
1317 interconnects 1311 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1318 1312 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1319 1313 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
1320 1314 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
1321 1315 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
1322 1316 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>;
1323 interconnect- 1317 interconnect-names = "qup-core",
1324 1318 "qup-config",
1325 1319 "qup-memory";
1326 #address-cell 1320 #address-cells = <1>;
1327 #size-cells = 1321 #size-cells = <0>;
1328 status = "dis 1322 status = "disabled";
1329 }; 1323 };
1330 1324
1331 spi5: spi@4a94000 { 1325 spi5: spi@4a94000 {
1332 compatible = 1326 compatible = "qcom,geni-spi";
1333 reg = <0x0 0x 1327 reg = <0x0 0x04a94000 0x0 0x4000>;
1334 interrupts = 1328 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
1335 clocks = <&gc 1329 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1336 clock-names = 1330 clock-names = "se";
1337 pinctrl-0 = < 1331 pinctrl-0 = <&qup_spi5_default>;
1338 pinctrl-names 1332 pinctrl-names = "default";
1339 dmas = <&gpi_ 1333 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1340 <&gpi_ 1334 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1341 dma-names = " 1335 dma-names = "tx", "rx";
1342 interconnects 1336 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1343 1337 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1344 1338 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
1345 1339 &config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>;
1346 interconnect- 1340 interconnect-names = "qup-core",
1347 1341 "qup-config";
1348 #address-cell 1342 #address-cells = <1>;
1349 #size-cells = 1343 #size-cells = <0>;
1350 status = "dis 1344 status = "disabled";
1351 }; 1345 };
1352 }; 1346 };
1353 1347
1354 usb: usb@4ef8800 { 1348 usb: usb@4ef8800 {
1355 compatible = "qcom,qc 1349 compatible = "qcom,qcm2290-dwc3", "qcom,dwc3";
1356 reg = <0x0 0x04ef8800 1350 reg = <0x0 0x04ef8800 0x0 0x400>;
1357 interrupts-extended = 1351 interrupts-extended = <&intc GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
1358 1352 <&mpm 12 IRQ_TYPE_LEVEL_HIGH>;
1359 interrupt-names = "hs 1353 interrupt-names = "hs_phy_irq",
1360 "ss 1354 "ss_phy_irq";
1361 1355
1362 clocks = <&gcc GCC_CF 1356 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
1363 <&gcc GCC_US 1357 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
1364 <&gcc GCC_SY 1358 <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>,
1365 <&gcc GCC_US 1359 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
1366 <&gcc GCC_US 1360 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1367 <&gcc GCC_US 1361 <&gcc GCC_USB3_PRIM_CLKREF_CLK>;
1368 clock-names = "cfg_no 1362 clock-names = "cfg_noc",
1369 "core", 1363 "core",
1370 "iface" 1364 "iface",
1371 "sleep" 1365 "sleep",
1372 "mock_u 1366 "mock_utmi",
1373 "xo"; 1367 "xo";
1374 1368
1375 assigned-clocks = <&g 1369 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1376 <&g 1370 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
1377 assigned-clock-rates 1371 assigned-clock-rates = <19200000>, <133333333>;
1378 1372
1379 resets = <&gcc GCC_US 1373 resets = <&gcc GCC_USB30_PRIM_BCR>;
1380 power-domains = <&gcc 1374 power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
1381 /* TODO: USB<->IPA pa 1375 /* TODO: USB<->IPA path */
1382 interconnects = <&sys 1376 interconnects = <&system_noc MASTER_USB3_0 RPM_ALWAYS_TAG
1383 &bim 1377 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>,
1384 <&bim 1378 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
1385 &con 1379 &config_noc SLAVE_USB3 RPM_ALWAYS_TAG>;
1386 interconnect-names = 1380 interconnect-names = "usb-ddr",
1387 1381 "apps-usb";
1388 wakeup-source; 1382 wakeup-source;
1389 1383
1390 #address-cells = <2>; 1384 #address-cells = <2>;
1391 #size-cells = <2>; 1385 #size-cells = <2>;
1392 ranges; 1386 ranges;
1393 1387
1394 status = "disabled"; 1388 status = "disabled";
1395 1389
1396 usb_dwc3: usb@4e00000 1390 usb_dwc3: usb@4e00000 {
1397 compatible = 1391 compatible = "snps,dwc3";
1398 reg = <0x0 0x 1392 reg = <0x0 0x04e00000 0x0 0xcd00>;
1399 interrupts = 1393 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
1400 phys = <&usb_ 1394 phys = <&usb_hsphy>, <&usb_qmpphy>;
1401 phy-names = " 1395 phy-names = "usb2-phy", "usb3-phy";
1402 iommus = <&ap 1396 iommus = <&apps_smmu 0x120 0x0>;
1403 snps,dis_u2_s 1397 snps,dis_u2_susphy_quirk;
1404 snps,dis_enbl 1398 snps,dis_enblslpm_quirk;
1405 snps,has-lpm- 1399 snps,has-lpm-erratum;
1406 snps,hird-thr 1400 snps,hird-threshold = /bits/ 8 <0x10>;
1407 snps,usb3_lpm 1401 snps,usb3_lpm_capable;
1408 maximum-speed 1402 maximum-speed = "super-speed";
1409 dr_mode = "ot 1403 dr_mode = "otg";
1410 usb-role-swit 1404 usb-role-switch;
1411 1405
1412 ports { 1406 ports {
1413 #addr 1407 #address-cells = <1>;
1414 #size 1408 #size-cells = <0>;
1415 1409
1416 port@ 1410 port@0 {
1417 1411 reg = <0>;
1418 1412
1419 1413 usb_dwc3_hs: endpoint {
1420 1414 };
1421 }; 1415 };
1422 1416
1423 port@ 1417 port@1 {
1424 1418 reg = <1>;
1425 1419
1426 1420 usb_dwc3_ss: endpoint {
1427 1421 remote-endpoint = <&usb_qmpphy_usb_ss_in>;
1428 1422 };
1429 }; 1423 };
1430 }; 1424 };
1431 }; 1425 };
1432 }; 1426 };
1433 1427
1434 gpu: gpu@5900000 { <<
1435 compatible = "qcom,ad <<
1436 reg = <0x0 0x05900000 <<
1437 reg-names = "kgsl_3d0 <<
1438 <<
1439 interrupts = <GIC_SPI <<
1440 <<
1441 clocks = <&gpucc GPU_ <<
1442 <&gpucc GPU_ <<
1443 <&gcc GCC_BI <<
1444 <&gcc GCC_GP <<
1445 <&gpucc GPU_ <<
1446 <&gpucc GPU_ <<
1447 clock-names = "core", <<
1448 "iface" <<
1449 "mem_if <<
1450 "alt_me <<
1451 "gmu", <<
1452 "xo"; <<
1453 <<
1454 interconnects = <&bim <<
1455 &bim <<
1456 interconnect-names = <<
1457 <<
1458 iommus = <&adreno_smm <<
1459 <&adreno_smm <<
1460 operating-points-v2 = <<
1461 power-domains = <&rpm <<
1462 qcom,gmu = <&gmu_wrap <<
1463 <<
1464 nvmem-cells = <&gpu_s <<
1465 nvmem-cell-names = "s <<
1466 #cooling-cells = <2>; <<
1467 <<
1468 status = "disabled"; <<
1469 <<
1470 zap-shader { <<
1471 memory-region <<
1472 }; <<
1473 <<
1474 gpu_opp_table: opp-ta <<
1475 compatible = <<
1476 <<
1477 /* TODO: Scal <<
1478 opp-112320000 <<
1479 opp-h <<
1480 requi <<
1481 opp-p <<
1482 opp-s <<
1483 turbo <<
1484 }; <<
1485 <<
1486 opp-101760000 <<
1487 opp-h <<
1488 requi <<
1489 opp-p <<
1490 opp-s <<
1491 turbo <<
1492 }; <<
1493 <<
1494 opp-921600000 <<
1495 opp-h <<
1496 requi <<
1497 opp-p <<
1498 opp-s <<
1499 }; <<
1500 <<
1501 opp-844800000 <<
1502 opp-h <<
1503 requi <<
1504 opp-p <<
1505 opp-s <<
1506 }; <<
1507 <<
1508 opp-672000000 <<
1509 opp-h <<
1510 requi <<
1511 opp-p <<
1512 opp-s <<
1513 }; <<
1514 <<
1515 opp-537600000 <<
1516 opp-h <<
1517 requi <<
1518 opp-p <<
1519 opp-s <<
1520 }; <<
1521 <<
1522 opp-355200000 <<
1523 opp-h <<
1524 requi <<
1525 opp-p <<
1526 opp-s <<
1527 }; <<
1528 }; <<
1529 }; <<
1530 <<
1531 gmu_wrapper: gmu@596a000 { <<
1532 compatible = "qcom,ad <<
1533 reg = <0x0 0x0596a000 <<
1534 reg-names = "gmu"; <<
1535 power-domains = <&gpu <<
1536 <&gpu <<
1537 power-domain-names = <<
1538 <<
1539 }; <<
1540 <<
1541 gpucc: clock-controller@59900 <<
1542 compatible = "qcom,qc <<
1543 reg = <0x0 0x05990000 <<
1544 clocks = <&gcc GCC_GP <<
1545 <&rpmcc RPM_ <<
1546 <&gcc GCC_GP <<
1547 <&gcc GCC_GP <<
1548 power-domains = <&rpm <<
1549 required-opps = <&rpm <<
1550 #clock-cells = <1>; <<
1551 #reset-cells = <1>; <<
1552 #power-domain-cells = <<
1553 }; <<
1554 <<
1555 adreno_smmu: iommu@59a0000 { <<
1556 compatible = "qcom,qc <<
1557 "qcom,sm <<
1558 reg = <0x0 0x059a0000 <<
1559 interrupts = <GIC_SPI <<
1560 <GIC_SPI <<
1561 <GIC_SPI <<
1562 <GIC_SPI <<
1563 <GIC_SPI <<
1564 <GIC_SPI <<
1565 <GIC_SPI <<
1566 <GIC_SPI <<
1567 <GIC_SPI <<
1568 <<
1569 clocks = <&gcc GCC_GP <<
1570 <&gpucc GPU_ <<
1571 <&gcc GCC_GP <<
1572 clock-names = "mem", <<
1573 "hlos", <<
1574 "iface" <<
1575 <<
1576 power-domains = <&gpu <<
1577 <<
1578 #global-interrupts = <<
1579 #iommu-cells = <2>; <<
1580 }; <<
1581 <<
1582 mdss: display-subsystem@5e000 1428 mdss: display-subsystem@5e00000 {
1583 compatible = "qcom,qc 1429 compatible = "qcom,qcm2290-mdss";
1584 reg = <0x0 0x05e00000 1430 reg = <0x0 0x05e00000 0x0 0x1000>;
1585 reg-names = "mdss"; 1431 reg-names = "mdss";
1586 interrupts = <GIC_SPI 1432 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
1587 interrupt-controller; 1433 interrupt-controller;
1588 #interrupt-cells = <1 1434 #interrupt-cells = <1>;
1589 1435
1590 clocks = <&gcc GCC_DI 1436 clocks = <&gcc GCC_DISP_AHB_CLK>,
1591 <&gcc GCC_DI 1437 <&gcc GCC_DISP_HF_AXI_CLK>,
1592 <&dispcc DIS 1438 <&dispcc DISP_CC_MDSS_MDP_CLK>;
1593 clock-names = "iface" 1439 clock-names = "iface",
1594 "bus", 1440 "bus",
1595 "core"; 1441 "core";
1596 1442
1597 resets = <&dispcc DIS 1443 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
1598 1444
1599 power-domains = <&dis 1445 power-domains = <&dispcc MDSS_GDSC>;
1600 1446
1601 iommus = <&apps_smmu 1447 iommus = <&apps_smmu 0x420 0x2>,
1602 <&apps_smmu 1448 <&apps_smmu 0x421 0x0>;
1603 interconnects = <&mmr 1449 interconnects = <&mmrt_virt MASTER_MDP0 RPM_ALWAYS_TAG
1604 &bim 1450 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>,
1605 <&bim 1451 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
1606 &con 1452 &config_noc SLAVE_DISPLAY_CFG RPM_ALWAYS_TAG>;
1607 interconnect-names = 1453 interconnect-names = "mdp0-mem",
1608 1454 "cpu-cfg";
1609 1455
1610 #address-cells = <2>; 1456 #address-cells = <2>;
1611 #size-cells = <2>; 1457 #size-cells = <2>;
1612 ranges; 1458 ranges;
1613 1459
1614 status = "disabled"; 1460 status = "disabled";
1615 1461
1616 mdp: display-controll 1462 mdp: display-controller@5e01000 {
1617 compatible = 1463 compatible = "qcom,qcm2290-dpu";
1618 reg = <0x0 0x 1464 reg = <0x0 0x05e01000 0x0 0x8f000>,
1619 <0x0 0x 1465 <0x0 0x05eb0000 0x0 0x2008>;
1620 reg-names = " 1466 reg-names = "mdp",
1621 " 1467 "vbif";
1622 1468
1623 interrupt-par 1469 interrupt-parent = <&mdss>;
1624 interrupts = 1470 interrupts = <0>;
1625 1471
1626 clocks = <&gc 1472 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
1627 <&di 1473 <&dispcc DISP_CC_MDSS_AHB_CLK>,
1628 <&di 1474 <&dispcc DISP_CC_MDSS_MDP_CLK>,
1629 <&di 1475 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
1630 <&di 1476 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
1631 clock-names = 1477 clock-names = "bus",
1632 1478 "iface",
1633 1479 "core",
1634 1480 "lut",
1635 1481 "vsync";
1636 1482
1637 operating-poi 1483 operating-points-v2 = <&mdp_opp_table>;
1638 power-domains 1484 power-domains = <&rpmpd QCM2290_VDDCX>;
1639 1485
1640 ports { 1486 ports {
1641 #addr 1487 #address-cells = <1>;
1642 #size 1488 #size-cells = <0>;
1643 1489
1644 port@ 1490 port@0 {
1645 1491 reg = <0>;
1646 1492 dpu_intf1_out: endpoint {
1647 1493 remote-endpoint = <&mdss_dsi0_in>;
1648 1494 };
1649 }; 1495 };
1650 }; 1496 };
1651 1497
1652 mdp_opp_table 1498 mdp_opp_table: opp-table {
1653 compa 1499 compatible = "operating-points-v2";
1654 1500
1655 opp-1 1501 opp-19200000 {
1656 1502 opp-hz = /bits/ 64 <19200000>;
1657 1503 required-opps = <&rpmpd_opp_min_svs>;
1658 }; 1504 };
1659 1505
1660 opp-1 1506 opp-192000000 {
1661 1507 opp-hz = /bits/ 64 <192000000>;
1662 1508 required-opps = <&rpmpd_opp_low_svs>;
1663 }; 1509 };
1664 1510
1665 opp-2 1511 opp-256000000 {
1666 1512 opp-hz = /bits/ 64 <256000000>;
1667 1513 required-opps = <&rpmpd_opp_svs>;
1668 }; 1514 };
1669 1515
1670 opp-3 1516 opp-307200000 {
1671 1517 opp-hz = /bits/ 64 <307200000>;
1672 1518 required-opps = <&rpmpd_opp_svs_plus>;
1673 }; 1519 };
1674 1520
1675 opp-3 1521 opp-384000000 {
1676 1522 opp-hz = /bits/ 64 <384000000>;
1677 1523 required-opps = <&rpmpd_opp_nom>;
1678 }; 1524 };
1679 }; 1525 };
1680 }; 1526 };
1681 1527
1682 mdss_dsi0: dsi@5e9400 1528 mdss_dsi0: dsi@5e94000 {
1683 compatible = 1529 compatible = "qcom,qcm2290-dsi-ctrl", "qcom,mdss-dsi-ctrl";
1684 reg = <0x0 0x 1530 reg = <0x0 0x05e94000 0x0 0x400>;
1685 reg-names = " 1531 reg-names = "dsi_ctrl";
1686 1532
1687 interrupt-par 1533 interrupt-parent = <&mdss>;
1688 interrupts = 1534 interrupts = <4>;
1689 1535
1690 clocks = <&di 1536 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
1691 <&di 1537 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
1692 <&di 1538 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
1693 <&di 1539 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
1694 <&di 1540 <&dispcc DISP_CC_MDSS_AHB_CLK>,
1695 <&gc 1541 <&gcc GCC_DISP_HF_AXI_CLK>;
1696 clock-names = 1542 clock-names = "byte",
1697 1543 "byte_intf",
1698 1544 "pixel",
1699 1545 "core",
1700 1546 "iface",
1701 1547 "bus";
1702 1548
1703 assigned-cloc 1549 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
1704 1550 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
1705 assigned-cloc 1551 assigned-clock-parents = <&mdss_dsi0_phy 0>,
1706 1552 <&mdss_dsi0_phy 1>;
1707 1553
1708 operating-poi 1554 operating-points-v2 = <&dsi_opp_table>;
1709 power-domains 1555 power-domains = <&rpmpd QCM2290_VDDCX>;
1710 phys = <&mdss 1556 phys = <&mdss_dsi0_phy>;
1711 1557
1712 #address-cell 1558 #address-cells = <1>;
1713 #size-cells = 1559 #size-cells = <0>;
1714 1560
1715 status = "dis 1561 status = "disabled";
1716 1562
1717 dsi_opp_table 1563 dsi_opp_table: opp-table {
1718 compa 1564 compatible = "operating-points-v2";
1719 1565
1720 opp-1 1566 opp-19200000 {
1721 1567 opp-hz = /bits/ 64 <19200000>;
1722 1568 required-opps = <&rpmpd_opp_min_svs>;
1723 }; 1569 };
1724 1570
1725 opp-1 1571 opp-164000000 {
1726 1572 opp-hz = /bits/ 64 <164000000>;
1727 1573 required-opps = <&rpmpd_opp_low_svs>;
1728 }; 1574 };
1729 1575
1730 opp-1 1576 opp-187500000 {
1731 1577 opp-hz = /bits/ 64 <187500000>;
1732 1578 required-opps = <&rpmpd_opp_svs>;
1733 }; 1579 };
1734 }; 1580 };
1735 1581
1736 ports { 1582 ports {
1737 #addr 1583 #address-cells = <1>;
1738 #size 1584 #size-cells = <0>;
1739 1585
1740 port@ 1586 port@0 {
1741 1587 reg = <0>;
1742 1588
1743 1589 mdss_dsi0_in: endpoint {
1744 1590 remote-endpoint = <&dpu_intf1_out>;
1745 1591 };
1746 }; 1592 };
1747 1593
1748 port@ 1594 port@1 {
1749 1595 reg = <1>;
1750 1596
1751 1597 mdss_dsi0_out: endpoint {
1752 1598 };
1753 }; 1599 };
1754 }; 1600 };
1755 }; 1601 };
1756 1602
1757 mdss_dsi0_phy: phy@5e 1603 mdss_dsi0_phy: phy@5e94400 {
1758 compatible = 1604 compatible = "qcom,dsi-phy-14nm-2290";
1759 reg = <0x0 0x 1605 reg = <0x0 0x05e94400 0x0 0x100>,
1760 <0x0 0x 1606 <0x0 0x05e94500 0x0 0x300>,
1761 <0x0 0x 1607 <0x0 0x05e94800 0x0 0x188>;
1762 reg-names = " 1608 reg-names = "dsi_phy",
1763 " 1609 "dsi_phy_lane",
1764 " 1610 "dsi_pll";
1765 1611
1766 clocks = <&di 1612 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
1767 <&rp 1613 <&rpmcc RPM_SMD_XO_CLK_SRC>;
1768 clock-names = 1614 clock-names = "iface",
1769 1615 "ref";
1770 1616
1771 power-domains 1617 power-domains = <&rpmpd QCM2290_VDDMX>;
1772 required-opps 1618 required-opps = <&rpmpd_opp_nom>;
1773 1619
1774 #clock-cells 1620 #clock-cells = <1>;
1775 #phy-cells = 1621 #phy-cells = <0>;
1776 1622
1777 status = "dis 1623 status = "disabled";
1778 }; 1624 };
1779 }; 1625 };
1780 1626
1781 dispcc: clock-controller@5f00 1627 dispcc: clock-controller@5f00000 {
1782 compatible = "qcom,qc 1628 compatible = "qcom,qcm2290-dispcc";
1783 reg = <0x0 0x05f00000 1629 reg = <0x0 0x05f00000 0x0 0x20000>;
1784 clocks = <&rpmcc RPM_ 1630 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1785 <&rpmcc RPM_ 1631 <&rpmcc RPM_SMD_XO_A_CLK_SRC>,
1786 <&gcc GCC_DI 1632 <&gcc GCC_DISP_GPLL0_CLK_SRC>,
1787 <&gcc GCC_DI 1633 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
1788 <&mdss_dsi0_ 1634 <&mdss_dsi0_phy 0>,
1789 <&mdss_dsi0_ 1635 <&mdss_dsi0_phy 1>;
1790 clock-names = "bi_tcx 1636 clock-names = "bi_tcxo",
1791 "bi_tcx 1637 "bi_tcxo_ao",
1792 "gcc_di 1638 "gcc_disp_gpll0_clk_src",
1793 "gcc_di 1639 "gcc_disp_gpll0_div_clk_src",
1794 "dsi0_p 1640 "dsi0_phy_pll_out_byteclk",
1795 "dsi0_p 1641 "dsi0_phy_pll_out_dsiclk";
1796 #power-domain-cells = 1642 #power-domain-cells = <1>;
1797 #clock-cells = <1>; 1643 #clock-cells = <1>;
1798 #reset-cells = <1>; 1644 #reset-cells = <1>;
1799 }; 1645 };
1800 1646
1801 remoteproc_mpss: remoteproc@6 1647 remoteproc_mpss: remoteproc@6080000 {
1802 compatible = "qcom,qc 1648 compatible = "qcom,qcm2290-mpss-pas", "qcom,sm6115-mpss-pas";
1803 reg = <0x0 0x06080000 1649 reg = <0x0 0x06080000 0x0 0x100>;
1804 1650
1805 interrupts-extended = 1651 interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING>,
1806 1652 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1807 1653 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1808 1654 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1809 1655 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
1810 1656 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
1811 interrupt-names = "wd 1657 interrupt-names = "wdog",
1812 "fa 1658 "fatal",
1813 "re 1659 "ready",
1814 "ha 1660 "handover",
1815 "st 1661 "stop-ack",
1816 "sh 1662 "shutdown-ack";
1817 1663
1818 clocks = <&rpmcc RPM_ 1664 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
1819 clock-names = "xo"; 1665 clock-names = "xo";
1820 1666
1821 power-domains = <&rpm 1667 power-domains = <&rpmpd QCM2290_VDDCX>;
1822 1668
1823 memory-region = <&pil 1669 memory-region = <&pil_modem_mem>;
1824 1670
1825 qcom,smem-states = <& 1671 qcom,smem-states = <&modem_smp2p_out 0>;
1826 qcom,smem-state-names 1672 qcom,smem-state-names = "stop";
1827 1673
1828 status = "disabled"; 1674 status = "disabled";
1829 1675
1830 glink-edge { 1676 glink-edge {
1831 interrupts = 1677 interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>;
1832 label = "mpss 1678 label = "mpss";
1833 qcom,remote-p 1679 qcom,remote-pid = <1>;
1834 mboxes = <&ap 1680 mboxes = <&apcs_glb 12>;
1835 }; 1681 };
1836 }; 1682 };
1837 1683
1838 remoteproc_adsp: remoteproc@a 1684 remoteproc_adsp: remoteproc@ab00000 {
1839 compatible = "qcom,qc 1685 compatible = "qcom,qcm2290-adsp-pas", "qcom,sm6115-adsp-pas";
1840 reg = <0x0 0x0ab00000 1686 reg = <0x0 0x0ab00000 0x0 0x100>;
1841 1687
1842 interrupts-extended = 1688 interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_EDGE_RISING>,
1843 1689 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1844 1690 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1845 1691 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1846 1692 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1847 interrupt-names = "wd 1693 interrupt-names = "wdog",
1848 "fa 1694 "fatal",
1849 "re 1695 "ready",
1850 "ha 1696 "handover",
1851 "st 1697 "stop-ack";
1852 1698
1853 clocks = <&rpmcc RPM_ 1699 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
1854 clock-names = "xo"; 1700 clock-names = "xo";
1855 1701
1856 power-domains = <&rpm 1702 power-domains = <&rpmpd QCM2290_VDD_LPI_CX>,
1857 <&rpm 1703 <&rpmpd QCM2290_VDD_LPI_MX>;
1858 1704
1859 memory-region = <&pil 1705 memory-region = <&pil_adsp_mem>;
1860 1706
1861 qcom,smem-states = <& 1707 qcom,smem-states = <&adsp_smp2p_out 0>;
1862 qcom,smem-state-names 1708 qcom,smem-state-names = "stop";
1863 1709
1864 status = "disabled"; 1710 status = "disabled";
1865 1711
1866 glink-edge { 1712 glink-edge {
1867 interrupts = 1713 interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>;
1868 label = "lpas 1714 label = "lpass";
1869 qcom,remote-p 1715 qcom,remote-pid = <2>;
1870 mboxes = <&ap 1716 mboxes = <&apcs_glb 8>;
1871 }; 1717 };
1872 }; 1718 };
1873 1719
1874 apps_smmu: iommu@c600000 { 1720 apps_smmu: iommu@c600000 {
1875 compatible = "qcom,qc 1721 compatible = "qcom,qcm2290-smmu-500", "qcom,smmu-500", "arm,mmu-500";
1876 reg = <0x0 0x0c600000 1722 reg = <0x0 0x0c600000 0x0 0x80000>;
1877 #iommu-cells = <2>; 1723 #iommu-cells = <2>;
1878 #global-interrupts = 1724 #global-interrupts = <1>;
1879 1725
1880 interrupts = <GIC_SPI 1726 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
1881 <GIC_SPI 1727 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
1882 <GIC_SPI 1728 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1883 <GIC_SPI 1729 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
1884 <GIC_SPI 1730 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
1885 <GIC_SPI 1731 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
1886 <GIC_SPI 1732 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
1887 <GIC_SPI 1733 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
1888 <GIC_SPI 1734 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
1889 <GIC_SPI 1735 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
1890 <GIC_SPI 1736 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
1891 <GIC_SPI 1737 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
1892 <GIC_SPI 1738 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
1893 <GIC_SPI 1739 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
1894 <GIC_SPI 1740 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1895 <GIC_SPI 1741 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1896 <GIC_SPI 1742 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1897 <GIC_SPI 1743 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1898 <GIC_SPI 1744 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1899 <GIC_SPI 1745 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
1900 <GIC_SPI 1746 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1901 <GIC_SPI 1747 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
1902 <GIC_SPI 1748 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1903 <GIC_SPI 1749 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1904 <GIC_SPI 1750 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
1905 <GIC_SPI 1751 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
1906 <GIC_SPI 1752 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
1907 <GIC_SPI 1753 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
1908 <GIC_SPI 1754 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
1909 <GIC_SPI 1755 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
1910 <GIC_SPI 1756 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1911 <GIC_SPI 1757 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1912 <GIC_SPI 1758 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1913 <GIC_SPI 1759 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1914 <GIC_SPI 1760 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1915 <GIC_SPI 1761 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1916 <GIC_SPI 1762 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
1917 <GIC_SPI 1763 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1918 <GIC_SPI 1764 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1919 <GIC_SPI 1765 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1920 <GIC_SPI 1766 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
1921 <GIC_SPI 1767 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
1922 <GIC_SPI 1768 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
1923 <GIC_SPI 1769 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
1924 <GIC_SPI 1770 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
1925 <GIC_SPI 1771 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
1926 <GIC_SPI 1772 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
1927 <GIC_SPI 1773 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
1928 <GIC_SPI 1774 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
1929 <GIC_SPI 1775 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1930 <GIC_SPI 1776 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
1931 <GIC_SPI 1777 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
1932 <GIC_SPI 1778 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
1933 <GIC_SPI 1779 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
1934 <GIC_SPI 1780 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
1935 <GIC_SPI 1781 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
1936 <GIC_SPI 1782 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
1937 <GIC_SPI 1783 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
1938 <GIC_SPI 1784 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
1939 <GIC_SPI 1785 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1940 <GIC_SPI 1786 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1941 <GIC_SPI 1787 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
1942 <GIC_SPI 1788 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
1943 <GIC_SPI 1789 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
1944 <GIC_SPI 1790 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
1945 }; 1791 };
1946 1792
1947 wifi: wifi@c800000 { 1793 wifi: wifi@c800000 {
1948 compatible = "qcom,wc 1794 compatible = "qcom,wcn3990-wifi";
1949 reg = <0x0 0x0c800000 1795 reg = <0x0 0x0c800000 0x0 0x800000>;
1950 reg-names = "membase" 1796 reg-names = "membase";
1951 memory-region = <&wla 1797 memory-region = <&wlan_msa_mem>;
1952 interrupts = <GIC_SPI 1798 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
1953 <GIC_SPI 1799 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
1954 <GIC_SPI 1800 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
1955 <GIC_SPI 1801 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
1956 <GIC_SPI 1802 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
1957 <GIC_SPI 1803 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>,
1958 <GIC_SPI 1804 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
1959 <GIC_SPI 1805 <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,
1960 <GIC_SPI 1806 <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
1961 <GIC_SPI 1807 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
1962 <GIC_SPI 1808 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
1963 <GIC_SPI 1809 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
1964 iommus = <&apps_smmu 1810 iommus = <&apps_smmu 0x1a0 0x1>;
1965 qcom,msa-fixed-perm; 1811 qcom,msa-fixed-perm;
1966 status = "disabled"; 1812 status = "disabled";
1967 }; 1813 };
1968 1814
1969 watchdog@f017000 { 1815 watchdog@f017000 {
1970 compatible = "qcom,ap 1816 compatible = "qcom,apss-wdt-qcm2290", "qcom,kpss-wdt";
1971 reg = <0x0 0x0f017000 1817 reg = <0x0 0x0f017000 0x0 0x1000>;
1972 interrupts = <GIC_SPI 1818 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>,
1973 <GIC_SPI 1819 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1974 clocks = <&sleep_clk> 1820 clocks = <&sleep_clk>;
1975 }; 1821 };
1976 1822
1977 apcs_glb: mailbox@f111000 { 1823 apcs_glb: mailbox@f111000 {
1978 compatible = "qcom,qc 1824 compatible = "qcom,qcm2290-apcs-hmss-global";
1979 reg = <0x0 0x0f111000 1825 reg = <0x0 0x0f111000 0x0 0x1000>;
1980 #mbox-cells = <1>; 1826 #mbox-cells = <1>;
1981 }; 1827 };
1982 1828
1983 timer@f120000 { 1829 timer@f120000 {
1984 compatible = "arm,arm 1830 compatible = "arm,armv7-timer-mem";
1985 reg = <0x0 0x0f120000 1831 reg = <0x0 0x0f120000 0x0 0x1000>;
1986 #address-cells = <1>; 1832 #address-cells = <1>;
1987 #size-cells = <1>; 1833 #size-cells = <1>;
1988 ranges = <0 0x0 0x0f1 1834 ranges = <0 0x0 0x0f121000 0x8000>;
1989 1835
1990 frame@0 { 1836 frame@0 {
1991 reg = <0x0 0x 1837 reg = <0x0 0x1000>,
1992 <0x1000 1838 <0x1000 0x1000>;
1993 interrupts = 1839 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
1994 1840 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1995 frame-number 1841 frame-number = <0>;
1996 }; 1842 };
1997 1843
1998 frame@2000 { 1844 frame@2000 {
1999 reg = <0x2000 1845 reg = <0x2000 0x1000>;
2000 interrupts = 1846 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
2001 frame-number 1847 frame-number = <1>;
2002 status = "dis 1848 status = "disabled";
2003 }; 1849 };
2004 1850
2005 frame@3000 { 1851 frame@3000 {
2006 reg = <0x3000 1852 reg = <0x3000 0x1000>;
2007 interrupts = 1853 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
2008 frame-number 1854 frame-number = <2>;
2009 status = "dis 1855 status = "disabled";
2010 }; 1856 };
2011 1857
2012 frame@4000 { 1858 frame@4000 {
2013 reg = <0x4000 1859 reg = <0x4000 0x1000>;
2014 interrupts = 1860 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
2015 frame-number 1861 frame-number = <3>;
2016 status = "dis 1862 status = "disabled";
2017 }; 1863 };
2018 1864
2019 frame@5000 { 1865 frame@5000 {
2020 reg = <0x5000 1866 reg = <0x5000 0x1000>;
2021 interrupts = 1867 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
2022 frame-number 1868 frame-number = <4>;
2023 status = "dis 1869 status = "disabled";
2024 }; 1870 };
2025 1871
2026 frame@6000 { 1872 frame@6000 {
2027 reg = <0x6000 1873 reg = <0x6000 0x1000>;
2028 interrupts = 1874 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
2029 frame-number 1875 frame-number = <5>;
2030 status = "dis 1876 status = "disabled";
2031 }; 1877 };
2032 1878
2033 frame@7000 { 1879 frame@7000 {
2034 reg = <0x7000 1880 reg = <0x7000 0x1000>;
2035 interrupts = 1881 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
2036 frame-number 1882 frame-number = <6>;
2037 status = "dis 1883 status = "disabled";
2038 }; 1884 };
2039 }; 1885 };
2040 1886
2041 intc: interrupt-controller@f2 1887 intc: interrupt-controller@f200000 {
2042 compatible = "arm,gic 1888 compatible = "arm,gic-v3";
2043 reg = <0x0 0x0f200000 1889 reg = <0x0 0x0f200000 0x0 0x10000>,
2044 <0x0 0x0f300000 1890 <0x0 0x0f300000 0x0 0x100000>;
2045 interrupts = <GIC_PPI 1891 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
2046 #interrupt-cells = <3 1892 #interrupt-cells = <3>;
2047 interrupt-controller; 1893 interrupt-controller;
2048 interrupt-parent = <& 1894 interrupt-parent = <&intc>;
2049 #redistributor-region 1895 #redistributor-regions = <1>;
2050 redistributor-stride 1896 redistributor-stride = <0x0 0x20000>;
2051 }; 1897 };
2052 1898
2053 cpufreq_hw: cpufreq@f521000 { 1899 cpufreq_hw: cpufreq@f521000 {
2054 compatible = "qcom,qc 1900 compatible = "qcom,qcm2290-cpufreq-hw", "qcom,cpufreq-hw";
2055 reg = <0x0 0x0f521000 1901 reg = <0x0 0x0f521000 0x0 0x1000>;
2056 reg-names = "freq-dom 1902 reg-names = "freq-domain0";
2057 interrupts-extended = 1903 interrupts-extended = <&lmh_cluster 0>;
2058 interrupt-names = "dc 1904 interrupt-names = "dcvsh-irq-0";
2059 clocks = <&rpmcc RPM_ 1905 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>;
2060 clock-names = "xo", " 1906 clock-names = "xo", "alternate";
2061 1907
2062 #freq-domain-cells = 1908 #freq-domain-cells = <1>;
2063 #clock-cells = <1>; 1909 #clock-cells = <1>;
2064 }; 1910 };
2065 1911
2066 lmh_cluster: lmh@f550800 { 1912 lmh_cluster: lmh@f550800 {
2067 compatible = "qcom,qc 1913 compatible = "qcom,qcm2290-lmh", "qcom,sm8150-lmh";
2068 reg = <0x0 0x0f550800 1914 reg = <0x0 0x0f550800 0x0 0x400>;
2069 interrupts = <GIC_SPI 1915 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
2070 cpus = <&CPU0>; 1916 cpus = <&CPU0>;
2071 qcom,lmh-temp-arm-mil 1917 qcom,lmh-temp-arm-millicelsius = <65000>;
2072 qcom,lmh-temp-low-mil 1918 qcom,lmh-temp-low-millicelsius = <94500>;
2073 qcom,lmh-temp-high-mi 1919 qcom,lmh-temp-high-millicelsius = <95000>;
2074 interrupt-controller; 1920 interrupt-controller;
2075 #interrupt-cells = <1 1921 #interrupt-cells = <1>;
2076 }; 1922 };
2077 }; 1923 };
2078 1924
2079 thermal-zones { 1925 thermal-zones {
2080 mapss-thermal { 1926 mapss-thermal {
>> 1927 polling-delay-passive = <0>;
>> 1928 polling-delay = <0>;
>> 1929
2081 thermal-sensors = <&t 1930 thermal-sensors = <&tsens0 0>;
2082 1931
2083 trips { 1932 trips {
2084 mapss_alert0: 1933 mapss_alert0: trip-point0 {
2085 tempe 1934 temperature = <90000>;
2086 hyste 1935 hysteresis = <2000>;
2087 type 1936 type = "passive";
2088 }; 1937 };
2089 1938
2090 mapss_alert1: 1939 mapss_alert1: trip-point1 {
2091 tempe 1940 temperature = <95000>;
2092 hyste 1941 hysteresis = <2000>;
2093 type 1942 type = "passive";
2094 }; 1943 };
2095 1944
2096 mapss_crit: m 1945 mapss_crit: mapss-crit {
2097 tempe 1946 temperature = <110000>;
2098 hyste 1947 hysteresis = <1000>;
2099 type 1948 type = "critical";
2100 }; 1949 };
2101 }; 1950 };
2102 }; 1951 };
2103 1952
2104 video-thermal { 1953 video-thermal {
>> 1954 polling-delay-passive = <0>;
>> 1955 polling-delay = <0>;
>> 1956
2105 thermal-sensors = <&t 1957 thermal-sensors = <&tsens0 1>;
2106 1958
2107 trips { 1959 trips {
2108 video_alert0: 1960 video_alert0: trip-point0 {
2109 tempe 1961 temperature = <90000>;
2110 hyste 1962 hysteresis = <2000>;
2111 type 1963 type = "passive";
2112 }; 1964 };
2113 1965
2114 video_alert1: 1966 video_alert1: trip-point1 {
2115 tempe 1967 temperature = <95000>;
2116 hyste 1968 hysteresis = <2000>;
2117 type 1969 type = "passive";
2118 }; 1970 };
2119 1971
2120 video_crit: v 1972 video_crit: video-crit {
2121 tempe 1973 temperature = <110000>;
2122 hyste 1974 hysteresis = <1000>;
2123 type 1975 type = "critical";
2124 }; 1976 };
2125 }; 1977 };
2126 }; 1978 };
2127 1979
2128 wlan-thermal { 1980 wlan-thermal {
>> 1981 polling-delay-passive = <0>;
>> 1982 polling-delay = <0>;
>> 1983
2129 thermal-sensors = <&t 1984 thermal-sensors = <&tsens0 2>;
2130 1985
2131 trips { 1986 trips {
2132 wlan_alert0: 1987 wlan_alert0: trip-point0 {
2133 tempe 1988 temperature = <90000>;
2134 hyste 1989 hysteresis = <2000>;
2135 type 1990 type = "passive";
2136 }; 1991 };
2137 1992
2138 wlan_alert1: 1993 wlan_alert1: trip-point1 {
2139 tempe 1994 temperature = <95000>;
2140 hyste 1995 hysteresis = <2000>;
2141 type 1996 type = "passive";
2142 }; 1997 };
2143 1998
2144 wlan_crit: wl 1999 wlan_crit: wlan-crit {
2145 tempe 2000 temperature = <110000>;
2146 hyste 2001 hysteresis = <1000>;
2147 type 2002 type = "critical";
2148 }; 2003 };
2149 }; 2004 };
2150 }; 2005 };
2151 2006
2152 cpuss0-thermal { 2007 cpuss0-thermal {
>> 2008 polling-delay-passive = <0>;
>> 2009 polling-delay = <0>;
>> 2010
2153 thermal-sensors = <&t 2011 thermal-sensors = <&tsens0 3>;
2154 2012
2155 trips { 2013 trips {
2156 cpuss0_alert0 2014 cpuss0_alert0: trip-point0 {
2157 tempe 2015 temperature = <90000>;
2158 hyste 2016 hysteresis = <2000>;
2159 type 2017 type = "passive";
2160 }; 2018 };
2161 2019
2162 cpuss0_alert1 2020 cpuss0_alert1: trip-point1 {
2163 tempe 2021 temperature = <95000>;
2164 hyste 2022 hysteresis = <2000>;
2165 type 2023 type = "passive";
2166 }; 2024 };
2167 2025
2168 cpuss0_crit: 2026 cpuss0_crit: cpuss0-crit {
2169 tempe 2027 temperature = <110000>;
2170 hyste 2028 hysteresis = <1000>;
2171 type 2029 type = "critical";
2172 }; 2030 };
2173 }; 2031 };
2174 }; 2032 };
2175 2033
2176 cpuss1-thermal { 2034 cpuss1-thermal {
>> 2035 polling-delay-passive = <0>;
>> 2036 polling-delay = <0>;
>> 2037
2177 thermal-sensors = <&t 2038 thermal-sensors = <&tsens0 4>;
2178 2039
2179 trips { 2040 trips {
2180 cpuss1_alert0 2041 cpuss1_alert0: trip-point0 {
2181 tempe 2042 temperature = <90000>;
2182 hyste 2043 hysteresis = <2000>;
2183 type 2044 type = "passive";
2184 }; 2045 };
2185 2046
2186 cpuss1_alert1 2047 cpuss1_alert1: trip-point1 {
2187 tempe 2048 temperature = <95000>;
2188 hyste 2049 hysteresis = <2000>;
2189 type 2050 type = "passive";
2190 }; 2051 };
2191 2052
2192 cpuss1_crit: 2053 cpuss1_crit: cpuss1-crit {
2193 tempe 2054 temperature = <110000>;
2194 hyste 2055 hysteresis = <1000>;
2195 type 2056 type = "critical";
2196 }; 2057 };
2197 }; 2058 };
2198 }; 2059 };
2199 2060
2200 mdm0-thermal { 2061 mdm0-thermal {
>> 2062 polling-delay-passive = <0>;
>> 2063 polling-delay = <0>;
>> 2064
2201 thermal-sensors = <&t 2065 thermal-sensors = <&tsens0 5>;
2202 2066
2203 trips { 2067 trips {
2204 mdm0_alert0: 2068 mdm0_alert0: trip-point0 {
2205 tempe 2069 temperature = <90000>;
2206 hyste 2070 hysteresis = <2000>;
2207 type 2071 type = "passive";
2208 }; 2072 };
2209 2073
2210 mdm0_alert1: 2074 mdm0_alert1: trip-point1 {
2211 tempe 2075 temperature = <95000>;
2212 hyste 2076 hysteresis = <2000>;
2213 type 2077 type = "passive";
2214 }; 2078 };
2215 2079
2216 mdm0_crit: md 2080 mdm0_crit: mdm0-crit {
2217 tempe 2081 temperature = <110000>;
2218 hyste 2082 hysteresis = <1000>;
2219 type 2083 type = "critical";
2220 }; 2084 };
2221 }; 2085 };
2222 }; 2086 };
2223 2087
2224 mdm1-thermal { 2088 mdm1-thermal {
>> 2089 polling-delay-passive = <0>;
>> 2090 polling-delay = <0>;
>> 2091
2225 thermal-sensors = <&t 2092 thermal-sensors = <&tsens0 6>;
2226 2093
2227 trips { 2094 trips {
2228 mdm1_alert0: 2095 mdm1_alert0: trip-point0 {
2229 tempe 2096 temperature = <90000>;
2230 hyste 2097 hysteresis = <2000>;
2231 type 2098 type = "passive";
2232 }; 2099 };
2233 2100
2234 mdm1_alert1: 2101 mdm1_alert1: trip-point1 {
2235 tempe 2102 temperature = <95000>;
2236 hyste 2103 hysteresis = <2000>;
2237 type 2104 type = "passive";
2238 }; 2105 };
2239 2106
2240 mdm1_crit: md 2107 mdm1_crit: mdm1-crit {
2241 tempe 2108 temperature = <110000>;
2242 hyste 2109 hysteresis = <1000>;
2243 type 2110 type = "critical";
2244 }; 2111 };
2245 }; 2112 };
2246 }; 2113 };
2247 2114
2248 gpu-thermal { 2115 gpu-thermal {
>> 2116 polling-delay-passive = <0>;
>> 2117 polling-delay = <0>;
>> 2118
2249 thermal-sensors = <&t 2119 thermal-sensors = <&tsens0 7>;
2250 2120
2251 trips { 2121 trips {
2252 gpu_alert0: t 2122 gpu_alert0: trip-point0 {
2253 tempe 2123 temperature = <90000>;
2254 hyste 2124 hysteresis = <2000>;
2255 type 2125 type = "passive";
2256 }; 2126 };
2257 2127
2258 gpu_alert1: t 2128 gpu_alert1: trip-point1 {
2259 tempe 2129 temperature = <95000>;
2260 hyste 2130 hysteresis = <2000>;
2261 type 2131 type = "passive";
2262 }; 2132 };
2263 2133
2264 gpu_crit: gpu 2134 gpu_crit: gpu-crit {
2265 tempe 2135 temperature = <110000>;
2266 hyste 2136 hysteresis = <1000>;
2267 type 2137 type = "critical";
2268 }; 2138 };
2269 }; 2139 };
2270 }; 2140 };
2271 2141
2272 hm-center-thermal { 2142 hm-center-thermal {
>> 2143 polling-delay-passive = <0>;
>> 2144 polling-delay = <0>;
>> 2145
2273 thermal-sensors = <&t 2146 thermal-sensors = <&tsens0 8>;
2274 2147
2275 trips { 2148 trips {
2276 hm_center_ale 2149 hm_center_alert0: trip-point0 {
2277 tempe 2150 temperature = <90000>;
2278 hyste 2151 hysteresis = <2000>;
2279 type 2152 type = "passive";
2280 }; 2153 };
2281 2154
2282 hm_center_ale 2155 hm_center_alert1: trip-point1 {
2283 tempe 2156 temperature = <95000>;
2284 hyste 2157 hysteresis = <2000>;
2285 type 2158 type = "passive";
2286 }; 2159 };
2287 2160
2288 hm_center_cri 2161 hm_center_crit: hm-center-crit {
2289 tempe 2162 temperature = <110000>;
2290 hyste 2163 hysteresis = <1000>;
2291 type 2164 type = "critical";
2292 }; 2165 };
2293 }; 2166 };
2294 }; 2167 };
2295 2168
2296 camera-thermal { 2169 camera-thermal {
>> 2170 polling-delay-passive = <0>;
>> 2171 polling-delay = <0>;
>> 2172
2297 thermal-sensors = <&t 2173 thermal-sensors = <&tsens0 9>;
2298 2174
2299 trips { 2175 trips {
2300 camera_alert0 2176 camera_alert0: trip-point0 {
2301 tempe 2177 temperature = <90000>;
2302 hyste 2178 hysteresis = <2000>;
2303 type 2179 type = "passive";
2304 }; 2180 };
2305 2181
2306 camera_alert1 2182 camera_alert1: trip-point1 {
2307 tempe 2183 temperature = <95000>;
2308 hyste 2184 hysteresis = <2000>;
2309 type 2185 type = "passive";
2310 }; 2186 };
2311 2187
2312 camera_crit: 2188 camera_crit: camera-crit {
2313 tempe 2189 temperature = <110000>;
2314 hyste 2190 hysteresis = <1000>;
2315 type 2191 type = "critical";
2316 }; 2192 };
2317 }; 2193 };
2318 }; 2194 };
2319 }; 2195 };
2320 2196
2321 timer { 2197 timer {
2322 compatible = "arm,armv8-timer 2198 compatible = "arm,armv8-timer";
2323 interrupts = <GIC_PPI 1 (GIC_ 2199 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2324 <GIC_PPI 2 (GIC_ 2200 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2325 <GIC_PPI 3 (GIC_ 2201 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2326 <GIC_PPI 0 (GIC_ 2202 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
2327 }; 2203 };
2328 }; 2204 };
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