1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3 1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2 /* 2 /*
3 * Copyright (c) 2023, Linaro Ltd 3 * Copyright (c) 2023, Linaro Ltd
4 * 4 *
5 * Based on sm6115.dtsi and previous efforts b 5 * Based on sm6115.dtsi and previous efforts by Shawn Guo & Loic Poulain.
6 */ 6 */
7 7
8 #include <dt-bindings/clock/qcom,dispcc-qcm229 <<
9 #include <dt-bindings/clock/qcom,gcc-qcm2290.h 8 #include <dt-bindings/clock/qcom,gcc-qcm2290.h>
10 #include <dt-bindings/clock/qcom,qcm2290-gpucc <<
11 #include <dt-bindings/clock/qcom,rpmcc.h> 9 #include <dt-bindings/clock/qcom,rpmcc.h>
12 #include <dt-bindings/dma/qcom-gpi.h> 10 #include <dt-bindings/dma/qcom-gpi.h>
13 #include <dt-bindings/firmware/qcom,scm.h> 11 #include <dt-bindings/firmware/qcom,scm.h>
14 #include <dt-bindings/gpio/gpio.h> 12 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/interrupt-controller/arm 13 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/interconnect/qcom,qcm229 <<
17 #include <dt-bindings/interconnect/qcom,rpm-ic <<
18 #include <dt-bindings/power/qcom-rpmpd.h> 14 #include <dt-bindings/power/qcom-rpmpd.h>
19 15
20 / { 16 / {
21 interrupt-parent = <&intc>; 17 interrupt-parent = <&intc>;
22 18
23 #address-cells = <2>; 19 #address-cells = <2>;
24 #size-cells = <2>; 20 #size-cells = <2>;
25 21
26 chosen { }; 22 chosen { };
27 23
28 clocks { 24 clocks {
29 xo_board: xo-board { 25 xo_board: xo-board {
30 compatible = "fixed-cl 26 compatible = "fixed-clock";
31 #clock-cells = <0>; 27 #clock-cells = <0>;
32 }; 28 };
33 29
34 sleep_clk: sleep-clk { 30 sleep_clk: sleep-clk {
35 compatible = "fixed-cl 31 compatible = "fixed-clock";
36 clock-frequency = <327 32 clock-frequency = <32764>;
37 #clock-cells = <0>; 33 #clock-cells = <0>;
38 }; 34 };
39 }; 35 };
40 36
41 cpus { 37 cpus {
42 #address-cells = <2>; 38 #address-cells = <2>;
43 #size-cells = <0>; 39 #size-cells = <0>;
44 40
45 CPU0: cpu@0 { 41 CPU0: cpu@0 {
46 device_type = "cpu"; 42 device_type = "cpu";
47 compatible = "arm,cort 43 compatible = "arm,cortex-a53";
48 reg = <0x0 0x0>; 44 reg = <0x0 0x0>;
49 clocks = <&cpufreq_hw 45 clocks = <&cpufreq_hw 0>;
50 capacity-dmips-mhz = < 46 capacity-dmips-mhz = <1024>;
51 dynamic-power-coeffici 47 dynamic-power-coefficient = <100>;
52 enable-method = "psci" 48 enable-method = "psci";
53 next-level-cache = <&L 49 next-level-cache = <&L2_0>;
54 qcom,freq-domain = <&c 50 qcom,freq-domain = <&cpufreq_hw 0>;
55 power-domains = <&CPU_ <<
56 power-domain-names = " <<
57 L2_0: l2-cache { 51 L2_0: l2-cache {
58 compatible = " 52 compatible = "cache";
59 cache-level = 53 cache-level = <2>;
60 cache-unified; 54 cache-unified;
61 }; 55 };
62 }; 56 };
63 57
64 CPU1: cpu@1 { 58 CPU1: cpu@1 {
65 device_type = "cpu"; 59 device_type = "cpu";
66 compatible = "arm,cort 60 compatible = "arm,cortex-a53";
67 reg = <0x0 0x1>; 61 reg = <0x0 0x1>;
68 clocks = <&cpufreq_hw 62 clocks = <&cpufreq_hw 0>;
69 capacity-dmips-mhz = < 63 capacity-dmips-mhz = <1024>;
70 dynamic-power-coeffici 64 dynamic-power-coefficient = <100>;
71 enable-method = "psci" 65 enable-method = "psci";
72 next-level-cache = <&L 66 next-level-cache = <&L2_0>;
73 qcom,freq-domain = <&c 67 qcom,freq-domain = <&cpufreq_hw 0>;
74 power-domains = <&CPU_ <<
75 power-domain-names = " <<
76 }; 68 };
77 69
78 CPU2: cpu@2 { 70 CPU2: cpu@2 {
79 device_type = "cpu"; 71 device_type = "cpu";
80 compatible = "arm,cort 72 compatible = "arm,cortex-a53";
81 reg = <0x0 0x2>; 73 reg = <0x0 0x2>;
82 clocks = <&cpufreq_hw 74 clocks = <&cpufreq_hw 0>;
83 capacity-dmips-mhz = < 75 capacity-dmips-mhz = <1024>;
84 dynamic-power-coeffici 76 dynamic-power-coefficient = <100>;
85 enable-method = "psci" 77 enable-method = "psci";
86 next-level-cache = <&L 78 next-level-cache = <&L2_0>;
87 qcom,freq-domain = <&c 79 qcom,freq-domain = <&cpufreq_hw 0>;
88 power-domains = <&CPU_ <<
89 power-domain-names = " <<
90 }; 80 };
91 81
92 CPU3: cpu@3 { 82 CPU3: cpu@3 {
93 device_type = "cpu"; 83 device_type = "cpu";
94 compatible = "arm,cort 84 compatible = "arm,cortex-a53";
95 reg = <0x0 0x3>; 85 reg = <0x0 0x3>;
96 clocks = <&cpufreq_hw 86 clocks = <&cpufreq_hw 0>;
97 capacity-dmips-mhz = < 87 capacity-dmips-mhz = <1024>;
98 dynamic-power-coeffici 88 dynamic-power-coefficient = <100>;
99 enable-method = "psci" 89 enable-method = "psci";
100 next-level-cache = <&L 90 next-level-cache = <&L2_0>;
101 qcom,freq-domain = <&c 91 qcom,freq-domain = <&cpufreq_hw 0>;
102 power-domains = <&CPU_ <<
103 power-domain-names = " <<
104 }; 92 };
105 93
106 cpu-map { 94 cpu-map {
107 cluster0 { 95 cluster0 {
108 core0 { 96 core0 {
109 cpu = 97 cpu = <&CPU0>;
110 }; 98 };
111 99
112 core1 { 100 core1 {
113 cpu = 101 cpu = <&CPU1>;
114 }; 102 };
115 103
116 core2 { 104 core2 {
117 cpu = 105 cpu = <&CPU2>;
118 }; 106 };
119 107
120 core3 { 108 core3 {
121 cpu = 109 cpu = <&CPU3>;
122 }; 110 };
123 }; 111 };
124 }; 112 };
125 <<
126 domain-idle-states { <<
127 CLUSTER_SLEEP: cluster <<
128 compatible = " <<
129 arm,psci-suspe <<
130 entry-latency- <<
131 exit-latency-u <<
132 min-residency- <<
133 }; <<
134 }; <<
135 <<
136 idle-states { <<
137 entry-method = "psci"; <<
138 <<
139 CPU_SLEEP: cpu-sleep-0 <<
140 compatible = " <<
141 idle-state-nam <<
142 arm,psci-suspe <<
143 entry-latency- <<
144 exit-latency-u <<
145 min-residency- <<
146 local-timer-st <<
147 }; <<
148 }; <<
149 }; 113 };
150 114
151 firmware { 115 firmware {
152 scm: scm { 116 scm: scm {
153 compatible = "qcom,scm 117 compatible = "qcom,scm-qcm2290", "qcom,scm";
154 clocks = <&rpmcc RPM_S 118 clocks = <&rpmcc RPM_SMD_CE1_CLK>;
155 clock-names = "core"; 119 clock-names = "core";
156 #reset-cells = <1>; 120 #reset-cells = <1>;
157 interconnects = <&syst <<
158 &bimc <<
159 }; 121 };
160 }; 122 };
161 123
162 memory@40000000 { 124 memory@40000000 {
163 device_type = "memory"; 125 device_type = "memory";
164 /* We expect the bootloader to 126 /* We expect the bootloader to fill in the size */
165 reg = <0 0x40000000 0 0>; 127 reg = <0 0x40000000 0 0>;
166 }; 128 };
167 129
168 pmu { 130 pmu {
169 compatible = "arm,cortex-a53-p !! 131 compatible = "arm,armv8-pmuv3";
170 interrupts = <GIC_PPI 6 IRQ_TY 132 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>;
171 }; 133 };
172 134
173 psci { 135 psci {
174 compatible = "arm,psci-1.0"; 136 compatible = "arm,psci-1.0";
175 method = "smc"; 137 method = "smc";
176 <<
177 CPU_PD0: power-domain-cpu0 { <<
178 #power-domain-cells = <<
179 power-domains = <&CLUS <<
180 domain-idle-states = < <<
181 }; <<
182 <<
183 CPU_PD1: power-domain-cpu1 { <<
184 #power-domain-cells = <<
185 power-domains = <&CLUS <<
186 domain-idle-states = < <<
187 }; <<
188 <<
189 CPU_PD2: power-domain-cpu2 { <<
190 #power-domain-cells = <<
191 power-domains = <&CLUS <<
192 domain-idle-states = < <<
193 }; <<
194 <<
195 CPU_PD3: power-domain-cpu3 { <<
196 #power-domain-cells = <<
197 power-domains = <&CLUS <<
198 domain-idle-states = < <<
199 }; <<
200 <<
201 CLUSTER_PD: power-domain-cpu-c <<
202 #power-domain-cells = <<
203 power-domains = <&mpm> <<
204 domain-idle-states = < <<
205 }; <<
206 }; <<
207 <<
208 rpm: remoteproc { <<
209 compatible = "qcom,qcm2290-rpm <<
210 <<
211 glink-edge { <<
212 compatible = "qcom,gli <<
213 interrupts = <GIC_SPI <<
214 qcom,rpm-msg-ram = <&r <<
215 mboxes = <&apcs_glb 0> <<
216 <<
217 rpm_requests: rpm-requ <<
218 compatible = " <<
219 qcom,glink-cha <<
220 <<
221 rpmcc: clock-c <<
222 compat <<
223 clocks <<
224 clock- <<
225 #clock <<
226 }; <<
227 <<
228 rpmpd: power-c <<
229 compat <<
230 #power <<
231 operat <<
232 <<
233 rpmpd_ <<
234 <<
235 <<
236 <<
237 <<
238 <<
239 <<
240 <<
241 <<
242 <<
243 <<
244 <<
245 <<
246 <<
247 <<
248 <<
249 <<
250 <<
251 <<
252 <<
253 <<
254 <<
255 <<
256 <<
257 <<
258 <<
259 <<
260 <<
261 <<
262 <<
263 <<
264 <<
265 <<
266 <<
267 }; <<
268 }; <<
269 }; <<
270 }; <<
271 <<
272 mpm: interrupt-controller { <<
273 compatible = "qcom,mpm <<
274 qcom,rpm-msg-ram = <&a <<
275 interrupts = <GIC_SPI <<
276 mboxes = <&apcs_glb 1> <<
277 interrupt-controller; <<
278 #interrupt-cells = <2> <<
279 #power-domain-cells = <<
280 interrupt-parent = <&i <<
281 qcom,mpm-pin-count = < <<
282 qcom,mpm-pin-map = <2 <<
283 <5 <<
284 <12 <<
285 <24 <<
286 <86 <<
287 <90 <<
288 }; <<
289 }; 138 };
290 139
291 reserved_memory: reserved-memory { 140 reserved_memory: reserved-memory {
292 #address-cells = <2>; 141 #address-cells = <2>;
293 #size-cells = <2>; 142 #size-cells = <2>;
294 ranges; 143 ranges;
295 144
296 hyp_mem: hyp@45700000 { 145 hyp_mem: hyp@45700000 {
297 reg = <0x0 0x45700000 146 reg = <0x0 0x45700000 0x0 0x600000>;
298 no-map; 147 no-map;
299 }; 148 };
300 149
301 xbl_aop_mem: xbl-aop@45e00000 150 xbl_aop_mem: xbl-aop@45e00000 {
302 reg = <0x0 0x45e00000 151 reg = <0x0 0x45e00000 0x0 0x140000>;
303 no-map; 152 no-map;
304 }; 153 };
305 154
306 sec_apps_mem: sec-apps@45fff00 155 sec_apps_mem: sec-apps@45fff000 {
307 reg = <0x0 0x45fff000 156 reg = <0x0 0x45fff000 0x0 0x1000>;
308 no-map; 157 no-map;
309 }; 158 };
310 159
311 smem_mem: smem@46000000 { 160 smem_mem: smem@46000000 {
312 compatible = "qcom,sme 161 compatible = "qcom,smem";
313 reg = <0x0 0x46000000 162 reg = <0x0 0x46000000 0x0 0x200000>;
314 no-map; 163 no-map;
315 164
316 hwlocks = <&tcsr_mutex 165 hwlocks = <&tcsr_mutex 3>;
317 qcom,rpm-msg-ram = <&r 166 qcom,rpm-msg-ram = <&rpm_msg_ram>;
318 }; 167 };
319 168
320 pil_modem_mem: modem@4ab00000 169 pil_modem_mem: modem@4ab00000 {
321 reg = <0x0 0x4ab00000 170 reg = <0x0 0x4ab00000 0x0 0x6900000>;
322 no-map; 171 no-map;
323 }; 172 };
324 173
325 pil_video_mem: video@51400000 174 pil_video_mem: video@51400000 {
326 reg = <0x0 0x51400000 175 reg = <0x0 0x51400000 0x0 0x500000>;
327 no-map; 176 no-map;
328 }; 177 };
329 178
330 wlan_msa_mem: wlan-msa@5190000 179 wlan_msa_mem: wlan-msa@51900000 {
331 reg = <0x0 0x51900000 180 reg = <0x0 0x51900000 0x0 0x100000>;
332 no-map; 181 no-map;
333 }; 182 };
334 183
335 pil_adsp_mem: adsp@51a00000 { 184 pil_adsp_mem: adsp@51a00000 {
336 reg = <0x0 0x51a00000 185 reg = <0x0 0x51a00000 0x0 0x1c00000>;
337 no-map; 186 no-map;
338 }; 187 };
339 188
340 pil_ipa_fw_mem: ipa-fw@5360000 189 pil_ipa_fw_mem: ipa-fw@53600000 {
341 reg = <0x0 0x53600000 190 reg = <0x0 0x53600000 0x0 0x10000>;
342 no-map; 191 no-map;
343 }; 192 };
344 193
345 pil_ipa_gsi_mem: ipa-gsi@53610 194 pil_ipa_gsi_mem: ipa-gsi@53610000 {
346 reg = <0x0 0x53610000 195 reg = <0x0 0x53610000 0x0 0x5000>;
347 no-map; 196 no-map;
348 }; 197 };
349 198
350 pil_gpu_mem: zap@53615000 { 199 pil_gpu_mem: zap@53615000 {
351 compatible = "shared-d 200 compatible = "shared-dma-pool";
352 reg = <0x0 0x53615000 201 reg = <0x0 0x53615000 0x0 0x2000>;
353 no-map; 202 no-map;
354 }; 203 };
355 204
356 cont_splash_memory: framebuffe 205 cont_splash_memory: framebuffer@5c000000 {
357 reg = <0x0 0x5c000000 206 reg = <0x0 0x5c000000 0x0 0x00f00000>;
358 no-map; 207 no-map;
359 }; 208 };
360 209
361 dfps_data_memory: dpfs-data@5c 210 dfps_data_memory: dpfs-data@5cf00000 {
362 reg = <0x0 0x5cf00000 211 reg = <0x0 0x5cf00000 0x0 0x0100000>;
363 no-map; 212 no-map;
364 }; 213 };
365 214
366 removed_mem: reserved@60000000 215 removed_mem: reserved@60000000 {
367 reg = <0x0 0x60000000 216 reg = <0x0 0x60000000 0x0 0x3900000>;
368 no-map; 217 no-map;
369 }; 218 };
370 219
371 rmtfs_mem: memory@89b01000 { 220 rmtfs_mem: memory@89b01000 {
372 compatible = "qcom,rmt 221 compatible = "qcom,rmtfs-mem";
373 reg = <0x0 0x89b01000 222 reg = <0x0 0x89b01000 0x0 0x200000>;
374 no-map; 223 no-map;
375 224
376 qcom,client-id = <1>; 225 qcom,client-id = <1>;
377 qcom,vmid = <QCOM_SCM_ 226 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA QCOM_SCM_VMID_NAV>;
378 }; 227 };
379 }; 228 };
380 229
>> 230 rpm-glink {
>> 231 compatible = "qcom,glink-rpm";
>> 232 interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>;
>> 233 qcom,rpm-msg-ram = <&rpm_msg_ram>;
>> 234 mboxes = <&apcs_glb 0>;
>> 235
>> 236 rpm_requests: rpm-requests {
>> 237 compatible = "qcom,rpm-qcm2290";
>> 238 qcom,glink-channels = "rpm_requests";
>> 239
>> 240 rpmcc: clock-controller {
>> 241 compatible = "qcom,rpmcc-qcm2290", "qcom,rpmcc";
>> 242 clocks = <&xo_board>;
>> 243 clock-names = "xo";
>> 244 #clock-cells = <1>;
>> 245 };
>> 246
>> 247 rpmpd: power-controller {
>> 248 compatible = "qcom,qcm2290-rpmpd";
>> 249 #power-domain-cells = <1>;
>> 250 operating-points-v2 = <&rpmpd_opp_table>;
>> 251
>> 252 rpmpd_opp_table: opp-table {
>> 253 compatible = "operating-points-v2";
>> 254
>> 255 rpmpd_opp_min_svs: opp1 {
>> 256 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
>> 257 };
>> 258
>> 259 rpmpd_opp_low_svs: opp2 {
>> 260 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
>> 261 };
>> 262
>> 263 rpmpd_opp_svs: opp3 {
>> 264 opp-level = <RPM_SMD_LEVEL_SVS>;
>> 265 };
>> 266
>> 267 rpmpd_opp_svs_plus: opp4 {
>> 268 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
>> 269 };
>> 270
>> 271 rpmpd_opp_nom: opp5 {
>> 272 opp-level = <RPM_SMD_LEVEL_NOM>;
>> 273 };
>> 274
>> 275 rpmpd_opp_nom_plus: opp6 {
>> 276 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
>> 277 };
>> 278
>> 279 rpmpd_opp_turbo: opp7 {
>> 280 opp-level = <RPM_SMD_LEVEL_TURBO>;
>> 281 };
>> 282
>> 283 rpmpd_opp_turbo_plus: opp8 {
>> 284 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>;
>> 285 };
>> 286 };
>> 287 };
>> 288 };
>> 289 };
>> 290
381 smp2p-adsp { 291 smp2p-adsp {
382 compatible = "qcom,smp2p"; 292 compatible = "qcom,smp2p";
383 qcom,smem = <443>, <429>; 293 qcom,smem = <443>, <429>;
384 294
385 interrupts = <GIC_SPI 279 IRQ_ 295 interrupts = <GIC_SPI 279 IRQ_TYPE_EDGE_RISING>;
386 296
387 mboxes = <&apcs_glb 10>; 297 mboxes = <&apcs_glb 10>;
388 298
389 qcom,local-pid = <0>; 299 qcom,local-pid = <0>;
390 qcom,remote-pid = <2>; 300 qcom,remote-pid = <2>;
391 301
392 adsp_smp2p_out: master-kernel 302 adsp_smp2p_out: master-kernel {
393 qcom,entry-name = "mas 303 qcom,entry-name = "master-kernel";
394 #qcom,smem-state-cells 304 #qcom,smem-state-cells = <1>;
395 }; 305 };
396 306
397 adsp_smp2p_in: slave-kernel { 307 adsp_smp2p_in: slave-kernel {
398 qcom,entry-name = "sla 308 qcom,entry-name = "slave-kernel";
399 interrupt-controller; 309 interrupt-controller;
400 #interrupt-cells = <2> 310 #interrupt-cells = <2>;
401 }; 311 };
402 }; 312 };
403 313
404 smp2p-mpss { 314 smp2p-mpss {
405 compatible = "qcom,smp2p"; 315 compatible = "qcom,smp2p";
406 qcom,smem = <435>, <428>; 316 qcom,smem = <435>, <428>;
407 317
408 interrupts = <GIC_SPI 70 IRQ_T 318 interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>;
409 319
410 mboxes = <&apcs_glb 14>; 320 mboxes = <&apcs_glb 14>;
411 321
412 qcom,local-pid = <0>; 322 qcom,local-pid = <0>;
413 qcom,remote-pid = <1>; 323 qcom,remote-pid = <1>;
414 324
415 modem_smp2p_out: master-kernel 325 modem_smp2p_out: master-kernel {
416 qcom,entry-name = "mas 326 qcom,entry-name = "master-kernel";
417 #qcom,smem-state-cells 327 #qcom,smem-state-cells = <1>;
418 }; 328 };
419 329
420 modem_smp2p_in: slave-kernel { 330 modem_smp2p_in: slave-kernel {
421 qcom,entry-name = "sla 331 qcom,entry-name = "slave-kernel";
422 interrupt-controller; 332 interrupt-controller;
423 #interrupt-cells = <2> 333 #interrupt-cells = <2>;
424 }; 334 };
425 335
426 wlan_smp2p_in: wlan-wpss-to-ap 336 wlan_smp2p_in: wlan-wpss-to-ap {
427 qcom,entry-name = "wla 337 qcom,entry-name = "wlan";
428 interrupt-controller; 338 interrupt-controller;
429 #interrupt-cells = <2> 339 #interrupt-cells = <2>;
430 }; 340 };
431 }; 341 };
432 342
433 soc: soc@0 { 343 soc: soc@0 {
434 compatible = "simple-bus"; 344 compatible = "simple-bus";
435 #address-cells = <2>; 345 #address-cells = <2>;
436 #size-cells = <2>; 346 #size-cells = <2>;
437 ranges = <0 0 0 0 0x10 0>; 347 ranges = <0 0 0 0 0x10 0>;
438 dma-ranges = <0 0 0 0 0x10 0>; 348 dma-ranges = <0 0 0 0 0x10 0>;
439 349
440 tcsr_mutex: hwlock@340000 { 350 tcsr_mutex: hwlock@340000 {
441 compatible = "qcom,tcs 351 compatible = "qcom,tcsr-mutex";
442 reg = <0x0 0x00340000 352 reg = <0x0 0x00340000 0x0 0x20000>;
443 #hwlock-cells = <1>; 353 #hwlock-cells = <1>;
444 }; 354 };
445 355
446 tcsr_regs: syscon@3c0000 { <<
447 compatible = "qcom,qcm <<
448 reg = <0x0 0x003c0000 <<
449 }; <<
450 <<
451 tlmm: pinctrl@500000 { 356 tlmm: pinctrl@500000 {
452 compatible = "qcom,qcm 357 compatible = "qcom,qcm2290-tlmm";
453 reg = <0x0 0x00500000 358 reg = <0x0 0x00500000 0x0 0x300000>;
454 interrupts = <GIC_SPI 359 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
455 gpio-controller; 360 gpio-controller;
456 gpio-ranges = <&tlmm 0 361 gpio-ranges = <&tlmm 0 0 127>;
457 wakeup-parent = <&mpm> <<
458 #gpio-cells = <2>; 362 #gpio-cells = <2>;
459 interrupt-controller; 363 interrupt-controller;
460 #interrupt-cells = <2> 364 #interrupt-cells = <2>;
461 365
462 qup_i2c0_default: qup- 366 qup_i2c0_default: qup-i2c0-default-state {
463 pins = "gpio0" 367 pins = "gpio0", "gpio1";
464 function = "qu 368 function = "qup0";
465 drive-strength 369 drive-strength = <2>;
466 bias-pull-up; 370 bias-pull-up;
467 }; 371 };
468 372
469 qup_i2c1_default: qup- 373 qup_i2c1_default: qup-i2c1-default-state {
470 pins = "gpio4" 374 pins = "gpio4", "gpio5";
471 function = "qu 375 function = "qup1";
472 drive-strength 376 drive-strength = <2>;
473 bias-pull-up; 377 bias-pull-up;
474 }; 378 };
475 379
476 qup_i2c2_default: qup- 380 qup_i2c2_default: qup-i2c2-default-state {
477 pins = "gpio6" 381 pins = "gpio6", "gpio7";
478 function = "qu 382 function = "qup2";
479 drive-strength 383 drive-strength = <2>;
480 bias-pull-up; 384 bias-pull-up;
481 }; 385 };
482 386
483 qup_i2c3_default: qup- 387 qup_i2c3_default: qup-i2c3-default-state {
484 pins = "gpio8" 388 pins = "gpio8", "gpio9";
485 function = "qu 389 function = "qup3";
486 drive-strength 390 drive-strength = <2>;
487 bias-pull-up; 391 bias-pull-up;
488 }; 392 };
489 393
490 qup_i2c4_default: qup- 394 qup_i2c4_default: qup-i2c4-default-state {
491 pins = "gpio12 395 pins = "gpio12", "gpio13";
492 function = "qu 396 function = "qup4";
493 drive-strength 397 drive-strength = <2>;
494 bias-pull-up; 398 bias-pull-up;
495 }; 399 };
496 400
497 qup_i2c5_default: qup- 401 qup_i2c5_default: qup-i2c5-default-state {
498 pins = "gpio14 402 pins = "gpio14", "gpio15";
499 function = "qu 403 function = "qup5";
500 drive-strength 404 drive-strength = <2>;
501 bias-pull-up; 405 bias-pull-up;
502 }; 406 };
503 407
504 qup_spi0_default: qup- 408 qup_spi0_default: qup-spi0-default-state {
505 pins = "gpio0" 409 pins = "gpio0", "gpio1","gpio2", "gpio3";
506 function = "qu 410 function = "qup0";
507 drive-strength 411 drive-strength = <2>;
508 bias-pull-up; 412 bias-pull-up;
509 }; 413 };
510 414
511 qup_spi1_default: qup- 415 qup_spi1_default: qup-spi1-default-state {
512 pins = "gpio4" 416 pins = "gpio4", "gpio5", "gpio69", "gpio70";
513 function = "qu 417 function = "qup1";
514 drive-strength 418 drive-strength = <2>;
515 bias-pull-up; 419 bias-pull-up;
516 }; 420 };
517 421
518 qup_spi2_default: qup- 422 qup_spi2_default: qup-spi2-default-state {
519 pins = "gpio6" 423 pins = "gpio6", "gpio7", "gpio71", "gpio80";
520 function = "qu 424 function = "qup2";
521 drive-strength 425 drive-strength = <2>;
522 bias-pull-up; 426 bias-pull-up;
523 }; 427 };
524 428
525 qup_spi3_default: qup- 429 qup_spi3_default: qup-spi3-default-state {
526 pins = "gpio8" 430 pins = "gpio8", "gpio9", "gpio10", "gpio11";
527 function = "qu 431 function = "qup3";
528 drive-strength 432 drive-strength = <2>;
529 bias-pull-up; 433 bias-pull-up;
530 }; 434 };
531 435
532 qup_spi4_default: qup- 436 qup_spi4_default: qup-spi4-default-state {
533 pins = "gpio12 437 pins = "gpio12", "gpio13", "gpio96", "gpio97";
534 function = "qu 438 function = "qup4";
535 drive-strength 439 drive-strength = <2>;
536 bias-pull-up; 440 bias-pull-up;
537 }; 441 };
538 442
539 qup_spi5_default: qup- 443 qup_spi5_default: qup-spi5-default-state {
540 pins = "gpio14 444 pins = "gpio14", "gpio15", "gpio16", "gpio17";
541 function = "qu 445 function = "qup5";
542 drive-strength 446 drive-strength = <2>;
543 bias-pull-up; 447 bias-pull-up;
544 }; 448 };
545 449
546 qup_uart0_default: qup 450 qup_uart0_default: qup-uart0-default-state {
547 pins = "gpio0" 451 pins = "gpio0", "gpio1", "gpio2", "gpio3";
548 function = "qu 452 function = "qup0";
549 drive-strength 453 drive-strength = <2>;
550 bias-disable; 454 bias-disable;
551 }; 455 };
552 456
553 qup_uart4_default: qup 457 qup_uart4_default: qup-uart4-default-state {
554 pins = "gpio12 458 pins = "gpio12", "gpio13";
555 function = "qu 459 function = "qup4";
556 drive-strength 460 drive-strength = <2>;
557 bias-disable; 461 bias-disable;
558 }; 462 };
559 463
560 sdc1_state_on: sdc1-on 464 sdc1_state_on: sdc1-on-state {
561 clk-pins { 465 clk-pins {
562 pins = 466 pins = "sdc1_clk";
563 drive- 467 drive-strength = <16>;
564 bias-d 468 bias-disable;
565 }; 469 };
566 470
567 cmd-pins { 471 cmd-pins {
568 pins = 472 pins = "sdc1_cmd";
569 drive- 473 drive-strength = <10>;
570 bias-p 474 bias-pull-up;
571 }; 475 };
572 476
573 data-pins { 477 data-pins {
574 pins = 478 pins = "sdc1_data";
575 drive- 479 drive-strength = <10>;
576 bias-p 480 bias-pull-up;
577 }; 481 };
578 482
579 rclk-pins { 483 rclk-pins {
580 pins = 484 pins = "sdc1_rclk";
581 bias-p 485 bias-pull-down;
582 }; 486 };
583 }; 487 };
584 488
585 sdc1_state_off: sdc1-o 489 sdc1_state_off: sdc1-off-state {
586 clk-pins { 490 clk-pins {
587 pins = 491 pins = "sdc1_clk";
588 drive- 492 drive-strength = <2>;
589 bias-d 493 bias-disable;
590 }; 494 };
591 495
592 cmd-pins { 496 cmd-pins {
593 pins = 497 pins = "sdc1_cmd";
594 drive- 498 drive-strength = <2>;
595 bias-p 499 bias-pull-up;
596 }; 500 };
597 501
598 data-pins { 502 data-pins {
599 pins = 503 pins = "sdc1_data";
600 drive- 504 drive-strength = <2>;
601 bias-p 505 bias-pull-up;
602 }; 506 };
603 507
604 rclk-pins { 508 rclk-pins {
605 pins = 509 pins = "sdc1_rclk";
606 bias-p 510 bias-pull-down;
607 }; 511 };
608 }; 512 };
609 513
610 sdc2_state_on: sdc2-on 514 sdc2_state_on: sdc2-on-state {
611 clk-pins { 515 clk-pins {
612 pins = 516 pins = "sdc2_clk";
613 drive- 517 drive-strength = <16>;
614 bias-d 518 bias-disable;
615 }; 519 };
616 520
617 cmd-pins { 521 cmd-pins {
618 pins = 522 pins = "sdc2_cmd";
619 drive- 523 drive-strength = <10>;
620 bias-p 524 bias-pull-up;
621 }; 525 };
622 526
623 data-pins { 527 data-pins {
624 pins = 528 pins = "sdc2_data";
625 drive- 529 drive-strength = <10>;
626 bias-p 530 bias-pull-up;
627 }; 531 };
628 }; 532 };
629 533
630 sdc2_state_off: sdc2-o 534 sdc2_state_off: sdc2-off-state {
631 clk-pins { 535 clk-pins {
632 pins = 536 pins = "sdc2_clk";
633 drive- 537 drive-strength = <2>;
634 bias-d 538 bias-disable;
635 }; 539 };
636 540
637 cmd-pins { 541 cmd-pins {
638 pins = 542 pins = "sdc2_cmd";
639 drive- 543 drive-strength = <2>;
640 bias-p 544 bias-pull-up;
641 }; 545 };
642 546
643 data-pins { 547 data-pins {
644 pins = 548 pins = "sdc2_data";
645 drive- 549 drive-strength = <2>;
646 bias-p 550 bias-pull-up;
647 }; 551 };
648 }; 552 };
649 }; 553 };
650 554
651 gcc: clock-controller@1400000 555 gcc: clock-controller@1400000 {
652 compatible = "qcom,gcc 556 compatible = "qcom,gcc-qcm2290";
653 reg = <0x0 0x01400000 557 reg = <0x0 0x01400000 0x0 0x1f0000>;
654 clocks = <&rpmcc RPM_S 558 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>;
655 clock-names = "bi_tcxo 559 clock-names = "bi_tcxo", "sleep_clk";
656 #clock-cells = <1>; 560 #clock-cells = <1>;
657 #reset-cells = <1>; 561 #reset-cells = <1>;
658 #power-domain-cells = 562 #power-domain-cells = <1>;
659 }; 563 };
660 564
661 usb_hsphy: phy@1613000 { 565 usb_hsphy: phy@1613000 {
662 compatible = "qcom,qcm 566 compatible = "qcom,qcm2290-qusb2-phy";
663 reg = <0x0 0x01613000 567 reg = <0x0 0x01613000 0x0 0x180>;
664 568
665 clocks = <&gcc GCC_AHB 569 clocks = <&gcc GCC_AHB2PHY_USB_CLK>,
666 <&rpmcc RPM_S 570 <&rpmcc RPM_SMD_XO_CLK_SRC>;
667 clock-names = "cfg_ahb 571 clock-names = "cfg_ahb", "ref";
668 572
669 resets = <&gcc GCC_QUS 573 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
670 nvmem-cells = <&qusb2_ 574 nvmem-cells = <&qusb2_hstx_trim>;
671 #phy-cells = <0>; 575 #phy-cells = <0>;
672 576
673 status = "disabled"; 577 status = "disabled";
674 }; 578 };
675 579
676 usb_qmpphy: phy@1615000 { <<
677 compatible = "qcom,qcm <<
678 reg = <0x0 0x01615000 <<
679 <<
680 clocks = <&gcc GCC_AHB <<
681 <&gcc GCC_USB <<
682 <&gcc GCC_USB <<
683 <&gcc GCC_USB <<
684 clock-names = "cfg_ahb <<
685 "ref", <<
686 "com_aux <<
687 "pipe"; <<
688 <<
689 resets = <&gcc GCC_USB <<
690 <&gcc GCC_USB <<
691 reset-names = "phy", <<
692 "phy_phy <<
693 <<
694 #clock-cells = <0>; <<
695 clock-output-names = " <<
696 <<
697 #phy-cells = <0>; <<
698 orientation-switch; <<
699 <<
700 qcom,tcsr-reg = <&tcsr <<
701 <<
702 status = "disabled"; <<
703 <<
704 ports { <<
705 #address-cells <<
706 #size-cells = <<
707 <<
708 port@0 { <<
709 reg = <<
710 <<
711 usb_qm <<
712 }; <<
713 }; <<
714 <<
715 port@1 { <<
716 reg = <<
717 <<
718 usb_qm <<
719 <<
720 }; <<
721 }; <<
722 }; <<
723 }; <<
724 <<
725 system_noc: interconnect@18800 <<
726 compatible = "qcom,qcm <<
727 reg = <0x0 0x01880000 <<
728 #interconnect-cells = <<
729 <<
730 qup_virt: interconnect <<
731 compatible = " <<
732 #interconnect- <<
733 }; <<
734 <<
735 mmnrt_virt: interconne <<
736 compatible = " <<
737 #interconnect- <<
738 }; <<
739 <<
740 mmrt_virt: interconnec <<
741 compatible = " <<
742 #interconnect- <<
743 }; <<
744 }; <<
745 <<
746 config_noc: interconnect@19000 <<
747 compatible = "qcom,qcm <<
748 reg = <0x0 0x01900000 <<
749 #interconnect-cells = <<
750 }; <<
751 <<
752 qfprom@1b44000 { 580 qfprom@1b44000 {
753 compatible = "qcom,qcm 581 compatible = "qcom,qcm2290-qfprom", "qcom,qfprom";
754 reg = <0x0 0x01b44000 582 reg = <0x0 0x01b44000 0x0 0x3000>;
755 #address-cells = <1>; 583 #address-cells = <1>;
756 #size-cells = <1>; 584 #size-cells = <1>;
757 585
758 qusb2_hstx_trim: hstx- 586 qusb2_hstx_trim: hstx-trim@25b {
759 reg = <0x25b 0 587 reg = <0x25b 0x1>;
760 bits = <1 4>; 588 bits = <1 4>;
761 }; 589 };
762 <<
763 gpu_speed_bin: gpu-spe <<
764 reg = <0x2006 <<
765 bits = <5 8>; <<
766 }; <<
767 }; <<
768 <<
769 pmu@1b8e300 { <<
770 compatible = "qcom,qcm <<
771 reg = <0x0 0x01b8e300 <<
772 interrupts = <GIC_SPI <<
773 <<
774 operating-points-v2 = <<
775 interconnects = <&bimc <<
776 &bimc <<
777 <<
778 cpu_bwmon_opp_table: o <<
779 compatible = " <<
780 <<
781 opp-0 { <<
782 opp-pe <<
783 }; <<
784 <<
785 opp-1 { <<
786 opp-pe <<
787 }; <<
788 <<
789 opp-2 { <<
790 opp-pe <<
791 }; <<
792 <<
793 opp-3 { <<
794 opp-pe <<
795 }; <<
796 <<
797 opp-4 { <<
798 opp-pe <<
799 }; <<
800 <<
801 opp-5 { <<
802 opp-pe <<
803 }; <<
804 <<
805 opp-6 { <<
806 opp-pe <<
807 }; <<
808 <<
809 opp-7 { <<
810 opp-pe <<
811 }; <<
812 <<
813 opp-8 { <<
814 opp-pe <<
815 }; <<
816 <<
817 opp-9 { <<
818 opp-pe <<
819 }; <<
820 }; <<
821 }; 590 };
822 591
823 spmi_bus: spmi@1c40000 { 592 spmi_bus: spmi@1c40000 {
824 compatible = "qcom,spm 593 compatible = "qcom,spmi-pmic-arb";
825 reg = <0x0 0x01c40000 594 reg = <0x0 0x01c40000 0x0 0x1100>,
826 <0x0 0x01e00000 595 <0x0 0x01e00000 0x0 0x2000000>,
827 <0x0 0x03e00000 596 <0x0 0x03e00000 0x0 0x100000>,
828 <0x0 0x03f00000 597 <0x0 0x03f00000 0x0 0xa0000>,
829 <0x0 0x01c0a000 598 <0x0 0x01c0a000 0x0 0x26000>;
830 reg-names = "core", 599 reg-names = "core",
831 "chnls", 600 "chnls",
832 "obsrvr", 601 "obsrvr",
833 "intr", 602 "intr",
834 "cnfg"; 603 "cnfg";
835 interrupts-extended = !! 604 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
836 interrupt-names = "per 605 interrupt-names = "periph_irq";
837 qcom,ee = <0>; 606 qcom,ee = <0>;
838 qcom,channel = <0>; 607 qcom,channel = <0>;
839 #address-cells = <2>; 608 #address-cells = <2>;
840 #size-cells = <0>; 609 #size-cells = <0>;
841 interrupt-controller; 610 interrupt-controller;
842 #interrupt-cells = <4> 611 #interrupt-cells = <4>;
843 }; 612 };
844 613
845 tsens0: thermal-sensor@4411000 614 tsens0: thermal-sensor@4411000 {
846 compatible = "qcom,qcm 615 compatible = "qcom,qcm2290-tsens", "qcom,tsens-v2";
847 reg = <0x0 0x04411000 616 reg = <0x0 0x04411000 0x0 0x1ff>,
848 <0x0 0x04410000 617 <0x0 0x04410000 0x0 0x8>;
849 #qcom,sensors = <10>; 618 #qcom,sensors = <10>;
850 interrupts-extended = !! 619 interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
851 !! 620 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
852 interrupt-names = "upl 621 interrupt-names = "uplow", "critical";
853 #thermal-sensor-cells 622 #thermal-sensor-cells = <1>;
854 }; 623 };
855 624
856 rng: rng@4453000 { 625 rng: rng@4453000 {
857 compatible = "qcom,prn 626 compatible = "qcom,prng-ee";
858 reg = <0x0 0x04453000 627 reg = <0x0 0x04453000 0x0 0x1000>;
859 clocks = <&rpmcc RPM_S 628 clocks = <&rpmcc RPM_SMD_HWKM_CLK>;
860 clock-names = "core"; 629 clock-names = "core";
861 }; 630 };
862 631
863 bimc: interconnect@4480000 { <<
864 compatible = "qcom,qcm <<
865 reg = <0x0 0x04480000 <<
866 #interconnect-cells = <<
867 }; <<
868 <<
869 rpm_msg_ram: sram@45f0000 { 632 rpm_msg_ram: sram@45f0000 {
870 compatible = "qcom,rpm !! 633 compatible = "qcom,rpm-msg-ram";
871 reg = <0x0 0x045f0000 634 reg = <0x0 0x045f0000 0x0 0x7000>;
872 #address-cells = <1>; <<
873 #size-cells = <1>; <<
874 ranges = <0 0x0 0x045f <<
875 <<
876 apss_mpm: sram@1b8 { <<
877 reg = <0x1b8 0 <<
878 }; <<
879 }; 635 };
880 636
881 sram@4690000 { 637 sram@4690000 {
882 compatible = "qcom,rpm 638 compatible = "qcom,rpm-stats";
883 reg = <0x0 0x04690000 639 reg = <0x0 0x04690000 0x0 0x10000>;
884 }; 640 };
885 641
886 sdhc_1: mmc@4744000 { 642 sdhc_1: mmc@4744000 {
887 compatible = "qcom,qcm 643 compatible = "qcom,qcm2290-sdhci", "qcom,sdhci-msm-v5";
888 reg = <0x0 0x04744000 644 reg = <0x0 0x04744000 0x0 0x1000>,
889 <0x0 0x04745000 645 <0x0 0x04745000 0x0 0x1000>,
890 <0x0 0x04748000 646 <0x0 0x04748000 0x0 0x8000>;
891 reg-names = "hc", 647 reg-names = "hc",
892 "cqhci", 648 "cqhci",
893 "ice"; 649 "ice";
894 650
895 interrupts = <GIC_SPI 651 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
896 <GIC_SPI 652 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
897 interrupt-names = "hc_ 653 interrupt-names = "hc_irq", "pwr_irq";
898 654
899 clocks = <&gcc GCC_SDC 655 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
900 <&gcc GCC_SDC 656 <&gcc GCC_SDCC1_APPS_CLK>,
901 <&rpmcc RPM_S 657 <&rpmcc RPM_SMD_XO_CLK_SRC>,
902 <&gcc GCC_SDC 658 <&gcc GCC_SDCC1_ICE_CORE_CLK>;
903 clock-names = "iface", 659 clock-names = "iface",
904 "core", 660 "core",
905 "xo", 661 "xo",
906 "ice"; 662 "ice";
907 663
908 resets = <&gcc GCC_SDC 664 resets = <&gcc GCC_SDCC1_BCR>;
909 665
910 power-domains = <&rpmp 666 power-domains = <&rpmpd QCM2290_VDDCX>;
911 operating-points-v2 = <<
912 iommus = <&apps_smmu 0 667 iommus = <&apps_smmu 0xc0 0x0>;
913 interconnects = <&syst <<
914 &bimc <<
915 <&bimc <<
916 &conf <<
917 interconnect-names = " <<
918 " <<
919 668
920 qcom,dll-config = <0x0 669 qcom,dll-config = <0x000f642c>;
921 qcom,ddr-config = <0x8 670 qcom,ddr-config = <0x80040868>;
922 bus-width = <8>; 671 bus-width = <8>;
923 672
924 status = "disabled"; 673 status = "disabled";
925 <<
926 sdhc1_opp_table: opp-t <<
927 compatible = " <<
928 <<
929 opp-100000000 <<
930 opp-hz <<
931 requir <<
932 opp-pe <<
933 opp-av <<
934 }; <<
935 <<
936 opp-192000000 <<
937 opp-hz <<
938 requir <<
939 opp-pe <<
940 opp-av <<
941 }; <<
942 <<
943 opp-384000000 <<
944 opp-hz <<
945 requir <<
946 opp-pe <<
947 opp-av <<
948 }; <<
949 }; <<
950 }; 674 };
951 675
952 sdhc_2: mmc@4784000 { 676 sdhc_2: mmc@4784000 {
953 compatible = "qcom,qcm 677 compatible = "qcom,qcm2290-sdhci", "qcom,sdhci-msm-v5";
954 reg = <0x0 0x04784000 678 reg = <0x0 0x04784000 0x0 0x1000>;
955 reg-names = "hc"; 679 reg-names = "hc";
956 680
957 interrupts = <GIC_SPI 681 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
958 <GIC_SPI 682 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
959 interrupt-names = "hc_ 683 interrupt-names = "hc_irq", "pwr_irq";
960 684
961 clocks = <&gcc GCC_SDC 685 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
962 <&gcc GCC_SDC 686 <&gcc GCC_SDCC2_APPS_CLK>,
963 <&rpmcc RPM_S 687 <&rpmcc RPM_SMD_XO_CLK_SRC>;
964 clock-names = "iface", 688 clock-names = "iface",
965 "core", 689 "core",
966 "xo"; 690 "xo";
967 691
968 resets = <&gcc GCC_SDC 692 resets = <&gcc GCC_SDCC2_BCR>;
969 693
970 power-domains = <&rpmp 694 power-domains = <&rpmpd QCM2290_VDDCX>;
971 operating-points-v2 = 695 operating-points-v2 = <&sdhc2_opp_table>;
972 iommus = <&apps_smmu 0 696 iommus = <&apps_smmu 0xa0 0x0>;
973 interconnects = <&syst <<
974 &bimc <<
975 <&bimc <<
976 &conf <<
977 interconnect-names = " <<
978 " <<
979 697
980 qcom,dll-config = <0x0 698 qcom,dll-config = <0x0007642c>;
981 qcom,ddr-config = <0x8 699 qcom,ddr-config = <0x80040868>;
982 bus-width = <4>; 700 bus-width = <4>;
983 701
984 status = "disabled"; 702 status = "disabled";
985 703
986 sdhc2_opp_table: opp-t 704 sdhc2_opp_table: opp-table {
987 compatible = " 705 compatible = "operating-points-v2";
988 706
989 opp-100000000 707 opp-100000000 {
990 opp-hz 708 opp-hz = /bits/ 64 <100000000>;
991 requir 709 required-opps = <&rpmpd_opp_low_svs>;
992 opp-pe <<
993 opp-av <<
994 }; 710 };
995 711
996 opp-202000000 712 opp-202000000 {
997 opp-hz 713 opp-hz = /bits/ 64 <202000000>;
998 requir 714 required-opps = <&rpmpd_opp_svs_plus>;
999 opp-pe <<
1000 opp-a <<
1001 }; 715 };
1002 }; 716 };
1003 }; 717 };
1004 718
1005 gpi_dma0: dma-controller@4a00 719 gpi_dma0: dma-controller@4a00000 {
1006 compatible = "qcom,qc 720 compatible = "qcom,qcm2290-gpi-dma", "qcom,sm6350-gpi-dma";
1007 reg = <0x0 0x04a00000 721 reg = <0x0 0x04a00000 0x0 0x60000>;
1008 interrupts = <GIC_SPI 722 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1009 <GIC_SPI 723 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1010 <GIC_SPI 724 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
1011 <GIC_SPI 725 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
1012 <GIC_SPI 726 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
1013 <GIC_SPI 727 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
1014 <GIC_SPI 728 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
1015 <GIC_SPI 729 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
1016 <GIC_SPI 730 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
1017 <GIC_SPI 731 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1018 dma-channels = <10>; !! 732 dma-channels = <10>;
1019 dma-channel-mask = <0 733 dma-channel-mask = <0x1f>;
1020 iommus = <&apps_smmu 734 iommus = <&apps_smmu 0xf6 0x0>;
1021 #dma-cells = <3>; 735 #dma-cells = <3>;
1022 status = "disabled"; 736 status = "disabled";
1023 }; 737 };
1024 738
1025 qupv3_id_0: geniqup@4ac0000 { 739 qupv3_id_0: geniqup@4ac0000 {
1026 compatible = "qcom,ge 740 compatible = "qcom,geni-se-qup";
1027 reg = <0x0 0x04ac0000 741 reg = <0x0 0x04ac0000 0x0 0x2000>;
1028 clocks = <&gcc GCC_QU 742 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1029 <&gcc GCC_QU 743 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1030 clock-names = "m-ahb" 744 clock-names = "m-ahb", "s-ahb";
1031 iommus = <&apps_smmu 745 iommus = <&apps_smmu 0xe3 0x0>;
1032 #address-cells = <2>; 746 #address-cells = <2>;
1033 #size-cells = <2>; 747 #size-cells = <2>;
1034 ranges; 748 ranges;
1035 status = "disabled"; 749 status = "disabled";
1036 750
1037 i2c0: i2c@4a80000 { 751 i2c0: i2c@4a80000 {
1038 compatible = 752 compatible = "qcom,geni-i2c";
1039 reg = <0x0 0x 753 reg = <0x0 0x04a80000 0x0 0x4000>;
1040 interrupts = 754 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
1041 clocks = <&gc 755 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1042 clock-names = 756 clock-names = "se";
1043 pinctrl-0 = < 757 pinctrl-0 = <&qup_i2c0_default>;
1044 pinctrl-names 758 pinctrl-names = "default";
1045 dmas = <&gpi_ 759 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1046 <&gpi_ 760 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1047 dma-names = " 761 dma-names = "tx", "rx";
1048 interconnects <<
1049 <<
1050 <<
1051 <<
1052 <<
1053 <<
1054 interconnect- <<
1055 <<
1056 <<
1057 #address-cell 762 #address-cells = <1>;
1058 #size-cells = 763 #size-cells = <0>;
1059 status = "dis 764 status = "disabled";
1060 }; 765 };
1061 766
1062 spi0: spi@4a80000 { 767 spi0: spi@4a80000 {
1063 compatible = 768 compatible = "qcom,geni-spi";
1064 reg = <0x0 0x 769 reg = <0x0 0x04a80000 0x0 0x4000>;
1065 interrupts = 770 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
1066 clocks = <&gc 771 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1067 clock-names = 772 clock-names = "se";
1068 pinctrl-0 = < 773 pinctrl-0 = <&qup_spi0_default>;
1069 pinctrl-names 774 pinctrl-names = "default";
1070 dmas = <&gpi_ 775 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1071 <&gpi_ 776 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1072 dma-names = " 777 dma-names = "tx", "rx";
1073 interconnects <<
1074 <<
1075 <<
1076 <<
1077 interconnect- <<
1078 <<
1079 #address-cell 778 #address-cells = <1>;
1080 #size-cells = 779 #size-cells = <0>;
1081 status = "dis 780 status = "disabled";
1082 }; 781 };
1083 782
1084 uart0: serial@4a80000 783 uart0: serial@4a80000 {
1085 compatible = 784 compatible = "qcom,geni-uart";
1086 reg = <0x0 0x 785 reg = <0x0 0x04a80000 0x0 0x4000>;
1087 interrupts = 786 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
1088 clocks = <&gc 787 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1089 clock-names = 788 clock-names = "se";
1090 pinctrl-0 = < 789 pinctrl-0 = <&qup_uart0_default>;
1091 pinctrl-names 790 pinctrl-names = "default";
1092 interconnects <<
1093 <<
1094 <<
1095 <<
1096 interconnect- <<
1097 <<
1098 status = "dis 791 status = "disabled";
1099 }; 792 };
1100 793
1101 i2c1: i2c@4a84000 { 794 i2c1: i2c@4a84000 {
1102 compatible = 795 compatible = "qcom,geni-i2c";
1103 reg = <0x0 0x 796 reg = <0x0 0x04a84000 0x0 0x4000>;
1104 interrupts = 797 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
1105 clocks = <&gc 798 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1106 clock-names = 799 clock-names = "se";
1107 pinctrl-0 = < 800 pinctrl-0 = <&qup_i2c1_default>;
1108 pinctrl-names 801 pinctrl-names = "default";
1109 dmas = <&gpi_ 802 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1110 <&gpi_ 803 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1111 dma-names = " 804 dma-names = "tx", "rx";
1112 interconnects <<
1113 <<
1114 <<
1115 <<
1116 <<
1117 <<
1118 interconnect- <<
1119 <<
1120 <<
1121 #address-cell 805 #address-cells = <1>;
1122 #size-cells = 806 #size-cells = <0>;
1123 status = "dis 807 status = "disabled";
1124 }; 808 };
1125 809
1126 spi1: spi@4a84000 { 810 spi1: spi@4a84000 {
1127 compatible = 811 compatible = "qcom,geni-spi";
1128 reg = <0x0 0x 812 reg = <0x0 0x04a84000 0x0 0x4000>;
1129 interrupts = 813 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
1130 clocks = <&gc 814 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1131 clock-names = 815 clock-names = "se";
1132 pinctrl-0 = < 816 pinctrl-0 = <&qup_spi1_default>;
1133 pinctrl-names 817 pinctrl-names = "default";
1134 dmas = <&gpi_ 818 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1135 <&gpi_ 819 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1136 dma-names = " 820 dma-names = "tx", "rx";
1137 interconnects <<
1138 <<
1139 <<
1140 <<
1141 interconnect- <<
1142 <<
1143 #address-cell 821 #address-cells = <1>;
1144 #size-cells = 822 #size-cells = <0>;
1145 status = "dis 823 status = "disabled";
1146 }; 824 };
1147 825
1148 i2c2: i2c@4a88000 { 826 i2c2: i2c@4a88000 {
1149 compatible = 827 compatible = "qcom,geni-i2c";
1150 reg = <0x0 0x 828 reg = <0x0 0x04a88000 0x0 0x4000>;
1151 interrupts = 829 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
1152 clocks = <&gc 830 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1153 clock-names = 831 clock-names = "se";
1154 pinctrl-0 = < 832 pinctrl-0 = <&qup_i2c2_default>;
1155 pinctrl-names 833 pinctrl-names = "default";
1156 dmas = <&gpi_ 834 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1157 <&gpi_ 835 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1158 dma-names = " 836 dma-names = "tx", "rx";
1159 interconnects <<
1160 <<
1161 <<
1162 <<
1163 <<
1164 <<
1165 interconnect- <<
1166 <<
1167 <<
1168 #address-cell 837 #address-cells = <1>;
1169 #size-cells = 838 #size-cells = <0>;
1170 status = "dis 839 status = "disabled";
1171 }; 840 };
1172 841
1173 spi2: spi@4a88000 { 842 spi2: spi@4a88000 {
1174 compatible = 843 compatible = "qcom,geni-spi";
1175 reg = <0x0 0x 844 reg = <0x0 0x04a88000 0x0 0x4000>;
1176 interrupts = 845 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
1177 clocks = <&gc 846 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1178 clock-names = 847 clock-names = "se";
1179 pinctrl-0 = < 848 pinctrl-0 = <&qup_spi2_default>;
1180 pinctrl-names 849 pinctrl-names = "default";
1181 dmas = <&gpi_ 850 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1182 <&gpi_ 851 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1183 dma-names = " 852 dma-names = "tx", "rx";
1184 interconnects <<
1185 <<
1186 <<
1187 <<
1188 interconnect- <<
1189 <<
1190 #address-cell 853 #address-cells = <1>;
1191 #size-cells = 854 #size-cells = <0>;
1192 status = "dis 855 status = "disabled";
1193 }; 856 };
1194 857
1195 i2c3: i2c@4a8c000 { 858 i2c3: i2c@4a8c000 {
1196 compatible = 859 compatible = "qcom,geni-i2c";
1197 reg = <0x0 0x 860 reg = <0x0 0x04a8c000 0x0 0x4000>;
1198 interrupts = 861 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
1199 clocks = <&gc 862 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1200 clock-names = 863 clock-names = "se";
1201 pinctrl-0 = < 864 pinctrl-0 = <&qup_i2c3_default>;
1202 pinctrl-names 865 pinctrl-names = "default";
1203 dmas = <&gpi_ 866 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1204 <&gpi_ 867 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1205 dma-names = " 868 dma-names = "tx", "rx";
1206 interconnects <<
1207 <<
1208 <<
1209 <<
1210 <<
1211 <<
1212 interconnect- <<
1213 <<
1214 <<
1215 #address-cell 869 #address-cells = <1>;
1216 #size-cells = 870 #size-cells = <0>;
1217 status = "dis 871 status = "disabled";
1218 }; 872 };
1219 873
1220 spi3: spi@4a8c000 { 874 spi3: spi@4a8c000 {
1221 compatible = 875 compatible = "qcom,geni-spi";
1222 reg = <0x0 0x 876 reg = <0x0 0x04a8c000 0x0 0x4000>;
1223 interrupts = 877 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
1224 clocks = <&gc 878 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1225 clock-names = 879 clock-names = "se";
1226 pinctrl-0 = < 880 pinctrl-0 = <&qup_spi3_default>;
1227 pinctrl-names 881 pinctrl-names = "default";
1228 dmas = <&gpi_ 882 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1229 <&gpi_ 883 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1230 dma-names = " 884 dma-names = "tx", "rx";
1231 interconnects <<
1232 <<
1233 <<
1234 <<
1235 interconnect- <<
1236 <<
1237 #address-cell 885 #address-cells = <1>;
1238 #size-cells = 886 #size-cells = <0>;
1239 status = "dis 887 status = "disabled";
1240 }; 888 };
1241 889
1242 i2c4: i2c@4a90000 { 890 i2c4: i2c@4a90000 {
1243 compatible = 891 compatible = "qcom,geni-i2c";
1244 reg = <0x0 0x 892 reg = <0x0 0x04a90000 0x0 0x4000>;
1245 interrupts = 893 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
1246 clocks = <&gc 894 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1247 clock-names = 895 clock-names = "se";
1248 pinctrl-0 = < 896 pinctrl-0 = <&qup_i2c4_default>;
1249 pinctrl-names 897 pinctrl-names = "default";
1250 dmas = <&gpi_ 898 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1251 <&gpi_ 899 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1252 dma-names = " 900 dma-names = "tx", "rx";
1253 interconnects <<
1254 <<
1255 <<
1256 <<
1257 <<
1258 <<
1259 interconnect- <<
1260 <<
1261 <<
1262 #address-cell 901 #address-cells = <1>;
1263 #size-cells = 902 #size-cells = <0>;
1264 status = "dis 903 status = "disabled";
1265 }; 904 };
1266 905
1267 spi4: spi@4a90000 { 906 spi4: spi@4a90000 {
1268 compatible = 907 compatible = "qcom,geni-spi";
1269 reg = <0x0 0x 908 reg = <0x0 0x04a90000 0x0 0x4000>;
1270 interrupts = 909 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
1271 clock-names = 910 clock-names = "se";
1272 clocks = <&gc 911 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1273 pinctrl-names 912 pinctrl-names = "default";
1274 pinctrl-0 = < 913 pinctrl-0 = <&qup_spi4_default>;
1275 dmas = <&gpi_ 914 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1276 <&gpi_ 915 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1277 dma-names = " 916 dma-names = "tx", "rx";
1278 interconnects <<
1279 <<
1280 <<
1281 <<
1282 interconnect- <<
1283 <<
1284 #address-cell 917 #address-cells = <1>;
1285 #size-cells = 918 #size-cells = <0>;
1286 status = "dis 919 status = "disabled";
1287 }; 920 };
1288 921
1289 uart4: serial@4a90000 922 uart4: serial@4a90000 {
1290 compatible = 923 compatible = "qcom,geni-uart";
1291 reg = <0x0 0x 924 reg = <0x0 0x04a90000 0x0 0x4000>;
1292 interrupts = 925 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
1293 clocks = <&gc 926 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1294 clock-names = 927 clock-names = "se";
1295 pinctrl-0 = < 928 pinctrl-0 = <&qup_uart4_default>;
1296 pinctrl-names 929 pinctrl-names = "default";
1297 interconnects <<
1298 <<
1299 <<
1300 <<
1301 interconnect- <<
1302 <<
1303 status = "dis 930 status = "disabled";
1304 }; 931 };
1305 932
1306 i2c5: i2c@4a94000 { 933 i2c5: i2c@4a94000 {
1307 compatible = 934 compatible = "qcom,geni-i2c";
1308 reg = <0x0 0x 935 reg = <0x0 0x04a94000 0x0 0x4000>;
1309 interrupts = 936 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
1310 clocks = <&gc 937 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1311 clock-names = 938 clock-names = "se";
1312 pinctrl-0 = < 939 pinctrl-0 = <&qup_i2c5_default>;
1313 pinctrl-names 940 pinctrl-names = "default";
1314 dmas = <&gpi_ 941 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1315 <&gpi_ 942 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1316 dma-names = " 943 dma-names = "tx", "rx";
1317 interconnects <<
1318 <<
1319 <<
1320 <<
1321 <<
1322 <<
1323 interconnect- <<
1324 <<
1325 <<
1326 #address-cell 944 #address-cells = <1>;
1327 #size-cells = 945 #size-cells = <0>;
1328 status = "dis 946 status = "disabled";
1329 }; 947 };
1330 948
1331 spi5: spi@4a94000 { 949 spi5: spi@4a94000 {
1332 compatible = 950 compatible = "qcom,geni-spi";
1333 reg = <0x0 0x 951 reg = <0x0 0x04a94000 0x0 0x4000>;
1334 interrupts = 952 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
1335 clocks = <&gc 953 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1336 clock-names = 954 clock-names = "se";
1337 pinctrl-0 = < 955 pinctrl-0 = <&qup_spi5_default>;
1338 pinctrl-names 956 pinctrl-names = "default";
1339 dmas = <&gpi_ 957 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1340 <&gpi_ 958 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1341 dma-names = " 959 dma-names = "tx", "rx";
1342 interconnects <<
1343 <<
1344 <<
1345 <<
1346 interconnect- <<
1347 <<
1348 #address-cell 960 #address-cells = <1>;
1349 #size-cells = 961 #size-cells = <0>;
1350 status = "dis 962 status = "disabled";
1351 }; 963 };
1352 }; 964 };
1353 965
1354 usb: usb@4ef8800 { 966 usb: usb@4ef8800 {
1355 compatible = "qcom,qc 967 compatible = "qcom,qcm2290-dwc3", "qcom,dwc3";
1356 reg = <0x0 0x04ef8800 968 reg = <0x0 0x04ef8800 0x0 0x400>;
1357 interrupts-extended = !! 969 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
1358 !! 970 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
1359 interrupt-names = "hs !! 971 interrupt-names = "hs_phy_irq", "ss_phy_irq";
1360 "ss <<
1361 972
1362 clocks = <&gcc GCC_CF 973 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
1363 <&gcc GCC_US 974 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
1364 <&gcc GCC_SY 975 <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>,
1365 <&gcc GCC_US 976 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
1366 <&gcc GCC_US 977 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1367 <&gcc GCC_US 978 <&gcc GCC_USB3_PRIM_CLKREF_CLK>;
1368 clock-names = "cfg_no 979 clock-names = "cfg_noc",
1369 "core", 980 "core",
1370 "iface" 981 "iface",
1371 "sleep" 982 "sleep",
1372 "mock_u 983 "mock_utmi",
1373 "xo"; 984 "xo";
1374 985
1375 assigned-clocks = <&g 986 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1376 <&g 987 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
1377 assigned-clock-rates 988 assigned-clock-rates = <19200000>, <133333333>;
1378 989
1379 resets = <&gcc GCC_US 990 resets = <&gcc GCC_USB30_PRIM_BCR>;
1380 power-domains = <&gcc 991 power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
1381 /* TODO: USB<->IPA pa <<
1382 interconnects = <&sys <<
1383 &bim <<
1384 <&bim <<
1385 &con <<
1386 interconnect-names = <<
1387 <<
1388 wakeup-source; 992 wakeup-source;
1389 993
1390 #address-cells = <2>; 994 #address-cells = <2>;
1391 #size-cells = <2>; 995 #size-cells = <2>;
1392 ranges; 996 ranges;
1393 997
1394 status = "disabled"; 998 status = "disabled";
1395 999
1396 usb_dwc3: usb@4e00000 1000 usb_dwc3: usb@4e00000 {
1397 compatible = 1001 compatible = "snps,dwc3";
1398 reg = <0x0 0x 1002 reg = <0x0 0x04e00000 0x0 0xcd00>;
1399 interrupts = 1003 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
1400 phys = <&usb_ !! 1004 phys = <&usb_hsphy>;
1401 phy-names = " !! 1005 phy-names = "usb2-phy";
1402 iommus = <&ap 1006 iommus = <&apps_smmu 0x120 0x0>;
1403 snps,dis_u2_s 1007 snps,dis_u2_susphy_quirk;
1404 snps,dis_enbl 1008 snps,dis_enblslpm_quirk;
1405 snps,has-lpm- 1009 snps,has-lpm-erratum;
1406 snps,hird-thr 1010 snps,hird-threshold = /bits/ 8 <0x10>;
1407 snps,usb3_lpm 1011 snps,usb3_lpm_capable;
1408 maximum-speed 1012 maximum-speed = "super-speed";
1409 dr_mode = "ot 1013 dr_mode = "otg";
1410 usb-role-swit <<
1411 <<
1412 ports { <<
1413 #addr <<
1414 #size <<
1415 <<
1416 port@ <<
1417 <<
1418 <<
1419 <<
1420 <<
1421 }; <<
1422 <<
1423 port@ <<
1424 <<
1425 <<
1426 <<
1427 <<
1428 <<
1429 }; <<
1430 }; <<
1431 }; 1014 };
1432 }; 1015 };
1433 1016
1434 gpu: gpu@5900000 { <<
1435 compatible = "qcom,ad <<
1436 reg = <0x0 0x05900000 <<
1437 reg-names = "kgsl_3d0 <<
1438 <<
1439 interrupts = <GIC_SPI <<
1440 <<
1441 clocks = <&gpucc GPU_ <<
1442 <&gpucc GPU_ <<
1443 <&gcc GCC_BI <<
1444 <&gcc GCC_GP <<
1445 <&gpucc GPU_ <<
1446 <&gpucc GPU_ <<
1447 clock-names = "core", <<
1448 "iface" <<
1449 "mem_if <<
1450 "alt_me <<
1451 "gmu", <<
1452 "xo"; <<
1453 <<
1454 interconnects = <&bim <<
1455 &bim <<
1456 interconnect-names = <<
1457 <<
1458 iommus = <&adreno_smm <<
1459 <&adreno_smm <<
1460 operating-points-v2 = <<
1461 power-domains = <&rpm <<
1462 qcom,gmu = <&gmu_wrap <<
1463 <<
1464 nvmem-cells = <&gpu_s <<
1465 nvmem-cell-names = "s <<
1466 #cooling-cells = <2>; <<
1467 <<
1468 status = "disabled"; <<
1469 <<
1470 zap-shader { <<
1471 memory-region <<
1472 }; <<
1473 <<
1474 gpu_opp_table: opp-ta <<
1475 compatible = <<
1476 <<
1477 /* TODO: Scal <<
1478 opp-112320000 <<
1479 opp-h <<
1480 requi <<
1481 opp-p <<
1482 opp-s <<
1483 turbo <<
1484 }; <<
1485 <<
1486 opp-101760000 <<
1487 opp-h <<
1488 requi <<
1489 opp-p <<
1490 opp-s <<
1491 turbo <<
1492 }; <<
1493 <<
1494 opp-921600000 <<
1495 opp-h <<
1496 requi <<
1497 opp-p <<
1498 opp-s <<
1499 }; <<
1500 <<
1501 opp-844800000 <<
1502 opp-h <<
1503 requi <<
1504 opp-p <<
1505 opp-s <<
1506 }; <<
1507 <<
1508 opp-672000000 <<
1509 opp-h <<
1510 requi <<
1511 opp-p <<
1512 opp-s <<
1513 }; <<
1514 <<
1515 opp-537600000 <<
1516 opp-h <<
1517 requi <<
1518 opp-p <<
1519 opp-s <<
1520 }; <<
1521 <<
1522 opp-355200000 <<
1523 opp-h <<
1524 requi <<
1525 opp-p <<
1526 opp-s <<
1527 }; <<
1528 }; <<
1529 }; <<
1530 <<
1531 gmu_wrapper: gmu@596a000 { <<
1532 compatible = "qcom,ad <<
1533 reg = <0x0 0x0596a000 <<
1534 reg-names = "gmu"; <<
1535 power-domains = <&gpu <<
1536 <&gpu <<
1537 power-domain-names = <<
1538 <<
1539 }; <<
1540 <<
1541 gpucc: clock-controller@59900 <<
1542 compatible = "qcom,qc <<
1543 reg = <0x0 0x05990000 <<
1544 clocks = <&gcc GCC_GP <<
1545 <&rpmcc RPM_ <<
1546 <&gcc GCC_GP <<
1547 <&gcc GCC_GP <<
1548 power-domains = <&rpm <<
1549 required-opps = <&rpm <<
1550 #clock-cells = <1>; <<
1551 #reset-cells = <1>; <<
1552 #power-domain-cells = <<
1553 }; <<
1554 <<
1555 adreno_smmu: iommu@59a0000 { <<
1556 compatible = "qcom,qc <<
1557 "qcom,sm <<
1558 reg = <0x0 0x059a0000 <<
1559 interrupts = <GIC_SPI <<
1560 <GIC_SPI <<
1561 <GIC_SPI <<
1562 <GIC_SPI <<
1563 <GIC_SPI <<
1564 <GIC_SPI <<
1565 <GIC_SPI <<
1566 <GIC_SPI <<
1567 <GIC_SPI <<
1568 <<
1569 clocks = <&gcc GCC_GP <<
1570 <&gpucc GPU_ <<
1571 <&gcc GCC_GP <<
1572 clock-names = "mem", <<
1573 "hlos", <<
1574 "iface" <<
1575 <<
1576 power-domains = <&gpu <<
1577 <<
1578 #global-interrupts = <<
1579 #iommu-cells = <2>; <<
1580 }; <<
1581 <<
1582 mdss: display-subsystem@5e000 <<
1583 compatible = "qcom,qc <<
1584 reg = <0x0 0x05e00000 <<
1585 reg-names = "mdss"; <<
1586 interrupts = <GIC_SPI <<
1587 interrupt-controller; <<
1588 #interrupt-cells = <1 <<
1589 <<
1590 clocks = <&gcc GCC_DI <<
1591 <&gcc GCC_DI <<
1592 <&dispcc DIS <<
1593 clock-names = "iface" <<
1594 "bus", <<
1595 "core"; <<
1596 <<
1597 resets = <&dispcc DIS <<
1598 <<
1599 power-domains = <&dis <<
1600 <<
1601 iommus = <&apps_smmu <<
1602 <&apps_smmu <<
1603 interconnects = <&mmr <<
1604 &bim <<
1605 <&bim <<
1606 &con <<
1607 interconnect-names = <<
1608 <<
1609 <<
1610 #address-cells = <2>; <<
1611 #size-cells = <2>; <<
1612 ranges; <<
1613 <<
1614 status = "disabled"; <<
1615 <<
1616 mdp: display-controll <<
1617 compatible = <<
1618 reg = <0x0 0x <<
1619 <0x0 0x <<
1620 reg-names = " <<
1621 " <<
1622 <<
1623 interrupt-par <<
1624 interrupts = <<
1625 <<
1626 clocks = <&gc <<
1627 <&di <<
1628 <&di <<
1629 <&di <<
1630 <&di <<
1631 clock-names = <<
1632 <<
1633 <<
1634 <<
1635 <<
1636 <<
1637 operating-poi <<
1638 power-domains <<
1639 <<
1640 ports { <<
1641 #addr <<
1642 #size <<
1643 <<
1644 port@ <<
1645 <<
1646 <<
1647 <<
1648 <<
1649 }; <<
1650 }; <<
1651 <<
1652 mdp_opp_table <<
1653 compa <<
1654 <<
1655 opp-1 <<
1656 <<
1657 <<
1658 }; <<
1659 <<
1660 opp-1 <<
1661 <<
1662 <<
1663 }; <<
1664 <<
1665 opp-2 <<
1666 <<
1667 <<
1668 }; <<
1669 <<
1670 opp-3 <<
1671 <<
1672 <<
1673 }; <<
1674 <<
1675 opp-3 <<
1676 <<
1677 <<
1678 }; <<
1679 }; <<
1680 }; <<
1681 <<
1682 mdss_dsi0: dsi@5e9400 <<
1683 compatible = <<
1684 reg = <0x0 0x <<
1685 reg-names = " <<
1686 <<
1687 interrupt-par <<
1688 interrupts = <<
1689 <<
1690 clocks = <&di <<
1691 <&di <<
1692 <&di <<
1693 <&di <<
1694 <&di <<
1695 <&gc <<
1696 clock-names = <<
1697 <<
1698 <<
1699 <<
1700 <<
1701 <<
1702 <<
1703 assigned-cloc <<
1704 <<
1705 assigned-cloc <<
1706 <<
1707 <<
1708 operating-poi <<
1709 power-domains <<
1710 phys = <&mdss <<
1711 <<
1712 #address-cell <<
1713 #size-cells = <<
1714 <<
1715 status = "dis <<
1716 <<
1717 dsi_opp_table <<
1718 compa <<
1719 <<
1720 opp-1 <<
1721 <<
1722 <<
1723 }; <<
1724 <<
1725 opp-1 <<
1726 <<
1727 <<
1728 }; <<
1729 <<
1730 opp-1 <<
1731 <<
1732 <<
1733 }; <<
1734 }; <<
1735 <<
1736 ports { <<
1737 #addr <<
1738 #size <<
1739 <<
1740 port@ <<
1741 <<
1742 <<
1743 <<
1744 <<
1745 <<
1746 }; <<
1747 <<
1748 port@ <<
1749 <<
1750 <<
1751 <<
1752 <<
1753 }; <<
1754 }; <<
1755 }; <<
1756 <<
1757 mdss_dsi0_phy: phy@5e <<
1758 compatible = <<
1759 reg = <0x0 0x <<
1760 <0x0 0x <<
1761 <0x0 0x <<
1762 reg-names = " <<
1763 " <<
1764 " <<
1765 <<
1766 clocks = <&di <<
1767 <&rp <<
1768 clock-names = <<
1769 <<
1770 <<
1771 power-domains <<
1772 required-opps <<
1773 <<
1774 #clock-cells <<
1775 #phy-cells = <<
1776 <<
1777 status = "dis <<
1778 }; <<
1779 }; <<
1780 <<
1781 dispcc: clock-controller@5f00 <<
1782 compatible = "qcom,qc <<
1783 reg = <0x0 0x05f00000 <<
1784 clocks = <&rpmcc RPM_ <<
1785 <&rpmcc RPM_ <<
1786 <&gcc GCC_DI <<
1787 <&gcc GCC_DI <<
1788 <&mdss_dsi0_ <<
1789 <&mdss_dsi0_ <<
1790 clock-names = "bi_tcx <<
1791 "bi_tcx <<
1792 "gcc_di <<
1793 "gcc_di <<
1794 "dsi0_p <<
1795 "dsi0_p <<
1796 #power-domain-cells = <<
1797 #clock-cells = <1>; <<
1798 #reset-cells = <1>; <<
1799 }; <<
1800 <<
1801 remoteproc_mpss: remoteproc@6 1017 remoteproc_mpss: remoteproc@6080000 {
1802 compatible = "qcom,qc 1018 compatible = "qcom,qcm2290-mpss-pas", "qcom,sm6115-mpss-pas";
1803 reg = <0x0 0x06080000 1019 reg = <0x0 0x06080000 0x0 0x100>;
1804 1020
1805 interrupts-extended = 1021 interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING>,
1806 1022 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1807 1023 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1808 1024 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1809 1025 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
1810 1026 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
1811 interrupt-names = "wd 1027 interrupt-names = "wdog",
1812 "fa 1028 "fatal",
1813 "re 1029 "ready",
1814 "ha 1030 "handover",
1815 "st 1031 "stop-ack",
1816 "sh 1032 "shutdown-ack";
1817 1033
1818 clocks = <&rpmcc RPM_ 1034 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
1819 clock-names = "xo"; 1035 clock-names = "xo";
1820 1036
1821 power-domains = <&rpm 1037 power-domains = <&rpmpd QCM2290_VDDCX>;
1822 1038
1823 memory-region = <&pil 1039 memory-region = <&pil_modem_mem>;
1824 1040
1825 qcom,smem-states = <& 1041 qcom,smem-states = <&modem_smp2p_out 0>;
1826 qcom,smem-state-names 1042 qcom,smem-state-names = "stop";
1827 1043
1828 status = "disabled"; 1044 status = "disabled";
1829 1045
1830 glink-edge { 1046 glink-edge {
1831 interrupts = 1047 interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>;
1832 label = "mpss 1048 label = "mpss";
1833 qcom,remote-p 1049 qcom,remote-pid = <1>;
1834 mboxes = <&ap 1050 mboxes = <&apcs_glb 12>;
1835 }; 1051 };
1836 }; 1052 };
1837 1053
1838 remoteproc_adsp: remoteproc@a 1054 remoteproc_adsp: remoteproc@ab00000 {
1839 compatible = "qcom,qc 1055 compatible = "qcom,qcm2290-adsp-pas", "qcom,sm6115-adsp-pas";
1840 reg = <0x0 0x0ab00000 1056 reg = <0x0 0x0ab00000 0x0 0x100>;
1841 1057
1842 interrupts-extended = 1058 interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_EDGE_RISING>,
1843 1059 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1844 1060 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1845 1061 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1846 1062 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1847 interrupt-names = "wd 1063 interrupt-names = "wdog",
1848 "fa 1064 "fatal",
1849 "re 1065 "ready",
1850 "ha 1066 "handover",
1851 "st 1067 "stop-ack";
1852 1068
1853 clocks = <&rpmcc RPM_ 1069 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
1854 clock-names = "xo"; 1070 clock-names = "xo";
1855 1071
1856 power-domains = <&rpm 1072 power-domains = <&rpmpd QCM2290_VDD_LPI_CX>,
1857 <&rpm 1073 <&rpmpd QCM2290_VDD_LPI_MX>;
1858 1074
1859 memory-region = <&pil 1075 memory-region = <&pil_adsp_mem>;
1860 1076
1861 qcom,smem-states = <& 1077 qcom,smem-states = <&adsp_smp2p_out 0>;
1862 qcom,smem-state-names 1078 qcom,smem-state-names = "stop";
1863 1079
1864 status = "disabled"; 1080 status = "disabled";
1865 1081
1866 glink-edge { 1082 glink-edge {
1867 interrupts = 1083 interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>;
1868 label = "lpas 1084 label = "lpass";
1869 qcom,remote-p 1085 qcom,remote-pid = <2>;
1870 mboxes = <&ap 1086 mboxes = <&apcs_glb 8>;
1871 }; 1087 };
1872 }; 1088 };
1873 1089
1874 apps_smmu: iommu@c600000 { 1090 apps_smmu: iommu@c600000 {
1875 compatible = "qcom,qc 1091 compatible = "qcom,qcm2290-smmu-500", "qcom,smmu-500", "arm,mmu-500";
1876 reg = <0x0 0x0c600000 1092 reg = <0x0 0x0c600000 0x0 0x80000>;
1877 #iommu-cells = <2>; 1093 #iommu-cells = <2>;
1878 #global-interrupts = 1094 #global-interrupts = <1>;
1879 1095
1880 interrupts = <GIC_SPI 1096 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
1881 <GIC_SPI 1097 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
1882 <GIC_SPI 1098 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1883 <GIC_SPI 1099 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
1884 <GIC_SPI 1100 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
1885 <GIC_SPI 1101 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
1886 <GIC_SPI 1102 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
1887 <GIC_SPI 1103 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
1888 <GIC_SPI 1104 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
1889 <GIC_SPI 1105 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
1890 <GIC_SPI 1106 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
1891 <GIC_SPI 1107 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
1892 <GIC_SPI 1108 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
1893 <GIC_SPI 1109 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
1894 <GIC_SPI 1110 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1895 <GIC_SPI 1111 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1896 <GIC_SPI 1112 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1897 <GIC_SPI 1113 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1898 <GIC_SPI 1114 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1899 <GIC_SPI 1115 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
1900 <GIC_SPI 1116 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1901 <GIC_SPI 1117 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
1902 <GIC_SPI 1118 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1903 <GIC_SPI 1119 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1904 <GIC_SPI 1120 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
1905 <GIC_SPI 1121 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
1906 <GIC_SPI 1122 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
1907 <GIC_SPI 1123 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
1908 <GIC_SPI 1124 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
1909 <GIC_SPI 1125 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
1910 <GIC_SPI 1126 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1911 <GIC_SPI 1127 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1912 <GIC_SPI 1128 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1913 <GIC_SPI 1129 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1914 <GIC_SPI 1130 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1915 <GIC_SPI 1131 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1916 <GIC_SPI 1132 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
1917 <GIC_SPI 1133 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1918 <GIC_SPI 1134 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1919 <GIC_SPI 1135 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1920 <GIC_SPI 1136 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
1921 <GIC_SPI 1137 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
1922 <GIC_SPI 1138 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
1923 <GIC_SPI 1139 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
1924 <GIC_SPI 1140 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
1925 <GIC_SPI 1141 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
1926 <GIC_SPI 1142 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
1927 <GIC_SPI 1143 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
1928 <GIC_SPI 1144 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
1929 <GIC_SPI 1145 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1930 <GIC_SPI 1146 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
1931 <GIC_SPI 1147 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
1932 <GIC_SPI 1148 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
1933 <GIC_SPI 1149 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
1934 <GIC_SPI 1150 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
1935 <GIC_SPI 1151 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
1936 <GIC_SPI 1152 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
1937 <GIC_SPI 1153 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
1938 <GIC_SPI 1154 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
1939 <GIC_SPI 1155 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1940 <GIC_SPI 1156 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1941 <GIC_SPI 1157 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
1942 <GIC_SPI 1158 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
1943 <GIC_SPI 1159 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
1944 <GIC_SPI 1160 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
1945 }; 1161 };
1946 1162
1947 wifi: wifi@c800000 { 1163 wifi: wifi@c800000 {
1948 compatible = "qcom,wc 1164 compatible = "qcom,wcn3990-wifi";
1949 reg = <0x0 0x0c800000 1165 reg = <0x0 0x0c800000 0x0 0x800000>;
1950 reg-names = "membase" 1166 reg-names = "membase";
1951 memory-region = <&wla 1167 memory-region = <&wlan_msa_mem>;
1952 interrupts = <GIC_SPI 1168 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
1953 <GIC_SPI 1169 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
1954 <GIC_SPI 1170 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
1955 <GIC_SPI 1171 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
1956 <GIC_SPI 1172 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
1957 <GIC_SPI 1173 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>,
1958 <GIC_SPI 1174 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
1959 <GIC_SPI 1175 <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,
1960 <GIC_SPI 1176 <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
1961 <GIC_SPI 1177 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
1962 <GIC_SPI 1178 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
1963 <GIC_SPI 1179 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
1964 iommus = <&apps_smmu 1180 iommus = <&apps_smmu 0x1a0 0x1>;
1965 qcom,msa-fixed-perm; 1181 qcom,msa-fixed-perm;
1966 status = "disabled"; 1182 status = "disabled";
1967 }; 1183 };
1968 1184
1969 watchdog@f017000 { 1185 watchdog@f017000 {
1970 compatible = "qcom,ap 1186 compatible = "qcom,apss-wdt-qcm2290", "qcom,kpss-wdt";
1971 reg = <0x0 0x0f017000 1187 reg = <0x0 0x0f017000 0x0 0x1000>;
1972 interrupts = <GIC_SPI 1188 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>,
1973 <GIC_SPI 1189 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1974 clocks = <&sleep_clk> 1190 clocks = <&sleep_clk>;
1975 }; 1191 };
1976 1192
1977 apcs_glb: mailbox@f111000 { 1193 apcs_glb: mailbox@f111000 {
1978 compatible = "qcom,qc 1194 compatible = "qcom,qcm2290-apcs-hmss-global";
1979 reg = <0x0 0x0f111000 1195 reg = <0x0 0x0f111000 0x0 0x1000>;
1980 #mbox-cells = <1>; 1196 #mbox-cells = <1>;
1981 }; 1197 };
1982 1198
1983 timer@f120000 { 1199 timer@f120000 {
1984 compatible = "arm,arm 1200 compatible = "arm,armv7-timer-mem";
1985 reg = <0x0 0x0f120000 1201 reg = <0x0 0x0f120000 0x0 0x1000>;
1986 #address-cells = <1>; 1202 #address-cells = <1>;
1987 #size-cells = <1>; 1203 #size-cells = <1>;
1988 ranges = <0 0x0 0x0f1 1204 ranges = <0 0x0 0x0f121000 0x8000>;
1989 1205
1990 frame@0 { 1206 frame@0 {
1991 reg = <0x0 0x 1207 reg = <0x0 0x1000>,
1992 <0x1000 1208 <0x1000 0x1000>;
1993 interrupts = 1209 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
1994 1210 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1995 frame-number 1211 frame-number = <0>;
1996 }; 1212 };
1997 1213
1998 frame@2000 { 1214 frame@2000 {
1999 reg = <0x2000 1215 reg = <0x2000 0x1000>;
2000 interrupts = 1216 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
2001 frame-number 1217 frame-number = <1>;
2002 status = "dis 1218 status = "disabled";
2003 }; 1219 };
2004 1220
2005 frame@3000 { 1221 frame@3000 {
2006 reg = <0x3000 1222 reg = <0x3000 0x1000>;
2007 interrupts = 1223 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
2008 frame-number 1224 frame-number = <2>;
2009 status = "dis 1225 status = "disabled";
2010 }; 1226 };
2011 1227
2012 frame@4000 { 1228 frame@4000 {
2013 reg = <0x4000 1229 reg = <0x4000 0x1000>;
2014 interrupts = 1230 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
2015 frame-number 1231 frame-number = <3>;
2016 status = "dis 1232 status = "disabled";
2017 }; 1233 };
2018 1234
2019 frame@5000 { 1235 frame@5000 {
2020 reg = <0x5000 1236 reg = <0x5000 0x1000>;
2021 interrupts = 1237 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
2022 frame-number 1238 frame-number = <4>;
2023 status = "dis 1239 status = "disabled";
2024 }; 1240 };
2025 1241
2026 frame@6000 { 1242 frame@6000 {
2027 reg = <0x6000 1243 reg = <0x6000 0x1000>;
2028 interrupts = 1244 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
2029 frame-number 1245 frame-number = <5>;
2030 status = "dis 1246 status = "disabled";
2031 }; 1247 };
2032 1248
2033 frame@7000 { 1249 frame@7000 {
2034 reg = <0x7000 1250 reg = <0x7000 0x1000>;
2035 interrupts = 1251 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
2036 frame-number 1252 frame-number = <6>;
2037 status = "dis 1253 status = "disabled";
2038 }; 1254 };
2039 }; 1255 };
2040 1256
2041 intc: interrupt-controller@f2 1257 intc: interrupt-controller@f200000 {
2042 compatible = "arm,gic 1258 compatible = "arm,gic-v3";
2043 reg = <0x0 0x0f200000 1259 reg = <0x0 0x0f200000 0x0 0x10000>,
2044 <0x0 0x0f300000 1260 <0x0 0x0f300000 0x0 0x100000>;
2045 interrupts = <GIC_PPI 1261 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
2046 #interrupt-cells = <3 1262 #interrupt-cells = <3>;
2047 interrupt-controller; 1263 interrupt-controller;
2048 interrupt-parent = <& 1264 interrupt-parent = <&intc>;
2049 #redistributor-region 1265 #redistributor-regions = <1>;
2050 redistributor-stride 1266 redistributor-stride = <0x0 0x20000>;
2051 }; 1267 };
2052 1268
2053 cpufreq_hw: cpufreq@f521000 { 1269 cpufreq_hw: cpufreq@f521000 {
2054 compatible = "qcom,qc 1270 compatible = "qcom,qcm2290-cpufreq-hw", "qcom,cpufreq-hw";
2055 reg = <0x0 0x0f521000 1271 reg = <0x0 0x0f521000 0x0 0x1000>;
2056 reg-names = "freq-dom 1272 reg-names = "freq-domain0";
2057 interrupts-extended = !! 1273 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
2058 interrupt-names = "dc 1274 interrupt-names = "dcvsh-irq-0";
2059 clocks = <&rpmcc RPM_ 1275 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>;
2060 clock-names = "xo", " 1276 clock-names = "xo", "alternate";
2061 1277
2062 #freq-domain-cells = 1278 #freq-domain-cells = <1>;
2063 #clock-cells = <1>; 1279 #clock-cells = <1>;
2064 }; 1280 };
2065 <<
2066 lmh_cluster: lmh@f550800 { <<
2067 compatible = "qcom,qc <<
2068 reg = <0x0 0x0f550800 <<
2069 interrupts = <GIC_SPI <<
2070 cpus = <&CPU0>; <<
2071 qcom,lmh-temp-arm-mil <<
2072 qcom,lmh-temp-low-mil <<
2073 qcom,lmh-temp-high-mi <<
2074 interrupt-controller; <<
2075 #interrupt-cells = <1 <<
2076 }; <<
2077 }; 1281 };
2078 1282
2079 thermal-zones { 1283 thermal-zones {
2080 mapss-thermal { 1284 mapss-thermal {
>> 1285 polling-delay-passive = <0>;
>> 1286 polling-delay = <0>;
>> 1287
2081 thermal-sensors = <&t 1288 thermal-sensors = <&tsens0 0>;
2082 1289
2083 trips { 1290 trips {
2084 mapss_alert0: 1291 mapss_alert0: trip-point0 {
2085 tempe 1292 temperature = <90000>;
2086 hyste 1293 hysteresis = <2000>;
2087 type 1294 type = "passive";
2088 }; 1295 };
2089 1296
2090 mapss_alert1: 1297 mapss_alert1: trip-point1 {
2091 tempe 1298 temperature = <95000>;
2092 hyste 1299 hysteresis = <2000>;
2093 type 1300 type = "passive";
2094 }; 1301 };
2095 1302
2096 mapss_crit: m 1303 mapss_crit: mapss-crit {
2097 tempe 1304 temperature = <110000>;
2098 hyste 1305 hysteresis = <1000>;
2099 type 1306 type = "critical";
2100 }; 1307 };
2101 }; 1308 };
2102 }; 1309 };
2103 1310
2104 video-thermal { 1311 video-thermal {
>> 1312 polling-delay-passive = <0>;
>> 1313 polling-delay = <0>;
>> 1314
2105 thermal-sensors = <&t 1315 thermal-sensors = <&tsens0 1>;
2106 1316
2107 trips { 1317 trips {
2108 video_alert0: 1318 video_alert0: trip-point0 {
2109 tempe 1319 temperature = <90000>;
2110 hyste 1320 hysteresis = <2000>;
2111 type 1321 type = "passive";
2112 }; 1322 };
2113 1323
2114 video_alert1: 1324 video_alert1: trip-point1 {
2115 tempe 1325 temperature = <95000>;
2116 hyste 1326 hysteresis = <2000>;
2117 type 1327 type = "passive";
2118 }; 1328 };
2119 1329
2120 video_crit: v 1330 video_crit: video-crit {
2121 tempe 1331 temperature = <110000>;
2122 hyste 1332 hysteresis = <1000>;
2123 type 1333 type = "critical";
2124 }; 1334 };
2125 }; 1335 };
2126 }; 1336 };
2127 1337
2128 wlan-thermal { 1338 wlan-thermal {
>> 1339 polling-delay-passive = <0>;
>> 1340 polling-delay = <0>;
>> 1341
2129 thermal-sensors = <&t 1342 thermal-sensors = <&tsens0 2>;
2130 1343
2131 trips { 1344 trips {
2132 wlan_alert0: 1345 wlan_alert0: trip-point0 {
2133 tempe 1346 temperature = <90000>;
2134 hyste 1347 hysteresis = <2000>;
2135 type 1348 type = "passive";
2136 }; 1349 };
2137 1350
2138 wlan_alert1: 1351 wlan_alert1: trip-point1 {
2139 tempe 1352 temperature = <95000>;
2140 hyste 1353 hysteresis = <2000>;
2141 type 1354 type = "passive";
2142 }; 1355 };
2143 1356
2144 wlan_crit: wl 1357 wlan_crit: wlan-crit {
2145 tempe 1358 temperature = <110000>;
2146 hyste 1359 hysteresis = <1000>;
2147 type 1360 type = "critical";
2148 }; 1361 };
2149 }; 1362 };
2150 }; 1363 };
2151 1364
2152 cpuss0-thermal { 1365 cpuss0-thermal {
>> 1366 polling-delay-passive = <0>;
>> 1367 polling-delay = <0>;
>> 1368
2153 thermal-sensors = <&t 1369 thermal-sensors = <&tsens0 3>;
2154 1370
2155 trips { 1371 trips {
2156 cpuss0_alert0 1372 cpuss0_alert0: trip-point0 {
2157 tempe 1373 temperature = <90000>;
2158 hyste 1374 hysteresis = <2000>;
2159 type 1375 type = "passive";
2160 }; 1376 };
2161 1377
2162 cpuss0_alert1 1378 cpuss0_alert1: trip-point1 {
2163 tempe 1379 temperature = <95000>;
2164 hyste 1380 hysteresis = <2000>;
2165 type 1381 type = "passive";
2166 }; 1382 };
2167 1383
2168 cpuss0_crit: 1384 cpuss0_crit: cpuss0-crit {
2169 tempe 1385 temperature = <110000>;
2170 hyste 1386 hysteresis = <1000>;
2171 type 1387 type = "critical";
2172 }; 1388 };
2173 }; 1389 };
2174 }; 1390 };
2175 1391
2176 cpuss1-thermal { 1392 cpuss1-thermal {
>> 1393 polling-delay-passive = <0>;
>> 1394 polling-delay = <0>;
>> 1395
2177 thermal-sensors = <&t 1396 thermal-sensors = <&tsens0 4>;
2178 1397
2179 trips { 1398 trips {
2180 cpuss1_alert0 1399 cpuss1_alert0: trip-point0 {
2181 tempe 1400 temperature = <90000>;
2182 hyste 1401 hysteresis = <2000>;
2183 type 1402 type = "passive";
2184 }; 1403 };
2185 1404
2186 cpuss1_alert1 1405 cpuss1_alert1: trip-point1 {
2187 tempe 1406 temperature = <95000>;
2188 hyste 1407 hysteresis = <2000>;
2189 type 1408 type = "passive";
2190 }; 1409 };
2191 1410
2192 cpuss1_crit: 1411 cpuss1_crit: cpuss1-crit {
2193 tempe 1412 temperature = <110000>;
2194 hyste 1413 hysteresis = <1000>;
2195 type 1414 type = "critical";
2196 }; 1415 };
2197 }; 1416 };
2198 }; 1417 };
2199 1418
2200 mdm0-thermal { 1419 mdm0-thermal {
>> 1420 polling-delay-passive = <0>;
>> 1421 polling-delay = <0>;
>> 1422
2201 thermal-sensors = <&t 1423 thermal-sensors = <&tsens0 5>;
2202 1424
2203 trips { 1425 trips {
2204 mdm0_alert0: 1426 mdm0_alert0: trip-point0 {
2205 tempe 1427 temperature = <90000>;
2206 hyste 1428 hysteresis = <2000>;
2207 type 1429 type = "passive";
2208 }; 1430 };
2209 1431
2210 mdm0_alert1: 1432 mdm0_alert1: trip-point1 {
2211 tempe 1433 temperature = <95000>;
2212 hyste 1434 hysteresis = <2000>;
2213 type 1435 type = "passive";
2214 }; 1436 };
2215 1437
2216 mdm0_crit: md 1438 mdm0_crit: mdm0-crit {
2217 tempe 1439 temperature = <110000>;
2218 hyste 1440 hysteresis = <1000>;
2219 type 1441 type = "critical";
2220 }; 1442 };
2221 }; 1443 };
2222 }; 1444 };
2223 1445
2224 mdm1-thermal { 1446 mdm1-thermal {
>> 1447 polling-delay-passive = <0>;
>> 1448 polling-delay = <0>;
>> 1449
2225 thermal-sensors = <&t 1450 thermal-sensors = <&tsens0 6>;
2226 1451
2227 trips { 1452 trips {
2228 mdm1_alert0: 1453 mdm1_alert0: trip-point0 {
2229 tempe 1454 temperature = <90000>;
2230 hyste 1455 hysteresis = <2000>;
2231 type 1456 type = "passive";
2232 }; 1457 };
2233 1458
2234 mdm1_alert1: 1459 mdm1_alert1: trip-point1 {
2235 tempe 1460 temperature = <95000>;
2236 hyste 1461 hysteresis = <2000>;
2237 type 1462 type = "passive";
2238 }; 1463 };
2239 1464
2240 mdm1_crit: md 1465 mdm1_crit: mdm1-crit {
2241 tempe 1466 temperature = <110000>;
2242 hyste 1467 hysteresis = <1000>;
2243 type 1468 type = "critical";
2244 }; 1469 };
2245 }; 1470 };
2246 }; 1471 };
2247 1472
2248 gpu-thermal { 1473 gpu-thermal {
>> 1474 polling-delay-passive = <0>;
>> 1475 polling-delay = <0>;
>> 1476
2249 thermal-sensors = <&t 1477 thermal-sensors = <&tsens0 7>;
2250 1478
2251 trips { 1479 trips {
2252 gpu_alert0: t 1480 gpu_alert0: trip-point0 {
2253 tempe 1481 temperature = <90000>;
2254 hyste 1482 hysteresis = <2000>;
2255 type 1483 type = "passive";
2256 }; 1484 };
2257 1485
2258 gpu_alert1: t 1486 gpu_alert1: trip-point1 {
2259 tempe 1487 temperature = <95000>;
2260 hyste 1488 hysteresis = <2000>;
2261 type 1489 type = "passive";
2262 }; 1490 };
2263 1491
2264 gpu_crit: gpu 1492 gpu_crit: gpu-crit {
2265 tempe 1493 temperature = <110000>;
2266 hyste 1494 hysteresis = <1000>;
2267 type 1495 type = "critical";
2268 }; 1496 };
2269 }; 1497 };
2270 }; 1498 };
2271 1499
2272 hm-center-thermal { 1500 hm-center-thermal {
>> 1501 polling-delay-passive = <0>;
>> 1502 polling-delay = <0>;
>> 1503
2273 thermal-sensors = <&t 1504 thermal-sensors = <&tsens0 8>;
2274 1505
2275 trips { 1506 trips {
2276 hm_center_ale 1507 hm_center_alert0: trip-point0 {
2277 tempe 1508 temperature = <90000>;
2278 hyste 1509 hysteresis = <2000>;
2279 type 1510 type = "passive";
2280 }; 1511 };
2281 1512
2282 hm_center_ale 1513 hm_center_alert1: trip-point1 {
2283 tempe 1514 temperature = <95000>;
2284 hyste 1515 hysteresis = <2000>;
2285 type 1516 type = "passive";
2286 }; 1517 };
2287 1518
2288 hm_center_cri 1519 hm_center_crit: hm-center-crit {
2289 tempe 1520 temperature = <110000>;
2290 hyste 1521 hysteresis = <1000>;
2291 type 1522 type = "critical";
2292 }; 1523 };
2293 }; 1524 };
2294 }; 1525 };
2295 1526
2296 camera-thermal { 1527 camera-thermal {
>> 1528 polling-delay-passive = <0>;
>> 1529 polling-delay = <0>;
>> 1530
2297 thermal-sensors = <&t 1531 thermal-sensors = <&tsens0 9>;
2298 1532
2299 trips { 1533 trips {
2300 camera_alert0 1534 camera_alert0: trip-point0 {
2301 tempe 1535 temperature = <90000>;
2302 hyste 1536 hysteresis = <2000>;
2303 type 1537 type = "passive";
2304 }; 1538 };
2305 1539
2306 camera_alert1 1540 camera_alert1: trip-point1 {
2307 tempe 1541 temperature = <95000>;
2308 hyste 1542 hysteresis = <2000>;
2309 type 1543 type = "passive";
2310 }; 1544 };
2311 1545
2312 camera_crit: 1546 camera_crit: camera-crit {
2313 tempe 1547 temperature = <110000>;
2314 hyste 1548 hysteresis = <1000>;
2315 type 1549 type = "critical";
2316 }; 1550 };
2317 }; 1551 };
2318 }; 1552 };
2319 }; 1553 };
2320 1554
2321 timer { 1555 timer {
2322 compatible = "arm,armv8-timer 1556 compatible = "arm,armv8-timer";
2323 interrupts = <GIC_PPI 1 (GIC_ 1557 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2324 <GIC_PPI 2 (GIC_ 1558 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2325 <GIC_PPI 3 (GIC_ 1559 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2326 <GIC_PPI 0 (GIC_ 1560 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
2327 }; 1561 };
2328 }; 1562 };
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