1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3 1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2 /* 2 /*
3 * Copyright (c) 2023, Linaro Ltd 3 * Copyright (c) 2023, Linaro Ltd
4 * 4 *
5 * Based on sm6115.dtsi and previous efforts b 5 * Based on sm6115.dtsi and previous efforts by Shawn Guo & Loic Poulain.
6 */ 6 */
7 7
8 #include <dt-bindings/clock/qcom,dispcc-qcm229 <<
9 #include <dt-bindings/clock/qcom,gcc-qcm2290.h 8 #include <dt-bindings/clock/qcom,gcc-qcm2290.h>
10 #include <dt-bindings/clock/qcom,qcm2290-gpucc <<
11 #include <dt-bindings/clock/qcom,rpmcc.h> 9 #include <dt-bindings/clock/qcom,rpmcc.h>
12 #include <dt-bindings/dma/qcom-gpi.h> 10 #include <dt-bindings/dma/qcom-gpi.h>
13 #include <dt-bindings/firmware/qcom,scm.h> 11 #include <dt-bindings/firmware/qcom,scm.h>
14 #include <dt-bindings/gpio/gpio.h> 12 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/interrupt-controller/arm 13 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/interconnect/qcom,qcm229 <<
17 #include <dt-bindings/interconnect/qcom,rpm-ic <<
18 #include <dt-bindings/power/qcom-rpmpd.h> 14 #include <dt-bindings/power/qcom-rpmpd.h>
19 15
20 / { 16 / {
21 interrupt-parent = <&intc>; 17 interrupt-parent = <&intc>;
22 18
23 #address-cells = <2>; 19 #address-cells = <2>;
24 #size-cells = <2>; 20 #size-cells = <2>;
25 21
26 chosen { }; 22 chosen { };
27 23
28 clocks { 24 clocks {
29 xo_board: xo-board { 25 xo_board: xo-board {
30 compatible = "fixed-cl 26 compatible = "fixed-clock";
31 #clock-cells = <0>; 27 #clock-cells = <0>;
32 }; 28 };
33 29
34 sleep_clk: sleep-clk { 30 sleep_clk: sleep-clk {
35 compatible = "fixed-cl 31 compatible = "fixed-clock";
36 clock-frequency = <327 32 clock-frequency = <32764>;
37 #clock-cells = <0>; 33 #clock-cells = <0>;
38 }; 34 };
39 }; 35 };
40 36
41 cpus { 37 cpus {
42 #address-cells = <2>; 38 #address-cells = <2>;
43 #size-cells = <0>; 39 #size-cells = <0>;
44 40
45 CPU0: cpu@0 { 41 CPU0: cpu@0 {
46 device_type = "cpu"; 42 device_type = "cpu";
47 compatible = "arm,cort 43 compatible = "arm,cortex-a53";
48 reg = <0x0 0x0>; 44 reg = <0x0 0x0>;
49 clocks = <&cpufreq_hw 45 clocks = <&cpufreq_hw 0>;
50 capacity-dmips-mhz = < 46 capacity-dmips-mhz = <1024>;
51 dynamic-power-coeffici 47 dynamic-power-coefficient = <100>;
52 enable-method = "psci" 48 enable-method = "psci";
53 next-level-cache = <&L 49 next-level-cache = <&L2_0>;
54 qcom,freq-domain = <&c 50 qcom,freq-domain = <&cpufreq_hw 0>;
55 power-domains = <&CPU_ 51 power-domains = <&CPU_PD0>;
56 power-domain-names = " 52 power-domain-names = "psci";
57 L2_0: l2-cache { 53 L2_0: l2-cache {
58 compatible = " 54 compatible = "cache";
59 cache-level = 55 cache-level = <2>;
60 cache-unified; 56 cache-unified;
61 }; 57 };
62 }; 58 };
63 59
64 CPU1: cpu@1 { 60 CPU1: cpu@1 {
65 device_type = "cpu"; 61 device_type = "cpu";
66 compatible = "arm,cort 62 compatible = "arm,cortex-a53";
67 reg = <0x0 0x1>; 63 reg = <0x0 0x1>;
68 clocks = <&cpufreq_hw 64 clocks = <&cpufreq_hw 0>;
69 capacity-dmips-mhz = < 65 capacity-dmips-mhz = <1024>;
70 dynamic-power-coeffici 66 dynamic-power-coefficient = <100>;
71 enable-method = "psci" 67 enable-method = "psci";
72 next-level-cache = <&L 68 next-level-cache = <&L2_0>;
73 qcom,freq-domain = <&c 69 qcom,freq-domain = <&cpufreq_hw 0>;
74 power-domains = <&CPU_ 70 power-domains = <&CPU_PD1>;
75 power-domain-names = " 71 power-domain-names = "psci";
76 }; 72 };
77 73
78 CPU2: cpu@2 { 74 CPU2: cpu@2 {
79 device_type = "cpu"; 75 device_type = "cpu";
80 compatible = "arm,cort 76 compatible = "arm,cortex-a53";
81 reg = <0x0 0x2>; 77 reg = <0x0 0x2>;
82 clocks = <&cpufreq_hw 78 clocks = <&cpufreq_hw 0>;
83 capacity-dmips-mhz = < 79 capacity-dmips-mhz = <1024>;
84 dynamic-power-coeffici 80 dynamic-power-coefficient = <100>;
85 enable-method = "psci" 81 enable-method = "psci";
86 next-level-cache = <&L 82 next-level-cache = <&L2_0>;
87 qcom,freq-domain = <&c 83 qcom,freq-domain = <&cpufreq_hw 0>;
88 power-domains = <&CPU_ 84 power-domains = <&CPU_PD2>;
89 power-domain-names = " 85 power-domain-names = "psci";
90 }; 86 };
91 87
92 CPU3: cpu@3 { 88 CPU3: cpu@3 {
93 device_type = "cpu"; 89 device_type = "cpu";
94 compatible = "arm,cort 90 compatible = "arm,cortex-a53";
95 reg = <0x0 0x3>; 91 reg = <0x0 0x3>;
96 clocks = <&cpufreq_hw 92 clocks = <&cpufreq_hw 0>;
97 capacity-dmips-mhz = < 93 capacity-dmips-mhz = <1024>;
98 dynamic-power-coeffici 94 dynamic-power-coefficient = <100>;
99 enable-method = "psci" 95 enable-method = "psci";
100 next-level-cache = <&L 96 next-level-cache = <&L2_0>;
101 qcom,freq-domain = <&c 97 qcom,freq-domain = <&cpufreq_hw 0>;
102 power-domains = <&CPU_ 98 power-domains = <&CPU_PD3>;
103 power-domain-names = " 99 power-domain-names = "psci";
104 }; 100 };
105 101
106 cpu-map { 102 cpu-map {
107 cluster0 { 103 cluster0 {
108 core0 { 104 core0 {
109 cpu = 105 cpu = <&CPU0>;
110 }; 106 };
111 107
112 core1 { 108 core1 {
113 cpu = 109 cpu = <&CPU1>;
114 }; 110 };
115 111
116 core2 { 112 core2 {
117 cpu = 113 cpu = <&CPU2>;
118 }; 114 };
119 115
120 core3 { 116 core3 {
121 cpu = 117 cpu = <&CPU3>;
122 }; 118 };
123 }; 119 };
124 }; 120 };
125 121
126 domain-idle-states { 122 domain-idle-states {
127 CLUSTER_SLEEP: cluster 123 CLUSTER_SLEEP: cluster-sleep-0 {
128 compatible = " 124 compatible = "domain-idle-state";
129 arm,psci-suspe 125 arm,psci-suspend-param = <0x41000043>;
130 entry-latency- 126 entry-latency-us = <800>;
131 exit-latency-u 127 exit-latency-us = <2118>;
132 min-residency- 128 min-residency-us = <7376>;
133 }; 129 };
134 }; 130 };
135 131
136 idle-states { 132 idle-states {
137 entry-method = "psci"; 133 entry-method = "psci";
138 134
139 CPU_SLEEP: cpu-sleep-0 135 CPU_SLEEP: cpu-sleep-0 {
140 compatible = " 136 compatible = "arm,idle-state";
141 idle-state-nam 137 idle-state-name = "power-collapse";
142 arm,psci-suspe 138 arm,psci-suspend-param = <0x40000003>;
143 entry-latency- 139 entry-latency-us = <290>;
144 exit-latency-u 140 exit-latency-us = <376>;
145 min-residency- 141 min-residency-us = <1182>;
146 local-timer-st 142 local-timer-stop;
147 }; 143 };
148 }; 144 };
149 }; 145 };
150 146
151 firmware { 147 firmware {
152 scm: scm { 148 scm: scm {
153 compatible = "qcom,scm 149 compatible = "qcom,scm-qcm2290", "qcom,scm";
154 clocks = <&rpmcc RPM_S 150 clocks = <&rpmcc RPM_SMD_CE1_CLK>;
155 clock-names = "core"; 151 clock-names = "core";
156 #reset-cells = <1>; 152 #reset-cells = <1>;
157 interconnects = <&syst <<
158 &bimc <<
159 }; 153 };
160 }; 154 };
161 155
162 memory@40000000 { 156 memory@40000000 {
163 device_type = "memory"; 157 device_type = "memory";
164 /* We expect the bootloader to 158 /* We expect the bootloader to fill in the size */
165 reg = <0 0x40000000 0 0>; 159 reg = <0 0x40000000 0 0>;
166 }; 160 };
167 161
168 pmu { 162 pmu {
169 compatible = "arm,cortex-a53-p !! 163 compatible = "arm,armv8-pmuv3";
170 interrupts = <GIC_PPI 6 IRQ_TY 164 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>;
171 }; 165 };
172 166
173 psci { 167 psci {
174 compatible = "arm,psci-1.0"; 168 compatible = "arm,psci-1.0";
175 method = "smc"; 169 method = "smc";
176 170
177 CPU_PD0: power-domain-cpu0 { 171 CPU_PD0: power-domain-cpu0 {
178 #power-domain-cells = 172 #power-domain-cells = <0>;
179 power-domains = <&CLUS 173 power-domains = <&CLUSTER_PD>;
180 domain-idle-states = < 174 domain-idle-states = <&CPU_SLEEP>;
181 }; 175 };
182 176
183 CPU_PD1: power-domain-cpu1 { 177 CPU_PD1: power-domain-cpu1 {
184 #power-domain-cells = 178 #power-domain-cells = <0>;
185 power-domains = <&CLUS 179 power-domains = <&CLUSTER_PD>;
186 domain-idle-states = < 180 domain-idle-states = <&CPU_SLEEP>;
187 }; 181 };
188 182
189 CPU_PD2: power-domain-cpu2 { 183 CPU_PD2: power-domain-cpu2 {
190 #power-domain-cells = 184 #power-domain-cells = <0>;
191 power-domains = <&CLUS 185 power-domains = <&CLUSTER_PD>;
192 domain-idle-states = < 186 domain-idle-states = <&CPU_SLEEP>;
193 }; 187 };
194 188
195 CPU_PD3: power-domain-cpu3 { 189 CPU_PD3: power-domain-cpu3 {
196 #power-domain-cells = 190 #power-domain-cells = <0>;
197 power-domains = <&CLUS 191 power-domains = <&CLUSTER_PD>;
198 domain-idle-states = < 192 domain-idle-states = <&CPU_SLEEP>;
199 }; 193 };
200 194
201 CLUSTER_PD: power-domain-cpu-c 195 CLUSTER_PD: power-domain-cpu-cluster {
202 #power-domain-cells = 196 #power-domain-cells = <0>;
203 power-domains = <&mpm> <<
204 domain-idle-states = < 197 domain-idle-states = <&CLUSTER_SLEEP>;
205 }; 198 };
206 }; 199 };
207 200
208 rpm: remoteproc { 201 rpm: remoteproc {
209 compatible = "qcom,qcm2290-rpm 202 compatible = "qcom,qcm2290-rpm-proc", "qcom,rpm-proc";
210 203
211 glink-edge { 204 glink-edge {
212 compatible = "qcom,gli 205 compatible = "qcom,glink-rpm";
213 interrupts = <GIC_SPI 206 interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>;
214 qcom,rpm-msg-ram = <&r 207 qcom,rpm-msg-ram = <&rpm_msg_ram>;
215 mboxes = <&apcs_glb 0> 208 mboxes = <&apcs_glb 0>;
216 209
217 rpm_requests: rpm-requ 210 rpm_requests: rpm-requests {
218 compatible = " !! 211 compatible = "qcom,rpm-qcm2290";
219 qcom,glink-cha 212 qcom,glink-channels = "rpm_requests";
220 213
221 rpmcc: clock-c 214 rpmcc: clock-controller {
222 compat 215 compatible = "qcom,rpmcc-qcm2290", "qcom,rpmcc";
223 clocks 216 clocks = <&xo_board>;
224 clock- 217 clock-names = "xo";
225 #clock 218 #clock-cells = <1>;
226 }; 219 };
227 220
228 rpmpd: power-c 221 rpmpd: power-controller {
229 compat 222 compatible = "qcom,qcm2290-rpmpd";
230 #power 223 #power-domain-cells = <1>;
231 operat 224 operating-points-v2 = <&rpmpd_opp_table>;
232 225
233 rpmpd_ 226 rpmpd_opp_table: opp-table {
234 227 compatible = "operating-points-v2";
235 228
236 229 rpmpd_opp_min_svs: opp1 {
237 230 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
238 231 };
239 232
240 233 rpmpd_opp_low_svs: opp2 {
241 234 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
242 235 };
243 236
244 237 rpmpd_opp_svs: opp3 {
245 238 opp-level = <RPM_SMD_LEVEL_SVS>;
246 239 };
247 240
248 241 rpmpd_opp_svs_plus: opp4 {
249 242 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
250 243 };
251 244
252 245 rpmpd_opp_nom: opp5 {
253 246 opp-level = <RPM_SMD_LEVEL_NOM>;
254 247 };
255 248
256 249 rpmpd_opp_nom_plus: opp6 {
257 250 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
258 251 };
259 252
260 253 rpmpd_opp_turbo: opp7 {
261 254 opp-level = <RPM_SMD_LEVEL_TURBO>;
262 255 };
263 256
264 257 rpmpd_opp_turbo_plus: opp8 {
265 258 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>;
266 259 };
267 }; 260 };
268 }; 261 };
269 }; 262 };
270 }; 263 };
271 <<
272 mpm: interrupt-controller { <<
273 compatible = "qcom,mpm <<
274 qcom,rpm-msg-ram = <&a <<
275 interrupts = <GIC_SPI <<
276 mboxes = <&apcs_glb 1> <<
277 interrupt-controller; <<
278 #interrupt-cells = <2> <<
279 #power-domain-cells = <<
280 interrupt-parent = <&i <<
281 qcom,mpm-pin-count = < <<
282 qcom,mpm-pin-map = <2 <<
283 <5 <<
284 <12 <<
285 <24 <<
286 <86 <<
287 <90 <<
288 }; <<
289 }; 264 };
290 265
291 reserved_memory: reserved-memory { 266 reserved_memory: reserved-memory {
292 #address-cells = <2>; 267 #address-cells = <2>;
293 #size-cells = <2>; 268 #size-cells = <2>;
294 ranges; 269 ranges;
295 270
296 hyp_mem: hyp@45700000 { 271 hyp_mem: hyp@45700000 {
297 reg = <0x0 0x45700000 272 reg = <0x0 0x45700000 0x0 0x600000>;
298 no-map; 273 no-map;
299 }; 274 };
300 275
301 xbl_aop_mem: xbl-aop@45e00000 276 xbl_aop_mem: xbl-aop@45e00000 {
302 reg = <0x0 0x45e00000 277 reg = <0x0 0x45e00000 0x0 0x140000>;
303 no-map; 278 no-map;
304 }; 279 };
305 280
306 sec_apps_mem: sec-apps@45fff00 281 sec_apps_mem: sec-apps@45fff000 {
307 reg = <0x0 0x45fff000 282 reg = <0x0 0x45fff000 0x0 0x1000>;
308 no-map; 283 no-map;
309 }; 284 };
310 285
311 smem_mem: smem@46000000 { 286 smem_mem: smem@46000000 {
312 compatible = "qcom,sme 287 compatible = "qcom,smem";
313 reg = <0x0 0x46000000 288 reg = <0x0 0x46000000 0x0 0x200000>;
314 no-map; 289 no-map;
315 290
316 hwlocks = <&tcsr_mutex 291 hwlocks = <&tcsr_mutex 3>;
317 qcom,rpm-msg-ram = <&r 292 qcom,rpm-msg-ram = <&rpm_msg_ram>;
318 }; 293 };
319 294
320 pil_modem_mem: modem@4ab00000 295 pil_modem_mem: modem@4ab00000 {
321 reg = <0x0 0x4ab00000 296 reg = <0x0 0x4ab00000 0x0 0x6900000>;
322 no-map; 297 no-map;
323 }; 298 };
324 299
325 pil_video_mem: video@51400000 300 pil_video_mem: video@51400000 {
326 reg = <0x0 0x51400000 301 reg = <0x0 0x51400000 0x0 0x500000>;
327 no-map; 302 no-map;
328 }; 303 };
329 304
330 wlan_msa_mem: wlan-msa@5190000 305 wlan_msa_mem: wlan-msa@51900000 {
331 reg = <0x0 0x51900000 306 reg = <0x0 0x51900000 0x0 0x100000>;
332 no-map; 307 no-map;
333 }; 308 };
334 309
335 pil_adsp_mem: adsp@51a00000 { 310 pil_adsp_mem: adsp@51a00000 {
336 reg = <0x0 0x51a00000 311 reg = <0x0 0x51a00000 0x0 0x1c00000>;
337 no-map; 312 no-map;
338 }; 313 };
339 314
340 pil_ipa_fw_mem: ipa-fw@5360000 315 pil_ipa_fw_mem: ipa-fw@53600000 {
341 reg = <0x0 0x53600000 316 reg = <0x0 0x53600000 0x0 0x10000>;
342 no-map; 317 no-map;
343 }; 318 };
344 319
345 pil_ipa_gsi_mem: ipa-gsi@53610 320 pil_ipa_gsi_mem: ipa-gsi@53610000 {
346 reg = <0x0 0x53610000 321 reg = <0x0 0x53610000 0x0 0x5000>;
347 no-map; 322 no-map;
348 }; 323 };
349 324
350 pil_gpu_mem: zap@53615000 { 325 pil_gpu_mem: zap@53615000 {
351 compatible = "shared-d 326 compatible = "shared-dma-pool";
352 reg = <0x0 0x53615000 327 reg = <0x0 0x53615000 0x0 0x2000>;
353 no-map; 328 no-map;
354 }; 329 };
355 330
356 cont_splash_memory: framebuffe 331 cont_splash_memory: framebuffer@5c000000 {
357 reg = <0x0 0x5c000000 332 reg = <0x0 0x5c000000 0x0 0x00f00000>;
358 no-map; 333 no-map;
359 }; 334 };
360 335
361 dfps_data_memory: dpfs-data@5c 336 dfps_data_memory: dpfs-data@5cf00000 {
362 reg = <0x0 0x5cf00000 337 reg = <0x0 0x5cf00000 0x0 0x0100000>;
363 no-map; 338 no-map;
364 }; 339 };
365 340
366 removed_mem: reserved@60000000 341 removed_mem: reserved@60000000 {
367 reg = <0x0 0x60000000 342 reg = <0x0 0x60000000 0x0 0x3900000>;
368 no-map; 343 no-map;
369 }; 344 };
370 345
371 rmtfs_mem: memory@89b01000 { 346 rmtfs_mem: memory@89b01000 {
372 compatible = "qcom,rmt 347 compatible = "qcom,rmtfs-mem";
373 reg = <0x0 0x89b01000 348 reg = <0x0 0x89b01000 0x0 0x200000>;
374 no-map; 349 no-map;
375 350
376 qcom,client-id = <1>; 351 qcom,client-id = <1>;
377 qcom,vmid = <QCOM_SCM_ 352 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA QCOM_SCM_VMID_NAV>;
378 }; 353 };
379 }; 354 };
380 355
381 smp2p-adsp { 356 smp2p-adsp {
382 compatible = "qcom,smp2p"; 357 compatible = "qcom,smp2p";
383 qcom,smem = <443>, <429>; 358 qcom,smem = <443>, <429>;
384 359
385 interrupts = <GIC_SPI 279 IRQ_ 360 interrupts = <GIC_SPI 279 IRQ_TYPE_EDGE_RISING>;
386 361
387 mboxes = <&apcs_glb 10>; 362 mboxes = <&apcs_glb 10>;
388 363
389 qcom,local-pid = <0>; 364 qcom,local-pid = <0>;
390 qcom,remote-pid = <2>; 365 qcom,remote-pid = <2>;
391 366
392 adsp_smp2p_out: master-kernel 367 adsp_smp2p_out: master-kernel {
393 qcom,entry-name = "mas 368 qcom,entry-name = "master-kernel";
394 #qcom,smem-state-cells 369 #qcom,smem-state-cells = <1>;
395 }; 370 };
396 371
397 adsp_smp2p_in: slave-kernel { 372 adsp_smp2p_in: slave-kernel {
398 qcom,entry-name = "sla 373 qcom,entry-name = "slave-kernel";
399 interrupt-controller; 374 interrupt-controller;
400 #interrupt-cells = <2> 375 #interrupt-cells = <2>;
401 }; 376 };
402 }; 377 };
403 378
404 smp2p-mpss { 379 smp2p-mpss {
405 compatible = "qcom,smp2p"; 380 compatible = "qcom,smp2p";
406 qcom,smem = <435>, <428>; 381 qcom,smem = <435>, <428>;
407 382
408 interrupts = <GIC_SPI 70 IRQ_T 383 interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>;
409 384
410 mboxes = <&apcs_glb 14>; 385 mboxes = <&apcs_glb 14>;
411 386
412 qcom,local-pid = <0>; 387 qcom,local-pid = <0>;
413 qcom,remote-pid = <1>; 388 qcom,remote-pid = <1>;
414 389
415 modem_smp2p_out: master-kernel 390 modem_smp2p_out: master-kernel {
416 qcom,entry-name = "mas 391 qcom,entry-name = "master-kernel";
417 #qcom,smem-state-cells 392 #qcom,smem-state-cells = <1>;
418 }; 393 };
419 394
420 modem_smp2p_in: slave-kernel { 395 modem_smp2p_in: slave-kernel {
421 qcom,entry-name = "sla 396 qcom,entry-name = "slave-kernel";
422 interrupt-controller; 397 interrupt-controller;
423 #interrupt-cells = <2> 398 #interrupt-cells = <2>;
424 }; 399 };
425 400
426 wlan_smp2p_in: wlan-wpss-to-ap 401 wlan_smp2p_in: wlan-wpss-to-ap {
427 qcom,entry-name = "wla 402 qcom,entry-name = "wlan";
428 interrupt-controller; 403 interrupt-controller;
429 #interrupt-cells = <2> 404 #interrupt-cells = <2>;
430 }; 405 };
431 }; 406 };
432 407
433 soc: soc@0 { 408 soc: soc@0 {
434 compatible = "simple-bus"; 409 compatible = "simple-bus";
435 #address-cells = <2>; 410 #address-cells = <2>;
436 #size-cells = <2>; 411 #size-cells = <2>;
437 ranges = <0 0 0 0 0x10 0>; 412 ranges = <0 0 0 0 0x10 0>;
438 dma-ranges = <0 0 0 0 0x10 0>; 413 dma-ranges = <0 0 0 0 0x10 0>;
439 414
440 tcsr_mutex: hwlock@340000 { 415 tcsr_mutex: hwlock@340000 {
441 compatible = "qcom,tcs 416 compatible = "qcom,tcsr-mutex";
442 reg = <0x0 0x00340000 417 reg = <0x0 0x00340000 0x0 0x20000>;
443 #hwlock-cells = <1>; 418 #hwlock-cells = <1>;
444 }; 419 };
445 420
446 tcsr_regs: syscon@3c0000 { 421 tcsr_regs: syscon@3c0000 {
447 compatible = "qcom,qcm 422 compatible = "qcom,qcm2290-tcsr", "syscon";
448 reg = <0x0 0x003c0000 423 reg = <0x0 0x003c0000 0x0 0x40000>;
449 }; 424 };
450 425
451 tlmm: pinctrl@500000 { 426 tlmm: pinctrl@500000 {
452 compatible = "qcom,qcm 427 compatible = "qcom,qcm2290-tlmm";
453 reg = <0x0 0x00500000 428 reg = <0x0 0x00500000 0x0 0x300000>;
454 interrupts = <GIC_SPI 429 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
455 gpio-controller; 430 gpio-controller;
456 gpio-ranges = <&tlmm 0 431 gpio-ranges = <&tlmm 0 0 127>;
457 wakeup-parent = <&mpm> <<
458 #gpio-cells = <2>; 432 #gpio-cells = <2>;
459 interrupt-controller; 433 interrupt-controller;
460 #interrupt-cells = <2> 434 #interrupt-cells = <2>;
461 435
462 qup_i2c0_default: qup- 436 qup_i2c0_default: qup-i2c0-default-state {
463 pins = "gpio0" 437 pins = "gpio0", "gpio1";
464 function = "qu 438 function = "qup0";
465 drive-strength 439 drive-strength = <2>;
466 bias-pull-up; 440 bias-pull-up;
467 }; 441 };
468 442
469 qup_i2c1_default: qup- 443 qup_i2c1_default: qup-i2c1-default-state {
470 pins = "gpio4" 444 pins = "gpio4", "gpio5";
471 function = "qu 445 function = "qup1";
472 drive-strength 446 drive-strength = <2>;
473 bias-pull-up; 447 bias-pull-up;
474 }; 448 };
475 449
476 qup_i2c2_default: qup- 450 qup_i2c2_default: qup-i2c2-default-state {
477 pins = "gpio6" 451 pins = "gpio6", "gpio7";
478 function = "qu 452 function = "qup2";
479 drive-strength 453 drive-strength = <2>;
480 bias-pull-up; 454 bias-pull-up;
481 }; 455 };
482 456
483 qup_i2c3_default: qup- 457 qup_i2c3_default: qup-i2c3-default-state {
484 pins = "gpio8" 458 pins = "gpio8", "gpio9";
485 function = "qu 459 function = "qup3";
486 drive-strength 460 drive-strength = <2>;
487 bias-pull-up; 461 bias-pull-up;
488 }; 462 };
489 463
490 qup_i2c4_default: qup- 464 qup_i2c4_default: qup-i2c4-default-state {
491 pins = "gpio12 465 pins = "gpio12", "gpio13";
492 function = "qu 466 function = "qup4";
493 drive-strength 467 drive-strength = <2>;
494 bias-pull-up; 468 bias-pull-up;
495 }; 469 };
496 470
497 qup_i2c5_default: qup- 471 qup_i2c5_default: qup-i2c5-default-state {
498 pins = "gpio14 472 pins = "gpio14", "gpio15";
499 function = "qu 473 function = "qup5";
500 drive-strength 474 drive-strength = <2>;
501 bias-pull-up; 475 bias-pull-up;
502 }; 476 };
503 477
504 qup_spi0_default: qup- 478 qup_spi0_default: qup-spi0-default-state {
505 pins = "gpio0" 479 pins = "gpio0", "gpio1","gpio2", "gpio3";
506 function = "qu 480 function = "qup0";
507 drive-strength 481 drive-strength = <2>;
508 bias-pull-up; 482 bias-pull-up;
509 }; 483 };
510 484
511 qup_spi1_default: qup- 485 qup_spi1_default: qup-spi1-default-state {
512 pins = "gpio4" 486 pins = "gpio4", "gpio5", "gpio69", "gpio70";
513 function = "qu 487 function = "qup1";
514 drive-strength 488 drive-strength = <2>;
515 bias-pull-up; 489 bias-pull-up;
516 }; 490 };
517 491
518 qup_spi2_default: qup- 492 qup_spi2_default: qup-spi2-default-state {
519 pins = "gpio6" 493 pins = "gpio6", "gpio7", "gpio71", "gpio80";
520 function = "qu 494 function = "qup2";
521 drive-strength 495 drive-strength = <2>;
522 bias-pull-up; 496 bias-pull-up;
523 }; 497 };
524 498
525 qup_spi3_default: qup- 499 qup_spi3_default: qup-spi3-default-state {
526 pins = "gpio8" 500 pins = "gpio8", "gpio9", "gpio10", "gpio11";
527 function = "qu 501 function = "qup3";
528 drive-strength 502 drive-strength = <2>;
529 bias-pull-up; 503 bias-pull-up;
530 }; 504 };
531 505
532 qup_spi4_default: qup- 506 qup_spi4_default: qup-spi4-default-state {
533 pins = "gpio12 507 pins = "gpio12", "gpio13", "gpio96", "gpio97";
534 function = "qu 508 function = "qup4";
535 drive-strength 509 drive-strength = <2>;
536 bias-pull-up; 510 bias-pull-up;
537 }; 511 };
538 512
539 qup_spi5_default: qup- 513 qup_spi5_default: qup-spi5-default-state {
540 pins = "gpio14 514 pins = "gpio14", "gpio15", "gpio16", "gpio17";
541 function = "qu 515 function = "qup5";
542 drive-strength 516 drive-strength = <2>;
543 bias-pull-up; 517 bias-pull-up;
544 }; 518 };
545 519
546 qup_uart0_default: qup 520 qup_uart0_default: qup-uart0-default-state {
547 pins = "gpio0" 521 pins = "gpio0", "gpio1", "gpio2", "gpio3";
548 function = "qu 522 function = "qup0";
549 drive-strength 523 drive-strength = <2>;
550 bias-disable; 524 bias-disable;
551 }; 525 };
552 526
553 qup_uart4_default: qup 527 qup_uart4_default: qup-uart4-default-state {
554 pins = "gpio12 528 pins = "gpio12", "gpio13";
555 function = "qu 529 function = "qup4";
556 drive-strength 530 drive-strength = <2>;
557 bias-disable; 531 bias-disable;
558 }; 532 };
559 533
560 sdc1_state_on: sdc1-on 534 sdc1_state_on: sdc1-on-state {
561 clk-pins { 535 clk-pins {
562 pins = 536 pins = "sdc1_clk";
563 drive- 537 drive-strength = <16>;
564 bias-d 538 bias-disable;
565 }; 539 };
566 540
567 cmd-pins { 541 cmd-pins {
568 pins = 542 pins = "sdc1_cmd";
569 drive- 543 drive-strength = <10>;
570 bias-p 544 bias-pull-up;
571 }; 545 };
572 546
573 data-pins { 547 data-pins {
574 pins = 548 pins = "sdc1_data";
575 drive- 549 drive-strength = <10>;
576 bias-p 550 bias-pull-up;
577 }; 551 };
578 552
579 rclk-pins { 553 rclk-pins {
580 pins = 554 pins = "sdc1_rclk";
581 bias-p 555 bias-pull-down;
582 }; 556 };
583 }; 557 };
584 558
585 sdc1_state_off: sdc1-o 559 sdc1_state_off: sdc1-off-state {
586 clk-pins { 560 clk-pins {
587 pins = 561 pins = "sdc1_clk";
588 drive- 562 drive-strength = <2>;
589 bias-d 563 bias-disable;
590 }; 564 };
591 565
592 cmd-pins { 566 cmd-pins {
593 pins = 567 pins = "sdc1_cmd";
594 drive- 568 drive-strength = <2>;
595 bias-p 569 bias-pull-up;
596 }; 570 };
597 571
598 data-pins { 572 data-pins {
599 pins = 573 pins = "sdc1_data";
600 drive- 574 drive-strength = <2>;
601 bias-p 575 bias-pull-up;
602 }; 576 };
603 577
604 rclk-pins { 578 rclk-pins {
605 pins = 579 pins = "sdc1_rclk";
606 bias-p 580 bias-pull-down;
607 }; 581 };
608 }; 582 };
609 583
610 sdc2_state_on: sdc2-on 584 sdc2_state_on: sdc2-on-state {
611 clk-pins { 585 clk-pins {
612 pins = 586 pins = "sdc2_clk";
613 drive- 587 drive-strength = <16>;
614 bias-d 588 bias-disable;
615 }; 589 };
616 590
617 cmd-pins { 591 cmd-pins {
618 pins = 592 pins = "sdc2_cmd";
619 drive- 593 drive-strength = <10>;
620 bias-p 594 bias-pull-up;
621 }; 595 };
622 596
623 data-pins { 597 data-pins {
624 pins = 598 pins = "sdc2_data";
625 drive- 599 drive-strength = <10>;
626 bias-p 600 bias-pull-up;
627 }; 601 };
628 }; 602 };
629 603
630 sdc2_state_off: sdc2-o 604 sdc2_state_off: sdc2-off-state {
631 clk-pins { 605 clk-pins {
632 pins = 606 pins = "sdc2_clk";
633 drive- 607 drive-strength = <2>;
634 bias-d 608 bias-disable;
635 }; 609 };
636 610
637 cmd-pins { 611 cmd-pins {
638 pins = 612 pins = "sdc2_cmd";
639 drive- 613 drive-strength = <2>;
640 bias-p 614 bias-pull-up;
641 }; 615 };
642 616
643 data-pins { 617 data-pins {
644 pins = 618 pins = "sdc2_data";
645 drive- 619 drive-strength = <2>;
646 bias-p 620 bias-pull-up;
647 }; 621 };
648 }; 622 };
649 }; 623 };
650 624
651 gcc: clock-controller@1400000 625 gcc: clock-controller@1400000 {
652 compatible = "qcom,gcc 626 compatible = "qcom,gcc-qcm2290";
653 reg = <0x0 0x01400000 627 reg = <0x0 0x01400000 0x0 0x1f0000>;
654 clocks = <&rpmcc RPM_S 628 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>;
655 clock-names = "bi_tcxo 629 clock-names = "bi_tcxo", "sleep_clk";
656 #clock-cells = <1>; 630 #clock-cells = <1>;
657 #reset-cells = <1>; 631 #reset-cells = <1>;
658 #power-domain-cells = 632 #power-domain-cells = <1>;
659 }; 633 };
660 634
661 usb_hsphy: phy@1613000 { 635 usb_hsphy: phy@1613000 {
662 compatible = "qcom,qcm 636 compatible = "qcom,qcm2290-qusb2-phy";
663 reg = <0x0 0x01613000 637 reg = <0x0 0x01613000 0x0 0x180>;
664 638
665 clocks = <&gcc GCC_AHB 639 clocks = <&gcc GCC_AHB2PHY_USB_CLK>,
666 <&rpmcc RPM_S 640 <&rpmcc RPM_SMD_XO_CLK_SRC>;
667 clock-names = "cfg_ahb 641 clock-names = "cfg_ahb", "ref";
668 642
669 resets = <&gcc GCC_QUS 643 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
670 nvmem-cells = <&qusb2_ 644 nvmem-cells = <&qusb2_hstx_trim>;
671 #phy-cells = <0>; 645 #phy-cells = <0>;
672 646
673 status = "disabled"; 647 status = "disabled";
674 }; 648 };
675 649
676 usb_qmpphy: phy@1615000 { 650 usb_qmpphy: phy@1615000 {
677 compatible = "qcom,qcm 651 compatible = "qcom,qcm2290-qmp-usb3-phy";
678 reg = <0x0 0x01615000 652 reg = <0x0 0x01615000 0x0 0x1000>;
679 653
680 clocks = <&gcc GCC_AHB 654 clocks = <&gcc GCC_AHB2PHY_USB_CLK>,
681 <&gcc GCC_USB 655 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
682 <&gcc GCC_USB 656 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
683 <&gcc GCC_USB 657 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
684 clock-names = "cfg_ahb 658 clock-names = "cfg_ahb",
685 "ref", 659 "ref",
686 "com_aux 660 "com_aux",
687 "pipe"; 661 "pipe";
688 662
689 resets = <&gcc GCC_USB 663 resets = <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>,
690 <&gcc GCC_USB 664 <&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>;
691 reset-names = "phy", 665 reset-names = "phy",
692 "phy_phy 666 "phy_phy";
693 667
694 #clock-cells = <0>; 668 #clock-cells = <0>;
695 clock-output-names = " 669 clock-output-names = "usb3_phy_pipe_clk_src";
696 670
697 #phy-cells = <0>; 671 #phy-cells = <0>;
698 orientation-switch; <<
699 672
700 qcom,tcsr-reg = <&tcsr 673 qcom,tcsr-reg = <&tcsr_regs 0xb244>;
701 674
702 status = "disabled"; 675 status = "disabled";
703 <<
704 ports { <<
705 #address-cells <<
706 #size-cells = <<
707 <<
708 port@0 { <<
709 reg = <<
710 <<
711 usb_qm <<
712 }; <<
713 }; <<
714 <<
715 port@1 { <<
716 reg = <<
717 <<
718 usb_qm <<
719 <<
720 }; <<
721 }; <<
722 }; <<
723 }; <<
724 <<
725 system_noc: interconnect@18800 <<
726 compatible = "qcom,qcm <<
727 reg = <0x0 0x01880000 <<
728 #interconnect-cells = <<
729 <<
730 qup_virt: interconnect <<
731 compatible = " <<
732 #interconnect- <<
733 }; <<
734 <<
735 mmnrt_virt: interconne <<
736 compatible = " <<
737 #interconnect- <<
738 }; <<
739 <<
740 mmrt_virt: interconnec <<
741 compatible = " <<
742 #interconnect- <<
743 }; <<
744 }; <<
745 <<
746 config_noc: interconnect@19000 <<
747 compatible = "qcom,qcm <<
748 reg = <0x0 0x01900000 <<
749 #interconnect-cells = <<
750 }; 676 };
751 677
752 qfprom@1b44000 { 678 qfprom@1b44000 {
753 compatible = "qcom,qcm 679 compatible = "qcom,qcm2290-qfprom", "qcom,qfprom";
754 reg = <0x0 0x01b44000 680 reg = <0x0 0x01b44000 0x0 0x3000>;
755 #address-cells = <1>; 681 #address-cells = <1>;
756 #size-cells = <1>; 682 #size-cells = <1>;
757 683
758 qusb2_hstx_trim: hstx- 684 qusb2_hstx_trim: hstx-trim@25b {
759 reg = <0x25b 0 685 reg = <0x25b 0x1>;
760 bits = <1 4>; 686 bits = <1 4>;
761 }; 687 };
762 <<
763 gpu_speed_bin: gpu-spe <<
764 reg = <0x2006 <<
765 bits = <5 8>; <<
766 }; <<
767 }; <<
768 <<
769 pmu@1b8e300 { <<
770 compatible = "qcom,qcm <<
771 reg = <0x0 0x01b8e300 <<
772 interrupts = <GIC_SPI <<
773 <<
774 operating-points-v2 = <<
775 interconnects = <&bimc <<
776 &bimc <<
777 <<
778 cpu_bwmon_opp_table: o <<
779 compatible = " <<
780 <<
781 opp-0 { <<
782 opp-pe <<
783 }; <<
784 <<
785 opp-1 { <<
786 opp-pe <<
787 }; <<
788 <<
789 opp-2 { <<
790 opp-pe <<
791 }; <<
792 <<
793 opp-3 { <<
794 opp-pe <<
795 }; <<
796 <<
797 opp-4 { <<
798 opp-pe <<
799 }; <<
800 <<
801 opp-5 { <<
802 opp-pe <<
803 }; <<
804 <<
805 opp-6 { <<
806 opp-pe <<
807 }; <<
808 <<
809 opp-7 { <<
810 opp-pe <<
811 }; <<
812 <<
813 opp-8 { <<
814 opp-pe <<
815 }; <<
816 <<
817 opp-9 { <<
818 opp-pe <<
819 }; <<
820 }; <<
821 }; 688 };
822 689
823 spmi_bus: spmi@1c40000 { 690 spmi_bus: spmi@1c40000 {
824 compatible = "qcom,spm 691 compatible = "qcom,spmi-pmic-arb";
825 reg = <0x0 0x01c40000 692 reg = <0x0 0x01c40000 0x0 0x1100>,
826 <0x0 0x01e00000 693 <0x0 0x01e00000 0x0 0x2000000>,
827 <0x0 0x03e00000 694 <0x0 0x03e00000 0x0 0x100000>,
828 <0x0 0x03f00000 695 <0x0 0x03f00000 0x0 0xa0000>,
829 <0x0 0x01c0a000 696 <0x0 0x01c0a000 0x0 0x26000>;
830 reg-names = "core", 697 reg-names = "core",
831 "chnls", 698 "chnls",
832 "obsrvr", 699 "obsrvr",
833 "intr", 700 "intr",
834 "cnfg"; 701 "cnfg";
835 interrupts-extended = !! 702 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
836 interrupt-names = "per 703 interrupt-names = "periph_irq";
837 qcom,ee = <0>; 704 qcom,ee = <0>;
838 qcom,channel = <0>; 705 qcom,channel = <0>;
839 #address-cells = <2>; 706 #address-cells = <2>;
840 #size-cells = <0>; 707 #size-cells = <0>;
841 interrupt-controller; 708 interrupt-controller;
842 #interrupt-cells = <4> 709 #interrupt-cells = <4>;
843 }; 710 };
844 711
845 tsens0: thermal-sensor@4411000 712 tsens0: thermal-sensor@4411000 {
846 compatible = "qcom,qcm 713 compatible = "qcom,qcm2290-tsens", "qcom,tsens-v2";
847 reg = <0x0 0x04411000 714 reg = <0x0 0x04411000 0x0 0x1ff>,
848 <0x0 0x04410000 715 <0x0 0x04410000 0x0 0x8>;
849 #qcom,sensors = <10>; 716 #qcom,sensors = <10>;
850 interrupts-extended = !! 717 interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
851 !! 718 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
852 interrupt-names = "upl 719 interrupt-names = "uplow", "critical";
853 #thermal-sensor-cells 720 #thermal-sensor-cells = <1>;
854 }; 721 };
855 722
856 rng: rng@4453000 { 723 rng: rng@4453000 {
857 compatible = "qcom,prn 724 compatible = "qcom,prng-ee";
858 reg = <0x0 0x04453000 725 reg = <0x0 0x04453000 0x0 0x1000>;
859 clocks = <&rpmcc RPM_S 726 clocks = <&rpmcc RPM_SMD_HWKM_CLK>;
860 clock-names = "core"; 727 clock-names = "core";
861 }; 728 };
862 729
863 bimc: interconnect@4480000 { <<
864 compatible = "qcom,qcm <<
865 reg = <0x0 0x04480000 <<
866 #interconnect-cells = <<
867 }; <<
868 <<
869 rpm_msg_ram: sram@45f0000 { 730 rpm_msg_ram: sram@45f0000 {
870 compatible = "qcom,rpm !! 731 compatible = "qcom,rpm-msg-ram";
871 reg = <0x0 0x045f0000 732 reg = <0x0 0x045f0000 0x0 0x7000>;
872 #address-cells = <1>; <<
873 #size-cells = <1>; <<
874 ranges = <0 0x0 0x045f <<
875 <<
876 apss_mpm: sram@1b8 { <<
877 reg = <0x1b8 0 <<
878 }; <<
879 }; 733 };
880 734
881 sram@4690000 { 735 sram@4690000 {
882 compatible = "qcom,rpm 736 compatible = "qcom,rpm-stats";
883 reg = <0x0 0x04690000 737 reg = <0x0 0x04690000 0x0 0x10000>;
884 }; 738 };
885 739
886 sdhc_1: mmc@4744000 { 740 sdhc_1: mmc@4744000 {
887 compatible = "qcom,qcm 741 compatible = "qcom,qcm2290-sdhci", "qcom,sdhci-msm-v5";
888 reg = <0x0 0x04744000 742 reg = <0x0 0x04744000 0x0 0x1000>,
889 <0x0 0x04745000 743 <0x0 0x04745000 0x0 0x1000>,
890 <0x0 0x04748000 744 <0x0 0x04748000 0x0 0x8000>;
891 reg-names = "hc", 745 reg-names = "hc",
892 "cqhci", 746 "cqhci",
893 "ice"; 747 "ice";
894 748
895 interrupts = <GIC_SPI 749 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
896 <GIC_SPI 750 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
897 interrupt-names = "hc_ 751 interrupt-names = "hc_irq", "pwr_irq";
898 752
899 clocks = <&gcc GCC_SDC 753 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
900 <&gcc GCC_SDC 754 <&gcc GCC_SDCC1_APPS_CLK>,
901 <&rpmcc RPM_S 755 <&rpmcc RPM_SMD_XO_CLK_SRC>,
902 <&gcc GCC_SDC 756 <&gcc GCC_SDCC1_ICE_CORE_CLK>;
903 clock-names = "iface", 757 clock-names = "iface",
904 "core", 758 "core",
905 "xo", 759 "xo",
906 "ice"; 760 "ice";
907 761
908 resets = <&gcc GCC_SDC 762 resets = <&gcc GCC_SDCC1_BCR>;
909 763
910 power-domains = <&rpmp 764 power-domains = <&rpmpd QCM2290_VDDCX>;
911 operating-points-v2 = <<
912 iommus = <&apps_smmu 0 765 iommus = <&apps_smmu 0xc0 0x0>;
913 interconnects = <&syst <<
914 &bimc <<
915 <&bimc <<
916 &conf <<
917 interconnect-names = " <<
918 " <<
919 766
920 qcom,dll-config = <0x0 767 qcom,dll-config = <0x000f642c>;
921 qcom,ddr-config = <0x8 768 qcom,ddr-config = <0x80040868>;
922 bus-width = <8>; 769 bus-width = <8>;
923 770
924 status = "disabled"; 771 status = "disabled";
925 <<
926 sdhc1_opp_table: opp-t <<
927 compatible = " <<
928 <<
929 opp-100000000 <<
930 opp-hz <<
931 requir <<
932 opp-pe <<
933 opp-av <<
934 }; <<
935 <<
936 opp-192000000 <<
937 opp-hz <<
938 requir <<
939 opp-pe <<
940 opp-av <<
941 }; <<
942 <<
943 opp-384000000 <<
944 opp-hz <<
945 requir <<
946 opp-pe <<
947 opp-av <<
948 }; <<
949 }; <<
950 }; 772 };
951 773
952 sdhc_2: mmc@4784000 { 774 sdhc_2: mmc@4784000 {
953 compatible = "qcom,qcm 775 compatible = "qcom,qcm2290-sdhci", "qcom,sdhci-msm-v5";
954 reg = <0x0 0x04784000 776 reg = <0x0 0x04784000 0x0 0x1000>;
955 reg-names = "hc"; 777 reg-names = "hc";
956 778
957 interrupts = <GIC_SPI 779 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
958 <GIC_SPI 780 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
959 interrupt-names = "hc_ 781 interrupt-names = "hc_irq", "pwr_irq";
960 782
961 clocks = <&gcc GCC_SDC 783 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
962 <&gcc GCC_SDC 784 <&gcc GCC_SDCC2_APPS_CLK>,
963 <&rpmcc RPM_S 785 <&rpmcc RPM_SMD_XO_CLK_SRC>;
964 clock-names = "iface", 786 clock-names = "iface",
965 "core", 787 "core",
966 "xo"; 788 "xo";
967 789
968 resets = <&gcc GCC_SDC 790 resets = <&gcc GCC_SDCC2_BCR>;
969 791
970 power-domains = <&rpmp 792 power-domains = <&rpmpd QCM2290_VDDCX>;
971 operating-points-v2 = 793 operating-points-v2 = <&sdhc2_opp_table>;
972 iommus = <&apps_smmu 0 794 iommus = <&apps_smmu 0xa0 0x0>;
973 interconnects = <&syst <<
974 &bimc <<
975 <&bimc <<
976 &conf <<
977 interconnect-names = " <<
978 " <<
979 795
980 qcom,dll-config = <0x0 796 qcom,dll-config = <0x0007642c>;
981 qcom,ddr-config = <0x8 797 qcom,ddr-config = <0x80040868>;
982 bus-width = <4>; 798 bus-width = <4>;
983 799
984 status = "disabled"; 800 status = "disabled";
985 801
986 sdhc2_opp_table: opp-t 802 sdhc2_opp_table: opp-table {
987 compatible = " 803 compatible = "operating-points-v2";
988 804
989 opp-100000000 805 opp-100000000 {
990 opp-hz 806 opp-hz = /bits/ 64 <100000000>;
991 requir 807 required-opps = <&rpmpd_opp_low_svs>;
992 opp-pe <<
993 opp-av <<
994 }; 808 };
995 809
996 opp-202000000 810 opp-202000000 {
997 opp-hz 811 opp-hz = /bits/ 64 <202000000>;
998 requir 812 required-opps = <&rpmpd_opp_svs_plus>;
999 opp-pe <<
1000 opp-a <<
1001 }; 813 };
1002 }; 814 };
1003 }; 815 };
1004 816
1005 gpi_dma0: dma-controller@4a00 817 gpi_dma0: dma-controller@4a00000 {
1006 compatible = "qcom,qc 818 compatible = "qcom,qcm2290-gpi-dma", "qcom,sm6350-gpi-dma";
1007 reg = <0x0 0x04a00000 819 reg = <0x0 0x04a00000 0x0 0x60000>;
1008 interrupts = <GIC_SPI 820 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1009 <GIC_SPI 821 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1010 <GIC_SPI 822 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
1011 <GIC_SPI 823 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
1012 <GIC_SPI 824 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
1013 <GIC_SPI 825 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
1014 <GIC_SPI 826 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
1015 <GIC_SPI 827 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
1016 <GIC_SPI 828 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
1017 <GIC_SPI 829 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1018 dma-channels = <10>; 830 dma-channels = <10>;
1019 dma-channel-mask = <0 831 dma-channel-mask = <0x1f>;
1020 iommus = <&apps_smmu 832 iommus = <&apps_smmu 0xf6 0x0>;
1021 #dma-cells = <3>; 833 #dma-cells = <3>;
1022 status = "disabled"; 834 status = "disabled";
1023 }; 835 };
1024 836
1025 qupv3_id_0: geniqup@4ac0000 { 837 qupv3_id_0: geniqup@4ac0000 {
1026 compatible = "qcom,ge 838 compatible = "qcom,geni-se-qup";
1027 reg = <0x0 0x04ac0000 839 reg = <0x0 0x04ac0000 0x0 0x2000>;
1028 clocks = <&gcc GCC_QU 840 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1029 <&gcc GCC_QU 841 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1030 clock-names = "m-ahb" 842 clock-names = "m-ahb", "s-ahb";
1031 iommus = <&apps_smmu 843 iommus = <&apps_smmu 0xe3 0x0>;
1032 #address-cells = <2>; 844 #address-cells = <2>;
1033 #size-cells = <2>; 845 #size-cells = <2>;
1034 ranges; 846 ranges;
1035 status = "disabled"; 847 status = "disabled";
1036 848
1037 i2c0: i2c@4a80000 { 849 i2c0: i2c@4a80000 {
1038 compatible = 850 compatible = "qcom,geni-i2c";
1039 reg = <0x0 0x 851 reg = <0x0 0x04a80000 0x0 0x4000>;
1040 interrupts = 852 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
1041 clocks = <&gc 853 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1042 clock-names = 854 clock-names = "se";
1043 pinctrl-0 = < 855 pinctrl-0 = <&qup_i2c0_default>;
1044 pinctrl-names 856 pinctrl-names = "default";
1045 dmas = <&gpi_ 857 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1046 <&gpi_ 858 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1047 dma-names = " 859 dma-names = "tx", "rx";
1048 interconnects <<
1049 <<
1050 <<
1051 <<
1052 <<
1053 <<
1054 interconnect- <<
1055 <<
1056 <<
1057 #address-cell 860 #address-cells = <1>;
1058 #size-cells = 861 #size-cells = <0>;
1059 status = "dis 862 status = "disabled";
1060 }; 863 };
1061 864
1062 spi0: spi@4a80000 { 865 spi0: spi@4a80000 {
1063 compatible = 866 compatible = "qcom,geni-spi";
1064 reg = <0x0 0x 867 reg = <0x0 0x04a80000 0x0 0x4000>;
1065 interrupts = 868 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
1066 clocks = <&gc 869 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1067 clock-names = 870 clock-names = "se";
1068 pinctrl-0 = < 871 pinctrl-0 = <&qup_spi0_default>;
1069 pinctrl-names 872 pinctrl-names = "default";
1070 dmas = <&gpi_ 873 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1071 <&gpi_ 874 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1072 dma-names = " 875 dma-names = "tx", "rx";
1073 interconnects <<
1074 <<
1075 <<
1076 <<
1077 interconnect- <<
1078 <<
1079 #address-cell 876 #address-cells = <1>;
1080 #size-cells = 877 #size-cells = <0>;
1081 status = "dis 878 status = "disabled";
1082 }; 879 };
1083 880
1084 uart0: serial@4a80000 881 uart0: serial@4a80000 {
1085 compatible = 882 compatible = "qcom,geni-uart";
1086 reg = <0x0 0x 883 reg = <0x0 0x04a80000 0x0 0x4000>;
1087 interrupts = 884 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
1088 clocks = <&gc 885 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1089 clock-names = 886 clock-names = "se";
1090 pinctrl-0 = < 887 pinctrl-0 = <&qup_uart0_default>;
1091 pinctrl-names 888 pinctrl-names = "default";
1092 interconnects <<
1093 <<
1094 <<
1095 <<
1096 interconnect- <<
1097 <<
1098 status = "dis 889 status = "disabled";
1099 }; 890 };
1100 891
1101 i2c1: i2c@4a84000 { 892 i2c1: i2c@4a84000 {
1102 compatible = 893 compatible = "qcom,geni-i2c";
1103 reg = <0x0 0x 894 reg = <0x0 0x04a84000 0x0 0x4000>;
1104 interrupts = 895 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
1105 clocks = <&gc 896 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1106 clock-names = 897 clock-names = "se";
1107 pinctrl-0 = < 898 pinctrl-0 = <&qup_i2c1_default>;
1108 pinctrl-names 899 pinctrl-names = "default";
1109 dmas = <&gpi_ 900 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1110 <&gpi_ 901 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1111 dma-names = " 902 dma-names = "tx", "rx";
1112 interconnects <<
1113 <<
1114 <<
1115 <<
1116 <<
1117 <<
1118 interconnect- <<
1119 <<
1120 <<
1121 #address-cell 903 #address-cells = <1>;
1122 #size-cells = 904 #size-cells = <0>;
1123 status = "dis 905 status = "disabled";
1124 }; 906 };
1125 907
1126 spi1: spi@4a84000 { 908 spi1: spi@4a84000 {
1127 compatible = 909 compatible = "qcom,geni-spi";
1128 reg = <0x0 0x 910 reg = <0x0 0x04a84000 0x0 0x4000>;
1129 interrupts = 911 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
1130 clocks = <&gc 912 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1131 clock-names = 913 clock-names = "se";
1132 pinctrl-0 = < 914 pinctrl-0 = <&qup_spi1_default>;
1133 pinctrl-names 915 pinctrl-names = "default";
1134 dmas = <&gpi_ 916 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1135 <&gpi_ 917 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1136 dma-names = " 918 dma-names = "tx", "rx";
1137 interconnects <<
1138 <<
1139 <<
1140 <<
1141 interconnect- <<
1142 <<
1143 #address-cell 919 #address-cells = <1>;
1144 #size-cells = 920 #size-cells = <0>;
1145 status = "dis 921 status = "disabled";
1146 }; 922 };
1147 923
1148 i2c2: i2c@4a88000 { 924 i2c2: i2c@4a88000 {
1149 compatible = 925 compatible = "qcom,geni-i2c";
1150 reg = <0x0 0x 926 reg = <0x0 0x04a88000 0x0 0x4000>;
1151 interrupts = 927 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
1152 clocks = <&gc 928 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1153 clock-names = 929 clock-names = "se";
1154 pinctrl-0 = < 930 pinctrl-0 = <&qup_i2c2_default>;
1155 pinctrl-names 931 pinctrl-names = "default";
1156 dmas = <&gpi_ 932 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1157 <&gpi_ 933 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1158 dma-names = " 934 dma-names = "tx", "rx";
1159 interconnects <<
1160 <<
1161 <<
1162 <<
1163 <<
1164 <<
1165 interconnect- <<
1166 <<
1167 <<
1168 #address-cell 935 #address-cells = <1>;
1169 #size-cells = 936 #size-cells = <0>;
1170 status = "dis 937 status = "disabled";
1171 }; 938 };
1172 939
1173 spi2: spi@4a88000 { 940 spi2: spi@4a88000 {
1174 compatible = 941 compatible = "qcom,geni-spi";
1175 reg = <0x0 0x 942 reg = <0x0 0x04a88000 0x0 0x4000>;
1176 interrupts = 943 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
1177 clocks = <&gc 944 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1178 clock-names = 945 clock-names = "se";
1179 pinctrl-0 = < 946 pinctrl-0 = <&qup_spi2_default>;
1180 pinctrl-names 947 pinctrl-names = "default";
1181 dmas = <&gpi_ 948 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1182 <&gpi_ 949 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1183 dma-names = " 950 dma-names = "tx", "rx";
1184 interconnects <<
1185 <<
1186 <<
1187 <<
1188 interconnect- <<
1189 <<
1190 #address-cell 951 #address-cells = <1>;
1191 #size-cells = 952 #size-cells = <0>;
1192 status = "dis 953 status = "disabled";
1193 }; 954 };
1194 955
1195 i2c3: i2c@4a8c000 { 956 i2c3: i2c@4a8c000 {
1196 compatible = 957 compatible = "qcom,geni-i2c";
1197 reg = <0x0 0x 958 reg = <0x0 0x04a8c000 0x0 0x4000>;
1198 interrupts = 959 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
1199 clocks = <&gc 960 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1200 clock-names = 961 clock-names = "se";
1201 pinctrl-0 = < 962 pinctrl-0 = <&qup_i2c3_default>;
1202 pinctrl-names 963 pinctrl-names = "default";
1203 dmas = <&gpi_ 964 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1204 <&gpi_ 965 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1205 dma-names = " 966 dma-names = "tx", "rx";
1206 interconnects <<
1207 <<
1208 <<
1209 <<
1210 <<
1211 <<
1212 interconnect- <<
1213 <<
1214 <<
1215 #address-cell 967 #address-cells = <1>;
1216 #size-cells = 968 #size-cells = <0>;
1217 status = "dis 969 status = "disabled";
1218 }; 970 };
1219 971
1220 spi3: spi@4a8c000 { 972 spi3: spi@4a8c000 {
1221 compatible = 973 compatible = "qcom,geni-spi";
1222 reg = <0x0 0x 974 reg = <0x0 0x04a8c000 0x0 0x4000>;
1223 interrupts = 975 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
1224 clocks = <&gc 976 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1225 clock-names = 977 clock-names = "se";
1226 pinctrl-0 = < 978 pinctrl-0 = <&qup_spi3_default>;
1227 pinctrl-names 979 pinctrl-names = "default";
1228 dmas = <&gpi_ 980 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1229 <&gpi_ 981 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1230 dma-names = " 982 dma-names = "tx", "rx";
1231 interconnects <<
1232 <<
1233 <<
1234 <<
1235 interconnect- <<
1236 <<
1237 #address-cell 983 #address-cells = <1>;
1238 #size-cells = 984 #size-cells = <0>;
1239 status = "dis 985 status = "disabled";
1240 }; 986 };
1241 987
1242 i2c4: i2c@4a90000 { 988 i2c4: i2c@4a90000 {
1243 compatible = 989 compatible = "qcom,geni-i2c";
1244 reg = <0x0 0x 990 reg = <0x0 0x04a90000 0x0 0x4000>;
1245 interrupts = 991 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
1246 clocks = <&gc 992 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1247 clock-names = 993 clock-names = "se";
1248 pinctrl-0 = < 994 pinctrl-0 = <&qup_i2c4_default>;
1249 pinctrl-names 995 pinctrl-names = "default";
1250 dmas = <&gpi_ 996 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1251 <&gpi_ 997 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1252 dma-names = " 998 dma-names = "tx", "rx";
1253 interconnects <<
1254 <<
1255 <<
1256 <<
1257 <<
1258 <<
1259 interconnect- <<
1260 <<
1261 <<
1262 #address-cell 999 #address-cells = <1>;
1263 #size-cells = 1000 #size-cells = <0>;
1264 status = "dis 1001 status = "disabled";
1265 }; 1002 };
1266 1003
1267 spi4: spi@4a90000 { 1004 spi4: spi@4a90000 {
1268 compatible = 1005 compatible = "qcom,geni-spi";
1269 reg = <0x0 0x 1006 reg = <0x0 0x04a90000 0x0 0x4000>;
1270 interrupts = 1007 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
1271 clock-names = 1008 clock-names = "se";
1272 clocks = <&gc 1009 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1273 pinctrl-names 1010 pinctrl-names = "default";
1274 pinctrl-0 = < 1011 pinctrl-0 = <&qup_spi4_default>;
1275 dmas = <&gpi_ 1012 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1276 <&gpi_ 1013 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1277 dma-names = " 1014 dma-names = "tx", "rx";
1278 interconnects <<
1279 <<
1280 <<
1281 <<
1282 interconnect- <<
1283 <<
1284 #address-cell 1015 #address-cells = <1>;
1285 #size-cells = 1016 #size-cells = <0>;
1286 status = "dis 1017 status = "disabled";
1287 }; 1018 };
1288 1019
1289 uart4: serial@4a90000 1020 uart4: serial@4a90000 {
1290 compatible = 1021 compatible = "qcom,geni-uart";
1291 reg = <0x0 0x 1022 reg = <0x0 0x04a90000 0x0 0x4000>;
1292 interrupts = 1023 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
1293 clocks = <&gc 1024 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1294 clock-names = 1025 clock-names = "se";
1295 pinctrl-0 = < 1026 pinctrl-0 = <&qup_uart4_default>;
1296 pinctrl-names 1027 pinctrl-names = "default";
1297 interconnects <<
1298 <<
1299 <<
1300 <<
1301 interconnect- <<
1302 <<
1303 status = "dis 1028 status = "disabled";
1304 }; 1029 };
1305 1030
1306 i2c5: i2c@4a94000 { 1031 i2c5: i2c@4a94000 {
1307 compatible = 1032 compatible = "qcom,geni-i2c";
1308 reg = <0x0 0x 1033 reg = <0x0 0x04a94000 0x0 0x4000>;
1309 interrupts = 1034 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
1310 clocks = <&gc 1035 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1311 clock-names = 1036 clock-names = "se";
1312 pinctrl-0 = < 1037 pinctrl-0 = <&qup_i2c5_default>;
1313 pinctrl-names 1038 pinctrl-names = "default";
1314 dmas = <&gpi_ 1039 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1315 <&gpi_ 1040 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1316 dma-names = " 1041 dma-names = "tx", "rx";
1317 interconnects <<
1318 <<
1319 <<
1320 <<
1321 <<
1322 <<
1323 interconnect- <<
1324 <<
1325 <<
1326 #address-cell 1042 #address-cells = <1>;
1327 #size-cells = 1043 #size-cells = <0>;
1328 status = "dis 1044 status = "disabled";
1329 }; 1045 };
1330 1046
1331 spi5: spi@4a94000 { 1047 spi5: spi@4a94000 {
1332 compatible = 1048 compatible = "qcom,geni-spi";
1333 reg = <0x0 0x 1049 reg = <0x0 0x04a94000 0x0 0x4000>;
1334 interrupts = 1050 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
1335 clocks = <&gc 1051 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1336 clock-names = 1052 clock-names = "se";
1337 pinctrl-0 = < 1053 pinctrl-0 = <&qup_spi5_default>;
1338 pinctrl-names 1054 pinctrl-names = "default";
1339 dmas = <&gpi_ 1055 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1340 <&gpi_ 1056 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1341 dma-names = " 1057 dma-names = "tx", "rx";
1342 interconnects <<
1343 <<
1344 <<
1345 <<
1346 interconnect- <<
1347 <<
1348 #address-cell 1058 #address-cells = <1>;
1349 #size-cells = 1059 #size-cells = <0>;
1350 status = "dis 1060 status = "disabled";
1351 }; 1061 };
1352 }; 1062 };
1353 1063
1354 usb: usb@4ef8800 { 1064 usb: usb@4ef8800 {
1355 compatible = "qcom,qc 1065 compatible = "qcom,qcm2290-dwc3", "qcom,dwc3";
1356 reg = <0x0 0x04ef8800 1066 reg = <0x0 0x04ef8800 0x0 0x400>;
1357 interrupts-extended = !! 1067 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
1358 !! 1068 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
1359 interrupt-names = "hs !! 1069 interrupt-names = "hs_phy_irq", "ss_phy_irq";
1360 "ss <<
1361 1070
1362 clocks = <&gcc GCC_CF 1071 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
1363 <&gcc GCC_US 1072 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
1364 <&gcc GCC_SY 1073 <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>,
1365 <&gcc GCC_US 1074 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
1366 <&gcc GCC_US 1075 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1367 <&gcc GCC_US 1076 <&gcc GCC_USB3_PRIM_CLKREF_CLK>;
1368 clock-names = "cfg_no 1077 clock-names = "cfg_noc",
1369 "core", 1078 "core",
1370 "iface" 1079 "iface",
1371 "sleep" 1080 "sleep",
1372 "mock_u 1081 "mock_utmi",
1373 "xo"; 1082 "xo";
1374 1083
1375 assigned-clocks = <&g 1084 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1376 <&g 1085 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
1377 assigned-clock-rates 1086 assigned-clock-rates = <19200000>, <133333333>;
1378 1087
1379 resets = <&gcc GCC_US 1088 resets = <&gcc GCC_USB30_PRIM_BCR>;
1380 power-domains = <&gcc 1089 power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
1381 /* TODO: USB<->IPA pa <<
1382 interconnects = <&sys <<
1383 &bim <<
1384 <&bim <<
1385 &con <<
1386 interconnect-names = <<
1387 <<
1388 wakeup-source; 1090 wakeup-source;
1389 1091
1390 #address-cells = <2>; 1092 #address-cells = <2>;
1391 #size-cells = <2>; 1093 #size-cells = <2>;
1392 ranges; 1094 ranges;
1393 1095
1394 status = "disabled"; 1096 status = "disabled";
1395 1097
1396 usb_dwc3: usb@4e00000 1098 usb_dwc3: usb@4e00000 {
1397 compatible = 1099 compatible = "snps,dwc3";
1398 reg = <0x0 0x 1100 reg = <0x0 0x04e00000 0x0 0xcd00>;
1399 interrupts = 1101 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
1400 phys = <&usb_ 1102 phys = <&usb_hsphy>, <&usb_qmpphy>;
1401 phy-names = " 1103 phy-names = "usb2-phy", "usb3-phy";
1402 iommus = <&ap 1104 iommus = <&apps_smmu 0x120 0x0>;
1403 snps,dis_u2_s 1105 snps,dis_u2_susphy_quirk;
1404 snps,dis_enbl 1106 snps,dis_enblslpm_quirk;
1405 snps,has-lpm- 1107 snps,has-lpm-erratum;
1406 snps,hird-thr 1108 snps,hird-threshold = /bits/ 8 <0x10>;
1407 snps,usb3_lpm 1109 snps,usb3_lpm_capable;
1408 maximum-speed 1110 maximum-speed = "super-speed";
1409 dr_mode = "ot 1111 dr_mode = "otg";
1410 usb-role-swit <<
1411 <<
1412 ports { <<
1413 #addr <<
1414 #size <<
1415 <<
1416 port@ <<
1417 <<
1418 <<
1419 <<
1420 <<
1421 }; <<
1422 <<
1423 port@ <<
1424 <<
1425 <<
1426 <<
1427 <<
1428 <<
1429 }; <<
1430 }; <<
1431 }; 1112 };
1432 }; 1113 };
1433 1114
1434 gpu: gpu@5900000 { <<
1435 compatible = "qcom,ad <<
1436 reg = <0x0 0x05900000 <<
1437 reg-names = "kgsl_3d0 <<
1438 <<
1439 interrupts = <GIC_SPI <<
1440 <<
1441 clocks = <&gpucc GPU_ <<
1442 <&gpucc GPU_ <<
1443 <&gcc GCC_BI <<
1444 <&gcc GCC_GP <<
1445 <&gpucc GPU_ <<
1446 <&gpucc GPU_ <<
1447 clock-names = "core", <<
1448 "iface" <<
1449 "mem_if <<
1450 "alt_me <<
1451 "gmu", <<
1452 "xo"; <<
1453 <<
1454 interconnects = <&bim <<
1455 &bim <<
1456 interconnect-names = <<
1457 <<
1458 iommus = <&adreno_smm <<
1459 <&adreno_smm <<
1460 operating-points-v2 = <<
1461 power-domains = <&rpm <<
1462 qcom,gmu = <&gmu_wrap <<
1463 <<
1464 nvmem-cells = <&gpu_s <<
1465 nvmem-cell-names = "s <<
1466 #cooling-cells = <2>; <<
1467 <<
1468 status = "disabled"; <<
1469 <<
1470 zap-shader { <<
1471 memory-region <<
1472 }; <<
1473 <<
1474 gpu_opp_table: opp-ta <<
1475 compatible = <<
1476 <<
1477 /* TODO: Scal <<
1478 opp-112320000 <<
1479 opp-h <<
1480 requi <<
1481 opp-p <<
1482 opp-s <<
1483 turbo <<
1484 }; <<
1485 <<
1486 opp-101760000 <<
1487 opp-h <<
1488 requi <<
1489 opp-p <<
1490 opp-s <<
1491 turbo <<
1492 }; <<
1493 <<
1494 opp-921600000 <<
1495 opp-h <<
1496 requi <<
1497 opp-p <<
1498 opp-s <<
1499 }; <<
1500 <<
1501 opp-844800000 <<
1502 opp-h <<
1503 requi <<
1504 opp-p <<
1505 opp-s <<
1506 }; <<
1507 <<
1508 opp-672000000 <<
1509 opp-h <<
1510 requi <<
1511 opp-p <<
1512 opp-s <<
1513 }; <<
1514 <<
1515 opp-537600000 <<
1516 opp-h <<
1517 requi <<
1518 opp-p <<
1519 opp-s <<
1520 }; <<
1521 <<
1522 opp-355200000 <<
1523 opp-h <<
1524 requi <<
1525 opp-p <<
1526 opp-s <<
1527 }; <<
1528 }; <<
1529 }; <<
1530 <<
1531 gmu_wrapper: gmu@596a000 { <<
1532 compatible = "qcom,ad <<
1533 reg = <0x0 0x0596a000 <<
1534 reg-names = "gmu"; <<
1535 power-domains = <&gpu <<
1536 <&gpu <<
1537 power-domain-names = <<
1538 <<
1539 }; <<
1540 <<
1541 gpucc: clock-controller@59900 <<
1542 compatible = "qcom,qc <<
1543 reg = <0x0 0x05990000 <<
1544 clocks = <&gcc GCC_GP <<
1545 <&rpmcc RPM_ <<
1546 <&gcc GCC_GP <<
1547 <&gcc GCC_GP <<
1548 power-domains = <&rpm <<
1549 required-opps = <&rpm <<
1550 #clock-cells = <1>; <<
1551 #reset-cells = <1>; <<
1552 #power-domain-cells = <<
1553 }; <<
1554 <<
1555 adreno_smmu: iommu@59a0000 { <<
1556 compatible = "qcom,qc <<
1557 "qcom,sm <<
1558 reg = <0x0 0x059a0000 <<
1559 interrupts = <GIC_SPI <<
1560 <GIC_SPI <<
1561 <GIC_SPI <<
1562 <GIC_SPI <<
1563 <GIC_SPI <<
1564 <GIC_SPI <<
1565 <GIC_SPI <<
1566 <GIC_SPI <<
1567 <GIC_SPI <<
1568 <<
1569 clocks = <&gcc GCC_GP <<
1570 <&gpucc GPU_ <<
1571 <&gcc GCC_GP <<
1572 clock-names = "mem", <<
1573 "hlos", <<
1574 "iface" <<
1575 <<
1576 power-domains = <&gpu <<
1577 <<
1578 #global-interrupts = <<
1579 #iommu-cells = <2>; <<
1580 }; <<
1581 <<
1582 mdss: display-subsystem@5e000 <<
1583 compatible = "qcom,qc <<
1584 reg = <0x0 0x05e00000 <<
1585 reg-names = "mdss"; <<
1586 interrupts = <GIC_SPI <<
1587 interrupt-controller; <<
1588 #interrupt-cells = <1 <<
1589 <<
1590 clocks = <&gcc GCC_DI <<
1591 <&gcc GCC_DI <<
1592 <&dispcc DIS <<
1593 clock-names = "iface" <<
1594 "bus", <<
1595 "core"; <<
1596 <<
1597 resets = <&dispcc DIS <<
1598 <<
1599 power-domains = <&dis <<
1600 <<
1601 iommus = <&apps_smmu <<
1602 <&apps_smmu <<
1603 interconnects = <&mmr <<
1604 &bim <<
1605 <&bim <<
1606 &con <<
1607 interconnect-names = <<
1608 <<
1609 <<
1610 #address-cells = <2>; <<
1611 #size-cells = <2>; <<
1612 ranges; <<
1613 <<
1614 status = "disabled"; <<
1615 <<
1616 mdp: display-controll <<
1617 compatible = <<
1618 reg = <0x0 0x <<
1619 <0x0 0x <<
1620 reg-names = " <<
1621 " <<
1622 <<
1623 interrupt-par <<
1624 interrupts = <<
1625 <<
1626 clocks = <&gc <<
1627 <&di <<
1628 <&di <<
1629 <&di <<
1630 <&di <<
1631 clock-names = <<
1632 <<
1633 <<
1634 <<
1635 <<
1636 <<
1637 operating-poi <<
1638 power-domains <<
1639 <<
1640 ports { <<
1641 #addr <<
1642 #size <<
1643 <<
1644 port@ <<
1645 <<
1646 <<
1647 <<
1648 <<
1649 }; <<
1650 }; <<
1651 <<
1652 mdp_opp_table <<
1653 compa <<
1654 <<
1655 opp-1 <<
1656 <<
1657 <<
1658 }; <<
1659 <<
1660 opp-1 <<
1661 <<
1662 <<
1663 }; <<
1664 <<
1665 opp-2 <<
1666 <<
1667 <<
1668 }; <<
1669 <<
1670 opp-3 <<
1671 <<
1672 <<
1673 }; <<
1674 <<
1675 opp-3 <<
1676 <<
1677 <<
1678 }; <<
1679 }; <<
1680 }; <<
1681 <<
1682 mdss_dsi0: dsi@5e9400 <<
1683 compatible = <<
1684 reg = <0x0 0x <<
1685 reg-names = " <<
1686 <<
1687 interrupt-par <<
1688 interrupts = <<
1689 <<
1690 clocks = <&di <<
1691 <&di <<
1692 <&di <<
1693 <&di <<
1694 <&di <<
1695 <&gc <<
1696 clock-names = <<
1697 <<
1698 <<
1699 <<
1700 <<
1701 <<
1702 <<
1703 assigned-cloc <<
1704 <<
1705 assigned-cloc <<
1706 <<
1707 <<
1708 operating-poi <<
1709 power-domains <<
1710 phys = <&mdss <<
1711 <<
1712 #address-cell <<
1713 #size-cells = <<
1714 <<
1715 status = "dis <<
1716 <<
1717 dsi_opp_table <<
1718 compa <<
1719 <<
1720 opp-1 <<
1721 <<
1722 <<
1723 }; <<
1724 <<
1725 opp-1 <<
1726 <<
1727 <<
1728 }; <<
1729 <<
1730 opp-1 <<
1731 <<
1732 <<
1733 }; <<
1734 }; <<
1735 <<
1736 ports { <<
1737 #addr <<
1738 #size <<
1739 <<
1740 port@ <<
1741 <<
1742 <<
1743 <<
1744 <<
1745 <<
1746 }; <<
1747 <<
1748 port@ <<
1749 <<
1750 <<
1751 <<
1752 <<
1753 }; <<
1754 }; <<
1755 }; <<
1756 <<
1757 mdss_dsi0_phy: phy@5e <<
1758 compatible = <<
1759 reg = <0x0 0x <<
1760 <0x0 0x <<
1761 <0x0 0x <<
1762 reg-names = " <<
1763 " <<
1764 " <<
1765 <<
1766 clocks = <&di <<
1767 <&rp <<
1768 clock-names = <<
1769 <<
1770 <<
1771 power-domains <<
1772 required-opps <<
1773 <<
1774 #clock-cells <<
1775 #phy-cells = <<
1776 <<
1777 status = "dis <<
1778 }; <<
1779 }; <<
1780 <<
1781 dispcc: clock-controller@5f00 <<
1782 compatible = "qcom,qc <<
1783 reg = <0x0 0x05f00000 <<
1784 clocks = <&rpmcc RPM_ <<
1785 <&rpmcc RPM_ <<
1786 <&gcc GCC_DI <<
1787 <&gcc GCC_DI <<
1788 <&mdss_dsi0_ <<
1789 <&mdss_dsi0_ <<
1790 clock-names = "bi_tcx <<
1791 "bi_tcx <<
1792 "gcc_di <<
1793 "gcc_di <<
1794 "dsi0_p <<
1795 "dsi0_p <<
1796 #power-domain-cells = <<
1797 #clock-cells = <1>; <<
1798 #reset-cells = <1>; <<
1799 }; <<
1800 <<
1801 remoteproc_mpss: remoteproc@6 1115 remoteproc_mpss: remoteproc@6080000 {
1802 compatible = "qcom,qc 1116 compatible = "qcom,qcm2290-mpss-pas", "qcom,sm6115-mpss-pas";
1803 reg = <0x0 0x06080000 1117 reg = <0x0 0x06080000 0x0 0x100>;
1804 1118
1805 interrupts-extended = 1119 interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING>,
1806 1120 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1807 1121 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1808 1122 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1809 1123 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
1810 1124 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
1811 interrupt-names = "wd 1125 interrupt-names = "wdog",
1812 "fa 1126 "fatal",
1813 "re 1127 "ready",
1814 "ha 1128 "handover",
1815 "st 1129 "stop-ack",
1816 "sh 1130 "shutdown-ack";
1817 1131
1818 clocks = <&rpmcc RPM_ 1132 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
1819 clock-names = "xo"; 1133 clock-names = "xo";
1820 1134
1821 power-domains = <&rpm 1135 power-domains = <&rpmpd QCM2290_VDDCX>;
1822 1136
1823 memory-region = <&pil 1137 memory-region = <&pil_modem_mem>;
1824 1138
1825 qcom,smem-states = <& 1139 qcom,smem-states = <&modem_smp2p_out 0>;
1826 qcom,smem-state-names 1140 qcom,smem-state-names = "stop";
1827 1141
1828 status = "disabled"; 1142 status = "disabled";
1829 1143
1830 glink-edge { 1144 glink-edge {
1831 interrupts = 1145 interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>;
1832 label = "mpss 1146 label = "mpss";
1833 qcom,remote-p 1147 qcom,remote-pid = <1>;
1834 mboxes = <&ap 1148 mboxes = <&apcs_glb 12>;
1835 }; 1149 };
1836 }; 1150 };
1837 1151
1838 remoteproc_adsp: remoteproc@a 1152 remoteproc_adsp: remoteproc@ab00000 {
1839 compatible = "qcom,qc 1153 compatible = "qcom,qcm2290-adsp-pas", "qcom,sm6115-adsp-pas";
1840 reg = <0x0 0x0ab00000 1154 reg = <0x0 0x0ab00000 0x0 0x100>;
1841 1155
1842 interrupts-extended = 1156 interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_EDGE_RISING>,
1843 1157 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1844 1158 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1845 1159 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1846 1160 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1847 interrupt-names = "wd 1161 interrupt-names = "wdog",
1848 "fa 1162 "fatal",
1849 "re 1163 "ready",
1850 "ha 1164 "handover",
1851 "st 1165 "stop-ack";
1852 1166
1853 clocks = <&rpmcc RPM_ 1167 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
1854 clock-names = "xo"; 1168 clock-names = "xo";
1855 1169
1856 power-domains = <&rpm 1170 power-domains = <&rpmpd QCM2290_VDD_LPI_CX>,
1857 <&rpm 1171 <&rpmpd QCM2290_VDD_LPI_MX>;
1858 1172
1859 memory-region = <&pil 1173 memory-region = <&pil_adsp_mem>;
1860 1174
1861 qcom,smem-states = <& 1175 qcom,smem-states = <&adsp_smp2p_out 0>;
1862 qcom,smem-state-names 1176 qcom,smem-state-names = "stop";
1863 1177
1864 status = "disabled"; 1178 status = "disabled";
1865 1179
1866 glink-edge { 1180 glink-edge {
1867 interrupts = 1181 interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>;
1868 label = "lpas 1182 label = "lpass";
1869 qcom,remote-p 1183 qcom,remote-pid = <2>;
1870 mboxes = <&ap 1184 mboxes = <&apcs_glb 8>;
1871 }; 1185 };
1872 }; 1186 };
1873 1187
1874 apps_smmu: iommu@c600000 { 1188 apps_smmu: iommu@c600000 {
1875 compatible = "qcom,qc 1189 compatible = "qcom,qcm2290-smmu-500", "qcom,smmu-500", "arm,mmu-500";
1876 reg = <0x0 0x0c600000 1190 reg = <0x0 0x0c600000 0x0 0x80000>;
1877 #iommu-cells = <2>; 1191 #iommu-cells = <2>;
1878 #global-interrupts = 1192 #global-interrupts = <1>;
1879 1193
1880 interrupts = <GIC_SPI 1194 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
1881 <GIC_SPI 1195 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
1882 <GIC_SPI 1196 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1883 <GIC_SPI 1197 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
1884 <GIC_SPI 1198 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
1885 <GIC_SPI 1199 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
1886 <GIC_SPI 1200 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
1887 <GIC_SPI 1201 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
1888 <GIC_SPI 1202 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
1889 <GIC_SPI 1203 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
1890 <GIC_SPI 1204 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
1891 <GIC_SPI 1205 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
1892 <GIC_SPI 1206 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
1893 <GIC_SPI 1207 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
1894 <GIC_SPI 1208 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1895 <GIC_SPI 1209 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1896 <GIC_SPI 1210 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1897 <GIC_SPI 1211 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1898 <GIC_SPI 1212 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1899 <GIC_SPI 1213 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
1900 <GIC_SPI 1214 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1901 <GIC_SPI 1215 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
1902 <GIC_SPI 1216 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1903 <GIC_SPI 1217 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1904 <GIC_SPI 1218 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
1905 <GIC_SPI 1219 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
1906 <GIC_SPI 1220 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
1907 <GIC_SPI 1221 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
1908 <GIC_SPI 1222 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
1909 <GIC_SPI 1223 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
1910 <GIC_SPI 1224 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1911 <GIC_SPI 1225 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1912 <GIC_SPI 1226 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1913 <GIC_SPI 1227 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1914 <GIC_SPI 1228 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1915 <GIC_SPI 1229 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1916 <GIC_SPI 1230 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
1917 <GIC_SPI 1231 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1918 <GIC_SPI 1232 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1919 <GIC_SPI 1233 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1920 <GIC_SPI 1234 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
1921 <GIC_SPI 1235 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
1922 <GIC_SPI 1236 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
1923 <GIC_SPI 1237 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
1924 <GIC_SPI 1238 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
1925 <GIC_SPI 1239 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
1926 <GIC_SPI 1240 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
1927 <GIC_SPI 1241 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
1928 <GIC_SPI 1242 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
1929 <GIC_SPI 1243 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1930 <GIC_SPI 1244 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
1931 <GIC_SPI 1245 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
1932 <GIC_SPI 1246 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
1933 <GIC_SPI 1247 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
1934 <GIC_SPI 1248 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
1935 <GIC_SPI 1249 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
1936 <GIC_SPI 1250 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
1937 <GIC_SPI 1251 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
1938 <GIC_SPI 1252 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
1939 <GIC_SPI 1253 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1940 <GIC_SPI 1254 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1941 <GIC_SPI 1255 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
1942 <GIC_SPI 1256 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
1943 <GIC_SPI 1257 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
1944 <GIC_SPI 1258 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
1945 }; 1259 };
1946 1260
1947 wifi: wifi@c800000 { 1261 wifi: wifi@c800000 {
1948 compatible = "qcom,wc 1262 compatible = "qcom,wcn3990-wifi";
1949 reg = <0x0 0x0c800000 1263 reg = <0x0 0x0c800000 0x0 0x800000>;
1950 reg-names = "membase" 1264 reg-names = "membase";
1951 memory-region = <&wla 1265 memory-region = <&wlan_msa_mem>;
1952 interrupts = <GIC_SPI 1266 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
1953 <GIC_SPI 1267 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
1954 <GIC_SPI 1268 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
1955 <GIC_SPI 1269 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
1956 <GIC_SPI 1270 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
1957 <GIC_SPI 1271 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>,
1958 <GIC_SPI 1272 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
1959 <GIC_SPI 1273 <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,
1960 <GIC_SPI 1274 <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
1961 <GIC_SPI 1275 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
1962 <GIC_SPI 1276 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
1963 <GIC_SPI 1277 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
1964 iommus = <&apps_smmu 1278 iommus = <&apps_smmu 0x1a0 0x1>;
1965 qcom,msa-fixed-perm; 1279 qcom,msa-fixed-perm;
1966 status = "disabled"; 1280 status = "disabled";
1967 }; 1281 };
1968 1282
1969 watchdog@f017000 { 1283 watchdog@f017000 {
1970 compatible = "qcom,ap 1284 compatible = "qcom,apss-wdt-qcm2290", "qcom,kpss-wdt";
1971 reg = <0x0 0x0f017000 1285 reg = <0x0 0x0f017000 0x0 0x1000>;
1972 interrupts = <GIC_SPI 1286 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>,
1973 <GIC_SPI 1287 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1974 clocks = <&sleep_clk> 1288 clocks = <&sleep_clk>;
1975 }; 1289 };
1976 1290
1977 apcs_glb: mailbox@f111000 { 1291 apcs_glb: mailbox@f111000 {
1978 compatible = "qcom,qc 1292 compatible = "qcom,qcm2290-apcs-hmss-global";
1979 reg = <0x0 0x0f111000 1293 reg = <0x0 0x0f111000 0x0 0x1000>;
1980 #mbox-cells = <1>; 1294 #mbox-cells = <1>;
1981 }; 1295 };
1982 1296
1983 timer@f120000 { 1297 timer@f120000 {
1984 compatible = "arm,arm 1298 compatible = "arm,armv7-timer-mem";
1985 reg = <0x0 0x0f120000 1299 reg = <0x0 0x0f120000 0x0 0x1000>;
1986 #address-cells = <1>; 1300 #address-cells = <1>;
1987 #size-cells = <1>; 1301 #size-cells = <1>;
1988 ranges = <0 0x0 0x0f1 1302 ranges = <0 0x0 0x0f121000 0x8000>;
1989 1303
1990 frame@0 { 1304 frame@0 {
1991 reg = <0x0 0x 1305 reg = <0x0 0x1000>,
1992 <0x1000 1306 <0x1000 0x1000>;
1993 interrupts = 1307 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
1994 1308 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1995 frame-number 1309 frame-number = <0>;
1996 }; 1310 };
1997 1311
1998 frame@2000 { 1312 frame@2000 {
1999 reg = <0x2000 1313 reg = <0x2000 0x1000>;
2000 interrupts = 1314 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
2001 frame-number 1315 frame-number = <1>;
2002 status = "dis 1316 status = "disabled";
2003 }; 1317 };
2004 1318
2005 frame@3000 { 1319 frame@3000 {
2006 reg = <0x3000 1320 reg = <0x3000 0x1000>;
2007 interrupts = 1321 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
2008 frame-number 1322 frame-number = <2>;
2009 status = "dis 1323 status = "disabled";
2010 }; 1324 };
2011 1325
2012 frame@4000 { 1326 frame@4000 {
2013 reg = <0x4000 1327 reg = <0x4000 0x1000>;
2014 interrupts = 1328 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
2015 frame-number 1329 frame-number = <3>;
2016 status = "dis 1330 status = "disabled";
2017 }; 1331 };
2018 1332
2019 frame@5000 { 1333 frame@5000 {
2020 reg = <0x5000 1334 reg = <0x5000 0x1000>;
2021 interrupts = 1335 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
2022 frame-number 1336 frame-number = <4>;
2023 status = "dis 1337 status = "disabled";
2024 }; 1338 };
2025 1339
2026 frame@6000 { 1340 frame@6000 {
2027 reg = <0x6000 1341 reg = <0x6000 0x1000>;
2028 interrupts = 1342 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
2029 frame-number 1343 frame-number = <5>;
2030 status = "dis 1344 status = "disabled";
2031 }; 1345 };
2032 1346
2033 frame@7000 { 1347 frame@7000 {
2034 reg = <0x7000 1348 reg = <0x7000 0x1000>;
2035 interrupts = 1349 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
2036 frame-number 1350 frame-number = <6>;
2037 status = "dis 1351 status = "disabled";
2038 }; 1352 };
2039 }; 1353 };
2040 1354
2041 intc: interrupt-controller@f2 1355 intc: interrupt-controller@f200000 {
2042 compatible = "arm,gic 1356 compatible = "arm,gic-v3";
2043 reg = <0x0 0x0f200000 1357 reg = <0x0 0x0f200000 0x0 0x10000>,
2044 <0x0 0x0f300000 1358 <0x0 0x0f300000 0x0 0x100000>;
2045 interrupts = <GIC_PPI 1359 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
2046 #interrupt-cells = <3 1360 #interrupt-cells = <3>;
2047 interrupt-controller; 1361 interrupt-controller;
2048 interrupt-parent = <& 1362 interrupt-parent = <&intc>;
2049 #redistributor-region 1363 #redistributor-regions = <1>;
2050 redistributor-stride 1364 redistributor-stride = <0x0 0x20000>;
2051 }; 1365 };
2052 1366
2053 cpufreq_hw: cpufreq@f521000 { 1367 cpufreq_hw: cpufreq@f521000 {
2054 compatible = "qcom,qc 1368 compatible = "qcom,qcm2290-cpufreq-hw", "qcom,cpufreq-hw";
2055 reg = <0x0 0x0f521000 1369 reg = <0x0 0x0f521000 0x0 0x1000>;
2056 reg-names = "freq-dom 1370 reg-names = "freq-domain0";
2057 interrupts-extended = !! 1371 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
2058 interrupt-names = "dc 1372 interrupt-names = "dcvsh-irq-0";
2059 clocks = <&rpmcc RPM_ 1373 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>;
2060 clock-names = "xo", " 1374 clock-names = "xo", "alternate";
2061 1375
2062 #freq-domain-cells = 1376 #freq-domain-cells = <1>;
2063 #clock-cells = <1>; 1377 #clock-cells = <1>;
2064 }; 1378 };
2065 <<
2066 lmh_cluster: lmh@f550800 { <<
2067 compatible = "qcom,qc <<
2068 reg = <0x0 0x0f550800 <<
2069 interrupts = <GIC_SPI <<
2070 cpus = <&CPU0>; <<
2071 qcom,lmh-temp-arm-mil <<
2072 qcom,lmh-temp-low-mil <<
2073 qcom,lmh-temp-high-mi <<
2074 interrupt-controller; <<
2075 #interrupt-cells = <1 <<
2076 }; <<
2077 }; 1379 };
2078 1380
2079 thermal-zones { 1381 thermal-zones {
2080 mapss-thermal { 1382 mapss-thermal {
>> 1383 polling-delay-passive = <0>;
>> 1384 polling-delay = <0>;
>> 1385
2081 thermal-sensors = <&t 1386 thermal-sensors = <&tsens0 0>;
2082 1387
2083 trips { 1388 trips {
2084 mapss_alert0: 1389 mapss_alert0: trip-point0 {
2085 tempe 1390 temperature = <90000>;
2086 hyste 1391 hysteresis = <2000>;
2087 type 1392 type = "passive";
2088 }; 1393 };
2089 1394
2090 mapss_alert1: 1395 mapss_alert1: trip-point1 {
2091 tempe 1396 temperature = <95000>;
2092 hyste 1397 hysteresis = <2000>;
2093 type 1398 type = "passive";
2094 }; 1399 };
2095 1400
2096 mapss_crit: m 1401 mapss_crit: mapss-crit {
2097 tempe 1402 temperature = <110000>;
2098 hyste 1403 hysteresis = <1000>;
2099 type 1404 type = "critical";
2100 }; 1405 };
2101 }; 1406 };
2102 }; 1407 };
2103 1408
2104 video-thermal { 1409 video-thermal {
>> 1410 polling-delay-passive = <0>;
>> 1411 polling-delay = <0>;
>> 1412
2105 thermal-sensors = <&t 1413 thermal-sensors = <&tsens0 1>;
2106 1414
2107 trips { 1415 trips {
2108 video_alert0: 1416 video_alert0: trip-point0 {
2109 tempe 1417 temperature = <90000>;
2110 hyste 1418 hysteresis = <2000>;
2111 type 1419 type = "passive";
2112 }; 1420 };
2113 1421
2114 video_alert1: 1422 video_alert1: trip-point1 {
2115 tempe 1423 temperature = <95000>;
2116 hyste 1424 hysteresis = <2000>;
2117 type 1425 type = "passive";
2118 }; 1426 };
2119 1427
2120 video_crit: v 1428 video_crit: video-crit {
2121 tempe 1429 temperature = <110000>;
2122 hyste 1430 hysteresis = <1000>;
2123 type 1431 type = "critical";
2124 }; 1432 };
2125 }; 1433 };
2126 }; 1434 };
2127 1435
2128 wlan-thermal { 1436 wlan-thermal {
>> 1437 polling-delay-passive = <0>;
>> 1438 polling-delay = <0>;
>> 1439
2129 thermal-sensors = <&t 1440 thermal-sensors = <&tsens0 2>;
2130 1441
2131 trips { 1442 trips {
2132 wlan_alert0: 1443 wlan_alert0: trip-point0 {
2133 tempe 1444 temperature = <90000>;
2134 hyste 1445 hysteresis = <2000>;
2135 type 1446 type = "passive";
2136 }; 1447 };
2137 1448
2138 wlan_alert1: 1449 wlan_alert1: trip-point1 {
2139 tempe 1450 temperature = <95000>;
2140 hyste 1451 hysteresis = <2000>;
2141 type 1452 type = "passive";
2142 }; 1453 };
2143 1454
2144 wlan_crit: wl 1455 wlan_crit: wlan-crit {
2145 tempe 1456 temperature = <110000>;
2146 hyste 1457 hysteresis = <1000>;
2147 type 1458 type = "critical";
2148 }; 1459 };
2149 }; 1460 };
2150 }; 1461 };
2151 1462
2152 cpuss0-thermal { 1463 cpuss0-thermal {
>> 1464 polling-delay-passive = <0>;
>> 1465 polling-delay = <0>;
>> 1466
2153 thermal-sensors = <&t 1467 thermal-sensors = <&tsens0 3>;
2154 1468
2155 trips { 1469 trips {
2156 cpuss0_alert0 1470 cpuss0_alert0: trip-point0 {
2157 tempe 1471 temperature = <90000>;
2158 hyste 1472 hysteresis = <2000>;
2159 type 1473 type = "passive";
2160 }; 1474 };
2161 1475
2162 cpuss0_alert1 1476 cpuss0_alert1: trip-point1 {
2163 tempe 1477 temperature = <95000>;
2164 hyste 1478 hysteresis = <2000>;
2165 type 1479 type = "passive";
2166 }; 1480 };
2167 1481
2168 cpuss0_crit: 1482 cpuss0_crit: cpuss0-crit {
2169 tempe 1483 temperature = <110000>;
2170 hyste 1484 hysteresis = <1000>;
2171 type 1485 type = "critical";
2172 }; 1486 };
2173 }; 1487 };
2174 }; 1488 };
2175 1489
2176 cpuss1-thermal { 1490 cpuss1-thermal {
>> 1491 polling-delay-passive = <0>;
>> 1492 polling-delay = <0>;
>> 1493
2177 thermal-sensors = <&t 1494 thermal-sensors = <&tsens0 4>;
2178 1495
2179 trips { 1496 trips {
2180 cpuss1_alert0 1497 cpuss1_alert0: trip-point0 {
2181 tempe 1498 temperature = <90000>;
2182 hyste 1499 hysteresis = <2000>;
2183 type 1500 type = "passive";
2184 }; 1501 };
2185 1502
2186 cpuss1_alert1 1503 cpuss1_alert1: trip-point1 {
2187 tempe 1504 temperature = <95000>;
2188 hyste 1505 hysteresis = <2000>;
2189 type 1506 type = "passive";
2190 }; 1507 };
2191 1508
2192 cpuss1_crit: 1509 cpuss1_crit: cpuss1-crit {
2193 tempe 1510 temperature = <110000>;
2194 hyste 1511 hysteresis = <1000>;
2195 type 1512 type = "critical";
2196 }; 1513 };
2197 }; 1514 };
2198 }; 1515 };
2199 1516
2200 mdm0-thermal { 1517 mdm0-thermal {
>> 1518 polling-delay-passive = <0>;
>> 1519 polling-delay = <0>;
>> 1520
2201 thermal-sensors = <&t 1521 thermal-sensors = <&tsens0 5>;
2202 1522
2203 trips { 1523 trips {
2204 mdm0_alert0: 1524 mdm0_alert0: trip-point0 {
2205 tempe 1525 temperature = <90000>;
2206 hyste 1526 hysteresis = <2000>;
2207 type 1527 type = "passive";
2208 }; 1528 };
2209 1529
2210 mdm0_alert1: 1530 mdm0_alert1: trip-point1 {
2211 tempe 1531 temperature = <95000>;
2212 hyste 1532 hysteresis = <2000>;
2213 type 1533 type = "passive";
2214 }; 1534 };
2215 1535
2216 mdm0_crit: md 1536 mdm0_crit: mdm0-crit {
2217 tempe 1537 temperature = <110000>;
2218 hyste 1538 hysteresis = <1000>;
2219 type 1539 type = "critical";
2220 }; 1540 };
2221 }; 1541 };
2222 }; 1542 };
2223 1543
2224 mdm1-thermal { 1544 mdm1-thermal {
>> 1545 polling-delay-passive = <0>;
>> 1546 polling-delay = <0>;
>> 1547
2225 thermal-sensors = <&t 1548 thermal-sensors = <&tsens0 6>;
2226 1549
2227 trips { 1550 trips {
2228 mdm1_alert0: 1551 mdm1_alert0: trip-point0 {
2229 tempe 1552 temperature = <90000>;
2230 hyste 1553 hysteresis = <2000>;
2231 type 1554 type = "passive";
2232 }; 1555 };
2233 1556
2234 mdm1_alert1: 1557 mdm1_alert1: trip-point1 {
2235 tempe 1558 temperature = <95000>;
2236 hyste 1559 hysteresis = <2000>;
2237 type 1560 type = "passive";
2238 }; 1561 };
2239 1562
2240 mdm1_crit: md 1563 mdm1_crit: mdm1-crit {
2241 tempe 1564 temperature = <110000>;
2242 hyste 1565 hysteresis = <1000>;
2243 type 1566 type = "critical";
2244 }; 1567 };
2245 }; 1568 };
2246 }; 1569 };
2247 1570
2248 gpu-thermal { 1571 gpu-thermal {
>> 1572 polling-delay-passive = <0>;
>> 1573 polling-delay = <0>;
>> 1574
2249 thermal-sensors = <&t 1575 thermal-sensors = <&tsens0 7>;
2250 1576
2251 trips { 1577 trips {
2252 gpu_alert0: t 1578 gpu_alert0: trip-point0 {
2253 tempe 1579 temperature = <90000>;
2254 hyste 1580 hysteresis = <2000>;
2255 type 1581 type = "passive";
2256 }; 1582 };
2257 1583
2258 gpu_alert1: t 1584 gpu_alert1: trip-point1 {
2259 tempe 1585 temperature = <95000>;
2260 hyste 1586 hysteresis = <2000>;
2261 type 1587 type = "passive";
2262 }; 1588 };
2263 1589
2264 gpu_crit: gpu 1590 gpu_crit: gpu-crit {
2265 tempe 1591 temperature = <110000>;
2266 hyste 1592 hysteresis = <1000>;
2267 type 1593 type = "critical";
2268 }; 1594 };
2269 }; 1595 };
2270 }; 1596 };
2271 1597
2272 hm-center-thermal { 1598 hm-center-thermal {
>> 1599 polling-delay-passive = <0>;
>> 1600 polling-delay = <0>;
>> 1601
2273 thermal-sensors = <&t 1602 thermal-sensors = <&tsens0 8>;
2274 1603
2275 trips { 1604 trips {
2276 hm_center_ale 1605 hm_center_alert0: trip-point0 {
2277 tempe 1606 temperature = <90000>;
2278 hyste 1607 hysteresis = <2000>;
2279 type 1608 type = "passive";
2280 }; 1609 };
2281 1610
2282 hm_center_ale 1611 hm_center_alert1: trip-point1 {
2283 tempe 1612 temperature = <95000>;
2284 hyste 1613 hysteresis = <2000>;
2285 type 1614 type = "passive";
2286 }; 1615 };
2287 1616
2288 hm_center_cri 1617 hm_center_crit: hm-center-crit {
2289 tempe 1618 temperature = <110000>;
2290 hyste 1619 hysteresis = <1000>;
2291 type 1620 type = "critical";
2292 }; 1621 };
2293 }; 1622 };
2294 }; 1623 };
2295 1624
2296 camera-thermal { 1625 camera-thermal {
>> 1626 polling-delay-passive = <0>;
>> 1627 polling-delay = <0>;
>> 1628
2297 thermal-sensors = <&t 1629 thermal-sensors = <&tsens0 9>;
2298 1630
2299 trips { 1631 trips {
2300 camera_alert0 1632 camera_alert0: trip-point0 {
2301 tempe 1633 temperature = <90000>;
2302 hyste 1634 hysteresis = <2000>;
2303 type 1635 type = "passive";
2304 }; 1636 };
2305 1637
2306 camera_alert1 1638 camera_alert1: trip-point1 {
2307 tempe 1639 temperature = <95000>;
2308 hyste 1640 hysteresis = <2000>;
2309 type 1641 type = "passive";
2310 }; 1642 };
2311 1643
2312 camera_crit: 1644 camera_crit: camera-crit {
2313 tempe 1645 temperature = <110000>;
2314 hyste 1646 hysteresis = <1000>;
2315 type 1647 type = "critical";
2316 }; 1648 };
2317 }; 1649 };
2318 }; 1650 };
2319 }; 1651 };
2320 1652
2321 timer { 1653 timer {
2322 compatible = "arm,armv8-timer 1654 compatible = "arm,armv8-timer";
2323 interrupts = <GIC_PPI 1 (GIC_ 1655 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2324 <GIC_PPI 2 (GIC_ 1656 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2325 <GIC_PPI 3 (GIC_ 1657 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2326 <GIC_PPI 0 (GIC_ 1658 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
2327 }; 1659 };
2328 }; 1660 };
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