1 // SPDX-License-Identifier: BSD-3-Clause
2 /*
3 * Copyright (c) 2022 Qualcomm Innovation Cent
4 */
5
6 #include <dt-bindings/clock/qcom,qdu1000-gcc.h
7 #include <dt-bindings/clock/qcom,rpmh.h>
8 #include <dt-bindings/dma/qcom-gpi.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interconnect/qcom,icc.h>
11 #include <dt-bindings/interconnect/qcom,qdu100
12 #include <dt-bindings/interrupt-controller/arm
13 #include <dt-bindings/power/qcom-rpmpd.h>
14 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
15
16 / {
17 interrupt-parent = <&intc>;
18
19 #address-cells = <2>;
20 #size-cells = <2>;
21
22 chosen: chosen { };
23
24 cpus {
25 #address-cells = <2>;
26 #size-cells = <0>;
27
28 CPU0: cpu@0 {
29 device_type = "cpu";
30 compatible = "arm,cort
31 reg = <0x0 0x0>;
32 clocks = <&cpufreq_hw
33 enable-method = "psci"
34 power-domains = <&CPU_
35 power-domain-names = "
36 qcom,freq-domains = <&
37 next-level-cache = <&L
38 L2_0: l2-cache {
39 compatible = "
40 cache-level =
41 cache-unified;
42 next-level-cac
43 L3_0: l3-cache
44 compat
45 cache-
46 cache-
47 };
48 };
49 };
50
51 CPU1: cpu@100 {
52 device_type = "cpu";
53 compatible = "arm,cort
54 reg = <0x0 0x100>;
55 clocks = <&cpufreq_hw
56 enable-method = "psci"
57 power-domains = <&CPU_
58 power-domain-names = "
59 qcom,freq-domains = <&
60 next-level-cache = <&L
61 L2_100: l2-cache {
62 compatible = "
63 cache-level =
64 cache-unified;
65 next-level-cac
66 };
67 };
68
69 CPU2: cpu@200 {
70 device_type = "cpu";
71 compatible = "arm,cort
72 reg = <0x0 0x200>;
73 clocks = <&cpufreq_hw
74 enable-method = "psci"
75 power-domains = <&CPU_
76 power-domain-names = "
77 qcom,freq-domains = <&
78 next-level-cache = <&L
79 L2_200: l2-cache {
80 compatible = "
81 cache-level =
82 cache-unified;
83 next-level-cac
84 };
85 };
86
87 CPU3: cpu@300 {
88 device_type = "cpu";
89 compatible = "arm,cort
90 reg = <0x0 0x300>;
91 clocks = <&cpufreq_hw
92 enable-method = "psci"
93 power-domains = <&CPU_
94 power-domain-names = "
95 qcom,freq-domains = <&
96 next-level-cache = <&L
97 L2_300: l2-cache {
98 compatible = "
99 cache-level =
100 cache-unified;
101 next-level-cac
102 };
103 };
104
105 cpu-map {
106 cluster0 {
107 core0 {
108 cpu =
109 };
110
111 core1 {
112 cpu =
113 };
114
115 core2 {
116 cpu =
117 };
118
119 core3 {
120 cpu =
121 };
122 };
123 };
124 };
125
126 idle-states {
127 entry-method = "psci";
128
129 CPU_OFF: cpu-sleep-0 {
130 compatible = "arm,idle
131 entry-latency-us = <27
132 exit-latency-us = <480
133 min-residency-us = <39
134 arm,psci-suspend-param
135 local-timer-stop;
136 };
137 };
138
139 domain-idle-states {
140 CLUSTER_SLEEP_0: cluster-sleep
141 compatible = "domain-i
142 entry-latency-us = <58
143 exit-latency-us = <233
144 min-residency-us = <61
145 arm,psci-suspend-param
146 };
147
148 CLUSTER_SLEEP_1: cluster-sleep
149 compatible = "domain-i
150 entry-latency-us = <28
151 exit-latency-us = <402
152 min-residency-us = <99
153 arm,psci-suspend-param
154 };
155 };
156
157 firmware {
158 scm {
159 compatible = "qcom,scm
160 };
161 };
162
163 mc_virt: interconnect-0 {
164 compatible = "qcom,qdu1000-mc-
165 qcom,bcm-voters = <&apps_bcm_v
166 #interconnect-cells = <2>;
167 };
168
169 clk_virt: interconnect-1 {
170 compatible = "qcom,qdu1000-clk
171 qcom,bcm-voters = <&apps_bcm_v
172 #interconnect-cells = <2>;
173 };
174
175 memory@80000000 {
176 device_type = "memory";
177 /* We expect the bootloader to
178 reg = <0x0 0x80000000 0x0 0x0>
179 };
180
181 pmu {
182 compatible = "arm,cortex-a55-p
183 interrupts = <GIC_PPI 7 IRQ_TY
184 };
185
186 psci {
187 compatible = "arm,psci-1.0";
188 method = "smc";
189
190 CPU_PD0: power-domain-cpu0 {
191 #power-domain-cells =
192 power-domains = <&CLUS
193 domain-idle-states = <
194 };
195
196 CPU_PD1: power-domain-cpu1 {
197 #power-domain-cells =
198 power-domains = <&CLUS
199 domain-idle-states = <
200 };
201
202 CPU_PD2: power-domain-cpu2 {
203 #power-domain-cells =
204 power-domains = <&CLUS
205 domain-idle-states = <
206 };
207
208 CPU_PD3: power-domain-cpu3 {
209 #power-domain-cells =
210 power-domains = <&CLUS
211 domain-idle-states = <
212 };
213
214 CLUSTER_PD: power-domain-clust
215 #power-domain-cells =
216 domain-idle-states = <
217 };
218 };
219
220 reserved_memory: reserved-memory {
221 #address-cells = <2>;
222 #size-cells = <2>;
223 ranges;
224
225 hyp_mem: hyp@80000000 {
226 reg = <0x0 0x80000000
227 no-map;
228 };
229
230 xbl_dt_log_mem: xbl-dt-log@806
231 reg = <0x0 0x80600000
232 no-map;
233 };
234
235 xbl_ramdump_mem: xbl-ramdump@8
236 reg = <0x0 0x80640000
237 no-map;
238 };
239
240 aop_image_mem: aop-image@80800
241 reg = <0x0 0x80800000
242 no-map;
243 };
244
245 aop_cmd_db_mem: aop-cmd-db@808
246 compatible = "qcom,cmd
247 reg = <0x0 0x80860000
248 no-map;
249 };
250
251 aop_config_mem: aop-config@808
252 reg = <0x0 0x80880000
253 no-map;
254 };
255
256 tme_crash_dump_mem: tme-crash-
257 reg = <0x0 0x808a0000
258 no-map;
259 };
260
261 tme_log_mem: tme-log@808e0000
262 reg = <0x0 0x808e0000
263 no-map;
264 };
265
266 uefi_log_mem: uefi-log@808e400
267 reg = <0x0 0x808e4000
268 no-map;
269 };
270
271 smem_mem: smem@80900000 {
272 compatible = "qcom,sme
273 reg = <0x0 0x80900000
274 no-map;
275 hwlocks = <&tcsr_mutex
276 };
277
278 cpucp_fw_mem: cpucp-fw@80b0000
279 reg = <0x0 0x80b00000
280 no-map;
281 };
282
283 xbl_sc_mem: memory@80c00000 {
284 reg = <0x0 0x80c00000
285 no-map;
286 };
287
288 tz_stat_mem: tz-stat@81d00000
289 reg = <0x0 0x81d00000
290 no-map;
291 };
292
293 tags_mem: tags@81e00000 {
294 reg = <0x0 0x81e00000
295 no-map;
296 };
297
298 qtee_mem: qtee@82300000 {
299 reg = <0x0 0x82300000
300 no-map;
301 };
302
303 ta_mem: ta@82800000 {
304 reg = <0x0 0x82800000
305 no-map;
306 };
307
308 fs1_mem: fs1@83200000 {
309 reg = <0x0 0x83200000
310 no-map;
311 };
312
313 fs2_mem: fs2@83600000 {
314 reg = <0x0 0x83600000
315 no-map;
316 };
317
318 fs3_mem: fs3@83a00000 {
319 reg = <0x0 0x83a00000
320 no-map;
321 };
322
323 /* Linux kernel image is loade
324
325 ipa_fw_mem: ipa-fw@8be00000 {
326 reg = <0x0 0x8be00000
327 no-map;
328 };
329
330 ipa_gsi_mem: ipa-gsi@8be10000
331 reg = <0x0 0x8be10000
332 no-map;
333 };
334
335 mpss_mem: mpss@8c000000 {
336 reg = <0x0 0x8c000000
337 no-map;
338 };
339
340 q6_mpss_dtb_mem: q6-mpss-dtb@9
341 reg = <0x0 0x9ec00000
342 no-map;
343 };
344
345 tenx_mem: tenx@a0000000 {
346 reg = <0x0 0xa0000000
347 no-map;
348 };
349
350 oem_tenx_mem: oem-tenx@b960000
351 reg = <0x0 0xb9600000
352 no-map;
353 };
354
355 tenx_q6_buffer_mem: tenx-q6-bu
356 reg = <0x0 0xc0000000
357 no-map;
358 };
359
360 ipa_buffer_mem: ipa-buffer@c32
361 reg = <0x0 0xc3200000
362 no-map;
363 };
364 };
365
366 soc: soc@0 {
367 compatible = "simple-bus";
368 #address-cells = <2>;
369 #size-cells = <2>;
370 ranges = <0 0 0 0 0x10 0>;
371 dma-ranges = <0 0 0 0 0x10 0>;
372
373 gcc: clock-controller@80000 {
374 compatible = "qcom,qdu
375 reg = <0x0 0x80000 0x0
376 clocks = <&rpmhcc RPMH
377 <&sleep_clk>,
378 <0>,
379 <0>,
380 <0>;
381 #clock-cells = <1>;
382 #reset-cells = <1>;
383 #power-domain-cells =
384 };
385
386 ecpricc: clock-controller@2800
387 compatible = "qcom,qdu
388 reg = <0x0 0x00280000
389 clocks = <&rpmhcc RPMH
390 <&gcc GCC_ECP
391 <&gcc GCC_ECP
392 <&gcc GCC_ECP
393 <&gcc GCC_ECP
394 <&gcc GCC_ECP
395 <&gcc GCC_ECP
396 #clock-cells = <1>;
397 #reset-cells = <1>;
398 };
399
400 gpi_dma0: dma-controller@90000
401 compatible = "qcom,qdu
402 reg = <0x0 0x900000 0x
403 interrupts = <GIC_SPI
404 <GIC_SPI
405 <GIC_SPI
406 <GIC_SPI
407 <GIC_SPI
408 <GIC_SPI
409 <GIC_SPI
410 <GIC_SPI
411 <GIC_SPI
412 <GIC_SPI
413 <GIC_SPI
414 <GIC_SPI
415 dma-channels = <12>;
416 dma-channel-mask = <0x
417 iommus = <&apps_smmu 0
418 #dma-cells = <3>;
419 };
420
421 qupv3_id_0: geniqup@9c0000 {
422 compatible = "qcom,gen
423 reg = <0x0 0x9c0000 0x
424 clocks = <&gcc GCC_QUP
425 <&gcc GCC_QUPV
426 clock-names = "m-ahb",
427 iommus = <&apps_smmu 0
428 interconnects = <&clk_
429 &clk_
430 interconnect-names = "
431
432 #address-cells = <2>;
433 #size-cells = <2>;
434 ranges;
435 status = "disabled";
436
437 uart0: serial@980000 {
438 compatible = "
439 reg = <0x0 0x9
440 clocks = <&gcc
441 clock-names =
442 pinctrl-0 = <&
443 pinctrl-names
444 interrupts = <
445 status = "disa
446 };
447
448 i2c1: i2c@984000 {
449 compatible = "
450 reg = <0x0 0x9
451 clocks = <&gcc
452 clock-names =
453 interrupts = <
454 pinctrl-0 = <&
455 pinctrl-names
456 #address-cells
457 #size-cells =
458 status = "disa
459 };
460
461 spi1: spi@984000 {
462 compatible = "
463 reg = <0x0 0x9
464 #address-cells
465 #size-cells =
466 interrupts = <
467 clocks = <&gcc
468 clock-names =
469 pinctrl-0 = <&
470 pinctrl-names
471 status = "disa
472 };
473
474 i2c2: i2c@988000 {
475 compatible = "
476 reg = <0x0 0x9
477 clocks = <&gcc
478 clock-names =
479 interrupts = <
480 pinctrl-0 = <&
481 pinctrl-names
482 #address-cells
483 #size-cells =
484 status = "disa
485 };
486
487 spi2: spi@988000 {
488 compatible = "
489 reg = <0x0 0x9
490 #address-cells
491 #size-cells =
492 interrupts = <
493 clocks = <&gcc
494 clock-names =
495 pinctrl-0 = <&
496 pinctrl-names
497 status = "disa
498 };
499
500 i2c3: i2c@98c000 {
501 compatible = "
502 reg = <0x0 0x9
503 clocks = <&gcc
504 clock-names =
505 interrupts = <
506 pinctrl-0 = <&
507 pinctrl-names
508 #address-cells
509 #size-cells =
510 status = "disa
511 };
512
513 spi3: spi@98c000 {
514 compatible = "
515 reg = <0x0 0x9
516 #address-cells
517 #size-cells =
518 interrupts = <
519 clocks = <&gcc
520 clock-names =
521 pinctrl-0 = <&
522 pinctrl-names
523 status = "disa
524 };
525
526 i2c4: i2c@990000 {
527 compatible = "
528 reg = <0x0 0x9
529 clocks = <&gcc
530 clock-names =
531 interrupts = <
532 pinctrl-0 = <&
533 pinctrl-names
534 #address-cells
535 #size-cells =
536 status = "disa
537 };
538
539 spi4: spi@990000 {
540 compatible = "
541 reg = <0x0 0x9
542 #address-cells
543 #size-cells =
544 interrupts = <
545 clocks = <&gcc
546 clock-names =
547 pinctrl-0 = <&
548 pinctrl-names
549 status = "disa
550 };
551
552 i2c5: i2c@994000 {
553 compatible = "
554 reg = <0x0 0x9
555 clocks = <&gcc
556 clock-names =
557 interrupts = <
558 pinctrl-0 = <&
559 pinctrl-names
560 #address-cells
561 #size-cells =
562 status = "disa
563 };
564
565 spi5: spi@994000 {
566 compatible = "
567 reg = <0x0 0x9
568 #address-cells
569 #size-cells =
570 interrupts = <
571 clocks = <&gcc
572 clock-names =
573 pinctrl-0 = <&
574 pinctrl-names
575 status = "disa
576 };
577
578 i2c6: i2c@998000 {
579 compatible = "
580 reg = <0x0 0x9
581 clocks = <&gcc
582 clock-names =
583 interrupts = <
584 pinctrl-0 = <&
585 pinctrl-names
586 #address-cells
587 #size-cells =
588 status = "disa
589 };
590
591 spi6: spi@998000 {
592 compatible = "
593 reg = <0x0 0x9
594 #address-cells
595 #size-cells =
596 interrupts = <
597 clocks = <&gcc
598 clock-names =
599 pinctrl-0 = <&
600 pinctrl-names
601 status = "disa
602 };
603
604 uart7: serial@99c000 {
605 compatible = "
606 reg = <0x0 0x9
607 clocks = <&gcc
608 clock-names =
609 pinctrl-0 = <&
610 pinctrl-names
611 interrupts = <
612 status = "disa
613 };
614 };
615
616 gpi_dma1: dma-controller@a0000
617 compatible = "qcom,qdu
618 reg = <0x0 0xa00000 0x
619 interrupts = <GIC_SPI
620 <GIC_SPI
621 <GIC_SPI
622 <GIC_SPI
623 <GIC_SPI
624 <GIC_SPI
625 <GIC_SPI
626 <GIC_SPI
627 <GIC_SPI
628 <GIC_SPI
629 <GIC_SPI
630 <GIC_SPI
631 dma-channels = <12>;
632 dma-channel-mask = <0x
633 iommus = <&apps_smmu 0
634 #dma-cells = <3>;
635 };
636
637 qupv3_id_1: geniqup@ac0000 {
638 compatible = "qcom,gen
639 reg = <0x0 0xac0000 0x
640 clocks = <&gcc GCC_QUP
641 <&gcc GCC_QUPV
642 clock-names = "m-ahb",
643 iommus = <&apps_smmu 0
644 #address-cells = <2>;
645 #size-cells = <2>;
646 ranges;
647 status = "disabled";
648
649 uart8: serial@a80000 {
650 compatible = "
651 reg = <0x0 0xa
652 clocks = <&gcc
653 clock-names =
654 pinctrl-0 = <&
655 pinctrl-names
656 interrupts = <
657 #address-cells
658 #size-cells =
659 status = "disa
660 };
661
662 i2c9: i2c@a84000 {
663 compatible = "
664 reg = <0x0 0xa
665 clocks = <&gcc
666 clock-names =
667 interrupts = <
668 pinctrl-0 = <&
669 pinctrl-names
670 #address-cells
671 #size-cells =
672 status = "disa
673 };
674
675 spi9: spi@a84000 {
676 compatible = "
677 reg = <0x0 0xa
678 #address-cells
679 #size-cells =
680 interrupts = <
681 clocks = <&gcc
682 clock-names =
683 pinctrl-0 = <&
684 pinctrl-names
685 status = "disa
686 };
687
688 i2c10: i2c@a88000 {
689 compatible = "
690 reg = <0x0 0xa
691 clocks = <&gcc
692 clock-names =
693 interrupts = <
694 pinctrl-0 = <&
695 pinctrl-names
696 #address-cells
697 #size-cells =
698 status = "disa
699 };
700
701 spi10: spi@a88000 {
702 compatible = "
703 reg = <0x0 0xa
704 #address-cells
705 #size-cells =
706 interrupts = <
707 clocks = <&gcc
708 clock-names =
709 pinctrl-0 = <&
710 pinctrl-names
711 status = "disa
712 };
713
714 i2c11: i2c@a8c000 {
715 compatible = "
716 reg = <0x0 0xa
717 clocks = <&gcc
718 clock-names =
719 interrupts = <
720 pinctrl-0 = <&
721 pinctrl-names
722 #address-cells
723 #size-cells =
724 status = "disa
725 };
726
727 spi11: spi@a8c000 {
728 compatible = "
729 reg = <0x0 0xa
730 #address-cells
731 #size-cells =
732 interrupts = <
733 clocks = <&gcc
734 clock-names =
735 pinctrl-0 = <&
736 pinctrl-names
737 status = "disa
738 };
739
740 i2c12: i2c@a90000 {
741 compatible = "
742 reg = <0x0 0xa
743 clocks = <&gcc
744 clock-names =
745 interrupts = <
746 pinctrl-0 = <&
747 pinctrl-names
748 #address-cells
749 #size-cells =
750 status = "disa
751 };
752
753 spi12: spi@a90000 {
754 compatible = "
755 reg = <0x0 0xa
756 #address-cells
757 #size-cells =
758 interrupts = <
759 clocks = <&gcc
760 clock-names =
761 pinctrl-0 = <&
762 pinctrl-names
763 status = "disa
764 };
765
766 i2c13: i2c@a94000 {
767 compatible = "
768 reg = <0x0 0xa
769 clocks = <&gcc
770 clock-names =
771 interrupts = <
772 pinctrl-0 = <&
773 pinctrl-names
774 #address-cells
775 #size-cells =
776 status = "disa
777 };
778
779 uart13: serial@a94000
780 compatible = "
781 reg = <0x0 0xa
782 clocks = <&gcc
783 clock-names =
784 pinctrl-0 = <&
785 pinctrl-names
786 interrupts = <
787 #address-cells
788 #size-cells =
789 status = "disa
790 };
791
792 spi13: spi@a94000 {
793 compatible = "
794 reg = <0x0 0xa
795 #address-cells
796 #size-cells =
797 interrupts = <
798 clocks = <&gcc
799 clock-names =
800 pinctrl-0 = <&
801 pinctrl-names
802 status = "disa
803 };
804
805 i2c14: i2c@a98000 {
806 compatible = "
807 reg = <0x0 0xa
808 clocks = <&gcc
809 clock-names =
810 interrupts = <
811 pinctrl-0 = <&
812 pinctrl-names
813 #address-cells
814 #size-cells =
815 status = "disa
816 };
817
818 spi14: spi@a98000 {
819 compatible = "
820 reg = <0x0 0xa
821 #address-cells
822 #size-cells =
823 interrupts = <
824 clocks = <&gcc
825 clock-names =
826 pinctrl-0 = <&
827 pinctrl-names
828 status = "disa
829 };
830
831 i2c15: i2c@a9c000 {
832 compatible = "
833 reg = <0x0 0xa
834 clocks = <&gcc
835 clock-names =
836 interrupts = <
837 pinctrl-0 = <&
838 pinctrl-names
839 #address-cells
840 #size-cells =
841 status = "disa
842 };
843
844 spi15: spi@a9c000 {
845 compatible = "
846 reg = <0x0 0xa
847 #address-cells
848 #size-cells =
849 interrupts = <
850 clocks = <&gcc
851 clock-names =
852 pinctrl-0 = <&
853 pinctrl-names
854 status = "disa
855 };
856 };
857
858 system_noc: interconnect@16400
859 compatible = "qcom,qdu
860 reg = <0x0 0x1640000 0
861 qcom,bcm-voters = <&ap
862 #interconnect-cells =
863 };
864
865 tcsr_mutex: hwlock@1f40000 {
866 compatible = "qcom,tcs
867 reg = <0x0 0x1f40000 0
868 #hwlock-cells = <1>;
869 };
870
871 sdhc: mmc@8804000 {
872 compatible = "qcom,qdu
873 reg = <0x0 0x08804000
874 <0x0 0x08805000
875 reg-names = "hc", "cqh
876
877 interrupts = <GIC_SPI
878 <GIC_SPI
879 interrupt-names = "hc_
880
881 clocks = <&gcc GCC_SDC
882 <&gcc GCC_SDC
883 <&rpmhcc RPMH
884 clock-names = "iface",
885 "core",
886 "xo";
887
888 resets = <&gcc GCC_SDC
889
890 interconnects = <&syst
891 <&gem_
892 interconnect-names = "
893 power-domains = <&rpmh
894 operating-points-v2 =
895
896 iommus = <&apps_smmu 0
897 dma-coherent;
898
899 bus-width = <8>;
900
901 qcom,dll-config = <0x0
902 qcom,ddr-config = <0x8
903
904 status = "disabled";
905
906 sdhc1_opp_table: opp-t
907 compatible = "
908
909 opp-384000000
910 opp-hz
911 requir
912 opp-pe
913 opp-av
914 };
915 };
916 };
917
918 usb_1_hsphy: phy@88e3000 {
919 compatible = "qcom,qdu
920 "qcom,usb
921 reg = <0x0 0x088e3000
922 #phy-cells = <0>;
923
924 clocks =<&gcc GCC_USB2
925 clock-names = "ref";
926
927 resets = <&gcc GCC_QUS
928
929 status = "disabled";
930 };
931
932 usb_1_qmpphy: phy@88e5000 {
933 compatible = "qcom,qdu
934 reg = <0x0 0x088e5000
935
936 clocks = <&gcc GCC_USB
937 <&gcc GCC_USB
938 <&gcc GCC_USB
939 <&gcc GCC_USB
940 clock-names = "aux",
941 "ref",
942 "com_aux
943 "pipe";
944
945 resets = <&gcc GCC_USB
946 <&gcc GCC_USB
947 reset-names = "phy",
948 "phy_phy
949
950 #clock-cells = <0>;
951 clock-output-names = "
952
953 #phy-cells = <0>;
954
955 status = "disabled";
956 };
957
958 usb_1: usb@a6f8800 {
959 compatible = "qcom,qdu
960 reg = <0 0x0a6f8800 0
961 #address-cells = <2>;
962 #size-cells = <2>;
963 ranges;
964
965 clocks = <&gcc GCC_CFG
966 <&gcc GCC_USB
967 <&gcc GCC_USB
968 <&gcc GCC_USB
969 clock-names = "cfg_noc
970 "core",
971 "sleep",
972 "mock_ut
973
974 assigned-clocks = <&gc
975 <&gc
976 assigned-clock-rates =
977
978 interrupts-extended =
979
980
981
982
983 interrupt-names = "pwr
984 "hs_
985 "dp_
986 "dm_
987 "ss_
988
989 power-domains = <&gcc
990 required-opps = <&rpmh
991
992 resets = <&gcc GCC_USB
993
994 interconnects = <&syst
995 &mc_v
996 <&gem_
997 &syst
998
999 interconnect-names = "
1000
1001
1002 status = "disabled";
1003
1004 usb_1_dwc3: usb@a6000
1005 compatible =
1006 reg = <0 0x0a
1007 interrupts =
1008
1009 iommus = <&ap
1010 snps,dis_u2_s
1011 snps,dis_enbl
1012 phys = <&usb_
1013 <&usb_
1014 phy-names = "
1015 "
1016
1017 ports {
1018 #addr
1019 #size
1020
1021 port@
1022
1023
1024
1025
1026 };
1027
1028 port@
1029
1030
1031
1032
1033 };
1034 };
1035 };
1036 };
1037
1038 pdc: interrupt-controller@b22
1039 compatible = "qcom,qd
1040 reg = <0x0 0xb220000
1041 qcom,pdc-ranges = <0
1042 <94
1043 #interrupt-cells = <2
1044 interrupt-parent = <&
1045 interrupt-controller;
1046 };
1047
1048 spmi_bus: spmi@c400000 {
1049 compatible = "qcom,sp
1050 reg = <0x0 0xc400000
1051 <0x0 0xc500000
1052 <0x0 0xc440000
1053 <0x0 0xc4c0000
1054 <0x0 0xc42d000
1055 reg-names = "core", "
1056 interrupts-extended =
1057 interrupt-names = "pe
1058 qcom,ee = <0>;
1059 qcom,channel = <0>;
1060 #address-cells = <2>;
1061 #size-cells = <0>;
1062 interrupt-controller;
1063 #interrupt-cells = <4
1064 };
1065
1066 tlmm: pinctrl@f000000 {
1067 compatible = "qcom,qd
1068 reg = <0x0 0xf000000
1069 interrupts = <GIC_SPI
1070 gpio-controller;
1071 #gpio-cells = <2>;
1072 interrupt-controller;
1073 #interrupt-cells = <2
1074 gpio-ranges = <&tlmm
1075 wakeup-parent = <&pdc
1076
1077 qup_uart0_default: qu
1078 pins = "gpio6
1079 function = "q
1080 };
1081
1082 qup_i2c1_data_clk: qu
1083 pins = "gpio1
1084 function = "q
1085 };
1086
1087 qup_spi1_data_clk: qu
1088 pins = "gpio1
1089 function = "q
1090 };
1091
1092 qup_spi1_cs: qup-spi1
1093 pins = "gpio1
1094 function = "g
1095 };
1096
1097 qup_i2c2_data_clk: qu
1098 pins = "gpio1
1099 function = "q
1100 };
1101
1102 qup_spi2_data_clk: qu
1103 pins = "gpio1
1104 function = "q
1105 };
1106
1107 qup_spi2_cs: qup-spi2
1108 pins = "gpio1
1109 function = "g
1110 };
1111
1112 qup_i2c3_data_clk: qu
1113 pins = "gpio1
1114 function = "q
1115 };
1116
1117 qup_spi3_data_clk: qu
1118 pins = "gpio1
1119 function = "q
1120 };
1121
1122 qup_spi3_cs: qup-spi3
1123 pins = "gpio1
1124 function = "g
1125 };
1126
1127 qup_i2c4_data_clk: qu
1128 pins = "gpio1
1129 function = "q
1130 };
1131
1132 qup_spi4_data_clk: qu
1133 pins = "gpio1
1134 function = "q
1135 };
1136
1137 qup_spi4_cs: qup-spi4
1138 pins = "gpio1
1139 function = "g
1140 };
1141
1142 qup_i2c5_data_clk: qu
1143 pins = "gpio1
1144 function = "q
1145 };
1146
1147 qup_spi5_data_clk: qu
1148 pins = "gpio1
1149 function = "q
1150 };
1151
1152 qup_spi5_cs: qup-spi5
1153 pins = "gpio1
1154 function = "g
1155 };
1156
1157 qup_i2c6_data_clk: qu
1158 pins = "gpio1
1159 function = "q
1160 };
1161
1162 qup_spi6_data_clk: qu
1163 pins = "gpio1
1164 function = "q
1165 };
1166
1167 qup_spi6_cs: qup-spi6
1168 pins = "gpio1
1169 function = "g
1170 };
1171
1172 qup_uart7_rx: qup-uar
1173 pins = "gpio1
1174 function = "q
1175 };
1176
1177 qup_uart7_tx: qup-uar
1178 pins = "gpio1
1179 function = "q
1180 };
1181
1182 qup_uart8_default: qu
1183 pins = "gpio1
1184 function = "q
1185 };
1186
1187 qup_i2c9_data_clk: qu
1188 pins = "gpio2
1189 function = "q
1190 };
1191
1192 qup_spi9_data_clk: qu
1193 pins = "gpio2
1194 function = "q
1195 };
1196
1197 qup_spi9_cs: qup-spi9
1198 pins = "gpio2
1199 function = "g
1200 };
1201
1202 qup_i2c10_data_clk: q
1203 pins = "gpio2
1204 function = "q
1205 };
1206
1207 qup_spi10_data_clk: q
1208 pins = "gpio2
1209 function = "q
1210 };
1211
1212 qup_spi10_cs: qup-spi
1213 pins = "gpio2
1214 function = "g
1215 };
1216
1217 qup_i2c11_data_clk: q
1218 pins = "gpio2
1219 function = "q
1220 };
1221
1222 qup_spi11_data_clk: q
1223 pins = "gpio2
1224 function = "q
1225 };
1226
1227 qup_spi11_cs: qup-spi
1228 pins = "gpio2
1229 function = "g
1230 };
1231
1232 qup_i2c12_data_clk: q
1233 pins = "gpio2
1234 function = "q
1235 };
1236
1237 qup_spi12_data_clk: q
1238 pins = "gpio2
1239 function = "q
1240 };
1241
1242 qup_spi12_cs: qup-spi
1243 pins = "gpio2
1244 function = "g
1245 };
1246
1247 qup_i2c13_data_clk: q
1248 pins = "gpio3
1249 function = "q
1250 };
1251
1252 qup_spi13_data_clk: q
1253 pins = "gpio3
1254 function = "q
1255 };
1256
1257 qup_spi13_cs: qup-spi
1258 pins = "gpio3
1259 function = "g
1260 };
1261
1262 qup_uart13_default: q
1263 pins = "gpio3
1264 function = "q
1265 };
1266
1267 qup_i2c14_data_clk: q
1268 pins = "gpio3
1269 function = "q
1270 };
1271
1272 qup_spi14_data_clk: q
1273 pins = "gpio3
1274 function = "q
1275 };
1276
1277 qup_spi14_cs: qup-spi
1278 pins = "gpio3
1279 function = "g
1280 };
1281
1282 qup_i2c15_data_clk: q
1283 pins = "gpio4
1284 function = "q
1285 };
1286
1287 qup_spi15_data_clk: q
1288 pins = "gpio4
1289 function = "q
1290 };
1291
1292 qup_spi15_cs: qup-spi
1293 pins = "gpio3
1294 function = "g
1295 };
1296
1297 sdc_on_state: sdc-on-
1298 clk-pins {
1299 pins
1300 drive
1301 bias-
1302 };
1303
1304 cmd-pins {
1305 pins
1306 drive
1307 bias-
1308 };
1309
1310 data-pins {
1311 pins
1312 drive
1313 bias-
1314 };
1315
1316 rclk-pins {
1317 pins
1318 bias-
1319 };
1320 };
1321
1322 sdc_off_state: sdc-of
1323 clk-pins {
1324 pins
1325 drive
1326 bias-
1327 };
1328
1329 cmd-pins {
1330 pins
1331 drive
1332 bias-
1333 };
1334
1335 data-pins {
1336 pins
1337 drive
1338 bias-
1339 };
1340
1341 rclk-pins {
1342 pins
1343 bias-
1344 };
1345 };
1346 };
1347
1348 sram@14680000 {
1349 compatible = "qcom,qd
1350 reg = <0 0x14680000 0
1351 ranges = <0 0 0x14680
1352 #address-cells = <1>;
1353 #size-cells = <1>;
1354
1355 pil-reloc@94c {
1356 compatible =
1357 reg = <0x94c
1358 };
1359 };
1360
1361 apps_smmu: iommu@15000000 {
1362 compatible = "qcom,qd
1363 reg = <0x0 0x15000000
1364 #iommu-cells = <2>;
1365 #global-interrupts =
1366 interrupts = <GIC_SPI
1367 <GIC_SPI
1368 <GIC_SPI
1369 <GIC_SPI
1370 <GIC_SPI
1371 <GIC_SPI
1372 <GIC_SPI
1373 <GIC_SPI
1374 <GIC_SPI
1375 <GIC_SPI
1376 <GIC_SPI
1377 <GIC_SPI
1378 <GIC_SPI
1379 <GIC_SPI
1380 <GIC_SPI
1381 <GIC_SPI
1382 <GIC_SPI
1383 <GIC_SPI
1384 <GIC_SPI
1385 <GIC_SPI
1386 <GIC_SPI
1387 <GIC_SPI
1388 <GIC_SPI
1389 <GIC_SPI
1390 <GIC_SPI
1391 <GIC_SPI
1392 <GIC_SPI
1393 <GIC_SPI
1394 <GIC_SPI
1395 <GIC_SPI
1396 <GIC_SPI
1397 <GIC_SPI
1398 <GIC_SPI
1399 <GIC_SPI
1400 <GIC_SPI
1401 <GIC_SPI
1402 <GIC_SPI
1403 <GIC_SPI
1404 <GIC_SPI
1405 <GIC_SPI
1406 <GIC_SPI
1407 <GIC_SPI
1408 <GIC_SPI
1409 <GIC_SPI
1410 <GIC_SPI
1411 <GIC_SPI
1412 <GIC_SPI
1413 <GIC_SPI
1414 <GIC_SPI
1415 };
1416
1417 intc: interrupt-controller@17
1418 compatible = "arm,gic
1419 reg = <0x0 0x17200000
1420 <0x0 0x17260000
1421 interrupts = <GIC_PPI
1422 #interrupt-cells = <3
1423 interrupt-controller;
1424 #redistributor-region
1425 redistributor-stride
1426 };
1427
1428 timer@17420000 {
1429 compatible = "arm,arm
1430 reg = <0x0 0x17420000
1431 #address-cells = <1>;
1432 #size-cells = <1>;
1433 ranges = <0x0 0x0 0x0
1434
1435 frame@17421000 {
1436 reg = <0x1742
1437 <0x1742
1438 interrupts =
1439
1440 frame-number
1441 };
1442
1443 frame@17423000 {
1444 reg = <0x1742
1445 interrupts =
1446 frame-number
1447 status = "dis
1448 };
1449
1450 frame@17425000 {
1451 reg = <0x1742
1452 <0x1742
1453 interrupts =
1454 frame-number
1455 status = "dis
1456 };
1457
1458 frame@17427000 {
1459 reg = <0x1742
1460 interrupts =
1461 frame-number
1462 status = "dis
1463 };
1464
1465 frame@17429000 {
1466 reg = <0x1742
1467 interrupts =
1468 frame-number
1469 status = "dis
1470 };
1471
1472 frame@1742b000 {
1473 reg = <0x1742
1474 interrupts =
1475 frame-number
1476 status = "dis
1477 };
1478
1479 frame@1742d000 {
1480 reg = <0x1742
1481 interrupts =
1482 frame-number
1483 status = "dis
1484 };
1485 };
1486
1487 apps_rsc: rsc@17a00000 {
1488 compatible = "qcom,rp
1489 reg = <0x0 0x17a00000
1490 <0x0 0x17a10000
1491 <0x0 0x17a20000
1492 reg-names = "drv-0",
1493 interrupts = <GIC_SPI
1494 <GIC_SPI
1495 <GIC_SPI
1496 qcom,tcs-offset = <0x
1497 qcom,drv-id = <2>;
1498 qcom,tcs-config = <AC
1499 <WA
1500 label = "apps_rsc";
1501 power-domains = <&CLU
1502
1503 apps_bcm_voter: bcm-v
1504 compatible =
1505 };
1506
1507 rpmhcc: clock-control
1508 compatible =
1509 clocks = <&xo
1510 clock-names =
1511 #clock-cells
1512 };
1513
1514 rpmhpd: power-control
1515 compatible =
1516 #power-domain
1517 operating-poi
1518
1519 rpmhpd_opp_ta
1520 compa
1521
1522 rpmhp
1523
1524 };
1525
1526 rpmhp
1527
1528 };
1529
1530 rpmhp
1531
1532 };
1533
1534 rpmhp
1535
1536 };
1537
1538 rpmhp
1539
1540 };
1541
1542 rpmhp
1543
1544 };
1545
1546 rpmhp
1547
1548 };
1549
1550 rpmhp
1551
1552 };
1553
1554 rpmhp
1555
1556 };
1557
1558 rpmhp
1559
1560 };
1561 };
1562 };
1563 };
1564
1565 cpufreq_hw: cpufreq@17d90000
1566 compatible = "qcom,qd
1567 reg = <0x0 0x17d90000
1568 reg-names = "freq-dom
1569 clocks = <&rpmhcc RPM
1570 clock-names = "xo", "
1571 #freq-domain-cells =
1572 #clock-cells = <1>;
1573 };
1574
1575 gem_noc: interconnect@1910000
1576 compatible = "qcom,qd
1577 reg = <0x0 0x19100000
1578 qcom,bcm-voters = <&a
1579 #interconnect-cells =
1580 };
1581
1582 system-cache-controller@19200
1583 compatible = "qcom,qd
1584 reg = <0 0x19200000 0
1585 <0 0x19300000 0
1586 <0 0x19600000 0
1587 <0 0x19700000 0
1588 <0 0x19a00000 0
1589 <0 0x19b00000 0
1590 <0 0x19e00000 0
1591 <0 0x19f00000 0
1592 <0 0x1a200000 0
1593 reg-names = "llcc0_ba
1594 "llcc1_ba
1595 "llcc2_ba
1596 "llcc3_ba
1597 "llcc4_ba
1598 "llcc5_ba
1599 "llcc6_ba
1600 "llcc7_ba
1601 "llcc_bro
1602 interrupts = <GIC_SPI
1603
1604 nvmem-cells = <&multi
1605 nvmem-cell-names = "m
1606 };
1607
1608 sec_qfprom: efuse@221c8000 {
1609 compatible = "qcom,qd
1610 reg = <0 0x221c8000 0
1611 #address-cells = <1>;
1612 #size-cells = <1>;
1613
1614 multi_chan_ddr: multi
1615 reg = <0x12b
1616 bits = <0 2>;
1617 };
1618 };
1619 };
1620
1621 timer {
1622 compatible = "arm,armv8-timer
1623 interrupts = <GIC_PPI 13 (GIC
1624 <GIC_PPI 14 (GIC
1625 <GIC_PPI 11 (GIC
1626 <GIC_PPI 10 (GIC
1627 <GIC_PPI 12 (GIC
1628 };
1629 };
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