1 // SPDX-License-Identifier: BSD-3-Clause 1 // SPDX-License-Identifier: BSD-3-Clause
2 /* 2 /*
3 * Copyright (c) 2022 Qualcomm Innovation Cent 3 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
4 */ 4 */
5 5
6 #include <dt-bindings/clock/qcom,qdu1000-gcc.h 6 #include <dt-bindings/clock/qcom,qdu1000-gcc.h>
7 #include <dt-bindings/clock/qcom,rpmh.h> 7 #include <dt-bindings/clock/qcom,rpmh.h>
8 #include <dt-bindings/dma/qcom-gpi.h> 8 #include <dt-bindings/dma/qcom-gpi.h>
9 #include <dt-bindings/gpio/gpio.h> <<
10 #include <dt-bindings/interconnect/qcom,icc.h> <<
11 #include <dt-bindings/interconnect/qcom,qdu100 9 #include <dt-bindings/interconnect/qcom,qdu1000-rpmh.h>
12 #include <dt-bindings/interrupt-controller/arm 10 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/power/qcom-rpmpd.h> 11 #include <dt-bindings/power/qcom-rpmpd.h>
14 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 12 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
15 13
16 / { 14 / {
17 interrupt-parent = <&intc>; 15 interrupt-parent = <&intc>;
18 16
19 #address-cells = <2>; 17 #address-cells = <2>;
20 #size-cells = <2>; 18 #size-cells = <2>;
21 19
22 chosen: chosen { }; 20 chosen: chosen { };
23 21
24 cpus { 22 cpus {
25 #address-cells = <2>; 23 #address-cells = <2>;
26 #size-cells = <0>; 24 #size-cells = <0>;
27 25
28 CPU0: cpu@0 { 26 CPU0: cpu@0 {
29 device_type = "cpu"; 27 device_type = "cpu";
30 compatible = "arm,cort 28 compatible = "arm,cortex-a55";
31 reg = <0x0 0x0>; 29 reg = <0x0 0x0>;
32 clocks = <&cpufreq_hw <<
33 enable-method = "psci" 30 enable-method = "psci";
34 power-domains = <&CPU_ 31 power-domains = <&CPU_PD0>;
35 power-domain-names = " 32 power-domain-names = "psci";
36 qcom,freq-domains = <& 33 qcom,freq-domains = <&cpufreq_hw 0>;
37 next-level-cache = <&L 34 next-level-cache = <&L2_0>;
38 L2_0: l2-cache { 35 L2_0: l2-cache {
39 compatible = " 36 compatible = "cache";
40 cache-level = <<
41 cache-unified; <<
42 next-level-cac 37 next-level-cache = <&L3_0>;
43 L3_0: l3-cache 38 L3_0: l3-cache {
44 compat 39 compatible = "cache";
45 cache- <<
46 cache- <<
47 }; 40 };
48 }; 41 };
49 }; 42 };
50 43
51 CPU1: cpu@100 { 44 CPU1: cpu@100 {
52 device_type = "cpu"; 45 device_type = "cpu";
53 compatible = "arm,cort 46 compatible = "arm,cortex-a55";
54 reg = <0x0 0x100>; 47 reg = <0x0 0x100>;
55 clocks = <&cpufreq_hw <<
56 enable-method = "psci" 48 enable-method = "psci";
57 power-domains = <&CPU_ 49 power-domains = <&CPU_PD1>;
58 power-domain-names = " 50 power-domain-names = "psci";
59 qcom,freq-domains = <& 51 qcom,freq-domains = <&cpufreq_hw 0>;
60 next-level-cache = <&L 52 next-level-cache = <&L2_100>;
61 L2_100: l2-cache { 53 L2_100: l2-cache {
62 compatible = " 54 compatible = "cache";
63 cache-level = <<
64 cache-unified; <<
65 next-level-cac 55 next-level-cache = <&L3_0>;
66 }; 56 };
67 }; 57 };
68 58
69 CPU2: cpu@200 { 59 CPU2: cpu@200 {
70 device_type = "cpu"; 60 device_type = "cpu";
71 compatible = "arm,cort 61 compatible = "arm,cortex-a55";
72 reg = <0x0 0x200>; 62 reg = <0x0 0x200>;
73 clocks = <&cpufreq_hw <<
74 enable-method = "psci" 63 enable-method = "psci";
75 power-domains = <&CPU_ 64 power-domains = <&CPU_PD2>;
76 power-domain-names = " 65 power-domain-names = "psci";
77 qcom,freq-domains = <& 66 qcom,freq-domains = <&cpufreq_hw 0>;
78 next-level-cache = <&L 67 next-level-cache = <&L2_200>;
79 L2_200: l2-cache { 68 L2_200: l2-cache {
80 compatible = " 69 compatible = "cache";
81 cache-level = <<
82 cache-unified; <<
83 next-level-cac 70 next-level-cache = <&L3_0>;
84 }; 71 };
85 }; 72 };
86 73
87 CPU3: cpu@300 { 74 CPU3: cpu@300 {
88 device_type = "cpu"; 75 device_type = "cpu";
89 compatible = "arm,cort 76 compatible = "arm,cortex-a55";
90 reg = <0x0 0x300>; 77 reg = <0x0 0x300>;
91 clocks = <&cpufreq_hw <<
92 enable-method = "psci" 78 enable-method = "psci";
93 power-domains = <&CPU_ 79 power-domains = <&CPU_PD3>;
94 power-domain-names = " 80 power-domain-names = "psci";
95 qcom,freq-domains = <& 81 qcom,freq-domains = <&cpufreq_hw 0>;
96 next-level-cache = <&L 82 next-level-cache = <&L2_300>;
97 L2_300: l2-cache { 83 L2_300: l2-cache {
98 compatible = " 84 compatible = "cache";
99 cache-level = <<
100 cache-unified; <<
101 next-level-cac 85 next-level-cache = <&L3_0>;
102 }; 86 };
103 }; 87 };
104 88
105 cpu-map { 89 cpu-map {
106 cluster0 { 90 cluster0 {
107 core0 { 91 core0 {
108 cpu = 92 cpu = <&CPU0>;
109 }; 93 };
110 94
111 core1 { 95 core1 {
112 cpu = 96 cpu = <&CPU1>;
113 }; 97 };
114 98
115 core2 { 99 core2 {
116 cpu = 100 cpu = <&CPU2>;
117 }; 101 };
118 102
119 core3 { 103 core3 {
120 cpu = 104 cpu = <&CPU3>;
121 }; 105 };
122 }; 106 };
123 }; 107 };
124 }; 108 };
125 109
126 idle-states { 110 idle-states {
127 entry-method = "psci"; 111 entry-method = "psci";
128 112
129 CPU_OFF: cpu-sleep-0 { 113 CPU_OFF: cpu-sleep-0 {
130 compatible = "arm,idle 114 compatible = "arm,idle-state";
131 entry-latency-us = <27 115 entry-latency-us = <274>;
132 exit-latency-us = <480 116 exit-latency-us = <480>;
133 min-residency-us = <39 117 min-residency-us = <3934>;
134 arm,psci-suspend-param 118 arm,psci-suspend-param = <0x40000004>;
135 local-timer-stop; 119 local-timer-stop;
136 }; 120 };
137 }; 121 };
138 122
139 domain-idle-states { 123 domain-idle-states {
140 CLUSTER_SLEEP_0: cluster-sleep 124 CLUSTER_SLEEP_0: cluster-sleep-0 {
141 compatible = "domain-i 125 compatible = "domain-idle-state";
142 entry-latency-us = <58 126 entry-latency-us = <584>;
143 exit-latency-us = <233 127 exit-latency-us = <2332>;
144 min-residency-us = <61 128 min-residency-us = <6118>;
145 arm,psci-suspend-param 129 arm,psci-suspend-param = <0x41000044>;
146 }; 130 };
147 131
148 CLUSTER_SLEEP_1: cluster-sleep 132 CLUSTER_SLEEP_1: cluster-sleep-1 {
149 compatible = "domain-i 133 compatible = "domain-idle-state";
150 entry-latency-us = <28 134 entry-latency-us = <2893>;
151 exit-latency-us = <402 135 exit-latency-us = <4023>;
152 min-residency-us = <99 136 min-residency-us = <9987>;
153 arm,psci-suspend-param 137 arm,psci-suspend-param = <0x41003344>;
154 }; 138 };
155 }; 139 };
156 140
157 firmware { 141 firmware {
158 scm { 142 scm {
159 compatible = "qcom,scm 143 compatible = "qcom,scm-qdu1000", "qcom,scm";
160 }; 144 };
161 }; 145 };
162 146
163 mc_virt: interconnect-0 { 147 mc_virt: interconnect-0 {
164 compatible = "qcom,qdu1000-mc- 148 compatible = "qcom,qdu1000-mc-virt";
165 qcom,bcm-voters = <&apps_bcm_v 149 qcom,bcm-voters = <&apps_bcm_voter>;
166 #interconnect-cells = <2>; 150 #interconnect-cells = <2>;
167 }; 151 };
168 152
169 clk_virt: interconnect-1 { 153 clk_virt: interconnect-1 {
170 compatible = "qcom,qdu1000-clk 154 compatible = "qcom,qdu1000-clk-virt";
171 qcom,bcm-voters = <&apps_bcm_v 155 qcom,bcm-voters = <&apps_bcm_voter>;
172 #interconnect-cells = <2>; 156 #interconnect-cells = <2>;
173 }; 157 };
174 158
175 memory@80000000 { 159 memory@80000000 {
176 device_type = "memory"; 160 device_type = "memory";
177 /* We expect the bootloader to 161 /* We expect the bootloader to fill in the size */
178 reg = <0x0 0x80000000 0x0 0x0> 162 reg = <0x0 0x80000000 0x0 0x0>;
179 }; 163 };
180 164
181 pmu { 165 pmu {
182 compatible = "arm,cortex-a55-p !! 166 compatible = "arm,armv8-pmuv3";
183 interrupts = <GIC_PPI 7 IRQ_TY 167 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
184 }; 168 };
185 169
186 psci { 170 psci {
187 compatible = "arm,psci-1.0"; 171 compatible = "arm,psci-1.0";
188 method = "smc"; 172 method = "smc";
189 173
190 CPU_PD0: power-domain-cpu0 { 174 CPU_PD0: power-domain-cpu0 {
191 #power-domain-cells = 175 #power-domain-cells = <0>;
192 power-domains = <&CLUS 176 power-domains = <&CLUSTER_PD>;
193 domain-idle-states = < 177 domain-idle-states = <&CPU_OFF>;
194 }; 178 };
195 179
196 CPU_PD1: power-domain-cpu1 { 180 CPU_PD1: power-domain-cpu1 {
197 #power-domain-cells = 181 #power-domain-cells = <0>;
198 power-domains = <&CLUS 182 power-domains = <&CLUSTER_PD>;
199 domain-idle-states = < 183 domain-idle-states = <&CPU_OFF>;
200 }; 184 };
201 185
202 CPU_PD2: power-domain-cpu2 { 186 CPU_PD2: power-domain-cpu2 {
203 #power-domain-cells = 187 #power-domain-cells = <0>;
204 power-domains = <&CLUS 188 power-domains = <&CLUSTER_PD>;
205 domain-idle-states = < 189 domain-idle-states = <&CPU_OFF>;
206 }; 190 };
207 191
208 CPU_PD3: power-domain-cpu3 { 192 CPU_PD3: power-domain-cpu3 {
209 #power-domain-cells = 193 #power-domain-cells = <0>;
210 power-domains = <&CLUS 194 power-domains = <&CLUSTER_PD>;
211 domain-idle-states = < 195 domain-idle-states = <&CPU_OFF>;
212 }; 196 };
213 197
214 CLUSTER_PD: power-domain-clust 198 CLUSTER_PD: power-domain-cluster {
215 #power-domain-cells = 199 #power-domain-cells = <0>;
216 domain-idle-states = < 200 domain-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_1>;
217 }; 201 };
218 }; 202 };
219 203
220 reserved_memory: reserved-memory { 204 reserved_memory: reserved-memory {
221 #address-cells = <2>; 205 #address-cells = <2>;
222 #size-cells = <2>; 206 #size-cells = <2>;
223 ranges; 207 ranges;
224 208
225 hyp_mem: hyp@80000000 { 209 hyp_mem: hyp@80000000 {
226 reg = <0x0 0x80000000 210 reg = <0x0 0x80000000 0x0 0x600000>;
227 no-map; 211 no-map;
228 }; 212 };
229 213
230 xbl_dt_log_mem: xbl-dt-log@806 214 xbl_dt_log_mem: xbl-dt-log@80600000 {
231 reg = <0x0 0x80600000 215 reg = <0x0 0x80600000 0x0 0x40000>;
232 no-map; 216 no-map;
233 }; 217 };
234 218
235 xbl_ramdump_mem: xbl-ramdump@8 219 xbl_ramdump_mem: xbl-ramdump@80640000 {
236 reg = <0x0 0x80640000 220 reg = <0x0 0x80640000 0x0 0x1c0000>;
237 no-map; 221 no-map;
238 }; 222 };
239 223
240 aop_image_mem: aop-image@80800 224 aop_image_mem: aop-image@80800000 {
241 reg = <0x0 0x80800000 225 reg = <0x0 0x80800000 0x0 0x60000>;
242 no-map; 226 no-map;
243 }; 227 };
244 228
245 aop_cmd_db_mem: aop-cmd-db@808 229 aop_cmd_db_mem: aop-cmd-db@80860000 {
246 compatible = "qcom,cmd 230 compatible = "qcom,cmd-db";
247 reg = <0x0 0x80860000 231 reg = <0x0 0x80860000 0x0 0x20000>;
248 no-map; 232 no-map;
249 }; 233 };
250 234
251 aop_config_mem: aop-config@808 235 aop_config_mem: aop-config@80880000 {
252 reg = <0x0 0x80880000 236 reg = <0x0 0x80880000 0x0 0x20000>;
253 no-map; 237 no-map;
254 }; 238 };
255 239
256 tme_crash_dump_mem: tme-crash- 240 tme_crash_dump_mem: tme-crash-dump@808a0000 {
257 reg = <0x0 0x808a0000 241 reg = <0x0 0x808a0000 0x0 0x40000>;
258 no-map; 242 no-map;
259 }; 243 };
260 244
261 tme_log_mem: tme-log@808e0000 245 tme_log_mem: tme-log@808e0000 {
262 reg = <0x0 0x808e0000 246 reg = <0x0 0x808e0000 0x0 0x4000>;
263 no-map; 247 no-map;
264 }; 248 };
265 249
266 uefi_log_mem: uefi-log@808e400 250 uefi_log_mem: uefi-log@808e4000 {
267 reg = <0x0 0x808e4000 251 reg = <0x0 0x808e4000 0x0 0x10000>;
268 no-map; 252 no-map;
269 }; 253 };
270 254
271 smem_mem: smem@80900000 { 255 smem_mem: smem@80900000 {
272 compatible = "qcom,sme 256 compatible = "qcom,smem";
273 reg = <0x0 0x80900000 257 reg = <0x0 0x80900000 0x0 0x200000>;
274 no-map; 258 no-map;
275 hwlocks = <&tcsr_mutex 259 hwlocks = <&tcsr_mutex 3>;
276 }; 260 };
277 261
278 cpucp_fw_mem: cpucp-fw@80b0000 262 cpucp_fw_mem: cpucp-fw@80b00000 {
279 reg = <0x0 0x80b00000 263 reg = <0x0 0x80b00000 0x0 0x100000>;
280 no-map; 264 no-map;
281 }; 265 };
282 266
283 xbl_sc_mem: memory@80c00000 { 267 xbl_sc_mem: memory@80c00000 {
284 reg = <0x0 0x80c00000 268 reg = <0x0 0x80c00000 0x0 0x40000>;
285 no-map; 269 no-map;
286 }; 270 };
287 271
288 tz_stat_mem: tz-stat@81d00000 272 tz_stat_mem: tz-stat@81d00000 {
289 reg = <0x0 0x81d00000 273 reg = <0x0 0x81d00000 0x0 0x100000>;
290 no-map; 274 no-map;
291 }; 275 };
292 276
293 tags_mem: tags@81e00000 { 277 tags_mem: tags@81e00000 {
294 reg = <0x0 0x81e00000 278 reg = <0x0 0x81e00000 0x0 0x500000>;
295 no-map; 279 no-map;
296 }; 280 };
297 281
298 qtee_mem: qtee@82300000 { 282 qtee_mem: qtee@82300000 {
299 reg = <0x0 0x82300000 283 reg = <0x0 0x82300000 0x0 0x500000>;
300 no-map; 284 no-map;
301 }; 285 };
302 286
303 ta_mem: ta@82800000 { 287 ta_mem: ta@82800000 {
304 reg = <0x0 0x82800000 288 reg = <0x0 0x82800000 0x0 0xa00000>;
305 no-map; 289 no-map;
306 }; 290 };
307 291
308 fs1_mem: fs1@83200000 { 292 fs1_mem: fs1@83200000 {
309 reg = <0x0 0x83200000 293 reg = <0x0 0x83200000 0x0 0x400000>;
310 no-map; 294 no-map;
311 }; 295 };
312 296
313 fs2_mem: fs2@83600000 { 297 fs2_mem: fs2@83600000 {
314 reg = <0x0 0x83600000 298 reg = <0x0 0x83600000 0x0 0x400000>;
315 no-map; 299 no-map;
316 }; 300 };
317 301
318 fs3_mem: fs3@83a00000 { 302 fs3_mem: fs3@83a00000 {
319 reg = <0x0 0x83a00000 303 reg = <0x0 0x83a00000 0x0 0x400000>;
320 no-map; 304 no-map;
321 }; 305 };
322 306
323 /* Linux kernel image is loade 307 /* Linux kernel image is loaded at 0x83e00000 */
324 308
325 ipa_fw_mem: ipa-fw@8be00000 { 309 ipa_fw_mem: ipa-fw@8be00000 {
326 reg = <0x0 0x8be00000 310 reg = <0x0 0x8be00000 0x0 0x10000>;
327 no-map; 311 no-map;
328 }; 312 };
329 313
330 ipa_gsi_mem: ipa-gsi@8be10000 314 ipa_gsi_mem: ipa-gsi@8be10000 {
331 reg = <0x0 0x8be10000 315 reg = <0x0 0x8be10000 0x0 0x14000>;
332 no-map; 316 no-map;
333 }; 317 };
334 318
335 mpss_mem: mpss@8c000000 { 319 mpss_mem: mpss@8c000000 {
336 reg = <0x0 0x8c000000 320 reg = <0x0 0x8c000000 0x0 0x12c00000>;
337 no-map; 321 no-map;
338 }; 322 };
339 323
340 q6_mpss_dtb_mem: q6-mpss-dtb@9 324 q6_mpss_dtb_mem: q6-mpss-dtb@9ec00000 {
341 reg = <0x0 0x9ec00000 325 reg = <0x0 0x9ec00000 0x0 0x80000>;
342 no-map; 326 no-map;
343 }; 327 };
344 328
345 tenx_mem: tenx@a0000000 { 329 tenx_mem: tenx@a0000000 {
346 reg = <0x0 0xa0000000 330 reg = <0x0 0xa0000000 0x0 0x19600000>;
347 no-map; 331 no-map;
348 }; 332 };
349 333
350 oem_tenx_mem: oem-tenx@b960000 334 oem_tenx_mem: oem-tenx@b9600000 {
351 reg = <0x0 0xb9600000 335 reg = <0x0 0xb9600000 0x0 0x6a00000>;
352 no-map; 336 no-map;
353 }; 337 };
354 338
355 tenx_q6_buffer_mem: tenx-q6-bu 339 tenx_q6_buffer_mem: tenx-q6-buffer@c0000000 {
356 reg = <0x0 0xc0000000 340 reg = <0x0 0xc0000000 0x0 0x3200000>;
357 no-map; 341 no-map;
358 }; 342 };
359 343
360 ipa_buffer_mem: ipa-buffer@c32 344 ipa_buffer_mem: ipa-buffer@c3200000 {
361 reg = <0x0 0xc3200000 345 reg = <0x0 0xc3200000 0x0 0x12c00000>;
362 no-map; 346 no-map;
363 }; 347 };
364 }; 348 };
365 349
366 soc: soc@0 { 350 soc: soc@0 {
367 compatible = "simple-bus"; 351 compatible = "simple-bus";
368 #address-cells = <2>; 352 #address-cells = <2>;
369 #size-cells = <2>; 353 #size-cells = <2>;
370 ranges = <0 0 0 0 0x10 0>; 354 ranges = <0 0 0 0 0x10 0>;
371 dma-ranges = <0 0 0 0 0x10 0>; 355 dma-ranges = <0 0 0 0 0x10 0>;
372 356
373 gcc: clock-controller@80000 { 357 gcc: clock-controller@80000 {
374 compatible = "qcom,qdu 358 compatible = "qcom,qdu1000-gcc";
375 reg = <0x0 0x80000 0x0 359 reg = <0x0 0x80000 0x0 0x1f4200>;
376 clocks = <&rpmhcc RPMH 360 clocks = <&rpmhcc RPMH_CXO_CLK>,
377 <&sleep_clk>, 361 <&sleep_clk>,
378 <0>, 362 <0>,
379 <0>, 363 <0>,
380 <0>; 364 <0>;
381 #clock-cells = <1>; 365 #clock-cells = <1>;
382 #reset-cells = <1>; 366 #reset-cells = <1>;
383 #power-domain-cells = 367 #power-domain-cells = <1>;
384 }; 368 };
385 369
386 ecpricc: clock-controller@2800 <<
387 compatible = "qcom,qdu <<
388 reg = <0x0 0x00280000 <<
389 clocks = <&rpmhcc RPMH <<
390 <&gcc GCC_ECP <<
391 <&gcc GCC_ECP <<
392 <&gcc GCC_ECP <<
393 <&gcc GCC_ECP <<
394 <&gcc GCC_ECP <<
395 <&gcc GCC_ECP <<
396 #clock-cells = <1>; <<
397 #reset-cells = <1>; <<
398 }; <<
399 <<
400 gpi_dma0: dma-controller@90000 370 gpi_dma0: dma-controller@900000 {
401 compatible = "qcom,qdu 371 compatible = "qcom,qdu1000-gpi-dma", "qcom,sm6350-gpi-dma";
402 reg = <0x0 0x900000 0x 372 reg = <0x0 0x900000 0x0 0x60000>;
403 interrupts = <GIC_SPI 373 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
404 <GIC_SPI 374 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
405 <GIC_SPI 375 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
406 <GIC_SPI 376 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
407 <GIC_SPI 377 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
408 <GIC_SPI 378 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
409 <GIC_SPI 379 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
410 <GIC_SPI 380 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
411 <GIC_SPI 381 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
412 <GIC_SPI 382 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
413 <GIC_SPI 383 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
414 <GIC_SPI 384 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
415 dma-channels = <12>; 385 dma-channels = <12>;
416 dma-channel-mask = <0x 386 dma-channel-mask = <0x3f>;
417 iommus = <&apps_smmu 0 387 iommus = <&apps_smmu 0xf6 0x0>;
418 #dma-cells = <3>; 388 #dma-cells = <3>;
419 }; 389 };
420 390
421 qupv3_id_0: geniqup@9c0000 { 391 qupv3_id_0: geniqup@9c0000 {
422 compatible = "qcom,gen 392 compatible = "qcom,geni-se-qup";
423 reg = <0x0 0x9c0000 0x 393 reg = <0x0 0x9c0000 0x0 0x2000>;
424 clocks = <&gcc GCC_QUP 394 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
425 <&gcc GCC_QUPV 395 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
426 clock-names = "m-ahb", 396 clock-names = "m-ahb", "s-ahb";
427 iommus = <&apps_smmu 0 397 iommus = <&apps_smmu 0xe3 0x0>;
428 interconnects = <&clk_ 398 interconnects = <&clk_virt MASTER_QUP_CORE_0 0
429 &clk_ 399 &clk_virt SLAVE_QUP_CORE_0 0>;
430 interconnect-names = " 400 interconnect-names = "qup-core";
431 401
432 #address-cells = <2>; 402 #address-cells = <2>;
433 #size-cells = <2>; 403 #size-cells = <2>;
434 ranges; 404 ranges;
435 status = "disabled"; 405 status = "disabled";
436 406
437 uart0: serial@980000 { 407 uart0: serial@980000 {
438 compatible = " 408 compatible = "qcom,geni-uart";
439 reg = <0x0 0x9 409 reg = <0x0 0x980000 0x0 0x4000>;
440 clocks = <&gcc 410 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
441 clock-names = 411 clock-names = "se";
442 pinctrl-0 = <& 412 pinctrl-0 = <&qup_uart0_default>;
443 pinctrl-names 413 pinctrl-names = "default";
444 interrupts = < 414 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
445 status = "disa 415 status = "disabled";
446 }; 416 };
447 417
448 i2c1: i2c@984000 { 418 i2c1: i2c@984000 {
449 compatible = " 419 compatible = "qcom,geni-i2c";
450 reg = <0x0 0x9 420 reg = <0x0 0x984000 0x0 0x4000>;
451 clocks = <&gcc 421 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
452 clock-names = 422 clock-names = "se";
453 interrupts = < 423 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
454 pinctrl-0 = <& 424 pinctrl-0 = <&qup_i2c1_data_clk>;
455 pinctrl-names 425 pinctrl-names = "default";
456 #address-cells 426 #address-cells = <1>;
457 #size-cells = 427 #size-cells = <0>;
458 status = "disa 428 status = "disabled";
459 }; 429 };
460 430
461 spi1: spi@984000 { 431 spi1: spi@984000 {
462 compatible = " 432 compatible = "qcom,geni-spi";
463 reg = <0x0 0x9 433 reg = <0x0 0x984000 0x0 0x4000>;
464 #address-cells 434 #address-cells = <1>;
465 #size-cells = 435 #size-cells = <0>;
466 interrupts = < 436 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
467 clocks = <&gcc 437 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
468 clock-names = 438 clock-names = "se";
469 pinctrl-0 = <& 439 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
470 pinctrl-names 440 pinctrl-names = "default";
471 status = "disa 441 status = "disabled";
472 }; 442 };
473 443
474 i2c2: i2c@988000 { 444 i2c2: i2c@988000 {
475 compatible = " 445 compatible = "qcom,geni-i2c";
476 reg = <0x0 0x9 446 reg = <0x0 0x988000 0x0 0x4000>;
477 clocks = <&gcc 447 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
478 clock-names = 448 clock-names = "se";
479 interrupts = < 449 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
480 pinctrl-0 = <& 450 pinctrl-0 = <&qup_i2c2_data_clk>;
481 pinctrl-names 451 pinctrl-names = "default";
482 #address-cells 452 #address-cells = <1>;
483 #size-cells = 453 #size-cells = <0>;
484 status = "disa 454 status = "disabled";
485 }; 455 };
486 456
487 spi2: spi@988000 { 457 spi2: spi@988000 {
488 compatible = " 458 compatible = "qcom,geni-spi";
489 reg = <0x0 0x9 459 reg = <0x0 0x988000 0x0 0x4000>;
490 #address-cells 460 #address-cells = <1>;
491 #size-cells = 461 #size-cells = <0>;
492 interrupts = < 462 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
493 clocks = <&gcc 463 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
494 clock-names = 464 clock-names = "se";
495 pinctrl-0 = <& 465 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
496 pinctrl-names 466 pinctrl-names = "default";
497 status = "disa 467 status = "disabled";
498 }; 468 };
499 469
500 i2c3: i2c@98c000 { 470 i2c3: i2c@98c000 {
501 compatible = " 471 compatible = "qcom,geni-i2c";
502 reg = <0x0 0x9 472 reg = <0x0 0x98c000 0x0 0x4000>;
503 clocks = <&gcc 473 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
504 clock-names = 474 clock-names = "se";
505 interrupts = < 475 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
506 pinctrl-0 = <& 476 pinctrl-0 = <&qup_i2c3_data_clk>;
507 pinctrl-names 477 pinctrl-names = "default";
508 #address-cells 478 #address-cells = <1>;
509 #size-cells = 479 #size-cells = <0>;
510 status = "disa 480 status = "disabled";
511 }; 481 };
512 482
513 spi3: spi@98c000 { 483 spi3: spi@98c000 {
514 compatible = " 484 compatible = "qcom,geni-spi";
515 reg = <0x0 0x9 485 reg = <0x0 0x98c000 0x0 0x4000>;
516 #address-cells 486 #address-cells = <1>;
517 #size-cells = 487 #size-cells = <0>;
518 interrupts = < 488 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
519 clocks = <&gcc 489 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
520 clock-names = 490 clock-names = "se";
521 pinctrl-0 = <& 491 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
522 pinctrl-names 492 pinctrl-names = "default";
523 status = "disa 493 status = "disabled";
524 }; 494 };
525 495
526 i2c4: i2c@990000 { 496 i2c4: i2c@990000 {
527 compatible = " 497 compatible = "qcom,geni-i2c";
528 reg = <0x0 0x9 498 reg = <0x0 0x990000 0x0 0x4000>;
529 clocks = <&gcc 499 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
530 clock-names = 500 clock-names = "se";
531 interrupts = < 501 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
532 pinctrl-0 = <& 502 pinctrl-0 = <&qup_i2c4_data_clk>;
533 pinctrl-names 503 pinctrl-names = "default";
534 #address-cells 504 #address-cells = <1>;
535 #size-cells = 505 #size-cells = <0>;
536 status = "disa 506 status = "disabled";
537 }; 507 };
538 508
539 spi4: spi@990000 { 509 spi4: spi@990000 {
540 compatible = " 510 compatible = "qcom,geni-spi";
541 reg = <0x0 0x9 511 reg = <0x0 0x990000 0x0 0x4000>;
542 #address-cells 512 #address-cells = <1>;
543 #size-cells = 513 #size-cells = <0>;
544 interrupts = < 514 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
545 clocks = <&gcc 515 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
546 clock-names = 516 clock-names = "se";
547 pinctrl-0 = <& 517 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
548 pinctrl-names 518 pinctrl-names = "default";
549 status = "disa 519 status = "disabled";
550 }; 520 };
551 521
552 i2c5: i2c@994000 { 522 i2c5: i2c@994000 {
553 compatible = " 523 compatible = "qcom,geni-i2c";
554 reg = <0x0 0x9 524 reg = <0x0 0x994000 0x0 0x4000>;
555 clocks = <&gcc 525 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
556 clock-names = 526 clock-names = "se";
557 interrupts = < 527 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
558 pinctrl-0 = <& 528 pinctrl-0 = <&qup_i2c5_data_clk>;
559 pinctrl-names 529 pinctrl-names = "default";
560 #address-cells 530 #address-cells = <1>;
561 #size-cells = 531 #size-cells = <0>;
562 status = "disa 532 status = "disabled";
563 }; 533 };
564 534
565 spi5: spi@994000 { 535 spi5: spi@994000 {
566 compatible = " 536 compatible = "qcom,geni-spi";
567 reg = <0x0 0x9 537 reg = <0x0 0x994000 0x0 0x4000>;
568 #address-cells 538 #address-cells = <1>;
569 #size-cells = 539 #size-cells = <0>;
570 interrupts = < 540 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
571 clocks = <&gcc 541 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
572 clock-names = 542 clock-names = "se";
573 pinctrl-0 = <& 543 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
574 pinctrl-names 544 pinctrl-names = "default";
575 status = "disa 545 status = "disabled";
576 }; 546 };
577 547
578 i2c6: i2c@998000 { 548 i2c6: i2c@998000 {
579 compatible = " 549 compatible = "qcom,geni-i2c";
580 reg = <0x0 0x9 550 reg = <0x0 0x998000 0x0 0x4000>;
581 clocks = <&gcc 551 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
582 clock-names = 552 clock-names = "se";
583 interrupts = < 553 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
584 pinctrl-0 = <& 554 pinctrl-0 = <&qup_i2c6_data_clk>;
585 pinctrl-names 555 pinctrl-names = "default";
586 #address-cells 556 #address-cells = <1>;
587 #size-cells = 557 #size-cells = <0>;
588 status = "disa 558 status = "disabled";
589 }; 559 };
590 560
591 spi6: spi@998000 { 561 spi6: spi@998000 {
592 compatible = " 562 compatible = "qcom,geni-spi";
593 reg = <0x0 0x9 563 reg = <0x0 0x998000 0x0 0x4000>;
594 #address-cells 564 #address-cells = <1>;
595 #size-cells = 565 #size-cells = <0>;
596 interrupts = < 566 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
597 clocks = <&gcc 567 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
598 clock-names = 568 clock-names = "se";
599 pinctrl-0 = <& 569 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
600 pinctrl-names 570 pinctrl-names = "default";
601 status = "disa 571 status = "disabled";
602 }; 572 };
603 573
604 uart7: serial@99c000 { 574 uart7: serial@99c000 {
605 compatible = " 575 compatible = "qcom,geni-debug-uart";
606 reg = <0x0 0x9 576 reg = <0x0 0x99c000 0x0 0x4000>;
607 clocks = <&gcc 577 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
608 clock-names = 578 clock-names = "se";
609 pinctrl-0 = <& 579 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>;
610 pinctrl-names 580 pinctrl-names = "default";
611 interrupts = < 581 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
612 status = "disa 582 status = "disabled";
613 }; 583 };
614 }; 584 };
615 585
616 gpi_dma1: dma-controller@a0000 586 gpi_dma1: dma-controller@a00000 {
617 compatible = "qcom,qdu 587 compatible = "qcom,qdu1000-gpi-dma", "qcom,sm6350-gpi-dma";
618 reg = <0x0 0xa00000 0x 588 reg = <0x0 0xa00000 0x0 0x60000>;
619 interrupts = <GIC_SPI 589 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
620 <GIC_SPI 590 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
621 <GIC_SPI 591 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
622 <GIC_SPI 592 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
623 <GIC_SPI 593 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
624 <GIC_SPI 594 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
625 <GIC_SPI 595 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
626 <GIC_SPI 596 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
627 <GIC_SPI 597 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
628 <GIC_SPI 598 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
629 <GIC_SPI 599 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
630 <GIC_SPI 600 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
631 dma-channels = <12>; 601 dma-channels = <12>;
632 dma-channel-mask = <0x 602 dma-channel-mask = <0x3f>;
633 iommus = <&apps_smmu 0 603 iommus = <&apps_smmu 0x116 0x0>;
634 #dma-cells = <3>; 604 #dma-cells = <3>;
635 }; 605 };
636 606
637 qupv3_id_1: geniqup@ac0000 { 607 qupv3_id_1: geniqup@ac0000 {
638 compatible = "qcom,gen 608 compatible = "qcom,geni-se-qup";
639 reg = <0x0 0xac0000 0x 609 reg = <0x0 0xac0000 0x0 0x2000>;
640 clocks = <&gcc GCC_QUP 610 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
641 <&gcc GCC_QUPV 611 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
642 clock-names = "m-ahb", 612 clock-names = "m-ahb", "s-ahb";
643 iommus = <&apps_smmu 0 613 iommus = <&apps_smmu 0x103 0x0>;
644 #address-cells = <2>; 614 #address-cells = <2>;
645 #size-cells = <2>; 615 #size-cells = <2>;
646 ranges; 616 ranges;
647 status = "disabled"; 617 status = "disabled";
648 618
649 uart8: serial@a80000 { 619 uart8: serial@a80000 {
650 compatible = " 620 compatible = "qcom,geni-uart";
651 reg = <0x0 0xa 621 reg = <0x0 0xa80000 0x0 0x4000>;
652 clocks = <&gcc 622 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
653 clock-names = 623 clock-names = "se";
654 pinctrl-0 = <& 624 pinctrl-0 = <&qup_uart8_default>;
655 pinctrl-names 625 pinctrl-names = "default";
656 interrupts = < 626 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
657 #address-cells 627 #address-cells = <1>;
658 #size-cells = 628 #size-cells = <0>;
659 status = "disa 629 status = "disabled";
660 }; 630 };
661 631
662 i2c9: i2c@a84000 { 632 i2c9: i2c@a84000 {
663 compatible = " 633 compatible = "qcom,geni-i2c";
664 reg = <0x0 0xa 634 reg = <0x0 0xa84000 0x0 0x4000>;
665 clocks = <&gcc 635 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
666 clock-names = 636 clock-names = "se";
667 interrupts = < 637 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
668 pinctrl-0 = <& 638 pinctrl-0 = <&qup_i2c9_data_clk>;
669 pinctrl-names 639 pinctrl-names = "default";
670 #address-cells 640 #address-cells = <1>;
671 #size-cells = 641 #size-cells = <0>;
672 status = "disa 642 status = "disabled";
673 }; 643 };
674 644
675 spi9: spi@a84000 { 645 spi9: spi@a84000 {
676 compatible = " 646 compatible = "qcom,geni-spi";
677 reg = <0x0 0xa 647 reg = <0x0 0xa84000 0x0 0x4000>;
678 #address-cells 648 #address-cells = <1>;
679 #size-cells = 649 #size-cells = <0>;
680 interrupts = < 650 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
681 clocks = <&gcc 651 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
682 clock-names = 652 clock-names = "se";
683 pinctrl-0 = <& 653 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
684 pinctrl-names 654 pinctrl-names = "default";
685 status = "disa 655 status = "disabled";
686 }; 656 };
687 657
688 i2c10: i2c@a88000 { 658 i2c10: i2c@a88000 {
689 compatible = " 659 compatible = "qcom,geni-i2c";
690 reg = <0x0 0xa 660 reg = <0x0 0xa88000 0x0 0x4000>;
691 clocks = <&gcc 661 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
692 clock-names = 662 clock-names = "se";
693 interrupts = < 663 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
694 pinctrl-0 = <& 664 pinctrl-0 = <&qup_i2c10_data_clk>;
695 pinctrl-names 665 pinctrl-names = "default";
696 #address-cells 666 #address-cells = <1>;
697 #size-cells = 667 #size-cells = <0>;
698 status = "disa 668 status = "disabled";
699 }; 669 };
700 670
701 spi10: spi@a88000 { 671 spi10: spi@a88000 {
702 compatible = " 672 compatible = "qcom,geni-spi";
703 reg = <0x0 0xa 673 reg = <0x0 0xa88000 0x0 0x4000>;
704 #address-cells 674 #address-cells = <1>;
705 #size-cells = 675 #size-cells = <0>;
706 interrupts = < 676 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
707 clocks = <&gcc 677 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
708 clock-names = 678 clock-names = "se";
709 pinctrl-0 = <& 679 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
710 pinctrl-names 680 pinctrl-names = "default";
711 status = "disa 681 status = "disabled";
712 }; 682 };
713 683
714 i2c11: i2c@a8c000 { 684 i2c11: i2c@a8c000 {
715 compatible = " 685 compatible = "qcom,geni-i2c";
716 reg = <0x0 0xa 686 reg = <0x0 0xa8c000 0x0 0x4000>;
717 clocks = <&gcc 687 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
718 clock-names = 688 clock-names = "se";
719 interrupts = < 689 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
720 pinctrl-0 = <& 690 pinctrl-0 = <&qup_i2c11_data_clk>;
721 pinctrl-names 691 pinctrl-names = "default";
722 #address-cells 692 #address-cells = <1>;
723 #size-cells = 693 #size-cells = <0>;
724 status = "disa 694 status = "disabled";
725 }; 695 };
726 696
727 spi11: spi@a8c000 { 697 spi11: spi@a8c000 {
728 compatible = " 698 compatible = "qcom,geni-spi";
729 reg = <0x0 0xa 699 reg = <0x0 0xa8c000 0x0 0x4000>;
730 #address-cells 700 #address-cells = <1>;
731 #size-cells = 701 #size-cells = <0>;
732 interrupts = < 702 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
733 clocks = <&gcc 703 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
734 clock-names = 704 clock-names = "se";
735 pinctrl-0 = <& 705 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
736 pinctrl-names 706 pinctrl-names = "default";
737 status = "disa 707 status = "disabled";
738 }; 708 };
739 709
740 i2c12: i2c@a90000 { 710 i2c12: i2c@a90000 {
741 compatible = " 711 compatible = "qcom,geni-i2c";
742 reg = <0x0 0xa 712 reg = <0x0 0xa90000 0x0 0x4000>;
743 clocks = <&gcc 713 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
744 clock-names = 714 clock-names = "se";
745 interrupts = < 715 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
746 pinctrl-0 = <& 716 pinctrl-0 = <&qup_i2c12_data_clk>;
747 pinctrl-names 717 pinctrl-names = "default";
748 #address-cells 718 #address-cells = <1>;
749 #size-cells = 719 #size-cells = <0>;
750 status = "disa 720 status = "disabled";
751 }; 721 };
752 722
753 spi12: spi@a90000 { 723 spi12: spi@a90000 {
754 compatible = " 724 compatible = "qcom,geni-spi";
755 reg = <0x0 0xa 725 reg = <0x0 0xa90000 0x0 0x4000>;
756 #address-cells 726 #address-cells = <1>;
757 #size-cells = 727 #size-cells = <0>;
758 interrupts = < 728 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
759 clocks = <&gcc 729 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
760 clock-names = 730 clock-names = "se";
761 pinctrl-0 = <& 731 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
762 pinctrl-names 732 pinctrl-names = "default";
763 status = "disa 733 status = "disabled";
764 }; 734 };
765 735
766 i2c13: i2c@a94000 { 736 i2c13: i2c@a94000 {
767 compatible = " 737 compatible = "qcom,geni-i2c";
768 reg = <0x0 0xa 738 reg = <0x0 0xa94000 0x0 0x4000>;
769 clocks = <&gcc 739 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
770 clock-names = 740 clock-names = "se";
771 interrupts = < 741 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
772 pinctrl-0 = <& 742 pinctrl-0 = <&qup_i2c13_data_clk>;
773 pinctrl-names 743 pinctrl-names = "default";
774 #address-cells 744 #address-cells = <1>;
775 #size-cells = 745 #size-cells = <0>;
776 status = "disa 746 status = "disabled";
777 }; 747 };
778 748
779 uart13: serial@a94000 749 uart13: serial@a94000 {
780 compatible = " 750 compatible = "qcom,geni-uart";
781 reg = <0x0 0xa 751 reg = <0x0 0xa94000 0x0 0x4000>;
782 clocks = <&gcc 752 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
783 clock-names = 753 clock-names = "se";
784 pinctrl-0 = <& 754 pinctrl-0 = <&qup_uart13_default>;
785 pinctrl-names 755 pinctrl-names = "default";
786 interrupts = < 756 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
787 #address-cells 757 #address-cells = <1>;
788 #size-cells = 758 #size-cells = <0>;
789 status = "disa 759 status = "disabled";
790 }; 760 };
791 761
792 spi13: spi@a94000 { 762 spi13: spi@a94000 {
793 compatible = " 763 compatible = "qcom,geni-spi";
794 reg = <0x0 0xa 764 reg = <0x0 0xa94000 0x0 0x4000>;
795 #address-cells 765 #address-cells = <1>;
796 #size-cells = 766 #size-cells = <0>;
797 interrupts = < 767 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
798 clocks = <&gcc 768 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
799 clock-names = 769 clock-names = "se";
800 pinctrl-0 = <& 770 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
801 pinctrl-names 771 pinctrl-names = "default";
802 status = "disa 772 status = "disabled";
803 }; 773 };
804 774
805 i2c14: i2c@a98000 { 775 i2c14: i2c@a98000 {
806 compatible = " 776 compatible = "qcom,geni-i2c";
807 reg = <0x0 0xa 777 reg = <0x0 0xa98000 0x0 0x4000>;
808 clocks = <&gcc 778 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
809 clock-names = 779 clock-names = "se";
810 interrupts = < 780 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
811 pinctrl-0 = <& 781 pinctrl-0 = <&qup_i2c14_data_clk>;
812 pinctrl-names 782 pinctrl-names = "default";
813 #address-cells 783 #address-cells = <1>;
814 #size-cells = 784 #size-cells = <0>;
815 status = "disa 785 status = "disabled";
816 }; 786 };
817 787
818 spi14: spi@a98000 { 788 spi14: spi@a98000 {
819 compatible = " 789 compatible = "qcom,geni-spi";
820 reg = <0x0 0xa 790 reg = <0x0 0xa98000 0x0 0x4000>;
821 #address-cells 791 #address-cells = <1>;
822 #size-cells = 792 #size-cells = <0>;
823 interrupts = < 793 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
824 clocks = <&gcc 794 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
825 clock-names = 795 clock-names = "se";
826 pinctrl-0 = <& 796 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
827 pinctrl-names 797 pinctrl-names = "default";
828 status = "disa 798 status = "disabled";
829 }; 799 };
830 800
831 i2c15: i2c@a9c000 { 801 i2c15: i2c@a9c000 {
832 compatible = " 802 compatible = "qcom,geni-i2c";
833 reg = <0x0 0xa 803 reg = <0x0 0xa9c000 0x0 0x4000>;
834 clocks = <&gcc 804 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
835 clock-names = 805 clock-names = "se";
836 interrupts = < 806 interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>;
837 pinctrl-0 = <& 807 pinctrl-0 = <&qup_i2c15_data_clk>;
838 pinctrl-names 808 pinctrl-names = "default";
839 #address-cells 809 #address-cells = <1>;
840 #size-cells = 810 #size-cells = <0>;
841 status = "disa 811 status = "disabled";
842 }; 812 };
843 813
844 spi15: spi@a9c000 { 814 spi15: spi@a9c000 {
845 compatible = " 815 compatible = "qcom,geni-spi";
846 reg = <0x0 0xa 816 reg = <0x0 0xa9c000 0x0 0x4000>;
847 #address-cells 817 #address-cells = <1>;
848 #size-cells = 818 #size-cells = <0>;
849 interrupts = < 819 interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>;
850 clocks = <&gcc 820 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
851 clock-names = 821 clock-names = "se";
852 pinctrl-0 = <& 822 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
853 pinctrl-names 823 pinctrl-names = "default";
854 status = "disa 824 status = "disabled";
855 }; 825 };
856 }; 826 };
857 827
858 system_noc: interconnect@16400 828 system_noc: interconnect@1640000 {
859 compatible = "qcom,qdu 829 compatible = "qcom,qdu1000-system-noc";
860 reg = <0x0 0x1640000 0 830 reg = <0x0 0x1640000 0x0 0x45080>;
861 qcom,bcm-voters = <&ap 831 qcom,bcm-voters = <&apps_bcm_voter>;
862 #interconnect-cells = 832 #interconnect-cells = <2>;
863 }; 833 };
864 834
865 tcsr_mutex: hwlock@1f40000 { 835 tcsr_mutex: hwlock@1f40000 {
866 compatible = "qcom,tcs 836 compatible = "qcom,tcsr-mutex";
867 reg = <0x0 0x1f40000 0 837 reg = <0x0 0x1f40000 0x0 0x20000>;
868 #hwlock-cells = <1>; 838 #hwlock-cells = <1>;
869 }; 839 };
870 840
871 sdhc: mmc@8804000 { <<
872 compatible = "qcom,qdu <<
873 reg = <0x0 0x08804000 <<
874 <0x0 0x08805000 <<
875 reg-names = "hc", "cqh <<
876 <<
877 interrupts = <GIC_SPI <<
878 <GIC_SPI <<
879 interrupt-names = "hc_ <<
880 <<
881 clocks = <&gcc GCC_SDC <<
882 <&gcc GCC_SDC <<
883 <&rpmhcc RPMH <<
884 clock-names = "iface", <<
885 "core", <<
886 "xo"; <<
887 <<
888 resets = <&gcc GCC_SDC <<
889 <<
890 interconnects = <&syst <<
891 <&gem_ <<
892 interconnect-names = " <<
893 power-domains = <&rpmh <<
894 operating-points-v2 = <<
895 <<
896 iommus = <&apps_smmu 0 <<
897 dma-coherent; <<
898 <<
899 bus-width = <8>; <<
900 <<
901 qcom,dll-config = <0x0 <<
902 qcom,ddr-config = <0x8 <<
903 <<
904 status = "disabled"; <<
905 <<
906 sdhc1_opp_table: opp-t <<
907 compatible = " <<
908 <<
909 opp-384000000 <<
910 opp-hz <<
911 requir <<
912 opp-pe <<
913 opp-av <<
914 }; <<
915 }; <<
916 }; <<
917 <<
918 usb_1_hsphy: phy@88e3000 { <<
919 compatible = "qcom,qdu <<
920 "qcom,usb <<
921 reg = <0x0 0x088e3000 <<
922 #phy-cells = <0>; <<
923 <<
924 clocks =<&gcc GCC_USB2 <<
925 clock-names = "ref"; <<
926 <<
927 resets = <&gcc GCC_QUS <<
928 <<
929 status = "disabled"; <<
930 }; <<
931 <<
932 usb_1_qmpphy: phy@88e5000 { <<
933 compatible = "qcom,qdu <<
934 reg = <0x0 0x088e5000 <<
935 <<
936 clocks = <&gcc GCC_USB <<
937 <&gcc GCC_USB <<
938 <&gcc GCC_USB <<
939 <&gcc GCC_USB <<
940 clock-names = "aux", <<
941 "ref", <<
942 "com_aux <<
943 "pipe"; <<
944 <<
945 resets = <&gcc GCC_USB <<
946 <&gcc GCC_USB <<
947 reset-names = "phy", <<
948 "phy_phy <<
949 <<
950 #clock-cells = <0>; <<
951 clock-output-names = " <<
952 <<
953 #phy-cells = <0>; <<
954 <<
955 status = "disabled"; <<
956 }; <<
957 <<
958 usb_1: usb@a6f8800 { <<
959 compatible = "qcom,qdu <<
960 reg = <0 0x0a6f8800 0 <<
961 #address-cells = <2>; <<
962 #size-cells = <2>; <<
963 ranges; <<
964 <<
965 clocks = <&gcc GCC_CFG <<
966 <&gcc GCC_USB <<
967 <&gcc GCC_USB <<
968 <&gcc GCC_USB <<
969 clock-names = "cfg_noc <<
970 "core", <<
971 "sleep", <<
972 "mock_ut <<
973 <<
974 assigned-clocks = <&gc <<
975 <&gc <<
976 assigned-clock-rates = <<
977 <<
978 interrupts-extended = <<
979 <<
980 <<
981 <<
982 <<
983 interrupt-names = "pwr <<
984 "hs_ <<
985 "dp_ <<
986 "dm_ <<
987 "ss_ <<
988 <<
989 power-domains = <&gcc <<
990 required-opps = <&rpmh <<
991 <<
992 resets = <&gcc GCC_USB <<
993 <<
994 interconnects = <&syst <<
995 &mc_v <<
996 <&gem_ <<
997 &syst <<
998 <<
999 interconnect-names = " <<
1000 <<
1001 <<
1002 status = "disabled"; <<
1003 <<
1004 usb_1_dwc3: usb@a6000 <<
1005 compatible = <<
1006 reg = <0 0x0a <<
1007 interrupts = <<
1008 <<
1009 iommus = <&ap <<
1010 snps,dis_u2_s <<
1011 snps,dis_enbl <<
1012 phys = <&usb_ <<
1013 <&usb_ <<
1014 phy-names = " <<
1015 " <<
1016 <<
1017 ports { <<
1018 #addr <<
1019 #size <<
1020 <<
1021 port@ <<
1022 <<
1023 <<
1024 <<
1025 <<
1026 }; <<
1027 <<
1028 port@ <<
1029 <<
1030 <<
1031 <<
1032 <<
1033 }; <<
1034 }; <<
1035 }; <<
1036 }; <<
1037 <<
1038 pdc: interrupt-controller@b22 841 pdc: interrupt-controller@b220000 {
1039 compatible = "qcom,qd 842 compatible = "qcom,qdu1000-pdc", "qcom,pdc";
1040 reg = <0x0 0xb220000 843 reg = <0x0 0xb220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>;
1041 qcom,pdc-ranges = <0 844 qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>,
1042 <94 845 <94 609 31>, <125 63 1>;
1043 #interrupt-cells = <2 846 #interrupt-cells = <2>;
1044 interrupt-parent = <& 847 interrupt-parent = <&intc>;
1045 interrupt-controller; 848 interrupt-controller;
1046 }; 849 };
1047 850
1048 spmi_bus: spmi@c400000 { 851 spmi_bus: spmi@c400000 {
1049 compatible = "qcom,sp 852 compatible = "qcom,spmi-pmic-arb";
1050 reg = <0x0 0xc400000 853 reg = <0x0 0xc400000 0x0 0x3000>,
1051 <0x0 0xc500000 854 <0x0 0xc500000 0x0 0x400000>,
1052 <0x0 0xc440000 855 <0x0 0xc440000 0x0 0x80000>,
1053 <0x0 0xc4c0000 856 <0x0 0xc4c0000 0x0 0x10000>,
1054 <0x0 0xc42d000 857 <0x0 0xc42d000 0x0 0x4000>;
1055 reg-names = "core", " 858 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1056 interrupts-extended = 859 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
1057 interrupt-names = "pe 860 interrupt-names = "periph_irq";
1058 qcom,ee = <0>; 861 qcom,ee = <0>;
1059 qcom,channel = <0>; 862 qcom,channel = <0>;
1060 #address-cells = <2>; 863 #address-cells = <2>;
1061 #size-cells = <0>; 864 #size-cells = <0>;
1062 interrupt-controller; 865 interrupt-controller;
1063 #interrupt-cells = <4 866 #interrupt-cells = <4>;
1064 }; 867 };
1065 868
1066 tlmm: pinctrl@f000000 { 869 tlmm: pinctrl@f000000 {
1067 compatible = "qcom,qd 870 compatible = "qcom,qdu1000-tlmm";
1068 reg = <0x0 0xf000000 871 reg = <0x0 0xf000000 0x0 0x1000000>;
1069 interrupts = <GIC_SPI 872 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1070 gpio-controller; 873 gpio-controller;
1071 #gpio-cells = <2>; 874 #gpio-cells = <2>;
1072 interrupt-controller; 875 interrupt-controller;
1073 #interrupt-cells = <2 876 #interrupt-cells = <2>;
1074 gpio-ranges = <&tlmm 877 gpio-ranges = <&tlmm 0 0 151>;
1075 wakeup-parent = <&pdc 878 wakeup-parent = <&pdc>;
1076 879
1077 qup_uart0_default: qu 880 qup_uart0_default: qup-uart0-default-state {
1078 pins = "gpio6 881 pins = "gpio6", "gpio7", "gpio8", "gpio9";
1079 function = "q 882 function = "qup00";
1080 }; 883 };
1081 884
1082 qup_i2c1_data_clk: qu 885 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
1083 pins = "gpio1 886 pins = "gpio10", "gpio11";
1084 function = "q 887 function = "qup01";
1085 }; 888 };
1086 889
1087 qup_spi1_data_clk: qu 890 qup_spi1_data_clk: qup-spi1-data-clk-state {
1088 pins = "gpio1 891 pins = "gpio10", "gpio11", "gpio12";
1089 function = "q 892 function = "qup01";
1090 }; 893 };
1091 894
1092 qup_spi1_cs: qup-spi1 895 qup_spi1_cs: qup-spi1-cs-state {
1093 pins = "gpio1 896 pins = "gpio13";
1094 function = "g 897 function = "gpio";
1095 }; 898 };
1096 899
1097 qup_i2c2_data_clk: qu 900 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
1098 pins = "gpio1 901 pins = "gpio12", "gpio13";
1099 function = "q 902 function = "qup02";
1100 }; 903 };
1101 904
1102 qup_spi2_data_clk: qu 905 qup_spi2_data_clk: qup-spi2-data-clk-state {
1103 pins = "gpio1 906 pins = "gpio12", "gpio13", "gpio10";
1104 function = "q 907 function = "qup02";
1105 }; 908 };
1106 909
1107 qup_spi2_cs: qup-spi2 910 qup_spi2_cs: qup-spi2-cs-state {
1108 pins = "gpio1 911 pins = "gpio11";
1109 function = "g 912 function = "gpio";
1110 }; 913 };
1111 914
1112 qup_i2c3_data_clk: qu 915 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
1113 pins = "gpio1 916 pins = "gpio14", "gpio15";
1114 function = "q 917 function = "qup03";
1115 }; 918 };
1116 919
1117 qup_spi3_data_clk: qu 920 qup_spi3_data_clk: qup-spi3-data-clk-state {
1118 pins = "gpio1 921 pins = "gpio14", "gpio15", "gpio16";
1119 function = "q 922 function = "qup03";
1120 }; 923 };
1121 924
1122 qup_spi3_cs: qup-spi3 925 qup_spi3_cs: qup-spi3-cs-state {
1123 pins = "gpio1 926 pins = "gpio17";
1124 function = "g 927 function = "gpio";
1125 }; 928 };
1126 929
1127 qup_i2c4_data_clk: qu 930 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
1128 pins = "gpio1 931 pins = "gpio16", "gpio17";
1129 function = "q 932 function = "qup04";
1130 }; 933 };
1131 934
1132 qup_spi4_data_clk: qu 935 qup_spi4_data_clk: qup-spi4-data-clk-state {
1133 pins = "gpio1 936 pins = "gpio16", "gpio17", "gpio14";
1134 function = "q 937 function = "qup04";
1135 }; 938 };
1136 939
1137 qup_spi4_cs: qup-spi4 940 qup_spi4_cs: qup-spi4-cs-state {
1138 pins = "gpio1 941 pins = "gpio15";
1139 function = "g 942 function = "gpio";
1140 }; 943 };
1141 944
1142 qup_i2c5_data_clk: qu 945 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
1143 pins = "gpio1 946 pins = "gpio130", "gpio131";
1144 function = "q 947 function = "qup05";
1145 }; 948 };
1146 949
1147 qup_spi5_data_clk: qu 950 qup_spi5_data_clk: qup-spi5-data-clk-state {
1148 pins = "gpio1 951 pins = "gpio130", "gpio131", "gpio132";
1149 function = "q 952 function = "qup05";
1150 }; 953 };
1151 954
1152 qup_spi5_cs: qup-spi5 955 qup_spi5_cs: qup-spi5-cs-state {
1153 pins = "gpio1 956 pins = "gpio133";
1154 function = "g 957 function = "gpio";
1155 }; 958 };
1156 959
1157 qup_i2c6_data_clk: qu 960 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
1158 pins = "gpio1 961 pins = "gpio132", "gpio133";
1159 function = "q 962 function = "qup06";
1160 }; 963 };
1161 964
1162 qup_spi6_data_clk: qu 965 qup_spi6_data_clk: qup-spi6-data-clk-state {
1163 pins = "gpio1 966 pins = "gpio132", "gpio133", "gpio130";
1164 function = "q 967 function = "qup06";
1165 }; 968 };
1166 969
1167 qup_spi6_cs: qup-spi6 970 qup_spi6_cs: qup-spi6-cs-state {
1168 pins = "gpio1 971 pins = "gpio131";
1169 function = "g 972 function = "gpio";
1170 }; 973 };
1171 974
1172 qup_uart7_rx: qup-uar 975 qup_uart7_rx: qup-uart7-rx-state {
1173 pins = "gpio1 976 pins = "gpio135";
1174 function = "q 977 function = "qup07";
1175 }; 978 };
1176 979
1177 qup_uart7_tx: qup-uar 980 qup_uart7_tx: qup-uart7-tx-state {
1178 pins = "gpio1 981 pins = "gpio134";
1179 function = "q 982 function = "qup07";
1180 }; 983 };
1181 984
1182 qup_uart8_default: qu 985 qup_uart8_default: qup-uart8-default-state {
1183 pins = "gpio1 986 pins = "gpio18", "gpio19", "gpio20", "gpio21";
1184 function = "q 987 function = "qup10";
1185 }; 988 };
1186 989
1187 qup_i2c9_data_clk: qu 990 qup_i2c9_data_clk: qup-i2c9-data-clk-state {
1188 pins = "gpio2 991 pins = "gpio22", "gpio23";
1189 function = "q 992 function = "qup11";
1190 }; 993 };
1191 994
1192 qup_spi9_data_clk: qu 995 qup_spi9_data_clk: qup-spi9-data-clk-state {
1193 pins = "gpio2 996 pins = "gpio22", "gpio23", "gpio24";
1194 function = "q 997 function = "qup11";
1195 }; 998 };
1196 999
1197 qup_spi9_cs: qup-spi9 1000 qup_spi9_cs: qup-spi9-cs-state {
1198 pins = "gpio2 1001 pins = "gpio25";
1199 function = "g 1002 function = "gpio";
1200 }; 1003 };
1201 1004
1202 qup_i2c10_data_clk: q 1005 qup_i2c10_data_clk: qup-i2c10-data-clk-state {
1203 pins = "gpio2 1006 pins = "gpio24", "gpio25";
1204 function = "q 1007 function = "qup12";
1205 }; 1008 };
1206 1009
1207 qup_spi10_data_clk: q 1010 qup_spi10_data_clk: qup-spi10-data-clk-state {
1208 pins = "gpio2 1011 pins = "gpio24", "gpio25", "gpio22";
1209 function = "q 1012 function = "qup12";
1210 }; 1013 };
1211 1014
1212 qup_spi10_cs: qup-spi 1015 qup_spi10_cs: qup-spi10-cs-state {
1213 pins = "gpio2 1016 pins = "gpio23";
1214 function = "g 1017 function = "gpio";
1215 }; 1018 };
1216 1019
1217 qup_i2c11_data_clk: q 1020 qup_i2c11_data_clk: qup-i2c11-data-clk-state {
1218 pins = "gpio2 1021 pins = "gpio26", "gpio27";
1219 function = "q 1022 function = "qup13";
1220 }; 1023 };
1221 1024
1222 qup_spi11_data_clk: q 1025 qup_spi11_data_clk: qup-spi11-data-clk-state {
1223 pins = "gpio2 1026 pins = "gpio26", "gpio27", "gpio28";
1224 function = "q 1027 function = "qup13";
1225 }; 1028 };
1226 1029
1227 qup_spi11_cs: qup-spi 1030 qup_spi11_cs: qup-spi11-cs-state {
1228 pins = "gpio2 1031 pins = "gpio29";
1229 function = "g 1032 function = "gpio";
1230 }; 1033 };
1231 1034
1232 qup_i2c12_data_clk: q 1035 qup_i2c12_data_clk: qup-i2c12-data-clk-state {
1233 pins = "gpio2 1036 pins = "gpio28", "gpio29";
1234 function = "q 1037 function = "qup14";
1235 }; 1038 };
1236 1039
1237 qup_spi12_data_clk: q 1040 qup_spi12_data_clk: qup-spi12-data-clk-state {
1238 pins = "gpio2 1041 pins = "gpio28", "gpio29", "gpio26";
1239 function = "q 1042 function = "qup14";
1240 }; 1043 };
1241 1044
1242 qup_spi12_cs: qup-spi 1045 qup_spi12_cs: qup-spi12-cs-state {
1243 pins = "gpio2 1046 pins = "gpio27";
1244 function = "g 1047 function = "gpio";
1245 }; 1048 };
1246 1049
1247 qup_i2c13_data_clk: q 1050 qup_i2c13_data_clk: qup-i2c13-data-clk-state {
1248 pins = "gpio3 1051 pins = "gpio30", "gpio31";
1249 function = "q 1052 function = "qup15";
1250 }; 1053 };
1251 1054
1252 qup_spi13_data_clk: q 1055 qup_spi13_data_clk: qup-spi13-data-clk-state {
1253 pins = "gpio3 1056 pins = "gpio30", "gpio31", "gpio32";
1254 function = "q 1057 function = "qup15";
1255 }; 1058 };
1256 1059
1257 qup_spi13_cs: qup-spi 1060 qup_spi13_cs: qup-spi13-cs-state {
1258 pins = "gpio3 1061 pins = "gpio33";
1259 function = "g 1062 function = "gpio";
1260 }; 1063 };
1261 1064
1262 qup_uart13_default: q 1065 qup_uart13_default: qup-uart13-default-state {
1263 pins = "gpio3 1066 pins = "gpio30", "gpio31", "gpio32", "gpio33";
1264 function = "q 1067 function = "qup15";
1265 }; 1068 };
1266 1069
1267 qup_i2c14_data_clk: q 1070 qup_i2c14_data_clk: qup-i2c14-data-clk-state {
1268 pins = "gpio3 1071 pins = "gpio34", "gpio35";
1269 function = "q 1072 function = "qup16";
1270 }; 1073 };
1271 1074
1272 qup_spi14_data_clk: q 1075 qup_spi14_data_clk: qup-spi14-data-clk-state {
1273 pins = "gpio3 1076 pins = "gpio34", "gpio35", "gpio36";
1274 function = "q 1077 function = "qup16";
1275 }; 1078 };
1276 1079
1277 qup_spi14_cs: qup-spi 1080 qup_spi14_cs: qup-spi14-cs-state {
1278 pins = "gpio3 1081 pins = "gpio37", "gpio38";
1279 function = "g 1082 function = "gpio";
1280 }; 1083 };
1281 1084
1282 qup_i2c15_data_clk: q 1085 qup_i2c15_data_clk: qup-i2c15-data-clk-state {
1283 pins = "gpio4 1086 pins = "gpio40", "gpio41";
1284 function = "q 1087 function = "qup17";
1285 }; 1088 };
1286 1089
1287 qup_spi15_data_clk: q 1090 qup_spi15_data_clk: qup-spi15-data-clk-state {
1288 pins = "gpio4 1091 pins = "gpio40", "gpio41", "gpio30";
1289 function = "q 1092 function = "qup17";
1290 }; 1093 };
1291 1094
1292 qup_spi15_cs: qup-spi 1095 qup_spi15_cs: qup-spi15-cs-state {
1293 pins = "gpio3 1096 pins = "gpio31";
1294 function = "g 1097 function = "gpio";
1295 }; 1098 };
1296 <<
1297 sdc_on_state: sdc-on- <<
1298 clk-pins { <<
1299 pins <<
1300 drive <<
1301 bias- <<
1302 }; <<
1303 <<
1304 cmd-pins { <<
1305 pins <<
1306 drive <<
1307 bias- <<
1308 }; <<
1309 <<
1310 data-pins { <<
1311 pins <<
1312 drive <<
1313 bias- <<
1314 }; <<
1315 <<
1316 rclk-pins { <<
1317 pins <<
1318 bias- <<
1319 }; <<
1320 }; <<
1321 <<
1322 sdc_off_state: sdc-of <<
1323 clk-pins { <<
1324 pins <<
1325 drive <<
1326 bias- <<
1327 }; <<
1328 <<
1329 cmd-pins { <<
1330 pins <<
1331 drive <<
1332 bias- <<
1333 }; <<
1334 <<
1335 data-pins { <<
1336 pins <<
1337 drive <<
1338 bias- <<
1339 }; <<
1340 <<
1341 rclk-pins { <<
1342 pins <<
1343 bias- <<
1344 }; <<
1345 }; <<
1346 }; <<
1347 <<
1348 sram@14680000 { <<
1349 compatible = "qcom,qd <<
1350 reg = <0 0x14680000 0 <<
1351 ranges = <0 0 0x14680 <<
1352 #address-cells = <1>; <<
1353 #size-cells = <1>; <<
1354 <<
1355 pil-reloc@94c { <<
1356 compatible = <<
1357 reg = <0x94c <<
1358 }; <<
1359 }; 1099 };
1360 1100
1361 apps_smmu: iommu@15000000 { 1101 apps_smmu: iommu@15000000 {
1362 compatible = "qcom,qd !! 1102 compatible = "qcom,qdu1000-smmu-500", "arm,mmu-500";
1363 reg = <0x0 0x15000000 1103 reg = <0x0 0x15000000 0x0 0x100000>;
1364 #iommu-cells = <2>; 1104 #iommu-cells = <2>;
1365 #global-interrupts = 1105 #global-interrupts = <2>;
1366 interrupts = <GIC_SPI 1106 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
1367 <GIC_SPI 1107 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
1368 <GIC_SPI 1108 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1369 <GIC_SPI 1109 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
1370 <GIC_SPI 1110 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
1371 <GIC_SPI 1111 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
1372 <GIC_SPI 1112 <GIC_SPI 671 IRQ_TYPE_LEVEL_HIGH>,
1373 <GIC_SPI 1113 <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
1374 <GIC_SPI 1114 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
1375 <GIC_SPI 1115 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
1376 <GIC_SPI 1116 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
1377 <GIC_SPI 1117 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1378 <GIC_SPI 1118 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1379 <GIC_SPI 1119 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1380 <GIC_SPI 1120 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1381 <GIC_SPI 1121 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1382 <GIC_SPI 1122 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
1383 <GIC_SPI 1123 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1384 <GIC_SPI 1124 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
1385 <GIC_SPI 1125 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1386 <GIC_SPI 1126 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1387 <GIC_SPI 1127 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
1388 <GIC_SPI 1128 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
1389 <GIC_SPI 1129 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
1390 <GIC_SPI 1130 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
1391 <GIC_SPI 1131 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
1392 <GIC_SPI 1132 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
1393 <GIC_SPI 1133 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1394 <GIC_SPI 1134 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1395 <GIC_SPI 1135 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1396 <GIC_SPI 1136 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
1397 <GIC_SPI 1137 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
1398 <GIC_SPI 1138 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
1399 <GIC_SPI 1139 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
1400 <GIC_SPI 1140 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
1401 <GIC_SPI 1141 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
1402 <GIC_SPI 1142 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
1403 <GIC_SPI 1143 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
1404 <GIC_SPI 1144 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
1405 <GIC_SPI 1145 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
1406 <GIC_SPI 1146 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
1407 <GIC_SPI 1147 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
1408 <GIC_SPI 1148 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
1409 <GIC_SPI 1149 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
1410 <GIC_SPI 1150 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
1411 <GIC_SPI 1151 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
1412 <GIC_SPI 1152 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
1413 <GIC_SPI 1153 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
1414 <GIC_SPI 1154 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
1415 }; 1155 };
1416 1156
1417 intc: interrupt-controller@17 1157 intc: interrupt-controller@17200000 {
1418 compatible = "arm,gic 1158 compatible = "arm,gic-v3";
1419 reg = <0x0 0x17200000 1159 reg = <0x0 0x17200000 0x0 0x10000>, /* GICD */
1420 <0x0 0x17260000 1160 <0x0 0x17260000 0x0 0x80000>; /* GICR * 4 */
1421 interrupts = <GIC_PPI 1161 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
1422 #interrupt-cells = <3 1162 #interrupt-cells = <3>;
1423 interrupt-controller; 1163 interrupt-controller;
1424 #redistributor-region 1164 #redistributor-regions = <1>;
1425 redistributor-stride 1165 redistributor-stride = <0x0 0x20000>;
1426 }; 1166 };
1427 1167
1428 timer@17420000 { 1168 timer@17420000 {
1429 compatible = "arm,arm 1169 compatible = "arm,armv7-timer-mem";
1430 reg = <0x0 0x17420000 1170 reg = <0x0 0x17420000 0x0 0x1000>;
1431 #address-cells = <1>; 1171 #address-cells = <1>;
1432 #size-cells = <1>; 1172 #size-cells = <1>;
1433 ranges = <0x0 0x0 0x0 1173 ranges = <0x0 0x0 0x0 0x20000000>;
1434 1174
1435 frame@17421000 { 1175 frame@17421000 {
1436 reg = <0x1742 1176 reg = <0x17421000 0x1000>,
1437 <0x1742 1177 <0x17422000 0x1000>;
1438 interrupts = 1178 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
1439 1179 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1440 frame-number 1180 frame-number = <0>;
1441 }; 1181 };
1442 1182
1443 frame@17423000 { 1183 frame@17423000 {
1444 reg = <0x1742 1184 reg = <0x17423000 0x1000>;
1445 interrupts = 1185 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1446 frame-number 1186 frame-number = <1>;
1447 status = "dis 1187 status = "disabled";
1448 }; 1188 };
1449 1189
1450 frame@17425000 { 1190 frame@17425000 {
1451 reg = <0x1742 1191 reg = <0x17425000 0x1000>,
1452 <0x1742 1192 <0x17426000 0x1000>;
1453 interrupts = 1193 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1454 frame-number 1194 frame-number = <2>;
1455 status = "dis 1195 status = "disabled";
1456 }; 1196 };
1457 1197
1458 frame@17427000 { 1198 frame@17427000 {
1459 reg = <0x1742 1199 reg = <0x17427000 0x1000>;
1460 interrupts = 1200 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1461 frame-number 1201 frame-number = <3>;
1462 status = "dis 1202 status = "disabled";
1463 }; 1203 };
1464 1204
1465 frame@17429000 { 1205 frame@17429000 {
1466 reg = <0x1742 1206 reg = <0x17429000 0x1000>;
1467 interrupts = 1207 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1468 frame-number 1208 frame-number = <4>;
1469 status = "dis 1209 status = "disabled";
1470 }; 1210 };
1471 1211
1472 frame@1742b000 { 1212 frame@1742b000 {
1473 reg = <0x1742 1213 reg = <0x1742b000 0x1000>;
1474 interrupts = 1214 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1475 frame-number 1215 frame-number = <5>;
1476 status = "dis 1216 status = "disabled";
1477 }; 1217 };
1478 1218
1479 frame@1742d000 { 1219 frame@1742d000 {
1480 reg = <0x1742 1220 reg = <0x1742d000 0x1000>;
1481 interrupts = 1221 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1482 frame-number 1222 frame-number = <6>;
1483 status = "dis 1223 status = "disabled";
1484 }; 1224 };
1485 }; 1225 };
1486 1226
1487 apps_rsc: rsc@17a00000 { 1227 apps_rsc: rsc@17a00000 {
1488 compatible = "qcom,rp 1228 compatible = "qcom,rpmh-rsc";
1489 reg = <0x0 0x17a00000 1229 reg = <0x0 0x17a00000 0x0 0x10000>,
1490 <0x0 0x17a10000 1230 <0x0 0x17a10000 0x0 0x10000>,
1491 <0x0 0x17a20000 1231 <0x0 0x17a20000 0x0 0x10000>;
1492 reg-names = "drv-0", 1232 reg-names = "drv-0", "drv-1", "drv-2";
1493 interrupts = <GIC_SPI 1233 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
1494 <GIC_SPI 1234 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
1495 <GIC_SPI 1235 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1496 qcom,tcs-offset = <0x 1236 qcom,tcs-offset = <0xd00>;
1497 qcom,drv-id = <2>; 1237 qcom,drv-id = <2>;
1498 qcom,tcs-config = <AC 1238 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
1499 <WA 1239 <WAKE_TCS 3>, <CONTROL_TCS 0>;
1500 label = "apps_rsc"; 1240 label = "apps_rsc";
1501 power-domains = <&CLU 1241 power-domains = <&CLUSTER_PD>;
1502 1242
1503 apps_bcm_voter: bcm-v 1243 apps_bcm_voter: bcm-voter {
1504 compatible = 1244 compatible = "qcom,bcm-voter";
1505 }; 1245 };
1506 1246
1507 rpmhcc: clock-control 1247 rpmhcc: clock-controller {
1508 compatible = 1248 compatible = "qcom,qdu1000-rpmh-clk";
1509 clocks = <&xo 1249 clocks = <&xo_board>;
1510 clock-names = 1250 clock-names = "xo";
1511 #clock-cells 1251 #clock-cells = <1>;
1512 }; 1252 };
1513 1253
1514 rpmhpd: power-control 1254 rpmhpd: power-controller {
1515 compatible = 1255 compatible = "qcom,qdu1000-rpmhpd";
1516 #power-domain 1256 #power-domain-cells = <1>;
1517 operating-poi 1257 operating-points-v2 = <&rpmhpd_opp_table>;
1518 1258
1519 rpmhpd_opp_ta 1259 rpmhpd_opp_table: opp-table {
1520 compa 1260 compatible = "operating-points-v2";
1521 1261
1522 rpmhp 1262 rpmhpd_opp_ret: opp1 {
1523 1263 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
1524 }; 1264 };
1525 1265
1526 rpmhp 1266 rpmhpd_opp_min_svs: opp2 {
1527 1267 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
1528 }; 1268 };
1529 1269
1530 rpmhp 1270 rpmhpd_opp_low_svs: opp3 {
1531 1271 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1532 }; 1272 };
1533 1273
1534 rpmhp 1274 rpmhpd_opp_svs: opp4 {
1535 1275 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1536 }; 1276 };
1537 1277
1538 rpmhp 1278 rpmhpd_opp_svs_l1: opp5 {
1539 1279 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1540 }; 1280 };
1541 1281
1542 rpmhp 1282 rpmhpd_opp_nom: opp6 {
1543 1283 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1544 }; 1284 };
1545 1285
1546 rpmhp 1286 rpmhpd_opp_nom_l1: opp7 {
1547 1287 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1548 }; 1288 };
1549 1289
1550 rpmhp 1290 rpmhpd_opp_nom_l2: opp8 {
1551 1291 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
1552 }; 1292 };
1553 1293
1554 rpmhp 1294 rpmhpd_opp_turbo: opp9 {
1555 1295 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1556 }; 1296 };
1557 1297
1558 rpmhp 1298 rpmhpd_opp_turbo_l1: opp10 {
1559 1299 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
1560 }; 1300 };
1561 }; 1301 };
1562 }; 1302 };
1563 }; 1303 };
1564 1304
1565 cpufreq_hw: cpufreq@17d90000 1305 cpufreq_hw: cpufreq@17d90000 {
1566 compatible = "qcom,qd 1306 compatible = "qcom,qdu1000-cpufreq-epss", "qcom,cpufreq-epss";
1567 reg = <0x0 0x17d90000 1307 reg = <0x0 0x17d90000 0x0 0x1000>, <0x0 0x17d91000 0x0 0x1000>;
1568 reg-names = "freq-dom 1308 reg-names = "freq-domain0", "freq-domain1";
1569 clocks = <&rpmhcc RPM 1309 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
1570 clock-names = "xo", " 1310 clock-names = "xo", "alternate";
1571 #freq-domain-cells = 1311 #freq-domain-cells = <1>;
1572 #clock-cells = <1>; <<
1573 }; 1312 };
1574 1313
1575 gem_noc: interconnect@1910000 1314 gem_noc: interconnect@19100000 {
1576 compatible = "qcom,qd 1315 compatible = "qcom,qdu1000-gem-noc";
1577 reg = <0x0 0x19100000 1316 reg = <0x0 0x19100000 0x0 0xB8080>;
1578 qcom,bcm-voters = <&a 1317 qcom,bcm-voters = <&apps_bcm_voter>;
1579 #interconnect-cells = 1318 #interconnect-cells = <2>;
1580 }; <<
1581 <<
1582 system-cache-controller@19200 <<
1583 compatible = "qcom,qd <<
1584 reg = <0 0x19200000 0 <<
1585 <0 0x19300000 0 <<
1586 <0 0x19600000 0 <<
1587 <0 0x19700000 0 <<
1588 <0 0x19a00000 0 <<
1589 <0 0x19b00000 0 <<
1590 <0 0x19e00000 0 <<
1591 <0 0x19f00000 0 <<
1592 <0 0x1a200000 0 <<
1593 reg-names = "llcc0_ba <<
1594 "llcc1_ba <<
1595 "llcc2_ba <<
1596 "llcc3_ba <<
1597 "llcc4_ba <<
1598 "llcc5_ba <<
1599 "llcc6_ba <<
1600 "llcc7_ba <<
1601 "llcc_bro <<
1602 interrupts = <GIC_SPI <<
1603 <<
1604 nvmem-cells = <&multi <<
1605 nvmem-cell-names = "m <<
1606 }; <<
1607 <<
1608 sec_qfprom: efuse@221c8000 { <<
1609 compatible = "qcom,qd <<
1610 reg = <0 0x221c8000 0 <<
1611 #address-cells = <1>; <<
1612 #size-cells = <1>; <<
1613 <<
1614 multi_chan_ddr: multi <<
1615 reg = <0x12b <<
1616 bits = <0 2>; <<
1617 }; <<
1618 }; 1319 };
1619 }; 1320 };
1620 1321
1621 timer { 1322 timer {
1622 compatible = "arm,armv8-timer 1323 compatible = "arm,armv8-timer";
1623 interrupts = <GIC_PPI 13 (GIC 1324 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1624 <GIC_PPI 14 (GIC 1325 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1625 <GIC_PPI 11 (GIC 1326 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1626 <GIC_PPI 10 (GIC 1327 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1627 <GIC_PPI 12 (GIC 1328 <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
1628 }; 1329 };
1629 }; 1330 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.