1 // SPDX-License-Identifier: BSD-3-Clause 1 // SPDX-License-Identifier: BSD-3-Clause
2 /* 2 /*
3 * Copyright (c) 2022 Qualcomm Innovation Cent 3 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
4 */ 4 */
5 5
6 #include <dt-bindings/clock/qcom,qdu1000-gcc.h 6 #include <dt-bindings/clock/qcom,qdu1000-gcc.h>
7 #include <dt-bindings/clock/qcom,rpmh.h> 7 #include <dt-bindings/clock/qcom,rpmh.h>
8 #include <dt-bindings/dma/qcom-gpi.h> 8 #include <dt-bindings/dma/qcom-gpi.h>
9 #include <dt-bindings/gpio/gpio.h> <<
10 #include <dt-bindings/interconnect/qcom,icc.h> <<
11 #include <dt-bindings/interconnect/qcom,qdu100 9 #include <dt-bindings/interconnect/qcom,qdu1000-rpmh.h>
12 #include <dt-bindings/interrupt-controller/arm 10 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/power/qcom-rpmpd.h> 11 #include <dt-bindings/power/qcom-rpmpd.h>
14 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 12 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
15 13
16 / { 14 / {
17 interrupt-parent = <&intc>; 15 interrupt-parent = <&intc>;
18 16
19 #address-cells = <2>; 17 #address-cells = <2>;
20 #size-cells = <2>; 18 #size-cells = <2>;
21 19
22 chosen: chosen { }; 20 chosen: chosen { };
23 21
24 cpus { 22 cpus {
25 #address-cells = <2>; 23 #address-cells = <2>;
26 #size-cells = <0>; 24 #size-cells = <0>;
27 25
28 CPU0: cpu@0 { 26 CPU0: cpu@0 {
29 device_type = "cpu"; 27 device_type = "cpu";
30 compatible = "arm,cort 28 compatible = "arm,cortex-a55";
31 reg = <0x0 0x0>; 29 reg = <0x0 0x0>;
32 clocks = <&cpufreq_hw 30 clocks = <&cpufreq_hw 0>;
33 enable-method = "psci" 31 enable-method = "psci";
34 power-domains = <&CPU_ 32 power-domains = <&CPU_PD0>;
35 power-domain-names = " 33 power-domain-names = "psci";
36 qcom,freq-domains = <& 34 qcom,freq-domains = <&cpufreq_hw 0>;
37 next-level-cache = <&L 35 next-level-cache = <&L2_0>;
38 L2_0: l2-cache { 36 L2_0: l2-cache {
39 compatible = " 37 compatible = "cache";
40 cache-level = 38 cache-level = <2>;
41 cache-unified; 39 cache-unified;
42 next-level-cac 40 next-level-cache = <&L3_0>;
43 L3_0: l3-cache 41 L3_0: l3-cache {
44 compat 42 compatible = "cache";
45 cache- 43 cache-level = <3>;
46 cache- 44 cache-unified;
47 }; 45 };
48 }; 46 };
49 }; 47 };
50 48
51 CPU1: cpu@100 { 49 CPU1: cpu@100 {
52 device_type = "cpu"; 50 device_type = "cpu";
53 compatible = "arm,cort 51 compatible = "arm,cortex-a55";
54 reg = <0x0 0x100>; 52 reg = <0x0 0x100>;
55 clocks = <&cpufreq_hw 53 clocks = <&cpufreq_hw 0>;
56 enable-method = "psci" 54 enable-method = "psci";
57 power-domains = <&CPU_ 55 power-domains = <&CPU_PD1>;
58 power-domain-names = " 56 power-domain-names = "psci";
59 qcom,freq-domains = <& 57 qcom,freq-domains = <&cpufreq_hw 0>;
60 next-level-cache = <&L 58 next-level-cache = <&L2_100>;
61 L2_100: l2-cache { 59 L2_100: l2-cache {
62 compatible = " 60 compatible = "cache";
63 cache-level = 61 cache-level = <2>;
64 cache-unified; 62 cache-unified;
65 next-level-cac 63 next-level-cache = <&L3_0>;
66 }; 64 };
67 }; 65 };
68 66
69 CPU2: cpu@200 { 67 CPU2: cpu@200 {
70 device_type = "cpu"; 68 device_type = "cpu";
71 compatible = "arm,cort 69 compatible = "arm,cortex-a55";
72 reg = <0x0 0x200>; 70 reg = <0x0 0x200>;
73 clocks = <&cpufreq_hw 71 clocks = <&cpufreq_hw 0>;
74 enable-method = "psci" 72 enable-method = "psci";
75 power-domains = <&CPU_ 73 power-domains = <&CPU_PD2>;
76 power-domain-names = " 74 power-domain-names = "psci";
77 qcom,freq-domains = <& 75 qcom,freq-domains = <&cpufreq_hw 0>;
78 next-level-cache = <&L 76 next-level-cache = <&L2_200>;
79 L2_200: l2-cache { 77 L2_200: l2-cache {
80 compatible = " 78 compatible = "cache";
81 cache-level = 79 cache-level = <2>;
82 cache-unified; 80 cache-unified;
83 next-level-cac 81 next-level-cache = <&L3_0>;
84 }; 82 };
85 }; 83 };
86 84
87 CPU3: cpu@300 { 85 CPU3: cpu@300 {
88 device_type = "cpu"; 86 device_type = "cpu";
89 compatible = "arm,cort 87 compatible = "arm,cortex-a55";
90 reg = <0x0 0x300>; 88 reg = <0x0 0x300>;
91 clocks = <&cpufreq_hw 89 clocks = <&cpufreq_hw 0>;
92 enable-method = "psci" 90 enable-method = "psci";
93 power-domains = <&CPU_ 91 power-domains = <&CPU_PD3>;
94 power-domain-names = " 92 power-domain-names = "psci";
95 qcom,freq-domains = <& 93 qcom,freq-domains = <&cpufreq_hw 0>;
96 next-level-cache = <&L 94 next-level-cache = <&L2_300>;
97 L2_300: l2-cache { 95 L2_300: l2-cache {
98 compatible = " 96 compatible = "cache";
99 cache-level = 97 cache-level = <2>;
100 cache-unified; 98 cache-unified;
101 next-level-cac 99 next-level-cache = <&L3_0>;
102 }; 100 };
103 }; 101 };
104 102
105 cpu-map { 103 cpu-map {
106 cluster0 { 104 cluster0 {
107 core0 { 105 core0 {
108 cpu = 106 cpu = <&CPU0>;
109 }; 107 };
110 108
111 core1 { 109 core1 {
112 cpu = 110 cpu = <&CPU1>;
113 }; 111 };
114 112
115 core2 { 113 core2 {
116 cpu = 114 cpu = <&CPU2>;
117 }; 115 };
118 116
119 core3 { 117 core3 {
120 cpu = 118 cpu = <&CPU3>;
121 }; 119 };
122 }; 120 };
123 }; 121 };
124 }; 122 };
125 123
126 idle-states { 124 idle-states {
127 entry-method = "psci"; 125 entry-method = "psci";
128 126
129 CPU_OFF: cpu-sleep-0 { 127 CPU_OFF: cpu-sleep-0 {
130 compatible = "arm,idle 128 compatible = "arm,idle-state";
131 entry-latency-us = <27 129 entry-latency-us = <274>;
132 exit-latency-us = <480 130 exit-latency-us = <480>;
133 min-residency-us = <39 131 min-residency-us = <3934>;
134 arm,psci-suspend-param 132 arm,psci-suspend-param = <0x40000004>;
135 local-timer-stop; 133 local-timer-stop;
136 }; 134 };
137 }; 135 };
138 136
139 domain-idle-states { 137 domain-idle-states {
140 CLUSTER_SLEEP_0: cluster-sleep 138 CLUSTER_SLEEP_0: cluster-sleep-0 {
141 compatible = "domain-i 139 compatible = "domain-idle-state";
142 entry-latency-us = <58 140 entry-latency-us = <584>;
143 exit-latency-us = <233 141 exit-latency-us = <2332>;
144 min-residency-us = <61 142 min-residency-us = <6118>;
145 arm,psci-suspend-param 143 arm,psci-suspend-param = <0x41000044>;
146 }; 144 };
147 145
148 CLUSTER_SLEEP_1: cluster-sleep 146 CLUSTER_SLEEP_1: cluster-sleep-1 {
149 compatible = "domain-i 147 compatible = "domain-idle-state";
150 entry-latency-us = <28 148 entry-latency-us = <2893>;
151 exit-latency-us = <402 149 exit-latency-us = <4023>;
152 min-residency-us = <99 150 min-residency-us = <9987>;
153 arm,psci-suspend-param 151 arm,psci-suspend-param = <0x41003344>;
154 }; 152 };
155 }; 153 };
156 154
157 firmware { 155 firmware {
158 scm { 156 scm {
159 compatible = "qcom,scm 157 compatible = "qcom,scm-qdu1000", "qcom,scm";
160 }; 158 };
161 }; 159 };
162 160
163 mc_virt: interconnect-0 { 161 mc_virt: interconnect-0 {
164 compatible = "qcom,qdu1000-mc- 162 compatible = "qcom,qdu1000-mc-virt";
165 qcom,bcm-voters = <&apps_bcm_v 163 qcom,bcm-voters = <&apps_bcm_voter>;
166 #interconnect-cells = <2>; 164 #interconnect-cells = <2>;
167 }; 165 };
168 166
169 clk_virt: interconnect-1 { 167 clk_virt: interconnect-1 {
170 compatible = "qcom,qdu1000-clk 168 compatible = "qcom,qdu1000-clk-virt";
171 qcom,bcm-voters = <&apps_bcm_v 169 qcom,bcm-voters = <&apps_bcm_voter>;
172 #interconnect-cells = <2>; 170 #interconnect-cells = <2>;
173 }; 171 };
174 172
175 memory@80000000 { 173 memory@80000000 {
176 device_type = "memory"; 174 device_type = "memory";
177 /* We expect the bootloader to 175 /* We expect the bootloader to fill in the size */
178 reg = <0x0 0x80000000 0x0 0x0> 176 reg = <0x0 0x80000000 0x0 0x0>;
179 }; 177 };
180 178
181 pmu { 179 pmu {
182 compatible = "arm,cortex-a55-p !! 180 compatible = "arm,armv8-pmuv3";
183 interrupts = <GIC_PPI 7 IRQ_TY 181 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
184 }; 182 };
185 183
186 psci { 184 psci {
187 compatible = "arm,psci-1.0"; 185 compatible = "arm,psci-1.0";
188 method = "smc"; 186 method = "smc";
189 187
190 CPU_PD0: power-domain-cpu0 { 188 CPU_PD0: power-domain-cpu0 {
191 #power-domain-cells = 189 #power-domain-cells = <0>;
192 power-domains = <&CLUS 190 power-domains = <&CLUSTER_PD>;
193 domain-idle-states = < 191 domain-idle-states = <&CPU_OFF>;
194 }; 192 };
195 193
196 CPU_PD1: power-domain-cpu1 { 194 CPU_PD1: power-domain-cpu1 {
197 #power-domain-cells = 195 #power-domain-cells = <0>;
198 power-domains = <&CLUS 196 power-domains = <&CLUSTER_PD>;
199 domain-idle-states = < 197 domain-idle-states = <&CPU_OFF>;
200 }; 198 };
201 199
202 CPU_PD2: power-domain-cpu2 { 200 CPU_PD2: power-domain-cpu2 {
203 #power-domain-cells = 201 #power-domain-cells = <0>;
204 power-domains = <&CLUS 202 power-domains = <&CLUSTER_PD>;
205 domain-idle-states = < 203 domain-idle-states = <&CPU_OFF>;
206 }; 204 };
207 205
208 CPU_PD3: power-domain-cpu3 { 206 CPU_PD3: power-domain-cpu3 {
209 #power-domain-cells = 207 #power-domain-cells = <0>;
210 power-domains = <&CLUS 208 power-domains = <&CLUSTER_PD>;
211 domain-idle-states = < 209 domain-idle-states = <&CPU_OFF>;
212 }; 210 };
213 211
214 CLUSTER_PD: power-domain-clust 212 CLUSTER_PD: power-domain-cluster {
215 #power-domain-cells = 213 #power-domain-cells = <0>;
216 domain-idle-states = < 214 domain-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_1>;
217 }; 215 };
218 }; 216 };
219 217
220 reserved_memory: reserved-memory { 218 reserved_memory: reserved-memory {
221 #address-cells = <2>; 219 #address-cells = <2>;
222 #size-cells = <2>; 220 #size-cells = <2>;
223 ranges; 221 ranges;
224 222
225 hyp_mem: hyp@80000000 { 223 hyp_mem: hyp@80000000 {
226 reg = <0x0 0x80000000 224 reg = <0x0 0x80000000 0x0 0x600000>;
227 no-map; 225 no-map;
228 }; 226 };
229 227
230 xbl_dt_log_mem: xbl-dt-log@806 228 xbl_dt_log_mem: xbl-dt-log@80600000 {
231 reg = <0x0 0x80600000 229 reg = <0x0 0x80600000 0x0 0x40000>;
232 no-map; 230 no-map;
233 }; 231 };
234 232
235 xbl_ramdump_mem: xbl-ramdump@8 233 xbl_ramdump_mem: xbl-ramdump@80640000 {
236 reg = <0x0 0x80640000 234 reg = <0x0 0x80640000 0x0 0x1c0000>;
237 no-map; 235 no-map;
238 }; 236 };
239 237
240 aop_image_mem: aop-image@80800 238 aop_image_mem: aop-image@80800000 {
241 reg = <0x0 0x80800000 239 reg = <0x0 0x80800000 0x0 0x60000>;
242 no-map; 240 no-map;
243 }; 241 };
244 242
245 aop_cmd_db_mem: aop-cmd-db@808 243 aop_cmd_db_mem: aop-cmd-db@80860000 {
246 compatible = "qcom,cmd 244 compatible = "qcom,cmd-db";
247 reg = <0x0 0x80860000 245 reg = <0x0 0x80860000 0x0 0x20000>;
248 no-map; 246 no-map;
249 }; 247 };
250 248
251 aop_config_mem: aop-config@808 249 aop_config_mem: aop-config@80880000 {
252 reg = <0x0 0x80880000 250 reg = <0x0 0x80880000 0x0 0x20000>;
253 no-map; 251 no-map;
254 }; 252 };
255 253
256 tme_crash_dump_mem: tme-crash- 254 tme_crash_dump_mem: tme-crash-dump@808a0000 {
257 reg = <0x0 0x808a0000 255 reg = <0x0 0x808a0000 0x0 0x40000>;
258 no-map; 256 no-map;
259 }; 257 };
260 258
261 tme_log_mem: tme-log@808e0000 259 tme_log_mem: tme-log@808e0000 {
262 reg = <0x0 0x808e0000 260 reg = <0x0 0x808e0000 0x0 0x4000>;
263 no-map; 261 no-map;
264 }; 262 };
265 263
266 uefi_log_mem: uefi-log@808e400 264 uefi_log_mem: uefi-log@808e4000 {
267 reg = <0x0 0x808e4000 265 reg = <0x0 0x808e4000 0x0 0x10000>;
268 no-map; 266 no-map;
269 }; 267 };
270 268
271 smem_mem: smem@80900000 { 269 smem_mem: smem@80900000 {
272 compatible = "qcom,sme 270 compatible = "qcom,smem";
273 reg = <0x0 0x80900000 271 reg = <0x0 0x80900000 0x0 0x200000>;
274 no-map; 272 no-map;
275 hwlocks = <&tcsr_mutex 273 hwlocks = <&tcsr_mutex 3>;
276 }; 274 };
277 275
278 cpucp_fw_mem: cpucp-fw@80b0000 276 cpucp_fw_mem: cpucp-fw@80b00000 {
279 reg = <0x0 0x80b00000 277 reg = <0x0 0x80b00000 0x0 0x100000>;
280 no-map; 278 no-map;
281 }; 279 };
282 280
283 xbl_sc_mem: memory@80c00000 { 281 xbl_sc_mem: memory@80c00000 {
284 reg = <0x0 0x80c00000 282 reg = <0x0 0x80c00000 0x0 0x40000>;
285 no-map; 283 no-map;
286 }; 284 };
287 285
288 tz_stat_mem: tz-stat@81d00000 286 tz_stat_mem: tz-stat@81d00000 {
289 reg = <0x0 0x81d00000 287 reg = <0x0 0x81d00000 0x0 0x100000>;
290 no-map; 288 no-map;
291 }; 289 };
292 290
293 tags_mem: tags@81e00000 { 291 tags_mem: tags@81e00000 {
294 reg = <0x0 0x81e00000 292 reg = <0x0 0x81e00000 0x0 0x500000>;
295 no-map; 293 no-map;
296 }; 294 };
297 295
298 qtee_mem: qtee@82300000 { 296 qtee_mem: qtee@82300000 {
299 reg = <0x0 0x82300000 297 reg = <0x0 0x82300000 0x0 0x500000>;
300 no-map; 298 no-map;
301 }; 299 };
302 300
303 ta_mem: ta@82800000 { 301 ta_mem: ta@82800000 {
304 reg = <0x0 0x82800000 302 reg = <0x0 0x82800000 0x0 0xa00000>;
305 no-map; 303 no-map;
306 }; 304 };
307 305
308 fs1_mem: fs1@83200000 { 306 fs1_mem: fs1@83200000 {
309 reg = <0x0 0x83200000 307 reg = <0x0 0x83200000 0x0 0x400000>;
310 no-map; 308 no-map;
311 }; 309 };
312 310
313 fs2_mem: fs2@83600000 { 311 fs2_mem: fs2@83600000 {
314 reg = <0x0 0x83600000 312 reg = <0x0 0x83600000 0x0 0x400000>;
315 no-map; 313 no-map;
316 }; 314 };
317 315
318 fs3_mem: fs3@83a00000 { 316 fs3_mem: fs3@83a00000 {
319 reg = <0x0 0x83a00000 317 reg = <0x0 0x83a00000 0x0 0x400000>;
320 no-map; 318 no-map;
321 }; 319 };
322 320
323 /* Linux kernel image is loade 321 /* Linux kernel image is loaded at 0x83e00000 */
324 322
325 ipa_fw_mem: ipa-fw@8be00000 { 323 ipa_fw_mem: ipa-fw@8be00000 {
326 reg = <0x0 0x8be00000 324 reg = <0x0 0x8be00000 0x0 0x10000>;
327 no-map; 325 no-map;
328 }; 326 };
329 327
330 ipa_gsi_mem: ipa-gsi@8be10000 328 ipa_gsi_mem: ipa-gsi@8be10000 {
331 reg = <0x0 0x8be10000 329 reg = <0x0 0x8be10000 0x0 0x14000>;
332 no-map; 330 no-map;
333 }; 331 };
334 332
335 mpss_mem: mpss@8c000000 { 333 mpss_mem: mpss@8c000000 {
336 reg = <0x0 0x8c000000 334 reg = <0x0 0x8c000000 0x0 0x12c00000>;
337 no-map; 335 no-map;
338 }; 336 };
339 337
340 q6_mpss_dtb_mem: q6-mpss-dtb@9 338 q6_mpss_dtb_mem: q6-mpss-dtb@9ec00000 {
341 reg = <0x0 0x9ec00000 339 reg = <0x0 0x9ec00000 0x0 0x80000>;
342 no-map; 340 no-map;
343 }; 341 };
344 342
345 tenx_mem: tenx@a0000000 { 343 tenx_mem: tenx@a0000000 {
346 reg = <0x0 0xa0000000 344 reg = <0x0 0xa0000000 0x0 0x19600000>;
347 no-map; 345 no-map;
348 }; 346 };
349 347
350 oem_tenx_mem: oem-tenx@b960000 348 oem_tenx_mem: oem-tenx@b9600000 {
351 reg = <0x0 0xb9600000 349 reg = <0x0 0xb9600000 0x0 0x6a00000>;
352 no-map; 350 no-map;
353 }; 351 };
354 352
355 tenx_q6_buffer_mem: tenx-q6-bu 353 tenx_q6_buffer_mem: tenx-q6-buffer@c0000000 {
356 reg = <0x0 0xc0000000 354 reg = <0x0 0xc0000000 0x0 0x3200000>;
357 no-map; 355 no-map;
358 }; 356 };
359 357
360 ipa_buffer_mem: ipa-buffer@c32 358 ipa_buffer_mem: ipa-buffer@c3200000 {
361 reg = <0x0 0xc3200000 359 reg = <0x0 0xc3200000 0x0 0x12c00000>;
362 no-map; 360 no-map;
363 }; 361 };
364 }; 362 };
365 363
366 soc: soc@0 { 364 soc: soc@0 {
367 compatible = "simple-bus"; 365 compatible = "simple-bus";
368 #address-cells = <2>; 366 #address-cells = <2>;
369 #size-cells = <2>; 367 #size-cells = <2>;
370 ranges = <0 0 0 0 0x10 0>; 368 ranges = <0 0 0 0 0x10 0>;
371 dma-ranges = <0 0 0 0 0x10 0>; 369 dma-ranges = <0 0 0 0 0x10 0>;
372 370
373 gcc: clock-controller@80000 { 371 gcc: clock-controller@80000 {
374 compatible = "qcom,qdu 372 compatible = "qcom,qdu1000-gcc";
375 reg = <0x0 0x80000 0x0 373 reg = <0x0 0x80000 0x0 0x1f4200>;
376 clocks = <&rpmhcc RPMH 374 clocks = <&rpmhcc RPMH_CXO_CLK>,
377 <&sleep_clk>, 375 <&sleep_clk>,
378 <0>, 376 <0>,
379 <0>, 377 <0>,
380 <0>; 378 <0>;
381 #clock-cells = <1>; 379 #clock-cells = <1>;
382 #reset-cells = <1>; 380 #reset-cells = <1>;
383 #power-domain-cells = 381 #power-domain-cells = <1>;
384 }; 382 };
385 383
386 ecpricc: clock-controller@2800 <<
387 compatible = "qcom,qdu <<
388 reg = <0x0 0x00280000 <<
389 clocks = <&rpmhcc RPMH <<
390 <&gcc GCC_ECP <<
391 <&gcc GCC_ECP <<
392 <&gcc GCC_ECP <<
393 <&gcc GCC_ECP <<
394 <&gcc GCC_ECP <<
395 <&gcc GCC_ECP <<
396 #clock-cells = <1>; <<
397 #reset-cells = <1>; <<
398 }; <<
399 <<
400 gpi_dma0: dma-controller@90000 384 gpi_dma0: dma-controller@900000 {
401 compatible = "qcom,qdu 385 compatible = "qcom,qdu1000-gpi-dma", "qcom,sm6350-gpi-dma";
402 reg = <0x0 0x900000 0x 386 reg = <0x0 0x900000 0x0 0x60000>;
403 interrupts = <GIC_SPI 387 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
404 <GIC_SPI 388 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
405 <GIC_SPI 389 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
406 <GIC_SPI 390 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
407 <GIC_SPI 391 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
408 <GIC_SPI 392 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
409 <GIC_SPI 393 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
410 <GIC_SPI 394 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
411 <GIC_SPI 395 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
412 <GIC_SPI 396 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
413 <GIC_SPI 397 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
414 <GIC_SPI 398 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
415 dma-channels = <12>; 399 dma-channels = <12>;
416 dma-channel-mask = <0x 400 dma-channel-mask = <0x3f>;
417 iommus = <&apps_smmu 0 401 iommus = <&apps_smmu 0xf6 0x0>;
418 #dma-cells = <3>; 402 #dma-cells = <3>;
419 }; 403 };
420 404
421 qupv3_id_0: geniqup@9c0000 { 405 qupv3_id_0: geniqup@9c0000 {
422 compatible = "qcom,gen 406 compatible = "qcom,geni-se-qup";
423 reg = <0x0 0x9c0000 0x 407 reg = <0x0 0x9c0000 0x0 0x2000>;
424 clocks = <&gcc GCC_QUP 408 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
425 <&gcc GCC_QUPV 409 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
426 clock-names = "m-ahb", 410 clock-names = "m-ahb", "s-ahb";
427 iommus = <&apps_smmu 0 411 iommus = <&apps_smmu 0xe3 0x0>;
428 interconnects = <&clk_ 412 interconnects = <&clk_virt MASTER_QUP_CORE_0 0
429 &clk_ 413 &clk_virt SLAVE_QUP_CORE_0 0>;
430 interconnect-names = " 414 interconnect-names = "qup-core";
431 415
432 #address-cells = <2>; 416 #address-cells = <2>;
433 #size-cells = <2>; 417 #size-cells = <2>;
434 ranges; 418 ranges;
435 status = "disabled"; 419 status = "disabled";
436 420
437 uart0: serial@980000 { 421 uart0: serial@980000 {
438 compatible = " 422 compatible = "qcom,geni-uart";
439 reg = <0x0 0x9 423 reg = <0x0 0x980000 0x0 0x4000>;
440 clocks = <&gcc 424 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
441 clock-names = 425 clock-names = "se";
442 pinctrl-0 = <& 426 pinctrl-0 = <&qup_uart0_default>;
443 pinctrl-names 427 pinctrl-names = "default";
444 interrupts = < 428 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
445 status = "disa 429 status = "disabled";
446 }; 430 };
447 431
448 i2c1: i2c@984000 { 432 i2c1: i2c@984000 {
449 compatible = " 433 compatible = "qcom,geni-i2c";
450 reg = <0x0 0x9 434 reg = <0x0 0x984000 0x0 0x4000>;
451 clocks = <&gcc 435 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
452 clock-names = 436 clock-names = "se";
453 interrupts = < 437 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
454 pinctrl-0 = <& 438 pinctrl-0 = <&qup_i2c1_data_clk>;
455 pinctrl-names 439 pinctrl-names = "default";
456 #address-cells 440 #address-cells = <1>;
457 #size-cells = 441 #size-cells = <0>;
458 status = "disa 442 status = "disabled";
459 }; 443 };
460 444
461 spi1: spi@984000 { 445 spi1: spi@984000 {
462 compatible = " 446 compatible = "qcom,geni-spi";
463 reg = <0x0 0x9 447 reg = <0x0 0x984000 0x0 0x4000>;
464 #address-cells 448 #address-cells = <1>;
465 #size-cells = 449 #size-cells = <0>;
466 interrupts = < 450 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
467 clocks = <&gcc 451 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
468 clock-names = 452 clock-names = "se";
469 pinctrl-0 = <& 453 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
470 pinctrl-names 454 pinctrl-names = "default";
471 status = "disa 455 status = "disabled";
472 }; 456 };
473 457
474 i2c2: i2c@988000 { 458 i2c2: i2c@988000 {
475 compatible = " 459 compatible = "qcom,geni-i2c";
476 reg = <0x0 0x9 460 reg = <0x0 0x988000 0x0 0x4000>;
477 clocks = <&gcc 461 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
478 clock-names = 462 clock-names = "se";
479 interrupts = < 463 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
480 pinctrl-0 = <& 464 pinctrl-0 = <&qup_i2c2_data_clk>;
481 pinctrl-names 465 pinctrl-names = "default";
482 #address-cells 466 #address-cells = <1>;
483 #size-cells = 467 #size-cells = <0>;
484 status = "disa 468 status = "disabled";
485 }; 469 };
486 470
487 spi2: spi@988000 { 471 spi2: spi@988000 {
488 compatible = " 472 compatible = "qcom,geni-spi";
489 reg = <0x0 0x9 473 reg = <0x0 0x988000 0x0 0x4000>;
490 #address-cells 474 #address-cells = <1>;
491 #size-cells = 475 #size-cells = <0>;
492 interrupts = < 476 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
493 clocks = <&gcc 477 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
494 clock-names = 478 clock-names = "se";
495 pinctrl-0 = <& 479 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
496 pinctrl-names 480 pinctrl-names = "default";
497 status = "disa 481 status = "disabled";
498 }; 482 };
499 483
500 i2c3: i2c@98c000 { 484 i2c3: i2c@98c000 {
501 compatible = " 485 compatible = "qcom,geni-i2c";
502 reg = <0x0 0x9 486 reg = <0x0 0x98c000 0x0 0x4000>;
503 clocks = <&gcc 487 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
504 clock-names = 488 clock-names = "se";
505 interrupts = < 489 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
506 pinctrl-0 = <& 490 pinctrl-0 = <&qup_i2c3_data_clk>;
507 pinctrl-names 491 pinctrl-names = "default";
508 #address-cells 492 #address-cells = <1>;
509 #size-cells = 493 #size-cells = <0>;
510 status = "disa 494 status = "disabled";
511 }; 495 };
512 496
513 spi3: spi@98c000 { 497 spi3: spi@98c000 {
514 compatible = " 498 compatible = "qcom,geni-spi";
515 reg = <0x0 0x9 499 reg = <0x0 0x98c000 0x0 0x4000>;
516 #address-cells 500 #address-cells = <1>;
517 #size-cells = 501 #size-cells = <0>;
518 interrupts = < 502 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
519 clocks = <&gcc 503 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
520 clock-names = 504 clock-names = "se";
521 pinctrl-0 = <& 505 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
522 pinctrl-names 506 pinctrl-names = "default";
523 status = "disa 507 status = "disabled";
524 }; 508 };
525 509
526 i2c4: i2c@990000 { 510 i2c4: i2c@990000 {
527 compatible = " 511 compatible = "qcom,geni-i2c";
528 reg = <0x0 0x9 512 reg = <0x0 0x990000 0x0 0x4000>;
529 clocks = <&gcc 513 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
530 clock-names = 514 clock-names = "se";
531 interrupts = < 515 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
532 pinctrl-0 = <& 516 pinctrl-0 = <&qup_i2c4_data_clk>;
533 pinctrl-names 517 pinctrl-names = "default";
534 #address-cells 518 #address-cells = <1>;
535 #size-cells = 519 #size-cells = <0>;
536 status = "disa 520 status = "disabled";
537 }; 521 };
538 522
539 spi4: spi@990000 { 523 spi4: spi@990000 {
540 compatible = " 524 compatible = "qcom,geni-spi";
541 reg = <0x0 0x9 525 reg = <0x0 0x990000 0x0 0x4000>;
542 #address-cells 526 #address-cells = <1>;
543 #size-cells = 527 #size-cells = <0>;
544 interrupts = < 528 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
545 clocks = <&gcc 529 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
546 clock-names = 530 clock-names = "se";
547 pinctrl-0 = <& 531 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
548 pinctrl-names 532 pinctrl-names = "default";
549 status = "disa 533 status = "disabled";
550 }; 534 };
551 535
552 i2c5: i2c@994000 { 536 i2c5: i2c@994000 {
553 compatible = " 537 compatible = "qcom,geni-i2c";
554 reg = <0x0 0x9 538 reg = <0x0 0x994000 0x0 0x4000>;
555 clocks = <&gcc 539 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
556 clock-names = 540 clock-names = "se";
557 interrupts = < 541 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
558 pinctrl-0 = <& 542 pinctrl-0 = <&qup_i2c5_data_clk>;
559 pinctrl-names 543 pinctrl-names = "default";
560 #address-cells 544 #address-cells = <1>;
561 #size-cells = 545 #size-cells = <0>;
562 status = "disa 546 status = "disabled";
563 }; 547 };
564 548
565 spi5: spi@994000 { 549 spi5: spi@994000 {
566 compatible = " 550 compatible = "qcom,geni-spi";
567 reg = <0x0 0x9 551 reg = <0x0 0x994000 0x0 0x4000>;
568 #address-cells 552 #address-cells = <1>;
569 #size-cells = 553 #size-cells = <0>;
570 interrupts = < 554 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
571 clocks = <&gcc 555 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
572 clock-names = 556 clock-names = "se";
573 pinctrl-0 = <& 557 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
574 pinctrl-names 558 pinctrl-names = "default";
575 status = "disa 559 status = "disabled";
576 }; 560 };
577 561
578 i2c6: i2c@998000 { 562 i2c6: i2c@998000 {
579 compatible = " 563 compatible = "qcom,geni-i2c";
580 reg = <0x0 0x9 564 reg = <0x0 0x998000 0x0 0x4000>;
581 clocks = <&gcc 565 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
582 clock-names = 566 clock-names = "se";
583 interrupts = < 567 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
584 pinctrl-0 = <& 568 pinctrl-0 = <&qup_i2c6_data_clk>;
585 pinctrl-names 569 pinctrl-names = "default";
586 #address-cells 570 #address-cells = <1>;
587 #size-cells = 571 #size-cells = <0>;
588 status = "disa 572 status = "disabled";
589 }; 573 };
590 574
591 spi6: spi@998000 { 575 spi6: spi@998000 {
592 compatible = " 576 compatible = "qcom,geni-spi";
593 reg = <0x0 0x9 577 reg = <0x0 0x998000 0x0 0x4000>;
594 #address-cells 578 #address-cells = <1>;
595 #size-cells = 579 #size-cells = <0>;
596 interrupts = < 580 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
597 clocks = <&gcc 581 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
598 clock-names = 582 clock-names = "se";
599 pinctrl-0 = <& 583 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
600 pinctrl-names 584 pinctrl-names = "default";
601 status = "disa 585 status = "disabled";
602 }; 586 };
603 587
604 uart7: serial@99c000 { 588 uart7: serial@99c000 {
605 compatible = " 589 compatible = "qcom,geni-debug-uart";
606 reg = <0x0 0x9 590 reg = <0x0 0x99c000 0x0 0x4000>;
607 clocks = <&gcc 591 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
608 clock-names = 592 clock-names = "se";
609 pinctrl-0 = <& 593 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>;
610 pinctrl-names 594 pinctrl-names = "default";
611 interrupts = < 595 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
612 status = "disa 596 status = "disabled";
613 }; 597 };
614 }; 598 };
615 599
616 gpi_dma1: dma-controller@a0000 600 gpi_dma1: dma-controller@a00000 {
617 compatible = "qcom,qdu 601 compatible = "qcom,qdu1000-gpi-dma", "qcom,sm6350-gpi-dma";
618 reg = <0x0 0xa00000 0x 602 reg = <0x0 0xa00000 0x0 0x60000>;
619 interrupts = <GIC_SPI 603 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
620 <GIC_SPI 604 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
621 <GIC_SPI 605 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
622 <GIC_SPI 606 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
623 <GIC_SPI 607 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
624 <GIC_SPI 608 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
625 <GIC_SPI 609 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
626 <GIC_SPI 610 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
627 <GIC_SPI 611 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
628 <GIC_SPI 612 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
629 <GIC_SPI 613 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
630 <GIC_SPI 614 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
631 dma-channels = <12>; 615 dma-channels = <12>;
632 dma-channel-mask = <0x 616 dma-channel-mask = <0x3f>;
633 iommus = <&apps_smmu 0 617 iommus = <&apps_smmu 0x116 0x0>;
634 #dma-cells = <3>; 618 #dma-cells = <3>;
635 }; 619 };
636 620
637 qupv3_id_1: geniqup@ac0000 { 621 qupv3_id_1: geniqup@ac0000 {
638 compatible = "qcom,gen 622 compatible = "qcom,geni-se-qup";
639 reg = <0x0 0xac0000 0x 623 reg = <0x0 0xac0000 0x0 0x2000>;
640 clocks = <&gcc GCC_QUP 624 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
641 <&gcc GCC_QUPV 625 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
642 clock-names = "m-ahb", 626 clock-names = "m-ahb", "s-ahb";
643 iommus = <&apps_smmu 0 627 iommus = <&apps_smmu 0x103 0x0>;
644 #address-cells = <2>; 628 #address-cells = <2>;
645 #size-cells = <2>; 629 #size-cells = <2>;
646 ranges; 630 ranges;
647 status = "disabled"; 631 status = "disabled";
648 632
649 uart8: serial@a80000 { 633 uart8: serial@a80000 {
650 compatible = " 634 compatible = "qcom,geni-uart";
651 reg = <0x0 0xa 635 reg = <0x0 0xa80000 0x0 0x4000>;
652 clocks = <&gcc 636 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
653 clock-names = 637 clock-names = "se";
654 pinctrl-0 = <& 638 pinctrl-0 = <&qup_uart8_default>;
655 pinctrl-names 639 pinctrl-names = "default";
656 interrupts = < 640 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
657 #address-cells 641 #address-cells = <1>;
658 #size-cells = 642 #size-cells = <0>;
659 status = "disa 643 status = "disabled";
660 }; 644 };
661 645
662 i2c9: i2c@a84000 { 646 i2c9: i2c@a84000 {
663 compatible = " 647 compatible = "qcom,geni-i2c";
664 reg = <0x0 0xa 648 reg = <0x0 0xa84000 0x0 0x4000>;
665 clocks = <&gcc 649 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
666 clock-names = 650 clock-names = "se";
667 interrupts = < 651 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
668 pinctrl-0 = <& 652 pinctrl-0 = <&qup_i2c9_data_clk>;
669 pinctrl-names 653 pinctrl-names = "default";
670 #address-cells 654 #address-cells = <1>;
671 #size-cells = 655 #size-cells = <0>;
672 status = "disa 656 status = "disabled";
673 }; 657 };
674 658
675 spi9: spi@a84000 { 659 spi9: spi@a84000 {
676 compatible = " 660 compatible = "qcom,geni-spi";
677 reg = <0x0 0xa 661 reg = <0x0 0xa84000 0x0 0x4000>;
678 #address-cells 662 #address-cells = <1>;
679 #size-cells = 663 #size-cells = <0>;
680 interrupts = < 664 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
681 clocks = <&gcc 665 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
682 clock-names = 666 clock-names = "se";
683 pinctrl-0 = <& 667 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
684 pinctrl-names 668 pinctrl-names = "default";
685 status = "disa 669 status = "disabled";
686 }; 670 };
687 671
688 i2c10: i2c@a88000 { 672 i2c10: i2c@a88000 {
689 compatible = " 673 compatible = "qcom,geni-i2c";
690 reg = <0x0 0xa 674 reg = <0x0 0xa88000 0x0 0x4000>;
691 clocks = <&gcc 675 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
692 clock-names = 676 clock-names = "se";
693 interrupts = < 677 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
694 pinctrl-0 = <& 678 pinctrl-0 = <&qup_i2c10_data_clk>;
695 pinctrl-names 679 pinctrl-names = "default";
696 #address-cells 680 #address-cells = <1>;
697 #size-cells = 681 #size-cells = <0>;
698 status = "disa 682 status = "disabled";
699 }; 683 };
700 684
701 spi10: spi@a88000 { 685 spi10: spi@a88000 {
702 compatible = " 686 compatible = "qcom,geni-spi";
703 reg = <0x0 0xa 687 reg = <0x0 0xa88000 0x0 0x4000>;
704 #address-cells 688 #address-cells = <1>;
705 #size-cells = 689 #size-cells = <0>;
706 interrupts = < 690 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
707 clocks = <&gcc 691 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
708 clock-names = 692 clock-names = "se";
709 pinctrl-0 = <& 693 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
710 pinctrl-names 694 pinctrl-names = "default";
711 status = "disa 695 status = "disabled";
712 }; 696 };
713 697
714 i2c11: i2c@a8c000 { 698 i2c11: i2c@a8c000 {
715 compatible = " 699 compatible = "qcom,geni-i2c";
716 reg = <0x0 0xa 700 reg = <0x0 0xa8c000 0x0 0x4000>;
717 clocks = <&gcc 701 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
718 clock-names = 702 clock-names = "se";
719 interrupts = < 703 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
720 pinctrl-0 = <& 704 pinctrl-0 = <&qup_i2c11_data_clk>;
721 pinctrl-names 705 pinctrl-names = "default";
722 #address-cells 706 #address-cells = <1>;
723 #size-cells = 707 #size-cells = <0>;
724 status = "disa 708 status = "disabled";
725 }; 709 };
726 710
727 spi11: spi@a8c000 { 711 spi11: spi@a8c000 {
728 compatible = " 712 compatible = "qcom,geni-spi";
729 reg = <0x0 0xa 713 reg = <0x0 0xa8c000 0x0 0x4000>;
730 #address-cells 714 #address-cells = <1>;
731 #size-cells = 715 #size-cells = <0>;
732 interrupts = < 716 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
733 clocks = <&gcc 717 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
734 clock-names = 718 clock-names = "se";
735 pinctrl-0 = <& 719 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
736 pinctrl-names 720 pinctrl-names = "default";
737 status = "disa 721 status = "disabled";
738 }; 722 };
739 723
740 i2c12: i2c@a90000 { 724 i2c12: i2c@a90000 {
741 compatible = " 725 compatible = "qcom,geni-i2c";
742 reg = <0x0 0xa 726 reg = <0x0 0xa90000 0x0 0x4000>;
743 clocks = <&gcc 727 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
744 clock-names = 728 clock-names = "se";
745 interrupts = < 729 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
746 pinctrl-0 = <& 730 pinctrl-0 = <&qup_i2c12_data_clk>;
747 pinctrl-names 731 pinctrl-names = "default";
748 #address-cells 732 #address-cells = <1>;
749 #size-cells = 733 #size-cells = <0>;
750 status = "disa 734 status = "disabled";
751 }; 735 };
752 736
753 spi12: spi@a90000 { 737 spi12: spi@a90000 {
754 compatible = " 738 compatible = "qcom,geni-spi";
755 reg = <0x0 0xa 739 reg = <0x0 0xa90000 0x0 0x4000>;
756 #address-cells 740 #address-cells = <1>;
757 #size-cells = 741 #size-cells = <0>;
758 interrupts = < 742 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
759 clocks = <&gcc 743 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
760 clock-names = 744 clock-names = "se";
761 pinctrl-0 = <& 745 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
762 pinctrl-names 746 pinctrl-names = "default";
763 status = "disa 747 status = "disabled";
764 }; 748 };
765 749
766 i2c13: i2c@a94000 { 750 i2c13: i2c@a94000 {
767 compatible = " 751 compatible = "qcom,geni-i2c";
768 reg = <0x0 0xa 752 reg = <0x0 0xa94000 0x0 0x4000>;
769 clocks = <&gcc 753 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
770 clock-names = 754 clock-names = "se";
771 interrupts = < 755 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
772 pinctrl-0 = <& 756 pinctrl-0 = <&qup_i2c13_data_clk>;
773 pinctrl-names 757 pinctrl-names = "default";
774 #address-cells 758 #address-cells = <1>;
775 #size-cells = 759 #size-cells = <0>;
776 status = "disa 760 status = "disabled";
777 }; 761 };
778 762
779 uart13: serial@a94000 763 uart13: serial@a94000 {
780 compatible = " 764 compatible = "qcom,geni-uart";
781 reg = <0x0 0xa 765 reg = <0x0 0xa94000 0x0 0x4000>;
782 clocks = <&gcc 766 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
783 clock-names = 767 clock-names = "se";
784 pinctrl-0 = <& 768 pinctrl-0 = <&qup_uart13_default>;
785 pinctrl-names 769 pinctrl-names = "default";
786 interrupts = < 770 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
787 #address-cells 771 #address-cells = <1>;
788 #size-cells = 772 #size-cells = <0>;
789 status = "disa 773 status = "disabled";
790 }; 774 };
791 775
792 spi13: spi@a94000 { 776 spi13: spi@a94000 {
793 compatible = " 777 compatible = "qcom,geni-spi";
794 reg = <0x0 0xa 778 reg = <0x0 0xa94000 0x0 0x4000>;
795 #address-cells 779 #address-cells = <1>;
796 #size-cells = 780 #size-cells = <0>;
797 interrupts = < 781 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
798 clocks = <&gcc 782 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
799 clock-names = 783 clock-names = "se";
800 pinctrl-0 = <& 784 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
801 pinctrl-names 785 pinctrl-names = "default";
802 status = "disa 786 status = "disabled";
803 }; 787 };
804 788
805 i2c14: i2c@a98000 { 789 i2c14: i2c@a98000 {
806 compatible = " 790 compatible = "qcom,geni-i2c";
807 reg = <0x0 0xa 791 reg = <0x0 0xa98000 0x0 0x4000>;
808 clocks = <&gcc 792 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
809 clock-names = 793 clock-names = "se";
810 interrupts = < 794 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
811 pinctrl-0 = <& 795 pinctrl-0 = <&qup_i2c14_data_clk>;
812 pinctrl-names 796 pinctrl-names = "default";
813 #address-cells 797 #address-cells = <1>;
814 #size-cells = 798 #size-cells = <0>;
815 status = "disa 799 status = "disabled";
816 }; 800 };
817 801
818 spi14: spi@a98000 { 802 spi14: spi@a98000 {
819 compatible = " 803 compatible = "qcom,geni-spi";
820 reg = <0x0 0xa 804 reg = <0x0 0xa98000 0x0 0x4000>;
821 #address-cells 805 #address-cells = <1>;
822 #size-cells = 806 #size-cells = <0>;
823 interrupts = < 807 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
824 clocks = <&gcc 808 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
825 clock-names = 809 clock-names = "se";
826 pinctrl-0 = <& 810 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
827 pinctrl-names 811 pinctrl-names = "default";
828 status = "disa 812 status = "disabled";
829 }; 813 };
830 814
831 i2c15: i2c@a9c000 { 815 i2c15: i2c@a9c000 {
832 compatible = " 816 compatible = "qcom,geni-i2c";
833 reg = <0x0 0xa 817 reg = <0x0 0xa9c000 0x0 0x4000>;
834 clocks = <&gcc 818 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
835 clock-names = 819 clock-names = "se";
836 interrupts = < 820 interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>;
837 pinctrl-0 = <& 821 pinctrl-0 = <&qup_i2c15_data_clk>;
838 pinctrl-names 822 pinctrl-names = "default";
839 #address-cells 823 #address-cells = <1>;
840 #size-cells = 824 #size-cells = <0>;
841 status = "disa 825 status = "disabled";
842 }; 826 };
843 827
844 spi15: spi@a9c000 { 828 spi15: spi@a9c000 {
845 compatible = " 829 compatible = "qcom,geni-spi";
846 reg = <0x0 0xa 830 reg = <0x0 0xa9c000 0x0 0x4000>;
847 #address-cells 831 #address-cells = <1>;
848 #size-cells = 832 #size-cells = <0>;
849 interrupts = < 833 interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>;
850 clocks = <&gcc 834 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
851 clock-names = 835 clock-names = "se";
852 pinctrl-0 = <& 836 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
853 pinctrl-names 837 pinctrl-names = "default";
854 status = "disa 838 status = "disabled";
855 }; 839 };
856 }; 840 };
857 841
858 system_noc: interconnect@16400 842 system_noc: interconnect@1640000 {
859 compatible = "qcom,qdu 843 compatible = "qcom,qdu1000-system-noc";
860 reg = <0x0 0x1640000 0 844 reg = <0x0 0x1640000 0x0 0x45080>;
861 qcom,bcm-voters = <&ap 845 qcom,bcm-voters = <&apps_bcm_voter>;
862 #interconnect-cells = 846 #interconnect-cells = <2>;
863 }; 847 };
864 848
865 tcsr_mutex: hwlock@1f40000 { 849 tcsr_mutex: hwlock@1f40000 {
866 compatible = "qcom,tcs 850 compatible = "qcom,tcsr-mutex";
867 reg = <0x0 0x1f40000 0 851 reg = <0x0 0x1f40000 0x0 0x20000>;
868 #hwlock-cells = <1>; 852 #hwlock-cells = <1>;
869 }; 853 };
870 854
871 sdhc: mmc@8804000 { <<
872 compatible = "qcom,qdu <<
873 reg = <0x0 0x08804000 <<
874 <0x0 0x08805000 <<
875 reg-names = "hc", "cqh <<
876 <<
877 interrupts = <GIC_SPI <<
878 <GIC_SPI <<
879 interrupt-names = "hc_ <<
880 <<
881 clocks = <&gcc GCC_SDC <<
882 <&gcc GCC_SDC <<
883 <&rpmhcc RPMH <<
884 clock-names = "iface", <<
885 "core", <<
886 "xo"; <<
887 <<
888 resets = <&gcc GCC_SDC <<
889 <<
890 interconnects = <&syst <<
891 <&gem_ <<
892 interconnect-names = " <<
893 power-domains = <&rpmh <<
894 operating-points-v2 = <<
895 <<
896 iommus = <&apps_smmu 0 <<
897 dma-coherent; <<
898 <<
899 bus-width = <8>; <<
900 <<
901 qcom,dll-config = <0x0 <<
902 qcom,ddr-config = <0x8 <<
903 <<
904 status = "disabled"; <<
905 <<
906 sdhc1_opp_table: opp-t <<
907 compatible = " <<
908 <<
909 opp-384000000 <<
910 opp-hz <<
911 requir <<
912 opp-pe <<
913 opp-av <<
914 }; <<
915 }; <<
916 }; <<
917 <<
918 usb_1_hsphy: phy@88e3000 { <<
919 compatible = "qcom,qdu <<
920 "qcom,usb <<
921 reg = <0x0 0x088e3000 <<
922 #phy-cells = <0>; <<
923 <<
924 clocks =<&gcc GCC_USB2 <<
925 clock-names = "ref"; <<
926 <<
927 resets = <&gcc GCC_QUS <<
928 <<
929 status = "disabled"; <<
930 }; <<
931 <<
932 usb_1_qmpphy: phy@88e5000 { <<
933 compatible = "qcom,qdu <<
934 reg = <0x0 0x088e5000 <<
935 <<
936 clocks = <&gcc GCC_USB <<
937 <&gcc GCC_USB <<
938 <&gcc GCC_USB <<
939 <&gcc GCC_USB <<
940 clock-names = "aux", <<
941 "ref", <<
942 "com_aux <<
943 "pipe"; <<
944 <<
945 resets = <&gcc GCC_USB <<
946 <&gcc GCC_USB <<
947 reset-names = "phy", <<
948 "phy_phy <<
949 <<
950 #clock-cells = <0>; <<
951 clock-output-names = " <<
952 <<
953 #phy-cells = <0>; <<
954 <<
955 status = "disabled"; <<
956 }; <<
957 <<
958 usb_1: usb@a6f8800 { <<
959 compatible = "qcom,qdu <<
960 reg = <0 0x0a6f8800 0 <<
961 #address-cells = <2>; <<
962 #size-cells = <2>; <<
963 ranges; <<
964 <<
965 clocks = <&gcc GCC_CFG <<
966 <&gcc GCC_USB <<
967 <&gcc GCC_USB <<
968 <&gcc GCC_USB <<
969 clock-names = "cfg_noc <<
970 "core", <<
971 "sleep", <<
972 "mock_ut <<
973 <<
974 assigned-clocks = <&gc <<
975 <&gc <<
976 assigned-clock-rates = <<
977 <<
978 interrupts-extended = <<
979 <<
980 <<
981 <<
982 <<
983 interrupt-names = "pwr <<
984 "hs_ <<
985 "dp_ <<
986 "dm_ <<
987 "ss_ <<
988 <<
989 power-domains = <&gcc <<
990 required-opps = <&rpmh <<
991 <<
992 resets = <&gcc GCC_USB <<
993 <<
994 interconnects = <&syst <<
995 &mc_v <<
996 <&gem_ <<
997 &syst <<
998 <<
999 interconnect-names = " <<
1000 <<
1001 <<
1002 status = "disabled"; <<
1003 <<
1004 usb_1_dwc3: usb@a6000 <<
1005 compatible = <<
1006 reg = <0 0x0a <<
1007 interrupts = <<
1008 <<
1009 iommus = <&ap <<
1010 snps,dis_u2_s <<
1011 snps,dis_enbl <<
1012 phys = <&usb_ <<
1013 <&usb_ <<
1014 phy-names = " <<
1015 " <<
1016 <<
1017 ports { <<
1018 #addr <<
1019 #size <<
1020 <<
1021 port@ <<
1022 <<
1023 <<
1024 <<
1025 <<
1026 }; <<
1027 <<
1028 port@ <<
1029 <<
1030 <<
1031 <<
1032 <<
1033 }; <<
1034 }; <<
1035 }; <<
1036 }; <<
1037 <<
1038 pdc: interrupt-controller@b22 855 pdc: interrupt-controller@b220000 {
1039 compatible = "qcom,qd 856 compatible = "qcom,qdu1000-pdc", "qcom,pdc";
1040 reg = <0x0 0xb220000 857 reg = <0x0 0xb220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>;
1041 qcom,pdc-ranges = <0 858 qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>,
1042 <94 859 <94 609 31>, <125 63 1>;
1043 #interrupt-cells = <2 860 #interrupt-cells = <2>;
1044 interrupt-parent = <& 861 interrupt-parent = <&intc>;
1045 interrupt-controller; 862 interrupt-controller;
1046 }; 863 };
1047 864
1048 spmi_bus: spmi@c400000 { 865 spmi_bus: spmi@c400000 {
1049 compatible = "qcom,sp 866 compatible = "qcom,spmi-pmic-arb";
1050 reg = <0x0 0xc400000 867 reg = <0x0 0xc400000 0x0 0x3000>,
1051 <0x0 0xc500000 868 <0x0 0xc500000 0x0 0x400000>,
1052 <0x0 0xc440000 869 <0x0 0xc440000 0x0 0x80000>,
1053 <0x0 0xc4c0000 870 <0x0 0xc4c0000 0x0 0x10000>,
1054 <0x0 0xc42d000 871 <0x0 0xc42d000 0x0 0x4000>;
1055 reg-names = "core", " 872 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1056 interrupts-extended = 873 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
1057 interrupt-names = "pe 874 interrupt-names = "periph_irq";
1058 qcom,ee = <0>; 875 qcom,ee = <0>;
1059 qcom,channel = <0>; 876 qcom,channel = <0>;
1060 #address-cells = <2>; 877 #address-cells = <2>;
1061 #size-cells = <0>; 878 #size-cells = <0>;
1062 interrupt-controller; 879 interrupt-controller;
1063 #interrupt-cells = <4 880 #interrupt-cells = <4>;
1064 }; 881 };
1065 882
1066 tlmm: pinctrl@f000000 { 883 tlmm: pinctrl@f000000 {
1067 compatible = "qcom,qd 884 compatible = "qcom,qdu1000-tlmm";
1068 reg = <0x0 0xf000000 885 reg = <0x0 0xf000000 0x0 0x1000000>;
1069 interrupts = <GIC_SPI 886 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1070 gpio-controller; 887 gpio-controller;
1071 #gpio-cells = <2>; 888 #gpio-cells = <2>;
1072 interrupt-controller; 889 interrupt-controller;
1073 #interrupt-cells = <2 890 #interrupt-cells = <2>;
1074 gpio-ranges = <&tlmm 891 gpio-ranges = <&tlmm 0 0 151>;
1075 wakeup-parent = <&pdc 892 wakeup-parent = <&pdc>;
1076 893
1077 qup_uart0_default: qu 894 qup_uart0_default: qup-uart0-default-state {
1078 pins = "gpio6 895 pins = "gpio6", "gpio7", "gpio8", "gpio9";
1079 function = "q 896 function = "qup00";
1080 }; 897 };
1081 898
1082 qup_i2c1_data_clk: qu 899 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
1083 pins = "gpio1 900 pins = "gpio10", "gpio11";
1084 function = "q 901 function = "qup01";
1085 }; 902 };
1086 903
1087 qup_spi1_data_clk: qu 904 qup_spi1_data_clk: qup-spi1-data-clk-state {
1088 pins = "gpio1 905 pins = "gpio10", "gpio11", "gpio12";
1089 function = "q 906 function = "qup01";
1090 }; 907 };
1091 908
1092 qup_spi1_cs: qup-spi1 909 qup_spi1_cs: qup-spi1-cs-state {
1093 pins = "gpio1 910 pins = "gpio13";
1094 function = "g 911 function = "gpio";
1095 }; 912 };
1096 913
1097 qup_i2c2_data_clk: qu 914 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
1098 pins = "gpio1 915 pins = "gpio12", "gpio13";
1099 function = "q 916 function = "qup02";
1100 }; 917 };
1101 918
1102 qup_spi2_data_clk: qu 919 qup_spi2_data_clk: qup-spi2-data-clk-state {
1103 pins = "gpio1 920 pins = "gpio12", "gpio13", "gpio10";
1104 function = "q 921 function = "qup02";
1105 }; 922 };
1106 923
1107 qup_spi2_cs: qup-spi2 924 qup_spi2_cs: qup-spi2-cs-state {
1108 pins = "gpio1 925 pins = "gpio11";
1109 function = "g 926 function = "gpio";
1110 }; 927 };
1111 928
1112 qup_i2c3_data_clk: qu 929 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
1113 pins = "gpio1 930 pins = "gpio14", "gpio15";
1114 function = "q 931 function = "qup03";
1115 }; 932 };
1116 933
1117 qup_spi3_data_clk: qu 934 qup_spi3_data_clk: qup-spi3-data-clk-state {
1118 pins = "gpio1 935 pins = "gpio14", "gpio15", "gpio16";
1119 function = "q 936 function = "qup03";
1120 }; 937 };
1121 938
1122 qup_spi3_cs: qup-spi3 939 qup_spi3_cs: qup-spi3-cs-state {
1123 pins = "gpio1 940 pins = "gpio17";
1124 function = "g 941 function = "gpio";
1125 }; 942 };
1126 943
1127 qup_i2c4_data_clk: qu 944 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
1128 pins = "gpio1 945 pins = "gpio16", "gpio17";
1129 function = "q 946 function = "qup04";
1130 }; 947 };
1131 948
1132 qup_spi4_data_clk: qu 949 qup_spi4_data_clk: qup-spi4-data-clk-state {
1133 pins = "gpio1 950 pins = "gpio16", "gpio17", "gpio14";
1134 function = "q 951 function = "qup04";
1135 }; 952 };
1136 953
1137 qup_spi4_cs: qup-spi4 954 qup_spi4_cs: qup-spi4-cs-state {
1138 pins = "gpio1 955 pins = "gpio15";
1139 function = "g 956 function = "gpio";
1140 }; 957 };
1141 958
1142 qup_i2c5_data_clk: qu 959 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
1143 pins = "gpio1 960 pins = "gpio130", "gpio131";
1144 function = "q 961 function = "qup05";
1145 }; 962 };
1146 963
1147 qup_spi5_data_clk: qu 964 qup_spi5_data_clk: qup-spi5-data-clk-state {
1148 pins = "gpio1 965 pins = "gpio130", "gpio131", "gpio132";
1149 function = "q 966 function = "qup05";
1150 }; 967 };
1151 968
1152 qup_spi5_cs: qup-spi5 969 qup_spi5_cs: qup-spi5-cs-state {
1153 pins = "gpio1 970 pins = "gpio133";
1154 function = "g 971 function = "gpio";
1155 }; 972 };
1156 973
1157 qup_i2c6_data_clk: qu 974 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
1158 pins = "gpio1 975 pins = "gpio132", "gpio133";
1159 function = "q 976 function = "qup06";
1160 }; 977 };
1161 978
1162 qup_spi6_data_clk: qu 979 qup_spi6_data_clk: qup-spi6-data-clk-state {
1163 pins = "gpio1 980 pins = "gpio132", "gpio133", "gpio130";
1164 function = "q 981 function = "qup06";
1165 }; 982 };
1166 983
1167 qup_spi6_cs: qup-spi6 984 qup_spi6_cs: qup-spi6-cs-state {
1168 pins = "gpio1 985 pins = "gpio131";
1169 function = "g 986 function = "gpio";
1170 }; 987 };
1171 988
1172 qup_uart7_rx: qup-uar 989 qup_uart7_rx: qup-uart7-rx-state {
1173 pins = "gpio1 990 pins = "gpio135";
1174 function = "q 991 function = "qup07";
1175 }; 992 };
1176 993
1177 qup_uart7_tx: qup-uar 994 qup_uart7_tx: qup-uart7-tx-state {
1178 pins = "gpio1 995 pins = "gpio134";
1179 function = "q 996 function = "qup07";
1180 }; 997 };
1181 998
1182 qup_uart8_default: qu 999 qup_uart8_default: qup-uart8-default-state {
1183 pins = "gpio1 1000 pins = "gpio18", "gpio19", "gpio20", "gpio21";
1184 function = "q 1001 function = "qup10";
1185 }; 1002 };
1186 1003
1187 qup_i2c9_data_clk: qu 1004 qup_i2c9_data_clk: qup-i2c9-data-clk-state {
1188 pins = "gpio2 1005 pins = "gpio22", "gpio23";
1189 function = "q 1006 function = "qup11";
1190 }; 1007 };
1191 1008
1192 qup_spi9_data_clk: qu 1009 qup_spi9_data_clk: qup-spi9-data-clk-state {
1193 pins = "gpio2 1010 pins = "gpio22", "gpio23", "gpio24";
1194 function = "q 1011 function = "qup11";
1195 }; 1012 };
1196 1013
1197 qup_spi9_cs: qup-spi9 1014 qup_spi9_cs: qup-spi9-cs-state {
1198 pins = "gpio2 1015 pins = "gpio25";
1199 function = "g 1016 function = "gpio";
1200 }; 1017 };
1201 1018
1202 qup_i2c10_data_clk: q 1019 qup_i2c10_data_clk: qup-i2c10-data-clk-state {
1203 pins = "gpio2 1020 pins = "gpio24", "gpio25";
1204 function = "q 1021 function = "qup12";
1205 }; 1022 };
1206 1023
1207 qup_spi10_data_clk: q 1024 qup_spi10_data_clk: qup-spi10-data-clk-state {
1208 pins = "gpio2 1025 pins = "gpio24", "gpio25", "gpio22";
1209 function = "q 1026 function = "qup12";
1210 }; 1027 };
1211 1028
1212 qup_spi10_cs: qup-spi 1029 qup_spi10_cs: qup-spi10-cs-state {
1213 pins = "gpio2 1030 pins = "gpio23";
1214 function = "g 1031 function = "gpio";
1215 }; 1032 };
1216 1033
1217 qup_i2c11_data_clk: q 1034 qup_i2c11_data_clk: qup-i2c11-data-clk-state {
1218 pins = "gpio2 1035 pins = "gpio26", "gpio27";
1219 function = "q 1036 function = "qup13";
1220 }; 1037 };
1221 1038
1222 qup_spi11_data_clk: q 1039 qup_spi11_data_clk: qup-spi11-data-clk-state {
1223 pins = "gpio2 1040 pins = "gpio26", "gpio27", "gpio28";
1224 function = "q 1041 function = "qup13";
1225 }; 1042 };
1226 1043
1227 qup_spi11_cs: qup-spi 1044 qup_spi11_cs: qup-spi11-cs-state {
1228 pins = "gpio2 1045 pins = "gpio29";
1229 function = "g 1046 function = "gpio";
1230 }; 1047 };
1231 1048
1232 qup_i2c12_data_clk: q 1049 qup_i2c12_data_clk: qup-i2c12-data-clk-state {
1233 pins = "gpio2 1050 pins = "gpio28", "gpio29";
1234 function = "q 1051 function = "qup14";
1235 }; 1052 };
1236 1053
1237 qup_spi12_data_clk: q 1054 qup_spi12_data_clk: qup-spi12-data-clk-state {
1238 pins = "gpio2 1055 pins = "gpio28", "gpio29", "gpio26";
1239 function = "q 1056 function = "qup14";
1240 }; 1057 };
1241 1058
1242 qup_spi12_cs: qup-spi 1059 qup_spi12_cs: qup-spi12-cs-state {
1243 pins = "gpio2 1060 pins = "gpio27";
1244 function = "g 1061 function = "gpio";
1245 }; 1062 };
1246 1063
1247 qup_i2c13_data_clk: q 1064 qup_i2c13_data_clk: qup-i2c13-data-clk-state {
1248 pins = "gpio3 1065 pins = "gpio30", "gpio31";
1249 function = "q 1066 function = "qup15";
1250 }; 1067 };
1251 1068
1252 qup_spi13_data_clk: q 1069 qup_spi13_data_clk: qup-spi13-data-clk-state {
1253 pins = "gpio3 1070 pins = "gpio30", "gpio31", "gpio32";
1254 function = "q 1071 function = "qup15";
1255 }; 1072 };
1256 1073
1257 qup_spi13_cs: qup-spi 1074 qup_spi13_cs: qup-spi13-cs-state {
1258 pins = "gpio3 1075 pins = "gpio33";
1259 function = "g 1076 function = "gpio";
1260 }; 1077 };
1261 1078
1262 qup_uart13_default: q 1079 qup_uart13_default: qup-uart13-default-state {
1263 pins = "gpio3 1080 pins = "gpio30", "gpio31", "gpio32", "gpio33";
1264 function = "q 1081 function = "qup15";
1265 }; 1082 };
1266 1083
1267 qup_i2c14_data_clk: q 1084 qup_i2c14_data_clk: qup-i2c14-data-clk-state {
1268 pins = "gpio3 1085 pins = "gpio34", "gpio35";
1269 function = "q 1086 function = "qup16";
1270 }; 1087 };
1271 1088
1272 qup_spi14_data_clk: q 1089 qup_spi14_data_clk: qup-spi14-data-clk-state {
1273 pins = "gpio3 1090 pins = "gpio34", "gpio35", "gpio36";
1274 function = "q 1091 function = "qup16";
1275 }; 1092 };
1276 1093
1277 qup_spi14_cs: qup-spi 1094 qup_spi14_cs: qup-spi14-cs-state {
1278 pins = "gpio3 1095 pins = "gpio37", "gpio38";
1279 function = "g 1096 function = "gpio";
1280 }; 1097 };
1281 1098
1282 qup_i2c15_data_clk: q 1099 qup_i2c15_data_clk: qup-i2c15-data-clk-state {
1283 pins = "gpio4 1100 pins = "gpio40", "gpio41";
1284 function = "q 1101 function = "qup17";
1285 }; 1102 };
1286 1103
1287 qup_spi15_data_clk: q 1104 qup_spi15_data_clk: qup-spi15-data-clk-state {
1288 pins = "gpio4 1105 pins = "gpio40", "gpio41", "gpio30";
1289 function = "q 1106 function = "qup17";
1290 }; 1107 };
1291 1108
1292 qup_spi15_cs: qup-spi 1109 qup_spi15_cs: qup-spi15-cs-state {
1293 pins = "gpio3 1110 pins = "gpio31";
1294 function = "g 1111 function = "gpio";
1295 }; 1112 };
1296 <<
1297 sdc_on_state: sdc-on- <<
1298 clk-pins { <<
1299 pins <<
1300 drive <<
1301 bias- <<
1302 }; <<
1303 <<
1304 cmd-pins { <<
1305 pins <<
1306 drive <<
1307 bias- <<
1308 }; <<
1309 <<
1310 data-pins { <<
1311 pins <<
1312 drive <<
1313 bias- <<
1314 }; <<
1315 <<
1316 rclk-pins { <<
1317 pins <<
1318 bias- <<
1319 }; <<
1320 }; <<
1321 <<
1322 sdc_off_state: sdc-of <<
1323 clk-pins { <<
1324 pins <<
1325 drive <<
1326 bias- <<
1327 }; <<
1328 <<
1329 cmd-pins { <<
1330 pins <<
1331 drive <<
1332 bias- <<
1333 }; <<
1334 <<
1335 data-pins { <<
1336 pins <<
1337 drive <<
1338 bias- <<
1339 }; <<
1340 <<
1341 rclk-pins { <<
1342 pins <<
1343 bias- <<
1344 }; <<
1345 }; <<
1346 }; <<
1347 <<
1348 sram@14680000 { <<
1349 compatible = "qcom,qd <<
1350 reg = <0 0x14680000 0 <<
1351 ranges = <0 0 0x14680 <<
1352 #address-cells = <1>; <<
1353 #size-cells = <1>; <<
1354 <<
1355 pil-reloc@94c { <<
1356 compatible = <<
1357 reg = <0x94c <<
1358 }; <<
1359 }; 1113 };
1360 1114
1361 apps_smmu: iommu@15000000 { 1115 apps_smmu: iommu@15000000 {
1362 compatible = "qcom,qd !! 1116 compatible = "qcom,qdu1000-smmu-500", "arm,mmu-500";
1363 reg = <0x0 0x15000000 1117 reg = <0x0 0x15000000 0x0 0x100000>;
1364 #iommu-cells = <2>; 1118 #iommu-cells = <2>;
1365 #global-interrupts = 1119 #global-interrupts = <2>;
1366 interrupts = <GIC_SPI 1120 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
1367 <GIC_SPI 1121 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
1368 <GIC_SPI 1122 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1369 <GIC_SPI 1123 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
1370 <GIC_SPI 1124 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
1371 <GIC_SPI 1125 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
1372 <GIC_SPI 1126 <GIC_SPI 671 IRQ_TYPE_LEVEL_HIGH>,
1373 <GIC_SPI 1127 <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
1374 <GIC_SPI 1128 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
1375 <GIC_SPI 1129 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
1376 <GIC_SPI 1130 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
1377 <GIC_SPI 1131 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1378 <GIC_SPI 1132 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1379 <GIC_SPI 1133 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1380 <GIC_SPI 1134 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1381 <GIC_SPI 1135 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1382 <GIC_SPI 1136 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
1383 <GIC_SPI 1137 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1384 <GIC_SPI 1138 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
1385 <GIC_SPI 1139 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1386 <GIC_SPI 1140 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1387 <GIC_SPI 1141 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
1388 <GIC_SPI 1142 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
1389 <GIC_SPI 1143 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
1390 <GIC_SPI 1144 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
1391 <GIC_SPI 1145 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
1392 <GIC_SPI 1146 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
1393 <GIC_SPI 1147 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1394 <GIC_SPI 1148 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1395 <GIC_SPI 1149 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1396 <GIC_SPI 1150 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
1397 <GIC_SPI 1151 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
1398 <GIC_SPI 1152 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
1399 <GIC_SPI 1153 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
1400 <GIC_SPI 1154 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
1401 <GIC_SPI 1155 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
1402 <GIC_SPI 1156 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
1403 <GIC_SPI 1157 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
1404 <GIC_SPI 1158 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
1405 <GIC_SPI 1159 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
1406 <GIC_SPI 1160 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
1407 <GIC_SPI 1161 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
1408 <GIC_SPI 1162 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
1409 <GIC_SPI 1163 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
1410 <GIC_SPI 1164 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
1411 <GIC_SPI 1165 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
1412 <GIC_SPI 1166 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
1413 <GIC_SPI 1167 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
1414 <GIC_SPI 1168 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
1415 }; 1169 };
1416 1170
1417 intc: interrupt-controller@17 1171 intc: interrupt-controller@17200000 {
1418 compatible = "arm,gic 1172 compatible = "arm,gic-v3";
1419 reg = <0x0 0x17200000 1173 reg = <0x0 0x17200000 0x0 0x10000>, /* GICD */
1420 <0x0 0x17260000 1174 <0x0 0x17260000 0x0 0x80000>; /* GICR * 4 */
1421 interrupts = <GIC_PPI 1175 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
1422 #interrupt-cells = <3 1176 #interrupt-cells = <3>;
1423 interrupt-controller; 1177 interrupt-controller;
1424 #redistributor-region 1178 #redistributor-regions = <1>;
1425 redistributor-stride 1179 redistributor-stride = <0x0 0x20000>;
1426 }; 1180 };
1427 1181
1428 timer@17420000 { 1182 timer@17420000 {
1429 compatible = "arm,arm 1183 compatible = "arm,armv7-timer-mem";
1430 reg = <0x0 0x17420000 1184 reg = <0x0 0x17420000 0x0 0x1000>;
1431 #address-cells = <1>; 1185 #address-cells = <1>;
1432 #size-cells = <1>; 1186 #size-cells = <1>;
1433 ranges = <0x0 0x0 0x0 1187 ranges = <0x0 0x0 0x0 0x20000000>;
1434 1188
1435 frame@17421000 { 1189 frame@17421000 {
1436 reg = <0x1742 1190 reg = <0x17421000 0x1000>,
1437 <0x1742 1191 <0x17422000 0x1000>;
1438 interrupts = 1192 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
1439 1193 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1440 frame-number 1194 frame-number = <0>;
1441 }; 1195 };
1442 1196
1443 frame@17423000 { 1197 frame@17423000 {
1444 reg = <0x1742 1198 reg = <0x17423000 0x1000>;
1445 interrupts = 1199 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1446 frame-number 1200 frame-number = <1>;
1447 status = "dis 1201 status = "disabled";
1448 }; 1202 };
1449 1203
1450 frame@17425000 { 1204 frame@17425000 {
1451 reg = <0x1742 1205 reg = <0x17425000 0x1000>,
1452 <0x1742 1206 <0x17426000 0x1000>;
1453 interrupts = 1207 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1454 frame-number 1208 frame-number = <2>;
1455 status = "dis 1209 status = "disabled";
1456 }; 1210 };
1457 1211
1458 frame@17427000 { 1212 frame@17427000 {
1459 reg = <0x1742 1213 reg = <0x17427000 0x1000>;
1460 interrupts = 1214 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1461 frame-number 1215 frame-number = <3>;
1462 status = "dis 1216 status = "disabled";
1463 }; 1217 };
1464 1218
1465 frame@17429000 { 1219 frame@17429000 {
1466 reg = <0x1742 1220 reg = <0x17429000 0x1000>;
1467 interrupts = 1221 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1468 frame-number 1222 frame-number = <4>;
1469 status = "dis 1223 status = "disabled";
1470 }; 1224 };
1471 1225
1472 frame@1742b000 { 1226 frame@1742b000 {
1473 reg = <0x1742 1227 reg = <0x1742b000 0x1000>;
1474 interrupts = 1228 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1475 frame-number 1229 frame-number = <5>;
1476 status = "dis 1230 status = "disabled";
1477 }; 1231 };
1478 1232
1479 frame@1742d000 { 1233 frame@1742d000 {
1480 reg = <0x1742 1234 reg = <0x1742d000 0x1000>;
1481 interrupts = 1235 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1482 frame-number 1236 frame-number = <6>;
1483 status = "dis 1237 status = "disabled";
1484 }; 1238 };
1485 }; 1239 };
1486 1240
1487 apps_rsc: rsc@17a00000 { 1241 apps_rsc: rsc@17a00000 {
1488 compatible = "qcom,rp 1242 compatible = "qcom,rpmh-rsc";
1489 reg = <0x0 0x17a00000 1243 reg = <0x0 0x17a00000 0x0 0x10000>,
1490 <0x0 0x17a10000 1244 <0x0 0x17a10000 0x0 0x10000>,
1491 <0x0 0x17a20000 1245 <0x0 0x17a20000 0x0 0x10000>;
1492 reg-names = "drv-0", 1246 reg-names = "drv-0", "drv-1", "drv-2";
1493 interrupts = <GIC_SPI 1247 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
1494 <GIC_SPI 1248 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
1495 <GIC_SPI 1249 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1496 qcom,tcs-offset = <0x 1250 qcom,tcs-offset = <0xd00>;
1497 qcom,drv-id = <2>; 1251 qcom,drv-id = <2>;
1498 qcom,tcs-config = <AC 1252 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
1499 <WA 1253 <WAKE_TCS 3>, <CONTROL_TCS 0>;
1500 label = "apps_rsc"; 1254 label = "apps_rsc";
1501 power-domains = <&CLU 1255 power-domains = <&CLUSTER_PD>;
1502 1256
1503 apps_bcm_voter: bcm-v 1257 apps_bcm_voter: bcm-voter {
1504 compatible = 1258 compatible = "qcom,bcm-voter";
1505 }; 1259 };
1506 1260
1507 rpmhcc: clock-control 1261 rpmhcc: clock-controller {
1508 compatible = 1262 compatible = "qcom,qdu1000-rpmh-clk";
1509 clocks = <&xo 1263 clocks = <&xo_board>;
1510 clock-names = 1264 clock-names = "xo";
1511 #clock-cells 1265 #clock-cells = <1>;
1512 }; 1266 };
1513 1267
1514 rpmhpd: power-control 1268 rpmhpd: power-controller {
1515 compatible = 1269 compatible = "qcom,qdu1000-rpmhpd";
1516 #power-domain 1270 #power-domain-cells = <1>;
1517 operating-poi 1271 operating-points-v2 = <&rpmhpd_opp_table>;
1518 1272
1519 rpmhpd_opp_ta 1273 rpmhpd_opp_table: opp-table {
1520 compa 1274 compatible = "operating-points-v2";
1521 1275
1522 rpmhp 1276 rpmhpd_opp_ret: opp1 {
1523 1277 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
1524 }; 1278 };
1525 1279
1526 rpmhp 1280 rpmhpd_opp_min_svs: opp2 {
1527 1281 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
1528 }; 1282 };
1529 1283
1530 rpmhp 1284 rpmhpd_opp_low_svs: opp3 {
1531 1285 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1532 }; 1286 };
1533 1287
1534 rpmhp 1288 rpmhpd_opp_svs: opp4 {
1535 1289 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1536 }; 1290 };
1537 1291
1538 rpmhp 1292 rpmhpd_opp_svs_l1: opp5 {
1539 1293 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1540 }; 1294 };
1541 1295
1542 rpmhp 1296 rpmhpd_opp_nom: opp6 {
1543 1297 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1544 }; 1298 };
1545 1299
1546 rpmhp 1300 rpmhpd_opp_nom_l1: opp7 {
1547 1301 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1548 }; 1302 };
1549 1303
1550 rpmhp 1304 rpmhpd_opp_nom_l2: opp8 {
1551 1305 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
1552 }; 1306 };
1553 1307
1554 rpmhp 1308 rpmhpd_opp_turbo: opp9 {
1555 1309 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1556 }; 1310 };
1557 1311
1558 rpmhp 1312 rpmhpd_opp_turbo_l1: opp10 {
1559 1313 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
1560 }; 1314 };
1561 }; 1315 };
1562 }; 1316 };
1563 }; 1317 };
1564 1318
1565 cpufreq_hw: cpufreq@17d90000 1319 cpufreq_hw: cpufreq@17d90000 {
1566 compatible = "qcom,qd 1320 compatible = "qcom,qdu1000-cpufreq-epss", "qcom,cpufreq-epss";
1567 reg = <0x0 0x17d90000 1321 reg = <0x0 0x17d90000 0x0 0x1000>, <0x0 0x17d91000 0x0 0x1000>;
1568 reg-names = "freq-dom 1322 reg-names = "freq-domain0", "freq-domain1";
1569 clocks = <&rpmhcc RPM 1323 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
1570 clock-names = "xo", " 1324 clock-names = "xo", "alternate";
1571 #freq-domain-cells = 1325 #freq-domain-cells = <1>;
1572 #clock-cells = <1>; 1326 #clock-cells = <1>;
1573 }; 1327 };
1574 1328
1575 gem_noc: interconnect@1910000 1329 gem_noc: interconnect@19100000 {
1576 compatible = "qcom,qd 1330 compatible = "qcom,qdu1000-gem-noc";
1577 reg = <0x0 0x19100000 1331 reg = <0x0 0x19100000 0x0 0xB8080>;
1578 qcom,bcm-voters = <&a 1332 qcom,bcm-voters = <&apps_bcm_voter>;
1579 #interconnect-cells = 1333 #interconnect-cells = <2>;
1580 }; 1334 };
1581 1335
1582 system-cache-controller@19200 1336 system-cache-controller@19200000 {
1583 compatible = "qcom,qd 1337 compatible = "qcom,qdu1000-llcc";
1584 reg = <0 0x19200000 0 !! 1338 reg = <0 0x19200000 0 0xd80000>,
1585 <0 0x19300000 0 !! 1339 <0 0x1a200000 0 0x80000>,
1586 <0 0x19600000 0 !! 1340 <0 0x221c8128 0 0x4>;
1587 <0 0x19700000 0 !! 1341 reg-names = "llcc_base",
1588 <0 0x19a00000 0 !! 1342 "llcc_broadcast_base",
1589 <0 0x19b00000 0 !! 1343 "multi_channel_register";
1590 <0 0x19e00000 0 <<
1591 <0 0x19f00000 0 <<
1592 <0 0x1a200000 0 <<
1593 reg-names = "llcc0_ba <<
1594 "llcc1_ba <<
1595 "llcc2_ba <<
1596 "llcc3_ba <<
1597 "llcc4_ba <<
1598 "llcc5_ba <<
1599 "llcc6_ba <<
1600 "llcc7_ba <<
1601 "llcc_bro <<
1602 interrupts = <GIC_SPI 1344 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
1603 !! 1345 multi-ch-bit-off = <24 2>;
1604 nvmem-cells = <&multi <<
1605 nvmem-cell-names = "m <<
1606 }; <<
1607 <<
1608 sec_qfprom: efuse@221c8000 { <<
1609 compatible = "qcom,qd <<
1610 reg = <0 0x221c8000 0 <<
1611 #address-cells = <1>; <<
1612 #size-cells = <1>; <<
1613 <<
1614 multi_chan_ddr: multi <<
1615 reg = <0x12b <<
1616 bits = <0 2>; <<
1617 }; <<
1618 }; 1346 };
1619 }; 1347 };
1620 1348
1621 timer { 1349 timer {
1622 compatible = "arm,armv8-timer 1350 compatible = "arm,armv8-timer";
1623 interrupts = <GIC_PPI 13 (GIC 1351 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1624 <GIC_PPI 14 (GIC 1352 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1625 <GIC_PPI 11 (GIC 1353 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1626 <GIC_PPI 10 (GIC 1354 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1627 <GIC_PPI 12 (GIC 1355 <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
1628 }; 1356 };
1629 }; 1357 };
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