1 // SPDX-License-Identifier: BSD-3-Clause 1 // SPDX-License-Identifier: BSD-3-Clause
2 /* 2 /*
3 * Copyright (c) 2022 Qualcomm Innovation Cent 3 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
4 */ 4 */
5 5
6 #include <dt-bindings/clock/qcom,qdu1000-gcc.h 6 #include <dt-bindings/clock/qcom,qdu1000-gcc.h>
7 #include <dt-bindings/clock/qcom,rpmh.h> 7 #include <dt-bindings/clock/qcom,rpmh.h>
8 #include <dt-bindings/dma/qcom-gpi.h> 8 #include <dt-bindings/dma/qcom-gpi.h>
9 #include <dt-bindings/gpio/gpio.h> <<
10 #include <dt-bindings/interconnect/qcom,icc.h> <<
11 #include <dt-bindings/interconnect/qcom,qdu100 9 #include <dt-bindings/interconnect/qcom,qdu1000-rpmh.h>
12 #include <dt-bindings/interrupt-controller/arm 10 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/power/qcom-rpmpd.h> 11 #include <dt-bindings/power/qcom-rpmpd.h>
14 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 12 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
15 13
16 / { 14 / {
17 interrupt-parent = <&intc>; 15 interrupt-parent = <&intc>;
18 16
19 #address-cells = <2>; 17 #address-cells = <2>;
20 #size-cells = <2>; 18 #size-cells = <2>;
21 19
22 chosen: chosen { }; 20 chosen: chosen { };
23 21
24 cpus { 22 cpus {
25 #address-cells = <2>; 23 #address-cells = <2>;
26 #size-cells = <0>; 24 #size-cells = <0>;
27 25
28 CPU0: cpu@0 { 26 CPU0: cpu@0 {
29 device_type = "cpu"; 27 device_type = "cpu";
30 compatible = "arm,cort 28 compatible = "arm,cortex-a55";
31 reg = <0x0 0x0>; 29 reg = <0x0 0x0>;
32 clocks = <&cpufreq_hw 30 clocks = <&cpufreq_hw 0>;
33 enable-method = "psci" 31 enable-method = "psci";
34 power-domains = <&CPU_ 32 power-domains = <&CPU_PD0>;
35 power-domain-names = " 33 power-domain-names = "psci";
36 qcom,freq-domains = <& 34 qcom,freq-domains = <&cpufreq_hw 0>;
37 next-level-cache = <&L 35 next-level-cache = <&L2_0>;
38 L2_0: l2-cache { 36 L2_0: l2-cache {
39 compatible = " 37 compatible = "cache";
40 cache-level = 38 cache-level = <2>;
41 cache-unified; 39 cache-unified;
42 next-level-cac 40 next-level-cache = <&L3_0>;
43 L3_0: l3-cache 41 L3_0: l3-cache {
44 compat 42 compatible = "cache";
45 cache- 43 cache-level = <3>;
46 cache- 44 cache-unified;
47 }; 45 };
48 }; 46 };
49 }; 47 };
50 48
51 CPU1: cpu@100 { 49 CPU1: cpu@100 {
52 device_type = "cpu"; 50 device_type = "cpu";
53 compatible = "arm,cort 51 compatible = "arm,cortex-a55";
54 reg = <0x0 0x100>; 52 reg = <0x0 0x100>;
55 clocks = <&cpufreq_hw 53 clocks = <&cpufreq_hw 0>;
56 enable-method = "psci" 54 enable-method = "psci";
57 power-domains = <&CPU_ 55 power-domains = <&CPU_PD1>;
58 power-domain-names = " 56 power-domain-names = "psci";
59 qcom,freq-domains = <& 57 qcom,freq-domains = <&cpufreq_hw 0>;
60 next-level-cache = <&L 58 next-level-cache = <&L2_100>;
61 L2_100: l2-cache { 59 L2_100: l2-cache {
62 compatible = " 60 compatible = "cache";
63 cache-level = 61 cache-level = <2>;
64 cache-unified; 62 cache-unified;
65 next-level-cac 63 next-level-cache = <&L3_0>;
66 }; 64 };
67 }; 65 };
68 66
69 CPU2: cpu@200 { 67 CPU2: cpu@200 {
70 device_type = "cpu"; 68 device_type = "cpu";
71 compatible = "arm,cort 69 compatible = "arm,cortex-a55";
72 reg = <0x0 0x200>; 70 reg = <0x0 0x200>;
73 clocks = <&cpufreq_hw 71 clocks = <&cpufreq_hw 0>;
74 enable-method = "psci" 72 enable-method = "psci";
75 power-domains = <&CPU_ 73 power-domains = <&CPU_PD2>;
76 power-domain-names = " 74 power-domain-names = "psci";
77 qcom,freq-domains = <& 75 qcom,freq-domains = <&cpufreq_hw 0>;
78 next-level-cache = <&L 76 next-level-cache = <&L2_200>;
79 L2_200: l2-cache { 77 L2_200: l2-cache {
80 compatible = " 78 compatible = "cache";
81 cache-level = 79 cache-level = <2>;
82 cache-unified; 80 cache-unified;
83 next-level-cac 81 next-level-cache = <&L3_0>;
84 }; 82 };
85 }; 83 };
86 84
87 CPU3: cpu@300 { 85 CPU3: cpu@300 {
88 device_type = "cpu"; 86 device_type = "cpu";
89 compatible = "arm,cort 87 compatible = "arm,cortex-a55";
90 reg = <0x0 0x300>; 88 reg = <0x0 0x300>;
91 clocks = <&cpufreq_hw 89 clocks = <&cpufreq_hw 0>;
92 enable-method = "psci" 90 enable-method = "psci";
93 power-domains = <&CPU_ 91 power-domains = <&CPU_PD3>;
94 power-domain-names = " 92 power-domain-names = "psci";
95 qcom,freq-domains = <& 93 qcom,freq-domains = <&cpufreq_hw 0>;
96 next-level-cache = <&L 94 next-level-cache = <&L2_300>;
97 L2_300: l2-cache { 95 L2_300: l2-cache {
98 compatible = " 96 compatible = "cache";
99 cache-level = 97 cache-level = <2>;
100 cache-unified; 98 cache-unified;
101 next-level-cac 99 next-level-cache = <&L3_0>;
102 }; 100 };
103 }; 101 };
104 102
105 cpu-map { 103 cpu-map {
106 cluster0 { 104 cluster0 {
107 core0 { 105 core0 {
108 cpu = 106 cpu = <&CPU0>;
109 }; 107 };
110 108
111 core1 { 109 core1 {
112 cpu = 110 cpu = <&CPU1>;
113 }; 111 };
114 112
115 core2 { 113 core2 {
116 cpu = 114 cpu = <&CPU2>;
117 }; 115 };
118 116
119 core3 { 117 core3 {
120 cpu = 118 cpu = <&CPU3>;
121 }; 119 };
122 }; 120 };
123 }; 121 };
124 }; 122 };
125 123
126 idle-states { 124 idle-states {
127 entry-method = "psci"; 125 entry-method = "psci";
128 126
129 CPU_OFF: cpu-sleep-0 { 127 CPU_OFF: cpu-sleep-0 {
130 compatible = "arm,idle 128 compatible = "arm,idle-state";
131 entry-latency-us = <27 129 entry-latency-us = <274>;
132 exit-latency-us = <480 130 exit-latency-us = <480>;
133 min-residency-us = <39 131 min-residency-us = <3934>;
134 arm,psci-suspend-param 132 arm,psci-suspend-param = <0x40000004>;
135 local-timer-stop; 133 local-timer-stop;
136 }; 134 };
137 }; 135 };
138 136
139 domain-idle-states { 137 domain-idle-states {
140 CLUSTER_SLEEP_0: cluster-sleep 138 CLUSTER_SLEEP_0: cluster-sleep-0 {
141 compatible = "domain-i 139 compatible = "domain-idle-state";
142 entry-latency-us = <58 140 entry-latency-us = <584>;
143 exit-latency-us = <233 141 exit-latency-us = <2332>;
144 min-residency-us = <61 142 min-residency-us = <6118>;
145 arm,psci-suspend-param 143 arm,psci-suspend-param = <0x41000044>;
146 }; 144 };
147 145
148 CLUSTER_SLEEP_1: cluster-sleep 146 CLUSTER_SLEEP_1: cluster-sleep-1 {
149 compatible = "domain-i 147 compatible = "domain-idle-state";
150 entry-latency-us = <28 148 entry-latency-us = <2893>;
151 exit-latency-us = <402 149 exit-latency-us = <4023>;
152 min-residency-us = <99 150 min-residency-us = <9987>;
153 arm,psci-suspend-param 151 arm,psci-suspend-param = <0x41003344>;
154 }; 152 };
155 }; 153 };
156 154
157 firmware { 155 firmware {
158 scm { 156 scm {
159 compatible = "qcom,scm 157 compatible = "qcom,scm-qdu1000", "qcom,scm";
160 }; 158 };
161 }; 159 };
162 160
163 mc_virt: interconnect-0 { 161 mc_virt: interconnect-0 {
164 compatible = "qcom,qdu1000-mc- 162 compatible = "qcom,qdu1000-mc-virt";
165 qcom,bcm-voters = <&apps_bcm_v 163 qcom,bcm-voters = <&apps_bcm_voter>;
166 #interconnect-cells = <2>; 164 #interconnect-cells = <2>;
167 }; 165 };
168 166
169 clk_virt: interconnect-1 { 167 clk_virt: interconnect-1 {
170 compatible = "qcom,qdu1000-clk 168 compatible = "qcom,qdu1000-clk-virt";
171 qcom,bcm-voters = <&apps_bcm_v 169 qcom,bcm-voters = <&apps_bcm_voter>;
172 #interconnect-cells = <2>; 170 #interconnect-cells = <2>;
173 }; 171 };
174 172
175 memory@80000000 { 173 memory@80000000 {
176 device_type = "memory"; 174 device_type = "memory";
177 /* We expect the bootloader to 175 /* We expect the bootloader to fill in the size */
178 reg = <0x0 0x80000000 0x0 0x0> 176 reg = <0x0 0x80000000 0x0 0x0>;
179 }; 177 };
180 178
181 pmu { 179 pmu {
182 compatible = "arm,cortex-a55-p !! 180 compatible = "arm,armv8-pmuv3";
183 interrupts = <GIC_PPI 7 IRQ_TY 181 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
184 }; 182 };
185 183
186 psci { 184 psci {
187 compatible = "arm,psci-1.0"; 185 compatible = "arm,psci-1.0";
188 method = "smc"; 186 method = "smc";
189 187
190 CPU_PD0: power-domain-cpu0 { 188 CPU_PD0: power-domain-cpu0 {
191 #power-domain-cells = 189 #power-domain-cells = <0>;
192 power-domains = <&CLUS 190 power-domains = <&CLUSTER_PD>;
193 domain-idle-states = < 191 domain-idle-states = <&CPU_OFF>;
194 }; 192 };
195 193
196 CPU_PD1: power-domain-cpu1 { 194 CPU_PD1: power-domain-cpu1 {
197 #power-domain-cells = 195 #power-domain-cells = <0>;
198 power-domains = <&CLUS 196 power-domains = <&CLUSTER_PD>;
199 domain-idle-states = < 197 domain-idle-states = <&CPU_OFF>;
200 }; 198 };
201 199
202 CPU_PD2: power-domain-cpu2 { 200 CPU_PD2: power-domain-cpu2 {
203 #power-domain-cells = 201 #power-domain-cells = <0>;
204 power-domains = <&CLUS 202 power-domains = <&CLUSTER_PD>;
205 domain-idle-states = < 203 domain-idle-states = <&CPU_OFF>;
206 }; 204 };
207 205
208 CPU_PD3: power-domain-cpu3 { 206 CPU_PD3: power-domain-cpu3 {
209 #power-domain-cells = 207 #power-domain-cells = <0>;
210 power-domains = <&CLUS 208 power-domains = <&CLUSTER_PD>;
211 domain-idle-states = < 209 domain-idle-states = <&CPU_OFF>;
212 }; 210 };
213 211
214 CLUSTER_PD: power-domain-clust 212 CLUSTER_PD: power-domain-cluster {
215 #power-domain-cells = 213 #power-domain-cells = <0>;
216 domain-idle-states = < 214 domain-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_1>;
217 }; 215 };
218 }; 216 };
219 217
220 reserved_memory: reserved-memory { 218 reserved_memory: reserved-memory {
221 #address-cells = <2>; 219 #address-cells = <2>;
222 #size-cells = <2>; 220 #size-cells = <2>;
223 ranges; 221 ranges;
224 222
225 hyp_mem: hyp@80000000 { 223 hyp_mem: hyp@80000000 {
226 reg = <0x0 0x80000000 224 reg = <0x0 0x80000000 0x0 0x600000>;
227 no-map; 225 no-map;
228 }; 226 };
229 227
230 xbl_dt_log_mem: xbl-dt-log@806 228 xbl_dt_log_mem: xbl-dt-log@80600000 {
231 reg = <0x0 0x80600000 229 reg = <0x0 0x80600000 0x0 0x40000>;
232 no-map; 230 no-map;
233 }; 231 };
234 232
235 xbl_ramdump_mem: xbl-ramdump@8 233 xbl_ramdump_mem: xbl-ramdump@80640000 {
236 reg = <0x0 0x80640000 234 reg = <0x0 0x80640000 0x0 0x1c0000>;
237 no-map; 235 no-map;
238 }; 236 };
239 237
240 aop_image_mem: aop-image@80800 238 aop_image_mem: aop-image@80800000 {
241 reg = <0x0 0x80800000 239 reg = <0x0 0x80800000 0x0 0x60000>;
242 no-map; 240 no-map;
243 }; 241 };
244 242
245 aop_cmd_db_mem: aop-cmd-db@808 243 aop_cmd_db_mem: aop-cmd-db@80860000 {
246 compatible = "qcom,cmd 244 compatible = "qcom,cmd-db";
247 reg = <0x0 0x80860000 245 reg = <0x0 0x80860000 0x0 0x20000>;
248 no-map; 246 no-map;
249 }; 247 };
250 248
251 aop_config_mem: aop-config@808 249 aop_config_mem: aop-config@80880000 {
252 reg = <0x0 0x80880000 250 reg = <0x0 0x80880000 0x0 0x20000>;
253 no-map; 251 no-map;
254 }; 252 };
255 253
256 tme_crash_dump_mem: tme-crash- 254 tme_crash_dump_mem: tme-crash-dump@808a0000 {
257 reg = <0x0 0x808a0000 255 reg = <0x0 0x808a0000 0x0 0x40000>;
258 no-map; 256 no-map;
259 }; 257 };
260 258
261 tme_log_mem: tme-log@808e0000 259 tme_log_mem: tme-log@808e0000 {
262 reg = <0x0 0x808e0000 260 reg = <0x0 0x808e0000 0x0 0x4000>;
263 no-map; 261 no-map;
264 }; 262 };
265 263
266 uefi_log_mem: uefi-log@808e400 264 uefi_log_mem: uefi-log@808e4000 {
267 reg = <0x0 0x808e4000 265 reg = <0x0 0x808e4000 0x0 0x10000>;
268 no-map; 266 no-map;
269 }; 267 };
270 268
271 smem_mem: smem@80900000 { 269 smem_mem: smem@80900000 {
272 compatible = "qcom,sme 270 compatible = "qcom,smem";
273 reg = <0x0 0x80900000 271 reg = <0x0 0x80900000 0x0 0x200000>;
274 no-map; 272 no-map;
275 hwlocks = <&tcsr_mutex 273 hwlocks = <&tcsr_mutex 3>;
276 }; 274 };
277 275
278 cpucp_fw_mem: cpucp-fw@80b0000 276 cpucp_fw_mem: cpucp-fw@80b00000 {
279 reg = <0x0 0x80b00000 277 reg = <0x0 0x80b00000 0x0 0x100000>;
280 no-map; 278 no-map;
281 }; 279 };
282 280
283 xbl_sc_mem: memory@80c00000 { 281 xbl_sc_mem: memory@80c00000 {
284 reg = <0x0 0x80c00000 282 reg = <0x0 0x80c00000 0x0 0x40000>;
285 no-map; 283 no-map;
286 }; 284 };
287 285
288 tz_stat_mem: tz-stat@81d00000 286 tz_stat_mem: tz-stat@81d00000 {
289 reg = <0x0 0x81d00000 287 reg = <0x0 0x81d00000 0x0 0x100000>;
290 no-map; 288 no-map;
291 }; 289 };
292 290
293 tags_mem: tags@81e00000 { 291 tags_mem: tags@81e00000 {
294 reg = <0x0 0x81e00000 292 reg = <0x0 0x81e00000 0x0 0x500000>;
295 no-map; 293 no-map;
296 }; 294 };
297 295
298 qtee_mem: qtee@82300000 { 296 qtee_mem: qtee@82300000 {
299 reg = <0x0 0x82300000 297 reg = <0x0 0x82300000 0x0 0x500000>;
300 no-map; 298 no-map;
301 }; 299 };
302 300
303 ta_mem: ta@82800000 { 301 ta_mem: ta@82800000 {
304 reg = <0x0 0x82800000 302 reg = <0x0 0x82800000 0x0 0xa00000>;
305 no-map; 303 no-map;
306 }; 304 };
307 305
308 fs1_mem: fs1@83200000 { 306 fs1_mem: fs1@83200000 {
309 reg = <0x0 0x83200000 307 reg = <0x0 0x83200000 0x0 0x400000>;
310 no-map; 308 no-map;
311 }; 309 };
312 310
313 fs2_mem: fs2@83600000 { 311 fs2_mem: fs2@83600000 {
314 reg = <0x0 0x83600000 312 reg = <0x0 0x83600000 0x0 0x400000>;
315 no-map; 313 no-map;
316 }; 314 };
317 315
318 fs3_mem: fs3@83a00000 { 316 fs3_mem: fs3@83a00000 {
319 reg = <0x0 0x83a00000 317 reg = <0x0 0x83a00000 0x0 0x400000>;
320 no-map; 318 no-map;
321 }; 319 };
322 320
323 /* Linux kernel image is loade 321 /* Linux kernel image is loaded at 0x83e00000 */
324 322
325 ipa_fw_mem: ipa-fw@8be00000 { 323 ipa_fw_mem: ipa-fw@8be00000 {
326 reg = <0x0 0x8be00000 324 reg = <0x0 0x8be00000 0x0 0x10000>;
327 no-map; 325 no-map;
328 }; 326 };
329 327
330 ipa_gsi_mem: ipa-gsi@8be10000 328 ipa_gsi_mem: ipa-gsi@8be10000 {
331 reg = <0x0 0x8be10000 329 reg = <0x0 0x8be10000 0x0 0x14000>;
332 no-map; 330 no-map;
333 }; 331 };
334 332
335 mpss_mem: mpss@8c000000 { 333 mpss_mem: mpss@8c000000 {
336 reg = <0x0 0x8c000000 334 reg = <0x0 0x8c000000 0x0 0x12c00000>;
337 no-map; 335 no-map;
338 }; 336 };
339 337
340 q6_mpss_dtb_mem: q6-mpss-dtb@9 338 q6_mpss_dtb_mem: q6-mpss-dtb@9ec00000 {
341 reg = <0x0 0x9ec00000 339 reg = <0x0 0x9ec00000 0x0 0x80000>;
342 no-map; 340 no-map;
343 }; 341 };
344 342
345 tenx_mem: tenx@a0000000 { 343 tenx_mem: tenx@a0000000 {
346 reg = <0x0 0xa0000000 344 reg = <0x0 0xa0000000 0x0 0x19600000>;
347 no-map; 345 no-map;
348 }; 346 };
349 347
350 oem_tenx_mem: oem-tenx@b960000 348 oem_tenx_mem: oem-tenx@b9600000 {
351 reg = <0x0 0xb9600000 349 reg = <0x0 0xb9600000 0x0 0x6a00000>;
352 no-map; 350 no-map;
353 }; 351 };
354 352
355 tenx_q6_buffer_mem: tenx-q6-bu 353 tenx_q6_buffer_mem: tenx-q6-buffer@c0000000 {
356 reg = <0x0 0xc0000000 354 reg = <0x0 0xc0000000 0x0 0x3200000>;
357 no-map; 355 no-map;
358 }; 356 };
359 357
360 ipa_buffer_mem: ipa-buffer@c32 358 ipa_buffer_mem: ipa-buffer@c3200000 {
361 reg = <0x0 0xc3200000 359 reg = <0x0 0xc3200000 0x0 0x12c00000>;
362 no-map; 360 no-map;
363 }; 361 };
364 }; 362 };
365 363
366 soc: soc@0 { 364 soc: soc@0 {
367 compatible = "simple-bus"; 365 compatible = "simple-bus";
368 #address-cells = <2>; 366 #address-cells = <2>;
369 #size-cells = <2>; 367 #size-cells = <2>;
370 ranges = <0 0 0 0 0x10 0>; 368 ranges = <0 0 0 0 0x10 0>;
371 dma-ranges = <0 0 0 0 0x10 0>; 369 dma-ranges = <0 0 0 0 0x10 0>;
372 370
373 gcc: clock-controller@80000 { 371 gcc: clock-controller@80000 {
374 compatible = "qcom,qdu 372 compatible = "qcom,qdu1000-gcc";
375 reg = <0x0 0x80000 0x0 373 reg = <0x0 0x80000 0x0 0x1f4200>;
376 clocks = <&rpmhcc RPMH 374 clocks = <&rpmhcc RPMH_CXO_CLK>,
377 <&sleep_clk>, 375 <&sleep_clk>,
378 <0>, 376 <0>,
379 <0>, 377 <0>,
380 <0>; 378 <0>;
381 #clock-cells = <1>; 379 #clock-cells = <1>;
382 #reset-cells = <1>; 380 #reset-cells = <1>;
383 #power-domain-cells = 381 #power-domain-cells = <1>;
384 }; 382 };
385 383
386 ecpricc: clock-controller@2800 384 ecpricc: clock-controller@280000 {
387 compatible = "qcom,qdu 385 compatible = "qcom,qdu1000-ecpricc";
388 reg = <0x0 0x00280000 386 reg = <0x0 0x00280000 0x0 0x31c00>;
389 clocks = <&rpmhcc RPMH 387 clocks = <&rpmhcc RPMH_CXO_CLK>,
390 <&gcc GCC_ECP 388 <&gcc GCC_ECPRI_CC_GPLL0_CLK_SRC>,
391 <&gcc GCC_ECP 389 <&gcc GCC_ECPRI_CC_GPLL1_EVEN_CLK_SRC>,
392 <&gcc GCC_ECP 390 <&gcc GCC_ECPRI_CC_GPLL2_EVEN_CLK_SRC>,
393 <&gcc GCC_ECP 391 <&gcc GCC_ECPRI_CC_GPLL3_CLK_SRC>,
394 <&gcc GCC_ECP 392 <&gcc GCC_ECPRI_CC_GPLL4_CLK_SRC>,
395 <&gcc GCC_ECP 393 <&gcc GCC_ECPRI_CC_GPLL5_EVEN_CLK_SRC>;
396 #clock-cells = <1>; 394 #clock-cells = <1>;
397 #reset-cells = <1>; 395 #reset-cells = <1>;
398 }; 396 };
399 397
400 gpi_dma0: dma-controller@90000 398 gpi_dma0: dma-controller@900000 {
401 compatible = "qcom,qdu 399 compatible = "qcom,qdu1000-gpi-dma", "qcom,sm6350-gpi-dma";
402 reg = <0x0 0x900000 0x 400 reg = <0x0 0x900000 0x0 0x60000>;
403 interrupts = <GIC_SPI 401 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
404 <GIC_SPI 402 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
405 <GIC_SPI 403 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
406 <GIC_SPI 404 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
407 <GIC_SPI 405 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
408 <GIC_SPI 406 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
409 <GIC_SPI 407 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
410 <GIC_SPI 408 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
411 <GIC_SPI 409 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
412 <GIC_SPI 410 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
413 <GIC_SPI 411 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
414 <GIC_SPI 412 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
415 dma-channels = <12>; 413 dma-channels = <12>;
416 dma-channel-mask = <0x 414 dma-channel-mask = <0x3f>;
417 iommus = <&apps_smmu 0 415 iommus = <&apps_smmu 0xf6 0x0>;
418 #dma-cells = <3>; 416 #dma-cells = <3>;
419 }; 417 };
420 418
421 qupv3_id_0: geniqup@9c0000 { 419 qupv3_id_0: geniqup@9c0000 {
422 compatible = "qcom,gen 420 compatible = "qcom,geni-se-qup";
423 reg = <0x0 0x9c0000 0x 421 reg = <0x0 0x9c0000 0x0 0x2000>;
424 clocks = <&gcc GCC_QUP 422 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
425 <&gcc GCC_QUPV 423 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
426 clock-names = "m-ahb", 424 clock-names = "m-ahb", "s-ahb";
427 iommus = <&apps_smmu 0 425 iommus = <&apps_smmu 0xe3 0x0>;
428 interconnects = <&clk_ 426 interconnects = <&clk_virt MASTER_QUP_CORE_0 0
429 &clk_ 427 &clk_virt SLAVE_QUP_CORE_0 0>;
430 interconnect-names = " 428 interconnect-names = "qup-core";
431 429
432 #address-cells = <2>; 430 #address-cells = <2>;
433 #size-cells = <2>; 431 #size-cells = <2>;
434 ranges; 432 ranges;
435 status = "disabled"; 433 status = "disabled";
436 434
437 uart0: serial@980000 { 435 uart0: serial@980000 {
438 compatible = " 436 compatible = "qcom,geni-uart";
439 reg = <0x0 0x9 437 reg = <0x0 0x980000 0x0 0x4000>;
440 clocks = <&gcc 438 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
441 clock-names = 439 clock-names = "se";
442 pinctrl-0 = <& 440 pinctrl-0 = <&qup_uart0_default>;
443 pinctrl-names 441 pinctrl-names = "default";
444 interrupts = < 442 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
445 status = "disa 443 status = "disabled";
446 }; 444 };
447 445
448 i2c1: i2c@984000 { 446 i2c1: i2c@984000 {
449 compatible = " 447 compatible = "qcom,geni-i2c";
450 reg = <0x0 0x9 448 reg = <0x0 0x984000 0x0 0x4000>;
451 clocks = <&gcc 449 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
452 clock-names = 450 clock-names = "se";
453 interrupts = < 451 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
454 pinctrl-0 = <& 452 pinctrl-0 = <&qup_i2c1_data_clk>;
455 pinctrl-names 453 pinctrl-names = "default";
456 #address-cells 454 #address-cells = <1>;
457 #size-cells = 455 #size-cells = <0>;
458 status = "disa 456 status = "disabled";
459 }; 457 };
460 458
461 spi1: spi@984000 { 459 spi1: spi@984000 {
462 compatible = " 460 compatible = "qcom,geni-spi";
463 reg = <0x0 0x9 461 reg = <0x0 0x984000 0x0 0x4000>;
464 #address-cells 462 #address-cells = <1>;
465 #size-cells = 463 #size-cells = <0>;
466 interrupts = < 464 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
467 clocks = <&gcc 465 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
468 clock-names = 466 clock-names = "se";
469 pinctrl-0 = <& 467 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
470 pinctrl-names 468 pinctrl-names = "default";
471 status = "disa 469 status = "disabled";
472 }; 470 };
473 471
474 i2c2: i2c@988000 { 472 i2c2: i2c@988000 {
475 compatible = " 473 compatible = "qcom,geni-i2c";
476 reg = <0x0 0x9 474 reg = <0x0 0x988000 0x0 0x4000>;
477 clocks = <&gcc 475 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
478 clock-names = 476 clock-names = "se";
479 interrupts = < 477 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
480 pinctrl-0 = <& 478 pinctrl-0 = <&qup_i2c2_data_clk>;
481 pinctrl-names 479 pinctrl-names = "default";
482 #address-cells 480 #address-cells = <1>;
483 #size-cells = 481 #size-cells = <0>;
484 status = "disa 482 status = "disabled";
485 }; 483 };
486 484
487 spi2: spi@988000 { 485 spi2: spi@988000 {
488 compatible = " 486 compatible = "qcom,geni-spi";
489 reg = <0x0 0x9 487 reg = <0x0 0x988000 0x0 0x4000>;
490 #address-cells 488 #address-cells = <1>;
491 #size-cells = 489 #size-cells = <0>;
492 interrupts = < 490 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
493 clocks = <&gcc 491 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
494 clock-names = 492 clock-names = "se";
495 pinctrl-0 = <& 493 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
496 pinctrl-names 494 pinctrl-names = "default";
497 status = "disa 495 status = "disabled";
498 }; 496 };
499 497
500 i2c3: i2c@98c000 { 498 i2c3: i2c@98c000 {
501 compatible = " 499 compatible = "qcom,geni-i2c";
502 reg = <0x0 0x9 500 reg = <0x0 0x98c000 0x0 0x4000>;
503 clocks = <&gcc 501 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
504 clock-names = 502 clock-names = "se";
505 interrupts = < 503 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
506 pinctrl-0 = <& 504 pinctrl-0 = <&qup_i2c3_data_clk>;
507 pinctrl-names 505 pinctrl-names = "default";
508 #address-cells 506 #address-cells = <1>;
509 #size-cells = 507 #size-cells = <0>;
510 status = "disa 508 status = "disabled";
511 }; 509 };
512 510
513 spi3: spi@98c000 { 511 spi3: spi@98c000 {
514 compatible = " 512 compatible = "qcom,geni-spi";
515 reg = <0x0 0x9 513 reg = <0x0 0x98c000 0x0 0x4000>;
516 #address-cells 514 #address-cells = <1>;
517 #size-cells = 515 #size-cells = <0>;
518 interrupts = < 516 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
519 clocks = <&gcc 517 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
520 clock-names = 518 clock-names = "se";
521 pinctrl-0 = <& 519 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
522 pinctrl-names 520 pinctrl-names = "default";
523 status = "disa 521 status = "disabled";
524 }; 522 };
525 523
526 i2c4: i2c@990000 { 524 i2c4: i2c@990000 {
527 compatible = " 525 compatible = "qcom,geni-i2c";
528 reg = <0x0 0x9 526 reg = <0x0 0x990000 0x0 0x4000>;
529 clocks = <&gcc 527 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
530 clock-names = 528 clock-names = "se";
531 interrupts = < 529 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
532 pinctrl-0 = <& 530 pinctrl-0 = <&qup_i2c4_data_clk>;
533 pinctrl-names 531 pinctrl-names = "default";
534 #address-cells 532 #address-cells = <1>;
535 #size-cells = 533 #size-cells = <0>;
536 status = "disa 534 status = "disabled";
537 }; 535 };
538 536
539 spi4: spi@990000 { 537 spi4: spi@990000 {
540 compatible = " 538 compatible = "qcom,geni-spi";
541 reg = <0x0 0x9 539 reg = <0x0 0x990000 0x0 0x4000>;
542 #address-cells 540 #address-cells = <1>;
543 #size-cells = 541 #size-cells = <0>;
544 interrupts = < 542 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
545 clocks = <&gcc 543 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
546 clock-names = 544 clock-names = "se";
547 pinctrl-0 = <& 545 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
548 pinctrl-names 546 pinctrl-names = "default";
549 status = "disa 547 status = "disabled";
550 }; 548 };
551 549
552 i2c5: i2c@994000 { 550 i2c5: i2c@994000 {
553 compatible = " 551 compatible = "qcom,geni-i2c";
554 reg = <0x0 0x9 552 reg = <0x0 0x994000 0x0 0x4000>;
555 clocks = <&gcc 553 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
556 clock-names = 554 clock-names = "se";
557 interrupts = < 555 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
558 pinctrl-0 = <& 556 pinctrl-0 = <&qup_i2c5_data_clk>;
559 pinctrl-names 557 pinctrl-names = "default";
560 #address-cells 558 #address-cells = <1>;
561 #size-cells = 559 #size-cells = <0>;
562 status = "disa 560 status = "disabled";
563 }; 561 };
564 562
565 spi5: spi@994000 { 563 spi5: spi@994000 {
566 compatible = " 564 compatible = "qcom,geni-spi";
567 reg = <0x0 0x9 565 reg = <0x0 0x994000 0x0 0x4000>;
568 #address-cells 566 #address-cells = <1>;
569 #size-cells = 567 #size-cells = <0>;
570 interrupts = < 568 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
571 clocks = <&gcc 569 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
572 clock-names = 570 clock-names = "se";
573 pinctrl-0 = <& 571 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
574 pinctrl-names 572 pinctrl-names = "default";
575 status = "disa 573 status = "disabled";
576 }; 574 };
577 575
578 i2c6: i2c@998000 { 576 i2c6: i2c@998000 {
579 compatible = " 577 compatible = "qcom,geni-i2c";
580 reg = <0x0 0x9 578 reg = <0x0 0x998000 0x0 0x4000>;
581 clocks = <&gcc 579 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
582 clock-names = 580 clock-names = "se";
583 interrupts = < 581 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
584 pinctrl-0 = <& 582 pinctrl-0 = <&qup_i2c6_data_clk>;
585 pinctrl-names 583 pinctrl-names = "default";
586 #address-cells 584 #address-cells = <1>;
587 #size-cells = 585 #size-cells = <0>;
588 status = "disa 586 status = "disabled";
589 }; 587 };
590 588
591 spi6: spi@998000 { 589 spi6: spi@998000 {
592 compatible = " 590 compatible = "qcom,geni-spi";
593 reg = <0x0 0x9 591 reg = <0x0 0x998000 0x0 0x4000>;
594 #address-cells 592 #address-cells = <1>;
595 #size-cells = 593 #size-cells = <0>;
596 interrupts = < 594 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
597 clocks = <&gcc 595 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
598 clock-names = 596 clock-names = "se";
599 pinctrl-0 = <& 597 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
600 pinctrl-names 598 pinctrl-names = "default";
601 status = "disa 599 status = "disabled";
602 }; 600 };
603 601
604 uart7: serial@99c000 { 602 uart7: serial@99c000 {
605 compatible = " 603 compatible = "qcom,geni-debug-uart";
606 reg = <0x0 0x9 604 reg = <0x0 0x99c000 0x0 0x4000>;
607 clocks = <&gcc 605 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
608 clock-names = 606 clock-names = "se";
609 pinctrl-0 = <& 607 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>;
610 pinctrl-names 608 pinctrl-names = "default";
611 interrupts = < 609 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
612 status = "disa 610 status = "disabled";
613 }; 611 };
614 }; 612 };
615 613
616 gpi_dma1: dma-controller@a0000 614 gpi_dma1: dma-controller@a00000 {
617 compatible = "qcom,qdu 615 compatible = "qcom,qdu1000-gpi-dma", "qcom,sm6350-gpi-dma";
618 reg = <0x0 0xa00000 0x 616 reg = <0x0 0xa00000 0x0 0x60000>;
619 interrupts = <GIC_SPI 617 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
620 <GIC_SPI 618 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
621 <GIC_SPI 619 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
622 <GIC_SPI 620 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
623 <GIC_SPI 621 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
624 <GIC_SPI 622 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
625 <GIC_SPI 623 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
626 <GIC_SPI 624 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
627 <GIC_SPI 625 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
628 <GIC_SPI 626 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
629 <GIC_SPI 627 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
630 <GIC_SPI 628 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
631 dma-channels = <12>; 629 dma-channels = <12>;
632 dma-channel-mask = <0x 630 dma-channel-mask = <0x3f>;
633 iommus = <&apps_smmu 0 631 iommus = <&apps_smmu 0x116 0x0>;
634 #dma-cells = <3>; 632 #dma-cells = <3>;
635 }; 633 };
636 634
637 qupv3_id_1: geniqup@ac0000 { 635 qupv3_id_1: geniqup@ac0000 {
638 compatible = "qcom,gen 636 compatible = "qcom,geni-se-qup";
639 reg = <0x0 0xac0000 0x 637 reg = <0x0 0xac0000 0x0 0x2000>;
640 clocks = <&gcc GCC_QUP 638 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
641 <&gcc GCC_QUPV 639 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
642 clock-names = "m-ahb", 640 clock-names = "m-ahb", "s-ahb";
643 iommus = <&apps_smmu 0 641 iommus = <&apps_smmu 0x103 0x0>;
644 #address-cells = <2>; 642 #address-cells = <2>;
645 #size-cells = <2>; 643 #size-cells = <2>;
646 ranges; 644 ranges;
647 status = "disabled"; 645 status = "disabled";
648 646
649 uart8: serial@a80000 { 647 uart8: serial@a80000 {
650 compatible = " 648 compatible = "qcom,geni-uart";
651 reg = <0x0 0xa 649 reg = <0x0 0xa80000 0x0 0x4000>;
652 clocks = <&gcc 650 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
653 clock-names = 651 clock-names = "se";
654 pinctrl-0 = <& 652 pinctrl-0 = <&qup_uart8_default>;
655 pinctrl-names 653 pinctrl-names = "default";
656 interrupts = < 654 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
657 #address-cells 655 #address-cells = <1>;
658 #size-cells = 656 #size-cells = <0>;
659 status = "disa 657 status = "disabled";
660 }; 658 };
661 659
662 i2c9: i2c@a84000 { 660 i2c9: i2c@a84000 {
663 compatible = " 661 compatible = "qcom,geni-i2c";
664 reg = <0x0 0xa 662 reg = <0x0 0xa84000 0x0 0x4000>;
665 clocks = <&gcc 663 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
666 clock-names = 664 clock-names = "se";
667 interrupts = < 665 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
668 pinctrl-0 = <& 666 pinctrl-0 = <&qup_i2c9_data_clk>;
669 pinctrl-names 667 pinctrl-names = "default";
670 #address-cells 668 #address-cells = <1>;
671 #size-cells = 669 #size-cells = <0>;
672 status = "disa 670 status = "disabled";
673 }; 671 };
674 672
675 spi9: spi@a84000 { 673 spi9: spi@a84000 {
676 compatible = " 674 compatible = "qcom,geni-spi";
677 reg = <0x0 0xa 675 reg = <0x0 0xa84000 0x0 0x4000>;
678 #address-cells 676 #address-cells = <1>;
679 #size-cells = 677 #size-cells = <0>;
680 interrupts = < 678 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
681 clocks = <&gcc 679 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
682 clock-names = 680 clock-names = "se";
683 pinctrl-0 = <& 681 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
684 pinctrl-names 682 pinctrl-names = "default";
685 status = "disa 683 status = "disabled";
686 }; 684 };
687 685
688 i2c10: i2c@a88000 { 686 i2c10: i2c@a88000 {
689 compatible = " 687 compatible = "qcom,geni-i2c";
690 reg = <0x0 0xa 688 reg = <0x0 0xa88000 0x0 0x4000>;
691 clocks = <&gcc 689 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
692 clock-names = 690 clock-names = "se";
693 interrupts = < 691 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
694 pinctrl-0 = <& 692 pinctrl-0 = <&qup_i2c10_data_clk>;
695 pinctrl-names 693 pinctrl-names = "default";
696 #address-cells 694 #address-cells = <1>;
697 #size-cells = 695 #size-cells = <0>;
698 status = "disa 696 status = "disabled";
699 }; 697 };
700 698
701 spi10: spi@a88000 { 699 spi10: spi@a88000 {
702 compatible = " 700 compatible = "qcom,geni-spi";
703 reg = <0x0 0xa 701 reg = <0x0 0xa88000 0x0 0x4000>;
704 #address-cells 702 #address-cells = <1>;
705 #size-cells = 703 #size-cells = <0>;
706 interrupts = < 704 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
707 clocks = <&gcc 705 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
708 clock-names = 706 clock-names = "se";
709 pinctrl-0 = <& 707 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
710 pinctrl-names 708 pinctrl-names = "default";
711 status = "disa 709 status = "disabled";
712 }; 710 };
713 711
714 i2c11: i2c@a8c000 { 712 i2c11: i2c@a8c000 {
715 compatible = " 713 compatible = "qcom,geni-i2c";
716 reg = <0x0 0xa 714 reg = <0x0 0xa8c000 0x0 0x4000>;
717 clocks = <&gcc 715 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
718 clock-names = 716 clock-names = "se";
719 interrupts = < 717 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
720 pinctrl-0 = <& 718 pinctrl-0 = <&qup_i2c11_data_clk>;
721 pinctrl-names 719 pinctrl-names = "default";
722 #address-cells 720 #address-cells = <1>;
723 #size-cells = 721 #size-cells = <0>;
724 status = "disa 722 status = "disabled";
725 }; 723 };
726 724
727 spi11: spi@a8c000 { 725 spi11: spi@a8c000 {
728 compatible = " 726 compatible = "qcom,geni-spi";
729 reg = <0x0 0xa 727 reg = <0x0 0xa8c000 0x0 0x4000>;
730 #address-cells 728 #address-cells = <1>;
731 #size-cells = 729 #size-cells = <0>;
732 interrupts = < 730 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
733 clocks = <&gcc 731 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
734 clock-names = 732 clock-names = "se";
735 pinctrl-0 = <& 733 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
736 pinctrl-names 734 pinctrl-names = "default";
737 status = "disa 735 status = "disabled";
738 }; 736 };
739 737
740 i2c12: i2c@a90000 { 738 i2c12: i2c@a90000 {
741 compatible = " 739 compatible = "qcom,geni-i2c";
742 reg = <0x0 0xa 740 reg = <0x0 0xa90000 0x0 0x4000>;
743 clocks = <&gcc 741 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
744 clock-names = 742 clock-names = "se";
745 interrupts = < 743 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
746 pinctrl-0 = <& 744 pinctrl-0 = <&qup_i2c12_data_clk>;
747 pinctrl-names 745 pinctrl-names = "default";
748 #address-cells 746 #address-cells = <1>;
749 #size-cells = 747 #size-cells = <0>;
750 status = "disa 748 status = "disabled";
751 }; 749 };
752 750
753 spi12: spi@a90000 { 751 spi12: spi@a90000 {
754 compatible = " 752 compatible = "qcom,geni-spi";
755 reg = <0x0 0xa 753 reg = <0x0 0xa90000 0x0 0x4000>;
756 #address-cells 754 #address-cells = <1>;
757 #size-cells = 755 #size-cells = <0>;
758 interrupts = < 756 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
759 clocks = <&gcc 757 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
760 clock-names = 758 clock-names = "se";
761 pinctrl-0 = <& 759 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
762 pinctrl-names 760 pinctrl-names = "default";
763 status = "disa 761 status = "disabled";
764 }; 762 };
765 763
766 i2c13: i2c@a94000 { 764 i2c13: i2c@a94000 {
767 compatible = " 765 compatible = "qcom,geni-i2c";
768 reg = <0x0 0xa 766 reg = <0x0 0xa94000 0x0 0x4000>;
769 clocks = <&gcc 767 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
770 clock-names = 768 clock-names = "se";
771 interrupts = < 769 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
772 pinctrl-0 = <& 770 pinctrl-0 = <&qup_i2c13_data_clk>;
773 pinctrl-names 771 pinctrl-names = "default";
774 #address-cells 772 #address-cells = <1>;
775 #size-cells = 773 #size-cells = <0>;
776 status = "disa 774 status = "disabled";
777 }; 775 };
778 776
779 uart13: serial@a94000 777 uart13: serial@a94000 {
780 compatible = " 778 compatible = "qcom,geni-uart";
781 reg = <0x0 0xa 779 reg = <0x0 0xa94000 0x0 0x4000>;
782 clocks = <&gcc 780 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
783 clock-names = 781 clock-names = "se";
784 pinctrl-0 = <& 782 pinctrl-0 = <&qup_uart13_default>;
785 pinctrl-names 783 pinctrl-names = "default";
786 interrupts = < 784 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
787 #address-cells 785 #address-cells = <1>;
788 #size-cells = 786 #size-cells = <0>;
789 status = "disa 787 status = "disabled";
790 }; 788 };
791 789
792 spi13: spi@a94000 { 790 spi13: spi@a94000 {
793 compatible = " 791 compatible = "qcom,geni-spi";
794 reg = <0x0 0xa 792 reg = <0x0 0xa94000 0x0 0x4000>;
795 #address-cells 793 #address-cells = <1>;
796 #size-cells = 794 #size-cells = <0>;
797 interrupts = < 795 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
798 clocks = <&gcc 796 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
799 clock-names = 797 clock-names = "se";
800 pinctrl-0 = <& 798 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
801 pinctrl-names 799 pinctrl-names = "default";
802 status = "disa 800 status = "disabled";
803 }; 801 };
804 802
805 i2c14: i2c@a98000 { 803 i2c14: i2c@a98000 {
806 compatible = " 804 compatible = "qcom,geni-i2c";
807 reg = <0x0 0xa 805 reg = <0x0 0xa98000 0x0 0x4000>;
808 clocks = <&gcc 806 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
809 clock-names = 807 clock-names = "se";
810 interrupts = < 808 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
811 pinctrl-0 = <& 809 pinctrl-0 = <&qup_i2c14_data_clk>;
812 pinctrl-names 810 pinctrl-names = "default";
813 #address-cells 811 #address-cells = <1>;
814 #size-cells = 812 #size-cells = <0>;
815 status = "disa 813 status = "disabled";
816 }; 814 };
817 815
818 spi14: spi@a98000 { 816 spi14: spi@a98000 {
819 compatible = " 817 compatible = "qcom,geni-spi";
820 reg = <0x0 0xa 818 reg = <0x0 0xa98000 0x0 0x4000>;
821 #address-cells 819 #address-cells = <1>;
822 #size-cells = 820 #size-cells = <0>;
823 interrupts = < 821 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
824 clocks = <&gcc 822 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
825 clock-names = 823 clock-names = "se";
826 pinctrl-0 = <& 824 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
827 pinctrl-names 825 pinctrl-names = "default";
828 status = "disa 826 status = "disabled";
829 }; 827 };
830 828
831 i2c15: i2c@a9c000 { 829 i2c15: i2c@a9c000 {
832 compatible = " 830 compatible = "qcom,geni-i2c";
833 reg = <0x0 0xa 831 reg = <0x0 0xa9c000 0x0 0x4000>;
834 clocks = <&gcc 832 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
835 clock-names = 833 clock-names = "se";
836 interrupts = < 834 interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>;
837 pinctrl-0 = <& 835 pinctrl-0 = <&qup_i2c15_data_clk>;
838 pinctrl-names 836 pinctrl-names = "default";
839 #address-cells 837 #address-cells = <1>;
840 #size-cells = 838 #size-cells = <0>;
841 status = "disa 839 status = "disabled";
842 }; 840 };
843 841
844 spi15: spi@a9c000 { 842 spi15: spi@a9c000 {
845 compatible = " 843 compatible = "qcom,geni-spi";
846 reg = <0x0 0xa 844 reg = <0x0 0xa9c000 0x0 0x4000>;
847 #address-cells 845 #address-cells = <1>;
848 #size-cells = 846 #size-cells = <0>;
849 interrupts = < 847 interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>;
850 clocks = <&gcc 848 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
851 clock-names = 849 clock-names = "se";
852 pinctrl-0 = <& 850 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
853 pinctrl-names 851 pinctrl-names = "default";
854 status = "disa 852 status = "disabled";
855 }; 853 };
856 }; 854 };
857 855
858 system_noc: interconnect@16400 856 system_noc: interconnect@1640000 {
859 compatible = "qcom,qdu 857 compatible = "qcom,qdu1000-system-noc";
860 reg = <0x0 0x1640000 0 858 reg = <0x0 0x1640000 0x0 0x45080>;
861 qcom,bcm-voters = <&ap 859 qcom,bcm-voters = <&apps_bcm_voter>;
862 #interconnect-cells = 860 #interconnect-cells = <2>;
863 }; 861 };
864 862
865 tcsr_mutex: hwlock@1f40000 { 863 tcsr_mutex: hwlock@1f40000 {
866 compatible = "qcom,tcs 864 compatible = "qcom,tcsr-mutex";
867 reg = <0x0 0x1f40000 0 865 reg = <0x0 0x1f40000 0x0 0x20000>;
868 #hwlock-cells = <1>; 866 #hwlock-cells = <1>;
869 }; 867 };
870 868
871 sdhc: mmc@8804000 { 869 sdhc: mmc@8804000 {
872 compatible = "qcom,qdu 870 compatible = "qcom,qdu1000-sdhci", "qcom,sdhci-msm-v5";
873 reg = <0x0 0x08804000 871 reg = <0x0 0x08804000 0x0 0x1000>,
874 <0x0 0x08805000 872 <0x0 0x08805000 0x0 0x1000>;
875 reg-names = "hc", "cqh 873 reg-names = "hc", "cqhci";
876 874
877 interrupts = <GIC_SPI 875 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
878 <GIC_SPI 876 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
879 interrupt-names = "hc_ 877 interrupt-names = "hc_irq", "pwr_irq";
880 878
881 clocks = <&gcc GCC_SDC 879 clocks = <&gcc GCC_SDCC5_AHB_CLK>,
882 <&gcc GCC_SDC 880 <&gcc GCC_SDCC5_APPS_CLK>,
883 <&rpmhcc RPMH 881 <&rpmhcc RPMH_CXO_CLK>;
884 clock-names = "iface", 882 clock-names = "iface",
885 "core", 883 "core",
886 "xo"; 884 "xo";
887 885
888 resets = <&gcc GCC_SDC 886 resets = <&gcc GCC_SDCC5_BCR>;
889 887
890 interconnects = <&syst 888 interconnects = <&system_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>,
891 <&gem_ 889 <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_SDCC_2 0>;
892 interconnect-names = " 890 interconnect-names = "sdhc-ddr", "cpu-sdhc";
893 power-domains = <&rpmh 891 power-domains = <&rpmhpd QDU1000_CX>;
894 operating-points-v2 = 892 operating-points-v2 = <&sdhc1_opp_table>;
895 893
896 iommus = <&apps_smmu 0 894 iommus = <&apps_smmu 0x80 0x0>;
897 dma-coherent; 895 dma-coherent;
898 896
899 bus-width = <8>; 897 bus-width = <8>;
900 898
901 qcom,dll-config = <0x0 899 qcom,dll-config = <0x0007642c>;
902 qcom,ddr-config = <0x8 900 qcom,ddr-config = <0x80040868>;
903 901
904 status = "disabled"; 902 status = "disabled";
905 903
906 sdhc1_opp_table: opp-t 904 sdhc1_opp_table: opp-table {
907 compatible = " 905 compatible = "operating-points-v2";
908 906
909 opp-384000000 907 opp-384000000 {
910 opp-hz 908 opp-hz = /bits/ 64 <384000000>;
911 requir 909 required-opps = <&rpmhpd_opp_nom>;
912 opp-pe 910 opp-peak-kBps = <6528000 1652800>;
913 opp-av 911 opp-avg-kBps = <400000 0>;
914 }; 912 };
915 }; 913 };
916 }; 914 };
917 915
918 usb_1_hsphy: phy@88e3000 { <<
919 compatible = "qcom,qdu <<
920 "qcom,usb <<
921 reg = <0x0 0x088e3000 <<
922 #phy-cells = <0>; <<
923 <<
924 clocks =<&gcc GCC_USB2 <<
925 clock-names = "ref"; <<
926 <<
927 resets = <&gcc GCC_QUS <<
928 <<
929 status = "disabled"; <<
930 }; <<
931 <<
932 usb_1_qmpphy: phy@88e5000 { <<
933 compatible = "qcom,qdu <<
934 reg = <0x0 0x088e5000 <<
935 <<
936 clocks = <&gcc GCC_USB <<
937 <&gcc GCC_USB <<
938 <&gcc GCC_USB <<
939 <&gcc GCC_USB <<
940 clock-names = "aux", <<
941 "ref", <<
942 "com_aux <<
943 "pipe"; <<
944 <<
945 resets = <&gcc GCC_USB <<
946 <&gcc GCC_USB <<
947 reset-names = "phy", <<
948 "phy_phy <<
949 <<
950 #clock-cells = <0>; <<
951 clock-output-names = " <<
952 <<
953 #phy-cells = <0>; <<
954 <<
955 status = "disabled"; <<
956 }; <<
957 <<
958 usb_1: usb@a6f8800 { <<
959 compatible = "qcom,qdu <<
960 reg = <0 0x0a6f8800 0 <<
961 #address-cells = <2>; <<
962 #size-cells = <2>; <<
963 ranges; <<
964 <<
965 clocks = <&gcc GCC_CFG <<
966 <&gcc GCC_USB <<
967 <&gcc GCC_USB <<
968 <&gcc GCC_USB <<
969 clock-names = "cfg_noc <<
970 "core", <<
971 "sleep", <<
972 "mock_ut <<
973 <<
974 assigned-clocks = <&gc <<
975 <&gc <<
976 assigned-clock-rates = <<
977 <<
978 interrupts-extended = <<
979 <<
980 <<
981 <<
982 <<
983 interrupt-names = "pwr <<
984 "hs_ <<
985 "dp_ <<
986 "dm_ <<
987 "ss_ <<
988 <<
989 power-domains = <&gcc <<
990 required-opps = <&rpmh <<
991 <<
992 resets = <&gcc GCC_USB <<
993 <<
994 interconnects = <&syst <<
995 &mc_v <<
996 <&gem_ <<
997 &syst <<
998 <<
999 interconnect-names = " <<
1000 <<
1001 <<
1002 status = "disabled"; <<
1003 <<
1004 usb_1_dwc3: usb@a6000 <<
1005 compatible = <<
1006 reg = <0 0x0a <<
1007 interrupts = <<
1008 <<
1009 iommus = <&ap <<
1010 snps,dis_u2_s <<
1011 snps,dis_enbl <<
1012 phys = <&usb_ <<
1013 <&usb_ <<
1014 phy-names = " <<
1015 " <<
1016 <<
1017 ports { <<
1018 #addr <<
1019 #size <<
1020 <<
1021 port@ <<
1022 <<
1023 <<
1024 <<
1025 <<
1026 }; <<
1027 <<
1028 port@ <<
1029 <<
1030 <<
1031 <<
1032 <<
1033 }; <<
1034 }; <<
1035 }; <<
1036 }; <<
1037 <<
1038 pdc: interrupt-controller@b22 916 pdc: interrupt-controller@b220000 {
1039 compatible = "qcom,qd 917 compatible = "qcom,qdu1000-pdc", "qcom,pdc";
1040 reg = <0x0 0xb220000 918 reg = <0x0 0xb220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>;
1041 qcom,pdc-ranges = <0 919 qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>,
1042 <94 920 <94 609 31>, <125 63 1>;
1043 #interrupt-cells = <2 921 #interrupt-cells = <2>;
1044 interrupt-parent = <& 922 interrupt-parent = <&intc>;
1045 interrupt-controller; 923 interrupt-controller;
1046 }; 924 };
1047 925
1048 spmi_bus: spmi@c400000 { 926 spmi_bus: spmi@c400000 {
1049 compatible = "qcom,sp 927 compatible = "qcom,spmi-pmic-arb";
1050 reg = <0x0 0xc400000 928 reg = <0x0 0xc400000 0x0 0x3000>,
1051 <0x0 0xc500000 929 <0x0 0xc500000 0x0 0x400000>,
1052 <0x0 0xc440000 930 <0x0 0xc440000 0x0 0x80000>,
1053 <0x0 0xc4c0000 931 <0x0 0xc4c0000 0x0 0x10000>,
1054 <0x0 0xc42d000 932 <0x0 0xc42d000 0x0 0x4000>;
1055 reg-names = "core", " 933 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1056 interrupts-extended = 934 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
1057 interrupt-names = "pe 935 interrupt-names = "periph_irq";
1058 qcom,ee = <0>; 936 qcom,ee = <0>;
1059 qcom,channel = <0>; 937 qcom,channel = <0>;
1060 #address-cells = <2>; 938 #address-cells = <2>;
1061 #size-cells = <0>; 939 #size-cells = <0>;
1062 interrupt-controller; 940 interrupt-controller;
1063 #interrupt-cells = <4 941 #interrupt-cells = <4>;
1064 }; 942 };
1065 943
1066 tlmm: pinctrl@f000000 { 944 tlmm: pinctrl@f000000 {
1067 compatible = "qcom,qd 945 compatible = "qcom,qdu1000-tlmm";
1068 reg = <0x0 0xf000000 946 reg = <0x0 0xf000000 0x0 0x1000000>;
1069 interrupts = <GIC_SPI 947 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1070 gpio-controller; 948 gpio-controller;
1071 #gpio-cells = <2>; 949 #gpio-cells = <2>;
1072 interrupt-controller; 950 interrupt-controller;
1073 #interrupt-cells = <2 951 #interrupt-cells = <2>;
1074 gpio-ranges = <&tlmm 952 gpio-ranges = <&tlmm 0 0 151>;
1075 wakeup-parent = <&pdc 953 wakeup-parent = <&pdc>;
1076 954
1077 qup_uart0_default: qu 955 qup_uart0_default: qup-uart0-default-state {
1078 pins = "gpio6 956 pins = "gpio6", "gpio7", "gpio8", "gpio9";
1079 function = "q 957 function = "qup00";
1080 }; 958 };
1081 959
1082 qup_i2c1_data_clk: qu 960 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
1083 pins = "gpio1 961 pins = "gpio10", "gpio11";
1084 function = "q 962 function = "qup01";
1085 }; 963 };
1086 964
1087 qup_spi1_data_clk: qu 965 qup_spi1_data_clk: qup-spi1-data-clk-state {
1088 pins = "gpio1 966 pins = "gpio10", "gpio11", "gpio12";
1089 function = "q 967 function = "qup01";
1090 }; 968 };
1091 969
1092 qup_spi1_cs: qup-spi1 970 qup_spi1_cs: qup-spi1-cs-state {
1093 pins = "gpio1 971 pins = "gpio13";
1094 function = "g 972 function = "gpio";
1095 }; 973 };
1096 974
1097 qup_i2c2_data_clk: qu 975 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
1098 pins = "gpio1 976 pins = "gpio12", "gpio13";
1099 function = "q 977 function = "qup02";
1100 }; 978 };
1101 979
1102 qup_spi2_data_clk: qu 980 qup_spi2_data_clk: qup-spi2-data-clk-state {
1103 pins = "gpio1 981 pins = "gpio12", "gpio13", "gpio10";
1104 function = "q 982 function = "qup02";
1105 }; 983 };
1106 984
1107 qup_spi2_cs: qup-spi2 985 qup_spi2_cs: qup-spi2-cs-state {
1108 pins = "gpio1 986 pins = "gpio11";
1109 function = "g 987 function = "gpio";
1110 }; 988 };
1111 989
1112 qup_i2c3_data_clk: qu 990 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
1113 pins = "gpio1 991 pins = "gpio14", "gpio15";
1114 function = "q 992 function = "qup03";
1115 }; 993 };
1116 994
1117 qup_spi3_data_clk: qu 995 qup_spi3_data_clk: qup-spi3-data-clk-state {
1118 pins = "gpio1 996 pins = "gpio14", "gpio15", "gpio16";
1119 function = "q 997 function = "qup03";
1120 }; 998 };
1121 999
1122 qup_spi3_cs: qup-spi3 1000 qup_spi3_cs: qup-spi3-cs-state {
1123 pins = "gpio1 1001 pins = "gpio17";
1124 function = "g 1002 function = "gpio";
1125 }; 1003 };
1126 1004
1127 qup_i2c4_data_clk: qu 1005 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
1128 pins = "gpio1 1006 pins = "gpio16", "gpio17";
1129 function = "q 1007 function = "qup04";
1130 }; 1008 };
1131 1009
1132 qup_spi4_data_clk: qu 1010 qup_spi4_data_clk: qup-spi4-data-clk-state {
1133 pins = "gpio1 1011 pins = "gpio16", "gpio17", "gpio14";
1134 function = "q 1012 function = "qup04";
1135 }; 1013 };
1136 1014
1137 qup_spi4_cs: qup-spi4 1015 qup_spi4_cs: qup-spi4-cs-state {
1138 pins = "gpio1 1016 pins = "gpio15";
1139 function = "g 1017 function = "gpio";
1140 }; 1018 };
1141 1019
1142 qup_i2c5_data_clk: qu 1020 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
1143 pins = "gpio1 1021 pins = "gpio130", "gpio131";
1144 function = "q 1022 function = "qup05";
1145 }; 1023 };
1146 1024
1147 qup_spi5_data_clk: qu 1025 qup_spi5_data_clk: qup-spi5-data-clk-state {
1148 pins = "gpio1 1026 pins = "gpio130", "gpio131", "gpio132";
1149 function = "q 1027 function = "qup05";
1150 }; 1028 };
1151 1029
1152 qup_spi5_cs: qup-spi5 1030 qup_spi5_cs: qup-spi5-cs-state {
1153 pins = "gpio1 1031 pins = "gpio133";
1154 function = "g 1032 function = "gpio";
1155 }; 1033 };
1156 1034
1157 qup_i2c6_data_clk: qu 1035 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
1158 pins = "gpio1 1036 pins = "gpio132", "gpio133";
1159 function = "q 1037 function = "qup06";
1160 }; 1038 };
1161 1039
1162 qup_spi6_data_clk: qu 1040 qup_spi6_data_clk: qup-spi6-data-clk-state {
1163 pins = "gpio1 1041 pins = "gpio132", "gpio133", "gpio130";
1164 function = "q 1042 function = "qup06";
1165 }; 1043 };
1166 1044
1167 qup_spi6_cs: qup-spi6 1045 qup_spi6_cs: qup-spi6-cs-state {
1168 pins = "gpio1 1046 pins = "gpio131";
1169 function = "g 1047 function = "gpio";
1170 }; 1048 };
1171 1049
1172 qup_uart7_rx: qup-uar 1050 qup_uart7_rx: qup-uart7-rx-state {
1173 pins = "gpio1 1051 pins = "gpio135";
1174 function = "q 1052 function = "qup07";
1175 }; 1053 };
1176 1054
1177 qup_uart7_tx: qup-uar 1055 qup_uart7_tx: qup-uart7-tx-state {
1178 pins = "gpio1 1056 pins = "gpio134";
1179 function = "q 1057 function = "qup07";
1180 }; 1058 };
1181 1059
1182 qup_uart8_default: qu 1060 qup_uart8_default: qup-uart8-default-state {
1183 pins = "gpio1 1061 pins = "gpio18", "gpio19", "gpio20", "gpio21";
1184 function = "q 1062 function = "qup10";
1185 }; 1063 };
1186 1064
1187 qup_i2c9_data_clk: qu 1065 qup_i2c9_data_clk: qup-i2c9-data-clk-state {
1188 pins = "gpio2 1066 pins = "gpio22", "gpio23";
1189 function = "q 1067 function = "qup11";
1190 }; 1068 };
1191 1069
1192 qup_spi9_data_clk: qu 1070 qup_spi9_data_clk: qup-spi9-data-clk-state {
1193 pins = "gpio2 1071 pins = "gpio22", "gpio23", "gpio24";
1194 function = "q 1072 function = "qup11";
1195 }; 1073 };
1196 1074
1197 qup_spi9_cs: qup-spi9 1075 qup_spi9_cs: qup-spi9-cs-state {
1198 pins = "gpio2 1076 pins = "gpio25";
1199 function = "g 1077 function = "gpio";
1200 }; 1078 };
1201 1079
1202 qup_i2c10_data_clk: q 1080 qup_i2c10_data_clk: qup-i2c10-data-clk-state {
1203 pins = "gpio2 1081 pins = "gpio24", "gpio25";
1204 function = "q 1082 function = "qup12";
1205 }; 1083 };
1206 1084
1207 qup_spi10_data_clk: q 1085 qup_spi10_data_clk: qup-spi10-data-clk-state {
1208 pins = "gpio2 1086 pins = "gpio24", "gpio25", "gpio22";
1209 function = "q 1087 function = "qup12";
1210 }; 1088 };
1211 1089
1212 qup_spi10_cs: qup-spi 1090 qup_spi10_cs: qup-spi10-cs-state {
1213 pins = "gpio2 1091 pins = "gpio23";
1214 function = "g 1092 function = "gpio";
1215 }; 1093 };
1216 1094
1217 qup_i2c11_data_clk: q 1095 qup_i2c11_data_clk: qup-i2c11-data-clk-state {
1218 pins = "gpio2 1096 pins = "gpio26", "gpio27";
1219 function = "q 1097 function = "qup13";
1220 }; 1098 };
1221 1099
1222 qup_spi11_data_clk: q 1100 qup_spi11_data_clk: qup-spi11-data-clk-state {
1223 pins = "gpio2 1101 pins = "gpio26", "gpio27", "gpio28";
1224 function = "q 1102 function = "qup13";
1225 }; 1103 };
1226 1104
1227 qup_spi11_cs: qup-spi 1105 qup_spi11_cs: qup-spi11-cs-state {
1228 pins = "gpio2 1106 pins = "gpio29";
1229 function = "g 1107 function = "gpio";
1230 }; 1108 };
1231 1109
1232 qup_i2c12_data_clk: q 1110 qup_i2c12_data_clk: qup-i2c12-data-clk-state {
1233 pins = "gpio2 1111 pins = "gpio28", "gpio29";
1234 function = "q 1112 function = "qup14";
1235 }; 1113 };
1236 1114
1237 qup_spi12_data_clk: q 1115 qup_spi12_data_clk: qup-spi12-data-clk-state {
1238 pins = "gpio2 1116 pins = "gpio28", "gpio29", "gpio26";
1239 function = "q 1117 function = "qup14";
1240 }; 1118 };
1241 1119
1242 qup_spi12_cs: qup-spi 1120 qup_spi12_cs: qup-spi12-cs-state {
1243 pins = "gpio2 1121 pins = "gpio27";
1244 function = "g 1122 function = "gpio";
1245 }; 1123 };
1246 1124
1247 qup_i2c13_data_clk: q 1125 qup_i2c13_data_clk: qup-i2c13-data-clk-state {
1248 pins = "gpio3 1126 pins = "gpio30", "gpio31";
1249 function = "q 1127 function = "qup15";
1250 }; 1128 };
1251 1129
1252 qup_spi13_data_clk: q 1130 qup_spi13_data_clk: qup-spi13-data-clk-state {
1253 pins = "gpio3 1131 pins = "gpio30", "gpio31", "gpio32";
1254 function = "q 1132 function = "qup15";
1255 }; 1133 };
1256 1134
1257 qup_spi13_cs: qup-spi 1135 qup_spi13_cs: qup-spi13-cs-state {
1258 pins = "gpio3 1136 pins = "gpio33";
1259 function = "g 1137 function = "gpio";
1260 }; 1138 };
1261 1139
1262 qup_uart13_default: q 1140 qup_uart13_default: qup-uart13-default-state {
1263 pins = "gpio3 1141 pins = "gpio30", "gpio31", "gpio32", "gpio33";
1264 function = "q 1142 function = "qup15";
1265 }; 1143 };
1266 1144
1267 qup_i2c14_data_clk: q 1145 qup_i2c14_data_clk: qup-i2c14-data-clk-state {
1268 pins = "gpio3 1146 pins = "gpio34", "gpio35";
1269 function = "q 1147 function = "qup16";
1270 }; 1148 };
1271 1149
1272 qup_spi14_data_clk: q 1150 qup_spi14_data_clk: qup-spi14-data-clk-state {
1273 pins = "gpio3 1151 pins = "gpio34", "gpio35", "gpio36";
1274 function = "q 1152 function = "qup16";
1275 }; 1153 };
1276 1154
1277 qup_spi14_cs: qup-spi 1155 qup_spi14_cs: qup-spi14-cs-state {
1278 pins = "gpio3 1156 pins = "gpio37", "gpio38";
1279 function = "g 1157 function = "gpio";
1280 }; 1158 };
1281 1159
1282 qup_i2c15_data_clk: q 1160 qup_i2c15_data_clk: qup-i2c15-data-clk-state {
1283 pins = "gpio4 1161 pins = "gpio40", "gpio41";
1284 function = "q 1162 function = "qup17";
1285 }; 1163 };
1286 1164
1287 qup_spi15_data_clk: q 1165 qup_spi15_data_clk: qup-spi15-data-clk-state {
1288 pins = "gpio4 1166 pins = "gpio40", "gpio41", "gpio30";
1289 function = "q 1167 function = "qup17";
1290 }; 1168 };
1291 1169
1292 qup_spi15_cs: qup-spi 1170 qup_spi15_cs: qup-spi15-cs-state {
1293 pins = "gpio3 1171 pins = "gpio31";
1294 function = "g 1172 function = "gpio";
1295 }; 1173 };
1296 1174
1297 sdc_on_state: sdc-on- 1175 sdc_on_state: sdc-on-state {
1298 clk-pins { 1176 clk-pins {
1299 pins 1177 pins = "sdc1_clk";
1300 drive 1178 drive-strength = <16>;
1301 bias- 1179 bias-disable;
1302 }; 1180 };
1303 1181
1304 cmd-pins { 1182 cmd-pins {
1305 pins 1183 pins = "sdc1_cmd";
1306 drive 1184 drive-strength = <10>;
1307 bias- 1185 bias-pull-up;
1308 }; 1186 };
1309 1187
1310 data-pins { 1188 data-pins {
1311 pins 1189 pins = "sdc1_data";
1312 drive 1190 drive-strength = <10>;
1313 bias- 1191 bias-pull-up;
1314 }; 1192 };
1315 1193
1316 rclk-pins { 1194 rclk-pins {
1317 pins 1195 pins = "sdc1_rclk";
1318 bias- 1196 bias-pull-down;
1319 }; 1197 };
1320 }; 1198 };
1321 1199
1322 sdc_off_state: sdc-of 1200 sdc_off_state: sdc-off-state {
1323 clk-pins { 1201 clk-pins {
1324 pins 1202 pins = "sdc1_clk";
1325 drive 1203 drive-strength = <2>;
1326 bias- 1204 bias-disable;
1327 }; 1205 };
1328 1206
1329 cmd-pins { 1207 cmd-pins {
1330 pins 1208 pins = "sdc1_cmd";
1331 drive 1209 drive-strength = <2>;
1332 bias- 1210 bias-pull-up;
1333 }; 1211 };
1334 1212
1335 data-pins { 1213 data-pins {
1336 pins 1214 pins = "sdc1_data";
1337 drive 1215 drive-strength = <2>;
1338 bias- 1216 bias-pull-up;
1339 }; 1217 };
1340 1218
1341 rclk-pins { 1219 rclk-pins {
1342 pins 1220 pins = "sdc1_rclk";
1343 bias- 1221 bias-pull-down;
1344 }; 1222 };
1345 }; 1223 };
1346 }; 1224 };
1347 1225
1348 sram@14680000 { 1226 sram@14680000 {
1349 compatible = "qcom,qd 1227 compatible = "qcom,qdu1000-imem", "syscon", "simple-mfd";
1350 reg = <0 0x14680000 0 1228 reg = <0 0x14680000 0 0x1000>;
1351 ranges = <0 0 0x14680 1229 ranges = <0 0 0x14680000 0x1000>;
1352 #address-cells = <1>; 1230 #address-cells = <1>;
1353 #size-cells = <1>; 1231 #size-cells = <1>;
1354 1232
1355 pil-reloc@94c { 1233 pil-reloc@94c {
1356 compatible = 1234 compatible = "qcom,pil-reloc-info";
1357 reg = <0x94c 1235 reg = <0x94c 0xc8>;
1358 }; 1236 };
1359 }; 1237 };
1360 1238
1361 apps_smmu: iommu@15000000 { 1239 apps_smmu: iommu@15000000 {
1362 compatible = "qcom,qd 1240 compatible = "qcom,qdu1000-smmu-500", "qcom,smmu-500", "arm,mmu-500";
1363 reg = <0x0 0x15000000 1241 reg = <0x0 0x15000000 0x0 0x100000>;
1364 #iommu-cells = <2>; 1242 #iommu-cells = <2>;
1365 #global-interrupts = 1243 #global-interrupts = <2>;
1366 interrupts = <GIC_SPI 1244 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
1367 <GIC_SPI 1245 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
1368 <GIC_SPI 1246 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1369 <GIC_SPI 1247 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
1370 <GIC_SPI 1248 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
1371 <GIC_SPI 1249 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
1372 <GIC_SPI 1250 <GIC_SPI 671 IRQ_TYPE_LEVEL_HIGH>,
1373 <GIC_SPI 1251 <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
1374 <GIC_SPI 1252 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
1375 <GIC_SPI 1253 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
1376 <GIC_SPI 1254 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
1377 <GIC_SPI 1255 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1378 <GIC_SPI 1256 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1379 <GIC_SPI 1257 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1380 <GIC_SPI 1258 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1381 <GIC_SPI 1259 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1382 <GIC_SPI 1260 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
1383 <GIC_SPI 1261 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1384 <GIC_SPI 1262 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
1385 <GIC_SPI 1263 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1386 <GIC_SPI 1264 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1387 <GIC_SPI 1265 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
1388 <GIC_SPI 1266 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
1389 <GIC_SPI 1267 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
1390 <GIC_SPI 1268 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
1391 <GIC_SPI 1269 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
1392 <GIC_SPI 1270 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
1393 <GIC_SPI 1271 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1394 <GIC_SPI 1272 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1395 <GIC_SPI 1273 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1396 <GIC_SPI 1274 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
1397 <GIC_SPI 1275 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
1398 <GIC_SPI 1276 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
1399 <GIC_SPI 1277 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
1400 <GIC_SPI 1278 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
1401 <GIC_SPI 1279 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
1402 <GIC_SPI 1280 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
1403 <GIC_SPI 1281 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
1404 <GIC_SPI 1282 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
1405 <GIC_SPI 1283 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
1406 <GIC_SPI 1284 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
1407 <GIC_SPI 1285 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
1408 <GIC_SPI 1286 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
1409 <GIC_SPI 1287 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
1410 <GIC_SPI 1288 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
1411 <GIC_SPI 1289 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
1412 <GIC_SPI 1290 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
1413 <GIC_SPI 1291 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
1414 <GIC_SPI 1292 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
1415 }; 1293 };
1416 1294
1417 intc: interrupt-controller@17 1295 intc: interrupt-controller@17200000 {
1418 compatible = "arm,gic 1296 compatible = "arm,gic-v3";
1419 reg = <0x0 0x17200000 1297 reg = <0x0 0x17200000 0x0 0x10000>, /* GICD */
1420 <0x0 0x17260000 1298 <0x0 0x17260000 0x0 0x80000>; /* GICR * 4 */
1421 interrupts = <GIC_PPI 1299 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
1422 #interrupt-cells = <3 1300 #interrupt-cells = <3>;
1423 interrupt-controller; 1301 interrupt-controller;
1424 #redistributor-region 1302 #redistributor-regions = <1>;
1425 redistributor-stride 1303 redistributor-stride = <0x0 0x20000>;
1426 }; 1304 };
1427 1305
1428 timer@17420000 { 1306 timer@17420000 {
1429 compatible = "arm,arm 1307 compatible = "arm,armv7-timer-mem";
1430 reg = <0x0 0x17420000 1308 reg = <0x0 0x17420000 0x0 0x1000>;
1431 #address-cells = <1>; 1309 #address-cells = <1>;
1432 #size-cells = <1>; 1310 #size-cells = <1>;
1433 ranges = <0x0 0x0 0x0 1311 ranges = <0x0 0x0 0x0 0x20000000>;
1434 1312
1435 frame@17421000 { 1313 frame@17421000 {
1436 reg = <0x1742 1314 reg = <0x17421000 0x1000>,
1437 <0x1742 1315 <0x17422000 0x1000>;
1438 interrupts = 1316 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
1439 1317 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1440 frame-number 1318 frame-number = <0>;
1441 }; 1319 };
1442 1320
1443 frame@17423000 { 1321 frame@17423000 {
1444 reg = <0x1742 1322 reg = <0x17423000 0x1000>;
1445 interrupts = 1323 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1446 frame-number 1324 frame-number = <1>;
1447 status = "dis 1325 status = "disabled";
1448 }; 1326 };
1449 1327
1450 frame@17425000 { 1328 frame@17425000 {
1451 reg = <0x1742 1329 reg = <0x17425000 0x1000>,
1452 <0x1742 1330 <0x17426000 0x1000>;
1453 interrupts = 1331 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1454 frame-number 1332 frame-number = <2>;
1455 status = "dis 1333 status = "disabled";
1456 }; 1334 };
1457 1335
1458 frame@17427000 { 1336 frame@17427000 {
1459 reg = <0x1742 1337 reg = <0x17427000 0x1000>;
1460 interrupts = 1338 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1461 frame-number 1339 frame-number = <3>;
1462 status = "dis 1340 status = "disabled";
1463 }; 1341 };
1464 1342
1465 frame@17429000 { 1343 frame@17429000 {
1466 reg = <0x1742 1344 reg = <0x17429000 0x1000>;
1467 interrupts = 1345 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1468 frame-number 1346 frame-number = <4>;
1469 status = "dis 1347 status = "disabled";
1470 }; 1348 };
1471 1349
1472 frame@1742b000 { 1350 frame@1742b000 {
1473 reg = <0x1742 1351 reg = <0x1742b000 0x1000>;
1474 interrupts = 1352 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1475 frame-number 1353 frame-number = <5>;
1476 status = "dis 1354 status = "disabled";
1477 }; 1355 };
1478 1356
1479 frame@1742d000 { 1357 frame@1742d000 {
1480 reg = <0x1742 1358 reg = <0x1742d000 0x1000>;
1481 interrupts = 1359 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1482 frame-number 1360 frame-number = <6>;
1483 status = "dis 1361 status = "disabled";
1484 }; 1362 };
1485 }; 1363 };
1486 1364
1487 apps_rsc: rsc@17a00000 { 1365 apps_rsc: rsc@17a00000 {
1488 compatible = "qcom,rp 1366 compatible = "qcom,rpmh-rsc";
1489 reg = <0x0 0x17a00000 1367 reg = <0x0 0x17a00000 0x0 0x10000>,
1490 <0x0 0x17a10000 1368 <0x0 0x17a10000 0x0 0x10000>,
1491 <0x0 0x17a20000 1369 <0x0 0x17a20000 0x0 0x10000>;
1492 reg-names = "drv-0", 1370 reg-names = "drv-0", "drv-1", "drv-2";
1493 interrupts = <GIC_SPI 1371 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
1494 <GIC_SPI 1372 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
1495 <GIC_SPI 1373 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1496 qcom,tcs-offset = <0x 1374 qcom,tcs-offset = <0xd00>;
1497 qcom,drv-id = <2>; 1375 qcom,drv-id = <2>;
1498 qcom,tcs-config = <AC 1376 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
1499 <WA 1377 <WAKE_TCS 3>, <CONTROL_TCS 0>;
1500 label = "apps_rsc"; 1378 label = "apps_rsc";
1501 power-domains = <&CLU 1379 power-domains = <&CLUSTER_PD>;
1502 1380
1503 apps_bcm_voter: bcm-v 1381 apps_bcm_voter: bcm-voter {
1504 compatible = 1382 compatible = "qcom,bcm-voter";
1505 }; 1383 };
1506 1384
1507 rpmhcc: clock-control 1385 rpmhcc: clock-controller {
1508 compatible = 1386 compatible = "qcom,qdu1000-rpmh-clk";
1509 clocks = <&xo 1387 clocks = <&xo_board>;
1510 clock-names = 1388 clock-names = "xo";
1511 #clock-cells 1389 #clock-cells = <1>;
1512 }; 1390 };
1513 1391
1514 rpmhpd: power-control 1392 rpmhpd: power-controller {
1515 compatible = 1393 compatible = "qcom,qdu1000-rpmhpd";
1516 #power-domain 1394 #power-domain-cells = <1>;
1517 operating-poi 1395 operating-points-v2 = <&rpmhpd_opp_table>;
1518 1396
1519 rpmhpd_opp_ta 1397 rpmhpd_opp_table: opp-table {
1520 compa 1398 compatible = "operating-points-v2";
1521 1399
1522 rpmhp 1400 rpmhpd_opp_ret: opp1 {
1523 1401 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
1524 }; 1402 };
1525 1403
1526 rpmhp 1404 rpmhpd_opp_min_svs: opp2 {
1527 1405 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
1528 }; 1406 };
1529 1407
1530 rpmhp 1408 rpmhpd_opp_low_svs: opp3 {
1531 1409 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1532 }; 1410 };
1533 1411
1534 rpmhp 1412 rpmhpd_opp_svs: opp4 {
1535 1413 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1536 }; 1414 };
1537 1415
1538 rpmhp 1416 rpmhpd_opp_svs_l1: opp5 {
1539 1417 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1540 }; 1418 };
1541 1419
1542 rpmhp 1420 rpmhpd_opp_nom: opp6 {
1543 1421 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1544 }; 1422 };
1545 1423
1546 rpmhp 1424 rpmhpd_opp_nom_l1: opp7 {
1547 1425 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1548 }; 1426 };
1549 1427
1550 rpmhp 1428 rpmhpd_opp_nom_l2: opp8 {
1551 1429 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
1552 }; 1430 };
1553 1431
1554 rpmhp 1432 rpmhpd_opp_turbo: opp9 {
1555 1433 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1556 }; 1434 };
1557 1435
1558 rpmhp 1436 rpmhpd_opp_turbo_l1: opp10 {
1559 1437 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
1560 }; 1438 };
1561 }; 1439 };
1562 }; 1440 };
1563 }; 1441 };
1564 1442
1565 cpufreq_hw: cpufreq@17d90000 1443 cpufreq_hw: cpufreq@17d90000 {
1566 compatible = "qcom,qd 1444 compatible = "qcom,qdu1000-cpufreq-epss", "qcom,cpufreq-epss";
1567 reg = <0x0 0x17d90000 1445 reg = <0x0 0x17d90000 0x0 0x1000>, <0x0 0x17d91000 0x0 0x1000>;
1568 reg-names = "freq-dom 1446 reg-names = "freq-domain0", "freq-domain1";
1569 clocks = <&rpmhcc RPM 1447 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
1570 clock-names = "xo", " 1448 clock-names = "xo", "alternate";
1571 #freq-domain-cells = 1449 #freq-domain-cells = <1>;
1572 #clock-cells = <1>; 1450 #clock-cells = <1>;
1573 }; 1451 };
1574 1452
1575 gem_noc: interconnect@1910000 1453 gem_noc: interconnect@19100000 {
1576 compatible = "qcom,qd 1454 compatible = "qcom,qdu1000-gem-noc";
1577 reg = <0x0 0x19100000 1455 reg = <0x0 0x19100000 0x0 0xB8080>;
1578 qcom,bcm-voters = <&a 1456 qcom,bcm-voters = <&apps_bcm_voter>;
1579 #interconnect-cells = 1457 #interconnect-cells = <2>;
1580 }; 1458 };
1581 1459
1582 system-cache-controller@19200 1460 system-cache-controller@19200000 {
1583 compatible = "qcom,qd 1461 compatible = "qcom,qdu1000-llcc";
1584 reg = <0 0x19200000 0 !! 1462 reg = <0 0x19200000 0 0xd80000>,
1585 <0 0x19300000 0 <<
1586 <0 0x19600000 0 <<
1587 <0 0x19700000 0 <<
1588 <0 0x19a00000 0 <<
1589 <0 0x19b00000 0 <<
1590 <0 0x19e00000 0 <<
1591 <0 0x19f00000 0 <<
1592 <0 0x1a200000 0 1463 <0 0x1a200000 0 0x80000>;
1593 reg-names = "llcc0_ba 1464 reg-names = "llcc0_base",
1594 "llcc1_ba <<
1595 "llcc2_ba <<
1596 "llcc3_ba <<
1597 "llcc4_ba <<
1598 "llcc5_ba <<
1599 "llcc6_ba <<
1600 "llcc7_ba <<
1601 "llcc_bro 1465 "llcc_broadcast_base";
1602 interrupts = <GIC_SPI 1466 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
1603 <<
1604 nvmem-cells = <&multi <<
1605 nvmem-cell-names = "m <<
1606 }; <<
1607 <<
1608 sec_qfprom: efuse@221c8000 { <<
1609 compatible = "qcom,qd <<
1610 reg = <0 0x221c8000 0 <<
1611 #address-cells = <1>; <<
1612 #size-cells = <1>; <<
1613 <<
1614 multi_chan_ddr: multi <<
1615 reg = <0x12b <<
1616 bits = <0 2>; <<
1617 }; <<
1618 }; 1467 };
1619 }; 1468 };
1620 1469
1621 timer { 1470 timer {
1622 compatible = "arm,armv8-timer 1471 compatible = "arm,armv8-timer";
1623 interrupts = <GIC_PPI 13 (GIC 1472 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1624 <GIC_PPI 14 (GIC 1473 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1625 <GIC_PPI 11 (GIC 1474 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1626 <GIC_PPI 10 (GIC 1475 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1627 <GIC_PPI 12 (GIC 1476 <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
1628 }; 1477 };
1629 }; 1478 };
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