1 // SPDX-License-Identifier: BSD-3-Clause
2 /*
3 * Copyright (c) 2023, Linaro Limited
4 */
5
6 #include <dt-bindings/interconnect/qcom,icc.h>
7 #include <dt-bindings/interrupt-controller/arm
8 #include <dt-bindings/clock/qcom,rpmh.h>
9 #include <dt-bindings/clock/qcom,sa8775p-gcc.h
10 #include <dt-bindings/clock/qcom,sa8775p-gpucc
11 #include <dt-bindings/interconnect/qcom,sa8775
12 #include <dt-bindings/mailbox/qcom-ipcc.h>
13 #include <dt-bindings/firmware/qcom,scm.h>
14 #include <dt-bindings/power/qcom,rpmhpd.h>
15 #include <dt-bindings/power/qcom-rpmpd.h>
16 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
17
18 / {
19 interrupt-parent = <&intc>;
20
21 #address-cells = <2>;
22 #size-cells = <2>;
23
24 clocks {
25 xo_board_clk: xo-board-clk {
26 compatible = "fixed-cl
27 #clock-cells = <0>;
28 };
29
30 sleep_clk: sleep-clk {
31 compatible = "fixed-cl
32 #clock-cells = <0>;
33 };
34 };
35
36 cpus {
37 #address-cells = <2>;
38 #size-cells = <0>;
39
40 CPU0: cpu@0 {
41 device_type = "cpu";
42 compatible = "qcom,kry
43 reg = <0x0 0x0>;
44 enable-method = "psci"
45 qcom,freq-domain = <&c
46 next-level-cache = <&L
47 capacity-dmips-mhz = <
48 dynamic-power-coeffici
49 L2_0: l2-cache {
50 compatible = "
51 cache-level =
52 cache-unified;
53 next-level-cac
54 L3_0: l3-cache
55 compat
56 cache-
57 cache-
58 };
59 };
60 };
61
62 CPU1: cpu@100 {
63 device_type = "cpu";
64 compatible = "qcom,kry
65 reg = <0x0 0x100>;
66 enable-method = "psci"
67 qcom,freq-domain = <&c
68 next-level-cache = <&L
69 capacity-dmips-mhz = <
70 dynamic-power-coeffici
71 L2_1: l2-cache {
72 compatible = "
73 cache-level =
74 cache-unified;
75 next-level-cac
76 };
77 };
78
79 CPU2: cpu@200 {
80 device_type = "cpu";
81 compatible = "qcom,kry
82 reg = <0x0 0x200>;
83 enable-method = "psci"
84 qcom,freq-domain = <&c
85 next-level-cache = <&L
86 capacity-dmips-mhz = <
87 dynamic-power-coeffici
88 L2_2: l2-cache {
89 compatible = "
90 cache-level =
91 cache-unified;
92 next-level-cac
93 };
94 };
95
96 CPU3: cpu@300 {
97 device_type = "cpu";
98 compatible = "qcom,kry
99 reg = <0x0 0x300>;
100 enable-method = "psci"
101 qcom,freq-domain = <&c
102 next-level-cache = <&L
103 capacity-dmips-mhz = <
104 dynamic-power-coeffici
105 L2_3: l2-cache {
106 compatible = "
107 cache-level =
108 cache-unified;
109 next-level-cac
110 };
111 };
112
113 CPU4: cpu@10000 {
114 device_type = "cpu";
115 compatible = "qcom,kry
116 reg = <0x0 0x10000>;
117 enable-method = "psci"
118 qcom,freq-domain = <&c
119 next-level-cache = <&L
120 capacity-dmips-mhz = <
121 dynamic-power-coeffici
122 L2_4: l2-cache {
123 compatible = "
124 cache-level =
125 cache-unified;
126 next-level-cac
127 L3_1: l3-cache
128 compat
129 cache-
130 cache-
131 };
132
133 };
134 };
135
136 CPU5: cpu@10100 {
137 device_type = "cpu";
138 compatible = "qcom,kry
139 reg = <0x0 0x10100>;
140 enable-method = "psci"
141 qcom,freq-domain = <&c
142 next-level-cache = <&L
143 capacity-dmips-mhz = <
144 dynamic-power-coeffici
145 L2_5: l2-cache {
146 compatible = "
147 cache-level =
148 cache-unified;
149 next-level-cac
150 };
151 };
152
153 CPU6: cpu@10200 {
154 device_type = "cpu";
155 compatible = "qcom,kry
156 reg = <0x0 0x10200>;
157 enable-method = "psci"
158 qcom,freq-domain = <&c
159 next-level-cache = <&L
160 capacity-dmips-mhz = <
161 dynamic-power-coeffici
162 L2_6: l2-cache {
163 compatible = "
164 cache-level =
165 cache-unified;
166 next-level-cac
167 };
168 };
169
170 CPU7: cpu@10300 {
171 device_type = "cpu";
172 compatible = "qcom,kry
173 reg = <0x0 0x10300>;
174 enable-method = "psci"
175 qcom,freq-domain = <&c
176 next-level-cache = <&L
177 capacity-dmips-mhz = <
178 dynamic-power-coeffici
179 L2_7: l2-cache {
180 compatible = "
181 cache-level =
182 cache-unified;
183 next-level-cac
184 };
185 };
186
187 cpu-map {
188 cluster0 {
189 core0 {
190 cpu =
191 };
192
193 core1 {
194 cpu =
195 };
196
197 core2 {
198 cpu =
199 };
200
201 core3 {
202 cpu =
203 };
204 };
205
206 cluster1 {
207 core0 {
208 cpu =
209 };
210
211 core1 {
212 cpu =
213 };
214
215 core2 {
216 cpu =
217 };
218
219 core3 {
220 cpu =
221 };
222 };
223 };
224
225 idle-states {
226 entry-method = "psci";
227
228 GOLD_CPU_SLEEP_0: cpu-
229 compatible = "
230 idle-state-nam
231 arm,psci-suspe
232 entry-latency-
233 exit-latency-u
234 min-residency-
235 local-timer-st
236 };
237
238 GOLD_RAIL_CPU_SLEEP_0:
239 compatible = "
240 idle-state-nam
241 arm,psci-suspe
242 entry-latency-
243 exit-latency-u
244 min-residency-
245 local-timer-st
246 };
247 };
248
249 domain-idle-states {
250 CLUSTER_SLEEP_GOLD: cl
251 compatible = "
252 arm,psci-suspe
253 entry-latency-
254 exit-latency-u
255 min-residency-
256 };
257
258 CLUSTER_SLEEP_APSS_RSC
259 compatible = "
260 arm,psci-suspe
261 entry-latency-
262 exit-latency-u
263 min-residency-
264 };
265 };
266 };
267
268 dummy-sink {
269 compatible = "arm,coresight-du
270
271 in-ports {
272 port {
273 eud_in: endpoi
274 remote
275 <&swao
276 };
277 };
278 };
279 };
280
281 firmware {
282 scm {
283 compatible = "qcom,scm
284 memory-region = <&tz_f
285 };
286 };
287
288 aggre1_noc: interconnect-aggre1-noc {
289 compatible = "qcom,sa8775p-agg
290 #interconnect-cells = <2>;
291 qcom,bcm-voters = <&apps_bcm_v
292 };
293
294 aggre2_noc: interconnect-aggre2-noc {
295 compatible = "qcom,sa8775p-agg
296 #interconnect-cells = <2>;
297 qcom,bcm-voters = <&apps_bcm_v
298 };
299
300 clk_virt: interconnect-clk-virt {
301 compatible = "qcom,sa8775p-clk
302 #interconnect-cells = <2>;
303 qcom,bcm-voters = <&apps_bcm_v
304 };
305
306 config_noc: interconnect-config-noc {
307 compatible = "qcom,sa8775p-con
308 #interconnect-cells = <2>;
309 qcom,bcm-voters = <&apps_bcm_v
310 };
311
312 dc_noc: interconnect-dc-noc {
313 compatible = "qcom,sa8775p-dc-
314 #interconnect-cells = <2>;
315 qcom,bcm-voters = <&apps_bcm_v
316 };
317
318 gem_noc: interconnect-gem-noc {
319 compatible = "qcom,sa8775p-gem
320 #interconnect-cells = <2>;
321 qcom,bcm-voters = <&apps_bcm_v
322 };
323
324 gpdsp_anoc: interconnect-gpdsp-anoc {
325 compatible = "qcom,sa8775p-gpd
326 #interconnect-cells = <2>;
327 qcom,bcm-voters = <&apps_bcm_v
328 };
329
330 lpass_ag_noc: interconnect-lpass-ag-no
331 compatible = "qcom,sa8775p-lpa
332 #interconnect-cells = <2>;
333 qcom,bcm-voters = <&apps_bcm_v
334 };
335
336 mc_virt: interconnect-mc-virt {
337 compatible = "qcom,sa8775p-mc-
338 #interconnect-cells = <2>;
339 qcom,bcm-voters = <&apps_bcm_v
340 };
341
342 mmss_noc: interconnect-mmss-noc {
343 compatible = "qcom,sa8775p-mms
344 #interconnect-cells = <2>;
345 qcom,bcm-voters = <&apps_bcm_v
346 };
347
348 nspa_noc: interconnect-nspa-noc {
349 compatible = "qcom,sa8775p-nsp
350 #interconnect-cells = <2>;
351 qcom,bcm-voters = <&apps_bcm_v
352 };
353
354 nspb_noc: interconnect-nspb-noc {
355 compatible = "qcom,sa8775p-nsp
356 #interconnect-cells = <2>;
357 qcom,bcm-voters = <&apps_bcm_v
358 };
359
360 pcie_anoc: interconnect-pcie-anoc {
361 compatible = "qcom,sa8775p-pci
362 #interconnect-cells = <2>;
363 qcom,bcm-voters = <&apps_bcm_v
364 };
365
366 system_noc: interconnect-system-noc {
367 compatible = "qcom,sa8775p-sys
368 #interconnect-cells = <2>;
369 qcom,bcm-voters = <&apps_bcm_v
370 };
371
372 /* Will be updated by the bootloader.
373 memory@80000000 {
374 device_type = "memory";
375 reg = <0x0 0x80000000 0x0 0x0>
376 };
377
378 qup_opp_table_100mhz: opp-table-qup100
379 compatible = "operating-points
380
381 opp-100000000 {
382 opp-hz = /bits/ 64 <10
383 required-opps = <&rpmh
384 };
385 };
386
387 pmu {
388 compatible = "arm,armv8-pmuv3"
389 interrupts = <GIC_PPI 7 IRQ_TY
390 };
391
392 psci {
393 compatible = "arm,psci-1.0";
394 method = "smc";
395
396 CPU_PD0: power-domain-cpu0 {
397 #power-domain-cells =
398 power-domains = <&CLUS
399 domain-idle-states = <
400 <
401 };
402
403 CPU_PD1: power-domain-cpu1 {
404 #power-domain-cells =
405 power-domains = <&CLUS
406 domain-idle-states = <
407 <
408 };
409
410 CPU_PD2: power-domain-cpu2 {
411 #power-domain-cells =
412 power-domains = <&CLUS
413 domain-idle-states = <
414 <
415 };
416
417 CPU_PD3: power-domain-cpu3 {
418 #power-domain-cells =
419 power-domains = <&CLUS
420 domain-idle-states = <
421 <
422 };
423
424 CPU_PD4: power-domain-cpu4 {
425 #power-domain-cells =
426 power-domains = <&CLUS
427 domain-idle-states = <
428 <
429 };
430
431 CPU_PD5: power-domain-cpu5 {
432 #power-domain-cells =
433 power-domains = <&CLUS
434 domain-idle-states = <
435 <
436 };
437
438 CPU_PD6: power-domain-cpu6 {
439 #power-domain-cells =
440 power-domains = <&CLUS
441 domain-idle-states = <
442 <
443 };
444
445 CPU_PD7: power-domain-cpu7 {
446 #power-domain-cells =
447 power-domains = <&CLUS
448 domain-idle-states = <
449 <
450 };
451
452 CLUSTER_0_PD: power-domain-clu
453 #power-domain-cells =
454 power-domains = <&CLUS
455 domain-idle-states = <
456 };
457
458 CLUSTER_1_PD: power-domain-clu
459 #power-domain-cells =
460 power-domains = <&CLUS
461 domain-idle-states = <
462 };
463
464 CLUSTER_2_PD: power-domain-clu
465 #power-domain-cells =
466 domain-idle-states = <
467 };
468 };
469
470 reserved-memory {
471 #address-cells = <2>;
472 #size-cells = <2>;
473 ranges;
474
475 sail_ss_mem: sail-ss@80000000
476 reg = <0x0 0x80000000
477 no-map;
478 };
479
480 hyp_mem: hyp@90000000 {
481 reg = <0x0 0x90000000
482 no-map;
483 };
484
485 xbl_boot_mem: xbl-boot@9060000
486 reg = <0x0 0x90600000
487 no-map;
488 };
489
490 aop_image_mem: aop-image@90800
491 reg = <0x0 0x90800000
492 no-map;
493 };
494
495 aop_cmd_db_mem: aop-cmd-db@908
496 compatible = "qcom,cmd
497 reg = <0x0 0x90860000
498 no-map;
499 };
500
501 uefi_log: uefi-log@908b0000 {
502 reg = <0x0 0x908b0000
503 no-map;
504 };
505
506 ddr_training_checksum: ddr-tra
507 reg = <0x0 0x908c0000
508 no-map;
509 };
510
511 reserved_mem: reserved@908f000
512 reg = <0x0 0x908f0000
513 no-map;
514 };
515
516 secdata_apss_mem: secdata-apss
517 reg = <0x0 0x908fe000
518 no-map;
519 };
520
521 smem_mem: smem@90900000 {
522 compatible = "qcom,sme
523 reg = <0x0 0x90900000
524 no-map;
525 hwlocks = <&tcsr_mutex
526 };
527
528 tz_sail_mailbox_mem: tz-sail-m
529 reg = <0x0 0x90c00000
530 no-map;
531 };
532
533 sail_mailbox_mem: sail-ss@90d0
534 reg = <0x0 0x90d00000
535 no-map;
536 };
537
538 sail_ota_mem: sail-ss@90e00000
539 reg = <0x0 0x90e00000
540 no-map;
541 };
542
543 aoss_backup_mem: aoss-backup@9
544 reg = <0x0 0x91b00000
545 no-map;
546 };
547
548 cpucp_backup_mem: cpucp-backup
549 reg = <0x0 0x91b40000
550 no-map;
551 };
552
553 tz_config_backup_mem: tz-confi
554 reg = <0x0 0x91b80000
555 no-map;
556 };
557
558 ddr_training_data_mem: ddr-tra
559 reg = <0x0 0x91b90000
560 no-map;
561 };
562
563 cdt_data_backup_mem: cdt-data-
564 reg = <0x0 0x91ba0000
565 no-map;
566 };
567
568 tz_ffi_mem: tz-ffi@91c00000 {
569 compatible = "shared-d
570 reg = <0x0 0x91c00000
571 no-map;
572 };
573
574 lpass_machine_learning_mem: lp
575 reg = <0x0 0x93b00000
576 no-map;
577 };
578
579 adsp_rpc_remote_heap_mem: adsp
580 reg = <0x0 0x94a00000
581 no-map;
582 };
583
584 pil_camera_mem: pil-camera@952
585 reg = <0x0 0x95200000
586 no-map;
587 };
588
589 pil_adsp_mem: pil-adsp@95c0000
590 reg = <0x0 0x95c00000
591 no-map;
592 };
593
594 pil_gdsp0_mem: pil-gdsp0@97b00
595 reg = <0x0 0x97b00000
596 no-map;
597 };
598
599 pil_gdsp1_mem: pil-gdsp1@99900
600 reg = <0x0 0x99900000
601 no-map;
602 };
603
604 pil_cdsp0_mem: pil-cdsp0@9b800
605 reg = <0x0 0x9b800000
606 no-map;
607 };
608
609 pil_gpu_mem: pil-gpu@9d600000
610 reg = <0x0 0x9d600000
611 no-map;
612 };
613
614 pil_cdsp1_mem: pil-cdsp1@9d700
615 reg = <0x0 0x9d700000
616 no-map;
617 };
618
619 pil_cvp_mem: pil-cvp@9f500000
620 reg = <0x0 0x9f500000
621 no-map;
622 };
623
624 pil_video_mem: pil-video@9fc00
625 reg = <0x0 0x9fc00000
626 no-map;
627 };
628
629 audio_mdf_mem: audio-mdf-regio
630 reg = <0x0 0xae000000
631 no-map;
632 };
633
634 firmware_mem: firmware-region@
635 reg = <0x0 0xb0000000
636 no-map;
637 };
638
639 hyptz_reserved_mem: hyptz-rese
640 reg = <0x0 0xbeb00000
641 no-map;
642 };
643
644 scmi_mem: scmi-region@d0000000
645 reg = <0x0 0xd0000000
646 no-map;
647 };
648
649 firmware_logs_mem: firmware-lo
650 reg = <0x0 0xd0040000
651 no-map;
652 };
653
654 firmware_audio_mem: firmware-a
655 reg = <0x0 0xd0050000
656 no-map;
657 };
658
659 firmware_reserved_mem: firmwar
660 reg = <0x0 0xd0054000
661 no-map;
662 };
663
664 firmware_quantum_test_mem: fir
665 reg = <0x0 0xd00f0000
666 no-map;
667 };
668
669 tags_mem: tags@d0100000 {
670 reg = <0x0 0xd0100000
671 no-map;
672 };
673
674 qtee_mem: qtee@d1300000 {
675 reg = <0x0 0xd1300000
676 no-map;
677 };
678
679 deepsleep_backup_mem: deepslee
680 reg = <0x0 0xd1800000
681 no-map;
682 };
683
684 trusted_apps_mem: trusted-apps
685 reg = <0x0 0xd1900000
686 no-map;
687 };
688
689 tz_stat_mem: tz-stat@db100000
690 reg = <0x0 0xdb100000
691 no-map;
692 };
693
694 cpucp_fw_mem: cpucp-fw@db20000
695 reg = <0x0 0xdb200000
696 no-map;
697 };
698 };
699
700 smp2p-adsp {
701 compatible = "qcom,smp2p";
702 qcom,smem = <443>, <429>;
703 interrupts-extended = <&ipcc I
704 I
705 I
706 mboxes = <&ipcc IPCC_CLIENT_LP
707
708 qcom,local-pid = <0>;
709 qcom,remote-pid = <2>;
710
711 smp2p_adsp_out: master-kernel
712 qcom,entry-name = "mas
713 #qcom,smem-state-cells
714 };
715
716 smp2p_adsp_in: slave-kernel {
717 qcom,entry-name = "sla
718 interrupt-controller;
719 #interrupt-cells = <2>
720 };
721 };
722
723 smp2p-cdsp0 {
724 compatible = "qcom,smp2p";
725 qcom,smem = <94>, <432>;
726 interrupts-extended = <&ipcc I
727 I
728 I
729 mboxes = <&ipcc IPCC_CLIENT_CD
730
731 qcom,local-pid = <0>;
732 qcom,remote-pid = <5>;
733
734 smp2p_cdsp0_out: master-kernel
735 qcom,entry-name = "mas
736 #qcom,smem-state-cells
737 };
738
739 smp2p_cdsp0_in: slave-kernel {
740 qcom,entry-name = "sla
741 interrupt-controller;
742 #interrupt-cells = <2>
743 };
744 };
745
746 smp2p-cdsp1 {
747 compatible = "qcom,smp2p";
748 qcom,smem = <617>, <616>;
749 interrupts-extended = <&ipcc I
750 I
751 I
752 mboxes = <&ipcc IPCC_CLIENT_NS
753
754 qcom,local-pid = <0>;
755 qcom,remote-pid = <12>;
756
757 smp2p_cdsp1_out: master-kernel
758 qcom,entry-name = "mas
759 #qcom,smem-state-cells
760 };
761
762 smp2p_cdsp1_in: slave-kernel {
763 qcom,entry-name = "sla
764 interrupt-controller;
765 #interrupt-cells = <2>
766 };
767 };
768
769 smp2p-gpdsp0 {
770 compatible = "qcom,smp2p";
771 qcom,smem = <617>, <616>;
772 interrupts-extended = <&ipcc I
773 I
774 I
775 mboxes = <&ipcc IPCC_CLIENT_GP
776
777 qcom,local-pid = <0>;
778 qcom,remote-pid = <17>;
779
780 smp2p_gpdsp0_out: master-kerne
781 qcom,entry-name = "mas
782 #qcom,smem-state-cells
783 };
784
785 smp2p_gpdsp0_in: slave-kernel
786 qcom,entry-name = "sla
787 interrupt-controller;
788 #interrupt-cells = <2>
789 };
790 };
791
792 smp2p-gpdsp1 {
793 compatible = "qcom,smp2p";
794 qcom,smem = <617>, <616>;
795 interrupts-extended = <&ipcc I
796 I
797 I
798 mboxes = <&ipcc IPCC_CLIENT_GP
799
800 qcom,local-pid = <0>;
801 qcom,remote-pid = <18>;
802
803 smp2p_gpdsp1_out: master-kerne
804 qcom,entry-name = "mas
805 #qcom,smem-state-cells
806 };
807
808 smp2p_gpdsp1_in: slave-kernel
809 qcom,entry-name = "sla
810 interrupt-controller;
811 #interrupt-cells = <2>
812 };
813 };
814
815 soc: soc@0 {
816 compatible = "simple-bus";
817 #address-cells = <2>;
818 #size-cells = <2>;
819 ranges = <0 0 0 0 0x10 0>;
820
821 gcc: clock-controller@100000 {
822 compatible = "qcom,sa8
823 reg = <0x0 0x00100000
824 #clock-cells = <1>;
825 #reset-cells = <1>;
826 #power-domain-cells =
827 clocks = <&rpmhcc RPMH
828 <&sleep_clk>,
829 <0>,
830 <0>,
831 <0>,
832 <&usb_0_qmpph
833 <&usb_1_qmpph
834 <0>,
835 <0>,
836 <0>,
837 <&pcie0_phy>,
838 <&pcie1_phy>,
839 <0>,
840 <0>,
841 <0>;
842 power-domains = <&rpmh
843 };
844
845 ipcc: mailbox@408000 {
846 compatible = "qcom,sa8
847 reg = <0x0 0x00408000
848 interrupts = <GIC_SPI
849 interrupt-controller;
850 #interrupt-cells = <3>
851 #mbox-cells = <2>;
852 };
853
854 qupv3_id_2: geniqup@8c0000 {
855 compatible = "qcom,gen
856 reg = <0x0 0x008c0000
857 ranges;
858 clocks = <&gcc GCC_QUP
859 <&gcc GCC_QUP
860 clock-names = "m-ahb",
861 iommus = <&apps_smmu 0
862 #address-cells = <2>;
863 #size-cells = <2>;
864 status = "disabled";
865
866 i2c14: i2c@880000 {
867 compatible = "
868 reg = <0x0 0x8
869 #address-cells
870 #size-cells =
871 interrupts = <
872 clocks = <&gcc
873 clock-names =
874 interconnects
875
876
877
878
879
880 interconnect-n
881
882
883 power-domains
884 status = "disa
885 };
886
887 spi14: spi@880000 {
888 compatible = "
889 reg = <0x0 0x8
890 #address-cells
891 #size-cells =
892 interrupts = <
893 clocks = <&gcc
894 clock-names =
895 interconnects
896
897
898
899
900
901 interconnect-n
902
903
904 power-domains
905 status = "disa
906 };
907
908 i2c15: i2c@884000 {
909 compatible = "
910 reg = <0x0 0x8
911 #address-cells
912 #size-cells =
913 interrupts = <
914 clocks = <&gcc
915 clock-names =
916 interconnects
917
918
919
920
921
922 interconnect-n
923
924
925 power-domains
926 status = "disa
927 };
928
929 spi15: spi@884000 {
930 compatible = "
931 reg = <0x0 0x8
932 #address-cells
933 #size-cells =
934 interrupts = <
935 clocks = <&gcc
936 clock-names =
937 interconnects
938
939
940
941
942
943 interconnect-n
944
945
946 power-domains
947 status = "disa
948 };
949
950 i2c16: i2c@888000 {
951 compatible = "
952 reg = <0x0 0x8
953 #address-cells
954 #size-cells =
955 interrupts = <
956 clocks = <&gcc
957 clock-names =
958 interconnects
959
960
961
962
963
964 interconnect-n
965
966
967 power-domains
968 status = "disa
969 };
970
971 spi16: spi@888000 {
972 compatible = "
973 reg = <0x0 0x0
974 interrupts = <
975 clocks = <&gcc
976 clock-names =
977 interconnects
978
979
980
981
982
983 interconnect-n
984
985
986 power-domains
987 #address-cells
988 #size-cells =
989 status = "disa
990 };
991
992 i2c17: i2c@88c000 {
993 compatible = "
994 reg = <0x0 0x8
995 #address-cells
996 #size-cells =
997 interrupts = <
998 clocks = <&gcc
999 clock-names =
1000 interconnects
1001
1002
1003
1004
1005
1006 interconnect-
1007
1008
1009 power-domains
1010 status = "dis
1011 };
1012
1013 spi17: spi@88c000 {
1014 compatible =
1015 reg = <0x0 0x
1016 #address-cell
1017 #size-cells =
1018 interrupts =
1019 clocks = <&gc
1020 clock-names =
1021 interconnects
1022
1023
1024
1025
1026
1027 interconnect-
1028
1029
1030 power-domains
1031 status = "dis
1032 };
1033
1034 uart17: serial@88c000
1035 compatible =
1036 reg = <0x0 0x
1037 interrupts =
1038 clocks = <&gc
1039 clock-names =
1040 interconnects
1041
1042
1043
1044 interconnect-
1045 power-domains
1046 status = "dis
1047 };
1048
1049 i2c18: i2c@890000 {
1050 compatible =
1051 reg = <0x0 0x
1052 interrupts =
1053 clocks = <&gc
1054 clock-names =
1055 interconnects
1056
1057
1058
1059
1060
1061 interconnect-
1062
1063
1064 power-domains
1065 #address-cell
1066 #size-cells =
1067 status = "dis
1068 };
1069
1070 spi18: spi@890000 {
1071 compatible =
1072 reg = <0x0 0x
1073 #address-cell
1074 #size-cells =
1075 interrupts =
1076 clocks = <&gc
1077 clock-names =
1078 interconnects
1079
1080
1081
1082
1083
1084 interconnect-
1085
1086
1087 power-domains
1088 status = "dis
1089 };
1090
1091 i2c19: i2c@894000 {
1092 compatible =
1093 reg = <0x0 0x
1094 #address-cell
1095 #size-cells =
1096 interrupts =
1097 clocks = <&gc
1098 clock-names =
1099 interconnects
1100
1101
1102
1103
1104
1105 interconnect-
1106
1107
1108 power-domains
1109 status = "dis
1110 };
1111
1112 spi19: spi@894000 {
1113 compatible =
1114 reg = <0x0 0x
1115 #address-cell
1116 #size-cells =
1117 interrupts =
1118 clocks = <&gc
1119 clock-names =
1120 interconnects
1121
1122
1123
1124
1125
1126 interconnect-
1127
1128
1129 power-domains
1130 status = "dis
1131 };
1132
1133 i2c20: i2c@898000 {
1134 compatible =
1135 reg = <0x0 0x
1136 #address-cell
1137 #size-cells =
1138 interrupts =
1139 clocks = <&gc
1140 clock-names =
1141 interconnects
1142
1143
1144
1145
1146
1147 interconnect-
1148
1149
1150 power-domains
1151 status = "dis
1152 };
1153
1154 spi20: spi@898000 {
1155 compatible =
1156 reg = <0x0 0x
1157 #address-cell
1158 #size-cells =
1159 interrupts =
1160 clocks = <&gc
1161 clock-names =
1162 interconnects
1163
1164
1165
1166
1167
1168 interconnect-
1169
1170
1171 power-domains
1172 status = "dis
1173 };
1174 };
1175
1176 qupv3_id_0: geniqup@9c0000 {
1177 compatible = "qcom,ge
1178 reg = <0x0 0x9c0000 0
1179 #address-cells = <2>;
1180 #size-cells = <2>;
1181 ranges;
1182 clock-names = "m-ahb"
1183 clocks = <&gcc GCC_QU
1184 <&gcc GCC_QUP
1185 iommus = <&apps_smmu
1186 status = "disabled";
1187
1188 i2c0: i2c@980000 {
1189 compatible =
1190 reg = <0x0 0x
1191 #address-cell
1192 #size-cells =
1193 interrupts =
1194 clocks = <&gc
1195 clock-names =
1196 interconnects
1197
1198
1199
1200
1201
1202 interconnect-
1203
1204
1205 power-domains
1206 status = "dis
1207 };
1208
1209 spi0: spi@980000 {
1210 compatible =
1211 reg = <0x0 0x
1212 #address-cell
1213 #size-cells =
1214 interrupts =
1215 clocks = <&gc
1216 clock-names =
1217 interconnects
1218
1219
1220
1221
1222
1223 interconnect-
1224
1225
1226 power-domains
1227 status = "dis
1228 };
1229
1230 i2c1: i2c@984000 {
1231 compatible =
1232 reg = <0x0 0x
1233 #address-cell
1234 #size-cells =
1235 interrupts =
1236 clocks = <&gc
1237 clock-names =
1238 interconnects
1239
1240
1241
1242
1243
1244 interconnect-
1245
1246
1247 power-domains
1248 status = "dis
1249 };
1250
1251 spi1: spi@984000 {
1252 compatible =
1253 reg = <0x0 0x
1254 #address-cell
1255 #size-cells =
1256 interrupts =
1257 clocks = <&gc
1258 clock-names =
1259 interconnects
1260
1261
1262
1263
1264
1265 interconnect-
1266
1267
1268 power-domains
1269 status = "dis
1270 };
1271
1272 i2c2: i2c@988000 {
1273 compatible =
1274 reg = <0x0 0x
1275 #address-cell
1276 #size-cells =
1277 interrupts =
1278 clocks = <&gc
1279 clock-names =
1280 interconnects
1281
1282
1283
1284
1285
1286 interconnect-
1287
1288
1289 power-domains
1290 status = "dis
1291 };
1292
1293 spi2: spi@988000 {
1294 compatible =
1295 reg = <0x0 0x
1296 #address-cell
1297 #size-cells =
1298 interrupts =
1299 clocks = <&gc
1300 clock-names =
1301 interconnects
1302
1303
1304
1305
1306
1307 interconnect-
1308
1309
1310 power-domains
1311 status = "dis
1312 };
1313
1314 i2c3: i2c@98c000 {
1315 compatible =
1316 reg = <0x0 0x
1317 #address-cell
1318 #size-cells =
1319 interrupts =
1320 clocks = <&gc
1321 clock-names =
1322 interconnects
1323
1324
1325
1326
1327
1328 interconnect-
1329
1330
1331 power-domains
1332 status = "dis
1333 };
1334
1335 spi3: spi@98c000 {
1336 compatible =
1337 reg = <0x0 0x
1338 #address-cell
1339 #size-cells =
1340 interrupts =
1341 clocks = <&gc
1342 clock-names =
1343 interconnects
1344
1345
1346
1347
1348
1349 interconnect-
1350
1351
1352 power-domains
1353 status = "dis
1354 };
1355
1356 i2c4: i2c@990000 {
1357 compatible =
1358 reg = <0x0 0x
1359 #address-cell
1360 #size-cells =
1361 interrupts =
1362 clocks = <&gc
1363 clock-names =
1364 interconnects
1365
1366
1367
1368
1369
1370 interconnect-
1371
1372
1373 power-domains
1374 status = "dis
1375 };
1376
1377 spi4: spi@990000 {
1378 compatible =
1379 reg = <0x0 0x
1380 #address-cell
1381 #size-cells =
1382 interrupts =
1383 clocks = <&gc
1384 clock-names =
1385 interconnects
1386
1387
1388
1389
1390
1391 interconnect-
1392
1393
1394 power-domains
1395 status = "dis
1396 };
1397
1398 i2c5: i2c@994000 {
1399 compatible =
1400 reg = <0x0 0x
1401 #address-cell
1402 #size-cells =
1403 interrupts =
1404 clocks = <&gc
1405 clock-names =
1406 interconnects
1407
1408
1409
1410
1411
1412 interconnect-
1413
1414
1415 power-domains
1416 status = "dis
1417 };
1418
1419 spi5: spi@994000 {
1420 compatible =
1421 reg = <0x0 0x
1422 #address-cell
1423 #size-cells =
1424 interrupts =
1425 clocks = <&gc
1426 clock-names =
1427 interconnects
1428
1429
1430
1431
1432
1433 interconnect-
1434
1435
1436 power-domains
1437 status = "dis
1438 };
1439
1440 uart5: serial@994000
1441 compatible =
1442 reg = <0x0 0x
1443 interrupts =
1444 clocks = <&gc
1445 clock-names =
1446 interconnects
1447
1448
1449
1450 interconnect-
1451 power-domains
1452 status = "dis
1453 };
1454 };
1455
1456 qupv3_id_1: geniqup@ac0000 {
1457 compatible = "qcom,ge
1458 reg = <0x0 0x00ac0000
1459 #address-cells = <2>;
1460 #size-cells = <2>;
1461 ranges;
1462 clock-names = "m-ahb"
1463 clocks = <&gcc GCC_QU
1464 <&gcc GCC_QU
1465 iommus = <&apps_smmu
1466 status = "disabled";
1467
1468 i2c7: i2c@a80000 {
1469 compatible =
1470 reg = <0x0 0x
1471 #address-cell
1472 #size-cells =
1473 interrupts =
1474 clocks = <&gc
1475 clock-names =
1476 interconnects
1477
1478
1479
1480
1481
1482 interconnect-
1483
1484
1485 power-domains
1486 status = "dis
1487 };
1488
1489 spi7: spi@a80000 {
1490 compatible =
1491 reg = <0x0 0x
1492 #address-cell
1493 #size-cells =
1494 interrupts =
1495 clocks = <&gc
1496 clock-names =
1497 interconnects
1498
1499
1500
1501
1502
1503 interconnect-
1504
1505
1506 power-domains
1507 status = "dis
1508 };
1509
1510 i2c8: i2c@a84000 {
1511 compatible =
1512 reg = <0x0 0x
1513 #address-cell
1514 #size-cells =
1515 interrupts =
1516 clocks = <&gc
1517 clock-names =
1518 interconnects
1519
1520
1521
1522
1523
1524 interconnect-
1525
1526
1527 power-domains
1528 status = "dis
1529 };
1530
1531 spi8: spi@a84000 {
1532 compatible =
1533 reg = <0x0 0x
1534 #address-cell
1535 #size-cells =
1536 interrupts =
1537 clocks = <&gc
1538 clock-names =
1539 interconnects
1540
1541
1542
1543
1544
1545 interconnect-
1546
1547
1548 power-domains
1549 status = "dis
1550 };
1551
1552 i2c9: i2c@a88000 {
1553 compatible =
1554 reg = <0x0 0x
1555 #address-cell
1556 #size-cells =
1557 interrupts =
1558 clocks = <&gc
1559 clock-names =
1560 interconnects
1561
1562
1563
1564
1565
1566 interconnect-
1567
1568
1569 power-domains
1570 status = "dis
1571 };
1572
1573 spi9: spi@a88000 {
1574 compatible =
1575 reg = <0x0 0x
1576 #address-cell
1577 #size-cells =
1578 interrupts =
1579 clocks = <&gc
1580 clock-names =
1581 interconnects
1582
1583
1584
1585
1586
1587 interconnect-
1588
1589
1590 power-domains
1591 status = "dis
1592 };
1593
1594 uart9: serial@a88000
1595 compatible =
1596 reg = <0x0 0x
1597 interrupts =
1598 clocks = <&gc
1599 clock-names =
1600 interconnects
1601
1602
1603
1604 interconnect-
1605 power-domains
1606 status = "dis
1607 };
1608
1609 i2c10: i2c@a8c000 {
1610 compatible =
1611 reg = <0x0 0x
1612 #address-cell
1613 #size-cells =
1614 interrupts =
1615 clocks = <&gc
1616 clock-names =
1617 interconnects
1618
1619
1620
1621
1622
1623 interconnect-
1624
1625
1626 power-domains
1627 status = "dis
1628 };
1629
1630 spi10: spi@a8c000 {
1631 compatible =
1632 reg = <0x0 0x
1633 #address-cell
1634 #size-cells =
1635 interrupts =
1636 clocks = <&gc
1637 clock-names =
1638 interconnects
1639
1640
1641
1642
1643
1644 interconnect-
1645
1646
1647 power-domains
1648 status = "dis
1649 };
1650
1651 uart10: serial@a8c000
1652 compatible =
1653 reg = <0x0 0x
1654 interrupts =
1655 clock-names =
1656 clocks = <&gc
1657 interconnect-
1658 interconnects
1659
1660
1661
1662 power-domains
1663 operating-poi
1664 status = "dis
1665 };
1666
1667 i2c11: i2c@a90000 {
1668 compatible =
1669 reg = <0x0 0x
1670 #address-cell
1671 #size-cells =
1672 interrupts =
1673 clocks = <&gc
1674 clock-names =
1675 interconnects
1676
1677
1678
1679
1680
1681 interconnect-
1682
1683
1684 power-domains
1685 status = "dis
1686 };
1687
1688 spi11: spi@a90000 {
1689 compatible =
1690 reg = <0x0 0x
1691 #address-cell
1692 #size-cells =
1693 interrupts =
1694 clocks = <&gc
1695 clock-names =
1696 interconnects
1697
1698
1699
1700
1701
1702 interconnect-
1703
1704
1705 power-domains
1706 status = "dis
1707 };
1708
1709 i2c12: i2c@a94000 {
1710 compatible =
1711 reg = <0x0 0x
1712 #address-cell
1713 #size-cells =
1714 interrupts =
1715 clocks = <&gc
1716 clock-names =
1717 interconnects
1718
1719
1720
1721
1722
1723 interconnect-
1724
1725
1726 power-domains
1727 status = "dis
1728 };
1729
1730 spi12: spi@a94000 {
1731 compatible =
1732 reg = <0x0 0x
1733 #address-cell
1734 #size-cells =
1735 interrupts =
1736 clocks = <&gc
1737 clock-names =
1738 interconnects
1739
1740
1741
1742
1743
1744 interconnect-
1745
1746
1747 power-domains
1748 status = "dis
1749 };
1750
1751 uart12: serial@a94000
1752 compatible =
1753 reg = <0x0 0x
1754 interrupts =
1755 clocks = <&gc
1756 clock-names =
1757 interconnects
1758
1759
1760
1761 interconnect-
1762 power-domains
1763 status = "dis
1764 };
1765
1766 i2c13: i2c@a98000 {
1767 compatible =
1768 reg = <0x0 0x
1769 #address-cell
1770 #size-cells =
1771 interrupts =
1772 clocks = <&gc
1773 clock-names =
1774 interconnects
1775
1776
1777
1778
1779
1780 interconnect-
1781
1782
1783 power-domains
1784 status = "dis
1785 };
1786 };
1787
1788 qupv3_id_3: geniqup@bc0000 {
1789 compatible = "qcom,ge
1790 reg = <0x0 0xbc0000 0
1791 #address-cells = <2>;
1792 #size-cells = <2>;
1793 ranges;
1794 clock-names = "m-ahb"
1795 clocks = <&gcc GCC_QU
1796 <&gcc GCC_QUP
1797 iommus = <&apps_smmu
1798 status = "disabled";
1799
1800 i2c21: i2c@b80000 {
1801 compatible =
1802 reg = <0x0 0x
1803 #address-cell
1804 #size-cells =
1805 interrupts =
1806 clocks = <&gc
1807 clock-names =
1808 interconnects
1809
1810 <&
1811
1812 <&
1813
1814 interconnect-
1815
1816
1817 power-domains
1818 status = "dis
1819 };
1820
1821 spi21: spi@b80000 {
1822 compatible =
1823 reg = <0x0 0x
1824 #address-cell
1825 #size-cells =
1826 interrupts =
1827 clocks = <&gc
1828 clock-names =
1829 interconnects
1830
1831 <&
1832
1833 <&
1834
1835 interconnect-
1836
1837
1838 power-domains
1839 status = "dis
1840 };
1841 };
1842
1843 rng: rng@10d2000 {
1844 compatible = "qcom,sa
1845 reg = <0 0x010d2000 0
1846 };
1847
1848 ufs_mem_hc: ufs@1d84000 {
1849 compatible = "qcom,sa
1850 reg = <0x0 0x01d84000
1851 interrupts = <GIC_SPI
1852 phys = <&ufs_mem_phy>
1853 phy-names = "ufsphy";
1854 lanes-per-direction =
1855 #reset-cells = <1>;
1856 resets = <&gcc GCC_UF
1857 reset-names = "rst";
1858 power-domains = <&gcc
1859 required-opps = <&rpm
1860 iommus = <&apps_smmu
1861 dma-coherent;
1862 clocks = <&gcc GCC_UF
1863 <&gcc GCC_AG
1864 <&gcc GCC_UF
1865 <&gcc GCC_UF
1866 <&rpmhcc RPM
1867 <&gcc GCC_UF
1868 <&gcc GCC_UF
1869 <&gcc GCC_UF
1870 clock-names = "core_c
1871 "bus_ag
1872 "iface_
1873 "core_c
1874 "ref_cl
1875 "tx_lan
1876 "rx_lan
1877 "rx_lan
1878 freq-table-hz = <7500
1879 <0 0>
1880 <0 0>
1881 <7500
1882 <0 0>
1883 <0 0>
1884 <0 0>
1885 <0 0>
1886 qcom,ice = <&ice>;
1887 status = "disabled";
1888 };
1889
1890 ufs_mem_phy: phy@1d87000 {
1891 compatible = "qcom,sa
1892 reg = <0x0 0x01d87000
1893 /*
1894 * Yes, GCC_EDP_REF_C
1895 * enables the CXO cl
1896 */
1897 clocks = <&rpmhcc RPM
1898 <&gcc GCC_UF
1899 <&gcc GCC_ED
1900 clock-names = "ref",
1901 power-domains = <&gcc
1902 resets = <&ufs_mem_hc
1903 reset-names = "ufsphy
1904 #phy-cells = <0>;
1905 status = "disabled";
1906 };
1907
1908 ice: crypto@1d88000 {
1909 compatible = "qcom,sa
1910 "qcom,in
1911 reg = <0x0 0x01d88000
1912 clocks = <&gcc GCC_UF
1913 };
1914
1915 stm: stm@4002000 {
1916 compatible = "arm,cor
1917 reg = <0x0 0x4002000
1918 <0x0 0x1628
1919 reg-names = "stm-base
1920
1921 clocks = <&aoss_qmp>;
1922 clock-names = "apb_pc
1923
1924 out-ports {
1925 port {
1926 stm_o
1927
1928
1929 };
1930 };
1931 };
1932 };
1933
1934 tpdm@4003000 {
1935 compatible = "qcom,co
1936 reg = <0x0 0x4003000
1937
1938 clocks = <&aoss_qmp>;
1939 clock-names = "apb_pc
1940
1941 qcom,cmb-element-bits
1942 qcom,cmb-msrs-num = <
1943
1944 out-ports {
1945 port {
1946 qdss_
1947
1948
1949 };
1950 };
1951 };
1952 };
1953
1954 tpda@4004000 {
1955 compatible = "qcom,co
1956 reg = <0x0 0x4004000
1957
1958 clocks = <&aoss_qmp>;
1959 clock-names = "apb_pc
1960
1961 out-ports {
1962 port {
1963 qdss_
1964
1965
1966 };
1967 };
1968 };
1969
1970 in-ports {
1971 #address-cell
1972 #size-cells =
1973
1974 port@0 {
1975 reg =
1976 qdss_
1977
1978
1979 };
1980 };
1981
1982 port@1 {
1983 reg =
1984 qdss_
1985
1986
1987 };
1988 };
1989 };
1990 };
1991
1992 tpdm@400f000 {
1993 compatible = "qcom,co
1994 reg = <0x0 0x400f000
1995
1996 clocks = <&aoss_qmp>;
1997 clock-names = "apb_pc
1998
1999 qcom,cmb-element-bits
2000 qcom,cmb-msrs-num = <
2001
2002 out-ports {
2003 port {
2004 qdss_
2005
2006
2007 };
2008 };
2009 };
2010 };
2011
2012 funnel@4041000 {
2013 compatible = "arm,cor
2014 reg = <0x0 0x4041000
2015
2016 clocks = <&aoss_qmp>;
2017 clock-names = "apb_pc
2018
2019 out-ports {
2020 port {
2021 funne
2022
2023
2024 };
2025 };
2026 };
2027
2028 in-ports {
2029 #address-cell
2030 #size-cells =
2031
2032 port@6 {
2033 reg =
2034 funne
2035
2036
2037 };
2038 };
2039
2040 port@7 {
2041 reg =
2042 funne
2043
2044
2045 };
2046 };
2047 };
2048 };
2049
2050 funnel@4042000 {
2051 compatible = "arm,cor
2052 reg = <0x0 0x4042000
2053
2054 clocks = <&aoss_qmp>;
2055 clock-names = "apb_pc
2056
2057 out-ports {
2058 port {
2059 funne
2060
2061
2062 };
2063 };
2064 };
2065
2066 in-ports {
2067 #address-cell
2068 #size-cells =
2069
2070 port@4 {
2071 reg =
2072 funne
2073
2074
2075 };
2076 };
2077 };
2078 };
2079
2080 funnel@4045000 {
2081 compatible = "arm,cor
2082 reg = <0x0 0x4045000
2083
2084 clocks = <&aoss_qmp>;
2085 clock-names = "apb_pc
2086
2087 out-ports {
2088 port {
2089 qdss_
2090
2091
2092 };
2093 };
2094 };
2095
2096 in-ports {
2097 #address-cell
2098 #size-cells =
2099
2100 port@0 {
2101 reg =
2102 qdss_
2103
2104
2105 };
2106 };
2107
2108 port@1 {
2109 reg =
2110 qdss_
2111
2112
2113 };
2114 };
2115 };
2116 };
2117
2118 funnel@4b04000 {
2119 compatible = "arm,cor
2120 reg = <0x0 0x4b04000
2121
2122 clocks = <&aoss_qmp>;
2123 clock-names = "apb_pc
2124
2125 out-ports {
2126 port {
2127 aoss_
2128
2129
2130 };
2131 };
2132 };
2133
2134 in-ports {
2135 #address-cell
2136 #size-cells =
2137
2138 port@6 {
2139 reg =
2140 aoss_
2141
2142
2143 };
2144 };
2145
2146 port@7 {
2147 reg =
2148 aoss_
2149
2150
2151 };
2152 };
2153 };
2154 };
2155
2156 tmc_etf: tmc@4b05000 {
2157 compatible = "arm,cor
2158 reg = <0x0 0x4b05000
2159
2160 clocks = <&aoss_qmp>;
2161 clock-names = "apb_pc
2162
2163 out-ports {
2164 port {
2165 etf0_
2166
2167
2168 };
2169 };
2170 };
2171
2172 in-ports {
2173 port {
2174 etf0_
2175
2176
2177 };
2178 };
2179 };
2180 };
2181
2182 replicator@4b06000 {
2183 compatible = "arm,cor
2184 reg = <0x0 0x4b06000
2185
2186 clocks = <&aoss_qmp>;
2187 clock-names = "apb_pc
2188
2189 out-ports {
2190 #address-cell
2191 #size-cells =
2192
2193 port@1 {
2194 reg =
2195 swao_
2196
2197
2198 };
2199 };
2200 };
2201
2202 in-ports {
2203 port {
2204 swao_
2205
2206
2207 };
2208 };
2209 };
2210 };
2211
2212 tpda@4b08000 {
2213 compatible = "qcom,co
2214 reg = <0x0 0x4b08000
2215
2216 clocks = <&aoss_qmp>;
2217 clock-names = "apb_pc
2218
2219 out-ports {
2220 port {
2221 aoss_
2222
2223
2224 };
2225 };
2226 };
2227
2228 in-ports {
2229 #address-cell
2230 #size-cells =
2231
2232 port@0 {
2233 reg =
2234 aoss_
2235
2236
2237 };
2238 };
2239
2240 port@1 {
2241 reg =
2242 aoss_
2243
2244
2245 };
2246 };
2247
2248 port@2 {
2249 reg =
2250 aoss_
2251
2252
2253 };
2254 };
2255
2256 port@3 {
2257 reg =
2258 aoss_
2259
2260
2261 };
2262 };
2263
2264 port@4 {
2265 reg =
2266 aoss_
2267
2268
2269 };
2270 };
2271 };
2272 };
2273
2274 tpdm@4b09000 {
2275 compatible = "qcom,co
2276 reg = <0x0 0x4b09000
2277
2278 clocks = <&aoss_qmp>;
2279 clock-names = "apb_pc
2280
2281 qcom,cmb-element-bits
2282 qcom,cmb-msrs-num = <
2283
2284 out-ports {
2285 port {
2286 aoss_
2287
2288
2289 };
2290 };
2291 };
2292 };
2293
2294 tpdm@4b0a000 {
2295 compatible = "qcom,co
2296 reg = <0x0 0x4b0a000
2297
2298 clocks = <&aoss_qmp>;
2299 clock-names = "apb_pc
2300
2301 qcom,cmb-element-bits
2302 qcom,cmb-msrs-num = <
2303
2304 out-ports {
2305 port {
2306 aoss_
2307
2308
2309 };
2310 };
2311 };
2312 };
2313
2314 tpdm@4b0b000 {
2315 compatible = "qcom,co
2316 reg = <0x0 0x4b0b000
2317
2318 clocks = <&aoss_qmp>;
2319 clock-names = "apb_pc
2320
2321 qcom,cmb-element-bits
2322 qcom,cmb-msrs-num = <
2323
2324 out-ports {
2325 port {
2326 aoss_
2327
2328
2329 };
2330 };
2331 };
2332 };
2333
2334 tpdm@4b0c000 {
2335 compatible = "qcom,co
2336 reg = <0x0 0x4b0c000
2337
2338 clocks = <&aoss_qmp>;
2339 clock-names = "apb_pc
2340
2341 qcom,cmb-element-bits
2342 qcom,cmb-msrs-num = <
2343
2344 out-ports {
2345 port {
2346 aoss_
2347
2348
2349 };
2350 };
2351 };
2352 };
2353
2354 tpdm@4b0d000 {
2355 compatible = "qcom,co
2356 reg = <0x0 0x4b0d000
2357
2358 clocks = <&aoss_qmp>;
2359 clock-names = "apb_pc
2360
2361 qcom,dsb-element-bits
2362 qcom,dsb-msrs-num = <
2363
2364 out-ports {
2365 port {
2366 aoss_
2367
2368
2369 };
2370 };
2371 };
2372 };
2373
2374 aoss_cti: cti@4b13000 {
2375 compatible = "arm,cor
2376 reg = <0x0 0x4b13000
2377
2378 clocks = <&aoss_qmp>;
2379 clock-names = "apb_pc
2380 };
2381
2382 etm@6040000 {
2383 compatible = "arm,pri
2384 reg = <0x0 0x6040000
2385 cpu = <&CPU0>;
2386
2387 clocks = <&aoss_qmp>;
2388 clock-names = "apb_pc
2389 arm,coresight-loses-c
2390 qcom,skip-power-up;
2391
2392 out-ports {
2393 port {
2394 etm0_
2395
2396
2397 };
2398 };
2399 };
2400 };
2401
2402 etm@6140000 {
2403 compatible = "arm,pri
2404 reg = <0x0 0x6140000
2405 cpu = <&CPU1>;
2406
2407 clocks = <&aoss_qmp>;
2408 clock-names = "apb_pc
2409 arm,coresight-loses-c
2410 qcom,skip-power-up;
2411
2412 out-ports {
2413 port {
2414 etm1_
2415
2416
2417 };
2418 };
2419 };
2420 };
2421
2422 etm@6240000 {
2423 compatible = "arm,pri
2424 reg = <0x0 0x6240000
2425 cpu = <&CPU2>;
2426
2427 clocks = <&aoss_qmp>;
2428 clock-names = "apb_pc
2429 arm,coresight-loses-c
2430 qcom,skip-power-up;
2431
2432 out-ports {
2433 port {
2434 etm2_
2435
2436
2437 };
2438 };
2439 };
2440 };
2441
2442 etm@6340000 {
2443 compatible = "arm,pri
2444 reg = <0x0 0x6340000
2445 cpu = <&CPU3>;
2446
2447 clocks = <&aoss_qmp>;
2448 clock-names = "apb_pc
2449 arm,coresight-loses-c
2450 qcom,skip-power-up;
2451
2452 out-ports {
2453 port {
2454 etm3_
2455
2456
2457 };
2458 };
2459 };
2460 };
2461
2462 etm@6440000 {
2463 compatible = "arm,pri
2464 reg = <0x0 0x6440000
2465 cpu = <&CPU4>;
2466
2467 clocks = <&aoss_qmp>;
2468 clock-names = "apb_pc
2469 arm,coresight-loses-c
2470 qcom,skip-power-up;
2471
2472 out-ports {
2473 port {
2474 etm4_
2475
2476
2477 };
2478 };
2479 };
2480 };
2481
2482 etm@6540000 {
2483 compatible = "arm,pri
2484 reg = <0x0 0x6540000
2485 cpu = <&CPU5>;
2486
2487 clocks = <&aoss_qmp>;
2488 clock-names = "apb_pc
2489 arm,coresight-loses-c
2490 qcom,skip-power-up;
2491
2492 out-ports {
2493 port {
2494 etm5_
2495
2496
2497 };
2498 };
2499 };
2500 };
2501
2502 etm@6640000 {
2503 compatible = "arm,pri
2504 reg = <0x0 0x6640000
2505 cpu = <&CPU6>;
2506
2507 clocks = <&aoss_qmp>;
2508 clock-names = "apb_pc
2509 arm,coresight-loses-c
2510 qcom,skip-power-up;
2511
2512 out-ports {
2513 port {
2514 etm6_
2515
2516
2517 };
2518 };
2519 };
2520 };
2521
2522 etm@6740000 {
2523 compatible = "arm,pri
2524 reg = <0x0 0x6740000
2525 cpu = <&CPU7>;
2526
2527 clocks = <&aoss_qmp>;
2528 clock-names = "apb_pc
2529 arm,coresight-loses-c
2530 qcom,skip-power-up;
2531
2532 out-ports {
2533 port {
2534 etm7_
2535
2536
2537 };
2538 };
2539 };
2540 };
2541
2542 funnel@6800000 {
2543 compatible = "arm,cor
2544 reg = <0x0 0x6800000
2545
2546 clocks = <&aoss_qmp>;
2547 clock-names = "apb_pc
2548
2549 out-ports {
2550 port {
2551 apss_
2552
2553
2554 };
2555 };
2556 };
2557
2558 in-ports {
2559 #address-cell
2560 #size-cells =
2561
2562 port@0 {
2563 reg =
2564 apss_
2565
2566
2567 };
2568 };
2569
2570 port@1 {
2571 reg =
2572 apss_
2573
2574
2575 };
2576 };
2577
2578 port@2 {
2579 reg =
2580 apss_
2581
2582
2583 };
2584 };
2585
2586 port@3 {
2587 reg =
2588 apss_
2589
2590
2591 };
2592 };
2593
2594 port@4 {
2595 reg =
2596 apss_
2597
2598
2599 };
2600 };
2601
2602 port@5 {
2603 reg =
2604 apss_
2605
2606
2607 };
2608 };
2609
2610 port@6 {
2611 reg =
2612 apss_
2613
2614
2615 };
2616 };
2617
2618 port@7 {
2619 reg =
2620 apss_
2621
2622
2623 };
2624 };
2625 };
2626 };
2627
2628 funnel@6810000 {
2629 compatible = "arm,cor
2630 reg = <0x0 0x6810000
2631
2632 clocks = <&aoss_qmp>;
2633 clock-names = "apb_pc
2634
2635 out-ports {
2636 port {
2637 apss_
2638
2639
2640 };
2641 };
2642 };
2643
2644 in-ports {
2645 #address-cell
2646 #size-cells =
2647
2648 port@0 {
2649 reg =
2650 apss_
2651
2652
2653 };
2654 };
2655
2656 port@3 {
2657 reg =
2658 apss_
2659
2660
2661 };
2662 };
2663 };
2664 };
2665
2666 tpdm@6860000 {
2667 compatible = "qcom,co
2668 reg = <0x0 0x6860000
2669
2670 clocks = <&aoss_qmp>;
2671 clock-names = "apb_pc
2672
2673 qcom,cmb-element-bits
2674 qcom,cmb-msrs-num = <
2675
2676 out-ports {
2677 port {
2678 apss_
2679
2680
2681 };
2682 };
2683 };
2684 };
2685
2686 tpdm@6861000 {
2687 compatible = "qcom,co
2688 reg = <0x0 0x6861000
2689
2690 clocks = <&aoss_qmp>;
2691 clock-names = "apb_pc
2692
2693 qcom,dsb-element-bits
2694 qcom,dsb-msrs-num = <
2695
2696 out-ports {
2697 port {
2698 apss_
2699
2700
2701 };
2702 };
2703 };
2704 };
2705
2706 tpda@6863000 {
2707 compatible = "qcom,co
2708 reg = <0x0 0x6863000
2709
2710 clocks = <&aoss_qmp>;
2711 clock-names = "apb_pc
2712
2713 out-ports {
2714 port {
2715 apss_
2716
2717
2718 };
2719 };
2720 };
2721
2722 in-ports {
2723 #address-cell
2724 #size-cells =
2725
2726 port@0 {
2727 reg =
2728 apss_
2729
2730
2731 };
2732 };
2733
2734 port@1 {
2735 reg =
2736 apss_
2737
2738
2739 };
2740 };
2741
2742 port@2 {
2743 reg =
2744 apss_
2745
2746
2747 };
2748 };
2749
2750 port@3 {
2751 reg =
2752 apss_
2753
2754
2755 };
2756 };
2757
2758 port@4 {
2759 reg =
2760 apss_
2761
2762
2763 };
2764 };
2765 };
2766 };
2767
2768 tpdm@68a0000 {
2769 compatible = "qcom,co
2770 reg = <0x0 0x68a0000
2771
2772 clocks = <&aoss_qmp>;
2773 clock-names = "apb_pc
2774
2775 qcom,cmb-element-bits
2776 qcom,cmb-msrs-num = <
2777
2778 out-ports {
2779 port {
2780 apss_
2781
2782
2783 };
2784 };
2785 };
2786 };
2787
2788 tpdm@68b0000 {
2789 compatible = "qcom,co
2790 reg = <0x0 0x68b0000
2791
2792 clocks = <&aoss_qmp>;
2793 clock-names = "apb_pc
2794
2795 qcom,cmb-element-bits
2796 qcom,cmb-msrs-num = <
2797
2798 out-ports {
2799 port {
2800 apss_
2801
2802
2803 };
2804 };
2805 };
2806 };
2807
2808 tpdm@68c0000 {
2809 compatible = "qcom,co
2810 reg = <0x0 0x68c0000
2811
2812 clocks = <&aoss_qmp>;
2813 clock-names = "apb_pc
2814
2815 qcom,dsb-element-bits
2816 qcom,dsb-msrs-num = <
2817
2818 out-ports {
2819 port {
2820 apss_
2821
2822
2823 };
2824 };
2825 };
2826 };
2827
2828 usb_0_hsphy: phy@88e4000 {
2829 compatible = "qcom,sa
2830 "qcom,us
2831 reg = <0 0x088e4000 0
2832 clocks = <&rpmhcc RPM
2833 clock-names = "ref";
2834 resets = <&gcc GCC_US
2835
2836 #phy-cells = <0>;
2837
2838 status = "disabled";
2839 };
2840
2841 usb_0_qmpphy: phy@88e8000 {
2842 compatible = "qcom,sa
2843 reg = <0 0x088e8000 0
2844
2845 clocks = <&gcc GCC_US
2846 <&gcc GCC_US
2847 <&gcc GCC_US
2848 <&gcc GCC_US
2849 clock-names = "aux",
2850
2851 resets = <&gcc GCC_US
2852 <&gcc GCC_US
2853 reset-names = "phy",
2854
2855 power-domains = <&gcc
2856
2857 #clock-cells = <0>;
2858 clock-output-names =
2859
2860 #phy-cells = <0>;
2861
2862 status = "disabled";
2863 };
2864
2865 usb_0: usb@a6f8800 {
2866 compatible = "qcom,sa
2867 reg = <0 0x0a6f8800 0
2868 #address-cells = <2>;
2869 #size-cells = <2>;
2870 ranges;
2871
2872 clocks = <&gcc GCC_CF
2873 <&gcc GCC_US
2874 <&gcc GCC_AG
2875 <&gcc GCC_US
2876 <&gcc GCC_US
2877 clock-names = "cfg_no
2878
2879 assigned-clocks = <&g
2880 <&g
2881 assigned-clock-rates
2882
2883 interrupts-extended =
2884
2885
2886
2887
2888 interrupt-names = "pw
2889 "hs
2890 "dp
2891 "dm
2892 "ss
2893
2894 power-domains = <&gcc
2895 required-opps = <&rpm
2896
2897 resets = <&gcc GCC_US
2898
2899 interconnects = <&agg
2900 <&gem
2901 interconnect-names =
2902
2903 wakeup-source;
2904
2905 status = "disabled";
2906
2907 usb_0_dwc3: usb@a6000
2908 compatible =
2909 reg = <0 0x0a
2910 interrupts =
2911 iommus = <&ap
2912 phys = <&usb_
2913 phy-names = "
2914 };
2915 };
2916
2917 usb_1_hsphy: phy@88e6000 {
2918 compatible = "qcom,sa
2919 "qcom,us
2920 reg = <0 0x088e6000 0
2921 clocks = <&gcc GCC_US
2922 clock-names = "ref";
2923 resets = <&gcc GCC_US
2924
2925 #phy-cells = <0>;
2926
2927 status = "disabled";
2928 };
2929
2930 usb_1_qmpphy: phy@88ea000 {
2931 compatible = "qcom,sa
2932 reg = <0 0x088ea000 0
2933
2934 clocks = <&gcc GCC_US
2935 <&gcc GCC_US
2936 <&gcc GCC_US
2937 <&gcc GCC_US
2938 clock-names = "aux",
2939
2940 resets = <&gcc GCC_US
2941 <&gcc GCC_US
2942 reset-names = "phy",
2943
2944 power-domains = <&gcc
2945
2946 #clock-cells = <0>;
2947 clock-output-names =
2948
2949 #phy-cells = <0>;
2950
2951 status = "disabled";
2952 };
2953
2954 usb_1: usb@a8f8800 {
2955 compatible = "qcom,sa
2956 reg = <0 0x0a8f8800 0
2957 #address-cells = <2>;
2958 #size-cells = <2>;
2959 ranges;
2960
2961 clocks = <&gcc GCC_CF
2962 <&gcc GCC_US
2963 <&gcc GCC_AG
2964 <&gcc GCC_US
2965 <&gcc GCC_US
2966 clock-names = "cfg_no
2967
2968 assigned-clocks = <&g
2969 <&g
2970 assigned-clock-rates
2971
2972 interrupts-extended =
2973
2974
2975
2976
2977 interrupt-names = "pw
2978 "hs
2979 "dp
2980 "dm
2981 "ss
2982
2983 power-domains = <&gcc
2984 required-opps = <&rpm
2985
2986 resets = <&gcc GCC_US
2987
2988 interconnects = <&agg
2989 <&gem
2990 interconnect-names =
2991
2992 wakeup-source;
2993
2994 status = "disabled";
2995
2996 usb_1_dwc3: usb@a8000
2997 compatible =
2998 reg = <0 0x0a
2999 interrupts =
3000 iommus = <&ap
3001 phys = <&usb_
3002 phy-names = "
3003 };
3004 };
3005
3006 usb_2_hsphy: phy@88e7000 {
3007 compatible = "qcom,sa
3008 "qcom,us
3009 reg = <0 0x088e7000 0
3010 clocks = <&gcc GCC_US
3011 clock-names = "ref";
3012 resets = <&gcc GCC_US
3013
3014 #phy-cells = <0>;
3015
3016 status = "disabled";
3017 };
3018
3019 usb_2: usb@a4f8800 {
3020 compatible = "qcom,sa
3021 reg = <0 0x0a4f8800 0
3022 #address-cells = <2>;
3023 #size-cells = <2>;
3024 ranges;
3025
3026 clocks = <&gcc GCC_CF
3027 <&gcc GCC_US
3028 <&gcc GCC_AG
3029 <&gcc GCC_US
3030 <&gcc GCC_US
3031 clock-names = "cfg_no
3032
3033 assigned-clocks = <&g
3034 <&g
3035 assigned-clock-rates
3036
3037 interrupts-extended =
3038
3039
3040
3041 interrupt-names = "pw
3042 "hs
3043 "dp
3044 "dm
3045
3046 power-domains = <&gcc
3047 required-opps = <&rpm
3048
3049 resets = <&gcc GCC_US
3050
3051 interconnects = <&agg
3052 <&gem
3053 interconnect-names =
3054
3055 wakeup-source;
3056
3057 status = "disabled";
3058
3059 usb_2_dwc3: usb@a4000
3060 compatible =
3061 reg = <0 0x0a
3062 interrupts =
3063 iommus = <&ap
3064 phys = <&usb_
3065 phy-names = "
3066 };
3067 };
3068
3069 tcsr_mutex: hwlock@1f40000 {
3070 compatible = "qcom,tc
3071 reg = <0x0 0x01f40000
3072 #hwlock-cells = <1>;
3073 };
3074
3075 gpucc: clock-controller@3d900
3076 compatible = "qcom,sa
3077 reg = <0x0 0x03d90000
3078 clocks = <&rpmhcc RPM
3079 <&gcc GCC_GP
3080 <&gcc GCC_GP
3081 clock-names = "bi_tcx
3082 "gcc_gp
3083 "gcc_gp
3084 #clock-cells = <1>;
3085 #reset-cells = <1>;
3086 #power-domain-cells =
3087 };
3088
3089 adreno_smmu: iommu@3da0000 {
3090 compatible = "qcom,sa
3091 "qcom,sm
3092 reg = <0x0 0x03da0000
3093 #iommu-cells = <2>;
3094 #global-interrupts =
3095 dma-coherent;
3096 power-domains = <&gpu
3097 clocks = <&gcc GCC_GP
3098 <&gcc GCC_GP
3099 <&gpucc GPU_
3100 <&gpucc GPU_
3101 <&gpucc GPU_
3102 <&gpucc GPU_
3103 <&gpucc GPU_
3104 clock-names = "gcc_gp
3105 "gcc_gp
3106 "gpu_cc
3107 "gpu_cc
3108 "gpu_cc
3109 "gpu_cc
3110 "gpu_cc
3111 interrupts = <GIC_SPI
3112 <GIC_SPI
3113 <GIC_SPI
3114 <GIC_SPI
3115 <GIC_SPI
3116 <GIC_SPI
3117 <GIC_SPI
3118 <GIC_SPI
3119 <GIC_SPI
3120 <GIC_SPI
3121 <GIC_SPI
3122 <GIC_SPI
3123 };
3124
3125 serdes0: phy@8901000 {
3126 compatible = "qcom,sa
3127 reg = <0x0 0x08901000
3128 clocks = <&gcc GCC_SG
3129 clock-names = "sgmi_r
3130 #phy-cells = <0>;
3131 status = "disabled";
3132 };
3133
3134 serdes1: phy@8902000 {
3135 compatible = "qcom,sa
3136 reg = <0x0 0x08902000
3137 clocks = <&gcc GCC_SG
3138 clock-names = "sgmi_r
3139 #phy-cells = <0>;
3140 status = "disabled";
3141 };
3142
3143 pmu@9091000 {
3144 compatible = "qcom,sa
3145 reg = <0x0 0x9091000
3146 interrupts = <GIC_SPI
3147 interconnects = <&mc_
3148 &mc_
3149
3150 operating-points-v2 =
3151
3152 llcc_bwmon_opp_table:
3153 compatible =
3154
3155 opp-0 {
3156 opp-p
3157 };
3158
3159 opp-1 {
3160 opp-p
3161 };
3162
3163 opp-2 {
3164 opp-p
3165 };
3166
3167 opp-3 {
3168 opp-p
3169 };
3170
3171 opp-4 {
3172 opp-p
3173 };
3174
3175 opp-5 {
3176 opp-p
3177 };
3178
3179 opp-6 {
3180 opp-p
3181 };
3182
3183 opp-7 {
3184 opp-p
3185 };
3186
3187 opp-8 {
3188 opp-p
3189 };
3190
3191 opp-9 {
3192 opp-p
3193 };
3194 };
3195 };
3196
3197 pmu@90b5400 {
3198 compatible = "qcom,sa
3199 reg = <0x0 0x90b5400
3200 interrupts = <GIC_SPI
3201 interconnects = <&gem
3202 &gem
3203
3204 operating-points-v2 =
3205
3206 cpu_bwmon_opp_table:
3207 compatible =
3208
3209 opp-0 {
3210 opp-p
3211 };
3212
3213 opp-1 {
3214 opp-p
3215 };
3216
3217 opp-2 {
3218 opp-p
3219 };
3220
3221 opp-3 {
3222 opp-p
3223 };
3224 };
3225
3226 };
3227
3228 pmu@90b6400 {
3229 compatible = "qcom,sa
3230 reg = <0x0 0x90b6400
3231 interrupts = <GIC_SPI
3232 interconnects = <&gem
3233 &gem
3234
3235 operating-points-v2 =
3236 };
3237
3238 llcc: system-cache-controller
3239 compatible = "qcom,sa
3240 reg = <0x0 0x09200000
3241 <0x0 0x09300000
3242 <0x0 0x09400000
3243 <0x0 0x09500000
3244 <0x0 0x09600000
3245 <0x0 0x09700000
3246 <0x0 0x09a00000
3247 reg-names = "llcc0_ba
3248 "llcc1_ba
3249 "llcc2_ba
3250 "llcc3_ba
3251 "llcc4_ba
3252 "llcc5_ba
3253 "llcc_bro
3254 interrupts = <GIC_SPI
3255 };
3256
3257 pdc: interrupt-controller@b22
3258 compatible = "qcom,sa
3259 reg = <0x0 0x0b220000
3260 <0x0 0x17c000f0
3261 qcom,pdc-ranges = <0
3262 <40
3263 <54
3264 <55
3265 <59
3266 <62
3267 <64
3268 <66
3269 <70
3270 <73
3271 <11
3272 <12
3273 <15
3274 <16
3275 <16
3276 <19
3277 <20
3278 <20
3279 <20
3280 <20
3281 <20
3282 <20
3283 <20
3284 <20
3285 <20
3286 <21
3287 <21
3288 <21
3289 <21
3290 <21
3291 <21
3292 <22
3293 <22
3294 <22
3295 <22
3296 <23
3297 <23
3298 <23
3299 #interrupt-cells = <2
3300 interrupt-parent = <&
3301 interrupt-controller;
3302 };
3303
3304 tsens2: thermal-sensor@c25100
3305 compatible = "qcom,sa
3306 reg = <0x0 0x0c251000
3307 <0x0 0x0c224000
3308 interrupts = <GIC_SPI
3309 <GIC_SPI
3310 #qcom,sensors = <13>;
3311 interrupt-names = "up
3312 #thermal-sensor-cells
3313 };
3314
3315 tsens3: thermal-sensor@c25200
3316 compatible = "qcom,sa
3317 reg = <0x0 0x0c252000
3318 <0x0 0x0c225000
3319 interrupts = <GIC_SPI
3320 <GIC_SPI
3321 #qcom,sensors = <13>;
3322 interrupt-names = "up
3323 #thermal-sensor-cells
3324 };
3325
3326 tsens0: thermal-sensor@c26300
3327 compatible = "qcom,sa
3328 reg = <0x0 0x0c263000
3329 <0x0 0x0c222000
3330 interrupts = <GIC_SPI
3331 <GIC_SPI
3332 #qcom,sensors = <12>;
3333 interrupt-names = "up
3334 #thermal-sensor-cells
3335 };
3336
3337 tsens1: thermal-sensor@c26500
3338 compatible = "qcom,sa
3339 reg = <0x0 0x0c265000
3340 <0x0 0x0c223000
3341 interrupts = <GIC_SPI
3342 <GIC_SPI
3343 #qcom,sensors = <12>;
3344 interrupt-names = "up
3345 #thermal-sensor-cells
3346 };
3347
3348 aoss_qmp: power-management@c3
3349 compatible = "qcom,sa
3350 reg = <0x0 0x0c300000
3351 interrupts-extended =
3352
3353
3354 mboxes = <&ipcc IPCC_
3355 #clock-cells = <0>;
3356 };
3357
3358 sram@c3f0000 {
3359 compatible = "qcom,rp
3360 reg = <0x0 0x0c3f0000
3361 };
3362
3363 spmi_bus: spmi@c440000 {
3364 compatible = "qcom,sp
3365 reg = <0x0 0x0c440000
3366 <0x0 0x0c600000
3367 <0x0 0x0e600000
3368 <0x0 0x0e700000
3369 <0x0 0x0c40a000
3370 reg-names = "core",
3371 "chnls",
3372 "obsrvr",
3373 "intr",
3374 "cnfg";
3375 qcom,channel = <0>;
3376 qcom,ee = <0>;
3377 interrupts-extended =
3378 interrupt-names = "pe
3379 interrupt-controller;
3380 #interrupt-cells = <4
3381 #address-cells = <2>;
3382 #size-cells = <0>;
3383 };
3384
3385 tlmm: pinctrl@f000000 {
3386 compatible = "qcom,sa
3387 reg = <0x0 0x0f000000
3388 interrupts = <GIC_SPI
3389 gpio-controller;
3390 #gpio-cells = <2>;
3391 interrupt-controller;
3392 #interrupt-cells = <2
3393 gpio-ranges = <&tlmm
3394 wakeup-parent = <&pdc
3395 };
3396
3397 sram: sram@146d8000 {
3398 compatible = "qcom,sa
3399 reg = <0x0 0x146d8000
3400 ranges = <0x0 0x0 0x1
3401
3402 #address-cells = <1>;
3403 #size-cells = <1>;
3404
3405 pil-reloc@94c {
3406 compatible =
3407 reg = <0x94c
3408 };
3409 };
3410
3411 apps_smmu: iommu@15000000 {
3412 compatible = "qcom,sa
3413 reg = <0x0 0x15000000
3414 #iommu-cells = <2>;
3415 #global-interrupts =
3416 dma-coherent;
3417
3418 interrupts = <GIC_SPI
3419 <GIC_SPI
3420 <GIC_SPI
3421 <GIC_SPI
3422 <GIC_SPI
3423 <GIC_SPI
3424 <GIC_SPI
3425 <GIC_SPI
3426 <GIC_SPI
3427 <GIC_SPI
3428 <GIC_SPI
3429 <GIC_SPI
3430 <GIC_SPI
3431 <GIC_SPI
3432 <GIC_SPI
3433 <GIC_SPI
3434 <GIC_SPI
3435 <GIC_SPI
3436 <GIC_SPI
3437 <GIC_SPI
3438 <GIC_SPI
3439 <GIC_SPI
3440 <GIC_SPI
3441 <GIC_SPI
3442 <GIC_SPI
3443 <GIC_SPI
3444 <GIC_SPI
3445 <GIC_SPI
3446 <GIC_SPI
3447 <GIC_SPI
3448 <GIC_SPI
3449 <GIC_SPI
3450 <GIC_SPI
3451 <GIC_SPI
3452 <GIC_SPI
3453 <GIC_SPI
3454 <GIC_SPI
3455 <GIC_SPI
3456 <GIC_SPI
3457 <GIC_SPI
3458 <GIC_SPI
3459 <GIC_SPI
3460 <GIC_SPI
3461 <GIC_SPI
3462 <GIC_SPI
3463 <GIC_SPI
3464 <GIC_SPI
3465 <GIC_SPI
3466 <GIC_SPI
3467 <GIC_SPI
3468 <GIC_SPI
3469 <GIC_SPI
3470 <GIC_SPI
3471 <GIC_SPI
3472 <GIC_SPI
3473 <GIC_SPI
3474 <GIC_SPI
3475 <GIC_SPI
3476 <GIC_SPI
3477 <GIC_SPI
3478 <GIC_SPI
3479 <GIC_SPI
3480 <GIC_SPI
3481 <GIC_SPI
3482 <GIC_SPI
3483 <GIC_SPI
3484 <GIC_SPI
3485 <GIC_SPI
3486 <GIC_SPI
3487 <GIC_SPI
3488 <GIC_SPI
3489 <GIC_SPI
3490 <GIC_SPI
3491 <GIC_SPI
3492 <GIC_SPI
3493 <GIC_SPI
3494 <GIC_SPI
3495 <GIC_SPI
3496 <GIC_SPI
3497 <GIC_SPI
3498 <GIC_SPI
3499 <GIC_SPI
3500 <GIC_SPI
3501 <GIC_SPI
3502 <GIC_SPI
3503 <GIC_SPI
3504 <GIC_SPI
3505 <GIC_SPI
3506 <GIC_SPI
3507 <GIC_SPI
3508 <GIC_SPI
3509 <GIC_SPI
3510 <GIC_SPI
3511 <GIC_SPI
3512 <GIC_SPI
3513 <GIC_SPI
3514 <GIC_SPI
3515 <GIC_SPI
3516 <GIC_SPI
3517 <GIC_SPI
3518 <GIC_SPI
3519 <GIC_SPI
3520 <GIC_SPI
3521 <GIC_SPI
3522 <GIC_SPI
3523 <GIC_SPI
3524 <GIC_SPI
3525 <GIC_SPI
3526 <GIC_SPI
3527 <GIC_SPI
3528 <GIC_SPI
3529 <GIC_SPI
3530 <GIC_SPI
3531 <GIC_SPI
3532 <GIC_SPI
3533 <GIC_SPI
3534 <GIC_SPI
3535 <GIC_SPI
3536 <GIC_SPI
3537 <GIC_SPI
3538 <GIC_SPI
3539 <GIC_SPI
3540 <GIC_SPI
3541 <GIC_SPI
3542 <GIC_SPI
3543 <GIC_SPI
3544 <GIC_SPI
3545 <GIC_SPI
3546 <GIC_SPI
3547 <GIC_SPI
3548 };
3549
3550 pcie_smmu: iommu@15200000 {
3551 compatible = "qcom,sa
3552 reg = <0x0 0x15200000
3553 #iommu-cells = <2>;
3554 #global-interrupts =
3555 dma-coherent;
3556
3557 interrupts = <GIC_SPI
3558 <GIC_SPI
3559 <GIC_SPI
3560 <GIC_SPI
3561 <GIC_SPI
3562 <GIC_SPI
3563 <GIC_SPI
3564 <GIC_SPI
3565 <GIC_SPI
3566 <GIC_SPI
3567 <GIC_SPI
3568 <GIC_SPI
3569 <GIC_SPI
3570 <GIC_SPI
3571 <GIC_SPI
3572 <GIC_SPI
3573 <GIC_SPI
3574 <GIC_SPI
3575 <GIC_SPI
3576 <GIC_SPI
3577 <GIC_SPI
3578 <GIC_SPI
3579 <GIC_SPI
3580 <GIC_SPI
3581 <GIC_SPI
3582 <GIC_SPI
3583 <GIC_SPI
3584 <GIC_SPI
3585 <GIC_SPI
3586 <GIC_SPI
3587 <GIC_SPI
3588 <GIC_SPI
3589 <GIC_SPI
3590 <GIC_SPI
3591 <GIC_SPI
3592 <GIC_SPI
3593 <GIC_SPI
3594 <GIC_SPI
3595 <GIC_SPI
3596 <GIC_SPI
3597 <GIC_SPI
3598 <GIC_SPI
3599 <GIC_SPI
3600 <GIC_SPI
3601 <GIC_SPI
3602 <GIC_SPI
3603 <GIC_SPI
3604 <GIC_SPI
3605 <GIC_SPI
3606 <GIC_SPI
3607 <GIC_SPI
3608 <GIC_SPI
3609 <GIC_SPI
3610 <GIC_SPI
3611 <GIC_SPI
3612 <GIC_SPI
3613 <GIC_SPI
3614 <GIC_SPI
3615 <GIC_SPI
3616 <GIC_SPI
3617 <GIC_SPI
3618 <GIC_SPI
3619 <GIC_SPI
3620 <GIC_SPI
3621 <GIC_SPI
3622 <GIC_SPI
3623 };
3624
3625 intc: interrupt-controller@17
3626 compatible = "arm,gic
3627 reg = <0x0 0x17a00000
3628 <0x0 0x17a60000
3629 interrupt-controller;
3630 #interrupt-cells = <3
3631 interrupts = <GIC_PPI
3632 #redistributor-region
3633 redistributor-stride
3634 };
3635
3636 watchdog@17c10000 {
3637 compatible = "qcom,ap
3638 reg = <0x0 0x17c10000
3639 clocks = <&sleep_clk>
3640 interrupts = <GIC_SPI
3641 };
3642
3643 memtimer: timer@17c20000 {
3644 compatible = "arm,arm
3645 reg = <0x0 0x17c20000
3646 ranges = <0x0 0x0 0x0
3647 #address-cells = <1>;
3648 #size-cells = <1>;
3649
3650 frame@17c21000 {
3651 reg = <0x17c2
3652 <0x17c2
3653 interrupts =
3654
3655 frame-number
3656 };
3657
3658 frame@17c23000 {
3659 reg = <0x17c2
3660 interrupts =
3661 frame-number
3662 status = "dis
3663 };
3664
3665 frame@17c25000 {
3666 reg = <0x17c2
3667 interrupts =
3668 frame-number
3669 status = "dis
3670 };
3671
3672 frame@17c27000 {
3673 reg = <0x17c2
3674 interrupts =
3675 frame-number
3676 status = "dis
3677 };
3678
3679 frame@17c29000 {
3680 reg = <0x17c2
3681 interrupts =
3682 frame-number
3683 status = "dis
3684 };
3685
3686 frame@17c2b000 {
3687 reg = <0x17c2
3688 interrupts =
3689 frame-number
3690 status = "dis
3691 };
3692
3693 frame@17c2d000 {
3694 reg = <0x17c2
3695 interrupts =
3696 frame-number
3697 status = "dis
3698 };
3699 };
3700
3701 apps_rsc: rsc@18200000 {
3702 compatible = "qcom,rp
3703 reg = <0x0 0x18200000
3704 <0x0 0x18210000
3705 <0x0 0x18220000
3706 reg-names = "drv-0",
3707 interrupts = <GIC_SPI
3708 <GIC_SPI 4 IRQ_
3709 <GIC_SPI 5 IRQ_
3710 qcom,tcs-offset = <0x
3711 qcom,drv-id = <2>;
3712 qcom,tcs-config = <AC
3713 <SL
3714 <WA
3715 <CO
3716 label = "apps_rsc";
3717
3718 apps_bcm_voter: bcm-v
3719 compatible =
3720 };
3721
3722 rpmhcc: clock-control
3723 compatible =
3724 #clock-cells
3725 clock-names =
3726 clocks = <&xo
3727 };
3728
3729 rpmhpd: power-control
3730 compatible =
3731 #power-domain
3732 operating-poi
3733
3734 rpmhpd_opp_ta
3735 compa
3736
3737 rpmhp
3738
3739 };
3740
3741 rpmhp
3742
3743 };
3744
3745 rpmhp
3746
3747 };
3748
3749 rpmhp
3750
3751 };
3752
3753 rpmhp
3754
3755 };
3756
3757 rpmhp
3758
3759 };
3760
3761 rpmhp
3762
3763 };
3764
3765 rpmhp
3766
3767 };
3768
3769 rpmhp
3770
3771 };
3772
3773 rpmhp
3774
3775 };
3776 };
3777 };
3778 };
3779
3780 cpufreq_hw: cpufreq@18591000
3781 compatible = "qcom,sa
3782 "qcom,cp
3783 reg = <0x0 0x18591000
3784 <0x0 0x18593000
3785 reg-names = "freq-dom
3786
3787 clocks = <&rpmhcc RPM
3788 clock-names = "xo", "
3789
3790 #freq-domain-cells =
3791 };
3792
3793 remoteproc_gpdsp0: remoteproc
3794 compatible = "qcom,sa
3795 reg = <0x0 0x20c00000
3796
3797 interrupts-extended =
3798
3799
3800
3801
3802 interrupt-names = "wd
3803 "ha
3804
3805 clocks = <&rpmhcc RPM
3806 clock-names = "xo";
3807
3808 power-domains = <&rpm
3809 <&rpm
3810 power-domain-names =
3811
3812 interconnects = <&gpd
3813 &con
3814
3815 memory-region = <&pil
3816
3817 qcom,qmp = <&aoss_qmp
3818
3819 qcom,smem-states = <&
3820 qcom,smem-state-names
3821
3822 status = "disabled";
3823
3824 glink-edge {
3825 interrupts-ex
3826
3827
3828 mboxes = <&ip
3829
3830
3831 label = "gpds
3832 qcom,remote-p
3833 };
3834 };
3835
3836 remoteproc_gpdsp1: remoteproc
3837 compatible = "qcom,sa
3838 reg = <0x0 0x21c00000
3839
3840 interrupts-extended =
3841
3842
3843
3844
3845 interrupt-names = "wd
3846 "ha
3847
3848 clocks = <&rpmhcc RPM
3849 clock-names = "xo";
3850
3851 power-domains = <&rpm
3852 <&rpm
3853 power-domain-names =
3854
3855 interconnects = <&gpd
3856 &con
3857
3858 memory-region = <&pil
3859
3860 qcom,qmp = <&aoss_qmp
3861
3862 qcom,smem-states = <&
3863 qcom,smem-state-names
3864
3865 status = "disabled";
3866
3867 glink-edge {
3868 interrupts-ex
3869
3870
3871 mboxes = <&ip
3872
3873
3874 label = "gpds
3875 qcom,remote-p
3876 };
3877 };
3878
3879 ethernet1: ethernet@23000000
3880 compatible = "qcom,sa
3881 reg = <0x0 0x23000000
3882 <0x0 0x23016000
3883 reg-names = "stmmacet
3884
3885 interrupts = <GIC_SPI
3886 <GIC_SPI
3887 interrupt-names = "ma
3888
3889 clocks = <&gcc GCC_EM
3890 <&gcc GCC_EM
3891 <&gcc GCC_EM
3892 <&gcc GCC_EM
3893 clock-names = "stmmac
3894 "pclk",
3895 "ptp_re
3896 "phyaux
3897
3898 interconnects = <&agg
3899 &mc_
3900 <&gem
3901 &con
3902 interconnect-names =
3903
3904 power-domains = <&gcc
3905
3906 phys = <&serdes1>;
3907 phy-names = "serdes";
3908
3909 iommus = <&apps_smmu
3910 dma-coherent;
3911
3912 snps,tso;
3913 snps,pbl = <32>;
3914 rx-fifo-depth = <1638
3915 tx-fifo-depth = <1638
3916
3917 status = "disabled";
3918 };
3919
3920 ethernet0: ethernet@23040000
3921 compatible = "qcom,sa
3922 reg = <0x0 0x23040000
3923 <0x0 0x23056000
3924 reg-names = "stmmacet
3925
3926 interrupts = <GIC_SPI
3927 <GIC_SPI
3928 interrupt-names = "ma
3929
3930 clocks = <&gcc GCC_EM
3931 <&gcc GCC_EM
3932 <&gcc GCC_EM
3933 <&gcc GCC_EM
3934 clock-names = "stmmac
3935 "pclk",
3936 "ptp_re
3937 "phyaux
3938
3939 interconnects = <&agg
3940 &mc_
3941 <&gem
3942 &con
3943 interconnect-names =
3944
3945 power-domains = <&gcc
3946
3947 phys = <&serdes0>;
3948 phy-names = "serdes";
3949
3950 iommus = <&apps_smmu
3951 dma-coherent;
3952
3953 snps,tso;
3954 snps,pbl = <32>;
3955 rx-fifo-depth = <1638
3956 tx-fifo-depth = <1638
3957
3958 status = "disabled";
3959 };
3960
3961 remoteproc_cdsp0: remoteproc@
3962 compatible = "qcom,sa
3963 reg = <0x0 0x26300000
3964
3965 interrupts-extended =
3966
3967
3968
3969
3970 interrupt-names = "wd
3971 "ha
3972
3973 clocks = <&rpmhcc RPM
3974 clock-names = "xo";
3975
3976 power-domains = <&rpm
3977 <&rpm
3978 <&rpm
3979 power-domain-names =
3980
3981 interconnects = <&nsp
3982 &mc_
3983
3984 memory-region = <&pil
3985
3986 qcom,qmp = <&aoss_qmp
3987
3988 qcom,smem-states = <&
3989 qcom,smem-state-names
3990
3991 status = "disabled";
3992
3993 glink-edge {
3994 interrupts-ex
3995
3996
3997 mboxes = <&ip
3998
3999
4000 label = "cdsp
4001 qcom,remote-p
4002
4003 fastrpc {
4004 compa
4005 qcom,
4006 label
4007 #addr
4008 #size
4009
4010 compu
4011
4012
4013
4014
4015
4016
4017
4018
4019
4020
4021
4022
4023
4024 };
4025
4026 compu
4027
4028
4029
4030
4031
4032
4033
4034
4035
4036
4037
4038
4039
4040 };
4041
4042 compu
4043
4044
4045
4046
4047
4048
4049
4050
4051
4052
4053
4054
4055
4056 };
4057
4058 compu
4059
4060
4061
4062
4063
4064
4065
4066
4067
4068
4069
4070
4071
4072 };
4073
4074 compu
4075
4076
4077
4078
4079
4080
4081
4082
4083
4084
4085
4086
4087
4088 };
4089
4090 compu
4091
4092
4093
4094
4095
4096
4097
4098
4099
4100
4101
4102
4103
4104 };
4105
4106 compu
4107
4108
4109
4110
4111
4112
4113
4114
4115
4116
4117
4118
4119
4120 };
4121
4122 compu
4123
4124
4125
4126
4127
4128
4129
4130
4131
4132
4133
4134
4135
4136 };
4137
4138 compu
4139
4140
4141
4142
4143
4144
4145
4146
4147
4148
4149
4150
4151
4152 };
4153
4154 compu
4155
4156
4157
4158
4159
4160
4161
4162
4163
4164
4165
4166
4167
4168 };
4169
4170 compu
4171
4172
4173
4174
4175
4176
4177
4178
4179
4180
4181
4182
4183
4184 };
4185 };
4186 };
4187 };
4188
4189 remoteproc_cdsp1: remoteproc@
4190 compatible = "qcom,sa
4191 reg = <0x0 0x2A300000
4192
4193 interrupts-extended =
4194
4195
4196
4197
4198 interrupt-names = "wd
4199 "ha
4200
4201 clocks = <&rpmhcc RPM
4202 clock-names = "xo";
4203
4204 power-domains = <&rpm
4205 <&rpm
4206 <&rpm
4207 power-domain-names =
4208
4209 interconnects = <&nsp
4210 &mc_
4211
4212 memory-region = <&pil
4213
4214 qcom,qmp = <&aoss_qmp
4215
4216 qcom,smem-states = <&
4217 qcom,smem-state-names
4218
4219 status = "disabled";
4220
4221 glink-edge {
4222 interrupts-ex
4223
4224
4225 mboxes = <&ip
4226
4227
4228 label = "cdsp
4229 qcom,remote-p
4230
4231 fastrpc {
4232 compa
4233 qcom,
4234 label
4235 #addr
4236 #size
4237
4238 compu
4239
4240
4241
4242
4243
4244
4245
4246
4247
4248
4249
4250
4251
4252 };
4253
4254 compu
4255
4256
4257
4258
4259
4260
4261
4262
4263
4264
4265
4266
4267
4268 };
4269
4270 compu
4271
4272
4273
4274
4275
4276
4277
4278
4279
4280
4281
4282
4283
4284 };
4285
4286 compu
4287
4288
4289
4290
4291
4292
4293
4294
4295
4296
4297
4298
4299
4300 };
4301
4302 compu
4303
4304
4305
4306
4307
4308
4309
4310
4311
4312
4313
4314
4315
4316 };
4317
4318 compu
4319
4320
4321
4322
4323
4324
4325
4326
4327
4328
4329
4330
4331
4332 };
4333
4334 compu
4335
4336
4337
4338
4339
4340
4341
4342
4343
4344
4345
4346
4347
4348 };
4349
4350 compu
4351
4352
4353
4354
4355
4356
4357
4358
4359
4360
4361
4362
4363
4364 };
4365
4366 compu
4367
4368
4369
4370
4371
4372
4373
4374
4375
4376
4377
4378
4379
4380 };
4381
4382 compu
4383
4384
4385
4386
4387
4388
4389
4390
4391
4392
4393
4394
4395
4396 };
4397
4398 compu
4399
4400
4401
4402
4403
4404
4405
4406
4407
4408
4409
4410
4411
4412 };
4413
4414 compu
4415
4416
4417
4418
4419
4420
4421
4422
4423
4424
4425
4426
4427
4428 };
4429
4430 compu
4431
4432
4433
4434
4435
4436
4437
4438
4439
4440
4441
4442
4443
4444 };
4445 };
4446 };
4447 };
4448
4449 remoteproc_adsp: remoteproc@3
4450 compatible = "qcom,sa
4451 reg = <0x0 0x30000000
4452
4453 interrupts-extended =
4454
4455
4456
4457
4458 interrupt-names = "wd
4459 "st
4460
4461 clocks = <&rpmhcc RPM
4462 clock-names = "xo";
4463
4464 power-domains = <&rpm
4465 <&rpm
4466 power-domain-names =
4467
4468 interconnects = <&lpa
4469
4470 memory-region = <&pil
4471
4472 qcom,qmp = <&aoss_qmp
4473
4474 qcom,smem-states = <&
4475 qcom,smem-state-names
4476
4477 status = "disabled";
4478
4479 remoteproc_adsp_glink
4480 interrupts-ex
4481
4482
4483 mboxes = <&ip
4484
4485
4486 label = "lpas
4487 qcom,remote-p
4488
4489 fastrpc {
4490 compa
4491 qcom,
4492 label
4493 memor
4494 qcom,
4495
4496 #addr
4497 #size
4498
4499 compu
4500
4501
4502
4503
4504 };
4505
4506 compu
4507
4508
4509
4510
4511 };
4512
4513 compu
4514
4515
4516
4517
4518
4519 };
4520 };
4521 };
4522 };
4523 };
4524
4525 thermal-zones {
4526 aoss-0-thermal {
4527 thermal-sensors = <&t
4528
4529 trips {
4530 trip-point0 {
4531 tempe
4532 hyste
4533 type
4534 };
4535
4536 trip-point1 {
4537 tempe
4538 hyste
4539 type
4540 };
4541 };
4542 };
4543
4544 cpu-0-0-0-thermal {
4545 polling-delay-passive
4546
4547 thermal-sensors = <&t
4548
4549 trips {
4550 trip-point0 {
4551 tempe
4552 hyste
4553 type
4554 };
4555
4556 trip-point1 {
4557 tempe
4558 hyste
4559 type
4560 };
4561 };
4562 };
4563
4564 cpu-0-1-0-thermal {
4565 polling-delay-passive
4566
4567 thermal-sensors = <&t
4568
4569 trips {
4570 trip-point0 {
4571 tempe
4572 hyste
4573 type
4574 };
4575
4576 trip-point1 {
4577 tempe
4578 hyste
4579 type
4580 };
4581 };
4582 };
4583
4584 cpu-0-2-0-thermal {
4585 polling-delay-passive
4586
4587 thermal-sensors = <&t
4588
4589 trips {
4590 trip-point0 {
4591 tempe
4592 hyste
4593 type
4594 };
4595
4596 trip-point1 {
4597 tempe
4598 hyste
4599 type
4600 };
4601 };
4602 };
4603
4604 cpu-0-3-0-thermal {
4605 polling-delay-passive
4606
4607 thermal-sensors = <&t
4608
4609 trips {
4610 trip-point0 {
4611 tempe
4612 hyste
4613 type
4614 };
4615
4616 trip-point1 {
4617 tempe
4618 hyste
4619 type
4620 };
4621 };
4622 };
4623
4624 gpuss-0-thermal {
4625 polling-delay-passive
4626
4627 thermal-sensors = <&t
4628
4629 trips {
4630 trip-point0 {
4631 tempe
4632 hyste
4633 type
4634 };
4635
4636 trip-point1 {
4637 tempe
4638 hyste
4639 type
4640 };
4641 };
4642 };
4643
4644 gpuss-1-thermal {
4645 polling-delay-passive
4646
4647 thermal-sensors = <&t
4648
4649 trips {
4650 trip-point0 {
4651 tempe
4652 hyste
4653 type
4654 };
4655
4656 trip-point1 {
4657 tempe
4658 hyste
4659 type
4660 };
4661 };
4662 };
4663
4664 gpuss-2-thermal {
4665 polling-delay-passive
4666
4667 thermal-sensors = <&t
4668
4669 trips {
4670 trip-point0 {
4671 tempe
4672 hyste
4673 type
4674 };
4675
4676 trip-point1 {
4677 tempe
4678 hyste
4679 type
4680 };
4681 };
4682 };
4683
4684 audio-thermal {
4685 thermal-sensors = <&t
4686
4687 trips {
4688 trip-point0 {
4689 tempe
4690 hyste
4691 type
4692 };
4693
4694 trip-point1 {
4695 tempe
4696 hyste
4697 type
4698 };
4699 };
4700 };
4701
4702 camss-0-thermal {
4703 thermal-sensors = <&t
4704
4705 trips {
4706 trip-point0 {
4707 tempe
4708 hyste
4709 type
4710 };
4711
4712 trip-point1 {
4713 tempe
4714 hyste
4715 type
4716 };
4717 };
4718 };
4719
4720 pcie-0-thermal {
4721 thermal-sensors = <&t
4722
4723 trips {
4724 trip-point0 {
4725 tempe
4726 hyste
4727 type
4728 };
4729
4730 trip-point1 {
4731 tempe
4732 hyste
4733 type
4734 };
4735 };
4736 };
4737
4738 cpuss-0-0-thermal {
4739 thermal-sensors = <&t
4740
4741 trips {
4742 trip-point0 {
4743 tempe
4744 hyste
4745 type
4746 };
4747
4748 trip-point1 {
4749 tempe
4750 hyste
4751 type
4752 };
4753 };
4754 };
4755
4756 aoss-1-thermal {
4757 thermal-sensors = <&t
4758
4759 trips {
4760 trip-point0 {
4761 tempe
4762 hyste
4763 type
4764 };
4765
4766 trip-point1 {
4767 tempe
4768 hyste
4769 type
4770 };
4771 };
4772 };
4773
4774 cpu-0-0-1-thermal {
4775 polling-delay-passive
4776
4777 thermal-sensors = <&t
4778
4779 trips {
4780 trip-point0 {
4781 tempe
4782 hyste
4783 type
4784 };
4785
4786 trip-point1 {
4787 tempe
4788 hyste
4789 type
4790 };
4791 };
4792 };
4793
4794 cpu-0-1-1-thermal {
4795 polling-delay-passive
4796
4797 thermal-sensors = <&t
4798
4799 trips {
4800 trip-point0 {
4801 tempe
4802 hyste
4803 type
4804 };
4805
4806 trip-point1 {
4807 tempe
4808 hyste
4809 type
4810 };
4811 };
4812 };
4813
4814 cpu-0-2-1-thermal {
4815 polling-delay-passive
4816
4817 thermal-sensors = <&t
4818
4819 trips {
4820 trip-point0 {
4821 tempe
4822 hyste
4823 type
4824 };
4825
4826 trip-point1 {
4827 tempe
4828 hyste
4829 type
4830 };
4831 };
4832 };
4833
4834 cpu-0-3-1-thermal {
4835 polling-delay-passive
4836
4837 thermal-sensors = <&t
4838
4839 trips {
4840 trip-point0 {
4841 tempe
4842 hyste
4843 type
4844 };
4845
4846 trip-point1 {
4847 tempe
4848 hyste
4849 type
4850 };
4851 };
4852 };
4853
4854 gpuss-3-thermal {
4855 polling-delay-passive
4856
4857 thermal-sensors = <&t
4858
4859 trips {
4860 trip-point0 {
4861 tempe
4862 hyste
4863 type
4864 };
4865
4866 trip-point1 {
4867 tempe
4868 hyste
4869 type
4870 };
4871 };
4872 };
4873
4874 gpuss-4-thermal {
4875 polling-delay-passive
4876
4877 thermal-sensors = <&t
4878
4879 trips {
4880 trip-point0 {
4881 tempe
4882 hyste
4883 type
4884 };
4885
4886 trip-point1 {
4887 tempe
4888 hyste
4889 type
4890 };
4891 };
4892 };
4893
4894 gpuss-5-thermal {
4895 polling-delay-passive
4896
4897 thermal-sensors = <&t
4898
4899 trips {
4900 trip-point0 {
4901 tempe
4902 hyste
4903 type
4904 };
4905
4906 trip-point1 {
4907 tempe
4908 hyste
4909 type
4910 };
4911 };
4912 };
4913
4914 video-thermal {
4915 thermal-sensors = <&t
4916
4917 trips {
4918 trip-point0 {
4919 tempe
4920 hyste
4921 type
4922 };
4923
4924 trip-point1 {
4925 tempe
4926 hyste
4927 type
4928 };
4929 };
4930 };
4931
4932 camss-1-thermal {
4933 thermal-sensors = <&t
4934
4935 trips {
4936 trip-point0 {
4937 tempe
4938 hyste
4939 type
4940 };
4941
4942 trip-point1 {
4943 tempe
4944 hyste
4945 type
4946 };
4947 };
4948 };
4949
4950 pcie-1-thermal {
4951 thermal-sensors = <&t
4952
4953 trips {
4954 trip-point0 {
4955 tempe
4956 hyste
4957 type
4958 };
4959
4960 trip-point1 {
4961 tempe
4962 hyste
4963 type
4964 };
4965 };
4966 };
4967
4968 cpuss-0-1-thermal {
4969 thermal-sensors = <&t
4970
4971 trips {
4972 trip-point0 {
4973 tempe
4974 hyste
4975 type
4976 };
4977
4978 trip-point1 {
4979 tempe
4980 hyste
4981 type
4982 };
4983 };
4984 };
4985
4986 aoss-2-thermal {
4987 thermal-sensors = <&t
4988
4989 trips {
4990 trip-point0 {
4991 tempe
4992 hyste
4993 type
4994 };
4995
4996 trip-point1 {
4997 tempe
4998 hyste
4999 type
5000 };
5001 };
5002 };
5003
5004 cpu-1-0-0-thermal {
5005 polling-delay-passive
5006
5007 thermal-sensors = <&t
5008
5009 trips {
5010 trip-point0 {
5011 tempe
5012 hyste
5013 type
5014 };
5015
5016 trip-point1 {
5017 tempe
5018 hyste
5019 type
5020 };
5021 };
5022 };
5023
5024 cpu-1-1-0-thermal {
5025 polling-delay-passive
5026
5027 thermal-sensors = <&t
5028
5029 trips {
5030 trip-point0 {
5031 tempe
5032 hyste
5033 type
5034 };
5035
5036 trip-point1 {
5037 tempe
5038 hyste
5039 type
5040 };
5041 };
5042 };
5043
5044 cpu-1-2-0-thermal {
5045 polling-delay-passive
5046
5047 thermal-sensors = <&t
5048
5049 trips {
5050 trip-point0 {
5051 tempe
5052 hyste
5053 type
5054 };
5055
5056 trip-point1 {
5057 tempe
5058 hyste
5059 type
5060 };
5061 };
5062 };
5063
5064 cpu-1-3-0-thermal {
5065 polling-delay-passive
5066
5067 thermal-sensors = <&t
5068
5069 trips {
5070 trip-point0 {
5071 tempe
5072 hyste
5073 type
5074 };
5075
5076 trip-point1 {
5077 tempe
5078 hyste
5079 type
5080 };
5081 };
5082 };
5083
5084 nsp-0-0-0-thermal {
5085 polling-delay-passive
5086
5087 thermal-sensors = <&t
5088
5089 trips {
5090 trip-point0 {
5091 tempe
5092 hyste
5093 type
5094 };
5095
5096 trip-point1 {
5097 tempe
5098 hyste
5099 type
5100 };
5101 };
5102 };
5103
5104 nsp-0-1-0-thermal {
5105 polling-delay-passive
5106
5107 thermal-sensors = <&t
5108
5109 trips {
5110 trip-point0 {
5111 tempe
5112 hyste
5113 type
5114 };
5115
5116 trip-point1 {
5117 tempe
5118 hyste
5119 type
5120 };
5121 };
5122 };
5123
5124 nsp-0-2-0-thermal {
5125 polling-delay-passive
5126
5127 thermal-sensors = <&t
5128
5129 trips {
5130 trip-point0 {
5131 tempe
5132 hyste
5133 type
5134 };
5135
5136 trip-point1 {
5137 tempe
5138 hyste
5139 type
5140 };
5141 };
5142 };
5143
5144 nsp-1-0-0-thermal {
5145 polling-delay-passive
5146
5147 thermal-sensors = <&t
5148
5149 trips {
5150 trip-point0 {
5151 tempe
5152 hyste
5153 type
5154 };
5155
5156 trip-point1 {
5157 tempe
5158 hyste
5159 type
5160 };
5161 };
5162 };
5163
5164 nsp-1-1-0-thermal {
5165 polling-delay-passive
5166
5167 thermal-sensors = <&t
5168
5169 trips {
5170 trip-point0 {
5171 tempe
5172 hyste
5173 type
5174 };
5175
5176 trip-point1 {
5177 tempe
5178 hyste
5179 type
5180 };
5181 };
5182 };
5183
5184 nsp-1-2-0-thermal {
5185 polling-delay-passive
5186
5187 thermal-sensors = <&t
5188
5189 trips {
5190 trip-point0 {
5191 tempe
5192 hyste
5193 type
5194 };
5195
5196 trip-point1 {
5197 tempe
5198 hyste
5199 type
5200 };
5201 };
5202 };
5203
5204 ddrss-0-thermal {
5205 thermal-sensors = <&t
5206
5207 trips {
5208 trip-point0 {
5209 tempe
5210 hyste
5211 type
5212 };
5213
5214 trip-point1 {
5215 tempe
5216 hyste
5217 type
5218 };
5219 };
5220 };
5221
5222 cpuss-1-0-thermal {
5223 thermal-sensors = <&t
5224
5225 trips {
5226 trip-point0 {
5227 tempe
5228 hyste
5229 type
5230 };
5231
5232 trip-point1 {
5233 tempe
5234 hyste
5235 type
5236 };
5237 };
5238 };
5239
5240 aoss-3-thermal {
5241 thermal-sensors = <&t
5242
5243 trips {
5244 trip-point0 {
5245 tempe
5246 hyste
5247 type
5248 };
5249
5250 trip-point1 {
5251 tempe
5252 hyste
5253 type
5254 };
5255 };
5256 };
5257
5258 cpu-1-0-1-thermal {
5259 polling-delay-passive
5260
5261 thermal-sensors = <&t
5262
5263 trips {
5264 trip-point0 {
5265 tempe
5266 hyste
5267 type
5268 };
5269
5270 trip-point1 {
5271 tempe
5272 hyste
5273 type
5274 };
5275 };
5276 };
5277
5278 cpu-1-1-1-thermal {
5279 polling-delay-passive
5280
5281 thermal-sensors = <&t
5282
5283 trips {
5284 trip-point0 {
5285 tempe
5286 hyste
5287 type
5288 };
5289
5290 trip-point1 {
5291 tempe
5292 hyste
5293 type
5294 };
5295 };
5296 };
5297
5298 cpu-1-2-1-thermal {
5299 polling-delay-passive
5300
5301 thermal-sensors = <&t
5302
5303 trips {
5304 trip-point0 {
5305 tempe
5306 hyste
5307 type
5308 };
5309
5310 trip-point1 {
5311 tempe
5312 hyste
5313 type
5314 };
5315 };
5316 };
5317
5318 cpu-1-3-1-thermal {
5319 polling-delay-passive
5320
5321 thermal-sensors = <&t
5322
5323 trips {
5324 trip-point0 {
5325 tempe
5326 hyste
5327 type
5328 };
5329
5330 trip-point1 {
5331 tempe
5332 hyste
5333 type
5334 };
5335 };
5336 };
5337
5338 nsp-0-0-1-thermal {
5339 polling-delay-passive
5340
5341 thermal-sensors = <&t
5342
5343 trips {
5344 trip-point0 {
5345 tempe
5346 hyste
5347 type
5348 };
5349
5350 trip-point1 {
5351 tempe
5352 hyste
5353 type
5354 };
5355 };
5356 };
5357
5358 nsp-0-1-1-thermal {
5359 polling-delay-passive
5360
5361 thermal-sensors = <&t
5362
5363 trips {
5364 trip-point0 {
5365 tempe
5366 hyste
5367 type
5368 };
5369
5370 trip-point1 {
5371 tempe
5372 hyste
5373 type
5374 };
5375 };
5376 };
5377
5378 nsp-0-2-1-thermal {
5379 polling-delay-passive
5380
5381 thermal-sensors = <&t
5382
5383 trips {
5384 trip-point0 {
5385 tempe
5386 hyste
5387 type
5388 };
5389
5390 trip-point1 {
5391 tempe
5392 hyste
5393 type
5394 };
5395 };
5396 };
5397
5398 nsp-1-0-1-thermal {
5399 polling-delay-passive
5400
5401 thermal-sensors = <&t
5402
5403 trips {
5404 trip-point0 {
5405 tempe
5406 hyste
5407 type
5408 };
5409
5410 trip-point1 {
5411 tempe
5412 hyste
5413 type
5414 };
5415 };
5416 };
5417
5418 nsp-1-1-1-thermal {
5419 polling-delay-passive
5420
5421 thermal-sensors = <&t
5422
5423 trips {
5424 trip-point0 {
5425 tempe
5426 hyste
5427 type
5428 };
5429
5430 trip-point1 {
5431 tempe
5432 hyste
5433 type
5434 };
5435 };
5436 };
5437
5438 nsp-1-2-1-thermal {
5439 polling-delay-passive
5440
5441 thermal-sensors = <&t
5442
5443 trips {
5444 trip-point0 {
5445 tempe
5446 hyste
5447 type
5448 };
5449
5450 trip-point1 {
5451 tempe
5452 hyste
5453 type
5454 };
5455 };
5456 };
5457
5458 ddrss-1-thermal {
5459 thermal-sensors = <&t
5460
5461 trips {
5462 trip-point0 {
5463 tempe
5464 hyste
5465 type
5466 };
5467
5468 trip-point1 {
5469 tempe
5470 hyste
5471 type
5472 };
5473 };
5474 };
5475
5476 cpuss-1-1-thermal {
5477 thermal-sensors = <&t
5478
5479 trips {
5480 trip-point0 {
5481 tempe
5482 hyste
5483 type
5484 };
5485
5486 trip-point1 {
5487 tempe
5488 hyste
5489 type
5490 };
5491 };
5492 };
5493 };
5494
5495 arch_timer: timer {
5496 compatible = "arm,armv8-timer
5497 interrupts = <GIC_PPI 13 (GIC
5498 <GIC_PPI 14 (GIC
5499 <GIC_PPI 11 (GIC
5500 <GIC_PPI 10 (GIC
5501 };
5502
5503 pcie0: pcie@1c00000 {
5504 compatible = "qcom,pcie-sa877
5505 reg = <0x0 0x01c00000 0x0 0x3
5506 <0x0 0x40000000 0x0 0xf
5507 <0x0 0x40000f20 0x0 0xa
5508 <0x0 0x40001000 0x0 0x4
5509 <0x0 0x40100000 0x0 0x1
5510 <0x0 0x01c03000 0x0 0x1
5511 reg-names = "parf", "dbi", "e
5512 device_type = "pci";
5513
5514 #address-cells = <3>;
5515 #size-cells = <2>;
5516 ranges = <0x01000000 0x0 0x00
5517 <0x02000000 0x0 0x40
5518 bus-range = <0x00 0xff>;
5519
5520 dma-coherent;
5521
5522 linux,pci-domain = <0>;
5523 num-lanes = <2>;
5524
5525 interrupts = <GIC_SPI 307 IRQ
5526 <GIC_SPI 308 IRQ
5527 <GIC_SPI 309 IRQ
5528 <GIC_SPI 312 IRQ
5529 <GIC_SPI 313 IRQ
5530 <GIC_SPI 314 IRQ
5531 <GIC_SPI 374 IRQ
5532 <GIC_SPI 375 IRQ
5533 interrupt-names = "msi0", "ms
5534 "msi4", "ms
5535 #interrupt-cells = <1>;
5536 interrupt-map-mask = <0 0 0 0
5537 interrupt-map = <0 0 0 1 &int
5538 <0 0 0 2 &int
5539 <0 0 0 3 &int
5540 <0 0 0 4 &int
5541
5542 clocks = <&gcc GCC_PCIE_0_AUX
5543 <&gcc GCC_PCIE_0_CFG
5544 <&gcc GCC_PCIE_0_MST
5545 <&gcc GCC_PCIE_0_SLV
5546 <&gcc GCC_PCIE_0_SLV
5547
5548 clock-names = "aux",
5549 "cfg",
5550 "bus_master",
5551 "bus_slave",
5552 "slave_q2a";
5553
5554 assigned-clocks = <&gcc GCC_P
5555 assigned-clock-rates = <19200
5556
5557 interconnects = <&pcie_anoc M
5558 <&gem_noc MAS
5559 interconnect-names = "pcie-me
5560
5561 iommu-map = <0x0 &pcie_smmu 0
5562 <0x100 &pcie_smmu
5563
5564 resets = <&gcc GCC_PCIE_0_BCR
5565 reset-names = "pci";
5566 power-domains = <&gcc PCIE_0_
5567
5568 phys = <&pcie0_phy>;
5569 phy-names = "pciephy";
5570
5571 status = "disabled";
5572
5573 pcie@0 {
5574 device_type = "pci";
5575 reg = <0x0 0x0 0x0 0x
5576 bus-range = <0x01 0xf
5577
5578 #address-cells = <3>;
5579 #size-cells = <2>;
5580 ranges;
5581 };
5582 };
5583
5584 pcie0_ep: pcie-ep@1c00000 {
5585 compatible = "qcom,sa8775p-pc
5586 reg = <0x0 0x01c00000 0x0 0x3
5587 <0x0 0x40000000 0x0 0xf
5588 <0x0 0x40000f20 0x0 0xa
5589 <0x0 0x40001000 0x0 0x4
5590 <0x0 0x40200000 0x0 0x1
5591 <0x0 0x01c03000 0x0 0x1
5592 <0x0 0x40005000 0x0 0x2
5593 reg-names = "parf", "dbi", "e
5594 "mmio", "dma";
5595
5596 clocks = <&gcc GCC_PCIE_0_AUX
5597 <&gcc GCC_PCIE_0_CFG_
5598 <&gcc GCC_PCIE_0_MSTR
5599 <&gcc GCC_PCIE_0_SLV_
5600 <&gcc GCC_PCIE_0_SLV_
5601
5602 clock-names = "aux",
5603 "cfg",
5604 "bus_master",
5605 "bus_slave",
5606 "slave_q2a";
5607
5608 interrupts = <GIC_SPI 306 IRQ
5609 <GIC_SPI 147 IRQ
5610 <GIC_SPI 630 IRQ
5611
5612 interrupt-names = "global", "
5613
5614 interconnects = <&pcie_anoc M
5615 <&gem_noc MAS
5616 interconnect-names = "pcie-me
5617
5618 dma-coherent;
5619 iommus = <&pcie_smmu 0x0000 0
5620 resets = <&gcc GCC_PCIE_0_BCR
5621 reset-names = "core";
5622 power-domains = <&gcc PCIE_0_
5623 phys = <&pcie0_phy>;
5624 phy-names = "pciephy";
5625 max-link-speed = <3>; /* FIXM
5626 num-lanes = <2>;
5627
5628 status = "disabled";
5629 };
5630
5631 pcie0_phy: phy@1c04000 {
5632 compatible = "qcom,sa8775p-qm
5633 reg = <0x0 0x1c04000 0x0 0x20
5634
5635 clocks = <&gcc GCC_PCIE_0_AUX
5636 <&gcc GCC_PCIE_0_CFG
5637 <&gcc GCC_PCIE_CLKRE
5638 <&gcc GCC_PCIE_0_PHY
5639 <&gcc GCC_PCIE_0_PIP
5640 <&gcc GCC_PCIE_0_PIP
5641 <&gcc GCC_PCIE_0_PHY
5642
5643 clock-names = "aux", "cfg_ahb
5644 "pipediv2", "ph
5645
5646 assigned-clocks = <&gcc GCC_P
5647 assigned-clock-rates = <10000
5648
5649 resets = <&gcc GCC_PCIE_0_PHY
5650 reset-names = "phy";
5651
5652 #clock-cells = <0>;
5653 clock-output-names = "pcie_0_
5654
5655 #phy-cells = <0>;
5656
5657 status = "disabled";
5658 };
5659
5660 pcie1: pcie@1c10000 {
5661 compatible = "qcom,pcie-sa877
5662 reg = <0x0 0x01c10000 0x0 0x3
5663 <0x0 0x60000000 0x0 0xf
5664 <0x0 0x60000f20 0x0 0xa
5665 <0x0 0x60001000 0x0 0x4
5666 <0x0 0x60100000 0x0 0x1
5667 <0x0 0x01c13000 0x0 0x1
5668 reg-names = "parf", "dbi", "e
5669 device_type = "pci";
5670
5671 #address-cells = <3>;
5672 #size-cells = <2>;
5673 ranges = <0x01000000 0x0 0x00
5674 <0x02000000 0x0 0x60
5675 bus-range = <0x00 0xff>;
5676
5677 dma-coherent;
5678
5679 linux,pci-domain = <1>;
5680 num-lanes = <4>;
5681
5682 interrupts = <GIC_SPI 519 IRQ
5683 <GIC_SPI 140 IRQ
5684 <GIC_SPI 141 IRQ
5685 <GIC_SPI 142 IRQ
5686 <GIC_SPI 143 IRQ
5687 <GIC_SPI 144 IRQ
5688 <GIC_SPI 145 IRQ
5689 <GIC_SPI 146 IRQ
5690 interrupt-names = "msi0", "ms
5691 "msi4", "ms
5692 #interrupt-cells = <1>;
5693 interrupt-map-mask = <0 0 0 0
5694 interrupt-map = <0 0 0 1 &int
5695 <0 0 0 2 &int
5696 <0 0 0 3 &int
5697 <0 0 0 4 &int
5698
5699 clocks = <&gcc GCC_PCIE_1_AUX
5700 <&gcc GCC_PCIE_1_CFG
5701 <&gcc GCC_PCIE_1_MST
5702 <&gcc GCC_PCIE_1_SLV
5703 <&gcc GCC_PCIE_1_SLV
5704
5705 clock-names = "aux",
5706 "cfg",
5707 "bus_master",
5708 "bus_slave",
5709 "slave_q2a";
5710
5711 assigned-clocks = <&gcc GCC_P
5712 assigned-clock-rates = <19200
5713
5714 interconnects = <&pcie_anoc M
5715 <&gem_noc MAS
5716 interconnect-names = "pcie-me
5717
5718 iommu-map = <0x0 &pcie_smmu 0
5719 <0x100 &pcie_smmu
5720
5721 resets = <&gcc GCC_PCIE_1_BCR
5722 reset-names = "pci";
5723 power-domains = <&gcc PCIE_1_
5724
5725 phys = <&pcie1_phy>;
5726 phy-names = "pciephy";
5727
5728 status = "disabled";
5729
5730 pcie@0 {
5731 device_type = "pci";
5732 reg = <0x0 0x0 0x0 0x
5733 bus-range = <0x01 0xf
5734
5735 #address-cells = <3>;
5736 #size-cells = <2>;
5737 ranges;
5738 };
5739 };
5740
5741 pcie1_ep: pcie-ep@1c10000 {
5742 compatible = "qcom,sa8775p-pc
5743 reg = <0x0 0x01c10000 0x0 0x3
5744 <0x0 0x60000000 0x0 0xf
5745 <0x0 0x60000f20 0x0 0xa
5746 <0x0 0x60001000 0x0 0x4
5747 <0x0 0x60200000 0x0 0x1
5748 <0x0 0x01c13000 0x0 0x1
5749 <0x0 0x60005000 0x0 0x2
5750 reg-names = "parf", "dbi", "e
5751 "mmio", "dma";
5752
5753 clocks = <&gcc GCC_PCIE_1_AUX
5754 <&gcc GCC_PCIE_1_CFG
5755 <&gcc GCC_PCIE_1_MST
5756 <&gcc GCC_PCIE_1_SLV
5757 <&gcc GCC_PCIE_1_SLV
5758
5759 clock-names = "aux",
5760 "cfg",
5761 "bus_master",
5762 "bus_slave",
5763 "slave_q2a";
5764
5765 interrupts = <GIC_SPI 518 IRQ
5766 <GIC_SPI 152 IRQ
5767 <GIC_SPI 474 IRQ
5768
5769 interrupt-names = "global", "
5770
5771 interconnects = <&pcie_anoc M
5772 <&gem_noc MAS
5773 interconnect-names = "pcie-me
5774
5775 dma-coherent;
5776 iommus = <&pcie_smmu 0x80 0x7
5777 resets = <&gcc GCC_PCIE_1_BCR
5778 reset-names = "core";
5779 power-domains = <&gcc PCIE_1_
5780 phys = <&pcie1_phy>;
5781 phy-names = "pciephy";
5782 max-link-speed = <3>; /* FIXM
5783 num-lanes = <4>;
5784
5785 status = "disabled";
5786 };
5787
5788 pcie1_phy: phy@1c14000 {
5789 compatible = "qcom,sa8775p-qm
5790 reg = <0x0 0x1c14000 0x0 0x40
5791
5792 clocks = <&gcc GCC_PCIE_1_AUX
5793 <&gcc GCC_PCIE_1_CFG
5794 <&gcc GCC_PCIE_CLKRE
5795 <&gcc GCC_PCIE_1_PHY
5796 <&gcc GCC_PCIE_1_PIP
5797 <&gcc GCC_PCIE_1_PIP
5798 <&gcc GCC_PCIE_1_PHY
5799
5800 clock-names = "aux", "cfg_ahb
5801 "pipediv2", "ph
5802
5803 assigned-clocks = <&gcc GCC_P
5804 assigned-clock-rates = <10000
5805
5806 resets = <&gcc GCC_PCIE_1_PHY
5807 reset-names = "phy";
5808
5809 #clock-cells = <0>;
5810 clock-output-names = "pcie_1_
5811
5812 #phy-cells = <0>;
5813
5814 status = "disabled";
5815 };
5816 };
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