1 // SPDX-License-Identifier: BSD-3-Clause 1 // SPDX-License-Identifier: BSD-3-Clause
2 /* 2 /*
3 * Copyright (c) 2023, Linaro Limited 3 * Copyright (c) 2023, Linaro Limited
4 */ 4 */
5 5
6 #include <dt-bindings/interconnect/qcom,icc.h> 6 #include <dt-bindings/interconnect/qcom,icc.h>
7 #include <dt-bindings/interrupt-controller/arm 7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/clock/qcom,rpmh.h> 8 #include <dt-bindings/clock/qcom,rpmh.h>
9 #include <dt-bindings/clock/qcom,sa8775p-gcc.h 9 #include <dt-bindings/clock/qcom,sa8775p-gcc.h>
10 #include <dt-bindings/clock/qcom,sa8775p-gpucc 10 #include <dt-bindings/clock/qcom,sa8775p-gpucc.h>
11 #include <dt-bindings/interconnect/qcom,sa8775 11 #include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h>
12 #include <dt-bindings/mailbox/qcom-ipcc.h> 12 #include <dt-bindings/mailbox/qcom-ipcc.h>
13 #include <dt-bindings/firmware/qcom,scm.h> <<
14 #include <dt-bindings/power/qcom,rpmhpd.h> <<
15 #include <dt-bindings/power/qcom-rpmpd.h> 13 #include <dt-bindings/power/qcom-rpmpd.h>
16 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 14 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
17 15
18 / { 16 / {
19 interrupt-parent = <&intc>; 17 interrupt-parent = <&intc>;
20 18
21 #address-cells = <2>; 19 #address-cells = <2>;
22 #size-cells = <2>; 20 #size-cells = <2>;
23 21
24 clocks { 22 clocks {
25 xo_board_clk: xo-board-clk { 23 xo_board_clk: xo-board-clk {
26 compatible = "fixed-cl 24 compatible = "fixed-clock";
27 #clock-cells = <0>; 25 #clock-cells = <0>;
28 }; 26 };
29 27
30 sleep_clk: sleep-clk { 28 sleep_clk: sleep-clk {
31 compatible = "fixed-cl 29 compatible = "fixed-clock";
32 #clock-cells = <0>; 30 #clock-cells = <0>;
33 }; 31 };
34 }; 32 };
35 33
36 cpus { 34 cpus {
37 #address-cells = <2>; 35 #address-cells = <2>;
38 #size-cells = <0>; 36 #size-cells = <0>;
39 37
40 CPU0: cpu@0 { 38 CPU0: cpu@0 {
41 device_type = "cpu"; 39 device_type = "cpu";
42 compatible = "qcom,kry 40 compatible = "qcom,kryo";
43 reg = <0x0 0x0>; 41 reg = <0x0 0x0>;
44 enable-method = "psci" 42 enable-method = "psci";
45 qcom,freq-domain = <&c 43 qcom,freq-domain = <&cpufreq_hw 0>;
46 next-level-cache = <&L 44 next-level-cache = <&L2_0>;
47 capacity-dmips-mhz = < <<
48 dynamic-power-coeffici <<
49 L2_0: l2-cache { 45 L2_0: l2-cache {
50 compatible = " 46 compatible = "cache";
51 cache-level = 47 cache-level = <2>;
52 cache-unified; 48 cache-unified;
53 next-level-cac 49 next-level-cache = <&L3_0>;
54 L3_0: l3-cache 50 L3_0: l3-cache {
55 compat 51 compatible = "cache";
56 cache- 52 cache-level = <3>;
57 cache- 53 cache-unified;
58 }; 54 };
59 }; 55 };
60 }; 56 };
61 57
62 CPU1: cpu@100 { 58 CPU1: cpu@100 {
63 device_type = "cpu"; 59 device_type = "cpu";
64 compatible = "qcom,kry 60 compatible = "qcom,kryo";
65 reg = <0x0 0x100>; 61 reg = <0x0 0x100>;
66 enable-method = "psci" 62 enable-method = "psci";
67 qcom,freq-domain = <&c 63 qcom,freq-domain = <&cpufreq_hw 0>;
68 next-level-cache = <&L 64 next-level-cache = <&L2_1>;
69 capacity-dmips-mhz = < <<
70 dynamic-power-coeffici <<
71 L2_1: l2-cache { 65 L2_1: l2-cache {
72 compatible = " 66 compatible = "cache";
73 cache-level = 67 cache-level = <2>;
74 cache-unified; 68 cache-unified;
75 next-level-cac 69 next-level-cache = <&L3_0>;
76 }; 70 };
77 }; 71 };
78 72
79 CPU2: cpu@200 { 73 CPU2: cpu@200 {
80 device_type = "cpu"; 74 device_type = "cpu";
81 compatible = "qcom,kry 75 compatible = "qcom,kryo";
82 reg = <0x0 0x200>; 76 reg = <0x0 0x200>;
83 enable-method = "psci" 77 enable-method = "psci";
84 qcom,freq-domain = <&c 78 qcom,freq-domain = <&cpufreq_hw 0>;
85 next-level-cache = <&L 79 next-level-cache = <&L2_2>;
86 capacity-dmips-mhz = < <<
87 dynamic-power-coeffici <<
88 L2_2: l2-cache { 80 L2_2: l2-cache {
89 compatible = " 81 compatible = "cache";
90 cache-level = 82 cache-level = <2>;
91 cache-unified; 83 cache-unified;
92 next-level-cac 84 next-level-cache = <&L3_0>;
93 }; 85 };
94 }; 86 };
95 87
96 CPU3: cpu@300 { 88 CPU3: cpu@300 {
97 device_type = "cpu"; 89 device_type = "cpu";
98 compatible = "qcom,kry 90 compatible = "qcom,kryo";
99 reg = <0x0 0x300>; 91 reg = <0x0 0x300>;
100 enable-method = "psci" 92 enable-method = "psci";
101 qcom,freq-domain = <&c 93 qcom,freq-domain = <&cpufreq_hw 0>;
102 next-level-cache = <&L 94 next-level-cache = <&L2_3>;
103 capacity-dmips-mhz = < <<
104 dynamic-power-coeffici <<
105 L2_3: l2-cache { 95 L2_3: l2-cache {
106 compatible = " 96 compatible = "cache";
107 cache-level = 97 cache-level = <2>;
108 cache-unified; 98 cache-unified;
109 next-level-cac 99 next-level-cache = <&L3_0>;
110 }; 100 };
111 }; 101 };
112 102
113 CPU4: cpu@10000 { 103 CPU4: cpu@10000 {
114 device_type = "cpu"; 104 device_type = "cpu";
115 compatible = "qcom,kry 105 compatible = "qcom,kryo";
116 reg = <0x0 0x10000>; 106 reg = <0x0 0x10000>;
117 enable-method = "psci" 107 enable-method = "psci";
118 qcom,freq-domain = <&c 108 qcom,freq-domain = <&cpufreq_hw 1>;
119 next-level-cache = <&L 109 next-level-cache = <&L2_4>;
120 capacity-dmips-mhz = < <<
121 dynamic-power-coeffici <<
122 L2_4: l2-cache { 110 L2_4: l2-cache {
123 compatible = " 111 compatible = "cache";
124 cache-level = 112 cache-level = <2>;
125 cache-unified; 113 cache-unified;
126 next-level-cac 114 next-level-cache = <&L3_1>;
127 L3_1: l3-cache 115 L3_1: l3-cache {
128 compat 116 compatible = "cache";
129 cache- 117 cache-level = <3>;
130 cache- 118 cache-unified;
131 }; 119 };
132 120
133 }; 121 };
134 }; 122 };
135 123
136 CPU5: cpu@10100 { 124 CPU5: cpu@10100 {
137 device_type = "cpu"; 125 device_type = "cpu";
138 compatible = "qcom,kry 126 compatible = "qcom,kryo";
139 reg = <0x0 0x10100>; 127 reg = <0x0 0x10100>;
140 enable-method = "psci" 128 enable-method = "psci";
141 qcom,freq-domain = <&c 129 qcom,freq-domain = <&cpufreq_hw 1>;
142 next-level-cache = <&L 130 next-level-cache = <&L2_5>;
143 capacity-dmips-mhz = < <<
144 dynamic-power-coeffici <<
145 L2_5: l2-cache { 131 L2_5: l2-cache {
146 compatible = " 132 compatible = "cache";
147 cache-level = 133 cache-level = <2>;
148 cache-unified; 134 cache-unified;
149 next-level-cac 135 next-level-cache = <&L3_1>;
150 }; 136 };
151 }; 137 };
152 138
153 CPU6: cpu@10200 { 139 CPU6: cpu@10200 {
154 device_type = "cpu"; 140 device_type = "cpu";
155 compatible = "qcom,kry 141 compatible = "qcom,kryo";
156 reg = <0x0 0x10200>; 142 reg = <0x0 0x10200>;
157 enable-method = "psci" 143 enable-method = "psci";
158 qcom,freq-domain = <&c 144 qcom,freq-domain = <&cpufreq_hw 1>;
159 next-level-cache = <&L 145 next-level-cache = <&L2_6>;
160 capacity-dmips-mhz = < <<
161 dynamic-power-coeffici <<
162 L2_6: l2-cache { 146 L2_6: l2-cache {
163 compatible = " 147 compatible = "cache";
164 cache-level = 148 cache-level = <2>;
165 cache-unified; 149 cache-unified;
166 next-level-cac 150 next-level-cache = <&L3_1>;
167 }; 151 };
168 }; 152 };
169 153
170 CPU7: cpu@10300 { 154 CPU7: cpu@10300 {
171 device_type = "cpu"; 155 device_type = "cpu";
172 compatible = "qcom,kry 156 compatible = "qcom,kryo";
173 reg = <0x0 0x10300>; 157 reg = <0x0 0x10300>;
174 enable-method = "psci" 158 enable-method = "psci";
175 qcom,freq-domain = <&c 159 qcom,freq-domain = <&cpufreq_hw 1>;
176 next-level-cache = <&L 160 next-level-cache = <&L2_7>;
177 capacity-dmips-mhz = < <<
178 dynamic-power-coeffici <<
179 L2_7: l2-cache { 161 L2_7: l2-cache {
180 compatible = " 162 compatible = "cache";
181 cache-level = 163 cache-level = <2>;
182 cache-unified; 164 cache-unified;
183 next-level-cac 165 next-level-cache = <&L3_1>;
184 }; 166 };
185 }; 167 };
186 168
187 cpu-map { 169 cpu-map {
188 cluster0 { 170 cluster0 {
189 core0 { 171 core0 {
190 cpu = 172 cpu = <&CPU0>;
191 }; 173 };
192 174
193 core1 { 175 core1 {
194 cpu = 176 cpu = <&CPU1>;
195 }; 177 };
196 178
197 core2 { 179 core2 {
198 cpu = 180 cpu = <&CPU2>;
199 }; 181 };
200 182
201 core3 { 183 core3 {
202 cpu = 184 cpu = <&CPU3>;
203 }; 185 };
204 }; 186 };
205 187
206 cluster1 { 188 cluster1 {
207 core0 { 189 core0 {
208 cpu = 190 cpu = <&CPU4>;
209 }; 191 };
210 192
211 core1 { 193 core1 {
212 cpu = 194 cpu = <&CPU5>;
213 }; 195 };
214 196
215 core2 { 197 core2 {
216 cpu = 198 cpu = <&CPU6>;
217 }; 199 };
218 200
219 core3 { 201 core3 {
220 cpu = 202 cpu = <&CPU7>;
221 }; 203 };
222 }; 204 };
223 }; 205 };
224 <<
225 idle-states { <<
226 entry-method = "psci"; <<
227 <<
228 GOLD_CPU_SLEEP_0: cpu- <<
229 compatible = " <<
230 idle-state-nam <<
231 arm,psci-suspe <<
232 entry-latency- <<
233 exit-latency-u <<
234 min-residency- <<
235 local-timer-st <<
236 }; <<
237 <<
238 GOLD_RAIL_CPU_SLEEP_0: <<
239 compatible = " <<
240 idle-state-nam <<
241 arm,psci-suspe <<
242 entry-latency- <<
243 exit-latency-u <<
244 min-residency- <<
245 local-timer-st <<
246 }; <<
247 }; <<
248 <<
249 domain-idle-states { <<
250 CLUSTER_SLEEP_GOLD: cl <<
251 compatible = " <<
252 arm,psci-suspe <<
253 entry-latency- <<
254 exit-latency-u <<
255 min-residency- <<
256 }; <<
257 <<
258 CLUSTER_SLEEP_APSS_RSC <<
259 compatible = " <<
260 arm,psci-suspe <<
261 entry-latency- <<
262 exit-latency-u <<
263 min-residency- <<
264 }; <<
265 }; <<
266 }; 206 };
267 207
268 dummy-sink { 208 dummy-sink {
269 compatible = "arm,coresight-du 209 compatible = "arm,coresight-dummy-sink";
270 210
271 in-ports { 211 in-ports {
272 port { 212 port {
273 eud_in: endpoi 213 eud_in: endpoint {
274 remote 214 remote-endpoint =
275 <&swao 215 <&swao_rep_out1>;
276 }; 216 };
277 }; 217 };
278 }; 218 };
279 }; 219 };
280 220
281 firmware { 221 firmware {
282 scm { 222 scm {
283 compatible = "qcom,scm 223 compatible = "qcom,scm-sa8775p", "qcom,scm";
284 memory-region = <&tz_f 224 memory-region = <&tz_ffi_mem>;
285 }; 225 };
286 }; 226 };
287 227
288 aggre1_noc: interconnect-aggre1-noc { 228 aggre1_noc: interconnect-aggre1-noc {
289 compatible = "qcom,sa8775p-agg 229 compatible = "qcom,sa8775p-aggre1-noc";
290 #interconnect-cells = <2>; 230 #interconnect-cells = <2>;
291 qcom,bcm-voters = <&apps_bcm_v 231 qcom,bcm-voters = <&apps_bcm_voter>;
292 }; 232 };
293 233
294 aggre2_noc: interconnect-aggre2-noc { 234 aggre2_noc: interconnect-aggre2-noc {
295 compatible = "qcom,sa8775p-agg 235 compatible = "qcom,sa8775p-aggre2-noc";
296 #interconnect-cells = <2>; 236 #interconnect-cells = <2>;
297 qcom,bcm-voters = <&apps_bcm_v 237 qcom,bcm-voters = <&apps_bcm_voter>;
298 }; 238 };
299 239
300 clk_virt: interconnect-clk-virt { 240 clk_virt: interconnect-clk-virt {
301 compatible = "qcom,sa8775p-clk 241 compatible = "qcom,sa8775p-clk-virt";
302 #interconnect-cells = <2>; 242 #interconnect-cells = <2>;
303 qcom,bcm-voters = <&apps_bcm_v 243 qcom,bcm-voters = <&apps_bcm_voter>;
304 }; 244 };
305 245
306 config_noc: interconnect-config-noc { 246 config_noc: interconnect-config-noc {
307 compatible = "qcom,sa8775p-con 247 compatible = "qcom,sa8775p-config-noc";
308 #interconnect-cells = <2>; 248 #interconnect-cells = <2>;
309 qcom,bcm-voters = <&apps_bcm_v 249 qcom,bcm-voters = <&apps_bcm_voter>;
310 }; 250 };
311 251
312 dc_noc: interconnect-dc-noc { 252 dc_noc: interconnect-dc-noc {
313 compatible = "qcom,sa8775p-dc- 253 compatible = "qcom,sa8775p-dc-noc";
314 #interconnect-cells = <2>; 254 #interconnect-cells = <2>;
315 qcom,bcm-voters = <&apps_bcm_v 255 qcom,bcm-voters = <&apps_bcm_voter>;
316 }; 256 };
317 257
318 gem_noc: interconnect-gem-noc { 258 gem_noc: interconnect-gem-noc {
319 compatible = "qcom,sa8775p-gem 259 compatible = "qcom,sa8775p-gem-noc";
320 #interconnect-cells = <2>; 260 #interconnect-cells = <2>;
321 qcom,bcm-voters = <&apps_bcm_v 261 qcom,bcm-voters = <&apps_bcm_voter>;
322 }; 262 };
323 263
324 gpdsp_anoc: interconnect-gpdsp-anoc { 264 gpdsp_anoc: interconnect-gpdsp-anoc {
325 compatible = "qcom,sa8775p-gpd 265 compatible = "qcom,sa8775p-gpdsp-anoc";
326 #interconnect-cells = <2>; 266 #interconnect-cells = <2>;
327 qcom,bcm-voters = <&apps_bcm_v 267 qcom,bcm-voters = <&apps_bcm_voter>;
328 }; 268 };
329 269
330 lpass_ag_noc: interconnect-lpass-ag-no 270 lpass_ag_noc: interconnect-lpass-ag-noc {
331 compatible = "qcom,sa8775p-lpa 271 compatible = "qcom,sa8775p-lpass-ag-noc";
332 #interconnect-cells = <2>; 272 #interconnect-cells = <2>;
333 qcom,bcm-voters = <&apps_bcm_v 273 qcom,bcm-voters = <&apps_bcm_voter>;
334 }; 274 };
335 275
336 mc_virt: interconnect-mc-virt { 276 mc_virt: interconnect-mc-virt {
337 compatible = "qcom,sa8775p-mc- 277 compatible = "qcom,sa8775p-mc-virt";
338 #interconnect-cells = <2>; 278 #interconnect-cells = <2>;
339 qcom,bcm-voters = <&apps_bcm_v 279 qcom,bcm-voters = <&apps_bcm_voter>;
340 }; 280 };
341 281
342 mmss_noc: interconnect-mmss-noc { 282 mmss_noc: interconnect-mmss-noc {
343 compatible = "qcom,sa8775p-mms 283 compatible = "qcom,sa8775p-mmss-noc";
344 #interconnect-cells = <2>; 284 #interconnect-cells = <2>;
345 qcom,bcm-voters = <&apps_bcm_v 285 qcom,bcm-voters = <&apps_bcm_voter>;
346 }; 286 };
347 287
348 nspa_noc: interconnect-nspa-noc { 288 nspa_noc: interconnect-nspa-noc {
349 compatible = "qcom,sa8775p-nsp 289 compatible = "qcom,sa8775p-nspa-noc";
350 #interconnect-cells = <2>; 290 #interconnect-cells = <2>;
351 qcom,bcm-voters = <&apps_bcm_v 291 qcom,bcm-voters = <&apps_bcm_voter>;
352 }; 292 };
353 293
354 nspb_noc: interconnect-nspb-noc { 294 nspb_noc: interconnect-nspb-noc {
355 compatible = "qcom,sa8775p-nsp 295 compatible = "qcom,sa8775p-nspb-noc";
356 #interconnect-cells = <2>; 296 #interconnect-cells = <2>;
357 qcom,bcm-voters = <&apps_bcm_v 297 qcom,bcm-voters = <&apps_bcm_voter>;
358 }; 298 };
359 299
360 pcie_anoc: interconnect-pcie-anoc { 300 pcie_anoc: interconnect-pcie-anoc {
361 compatible = "qcom,sa8775p-pci 301 compatible = "qcom,sa8775p-pcie-anoc";
362 #interconnect-cells = <2>; 302 #interconnect-cells = <2>;
363 qcom,bcm-voters = <&apps_bcm_v 303 qcom,bcm-voters = <&apps_bcm_voter>;
364 }; 304 };
365 305
366 system_noc: interconnect-system-noc { 306 system_noc: interconnect-system-noc {
367 compatible = "qcom,sa8775p-sys 307 compatible = "qcom,sa8775p-system-noc";
368 #interconnect-cells = <2>; 308 #interconnect-cells = <2>;
369 qcom,bcm-voters = <&apps_bcm_v 309 qcom,bcm-voters = <&apps_bcm_voter>;
370 }; 310 };
371 311
372 /* Will be updated by the bootloader. 312 /* Will be updated by the bootloader. */
373 memory@80000000 { 313 memory@80000000 {
374 device_type = "memory"; 314 device_type = "memory";
375 reg = <0x0 0x80000000 0x0 0x0> 315 reg = <0x0 0x80000000 0x0 0x0>;
376 }; 316 };
377 317
378 qup_opp_table_100mhz: opp-table-qup100 318 qup_opp_table_100mhz: opp-table-qup100mhz {
379 compatible = "operating-points 319 compatible = "operating-points-v2";
380 320
381 opp-100000000 { 321 opp-100000000 {
382 opp-hz = /bits/ 64 <10 322 opp-hz = /bits/ 64 <100000000>;
383 required-opps = <&rpmh 323 required-opps = <&rpmhpd_opp_svs_l1>;
384 }; 324 };
385 }; 325 };
386 326
387 pmu { 327 pmu {
388 compatible = "arm,armv8-pmuv3" 328 compatible = "arm,armv8-pmuv3";
389 interrupts = <GIC_PPI 7 IRQ_TY 329 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
390 }; 330 };
391 331
392 psci { 332 psci {
393 compatible = "arm,psci-1.0"; 333 compatible = "arm,psci-1.0";
394 method = "smc"; 334 method = "smc";
395 <<
396 CPU_PD0: power-domain-cpu0 { <<
397 #power-domain-cells = <<
398 power-domains = <&CLUS <<
399 domain-idle-states = < <<
400 < <<
401 }; <<
402 <<
403 CPU_PD1: power-domain-cpu1 { <<
404 #power-domain-cells = <<
405 power-domains = <&CLUS <<
406 domain-idle-states = < <<
407 < <<
408 }; <<
409 <<
410 CPU_PD2: power-domain-cpu2 { <<
411 #power-domain-cells = <<
412 power-domains = <&CLUS <<
413 domain-idle-states = < <<
414 < <<
415 }; <<
416 <<
417 CPU_PD3: power-domain-cpu3 { <<
418 #power-domain-cells = <<
419 power-domains = <&CLUS <<
420 domain-idle-states = < <<
421 < <<
422 }; <<
423 <<
424 CPU_PD4: power-domain-cpu4 { <<
425 #power-domain-cells = <<
426 power-domains = <&CLUS <<
427 domain-idle-states = < <<
428 < <<
429 }; <<
430 <<
431 CPU_PD5: power-domain-cpu5 { <<
432 #power-domain-cells = <<
433 power-domains = <&CLUS <<
434 domain-idle-states = < <<
435 < <<
436 }; <<
437 <<
438 CPU_PD6: power-domain-cpu6 { <<
439 #power-domain-cells = <<
440 power-domains = <&CLUS <<
441 domain-idle-states = < <<
442 < <<
443 }; <<
444 <<
445 CPU_PD7: power-domain-cpu7 { <<
446 #power-domain-cells = <<
447 power-domains = <&CLUS <<
448 domain-idle-states = < <<
449 < <<
450 }; <<
451 <<
452 CLUSTER_0_PD: power-domain-clu <<
453 #power-domain-cells = <<
454 power-domains = <&CLUS <<
455 domain-idle-states = < <<
456 }; <<
457 <<
458 CLUSTER_1_PD: power-domain-clu <<
459 #power-domain-cells = <<
460 power-domains = <&CLUS <<
461 domain-idle-states = < <<
462 }; <<
463 <<
464 CLUSTER_2_PD: power-domain-clu <<
465 #power-domain-cells = <<
466 domain-idle-states = < <<
467 }; <<
468 }; 335 };
469 336
470 reserved-memory { 337 reserved-memory {
471 #address-cells = <2>; 338 #address-cells = <2>;
472 #size-cells = <2>; 339 #size-cells = <2>;
473 ranges; 340 ranges;
474 341
475 sail_ss_mem: sail-ss@80000000 342 sail_ss_mem: sail-ss@80000000 {
476 reg = <0x0 0x80000000 343 reg = <0x0 0x80000000 0x0 0x10000000>;
477 no-map; 344 no-map;
478 }; 345 };
479 346
480 hyp_mem: hyp@90000000 { 347 hyp_mem: hyp@90000000 {
481 reg = <0x0 0x90000000 348 reg = <0x0 0x90000000 0x0 0x600000>;
482 no-map; 349 no-map;
483 }; 350 };
484 351
485 xbl_boot_mem: xbl-boot@9060000 352 xbl_boot_mem: xbl-boot@90600000 {
486 reg = <0x0 0x90600000 353 reg = <0x0 0x90600000 0x0 0x200000>;
487 no-map; 354 no-map;
488 }; 355 };
489 356
490 aop_image_mem: aop-image@90800 357 aop_image_mem: aop-image@90800000 {
491 reg = <0x0 0x90800000 358 reg = <0x0 0x90800000 0x0 0x60000>;
492 no-map; 359 no-map;
493 }; 360 };
494 361
495 aop_cmd_db_mem: aop-cmd-db@908 362 aop_cmd_db_mem: aop-cmd-db@90860000 {
496 compatible = "qcom,cmd 363 compatible = "qcom,cmd-db";
497 reg = <0x0 0x90860000 364 reg = <0x0 0x90860000 0x0 0x20000>;
498 no-map; 365 no-map;
499 }; 366 };
500 367
501 uefi_log: uefi-log@908b0000 { 368 uefi_log: uefi-log@908b0000 {
502 reg = <0x0 0x908b0000 369 reg = <0x0 0x908b0000 0x0 0x10000>;
503 no-map; 370 no-map;
504 }; 371 };
505 372
506 ddr_training_checksum: ddr-tra 373 ddr_training_checksum: ddr-training-checksum@908c0000 {
507 reg = <0x0 0x908c0000 374 reg = <0x0 0x908c0000 0x0 0x1000>;
508 no-map; 375 no-map;
509 }; 376 };
510 377
511 reserved_mem: reserved@908f000 378 reserved_mem: reserved@908f0000 {
512 reg = <0x0 0x908f0000 379 reg = <0x0 0x908f0000 0x0 0xe000>;
513 no-map; 380 no-map;
514 }; 381 };
515 382
516 secdata_apss_mem: secdata-apss 383 secdata_apss_mem: secdata-apss@908fe000 {
517 reg = <0x0 0x908fe000 384 reg = <0x0 0x908fe000 0x0 0x2000>;
518 no-map; 385 no-map;
519 }; 386 };
520 387
521 smem_mem: smem@90900000 { 388 smem_mem: smem@90900000 {
522 compatible = "qcom,sme 389 compatible = "qcom,smem";
523 reg = <0x0 0x90900000 390 reg = <0x0 0x90900000 0x0 0x200000>;
524 no-map; 391 no-map;
525 hwlocks = <&tcsr_mutex 392 hwlocks = <&tcsr_mutex 3>;
526 }; 393 };
527 394
528 tz_sail_mailbox_mem: tz-sail-m 395 tz_sail_mailbox_mem: tz-sail-mailbox@90c00000 {
529 reg = <0x0 0x90c00000 396 reg = <0x0 0x90c00000 0x0 0x100000>;
530 no-map; 397 no-map;
531 }; 398 };
532 399
533 sail_mailbox_mem: sail-ss@90d0 400 sail_mailbox_mem: sail-ss@90d00000 {
534 reg = <0x0 0x90d00000 401 reg = <0x0 0x90d00000 0x0 0x100000>;
535 no-map; 402 no-map;
536 }; 403 };
537 404
538 sail_ota_mem: sail-ss@90e00000 405 sail_ota_mem: sail-ss@90e00000 {
539 reg = <0x0 0x90e00000 406 reg = <0x0 0x90e00000 0x0 0x300000>;
540 no-map; 407 no-map;
541 }; 408 };
542 409
543 aoss_backup_mem: aoss-backup@9 410 aoss_backup_mem: aoss-backup@91b00000 {
544 reg = <0x0 0x91b00000 411 reg = <0x0 0x91b00000 0x0 0x40000>;
545 no-map; 412 no-map;
546 }; 413 };
547 414
548 cpucp_backup_mem: cpucp-backup 415 cpucp_backup_mem: cpucp-backup@91b40000 {
549 reg = <0x0 0x91b40000 416 reg = <0x0 0x91b40000 0x0 0x40000>;
550 no-map; 417 no-map;
551 }; 418 };
552 419
553 tz_config_backup_mem: tz-confi 420 tz_config_backup_mem: tz-config-backup@91b80000 {
554 reg = <0x0 0x91b80000 421 reg = <0x0 0x91b80000 0x0 0x10000>;
555 no-map; 422 no-map;
556 }; 423 };
557 424
558 ddr_training_data_mem: ddr-tra 425 ddr_training_data_mem: ddr-training-data@91b90000 {
559 reg = <0x0 0x91b90000 426 reg = <0x0 0x91b90000 0x0 0x10000>;
560 no-map; 427 no-map;
561 }; 428 };
562 429
563 cdt_data_backup_mem: cdt-data- 430 cdt_data_backup_mem: cdt-data-backup@91ba0000 {
564 reg = <0x0 0x91ba0000 431 reg = <0x0 0x91ba0000 0x0 0x1000>;
565 no-map; 432 no-map;
566 }; 433 };
567 434
568 tz_ffi_mem: tz-ffi@91c00000 { 435 tz_ffi_mem: tz-ffi@91c00000 {
569 compatible = "shared-d 436 compatible = "shared-dma-pool";
570 reg = <0x0 0x91c00000 437 reg = <0x0 0x91c00000 0x0 0x1400000>;
571 no-map; 438 no-map;
572 }; 439 };
573 440
574 lpass_machine_learning_mem: lp 441 lpass_machine_learning_mem: lpass-machine-learning@93b00000 {
575 reg = <0x0 0x93b00000 442 reg = <0x0 0x93b00000 0x0 0xf00000>;
576 no-map; 443 no-map;
577 }; 444 };
578 445
579 adsp_rpc_remote_heap_mem: adsp 446 adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@94a00000 {
580 reg = <0x0 0x94a00000 447 reg = <0x0 0x94a00000 0x0 0x800000>;
581 no-map; 448 no-map;
582 }; 449 };
583 450
584 pil_camera_mem: pil-camera@952 451 pil_camera_mem: pil-camera@95200000 {
585 reg = <0x0 0x95200000 452 reg = <0x0 0x95200000 0x0 0x500000>;
586 no-map; 453 no-map;
587 }; 454 };
588 455
589 pil_adsp_mem: pil-adsp@95c0000 456 pil_adsp_mem: pil-adsp@95c00000 {
590 reg = <0x0 0x95c00000 457 reg = <0x0 0x95c00000 0x0 0x1e00000>;
591 no-map; 458 no-map;
592 }; 459 };
593 460
594 pil_gdsp0_mem: pil-gdsp0@97b00 461 pil_gdsp0_mem: pil-gdsp0@97b00000 {
595 reg = <0x0 0x97b00000 462 reg = <0x0 0x97b00000 0x0 0x1e00000>;
596 no-map; 463 no-map;
597 }; 464 };
598 465
599 pil_gdsp1_mem: pil-gdsp1@99900 466 pil_gdsp1_mem: pil-gdsp1@99900000 {
600 reg = <0x0 0x99900000 467 reg = <0x0 0x99900000 0x0 0x1e00000>;
601 no-map; 468 no-map;
602 }; 469 };
603 470
604 pil_cdsp0_mem: pil-cdsp0@9b800 471 pil_cdsp0_mem: pil-cdsp0@9b800000 {
605 reg = <0x0 0x9b800000 472 reg = <0x0 0x9b800000 0x0 0x1e00000>;
606 no-map; 473 no-map;
607 }; 474 };
608 475
609 pil_gpu_mem: pil-gpu@9d600000 476 pil_gpu_mem: pil-gpu@9d600000 {
610 reg = <0x0 0x9d600000 477 reg = <0x0 0x9d600000 0x0 0x2000>;
611 no-map; 478 no-map;
612 }; 479 };
613 480
614 pil_cdsp1_mem: pil-cdsp1@9d700 481 pil_cdsp1_mem: pil-cdsp1@9d700000 {
615 reg = <0x0 0x9d700000 482 reg = <0x0 0x9d700000 0x0 0x1e00000>;
616 no-map; 483 no-map;
617 }; 484 };
618 485
619 pil_cvp_mem: pil-cvp@9f500000 486 pil_cvp_mem: pil-cvp@9f500000 {
620 reg = <0x0 0x9f500000 487 reg = <0x0 0x9f500000 0x0 0x700000>;
621 no-map; 488 no-map;
622 }; 489 };
623 490
624 pil_video_mem: pil-video@9fc00 491 pil_video_mem: pil-video@9fc00000 {
625 reg = <0x0 0x9fc00000 492 reg = <0x0 0x9fc00000 0x0 0x700000>;
626 no-map; 493 no-map;
627 }; 494 };
628 495
629 audio_mdf_mem: audio-mdf-regio 496 audio_mdf_mem: audio-mdf-region@ae000000 {
630 reg = <0x0 0xae000000 497 reg = <0x0 0xae000000 0x0 0x1000000>;
631 no-map; 498 no-map;
632 }; 499 };
633 500
634 firmware_mem: firmware-region@ 501 firmware_mem: firmware-region@b0000000 {
635 reg = <0x0 0xb0000000 502 reg = <0x0 0xb0000000 0x0 0x800000>;
636 no-map; 503 no-map;
637 }; 504 };
638 505
639 hyptz_reserved_mem: hyptz-rese 506 hyptz_reserved_mem: hyptz-reserved@beb00000 {
640 reg = <0x0 0xbeb00000 507 reg = <0x0 0xbeb00000 0x0 0x11500000>;
641 no-map; 508 no-map;
642 }; 509 };
643 510
644 scmi_mem: scmi-region@d0000000 511 scmi_mem: scmi-region@d0000000 {
645 reg = <0x0 0xd0000000 512 reg = <0x0 0xd0000000 0x0 0x40000>;
646 no-map; 513 no-map;
647 }; 514 };
648 515
649 firmware_logs_mem: firmware-lo 516 firmware_logs_mem: firmware-logs@d0040000 {
650 reg = <0x0 0xd0040000 517 reg = <0x0 0xd0040000 0x0 0x10000>;
651 no-map; 518 no-map;
652 }; 519 };
653 520
654 firmware_audio_mem: firmware-a 521 firmware_audio_mem: firmware-audio@d0050000 {
655 reg = <0x0 0xd0050000 522 reg = <0x0 0xd0050000 0x0 0x4000>;
656 no-map; 523 no-map;
657 }; 524 };
658 525
659 firmware_reserved_mem: firmwar 526 firmware_reserved_mem: firmware-reserved@d0054000 {
660 reg = <0x0 0xd0054000 527 reg = <0x0 0xd0054000 0x0 0x9c000>;
661 no-map; 528 no-map;
662 }; 529 };
663 530
664 firmware_quantum_test_mem: fir 531 firmware_quantum_test_mem: firmware-quantum-test@d00f0000 {
665 reg = <0x0 0xd00f0000 532 reg = <0x0 0xd00f0000 0x0 0x10000>;
666 no-map; 533 no-map;
667 }; 534 };
668 535
669 tags_mem: tags@d0100000 { 536 tags_mem: tags@d0100000 {
670 reg = <0x0 0xd0100000 537 reg = <0x0 0xd0100000 0x0 0x1200000>;
671 no-map; 538 no-map;
672 }; 539 };
673 540
674 qtee_mem: qtee@d1300000 { 541 qtee_mem: qtee@d1300000 {
675 reg = <0x0 0xd1300000 542 reg = <0x0 0xd1300000 0x0 0x500000>;
676 no-map; 543 no-map;
677 }; 544 };
678 545
679 deepsleep_backup_mem: deepslee 546 deepsleep_backup_mem: deepsleep-backup@d1800000 {
680 reg = <0x0 0xd1800000 547 reg = <0x0 0xd1800000 0x0 0x100000>;
681 no-map; 548 no-map;
682 }; 549 };
683 550
684 trusted_apps_mem: trusted-apps 551 trusted_apps_mem: trusted-apps@d1900000 {
685 reg = <0x0 0xd1900000 552 reg = <0x0 0xd1900000 0x0 0x3800000>;
686 no-map; 553 no-map;
687 }; 554 };
688 555
689 tz_stat_mem: tz-stat@db100000 556 tz_stat_mem: tz-stat@db100000 {
690 reg = <0x0 0xdb100000 557 reg = <0x0 0xdb100000 0x0 0x100000>;
691 no-map; 558 no-map;
692 }; 559 };
693 560
694 cpucp_fw_mem: cpucp-fw@db20000 561 cpucp_fw_mem: cpucp-fw@db200000 {
695 reg = <0x0 0xdb200000 562 reg = <0x0 0xdb200000 0x0 0x100000>;
696 no-map; 563 no-map;
697 }; 564 };
698 }; 565 };
699 566
700 smp2p-adsp { <<
701 compatible = "qcom,smp2p"; <<
702 qcom,smem = <443>, <429>; <<
703 interrupts-extended = <&ipcc I <<
704 I <<
705 I <<
706 mboxes = <&ipcc IPCC_CLIENT_LP <<
707 <<
708 qcom,local-pid = <0>; <<
709 qcom,remote-pid = <2>; <<
710 <<
711 smp2p_adsp_out: master-kernel <<
712 qcom,entry-name = "mas <<
713 #qcom,smem-state-cells <<
714 }; <<
715 <<
716 smp2p_adsp_in: slave-kernel { <<
717 qcom,entry-name = "sla <<
718 interrupt-controller; <<
719 #interrupt-cells = <2> <<
720 }; <<
721 }; <<
722 <<
723 smp2p-cdsp0 { <<
724 compatible = "qcom,smp2p"; <<
725 qcom,smem = <94>, <432>; <<
726 interrupts-extended = <&ipcc I <<
727 I <<
728 I <<
729 mboxes = <&ipcc IPCC_CLIENT_CD <<
730 <<
731 qcom,local-pid = <0>; <<
732 qcom,remote-pid = <5>; <<
733 <<
734 smp2p_cdsp0_out: master-kernel <<
735 qcom,entry-name = "mas <<
736 #qcom,smem-state-cells <<
737 }; <<
738 <<
739 smp2p_cdsp0_in: slave-kernel { <<
740 qcom,entry-name = "sla <<
741 interrupt-controller; <<
742 #interrupt-cells = <2> <<
743 }; <<
744 }; <<
745 <<
746 smp2p-cdsp1 { <<
747 compatible = "qcom,smp2p"; <<
748 qcom,smem = <617>, <616>; <<
749 interrupts-extended = <&ipcc I <<
750 I <<
751 I <<
752 mboxes = <&ipcc IPCC_CLIENT_NS <<
753 <<
754 qcom,local-pid = <0>; <<
755 qcom,remote-pid = <12>; <<
756 <<
757 smp2p_cdsp1_out: master-kernel <<
758 qcom,entry-name = "mas <<
759 #qcom,smem-state-cells <<
760 }; <<
761 <<
762 smp2p_cdsp1_in: slave-kernel { <<
763 qcom,entry-name = "sla <<
764 interrupt-controller; <<
765 #interrupt-cells = <2> <<
766 }; <<
767 }; <<
768 <<
769 smp2p-gpdsp0 { <<
770 compatible = "qcom,smp2p"; <<
771 qcom,smem = <617>, <616>; <<
772 interrupts-extended = <&ipcc I <<
773 I <<
774 I <<
775 mboxes = <&ipcc IPCC_CLIENT_GP <<
776 <<
777 qcom,local-pid = <0>; <<
778 qcom,remote-pid = <17>; <<
779 <<
780 smp2p_gpdsp0_out: master-kerne <<
781 qcom,entry-name = "mas <<
782 #qcom,smem-state-cells <<
783 }; <<
784 <<
785 smp2p_gpdsp0_in: slave-kernel <<
786 qcom,entry-name = "sla <<
787 interrupt-controller; <<
788 #interrupt-cells = <2> <<
789 }; <<
790 }; <<
791 <<
792 smp2p-gpdsp1 { <<
793 compatible = "qcom,smp2p"; <<
794 qcom,smem = <617>, <616>; <<
795 interrupts-extended = <&ipcc I <<
796 I <<
797 I <<
798 mboxes = <&ipcc IPCC_CLIENT_GP <<
799 <<
800 qcom,local-pid = <0>; <<
801 qcom,remote-pid = <18>; <<
802 <<
803 smp2p_gpdsp1_out: master-kerne <<
804 qcom,entry-name = "mas <<
805 #qcom,smem-state-cells <<
806 }; <<
807 <<
808 smp2p_gpdsp1_in: slave-kernel <<
809 qcom,entry-name = "sla <<
810 interrupt-controller; <<
811 #interrupt-cells = <2> <<
812 }; <<
813 }; <<
814 <<
815 soc: soc@0 { 567 soc: soc@0 {
816 compatible = "simple-bus"; 568 compatible = "simple-bus";
817 #address-cells = <2>; 569 #address-cells = <2>;
818 #size-cells = <2>; 570 #size-cells = <2>;
819 ranges = <0 0 0 0 0x10 0>; 571 ranges = <0 0 0 0 0x10 0>;
820 572
821 gcc: clock-controller@100000 { 573 gcc: clock-controller@100000 {
822 compatible = "qcom,sa8 574 compatible = "qcom,sa8775p-gcc";
823 reg = <0x0 0x00100000 575 reg = <0x0 0x00100000 0x0 0xc7018>;
824 #clock-cells = <1>; 576 #clock-cells = <1>;
825 #reset-cells = <1>; 577 #reset-cells = <1>;
826 #power-domain-cells = 578 #power-domain-cells = <1>;
827 clocks = <&rpmhcc RPMH 579 clocks = <&rpmhcc RPMH_CXO_CLK>,
828 <&sleep_clk>, 580 <&sleep_clk>,
829 <0>, 581 <0>,
830 <0>, 582 <0>,
831 <0>, 583 <0>,
832 <&usb_0_qmpph 584 <&usb_0_qmpphy>,
833 <&usb_1_qmpph 585 <&usb_1_qmpphy>,
834 <0>, 586 <0>,
835 <0>, 587 <0>,
836 <0>, 588 <0>,
837 <&pcie0_phy>, 589 <&pcie0_phy>,
838 <&pcie1_phy>, 590 <&pcie1_phy>,
839 <0>, 591 <0>,
840 <0>, 592 <0>,
841 <0>; 593 <0>;
842 power-domains = <&rpmh 594 power-domains = <&rpmhpd SA8775P_CX>;
843 }; 595 };
844 596
845 ipcc: mailbox@408000 { 597 ipcc: mailbox@408000 {
846 compatible = "qcom,sa8 598 compatible = "qcom,sa8775p-ipcc", "qcom,ipcc";
847 reg = <0x0 0x00408000 599 reg = <0x0 0x00408000 0x0 0x1000>;
848 interrupts = <GIC_SPI 600 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
849 interrupt-controller; 601 interrupt-controller;
850 #interrupt-cells = <3> 602 #interrupt-cells = <3>;
851 #mbox-cells = <2>; 603 #mbox-cells = <2>;
852 }; 604 };
853 605
854 qupv3_id_2: geniqup@8c0000 { 606 qupv3_id_2: geniqup@8c0000 {
855 compatible = "qcom,gen 607 compatible = "qcom,geni-se-qup";
856 reg = <0x0 0x008c0000 608 reg = <0x0 0x008c0000 0x0 0x6000>;
857 ranges; 609 ranges;
858 clocks = <&gcc GCC_QUP 610 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
859 <&gcc GCC_QUP 611 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
860 clock-names = "m-ahb", 612 clock-names = "m-ahb", "s-ahb";
861 iommus = <&apps_smmu 0 613 iommus = <&apps_smmu 0x5a3 0x0>;
862 #address-cells = <2>; 614 #address-cells = <2>;
863 #size-cells = <2>; 615 #size-cells = <2>;
864 status = "disabled"; 616 status = "disabled";
865 617
866 i2c14: i2c@880000 { 618 i2c14: i2c@880000 {
867 compatible = " 619 compatible = "qcom,geni-i2c";
868 reg = <0x0 0x8 620 reg = <0x0 0x880000 0x0 0x4000>;
869 #address-cells 621 #address-cells = <1>;
870 #size-cells = 622 #size-cells = <0>;
871 interrupts = < 623 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
872 clocks = <&gcc 624 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
873 clock-names = 625 clock-names = "se";
874 interconnects 626 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
875 627 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
876 628 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
877 629 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
878 630 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
879 631 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
880 interconnect-n 632 interconnect-names = "qup-core",
881 633 "qup-config",
882 634 "qup-memory";
883 power-domains 635 power-domains = <&rpmhpd SA8775P_CX>;
884 status = "disa 636 status = "disabled";
885 }; 637 };
886 638
887 spi14: spi@880000 { 639 spi14: spi@880000 {
888 compatible = " 640 compatible = "qcom,geni-spi";
889 reg = <0x0 0x8 641 reg = <0x0 0x880000 0x0 0x4000>;
890 #address-cells 642 #address-cells = <1>;
891 #size-cells = 643 #size-cells = <0>;
892 interrupts = < 644 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
893 clocks = <&gcc 645 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
894 clock-names = 646 clock-names = "se";
895 interconnects 647 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
896 648 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
897 649 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
898 650 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
899 651 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
900 652 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
901 interconnect-n 653 interconnect-names = "qup-core",
902 654 "qup-config",
903 655 "qup-memory";
904 power-domains 656 power-domains = <&rpmhpd SA8775P_CX>;
905 status = "disa 657 status = "disabled";
906 }; 658 };
907 659
908 i2c15: i2c@884000 { 660 i2c15: i2c@884000 {
909 compatible = " 661 compatible = "qcom,geni-i2c";
910 reg = <0x0 0x8 662 reg = <0x0 0x884000 0x0 0x4000>;
911 #address-cells 663 #address-cells = <1>;
912 #size-cells = 664 #size-cells = <0>;
913 interrupts = < 665 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
914 clocks = <&gcc 666 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
915 clock-names = 667 clock-names = "se";
916 interconnects 668 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
917 669 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
918 670 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
919 671 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
920 672 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
921 673 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
922 interconnect-n 674 interconnect-names = "qup-core",
923 675 "qup-config",
924 676 "qup-memory";
925 power-domains 677 power-domains = <&rpmhpd SA8775P_CX>;
926 status = "disa 678 status = "disabled";
927 }; 679 };
928 680
929 spi15: spi@884000 { 681 spi15: spi@884000 {
930 compatible = " 682 compatible = "qcom,geni-spi";
931 reg = <0x0 0x8 683 reg = <0x0 0x884000 0x0 0x4000>;
932 #address-cells 684 #address-cells = <1>;
933 #size-cells = 685 #size-cells = <0>;
934 interrupts = < 686 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
935 clocks = <&gcc 687 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
936 clock-names = 688 clock-names = "se";
937 interconnects 689 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
938 690 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
939 691 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
940 692 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
941 693 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
942 694 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
943 interconnect-n 695 interconnect-names = "qup-core",
944 696 "qup-config",
945 697 "qup-memory";
946 power-domains 698 power-domains = <&rpmhpd SA8775P_CX>;
947 status = "disa 699 status = "disabled";
948 }; 700 };
949 701
950 i2c16: i2c@888000 { 702 i2c16: i2c@888000 {
951 compatible = " 703 compatible = "qcom,geni-i2c";
952 reg = <0x0 0x8 704 reg = <0x0 0x888000 0x0 0x4000>;
953 #address-cells 705 #address-cells = <1>;
954 #size-cells = 706 #size-cells = <0>;
955 interrupts = < 707 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
956 clocks = <&gcc 708 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
957 clock-names = 709 clock-names = "se";
958 interconnects 710 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
959 711 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
960 712 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
961 713 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
962 714 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
963 715 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
964 interconnect-n 716 interconnect-names = "qup-core",
965 717 "qup-config",
966 718 "qup-memory";
967 power-domains 719 power-domains = <&rpmhpd SA8775P_CX>;
968 status = "disa 720 status = "disabled";
969 }; 721 };
970 722
971 spi16: spi@888000 { 723 spi16: spi@888000 {
972 compatible = " 724 compatible = "qcom,geni-spi";
973 reg = <0x0 0x0 725 reg = <0x0 0x00888000 0x0 0x4000>;
974 interrupts = < 726 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
975 clocks = <&gcc 727 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
976 clock-names = 728 clock-names = "se";
977 interconnects 729 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
978 730 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
979 731 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
980 732 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
981 733 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
982 734 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
983 interconnect-n 735 interconnect-names = "qup-core",
984 736 "qup-config",
985 737 "qup-memory";
986 power-domains 738 power-domains = <&rpmhpd SA8775P_CX>;
987 #address-cells 739 #address-cells = <1>;
988 #size-cells = 740 #size-cells = <0>;
989 status = "disa 741 status = "disabled";
990 }; 742 };
991 743
992 i2c17: i2c@88c000 { 744 i2c17: i2c@88c000 {
993 compatible = " 745 compatible = "qcom,geni-i2c";
994 reg = <0x0 0x8 746 reg = <0x0 0x88c000 0x0 0x4000>;
995 #address-cells 747 #address-cells = <1>;
996 #size-cells = 748 #size-cells = <0>;
997 interrupts = < 749 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
998 clocks = <&gcc 750 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
999 clock-names = 751 clock-names = "se";
1000 interconnects 752 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1001 753 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1002 754 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1003 755 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1004 756 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1005 757 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1006 interconnect- 758 interconnect-names = "qup-core",
1007 759 "qup-config",
1008 760 "qup-memory";
1009 power-domains 761 power-domains = <&rpmhpd SA8775P_CX>;
1010 status = "dis 762 status = "disabled";
1011 }; 763 };
1012 764
1013 spi17: spi@88c000 { 765 spi17: spi@88c000 {
1014 compatible = 766 compatible = "qcom,geni-spi";
1015 reg = <0x0 0x 767 reg = <0x0 0x88c000 0x0 0x4000>;
1016 #address-cell 768 #address-cells = <1>;
1017 #size-cells = 769 #size-cells = <0>;
1018 interrupts = 770 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1019 clocks = <&gc 771 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1020 clock-names = 772 clock-names = "se";
1021 interconnects 773 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1022 774 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1023 775 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1024 776 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1025 777 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1026 778 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1027 interconnect- 779 interconnect-names = "qup-core",
1028 780 "qup-config",
1029 781 "qup-memory";
1030 power-domains 782 power-domains = <&rpmhpd SA8775P_CX>;
1031 status = "dis 783 status = "disabled";
1032 }; 784 };
1033 785
1034 uart17: serial@88c000 786 uart17: serial@88c000 {
1035 compatible = 787 compatible = "qcom,geni-uart";
1036 reg = <0x0 0x 788 reg = <0x0 0x0088c000 0x0 0x4000>;
1037 interrupts = 789 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1038 clocks = <&gc 790 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1039 clock-names = 791 clock-names = "se";
1040 interconnects 792 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1041 793 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1042 794 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1043 795 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
1044 interconnect- 796 interconnect-names = "qup-core", "qup-config";
1045 power-domains 797 power-domains = <&rpmhpd SA8775P_CX>;
1046 status = "dis 798 status = "disabled";
1047 }; 799 };
1048 800
1049 i2c18: i2c@890000 { 801 i2c18: i2c@890000 {
1050 compatible = 802 compatible = "qcom,geni-i2c";
1051 reg = <0x0 0x 803 reg = <0x0 0x00890000 0x0 0x4000>;
1052 interrupts = 804 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1053 clocks = <&gc 805 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1054 clock-names = 806 clock-names = "se";
1055 interconnects 807 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1056 808 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1057 809 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1058 810 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1059 811 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1060 812 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1061 interconnect- 813 interconnect-names = "qup-core",
1062 814 "qup-config",
1063 815 "qup-memory";
1064 power-domains 816 power-domains = <&rpmhpd SA8775P_CX>;
1065 #address-cell 817 #address-cells = <1>;
1066 #size-cells = 818 #size-cells = <0>;
1067 status = "dis 819 status = "disabled";
1068 }; 820 };
1069 821
1070 spi18: spi@890000 { 822 spi18: spi@890000 {
1071 compatible = 823 compatible = "qcom,geni-spi";
1072 reg = <0x0 0x 824 reg = <0x0 0x890000 0x0 0x4000>;
1073 #address-cell 825 #address-cells = <1>;
1074 #size-cells = 826 #size-cells = <0>;
1075 interrupts = 827 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1076 clocks = <&gc 828 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1077 clock-names = 829 clock-names = "se";
1078 interconnects 830 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1079 831 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1080 832 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1081 833 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1082 834 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1083 835 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1084 interconnect- 836 interconnect-names = "qup-core",
1085 837 "qup-config",
1086 838 "qup-memory";
1087 power-domains 839 power-domains = <&rpmhpd SA8775P_CX>;
1088 status = "dis 840 status = "disabled";
1089 }; 841 };
1090 842
1091 i2c19: i2c@894000 { 843 i2c19: i2c@894000 {
1092 compatible = 844 compatible = "qcom,geni-i2c";
1093 reg = <0x0 0x 845 reg = <0x0 0x894000 0x0 0x4000>;
1094 #address-cell 846 #address-cells = <1>;
1095 #size-cells = 847 #size-cells = <0>;
1096 interrupts = 848 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1097 clocks = <&gc 849 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1098 clock-names = 850 clock-names = "se";
1099 interconnects 851 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1100 852 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1101 853 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1102 854 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1103 855 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1104 856 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1105 interconnect- 857 interconnect-names = "qup-core",
1106 858 "qup-config",
1107 859 "qup-memory";
1108 power-domains 860 power-domains = <&rpmhpd SA8775P_CX>;
1109 status = "dis 861 status = "disabled";
1110 }; 862 };
1111 863
1112 spi19: spi@894000 { 864 spi19: spi@894000 {
1113 compatible = 865 compatible = "qcom,geni-spi";
1114 reg = <0x0 0x 866 reg = <0x0 0x894000 0x0 0x4000>;
1115 #address-cell 867 #address-cells = <1>;
1116 #size-cells = 868 #size-cells = <0>;
1117 interrupts = 869 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1118 clocks = <&gc 870 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1119 clock-names = 871 clock-names = "se";
1120 interconnects 872 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1121 873 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1122 874 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1123 875 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1124 876 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1125 877 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1126 interconnect- 878 interconnect-names = "qup-core",
1127 879 "qup-config",
1128 880 "qup-memory";
1129 power-domains 881 power-domains = <&rpmhpd SA8775P_CX>;
1130 status = "dis 882 status = "disabled";
1131 }; 883 };
1132 884
1133 i2c20: i2c@898000 { 885 i2c20: i2c@898000 {
1134 compatible = 886 compatible = "qcom,geni-i2c";
1135 reg = <0x0 0x 887 reg = <0x0 0x898000 0x0 0x4000>;
1136 #address-cell 888 #address-cells = <1>;
1137 #size-cells = 889 #size-cells = <0>;
1138 interrupts = 890 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>;
1139 clocks = <&gc 891 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1140 clock-names = 892 clock-names = "se";
1141 interconnects 893 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1142 894 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1143 895 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1144 896 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1145 897 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1146 898 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1147 interconnect- 899 interconnect-names = "qup-core",
1148 900 "qup-config",
1149 901 "qup-memory";
1150 power-domains 902 power-domains = <&rpmhpd SA8775P_CX>;
1151 status = "dis 903 status = "disabled";
1152 }; 904 };
1153 905
1154 spi20: spi@898000 { 906 spi20: spi@898000 {
1155 compatible = 907 compatible = "qcom,geni-spi";
1156 reg = <0x0 0x 908 reg = <0x0 0x898000 0x0 0x4000>;
1157 #address-cell 909 #address-cells = <1>;
1158 #size-cells = 910 #size-cells = <0>;
1159 interrupts = 911 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>;
1160 clocks = <&gc 912 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1161 clock-names = 913 clock-names = "se";
1162 interconnects 914 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1163 915 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1164 916 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1165 917 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1166 918 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1167 919 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1168 interconnect- 920 interconnect-names = "qup-core",
1169 921 "qup-config",
1170 922 "qup-memory";
1171 power-domains 923 power-domains = <&rpmhpd SA8775P_CX>;
1172 status = "dis 924 status = "disabled";
1173 }; 925 };
1174 }; 926 };
1175 927
1176 qupv3_id_0: geniqup@9c0000 { 928 qupv3_id_0: geniqup@9c0000 {
1177 compatible = "qcom,ge 929 compatible = "qcom,geni-se-qup";
1178 reg = <0x0 0x9c0000 0 930 reg = <0x0 0x9c0000 0x0 0x6000>;
1179 #address-cells = <2>; 931 #address-cells = <2>;
1180 #size-cells = <2>; 932 #size-cells = <2>;
1181 ranges; 933 ranges;
1182 clock-names = "m-ahb" 934 clock-names = "m-ahb", "s-ahb";
1183 clocks = <&gcc GCC_QU 935 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1184 <&gcc GCC_QUP 936 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1185 iommus = <&apps_smmu 937 iommus = <&apps_smmu 0x403 0x0>;
1186 status = "disabled"; 938 status = "disabled";
1187 939
1188 i2c0: i2c@980000 { 940 i2c0: i2c@980000 {
1189 compatible = 941 compatible = "qcom,geni-i2c";
1190 reg = <0x0 0x 942 reg = <0x0 0x980000 0x0 0x4000>;
1191 #address-cell 943 #address-cells = <1>;
1192 #size-cells = 944 #size-cells = <0>;
1193 interrupts = 945 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>;
1194 clocks = <&gc 946 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1195 clock-names = 947 clock-names = "se";
1196 interconnects 948 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1197 949 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1198 950 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1199 951 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
1200 952 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
1201 953 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1202 interconnect- 954 interconnect-names = "qup-core",
1203 955 "qup-config",
1204 956 "qup-memory";
1205 power-domains 957 power-domains = <&rpmhpd SA8775P_CX>;
1206 status = "dis 958 status = "disabled";
1207 }; 959 };
1208 960
1209 spi0: spi@980000 { 961 spi0: spi@980000 {
1210 compatible = 962 compatible = "qcom,geni-spi";
1211 reg = <0x0 0x 963 reg = <0x0 0x980000 0x0 0x4000>;
1212 #address-cell 964 #address-cells = <1>;
1213 #size-cells = 965 #size-cells = <0>;
1214 interrupts = 966 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>;
1215 clocks = <&gc 967 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1216 clock-names = 968 clock-names = "se";
1217 interconnects 969 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1218 970 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1219 971 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1220 972 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
1221 973 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
1222 974 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1223 interconnect- 975 interconnect-names = "qup-core",
1224 976 "qup-config",
1225 977 "qup-memory";
1226 power-domains 978 power-domains = <&rpmhpd SA8775P_CX>;
1227 status = "dis 979 status = "disabled";
1228 }; 980 };
1229 981
1230 i2c1: i2c@984000 { 982 i2c1: i2c@984000 {
1231 compatible = 983 compatible = "qcom,geni-i2c";
1232 reg = <0x0 0x 984 reg = <0x0 0x984000 0x0 0x4000>;
1233 #address-cell 985 #address-cells = <1>;
1234 #size-cells = 986 #size-cells = <0>;
1235 interrupts = 987 interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;
1236 clocks = <&gc 988 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1237 clock-names = 989 clock-names = "se";
1238 interconnects 990 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1239 991 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1240 992 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1241 993 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
1242 994 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
1243 995 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1244 interconnect- 996 interconnect-names = "qup-core",
1245 997 "qup-config",
1246 998 "qup-memory";
1247 power-domains 999 power-domains = <&rpmhpd SA8775P_CX>;
1248 status = "dis 1000 status = "disabled";
1249 }; 1001 };
1250 1002
1251 spi1: spi@984000 { 1003 spi1: spi@984000 {
1252 compatible = 1004 compatible = "qcom,geni-spi";
1253 reg = <0x0 0x 1005 reg = <0x0 0x984000 0x0 0x4000>;
1254 #address-cell 1006 #address-cells = <1>;
1255 #size-cells = 1007 #size-cells = <0>;
1256 interrupts = 1008 interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;
1257 clocks = <&gc 1009 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1258 clock-names = 1010 clock-names = "se";
1259 interconnects 1011 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1260 1012 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1261 1013 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1262 1014 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
1263 1015 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
1264 1016 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1265 interconnect- 1017 interconnect-names = "qup-core",
1266 1018 "qup-config",
1267 1019 "qup-memory";
1268 power-domains 1020 power-domains = <&rpmhpd SA8775P_CX>;
1269 status = "dis 1021 status = "disabled";
1270 }; 1022 };
1271 1023
1272 i2c2: i2c@988000 { 1024 i2c2: i2c@988000 {
1273 compatible = 1025 compatible = "qcom,geni-i2c";
1274 reg = <0x0 0x 1026 reg = <0x0 0x988000 0x0 0x4000>;
1275 #address-cell 1027 #address-cells = <1>;
1276 #size-cells = 1028 #size-cells = <0>;
1277 interrupts = 1029 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>;
1278 clocks = <&gc 1030 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1279 clock-names = 1031 clock-names = "se";
1280 interconnects 1032 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1281 1033 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1282 1034 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1283 1035 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
1284 1036 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
1285 1037 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1286 interconnect- 1038 interconnect-names = "qup-core",
1287 1039 "qup-config",
1288 1040 "qup-memory";
1289 power-domains 1041 power-domains = <&rpmhpd SA8775P_CX>;
1290 status = "dis 1042 status = "disabled";
1291 }; 1043 };
1292 1044
1293 spi2: spi@988000 { 1045 spi2: spi@988000 {
1294 compatible = 1046 compatible = "qcom,geni-spi";
1295 reg = <0x0 0x 1047 reg = <0x0 0x988000 0x0 0x4000>;
1296 #address-cell 1048 #address-cells = <1>;
1297 #size-cells = 1049 #size-cells = <0>;
1298 interrupts = 1050 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>;
1299 clocks = <&gc 1051 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1300 clock-names = 1052 clock-names = "se";
1301 interconnects 1053 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1302 1054 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1303 1055 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1304 1056 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
1305 1057 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
1306 1058 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1307 interconnect- 1059 interconnect-names = "qup-core",
1308 1060 "qup-config",
1309 1061 "qup-memory";
1310 power-domains 1062 power-domains = <&rpmhpd SA8775P_CX>;
1311 status = "dis 1063 status = "disabled";
1312 }; 1064 };
1313 1065
1314 i2c3: i2c@98c000 { 1066 i2c3: i2c@98c000 {
1315 compatible = 1067 compatible = "qcom,geni-i2c";
1316 reg = <0x0 0x 1068 reg = <0x0 0x98c000 0x0 0x4000>;
1317 #address-cell 1069 #address-cells = <1>;
1318 #size-cells = 1070 #size-cells = <0>;
1319 interrupts = 1071 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>;
1320 clocks = <&gc 1072 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1321 clock-names = 1073 clock-names = "se";
1322 interconnects 1074 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1323 1075 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1324 1076 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1325 1077 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
1326 1078 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
1327 1079 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1328 interconnect- 1080 interconnect-names = "qup-core",
1329 1081 "qup-config",
1330 1082 "qup-memory";
1331 power-domains 1083 power-domains = <&rpmhpd SA8775P_CX>;
1332 status = "dis 1084 status = "disabled";
1333 }; 1085 };
1334 1086
1335 spi3: spi@98c000 { 1087 spi3: spi@98c000 {
1336 compatible = 1088 compatible = "qcom,geni-spi";
1337 reg = <0x0 0x 1089 reg = <0x0 0x98c000 0x0 0x4000>;
1338 #address-cell 1090 #address-cells = <1>;
1339 #size-cells = 1091 #size-cells = <0>;
1340 interrupts = 1092 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>;
1341 clocks = <&gc 1093 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1342 clock-names = 1094 clock-names = "se";
1343 interconnects 1095 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1344 1096 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1345 1097 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1346 1098 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
1347 1099 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
1348 1100 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1349 interconnect- 1101 interconnect-names = "qup-core",
1350 1102 "qup-config",
1351 1103 "qup-memory";
1352 power-domains 1104 power-domains = <&rpmhpd SA8775P_CX>;
1353 status = "dis 1105 status = "disabled";
1354 }; 1106 };
1355 1107
1356 i2c4: i2c@990000 { 1108 i2c4: i2c@990000 {
1357 compatible = 1109 compatible = "qcom,geni-i2c";
1358 reg = <0x0 0x 1110 reg = <0x0 0x990000 0x0 0x4000>;
1359 #address-cell 1111 #address-cells = <1>;
1360 #size-cells = 1112 #size-cells = <0>;
1361 interrupts = 1113 interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>;
1362 clocks = <&gc 1114 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1363 clock-names = 1115 clock-names = "se";
1364 interconnects 1116 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1365 1117 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1366 1118 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1367 1119 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
1368 1120 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
1369 1121 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1370 interconnect- 1122 interconnect-names = "qup-core",
1371 1123 "qup-config",
1372 1124 "qup-memory";
1373 power-domains 1125 power-domains = <&rpmhpd SA8775P_CX>;
1374 status = "dis 1126 status = "disabled";
1375 }; 1127 };
1376 1128
1377 spi4: spi@990000 { 1129 spi4: spi@990000 {
1378 compatible = 1130 compatible = "qcom,geni-spi";
1379 reg = <0x0 0x 1131 reg = <0x0 0x990000 0x0 0x4000>;
1380 #address-cell 1132 #address-cells = <1>;
1381 #size-cells = 1133 #size-cells = <0>;
1382 interrupts = 1134 interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>;
1383 clocks = <&gc 1135 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1384 clock-names = 1136 clock-names = "se";
1385 interconnects 1137 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1386 1138 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1387 1139 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1388 1140 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
1389 1141 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
1390 1142 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1391 interconnect- 1143 interconnect-names = "qup-core",
1392 1144 "qup-config",
1393 1145 "qup-memory";
1394 power-domains 1146 power-domains = <&rpmhpd SA8775P_CX>;
1395 status = "dis 1147 status = "disabled";
1396 }; 1148 };
1397 1149
1398 i2c5: i2c@994000 { 1150 i2c5: i2c@994000 {
1399 compatible = 1151 compatible = "qcom,geni-i2c";
1400 reg = <0x0 0x 1152 reg = <0x0 0x994000 0x0 0x4000>;
1401 #address-cell 1153 #address-cells = <1>;
1402 #size-cells = 1154 #size-cells = <0>;
1403 interrupts = 1155 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>;
1404 clocks = <&gc 1156 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1405 clock-names = 1157 clock-names = "se";
1406 interconnects 1158 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1407 1159 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1408 1160 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1409 1161 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
1410 1162 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
1411 1163 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1412 interconnect- 1164 interconnect-names = "qup-core",
1413 1165 "qup-config",
1414 1166 "qup-memory";
1415 power-domains 1167 power-domains = <&rpmhpd SA8775P_CX>;
1416 status = "dis 1168 status = "disabled";
1417 }; 1169 };
1418 1170
1419 spi5: spi@994000 { 1171 spi5: spi@994000 {
1420 compatible = 1172 compatible = "qcom,geni-spi";
1421 reg = <0x0 0x 1173 reg = <0x0 0x994000 0x0 0x4000>;
1422 #address-cell 1174 #address-cells = <1>;
1423 #size-cells = 1175 #size-cells = <0>;
1424 interrupts = 1176 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>;
1425 clocks = <&gc 1177 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1426 clock-names = 1178 clock-names = "se";
1427 interconnects 1179 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1428 1180 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1429 1181 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1430 1182 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
1431 1183 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
1432 1184 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1433 interconnect- 1185 interconnect-names = "qup-core",
1434 1186 "qup-config",
1435 1187 "qup-memory";
1436 power-domains 1188 power-domains = <&rpmhpd SA8775P_CX>;
1437 status = "dis 1189 status = "disabled";
1438 }; 1190 };
1439 1191
1440 uart5: serial@994000 1192 uart5: serial@994000 {
1441 compatible = 1193 compatible = "qcom,geni-uart";
1442 reg = <0x0 0x 1194 reg = <0x0 0x994000 0x0 0x4000>;
1443 interrupts = 1195 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>;
1444 clocks = <&gc 1196 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1445 clock-names = 1197 clock-names = "se";
1446 interconnects 1198 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1447 1199 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1448 1200 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1449 1201 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
1450 interconnect- 1202 interconnect-names = "qup-core", "qup-config";
1451 power-domains 1203 power-domains = <&rpmhpd SA8775P_CX>;
1452 status = "dis 1204 status = "disabled";
1453 }; 1205 };
1454 }; 1206 };
1455 1207
1456 qupv3_id_1: geniqup@ac0000 { 1208 qupv3_id_1: geniqup@ac0000 {
1457 compatible = "qcom,ge 1209 compatible = "qcom,geni-se-qup";
1458 reg = <0x0 0x00ac0000 1210 reg = <0x0 0x00ac0000 0x0 0x6000>;
1459 #address-cells = <2>; 1211 #address-cells = <2>;
1460 #size-cells = <2>; 1212 #size-cells = <2>;
1461 ranges; 1213 ranges;
1462 clock-names = "m-ahb" 1214 clock-names = "m-ahb", "s-ahb";
1463 clocks = <&gcc GCC_QU 1215 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1464 <&gcc GCC_QU 1216 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1465 iommus = <&apps_smmu 1217 iommus = <&apps_smmu 0x443 0x0>;
1466 status = "disabled"; 1218 status = "disabled";
1467 1219
1468 i2c7: i2c@a80000 { 1220 i2c7: i2c@a80000 {
1469 compatible = 1221 compatible = "qcom,geni-i2c";
1470 reg = <0x0 0x 1222 reg = <0x0 0xa80000 0x0 0x4000>;
1471 #address-cell 1223 #address-cells = <1>;
1472 #size-cells = 1224 #size-cells = <0>;
1473 interrupts = 1225 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1474 clocks = <&gc 1226 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1475 clock-names = 1227 clock-names = "se";
1476 interconnects 1228 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1477 1229 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1478 1230 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1479 1231 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1480 1232 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1481 1233 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1482 interconnect- 1234 interconnect-names = "qup-core",
1483 1235 "qup-config",
1484 1236 "qup-memory";
1485 power-domains 1237 power-domains = <&rpmhpd SA8775P_CX>;
1486 status = "dis 1238 status = "disabled";
1487 }; 1239 };
1488 1240
1489 spi7: spi@a80000 { 1241 spi7: spi@a80000 {
1490 compatible = 1242 compatible = "qcom,geni-spi";
1491 reg = <0x0 0x 1243 reg = <0x0 0xa80000 0x0 0x4000>;
1492 #address-cell 1244 #address-cells = <1>;
1493 #size-cells = 1245 #size-cells = <0>;
1494 interrupts = 1246 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1495 clocks = <&gc 1247 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1496 clock-names = 1248 clock-names = "se";
1497 interconnects 1249 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1498 1250 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1499 1251 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1500 1252 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1501 1253 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1502 1254 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1503 interconnect- 1255 interconnect-names = "qup-core",
1504 1256 "qup-config",
1505 1257 "qup-memory";
1506 power-domains 1258 power-domains = <&rpmhpd SA8775P_CX>;
1507 status = "dis 1259 status = "disabled";
1508 }; 1260 };
1509 1261
1510 i2c8: i2c@a84000 { 1262 i2c8: i2c@a84000 {
1511 compatible = 1263 compatible = "qcom,geni-i2c";
1512 reg = <0x0 0x 1264 reg = <0x0 0xa84000 0x0 0x4000>;
1513 #address-cell 1265 #address-cells = <1>;
1514 #size-cells = 1266 #size-cells = <0>;
1515 interrupts = 1267 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1516 clocks = <&gc 1268 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1517 clock-names = 1269 clock-names = "se";
1518 interconnects 1270 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1519 1271 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1520 1272 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1521 1273 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1522 1274 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1523 1275 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1524 interconnect- 1276 interconnect-names = "qup-core",
1525 1277 "qup-config",
1526 1278 "qup-memory";
1527 power-domains 1279 power-domains = <&rpmhpd SA8775P_CX>;
1528 status = "dis 1280 status = "disabled";
1529 }; 1281 };
1530 1282
1531 spi8: spi@a84000 { 1283 spi8: spi@a84000 {
1532 compatible = 1284 compatible = "qcom,geni-spi";
1533 reg = <0x0 0x 1285 reg = <0x0 0xa84000 0x0 0x4000>;
1534 #address-cell 1286 #address-cells = <1>;
1535 #size-cells = 1287 #size-cells = <0>;
1536 interrupts = 1288 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1537 clocks = <&gc 1289 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1538 clock-names = 1290 clock-names = "se";
1539 interconnects 1291 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1540 1292 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1541 1293 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1542 1294 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1543 1295 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1544 1296 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1545 interconnect- 1297 interconnect-names = "qup-core",
1546 1298 "qup-config",
1547 1299 "qup-memory";
1548 power-domains 1300 power-domains = <&rpmhpd SA8775P_CX>;
1549 status = "dis 1301 status = "disabled";
1550 }; 1302 };
1551 1303
1552 i2c9: i2c@a88000 { 1304 i2c9: i2c@a88000 {
1553 compatible = 1305 compatible = "qcom,geni-i2c";
1554 reg = <0x0 0x 1306 reg = <0x0 0xa88000 0x0 0x4000>;
1555 #address-cell 1307 #address-cells = <1>;
1556 #size-cells = 1308 #size-cells = <0>;
1557 interrupts = 1309 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1558 clocks = <&gc 1310 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1559 clock-names = 1311 clock-names = "se";
1560 interconnects 1312 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1561 1313 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1562 1314 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1563 1315 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1564 1316 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1565 1317 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1566 interconnect- 1318 interconnect-names = "qup-core",
1567 1319 "qup-config",
1568 1320 "qup-memory";
1569 power-domains 1321 power-domains = <&rpmhpd SA8775P_CX>;
1570 status = "dis 1322 status = "disabled";
1571 }; 1323 };
1572 1324
1573 spi9: spi@a88000 { 1325 spi9: spi@a88000 {
1574 compatible = 1326 compatible = "qcom,geni-spi";
1575 reg = <0x0 0x 1327 reg = <0x0 0xa88000 0x0 0x4000>;
1576 #address-cell 1328 #address-cells = <1>;
1577 #size-cells = 1329 #size-cells = <0>;
1578 interrupts = 1330 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1579 clocks = <&gc 1331 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1580 clock-names = 1332 clock-names = "se";
1581 interconnects 1333 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1582 1334 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1583 1335 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1584 1336 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1585 1337 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1586 1338 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1587 interconnect- 1339 interconnect-names = "qup-core",
1588 1340 "qup-config",
1589 1341 "qup-memory";
1590 power-domains 1342 power-domains = <&rpmhpd SA8775P_CX>;
1591 status = "dis 1343 status = "disabled";
1592 }; 1344 };
1593 1345
1594 uart9: serial@a88000 1346 uart9: serial@a88000 {
1595 compatible = 1347 compatible = "qcom,geni-uart";
1596 reg = <0x0 0x 1348 reg = <0x0 0xa88000 0x0 0x4000>;
1597 interrupts = 1349 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1598 clocks = <&gc 1350 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1599 clock-names = 1351 clock-names = "se";
1600 interconnects 1352 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1601 1353 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1602 1354 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1603 1355 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
1604 interconnect- 1356 interconnect-names = "qup-core", "qup-config";
1605 power-domains 1357 power-domains = <&rpmhpd SA8775P_CX>;
1606 status = "dis 1358 status = "disabled";
1607 }; 1359 };
1608 1360
1609 i2c10: i2c@a8c000 { 1361 i2c10: i2c@a8c000 {
1610 compatible = 1362 compatible = "qcom,geni-i2c";
1611 reg = <0x0 0x 1363 reg = <0x0 0xa8c000 0x0 0x4000>;
1612 #address-cell 1364 #address-cells = <1>;
1613 #size-cells = 1365 #size-cells = <0>;
1614 interrupts = 1366 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1615 clocks = <&gc 1367 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1616 clock-names = 1368 clock-names = "se";
1617 interconnects 1369 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1618 1370 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1619 1371 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1620 1372 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1621 1373 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1622 1374 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1623 interconnect- 1375 interconnect-names = "qup-core",
1624 1376 "qup-config",
1625 1377 "qup-memory";
1626 power-domains 1378 power-domains = <&rpmhpd SA8775P_CX>;
1627 status = "dis 1379 status = "disabled";
1628 }; 1380 };
1629 1381
1630 spi10: spi@a8c000 { 1382 spi10: spi@a8c000 {
1631 compatible = 1383 compatible = "qcom,geni-spi";
1632 reg = <0x0 0x 1384 reg = <0x0 0xa8c000 0x0 0x4000>;
1633 #address-cell 1385 #address-cells = <1>;
1634 #size-cells = 1386 #size-cells = <0>;
1635 interrupts = 1387 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1636 clocks = <&gc 1388 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1637 clock-names = 1389 clock-names = "se";
1638 interconnects 1390 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1639 1391 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1640 1392 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1641 1393 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1642 1394 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1643 1395 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1644 interconnect- 1396 interconnect-names = "qup-core",
1645 1397 "qup-config",
1646 1398 "qup-memory";
1647 power-domains 1399 power-domains = <&rpmhpd SA8775P_CX>;
1648 status = "dis 1400 status = "disabled";
1649 }; 1401 };
1650 1402
1651 uart10: serial@a8c000 1403 uart10: serial@a8c000 {
1652 compatible = 1404 compatible = "qcom,geni-uart";
1653 reg = <0x0 0x 1405 reg = <0x0 0x00a8c000 0x0 0x4000>;
1654 interrupts = 1406 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1655 clock-names = 1407 clock-names = "se";
1656 clocks = <&gc 1408 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1657 interconnect- 1409 interconnect-names = "qup-core", "qup-config";
1658 interconnects 1410 interconnects = <&clk_virt MASTER_QUP_CORE_1 0
1659 1411 &clk_virt SLAVE_QUP_CORE_1 0>,
1660 1412 <&gem_noc MASTER_APPSS_PROC 0
1661 1413 &config_noc SLAVE_QUP_1 0>;
1662 power-domains 1414 power-domains = <&rpmhpd SA8775P_CX>;
1663 operating-poi 1415 operating-points-v2 = <&qup_opp_table_100mhz>;
1664 status = "dis 1416 status = "disabled";
1665 }; 1417 };
1666 1418
1667 i2c11: i2c@a90000 { 1419 i2c11: i2c@a90000 {
1668 compatible = 1420 compatible = "qcom,geni-i2c";
1669 reg = <0x0 0x 1421 reg = <0x0 0xa90000 0x0 0x4000>;
1670 #address-cell 1422 #address-cells = <1>;
1671 #size-cells = 1423 #size-cells = <0>;
1672 interrupts = 1424 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1673 clocks = <&gc 1425 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1674 clock-names = 1426 clock-names = "se";
1675 interconnects 1427 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1676 1428 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1677 1429 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1678 1430 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1679 1431 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1680 1432 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1681 interconnect- 1433 interconnect-names = "qup-core",
1682 1434 "qup-config",
1683 1435 "qup-memory";
1684 power-domains 1436 power-domains = <&rpmhpd SA8775P_CX>;
1685 status = "dis 1437 status = "disabled";
1686 }; 1438 };
1687 1439
1688 spi11: spi@a90000 { 1440 spi11: spi@a90000 {
1689 compatible = 1441 compatible = "qcom,geni-spi";
1690 reg = <0x0 0x 1442 reg = <0x0 0xa90000 0x0 0x4000>;
1691 #address-cell 1443 #address-cells = <1>;
1692 #size-cells = 1444 #size-cells = <0>;
1693 interrupts = 1445 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1694 clocks = <&gc 1446 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1695 clock-names = 1447 clock-names = "se";
1696 interconnects 1448 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1697 1449 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1698 1450 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1699 1451 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1700 1452 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1701 1453 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1702 interconnect- 1454 interconnect-names = "qup-core",
1703 1455 "qup-config",
1704 1456 "qup-memory";
1705 power-domains 1457 power-domains = <&rpmhpd SA8775P_CX>;
1706 status = "dis 1458 status = "disabled";
1707 }; 1459 };
1708 1460
1709 i2c12: i2c@a94000 { 1461 i2c12: i2c@a94000 {
1710 compatible = 1462 compatible = "qcom,geni-i2c";
1711 reg = <0x0 0x 1463 reg = <0x0 0xa94000 0x0 0x4000>;
1712 #address-cell 1464 #address-cells = <1>;
1713 #size-cells = 1465 #size-cells = <0>;
1714 interrupts = 1466 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1715 clocks = <&gc 1467 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1716 clock-names = 1468 clock-names = "se";
1717 interconnects 1469 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1718 1470 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1719 1471 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1720 1472 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1721 1473 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1722 1474 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1723 interconnect- 1475 interconnect-names = "qup-core",
1724 1476 "qup-config",
1725 1477 "qup-memory";
1726 power-domains 1478 power-domains = <&rpmhpd SA8775P_CX>;
1727 status = "dis 1479 status = "disabled";
1728 }; 1480 };
1729 1481
1730 spi12: spi@a94000 { 1482 spi12: spi@a94000 {
1731 compatible = 1483 compatible = "qcom,geni-spi";
1732 reg = <0x0 0x 1484 reg = <0x0 0xa94000 0x0 0x4000>;
1733 #address-cell 1485 #address-cells = <1>;
1734 #size-cells = 1486 #size-cells = <0>;
1735 interrupts = 1487 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1736 clocks = <&gc 1488 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1737 clock-names = 1489 clock-names = "se";
1738 interconnects 1490 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1739 1491 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1740 1492 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1741 1493 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1742 1494 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1743 1495 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1744 interconnect- 1496 interconnect-names = "qup-core",
1745 1497 "qup-config",
1746 1498 "qup-memory";
1747 power-domains 1499 power-domains = <&rpmhpd SA8775P_CX>;
1748 status = "dis 1500 status = "disabled";
1749 }; 1501 };
1750 1502
1751 uart12: serial@a94000 1503 uart12: serial@a94000 {
1752 compatible = 1504 compatible = "qcom,geni-uart";
1753 reg = <0x0 0x 1505 reg = <0x0 0x00a94000 0x0 0x4000>;
1754 interrupts = 1506 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1755 clocks = <&gc 1507 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1756 clock-names = 1508 clock-names = "se";
1757 interconnects 1509 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1758 1510 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1759 1511 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1760 1512 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
1761 interconnect- 1513 interconnect-names = "qup-core", "qup-config";
1762 power-domains 1514 power-domains = <&rpmhpd SA8775P_CX>;
1763 status = "dis 1515 status = "disabled";
1764 }; 1516 };
1765 1517
1766 i2c13: i2c@a98000 { 1518 i2c13: i2c@a98000 {
1767 compatible = 1519 compatible = "qcom,geni-i2c";
1768 reg = <0x0 0x 1520 reg = <0x0 0xa98000 0x0 0x4000>;
1769 #address-cell 1521 #address-cells = <1>;
1770 #size-cells = 1522 #size-cells = <0>;
1771 interrupts = 1523 interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
1772 clocks = <&gc 1524 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1773 clock-names = 1525 clock-names = "se";
1774 interconnects 1526 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1775 1527 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1776 1528 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1777 1529 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1778 1530 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1779 1531 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1780 interconnect- 1532 interconnect-names = "qup-core",
1781 1533 "qup-config",
1782 1534 "qup-memory";
1783 power-domains 1535 power-domains = <&rpmhpd SA8775P_CX>;
1784 status = "dis 1536 status = "disabled";
1785 }; 1537 };
1786 }; 1538 };
1787 1539
1788 qupv3_id_3: geniqup@bc0000 { 1540 qupv3_id_3: geniqup@bc0000 {
1789 compatible = "qcom,ge 1541 compatible = "qcom,geni-se-qup";
1790 reg = <0x0 0xbc0000 0 1542 reg = <0x0 0xbc0000 0x0 0x6000>;
1791 #address-cells = <2>; 1543 #address-cells = <2>;
1792 #size-cells = <2>; 1544 #size-cells = <2>;
1793 ranges; 1545 ranges;
1794 clock-names = "m-ahb" 1546 clock-names = "m-ahb", "s-ahb";
1795 clocks = <&gcc GCC_QU 1547 clocks = <&gcc GCC_QUPV3_WRAP_3_M_AHB_CLK>,
1796 <&gcc GCC_QUP 1548 <&gcc GCC_QUPV3_WRAP_3_S_AHB_CLK>;
1797 iommus = <&apps_smmu 1549 iommus = <&apps_smmu 0x43 0x0>;
1798 status = "disabled"; 1550 status = "disabled";
1799 1551
1800 i2c21: i2c@b80000 { 1552 i2c21: i2c@b80000 {
1801 compatible = 1553 compatible = "qcom,geni-i2c";
1802 reg = <0x0 0x 1554 reg = <0x0 0xb80000 0x0 0x4000>;
1803 #address-cell 1555 #address-cells = <1>;
1804 #size-cells = 1556 #size-cells = <0>;
1805 interrupts = 1557 interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>;
1806 clocks = <&gc 1558 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>;
1807 clock-names = 1559 clock-names = "se";
1808 interconnects 1560 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS
1809 1561 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>,
1810 <& 1562 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1811 1563 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>,
1812 <& 1564 <&aggre1_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS
1813 1565 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1814 interconnect- 1566 interconnect-names = "qup-core",
1815 1567 "qup-config",
1816 1568 "qup-memory";
1817 power-domains 1569 power-domains = <&rpmhpd SA8775P_CX>;
1818 status = "dis 1570 status = "disabled";
1819 }; 1571 };
1820 1572
1821 spi21: spi@b80000 { 1573 spi21: spi@b80000 {
1822 compatible = 1574 compatible = "qcom,geni-spi";
1823 reg = <0x0 0x 1575 reg = <0x0 0xb80000 0x0 0x4000>;
1824 #address-cell 1576 #address-cells = <1>;
1825 #size-cells = 1577 #size-cells = <0>;
1826 interrupts = 1578 interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>;
1827 clocks = <&gc 1579 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>;
1828 clock-names = 1580 clock-names = "se";
1829 interconnects 1581 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS
1830 1582 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>,
1831 <& 1583 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1832 1584 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>,
1833 <& 1585 <&aggre1_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS
1834 1586 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1835 interconnect- 1587 interconnect-names = "qup-core",
1836 1588 "qup-config",
1837 1589 "qup-memory";
1838 power-domains 1590 power-domains = <&rpmhpd SA8775P_CX>;
1839 status = "dis 1591 status = "disabled";
1840 }; 1592 };
1841 }; 1593 };
1842 1594
1843 rng: rng@10d2000 { 1595 rng: rng@10d2000 {
1844 compatible = "qcom,sa 1596 compatible = "qcom,sa8775p-trng", "qcom,trng";
1845 reg = <0 0x010d2000 0 1597 reg = <0 0x010d2000 0 0x1000>;
1846 }; 1598 };
1847 1599
1848 ufs_mem_hc: ufs@1d84000 { 1600 ufs_mem_hc: ufs@1d84000 {
1849 compatible = "qcom,sa 1601 compatible = "qcom,sa8775p-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
1850 reg = <0x0 0x01d84000 1602 reg = <0x0 0x01d84000 0x0 0x3000>;
1851 interrupts = <GIC_SPI 1603 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
1852 phys = <&ufs_mem_phy> 1604 phys = <&ufs_mem_phy>;
1853 phy-names = "ufsphy"; 1605 phy-names = "ufsphy";
1854 lanes-per-direction = 1606 lanes-per-direction = <2>;
1855 #reset-cells = <1>; 1607 #reset-cells = <1>;
1856 resets = <&gcc GCC_UF 1608 resets = <&gcc GCC_UFS_PHY_BCR>;
1857 reset-names = "rst"; 1609 reset-names = "rst";
1858 power-domains = <&gcc 1610 power-domains = <&gcc UFS_PHY_GDSC>;
1859 required-opps = <&rpm 1611 required-opps = <&rpmhpd_opp_nom>;
1860 iommus = <&apps_smmu 1612 iommus = <&apps_smmu 0x100 0x0>;
1861 dma-coherent; 1613 dma-coherent;
1862 clocks = <&gcc GCC_UF 1614 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
1863 <&gcc GCC_AG 1615 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
1864 <&gcc GCC_UF 1616 <&gcc GCC_UFS_PHY_AHB_CLK>,
1865 <&gcc GCC_UF 1617 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
1866 <&rpmhcc RPM 1618 <&rpmhcc RPMH_CXO_CLK>,
1867 <&gcc GCC_UF 1619 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
1868 <&gcc GCC_UF 1620 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
1869 <&gcc GCC_UF 1621 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
1870 clock-names = "core_c 1622 clock-names = "core_clk",
1871 "bus_ag 1623 "bus_aggr_clk",
1872 "iface_ 1624 "iface_clk",
1873 "core_c 1625 "core_clk_unipro",
1874 "ref_cl 1626 "ref_clk",
1875 "tx_lan 1627 "tx_lane0_sync_clk",
1876 "rx_lan 1628 "rx_lane0_sync_clk",
1877 "rx_lan 1629 "rx_lane1_sync_clk";
1878 freq-table-hz = <7500 1630 freq-table-hz = <75000000 300000000>,
1879 <0 0> 1631 <0 0>,
1880 <0 0> 1632 <0 0>,
1881 <7500 1633 <75000000 300000000>,
1882 <0 0> 1634 <0 0>,
1883 <0 0> 1635 <0 0>,
1884 <0 0> 1636 <0 0>,
1885 <0 0> 1637 <0 0>;
1886 qcom,ice = <&ice>; 1638 qcom,ice = <&ice>;
1887 status = "disabled"; 1639 status = "disabled";
1888 }; 1640 };
1889 1641
1890 ufs_mem_phy: phy@1d87000 { 1642 ufs_mem_phy: phy@1d87000 {
1891 compatible = "qcom,sa 1643 compatible = "qcom,sa8775p-qmp-ufs-phy";
1892 reg = <0x0 0x01d87000 1644 reg = <0x0 0x01d87000 0x0 0xe10>;
1893 /* 1645 /*
1894 * Yes, GCC_EDP_REF_C 1646 * Yes, GCC_EDP_REF_CLKREF_EN is correct in qref. It
1895 * enables the CXO cl 1647 * enables the CXO clock to eDP *and* UFS PHY.
1896 */ 1648 */
1897 clocks = <&rpmhcc RPM 1649 clocks = <&rpmhcc RPMH_CXO_CLK>,
1898 <&gcc GCC_UF 1650 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
1899 <&gcc GCC_ED 1651 <&gcc GCC_EDP_REF_CLKREF_EN>;
1900 clock-names = "ref", 1652 clock-names = "ref", "ref_aux", "qref";
1901 power-domains = <&gcc 1653 power-domains = <&gcc UFS_PHY_GDSC>;
1902 resets = <&ufs_mem_hc 1654 resets = <&ufs_mem_hc 0>;
1903 reset-names = "ufsphy 1655 reset-names = "ufsphy";
1904 #phy-cells = <0>; 1656 #phy-cells = <0>;
1905 status = "disabled"; 1657 status = "disabled";
1906 }; 1658 };
1907 1659
1908 ice: crypto@1d88000 { 1660 ice: crypto@1d88000 {
1909 compatible = "qcom,sa 1661 compatible = "qcom,sa8775p-inline-crypto-engine",
1910 "qcom,in 1662 "qcom,inline-crypto-engine";
1911 reg = <0x0 0x01d88000 1663 reg = <0x0 0x01d88000 0x0 0x8000>;
1912 clocks = <&gcc GCC_UF 1664 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
1913 }; 1665 };
1914 1666
1915 stm: stm@4002000 { 1667 stm: stm@4002000 {
1916 compatible = "arm,cor 1668 compatible = "arm,coresight-stm", "arm,primecell";
1917 reg = <0x0 0x4002000 1669 reg = <0x0 0x4002000 0x0 0x1000>,
1918 <0x0 0x1628 1670 <0x0 0x16280000 0x0 0x180000>;
1919 reg-names = "stm-base 1671 reg-names = "stm-base", "stm-stimulus-base";
1920 1672
1921 clocks = <&aoss_qmp>; 1673 clocks = <&aoss_qmp>;
1922 clock-names = "apb_pc 1674 clock-names = "apb_pclk";
1923 1675
1924 out-ports { 1676 out-ports {
1925 port { 1677 port {
1926 stm_o 1678 stm_out: endpoint {
1927 1679 remote-endpoint =
1928 1680 <&funnel0_in7>;
1929 }; 1681 };
1930 }; 1682 };
1931 }; 1683 };
1932 }; 1684 };
1933 1685
1934 tpdm@4003000 { 1686 tpdm@4003000 {
1935 compatible = "qcom,co 1687 compatible = "qcom,coresight-tpdm", "arm,primecell";
1936 reg = <0x0 0x4003000 1688 reg = <0x0 0x4003000 0x0 0x1000>;
1937 1689
1938 clocks = <&aoss_qmp>; 1690 clocks = <&aoss_qmp>;
1939 clock-names = "apb_pc 1691 clock-names = "apb_pclk";
1940 1692
1941 qcom,cmb-element-bits 1693 qcom,cmb-element-bits = <32>;
1942 qcom,cmb-msrs-num = < 1694 qcom,cmb-msrs-num = <32>;
1943 1695
1944 out-ports { 1696 out-ports {
1945 port { 1697 port {
1946 qdss_ 1698 qdss_tpdm0_out: endpoint {
1947 1699 remote-endpoint =
1948 1700 <&qdss_tpda_in0>;
1949 }; 1701 };
1950 }; 1702 };
1951 }; 1703 };
1952 }; 1704 };
1953 1705
1954 tpda@4004000 { 1706 tpda@4004000 {
1955 compatible = "qcom,co 1707 compatible = "qcom,coresight-tpda", "arm,primecell";
1956 reg = <0x0 0x4004000 1708 reg = <0x0 0x4004000 0x0 0x1000>;
1957 1709
1958 clocks = <&aoss_qmp>; 1710 clocks = <&aoss_qmp>;
1959 clock-names = "apb_pc 1711 clock-names = "apb_pclk";
1960 1712
1961 out-ports { 1713 out-ports {
1962 port { 1714 port {
1963 qdss_ 1715 qdss_tpda_out: endpoint {
1964 1716 remote-endpoint =
1965 1717 <&funnel0_in6>;
1966 }; 1718 };
1967 }; 1719 };
1968 }; 1720 };
1969 1721
1970 in-ports { 1722 in-ports {
1971 #address-cell 1723 #address-cells = <1>;
1972 #size-cells = 1724 #size-cells = <0>;
1973 1725
1974 port@0 { 1726 port@0 {
1975 reg = 1727 reg = <0>;
1976 qdss_ 1728 qdss_tpda_in0: endpoint {
1977 1729 remote-endpoint =
1978 1730 <&qdss_tpdm0_out>;
1979 }; 1731 };
1980 }; 1732 };
1981 1733
1982 port@1 { 1734 port@1 {
1983 reg = 1735 reg = <1>;
1984 qdss_ 1736 qdss_tpda_in1: endpoint {
1985 1737 remote-endpoint =
1986 1738 <&qdss_tpdm1_out>;
1987 }; 1739 };
1988 }; 1740 };
1989 }; 1741 };
1990 }; 1742 };
1991 1743
1992 tpdm@400f000 { 1744 tpdm@400f000 {
1993 compatible = "qcom,co 1745 compatible = "qcom,coresight-tpdm", "arm,primecell";
1994 reg = <0x0 0x400f000 1746 reg = <0x0 0x400f000 0x0 0x1000>;
1995 1747
1996 clocks = <&aoss_qmp>; 1748 clocks = <&aoss_qmp>;
1997 clock-names = "apb_pc 1749 clock-names = "apb_pclk";
1998 1750
1999 qcom,cmb-element-bits 1751 qcom,cmb-element-bits = <32>;
2000 qcom,cmb-msrs-num = < 1752 qcom,cmb-msrs-num = <32>;
2001 1753
2002 out-ports { 1754 out-ports {
2003 port { 1755 port {
2004 qdss_ 1756 qdss_tpdm1_out: endpoint {
2005 1757 remote-endpoint =
2006 1758 <&qdss_tpda_in1>;
2007 }; 1759 };
2008 }; 1760 };
2009 }; 1761 };
2010 }; 1762 };
2011 1763
2012 funnel@4041000 { 1764 funnel@4041000 {
2013 compatible = "arm,cor 1765 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2014 reg = <0x0 0x4041000 1766 reg = <0x0 0x4041000 0x0 0x1000>;
2015 1767
2016 clocks = <&aoss_qmp>; 1768 clocks = <&aoss_qmp>;
2017 clock-names = "apb_pc 1769 clock-names = "apb_pclk";
2018 1770
2019 out-ports { 1771 out-ports {
2020 port { 1772 port {
2021 funne 1773 funnel0_out: endpoint {
2022 1774 remote-endpoint =
2023 1775 <&qdss_funnel_in0>;
2024 }; 1776 };
2025 }; 1777 };
2026 }; 1778 };
2027 1779
2028 in-ports { 1780 in-ports {
2029 #address-cell 1781 #address-cells = <1>;
2030 #size-cells = 1782 #size-cells = <0>;
2031 1783
2032 port@6 { 1784 port@6 {
2033 reg = 1785 reg = <6>;
2034 funne 1786 funnel0_in6: endpoint {
2035 1787 remote-endpoint =
2036 1788 <&qdss_tpda_out>;
2037 }; 1789 };
2038 }; 1790 };
2039 1791
2040 port@7 { 1792 port@7 {
2041 reg = 1793 reg = <7>;
2042 funne 1794 funnel0_in7: endpoint {
2043 1795 remote-endpoint =
2044 1796 <&stm_out>;
2045 }; 1797 };
2046 }; 1798 };
2047 }; 1799 };
2048 }; 1800 };
2049 1801
2050 funnel@4042000 { 1802 funnel@4042000 {
2051 compatible = "arm,cor 1803 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2052 reg = <0x0 0x4042000 1804 reg = <0x0 0x4042000 0x0 0x1000>;
2053 1805
2054 clocks = <&aoss_qmp>; 1806 clocks = <&aoss_qmp>;
2055 clock-names = "apb_pc 1807 clock-names = "apb_pclk";
2056 1808
2057 out-ports { 1809 out-ports {
2058 port { 1810 port {
2059 funne 1811 funnel1_out: endpoint {
2060 1812 remote-endpoint =
2061 1813 <&qdss_funnel_in1>;
2062 }; 1814 };
2063 }; 1815 };
2064 }; 1816 };
2065 1817
2066 in-ports { 1818 in-ports {
2067 #address-cell 1819 #address-cells = <1>;
2068 #size-cells = 1820 #size-cells = <0>;
2069 1821
2070 port@4 { 1822 port@4 {
2071 reg = 1823 reg = <4>;
2072 funne 1824 funnel1_in4: endpoint {
2073 1825 remote-endpoint =
2074 1826 <&apss_funnel1_out>;
2075 }; 1827 };
2076 }; 1828 };
2077 }; 1829 };
2078 }; 1830 };
2079 1831
2080 funnel@4045000 { 1832 funnel@4045000 {
2081 compatible = "arm,cor 1833 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2082 reg = <0x0 0x4045000 1834 reg = <0x0 0x4045000 0x0 0x1000>;
2083 1835
2084 clocks = <&aoss_qmp>; 1836 clocks = <&aoss_qmp>;
2085 clock-names = "apb_pc 1837 clock-names = "apb_pclk";
2086 1838
2087 out-ports { 1839 out-ports {
2088 port { 1840 port {
2089 qdss_ 1841 qdss_funnel_out: endpoint {
2090 1842 remote-endpoint =
2091 1843 <&aoss_funnel_in7>;
2092 }; 1844 };
2093 }; 1845 };
2094 }; 1846 };
2095 1847
2096 in-ports { 1848 in-ports {
2097 #address-cell 1849 #address-cells = <1>;
2098 #size-cells = 1850 #size-cells = <0>;
2099 1851
2100 port@0 { 1852 port@0 {
2101 reg = 1853 reg = <0>;
2102 qdss_ 1854 qdss_funnel_in0: endpoint {
2103 1855 remote-endpoint =
2104 1856 <&funnel0_out>;
2105 }; 1857 };
2106 }; 1858 };
2107 1859
2108 port@1 { 1860 port@1 {
2109 reg = 1861 reg = <1>;
2110 qdss_ 1862 qdss_funnel_in1: endpoint {
2111 1863 remote-endpoint =
2112 1864 <&funnel1_out>;
2113 }; 1865 };
2114 }; 1866 };
2115 }; 1867 };
2116 }; 1868 };
2117 1869
2118 funnel@4b04000 { 1870 funnel@4b04000 {
2119 compatible = "arm,cor 1871 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2120 reg = <0x0 0x4b04000 1872 reg = <0x0 0x4b04000 0x0 0x1000>;
2121 1873
2122 clocks = <&aoss_qmp>; 1874 clocks = <&aoss_qmp>;
2123 clock-names = "apb_pc 1875 clock-names = "apb_pclk";
2124 1876
2125 out-ports { 1877 out-ports {
2126 port { 1878 port {
2127 aoss_ 1879 aoss_funnel_out: endpoint {
2128 1880 remote-endpoint =
2129 1881 <&etf0_in>;
2130 }; 1882 };
2131 }; 1883 };
2132 }; 1884 };
2133 1885
2134 in-ports { 1886 in-ports {
2135 #address-cell 1887 #address-cells = <1>;
2136 #size-cells = 1888 #size-cells = <0>;
2137 1889
2138 port@6 { 1890 port@6 {
2139 reg = 1891 reg = <6>;
2140 aoss_ 1892 aoss_funnel_in6: endpoint {
2141 1893 remote-endpoint =
2142 1894 <&aoss_tpda_out>;
2143 }; 1895 };
2144 }; 1896 };
2145 1897
2146 port@7 { 1898 port@7 {
2147 reg = 1899 reg = <7>;
2148 aoss_ 1900 aoss_funnel_in7: endpoint {
2149 1901 remote-endpoint =
2150 1902 <&qdss_funnel_out>;
2151 }; 1903 };
2152 }; 1904 };
2153 }; 1905 };
2154 }; 1906 };
2155 1907
2156 tmc_etf: tmc@4b05000 { 1908 tmc_etf: tmc@4b05000 {
2157 compatible = "arm,cor 1909 compatible = "arm,coresight-tmc", "arm,primecell";
2158 reg = <0x0 0x4b05000 1910 reg = <0x0 0x4b05000 0x0 0x1000>;
2159 1911
2160 clocks = <&aoss_qmp>; 1912 clocks = <&aoss_qmp>;
2161 clock-names = "apb_pc 1913 clock-names = "apb_pclk";
2162 1914
2163 out-ports { 1915 out-ports {
2164 port { 1916 port {
2165 etf0_ 1917 etf0_out: endpoint {
2166 1918 remote-endpoint =
2167 1919 <&swao_rep_in>;
2168 }; 1920 };
2169 }; 1921 };
2170 }; 1922 };
2171 1923
2172 in-ports { 1924 in-ports {
2173 port { 1925 port {
2174 etf0_ 1926 etf0_in: endpoint {
2175 1927 remote-endpoint =
2176 1928 <&aoss_funnel_out>;
2177 }; 1929 };
2178 }; 1930 };
2179 }; 1931 };
2180 }; 1932 };
2181 1933
2182 replicator@4b06000 { 1934 replicator@4b06000 {
2183 compatible = "arm,cor 1935 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2184 reg = <0x0 0x4b06000 1936 reg = <0x0 0x4b06000 0x0 0x1000>;
2185 1937
2186 clocks = <&aoss_qmp>; 1938 clocks = <&aoss_qmp>;
2187 clock-names = "apb_pc 1939 clock-names = "apb_pclk";
2188 1940
2189 out-ports { 1941 out-ports {
2190 #address-cell 1942 #address-cells = <1>;
2191 #size-cells = 1943 #size-cells = <0>;
2192 1944
2193 port@1 { 1945 port@1 {
2194 reg = 1946 reg = <1>;
2195 swao_ 1947 swao_rep_out1: endpoint {
2196 1948 remote-endpoint =
2197 1949 <&eud_in>;
2198 }; 1950 };
2199 }; 1951 };
2200 }; 1952 };
2201 1953
2202 in-ports { 1954 in-ports {
2203 port { 1955 port {
2204 swao_ 1956 swao_rep_in: endpoint {
2205 1957 remote-endpoint =
2206 1958 <&etf0_out>;
2207 }; 1959 };
2208 }; 1960 };
2209 }; 1961 };
2210 }; 1962 };
2211 1963
2212 tpda@4b08000 { 1964 tpda@4b08000 {
2213 compatible = "qcom,co 1965 compatible = "qcom,coresight-tpda", "arm,primecell";
2214 reg = <0x0 0x4b08000 1966 reg = <0x0 0x4b08000 0x0 0x1000>;
2215 1967
2216 clocks = <&aoss_qmp>; 1968 clocks = <&aoss_qmp>;
2217 clock-names = "apb_pc 1969 clock-names = "apb_pclk";
2218 1970
2219 out-ports { 1971 out-ports {
2220 port { 1972 port {
2221 aoss_ 1973 aoss_tpda_out: endpoint {
2222 1974 remote-endpoint =
2223 1975 <&aoss_funnel_in6>;
2224 }; 1976 };
2225 }; 1977 };
2226 }; 1978 };
2227 1979
2228 in-ports { 1980 in-ports {
2229 #address-cell 1981 #address-cells = <1>;
2230 #size-cells = 1982 #size-cells = <0>;
2231 1983
2232 port@0 { 1984 port@0 {
2233 reg = 1985 reg = <0>;
2234 aoss_ 1986 aoss_tpda_in0: endpoint {
2235 1987 remote-endpoint =
2236 1988 <&aoss_tpdm0_out>;
2237 }; 1989 };
2238 }; 1990 };
2239 1991
2240 port@1 { 1992 port@1 {
2241 reg = 1993 reg = <1>;
2242 aoss_ 1994 aoss_tpda_in1: endpoint {
2243 1995 remote-endpoint =
2244 1996 <&aoss_tpdm1_out>;
2245 }; 1997 };
2246 }; 1998 };
2247 1999
2248 port@2 { 2000 port@2 {
2249 reg = 2001 reg = <2>;
2250 aoss_ 2002 aoss_tpda_in2: endpoint {
2251 2003 remote-endpoint =
2252 2004 <&aoss_tpdm2_out>;
2253 }; 2005 };
2254 }; 2006 };
2255 2007
2256 port@3 { 2008 port@3 {
2257 reg = 2009 reg = <3>;
2258 aoss_ 2010 aoss_tpda_in3: endpoint {
2259 2011 remote-endpoint =
2260 2012 <&aoss_tpdm3_out>;
2261 }; 2013 };
2262 }; 2014 };
2263 2015
2264 port@4 { 2016 port@4 {
2265 reg = 2017 reg = <4>;
2266 aoss_ 2018 aoss_tpda_in4: endpoint {
2267 2019 remote-endpoint =
2268 2020 <&aoss_tpdm4_out>;
2269 }; 2021 };
2270 }; 2022 };
2271 }; 2023 };
2272 }; 2024 };
2273 2025
2274 tpdm@4b09000 { 2026 tpdm@4b09000 {
2275 compatible = "qcom,co 2027 compatible = "qcom,coresight-tpdm", "arm,primecell";
2276 reg = <0x0 0x4b09000 2028 reg = <0x0 0x4b09000 0x0 0x1000>;
2277 2029
2278 clocks = <&aoss_qmp>; 2030 clocks = <&aoss_qmp>;
2279 clock-names = "apb_pc 2031 clock-names = "apb_pclk";
2280 2032
2281 qcom,cmb-element-bits 2033 qcom,cmb-element-bits = <64>;
2282 qcom,cmb-msrs-num = < 2034 qcom,cmb-msrs-num = <32>;
2283 2035
2284 out-ports { 2036 out-ports {
2285 port { 2037 port {
2286 aoss_ 2038 aoss_tpdm0_out: endpoint {
2287 2039 remote-endpoint =
2288 2040 <&aoss_tpda_in0>;
2289 }; 2041 };
2290 }; 2042 };
2291 }; 2043 };
2292 }; 2044 };
2293 2045
2294 tpdm@4b0a000 { 2046 tpdm@4b0a000 {
2295 compatible = "qcom,co 2047 compatible = "qcom,coresight-tpdm", "arm,primecell";
2296 reg = <0x0 0x4b0a000 2048 reg = <0x0 0x4b0a000 0x0 0x1000>;
2297 2049
2298 clocks = <&aoss_qmp>; 2050 clocks = <&aoss_qmp>;
2299 clock-names = "apb_pc 2051 clock-names = "apb_pclk";
2300 2052
2301 qcom,cmb-element-bits 2053 qcom,cmb-element-bits = <64>;
2302 qcom,cmb-msrs-num = < 2054 qcom,cmb-msrs-num = <32>;
2303 2055
2304 out-ports { 2056 out-ports {
2305 port { 2057 port {
2306 aoss_ 2058 aoss_tpdm1_out: endpoint {
2307 2059 remote-endpoint =
2308 2060 <&aoss_tpda_in1>;
2309 }; 2061 };
2310 }; 2062 };
2311 }; 2063 };
2312 }; 2064 };
2313 2065
2314 tpdm@4b0b000 { 2066 tpdm@4b0b000 {
2315 compatible = "qcom,co 2067 compatible = "qcom,coresight-tpdm", "arm,primecell";
2316 reg = <0x0 0x4b0b000 2068 reg = <0x0 0x4b0b000 0x0 0x1000>;
2317 2069
2318 clocks = <&aoss_qmp>; 2070 clocks = <&aoss_qmp>;
2319 clock-names = "apb_pc 2071 clock-names = "apb_pclk";
2320 2072
2321 qcom,cmb-element-bits 2073 qcom,cmb-element-bits = <64>;
2322 qcom,cmb-msrs-num = < 2074 qcom,cmb-msrs-num = <32>;
2323 2075
2324 out-ports { 2076 out-ports {
2325 port { 2077 port {
2326 aoss_ 2078 aoss_tpdm2_out: endpoint {
2327 2079 remote-endpoint =
2328 2080 <&aoss_tpda_in2>;
2329 }; 2081 };
2330 }; 2082 };
2331 }; 2083 };
2332 }; 2084 };
2333 2085
2334 tpdm@4b0c000 { 2086 tpdm@4b0c000 {
2335 compatible = "qcom,co 2087 compatible = "qcom,coresight-tpdm", "arm,primecell";
2336 reg = <0x0 0x4b0c000 2088 reg = <0x0 0x4b0c000 0x0 0x1000>;
2337 2089
2338 clocks = <&aoss_qmp>; 2090 clocks = <&aoss_qmp>;
2339 clock-names = "apb_pc 2091 clock-names = "apb_pclk";
2340 2092
2341 qcom,cmb-element-bits 2093 qcom,cmb-element-bits = <64>;
2342 qcom,cmb-msrs-num = < 2094 qcom,cmb-msrs-num = <32>;
2343 2095
2344 out-ports { 2096 out-ports {
2345 port { 2097 port {
2346 aoss_ 2098 aoss_tpdm3_out: endpoint {
2347 2099 remote-endpoint =
2348 2100 <&aoss_tpda_in3>;
2349 }; 2101 };
2350 }; 2102 };
2351 }; 2103 };
2352 }; 2104 };
2353 2105
2354 tpdm@4b0d000 { 2106 tpdm@4b0d000 {
2355 compatible = "qcom,co 2107 compatible = "qcom,coresight-tpdm", "arm,primecell";
2356 reg = <0x0 0x4b0d000 2108 reg = <0x0 0x4b0d000 0x0 0x1000>;
2357 2109
2358 clocks = <&aoss_qmp>; 2110 clocks = <&aoss_qmp>;
2359 clock-names = "apb_pc 2111 clock-names = "apb_pclk";
2360 2112
2361 qcom,dsb-element-bits 2113 qcom,dsb-element-bits = <32>;
2362 qcom,dsb-msrs-num = < 2114 qcom,dsb-msrs-num = <32>;
2363 2115
2364 out-ports { 2116 out-ports {
2365 port { 2117 port {
2366 aoss_ 2118 aoss_tpdm4_out: endpoint {
2367 2119 remote-endpoint =
2368 2120 <&aoss_tpda_in4>;
2369 }; 2121 };
2370 }; 2122 };
2371 }; 2123 };
2372 }; 2124 };
2373 2125
2374 aoss_cti: cti@4b13000 { 2126 aoss_cti: cti@4b13000 {
2375 compatible = "arm,cor 2127 compatible = "arm,coresight-cti", "arm,primecell";
2376 reg = <0x0 0x4b13000 2128 reg = <0x0 0x4b13000 0x0 0x1000>;
2377 2129
2378 clocks = <&aoss_qmp>; 2130 clocks = <&aoss_qmp>;
2379 clock-names = "apb_pc 2131 clock-names = "apb_pclk";
2380 }; 2132 };
2381 2133
2382 etm@6040000 { 2134 etm@6040000 {
2383 compatible = "arm,pri 2135 compatible = "arm,primecell";
2384 reg = <0x0 0x6040000 2136 reg = <0x0 0x6040000 0x0 0x1000>;
2385 cpu = <&CPU0>; 2137 cpu = <&CPU0>;
2386 2138
2387 clocks = <&aoss_qmp>; 2139 clocks = <&aoss_qmp>;
2388 clock-names = "apb_pc 2140 clock-names = "apb_pclk";
2389 arm,coresight-loses-c 2141 arm,coresight-loses-context-with-cpu;
2390 qcom,skip-power-up; 2142 qcom,skip-power-up;
2391 2143
2392 out-ports { 2144 out-ports {
2393 port { 2145 port {
2394 etm0_ 2146 etm0_out: endpoint {
2395 2147 remote-endpoint =
2396 2148 <&apss_funnel0_in0>;
2397 }; 2149 };
2398 }; 2150 };
2399 }; 2151 };
2400 }; 2152 };
2401 2153
2402 etm@6140000 { 2154 etm@6140000 {
2403 compatible = "arm,pri 2155 compatible = "arm,primecell";
2404 reg = <0x0 0x6140000 2156 reg = <0x0 0x6140000 0x0 0x1000>;
2405 cpu = <&CPU1>; 2157 cpu = <&CPU1>;
2406 2158
2407 clocks = <&aoss_qmp>; 2159 clocks = <&aoss_qmp>;
2408 clock-names = "apb_pc 2160 clock-names = "apb_pclk";
2409 arm,coresight-loses-c 2161 arm,coresight-loses-context-with-cpu;
2410 qcom,skip-power-up; 2162 qcom,skip-power-up;
2411 2163
2412 out-ports { 2164 out-ports {
2413 port { 2165 port {
2414 etm1_ 2166 etm1_out: endpoint {
2415 2167 remote-endpoint =
2416 2168 <&apss_funnel0_in1>;
2417 }; 2169 };
2418 }; 2170 };
2419 }; 2171 };
2420 }; 2172 };
2421 2173
2422 etm@6240000 { 2174 etm@6240000 {
2423 compatible = "arm,pri 2175 compatible = "arm,primecell";
2424 reg = <0x0 0x6240000 2176 reg = <0x0 0x6240000 0x0 0x1000>;
2425 cpu = <&CPU2>; 2177 cpu = <&CPU2>;
2426 2178
2427 clocks = <&aoss_qmp>; 2179 clocks = <&aoss_qmp>;
2428 clock-names = "apb_pc 2180 clock-names = "apb_pclk";
2429 arm,coresight-loses-c 2181 arm,coresight-loses-context-with-cpu;
2430 qcom,skip-power-up; 2182 qcom,skip-power-up;
2431 2183
2432 out-ports { 2184 out-ports {
2433 port { 2185 port {
2434 etm2_ 2186 etm2_out: endpoint {
2435 2187 remote-endpoint =
2436 2188 <&apss_funnel0_in2>;
2437 }; 2189 };
2438 }; 2190 };
2439 }; 2191 };
2440 }; 2192 };
2441 2193
2442 etm@6340000 { 2194 etm@6340000 {
2443 compatible = "arm,pri 2195 compatible = "arm,primecell";
2444 reg = <0x0 0x6340000 2196 reg = <0x0 0x6340000 0x0 0x1000>;
2445 cpu = <&CPU3>; 2197 cpu = <&CPU3>;
2446 2198
2447 clocks = <&aoss_qmp>; 2199 clocks = <&aoss_qmp>;
2448 clock-names = "apb_pc 2200 clock-names = "apb_pclk";
2449 arm,coresight-loses-c 2201 arm,coresight-loses-context-with-cpu;
2450 qcom,skip-power-up; 2202 qcom,skip-power-up;
2451 2203
2452 out-ports { 2204 out-ports {
2453 port { 2205 port {
2454 etm3_ 2206 etm3_out: endpoint {
2455 2207 remote-endpoint =
2456 2208 <&apss_funnel0_in3>;
2457 }; 2209 };
2458 }; 2210 };
2459 }; 2211 };
2460 }; 2212 };
2461 2213
2462 etm@6440000 { 2214 etm@6440000 {
2463 compatible = "arm,pri 2215 compatible = "arm,primecell";
2464 reg = <0x0 0x6440000 2216 reg = <0x0 0x6440000 0x0 0x1000>;
2465 cpu = <&CPU4>; 2217 cpu = <&CPU4>;
2466 2218
2467 clocks = <&aoss_qmp>; 2219 clocks = <&aoss_qmp>;
2468 clock-names = "apb_pc 2220 clock-names = "apb_pclk";
2469 arm,coresight-loses-c 2221 arm,coresight-loses-context-with-cpu;
2470 qcom,skip-power-up; 2222 qcom,skip-power-up;
2471 2223
2472 out-ports { 2224 out-ports {
2473 port { 2225 port {
2474 etm4_ 2226 etm4_out: endpoint {
2475 2227 remote-endpoint =
2476 2228 <&apss_funnel0_in4>;
2477 }; 2229 };
2478 }; 2230 };
2479 }; 2231 };
2480 }; 2232 };
2481 2233
2482 etm@6540000 { 2234 etm@6540000 {
2483 compatible = "arm,pri 2235 compatible = "arm,primecell";
2484 reg = <0x0 0x6540000 2236 reg = <0x0 0x6540000 0x0 0x1000>;
2485 cpu = <&CPU5>; 2237 cpu = <&CPU5>;
2486 2238
2487 clocks = <&aoss_qmp>; 2239 clocks = <&aoss_qmp>;
2488 clock-names = "apb_pc 2240 clock-names = "apb_pclk";
2489 arm,coresight-loses-c 2241 arm,coresight-loses-context-with-cpu;
2490 qcom,skip-power-up; 2242 qcom,skip-power-up;
2491 2243
2492 out-ports { 2244 out-ports {
2493 port { 2245 port {
2494 etm5_ 2246 etm5_out: endpoint {
2495 2247 remote-endpoint =
2496 2248 <&apss_funnel0_in5>;
2497 }; 2249 };
2498 }; 2250 };
2499 }; 2251 };
2500 }; 2252 };
2501 2253
2502 etm@6640000 { 2254 etm@6640000 {
2503 compatible = "arm,pri 2255 compatible = "arm,primecell";
2504 reg = <0x0 0x6640000 2256 reg = <0x0 0x6640000 0x0 0x1000>;
2505 cpu = <&CPU6>; 2257 cpu = <&CPU6>;
2506 2258
2507 clocks = <&aoss_qmp>; 2259 clocks = <&aoss_qmp>;
2508 clock-names = "apb_pc 2260 clock-names = "apb_pclk";
2509 arm,coresight-loses-c 2261 arm,coresight-loses-context-with-cpu;
2510 qcom,skip-power-up; 2262 qcom,skip-power-up;
2511 2263
2512 out-ports { 2264 out-ports {
2513 port { 2265 port {
2514 etm6_ 2266 etm6_out: endpoint {
2515 2267 remote-endpoint =
2516 2268 <&apss_funnel0_in6>;
2517 }; 2269 };
2518 }; 2270 };
2519 }; 2271 };
2520 }; 2272 };
2521 2273
2522 etm@6740000 { 2274 etm@6740000 {
2523 compatible = "arm,pri 2275 compatible = "arm,primecell";
2524 reg = <0x0 0x6740000 2276 reg = <0x0 0x6740000 0x0 0x1000>;
2525 cpu = <&CPU7>; 2277 cpu = <&CPU7>;
2526 2278
2527 clocks = <&aoss_qmp>; 2279 clocks = <&aoss_qmp>;
2528 clock-names = "apb_pc 2280 clock-names = "apb_pclk";
2529 arm,coresight-loses-c 2281 arm,coresight-loses-context-with-cpu;
2530 qcom,skip-power-up; 2282 qcom,skip-power-up;
2531 2283
2532 out-ports { 2284 out-ports {
2533 port { 2285 port {
2534 etm7_ 2286 etm7_out: endpoint {
2535 2287 remote-endpoint =
2536 2288 <&apss_funnel0_in7>;
2537 }; 2289 };
2538 }; 2290 };
2539 }; 2291 };
2540 }; 2292 };
2541 2293
2542 funnel@6800000 { 2294 funnel@6800000 {
2543 compatible = "arm,cor 2295 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2544 reg = <0x0 0x6800000 2296 reg = <0x0 0x6800000 0x0 0x1000>;
2545 2297
2546 clocks = <&aoss_qmp>; 2298 clocks = <&aoss_qmp>;
2547 clock-names = "apb_pc 2299 clock-names = "apb_pclk";
2548 2300
2549 out-ports { 2301 out-ports {
2550 port { 2302 port {
2551 apss_ 2303 apss_funnel0_out: endpoint {
2552 2304 remote-endpoint =
2553 2305 <&apss_funnel1_in0>;
2554 }; 2306 };
2555 }; 2307 };
2556 }; 2308 };
2557 2309
2558 in-ports { 2310 in-ports {
2559 #address-cell 2311 #address-cells = <1>;
2560 #size-cells = 2312 #size-cells = <0>;
2561 2313
2562 port@0 { 2314 port@0 {
2563 reg = 2315 reg = <0>;
2564 apss_ 2316 apss_funnel0_in0: endpoint {
2565 2317 remote-endpoint =
2566 2318 <&etm0_out>;
2567 }; 2319 };
2568 }; 2320 };
2569 2321
2570 port@1 { 2322 port@1 {
2571 reg = 2323 reg = <1>;
2572 apss_ 2324 apss_funnel0_in1: endpoint {
2573 2325 remote-endpoint =
2574 2326 <&etm1_out>;
2575 }; 2327 };
2576 }; 2328 };
2577 2329
2578 port@2 { 2330 port@2 {
2579 reg = 2331 reg = <2>;
2580 apss_ 2332 apss_funnel0_in2: endpoint {
2581 2333 remote-endpoint =
2582 2334 <&etm2_out>;
2583 }; 2335 };
2584 }; 2336 };
2585 2337
2586 port@3 { 2338 port@3 {
2587 reg = 2339 reg = <3>;
2588 apss_ 2340 apss_funnel0_in3: endpoint {
2589 2341 remote-endpoint =
2590 2342 <&etm3_out>;
2591 }; 2343 };
2592 }; 2344 };
2593 2345
2594 port@4 { 2346 port@4 {
2595 reg = 2347 reg = <4>;
2596 apss_ 2348 apss_funnel0_in4: endpoint {
2597 2349 remote-endpoint =
2598 2350 <&etm4_out>;
2599 }; 2351 };
2600 }; 2352 };
2601 2353
2602 port@5 { 2354 port@5 {
2603 reg = 2355 reg = <5>;
2604 apss_ 2356 apss_funnel0_in5: endpoint {
2605 2357 remote-endpoint =
2606 2358 <&etm5_out>;
2607 }; 2359 };
2608 }; 2360 };
2609 2361
2610 port@6 { 2362 port@6 {
2611 reg = 2363 reg = <6>;
2612 apss_ 2364 apss_funnel0_in6: endpoint {
2613 2365 remote-endpoint =
2614 2366 <&etm6_out>;
2615 }; 2367 };
2616 }; 2368 };
2617 2369
2618 port@7 { 2370 port@7 {
2619 reg = 2371 reg = <7>;
2620 apss_ 2372 apss_funnel0_in7: endpoint {
2621 2373 remote-endpoint =
2622 2374 <&etm7_out>;
2623 }; 2375 };
2624 }; 2376 };
2625 }; 2377 };
2626 }; 2378 };
2627 2379
2628 funnel@6810000 { 2380 funnel@6810000 {
2629 compatible = "arm,cor 2381 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2630 reg = <0x0 0x6810000 2382 reg = <0x0 0x6810000 0x0 0x1000>;
2631 2383
2632 clocks = <&aoss_qmp>; 2384 clocks = <&aoss_qmp>;
2633 clock-names = "apb_pc 2385 clock-names = "apb_pclk";
2634 2386
2635 out-ports { 2387 out-ports {
2636 port { 2388 port {
2637 apss_ 2389 apss_funnel1_out: endpoint {
2638 2390 remote-endpoint =
2639 2391 <&funnel1_in4>;
2640 }; 2392 };
2641 }; 2393 };
2642 }; 2394 };
2643 2395
2644 in-ports { 2396 in-ports {
2645 #address-cell 2397 #address-cells = <1>;
2646 #size-cells = 2398 #size-cells = <0>;
2647 2399
2648 port@0 { 2400 port@0 {
2649 reg = 2401 reg = <0>;
2650 apss_ 2402 apss_funnel1_in0: endpoint {
2651 2403 remote-endpoint =
2652 2404 <&apss_funnel0_out>;
2653 }; 2405 };
2654 }; 2406 };
2655 2407
2656 port@3 { 2408 port@3 {
2657 reg = 2409 reg = <3>;
2658 apss_ 2410 apss_funnel1_in3: endpoint {
2659 2411 remote-endpoint =
2660 2412 <&apss_tpda_out>;
2661 }; 2413 };
2662 }; 2414 };
2663 }; 2415 };
2664 }; 2416 };
2665 2417
2666 tpdm@6860000 { 2418 tpdm@6860000 {
2667 compatible = "qcom,co 2419 compatible = "qcom,coresight-tpdm", "arm,primecell";
2668 reg = <0x0 0x6860000 2420 reg = <0x0 0x6860000 0x0 0x1000>;
2669 2421
2670 clocks = <&aoss_qmp>; 2422 clocks = <&aoss_qmp>;
2671 clock-names = "apb_pc 2423 clock-names = "apb_pclk";
2672 2424
2673 qcom,cmb-element-bits 2425 qcom,cmb-element-bits = <64>;
2674 qcom,cmb-msrs-num = < 2426 qcom,cmb-msrs-num = <32>;
2675 2427
2676 out-ports { 2428 out-ports {
2677 port { 2429 port {
2678 apss_ 2430 apss_tpdm3_out: endpoint {
2679 2431 remote-endpoint =
2680 2432 <&apss_tpda_in3>;
2681 }; 2433 };
2682 }; 2434 };
2683 }; 2435 };
2684 }; 2436 };
2685 2437
2686 tpdm@6861000 { 2438 tpdm@6861000 {
2687 compatible = "qcom,co 2439 compatible = "qcom,coresight-tpdm", "arm,primecell";
2688 reg = <0x0 0x6861000 2440 reg = <0x0 0x6861000 0x0 0x1000>;
2689 2441
2690 clocks = <&aoss_qmp>; 2442 clocks = <&aoss_qmp>;
2691 clock-names = "apb_pc 2443 clock-names = "apb_pclk";
2692 2444
2693 qcom,dsb-element-bits 2445 qcom,dsb-element-bits = <32>;
2694 qcom,dsb-msrs-num = < 2446 qcom,dsb-msrs-num = <32>;
2695 2447
2696 out-ports { 2448 out-ports {
2697 port { 2449 port {
2698 apss_ 2450 apss_tpdm4_out: endpoint {
2699 2451 remote-endpoint =
2700 2452 <&apss_tpda_in4>;
2701 }; 2453 };
2702 }; 2454 };
2703 }; 2455 };
2704 }; 2456 };
2705 2457
2706 tpda@6863000 { 2458 tpda@6863000 {
2707 compatible = "qcom,co 2459 compatible = "qcom,coresight-tpda", "arm,primecell";
2708 reg = <0x0 0x6863000 2460 reg = <0x0 0x6863000 0x0 0x1000>;
2709 2461
2710 clocks = <&aoss_qmp>; 2462 clocks = <&aoss_qmp>;
2711 clock-names = "apb_pc 2463 clock-names = "apb_pclk";
2712 2464
2713 out-ports { 2465 out-ports {
2714 port { 2466 port {
2715 apss_ 2467 apss_tpda_out: endpoint {
2716 2468 remote-endpoint =
2717 2469 <&apss_funnel1_in3>;
2718 }; 2470 };
2719 }; 2471 };
2720 }; 2472 };
2721 2473
2722 in-ports { 2474 in-ports {
2723 #address-cell 2475 #address-cells = <1>;
2724 #size-cells = 2476 #size-cells = <0>;
2725 2477
2726 port@0 { 2478 port@0 {
2727 reg = 2479 reg = <0>;
2728 apss_ 2480 apss_tpda_in0: endpoint {
2729 2481 remote-endpoint =
2730 2482 <&apss_tpdm0_out>;
2731 }; 2483 };
2732 }; 2484 };
2733 2485
2734 port@1 { 2486 port@1 {
2735 reg = 2487 reg = <1>;
2736 apss_ 2488 apss_tpda_in1: endpoint {
2737 2489 remote-endpoint =
2738 2490 <&apss_tpdm1_out>;
2739 }; 2491 };
2740 }; 2492 };
2741 2493
2742 port@2 { 2494 port@2 {
2743 reg = 2495 reg = <2>;
2744 apss_ 2496 apss_tpda_in2: endpoint {
2745 2497 remote-endpoint =
2746 2498 <&apss_tpdm2_out>;
2747 }; 2499 };
2748 }; 2500 };
2749 2501
2750 port@3 { 2502 port@3 {
2751 reg = 2503 reg = <3>;
2752 apss_ 2504 apss_tpda_in3: endpoint {
2753 2505 remote-endpoint =
2754 2506 <&apss_tpdm3_out>;
2755 }; 2507 };
2756 }; 2508 };
2757 2509
2758 port@4 { 2510 port@4 {
2759 reg = 2511 reg = <4>;
2760 apss_ 2512 apss_tpda_in4: endpoint {
2761 2513 remote-endpoint =
2762 2514 <&apss_tpdm4_out>;
2763 }; 2515 };
2764 }; 2516 };
2765 }; 2517 };
2766 }; 2518 };
2767 2519
2768 tpdm@68a0000 { 2520 tpdm@68a0000 {
2769 compatible = "qcom,co 2521 compatible = "qcom,coresight-tpdm", "arm,primecell";
2770 reg = <0x0 0x68a0000 2522 reg = <0x0 0x68a0000 0x0 0x1000>;
2771 2523
2772 clocks = <&aoss_qmp>; 2524 clocks = <&aoss_qmp>;
2773 clock-names = "apb_pc 2525 clock-names = "apb_pclk";
2774 2526
2775 qcom,cmb-element-bits 2527 qcom,cmb-element-bits = <32>;
2776 qcom,cmb-msrs-num = < 2528 qcom,cmb-msrs-num = <32>;
2777 2529
2778 out-ports { 2530 out-ports {
2779 port { 2531 port {
2780 apss_ 2532 apss_tpdm0_out: endpoint {
2781 2533 remote-endpoint =
2782 2534 <&apss_tpda_in0>;
2783 }; 2535 };
2784 }; 2536 };
2785 }; 2537 };
2786 }; 2538 };
2787 2539
2788 tpdm@68b0000 { 2540 tpdm@68b0000 {
2789 compatible = "qcom,co 2541 compatible = "qcom,coresight-tpdm", "arm,primecell";
2790 reg = <0x0 0x68b0000 2542 reg = <0x0 0x68b0000 0x0 0x1000>;
2791 2543
2792 clocks = <&aoss_qmp>; 2544 clocks = <&aoss_qmp>;
2793 clock-names = "apb_pc 2545 clock-names = "apb_pclk";
2794 2546
2795 qcom,cmb-element-bits 2547 qcom,cmb-element-bits = <32>;
2796 qcom,cmb-msrs-num = < 2548 qcom,cmb-msrs-num = <32>;
2797 2549
2798 out-ports { 2550 out-ports {
2799 port { 2551 port {
2800 apss_ 2552 apss_tpdm1_out: endpoint {
2801 2553 remote-endpoint =
2802 2554 <&apss_tpda_in1>;
2803 }; 2555 };
2804 }; 2556 };
2805 }; 2557 };
2806 }; 2558 };
2807 2559
2808 tpdm@68c0000 { 2560 tpdm@68c0000 {
2809 compatible = "qcom,co 2561 compatible = "qcom,coresight-tpdm", "arm,primecell";
2810 reg = <0x0 0x68c0000 2562 reg = <0x0 0x68c0000 0x0 0x1000>;
2811 2563
2812 clocks = <&aoss_qmp>; 2564 clocks = <&aoss_qmp>;
2813 clock-names = "apb_pc 2565 clock-names = "apb_pclk";
2814 2566
2815 qcom,dsb-element-bits 2567 qcom,dsb-element-bits = <32>;
2816 qcom,dsb-msrs-num = < 2568 qcom,dsb-msrs-num = <32>;
2817 2569
2818 out-ports { 2570 out-ports {
2819 port { 2571 port {
2820 apss_ 2572 apss_tpdm2_out: endpoint {
2821 2573 remote-endpoint =
2822 2574 <&apss_tpda_in2>;
2823 }; 2575 };
2824 }; 2576 };
2825 }; 2577 };
2826 }; 2578 };
2827 2579
2828 usb_0_hsphy: phy@88e4000 { 2580 usb_0_hsphy: phy@88e4000 {
2829 compatible = "qcom,sa 2581 compatible = "qcom,sa8775p-usb-hs-phy",
2830 "qcom,us 2582 "qcom,usb-snps-hs-5nm-phy";
2831 reg = <0 0x088e4000 0 2583 reg = <0 0x088e4000 0 0x120>;
2832 clocks = <&rpmhcc RPM 2584 clocks = <&rpmhcc RPMH_CXO_CLK>;
2833 clock-names = "ref"; 2585 clock-names = "ref";
2834 resets = <&gcc GCC_US 2586 resets = <&gcc GCC_USB2_PHY_PRIM_BCR>;
2835 2587
2836 #phy-cells = <0>; 2588 #phy-cells = <0>;
2837 2589
2838 status = "disabled"; 2590 status = "disabled";
2839 }; 2591 };
2840 2592
2841 usb_0_qmpphy: phy@88e8000 { 2593 usb_0_qmpphy: phy@88e8000 {
2842 compatible = "qcom,sa 2594 compatible = "qcom,sa8775p-qmp-usb3-uni-phy";
2843 reg = <0 0x088e8000 0 2595 reg = <0 0x088e8000 0 0x2000>;
2844 2596
2845 clocks = <&gcc GCC_US 2597 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2846 <&gcc GCC_US 2598 <&gcc GCC_USB_CLKREF_EN>,
2847 <&gcc GCC_US 2599 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
2848 <&gcc GCC_US 2600 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2849 clock-names = "aux", 2601 clock-names = "aux", "ref", "com_aux", "pipe";
2850 2602
2851 resets = <&gcc GCC_US 2603 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
2852 <&gcc GCC_US 2604 <&gcc GCC_USB3PHY_PHY_PRIM_BCR>;
2853 reset-names = "phy", 2605 reset-names = "phy", "phy_phy";
2854 2606
2855 power-domains = <&gcc 2607 power-domains = <&gcc USB30_PRIM_GDSC>;
2856 2608
2857 #clock-cells = <0>; 2609 #clock-cells = <0>;
2858 clock-output-names = 2610 clock-output-names = "usb3_prim_phy_pipe_clk_src";
2859 2611
2860 #phy-cells = <0>; 2612 #phy-cells = <0>;
2861 2613
2862 status = "disabled"; 2614 status = "disabled";
2863 }; 2615 };
2864 2616
2865 usb_0: usb@a6f8800 { 2617 usb_0: usb@a6f8800 {
2866 compatible = "qcom,sa 2618 compatible = "qcom,sa8775p-dwc3", "qcom,dwc3";
2867 reg = <0 0x0a6f8800 0 2619 reg = <0 0x0a6f8800 0 0x400>;
2868 #address-cells = <2>; 2620 #address-cells = <2>;
2869 #size-cells = <2>; 2621 #size-cells = <2>;
2870 ranges; 2622 ranges;
2871 2623
2872 clocks = <&gcc GCC_CF 2624 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
2873 <&gcc GCC_US 2625 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
2874 <&gcc GCC_AG 2626 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
2875 <&gcc GCC_US 2627 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
2876 <&gcc GCC_US 2628 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
2877 clock-names = "cfg_no 2629 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi";
2878 2630
2879 assigned-clocks = <&g 2631 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2880 <&g 2632 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
2881 assigned-clock-rates 2633 assigned-clock-rates = <19200000>, <200000000>;
2882 2634
2883 interrupts-extended = 2635 interrupts-extended = <&intc GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>,
2884 2636 <&intc GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
2885 2637 <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
2886 2638 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
2887 2639 <&pdc 12 IRQ_TYPE_LEVEL_HIGH>;
2888 interrupt-names = "pw 2640 interrupt-names = "pwr_event",
2889 "hs 2641 "hs_phy_irq",
2890 "dp 2642 "dp_hs_phy_irq",
2891 "dm 2643 "dm_hs_phy_irq",
2892 "ss 2644 "ss_phy_irq";
2893 2645
2894 power-domains = <&gcc 2646 power-domains = <&gcc USB30_PRIM_GDSC>;
2895 required-opps = <&rpm 2647 required-opps = <&rpmhpd_opp_nom>;
2896 2648
2897 resets = <&gcc GCC_US 2649 resets = <&gcc GCC_USB30_PRIM_BCR>;
2898 2650
2899 interconnects = <&agg 2651 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
2900 <&gem 2652 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
2901 interconnect-names = 2653 interconnect-names = "usb-ddr", "apps-usb";
2902 2654
2903 wakeup-source; 2655 wakeup-source;
2904 2656
2905 status = "disabled"; 2657 status = "disabled";
2906 2658
2907 usb_0_dwc3: usb@a6000 2659 usb_0_dwc3: usb@a600000 {
2908 compatible = 2660 compatible = "snps,dwc3";
2909 reg = <0 0x0a 2661 reg = <0 0x0a600000 0 0xe000>;
2910 interrupts = 2662 interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>;
2911 iommus = <&ap 2663 iommus = <&apps_smmu 0x080 0x0>;
2912 phys = <&usb_ 2664 phys = <&usb_0_hsphy>, <&usb_0_qmpphy>;
2913 phy-names = " 2665 phy-names = "usb2-phy", "usb3-phy";
2914 }; 2666 };
2915 }; 2667 };
2916 2668
2917 usb_1_hsphy: phy@88e6000 { 2669 usb_1_hsphy: phy@88e6000 {
2918 compatible = "qcom,sa 2670 compatible = "qcom,sa8775p-usb-hs-phy",
2919 "qcom,us 2671 "qcom,usb-snps-hs-5nm-phy";
2920 reg = <0 0x088e6000 0 2672 reg = <0 0x088e6000 0 0x120>;
2921 clocks = <&gcc GCC_US 2673 clocks = <&gcc GCC_USB_CLKREF_EN>;
2922 clock-names = "ref"; 2674 clock-names = "ref";
2923 resets = <&gcc GCC_US 2675 resets = <&gcc GCC_USB2_PHY_SEC_BCR>;
2924 2676
2925 #phy-cells = <0>; 2677 #phy-cells = <0>;
2926 2678
2927 status = "disabled"; 2679 status = "disabled";
2928 }; 2680 };
2929 2681
2930 usb_1_qmpphy: phy@88ea000 { 2682 usb_1_qmpphy: phy@88ea000 {
2931 compatible = "qcom,sa 2683 compatible = "qcom,sa8775p-qmp-usb3-uni-phy";
2932 reg = <0 0x088ea000 0 2684 reg = <0 0x088ea000 0 0x2000>;
2933 2685
2934 clocks = <&gcc GCC_US 2686 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
2935 <&gcc GCC_US 2687 <&gcc GCC_USB_CLKREF_EN>,
2936 <&gcc GCC_US 2688 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
2937 <&gcc GCC_US 2689 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
2938 clock-names = "aux", 2690 clock-names = "aux", "ref", "com_aux", "pipe";
2939 2691
2940 resets = <&gcc GCC_US 2692 resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
2941 <&gcc GCC_US 2693 <&gcc GCC_USB3PHY_PHY_SEC_BCR>;
2942 reset-names = "phy", 2694 reset-names = "phy", "phy_phy";
2943 2695
2944 power-domains = <&gcc 2696 power-domains = <&gcc USB30_SEC_GDSC>;
2945 2697
2946 #clock-cells = <0>; 2698 #clock-cells = <0>;
2947 clock-output-names = 2699 clock-output-names = "usb3_sec_phy_pipe_clk_src";
2948 2700
2949 #phy-cells = <0>; 2701 #phy-cells = <0>;
2950 2702
2951 status = "disabled"; 2703 status = "disabled";
2952 }; 2704 };
2953 2705
2954 usb_1: usb@a8f8800 { 2706 usb_1: usb@a8f8800 {
2955 compatible = "qcom,sa 2707 compatible = "qcom,sa8775p-dwc3", "qcom,dwc3";
2956 reg = <0 0x0a8f8800 0 2708 reg = <0 0x0a8f8800 0 0x400>;
2957 #address-cells = <2>; 2709 #address-cells = <2>;
2958 #size-cells = <2>; 2710 #size-cells = <2>;
2959 ranges; 2711 ranges;
2960 2712
2961 clocks = <&gcc GCC_CF 2713 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
2962 <&gcc GCC_US 2714 <&gcc GCC_USB30_SEC_MASTER_CLK>,
2963 <&gcc GCC_AG 2715 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
2964 <&gcc GCC_US 2716 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
2965 <&gcc GCC_US 2717 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>;
2966 clock-names = "cfg_no 2718 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi";
2967 2719
2968 assigned-clocks = <&g 2720 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2969 <&g 2721 <&gcc GCC_USB30_SEC_MASTER_CLK>;
2970 assigned-clock-rates 2722 assigned-clock-rates = <19200000>, <200000000>;
2971 2723
2972 interrupts-extended = 2724 interrupts-extended = <&intc GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
2973 2725 <&intc GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
2974 2726 <&pdc 8 IRQ_TYPE_EDGE_BOTH>,
2975 2727 <&pdc 7 IRQ_TYPE_EDGE_BOTH>,
2976 2728 <&pdc 13 IRQ_TYPE_LEVEL_HIGH>;
2977 interrupt-names = "pw 2729 interrupt-names = "pwr_event",
2978 "hs 2730 "hs_phy_irq",
2979 "dp 2731 "dp_hs_phy_irq",
2980 "dm 2732 "dm_hs_phy_irq",
2981 "ss 2733 "ss_phy_irq";
2982 2734
2983 power-domains = <&gcc 2735 power-domains = <&gcc USB30_SEC_GDSC>;
2984 required-opps = <&rpm 2736 required-opps = <&rpmhpd_opp_nom>;
2985 2737
2986 resets = <&gcc GCC_US 2738 resets = <&gcc GCC_USB30_SEC_BCR>;
2987 2739
2988 interconnects = <&agg 2740 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>,
2989 <&gem 2741 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
2990 interconnect-names = 2742 interconnect-names = "usb-ddr", "apps-usb";
2991 2743
2992 wakeup-source; 2744 wakeup-source;
2993 2745
2994 status = "disabled"; 2746 status = "disabled";
2995 2747
2996 usb_1_dwc3: usb@a8000 2748 usb_1_dwc3: usb@a800000 {
2997 compatible = 2749 compatible = "snps,dwc3";
2998 reg = <0 0x0a 2750 reg = <0 0x0a800000 0 0xe000>;
2999 interrupts = 2751 interrupts = <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>;
3000 iommus = <&ap 2752 iommus = <&apps_smmu 0x0a0 0x0>;
3001 phys = <&usb_ 2753 phys = <&usb_1_hsphy>, <&usb_1_qmpphy>;
3002 phy-names = " 2754 phy-names = "usb2-phy", "usb3-phy";
3003 }; 2755 };
3004 }; 2756 };
3005 2757
3006 usb_2_hsphy: phy@88e7000 { 2758 usb_2_hsphy: phy@88e7000 {
3007 compatible = "qcom,sa 2759 compatible = "qcom,sa8775p-usb-hs-phy",
3008 "qcom,us 2760 "qcom,usb-snps-hs-5nm-phy";
3009 reg = <0 0x088e7000 0 2761 reg = <0 0x088e7000 0 0x120>;
3010 clocks = <&gcc GCC_US 2762 clocks = <&gcc GCC_USB_CLKREF_EN>;
3011 clock-names = "ref"; 2763 clock-names = "ref";
3012 resets = <&gcc GCC_US 2764 resets = <&gcc GCC_USB3_PHY_TERT_BCR>;
3013 2765
3014 #phy-cells = <0>; 2766 #phy-cells = <0>;
3015 2767
3016 status = "disabled"; 2768 status = "disabled";
3017 }; 2769 };
3018 2770
3019 usb_2: usb@a4f8800 { 2771 usb_2: usb@a4f8800 {
3020 compatible = "qcom,sa 2772 compatible = "qcom,sa8775p-dwc3", "qcom,dwc3";
3021 reg = <0 0x0a4f8800 0 2773 reg = <0 0x0a4f8800 0 0x400>;
3022 #address-cells = <2>; 2774 #address-cells = <2>;
3023 #size-cells = <2>; 2775 #size-cells = <2>;
3024 ranges; 2776 ranges;
3025 2777
3026 clocks = <&gcc GCC_CF 2778 clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>,
3027 <&gcc GCC_US 2779 <&gcc GCC_USB20_MASTER_CLK>,
3028 <&gcc GCC_AG 2780 <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>,
3029 <&gcc GCC_US 2781 <&gcc GCC_USB20_SLEEP_CLK>,
3030 <&gcc GCC_US 2782 <&gcc GCC_USB20_MOCK_UTMI_CLK>;
3031 clock-names = "cfg_no 2783 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi";
3032 2784
3033 assigned-clocks = <&g 2785 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
3034 <&g 2786 <&gcc GCC_USB20_MASTER_CLK>;
3035 assigned-clock-rates 2787 assigned-clock-rates = <19200000>, <200000000>;
3036 2788
3037 interrupts-extended = 2789 interrupts-extended = <&intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
3038 2790 <&intc GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>,
3039 2791 <&pdc 10 IRQ_TYPE_EDGE_BOTH>,
3040 2792 <&pdc 9 IRQ_TYPE_EDGE_BOTH>;
3041 interrupt-names = "pw 2793 interrupt-names = "pwr_event",
3042 "hs 2794 "hs_phy_irq",
3043 "dp 2795 "dp_hs_phy_irq",
3044 "dm 2796 "dm_hs_phy_irq";
3045 2797
3046 power-domains = <&gcc 2798 power-domains = <&gcc USB20_PRIM_GDSC>;
3047 required-opps = <&rpm 2799 required-opps = <&rpmhpd_opp_nom>;
3048 2800
3049 resets = <&gcc GCC_US 2801 resets = <&gcc GCC_USB20_PRIM_BCR>;
3050 2802
3051 interconnects = <&agg 2803 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>,
3052 <&gem 2804 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB2 0>;
3053 interconnect-names = 2805 interconnect-names = "usb-ddr", "apps-usb";
3054 2806
3055 wakeup-source; 2807 wakeup-source;
3056 2808
3057 status = "disabled"; 2809 status = "disabled";
3058 2810
3059 usb_2_dwc3: usb@a4000 2811 usb_2_dwc3: usb@a400000 {
3060 compatible = 2812 compatible = "snps,dwc3";
3061 reg = <0 0x0a 2813 reg = <0 0x0a400000 0 0xe000>;
3062 interrupts = 2814 interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>;
3063 iommus = <&ap 2815 iommus = <&apps_smmu 0x020 0x0>;
3064 phys = <&usb_ 2816 phys = <&usb_2_hsphy>;
3065 phy-names = " 2817 phy-names = "usb2-phy";
3066 }; 2818 };
3067 }; 2819 };
3068 2820
3069 tcsr_mutex: hwlock@1f40000 { 2821 tcsr_mutex: hwlock@1f40000 {
3070 compatible = "qcom,tc 2822 compatible = "qcom,tcsr-mutex";
3071 reg = <0x0 0x01f40000 2823 reg = <0x0 0x01f40000 0x0 0x20000>;
3072 #hwlock-cells = <1>; 2824 #hwlock-cells = <1>;
3073 }; 2825 };
3074 2826
3075 gpucc: clock-controller@3d900 2827 gpucc: clock-controller@3d90000 {
3076 compatible = "qcom,sa 2828 compatible = "qcom,sa8775p-gpucc";
3077 reg = <0x0 0x03d90000 2829 reg = <0x0 0x03d90000 0x0 0xa000>;
3078 clocks = <&rpmhcc RPM 2830 clocks = <&rpmhcc RPMH_CXO_CLK>,
3079 <&gcc GCC_GP 2831 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
3080 <&gcc GCC_GP 2832 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
3081 clock-names = "bi_tcx 2833 clock-names = "bi_tcxo",
3082 "gcc_gp 2834 "gcc_gpu_gpll0_clk_src",
3083 "gcc_gp 2835 "gcc_gpu_gpll0_div_clk_src";
3084 #clock-cells = <1>; 2836 #clock-cells = <1>;
3085 #reset-cells = <1>; 2837 #reset-cells = <1>;
3086 #power-domain-cells = 2838 #power-domain-cells = <1>;
3087 }; 2839 };
3088 2840
3089 adreno_smmu: iommu@3da0000 { 2841 adreno_smmu: iommu@3da0000 {
3090 compatible = "qcom,sa 2842 compatible = "qcom,sa8775p-smmu-500", "qcom,adreno-smmu",
3091 "qcom,sm 2843 "qcom,smmu-500", "arm,mmu-500";
3092 reg = <0x0 0x03da0000 2844 reg = <0x0 0x03da0000 0x0 0x20000>;
3093 #iommu-cells = <2>; 2845 #iommu-cells = <2>;
3094 #global-interrupts = 2846 #global-interrupts = <2>;
3095 dma-coherent; 2847 dma-coherent;
3096 power-domains = <&gpu 2848 power-domains = <&gpucc GPU_CC_CX_GDSC>;
3097 clocks = <&gcc GCC_GP 2849 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
3098 <&gcc GCC_GP 2850 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
3099 <&gpucc GPU_ 2851 <&gpucc GPU_CC_AHB_CLK>,
3100 <&gpucc GPU_ 2852 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
3101 <&gpucc GPU_ 2853 <&gpucc GPU_CC_CX_GMU_CLK>,
3102 <&gpucc GPU_ 2854 <&gpucc GPU_CC_HUB_CX_INT_CLK>,
3103 <&gpucc GPU_ 2855 <&gpucc GPU_CC_HUB_AON_CLK>;
3104 clock-names = "gcc_gp 2856 clock-names = "gcc_gpu_memnoc_gfx_clk",
3105 "gcc_gp 2857 "gcc_gpu_snoc_dvm_gfx_clk",
3106 "gpu_cc 2858 "gpu_cc_ahb_clk",
3107 "gpu_cc 2859 "gpu_cc_hlos1_vote_gpu_smmu_clk",
3108 "gpu_cc 2860 "gpu_cc_cx_gmu_clk",
3109 "gpu_cc 2861 "gpu_cc_hub_cx_int_clk",
3110 "gpu_cc 2862 "gpu_cc_hub_aon_clk";
3111 interrupts = <GIC_SPI 2863 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
3112 <GIC_SPI 2864 <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
3113 <GIC_SPI 2865 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
3114 <GIC_SPI 2866 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
3115 <GIC_SPI 2867 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
3116 <GIC_SPI 2868 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
3117 <GIC_SPI 2869 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
3118 <GIC_SPI 2870 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
3119 <GIC_SPI 2871 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
3120 <GIC_SPI 2872 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
3121 <GIC_SPI 2873 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
3122 <GIC_SPI 2874 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>;
3123 }; 2875 };
3124 2876
3125 serdes0: phy@8901000 { 2877 serdes0: phy@8901000 {
3126 compatible = "qcom,sa 2878 compatible = "qcom,sa8775p-dwmac-sgmii-phy";
3127 reg = <0x0 0x08901000 2879 reg = <0x0 0x08901000 0x0 0xe10>;
3128 clocks = <&gcc GCC_SG 2880 clocks = <&gcc GCC_SGMI_CLKREF_EN>;
3129 clock-names = "sgmi_r 2881 clock-names = "sgmi_ref";
3130 #phy-cells = <0>; 2882 #phy-cells = <0>;
3131 status = "disabled"; 2883 status = "disabled";
3132 }; 2884 };
3133 2885
3134 serdes1: phy@8902000 { 2886 serdes1: phy@8902000 {
3135 compatible = "qcom,sa 2887 compatible = "qcom,sa8775p-dwmac-sgmii-phy";
3136 reg = <0x0 0x08902000 2888 reg = <0x0 0x08902000 0x0 0xe10>;
3137 clocks = <&gcc GCC_SG 2889 clocks = <&gcc GCC_SGMI_CLKREF_EN>;
3138 clock-names = "sgmi_r 2890 clock-names = "sgmi_ref";
3139 #phy-cells = <0>; 2891 #phy-cells = <0>;
3140 status = "disabled"; 2892 status = "disabled";
3141 }; 2893 };
3142 2894
3143 pmu@9091000 { <<
3144 compatible = "qcom,sa <<
3145 reg = <0x0 0x9091000 <<
3146 interrupts = <GIC_SPI <<
3147 interconnects = <&mc_ <<
3148 &mc_ <<
3149 <<
3150 operating-points-v2 = <<
3151 <<
3152 llcc_bwmon_opp_table: <<
3153 compatible = <<
3154 <<
3155 opp-0 { <<
3156 opp-p <<
3157 }; <<
3158 <<
3159 opp-1 { <<
3160 opp-p <<
3161 }; <<
3162 <<
3163 opp-2 { <<
3164 opp-p <<
3165 }; <<
3166 <<
3167 opp-3 { <<
3168 opp-p <<
3169 }; <<
3170 <<
3171 opp-4 { <<
3172 opp-p <<
3173 }; <<
3174 <<
3175 opp-5 { <<
3176 opp-p <<
3177 }; <<
3178 <<
3179 opp-6 { <<
3180 opp-p <<
3181 }; <<
3182 <<
3183 opp-7 { <<
3184 opp-p <<
3185 }; <<
3186 <<
3187 opp-8 { <<
3188 opp-p <<
3189 }; <<
3190 <<
3191 opp-9 { <<
3192 opp-p <<
3193 }; <<
3194 }; <<
3195 }; <<
3196 <<
3197 pmu@90b5400 { <<
3198 compatible = "qcom,sa <<
3199 reg = <0x0 0x90b5400 <<
3200 interrupts = <GIC_SPI <<
3201 interconnects = <&gem <<
3202 &gem <<
3203 <<
3204 operating-points-v2 = <<
3205 <<
3206 cpu_bwmon_opp_table: <<
3207 compatible = <<
3208 <<
3209 opp-0 { <<
3210 opp-p <<
3211 }; <<
3212 <<
3213 opp-1 { <<
3214 opp-p <<
3215 }; <<
3216 <<
3217 opp-2 { <<
3218 opp-p <<
3219 }; <<
3220 <<
3221 opp-3 { <<
3222 opp-p <<
3223 }; <<
3224 }; <<
3225 <<
3226 }; <<
3227 <<
3228 pmu@90b6400 { <<
3229 compatible = "qcom,sa <<
3230 reg = <0x0 0x90b6400 <<
3231 interrupts = <GIC_SPI <<
3232 interconnects = <&gem <<
3233 &gem <<
3234 <<
3235 operating-points-v2 = <<
3236 }; <<
3237 <<
3238 llcc: system-cache-controller 2895 llcc: system-cache-controller@9200000 {
3239 compatible = "qcom,sa 2896 compatible = "qcom,sa8775p-llcc";
3240 reg = <0x0 0x09200000 2897 reg = <0x0 0x09200000 0x0 0x80000>,
3241 <0x0 0x09300000 2898 <0x0 0x09300000 0x0 0x80000>,
3242 <0x0 0x09400000 2899 <0x0 0x09400000 0x0 0x80000>,
3243 <0x0 0x09500000 2900 <0x0 0x09500000 0x0 0x80000>,
3244 <0x0 0x09600000 2901 <0x0 0x09600000 0x0 0x80000>,
3245 <0x0 0x09700000 2902 <0x0 0x09700000 0x0 0x80000>,
3246 <0x0 0x09a00000 2903 <0x0 0x09a00000 0x0 0x80000>;
3247 reg-names = "llcc0_ba 2904 reg-names = "llcc0_base",
3248 "llcc1_ba 2905 "llcc1_base",
3249 "llcc2_ba 2906 "llcc2_base",
3250 "llcc3_ba 2907 "llcc3_base",
3251 "llcc4_ba 2908 "llcc4_base",
3252 "llcc5_ba 2909 "llcc5_base",
3253 "llcc_bro 2910 "llcc_broadcast_base";
3254 interrupts = <GIC_SPI 2911 interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
3255 }; 2912 };
3256 2913
3257 pdc: interrupt-controller@b22 2914 pdc: interrupt-controller@b220000 {
3258 compatible = "qcom,sa 2915 compatible = "qcom,sa8775p-pdc", "qcom,pdc";
3259 reg = <0x0 0x0b220000 2916 reg = <0x0 0x0b220000 0x0 0x30000>,
3260 <0x0 0x17c000f0 2917 <0x0 0x17c000f0 0x0 0x64>;
3261 qcom,pdc-ranges = <0 2918 qcom,pdc-ranges = <0 480 40>,
3262 <40 2919 <40 140 14>,
3263 <54 2920 <54 263 1>,
3264 <55 2921 <55 306 4>,
3265 <59 2922 <59 312 3>,
3266 <62 2923 <62 374 2>,
3267 <64 2924 <64 434 2>,
3268 <66 2925 <66 438 2>,
3269 <70 2926 <70 520 1>,
3270 <73 2927 <73 523 1>,
3271 <11 2928 <118 568 6>,
3272 <12 2929 <124 609 3>,
3273 <15 2930 <159 638 1>,
3274 <16 2931 <160 720 3>,
3275 <16 2932 <169 728 30>,
3276 <19 2933 <199 416 2>,
3277 <20 2934 <201 449 1>,
3278 <20 2935 <202 89 1>,
3279 <20 2936 <203 451 1>,
3280 <20 2937 <204 462 1>,
3281 <20 2938 <205 264 1>,
3282 <20 2939 <206 579 1>,
3283 <20 2940 <207 653 1>,
3284 <20 2941 <208 656 1>,
3285 <20 2942 <209 659 1>,
3286 <21 2943 <210 122 1>,
3287 <21 2944 <211 699 1>,
3288 <21 2945 <212 705 1>,
3289 <21 2946 <213 450 1>,
3290 <21 2947 <214 643 2>,
3291 <21 2948 <216 646 5>,
3292 <22 2949 <221 390 5>,
3293 <22 2950 <226 700 2>,
3294 <22 2951 <228 440 1>,
3295 <22 2952 <229 663 1>,
3296 <23 2953 <230 524 2>,
3297 <23 2954 <232 612 3>,
3298 <23 2955 <235 723 5>;
3299 #interrupt-cells = <2 2956 #interrupt-cells = <2>;
3300 interrupt-parent = <& 2957 interrupt-parent = <&intc>;
3301 interrupt-controller; 2958 interrupt-controller;
3302 }; 2959 };
3303 2960
3304 tsens2: thermal-sensor@c25100 2961 tsens2: thermal-sensor@c251000 {
3305 compatible = "qcom,sa 2962 compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2";
3306 reg = <0x0 0x0c251000 2963 reg = <0x0 0x0c251000 0x0 0x1ff>,
3307 <0x0 0x0c224000 2964 <0x0 0x0c224000 0x0 0x8>;
3308 interrupts = <GIC_SPI 2965 interrupts = <GIC_SPI 572 IRQ_TYPE_LEVEL_HIGH>,
3309 <GIC_SPI 2966 <GIC_SPI 609 IRQ_TYPE_LEVEL_HIGH>;
3310 #qcom,sensors = <13>; 2967 #qcom,sensors = <13>;
3311 interrupt-names = "up 2968 interrupt-names = "uplow", "critical";
3312 #thermal-sensor-cells 2969 #thermal-sensor-cells = <1>;
3313 }; 2970 };
3314 2971
3315 tsens3: thermal-sensor@c25200 2972 tsens3: thermal-sensor@c252000 {
3316 compatible = "qcom,sa 2973 compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2";
3317 reg = <0x0 0x0c252000 2974 reg = <0x0 0x0c252000 0x0 0x1ff>,
3318 <0x0 0x0c225000 2975 <0x0 0x0c225000 0x0 0x8>;
3319 interrupts = <GIC_SPI 2976 interrupts = <GIC_SPI 573 IRQ_TYPE_LEVEL_HIGH>,
3320 <GIC_SPI 2977 <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>;
3321 #qcom,sensors = <13>; 2978 #qcom,sensors = <13>;
3322 interrupt-names = "up 2979 interrupt-names = "uplow", "critical";
3323 #thermal-sensor-cells 2980 #thermal-sensor-cells = <1>;
3324 }; 2981 };
3325 2982
3326 tsens0: thermal-sensor@c26300 2983 tsens0: thermal-sensor@c263000 {
3327 compatible = "qcom,sa 2984 compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2";
3328 reg = <0x0 0x0c263000 2985 reg = <0x0 0x0c263000 0x0 0x1ff>,
3329 <0x0 0x0c222000 2986 <0x0 0x0c222000 0x0 0x8>;
3330 interrupts = <GIC_SPI 2987 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
3331 <GIC_SPI 2988 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
3332 #qcom,sensors = <12>; 2989 #qcom,sensors = <12>;
3333 interrupt-names = "up 2990 interrupt-names = "uplow", "critical";
3334 #thermal-sensor-cells 2991 #thermal-sensor-cells = <1>;
3335 }; 2992 };
3336 2993
3337 tsens1: thermal-sensor@c26500 2994 tsens1: thermal-sensor@c265000 {
3338 compatible = "qcom,sa 2995 compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2";
3339 reg = <0x0 0x0c265000 2996 reg = <0x0 0x0c265000 0x0 0x1ff>,
3340 <0x0 0x0c223000 2997 <0x0 0x0c223000 0x0 0x8>;
3341 interrupts = <GIC_SPI 2998 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
3342 <GIC_SPI 2999 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
3343 #qcom,sensors = <12>; 3000 #qcom,sensors = <12>;
3344 interrupt-names = "up 3001 interrupt-names = "uplow", "critical";
3345 #thermal-sensor-cells 3002 #thermal-sensor-cells = <1>;
3346 }; 3003 };
3347 3004
3348 aoss_qmp: power-management@c3 3005 aoss_qmp: power-management@c300000 {
3349 compatible = "qcom,sa 3006 compatible = "qcom,sa8775p-aoss-qmp", "qcom,aoss-qmp";
3350 reg = <0x0 0x0c300000 3007 reg = <0x0 0x0c300000 0x0 0x400>;
3351 interrupts-extended = 3008 interrupts-extended = <&ipcc IPCC_CLIENT_AOP
3352 3009 IPCC_MPROC_SIGNAL_GLINK_QMP
3353 3010 IRQ_TYPE_EDGE_RISING>;
3354 mboxes = <&ipcc IPCC_ 3011 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
3355 #clock-cells = <0>; 3012 #clock-cells = <0>;
3356 }; 3013 };
3357 3014
3358 sram@c3f0000 { 3015 sram@c3f0000 {
3359 compatible = "qcom,rp 3016 compatible = "qcom,rpmh-stats";
3360 reg = <0x0 0x0c3f0000 3017 reg = <0x0 0x0c3f0000 0x0 0x400>;
3361 }; 3018 };
3362 3019
3363 spmi_bus: spmi@c440000 { 3020 spmi_bus: spmi@c440000 {
3364 compatible = "qcom,sp 3021 compatible = "qcom,spmi-pmic-arb";
3365 reg = <0x0 0x0c440000 3022 reg = <0x0 0x0c440000 0x0 0x1100>,
3366 <0x0 0x0c600000 3023 <0x0 0x0c600000 0x0 0x2000000>,
3367 <0x0 0x0e600000 3024 <0x0 0x0e600000 0x0 0x100000>,
3368 <0x0 0x0e700000 3025 <0x0 0x0e700000 0x0 0xa0000>,
3369 <0x0 0x0c40a000 3026 <0x0 0x0c40a000 0x0 0x26000>;
3370 reg-names = "core", 3027 reg-names = "core",
3371 "chnls", 3028 "chnls",
3372 "obsrvr", 3029 "obsrvr",
3373 "intr", 3030 "intr",
3374 "cnfg"; 3031 "cnfg";
3375 qcom,channel = <0>; 3032 qcom,channel = <0>;
3376 qcom,ee = <0>; 3033 qcom,ee = <0>;
3377 interrupts-extended = 3034 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3378 interrupt-names = "pe 3035 interrupt-names = "periph_irq";
3379 interrupt-controller; 3036 interrupt-controller;
3380 #interrupt-cells = <4 3037 #interrupt-cells = <4>;
3381 #address-cells = <2>; 3038 #address-cells = <2>;
3382 #size-cells = <0>; 3039 #size-cells = <0>;
3383 }; 3040 };
3384 3041
3385 tlmm: pinctrl@f000000 { 3042 tlmm: pinctrl@f000000 {
3386 compatible = "qcom,sa 3043 compatible = "qcom,sa8775p-tlmm";
3387 reg = <0x0 0x0f000000 3044 reg = <0x0 0x0f000000 0x0 0x1000000>;
3388 interrupts = <GIC_SPI 3045 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
3389 gpio-controller; 3046 gpio-controller;
3390 #gpio-cells = <2>; 3047 #gpio-cells = <2>;
3391 interrupt-controller; 3048 interrupt-controller;
3392 #interrupt-cells = <2 3049 #interrupt-cells = <2>;
3393 gpio-ranges = <&tlmm 3050 gpio-ranges = <&tlmm 0 0 149>;
3394 wakeup-parent = <&pdc 3051 wakeup-parent = <&pdc>;
3395 }; 3052 };
3396 3053
3397 sram: sram@146d8000 { 3054 sram: sram@146d8000 {
3398 compatible = "qcom,sa 3055 compatible = "qcom,sa8775p-imem", "syscon", "simple-mfd";
3399 reg = <0x0 0x146d8000 3056 reg = <0x0 0x146d8000 0x0 0x1000>;
3400 ranges = <0x0 0x0 0x1 3057 ranges = <0x0 0x0 0x146d8000 0x1000>;
3401 3058
3402 #address-cells = <1>; 3059 #address-cells = <1>;
3403 #size-cells = <1>; 3060 #size-cells = <1>;
3404 3061
3405 pil-reloc@94c { 3062 pil-reloc@94c {
3406 compatible = 3063 compatible = "qcom,pil-reloc-info";
3407 reg = <0x94c 3064 reg = <0x94c 0xc8>;
3408 }; 3065 };
3409 }; 3066 };
3410 3067
3411 apps_smmu: iommu@15000000 { 3068 apps_smmu: iommu@15000000 {
3412 compatible = "qcom,sa 3069 compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500";
3413 reg = <0x0 0x15000000 3070 reg = <0x0 0x15000000 0x0 0x100000>;
3414 #iommu-cells = <2>; 3071 #iommu-cells = <2>;
3415 #global-interrupts = 3072 #global-interrupts = <2>;
3416 dma-coherent; 3073 dma-coherent;
3417 3074
3418 interrupts = <GIC_SPI 3075 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
3419 <GIC_SPI 3076 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
3420 <GIC_SPI 3077 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
3421 <GIC_SPI 3078 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
3422 <GIC_SPI 3079 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
3423 <GIC_SPI 3080 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
3424 <GIC_SPI 3081 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
3425 <GIC_SPI 3082 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
3426 <GIC_SPI 3083 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
3427 <GIC_SPI 3084 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
3428 <GIC_SPI 3085 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
3429 <GIC_SPI 3086 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
3430 <GIC_SPI 3087 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
3431 <GIC_SPI 3088 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
3432 <GIC_SPI 3089 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
3433 <GIC_SPI 3090 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
3434 <GIC_SPI 3091 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
3435 <GIC_SPI 3092 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
3436 <GIC_SPI 3093 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
3437 <GIC_SPI 3094 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
3438 <GIC_SPI 3095 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
3439 <GIC_SPI 3096 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
3440 <GIC_SPI 3097 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
3441 <GIC_SPI 3098 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
3442 <GIC_SPI 3099 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
3443 <GIC_SPI 3100 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
3444 <GIC_SPI 3101 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
3445 <GIC_SPI 3102 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
3446 <GIC_SPI 3103 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
3447 <GIC_SPI 3104 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
3448 <GIC_SPI 3105 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
3449 <GIC_SPI 3106 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
3450 <GIC_SPI 3107 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
3451 <GIC_SPI 3108 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
3452 <GIC_SPI 3109 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
3453 <GIC_SPI 3110 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
3454 <GIC_SPI 3111 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
3455 <GIC_SPI 3112 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
3456 <GIC_SPI 3113 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
3457 <GIC_SPI 3114 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
3458 <GIC_SPI 3115 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
3459 <GIC_SPI 3116 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
3460 <GIC_SPI 3117 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
3461 <GIC_SPI 3118 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
3462 <GIC_SPI 3119 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
3463 <GIC_SPI 3120 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
3464 <GIC_SPI 3121 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
3465 <GIC_SPI 3122 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
3466 <GIC_SPI 3123 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
3467 <GIC_SPI 3124 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
3468 <GIC_SPI 3125 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
3469 <GIC_SPI 3126 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
3470 <GIC_SPI 3127 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
3471 <GIC_SPI 3128 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
3472 <GIC_SPI 3129 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
3473 <GIC_SPI 3130 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
3474 <GIC_SPI 3131 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
3475 <GIC_SPI 3132 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
3476 <GIC_SPI 3133 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
3477 <GIC_SPI 3134 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
3478 <GIC_SPI 3135 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
3479 <GIC_SPI 3136 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
3480 <GIC_SPI 3137 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
3481 <GIC_SPI 3138 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
3482 <GIC_SPI 3139 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
3483 <GIC_SPI 3140 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
3484 <GIC_SPI 3141 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
3485 <GIC_SPI 3142 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
3486 <GIC_SPI 3143 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
3487 <GIC_SPI 3144 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
3488 <GIC_SPI 3145 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
3489 <GIC_SPI 3146 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
3490 <GIC_SPI 3147 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
3491 <GIC_SPI 3148 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
3492 <GIC_SPI 3149 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
3493 <GIC_SPI 3150 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
3494 <GIC_SPI 3151 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
3495 <GIC_SPI 3152 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
3496 <GIC_SPI 3153 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
3497 <GIC_SPI 3154 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
3498 <GIC_SPI 3155 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
3499 <GIC_SPI 3156 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>,
3500 <GIC_SPI 3157 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
3501 <GIC_SPI 3158 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
3502 <GIC_SPI 3159 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
3503 <GIC_SPI 3160 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
3504 <GIC_SPI 3161 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
3505 <GIC_SPI 3162 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
3506 <GIC_SPI 3163 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
3507 <GIC_SPI 3164 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
3508 <GIC_SPI 3165 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
3509 <GIC_SPI 3166 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
3510 <GIC_SPI 3167 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
3511 <GIC_SPI 3168 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
3512 <GIC_SPI 3169 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
3513 <GIC_SPI 3170 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
3514 <GIC_SPI 3171 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
3515 <GIC_SPI 3172 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
3516 <GIC_SPI 3173 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
3517 <GIC_SPI 3174 <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>,
3518 <GIC_SPI 3175 <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>,
3519 <GIC_SPI 3176 <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>,
3520 <GIC_SPI 3177 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
3521 <GIC_SPI 3178 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
3522 <GIC_SPI 3179 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
3523 <GIC_SPI 3180 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>,
3524 <GIC_SPI 3181 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>,
3525 <GIC_SPI 3182 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>,
3526 <GIC_SPI 3183 <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>,
3527 <GIC_SPI 3184 <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>,
3528 <GIC_SPI 3185 <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>,
3529 <GIC_SPI 3186 <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>,
3530 <GIC_SPI 3187 <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>,
3531 <GIC_SPI 3188 <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>,
3532 <GIC_SPI 3189 <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>,
3533 <GIC_SPI 3190 <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>,
3534 <GIC_SPI 3191 <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>,
3535 <GIC_SPI 3192 <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>,
3536 <GIC_SPI 3193 <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>,
3537 <GIC_SPI 3194 <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>,
3538 <GIC_SPI 3195 <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>,
3539 <GIC_SPI 3196 <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>,
3540 <GIC_SPI 3197 <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>,
3541 <GIC_SPI 3198 <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>,
3542 <GIC_SPI 3199 <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>,
3543 <GIC_SPI 3200 <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>,
3544 <GIC_SPI 3201 <GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>,
3545 <GIC_SPI 3202 <GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>,
3546 <GIC_SPI 3203 <GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>,
3547 <GIC_SPI 3204 <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>;
3548 }; 3205 };
3549 3206
3550 pcie_smmu: iommu@15200000 { 3207 pcie_smmu: iommu@15200000 {
3551 compatible = "qcom,sa 3208 compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500";
3552 reg = <0x0 0x15200000 3209 reg = <0x0 0x15200000 0x0 0x80000>;
3553 #iommu-cells = <2>; 3210 #iommu-cells = <2>;
3554 #global-interrupts = 3211 #global-interrupts = <2>;
3555 dma-coherent; 3212 dma-coherent;
3556 3213
3557 interrupts = <GIC_SPI 3214 interrupts = <GIC_SPI 920 IRQ_TYPE_LEVEL_HIGH>,
3558 <GIC_SPI 3215 <GIC_SPI 921 IRQ_TYPE_LEVEL_HIGH>,
3559 <GIC_SPI 3216 <GIC_SPI 925 IRQ_TYPE_LEVEL_HIGH>,
3560 <GIC_SPI 3217 <GIC_SPI 926 IRQ_TYPE_LEVEL_HIGH>,
3561 <GIC_SPI 3218 <GIC_SPI 927 IRQ_TYPE_LEVEL_HIGH>,
3562 <GIC_SPI 3219 <GIC_SPI 928 IRQ_TYPE_LEVEL_HIGH>,
3563 <GIC_SPI 3220 <GIC_SPI 950 IRQ_TYPE_LEVEL_HIGH>,
3564 <GIC_SPI 3221 <GIC_SPI 951 IRQ_TYPE_LEVEL_HIGH>,
3565 <GIC_SPI 3222 <GIC_SPI 952 IRQ_TYPE_LEVEL_HIGH>,
3566 <GIC_SPI 3223 <GIC_SPI 953 IRQ_TYPE_LEVEL_HIGH>,
3567 <GIC_SPI 3224 <GIC_SPI 954 IRQ_TYPE_LEVEL_HIGH>,
3568 <GIC_SPI 3225 <GIC_SPI 955 IRQ_TYPE_LEVEL_HIGH>,
3569 <GIC_SPI 3226 <GIC_SPI 956 IRQ_TYPE_LEVEL_HIGH>,
3570 <GIC_SPI 3227 <GIC_SPI 957 IRQ_TYPE_LEVEL_HIGH>,
3571 <GIC_SPI 3228 <GIC_SPI 958 IRQ_TYPE_LEVEL_HIGH>,
3572 <GIC_SPI 3229 <GIC_SPI 885 IRQ_TYPE_LEVEL_HIGH>,
3573 <GIC_SPI 3230 <GIC_SPI 886 IRQ_TYPE_LEVEL_HIGH>,
3574 <GIC_SPI 3231 <GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>,
3575 <GIC_SPI 3232 <GIC_SPI 888 IRQ_TYPE_LEVEL_HIGH>,
3576 <GIC_SPI 3233 <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>,
3577 <GIC_SPI 3234 <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>,
3578 <GIC_SPI 3235 <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>,
3579 <GIC_SPI 3236 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
3580 <GIC_SPI 3237 <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
3581 <GIC_SPI 3238 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
3582 <GIC_SPI 3239 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
3583 <GIC_SPI 3240 <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>,
3584 <GIC_SPI 3241 <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>,
3585 <GIC_SPI 3242 <GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>,
3586 <GIC_SPI 3243 <GIC_SPI 843 IRQ_TYPE_LEVEL_HIGH>,
3587 <GIC_SPI 3244 <GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>,
3588 <GIC_SPI 3245 <GIC_SPI 845 IRQ_TYPE_LEVEL_HIGH>,
3589 <GIC_SPI 3246 <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>,
3590 <GIC_SPI 3247 <GIC_SPI 847 IRQ_TYPE_LEVEL_HIGH>,
3591 <GIC_SPI 3248 <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>,
3592 <GIC_SPI 3249 <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>,
3593 <GIC_SPI 3250 <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>,
3594 <GIC_SPI 3251 <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>,
3595 <GIC_SPI 3252 <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>,
3596 <GIC_SPI 3253 <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>,
3597 <GIC_SPI 3254 <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>,
3598 <GIC_SPI 3255 <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>,
3599 <GIC_SPI 3256 <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>,
3600 <GIC_SPI 3257 <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>,
3601 <GIC_SPI 3258 <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>,
3602 <GIC_SPI 3259 <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>,
3603 <GIC_SPI 3260 <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>,
3604 <GIC_SPI 3261 <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>,
3605 <GIC_SPI 3262 <GIC_SPI 814 IRQ_TYPE_LEVEL_HIGH>,
3606 <GIC_SPI 3263 <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>,
3607 <GIC_SPI 3264 <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>,
3608 <GIC_SPI 3265 <GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>,
3609 <GIC_SPI 3266 <GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>,
3610 <GIC_SPI 3267 <GIC_SPI 854 IRQ_TYPE_LEVEL_HIGH>,
3611 <GIC_SPI 3268 <GIC_SPI 855 IRQ_TYPE_LEVEL_HIGH>,
3612 <GIC_SPI 3269 <GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>,
3613 <GIC_SPI 3270 <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>,
3614 <GIC_SPI 3271 <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>,
3615 <GIC_SPI 3272 <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>,
3616 <GIC_SPI 3273 <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>,
3617 <GIC_SPI 3274 <GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>,
3618 <GIC_SPI 3275 <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>,
3619 <GIC_SPI 3276 <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>,
3620 <GIC_SPI 3277 <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>,
3621 <GIC_SPI 3278 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
3622 <GIC_SPI 3279 <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>;
3623 }; 3280 };
3624 3281
3625 intc: interrupt-controller@17 3282 intc: interrupt-controller@17a00000 {
3626 compatible = "arm,gic 3283 compatible = "arm,gic-v3";
3627 reg = <0x0 0x17a00000 3284 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
3628 <0x0 0x17a60000 3285 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
3629 interrupt-controller; 3286 interrupt-controller;
3630 #interrupt-cells = <3 3287 #interrupt-cells = <3>;
3631 interrupts = <GIC_PPI 3288 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3632 #redistributor-region 3289 #redistributor-regions = <1>;
3633 redistributor-stride 3290 redistributor-stride = <0x0 0x20000>;
3634 }; 3291 };
3635 3292
3636 watchdog@17c10000 { 3293 watchdog@17c10000 {
3637 compatible = "qcom,ap 3294 compatible = "qcom,apss-wdt-sa8775p", "qcom,kpss-wdt";
3638 reg = <0x0 0x17c10000 3295 reg = <0x0 0x17c10000 0x0 0x1000>;
3639 clocks = <&sleep_clk> 3296 clocks = <&sleep_clk>;
3640 interrupts = <GIC_SPI 3297 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
3641 }; 3298 };
3642 3299
3643 memtimer: timer@17c20000 { 3300 memtimer: timer@17c20000 {
3644 compatible = "arm,arm 3301 compatible = "arm,armv7-timer-mem";
3645 reg = <0x0 0x17c20000 3302 reg = <0x0 0x17c20000 0x0 0x1000>;
3646 ranges = <0x0 0x0 0x0 3303 ranges = <0x0 0x0 0x0 0x20000000>;
3647 #address-cells = <1>; 3304 #address-cells = <1>;
3648 #size-cells = <1>; 3305 #size-cells = <1>;
3649 3306
3650 frame@17c21000 { 3307 frame@17c21000 {
3651 reg = <0x17c2 3308 reg = <0x17c21000 0x1000>,
3652 <0x17c2 3309 <0x17c22000 0x1000>;
3653 interrupts = 3310 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
3654 3311 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
3655 frame-number 3312 frame-number = <0>;
3656 }; 3313 };
3657 3314
3658 frame@17c23000 { 3315 frame@17c23000 {
3659 reg = <0x17c2 3316 reg = <0x17c23000 0x1000>;
3660 interrupts = 3317 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
3661 frame-number 3318 frame-number = <1>;
3662 status = "dis 3319 status = "disabled";
3663 }; 3320 };
3664 3321
3665 frame@17c25000 { 3322 frame@17c25000 {
3666 reg = <0x17c2 3323 reg = <0x17c25000 0x1000>;
3667 interrupts = 3324 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
3668 frame-number 3325 frame-number = <2>;
3669 status = "dis 3326 status = "disabled";
3670 }; 3327 };
3671 3328
3672 frame@17c27000 { 3329 frame@17c27000 {
3673 reg = <0x17c2 3330 reg = <0x17c27000 0x1000>;
3674 interrupts = 3331 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3675 frame-number 3332 frame-number = <3>;
3676 status = "dis 3333 status = "disabled";
3677 }; 3334 };
3678 3335
3679 frame@17c29000 { 3336 frame@17c29000 {
3680 reg = <0x17c2 3337 reg = <0x17c29000 0x1000>;
3681 interrupts = 3338 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3682 frame-number 3339 frame-number = <4>;
3683 status = "dis 3340 status = "disabled";
3684 }; 3341 };
3685 3342
3686 frame@17c2b000 { 3343 frame@17c2b000 {
3687 reg = <0x17c2 3344 reg = <0x17c2b000 0x1000>;
3688 interrupts = 3345 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3689 frame-number 3346 frame-number = <5>;
3690 status = "dis 3347 status = "disabled";
3691 }; 3348 };
3692 3349
3693 frame@17c2d000 { 3350 frame@17c2d000 {
3694 reg = <0x17c2 3351 reg = <0x17c2d000 0x1000>;
3695 interrupts = 3352 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
3696 frame-number 3353 frame-number = <6>;
3697 status = "dis 3354 status = "disabled";
3698 }; 3355 };
3699 }; 3356 };
3700 3357
3701 apps_rsc: rsc@18200000 { 3358 apps_rsc: rsc@18200000 {
3702 compatible = "qcom,rp 3359 compatible = "qcom,rpmh-rsc";
3703 reg = <0x0 0x18200000 3360 reg = <0x0 0x18200000 0x0 0x10000>,
3704 <0x0 0x18210000 3361 <0x0 0x18210000 0x0 0x10000>,
3705 <0x0 0x18220000 3362 <0x0 0x18220000 0x0 0x10000>;
3706 reg-names = "drv-0", 3363 reg-names = "drv-0", "drv-1", "drv-2";
3707 interrupts = <GIC_SPI 3364 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
3708 <GIC_SPI 4 IRQ_ 3365 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
3709 <GIC_SPI 5 IRQ_ 3366 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
3710 qcom,tcs-offset = <0x 3367 qcom,tcs-offset = <0xd00>;
3711 qcom,drv-id = <2>; 3368 qcom,drv-id = <2>;
3712 qcom,tcs-config = <AC 3369 qcom,tcs-config = <ACTIVE_TCS 2>,
3713 <SL 3370 <SLEEP_TCS 3>,
3714 <WA 3371 <WAKE_TCS 3>,
3715 <CO 3372 <CONTROL_TCS 0>;
3716 label = "apps_rsc"; 3373 label = "apps_rsc";
3717 3374
3718 apps_bcm_voter: bcm-v 3375 apps_bcm_voter: bcm-voter {
3719 compatible = 3376 compatible = "qcom,bcm-voter";
3720 }; 3377 };
3721 3378
3722 rpmhcc: clock-control 3379 rpmhcc: clock-controller {
3723 compatible = 3380 compatible = "qcom,sa8775p-rpmh-clk";
3724 #clock-cells 3381 #clock-cells = <1>;
3725 clock-names = 3382 clock-names = "xo";
3726 clocks = <&xo 3383 clocks = <&xo_board_clk>;
3727 }; 3384 };
3728 3385
3729 rpmhpd: power-control 3386 rpmhpd: power-controller {
3730 compatible = 3387 compatible = "qcom,sa8775p-rpmhpd";
3731 #power-domain 3388 #power-domain-cells = <1>;
3732 operating-poi 3389 operating-points-v2 = <&rpmhpd_opp_table>;
3733 3390
3734 rpmhpd_opp_ta 3391 rpmhpd_opp_table: opp-table {
3735 compa 3392 compatible = "operating-points-v2";
3736 3393
3737 rpmhp 3394 rpmhpd_opp_ret: opp-0 {
3738 3395 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3739 }; 3396 };
3740 3397
3741 rpmhp 3398 rpmhpd_opp_min_svs: opp-1 {
3742 3399 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3743 }; 3400 };
3744 3401
3745 rpmhp 3402 rpmhpd_opp_low_svs: opp2 {
3746 3403 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3747 }; 3404 };
3748 3405
3749 rpmhp 3406 rpmhpd_opp_svs: opp3 {
3750 3407 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3751 }; 3408 };
3752 3409
3753 rpmhp 3410 rpmhpd_opp_svs_l1: opp-4 {
3754 3411 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3755 }; 3412 };
3756 3413
3757 rpmhp 3414 rpmhpd_opp_nom: opp-5 {
3758 3415 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3759 }; 3416 };
3760 3417
3761 rpmhp 3418 rpmhpd_opp_nom_l1: opp-6 {
3762 3419 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3763 }; 3420 };
3764 3421
3765 rpmhp 3422 rpmhpd_opp_nom_l2: opp-7 {
3766 3423 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3767 }; 3424 };
3768 3425
3769 rpmhp 3426 rpmhpd_opp_turbo: opp-8 {
3770 3427 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3771 }; 3428 };
3772 3429
3773 rpmhp 3430 rpmhpd_opp_turbo_l1: opp-9 {
3774 3431 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3775 }; 3432 };
3776 }; 3433 };
3777 }; 3434 };
3778 }; 3435 };
3779 3436
3780 cpufreq_hw: cpufreq@18591000 3437 cpufreq_hw: cpufreq@18591000 {
3781 compatible = "qcom,sa 3438 compatible = "qcom,sa8775p-cpufreq-epss",
3782 "qcom,cp 3439 "qcom,cpufreq-epss";
3783 reg = <0x0 0x18591000 3440 reg = <0x0 0x18591000 0x0 0x1000>,
3784 <0x0 0x18593000 3441 <0x0 0x18593000 0x0 0x1000>;
3785 reg-names = "freq-dom 3442 reg-names = "freq-domain0", "freq-domain1";
3786 3443
3787 clocks = <&rpmhcc RPM 3444 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
3788 clock-names = "xo", " 3445 clock-names = "xo", "alternate";
3789 3446
3790 #freq-domain-cells = 3447 #freq-domain-cells = <1>;
3791 }; 3448 };
3792 3449
3793 remoteproc_gpdsp0: remoteproc <<
3794 compatible = "qcom,sa <<
3795 reg = <0x0 0x20c00000 <<
3796 <<
3797 interrupts-extended = <<
3798 <<
3799 <<
3800 <<
3801 <<
3802 interrupt-names = "wd <<
3803 "ha <<
3804 <<
3805 clocks = <&rpmhcc RPM <<
3806 clock-names = "xo"; <<
3807 <<
3808 power-domains = <&rpm <<
3809 <&rpm <<
3810 power-domain-names = <<
3811 <<
3812 interconnects = <&gpd <<
3813 &con <<
3814 <<
3815 memory-region = <&pil <<
3816 <<
3817 qcom,qmp = <&aoss_qmp <<
3818 <<
3819 qcom,smem-states = <& <<
3820 qcom,smem-state-names <<
3821 <<
3822 status = "disabled"; <<
3823 <<
3824 glink-edge { <<
3825 interrupts-ex <<
3826 <<
3827 <<
3828 mboxes = <&ip <<
3829 <<
3830 <<
3831 label = "gpds <<
3832 qcom,remote-p <<
3833 }; <<
3834 }; <<
3835 <<
3836 remoteproc_gpdsp1: remoteproc <<
3837 compatible = "qcom,sa <<
3838 reg = <0x0 0x21c00000 <<
3839 <<
3840 interrupts-extended = <<
3841 <<
3842 <<
3843 <<
3844 <<
3845 interrupt-names = "wd <<
3846 "ha <<
3847 <<
3848 clocks = <&rpmhcc RPM <<
3849 clock-names = "xo"; <<
3850 <<
3851 power-domains = <&rpm <<
3852 <&rpm <<
3853 power-domain-names = <<
3854 <<
3855 interconnects = <&gpd <<
3856 &con <<
3857 <<
3858 memory-region = <&pil <<
3859 <<
3860 qcom,qmp = <&aoss_qmp <<
3861 <<
3862 qcom,smem-states = <& <<
3863 qcom,smem-state-names <<
3864 <<
3865 status = "disabled"; <<
3866 <<
3867 glink-edge { <<
3868 interrupts-ex <<
3869 <<
3870 <<
3871 mboxes = <&ip <<
3872 <<
3873 <<
3874 label = "gpds <<
3875 qcom,remote-p <<
3876 }; <<
3877 }; <<
3878 <<
3879 ethernet1: ethernet@23000000 3450 ethernet1: ethernet@23000000 {
3880 compatible = "qcom,sa 3451 compatible = "qcom,sa8775p-ethqos";
3881 reg = <0x0 0x23000000 3452 reg = <0x0 0x23000000 0x0 0x10000>,
3882 <0x0 0x23016000 3453 <0x0 0x23016000 0x0 0x100>;
3883 reg-names = "stmmacet 3454 reg-names = "stmmaceth", "rgmii";
3884 3455
3885 interrupts = <GIC_SPI 3456 interrupts = <GIC_SPI 929 IRQ_TYPE_LEVEL_HIGH>,
3886 <GIC_SPI 3457 <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>;
3887 interrupt-names = "ma 3458 interrupt-names = "macirq", "sfty";
3888 3459
3889 clocks = <&gcc GCC_EM 3460 clocks = <&gcc GCC_EMAC1_AXI_CLK>,
3890 <&gcc GCC_EM 3461 <&gcc GCC_EMAC1_SLV_AHB_CLK>,
3891 <&gcc GCC_EM 3462 <&gcc GCC_EMAC1_PTP_CLK>,
3892 <&gcc GCC_EM 3463 <&gcc GCC_EMAC1_PHY_AUX_CLK>;
3893 clock-names = "stmmac 3464 clock-names = "stmmaceth",
3894 "pclk", 3465 "pclk",
3895 "ptp_re 3466 "ptp_ref",
3896 "phyaux 3467 "phyaux";
3897 3468
3898 interconnects = <&agg <<
3899 &mc_ <<
3900 <&gem <<
3901 &con <<
3902 interconnect-names = <<
3903 <<
3904 power-domains = <&gcc 3469 power-domains = <&gcc EMAC1_GDSC>;
3905 3470
3906 phys = <&serdes1>; 3471 phys = <&serdes1>;
3907 phy-names = "serdes"; 3472 phy-names = "serdes";
3908 3473
3909 iommus = <&apps_smmu 3474 iommus = <&apps_smmu 0x140 0xf>;
3910 dma-coherent; 3475 dma-coherent;
3911 3476
3912 snps,tso; 3477 snps,tso;
3913 snps,pbl = <32>; 3478 snps,pbl = <32>;
3914 rx-fifo-depth = <1638 3479 rx-fifo-depth = <16384>;
3915 tx-fifo-depth = <1638 3480 tx-fifo-depth = <16384>;
3916 3481
3917 status = "disabled"; 3482 status = "disabled";
3918 }; 3483 };
3919 3484
3920 ethernet0: ethernet@23040000 3485 ethernet0: ethernet@23040000 {
3921 compatible = "qcom,sa 3486 compatible = "qcom,sa8775p-ethqos";
3922 reg = <0x0 0x23040000 3487 reg = <0x0 0x23040000 0x0 0x10000>,
3923 <0x0 0x23056000 3488 <0x0 0x23056000 0x0 0x100>;
3924 reg-names = "stmmacet 3489 reg-names = "stmmaceth", "rgmii";
3925 3490
3926 interrupts = <GIC_SPI 3491 interrupts = <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>,
3927 <GIC_SPI 3492 <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>;
3928 interrupt-names = "ma 3493 interrupt-names = "macirq", "sfty";
3929 3494
3930 clocks = <&gcc GCC_EM 3495 clocks = <&gcc GCC_EMAC0_AXI_CLK>,
3931 <&gcc GCC_EM 3496 <&gcc GCC_EMAC0_SLV_AHB_CLK>,
3932 <&gcc GCC_EM 3497 <&gcc GCC_EMAC0_PTP_CLK>,
3933 <&gcc GCC_EM 3498 <&gcc GCC_EMAC0_PHY_AUX_CLK>;
3934 clock-names = "stmmac 3499 clock-names = "stmmaceth",
3935 "pclk", 3500 "pclk",
3936 "ptp_re 3501 "ptp_ref",
3937 "phyaux 3502 "phyaux";
3938 3503
3939 interconnects = <&agg <<
3940 &mc_ <<
3941 <&gem <<
3942 &con <<
3943 interconnect-names = <<
3944 <<
3945 power-domains = <&gcc 3504 power-domains = <&gcc EMAC0_GDSC>;
3946 3505
3947 phys = <&serdes0>; 3506 phys = <&serdes0>;
3948 phy-names = "serdes"; 3507 phy-names = "serdes";
3949 3508
3950 iommus = <&apps_smmu 3509 iommus = <&apps_smmu 0x120 0xf>;
3951 dma-coherent; 3510 dma-coherent;
3952 3511
3953 snps,tso; 3512 snps,tso;
3954 snps,pbl = <32>; 3513 snps,pbl = <32>;
3955 rx-fifo-depth = <1638 3514 rx-fifo-depth = <16384>;
3956 tx-fifo-depth = <1638 3515 tx-fifo-depth = <16384>;
3957 3516
3958 status = "disabled"; 3517 status = "disabled";
3959 }; <<
3960 <<
3961 remoteproc_cdsp0: remoteproc@ <<
3962 compatible = "qcom,sa <<
3963 reg = <0x0 0x26300000 <<
3964 <<
3965 interrupts-extended = <<
3966 <<
3967 <<
3968 <<
3969 <<
3970 interrupt-names = "wd <<
3971 "ha <<
3972 <<
3973 clocks = <&rpmhcc RPM <<
3974 clock-names = "xo"; <<
3975 <<
3976 power-domains = <&rpm <<
3977 <&rpm <<
3978 <&rpm <<
3979 power-domain-names = <<
3980 <<
3981 interconnects = <&nsp <<
3982 &mc_ <<
3983 <<
3984 memory-region = <&pil <<
3985 <<
3986 qcom,qmp = <&aoss_qmp <<
3987 <<
3988 qcom,smem-states = <& <<
3989 qcom,smem-state-names <<
3990 <<
3991 status = "disabled"; <<
3992 <<
3993 glink-edge { <<
3994 interrupts-ex <<
3995 <<
3996 <<
3997 mboxes = <&ip <<
3998 <<
3999 <<
4000 label = "cdsp <<
4001 qcom,remote-p <<
4002 <<
4003 fastrpc { <<
4004 compa <<
4005 qcom, <<
4006 label <<
4007 #addr <<
4008 #size <<
4009 <<
4010 compu <<
4011 <<
4012 <<
4013 <<
4014 <<
4015 <<
4016 <<
4017 <<
4018 <<
4019 <<
4020 <<
4021 <<
4022 <<
4023 <<
4024 }; <<
4025 <<
4026 compu <<
4027 <<
4028 <<
4029 <<
4030 <<
4031 <<
4032 <<
4033 <<
4034 <<
4035 <<
4036 <<
4037 <<
4038 <<
4039 <<
4040 }; <<
4041 <<
4042 compu <<
4043 <<
4044 <<
4045 <<
4046 <<
4047 <<
4048 <<
4049 <<
4050 <<
4051 <<
4052 <<
4053 <<
4054 <<
4055 <<
4056 }; <<
4057 <<
4058 compu <<
4059 <<
4060 <<
4061 <<
4062 <<
4063 <<
4064 <<
4065 <<
4066 <<
4067 <<
4068 <<
4069 <<
4070 <<
4071 <<
4072 }; <<
4073 <<
4074 compu <<
4075 <<
4076 <<
4077 <<
4078 <<
4079 <<
4080 <<
4081 <<
4082 <<
4083 <<
4084 <<
4085 <<
4086 <<
4087 <<
4088 }; <<
4089 <<
4090 compu <<
4091 <<
4092 <<
4093 <<
4094 <<
4095 <<
4096 <<
4097 <<
4098 <<
4099 <<
4100 <<
4101 <<
4102 <<
4103 <<
4104 }; <<
4105 <<
4106 compu <<
4107 <<
4108 <<
4109 <<
4110 <<
4111 <<
4112 <<
4113 <<
4114 <<
4115 <<
4116 <<
4117 <<
4118 <<
4119 <<
4120 }; <<
4121 <<
4122 compu <<
4123 <<
4124 <<
4125 <<
4126 <<
4127 <<
4128 <<
4129 <<
4130 <<
4131 <<
4132 <<
4133 <<
4134 <<
4135 <<
4136 }; <<
4137 <<
4138 compu <<
4139 <<
4140 <<
4141 <<
4142 <<
4143 <<
4144 <<
4145 <<
4146 <<
4147 <<
4148 <<
4149 <<
4150 <<
4151 <<
4152 }; <<
4153 <<
4154 compu <<
4155 <<
4156 <<
4157 <<
4158 <<
4159 <<
4160 <<
4161 <<
4162 <<
4163 <<
4164 <<
4165 <<
4166 <<
4167 <<
4168 }; <<
4169 <<
4170 compu <<
4171 <<
4172 <<
4173 <<
4174 <<
4175 <<
4176 <<
4177 <<
4178 <<
4179 <<
4180 <<
4181 <<
4182 <<
4183 <<
4184 }; <<
4185 }; <<
4186 }; <<
4187 }; <<
4188 <<
4189 remoteproc_cdsp1: remoteproc@ <<
4190 compatible = "qcom,sa <<
4191 reg = <0x0 0x2A300000 <<
4192 <<
4193 interrupts-extended = <<
4194 <<
4195 <<
4196 <<
4197 <<
4198 interrupt-names = "wd <<
4199 "ha <<
4200 <<
4201 clocks = <&rpmhcc RPM <<
4202 clock-names = "xo"; <<
4203 <<
4204 power-domains = <&rpm <<
4205 <&rpm <<
4206 <&rpm <<
4207 power-domain-names = <<
4208 <<
4209 interconnects = <&nsp <<
4210 &mc_ <<
4211 <<
4212 memory-region = <&pil <<
4213 <<
4214 qcom,qmp = <&aoss_qmp <<
4215 <<
4216 qcom,smem-states = <& <<
4217 qcom,smem-state-names <<
4218 <<
4219 status = "disabled"; <<
4220 <<
4221 glink-edge { <<
4222 interrupts-ex <<
4223 <<
4224 <<
4225 mboxes = <&ip <<
4226 <<
4227 <<
4228 label = "cdsp <<
4229 qcom,remote-p <<
4230 <<
4231 fastrpc { <<
4232 compa <<
4233 qcom, <<
4234 label <<
4235 #addr <<
4236 #size <<
4237 <<
4238 compu <<
4239 <<
4240 <<
4241 <<
4242 <<
4243 <<
4244 <<
4245 <<
4246 <<
4247 <<
4248 <<
4249 <<
4250 <<
4251 <<
4252 }; <<
4253 <<
4254 compu <<
4255 <<
4256 <<
4257 <<
4258 <<
4259 <<
4260 <<
4261 <<
4262 <<
4263 <<
4264 <<
4265 <<
4266 <<
4267 <<
4268 }; <<
4269 <<
4270 compu <<
4271 <<
4272 <<
4273 <<
4274 <<
4275 <<
4276 <<
4277 <<
4278 <<
4279 <<
4280 <<
4281 <<
4282 <<
4283 <<
4284 }; <<
4285 <<
4286 compu <<
4287 <<
4288 <<
4289 <<
4290 <<
4291 <<
4292 <<
4293 <<
4294 <<
4295 <<
4296 <<
4297 <<
4298 <<
4299 <<
4300 }; <<
4301 <<
4302 compu <<
4303 <<
4304 <<
4305 <<
4306 <<
4307 <<
4308 <<
4309 <<
4310 <<
4311 <<
4312 <<
4313 <<
4314 <<
4315 <<
4316 }; <<
4317 <<
4318 compu <<
4319 <<
4320 <<
4321 <<
4322 <<
4323 <<
4324 <<
4325 <<
4326 <<
4327 <<
4328 <<
4329 <<
4330 <<
4331 <<
4332 }; <<
4333 <<
4334 compu <<
4335 <<
4336 <<
4337 <<
4338 <<
4339 <<
4340 <<
4341 <<
4342 <<
4343 <<
4344 <<
4345 <<
4346 <<
4347 <<
4348 }; <<
4349 <<
4350 compu <<
4351 <<
4352 <<
4353 <<
4354 <<
4355 <<
4356 <<
4357 <<
4358 <<
4359 <<
4360 <<
4361 <<
4362 <<
4363 <<
4364 }; <<
4365 <<
4366 compu <<
4367 <<
4368 <<
4369 <<
4370 <<
4371 <<
4372 <<
4373 <<
4374 <<
4375 <<
4376 <<
4377 <<
4378 <<
4379 <<
4380 }; <<
4381 <<
4382 compu <<
4383 <<
4384 <<
4385 <<
4386 <<
4387 <<
4388 <<
4389 <<
4390 <<
4391 <<
4392 <<
4393 <<
4394 <<
4395 <<
4396 }; <<
4397 <<
4398 compu <<
4399 <<
4400 <<
4401 <<
4402 <<
4403 <<
4404 <<
4405 <<
4406 <<
4407 <<
4408 <<
4409 <<
4410 <<
4411 <<
4412 }; <<
4413 <<
4414 compu <<
4415 <<
4416 <<
4417 <<
4418 <<
4419 <<
4420 <<
4421 <<
4422 <<
4423 <<
4424 <<
4425 <<
4426 <<
4427 <<
4428 }; <<
4429 <<
4430 compu <<
4431 <<
4432 <<
4433 <<
4434 <<
4435 <<
4436 <<
4437 <<
4438 <<
4439 <<
4440 <<
4441 <<
4442 <<
4443 <<
4444 }; <<
4445 }; <<
4446 }; <<
4447 }; <<
4448 <<
4449 remoteproc_adsp: remoteproc@3 <<
4450 compatible = "qcom,sa <<
4451 reg = <0x0 0x30000000 <<
4452 <<
4453 interrupts-extended = <<
4454 <<
4455 <<
4456 <<
4457 <<
4458 interrupt-names = "wd <<
4459 "st <<
4460 <<
4461 clocks = <&rpmhcc RPM <<
4462 clock-names = "xo"; <<
4463 <<
4464 power-domains = <&rpm <<
4465 <&rpm <<
4466 power-domain-names = <<
4467 <<
4468 interconnects = <&lpa <<
4469 <<
4470 memory-region = <&pil <<
4471 <<
4472 qcom,qmp = <&aoss_qmp <<
4473 <<
4474 qcom,smem-states = <& <<
4475 qcom,smem-state-names <<
4476 <<
4477 status = "disabled"; <<
4478 <<
4479 remoteproc_adsp_glink <<
4480 interrupts-ex <<
4481 <<
4482 <<
4483 mboxes = <&ip <<
4484 <<
4485 <<
4486 label = "lpas <<
4487 qcom,remote-p <<
4488 <<
4489 fastrpc { <<
4490 compa <<
4491 qcom, <<
4492 label <<
4493 memor <<
4494 qcom, <<
4495 <<
4496 #addr <<
4497 #size <<
4498 <<
4499 compu <<
4500 <<
4501 <<
4502 <<
4503 <<
4504 }; <<
4505 <<
4506 compu <<
4507 <<
4508 <<
4509 <<
4510 <<
4511 }; <<
4512 <<
4513 compu <<
4514 <<
4515 <<
4516 <<
4517 <<
4518 <<
4519 }; <<
4520 }; <<
4521 }; <<
4522 }; 3518 };
4523 }; 3519 };
4524 3520
4525 thermal-zones { 3521 thermal-zones {
4526 aoss-0-thermal { 3522 aoss-0-thermal {
4527 thermal-sensors = <&t 3523 thermal-sensors = <&tsens0 0>;
4528 3524
4529 trips { 3525 trips {
4530 trip-point0 { 3526 trip-point0 {
4531 tempe 3527 temperature = <105000>;
4532 hyste 3528 hysteresis = <5000>;
4533 type 3529 type = "passive";
4534 }; 3530 };
4535 3531
4536 trip-point1 { 3532 trip-point1 {
4537 tempe 3533 temperature = <115000>;
4538 hyste 3534 hysteresis = <5000>;
4539 type 3535 type = "passive";
4540 }; 3536 };
4541 }; 3537 };
4542 }; 3538 };
4543 3539
4544 cpu-0-0-0-thermal { 3540 cpu-0-0-0-thermal {
4545 polling-delay-passive 3541 polling-delay-passive = <10>;
4546 3542
4547 thermal-sensors = <&t 3543 thermal-sensors = <&tsens0 1>;
4548 3544
4549 trips { 3545 trips {
4550 trip-point0 { 3546 trip-point0 {
4551 tempe 3547 temperature = <105000>;
4552 hyste 3548 hysteresis = <5000>;
4553 type 3549 type = "passive";
4554 }; 3550 };
4555 3551
4556 trip-point1 { 3552 trip-point1 {
4557 tempe 3553 temperature = <115000>;
4558 hyste 3554 hysteresis = <5000>;
4559 type 3555 type = "passive";
4560 }; 3556 };
4561 }; 3557 };
4562 }; 3558 };
4563 3559
4564 cpu-0-1-0-thermal { 3560 cpu-0-1-0-thermal {
4565 polling-delay-passive 3561 polling-delay-passive = <10>;
4566 3562
4567 thermal-sensors = <&t 3563 thermal-sensors = <&tsens0 2>;
4568 3564
4569 trips { 3565 trips {
4570 trip-point0 { 3566 trip-point0 {
4571 tempe 3567 temperature = <105000>;
4572 hyste 3568 hysteresis = <5000>;
4573 type 3569 type = "passive";
4574 }; 3570 };
4575 3571
4576 trip-point1 { 3572 trip-point1 {
4577 tempe 3573 temperature = <115000>;
4578 hyste 3574 hysteresis = <5000>;
4579 type 3575 type = "passive";
4580 }; 3576 };
4581 }; 3577 };
4582 }; 3578 };
4583 3579
4584 cpu-0-2-0-thermal { 3580 cpu-0-2-0-thermal {
4585 polling-delay-passive 3581 polling-delay-passive = <10>;
4586 3582
4587 thermal-sensors = <&t 3583 thermal-sensors = <&tsens0 3>;
4588 3584
4589 trips { 3585 trips {
4590 trip-point0 { 3586 trip-point0 {
4591 tempe 3587 temperature = <105000>;
4592 hyste 3588 hysteresis = <5000>;
4593 type 3589 type = "passive";
4594 }; 3590 };
4595 3591
4596 trip-point1 { 3592 trip-point1 {
4597 tempe 3593 temperature = <115000>;
4598 hyste 3594 hysteresis = <5000>;
4599 type 3595 type = "passive";
4600 }; 3596 };
4601 }; 3597 };
4602 }; 3598 };
4603 3599
4604 cpu-0-3-0-thermal { 3600 cpu-0-3-0-thermal {
4605 polling-delay-passive 3601 polling-delay-passive = <10>;
4606 3602
4607 thermal-sensors = <&t 3603 thermal-sensors = <&tsens0 4>;
4608 3604
4609 trips { 3605 trips {
4610 trip-point0 { 3606 trip-point0 {
4611 tempe 3607 temperature = <105000>;
4612 hyste 3608 hysteresis = <5000>;
4613 type 3609 type = "passive";
4614 }; 3610 };
4615 3611
4616 trip-point1 { 3612 trip-point1 {
4617 tempe 3613 temperature = <115000>;
4618 hyste 3614 hysteresis = <5000>;
4619 type 3615 type = "passive";
4620 }; 3616 };
4621 }; 3617 };
4622 }; 3618 };
4623 3619
4624 gpuss-0-thermal { 3620 gpuss-0-thermal {
4625 polling-delay-passive 3621 polling-delay-passive = <10>;
4626 3622
4627 thermal-sensors = <&t 3623 thermal-sensors = <&tsens0 5>;
4628 3624
4629 trips { 3625 trips {
4630 trip-point0 { 3626 trip-point0 {
4631 tempe 3627 temperature = <105000>;
4632 hyste 3628 hysteresis = <5000>;
4633 type 3629 type = "passive";
4634 }; 3630 };
4635 3631
4636 trip-point1 { 3632 trip-point1 {
4637 tempe 3633 temperature = <115000>;
4638 hyste 3634 hysteresis = <5000>;
4639 type 3635 type = "passive";
4640 }; 3636 };
4641 }; 3637 };
4642 }; 3638 };
4643 3639
4644 gpuss-1-thermal { 3640 gpuss-1-thermal {
4645 polling-delay-passive 3641 polling-delay-passive = <10>;
4646 3642
4647 thermal-sensors = <&t 3643 thermal-sensors = <&tsens0 6>;
4648 3644
4649 trips { 3645 trips {
4650 trip-point0 { 3646 trip-point0 {
4651 tempe 3647 temperature = <105000>;
4652 hyste 3648 hysteresis = <5000>;
4653 type 3649 type = "passive";
4654 }; 3650 };
4655 3651
4656 trip-point1 { 3652 trip-point1 {
4657 tempe 3653 temperature = <115000>;
4658 hyste 3654 hysteresis = <5000>;
4659 type 3655 type = "passive";
4660 }; 3656 };
4661 }; 3657 };
4662 }; 3658 };
4663 3659
4664 gpuss-2-thermal { 3660 gpuss-2-thermal {
4665 polling-delay-passive 3661 polling-delay-passive = <10>;
4666 3662
4667 thermal-sensors = <&t 3663 thermal-sensors = <&tsens0 7>;
4668 3664
4669 trips { 3665 trips {
4670 trip-point0 { 3666 trip-point0 {
4671 tempe 3667 temperature = <105000>;
4672 hyste 3668 hysteresis = <5000>;
4673 type 3669 type = "passive";
4674 }; 3670 };
4675 3671
4676 trip-point1 { 3672 trip-point1 {
4677 tempe 3673 temperature = <115000>;
4678 hyste 3674 hysteresis = <5000>;
4679 type 3675 type = "passive";
4680 }; 3676 };
4681 }; 3677 };
4682 }; 3678 };
4683 3679
4684 audio-thermal { 3680 audio-thermal {
4685 thermal-sensors = <&t 3681 thermal-sensors = <&tsens0 8>;
4686 3682
4687 trips { 3683 trips {
4688 trip-point0 { 3684 trip-point0 {
4689 tempe 3685 temperature = <105000>;
4690 hyste 3686 hysteresis = <5000>;
4691 type 3687 type = "passive";
4692 }; 3688 };
4693 3689
4694 trip-point1 { 3690 trip-point1 {
4695 tempe 3691 temperature = <115000>;
4696 hyste 3692 hysteresis = <5000>;
4697 type 3693 type = "passive";
4698 }; 3694 };
4699 }; 3695 };
4700 }; 3696 };
4701 3697
4702 camss-0-thermal { 3698 camss-0-thermal {
4703 thermal-sensors = <&t 3699 thermal-sensors = <&tsens0 9>;
4704 3700
4705 trips { 3701 trips {
4706 trip-point0 { 3702 trip-point0 {
4707 tempe 3703 temperature = <105000>;
4708 hyste 3704 hysteresis = <5000>;
4709 type 3705 type = "passive";
4710 }; 3706 };
4711 3707
4712 trip-point1 { 3708 trip-point1 {
4713 tempe 3709 temperature = <115000>;
4714 hyste 3710 hysteresis = <5000>;
4715 type 3711 type = "passive";
4716 }; 3712 };
4717 }; 3713 };
4718 }; 3714 };
4719 3715
4720 pcie-0-thermal { 3716 pcie-0-thermal {
4721 thermal-sensors = <&t 3717 thermal-sensors = <&tsens0 10>;
4722 3718
4723 trips { 3719 trips {
4724 trip-point0 { 3720 trip-point0 {
4725 tempe 3721 temperature = <105000>;
4726 hyste 3722 hysteresis = <5000>;
4727 type 3723 type = "passive";
4728 }; 3724 };
4729 3725
4730 trip-point1 { 3726 trip-point1 {
4731 tempe 3727 temperature = <115000>;
4732 hyste 3728 hysteresis = <5000>;
4733 type 3729 type = "passive";
4734 }; 3730 };
4735 }; 3731 };
4736 }; 3732 };
4737 3733
4738 cpuss-0-0-thermal { 3734 cpuss-0-0-thermal {
4739 thermal-sensors = <&t 3735 thermal-sensors = <&tsens0 11>;
4740 3736
4741 trips { 3737 trips {
4742 trip-point0 { 3738 trip-point0 {
4743 tempe 3739 temperature = <105000>;
4744 hyste 3740 hysteresis = <5000>;
4745 type 3741 type = "passive";
4746 }; 3742 };
4747 3743
4748 trip-point1 { 3744 trip-point1 {
4749 tempe 3745 temperature = <115000>;
4750 hyste 3746 hysteresis = <5000>;
4751 type 3747 type = "passive";
4752 }; 3748 };
4753 }; 3749 };
4754 }; 3750 };
4755 3751
4756 aoss-1-thermal { 3752 aoss-1-thermal {
4757 thermal-sensors = <&t 3753 thermal-sensors = <&tsens1 0>;
4758 3754
4759 trips { 3755 trips {
4760 trip-point0 { 3756 trip-point0 {
4761 tempe 3757 temperature = <105000>;
4762 hyste 3758 hysteresis = <5000>;
4763 type 3759 type = "passive";
4764 }; 3760 };
4765 3761
4766 trip-point1 { 3762 trip-point1 {
4767 tempe 3763 temperature = <115000>;
4768 hyste 3764 hysteresis = <5000>;
4769 type 3765 type = "passive";
4770 }; 3766 };
4771 }; 3767 };
4772 }; 3768 };
4773 3769
4774 cpu-0-0-1-thermal { 3770 cpu-0-0-1-thermal {
4775 polling-delay-passive 3771 polling-delay-passive = <10>;
4776 3772
4777 thermal-sensors = <&t 3773 thermal-sensors = <&tsens1 1>;
4778 3774
4779 trips { 3775 trips {
4780 trip-point0 { 3776 trip-point0 {
4781 tempe 3777 temperature = <105000>;
4782 hyste 3778 hysteresis = <5000>;
4783 type 3779 type = "passive";
4784 }; 3780 };
4785 3781
4786 trip-point1 { 3782 trip-point1 {
4787 tempe 3783 temperature = <115000>;
4788 hyste 3784 hysteresis = <5000>;
4789 type 3785 type = "passive";
4790 }; 3786 };
4791 }; 3787 };
4792 }; 3788 };
4793 3789
4794 cpu-0-1-1-thermal { 3790 cpu-0-1-1-thermal {
4795 polling-delay-passive 3791 polling-delay-passive = <10>;
4796 3792
4797 thermal-sensors = <&t 3793 thermal-sensors = <&tsens1 2>;
4798 3794
4799 trips { 3795 trips {
4800 trip-point0 { 3796 trip-point0 {
4801 tempe 3797 temperature = <105000>;
4802 hyste 3798 hysteresis = <5000>;
4803 type 3799 type = "passive";
4804 }; 3800 };
4805 3801
4806 trip-point1 { 3802 trip-point1 {
4807 tempe 3803 temperature = <115000>;
4808 hyste 3804 hysteresis = <5000>;
4809 type 3805 type = "passive";
4810 }; 3806 };
4811 }; 3807 };
4812 }; 3808 };
4813 3809
4814 cpu-0-2-1-thermal { 3810 cpu-0-2-1-thermal {
4815 polling-delay-passive 3811 polling-delay-passive = <10>;
4816 3812
4817 thermal-sensors = <&t 3813 thermal-sensors = <&tsens1 3>;
4818 3814
4819 trips { 3815 trips {
4820 trip-point0 { 3816 trip-point0 {
4821 tempe 3817 temperature = <105000>;
4822 hyste 3818 hysteresis = <5000>;
4823 type 3819 type = "passive";
4824 }; 3820 };
4825 3821
4826 trip-point1 { 3822 trip-point1 {
4827 tempe 3823 temperature = <115000>;
4828 hyste 3824 hysteresis = <5000>;
4829 type 3825 type = "passive";
4830 }; 3826 };
4831 }; 3827 };
4832 }; 3828 };
4833 3829
4834 cpu-0-3-1-thermal { 3830 cpu-0-3-1-thermal {
4835 polling-delay-passive 3831 polling-delay-passive = <10>;
4836 3832
4837 thermal-sensors = <&t 3833 thermal-sensors = <&tsens1 4>;
4838 3834
4839 trips { 3835 trips {
4840 trip-point0 { 3836 trip-point0 {
4841 tempe 3837 temperature = <105000>;
4842 hyste 3838 hysteresis = <5000>;
4843 type 3839 type = "passive";
4844 }; 3840 };
4845 3841
4846 trip-point1 { 3842 trip-point1 {
4847 tempe 3843 temperature = <115000>;
4848 hyste 3844 hysteresis = <5000>;
4849 type 3845 type = "passive";
4850 }; 3846 };
4851 }; 3847 };
4852 }; 3848 };
4853 3849
4854 gpuss-3-thermal { 3850 gpuss-3-thermal {
4855 polling-delay-passive 3851 polling-delay-passive = <10>;
4856 3852
4857 thermal-sensors = <&t 3853 thermal-sensors = <&tsens1 5>;
4858 3854
4859 trips { 3855 trips {
4860 trip-point0 { 3856 trip-point0 {
4861 tempe 3857 temperature = <105000>;
4862 hyste 3858 hysteresis = <5000>;
4863 type 3859 type = "passive";
4864 }; 3860 };
4865 3861
4866 trip-point1 { 3862 trip-point1 {
4867 tempe 3863 temperature = <115000>;
4868 hyste 3864 hysteresis = <5000>;
4869 type 3865 type = "passive";
4870 }; 3866 };
4871 }; 3867 };
4872 }; 3868 };
4873 3869
4874 gpuss-4-thermal { 3870 gpuss-4-thermal {
4875 polling-delay-passive 3871 polling-delay-passive = <10>;
4876 3872
4877 thermal-sensors = <&t 3873 thermal-sensors = <&tsens1 6>;
4878 3874
4879 trips { 3875 trips {
4880 trip-point0 { 3876 trip-point0 {
4881 tempe 3877 temperature = <105000>;
4882 hyste 3878 hysteresis = <5000>;
4883 type 3879 type = "passive";
4884 }; 3880 };
4885 3881
4886 trip-point1 { 3882 trip-point1 {
4887 tempe 3883 temperature = <115000>;
4888 hyste 3884 hysteresis = <5000>;
4889 type 3885 type = "passive";
4890 }; 3886 };
4891 }; 3887 };
4892 }; 3888 };
4893 3889
4894 gpuss-5-thermal { 3890 gpuss-5-thermal {
4895 polling-delay-passive 3891 polling-delay-passive = <10>;
4896 3892
4897 thermal-sensors = <&t 3893 thermal-sensors = <&tsens1 7>;
4898 3894
4899 trips { 3895 trips {
4900 trip-point0 { 3896 trip-point0 {
4901 tempe 3897 temperature = <105000>;
4902 hyste 3898 hysteresis = <5000>;
4903 type 3899 type = "passive";
4904 }; 3900 };
4905 3901
4906 trip-point1 { 3902 trip-point1 {
4907 tempe 3903 temperature = <115000>;
4908 hyste 3904 hysteresis = <5000>;
4909 type 3905 type = "passive";
4910 }; 3906 };
4911 }; 3907 };
4912 }; 3908 };
4913 3909
4914 video-thermal { 3910 video-thermal {
4915 thermal-sensors = <&t 3911 thermal-sensors = <&tsens1 8>;
4916 3912
4917 trips { 3913 trips {
4918 trip-point0 { 3914 trip-point0 {
4919 tempe 3915 temperature = <105000>;
4920 hyste 3916 hysteresis = <5000>;
4921 type 3917 type = "passive";
4922 }; 3918 };
4923 3919
4924 trip-point1 { 3920 trip-point1 {
4925 tempe 3921 temperature = <115000>;
4926 hyste 3922 hysteresis = <5000>;
4927 type 3923 type = "passive";
4928 }; 3924 };
4929 }; 3925 };
4930 }; 3926 };
4931 3927
4932 camss-1-thermal { 3928 camss-1-thermal {
4933 thermal-sensors = <&t 3929 thermal-sensors = <&tsens1 9>;
4934 3930
4935 trips { 3931 trips {
4936 trip-point0 { 3932 trip-point0 {
4937 tempe 3933 temperature = <105000>;
4938 hyste 3934 hysteresis = <5000>;
4939 type 3935 type = "passive";
4940 }; 3936 };
4941 3937
4942 trip-point1 { 3938 trip-point1 {
4943 tempe 3939 temperature = <115000>;
4944 hyste 3940 hysteresis = <5000>;
4945 type 3941 type = "passive";
4946 }; 3942 };
4947 }; 3943 };
4948 }; 3944 };
4949 3945
4950 pcie-1-thermal { 3946 pcie-1-thermal {
4951 thermal-sensors = <&t 3947 thermal-sensors = <&tsens1 10>;
4952 3948
4953 trips { 3949 trips {
4954 trip-point0 { 3950 trip-point0 {
4955 tempe 3951 temperature = <105000>;
4956 hyste 3952 hysteresis = <5000>;
4957 type 3953 type = "passive";
4958 }; 3954 };
4959 3955
4960 trip-point1 { 3956 trip-point1 {
4961 tempe 3957 temperature = <115000>;
4962 hyste 3958 hysteresis = <5000>;
4963 type 3959 type = "passive";
4964 }; 3960 };
4965 }; 3961 };
4966 }; 3962 };
4967 3963
4968 cpuss-0-1-thermal { 3964 cpuss-0-1-thermal {
4969 thermal-sensors = <&t 3965 thermal-sensors = <&tsens1 11>;
4970 3966
4971 trips { 3967 trips {
4972 trip-point0 { 3968 trip-point0 {
4973 tempe 3969 temperature = <105000>;
4974 hyste 3970 hysteresis = <5000>;
4975 type 3971 type = "passive";
4976 }; 3972 };
4977 3973
4978 trip-point1 { 3974 trip-point1 {
4979 tempe 3975 temperature = <115000>;
4980 hyste 3976 hysteresis = <5000>;
4981 type 3977 type = "passive";
4982 }; 3978 };
4983 }; 3979 };
4984 }; 3980 };
4985 3981
4986 aoss-2-thermal { 3982 aoss-2-thermal {
4987 thermal-sensors = <&t 3983 thermal-sensors = <&tsens2 0>;
4988 3984
4989 trips { 3985 trips {
4990 trip-point0 { 3986 trip-point0 {
4991 tempe 3987 temperature = <105000>;
4992 hyste 3988 hysteresis = <5000>;
4993 type 3989 type = "passive";
4994 }; 3990 };
4995 3991
4996 trip-point1 { 3992 trip-point1 {
4997 tempe 3993 temperature = <115000>;
4998 hyste 3994 hysteresis = <5000>;
4999 type 3995 type = "passive";
5000 }; 3996 };
5001 }; 3997 };
5002 }; 3998 };
5003 3999
5004 cpu-1-0-0-thermal { 4000 cpu-1-0-0-thermal {
5005 polling-delay-passive 4001 polling-delay-passive = <10>;
5006 4002
5007 thermal-sensors = <&t 4003 thermal-sensors = <&tsens2 1>;
5008 4004
5009 trips { 4005 trips {
5010 trip-point0 { 4006 trip-point0 {
5011 tempe 4007 temperature = <105000>;
5012 hyste 4008 hysteresis = <5000>;
5013 type 4009 type = "passive";
5014 }; 4010 };
5015 4011
5016 trip-point1 { 4012 trip-point1 {
5017 tempe 4013 temperature = <115000>;
5018 hyste 4014 hysteresis = <5000>;
5019 type 4015 type = "passive";
5020 }; 4016 };
5021 }; 4017 };
5022 }; 4018 };
5023 4019
5024 cpu-1-1-0-thermal { 4020 cpu-1-1-0-thermal {
5025 polling-delay-passive 4021 polling-delay-passive = <10>;
5026 4022
5027 thermal-sensors = <&t 4023 thermal-sensors = <&tsens2 2>;
5028 4024
5029 trips { 4025 trips {
5030 trip-point0 { 4026 trip-point0 {
5031 tempe 4027 temperature = <105000>;
5032 hyste 4028 hysteresis = <5000>;
5033 type 4029 type = "passive";
5034 }; 4030 };
5035 4031
5036 trip-point1 { 4032 trip-point1 {
5037 tempe 4033 temperature = <115000>;
5038 hyste 4034 hysteresis = <5000>;
5039 type 4035 type = "passive";
5040 }; 4036 };
5041 }; 4037 };
5042 }; 4038 };
5043 4039
5044 cpu-1-2-0-thermal { 4040 cpu-1-2-0-thermal {
5045 polling-delay-passive 4041 polling-delay-passive = <10>;
5046 4042
5047 thermal-sensors = <&t 4043 thermal-sensors = <&tsens2 3>;
5048 4044
5049 trips { 4045 trips {
5050 trip-point0 { 4046 trip-point0 {
5051 tempe 4047 temperature = <105000>;
5052 hyste 4048 hysteresis = <5000>;
5053 type 4049 type = "passive";
5054 }; 4050 };
5055 4051
5056 trip-point1 { 4052 trip-point1 {
5057 tempe 4053 temperature = <115000>;
5058 hyste 4054 hysteresis = <5000>;
5059 type 4055 type = "passive";
5060 }; 4056 };
5061 }; 4057 };
5062 }; 4058 };
5063 4059
5064 cpu-1-3-0-thermal { 4060 cpu-1-3-0-thermal {
5065 polling-delay-passive 4061 polling-delay-passive = <10>;
5066 4062
5067 thermal-sensors = <&t 4063 thermal-sensors = <&tsens2 4>;
5068 4064
5069 trips { 4065 trips {
5070 trip-point0 { 4066 trip-point0 {
5071 tempe 4067 temperature = <105000>;
5072 hyste 4068 hysteresis = <5000>;
5073 type 4069 type = "passive";
5074 }; 4070 };
5075 4071
5076 trip-point1 { 4072 trip-point1 {
5077 tempe 4073 temperature = <115000>;
5078 hyste 4074 hysteresis = <5000>;
5079 type 4075 type = "passive";
5080 }; 4076 };
5081 }; 4077 };
5082 }; 4078 };
5083 4079
5084 nsp-0-0-0-thermal { 4080 nsp-0-0-0-thermal {
5085 polling-delay-passive 4081 polling-delay-passive = <10>;
5086 4082
5087 thermal-sensors = <&t 4083 thermal-sensors = <&tsens2 5>;
5088 4084
5089 trips { 4085 trips {
5090 trip-point0 { 4086 trip-point0 {
5091 tempe 4087 temperature = <105000>;
5092 hyste 4088 hysteresis = <5000>;
5093 type 4089 type = "passive";
5094 }; 4090 };
5095 4091
5096 trip-point1 { 4092 trip-point1 {
5097 tempe 4093 temperature = <115000>;
5098 hyste 4094 hysteresis = <5000>;
5099 type 4095 type = "passive";
5100 }; 4096 };
5101 }; 4097 };
5102 }; 4098 };
5103 4099
5104 nsp-0-1-0-thermal { 4100 nsp-0-1-0-thermal {
5105 polling-delay-passive 4101 polling-delay-passive = <10>;
5106 4102
5107 thermal-sensors = <&t 4103 thermal-sensors = <&tsens2 6>;
5108 4104
5109 trips { 4105 trips {
5110 trip-point0 { 4106 trip-point0 {
5111 tempe 4107 temperature = <105000>;
5112 hyste 4108 hysteresis = <5000>;
5113 type 4109 type = "passive";
5114 }; 4110 };
5115 4111
5116 trip-point1 { 4112 trip-point1 {
5117 tempe 4113 temperature = <115000>;
5118 hyste 4114 hysteresis = <5000>;
5119 type 4115 type = "passive";
5120 }; 4116 };
5121 }; 4117 };
5122 }; 4118 };
5123 4119
5124 nsp-0-2-0-thermal { 4120 nsp-0-2-0-thermal {
5125 polling-delay-passive 4121 polling-delay-passive = <10>;
5126 4122
5127 thermal-sensors = <&t 4123 thermal-sensors = <&tsens2 7>;
5128 4124
5129 trips { 4125 trips {
5130 trip-point0 { 4126 trip-point0 {
5131 tempe 4127 temperature = <105000>;
5132 hyste 4128 hysteresis = <5000>;
5133 type 4129 type = "passive";
5134 }; 4130 };
5135 4131
5136 trip-point1 { 4132 trip-point1 {
5137 tempe 4133 temperature = <115000>;
5138 hyste 4134 hysteresis = <5000>;
5139 type 4135 type = "passive";
5140 }; 4136 };
5141 }; 4137 };
5142 }; 4138 };
5143 4139
5144 nsp-1-0-0-thermal { 4140 nsp-1-0-0-thermal {
5145 polling-delay-passive 4141 polling-delay-passive = <10>;
5146 4142
5147 thermal-sensors = <&t 4143 thermal-sensors = <&tsens2 8>;
5148 4144
5149 trips { 4145 trips {
5150 trip-point0 { 4146 trip-point0 {
5151 tempe 4147 temperature = <105000>;
5152 hyste 4148 hysteresis = <5000>;
5153 type 4149 type = "passive";
5154 }; 4150 };
5155 4151
5156 trip-point1 { 4152 trip-point1 {
5157 tempe 4153 temperature = <115000>;
5158 hyste 4154 hysteresis = <5000>;
5159 type 4155 type = "passive";
5160 }; 4156 };
5161 }; 4157 };
5162 }; 4158 };
5163 4159
5164 nsp-1-1-0-thermal { 4160 nsp-1-1-0-thermal {
5165 polling-delay-passive 4161 polling-delay-passive = <10>;
5166 4162
5167 thermal-sensors = <&t 4163 thermal-sensors = <&tsens2 9>;
5168 4164
5169 trips { 4165 trips {
5170 trip-point0 { 4166 trip-point0 {
5171 tempe 4167 temperature = <105000>;
5172 hyste 4168 hysteresis = <5000>;
5173 type 4169 type = "passive";
5174 }; 4170 };
5175 4171
5176 trip-point1 { 4172 trip-point1 {
5177 tempe 4173 temperature = <115000>;
5178 hyste 4174 hysteresis = <5000>;
5179 type 4175 type = "passive";
5180 }; 4176 };
5181 }; 4177 };
5182 }; 4178 };
5183 4179
5184 nsp-1-2-0-thermal { 4180 nsp-1-2-0-thermal {
5185 polling-delay-passive 4181 polling-delay-passive = <10>;
5186 4182
5187 thermal-sensors = <&t 4183 thermal-sensors = <&tsens2 10>;
5188 4184
5189 trips { 4185 trips {
5190 trip-point0 { 4186 trip-point0 {
5191 tempe 4187 temperature = <105000>;
5192 hyste 4188 hysteresis = <5000>;
5193 type 4189 type = "passive";
5194 }; 4190 };
5195 4191
5196 trip-point1 { 4192 trip-point1 {
5197 tempe 4193 temperature = <115000>;
5198 hyste 4194 hysteresis = <5000>;
5199 type 4195 type = "passive";
5200 }; 4196 };
5201 }; 4197 };
5202 }; 4198 };
5203 4199
5204 ddrss-0-thermal { 4200 ddrss-0-thermal {
5205 thermal-sensors = <&t 4201 thermal-sensors = <&tsens2 11>;
5206 4202
5207 trips { 4203 trips {
5208 trip-point0 { 4204 trip-point0 {
5209 tempe 4205 temperature = <105000>;
5210 hyste 4206 hysteresis = <5000>;
5211 type 4207 type = "passive";
5212 }; 4208 };
5213 4209
5214 trip-point1 { 4210 trip-point1 {
5215 tempe 4211 temperature = <115000>;
5216 hyste 4212 hysteresis = <5000>;
5217 type 4213 type = "passive";
5218 }; 4214 };
5219 }; 4215 };
5220 }; 4216 };
5221 4217
5222 cpuss-1-0-thermal { 4218 cpuss-1-0-thermal {
5223 thermal-sensors = <&t 4219 thermal-sensors = <&tsens2 12>;
5224 4220
5225 trips { 4221 trips {
5226 trip-point0 { 4222 trip-point0 {
5227 tempe 4223 temperature = <105000>;
5228 hyste 4224 hysteresis = <5000>;
5229 type 4225 type = "passive";
5230 }; 4226 };
5231 4227
5232 trip-point1 { 4228 trip-point1 {
5233 tempe 4229 temperature = <115000>;
5234 hyste 4230 hysteresis = <5000>;
5235 type 4231 type = "passive";
5236 }; 4232 };
5237 }; 4233 };
5238 }; 4234 };
5239 4235
5240 aoss-3-thermal { 4236 aoss-3-thermal {
5241 thermal-sensors = <&t 4237 thermal-sensors = <&tsens3 0>;
5242 4238
5243 trips { 4239 trips {
5244 trip-point0 { 4240 trip-point0 {
5245 tempe 4241 temperature = <105000>;
5246 hyste 4242 hysteresis = <5000>;
5247 type 4243 type = "passive";
5248 }; 4244 };
5249 4245
5250 trip-point1 { 4246 trip-point1 {
5251 tempe 4247 temperature = <115000>;
5252 hyste 4248 hysteresis = <5000>;
5253 type 4249 type = "passive";
5254 }; 4250 };
5255 }; 4251 };
5256 }; 4252 };
5257 4253
5258 cpu-1-0-1-thermal { 4254 cpu-1-0-1-thermal {
5259 polling-delay-passive 4255 polling-delay-passive = <10>;
5260 4256
5261 thermal-sensors = <&t 4257 thermal-sensors = <&tsens3 1>;
5262 4258
5263 trips { 4259 trips {
5264 trip-point0 { 4260 trip-point0 {
5265 tempe 4261 temperature = <105000>;
5266 hyste 4262 hysteresis = <5000>;
5267 type 4263 type = "passive";
5268 }; 4264 };
5269 4265
5270 trip-point1 { 4266 trip-point1 {
5271 tempe 4267 temperature = <115000>;
5272 hyste 4268 hysteresis = <5000>;
5273 type 4269 type = "passive";
5274 }; 4270 };
5275 }; 4271 };
5276 }; 4272 };
5277 4273
5278 cpu-1-1-1-thermal { 4274 cpu-1-1-1-thermal {
5279 polling-delay-passive 4275 polling-delay-passive = <10>;
5280 4276
5281 thermal-sensors = <&t 4277 thermal-sensors = <&tsens3 2>;
5282 4278
5283 trips { 4279 trips {
5284 trip-point0 { 4280 trip-point0 {
5285 tempe 4281 temperature = <105000>;
5286 hyste 4282 hysteresis = <5000>;
5287 type 4283 type = "passive";
5288 }; 4284 };
5289 4285
5290 trip-point1 { 4286 trip-point1 {
5291 tempe 4287 temperature = <115000>;
5292 hyste 4288 hysteresis = <5000>;
5293 type 4289 type = "passive";
5294 }; 4290 };
5295 }; 4291 };
5296 }; 4292 };
5297 4293
5298 cpu-1-2-1-thermal { 4294 cpu-1-2-1-thermal {
5299 polling-delay-passive 4295 polling-delay-passive = <10>;
5300 4296
5301 thermal-sensors = <&t 4297 thermal-sensors = <&tsens3 3>;
5302 4298
5303 trips { 4299 trips {
5304 trip-point0 { 4300 trip-point0 {
5305 tempe 4301 temperature = <105000>;
5306 hyste 4302 hysteresis = <5000>;
5307 type 4303 type = "passive";
5308 }; 4304 };
5309 4305
5310 trip-point1 { 4306 trip-point1 {
5311 tempe 4307 temperature = <115000>;
5312 hyste 4308 hysteresis = <5000>;
5313 type 4309 type = "passive";
5314 }; 4310 };
5315 }; 4311 };
5316 }; 4312 };
5317 4313
5318 cpu-1-3-1-thermal { 4314 cpu-1-3-1-thermal {
5319 polling-delay-passive 4315 polling-delay-passive = <10>;
5320 4316
5321 thermal-sensors = <&t 4317 thermal-sensors = <&tsens3 4>;
5322 4318
5323 trips { 4319 trips {
5324 trip-point0 { 4320 trip-point0 {
5325 tempe 4321 temperature = <105000>;
5326 hyste 4322 hysteresis = <5000>;
5327 type 4323 type = "passive";
5328 }; 4324 };
5329 4325
5330 trip-point1 { 4326 trip-point1 {
5331 tempe 4327 temperature = <115000>;
5332 hyste 4328 hysteresis = <5000>;
5333 type 4329 type = "passive";
5334 }; 4330 };
5335 }; 4331 };
5336 }; 4332 };
5337 4333
5338 nsp-0-0-1-thermal { 4334 nsp-0-0-1-thermal {
5339 polling-delay-passive 4335 polling-delay-passive = <10>;
5340 4336
5341 thermal-sensors = <&t 4337 thermal-sensors = <&tsens3 5>;
5342 4338
5343 trips { 4339 trips {
5344 trip-point0 { 4340 trip-point0 {
5345 tempe 4341 temperature = <105000>;
5346 hyste 4342 hysteresis = <5000>;
5347 type 4343 type = "passive";
5348 }; 4344 };
5349 4345
5350 trip-point1 { 4346 trip-point1 {
5351 tempe 4347 temperature = <115000>;
5352 hyste 4348 hysteresis = <5000>;
5353 type 4349 type = "passive";
5354 }; 4350 };
5355 }; 4351 };
5356 }; 4352 };
5357 4353
5358 nsp-0-1-1-thermal { 4354 nsp-0-1-1-thermal {
5359 polling-delay-passive 4355 polling-delay-passive = <10>;
5360 4356
5361 thermal-sensors = <&t 4357 thermal-sensors = <&tsens3 6>;
5362 4358
5363 trips { 4359 trips {
5364 trip-point0 { 4360 trip-point0 {
5365 tempe 4361 temperature = <105000>;
5366 hyste 4362 hysteresis = <5000>;
5367 type 4363 type = "passive";
5368 }; 4364 };
5369 4365
5370 trip-point1 { 4366 trip-point1 {
5371 tempe 4367 temperature = <115000>;
5372 hyste 4368 hysteresis = <5000>;
5373 type 4369 type = "passive";
5374 }; 4370 };
5375 }; 4371 };
5376 }; 4372 };
5377 4373
5378 nsp-0-2-1-thermal { 4374 nsp-0-2-1-thermal {
5379 polling-delay-passive 4375 polling-delay-passive = <10>;
5380 4376
5381 thermal-sensors = <&t 4377 thermal-sensors = <&tsens3 7>;
5382 4378
5383 trips { 4379 trips {
5384 trip-point0 { 4380 trip-point0 {
5385 tempe 4381 temperature = <105000>;
5386 hyste 4382 hysteresis = <5000>;
5387 type 4383 type = "passive";
5388 }; 4384 };
5389 4385
5390 trip-point1 { 4386 trip-point1 {
5391 tempe 4387 temperature = <115000>;
5392 hyste 4388 hysteresis = <5000>;
5393 type 4389 type = "passive";
5394 }; 4390 };
5395 }; 4391 };
5396 }; 4392 };
5397 4393
5398 nsp-1-0-1-thermal { 4394 nsp-1-0-1-thermal {
5399 polling-delay-passive 4395 polling-delay-passive = <10>;
5400 4396
5401 thermal-sensors = <&t 4397 thermal-sensors = <&tsens3 8>;
5402 4398
5403 trips { 4399 trips {
5404 trip-point0 { 4400 trip-point0 {
5405 tempe 4401 temperature = <105000>;
5406 hyste 4402 hysteresis = <5000>;
5407 type 4403 type = "passive";
5408 }; 4404 };
5409 4405
5410 trip-point1 { 4406 trip-point1 {
5411 tempe 4407 temperature = <115000>;
5412 hyste 4408 hysteresis = <5000>;
5413 type 4409 type = "passive";
5414 }; 4410 };
5415 }; 4411 };
5416 }; 4412 };
5417 4413
5418 nsp-1-1-1-thermal { 4414 nsp-1-1-1-thermal {
5419 polling-delay-passive 4415 polling-delay-passive = <10>;
5420 4416
5421 thermal-sensors = <&t 4417 thermal-sensors = <&tsens3 9>;
5422 4418
5423 trips { 4419 trips {
5424 trip-point0 { 4420 trip-point0 {
5425 tempe 4421 temperature = <105000>;
5426 hyste 4422 hysteresis = <5000>;
5427 type 4423 type = "passive";
5428 }; 4424 };
5429 4425
5430 trip-point1 { 4426 trip-point1 {
5431 tempe 4427 temperature = <115000>;
5432 hyste 4428 hysteresis = <5000>;
5433 type 4429 type = "passive";
5434 }; 4430 };
5435 }; 4431 };
5436 }; 4432 };
5437 4433
5438 nsp-1-2-1-thermal { 4434 nsp-1-2-1-thermal {
5439 polling-delay-passive 4435 polling-delay-passive = <10>;
5440 4436
5441 thermal-sensors = <&t 4437 thermal-sensors = <&tsens3 10>;
5442 4438
5443 trips { 4439 trips {
5444 trip-point0 { 4440 trip-point0 {
5445 tempe 4441 temperature = <105000>;
5446 hyste 4442 hysteresis = <5000>;
5447 type 4443 type = "passive";
5448 }; 4444 };
5449 4445
5450 trip-point1 { 4446 trip-point1 {
5451 tempe 4447 temperature = <115000>;
5452 hyste 4448 hysteresis = <5000>;
5453 type 4449 type = "passive";
5454 }; 4450 };
5455 }; 4451 };
5456 }; 4452 };
5457 4453
5458 ddrss-1-thermal { 4454 ddrss-1-thermal {
5459 thermal-sensors = <&t 4455 thermal-sensors = <&tsens3 11>;
5460 4456
5461 trips { 4457 trips {
5462 trip-point0 { 4458 trip-point0 {
5463 tempe 4459 temperature = <105000>;
5464 hyste 4460 hysteresis = <5000>;
5465 type 4461 type = "passive";
5466 }; 4462 };
5467 4463
5468 trip-point1 { 4464 trip-point1 {
5469 tempe 4465 temperature = <115000>;
5470 hyste 4466 hysteresis = <5000>;
5471 type 4467 type = "passive";
5472 }; 4468 };
5473 }; 4469 };
5474 }; 4470 };
5475 4471
5476 cpuss-1-1-thermal { 4472 cpuss-1-1-thermal {
5477 thermal-sensors = <&t 4473 thermal-sensors = <&tsens3 12>;
5478 4474
5479 trips { 4475 trips {
5480 trip-point0 { 4476 trip-point0 {
5481 tempe 4477 temperature = <105000>;
5482 hyste 4478 hysteresis = <5000>;
5483 type 4479 type = "passive";
5484 }; 4480 };
5485 4481
5486 trip-point1 { 4482 trip-point1 {
5487 tempe 4483 temperature = <115000>;
5488 hyste 4484 hysteresis = <5000>;
5489 type 4485 type = "passive";
5490 }; 4486 };
5491 }; 4487 };
5492 }; 4488 };
5493 }; 4489 };
5494 4490
5495 arch_timer: timer { 4491 arch_timer: timer {
5496 compatible = "arm,armv8-timer 4492 compatible = "arm,armv8-timer";
5497 interrupts = <GIC_PPI 13 (GIC 4493 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5498 <GIC_PPI 14 (GIC 4494 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5499 <GIC_PPI 11 (GIC 4495 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5500 <GIC_PPI 10 (GIC 4496 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
5501 }; 4497 };
5502 4498
5503 pcie0: pcie@1c00000 { 4499 pcie0: pcie@1c00000 {
5504 compatible = "qcom,pcie-sa877 4500 compatible = "qcom,pcie-sa8775p";
5505 reg = <0x0 0x01c00000 0x0 0x3 4501 reg = <0x0 0x01c00000 0x0 0x3000>,
5506 <0x0 0x40000000 0x0 0xf 4502 <0x0 0x40000000 0x0 0xf20>,
5507 <0x0 0x40000f20 0x0 0xa 4503 <0x0 0x40000f20 0x0 0xa8>,
5508 <0x0 0x40001000 0x0 0x4 4504 <0x0 0x40001000 0x0 0x4000>,
5509 <0x0 0x40100000 0x0 0x1 4505 <0x0 0x40100000 0x0 0x100000>,
5510 <0x0 0x01c03000 0x0 0x1 4506 <0x0 0x01c03000 0x0 0x1000>;
5511 reg-names = "parf", "dbi", "e 4507 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
5512 device_type = "pci"; 4508 device_type = "pci";
5513 4509
5514 #address-cells = <3>; 4510 #address-cells = <3>;
5515 #size-cells = <2>; 4511 #size-cells = <2>;
5516 ranges = <0x01000000 0x0 0x00 4512 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
5517 <0x02000000 0x0 0x40 4513 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
5518 bus-range = <0x00 0xff>; 4514 bus-range = <0x00 0xff>;
5519 4515
5520 dma-coherent; 4516 dma-coherent;
5521 4517
5522 linux,pci-domain = <0>; 4518 linux,pci-domain = <0>;
5523 num-lanes = <2>; 4519 num-lanes = <2>;
5524 4520
5525 interrupts = <GIC_SPI 307 IRQ 4521 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
5526 <GIC_SPI 308 IRQ 4522 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
5527 <GIC_SPI 309 IRQ 4523 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
5528 <GIC_SPI 312 IRQ 4524 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
5529 <GIC_SPI 313 IRQ 4525 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
5530 <GIC_SPI 314 IRQ 4526 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
5531 <GIC_SPI 374 IRQ 4527 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
5532 <GIC_SPI 375 IRQ 4528 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
5533 interrupt-names = "msi0", "ms 4529 interrupt-names = "msi0", "msi1", "msi2", "msi3",
5534 "msi4", "ms 4530 "msi4", "msi5", "msi6", "msi7";
5535 #interrupt-cells = <1>; 4531 #interrupt-cells = <1>;
5536 interrupt-map-mask = <0 0 0 0 4532 interrupt-map-mask = <0 0 0 0x7>;
5537 interrupt-map = <0 0 0 1 &int 4533 interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
5538 <0 0 0 2 &int 4534 <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
5539 <0 0 0 3 &int 4535 <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
5540 <0 0 0 4 &int 4536 <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>;
5541 4537
5542 clocks = <&gcc GCC_PCIE_0_AUX 4538 clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
5543 <&gcc GCC_PCIE_0_CFG 4539 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
5544 <&gcc GCC_PCIE_0_MST 4540 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
5545 <&gcc GCC_PCIE_0_SLV 4541 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
5546 <&gcc GCC_PCIE_0_SLV 4542 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>;
5547 4543
5548 clock-names = "aux", 4544 clock-names = "aux",
5549 "cfg", 4545 "cfg",
5550 "bus_master", 4546 "bus_master",
5551 "bus_slave", 4547 "bus_slave",
5552 "slave_q2a"; 4548 "slave_q2a";
5553 4549
5554 assigned-clocks = <&gcc GCC_P 4550 assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>;
5555 assigned-clock-rates = <19200 4551 assigned-clock-rates = <19200000>;
5556 4552
5557 interconnects = <&pcie_anoc M 4553 interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>,
5558 <&gem_noc MAS 4554 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>;
5559 interconnect-names = "pcie-me 4555 interconnect-names = "pcie-mem", "cpu-pcie";
5560 4556
5561 iommu-map = <0x0 &pcie_smmu 0 4557 iommu-map = <0x0 &pcie_smmu 0x0000 0x1>,
5562 <0x100 &pcie_smmu 4558 <0x100 &pcie_smmu 0x0001 0x1>;
5563 4559
5564 resets = <&gcc GCC_PCIE_0_BCR 4560 resets = <&gcc GCC_PCIE_0_BCR>;
5565 reset-names = "pci"; 4561 reset-names = "pci";
5566 power-domains = <&gcc PCIE_0_ 4562 power-domains = <&gcc PCIE_0_GDSC>;
5567 4563
5568 phys = <&pcie0_phy>; 4564 phys = <&pcie0_phy>;
5569 phy-names = "pciephy"; 4565 phy-names = "pciephy";
5570 4566
5571 status = "disabled"; 4567 status = "disabled";
5572 4568
5573 pcie@0 { 4569 pcie@0 {
5574 device_type = "pci"; 4570 device_type = "pci";
5575 reg = <0x0 0x0 0x0 0x 4571 reg = <0x0 0x0 0x0 0x0 0x0>;
5576 bus-range = <0x01 0xf 4572 bus-range = <0x01 0xff>;
5577 4573
5578 #address-cells = <3>; 4574 #address-cells = <3>;
5579 #size-cells = <2>; 4575 #size-cells = <2>;
5580 ranges; 4576 ranges;
5581 }; 4577 };
5582 }; 4578 };
5583 4579
5584 pcie0_ep: pcie-ep@1c00000 { 4580 pcie0_ep: pcie-ep@1c00000 {
5585 compatible = "qcom,sa8775p-pc 4581 compatible = "qcom,sa8775p-pcie-ep";
5586 reg = <0x0 0x01c00000 0x0 0x3 4582 reg = <0x0 0x01c00000 0x0 0x3000>,
5587 <0x0 0x40000000 0x0 0xf 4583 <0x0 0x40000000 0x0 0xf20>,
5588 <0x0 0x40000f20 0x0 0xa 4584 <0x0 0x40000f20 0x0 0xa8>,
5589 <0x0 0x40001000 0x0 0x4 4585 <0x0 0x40001000 0x0 0x4000>,
5590 <0x0 0x40200000 0x0 0x1 4586 <0x0 0x40200000 0x0 0x100000>,
5591 <0x0 0x01c03000 0x0 0x1 4587 <0x0 0x01c03000 0x0 0x1000>,
5592 <0x0 0x40005000 0x0 0x2 4588 <0x0 0x40005000 0x0 0x2000>;
5593 reg-names = "parf", "dbi", "e 4589 reg-names = "parf", "dbi", "elbi", "atu", "addr_space",
5594 "mmio", "dma"; 4590 "mmio", "dma";
5595 4591
5596 clocks = <&gcc GCC_PCIE_0_AUX 4592 clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
5597 <&gcc GCC_PCIE_0_CFG_ 4593 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
5598 <&gcc GCC_PCIE_0_MSTR 4594 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
5599 <&gcc GCC_PCIE_0_SLV_ 4595 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
5600 <&gcc GCC_PCIE_0_SLV_ 4596 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>;
5601 4597
5602 clock-names = "aux", 4598 clock-names = "aux",
5603 "cfg", 4599 "cfg",
5604 "bus_master", 4600 "bus_master",
5605 "bus_slave", 4601 "bus_slave",
5606 "slave_q2a"; 4602 "slave_q2a";
5607 4603
5608 interrupts = <GIC_SPI 306 IRQ 4604 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
5609 <GIC_SPI 147 IRQ 4605 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
5610 <GIC_SPI 630 IRQ 4606 <GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH>;
5611 4607
5612 interrupt-names = "global", " 4608 interrupt-names = "global", "doorbell", "dma";
5613 4609
5614 interconnects = <&pcie_anoc M 4610 interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>,
5615 <&gem_noc MAS 4611 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>;
5616 interconnect-names = "pcie-me 4612 interconnect-names = "pcie-mem", "cpu-pcie";
5617 4613
5618 dma-coherent; 4614 dma-coherent;
5619 iommus = <&pcie_smmu 0x0000 0 4615 iommus = <&pcie_smmu 0x0000 0x7f>;
5620 resets = <&gcc GCC_PCIE_0_BCR 4616 resets = <&gcc GCC_PCIE_0_BCR>;
5621 reset-names = "core"; 4617 reset-names = "core";
5622 power-domains = <&gcc PCIE_0_ 4618 power-domains = <&gcc PCIE_0_GDSC>;
5623 phys = <&pcie0_phy>; 4619 phys = <&pcie0_phy>;
5624 phy-names = "pciephy"; 4620 phy-names = "pciephy";
5625 max-link-speed = <3>; /* FIXM 4621 max-link-speed = <3>; /* FIXME: Limiting the Gen speed due to stability issues */
5626 num-lanes = <2>; 4622 num-lanes = <2>;
5627 4623
5628 status = "disabled"; 4624 status = "disabled";
5629 }; 4625 };
5630 4626
5631 pcie0_phy: phy@1c04000 { 4627 pcie0_phy: phy@1c04000 {
5632 compatible = "qcom,sa8775p-qm 4628 compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy";
5633 reg = <0x0 0x1c04000 0x0 0x20 4629 reg = <0x0 0x1c04000 0x0 0x2000>;
5634 4630
5635 clocks = <&gcc GCC_PCIE_0_AUX 4631 clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
5636 <&gcc GCC_PCIE_0_CFG 4632 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
5637 <&gcc GCC_PCIE_CLKRE 4633 <&gcc GCC_PCIE_CLKREF_EN>,
5638 <&gcc GCC_PCIE_0_PHY 4634 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
5639 <&gcc GCC_PCIE_0_PIP 4635 <&gcc GCC_PCIE_0_PIPE_CLK>,
5640 <&gcc GCC_PCIE_0_PIP 4636 <&gcc GCC_PCIE_0_PIPEDIV2_CLK>,
5641 <&gcc GCC_PCIE_0_PHY 4637 <&gcc GCC_PCIE_0_PHY_AUX_CLK>;
5642 4638
5643 clock-names = "aux", "cfg_ahb 4639 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe",
5644 "pipediv2", "ph 4640 "pipediv2", "phy_aux";
5645 4641
5646 assigned-clocks = <&gcc GCC_P 4642 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
5647 assigned-clock-rates = <10000 4643 assigned-clock-rates = <100000000>;
5648 4644
5649 resets = <&gcc GCC_PCIE_0_PHY 4645 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
5650 reset-names = "phy"; 4646 reset-names = "phy";
5651 4647
5652 #clock-cells = <0>; 4648 #clock-cells = <0>;
5653 clock-output-names = "pcie_0_ 4649 clock-output-names = "pcie_0_pipe_clk";
5654 4650
5655 #phy-cells = <0>; 4651 #phy-cells = <0>;
5656 4652
5657 status = "disabled"; 4653 status = "disabled";
5658 }; 4654 };
5659 4655
5660 pcie1: pcie@1c10000 { 4656 pcie1: pcie@1c10000 {
5661 compatible = "qcom,pcie-sa877 4657 compatible = "qcom,pcie-sa8775p";
5662 reg = <0x0 0x01c10000 0x0 0x3 4658 reg = <0x0 0x01c10000 0x0 0x3000>,
5663 <0x0 0x60000000 0x0 0xf 4659 <0x0 0x60000000 0x0 0xf20>,
5664 <0x0 0x60000f20 0x0 0xa 4660 <0x0 0x60000f20 0x0 0xa8>,
5665 <0x0 0x60001000 0x0 0x4 4661 <0x0 0x60001000 0x0 0x4000>,
5666 <0x0 0x60100000 0x0 0x1 4662 <0x0 0x60100000 0x0 0x100000>,
5667 <0x0 0x01c13000 0x0 0x1 4663 <0x0 0x01c13000 0x0 0x1000>;
5668 reg-names = "parf", "dbi", "e 4664 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
5669 device_type = "pci"; 4665 device_type = "pci";
5670 4666
5671 #address-cells = <3>; 4667 #address-cells = <3>;
5672 #size-cells = <2>; 4668 #size-cells = <2>;
5673 ranges = <0x01000000 0x0 0x00 4669 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
5674 <0x02000000 0x0 0x60 4670 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x1fd00000>;
5675 bus-range = <0x00 0xff>; 4671 bus-range = <0x00 0xff>;
5676 4672
5677 dma-coherent; 4673 dma-coherent;
5678 4674
5679 linux,pci-domain = <1>; 4675 linux,pci-domain = <1>;
5680 num-lanes = <4>; 4676 num-lanes = <4>;
5681 4677
5682 interrupts = <GIC_SPI 519 IRQ 4678 interrupts = <GIC_SPI 519 IRQ_TYPE_LEVEL_HIGH>,
5683 <GIC_SPI 140 IRQ 4679 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
5684 <GIC_SPI 141 IRQ 4680 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
5685 <GIC_SPI 142 IRQ 4681 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
5686 <GIC_SPI 143 IRQ 4682 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
5687 <GIC_SPI 144 IRQ 4683 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
5688 <GIC_SPI 145 IRQ 4684 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
5689 <GIC_SPI 146 IRQ 4685 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
5690 interrupt-names = "msi0", "ms 4686 interrupt-names = "msi0", "msi1", "msi2", "msi3",
5691 "msi4", "ms 4687 "msi4", "msi5", "msi6", "msi7";
5692 #interrupt-cells = <1>; 4688 #interrupt-cells = <1>;
5693 interrupt-map-mask = <0 0 0 0 4689 interrupt-map-mask = <0 0 0 0x7>;
5694 interrupt-map = <0 0 0 1 &int 4690 interrupt-map = <0 0 0 1 &intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
5695 <0 0 0 2 &int 4691 <0 0 0 2 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
5696 <0 0 0 3 &int 4692 <0 0 0 3 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
5697 <0 0 0 4 &int 4693 <0 0 0 4 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
5698 4694
5699 clocks = <&gcc GCC_PCIE_1_AUX 4695 clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
5700 <&gcc GCC_PCIE_1_CFG 4696 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
5701 <&gcc GCC_PCIE_1_MST 4697 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
5702 <&gcc GCC_PCIE_1_SLV 4698 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
5703 <&gcc GCC_PCIE_1_SLV 4699 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>;
5704 4700
5705 clock-names = "aux", 4701 clock-names = "aux",
5706 "cfg", 4702 "cfg",
5707 "bus_master", 4703 "bus_master",
5708 "bus_slave", 4704 "bus_slave",
5709 "slave_q2a"; 4705 "slave_q2a";
5710 4706
5711 assigned-clocks = <&gcc GCC_P 4707 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
5712 assigned-clock-rates = <19200 4708 assigned-clock-rates = <19200000>;
5713 4709
5714 interconnects = <&pcie_anoc M 4710 interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>,
5715 <&gem_noc MAS 4711 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>;
5716 interconnect-names = "pcie-me 4712 interconnect-names = "pcie-mem", "cpu-pcie";
5717 4713
5718 iommu-map = <0x0 &pcie_smmu 0 4714 iommu-map = <0x0 &pcie_smmu 0x0080 0x1>,
5719 <0x100 &pcie_smmu 4715 <0x100 &pcie_smmu 0x0081 0x1>;
5720 4716
5721 resets = <&gcc GCC_PCIE_1_BCR 4717 resets = <&gcc GCC_PCIE_1_BCR>;
5722 reset-names = "pci"; 4718 reset-names = "pci";
5723 power-domains = <&gcc PCIE_1_ 4719 power-domains = <&gcc PCIE_1_GDSC>;
5724 4720
5725 phys = <&pcie1_phy>; 4721 phys = <&pcie1_phy>;
5726 phy-names = "pciephy"; 4722 phy-names = "pciephy";
5727 4723
5728 status = "disabled"; 4724 status = "disabled";
5729 4725
5730 pcie@0 { 4726 pcie@0 {
5731 device_type = "pci"; 4727 device_type = "pci";
5732 reg = <0x0 0x0 0x0 0x 4728 reg = <0x0 0x0 0x0 0x0 0x0>;
5733 bus-range = <0x01 0xf 4729 bus-range = <0x01 0xff>;
5734 4730
5735 #address-cells = <3>; 4731 #address-cells = <3>;
5736 #size-cells = <2>; 4732 #size-cells = <2>;
5737 ranges; 4733 ranges;
5738 }; 4734 };
5739 }; 4735 };
5740 4736
5741 pcie1_ep: pcie-ep@1c10000 { 4737 pcie1_ep: pcie-ep@1c10000 {
5742 compatible = "qcom,sa8775p-pc 4738 compatible = "qcom,sa8775p-pcie-ep";
5743 reg = <0x0 0x01c10000 0x0 0x3 4739 reg = <0x0 0x01c10000 0x0 0x3000>,
5744 <0x0 0x60000000 0x0 0xf 4740 <0x0 0x60000000 0x0 0xf20>,
5745 <0x0 0x60000f20 0x0 0xa 4741 <0x0 0x60000f20 0x0 0xa8>,
5746 <0x0 0x60001000 0x0 0x4 4742 <0x0 0x60001000 0x0 0x4000>,
5747 <0x0 0x60200000 0x0 0x1 4743 <0x0 0x60200000 0x0 0x100000>,
5748 <0x0 0x01c13000 0x0 0x1 4744 <0x0 0x01c13000 0x0 0x1000>,
5749 <0x0 0x60005000 0x0 0x2 4745 <0x0 0x60005000 0x0 0x2000>;
5750 reg-names = "parf", "dbi", "e 4746 reg-names = "parf", "dbi", "elbi", "atu", "addr_space",
5751 "mmio", "dma"; 4747 "mmio", "dma";
5752 4748
5753 clocks = <&gcc GCC_PCIE_1_AUX 4749 clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
5754 <&gcc GCC_PCIE_1_CFG 4750 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
5755 <&gcc GCC_PCIE_1_MST 4751 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
5756 <&gcc GCC_PCIE_1_SLV 4752 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
5757 <&gcc GCC_PCIE_1_SLV 4753 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>;
5758 4754
5759 clock-names = "aux", 4755 clock-names = "aux",
5760 "cfg", 4756 "cfg",
5761 "bus_master", 4757 "bus_master",
5762 "bus_slave", 4758 "bus_slave",
5763 "slave_q2a"; 4759 "slave_q2a";
5764 4760
5765 interrupts = <GIC_SPI 518 IRQ 4761 interrupts = <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>,
5766 <GIC_SPI 152 IRQ 4762 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
5767 <GIC_SPI 474 IRQ 4763 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
5768 4764
5769 interrupt-names = "global", " 4765 interrupt-names = "global", "doorbell", "dma";
5770 4766
5771 interconnects = <&pcie_anoc M 4767 interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>,
5772 <&gem_noc MAS 4768 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>;
5773 interconnect-names = "pcie-me 4769 interconnect-names = "pcie-mem", "cpu-pcie";
5774 4770
5775 dma-coherent; 4771 dma-coherent;
5776 iommus = <&pcie_smmu 0x80 0x7 4772 iommus = <&pcie_smmu 0x80 0x7f>;
5777 resets = <&gcc GCC_PCIE_1_BCR 4773 resets = <&gcc GCC_PCIE_1_BCR>;
5778 reset-names = "core"; 4774 reset-names = "core";
5779 power-domains = <&gcc PCIE_1_ 4775 power-domains = <&gcc PCIE_1_GDSC>;
5780 phys = <&pcie1_phy>; 4776 phys = <&pcie1_phy>;
5781 phy-names = "pciephy"; 4777 phy-names = "pciephy";
5782 max-link-speed = <3>; /* FIXM 4778 max-link-speed = <3>; /* FIXME: Limiting the Gen speed due to stability issues */
5783 num-lanes = <4>; 4779 num-lanes = <4>;
5784 4780
5785 status = "disabled"; 4781 status = "disabled";
5786 }; 4782 };
5787 4783
5788 pcie1_phy: phy@1c14000 { 4784 pcie1_phy: phy@1c14000 {
5789 compatible = "qcom,sa8775p-qm 4785 compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy";
5790 reg = <0x0 0x1c14000 0x0 0x40 4786 reg = <0x0 0x1c14000 0x0 0x4000>;
5791 4787
5792 clocks = <&gcc GCC_PCIE_1_AUX 4788 clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
5793 <&gcc GCC_PCIE_1_CFG 4789 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
5794 <&gcc GCC_PCIE_CLKRE 4790 <&gcc GCC_PCIE_CLKREF_EN>,
5795 <&gcc GCC_PCIE_1_PHY 4791 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
5796 <&gcc GCC_PCIE_1_PIP 4792 <&gcc GCC_PCIE_1_PIPE_CLK>,
5797 <&gcc GCC_PCIE_1_PIP 4793 <&gcc GCC_PCIE_1_PIPEDIV2_CLK>,
5798 <&gcc GCC_PCIE_1_PHY 4794 <&gcc GCC_PCIE_1_PHY_AUX_CLK>;
5799 4795
5800 clock-names = "aux", "cfg_ahb 4796 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe",
5801 "pipediv2", "ph 4797 "pipediv2", "phy_aux";
5802 4798
5803 assigned-clocks = <&gcc GCC_P 4799 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
5804 assigned-clock-rates = <10000 4800 assigned-clock-rates = <100000000>;
5805 4801
5806 resets = <&gcc GCC_PCIE_1_PHY 4802 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
5807 reset-names = "phy"; 4803 reset-names = "phy";
5808 4804
5809 #clock-cells = <0>; 4805 #clock-cells = <0>;
5810 clock-output-names = "pcie_1_ 4806 clock-output-names = "pcie_1_pipe_clk";
5811 4807
5812 #phy-cells = <0>; 4808 #phy-cells = <0>;
5813 4809
5814 status = "disabled"; 4810 status = "disabled";
5815 }; 4811 };
5816 }; 4812 };
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