1 // SPDX-License-Identifier: BSD-3-Clause 1 // SPDX-License-Identifier: BSD-3-Clause
2 /* 2 /*
3 * Copyright (c) 2023, Linaro Limited 3 * Copyright (c) 2023, Linaro Limited
4 */ 4 */
5 5
6 #include <dt-bindings/interconnect/qcom,icc.h> 6 #include <dt-bindings/interconnect/qcom,icc.h>
7 #include <dt-bindings/interrupt-controller/arm 7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/clock/qcom,rpmh.h> 8 #include <dt-bindings/clock/qcom,rpmh.h>
9 #include <dt-bindings/clock/qcom,sa8775p-gcc.h 9 #include <dt-bindings/clock/qcom,sa8775p-gcc.h>
10 #include <dt-bindings/clock/qcom,sa8775p-gpucc 10 #include <dt-bindings/clock/qcom,sa8775p-gpucc.h>
11 #include <dt-bindings/interconnect/qcom,sa8775 11 #include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h>
12 #include <dt-bindings/mailbox/qcom-ipcc.h> 12 #include <dt-bindings/mailbox/qcom-ipcc.h>
13 #include <dt-bindings/firmware/qcom,scm.h> <<
14 #include <dt-bindings/power/qcom,rpmhpd.h> <<
15 #include <dt-bindings/power/qcom-rpmpd.h> 13 #include <dt-bindings/power/qcom-rpmpd.h>
16 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 14 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
17 15
18 / { 16 / {
19 interrupt-parent = <&intc>; 17 interrupt-parent = <&intc>;
20 18
21 #address-cells = <2>; 19 #address-cells = <2>;
22 #size-cells = <2>; 20 #size-cells = <2>;
23 21
24 clocks { 22 clocks {
25 xo_board_clk: xo-board-clk { 23 xo_board_clk: xo-board-clk {
26 compatible = "fixed-cl 24 compatible = "fixed-clock";
27 #clock-cells = <0>; 25 #clock-cells = <0>;
28 }; 26 };
29 27
30 sleep_clk: sleep-clk { 28 sleep_clk: sleep-clk {
31 compatible = "fixed-cl 29 compatible = "fixed-clock";
32 #clock-cells = <0>; 30 #clock-cells = <0>;
33 }; 31 };
34 }; 32 };
35 33
36 cpus { 34 cpus {
37 #address-cells = <2>; 35 #address-cells = <2>;
38 #size-cells = <0>; 36 #size-cells = <0>;
39 37
40 CPU0: cpu@0 { 38 CPU0: cpu@0 {
41 device_type = "cpu"; 39 device_type = "cpu";
42 compatible = "qcom,kry 40 compatible = "qcom,kryo";
43 reg = <0x0 0x0>; 41 reg = <0x0 0x0>;
44 enable-method = "psci" 42 enable-method = "psci";
45 qcom,freq-domain = <&c 43 qcom,freq-domain = <&cpufreq_hw 0>;
46 next-level-cache = <&L 44 next-level-cache = <&L2_0>;
47 capacity-dmips-mhz = < <<
48 dynamic-power-coeffici <<
49 L2_0: l2-cache { 45 L2_0: l2-cache {
50 compatible = " 46 compatible = "cache";
51 cache-level = 47 cache-level = <2>;
52 cache-unified; 48 cache-unified;
53 next-level-cac 49 next-level-cache = <&L3_0>;
54 L3_0: l3-cache 50 L3_0: l3-cache {
55 compat 51 compatible = "cache";
56 cache- 52 cache-level = <3>;
57 cache- 53 cache-unified;
58 }; 54 };
59 }; 55 };
60 }; 56 };
61 57
62 CPU1: cpu@100 { 58 CPU1: cpu@100 {
63 device_type = "cpu"; 59 device_type = "cpu";
64 compatible = "qcom,kry 60 compatible = "qcom,kryo";
65 reg = <0x0 0x100>; 61 reg = <0x0 0x100>;
66 enable-method = "psci" 62 enable-method = "psci";
67 qcom,freq-domain = <&c 63 qcom,freq-domain = <&cpufreq_hw 0>;
68 next-level-cache = <&L 64 next-level-cache = <&L2_1>;
69 capacity-dmips-mhz = < <<
70 dynamic-power-coeffici <<
71 L2_1: l2-cache { 65 L2_1: l2-cache {
72 compatible = " 66 compatible = "cache";
73 cache-level = 67 cache-level = <2>;
74 cache-unified; 68 cache-unified;
75 next-level-cac 69 next-level-cache = <&L3_0>;
76 }; 70 };
77 }; 71 };
78 72
79 CPU2: cpu@200 { 73 CPU2: cpu@200 {
80 device_type = "cpu"; 74 device_type = "cpu";
81 compatible = "qcom,kry 75 compatible = "qcom,kryo";
82 reg = <0x0 0x200>; 76 reg = <0x0 0x200>;
83 enable-method = "psci" 77 enable-method = "psci";
84 qcom,freq-domain = <&c 78 qcom,freq-domain = <&cpufreq_hw 0>;
85 next-level-cache = <&L 79 next-level-cache = <&L2_2>;
86 capacity-dmips-mhz = < <<
87 dynamic-power-coeffici <<
88 L2_2: l2-cache { 80 L2_2: l2-cache {
89 compatible = " 81 compatible = "cache";
90 cache-level = 82 cache-level = <2>;
91 cache-unified; 83 cache-unified;
92 next-level-cac 84 next-level-cache = <&L3_0>;
93 }; 85 };
94 }; 86 };
95 87
96 CPU3: cpu@300 { 88 CPU3: cpu@300 {
97 device_type = "cpu"; 89 device_type = "cpu";
98 compatible = "qcom,kry 90 compatible = "qcom,kryo";
99 reg = <0x0 0x300>; 91 reg = <0x0 0x300>;
100 enable-method = "psci" 92 enable-method = "psci";
101 qcom,freq-domain = <&c 93 qcom,freq-domain = <&cpufreq_hw 0>;
102 next-level-cache = <&L 94 next-level-cache = <&L2_3>;
103 capacity-dmips-mhz = < <<
104 dynamic-power-coeffici <<
105 L2_3: l2-cache { 95 L2_3: l2-cache {
106 compatible = " 96 compatible = "cache";
107 cache-level = 97 cache-level = <2>;
108 cache-unified; 98 cache-unified;
109 next-level-cac 99 next-level-cache = <&L3_0>;
110 }; 100 };
111 }; 101 };
112 102
113 CPU4: cpu@10000 { 103 CPU4: cpu@10000 {
114 device_type = "cpu"; 104 device_type = "cpu";
115 compatible = "qcom,kry 105 compatible = "qcom,kryo";
116 reg = <0x0 0x10000>; 106 reg = <0x0 0x10000>;
117 enable-method = "psci" 107 enable-method = "psci";
118 qcom,freq-domain = <&c 108 qcom,freq-domain = <&cpufreq_hw 1>;
119 next-level-cache = <&L 109 next-level-cache = <&L2_4>;
120 capacity-dmips-mhz = < <<
121 dynamic-power-coeffici <<
122 L2_4: l2-cache { 110 L2_4: l2-cache {
123 compatible = " 111 compatible = "cache";
124 cache-level = 112 cache-level = <2>;
125 cache-unified; 113 cache-unified;
126 next-level-cac 114 next-level-cache = <&L3_1>;
127 L3_1: l3-cache 115 L3_1: l3-cache {
128 compat 116 compatible = "cache";
129 cache- 117 cache-level = <3>;
130 cache- 118 cache-unified;
131 }; 119 };
132 120
133 }; 121 };
134 }; 122 };
135 123
136 CPU5: cpu@10100 { 124 CPU5: cpu@10100 {
137 device_type = "cpu"; 125 device_type = "cpu";
138 compatible = "qcom,kry 126 compatible = "qcom,kryo";
139 reg = <0x0 0x10100>; 127 reg = <0x0 0x10100>;
140 enable-method = "psci" 128 enable-method = "psci";
141 qcom,freq-domain = <&c 129 qcom,freq-domain = <&cpufreq_hw 1>;
142 next-level-cache = <&L 130 next-level-cache = <&L2_5>;
143 capacity-dmips-mhz = < <<
144 dynamic-power-coeffici <<
145 L2_5: l2-cache { 131 L2_5: l2-cache {
146 compatible = " 132 compatible = "cache";
147 cache-level = 133 cache-level = <2>;
148 cache-unified; 134 cache-unified;
149 next-level-cac 135 next-level-cache = <&L3_1>;
150 }; 136 };
151 }; 137 };
152 138
153 CPU6: cpu@10200 { 139 CPU6: cpu@10200 {
154 device_type = "cpu"; 140 device_type = "cpu";
155 compatible = "qcom,kry 141 compatible = "qcom,kryo";
156 reg = <0x0 0x10200>; 142 reg = <0x0 0x10200>;
157 enable-method = "psci" 143 enable-method = "psci";
158 qcom,freq-domain = <&c 144 qcom,freq-domain = <&cpufreq_hw 1>;
159 next-level-cache = <&L 145 next-level-cache = <&L2_6>;
160 capacity-dmips-mhz = < <<
161 dynamic-power-coeffici <<
162 L2_6: l2-cache { 146 L2_6: l2-cache {
163 compatible = " 147 compatible = "cache";
164 cache-level = 148 cache-level = <2>;
165 cache-unified; 149 cache-unified;
166 next-level-cac 150 next-level-cache = <&L3_1>;
167 }; 151 };
168 }; 152 };
169 153
170 CPU7: cpu@10300 { 154 CPU7: cpu@10300 {
171 device_type = "cpu"; 155 device_type = "cpu";
172 compatible = "qcom,kry 156 compatible = "qcom,kryo";
173 reg = <0x0 0x10300>; 157 reg = <0x0 0x10300>;
174 enable-method = "psci" 158 enable-method = "psci";
175 qcom,freq-domain = <&c 159 qcom,freq-domain = <&cpufreq_hw 1>;
176 next-level-cache = <&L 160 next-level-cache = <&L2_7>;
177 capacity-dmips-mhz = < <<
178 dynamic-power-coeffici <<
179 L2_7: l2-cache { 161 L2_7: l2-cache {
180 compatible = " 162 compatible = "cache";
181 cache-level = 163 cache-level = <2>;
182 cache-unified; 164 cache-unified;
183 next-level-cac 165 next-level-cache = <&L3_1>;
184 }; 166 };
185 }; 167 };
186 168
187 cpu-map { 169 cpu-map {
188 cluster0 { 170 cluster0 {
189 core0 { 171 core0 {
190 cpu = 172 cpu = <&CPU0>;
191 }; 173 };
192 174
193 core1 { 175 core1 {
194 cpu = 176 cpu = <&CPU1>;
195 }; 177 };
196 178
197 core2 { 179 core2 {
198 cpu = 180 cpu = <&CPU2>;
199 }; 181 };
200 182
201 core3 { 183 core3 {
202 cpu = 184 cpu = <&CPU3>;
203 }; 185 };
204 }; 186 };
205 187
206 cluster1 { 188 cluster1 {
207 core0 { 189 core0 {
208 cpu = 190 cpu = <&CPU4>;
209 }; 191 };
210 192
211 core1 { 193 core1 {
212 cpu = 194 cpu = <&CPU5>;
213 }; 195 };
214 196
215 core2 { 197 core2 {
216 cpu = 198 cpu = <&CPU6>;
217 }; 199 };
218 200
219 core3 { 201 core3 {
220 cpu = 202 cpu = <&CPU7>;
221 }; 203 };
222 }; 204 };
223 }; 205 };
224 <<
225 idle-states { <<
226 entry-method = "psci"; <<
227 <<
228 GOLD_CPU_SLEEP_0: cpu- <<
229 compatible = " <<
230 idle-state-nam <<
231 arm,psci-suspe <<
232 entry-latency- <<
233 exit-latency-u <<
234 min-residency- <<
235 local-timer-st <<
236 }; <<
237 <<
238 GOLD_RAIL_CPU_SLEEP_0: <<
239 compatible = " <<
240 idle-state-nam <<
241 arm,psci-suspe <<
242 entry-latency- <<
243 exit-latency-u <<
244 min-residency- <<
245 local-timer-st <<
246 }; <<
247 }; <<
248 <<
249 domain-idle-states { <<
250 CLUSTER_SLEEP_GOLD: cl <<
251 compatible = " <<
252 arm,psci-suspe <<
253 entry-latency- <<
254 exit-latency-u <<
255 min-residency- <<
256 }; <<
257 <<
258 CLUSTER_SLEEP_APSS_RSC <<
259 compatible = " <<
260 arm,psci-suspe <<
261 entry-latency- <<
262 exit-latency-u <<
263 min-residency- <<
264 }; <<
265 }; <<
266 }; <<
267 <<
268 dummy-sink { <<
269 compatible = "arm,coresight-du <<
270 <<
271 in-ports { <<
272 port { <<
273 eud_in: endpoi <<
274 remote <<
275 <&swao <<
276 }; <<
277 }; <<
278 }; <<
279 }; 206 };
280 207
281 firmware { 208 firmware {
282 scm { 209 scm {
283 compatible = "qcom,scm 210 compatible = "qcom,scm-sa8775p", "qcom,scm";
284 memory-region = <&tz_f <<
285 }; 211 };
286 }; 212 };
287 213
288 aggre1_noc: interconnect-aggre1-noc { 214 aggre1_noc: interconnect-aggre1-noc {
289 compatible = "qcom,sa8775p-agg 215 compatible = "qcom,sa8775p-aggre1-noc";
290 #interconnect-cells = <2>; 216 #interconnect-cells = <2>;
291 qcom,bcm-voters = <&apps_bcm_v 217 qcom,bcm-voters = <&apps_bcm_voter>;
292 }; 218 };
293 219
294 aggre2_noc: interconnect-aggre2-noc { 220 aggre2_noc: interconnect-aggre2-noc {
295 compatible = "qcom,sa8775p-agg 221 compatible = "qcom,sa8775p-aggre2-noc";
296 #interconnect-cells = <2>; 222 #interconnect-cells = <2>;
297 qcom,bcm-voters = <&apps_bcm_v 223 qcom,bcm-voters = <&apps_bcm_voter>;
298 }; 224 };
299 225
300 clk_virt: interconnect-clk-virt { 226 clk_virt: interconnect-clk-virt {
301 compatible = "qcom,sa8775p-clk 227 compatible = "qcom,sa8775p-clk-virt";
302 #interconnect-cells = <2>; 228 #interconnect-cells = <2>;
303 qcom,bcm-voters = <&apps_bcm_v 229 qcom,bcm-voters = <&apps_bcm_voter>;
304 }; 230 };
305 231
306 config_noc: interconnect-config-noc { 232 config_noc: interconnect-config-noc {
307 compatible = "qcom,sa8775p-con 233 compatible = "qcom,sa8775p-config-noc";
308 #interconnect-cells = <2>; 234 #interconnect-cells = <2>;
309 qcom,bcm-voters = <&apps_bcm_v 235 qcom,bcm-voters = <&apps_bcm_voter>;
310 }; 236 };
311 237
312 dc_noc: interconnect-dc-noc { 238 dc_noc: interconnect-dc-noc {
313 compatible = "qcom,sa8775p-dc- 239 compatible = "qcom,sa8775p-dc-noc";
314 #interconnect-cells = <2>; 240 #interconnect-cells = <2>;
315 qcom,bcm-voters = <&apps_bcm_v 241 qcom,bcm-voters = <&apps_bcm_voter>;
316 }; 242 };
317 243
318 gem_noc: interconnect-gem-noc { 244 gem_noc: interconnect-gem-noc {
319 compatible = "qcom,sa8775p-gem 245 compatible = "qcom,sa8775p-gem-noc";
320 #interconnect-cells = <2>; 246 #interconnect-cells = <2>;
321 qcom,bcm-voters = <&apps_bcm_v 247 qcom,bcm-voters = <&apps_bcm_voter>;
322 }; 248 };
323 249
324 gpdsp_anoc: interconnect-gpdsp-anoc { 250 gpdsp_anoc: interconnect-gpdsp-anoc {
325 compatible = "qcom,sa8775p-gpd 251 compatible = "qcom,sa8775p-gpdsp-anoc";
326 #interconnect-cells = <2>; 252 #interconnect-cells = <2>;
327 qcom,bcm-voters = <&apps_bcm_v 253 qcom,bcm-voters = <&apps_bcm_voter>;
328 }; 254 };
329 255
330 lpass_ag_noc: interconnect-lpass-ag-no 256 lpass_ag_noc: interconnect-lpass-ag-noc {
331 compatible = "qcom,sa8775p-lpa 257 compatible = "qcom,sa8775p-lpass-ag-noc";
332 #interconnect-cells = <2>; 258 #interconnect-cells = <2>;
333 qcom,bcm-voters = <&apps_bcm_v 259 qcom,bcm-voters = <&apps_bcm_voter>;
334 }; 260 };
335 261
336 mc_virt: interconnect-mc-virt { 262 mc_virt: interconnect-mc-virt {
337 compatible = "qcom,sa8775p-mc- 263 compatible = "qcom,sa8775p-mc-virt";
338 #interconnect-cells = <2>; 264 #interconnect-cells = <2>;
339 qcom,bcm-voters = <&apps_bcm_v 265 qcom,bcm-voters = <&apps_bcm_voter>;
340 }; 266 };
341 267
342 mmss_noc: interconnect-mmss-noc { 268 mmss_noc: interconnect-mmss-noc {
343 compatible = "qcom,sa8775p-mms 269 compatible = "qcom,sa8775p-mmss-noc";
344 #interconnect-cells = <2>; 270 #interconnect-cells = <2>;
345 qcom,bcm-voters = <&apps_bcm_v 271 qcom,bcm-voters = <&apps_bcm_voter>;
346 }; 272 };
347 273
348 nspa_noc: interconnect-nspa-noc { 274 nspa_noc: interconnect-nspa-noc {
349 compatible = "qcom,sa8775p-nsp 275 compatible = "qcom,sa8775p-nspa-noc";
350 #interconnect-cells = <2>; 276 #interconnect-cells = <2>;
351 qcom,bcm-voters = <&apps_bcm_v 277 qcom,bcm-voters = <&apps_bcm_voter>;
352 }; 278 };
353 279
354 nspb_noc: interconnect-nspb-noc { 280 nspb_noc: interconnect-nspb-noc {
355 compatible = "qcom,sa8775p-nsp 281 compatible = "qcom,sa8775p-nspb-noc";
356 #interconnect-cells = <2>; 282 #interconnect-cells = <2>;
357 qcom,bcm-voters = <&apps_bcm_v 283 qcom,bcm-voters = <&apps_bcm_voter>;
358 }; 284 };
359 285
360 pcie_anoc: interconnect-pcie-anoc { 286 pcie_anoc: interconnect-pcie-anoc {
361 compatible = "qcom,sa8775p-pci 287 compatible = "qcom,sa8775p-pcie-anoc";
362 #interconnect-cells = <2>; 288 #interconnect-cells = <2>;
363 qcom,bcm-voters = <&apps_bcm_v 289 qcom,bcm-voters = <&apps_bcm_voter>;
364 }; 290 };
365 291
366 system_noc: interconnect-system-noc { 292 system_noc: interconnect-system-noc {
367 compatible = "qcom,sa8775p-sys 293 compatible = "qcom,sa8775p-system-noc";
368 #interconnect-cells = <2>; 294 #interconnect-cells = <2>;
369 qcom,bcm-voters = <&apps_bcm_v 295 qcom,bcm-voters = <&apps_bcm_voter>;
370 }; 296 };
371 297
372 /* Will be updated by the bootloader. 298 /* Will be updated by the bootloader. */
373 memory@80000000 { 299 memory@80000000 {
374 device_type = "memory"; 300 device_type = "memory";
375 reg = <0x0 0x80000000 0x0 0x0> 301 reg = <0x0 0x80000000 0x0 0x0>;
376 }; 302 };
377 303
378 qup_opp_table_100mhz: opp-table-qup100 304 qup_opp_table_100mhz: opp-table-qup100mhz {
379 compatible = "operating-points 305 compatible = "operating-points-v2";
380 306
381 opp-100000000 { 307 opp-100000000 {
382 opp-hz = /bits/ 64 <10 308 opp-hz = /bits/ 64 <100000000>;
383 required-opps = <&rpmh 309 required-opps = <&rpmhpd_opp_svs_l1>;
384 }; 310 };
385 }; 311 };
386 312
387 pmu { 313 pmu {
388 compatible = "arm,armv8-pmuv3" 314 compatible = "arm,armv8-pmuv3";
389 interrupts = <GIC_PPI 7 IRQ_TY 315 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
390 }; 316 };
391 317
392 psci { 318 psci {
393 compatible = "arm,psci-1.0"; 319 compatible = "arm,psci-1.0";
394 method = "smc"; 320 method = "smc";
395 <<
396 CPU_PD0: power-domain-cpu0 { <<
397 #power-domain-cells = <<
398 power-domains = <&CLUS <<
399 domain-idle-states = < <<
400 < <<
401 }; <<
402 <<
403 CPU_PD1: power-domain-cpu1 { <<
404 #power-domain-cells = <<
405 power-domains = <&CLUS <<
406 domain-idle-states = < <<
407 < <<
408 }; <<
409 <<
410 CPU_PD2: power-domain-cpu2 { <<
411 #power-domain-cells = <<
412 power-domains = <&CLUS <<
413 domain-idle-states = < <<
414 < <<
415 }; <<
416 <<
417 CPU_PD3: power-domain-cpu3 { <<
418 #power-domain-cells = <<
419 power-domains = <&CLUS <<
420 domain-idle-states = < <<
421 < <<
422 }; <<
423 <<
424 CPU_PD4: power-domain-cpu4 { <<
425 #power-domain-cells = <<
426 power-domains = <&CLUS <<
427 domain-idle-states = < <<
428 < <<
429 }; <<
430 <<
431 CPU_PD5: power-domain-cpu5 { <<
432 #power-domain-cells = <<
433 power-domains = <&CLUS <<
434 domain-idle-states = < <<
435 < <<
436 }; <<
437 <<
438 CPU_PD6: power-domain-cpu6 { <<
439 #power-domain-cells = <<
440 power-domains = <&CLUS <<
441 domain-idle-states = < <<
442 < <<
443 }; <<
444 <<
445 CPU_PD7: power-domain-cpu7 { <<
446 #power-domain-cells = <<
447 power-domains = <&CLUS <<
448 domain-idle-states = < <<
449 < <<
450 }; <<
451 <<
452 CLUSTER_0_PD: power-domain-clu <<
453 #power-domain-cells = <<
454 power-domains = <&CLUS <<
455 domain-idle-states = < <<
456 }; <<
457 <<
458 CLUSTER_1_PD: power-domain-clu <<
459 #power-domain-cells = <<
460 power-domains = <&CLUS <<
461 domain-idle-states = < <<
462 }; <<
463 <<
464 CLUSTER_2_PD: power-domain-clu <<
465 #power-domain-cells = <<
466 domain-idle-states = < <<
467 }; <<
468 }; 321 };
469 322
470 reserved-memory { 323 reserved-memory {
471 #address-cells = <2>; 324 #address-cells = <2>;
472 #size-cells = <2>; 325 #size-cells = <2>;
473 ranges; 326 ranges;
474 327
475 sail_ss_mem: sail-ss@80000000 328 sail_ss_mem: sail-ss@80000000 {
476 reg = <0x0 0x80000000 329 reg = <0x0 0x80000000 0x0 0x10000000>;
477 no-map; 330 no-map;
478 }; 331 };
479 332
480 hyp_mem: hyp@90000000 { 333 hyp_mem: hyp@90000000 {
481 reg = <0x0 0x90000000 334 reg = <0x0 0x90000000 0x0 0x600000>;
482 no-map; 335 no-map;
483 }; 336 };
484 337
485 xbl_boot_mem: xbl-boot@9060000 338 xbl_boot_mem: xbl-boot@90600000 {
486 reg = <0x0 0x90600000 339 reg = <0x0 0x90600000 0x0 0x200000>;
487 no-map; 340 no-map;
488 }; 341 };
489 342
490 aop_image_mem: aop-image@90800 343 aop_image_mem: aop-image@90800000 {
491 reg = <0x0 0x90800000 344 reg = <0x0 0x90800000 0x0 0x60000>;
492 no-map; 345 no-map;
493 }; 346 };
494 347
495 aop_cmd_db_mem: aop-cmd-db@908 348 aop_cmd_db_mem: aop-cmd-db@90860000 {
496 compatible = "qcom,cmd 349 compatible = "qcom,cmd-db";
497 reg = <0x0 0x90860000 350 reg = <0x0 0x90860000 0x0 0x20000>;
498 no-map; 351 no-map;
499 }; 352 };
500 353
501 uefi_log: uefi-log@908b0000 { 354 uefi_log: uefi-log@908b0000 {
502 reg = <0x0 0x908b0000 355 reg = <0x0 0x908b0000 0x0 0x10000>;
503 no-map; 356 no-map;
504 }; 357 };
505 358
506 ddr_training_checksum: ddr-tra <<
507 reg = <0x0 0x908c0000 <<
508 no-map; <<
509 }; <<
510 <<
511 reserved_mem: reserved@908f000 359 reserved_mem: reserved@908f0000 {
512 reg = <0x0 0x908f0000 !! 360 reg = <0x0 0x908f0000 0x0 0xf000>;
513 no-map; 361 no-map;
514 }; 362 };
515 363
516 secdata_apss_mem: secdata-apss !! 364 secdata_apss_mem: secdata-apss@908ff000 {
517 reg = <0x0 0x908fe000 !! 365 reg = <0x0 0x908ff000 0x0 0x1000>;
518 no-map; 366 no-map;
519 }; 367 };
520 368
521 smem_mem: smem@90900000 { 369 smem_mem: smem@90900000 {
522 compatible = "qcom,sme 370 compatible = "qcom,smem";
523 reg = <0x0 0x90900000 371 reg = <0x0 0x90900000 0x0 0x200000>;
524 no-map; 372 no-map;
525 hwlocks = <&tcsr_mutex 373 hwlocks = <&tcsr_mutex 3>;
526 }; 374 };
527 375
528 tz_sail_mailbox_mem: tz-sail-m !! 376 cpucp_fw_mem: cpucp-fw@90b00000 {
529 reg = <0x0 0x90c00000 !! 377 reg = <0x0 0x90b00000 0x0 0x100000>;
530 no-map; <<
531 }; <<
532 <<
533 sail_mailbox_mem: sail-ss@90d0 <<
534 reg = <0x0 0x90d00000 <<
535 no-map; <<
536 }; <<
537 <<
538 sail_ota_mem: sail-ss@90e00000 <<
539 reg = <0x0 0x90e00000 <<
540 no-map; <<
541 }; <<
542 <<
543 aoss_backup_mem: aoss-backup@9 <<
544 reg = <0x0 0x91b00000 <<
545 no-map; <<
546 }; <<
547 <<
548 cpucp_backup_mem: cpucp-backup <<
549 reg = <0x0 0x91b40000 <<
550 no-map; <<
551 }; <<
552 <<
553 tz_config_backup_mem: tz-confi <<
554 reg = <0x0 0x91b80000 <<
555 no-map; <<
556 }; <<
557 <<
558 ddr_training_data_mem: ddr-tra <<
559 reg = <0x0 0x91b90000 <<
560 no-map; <<
561 }; <<
562 <<
563 cdt_data_backup_mem: cdt-data- <<
564 reg = <0x0 0x91ba0000 <<
565 no-map; <<
566 }; <<
567 <<
568 tz_ffi_mem: tz-ffi@91c00000 { <<
569 compatible = "shared-d <<
570 reg = <0x0 0x91c00000 <<
571 no-map; 378 no-map;
572 }; 379 };
573 380
574 lpass_machine_learning_mem: lp 381 lpass_machine_learning_mem: lpass-machine-learning@93b00000 {
575 reg = <0x0 0x93b00000 382 reg = <0x0 0x93b00000 0x0 0xf00000>;
576 no-map; 383 no-map;
577 }; 384 };
578 385
579 adsp_rpc_remote_heap_mem: adsp 386 adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@94a00000 {
580 reg = <0x0 0x94a00000 387 reg = <0x0 0x94a00000 0x0 0x800000>;
581 no-map; 388 no-map;
582 }; 389 };
583 390
584 pil_camera_mem: pil-camera@952 391 pil_camera_mem: pil-camera@95200000 {
585 reg = <0x0 0x95200000 392 reg = <0x0 0x95200000 0x0 0x500000>;
586 no-map; 393 no-map;
587 }; 394 };
588 395
589 pil_adsp_mem: pil-adsp@95c0000 396 pil_adsp_mem: pil-adsp@95c00000 {
590 reg = <0x0 0x95c00000 397 reg = <0x0 0x95c00000 0x0 0x1e00000>;
591 no-map; 398 no-map;
592 }; 399 };
593 400
594 pil_gdsp0_mem: pil-gdsp0@97b00 401 pil_gdsp0_mem: pil-gdsp0@97b00000 {
595 reg = <0x0 0x97b00000 402 reg = <0x0 0x97b00000 0x0 0x1e00000>;
596 no-map; 403 no-map;
597 }; 404 };
598 405
599 pil_gdsp1_mem: pil-gdsp1@99900 406 pil_gdsp1_mem: pil-gdsp1@99900000 {
600 reg = <0x0 0x99900000 407 reg = <0x0 0x99900000 0x0 0x1e00000>;
601 no-map; 408 no-map;
602 }; 409 };
603 410
604 pil_cdsp0_mem: pil-cdsp0@9b800 411 pil_cdsp0_mem: pil-cdsp0@9b800000 {
605 reg = <0x0 0x9b800000 412 reg = <0x0 0x9b800000 0x0 0x1e00000>;
606 no-map; 413 no-map;
607 }; 414 };
608 415
609 pil_gpu_mem: pil-gpu@9d600000 416 pil_gpu_mem: pil-gpu@9d600000 {
610 reg = <0x0 0x9d600000 417 reg = <0x0 0x9d600000 0x0 0x2000>;
611 no-map; 418 no-map;
612 }; 419 };
613 420
614 pil_cdsp1_mem: pil-cdsp1@9d700 421 pil_cdsp1_mem: pil-cdsp1@9d700000 {
615 reg = <0x0 0x9d700000 422 reg = <0x0 0x9d700000 0x0 0x1e00000>;
616 no-map; 423 no-map;
617 }; 424 };
618 425
619 pil_cvp_mem: pil-cvp@9f500000 426 pil_cvp_mem: pil-cvp@9f500000 {
620 reg = <0x0 0x9f500000 427 reg = <0x0 0x9f500000 0x0 0x700000>;
621 no-map; 428 no-map;
622 }; 429 };
623 430
624 pil_video_mem: pil-video@9fc00 431 pil_video_mem: pil-video@9fc00000 {
625 reg = <0x0 0x9fc00000 432 reg = <0x0 0x9fc00000 0x0 0x700000>;
626 no-map; 433 no-map;
627 }; 434 };
628 435
629 audio_mdf_mem: audio-mdf-regio <<
630 reg = <0x0 0xae000000 <<
631 no-map; <<
632 }; <<
633 <<
634 firmware_mem: firmware-region@ <<
635 reg = <0x0 0xb0000000 <<
636 no-map; <<
637 }; <<
638 <<
639 hyptz_reserved_mem: hyptz-rese 436 hyptz_reserved_mem: hyptz-reserved@beb00000 {
640 reg = <0x0 0xbeb00000 437 reg = <0x0 0xbeb00000 0x0 0x11500000>;
641 no-map; 438 no-map;
642 }; 439 };
643 440
644 scmi_mem: scmi-region@d0000000 !! 441 tz_stat_mem: tz-stat@d0000000 {
645 reg = <0x0 0xd0000000 !! 442 reg = <0x0 0xd0000000 0x0 0x100000>;
646 no-map; <<
647 }; <<
648 <<
649 firmware_logs_mem: firmware-lo <<
650 reg = <0x0 0xd0040000 <<
651 no-map; <<
652 }; <<
653 <<
654 firmware_audio_mem: firmware-a <<
655 reg = <0x0 0xd0050000 <<
656 no-map; <<
657 }; <<
658 <<
659 firmware_reserved_mem: firmwar <<
660 reg = <0x0 0xd0054000 <<
661 no-map; <<
662 }; <<
663 <<
664 firmware_quantum_test_mem: fir <<
665 reg = <0x0 0xd00f0000 <<
666 no-map; 443 no-map;
667 }; 444 };
668 445
669 tags_mem: tags@d0100000 { 446 tags_mem: tags@d0100000 {
670 reg = <0x0 0xd0100000 447 reg = <0x0 0xd0100000 0x0 0x1200000>;
671 no-map; 448 no-map;
672 }; 449 };
673 450
674 qtee_mem: qtee@d1300000 { 451 qtee_mem: qtee@d1300000 {
675 reg = <0x0 0xd1300000 452 reg = <0x0 0xd1300000 0x0 0x500000>;
676 no-map; 453 no-map;
677 }; 454 };
678 455
679 deepsleep_backup_mem: deepslee !! 456 trusted_apps_mem: trusted-apps@d1800000 {
680 reg = <0x0 0xd1800000 !! 457 reg = <0x0 0xd1800000 0x0 0x3900000>;
681 no-map; <<
682 }; <<
683 <<
684 trusted_apps_mem: trusted-apps <<
685 reg = <0x0 0xd1900000 <<
686 no-map; 458 no-map;
687 }; 459 };
688 <<
689 tz_stat_mem: tz-stat@db100000 <<
690 reg = <0x0 0xdb100000 <<
691 no-map; <<
692 }; <<
693 <<
694 cpucp_fw_mem: cpucp-fw@db20000 <<
695 reg = <0x0 0xdb200000 <<
696 no-map; <<
697 }; <<
698 }; <<
699 <<
700 smp2p-adsp { <<
701 compatible = "qcom,smp2p"; <<
702 qcom,smem = <443>, <429>; <<
703 interrupts-extended = <&ipcc I <<
704 I <<
705 I <<
706 mboxes = <&ipcc IPCC_CLIENT_LP <<
707 <<
708 qcom,local-pid = <0>; <<
709 qcom,remote-pid = <2>; <<
710 <<
711 smp2p_adsp_out: master-kernel <<
712 qcom,entry-name = "mas <<
713 #qcom,smem-state-cells <<
714 }; <<
715 <<
716 smp2p_adsp_in: slave-kernel { <<
717 qcom,entry-name = "sla <<
718 interrupt-controller; <<
719 #interrupt-cells = <2> <<
720 }; <<
721 }; <<
722 <<
723 smp2p-cdsp0 { <<
724 compatible = "qcom,smp2p"; <<
725 qcom,smem = <94>, <432>; <<
726 interrupts-extended = <&ipcc I <<
727 I <<
728 I <<
729 mboxes = <&ipcc IPCC_CLIENT_CD <<
730 <<
731 qcom,local-pid = <0>; <<
732 qcom,remote-pid = <5>; <<
733 <<
734 smp2p_cdsp0_out: master-kernel <<
735 qcom,entry-name = "mas <<
736 #qcom,smem-state-cells <<
737 }; <<
738 <<
739 smp2p_cdsp0_in: slave-kernel { <<
740 qcom,entry-name = "sla <<
741 interrupt-controller; <<
742 #interrupt-cells = <2> <<
743 }; <<
744 }; <<
745 <<
746 smp2p-cdsp1 { <<
747 compatible = "qcom,smp2p"; <<
748 qcom,smem = <617>, <616>; <<
749 interrupts-extended = <&ipcc I <<
750 I <<
751 I <<
752 mboxes = <&ipcc IPCC_CLIENT_NS <<
753 <<
754 qcom,local-pid = <0>; <<
755 qcom,remote-pid = <12>; <<
756 <<
757 smp2p_cdsp1_out: master-kernel <<
758 qcom,entry-name = "mas <<
759 #qcom,smem-state-cells <<
760 }; <<
761 <<
762 smp2p_cdsp1_in: slave-kernel { <<
763 qcom,entry-name = "sla <<
764 interrupt-controller; <<
765 #interrupt-cells = <2> <<
766 }; <<
767 }; <<
768 <<
769 smp2p-gpdsp0 { <<
770 compatible = "qcom,smp2p"; <<
771 qcom,smem = <617>, <616>; <<
772 interrupts-extended = <&ipcc I <<
773 I <<
774 I <<
775 mboxes = <&ipcc IPCC_CLIENT_GP <<
776 <<
777 qcom,local-pid = <0>; <<
778 qcom,remote-pid = <17>; <<
779 <<
780 smp2p_gpdsp0_out: master-kerne <<
781 qcom,entry-name = "mas <<
782 #qcom,smem-state-cells <<
783 }; <<
784 <<
785 smp2p_gpdsp0_in: slave-kernel <<
786 qcom,entry-name = "sla <<
787 interrupt-controller; <<
788 #interrupt-cells = <2> <<
789 }; <<
790 }; <<
791 <<
792 smp2p-gpdsp1 { <<
793 compatible = "qcom,smp2p"; <<
794 qcom,smem = <617>, <616>; <<
795 interrupts-extended = <&ipcc I <<
796 I <<
797 I <<
798 mboxes = <&ipcc IPCC_CLIENT_GP <<
799 <<
800 qcom,local-pid = <0>; <<
801 qcom,remote-pid = <18>; <<
802 <<
803 smp2p_gpdsp1_out: master-kerne <<
804 qcom,entry-name = "mas <<
805 #qcom,smem-state-cells <<
806 }; <<
807 <<
808 smp2p_gpdsp1_in: slave-kernel <<
809 qcom,entry-name = "sla <<
810 interrupt-controller; <<
811 #interrupt-cells = <2> <<
812 }; <<
813 }; 460 };
814 461
815 soc: soc@0 { 462 soc: soc@0 {
816 compatible = "simple-bus"; 463 compatible = "simple-bus";
817 #address-cells = <2>; 464 #address-cells = <2>;
818 #size-cells = <2>; 465 #size-cells = <2>;
819 ranges = <0 0 0 0 0x10 0>; 466 ranges = <0 0 0 0 0x10 0>;
820 467
821 gcc: clock-controller@100000 { 468 gcc: clock-controller@100000 {
822 compatible = "qcom,sa8 469 compatible = "qcom,sa8775p-gcc";
823 reg = <0x0 0x00100000 470 reg = <0x0 0x00100000 0x0 0xc7018>;
824 #clock-cells = <1>; 471 #clock-cells = <1>;
825 #reset-cells = <1>; 472 #reset-cells = <1>;
826 #power-domain-cells = 473 #power-domain-cells = <1>;
827 clocks = <&rpmhcc RPMH 474 clocks = <&rpmhcc RPMH_CXO_CLK>,
828 <&sleep_clk>, 475 <&sleep_clk>,
829 <0>, 476 <0>,
830 <0>, 477 <0>,
831 <0>, 478 <0>,
832 <&usb_0_qmpph 479 <&usb_0_qmpphy>,
833 <&usb_1_qmpph 480 <&usb_1_qmpphy>,
834 <0>, 481 <0>,
835 <0>, 482 <0>,
836 <0>, 483 <0>,
837 <&pcie0_phy>, 484 <&pcie0_phy>,
838 <&pcie1_phy>, 485 <&pcie1_phy>,
839 <0>, 486 <0>,
840 <0>, 487 <0>,
841 <0>; 488 <0>;
842 power-domains = <&rpmh 489 power-domains = <&rpmhpd SA8775P_CX>;
843 }; 490 };
844 491
845 ipcc: mailbox@408000 { 492 ipcc: mailbox@408000 {
846 compatible = "qcom,sa8 493 compatible = "qcom,sa8775p-ipcc", "qcom,ipcc";
847 reg = <0x0 0x00408000 494 reg = <0x0 0x00408000 0x0 0x1000>;
848 interrupts = <GIC_SPI 495 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
849 interrupt-controller; 496 interrupt-controller;
850 #interrupt-cells = <3> 497 #interrupt-cells = <3>;
851 #mbox-cells = <2>; 498 #mbox-cells = <2>;
852 }; 499 };
853 500
854 qupv3_id_2: geniqup@8c0000 { 501 qupv3_id_2: geniqup@8c0000 {
855 compatible = "qcom,gen 502 compatible = "qcom,geni-se-qup";
856 reg = <0x0 0x008c0000 503 reg = <0x0 0x008c0000 0x0 0x6000>;
857 ranges; 504 ranges;
858 clocks = <&gcc GCC_QUP 505 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
859 <&gcc GCC_QUP 506 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
860 clock-names = "m-ahb", 507 clock-names = "m-ahb", "s-ahb";
861 iommus = <&apps_smmu 0 508 iommus = <&apps_smmu 0x5a3 0x0>;
862 #address-cells = <2>; 509 #address-cells = <2>;
863 #size-cells = <2>; 510 #size-cells = <2>;
864 status = "disabled"; 511 status = "disabled";
865 512
866 i2c14: i2c@880000 { 513 i2c14: i2c@880000 {
867 compatible = " 514 compatible = "qcom,geni-i2c";
868 reg = <0x0 0x8 515 reg = <0x0 0x880000 0x0 0x4000>;
869 #address-cells 516 #address-cells = <1>;
870 #size-cells = 517 #size-cells = <0>;
871 interrupts = < 518 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
872 clocks = <&gcc 519 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
873 clock-names = 520 clock-names = "se";
874 interconnects 521 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
875 522 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
876 523 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
877 524 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
878 525 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
879 526 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
880 interconnect-n 527 interconnect-names = "qup-core",
881 528 "qup-config",
882 529 "qup-memory";
883 power-domains 530 power-domains = <&rpmhpd SA8775P_CX>;
884 status = "disa 531 status = "disabled";
885 }; 532 };
886 533
887 spi14: spi@880000 { 534 spi14: spi@880000 {
888 compatible = " 535 compatible = "qcom,geni-spi";
889 reg = <0x0 0x8 536 reg = <0x0 0x880000 0x0 0x4000>;
890 #address-cells 537 #address-cells = <1>;
891 #size-cells = 538 #size-cells = <0>;
892 interrupts = < 539 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
893 clocks = <&gcc 540 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
894 clock-names = 541 clock-names = "se";
895 interconnects 542 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
896 543 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
897 544 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
898 545 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
899 546 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
900 547 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
901 interconnect-n 548 interconnect-names = "qup-core",
902 549 "qup-config",
903 550 "qup-memory";
904 power-domains 551 power-domains = <&rpmhpd SA8775P_CX>;
905 status = "disa 552 status = "disabled";
906 }; 553 };
907 554
908 i2c15: i2c@884000 { 555 i2c15: i2c@884000 {
909 compatible = " 556 compatible = "qcom,geni-i2c";
910 reg = <0x0 0x8 557 reg = <0x0 0x884000 0x0 0x4000>;
911 #address-cells 558 #address-cells = <1>;
912 #size-cells = 559 #size-cells = <0>;
913 interrupts = < 560 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
914 clocks = <&gcc 561 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
915 clock-names = 562 clock-names = "se";
916 interconnects 563 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
917 564 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
918 565 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
919 566 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
920 567 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
921 568 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
922 interconnect-n 569 interconnect-names = "qup-core",
923 570 "qup-config",
924 571 "qup-memory";
925 power-domains 572 power-domains = <&rpmhpd SA8775P_CX>;
926 status = "disa 573 status = "disabled";
927 }; 574 };
928 575
929 spi15: spi@884000 { 576 spi15: spi@884000 {
930 compatible = " 577 compatible = "qcom,geni-spi";
931 reg = <0x0 0x8 578 reg = <0x0 0x884000 0x0 0x4000>;
932 #address-cells 579 #address-cells = <1>;
933 #size-cells = 580 #size-cells = <0>;
934 interrupts = < 581 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
935 clocks = <&gcc 582 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
936 clock-names = 583 clock-names = "se";
937 interconnects 584 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
938 585 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
939 586 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
940 587 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
941 588 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
942 589 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
943 interconnect-n 590 interconnect-names = "qup-core",
944 591 "qup-config",
945 592 "qup-memory";
946 power-domains 593 power-domains = <&rpmhpd SA8775P_CX>;
947 status = "disa 594 status = "disabled";
948 }; 595 };
949 596
950 i2c16: i2c@888000 { 597 i2c16: i2c@888000 {
951 compatible = " 598 compatible = "qcom,geni-i2c";
952 reg = <0x0 0x8 599 reg = <0x0 0x888000 0x0 0x4000>;
953 #address-cells 600 #address-cells = <1>;
954 #size-cells = 601 #size-cells = <0>;
955 interrupts = < 602 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
956 clocks = <&gcc 603 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
957 clock-names = 604 clock-names = "se";
958 interconnects 605 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
959 606 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
960 607 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
961 608 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
962 609 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
963 610 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
964 interconnect-n 611 interconnect-names = "qup-core",
965 612 "qup-config",
966 613 "qup-memory";
967 power-domains 614 power-domains = <&rpmhpd SA8775P_CX>;
968 status = "disa 615 status = "disabled";
969 }; 616 };
970 617
971 spi16: spi@888000 { 618 spi16: spi@888000 {
972 compatible = " 619 compatible = "qcom,geni-spi";
973 reg = <0x0 0x0 620 reg = <0x0 0x00888000 0x0 0x4000>;
974 interrupts = < 621 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
975 clocks = <&gcc 622 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
976 clock-names = 623 clock-names = "se";
977 interconnects 624 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
978 625 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
979 626 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
980 627 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
981 628 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
982 629 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
983 interconnect-n 630 interconnect-names = "qup-core",
984 631 "qup-config",
985 632 "qup-memory";
986 power-domains 633 power-domains = <&rpmhpd SA8775P_CX>;
987 #address-cells 634 #address-cells = <1>;
988 #size-cells = 635 #size-cells = <0>;
989 status = "disa 636 status = "disabled";
990 }; 637 };
991 638
992 i2c17: i2c@88c000 { 639 i2c17: i2c@88c000 {
993 compatible = " 640 compatible = "qcom,geni-i2c";
994 reg = <0x0 0x8 641 reg = <0x0 0x88c000 0x0 0x4000>;
995 #address-cells 642 #address-cells = <1>;
996 #size-cells = 643 #size-cells = <0>;
997 interrupts = < 644 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
998 clocks = <&gcc 645 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
999 clock-names = 646 clock-names = "se";
1000 interconnects 647 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1001 648 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1002 649 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1003 650 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1004 651 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1005 652 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1006 interconnect- 653 interconnect-names = "qup-core",
1007 654 "qup-config",
1008 655 "qup-memory";
1009 power-domains 656 power-domains = <&rpmhpd SA8775P_CX>;
1010 status = "dis 657 status = "disabled";
1011 }; 658 };
1012 659
1013 spi17: spi@88c000 { 660 spi17: spi@88c000 {
1014 compatible = 661 compatible = "qcom,geni-spi";
1015 reg = <0x0 0x 662 reg = <0x0 0x88c000 0x0 0x4000>;
1016 #address-cell 663 #address-cells = <1>;
1017 #size-cells = 664 #size-cells = <0>;
1018 interrupts = 665 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1019 clocks = <&gc 666 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1020 clock-names = 667 clock-names = "se";
1021 interconnects 668 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1022 669 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1023 670 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1024 671 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1025 672 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1026 673 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1027 interconnect- 674 interconnect-names = "qup-core",
1028 675 "qup-config",
1029 676 "qup-memory";
1030 power-domains 677 power-domains = <&rpmhpd SA8775P_CX>;
1031 status = "dis 678 status = "disabled";
1032 }; 679 };
1033 680
1034 uart17: serial@88c000 681 uart17: serial@88c000 {
1035 compatible = 682 compatible = "qcom,geni-uart";
1036 reg = <0x0 0x 683 reg = <0x0 0x0088c000 0x0 0x4000>;
1037 interrupts = 684 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1038 clocks = <&gc 685 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1039 clock-names = 686 clock-names = "se";
1040 interconnects 687 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1041 688 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1042 689 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1043 690 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
1044 interconnect- 691 interconnect-names = "qup-core", "qup-config";
1045 power-domains 692 power-domains = <&rpmhpd SA8775P_CX>;
1046 status = "dis 693 status = "disabled";
1047 }; 694 };
1048 695
1049 i2c18: i2c@890000 { 696 i2c18: i2c@890000 {
1050 compatible = 697 compatible = "qcom,geni-i2c";
1051 reg = <0x0 0x 698 reg = <0x0 0x00890000 0x0 0x4000>;
1052 interrupts = 699 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1053 clocks = <&gc 700 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1054 clock-names = 701 clock-names = "se";
1055 interconnects 702 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1056 703 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1057 704 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1058 705 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1059 706 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1060 707 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1061 interconnect- 708 interconnect-names = "qup-core",
1062 709 "qup-config",
1063 710 "qup-memory";
1064 power-domains 711 power-domains = <&rpmhpd SA8775P_CX>;
1065 #address-cell 712 #address-cells = <1>;
1066 #size-cells = 713 #size-cells = <0>;
1067 status = "dis 714 status = "disabled";
1068 }; 715 };
1069 716
1070 spi18: spi@890000 { 717 spi18: spi@890000 {
1071 compatible = 718 compatible = "qcom,geni-spi";
1072 reg = <0x0 0x 719 reg = <0x0 0x890000 0x0 0x4000>;
1073 #address-cell 720 #address-cells = <1>;
1074 #size-cells = 721 #size-cells = <0>;
1075 interrupts = 722 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1076 clocks = <&gc 723 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1077 clock-names = 724 clock-names = "se";
1078 interconnects 725 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1079 726 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1080 727 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1081 728 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1082 729 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1083 730 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1084 interconnect- 731 interconnect-names = "qup-core",
1085 732 "qup-config",
1086 733 "qup-memory";
1087 power-domains 734 power-domains = <&rpmhpd SA8775P_CX>;
1088 status = "dis 735 status = "disabled";
1089 }; 736 };
1090 737
1091 i2c19: i2c@894000 { 738 i2c19: i2c@894000 {
1092 compatible = 739 compatible = "qcom,geni-i2c";
1093 reg = <0x0 0x 740 reg = <0x0 0x894000 0x0 0x4000>;
1094 #address-cell 741 #address-cells = <1>;
1095 #size-cells = 742 #size-cells = <0>;
1096 interrupts = 743 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1097 clocks = <&gc 744 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1098 clock-names = 745 clock-names = "se";
1099 interconnects 746 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1100 747 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1101 748 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1102 749 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1103 750 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1104 751 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1105 interconnect- 752 interconnect-names = "qup-core",
1106 753 "qup-config",
1107 754 "qup-memory";
1108 power-domains 755 power-domains = <&rpmhpd SA8775P_CX>;
1109 status = "dis 756 status = "disabled";
1110 }; 757 };
1111 758
1112 spi19: spi@894000 { 759 spi19: spi@894000 {
1113 compatible = 760 compatible = "qcom,geni-spi";
1114 reg = <0x0 0x 761 reg = <0x0 0x894000 0x0 0x4000>;
1115 #address-cell 762 #address-cells = <1>;
1116 #size-cells = 763 #size-cells = <0>;
1117 interrupts = 764 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1118 clocks = <&gc 765 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1119 clock-names = 766 clock-names = "se";
1120 interconnects 767 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1121 768 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1122 769 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1123 770 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1124 771 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1125 772 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1126 interconnect- 773 interconnect-names = "qup-core",
1127 774 "qup-config",
1128 775 "qup-memory";
1129 power-domains 776 power-domains = <&rpmhpd SA8775P_CX>;
1130 status = "dis 777 status = "disabled";
1131 }; 778 };
1132 779
1133 i2c20: i2c@898000 { 780 i2c20: i2c@898000 {
1134 compatible = 781 compatible = "qcom,geni-i2c";
1135 reg = <0x0 0x 782 reg = <0x0 0x898000 0x0 0x4000>;
1136 #address-cell 783 #address-cells = <1>;
1137 #size-cells = 784 #size-cells = <0>;
1138 interrupts = 785 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>;
1139 clocks = <&gc 786 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1140 clock-names = 787 clock-names = "se";
1141 interconnects 788 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1142 789 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1143 790 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1144 791 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1145 792 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1146 793 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1147 interconnect- 794 interconnect-names = "qup-core",
1148 795 "qup-config",
1149 796 "qup-memory";
1150 power-domains 797 power-domains = <&rpmhpd SA8775P_CX>;
1151 status = "dis 798 status = "disabled";
1152 }; 799 };
1153 800
1154 spi20: spi@898000 { 801 spi20: spi@898000 {
1155 compatible = 802 compatible = "qcom,geni-spi";
1156 reg = <0x0 0x 803 reg = <0x0 0x898000 0x0 0x4000>;
1157 #address-cell 804 #address-cells = <1>;
1158 #size-cells = 805 #size-cells = <0>;
1159 interrupts = 806 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>;
1160 clocks = <&gc 807 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1161 clock-names = 808 clock-names = "se";
1162 interconnects 809 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1163 810 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1164 811 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1165 812 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1166 813 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1167 814 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1168 interconnect- 815 interconnect-names = "qup-core",
1169 816 "qup-config",
1170 817 "qup-memory";
1171 power-domains 818 power-domains = <&rpmhpd SA8775P_CX>;
1172 status = "dis 819 status = "disabled";
1173 }; 820 };
1174 }; 821 };
1175 822
1176 qupv3_id_0: geniqup@9c0000 { 823 qupv3_id_0: geniqup@9c0000 {
1177 compatible = "qcom,ge 824 compatible = "qcom,geni-se-qup";
1178 reg = <0x0 0x9c0000 0 825 reg = <0x0 0x9c0000 0x0 0x6000>;
1179 #address-cells = <2>; 826 #address-cells = <2>;
1180 #size-cells = <2>; 827 #size-cells = <2>;
1181 ranges; 828 ranges;
1182 clock-names = "m-ahb" 829 clock-names = "m-ahb", "s-ahb";
1183 clocks = <&gcc GCC_QU 830 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1184 <&gcc GCC_QUP 831 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1185 iommus = <&apps_smmu 832 iommus = <&apps_smmu 0x403 0x0>;
1186 status = "disabled"; 833 status = "disabled";
1187 834
1188 i2c0: i2c@980000 { 835 i2c0: i2c@980000 {
1189 compatible = 836 compatible = "qcom,geni-i2c";
1190 reg = <0x0 0x 837 reg = <0x0 0x980000 0x0 0x4000>;
1191 #address-cell 838 #address-cells = <1>;
1192 #size-cells = 839 #size-cells = <0>;
1193 interrupts = 840 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>;
1194 clocks = <&gc 841 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1195 clock-names = 842 clock-names = "se";
1196 interconnects 843 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1197 844 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1198 845 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1199 846 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
1200 847 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
1201 848 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1202 interconnect- 849 interconnect-names = "qup-core",
1203 850 "qup-config",
1204 851 "qup-memory";
1205 power-domains 852 power-domains = <&rpmhpd SA8775P_CX>;
1206 status = "dis 853 status = "disabled";
1207 }; 854 };
1208 855
1209 spi0: spi@980000 { 856 spi0: spi@980000 {
1210 compatible = 857 compatible = "qcom,geni-spi";
1211 reg = <0x0 0x 858 reg = <0x0 0x980000 0x0 0x4000>;
1212 #address-cell 859 #address-cells = <1>;
1213 #size-cells = 860 #size-cells = <0>;
1214 interrupts = 861 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>;
1215 clocks = <&gc 862 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1216 clock-names = 863 clock-names = "se";
1217 interconnects 864 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1218 865 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1219 866 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1220 867 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
1221 868 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
1222 869 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1223 interconnect- 870 interconnect-names = "qup-core",
1224 871 "qup-config",
1225 872 "qup-memory";
1226 power-domains 873 power-domains = <&rpmhpd SA8775P_CX>;
1227 status = "dis 874 status = "disabled";
1228 }; 875 };
1229 876
1230 i2c1: i2c@984000 { 877 i2c1: i2c@984000 {
1231 compatible = 878 compatible = "qcom,geni-i2c";
1232 reg = <0x0 0x 879 reg = <0x0 0x984000 0x0 0x4000>;
1233 #address-cell 880 #address-cells = <1>;
1234 #size-cells = 881 #size-cells = <0>;
1235 interrupts = 882 interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;
1236 clocks = <&gc 883 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1237 clock-names = 884 clock-names = "se";
1238 interconnects 885 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1239 886 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1240 887 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1241 888 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
1242 889 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
1243 890 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1244 interconnect- 891 interconnect-names = "qup-core",
1245 892 "qup-config",
1246 893 "qup-memory";
1247 power-domains 894 power-domains = <&rpmhpd SA8775P_CX>;
1248 status = "dis 895 status = "disabled";
1249 }; 896 };
1250 897
1251 spi1: spi@984000 { 898 spi1: spi@984000 {
1252 compatible = 899 compatible = "qcom,geni-spi";
1253 reg = <0x0 0x 900 reg = <0x0 0x984000 0x0 0x4000>;
1254 #address-cell 901 #address-cells = <1>;
1255 #size-cells = 902 #size-cells = <0>;
1256 interrupts = 903 interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;
1257 clocks = <&gc 904 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1258 clock-names = 905 clock-names = "se";
1259 interconnects 906 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1260 907 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1261 908 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1262 909 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
1263 910 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
1264 911 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1265 interconnect- 912 interconnect-names = "qup-core",
1266 913 "qup-config",
1267 914 "qup-memory";
1268 power-domains 915 power-domains = <&rpmhpd SA8775P_CX>;
1269 status = "dis 916 status = "disabled";
1270 }; 917 };
1271 918
1272 i2c2: i2c@988000 { 919 i2c2: i2c@988000 {
1273 compatible = 920 compatible = "qcom,geni-i2c";
1274 reg = <0x0 0x 921 reg = <0x0 0x988000 0x0 0x4000>;
1275 #address-cell 922 #address-cells = <1>;
1276 #size-cells = 923 #size-cells = <0>;
1277 interrupts = 924 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>;
1278 clocks = <&gc 925 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1279 clock-names = 926 clock-names = "se";
1280 interconnects 927 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1281 928 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1282 929 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1283 930 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
1284 931 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
1285 932 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1286 interconnect- 933 interconnect-names = "qup-core",
1287 934 "qup-config",
1288 935 "qup-memory";
1289 power-domains 936 power-domains = <&rpmhpd SA8775P_CX>;
1290 status = "dis 937 status = "disabled";
1291 }; 938 };
1292 939
1293 spi2: spi@988000 { 940 spi2: spi@988000 {
1294 compatible = 941 compatible = "qcom,geni-spi";
1295 reg = <0x0 0x 942 reg = <0x0 0x988000 0x0 0x4000>;
1296 #address-cell 943 #address-cells = <1>;
1297 #size-cells = 944 #size-cells = <0>;
1298 interrupts = 945 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>;
1299 clocks = <&gc 946 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1300 clock-names = 947 clock-names = "se";
1301 interconnects 948 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1302 949 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1303 950 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1304 951 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
1305 952 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
1306 953 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1307 interconnect- 954 interconnect-names = "qup-core",
1308 955 "qup-config",
1309 956 "qup-memory";
1310 power-domains 957 power-domains = <&rpmhpd SA8775P_CX>;
1311 status = "dis 958 status = "disabled";
1312 }; 959 };
1313 960
1314 i2c3: i2c@98c000 { 961 i2c3: i2c@98c000 {
1315 compatible = 962 compatible = "qcom,geni-i2c";
1316 reg = <0x0 0x 963 reg = <0x0 0x98c000 0x0 0x4000>;
1317 #address-cell 964 #address-cells = <1>;
1318 #size-cells = 965 #size-cells = <0>;
1319 interrupts = 966 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>;
1320 clocks = <&gc 967 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1321 clock-names = 968 clock-names = "se";
1322 interconnects 969 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1323 970 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1324 971 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1325 972 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
1326 973 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
1327 974 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1328 interconnect- 975 interconnect-names = "qup-core",
1329 976 "qup-config",
1330 977 "qup-memory";
1331 power-domains 978 power-domains = <&rpmhpd SA8775P_CX>;
1332 status = "dis 979 status = "disabled";
1333 }; 980 };
1334 981
1335 spi3: spi@98c000 { 982 spi3: spi@98c000 {
1336 compatible = 983 compatible = "qcom,geni-spi";
1337 reg = <0x0 0x 984 reg = <0x0 0x98c000 0x0 0x4000>;
1338 #address-cell 985 #address-cells = <1>;
1339 #size-cells = 986 #size-cells = <0>;
1340 interrupts = 987 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>;
1341 clocks = <&gc 988 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1342 clock-names = 989 clock-names = "se";
1343 interconnects 990 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1344 991 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1345 992 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1346 993 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
1347 994 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
1348 995 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1349 interconnect- 996 interconnect-names = "qup-core",
1350 997 "qup-config",
1351 998 "qup-memory";
1352 power-domains 999 power-domains = <&rpmhpd SA8775P_CX>;
1353 status = "dis 1000 status = "disabled";
1354 }; 1001 };
1355 1002
1356 i2c4: i2c@990000 { 1003 i2c4: i2c@990000 {
1357 compatible = 1004 compatible = "qcom,geni-i2c";
1358 reg = <0x0 0x 1005 reg = <0x0 0x990000 0x0 0x4000>;
1359 #address-cell 1006 #address-cells = <1>;
1360 #size-cells = 1007 #size-cells = <0>;
1361 interrupts = 1008 interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>;
1362 clocks = <&gc 1009 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1363 clock-names = 1010 clock-names = "se";
1364 interconnects 1011 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1365 1012 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1366 1013 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1367 1014 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
1368 1015 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
1369 1016 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1370 interconnect- 1017 interconnect-names = "qup-core",
1371 1018 "qup-config",
1372 1019 "qup-memory";
1373 power-domains 1020 power-domains = <&rpmhpd SA8775P_CX>;
1374 status = "dis 1021 status = "disabled";
1375 }; 1022 };
1376 1023
1377 spi4: spi@990000 { 1024 spi4: spi@990000 {
1378 compatible = 1025 compatible = "qcom,geni-spi";
1379 reg = <0x0 0x 1026 reg = <0x0 0x990000 0x0 0x4000>;
1380 #address-cell 1027 #address-cells = <1>;
1381 #size-cells = 1028 #size-cells = <0>;
1382 interrupts = 1029 interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>;
1383 clocks = <&gc 1030 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1384 clock-names = 1031 clock-names = "se";
1385 interconnects 1032 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1386 1033 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1387 1034 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1388 1035 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
1389 1036 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
1390 1037 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1391 interconnect- 1038 interconnect-names = "qup-core",
1392 1039 "qup-config",
1393 1040 "qup-memory";
1394 power-domains 1041 power-domains = <&rpmhpd SA8775P_CX>;
1395 status = "dis 1042 status = "disabled";
1396 }; 1043 };
1397 1044
1398 i2c5: i2c@994000 { 1045 i2c5: i2c@994000 {
1399 compatible = 1046 compatible = "qcom,geni-i2c";
1400 reg = <0x0 0x 1047 reg = <0x0 0x994000 0x0 0x4000>;
1401 #address-cell 1048 #address-cells = <1>;
1402 #size-cells = 1049 #size-cells = <0>;
1403 interrupts = 1050 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>;
1404 clocks = <&gc 1051 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1405 clock-names = 1052 clock-names = "se";
1406 interconnects 1053 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1407 1054 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1408 1055 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1409 1056 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
1410 1057 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
1411 1058 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1412 interconnect- 1059 interconnect-names = "qup-core",
1413 1060 "qup-config",
1414 1061 "qup-memory";
1415 power-domains 1062 power-domains = <&rpmhpd SA8775P_CX>;
1416 status = "dis 1063 status = "disabled";
1417 }; 1064 };
1418 1065
1419 spi5: spi@994000 { 1066 spi5: spi@994000 {
1420 compatible = 1067 compatible = "qcom,geni-spi";
1421 reg = <0x0 0x 1068 reg = <0x0 0x994000 0x0 0x4000>;
1422 #address-cell 1069 #address-cells = <1>;
1423 #size-cells = 1070 #size-cells = <0>;
1424 interrupts = 1071 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>;
1425 clocks = <&gc 1072 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1426 clock-names = 1073 clock-names = "se";
1427 interconnects 1074 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1428 1075 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1429 1076 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1430 1077 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
1431 1078 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
1432 1079 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1433 interconnect- 1080 interconnect-names = "qup-core",
1434 1081 "qup-config",
1435 1082 "qup-memory";
1436 power-domains 1083 power-domains = <&rpmhpd SA8775P_CX>;
1437 status = "dis 1084 status = "disabled";
1438 }; 1085 };
1439 1086
1440 uart5: serial@994000 1087 uart5: serial@994000 {
1441 compatible = 1088 compatible = "qcom,geni-uart";
1442 reg = <0x0 0x 1089 reg = <0x0 0x994000 0x0 0x4000>;
1443 interrupts = 1090 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>;
1444 clocks = <&gc 1091 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1445 clock-names = 1092 clock-names = "se";
1446 interconnects 1093 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1447 1094 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1448 1095 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1449 1096 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
1450 interconnect- 1097 interconnect-names = "qup-core", "qup-config";
1451 power-domains 1098 power-domains = <&rpmhpd SA8775P_CX>;
1452 status = "dis 1099 status = "disabled";
1453 }; 1100 };
1454 }; 1101 };
1455 1102
1456 qupv3_id_1: geniqup@ac0000 { 1103 qupv3_id_1: geniqup@ac0000 {
1457 compatible = "qcom,ge 1104 compatible = "qcom,geni-se-qup";
1458 reg = <0x0 0x00ac0000 1105 reg = <0x0 0x00ac0000 0x0 0x6000>;
1459 #address-cells = <2>; 1106 #address-cells = <2>;
1460 #size-cells = <2>; 1107 #size-cells = <2>;
1461 ranges; 1108 ranges;
1462 clock-names = "m-ahb" 1109 clock-names = "m-ahb", "s-ahb";
1463 clocks = <&gcc GCC_QU 1110 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1464 <&gcc GCC_QU 1111 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1465 iommus = <&apps_smmu 1112 iommus = <&apps_smmu 0x443 0x0>;
1466 status = "disabled"; 1113 status = "disabled";
1467 1114
1468 i2c7: i2c@a80000 { 1115 i2c7: i2c@a80000 {
1469 compatible = 1116 compatible = "qcom,geni-i2c";
1470 reg = <0x0 0x 1117 reg = <0x0 0xa80000 0x0 0x4000>;
1471 #address-cell 1118 #address-cells = <1>;
1472 #size-cells = 1119 #size-cells = <0>;
1473 interrupts = 1120 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1474 clocks = <&gc 1121 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1475 clock-names = 1122 clock-names = "se";
1476 interconnects 1123 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1477 1124 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1478 1125 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1479 1126 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1480 1127 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1481 1128 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1482 interconnect- 1129 interconnect-names = "qup-core",
1483 1130 "qup-config",
1484 1131 "qup-memory";
1485 power-domains 1132 power-domains = <&rpmhpd SA8775P_CX>;
1486 status = "dis 1133 status = "disabled";
1487 }; 1134 };
1488 1135
1489 spi7: spi@a80000 { 1136 spi7: spi@a80000 {
1490 compatible = 1137 compatible = "qcom,geni-spi";
1491 reg = <0x0 0x 1138 reg = <0x0 0xa80000 0x0 0x4000>;
1492 #address-cell 1139 #address-cells = <1>;
1493 #size-cells = 1140 #size-cells = <0>;
1494 interrupts = 1141 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1495 clocks = <&gc 1142 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1496 clock-names = 1143 clock-names = "se";
1497 interconnects 1144 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1498 1145 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1499 1146 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1500 1147 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1501 1148 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1502 1149 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1503 interconnect- 1150 interconnect-names = "qup-core",
1504 1151 "qup-config",
1505 1152 "qup-memory";
1506 power-domains 1153 power-domains = <&rpmhpd SA8775P_CX>;
1507 status = "dis 1154 status = "disabled";
1508 }; 1155 };
1509 1156
1510 i2c8: i2c@a84000 { 1157 i2c8: i2c@a84000 {
1511 compatible = 1158 compatible = "qcom,geni-i2c";
1512 reg = <0x0 0x 1159 reg = <0x0 0xa84000 0x0 0x4000>;
1513 #address-cell 1160 #address-cells = <1>;
1514 #size-cells = 1161 #size-cells = <0>;
1515 interrupts = 1162 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1516 clocks = <&gc 1163 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1517 clock-names = 1164 clock-names = "se";
1518 interconnects 1165 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1519 1166 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1520 1167 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1521 1168 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1522 1169 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1523 1170 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1524 interconnect- 1171 interconnect-names = "qup-core",
1525 1172 "qup-config",
1526 1173 "qup-memory";
1527 power-domains 1174 power-domains = <&rpmhpd SA8775P_CX>;
1528 status = "dis 1175 status = "disabled";
1529 }; 1176 };
1530 1177
1531 spi8: spi@a84000 { 1178 spi8: spi@a84000 {
1532 compatible = 1179 compatible = "qcom,geni-spi";
1533 reg = <0x0 0x 1180 reg = <0x0 0xa84000 0x0 0x4000>;
1534 #address-cell 1181 #address-cells = <1>;
1535 #size-cells = 1182 #size-cells = <0>;
1536 interrupts = 1183 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1537 clocks = <&gc 1184 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1538 clock-names = 1185 clock-names = "se";
1539 interconnects 1186 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1540 1187 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1541 1188 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1542 1189 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1543 1190 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1544 1191 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1545 interconnect- 1192 interconnect-names = "qup-core",
1546 1193 "qup-config",
1547 1194 "qup-memory";
1548 power-domains 1195 power-domains = <&rpmhpd SA8775P_CX>;
1549 status = "dis 1196 status = "disabled";
1550 }; 1197 };
1551 1198
1552 i2c9: i2c@a88000 { 1199 i2c9: i2c@a88000 {
1553 compatible = 1200 compatible = "qcom,geni-i2c";
1554 reg = <0x0 0x 1201 reg = <0x0 0xa88000 0x0 0x4000>;
1555 #address-cell 1202 #address-cells = <1>;
1556 #size-cells = 1203 #size-cells = <0>;
1557 interrupts = 1204 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1558 clocks = <&gc 1205 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1559 clock-names = 1206 clock-names = "se";
1560 interconnects 1207 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1561 1208 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1562 1209 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1563 1210 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1564 1211 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1565 1212 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1566 interconnect- 1213 interconnect-names = "qup-core",
1567 1214 "qup-config",
1568 1215 "qup-memory";
1569 power-domains 1216 power-domains = <&rpmhpd SA8775P_CX>;
1570 status = "dis 1217 status = "disabled";
1571 }; 1218 };
1572 1219
1573 spi9: spi@a88000 { 1220 spi9: spi@a88000 {
1574 compatible = 1221 compatible = "qcom,geni-spi";
1575 reg = <0x0 0x 1222 reg = <0x0 0xa88000 0x0 0x4000>;
1576 #address-cell 1223 #address-cells = <1>;
1577 #size-cells = 1224 #size-cells = <0>;
1578 interrupts = 1225 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1579 clocks = <&gc 1226 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1580 clock-names = 1227 clock-names = "se";
1581 interconnects 1228 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1582 1229 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1583 1230 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1584 1231 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1585 1232 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1586 1233 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1587 interconnect- 1234 interconnect-names = "qup-core",
1588 1235 "qup-config",
1589 1236 "qup-memory";
1590 power-domains 1237 power-domains = <&rpmhpd SA8775P_CX>;
1591 status = "dis 1238 status = "disabled";
1592 }; 1239 };
1593 1240
1594 uart9: serial@a88000 1241 uart9: serial@a88000 {
1595 compatible = 1242 compatible = "qcom,geni-uart";
1596 reg = <0x0 0x 1243 reg = <0x0 0xa88000 0x0 0x4000>;
1597 interrupts = 1244 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1598 clocks = <&gc 1245 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1599 clock-names = 1246 clock-names = "se";
1600 interconnects 1247 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1601 1248 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1602 1249 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1603 1250 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
1604 interconnect- 1251 interconnect-names = "qup-core", "qup-config";
1605 power-domains 1252 power-domains = <&rpmhpd SA8775P_CX>;
1606 status = "dis 1253 status = "disabled";
1607 }; 1254 };
1608 1255
1609 i2c10: i2c@a8c000 { 1256 i2c10: i2c@a8c000 {
1610 compatible = 1257 compatible = "qcom,geni-i2c";
1611 reg = <0x0 0x 1258 reg = <0x0 0xa8c000 0x0 0x4000>;
1612 #address-cell 1259 #address-cells = <1>;
1613 #size-cells = 1260 #size-cells = <0>;
1614 interrupts = 1261 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1615 clocks = <&gc 1262 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1616 clock-names = 1263 clock-names = "se";
1617 interconnects 1264 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1618 1265 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1619 1266 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1620 1267 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1621 1268 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1622 1269 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1623 interconnect- 1270 interconnect-names = "qup-core",
1624 1271 "qup-config",
1625 1272 "qup-memory";
1626 power-domains 1273 power-domains = <&rpmhpd SA8775P_CX>;
1627 status = "dis 1274 status = "disabled";
1628 }; 1275 };
1629 1276
1630 spi10: spi@a8c000 { 1277 spi10: spi@a8c000 {
1631 compatible = 1278 compatible = "qcom,geni-spi";
1632 reg = <0x0 0x 1279 reg = <0x0 0xa8c000 0x0 0x4000>;
1633 #address-cell 1280 #address-cells = <1>;
1634 #size-cells = 1281 #size-cells = <0>;
1635 interrupts = 1282 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1636 clocks = <&gc 1283 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1637 clock-names = 1284 clock-names = "se";
1638 interconnects 1285 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1639 1286 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1640 1287 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1641 1288 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1642 1289 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1643 1290 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1644 interconnect- 1291 interconnect-names = "qup-core",
1645 1292 "qup-config",
1646 1293 "qup-memory";
1647 power-domains 1294 power-domains = <&rpmhpd SA8775P_CX>;
1648 status = "dis 1295 status = "disabled";
1649 }; 1296 };
1650 1297
1651 uart10: serial@a8c000 1298 uart10: serial@a8c000 {
1652 compatible = 1299 compatible = "qcom,geni-uart";
1653 reg = <0x0 0x 1300 reg = <0x0 0x00a8c000 0x0 0x4000>;
1654 interrupts = 1301 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1655 clock-names = 1302 clock-names = "se";
1656 clocks = <&gc 1303 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1657 interconnect- 1304 interconnect-names = "qup-core", "qup-config";
1658 interconnects 1305 interconnects = <&clk_virt MASTER_QUP_CORE_1 0
1659 1306 &clk_virt SLAVE_QUP_CORE_1 0>,
1660 1307 <&gem_noc MASTER_APPSS_PROC 0
1661 1308 &config_noc SLAVE_QUP_1 0>;
1662 power-domains 1309 power-domains = <&rpmhpd SA8775P_CX>;
1663 operating-poi 1310 operating-points-v2 = <&qup_opp_table_100mhz>;
1664 status = "dis 1311 status = "disabled";
1665 }; 1312 };
1666 1313
1667 i2c11: i2c@a90000 { 1314 i2c11: i2c@a90000 {
1668 compatible = 1315 compatible = "qcom,geni-i2c";
1669 reg = <0x0 0x 1316 reg = <0x0 0xa90000 0x0 0x4000>;
1670 #address-cell 1317 #address-cells = <1>;
1671 #size-cells = 1318 #size-cells = <0>;
1672 interrupts = 1319 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1673 clocks = <&gc 1320 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1674 clock-names = 1321 clock-names = "se";
1675 interconnects 1322 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1676 1323 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1677 1324 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1678 1325 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1679 1326 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1680 1327 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1681 interconnect- 1328 interconnect-names = "qup-core",
1682 1329 "qup-config",
1683 1330 "qup-memory";
1684 power-domains 1331 power-domains = <&rpmhpd SA8775P_CX>;
1685 status = "dis 1332 status = "disabled";
1686 }; 1333 };
1687 1334
1688 spi11: spi@a90000 { 1335 spi11: spi@a90000 {
1689 compatible = 1336 compatible = "qcom,geni-spi";
1690 reg = <0x0 0x 1337 reg = <0x0 0xa90000 0x0 0x4000>;
1691 #address-cell 1338 #address-cells = <1>;
1692 #size-cells = 1339 #size-cells = <0>;
1693 interrupts = 1340 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1694 clocks = <&gc 1341 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1695 clock-names = 1342 clock-names = "se";
1696 interconnects 1343 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1697 1344 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1698 1345 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1699 1346 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1700 1347 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1701 1348 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1702 interconnect- 1349 interconnect-names = "qup-core",
1703 1350 "qup-config",
1704 1351 "qup-memory";
1705 power-domains 1352 power-domains = <&rpmhpd SA8775P_CX>;
1706 status = "dis 1353 status = "disabled";
1707 }; 1354 };
1708 1355
1709 i2c12: i2c@a94000 { 1356 i2c12: i2c@a94000 {
1710 compatible = 1357 compatible = "qcom,geni-i2c";
1711 reg = <0x0 0x 1358 reg = <0x0 0xa94000 0x0 0x4000>;
1712 #address-cell 1359 #address-cells = <1>;
1713 #size-cells = 1360 #size-cells = <0>;
1714 interrupts = 1361 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1715 clocks = <&gc 1362 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1716 clock-names = 1363 clock-names = "se";
1717 interconnects 1364 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1718 1365 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1719 1366 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1720 1367 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1721 1368 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1722 1369 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1723 interconnect- 1370 interconnect-names = "qup-core",
1724 1371 "qup-config",
1725 1372 "qup-memory";
1726 power-domains 1373 power-domains = <&rpmhpd SA8775P_CX>;
1727 status = "dis 1374 status = "disabled";
1728 }; 1375 };
1729 1376
1730 spi12: spi@a94000 { 1377 spi12: spi@a94000 {
1731 compatible = 1378 compatible = "qcom,geni-spi";
1732 reg = <0x0 0x 1379 reg = <0x0 0xa94000 0x0 0x4000>;
1733 #address-cell 1380 #address-cells = <1>;
1734 #size-cells = 1381 #size-cells = <0>;
1735 interrupts = 1382 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1736 clocks = <&gc 1383 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1737 clock-names = 1384 clock-names = "se";
1738 interconnects 1385 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1739 1386 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1740 1387 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1741 1388 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1742 1389 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1743 1390 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1744 interconnect- 1391 interconnect-names = "qup-core",
1745 1392 "qup-config",
1746 1393 "qup-memory";
1747 power-domains 1394 power-domains = <&rpmhpd SA8775P_CX>;
1748 status = "dis 1395 status = "disabled";
1749 }; 1396 };
1750 1397
1751 uart12: serial@a94000 1398 uart12: serial@a94000 {
1752 compatible = 1399 compatible = "qcom,geni-uart";
1753 reg = <0x0 0x 1400 reg = <0x0 0x00a94000 0x0 0x4000>;
1754 interrupts = 1401 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1755 clocks = <&gc 1402 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1756 clock-names = 1403 clock-names = "se";
1757 interconnects 1404 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1758 1405 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1759 1406 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1760 1407 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
1761 interconnect- 1408 interconnect-names = "qup-core", "qup-config";
1762 power-domains 1409 power-domains = <&rpmhpd SA8775P_CX>;
1763 status = "dis 1410 status = "disabled";
1764 }; 1411 };
1765 1412
1766 i2c13: i2c@a98000 { 1413 i2c13: i2c@a98000 {
1767 compatible = 1414 compatible = "qcom,geni-i2c";
1768 reg = <0x0 0x 1415 reg = <0x0 0xa98000 0x0 0x4000>;
1769 #address-cell 1416 #address-cells = <1>;
1770 #size-cells = 1417 #size-cells = <0>;
1771 interrupts = 1418 interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
1772 clocks = <&gc 1419 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1773 clock-names = 1420 clock-names = "se";
1774 interconnects 1421 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1775 1422 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1776 1423 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1777 1424 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1778 1425 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1779 1426 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1780 interconnect- 1427 interconnect-names = "qup-core",
1781 1428 "qup-config",
1782 1429 "qup-memory";
1783 power-domains 1430 power-domains = <&rpmhpd SA8775P_CX>;
1784 status = "dis 1431 status = "disabled";
1785 }; 1432 };
1786 }; 1433 };
1787 1434
1788 qupv3_id_3: geniqup@bc0000 { 1435 qupv3_id_3: geniqup@bc0000 {
1789 compatible = "qcom,ge 1436 compatible = "qcom,geni-se-qup";
1790 reg = <0x0 0xbc0000 0 1437 reg = <0x0 0xbc0000 0x0 0x6000>;
1791 #address-cells = <2>; 1438 #address-cells = <2>;
1792 #size-cells = <2>; 1439 #size-cells = <2>;
1793 ranges; 1440 ranges;
1794 clock-names = "m-ahb" 1441 clock-names = "m-ahb", "s-ahb";
1795 clocks = <&gcc GCC_QU 1442 clocks = <&gcc GCC_QUPV3_WRAP_3_M_AHB_CLK>,
1796 <&gcc GCC_QUP 1443 <&gcc GCC_QUPV3_WRAP_3_S_AHB_CLK>;
1797 iommus = <&apps_smmu 1444 iommus = <&apps_smmu 0x43 0x0>;
1798 status = "disabled"; 1445 status = "disabled";
1799 1446
1800 i2c21: i2c@b80000 { 1447 i2c21: i2c@b80000 {
1801 compatible = 1448 compatible = "qcom,geni-i2c";
1802 reg = <0x0 0x 1449 reg = <0x0 0xb80000 0x0 0x4000>;
1803 #address-cell 1450 #address-cells = <1>;
1804 #size-cells = 1451 #size-cells = <0>;
1805 interrupts = 1452 interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>;
1806 clocks = <&gc 1453 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>;
1807 clock-names = 1454 clock-names = "se";
1808 interconnects 1455 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS
1809 1456 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>,
1810 <& 1457 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1811 1458 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>,
1812 <& 1459 <&aggre1_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS
1813 1460 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1814 interconnect- 1461 interconnect-names = "qup-core",
1815 1462 "qup-config",
1816 1463 "qup-memory";
1817 power-domains 1464 power-domains = <&rpmhpd SA8775P_CX>;
1818 status = "dis 1465 status = "disabled";
1819 }; 1466 };
1820 1467
1821 spi21: spi@b80000 { 1468 spi21: spi@b80000 {
1822 compatible = 1469 compatible = "qcom,geni-spi";
1823 reg = <0x0 0x 1470 reg = <0x0 0xb80000 0x0 0x4000>;
1824 #address-cell 1471 #address-cells = <1>;
1825 #size-cells = 1472 #size-cells = <0>;
1826 interrupts = 1473 interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>;
1827 clocks = <&gc 1474 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>;
1828 clock-names = 1475 clock-names = "se";
1829 interconnects 1476 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS
1830 1477 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>,
1831 <& 1478 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1832 1479 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>,
1833 <& 1480 <&aggre1_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS
1834 1481 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1835 interconnect- 1482 interconnect-names = "qup-core",
1836 1483 "qup-config",
1837 1484 "qup-memory";
1838 power-domains 1485 power-domains = <&rpmhpd SA8775P_CX>;
1839 status = "dis 1486 status = "disabled";
1840 }; 1487 };
1841 }; 1488 };
1842 1489
1843 rng: rng@10d2000 { <<
1844 compatible = "qcom,sa <<
1845 reg = <0 0x010d2000 0 <<
1846 }; <<
1847 <<
1848 ufs_mem_hc: ufs@1d84000 { 1490 ufs_mem_hc: ufs@1d84000 {
1849 compatible = "qcom,sa 1491 compatible = "qcom,sa8775p-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
1850 reg = <0x0 0x01d84000 1492 reg = <0x0 0x01d84000 0x0 0x3000>;
1851 interrupts = <GIC_SPI 1493 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
1852 phys = <&ufs_mem_phy> 1494 phys = <&ufs_mem_phy>;
1853 phy-names = "ufsphy"; 1495 phy-names = "ufsphy";
1854 lanes-per-direction = 1496 lanes-per-direction = <2>;
1855 #reset-cells = <1>; 1497 #reset-cells = <1>;
1856 resets = <&gcc GCC_UF 1498 resets = <&gcc GCC_UFS_PHY_BCR>;
1857 reset-names = "rst"; 1499 reset-names = "rst";
1858 power-domains = <&gcc 1500 power-domains = <&gcc UFS_PHY_GDSC>;
1859 required-opps = <&rpm 1501 required-opps = <&rpmhpd_opp_nom>;
1860 iommus = <&apps_smmu 1502 iommus = <&apps_smmu 0x100 0x0>;
1861 dma-coherent; 1503 dma-coherent;
1862 clocks = <&gcc GCC_UF 1504 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
1863 <&gcc GCC_AG 1505 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
1864 <&gcc GCC_UF 1506 <&gcc GCC_UFS_PHY_AHB_CLK>,
1865 <&gcc GCC_UF 1507 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
1866 <&rpmhcc RPM 1508 <&rpmhcc RPMH_CXO_CLK>,
1867 <&gcc GCC_UF 1509 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
1868 <&gcc GCC_UF 1510 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
1869 <&gcc GCC_UF 1511 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
1870 clock-names = "core_c 1512 clock-names = "core_clk",
1871 "bus_ag 1513 "bus_aggr_clk",
1872 "iface_ 1514 "iface_clk",
1873 "core_c 1515 "core_clk_unipro",
1874 "ref_cl 1516 "ref_clk",
1875 "tx_lan 1517 "tx_lane0_sync_clk",
1876 "rx_lan 1518 "rx_lane0_sync_clk",
1877 "rx_lan 1519 "rx_lane1_sync_clk";
1878 freq-table-hz = <7500 1520 freq-table-hz = <75000000 300000000>,
1879 <0 0> 1521 <0 0>,
1880 <0 0> 1522 <0 0>,
1881 <7500 1523 <75000000 300000000>,
1882 <0 0> 1524 <0 0>,
1883 <0 0> 1525 <0 0>,
1884 <0 0> 1526 <0 0>,
1885 <0 0> 1527 <0 0>;
1886 qcom,ice = <&ice>; 1528 qcom,ice = <&ice>;
1887 status = "disabled"; 1529 status = "disabled";
1888 }; 1530 };
1889 1531
1890 ufs_mem_phy: phy@1d87000 { 1532 ufs_mem_phy: phy@1d87000 {
1891 compatible = "qcom,sa 1533 compatible = "qcom,sa8775p-qmp-ufs-phy";
1892 reg = <0x0 0x01d87000 1534 reg = <0x0 0x01d87000 0x0 0xe10>;
1893 /* 1535 /*
1894 * Yes, GCC_EDP_REF_C 1536 * Yes, GCC_EDP_REF_CLKREF_EN is correct in qref. It
1895 * enables the CXO cl 1537 * enables the CXO clock to eDP *and* UFS PHY.
1896 */ 1538 */
1897 clocks = <&rpmhcc RPM 1539 clocks = <&rpmhcc RPMH_CXO_CLK>,
1898 <&gcc GCC_UF 1540 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
1899 <&gcc GCC_ED 1541 <&gcc GCC_EDP_REF_CLKREF_EN>;
1900 clock-names = "ref", 1542 clock-names = "ref", "ref_aux", "qref";
1901 power-domains = <&gcc 1543 power-domains = <&gcc UFS_PHY_GDSC>;
1902 resets = <&ufs_mem_hc 1544 resets = <&ufs_mem_hc 0>;
1903 reset-names = "ufsphy 1545 reset-names = "ufsphy";
1904 #phy-cells = <0>; 1546 #phy-cells = <0>;
1905 status = "disabled"; 1547 status = "disabled";
1906 }; 1548 };
1907 1549
1908 ice: crypto@1d88000 { 1550 ice: crypto@1d88000 {
1909 compatible = "qcom,sa 1551 compatible = "qcom,sa8775p-inline-crypto-engine",
1910 "qcom,in 1552 "qcom,inline-crypto-engine";
1911 reg = <0x0 0x01d88000 1553 reg = <0x0 0x01d88000 0x0 0x8000>;
1912 clocks = <&gcc GCC_UF 1554 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
1913 }; 1555 };
1914 1556
1915 stm: stm@4002000 { <<
1916 compatible = "arm,cor <<
1917 reg = <0x0 0x4002000 <<
1918 <0x0 0x1628 <<
1919 reg-names = "stm-base <<
1920 <<
1921 clocks = <&aoss_qmp>; <<
1922 clock-names = "apb_pc <<
1923 <<
1924 out-ports { <<
1925 port { <<
1926 stm_o <<
1927 <<
1928 <<
1929 }; <<
1930 }; <<
1931 }; <<
1932 }; <<
1933 <<
1934 tpdm@4003000 { <<
1935 compatible = "qcom,co <<
1936 reg = <0x0 0x4003000 <<
1937 <<
1938 clocks = <&aoss_qmp>; <<
1939 clock-names = "apb_pc <<
1940 <<
1941 qcom,cmb-element-bits <<
1942 qcom,cmb-msrs-num = < <<
1943 <<
1944 out-ports { <<
1945 port { <<
1946 qdss_ <<
1947 <<
1948 <<
1949 }; <<
1950 }; <<
1951 }; <<
1952 }; <<
1953 <<
1954 tpda@4004000 { <<
1955 compatible = "qcom,co <<
1956 reg = <0x0 0x4004000 <<
1957 <<
1958 clocks = <&aoss_qmp>; <<
1959 clock-names = "apb_pc <<
1960 <<
1961 out-ports { <<
1962 port { <<
1963 qdss_ <<
1964 <<
1965 <<
1966 }; <<
1967 }; <<
1968 }; <<
1969 <<
1970 in-ports { <<
1971 #address-cell <<
1972 #size-cells = <<
1973 <<
1974 port@0 { <<
1975 reg = <<
1976 qdss_ <<
1977 <<
1978 <<
1979 }; <<
1980 }; <<
1981 <<
1982 port@1 { <<
1983 reg = <<
1984 qdss_ <<
1985 <<
1986 <<
1987 }; <<
1988 }; <<
1989 }; <<
1990 }; <<
1991 <<
1992 tpdm@400f000 { <<
1993 compatible = "qcom,co <<
1994 reg = <0x0 0x400f000 <<
1995 <<
1996 clocks = <&aoss_qmp>; <<
1997 clock-names = "apb_pc <<
1998 <<
1999 qcom,cmb-element-bits <<
2000 qcom,cmb-msrs-num = < <<
2001 <<
2002 out-ports { <<
2003 port { <<
2004 qdss_ <<
2005 <<
2006 <<
2007 }; <<
2008 }; <<
2009 }; <<
2010 }; <<
2011 <<
2012 funnel@4041000 { <<
2013 compatible = "arm,cor <<
2014 reg = <0x0 0x4041000 <<
2015 <<
2016 clocks = <&aoss_qmp>; <<
2017 clock-names = "apb_pc <<
2018 <<
2019 out-ports { <<
2020 port { <<
2021 funne <<
2022 <<
2023 <<
2024 }; <<
2025 }; <<
2026 }; <<
2027 <<
2028 in-ports { <<
2029 #address-cell <<
2030 #size-cells = <<
2031 <<
2032 port@6 { <<
2033 reg = <<
2034 funne <<
2035 <<
2036 <<
2037 }; <<
2038 }; <<
2039 <<
2040 port@7 { <<
2041 reg = <<
2042 funne <<
2043 <<
2044 <<
2045 }; <<
2046 }; <<
2047 }; <<
2048 }; <<
2049 <<
2050 funnel@4042000 { <<
2051 compatible = "arm,cor <<
2052 reg = <0x0 0x4042000 <<
2053 <<
2054 clocks = <&aoss_qmp>; <<
2055 clock-names = "apb_pc <<
2056 <<
2057 out-ports { <<
2058 port { <<
2059 funne <<
2060 <<
2061 <<
2062 }; <<
2063 }; <<
2064 }; <<
2065 <<
2066 in-ports { <<
2067 #address-cell <<
2068 #size-cells = <<
2069 <<
2070 port@4 { <<
2071 reg = <<
2072 funne <<
2073 <<
2074 <<
2075 }; <<
2076 }; <<
2077 }; <<
2078 }; <<
2079 <<
2080 funnel@4045000 { <<
2081 compatible = "arm,cor <<
2082 reg = <0x0 0x4045000 <<
2083 <<
2084 clocks = <&aoss_qmp>; <<
2085 clock-names = "apb_pc <<
2086 <<
2087 out-ports { <<
2088 port { <<
2089 qdss_ <<
2090 <<
2091 <<
2092 }; <<
2093 }; <<
2094 }; <<
2095 <<
2096 in-ports { <<
2097 #address-cell <<
2098 #size-cells = <<
2099 <<
2100 port@0 { <<
2101 reg = <<
2102 qdss_ <<
2103 <<
2104 <<
2105 }; <<
2106 }; <<
2107 <<
2108 port@1 { <<
2109 reg = <<
2110 qdss_ <<
2111 <<
2112 <<
2113 }; <<
2114 }; <<
2115 }; <<
2116 }; <<
2117 <<
2118 funnel@4b04000 { <<
2119 compatible = "arm,cor <<
2120 reg = <0x0 0x4b04000 <<
2121 <<
2122 clocks = <&aoss_qmp>; <<
2123 clock-names = "apb_pc <<
2124 <<
2125 out-ports { <<
2126 port { <<
2127 aoss_ <<
2128 <<
2129 <<
2130 }; <<
2131 }; <<
2132 }; <<
2133 <<
2134 in-ports { <<
2135 #address-cell <<
2136 #size-cells = <<
2137 <<
2138 port@6 { <<
2139 reg = <<
2140 aoss_ <<
2141 <<
2142 <<
2143 }; <<
2144 }; <<
2145 <<
2146 port@7 { <<
2147 reg = <<
2148 aoss_ <<
2149 <<
2150 <<
2151 }; <<
2152 }; <<
2153 }; <<
2154 }; <<
2155 <<
2156 tmc_etf: tmc@4b05000 { <<
2157 compatible = "arm,cor <<
2158 reg = <0x0 0x4b05000 <<
2159 <<
2160 clocks = <&aoss_qmp>; <<
2161 clock-names = "apb_pc <<
2162 <<
2163 out-ports { <<
2164 port { <<
2165 etf0_ <<
2166 <<
2167 <<
2168 }; <<
2169 }; <<
2170 }; <<
2171 <<
2172 in-ports { <<
2173 port { <<
2174 etf0_ <<
2175 <<
2176 <<
2177 }; <<
2178 }; <<
2179 }; <<
2180 }; <<
2181 <<
2182 replicator@4b06000 { <<
2183 compatible = "arm,cor <<
2184 reg = <0x0 0x4b06000 <<
2185 <<
2186 clocks = <&aoss_qmp>; <<
2187 clock-names = "apb_pc <<
2188 <<
2189 out-ports { <<
2190 #address-cell <<
2191 #size-cells = <<
2192 <<
2193 port@1 { <<
2194 reg = <<
2195 swao_ <<
2196 <<
2197 <<
2198 }; <<
2199 }; <<
2200 }; <<
2201 <<
2202 in-ports { <<
2203 port { <<
2204 swao_ <<
2205 <<
2206 <<
2207 }; <<
2208 }; <<
2209 }; <<
2210 }; <<
2211 <<
2212 tpda@4b08000 { <<
2213 compatible = "qcom,co <<
2214 reg = <0x0 0x4b08000 <<
2215 <<
2216 clocks = <&aoss_qmp>; <<
2217 clock-names = "apb_pc <<
2218 <<
2219 out-ports { <<
2220 port { <<
2221 aoss_ <<
2222 <<
2223 <<
2224 }; <<
2225 }; <<
2226 }; <<
2227 <<
2228 in-ports { <<
2229 #address-cell <<
2230 #size-cells = <<
2231 <<
2232 port@0 { <<
2233 reg = <<
2234 aoss_ <<
2235 <<
2236 <<
2237 }; <<
2238 }; <<
2239 <<
2240 port@1 { <<
2241 reg = <<
2242 aoss_ <<
2243 <<
2244 <<
2245 }; <<
2246 }; <<
2247 <<
2248 port@2 { <<
2249 reg = <<
2250 aoss_ <<
2251 <<
2252 <<
2253 }; <<
2254 }; <<
2255 <<
2256 port@3 { <<
2257 reg = <<
2258 aoss_ <<
2259 <<
2260 <<
2261 }; <<
2262 }; <<
2263 <<
2264 port@4 { <<
2265 reg = <<
2266 aoss_ <<
2267 <<
2268 <<
2269 }; <<
2270 }; <<
2271 }; <<
2272 }; <<
2273 <<
2274 tpdm@4b09000 { <<
2275 compatible = "qcom,co <<
2276 reg = <0x0 0x4b09000 <<
2277 <<
2278 clocks = <&aoss_qmp>; <<
2279 clock-names = "apb_pc <<
2280 <<
2281 qcom,cmb-element-bits <<
2282 qcom,cmb-msrs-num = < <<
2283 <<
2284 out-ports { <<
2285 port { <<
2286 aoss_ <<
2287 <<
2288 <<
2289 }; <<
2290 }; <<
2291 }; <<
2292 }; <<
2293 <<
2294 tpdm@4b0a000 { <<
2295 compatible = "qcom,co <<
2296 reg = <0x0 0x4b0a000 <<
2297 <<
2298 clocks = <&aoss_qmp>; <<
2299 clock-names = "apb_pc <<
2300 <<
2301 qcom,cmb-element-bits <<
2302 qcom,cmb-msrs-num = < <<
2303 <<
2304 out-ports { <<
2305 port { <<
2306 aoss_ <<
2307 <<
2308 <<
2309 }; <<
2310 }; <<
2311 }; <<
2312 }; <<
2313 <<
2314 tpdm@4b0b000 { <<
2315 compatible = "qcom,co <<
2316 reg = <0x0 0x4b0b000 <<
2317 <<
2318 clocks = <&aoss_qmp>; <<
2319 clock-names = "apb_pc <<
2320 <<
2321 qcom,cmb-element-bits <<
2322 qcom,cmb-msrs-num = < <<
2323 <<
2324 out-ports { <<
2325 port { <<
2326 aoss_ <<
2327 <<
2328 <<
2329 }; <<
2330 }; <<
2331 }; <<
2332 }; <<
2333 <<
2334 tpdm@4b0c000 { <<
2335 compatible = "qcom,co <<
2336 reg = <0x0 0x4b0c000 <<
2337 <<
2338 clocks = <&aoss_qmp>; <<
2339 clock-names = "apb_pc <<
2340 <<
2341 qcom,cmb-element-bits <<
2342 qcom,cmb-msrs-num = < <<
2343 <<
2344 out-ports { <<
2345 port { <<
2346 aoss_ <<
2347 <<
2348 <<
2349 }; <<
2350 }; <<
2351 }; <<
2352 }; <<
2353 <<
2354 tpdm@4b0d000 { <<
2355 compatible = "qcom,co <<
2356 reg = <0x0 0x4b0d000 <<
2357 <<
2358 clocks = <&aoss_qmp>; <<
2359 clock-names = "apb_pc <<
2360 <<
2361 qcom,dsb-element-bits <<
2362 qcom,dsb-msrs-num = < <<
2363 <<
2364 out-ports { <<
2365 port { <<
2366 aoss_ <<
2367 <<
2368 <<
2369 }; <<
2370 }; <<
2371 }; <<
2372 }; <<
2373 <<
2374 aoss_cti: cti@4b13000 { <<
2375 compatible = "arm,cor <<
2376 reg = <0x0 0x4b13000 <<
2377 <<
2378 clocks = <&aoss_qmp>; <<
2379 clock-names = "apb_pc <<
2380 }; <<
2381 <<
2382 etm@6040000 { <<
2383 compatible = "arm,pri <<
2384 reg = <0x0 0x6040000 <<
2385 cpu = <&CPU0>; <<
2386 <<
2387 clocks = <&aoss_qmp>; <<
2388 clock-names = "apb_pc <<
2389 arm,coresight-loses-c <<
2390 qcom,skip-power-up; <<
2391 <<
2392 out-ports { <<
2393 port { <<
2394 etm0_ <<
2395 <<
2396 <<
2397 }; <<
2398 }; <<
2399 }; <<
2400 }; <<
2401 <<
2402 etm@6140000 { <<
2403 compatible = "arm,pri <<
2404 reg = <0x0 0x6140000 <<
2405 cpu = <&CPU1>; <<
2406 <<
2407 clocks = <&aoss_qmp>; <<
2408 clock-names = "apb_pc <<
2409 arm,coresight-loses-c <<
2410 qcom,skip-power-up; <<
2411 <<
2412 out-ports { <<
2413 port { <<
2414 etm1_ <<
2415 <<
2416 <<
2417 }; <<
2418 }; <<
2419 }; <<
2420 }; <<
2421 <<
2422 etm@6240000 { <<
2423 compatible = "arm,pri <<
2424 reg = <0x0 0x6240000 <<
2425 cpu = <&CPU2>; <<
2426 <<
2427 clocks = <&aoss_qmp>; <<
2428 clock-names = "apb_pc <<
2429 arm,coresight-loses-c <<
2430 qcom,skip-power-up; <<
2431 <<
2432 out-ports { <<
2433 port { <<
2434 etm2_ <<
2435 <<
2436 <<
2437 }; <<
2438 }; <<
2439 }; <<
2440 }; <<
2441 <<
2442 etm@6340000 { <<
2443 compatible = "arm,pri <<
2444 reg = <0x0 0x6340000 <<
2445 cpu = <&CPU3>; <<
2446 <<
2447 clocks = <&aoss_qmp>; <<
2448 clock-names = "apb_pc <<
2449 arm,coresight-loses-c <<
2450 qcom,skip-power-up; <<
2451 <<
2452 out-ports { <<
2453 port { <<
2454 etm3_ <<
2455 <<
2456 <<
2457 }; <<
2458 }; <<
2459 }; <<
2460 }; <<
2461 <<
2462 etm@6440000 { <<
2463 compatible = "arm,pri <<
2464 reg = <0x0 0x6440000 <<
2465 cpu = <&CPU4>; <<
2466 <<
2467 clocks = <&aoss_qmp>; <<
2468 clock-names = "apb_pc <<
2469 arm,coresight-loses-c <<
2470 qcom,skip-power-up; <<
2471 <<
2472 out-ports { <<
2473 port { <<
2474 etm4_ <<
2475 <<
2476 <<
2477 }; <<
2478 }; <<
2479 }; <<
2480 }; <<
2481 <<
2482 etm@6540000 { <<
2483 compatible = "arm,pri <<
2484 reg = <0x0 0x6540000 <<
2485 cpu = <&CPU5>; <<
2486 <<
2487 clocks = <&aoss_qmp>; <<
2488 clock-names = "apb_pc <<
2489 arm,coresight-loses-c <<
2490 qcom,skip-power-up; <<
2491 <<
2492 out-ports { <<
2493 port { <<
2494 etm5_ <<
2495 <<
2496 <<
2497 }; <<
2498 }; <<
2499 }; <<
2500 }; <<
2501 <<
2502 etm@6640000 { <<
2503 compatible = "arm,pri <<
2504 reg = <0x0 0x6640000 <<
2505 cpu = <&CPU6>; <<
2506 <<
2507 clocks = <&aoss_qmp>; <<
2508 clock-names = "apb_pc <<
2509 arm,coresight-loses-c <<
2510 qcom,skip-power-up; <<
2511 <<
2512 out-ports { <<
2513 port { <<
2514 etm6_ <<
2515 <<
2516 <<
2517 }; <<
2518 }; <<
2519 }; <<
2520 }; <<
2521 <<
2522 etm@6740000 { <<
2523 compatible = "arm,pri <<
2524 reg = <0x0 0x6740000 <<
2525 cpu = <&CPU7>; <<
2526 <<
2527 clocks = <&aoss_qmp>; <<
2528 clock-names = "apb_pc <<
2529 arm,coresight-loses-c <<
2530 qcom,skip-power-up; <<
2531 <<
2532 out-ports { <<
2533 port { <<
2534 etm7_ <<
2535 <<
2536 <<
2537 }; <<
2538 }; <<
2539 }; <<
2540 }; <<
2541 <<
2542 funnel@6800000 { <<
2543 compatible = "arm,cor <<
2544 reg = <0x0 0x6800000 <<
2545 <<
2546 clocks = <&aoss_qmp>; <<
2547 clock-names = "apb_pc <<
2548 <<
2549 out-ports { <<
2550 port { <<
2551 apss_ <<
2552 <<
2553 <<
2554 }; <<
2555 }; <<
2556 }; <<
2557 <<
2558 in-ports { <<
2559 #address-cell <<
2560 #size-cells = <<
2561 <<
2562 port@0 { <<
2563 reg = <<
2564 apss_ <<
2565 <<
2566 <<
2567 }; <<
2568 }; <<
2569 <<
2570 port@1 { <<
2571 reg = <<
2572 apss_ <<
2573 <<
2574 <<
2575 }; <<
2576 }; <<
2577 <<
2578 port@2 { <<
2579 reg = <<
2580 apss_ <<
2581 <<
2582 <<
2583 }; <<
2584 }; <<
2585 <<
2586 port@3 { <<
2587 reg = <<
2588 apss_ <<
2589 <<
2590 <<
2591 }; <<
2592 }; <<
2593 <<
2594 port@4 { <<
2595 reg = <<
2596 apss_ <<
2597 <<
2598 <<
2599 }; <<
2600 }; <<
2601 <<
2602 port@5 { <<
2603 reg = <<
2604 apss_ <<
2605 <<
2606 <<
2607 }; <<
2608 }; <<
2609 <<
2610 port@6 { <<
2611 reg = <<
2612 apss_ <<
2613 <<
2614 <<
2615 }; <<
2616 }; <<
2617 <<
2618 port@7 { <<
2619 reg = <<
2620 apss_ <<
2621 <<
2622 <<
2623 }; <<
2624 }; <<
2625 }; <<
2626 }; <<
2627 <<
2628 funnel@6810000 { <<
2629 compatible = "arm,cor <<
2630 reg = <0x0 0x6810000 <<
2631 <<
2632 clocks = <&aoss_qmp>; <<
2633 clock-names = "apb_pc <<
2634 <<
2635 out-ports { <<
2636 port { <<
2637 apss_ <<
2638 <<
2639 <<
2640 }; <<
2641 }; <<
2642 }; <<
2643 <<
2644 in-ports { <<
2645 #address-cell <<
2646 #size-cells = <<
2647 <<
2648 port@0 { <<
2649 reg = <<
2650 apss_ <<
2651 <<
2652 <<
2653 }; <<
2654 }; <<
2655 <<
2656 port@3 { <<
2657 reg = <<
2658 apss_ <<
2659 <<
2660 <<
2661 }; <<
2662 }; <<
2663 }; <<
2664 }; <<
2665 <<
2666 tpdm@6860000 { <<
2667 compatible = "qcom,co <<
2668 reg = <0x0 0x6860000 <<
2669 <<
2670 clocks = <&aoss_qmp>; <<
2671 clock-names = "apb_pc <<
2672 <<
2673 qcom,cmb-element-bits <<
2674 qcom,cmb-msrs-num = < <<
2675 <<
2676 out-ports { <<
2677 port { <<
2678 apss_ <<
2679 <<
2680 <<
2681 }; <<
2682 }; <<
2683 }; <<
2684 }; <<
2685 <<
2686 tpdm@6861000 { <<
2687 compatible = "qcom,co <<
2688 reg = <0x0 0x6861000 <<
2689 <<
2690 clocks = <&aoss_qmp>; <<
2691 clock-names = "apb_pc <<
2692 <<
2693 qcom,dsb-element-bits <<
2694 qcom,dsb-msrs-num = < <<
2695 <<
2696 out-ports { <<
2697 port { <<
2698 apss_ <<
2699 <<
2700 <<
2701 }; <<
2702 }; <<
2703 }; <<
2704 }; <<
2705 <<
2706 tpda@6863000 { <<
2707 compatible = "qcom,co <<
2708 reg = <0x0 0x6863000 <<
2709 <<
2710 clocks = <&aoss_qmp>; <<
2711 clock-names = "apb_pc <<
2712 <<
2713 out-ports { <<
2714 port { <<
2715 apss_ <<
2716 <<
2717 <<
2718 }; <<
2719 }; <<
2720 }; <<
2721 <<
2722 in-ports { <<
2723 #address-cell <<
2724 #size-cells = <<
2725 <<
2726 port@0 { <<
2727 reg = <<
2728 apss_ <<
2729 <<
2730 <<
2731 }; <<
2732 }; <<
2733 <<
2734 port@1 { <<
2735 reg = <<
2736 apss_ <<
2737 <<
2738 <<
2739 }; <<
2740 }; <<
2741 <<
2742 port@2 { <<
2743 reg = <<
2744 apss_ <<
2745 <<
2746 <<
2747 }; <<
2748 }; <<
2749 <<
2750 port@3 { <<
2751 reg = <<
2752 apss_ <<
2753 <<
2754 <<
2755 }; <<
2756 }; <<
2757 <<
2758 port@4 { <<
2759 reg = <<
2760 apss_ <<
2761 <<
2762 <<
2763 }; <<
2764 }; <<
2765 }; <<
2766 }; <<
2767 <<
2768 tpdm@68a0000 { <<
2769 compatible = "qcom,co <<
2770 reg = <0x0 0x68a0000 <<
2771 <<
2772 clocks = <&aoss_qmp>; <<
2773 clock-names = "apb_pc <<
2774 <<
2775 qcom,cmb-element-bits <<
2776 qcom,cmb-msrs-num = < <<
2777 <<
2778 out-ports { <<
2779 port { <<
2780 apss_ <<
2781 <<
2782 <<
2783 }; <<
2784 }; <<
2785 }; <<
2786 }; <<
2787 <<
2788 tpdm@68b0000 { <<
2789 compatible = "qcom,co <<
2790 reg = <0x0 0x68b0000 <<
2791 <<
2792 clocks = <&aoss_qmp>; <<
2793 clock-names = "apb_pc <<
2794 <<
2795 qcom,cmb-element-bits <<
2796 qcom,cmb-msrs-num = < <<
2797 <<
2798 out-ports { <<
2799 port { <<
2800 apss_ <<
2801 <<
2802 <<
2803 }; <<
2804 }; <<
2805 }; <<
2806 }; <<
2807 <<
2808 tpdm@68c0000 { <<
2809 compatible = "qcom,co <<
2810 reg = <0x0 0x68c0000 <<
2811 <<
2812 clocks = <&aoss_qmp>; <<
2813 clock-names = "apb_pc <<
2814 <<
2815 qcom,dsb-element-bits <<
2816 qcom,dsb-msrs-num = < <<
2817 <<
2818 out-ports { <<
2819 port { <<
2820 apss_ <<
2821 <<
2822 <<
2823 }; <<
2824 }; <<
2825 }; <<
2826 }; <<
2827 <<
2828 usb_0_hsphy: phy@88e4000 { 1557 usb_0_hsphy: phy@88e4000 {
2829 compatible = "qcom,sa 1558 compatible = "qcom,sa8775p-usb-hs-phy",
2830 "qcom,us 1559 "qcom,usb-snps-hs-5nm-phy";
2831 reg = <0 0x088e4000 0 1560 reg = <0 0x088e4000 0 0x120>;
2832 clocks = <&rpmhcc RPM 1561 clocks = <&rpmhcc RPMH_CXO_CLK>;
2833 clock-names = "ref"; 1562 clock-names = "ref";
2834 resets = <&gcc GCC_US 1563 resets = <&gcc GCC_USB2_PHY_PRIM_BCR>;
2835 1564
2836 #phy-cells = <0>; 1565 #phy-cells = <0>;
2837 1566
2838 status = "disabled"; 1567 status = "disabled";
2839 }; 1568 };
2840 1569
2841 usb_0_qmpphy: phy@88e8000 { 1570 usb_0_qmpphy: phy@88e8000 {
2842 compatible = "qcom,sa 1571 compatible = "qcom,sa8775p-qmp-usb3-uni-phy";
2843 reg = <0 0x088e8000 0 1572 reg = <0 0x088e8000 0 0x2000>;
2844 1573
2845 clocks = <&gcc GCC_US 1574 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2846 <&gcc GCC_US 1575 <&gcc GCC_USB_CLKREF_EN>,
2847 <&gcc GCC_US 1576 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
2848 <&gcc GCC_US 1577 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2849 clock-names = "aux", 1578 clock-names = "aux", "ref", "com_aux", "pipe";
2850 1579
2851 resets = <&gcc GCC_US 1580 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
2852 <&gcc GCC_US 1581 <&gcc GCC_USB3PHY_PHY_PRIM_BCR>;
2853 reset-names = "phy", 1582 reset-names = "phy", "phy_phy";
2854 1583
2855 power-domains = <&gcc 1584 power-domains = <&gcc USB30_PRIM_GDSC>;
2856 1585
2857 #clock-cells = <0>; 1586 #clock-cells = <0>;
2858 clock-output-names = 1587 clock-output-names = "usb3_prim_phy_pipe_clk_src";
2859 1588
2860 #phy-cells = <0>; 1589 #phy-cells = <0>;
2861 1590
2862 status = "disabled"; 1591 status = "disabled";
2863 }; 1592 };
2864 1593
2865 usb_0: usb@a6f8800 { 1594 usb_0: usb@a6f8800 {
2866 compatible = "qcom,sa 1595 compatible = "qcom,sa8775p-dwc3", "qcom,dwc3";
2867 reg = <0 0x0a6f8800 0 1596 reg = <0 0x0a6f8800 0 0x400>;
2868 #address-cells = <2>; 1597 #address-cells = <2>;
2869 #size-cells = <2>; 1598 #size-cells = <2>;
2870 ranges; 1599 ranges;
2871 1600
2872 clocks = <&gcc GCC_CF 1601 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
2873 <&gcc GCC_US 1602 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
2874 <&gcc GCC_AG 1603 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
2875 <&gcc GCC_US 1604 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
2876 <&gcc GCC_US 1605 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
2877 clock-names = "cfg_no 1606 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi";
2878 1607
2879 assigned-clocks = <&g 1608 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2880 <&g 1609 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
2881 assigned-clock-rates 1610 assigned-clock-rates = <19200000>, <200000000>;
2882 1611
2883 interrupts-extended = 1612 interrupts-extended = <&intc GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>,
2884 <<
2885 1613 <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
2886 1614 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
2887 1615 <&pdc 12 IRQ_TYPE_LEVEL_HIGH>;
2888 interrupt-names = "pw 1616 interrupt-names = "pwr_event",
2889 "hs <<
2890 "dp 1617 "dp_hs_phy_irq",
2891 "dm 1618 "dm_hs_phy_irq",
2892 "ss 1619 "ss_phy_irq";
2893 1620
2894 power-domains = <&gcc 1621 power-domains = <&gcc USB30_PRIM_GDSC>;
2895 required-opps = <&rpm 1622 required-opps = <&rpmhpd_opp_nom>;
2896 1623
2897 resets = <&gcc GCC_US 1624 resets = <&gcc GCC_USB30_PRIM_BCR>;
2898 1625
2899 interconnects = <&agg 1626 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
2900 <&gem 1627 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
2901 interconnect-names = 1628 interconnect-names = "usb-ddr", "apps-usb";
2902 1629
2903 wakeup-source; 1630 wakeup-source;
2904 1631
2905 status = "disabled"; 1632 status = "disabled";
2906 1633
2907 usb_0_dwc3: usb@a6000 1634 usb_0_dwc3: usb@a600000 {
2908 compatible = 1635 compatible = "snps,dwc3";
2909 reg = <0 0x0a 1636 reg = <0 0x0a600000 0 0xe000>;
2910 interrupts = 1637 interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>;
2911 iommus = <&ap 1638 iommus = <&apps_smmu 0x080 0x0>;
2912 phys = <&usb_ 1639 phys = <&usb_0_hsphy>, <&usb_0_qmpphy>;
2913 phy-names = " 1640 phy-names = "usb2-phy", "usb3-phy";
2914 }; 1641 };
2915 }; 1642 };
2916 1643
2917 usb_1_hsphy: phy@88e6000 { 1644 usb_1_hsphy: phy@88e6000 {
2918 compatible = "qcom,sa 1645 compatible = "qcom,sa8775p-usb-hs-phy",
2919 "qcom,us 1646 "qcom,usb-snps-hs-5nm-phy";
2920 reg = <0 0x088e6000 0 1647 reg = <0 0x088e6000 0 0x120>;
2921 clocks = <&gcc GCC_US 1648 clocks = <&gcc GCC_USB_CLKREF_EN>;
2922 clock-names = "ref"; 1649 clock-names = "ref";
2923 resets = <&gcc GCC_US 1650 resets = <&gcc GCC_USB2_PHY_SEC_BCR>;
2924 1651
2925 #phy-cells = <0>; 1652 #phy-cells = <0>;
2926 1653
2927 status = "disabled"; 1654 status = "disabled";
2928 }; 1655 };
2929 1656
2930 usb_1_qmpphy: phy@88ea000 { 1657 usb_1_qmpphy: phy@88ea000 {
2931 compatible = "qcom,sa 1658 compatible = "qcom,sa8775p-qmp-usb3-uni-phy";
2932 reg = <0 0x088ea000 0 1659 reg = <0 0x088ea000 0 0x2000>;
2933 1660
2934 clocks = <&gcc GCC_US 1661 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
2935 <&gcc GCC_US 1662 <&gcc GCC_USB_CLKREF_EN>,
2936 <&gcc GCC_US 1663 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
2937 <&gcc GCC_US 1664 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
2938 clock-names = "aux", 1665 clock-names = "aux", "ref", "com_aux", "pipe";
2939 1666
2940 resets = <&gcc GCC_US 1667 resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
2941 <&gcc GCC_US 1668 <&gcc GCC_USB3PHY_PHY_SEC_BCR>;
2942 reset-names = "phy", 1669 reset-names = "phy", "phy_phy";
2943 1670
2944 power-domains = <&gcc 1671 power-domains = <&gcc USB30_SEC_GDSC>;
2945 1672
2946 #clock-cells = <0>; 1673 #clock-cells = <0>;
2947 clock-output-names = 1674 clock-output-names = "usb3_sec_phy_pipe_clk_src";
2948 1675
2949 #phy-cells = <0>; 1676 #phy-cells = <0>;
2950 1677
2951 status = "disabled"; 1678 status = "disabled";
2952 }; 1679 };
2953 1680
2954 usb_1: usb@a8f8800 { 1681 usb_1: usb@a8f8800 {
2955 compatible = "qcom,sa 1682 compatible = "qcom,sa8775p-dwc3", "qcom,dwc3";
2956 reg = <0 0x0a8f8800 0 1683 reg = <0 0x0a8f8800 0 0x400>;
2957 #address-cells = <2>; 1684 #address-cells = <2>;
2958 #size-cells = <2>; 1685 #size-cells = <2>;
2959 ranges; 1686 ranges;
2960 1687
2961 clocks = <&gcc GCC_CF 1688 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
2962 <&gcc GCC_US 1689 <&gcc GCC_USB30_SEC_MASTER_CLK>,
2963 <&gcc GCC_AG 1690 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
2964 <&gcc GCC_US 1691 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
2965 <&gcc GCC_US 1692 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>;
2966 clock-names = "cfg_no 1693 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi";
2967 1694
2968 assigned-clocks = <&g 1695 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2969 <&g 1696 <&gcc GCC_USB30_SEC_MASTER_CLK>;
2970 assigned-clock-rates 1697 assigned-clock-rates = <19200000>, <200000000>;
2971 1698
2972 interrupts-extended = 1699 interrupts-extended = <&intc GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
2973 <<
2974 1700 <&pdc 8 IRQ_TYPE_EDGE_BOTH>,
2975 1701 <&pdc 7 IRQ_TYPE_EDGE_BOTH>,
2976 1702 <&pdc 13 IRQ_TYPE_LEVEL_HIGH>;
2977 interrupt-names = "pw 1703 interrupt-names = "pwr_event",
2978 "hs <<
2979 "dp 1704 "dp_hs_phy_irq",
2980 "dm 1705 "dm_hs_phy_irq",
2981 "ss 1706 "ss_phy_irq";
2982 1707
2983 power-domains = <&gcc 1708 power-domains = <&gcc USB30_SEC_GDSC>;
2984 required-opps = <&rpm 1709 required-opps = <&rpmhpd_opp_nom>;
2985 1710
2986 resets = <&gcc GCC_US 1711 resets = <&gcc GCC_USB30_SEC_BCR>;
2987 1712
2988 interconnects = <&agg 1713 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>,
2989 <&gem 1714 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
2990 interconnect-names = 1715 interconnect-names = "usb-ddr", "apps-usb";
2991 1716
2992 wakeup-source; 1717 wakeup-source;
2993 1718
2994 status = "disabled"; 1719 status = "disabled";
2995 1720
2996 usb_1_dwc3: usb@a8000 1721 usb_1_dwc3: usb@a800000 {
2997 compatible = 1722 compatible = "snps,dwc3";
2998 reg = <0 0x0a 1723 reg = <0 0x0a800000 0 0xe000>;
2999 interrupts = 1724 interrupts = <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>;
3000 iommus = <&ap 1725 iommus = <&apps_smmu 0x0a0 0x0>;
3001 phys = <&usb_ 1726 phys = <&usb_1_hsphy>, <&usb_1_qmpphy>;
3002 phy-names = " 1727 phy-names = "usb2-phy", "usb3-phy";
3003 }; 1728 };
3004 }; 1729 };
3005 1730
3006 usb_2_hsphy: phy@88e7000 { 1731 usb_2_hsphy: phy@88e7000 {
3007 compatible = "qcom,sa 1732 compatible = "qcom,sa8775p-usb-hs-phy",
3008 "qcom,us 1733 "qcom,usb-snps-hs-5nm-phy";
3009 reg = <0 0x088e7000 0 1734 reg = <0 0x088e7000 0 0x120>;
3010 clocks = <&gcc GCC_US 1735 clocks = <&gcc GCC_USB_CLKREF_EN>;
3011 clock-names = "ref"; 1736 clock-names = "ref";
3012 resets = <&gcc GCC_US 1737 resets = <&gcc GCC_USB3_PHY_TERT_BCR>;
3013 1738
3014 #phy-cells = <0>; 1739 #phy-cells = <0>;
3015 1740
3016 status = "disabled"; 1741 status = "disabled";
3017 }; 1742 };
3018 1743
3019 usb_2: usb@a4f8800 { 1744 usb_2: usb@a4f8800 {
3020 compatible = "qcom,sa 1745 compatible = "qcom,sa8775p-dwc3", "qcom,dwc3";
3021 reg = <0 0x0a4f8800 0 1746 reg = <0 0x0a4f8800 0 0x400>;
3022 #address-cells = <2>; 1747 #address-cells = <2>;
3023 #size-cells = <2>; 1748 #size-cells = <2>;
3024 ranges; 1749 ranges;
3025 1750
3026 clocks = <&gcc GCC_CF 1751 clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>,
3027 <&gcc GCC_US 1752 <&gcc GCC_USB20_MASTER_CLK>,
3028 <&gcc GCC_AG 1753 <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>,
3029 <&gcc GCC_US 1754 <&gcc GCC_USB20_SLEEP_CLK>,
3030 <&gcc GCC_US 1755 <&gcc GCC_USB20_MOCK_UTMI_CLK>;
3031 clock-names = "cfg_no 1756 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi";
3032 1757
3033 assigned-clocks = <&g 1758 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
3034 <&g 1759 <&gcc GCC_USB20_MASTER_CLK>;
3035 assigned-clock-rates 1760 assigned-clock-rates = <19200000>, <200000000>;
3036 1761
3037 interrupts-extended = 1762 interrupts-extended = <&intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
3038 <<
3039 1763 <&pdc 10 IRQ_TYPE_EDGE_BOTH>,
3040 1764 <&pdc 9 IRQ_TYPE_EDGE_BOTH>;
3041 interrupt-names = "pw 1765 interrupt-names = "pwr_event",
3042 "hs <<
3043 "dp 1766 "dp_hs_phy_irq",
3044 "dm 1767 "dm_hs_phy_irq";
3045 1768
3046 power-domains = <&gcc 1769 power-domains = <&gcc USB20_PRIM_GDSC>;
3047 required-opps = <&rpm 1770 required-opps = <&rpmhpd_opp_nom>;
3048 1771
3049 resets = <&gcc GCC_US 1772 resets = <&gcc GCC_USB20_PRIM_BCR>;
3050 1773
3051 interconnects = <&agg 1774 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>,
3052 <&gem 1775 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB2 0>;
3053 interconnect-names = 1776 interconnect-names = "usb-ddr", "apps-usb";
3054 1777
3055 wakeup-source; 1778 wakeup-source;
3056 1779
3057 status = "disabled"; 1780 status = "disabled";
3058 1781
3059 usb_2_dwc3: usb@a4000 1782 usb_2_dwc3: usb@a400000 {
3060 compatible = 1783 compatible = "snps,dwc3";
3061 reg = <0 0x0a 1784 reg = <0 0x0a400000 0 0xe000>;
3062 interrupts = 1785 interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>;
3063 iommus = <&ap 1786 iommus = <&apps_smmu 0x020 0x0>;
3064 phys = <&usb_ 1787 phys = <&usb_2_hsphy>;
3065 phy-names = " 1788 phy-names = "usb2-phy";
3066 }; 1789 };
3067 }; 1790 };
3068 1791
3069 tcsr_mutex: hwlock@1f40000 { 1792 tcsr_mutex: hwlock@1f40000 {
3070 compatible = "qcom,tc 1793 compatible = "qcom,tcsr-mutex";
3071 reg = <0x0 0x01f40000 1794 reg = <0x0 0x01f40000 0x0 0x20000>;
3072 #hwlock-cells = <1>; 1795 #hwlock-cells = <1>;
3073 }; 1796 };
3074 1797
3075 gpucc: clock-controller@3d900 1798 gpucc: clock-controller@3d90000 {
3076 compatible = "qcom,sa 1799 compatible = "qcom,sa8775p-gpucc";
3077 reg = <0x0 0x03d90000 1800 reg = <0x0 0x03d90000 0x0 0xa000>;
3078 clocks = <&rpmhcc RPM 1801 clocks = <&rpmhcc RPMH_CXO_CLK>,
3079 <&gcc GCC_GP 1802 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
3080 <&gcc GCC_GP 1803 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
3081 clock-names = "bi_tcx 1804 clock-names = "bi_tcxo",
3082 "gcc_gp 1805 "gcc_gpu_gpll0_clk_src",
3083 "gcc_gp 1806 "gcc_gpu_gpll0_div_clk_src";
3084 #clock-cells = <1>; 1807 #clock-cells = <1>;
3085 #reset-cells = <1>; 1808 #reset-cells = <1>;
3086 #power-domain-cells = 1809 #power-domain-cells = <1>;
3087 }; 1810 };
3088 1811
3089 adreno_smmu: iommu@3da0000 { 1812 adreno_smmu: iommu@3da0000 {
3090 compatible = "qcom,sa 1813 compatible = "qcom,sa8775p-smmu-500", "qcom,adreno-smmu",
3091 "qcom,sm 1814 "qcom,smmu-500", "arm,mmu-500";
3092 reg = <0x0 0x03da0000 1815 reg = <0x0 0x03da0000 0x0 0x20000>;
3093 #iommu-cells = <2>; 1816 #iommu-cells = <2>;
3094 #global-interrupts = 1817 #global-interrupts = <2>;
3095 dma-coherent; 1818 dma-coherent;
3096 power-domains = <&gpu 1819 power-domains = <&gpucc GPU_CC_CX_GDSC>;
3097 clocks = <&gcc GCC_GP 1820 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
3098 <&gcc GCC_GP 1821 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
3099 <&gpucc GPU_ 1822 <&gpucc GPU_CC_AHB_CLK>,
3100 <&gpucc GPU_ 1823 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
3101 <&gpucc GPU_ 1824 <&gpucc GPU_CC_CX_GMU_CLK>,
3102 <&gpucc GPU_ 1825 <&gpucc GPU_CC_HUB_CX_INT_CLK>,
3103 <&gpucc GPU_ 1826 <&gpucc GPU_CC_HUB_AON_CLK>;
3104 clock-names = "gcc_gp 1827 clock-names = "gcc_gpu_memnoc_gfx_clk",
3105 "gcc_gp 1828 "gcc_gpu_snoc_dvm_gfx_clk",
3106 "gpu_cc 1829 "gpu_cc_ahb_clk",
3107 "gpu_cc 1830 "gpu_cc_hlos1_vote_gpu_smmu_clk",
3108 "gpu_cc 1831 "gpu_cc_cx_gmu_clk",
3109 "gpu_cc 1832 "gpu_cc_hub_cx_int_clk",
3110 "gpu_cc 1833 "gpu_cc_hub_aon_clk";
3111 interrupts = <GIC_SPI 1834 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
3112 <GIC_SPI 1835 <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
3113 <GIC_SPI 1836 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
3114 <GIC_SPI 1837 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
3115 <GIC_SPI 1838 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
3116 <GIC_SPI 1839 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
3117 <GIC_SPI 1840 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
3118 <GIC_SPI 1841 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
3119 <GIC_SPI 1842 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
3120 <GIC_SPI 1843 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
3121 <GIC_SPI 1844 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
3122 <GIC_SPI 1845 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>;
3123 }; 1846 };
3124 1847
3125 serdes0: phy@8901000 { 1848 serdes0: phy@8901000 {
3126 compatible = "qcom,sa 1849 compatible = "qcom,sa8775p-dwmac-sgmii-phy";
3127 reg = <0x0 0x08901000 1850 reg = <0x0 0x08901000 0x0 0xe10>;
3128 clocks = <&gcc GCC_SG 1851 clocks = <&gcc GCC_SGMI_CLKREF_EN>;
3129 clock-names = "sgmi_r 1852 clock-names = "sgmi_ref";
3130 #phy-cells = <0>; 1853 #phy-cells = <0>;
3131 status = "disabled"; 1854 status = "disabled";
3132 }; 1855 };
3133 1856
3134 serdes1: phy@8902000 { 1857 serdes1: phy@8902000 {
3135 compatible = "qcom,sa 1858 compatible = "qcom,sa8775p-dwmac-sgmii-phy";
3136 reg = <0x0 0x08902000 1859 reg = <0x0 0x08902000 0x0 0xe10>;
3137 clocks = <&gcc GCC_SG 1860 clocks = <&gcc GCC_SGMI_CLKREF_EN>;
3138 clock-names = "sgmi_r 1861 clock-names = "sgmi_ref";
3139 #phy-cells = <0>; 1862 #phy-cells = <0>;
3140 status = "disabled"; 1863 status = "disabled";
3141 }; 1864 };
3142 1865
3143 pmu@9091000 { <<
3144 compatible = "qcom,sa <<
3145 reg = <0x0 0x9091000 <<
3146 interrupts = <GIC_SPI <<
3147 interconnects = <&mc_ <<
3148 &mc_ <<
3149 <<
3150 operating-points-v2 = <<
3151 <<
3152 llcc_bwmon_opp_table: <<
3153 compatible = <<
3154 <<
3155 opp-0 { <<
3156 opp-p <<
3157 }; <<
3158 <<
3159 opp-1 { <<
3160 opp-p <<
3161 }; <<
3162 <<
3163 opp-2 { <<
3164 opp-p <<
3165 }; <<
3166 <<
3167 opp-3 { <<
3168 opp-p <<
3169 }; <<
3170 <<
3171 opp-4 { <<
3172 opp-p <<
3173 }; <<
3174 <<
3175 opp-5 { <<
3176 opp-p <<
3177 }; <<
3178 <<
3179 opp-6 { <<
3180 opp-p <<
3181 }; <<
3182 <<
3183 opp-7 { <<
3184 opp-p <<
3185 }; <<
3186 <<
3187 opp-8 { <<
3188 opp-p <<
3189 }; <<
3190 <<
3191 opp-9 { <<
3192 opp-p <<
3193 }; <<
3194 }; <<
3195 }; <<
3196 <<
3197 pmu@90b5400 { <<
3198 compatible = "qcom,sa <<
3199 reg = <0x0 0x90b5400 <<
3200 interrupts = <GIC_SPI <<
3201 interconnects = <&gem <<
3202 &gem <<
3203 <<
3204 operating-points-v2 = <<
3205 <<
3206 cpu_bwmon_opp_table: <<
3207 compatible = <<
3208 <<
3209 opp-0 { <<
3210 opp-p <<
3211 }; <<
3212 <<
3213 opp-1 { <<
3214 opp-p <<
3215 }; <<
3216 <<
3217 opp-2 { <<
3218 opp-p <<
3219 }; <<
3220 <<
3221 opp-3 { <<
3222 opp-p <<
3223 }; <<
3224 }; <<
3225 <<
3226 }; <<
3227 <<
3228 pmu@90b6400 { <<
3229 compatible = "qcom,sa <<
3230 reg = <0x0 0x90b6400 <<
3231 interrupts = <GIC_SPI <<
3232 interconnects = <&gem <<
3233 &gem <<
3234 <<
3235 operating-points-v2 = <<
3236 }; <<
3237 <<
3238 llcc: system-cache-controller <<
3239 compatible = "qcom,sa <<
3240 reg = <0x0 0x09200000 <<
3241 <0x0 0x09300000 <<
3242 <0x0 0x09400000 <<
3243 <0x0 0x09500000 <<
3244 <0x0 0x09600000 <<
3245 <0x0 0x09700000 <<
3246 <0x0 0x09a00000 <<
3247 reg-names = "llcc0_ba <<
3248 "llcc1_ba <<
3249 "llcc2_ba <<
3250 "llcc3_ba <<
3251 "llcc4_ba <<
3252 "llcc5_ba <<
3253 "llcc_bro <<
3254 interrupts = <GIC_SPI <<
3255 }; <<
3256 <<
3257 pdc: interrupt-controller@b22 1866 pdc: interrupt-controller@b220000 {
3258 compatible = "qcom,sa 1867 compatible = "qcom,sa8775p-pdc", "qcom,pdc";
3259 reg = <0x0 0x0b220000 1868 reg = <0x0 0x0b220000 0x0 0x30000>,
3260 <0x0 0x17c000f0 1869 <0x0 0x17c000f0 0x0 0x64>;
3261 qcom,pdc-ranges = <0 1870 qcom,pdc-ranges = <0 480 40>,
3262 <40 1871 <40 140 14>,
3263 <54 1872 <54 263 1>,
3264 <55 1873 <55 306 4>,
3265 <59 1874 <59 312 3>,
3266 <62 1875 <62 374 2>,
3267 <64 1876 <64 434 2>,
3268 <66 1877 <66 438 2>,
3269 <70 1878 <70 520 1>,
3270 <73 1879 <73 523 1>,
3271 <11 1880 <118 568 6>,
3272 <12 1881 <124 609 3>,
3273 <15 1882 <159 638 1>,
3274 <16 1883 <160 720 3>,
3275 <16 1884 <169 728 30>,
3276 <19 1885 <199 416 2>,
3277 <20 1886 <201 449 1>,
3278 <20 1887 <202 89 1>,
3279 <20 1888 <203 451 1>,
3280 <20 1889 <204 462 1>,
3281 <20 1890 <205 264 1>,
3282 <20 1891 <206 579 1>,
3283 <20 1892 <207 653 1>,
3284 <20 1893 <208 656 1>,
3285 <20 1894 <209 659 1>,
3286 <21 1895 <210 122 1>,
3287 <21 1896 <211 699 1>,
3288 <21 1897 <212 705 1>,
3289 <21 1898 <213 450 1>,
3290 <21 1899 <214 643 2>,
3291 <21 1900 <216 646 5>,
3292 <22 1901 <221 390 5>,
3293 <22 1902 <226 700 2>,
3294 <22 1903 <228 440 1>,
3295 <22 1904 <229 663 1>,
3296 <23 1905 <230 524 2>,
3297 <23 1906 <232 612 3>,
3298 <23 1907 <235 723 5>;
3299 #interrupt-cells = <2 1908 #interrupt-cells = <2>;
3300 interrupt-parent = <& 1909 interrupt-parent = <&intc>;
3301 interrupt-controller; 1910 interrupt-controller;
3302 }; 1911 };
3303 1912
3304 tsens2: thermal-sensor@c25100 <<
3305 compatible = "qcom,sa <<
3306 reg = <0x0 0x0c251000 <<
3307 <0x0 0x0c224000 <<
3308 interrupts = <GIC_SPI <<
3309 <GIC_SPI <<
3310 #qcom,sensors = <13>; <<
3311 interrupt-names = "up <<
3312 #thermal-sensor-cells <<
3313 }; <<
3314 <<
3315 tsens3: thermal-sensor@c25200 <<
3316 compatible = "qcom,sa <<
3317 reg = <0x0 0x0c252000 <<
3318 <0x0 0x0c225000 <<
3319 interrupts = <GIC_SPI <<
3320 <GIC_SPI <<
3321 #qcom,sensors = <13>; <<
3322 interrupt-names = "up <<
3323 #thermal-sensor-cells <<
3324 }; <<
3325 <<
3326 tsens0: thermal-sensor@c26300 <<
3327 compatible = "qcom,sa <<
3328 reg = <0x0 0x0c263000 <<
3329 <0x0 0x0c222000 <<
3330 interrupts = <GIC_SPI <<
3331 <GIC_SPI <<
3332 #qcom,sensors = <12>; <<
3333 interrupt-names = "up <<
3334 #thermal-sensor-cells <<
3335 }; <<
3336 <<
3337 tsens1: thermal-sensor@c26500 <<
3338 compatible = "qcom,sa <<
3339 reg = <0x0 0x0c265000 <<
3340 <0x0 0x0c223000 <<
3341 interrupts = <GIC_SPI <<
3342 <GIC_SPI <<
3343 #qcom,sensors = <12>; <<
3344 interrupt-names = "up <<
3345 #thermal-sensor-cells <<
3346 }; <<
3347 <<
3348 aoss_qmp: power-management@c3 1913 aoss_qmp: power-management@c300000 {
3349 compatible = "qcom,sa 1914 compatible = "qcom,sa8775p-aoss-qmp", "qcom,aoss-qmp";
3350 reg = <0x0 0x0c300000 1915 reg = <0x0 0x0c300000 0x0 0x400>;
3351 interrupts-extended = 1916 interrupts-extended = <&ipcc IPCC_CLIENT_AOP
3352 1917 IPCC_MPROC_SIGNAL_GLINK_QMP
3353 1918 IRQ_TYPE_EDGE_RISING>;
3354 mboxes = <&ipcc IPCC_ 1919 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
3355 #clock-cells = <0>; 1920 #clock-cells = <0>;
3356 }; 1921 };
3357 1922
3358 sram@c3f0000 { <<
3359 compatible = "qcom,rp <<
3360 reg = <0x0 0x0c3f0000 <<
3361 }; <<
3362 <<
3363 spmi_bus: spmi@c440000 { 1923 spmi_bus: spmi@c440000 {
3364 compatible = "qcom,sp 1924 compatible = "qcom,spmi-pmic-arb";
3365 reg = <0x0 0x0c440000 1925 reg = <0x0 0x0c440000 0x0 0x1100>,
3366 <0x0 0x0c600000 1926 <0x0 0x0c600000 0x0 0x2000000>,
3367 <0x0 0x0e600000 1927 <0x0 0x0e600000 0x0 0x100000>,
3368 <0x0 0x0e700000 1928 <0x0 0x0e700000 0x0 0xa0000>,
3369 <0x0 0x0c40a000 1929 <0x0 0x0c40a000 0x0 0x26000>;
3370 reg-names = "core", 1930 reg-names = "core",
3371 "chnls", 1931 "chnls",
3372 "obsrvr", 1932 "obsrvr",
3373 "intr", 1933 "intr",
3374 "cnfg"; 1934 "cnfg";
3375 qcom,channel = <0>; 1935 qcom,channel = <0>;
3376 qcom,ee = <0>; 1936 qcom,ee = <0>;
3377 interrupts-extended = 1937 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3378 interrupt-names = "pe 1938 interrupt-names = "periph_irq";
3379 interrupt-controller; 1939 interrupt-controller;
3380 #interrupt-cells = <4 1940 #interrupt-cells = <4>;
3381 #address-cells = <2>; 1941 #address-cells = <2>;
3382 #size-cells = <0>; 1942 #size-cells = <0>;
3383 }; 1943 };
3384 1944
3385 tlmm: pinctrl@f000000 { 1945 tlmm: pinctrl@f000000 {
3386 compatible = "qcom,sa 1946 compatible = "qcom,sa8775p-tlmm";
3387 reg = <0x0 0x0f000000 1947 reg = <0x0 0x0f000000 0x0 0x1000000>;
3388 interrupts = <GIC_SPI 1948 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
3389 gpio-controller; 1949 gpio-controller;
3390 #gpio-cells = <2>; 1950 #gpio-cells = <2>;
3391 interrupt-controller; 1951 interrupt-controller;
3392 #interrupt-cells = <2 1952 #interrupt-cells = <2>;
3393 gpio-ranges = <&tlmm 1953 gpio-ranges = <&tlmm 0 0 149>;
3394 wakeup-parent = <&pdc 1954 wakeup-parent = <&pdc>;
3395 }; 1955 };
3396 1956
3397 sram: sram@146d8000 { <<
3398 compatible = "qcom,sa <<
3399 reg = <0x0 0x146d8000 <<
3400 ranges = <0x0 0x0 0x1 <<
3401 <<
3402 #address-cells = <1>; <<
3403 #size-cells = <1>; <<
3404 <<
3405 pil-reloc@94c { <<
3406 compatible = <<
3407 reg = <0x94c <<
3408 }; <<
3409 }; <<
3410 <<
3411 apps_smmu: iommu@15000000 { 1957 apps_smmu: iommu@15000000 {
3412 compatible = "qcom,sa 1958 compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500";
3413 reg = <0x0 0x15000000 1959 reg = <0x0 0x15000000 0x0 0x100000>;
3414 #iommu-cells = <2>; 1960 #iommu-cells = <2>;
3415 #global-interrupts = 1961 #global-interrupts = <2>;
3416 dma-coherent; <<
3417 1962
3418 interrupts = <GIC_SPI 1963 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
3419 <GIC_SPI 1964 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
3420 <GIC_SPI 1965 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
3421 <GIC_SPI 1966 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
3422 <GIC_SPI 1967 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
3423 <GIC_SPI 1968 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
3424 <GIC_SPI 1969 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
3425 <GIC_SPI 1970 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
3426 <GIC_SPI 1971 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
3427 <GIC_SPI 1972 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
3428 <GIC_SPI 1973 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
3429 <GIC_SPI 1974 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
3430 <GIC_SPI 1975 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
3431 <GIC_SPI 1976 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
3432 <GIC_SPI 1977 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
3433 <GIC_SPI 1978 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
3434 <GIC_SPI 1979 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
3435 <GIC_SPI 1980 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
3436 <GIC_SPI 1981 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
3437 <GIC_SPI 1982 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
3438 <GIC_SPI 1983 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
3439 <GIC_SPI 1984 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
3440 <GIC_SPI 1985 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
3441 <GIC_SPI 1986 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
3442 <GIC_SPI 1987 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
3443 <GIC_SPI 1988 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
3444 <GIC_SPI 1989 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
3445 <GIC_SPI 1990 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
3446 <GIC_SPI 1991 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
3447 <GIC_SPI 1992 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
3448 <GIC_SPI 1993 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
3449 <GIC_SPI 1994 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
3450 <GIC_SPI 1995 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
3451 <GIC_SPI 1996 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
3452 <GIC_SPI 1997 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
3453 <GIC_SPI 1998 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
3454 <GIC_SPI 1999 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
3455 <GIC_SPI 2000 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
3456 <GIC_SPI 2001 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
3457 <GIC_SPI 2002 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
3458 <GIC_SPI 2003 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
3459 <GIC_SPI 2004 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
3460 <GIC_SPI 2005 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
3461 <GIC_SPI 2006 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
3462 <GIC_SPI 2007 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
3463 <GIC_SPI 2008 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
3464 <GIC_SPI 2009 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
3465 <GIC_SPI 2010 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
3466 <GIC_SPI 2011 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
3467 <GIC_SPI 2012 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
3468 <GIC_SPI 2013 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
3469 <GIC_SPI 2014 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
3470 <GIC_SPI 2015 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
3471 <GIC_SPI 2016 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
3472 <GIC_SPI 2017 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
3473 <GIC_SPI 2018 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
3474 <GIC_SPI 2019 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
3475 <GIC_SPI 2020 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
3476 <GIC_SPI 2021 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
3477 <GIC_SPI 2022 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
3478 <GIC_SPI 2023 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
3479 <GIC_SPI 2024 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
3480 <GIC_SPI 2025 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
3481 <GIC_SPI 2026 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
3482 <GIC_SPI 2027 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
3483 <GIC_SPI 2028 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
3484 <GIC_SPI 2029 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
3485 <GIC_SPI 2030 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
3486 <GIC_SPI 2031 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
3487 <GIC_SPI 2032 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
3488 <GIC_SPI 2033 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
3489 <GIC_SPI 2034 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
3490 <GIC_SPI 2035 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
3491 <GIC_SPI 2036 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
3492 <GIC_SPI 2037 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
3493 <GIC_SPI 2038 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
3494 <GIC_SPI 2039 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
3495 <GIC_SPI 2040 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
3496 <GIC_SPI 2041 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
3497 <GIC_SPI 2042 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
3498 <GIC_SPI 2043 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
3499 <GIC_SPI 2044 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>,
3500 <GIC_SPI 2045 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
3501 <GIC_SPI 2046 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
3502 <GIC_SPI 2047 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
3503 <GIC_SPI 2048 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
3504 <GIC_SPI 2049 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
3505 <GIC_SPI 2050 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
3506 <GIC_SPI 2051 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
3507 <GIC_SPI 2052 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
3508 <GIC_SPI 2053 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
3509 <GIC_SPI 2054 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
3510 <GIC_SPI 2055 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
3511 <GIC_SPI 2056 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
3512 <GIC_SPI 2057 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
3513 <GIC_SPI 2058 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
3514 <GIC_SPI 2059 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
3515 <GIC_SPI 2060 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
3516 <GIC_SPI 2061 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
3517 <GIC_SPI 2062 <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>,
3518 <GIC_SPI 2063 <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>,
3519 <GIC_SPI 2064 <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>,
3520 <GIC_SPI 2065 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
3521 <GIC_SPI 2066 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
3522 <GIC_SPI 2067 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
3523 <GIC_SPI 2068 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>,
3524 <GIC_SPI 2069 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>,
3525 <GIC_SPI 2070 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>,
3526 <GIC_SPI 2071 <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>,
3527 <GIC_SPI 2072 <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>,
3528 <GIC_SPI 2073 <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>,
3529 <GIC_SPI 2074 <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>,
3530 <GIC_SPI 2075 <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>,
3531 <GIC_SPI 2076 <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>,
3532 <GIC_SPI 2077 <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>,
3533 <GIC_SPI 2078 <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>,
3534 <GIC_SPI 2079 <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>,
3535 <GIC_SPI 2080 <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>,
3536 <GIC_SPI 2081 <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>,
3537 <GIC_SPI 2082 <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>,
3538 <GIC_SPI 2083 <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>,
3539 <GIC_SPI 2084 <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>,
3540 <GIC_SPI 2085 <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>,
3541 <GIC_SPI 2086 <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>,
3542 <GIC_SPI 2087 <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>,
3543 <GIC_SPI 2088 <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>,
3544 <GIC_SPI 2089 <GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>,
3545 <GIC_SPI 2090 <GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>,
3546 <GIC_SPI 2091 <GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>,
3547 <GIC_SPI 2092 <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>;
3548 }; 2093 };
3549 2094
3550 pcie_smmu: iommu@15200000 { 2095 pcie_smmu: iommu@15200000 {
3551 compatible = "qcom,sa 2096 compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500";
3552 reg = <0x0 0x15200000 2097 reg = <0x0 0x15200000 0x0 0x80000>;
3553 #iommu-cells = <2>; 2098 #iommu-cells = <2>;
3554 #global-interrupts = 2099 #global-interrupts = <2>;
3555 dma-coherent; <<
3556 2100
3557 interrupts = <GIC_SPI 2101 interrupts = <GIC_SPI 920 IRQ_TYPE_LEVEL_HIGH>,
3558 <GIC_SPI 2102 <GIC_SPI 921 IRQ_TYPE_LEVEL_HIGH>,
3559 <GIC_SPI 2103 <GIC_SPI 925 IRQ_TYPE_LEVEL_HIGH>,
3560 <GIC_SPI 2104 <GIC_SPI 926 IRQ_TYPE_LEVEL_HIGH>,
3561 <GIC_SPI 2105 <GIC_SPI 927 IRQ_TYPE_LEVEL_HIGH>,
3562 <GIC_SPI 2106 <GIC_SPI 928 IRQ_TYPE_LEVEL_HIGH>,
3563 <GIC_SPI 2107 <GIC_SPI 950 IRQ_TYPE_LEVEL_HIGH>,
3564 <GIC_SPI 2108 <GIC_SPI 951 IRQ_TYPE_LEVEL_HIGH>,
3565 <GIC_SPI 2109 <GIC_SPI 952 IRQ_TYPE_LEVEL_HIGH>,
3566 <GIC_SPI 2110 <GIC_SPI 953 IRQ_TYPE_LEVEL_HIGH>,
3567 <GIC_SPI 2111 <GIC_SPI 954 IRQ_TYPE_LEVEL_HIGH>,
3568 <GIC_SPI 2112 <GIC_SPI 955 IRQ_TYPE_LEVEL_HIGH>,
3569 <GIC_SPI 2113 <GIC_SPI 956 IRQ_TYPE_LEVEL_HIGH>,
3570 <GIC_SPI 2114 <GIC_SPI 957 IRQ_TYPE_LEVEL_HIGH>,
3571 <GIC_SPI 2115 <GIC_SPI 958 IRQ_TYPE_LEVEL_HIGH>,
3572 <GIC_SPI 2116 <GIC_SPI 885 IRQ_TYPE_LEVEL_HIGH>,
3573 <GIC_SPI 2117 <GIC_SPI 886 IRQ_TYPE_LEVEL_HIGH>,
3574 <GIC_SPI 2118 <GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>,
3575 <GIC_SPI 2119 <GIC_SPI 888 IRQ_TYPE_LEVEL_HIGH>,
3576 <GIC_SPI 2120 <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>,
3577 <GIC_SPI 2121 <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>,
3578 <GIC_SPI 2122 <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>,
3579 <GIC_SPI 2123 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
3580 <GIC_SPI 2124 <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
3581 <GIC_SPI 2125 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
3582 <GIC_SPI 2126 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
3583 <GIC_SPI 2127 <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>,
3584 <GIC_SPI 2128 <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>,
3585 <GIC_SPI 2129 <GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>,
3586 <GIC_SPI 2130 <GIC_SPI 843 IRQ_TYPE_LEVEL_HIGH>,
3587 <GIC_SPI 2131 <GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>,
3588 <GIC_SPI 2132 <GIC_SPI 845 IRQ_TYPE_LEVEL_HIGH>,
3589 <GIC_SPI 2133 <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>,
3590 <GIC_SPI 2134 <GIC_SPI 847 IRQ_TYPE_LEVEL_HIGH>,
3591 <GIC_SPI 2135 <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>,
3592 <GIC_SPI 2136 <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>,
3593 <GIC_SPI 2137 <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>,
3594 <GIC_SPI 2138 <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>,
3595 <GIC_SPI 2139 <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>,
3596 <GIC_SPI 2140 <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>,
3597 <GIC_SPI 2141 <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>,
3598 <GIC_SPI 2142 <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>,
3599 <GIC_SPI 2143 <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>,
3600 <GIC_SPI 2144 <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>,
3601 <GIC_SPI 2145 <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>,
3602 <GIC_SPI 2146 <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>,
3603 <GIC_SPI 2147 <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>,
3604 <GIC_SPI 2148 <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>,
3605 <GIC_SPI 2149 <GIC_SPI 814 IRQ_TYPE_LEVEL_HIGH>,
3606 <GIC_SPI 2150 <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>,
3607 <GIC_SPI 2151 <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>,
3608 <GIC_SPI 2152 <GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>,
3609 <GIC_SPI 2153 <GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>,
3610 <GIC_SPI 2154 <GIC_SPI 854 IRQ_TYPE_LEVEL_HIGH>,
3611 <GIC_SPI 2155 <GIC_SPI 855 IRQ_TYPE_LEVEL_HIGH>,
3612 <GIC_SPI 2156 <GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>,
3613 <GIC_SPI 2157 <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>,
3614 <GIC_SPI 2158 <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>,
3615 <GIC_SPI 2159 <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>,
3616 <GIC_SPI 2160 <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>,
3617 <GIC_SPI 2161 <GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>,
3618 <GIC_SPI 2162 <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>,
3619 <GIC_SPI 2163 <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>,
3620 <GIC_SPI 2164 <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>,
3621 <GIC_SPI 2165 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
3622 <GIC_SPI 2166 <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>;
3623 }; 2167 };
3624 2168
3625 intc: interrupt-controller@17 2169 intc: interrupt-controller@17a00000 {
3626 compatible = "arm,gic 2170 compatible = "arm,gic-v3";
3627 reg = <0x0 0x17a00000 2171 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
3628 <0x0 0x17a60000 2172 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
3629 interrupt-controller; 2173 interrupt-controller;
3630 #interrupt-cells = <3 2174 #interrupt-cells = <3>;
3631 interrupts = <GIC_PPI 2175 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3632 #redistributor-region 2176 #redistributor-regions = <1>;
3633 redistributor-stride 2177 redistributor-stride = <0x0 0x20000>;
3634 }; 2178 };
3635 2179
3636 watchdog@17c10000 { 2180 watchdog@17c10000 {
3637 compatible = "qcom,ap 2181 compatible = "qcom,apss-wdt-sa8775p", "qcom,kpss-wdt";
3638 reg = <0x0 0x17c10000 2182 reg = <0x0 0x17c10000 0x0 0x1000>;
3639 clocks = <&sleep_clk> 2183 clocks = <&sleep_clk>;
3640 interrupts = <GIC_SPI 2184 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
3641 }; 2185 };
3642 2186
3643 memtimer: timer@17c20000 { 2187 memtimer: timer@17c20000 {
3644 compatible = "arm,arm 2188 compatible = "arm,armv7-timer-mem";
3645 reg = <0x0 0x17c20000 2189 reg = <0x0 0x17c20000 0x0 0x1000>;
3646 ranges = <0x0 0x0 0x0 2190 ranges = <0x0 0x0 0x0 0x20000000>;
3647 #address-cells = <1>; 2191 #address-cells = <1>;
3648 #size-cells = <1>; 2192 #size-cells = <1>;
3649 2193
3650 frame@17c21000 { 2194 frame@17c21000 {
3651 reg = <0x17c2 2195 reg = <0x17c21000 0x1000>,
3652 <0x17c2 2196 <0x17c22000 0x1000>;
3653 interrupts = 2197 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
3654 2198 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
3655 frame-number 2199 frame-number = <0>;
3656 }; 2200 };
3657 2201
3658 frame@17c23000 { 2202 frame@17c23000 {
3659 reg = <0x17c2 2203 reg = <0x17c23000 0x1000>;
3660 interrupts = 2204 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
3661 frame-number 2205 frame-number = <1>;
3662 status = "dis 2206 status = "disabled";
3663 }; 2207 };
3664 2208
3665 frame@17c25000 { 2209 frame@17c25000 {
3666 reg = <0x17c2 2210 reg = <0x17c25000 0x1000>;
3667 interrupts = 2211 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
3668 frame-number 2212 frame-number = <2>;
3669 status = "dis 2213 status = "disabled";
3670 }; 2214 };
3671 2215
3672 frame@17c27000 { 2216 frame@17c27000 {
3673 reg = <0x17c2 2217 reg = <0x17c27000 0x1000>;
3674 interrupts = 2218 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3675 frame-number 2219 frame-number = <3>;
3676 status = "dis 2220 status = "disabled";
3677 }; 2221 };
3678 2222
3679 frame@17c29000 { 2223 frame@17c29000 {
3680 reg = <0x17c2 2224 reg = <0x17c29000 0x1000>;
3681 interrupts = 2225 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3682 frame-number 2226 frame-number = <4>;
3683 status = "dis 2227 status = "disabled";
3684 }; 2228 };
3685 2229
3686 frame@17c2b000 { 2230 frame@17c2b000 {
3687 reg = <0x17c2 2231 reg = <0x17c2b000 0x1000>;
3688 interrupts = 2232 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3689 frame-number 2233 frame-number = <5>;
3690 status = "dis 2234 status = "disabled";
3691 }; 2235 };
3692 2236
3693 frame@17c2d000 { 2237 frame@17c2d000 {
3694 reg = <0x17c2 2238 reg = <0x17c2d000 0x1000>;
3695 interrupts = 2239 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
3696 frame-number 2240 frame-number = <6>;
3697 status = "dis 2241 status = "disabled";
3698 }; 2242 };
3699 }; 2243 };
3700 2244
3701 apps_rsc: rsc@18200000 { 2245 apps_rsc: rsc@18200000 {
3702 compatible = "qcom,rp 2246 compatible = "qcom,rpmh-rsc";
3703 reg = <0x0 0x18200000 2247 reg = <0x0 0x18200000 0x0 0x10000>,
3704 <0x0 0x18210000 2248 <0x0 0x18210000 0x0 0x10000>,
3705 <0x0 0x18220000 2249 <0x0 0x18220000 0x0 0x10000>;
3706 reg-names = "drv-0", 2250 reg-names = "drv-0", "drv-1", "drv-2";
3707 interrupts = <GIC_SPI 2251 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
3708 <GIC_SPI 4 IRQ_ 2252 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
3709 <GIC_SPI 5 IRQ_ 2253 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
3710 qcom,tcs-offset = <0x 2254 qcom,tcs-offset = <0xd00>;
3711 qcom,drv-id = <2>; 2255 qcom,drv-id = <2>;
3712 qcom,tcs-config = <AC 2256 qcom,tcs-config = <ACTIVE_TCS 2>,
3713 <SL 2257 <SLEEP_TCS 3>,
3714 <WA 2258 <WAKE_TCS 3>,
3715 <CO 2259 <CONTROL_TCS 0>;
3716 label = "apps_rsc"; 2260 label = "apps_rsc";
3717 2261
3718 apps_bcm_voter: bcm-v 2262 apps_bcm_voter: bcm-voter {
3719 compatible = 2263 compatible = "qcom,bcm-voter";
3720 }; 2264 };
3721 2265
3722 rpmhcc: clock-control 2266 rpmhcc: clock-controller {
3723 compatible = 2267 compatible = "qcom,sa8775p-rpmh-clk";
3724 #clock-cells 2268 #clock-cells = <1>;
3725 clock-names = 2269 clock-names = "xo";
3726 clocks = <&xo 2270 clocks = <&xo_board_clk>;
3727 }; 2271 };
3728 2272
3729 rpmhpd: power-control 2273 rpmhpd: power-controller {
3730 compatible = 2274 compatible = "qcom,sa8775p-rpmhpd";
3731 #power-domain 2275 #power-domain-cells = <1>;
3732 operating-poi 2276 operating-points-v2 = <&rpmhpd_opp_table>;
3733 2277
3734 rpmhpd_opp_ta 2278 rpmhpd_opp_table: opp-table {
3735 compa 2279 compatible = "operating-points-v2";
3736 2280
3737 rpmhp 2281 rpmhpd_opp_ret: opp-0 {
3738 2282 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3739 }; 2283 };
3740 2284
3741 rpmhp 2285 rpmhpd_opp_min_svs: opp-1 {
3742 2286 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3743 }; 2287 };
3744 2288
3745 rpmhp 2289 rpmhpd_opp_low_svs: opp2 {
3746 2290 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3747 }; 2291 };
3748 2292
3749 rpmhp 2293 rpmhpd_opp_svs: opp3 {
3750 2294 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3751 }; 2295 };
3752 2296
3753 rpmhp 2297 rpmhpd_opp_svs_l1: opp-4 {
3754 2298 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3755 }; 2299 };
3756 2300
3757 rpmhp 2301 rpmhpd_opp_nom: opp-5 {
3758 2302 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3759 }; 2303 };
3760 2304
3761 rpmhp 2305 rpmhpd_opp_nom_l1: opp-6 {
3762 2306 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3763 }; 2307 };
3764 2308
3765 rpmhp 2309 rpmhpd_opp_nom_l2: opp-7 {
3766 2310 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3767 }; 2311 };
3768 2312
3769 rpmhp 2313 rpmhpd_opp_turbo: opp-8 {
3770 2314 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3771 }; 2315 };
3772 2316
3773 rpmhp 2317 rpmhpd_opp_turbo_l1: opp-9 {
3774 2318 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3775 }; 2319 };
3776 }; 2320 };
3777 }; 2321 };
3778 }; 2322 };
3779 2323
3780 cpufreq_hw: cpufreq@18591000 2324 cpufreq_hw: cpufreq@18591000 {
3781 compatible = "qcom,sa 2325 compatible = "qcom,sa8775p-cpufreq-epss",
3782 "qcom,cp 2326 "qcom,cpufreq-epss";
3783 reg = <0x0 0x18591000 2327 reg = <0x0 0x18591000 0x0 0x1000>,
3784 <0x0 0x18593000 2328 <0x0 0x18593000 0x0 0x1000>;
3785 reg-names = "freq-dom 2329 reg-names = "freq-domain0", "freq-domain1";
3786 2330
3787 clocks = <&rpmhcc RPM 2331 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
3788 clock-names = "xo", " 2332 clock-names = "xo", "alternate";
3789 2333
3790 #freq-domain-cells = 2334 #freq-domain-cells = <1>;
3791 }; 2335 };
3792 2336
3793 remoteproc_gpdsp0: remoteproc <<
3794 compatible = "qcom,sa <<
3795 reg = <0x0 0x20c00000 <<
3796 <<
3797 interrupts-extended = <<
3798 <<
3799 <<
3800 <<
3801 <<
3802 interrupt-names = "wd <<
3803 "ha <<
3804 <<
3805 clocks = <&rpmhcc RPM <<
3806 clock-names = "xo"; <<
3807 <<
3808 power-domains = <&rpm <<
3809 <&rpm <<
3810 power-domain-names = <<
3811 <<
3812 interconnects = <&gpd <<
3813 &con <<
3814 <<
3815 memory-region = <&pil <<
3816 <<
3817 qcom,qmp = <&aoss_qmp <<
3818 <<
3819 qcom,smem-states = <& <<
3820 qcom,smem-state-names <<
3821 <<
3822 status = "disabled"; <<
3823 <<
3824 glink-edge { <<
3825 interrupts-ex <<
3826 <<
3827 <<
3828 mboxes = <&ip <<
3829 <<
3830 <<
3831 label = "gpds <<
3832 qcom,remote-p <<
3833 }; <<
3834 }; <<
3835 <<
3836 remoteproc_gpdsp1: remoteproc <<
3837 compatible = "qcom,sa <<
3838 reg = <0x0 0x21c00000 <<
3839 <<
3840 interrupts-extended = <<
3841 <<
3842 <<
3843 <<
3844 <<
3845 interrupt-names = "wd <<
3846 "ha <<
3847 <<
3848 clocks = <&rpmhcc RPM <<
3849 clock-names = "xo"; <<
3850 <<
3851 power-domains = <&rpm <<
3852 <&rpm <<
3853 power-domain-names = <<
3854 <<
3855 interconnects = <&gpd <<
3856 &con <<
3857 <<
3858 memory-region = <&pil <<
3859 <<
3860 qcom,qmp = <&aoss_qmp <<
3861 <<
3862 qcom,smem-states = <& <<
3863 qcom,smem-state-names <<
3864 <<
3865 status = "disabled"; <<
3866 <<
3867 glink-edge { <<
3868 interrupts-ex <<
3869 <<
3870 <<
3871 mboxes = <&ip <<
3872 <<
3873 <<
3874 label = "gpds <<
3875 qcom,remote-p <<
3876 }; <<
3877 }; <<
3878 <<
3879 ethernet1: ethernet@23000000 2337 ethernet1: ethernet@23000000 {
3880 compatible = "qcom,sa 2338 compatible = "qcom,sa8775p-ethqos";
3881 reg = <0x0 0x23000000 2339 reg = <0x0 0x23000000 0x0 0x10000>,
3882 <0x0 0x23016000 2340 <0x0 0x23016000 0x0 0x100>;
3883 reg-names = "stmmacet 2341 reg-names = "stmmaceth", "rgmii";
3884 2342
3885 interrupts = <GIC_SPI !! 2343 interrupts = <GIC_SPI 929 IRQ_TYPE_LEVEL_HIGH>;
3886 <GIC_SPI !! 2344 interrupt-names = "macirq";
3887 interrupt-names = "ma <<
3888 2345
3889 clocks = <&gcc GCC_EM 2346 clocks = <&gcc GCC_EMAC1_AXI_CLK>,
3890 <&gcc GCC_EM 2347 <&gcc GCC_EMAC1_SLV_AHB_CLK>,
3891 <&gcc GCC_EM 2348 <&gcc GCC_EMAC1_PTP_CLK>,
3892 <&gcc GCC_EM 2349 <&gcc GCC_EMAC1_PHY_AUX_CLK>;
3893 clock-names = "stmmac 2350 clock-names = "stmmaceth",
3894 "pclk", 2351 "pclk",
3895 "ptp_re 2352 "ptp_ref",
3896 "phyaux 2353 "phyaux";
3897 2354
3898 interconnects = <&agg <<
3899 &mc_ <<
3900 <&gem <<
3901 &con <<
3902 interconnect-names = <<
3903 <<
3904 power-domains = <&gcc 2355 power-domains = <&gcc EMAC1_GDSC>;
3905 2356
3906 phys = <&serdes1>; 2357 phys = <&serdes1>;
3907 phy-names = "serdes"; 2358 phy-names = "serdes";
3908 2359
3909 iommus = <&apps_smmu 2360 iommus = <&apps_smmu 0x140 0xf>;
3910 dma-coherent; <<
3911 2361
3912 snps,tso; 2362 snps,tso;
3913 snps,pbl = <32>; 2363 snps,pbl = <32>;
3914 rx-fifo-depth = <1638 2364 rx-fifo-depth = <16384>;
3915 tx-fifo-depth = <1638 2365 tx-fifo-depth = <16384>;
3916 2366
3917 status = "disabled"; 2367 status = "disabled";
3918 }; 2368 };
3919 2369
3920 ethernet0: ethernet@23040000 2370 ethernet0: ethernet@23040000 {
3921 compatible = "qcom,sa 2371 compatible = "qcom,sa8775p-ethqos";
3922 reg = <0x0 0x23040000 2372 reg = <0x0 0x23040000 0x0 0x10000>,
3923 <0x0 0x23056000 2373 <0x0 0x23056000 0x0 0x100>;
3924 reg-names = "stmmacet 2374 reg-names = "stmmaceth", "rgmii";
3925 2375
3926 interrupts = <GIC_SPI !! 2376 interrupts = <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>;
3927 <GIC_SPI !! 2377 interrupt-names = "macirq";
3928 interrupt-names = "ma <<
3929 2378
3930 clocks = <&gcc GCC_EM 2379 clocks = <&gcc GCC_EMAC0_AXI_CLK>,
3931 <&gcc GCC_EM 2380 <&gcc GCC_EMAC0_SLV_AHB_CLK>,
3932 <&gcc GCC_EM 2381 <&gcc GCC_EMAC0_PTP_CLK>,
3933 <&gcc GCC_EM 2382 <&gcc GCC_EMAC0_PHY_AUX_CLK>;
3934 clock-names = "stmmac 2383 clock-names = "stmmaceth",
3935 "pclk", 2384 "pclk",
3936 "ptp_re 2385 "ptp_ref",
3937 "phyaux 2386 "phyaux";
3938 2387
3939 interconnects = <&agg <<
3940 &mc_ <<
3941 <&gem <<
3942 &con <<
3943 interconnect-names = <<
3944 <<
3945 power-domains = <&gcc 2388 power-domains = <&gcc EMAC0_GDSC>;
3946 2389
3947 phys = <&serdes0>; 2390 phys = <&serdes0>;
3948 phy-names = "serdes"; 2391 phy-names = "serdes";
3949 2392
3950 iommus = <&apps_smmu 2393 iommus = <&apps_smmu 0x120 0xf>;
3951 dma-coherent; <<
3952 2394
3953 snps,tso; 2395 snps,tso;
3954 snps,pbl = <32>; 2396 snps,pbl = <32>;
3955 rx-fifo-depth = <1638 2397 rx-fifo-depth = <16384>;
3956 tx-fifo-depth = <1638 2398 tx-fifo-depth = <16384>;
3957 2399
3958 status = "disabled"; 2400 status = "disabled";
3959 }; 2401 };
3960 <<
3961 remoteproc_cdsp0: remoteproc@ <<
3962 compatible = "qcom,sa <<
3963 reg = <0x0 0x26300000 <<
3964 <<
3965 interrupts-extended = <<
3966 <<
3967 <<
3968 <<
3969 <<
3970 interrupt-names = "wd <<
3971 "ha <<
3972 <<
3973 clocks = <&rpmhcc RPM <<
3974 clock-names = "xo"; <<
3975 <<
3976 power-domains = <&rpm <<
3977 <&rpm <<
3978 <&rpm <<
3979 power-domain-names = <<
3980 <<
3981 interconnects = <&nsp <<
3982 &mc_ <<
3983 <<
3984 memory-region = <&pil <<
3985 <<
3986 qcom,qmp = <&aoss_qmp <<
3987 <<
3988 qcom,smem-states = <& <<
3989 qcom,smem-state-names <<
3990 <<
3991 status = "disabled"; <<
3992 <<
3993 glink-edge { <<
3994 interrupts-ex <<
3995 <<
3996 <<
3997 mboxes = <&ip <<
3998 <<
3999 <<
4000 label = "cdsp <<
4001 qcom,remote-p <<
4002 <<
4003 fastrpc { <<
4004 compa <<
4005 qcom, <<
4006 label <<
4007 #addr <<
4008 #size <<
4009 <<
4010 compu <<
4011 <<
4012 <<
4013 <<
4014 <<
4015 <<
4016 <<
4017 <<
4018 <<
4019 <<
4020 <<
4021 <<
4022 <<
4023 <<
4024 }; <<
4025 <<
4026 compu <<
4027 <<
4028 <<
4029 <<
4030 <<
4031 <<
4032 <<
4033 <<
4034 <<
4035 <<
4036 <<
4037 <<
4038 <<
4039 <<
4040 }; <<
4041 <<
4042 compu <<
4043 <<
4044 <<
4045 <<
4046 <<
4047 <<
4048 <<
4049 <<
4050 <<
4051 <<
4052 <<
4053 <<
4054 <<
4055 <<
4056 }; <<
4057 <<
4058 compu <<
4059 <<
4060 <<
4061 <<
4062 <<
4063 <<
4064 <<
4065 <<
4066 <<
4067 <<
4068 <<
4069 <<
4070 <<
4071 <<
4072 }; <<
4073 <<
4074 compu <<
4075 <<
4076 <<
4077 <<
4078 <<
4079 <<
4080 <<
4081 <<
4082 <<
4083 <<
4084 <<
4085 <<
4086 <<
4087 <<
4088 }; <<
4089 <<
4090 compu <<
4091 <<
4092 <<
4093 <<
4094 <<
4095 <<
4096 <<
4097 <<
4098 <<
4099 <<
4100 <<
4101 <<
4102 <<
4103 <<
4104 }; <<
4105 <<
4106 compu <<
4107 <<
4108 <<
4109 <<
4110 <<
4111 <<
4112 <<
4113 <<
4114 <<
4115 <<
4116 <<
4117 <<
4118 <<
4119 <<
4120 }; <<
4121 <<
4122 compu <<
4123 <<
4124 <<
4125 <<
4126 <<
4127 <<
4128 <<
4129 <<
4130 <<
4131 <<
4132 <<
4133 <<
4134 <<
4135 <<
4136 }; <<
4137 <<
4138 compu <<
4139 <<
4140 <<
4141 <<
4142 <<
4143 <<
4144 <<
4145 <<
4146 <<
4147 <<
4148 <<
4149 <<
4150 <<
4151 <<
4152 }; <<
4153 <<
4154 compu <<
4155 <<
4156 <<
4157 <<
4158 <<
4159 <<
4160 <<
4161 <<
4162 <<
4163 <<
4164 <<
4165 <<
4166 <<
4167 <<
4168 }; <<
4169 <<
4170 compu <<
4171 <<
4172 <<
4173 <<
4174 <<
4175 <<
4176 <<
4177 <<
4178 <<
4179 <<
4180 <<
4181 <<
4182 <<
4183 <<
4184 }; <<
4185 }; <<
4186 }; <<
4187 }; <<
4188 <<
4189 remoteproc_cdsp1: remoteproc@ <<
4190 compatible = "qcom,sa <<
4191 reg = <0x0 0x2A300000 <<
4192 <<
4193 interrupts-extended = <<
4194 <<
4195 <<
4196 <<
4197 <<
4198 interrupt-names = "wd <<
4199 "ha <<
4200 <<
4201 clocks = <&rpmhcc RPM <<
4202 clock-names = "xo"; <<
4203 <<
4204 power-domains = <&rpm <<
4205 <&rpm <<
4206 <&rpm <<
4207 power-domain-names = <<
4208 <<
4209 interconnects = <&nsp <<
4210 &mc_ <<
4211 <<
4212 memory-region = <&pil <<
4213 <<
4214 qcom,qmp = <&aoss_qmp <<
4215 <<
4216 qcom,smem-states = <& <<
4217 qcom,smem-state-names <<
4218 <<
4219 status = "disabled"; <<
4220 <<
4221 glink-edge { <<
4222 interrupts-ex <<
4223 <<
4224 <<
4225 mboxes = <&ip <<
4226 <<
4227 <<
4228 label = "cdsp <<
4229 qcom,remote-p <<
4230 <<
4231 fastrpc { <<
4232 compa <<
4233 qcom, <<
4234 label <<
4235 #addr <<
4236 #size <<
4237 <<
4238 compu <<
4239 <<
4240 <<
4241 <<
4242 <<
4243 <<
4244 <<
4245 <<
4246 <<
4247 <<
4248 <<
4249 <<
4250 <<
4251 <<
4252 }; <<
4253 <<
4254 compu <<
4255 <<
4256 <<
4257 <<
4258 <<
4259 <<
4260 <<
4261 <<
4262 <<
4263 <<
4264 <<
4265 <<
4266 <<
4267 <<
4268 }; <<
4269 <<
4270 compu <<
4271 <<
4272 <<
4273 <<
4274 <<
4275 <<
4276 <<
4277 <<
4278 <<
4279 <<
4280 <<
4281 <<
4282 <<
4283 <<
4284 }; <<
4285 <<
4286 compu <<
4287 <<
4288 <<
4289 <<
4290 <<
4291 <<
4292 <<
4293 <<
4294 <<
4295 <<
4296 <<
4297 <<
4298 <<
4299 <<
4300 }; <<
4301 <<
4302 compu <<
4303 <<
4304 <<
4305 <<
4306 <<
4307 <<
4308 <<
4309 <<
4310 <<
4311 <<
4312 <<
4313 <<
4314 <<
4315 <<
4316 }; <<
4317 <<
4318 compu <<
4319 <<
4320 <<
4321 <<
4322 <<
4323 <<
4324 <<
4325 <<
4326 <<
4327 <<
4328 <<
4329 <<
4330 <<
4331 <<
4332 }; <<
4333 <<
4334 compu <<
4335 <<
4336 <<
4337 <<
4338 <<
4339 <<
4340 <<
4341 <<
4342 <<
4343 <<
4344 <<
4345 <<
4346 <<
4347 <<
4348 }; <<
4349 <<
4350 compu <<
4351 <<
4352 <<
4353 <<
4354 <<
4355 <<
4356 <<
4357 <<
4358 <<
4359 <<
4360 <<
4361 <<
4362 <<
4363 <<
4364 }; <<
4365 <<
4366 compu <<
4367 <<
4368 <<
4369 <<
4370 <<
4371 <<
4372 <<
4373 <<
4374 <<
4375 <<
4376 <<
4377 <<
4378 <<
4379 <<
4380 }; <<
4381 <<
4382 compu <<
4383 <<
4384 <<
4385 <<
4386 <<
4387 <<
4388 <<
4389 <<
4390 <<
4391 <<
4392 <<
4393 <<
4394 <<
4395 <<
4396 }; <<
4397 <<
4398 compu <<
4399 <<
4400 <<
4401 <<
4402 <<
4403 <<
4404 <<
4405 <<
4406 <<
4407 <<
4408 <<
4409 <<
4410 <<
4411 <<
4412 }; <<
4413 <<
4414 compu <<
4415 <<
4416 <<
4417 <<
4418 <<
4419 <<
4420 <<
4421 <<
4422 <<
4423 <<
4424 <<
4425 <<
4426 <<
4427 <<
4428 }; <<
4429 <<
4430 compu <<
4431 <<
4432 <<
4433 <<
4434 <<
4435 <<
4436 <<
4437 <<
4438 <<
4439 <<
4440 <<
4441 <<
4442 <<
4443 <<
4444 }; <<
4445 }; <<
4446 }; <<
4447 }; <<
4448 <<
4449 remoteproc_adsp: remoteproc@3 <<
4450 compatible = "qcom,sa <<
4451 reg = <0x0 0x30000000 <<
4452 <<
4453 interrupts-extended = <<
4454 <<
4455 <<
4456 <<
4457 <<
4458 interrupt-names = "wd <<
4459 "st <<
4460 <<
4461 clocks = <&rpmhcc RPM <<
4462 clock-names = "xo"; <<
4463 <<
4464 power-domains = <&rpm <<
4465 <&rpm <<
4466 power-domain-names = <<
4467 <<
4468 interconnects = <&lpa <<
4469 <<
4470 memory-region = <&pil <<
4471 <<
4472 qcom,qmp = <&aoss_qmp <<
4473 <<
4474 qcom,smem-states = <& <<
4475 qcom,smem-state-names <<
4476 <<
4477 status = "disabled"; <<
4478 <<
4479 remoteproc_adsp_glink <<
4480 interrupts-ex <<
4481 <<
4482 <<
4483 mboxes = <&ip <<
4484 <<
4485 <<
4486 label = "lpas <<
4487 qcom,remote-p <<
4488 <<
4489 fastrpc { <<
4490 compa <<
4491 qcom, <<
4492 label <<
4493 memor <<
4494 qcom, <<
4495 <<
4496 #addr <<
4497 #size <<
4498 <<
4499 compu <<
4500 <<
4501 <<
4502 <<
4503 <<
4504 }; <<
4505 <<
4506 compu <<
4507 <<
4508 <<
4509 <<
4510 <<
4511 }; <<
4512 <<
4513 compu <<
4514 <<
4515 <<
4516 <<
4517 <<
4518 <<
4519 }; <<
4520 }; <<
4521 }; <<
4522 }; <<
4523 }; <<
4524 <<
4525 thermal-zones { <<
4526 aoss-0-thermal { <<
4527 thermal-sensors = <&t <<
4528 <<
4529 trips { <<
4530 trip-point0 { <<
4531 tempe <<
4532 hyste <<
4533 type <<
4534 }; <<
4535 <<
4536 trip-point1 { <<
4537 tempe <<
4538 hyste <<
4539 type <<
4540 }; <<
4541 }; <<
4542 }; <<
4543 <<
4544 cpu-0-0-0-thermal { <<
4545 polling-delay-passive <<
4546 <<
4547 thermal-sensors = <&t <<
4548 <<
4549 trips { <<
4550 trip-point0 { <<
4551 tempe <<
4552 hyste <<
4553 type <<
4554 }; <<
4555 <<
4556 trip-point1 { <<
4557 tempe <<
4558 hyste <<
4559 type <<
4560 }; <<
4561 }; <<
4562 }; <<
4563 <<
4564 cpu-0-1-0-thermal { <<
4565 polling-delay-passive <<
4566 <<
4567 thermal-sensors = <&t <<
4568 <<
4569 trips { <<
4570 trip-point0 { <<
4571 tempe <<
4572 hyste <<
4573 type <<
4574 }; <<
4575 <<
4576 trip-point1 { <<
4577 tempe <<
4578 hyste <<
4579 type <<
4580 }; <<
4581 }; <<
4582 }; <<
4583 <<
4584 cpu-0-2-0-thermal { <<
4585 polling-delay-passive <<
4586 <<
4587 thermal-sensors = <&t <<
4588 <<
4589 trips { <<
4590 trip-point0 { <<
4591 tempe <<
4592 hyste <<
4593 type <<
4594 }; <<
4595 <<
4596 trip-point1 { <<
4597 tempe <<
4598 hyste <<
4599 type <<
4600 }; <<
4601 }; <<
4602 }; <<
4603 <<
4604 cpu-0-3-0-thermal { <<
4605 polling-delay-passive <<
4606 <<
4607 thermal-sensors = <&t <<
4608 <<
4609 trips { <<
4610 trip-point0 { <<
4611 tempe <<
4612 hyste <<
4613 type <<
4614 }; <<
4615 <<
4616 trip-point1 { <<
4617 tempe <<
4618 hyste <<
4619 type <<
4620 }; <<
4621 }; <<
4622 }; <<
4623 <<
4624 gpuss-0-thermal { <<
4625 polling-delay-passive <<
4626 <<
4627 thermal-sensors = <&t <<
4628 <<
4629 trips { <<
4630 trip-point0 { <<
4631 tempe <<
4632 hyste <<
4633 type <<
4634 }; <<
4635 <<
4636 trip-point1 { <<
4637 tempe <<
4638 hyste <<
4639 type <<
4640 }; <<
4641 }; <<
4642 }; <<
4643 <<
4644 gpuss-1-thermal { <<
4645 polling-delay-passive <<
4646 <<
4647 thermal-sensors = <&t <<
4648 <<
4649 trips { <<
4650 trip-point0 { <<
4651 tempe <<
4652 hyste <<
4653 type <<
4654 }; <<
4655 <<
4656 trip-point1 { <<
4657 tempe <<
4658 hyste <<
4659 type <<
4660 }; <<
4661 }; <<
4662 }; <<
4663 <<
4664 gpuss-2-thermal { <<
4665 polling-delay-passive <<
4666 <<
4667 thermal-sensors = <&t <<
4668 <<
4669 trips { <<
4670 trip-point0 { <<
4671 tempe <<
4672 hyste <<
4673 type <<
4674 }; <<
4675 <<
4676 trip-point1 { <<
4677 tempe <<
4678 hyste <<
4679 type <<
4680 }; <<
4681 }; <<
4682 }; <<
4683 <<
4684 audio-thermal { <<
4685 thermal-sensors = <&t <<
4686 <<
4687 trips { <<
4688 trip-point0 { <<
4689 tempe <<
4690 hyste <<
4691 type <<
4692 }; <<
4693 <<
4694 trip-point1 { <<
4695 tempe <<
4696 hyste <<
4697 type <<
4698 }; <<
4699 }; <<
4700 }; <<
4701 <<
4702 camss-0-thermal { <<
4703 thermal-sensors = <&t <<
4704 <<
4705 trips { <<
4706 trip-point0 { <<
4707 tempe <<
4708 hyste <<
4709 type <<
4710 }; <<
4711 <<
4712 trip-point1 { <<
4713 tempe <<
4714 hyste <<
4715 type <<
4716 }; <<
4717 }; <<
4718 }; <<
4719 <<
4720 pcie-0-thermal { <<
4721 thermal-sensors = <&t <<
4722 <<
4723 trips { <<
4724 trip-point0 { <<
4725 tempe <<
4726 hyste <<
4727 type <<
4728 }; <<
4729 <<
4730 trip-point1 { <<
4731 tempe <<
4732 hyste <<
4733 type <<
4734 }; <<
4735 }; <<
4736 }; <<
4737 <<
4738 cpuss-0-0-thermal { <<
4739 thermal-sensors = <&t <<
4740 <<
4741 trips { <<
4742 trip-point0 { <<
4743 tempe <<
4744 hyste <<
4745 type <<
4746 }; <<
4747 <<
4748 trip-point1 { <<
4749 tempe <<
4750 hyste <<
4751 type <<
4752 }; <<
4753 }; <<
4754 }; <<
4755 <<
4756 aoss-1-thermal { <<
4757 thermal-sensors = <&t <<
4758 <<
4759 trips { <<
4760 trip-point0 { <<
4761 tempe <<
4762 hyste <<
4763 type <<
4764 }; <<
4765 <<
4766 trip-point1 { <<
4767 tempe <<
4768 hyste <<
4769 type <<
4770 }; <<
4771 }; <<
4772 }; <<
4773 <<
4774 cpu-0-0-1-thermal { <<
4775 polling-delay-passive <<
4776 <<
4777 thermal-sensors = <&t <<
4778 <<
4779 trips { <<
4780 trip-point0 { <<
4781 tempe <<
4782 hyste <<
4783 type <<
4784 }; <<
4785 <<
4786 trip-point1 { <<
4787 tempe <<
4788 hyste <<
4789 type <<
4790 }; <<
4791 }; <<
4792 }; <<
4793 <<
4794 cpu-0-1-1-thermal { <<
4795 polling-delay-passive <<
4796 <<
4797 thermal-sensors = <&t <<
4798 <<
4799 trips { <<
4800 trip-point0 { <<
4801 tempe <<
4802 hyste <<
4803 type <<
4804 }; <<
4805 <<
4806 trip-point1 { <<
4807 tempe <<
4808 hyste <<
4809 type <<
4810 }; <<
4811 }; <<
4812 }; <<
4813 <<
4814 cpu-0-2-1-thermal { <<
4815 polling-delay-passive <<
4816 <<
4817 thermal-sensors = <&t <<
4818 <<
4819 trips { <<
4820 trip-point0 { <<
4821 tempe <<
4822 hyste <<
4823 type <<
4824 }; <<
4825 <<
4826 trip-point1 { <<
4827 tempe <<
4828 hyste <<
4829 type <<
4830 }; <<
4831 }; <<
4832 }; <<
4833 <<
4834 cpu-0-3-1-thermal { <<
4835 polling-delay-passive <<
4836 <<
4837 thermal-sensors = <&t <<
4838 <<
4839 trips { <<
4840 trip-point0 { <<
4841 tempe <<
4842 hyste <<
4843 type <<
4844 }; <<
4845 <<
4846 trip-point1 { <<
4847 tempe <<
4848 hyste <<
4849 type <<
4850 }; <<
4851 }; <<
4852 }; <<
4853 <<
4854 gpuss-3-thermal { <<
4855 polling-delay-passive <<
4856 <<
4857 thermal-sensors = <&t <<
4858 <<
4859 trips { <<
4860 trip-point0 { <<
4861 tempe <<
4862 hyste <<
4863 type <<
4864 }; <<
4865 <<
4866 trip-point1 { <<
4867 tempe <<
4868 hyste <<
4869 type <<
4870 }; <<
4871 }; <<
4872 }; <<
4873 <<
4874 gpuss-4-thermal { <<
4875 polling-delay-passive <<
4876 <<
4877 thermal-sensors = <&t <<
4878 <<
4879 trips { <<
4880 trip-point0 { <<
4881 tempe <<
4882 hyste <<
4883 type <<
4884 }; <<
4885 <<
4886 trip-point1 { <<
4887 tempe <<
4888 hyste <<
4889 type <<
4890 }; <<
4891 }; <<
4892 }; <<
4893 <<
4894 gpuss-5-thermal { <<
4895 polling-delay-passive <<
4896 <<
4897 thermal-sensors = <&t <<
4898 <<
4899 trips { <<
4900 trip-point0 { <<
4901 tempe <<
4902 hyste <<
4903 type <<
4904 }; <<
4905 <<
4906 trip-point1 { <<
4907 tempe <<
4908 hyste <<
4909 type <<
4910 }; <<
4911 }; <<
4912 }; <<
4913 <<
4914 video-thermal { <<
4915 thermal-sensors = <&t <<
4916 <<
4917 trips { <<
4918 trip-point0 { <<
4919 tempe <<
4920 hyste <<
4921 type <<
4922 }; <<
4923 <<
4924 trip-point1 { <<
4925 tempe <<
4926 hyste <<
4927 type <<
4928 }; <<
4929 }; <<
4930 }; <<
4931 <<
4932 camss-1-thermal { <<
4933 thermal-sensors = <&t <<
4934 <<
4935 trips { <<
4936 trip-point0 { <<
4937 tempe <<
4938 hyste <<
4939 type <<
4940 }; <<
4941 <<
4942 trip-point1 { <<
4943 tempe <<
4944 hyste <<
4945 type <<
4946 }; <<
4947 }; <<
4948 }; <<
4949 <<
4950 pcie-1-thermal { <<
4951 thermal-sensors = <&t <<
4952 <<
4953 trips { <<
4954 trip-point0 { <<
4955 tempe <<
4956 hyste <<
4957 type <<
4958 }; <<
4959 <<
4960 trip-point1 { <<
4961 tempe <<
4962 hyste <<
4963 type <<
4964 }; <<
4965 }; <<
4966 }; <<
4967 <<
4968 cpuss-0-1-thermal { <<
4969 thermal-sensors = <&t <<
4970 <<
4971 trips { <<
4972 trip-point0 { <<
4973 tempe <<
4974 hyste <<
4975 type <<
4976 }; <<
4977 <<
4978 trip-point1 { <<
4979 tempe <<
4980 hyste <<
4981 type <<
4982 }; <<
4983 }; <<
4984 }; <<
4985 <<
4986 aoss-2-thermal { <<
4987 thermal-sensors = <&t <<
4988 <<
4989 trips { <<
4990 trip-point0 { <<
4991 tempe <<
4992 hyste <<
4993 type <<
4994 }; <<
4995 <<
4996 trip-point1 { <<
4997 tempe <<
4998 hyste <<
4999 type <<
5000 }; <<
5001 }; <<
5002 }; <<
5003 <<
5004 cpu-1-0-0-thermal { <<
5005 polling-delay-passive <<
5006 <<
5007 thermal-sensors = <&t <<
5008 <<
5009 trips { <<
5010 trip-point0 { <<
5011 tempe <<
5012 hyste <<
5013 type <<
5014 }; <<
5015 <<
5016 trip-point1 { <<
5017 tempe <<
5018 hyste <<
5019 type <<
5020 }; <<
5021 }; <<
5022 }; <<
5023 <<
5024 cpu-1-1-0-thermal { <<
5025 polling-delay-passive <<
5026 <<
5027 thermal-sensors = <&t <<
5028 <<
5029 trips { <<
5030 trip-point0 { <<
5031 tempe <<
5032 hyste <<
5033 type <<
5034 }; <<
5035 <<
5036 trip-point1 { <<
5037 tempe <<
5038 hyste <<
5039 type <<
5040 }; <<
5041 }; <<
5042 }; <<
5043 <<
5044 cpu-1-2-0-thermal { <<
5045 polling-delay-passive <<
5046 <<
5047 thermal-sensors = <&t <<
5048 <<
5049 trips { <<
5050 trip-point0 { <<
5051 tempe <<
5052 hyste <<
5053 type <<
5054 }; <<
5055 <<
5056 trip-point1 { <<
5057 tempe <<
5058 hyste <<
5059 type <<
5060 }; <<
5061 }; <<
5062 }; <<
5063 <<
5064 cpu-1-3-0-thermal { <<
5065 polling-delay-passive <<
5066 <<
5067 thermal-sensors = <&t <<
5068 <<
5069 trips { <<
5070 trip-point0 { <<
5071 tempe <<
5072 hyste <<
5073 type <<
5074 }; <<
5075 <<
5076 trip-point1 { <<
5077 tempe <<
5078 hyste <<
5079 type <<
5080 }; <<
5081 }; <<
5082 }; <<
5083 <<
5084 nsp-0-0-0-thermal { <<
5085 polling-delay-passive <<
5086 <<
5087 thermal-sensors = <&t <<
5088 <<
5089 trips { <<
5090 trip-point0 { <<
5091 tempe <<
5092 hyste <<
5093 type <<
5094 }; <<
5095 <<
5096 trip-point1 { <<
5097 tempe <<
5098 hyste <<
5099 type <<
5100 }; <<
5101 }; <<
5102 }; <<
5103 <<
5104 nsp-0-1-0-thermal { <<
5105 polling-delay-passive <<
5106 <<
5107 thermal-sensors = <&t <<
5108 <<
5109 trips { <<
5110 trip-point0 { <<
5111 tempe <<
5112 hyste <<
5113 type <<
5114 }; <<
5115 <<
5116 trip-point1 { <<
5117 tempe <<
5118 hyste <<
5119 type <<
5120 }; <<
5121 }; <<
5122 }; <<
5123 <<
5124 nsp-0-2-0-thermal { <<
5125 polling-delay-passive <<
5126 <<
5127 thermal-sensors = <&t <<
5128 <<
5129 trips { <<
5130 trip-point0 { <<
5131 tempe <<
5132 hyste <<
5133 type <<
5134 }; <<
5135 <<
5136 trip-point1 { <<
5137 tempe <<
5138 hyste <<
5139 type <<
5140 }; <<
5141 }; <<
5142 }; <<
5143 <<
5144 nsp-1-0-0-thermal { <<
5145 polling-delay-passive <<
5146 <<
5147 thermal-sensors = <&t <<
5148 <<
5149 trips { <<
5150 trip-point0 { <<
5151 tempe <<
5152 hyste <<
5153 type <<
5154 }; <<
5155 <<
5156 trip-point1 { <<
5157 tempe <<
5158 hyste <<
5159 type <<
5160 }; <<
5161 }; <<
5162 }; <<
5163 <<
5164 nsp-1-1-0-thermal { <<
5165 polling-delay-passive <<
5166 <<
5167 thermal-sensors = <&t <<
5168 <<
5169 trips { <<
5170 trip-point0 { <<
5171 tempe <<
5172 hyste <<
5173 type <<
5174 }; <<
5175 <<
5176 trip-point1 { <<
5177 tempe <<
5178 hyste <<
5179 type <<
5180 }; <<
5181 }; <<
5182 }; <<
5183 <<
5184 nsp-1-2-0-thermal { <<
5185 polling-delay-passive <<
5186 <<
5187 thermal-sensors = <&t <<
5188 <<
5189 trips { <<
5190 trip-point0 { <<
5191 tempe <<
5192 hyste <<
5193 type <<
5194 }; <<
5195 <<
5196 trip-point1 { <<
5197 tempe <<
5198 hyste <<
5199 type <<
5200 }; <<
5201 }; <<
5202 }; <<
5203 <<
5204 ddrss-0-thermal { <<
5205 thermal-sensors = <&t <<
5206 <<
5207 trips { <<
5208 trip-point0 { <<
5209 tempe <<
5210 hyste <<
5211 type <<
5212 }; <<
5213 <<
5214 trip-point1 { <<
5215 tempe <<
5216 hyste <<
5217 type <<
5218 }; <<
5219 }; <<
5220 }; <<
5221 <<
5222 cpuss-1-0-thermal { <<
5223 thermal-sensors = <&t <<
5224 <<
5225 trips { <<
5226 trip-point0 { <<
5227 tempe <<
5228 hyste <<
5229 type <<
5230 }; <<
5231 <<
5232 trip-point1 { <<
5233 tempe <<
5234 hyste <<
5235 type <<
5236 }; <<
5237 }; <<
5238 }; <<
5239 <<
5240 aoss-3-thermal { <<
5241 thermal-sensors = <&t <<
5242 <<
5243 trips { <<
5244 trip-point0 { <<
5245 tempe <<
5246 hyste <<
5247 type <<
5248 }; <<
5249 <<
5250 trip-point1 { <<
5251 tempe <<
5252 hyste <<
5253 type <<
5254 }; <<
5255 }; <<
5256 }; <<
5257 <<
5258 cpu-1-0-1-thermal { <<
5259 polling-delay-passive <<
5260 <<
5261 thermal-sensors = <&t <<
5262 <<
5263 trips { <<
5264 trip-point0 { <<
5265 tempe <<
5266 hyste <<
5267 type <<
5268 }; <<
5269 <<
5270 trip-point1 { <<
5271 tempe <<
5272 hyste <<
5273 type <<
5274 }; <<
5275 }; <<
5276 }; <<
5277 <<
5278 cpu-1-1-1-thermal { <<
5279 polling-delay-passive <<
5280 <<
5281 thermal-sensors = <&t <<
5282 <<
5283 trips { <<
5284 trip-point0 { <<
5285 tempe <<
5286 hyste <<
5287 type <<
5288 }; <<
5289 <<
5290 trip-point1 { <<
5291 tempe <<
5292 hyste <<
5293 type <<
5294 }; <<
5295 }; <<
5296 }; <<
5297 <<
5298 cpu-1-2-1-thermal { <<
5299 polling-delay-passive <<
5300 <<
5301 thermal-sensors = <&t <<
5302 <<
5303 trips { <<
5304 trip-point0 { <<
5305 tempe <<
5306 hyste <<
5307 type <<
5308 }; <<
5309 <<
5310 trip-point1 { <<
5311 tempe <<
5312 hyste <<
5313 type <<
5314 }; <<
5315 }; <<
5316 }; <<
5317 <<
5318 cpu-1-3-1-thermal { <<
5319 polling-delay-passive <<
5320 <<
5321 thermal-sensors = <&t <<
5322 <<
5323 trips { <<
5324 trip-point0 { <<
5325 tempe <<
5326 hyste <<
5327 type <<
5328 }; <<
5329 <<
5330 trip-point1 { <<
5331 tempe <<
5332 hyste <<
5333 type <<
5334 }; <<
5335 }; <<
5336 }; <<
5337 <<
5338 nsp-0-0-1-thermal { <<
5339 polling-delay-passive <<
5340 <<
5341 thermal-sensors = <&t <<
5342 <<
5343 trips { <<
5344 trip-point0 { <<
5345 tempe <<
5346 hyste <<
5347 type <<
5348 }; <<
5349 <<
5350 trip-point1 { <<
5351 tempe <<
5352 hyste <<
5353 type <<
5354 }; <<
5355 }; <<
5356 }; <<
5357 <<
5358 nsp-0-1-1-thermal { <<
5359 polling-delay-passive <<
5360 <<
5361 thermal-sensors = <&t <<
5362 <<
5363 trips { <<
5364 trip-point0 { <<
5365 tempe <<
5366 hyste <<
5367 type <<
5368 }; <<
5369 <<
5370 trip-point1 { <<
5371 tempe <<
5372 hyste <<
5373 type <<
5374 }; <<
5375 }; <<
5376 }; <<
5377 <<
5378 nsp-0-2-1-thermal { <<
5379 polling-delay-passive <<
5380 <<
5381 thermal-sensors = <&t <<
5382 <<
5383 trips { <<
5384 trip-point0 { <<
5385 tempe <<
5386 hyste <<
5387 type <<
5388 }; <<
5389 <<
5390 trip-point1 { <<
5391 tempe <<
5392 hyste <<
5393 type <<
5394 }; <<
5395 }; <<
5396 }; <<
5397 <<
5398 nsp-1-0-1-thermal { <<
5399 polling-delay-passive <<
5400 <<
5401 thermal-sensors = <&t <<
5402 <<
5403 trips { <<
5404 trip-point0 { <<
5405 tempe <<
5406 hyste <<
5407 type <<
5408 }; <<
5409 <<
5410 trip-point1 { <<
5411 tempe <<
5412 hyste <<
5413 type <<
5414 }; <<
5415 }; <<
5416 }; <<
5417 <<
5418 nsp-1-1-1-thermal { <<
5419 polling-delay-passive <<
5420 <<
5421 thermal-sensors = <&t <<
5422 <<
5423 trips { <<
5424 trip-point0 { <<
5425 tempe <<
5426 hyste <<
5427 type <<
5428 }; <<
5429 <<
5430 trip-point1 { <<
5431 tempe <<
5432 hyste <<
5433 type <<
5434 }; <<
5435 }; <<
5436 }; <<
5437 <<
5438 nsp-1-2-1-thermal { <<
5439 polling-delay-passive <<
5440 <<
5441 thermal-sensors = <&t <<
5442 <<
5443 trips { <<
5444 trip-point0 { <<
5445 tempe <<
5446 hyste <<
5447 type <<
5448 }; <<
5449 <<
5450 trip-point1 { <<
5451 tempe <<
5452 hyste <<
5453 type <<
5454 }; <<
5455 }; <<
5456 }; <<
5457 <<
5458 ddrss-1-thermal { <<
5459 thermal-sensors = <&t <<
5460 <<
5461 trips { <<
5462 trip-point0 { <<
5463 tempe <<
5464 hyste <<
5465 type <<
5466 }; <<
5467 <<
5468 trip-point1 { <<
5469 tempe <<
5470 hyste <<
5471 type <<
5472 }; <<
5473 }; <<
5474 }; <<
5475 <<
5476 cpuss-1-1-thermal { <<
5477 thermal-sensors = <&t <<
5478 <<
5479 trips { <<
5480 trip-point0 { <<
5481 tempe <<
5482 hyste <<
5483 type <<
5484 }; <<
5485 <<
5486 trip-point1 { <<
5487 tempe <<
5488 hyste <<
5489 type <<
5490 }; <<
5491 }; <<
5492 }; <<
5493 }; 2402 };
5494 2403
5495 arch_timer: timer { 2404 arch_timer: timer {
5496 compatible = "arm,armv8-timer 2405 compatible = "arm,armv8-timer";
5497 interrupts = <GIC_PPI 13 (GIC 2406 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5498 <GIC_PPI 14 (GIC 2407 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5499 <GIC_PPI 11 (GIC 2408 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5500 <GIC_PPI 10 (GIC !! 2409 <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
5501 }; 2410 };
5502 2411
5503 pcie0: pcie@1c00000 { !! 2412 pcie0: pci@1c00000{
5504 compatible = "qcom,pcie-sa877 2413 compatible = "qcom,pcie-sa8775p";
5505 reg = <0x0 0x01c00000 0x0 0x3 2414 reg = <0x0 0x01c00000 0x0 0x3000>,
5506 <0x0 0x40000000 0x0 0xf 2415 <0x0 0x40000000 0x0 0xf20>,
5507 <0x0 0x40000f20 0x0 0xa 2416 <0x0 0x40000f20 0x0 0xa8>,
5508 <0x0 0x40001000 0x0 0x4 2417 <0x0 0x40001000 0x0 0x4000>,
5509 <0x0 0x40100000 0x0 0x1 2418 <0x0 0x40100000 0x0 0x100000>,
5510 <0x0 0x01c03000 0x0 0x1 2419 <0x0 0x01c03000 0x0 0x1000>;
5511 reg-names = "parf", "dbi", "e 2420 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
5512 device_type = "pci"; 2421 device_type = "pci";
5513 2422
5514 #address-cells = <3>; 2423 #address-cells = <3>;
5515 #size-cells = <2>; 2424 #size-cells = <2>;
5516 ranges = <0x01000000 0x0 0x00 2425 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
5517 <0x02000000 0x0 0x40 2426 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
5518 bus-range = <0x00 0xff>; 2427 bus-range = <0x00 0xff>;
5519 2428
5520 dma-coherent; 2429 dma-coherent;
5521 2430
5522 linux,pci-domain = <0>; 2431 linux,pci-domain = <0>;
5523 num-lanes = <2>; 2432 num-lanes = <2>;
5524 2433
5525 interrupts = <GIC_SPI 307 IRQ 2434 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
5526 <GIC_SPI 308 IRQ 2435 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
5527 <GIC_SPI 309 IRQ 2436 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
5528 <GIC_SPI 312 IRQ 2437 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
5529 <GIC_SPI 313 IRQ 2438 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
5530 <GIC_SPI 314 IRQ 2439 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
5531 <GIC_SPI 374 IRQ 2440 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
5532 <GIC_SPI 375 IRQ 2441 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
5533 interrupt-names = "msi0", "ms 2442 interrupt-names = "msi0", "msi1", "msi2", "msi3",
5534 "msi4", "ms 2443 "msi4", "msi5", "msi6", "msi7";
5535 #interrupt-cells = <1>; 2444 #interrupt-cells = <1>;
5536 interrupt-map-mask = <0 0 0 0 2445 interrupt-map-mask = <0 0 0 0x7>;
5537 interrupt-map = <0 0 0 1 &int 2446 interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
5538 <0 0 0 2 &int 2447 <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
5539 <0 0 0 3 &int 2448 <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
5540 <0 0 0 4 &int 2449 <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>;
5541 2450
5542 clocks = <&gcc GCC_PCIE_0_AUX 2451 clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
5543 <&gcc GCC_PCIE_0_CFG 2452 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
5544 <&gcc GCC_PCIE_0_MST 2453 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
5545 <&gcc GCC_PCIE_0_SLV 2454 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
5546 <&gcc GCC_PCIE_0_SLV 2455 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>;
5547 2456
5548 clock-names = "aux", 2457 clock-names = "aux",
5549 "cfg", 2458 "cfg",
5550 "bus_master", 2459 "bus_master",
5551 "bus_slave", 2460 "bus_slave",
5552 "slave_q2a"; 2461 "slave_q2a";
5553 2462
5554 assigned-clocks = <&gcc GCC_P 2463 assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>;
5555 assigned-clock-rates = <19200 2464 assigned-clock-rates = <19200000>;
5556 2465
5557 interconnects = <&pcie_anoc M 2466 interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>,
5558 <&gem_noc MAS 2467 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>;
5559 interconnect-names = "pcie-me 2468 interconnect-names = "pcie-mem", "cpu-pcie";
5560 2469
5561 iommu-map = <0x0 &pcie_smmu 0 2470 iommu-map = <0x0 &pcie_smmu 0x0000 0x1>,
5562 <0x100 &pcie_smmu 2471 <0x100 &pcie_smmu 0x0001 0x1>;
5563 2472
5564 resets = <&gcc GCC_PCIE_0_BCR 2473 resets = <&gcc GCC_PCIE_0_BCR>;
5565 reset-names = "pci"; 2474 reset-names = "pci";
5566 power-domains = <&gcc PCIE_0_ 2475 power-domains = <&gcc PCIE_0_GDSC>;
5567 2476
5568 phys = <&pcie0_phy>; 2477 phys = <&pcie0_phy>;
5569 phy-names = "pciephy"; 2478 phy-names = "pciephy";
5570 2479
5571 status = "disabled"; 2480 status = "disabled";
5572 <<
5573 pcie@0 { <<
5574 device_type = "pci"; <<
5575 reg = <0x0 0x0 0x0 0x <<
5576 bus-range = <0x01 0xf <<
5577 <<
5578 #address-cells = <3>; <<
5579 #size-cells = <2>; <<
5580 ranges; <<
5581 }; <<
5582 }; <<
5583 <<
5584 pcie0_ep: pcie-ep@1c00000 { <<
5585 compatible = "qcom,sa8775p-pc <<
5586 reg = <0x0 0x01c00000 0x0 0x3 <<
5587 <0x0 0x40000000 0x0 0xf <<
5588 <0x0 0x40000f20 0x0 0xa <<
5589 <0x0 0x40001000 0x0 0x4 <<
5590 <0x0 0x40200000 0x0 0x1 <<
5591 <0x0 0x01c03000 0x0 0x1 <<
5592 <0x0 0x40005000 0x0 0x2 <<
5593 reg-names = "parf", "dbi", "e <<
5594 "mmio", "dma"; <<
5595 <<
5596 clocks = <&gcc GCC_PCIE_0_AUX <<
5597 <&gcc GCC_PCIE_0_CFG_ <<
5598 <&gcc GCC_PCIE_0_MSTR <<
5599 <&gcc GCC_PCIE_0_SLV_ <<
5600 <&gcc GCC_PCIE_0_SLV_ <<
5601 <<
5602 clock-names = "aux", <<
5603 "cfg", <<
5604 "bus_master", <<
5605 "bus_slave", <<
5606 "slave_q2a"; <<
5607 <<
5608 interrupts = <GIC_SPI 306 IRQ <<
5609 <GIC_SPI 147 IRQ <<
5610 <GIC_SPI 630 IRQ <<
5611 <<
5612 interrupt-names = "global", " <<
5613 <<
5614 interconnects = <&pcie_anoc M <<
5615 <&gem_noc MAS <<
5616 interconnect-names = "pcie-me <<
5617 <<
5618 dma-coherent; <<
5619 iommus = <&pcie_smmu 0x0000 0 <<
5620 resets = <&gcc GCC_PCIE_0_BCR <<
5621 reset-names = "core"; <<
5622 power-domains = <&gcc PCIE_0_ <<
5623 phys = <&pcie0_phy>; <<
5624 phy-names = "pciephy"; <<
5625 max-link-speed = <3>; /* FIXM <<
5626 num-lanes = <2>; <<
5627 <<
5628 status = "disabled"; <<
5629 }; 2481 };
5630 2482
5631 pcie0_phy: phy@1c04000 { 2483 pcie0_phy: phy@1c04000 {
5632 compatible = "qcom,sa8775p-qm 2484 compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy";
5633 reg = <0x0 0x1c04000 0x0 0x20 2485 reg = <0x0 0x1c04000 0x0 0x2000>;
5634 2486
5635 clocks = <&gcc GCC_PCIE_0_AUX 2487 clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
5636 <&gcc GCC_PCIE_0_CFG 2488 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
5637 <&gcc GCC_PCIE_CLKRE 2489 <&gcc GCC_PCIE_CLKREF_EN>,
5638 <&gcc GCC_PCIE_0_PHY 2490 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
5639 <&gcc GCC_PCIE_0_PIP 2491 <&gcc GCC_PCIE_0_PIPE_CLK>,
5640 <&gcc GCC_PCIE_0_PIP 2492 <&gcc GCC_PCIE_0_PIPEDIV2_CLK>,
5641 <&gcc GCC_PCIE_0_PHY 2493 <&gcc GCC_PCIE_0_PHY_AUX_CLK>;
5642 2494
5643 clock-names = "aux", "cfg_ahb 2495 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe",
5644 "pipediv2", "ph 2496 "pipediv2", "phy_aux";
5645 2497
5646 assigned-clocks = <&gcc GCC_P 2498 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
5647 assigned-clock-rates = <10000 2499 assigned-clock-rates = <100000000>;
5648 2500
5649 resets = <&gcc GCC_PCIE_0_PHY 2501 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
5650 reset-names = "phy"; 2502 reset-names = "phy";
5651 2503
5652 #clock-cells = <0>; 2504 #clock-cells = <0>;
5653 clock-output-names = "pcie_0_ 2505 clock-output-names = "pcie_0_pipe_clk";
5654 2506
5655 #phy-cells = <0>; 2507 #phy-cells = <0>;
5656 2508
5657 status = "disabled"; 2509 status = "disabled";
5658 }; 2510 };
5659 2511
5660 pcie1: pcie@1c10000 { !! 2512 pcie1: pci@1c10000{
5661 compatible = "qcom,pcie-sa877 2513 compatible = "qcom,pcie-sa8775p";
5662 reg = <0x0 0x01c10000 0x0 0x3 2514 reg = <0x0 0x01c10000 0x0 0x3000>,
5663 <0x0 0x60000000 0x0 0xf 2515 <0x0 0x60000000 0x0 0xf20>,
5664 <0x0 0x60000f20 0x0 0xa 2516 <0x0 0x60000f20 0x0 0xa8>,
5665 <0x0 0x60001000 0x0 0x4 2517 <0x0 0x60001000 0x0 0x4000>,
5666 <0x0 0x60100000 0x0 0x1 2518 <0x0 0x60100000 0x0 0x100000>,
5667 <0x0 0x01c13000 0x0 0x1 2519 <0x0 0x01c13000 0x0 0x1000>;
5668 reg-names = "parf", "dbi", "e 2520 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
5669 device_type = "pci"; 2521 device_type = "pci";
5670 2522
5671 #address-cells = <3>; 2523 #address-cells = <3>;
5672 #size-cells = <2>; 2524 #size-cells = <2>;
5673 ranges = <0x01000000 0x0 0x00 2525 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
5674 <0x02000000 0x0 0x60 2526 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x1fd00000>;
5675 bus-range = <0x00 0xff>; 2527 bus-range = <0x00 0xff>;
5676 2528
5677 dma-coherent; 2529 dma-coherent;
5678 2530
5679 linux,pci-domain = <1>; 2531 linux,pci-domain = <1>;
5680 num-lanes = <4>; 2532 num-lanes = <4>;
5681 2533
5682 interrupts = <GIC_SPI 519 IRQ 2534 interrupts = <GIC_SPI 519 IRQ_TYPE_LEVEL_HIGH>,
5683 <GIC_SPI 140 IRQ 2535 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
5684 <GIC_SPI 141 IRQ 2536 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
5685 <GIC_SPI 142 IRQ 2537 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
5686 <GIC_SPI 143 IRQ 2538 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
5687 <GIC_SPI 144 IRQ 2539 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
5688 <GIC_SPI 145 IRQ 2540 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
5689 <GIC_SPI 146 IRQ 2541 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
5690 interrupt-names = "msi0", "ms 2542 interrupt-names = "msi0", "msi1", "msi2", "msi3",
5691 "msi4", "ms 2543 "msi4", "msi5", "msi6", "msi7";
5692 #interrupt-cells = <1>; 2544 #interrupt-cells = <1>;
5693 interrupt-map-mask = <0 0 0 0 2545 interrupt-map-mask = <0 0 0 0x7>;
5694 interrupt-map = <0 0 0 1 &int 2546 interrupt-map = <0 0 0 1 &intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
5695 <0 0 0 2 &int 2547 <0 0 0 2 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
5696 <0 0 0 3 &int 2548 <0 0 0 3 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
5697 <0 0 0 4 &int 2549 <0 0 0 4 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
5698 2550
5699 clocks = <&gcc GCC_PCIE_1_AUX 2551 clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
5700 <&gcc GCC_PCIE_1_CFG 2552 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
5701 <&gcc GCC_PCIE_1_MST 2553 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
5702 <&gcc GCC_PCIE_1_SLV 2554 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
5703 <&gcc GCC_PCIE_1_SLV 2555 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>;
5704 2556
5705 clock-names = "aux", 2557 clock-names = "aux",
5706 "cfg", 2558 "cfg",
5707 "bus_master", 2559 "bus_master",
5708 "bus_slave", 2560 "bus_slave",
5709 "slave_q2a"; 2561 "slave_q2a";
5710 2562
5711 assigned-clocks = <&gcc GCC_P 2563 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
5712 assigned-clock-rates = <19200 2564 assigned-clock-rates = <19200000>;
5713 2565
5714 interconnects = <&pcie_anoc M 2566 interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>,
5715 <&gem_noc MAS 2567 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>;
5716 interconnect-names = "pcie-me 2568 interconnect-names = "pcie-mem", "cpu-pcie";
5717 2569
5718 iommu-map = <0x0 &pcie_smmu 0 2570 iommu-map = <0x0 &pcie_smmu 0x0080 0x1>,
5719 <0x100 &pcie_smmu 2571 <0x100 &pcie_smmu 0x0081 0x1>;
5720 2572
5721 resets = <&gcc GCC_PCIE_1_BCR 2573 resets = <&gcc GCC_PCIE_1_BCR>;
5722 reset-names = "pci"; 2574 reset-names = "pci";
5723 power-domains = <&gcc PCIE_1_ 2575 power-domains = <&gcc PCIE_1_GDSC>;
5724 2576
5725 phys = <&pcie1_phy>; 2577 phys = <&pcie1_phy>;
5726 phy-names = "pciephy"; 2578 phy-names = "pciephy";
5727 <<
5728 status = "disabled"; <<
5729 <<
5730 pcie@0 { <<
5731 device_type = "pci"; <<
5732 reg = <0x0 0x0 0x0 0x <<
5733 bus-range = <0x01 0xf <<
5734 <<
5735 #address-cells = <3>; <<
5736 #size-cells = <2>; <<
5737 ranges; <<
5738 }; <<
5739 }; <<
5740 <<
5741 pcie1_ep: pcie-ep@1c10000 { <<
5742 compatible = "qcom,sa8775p-pc <<
5743 reg = <0x0 0x01c10000 0x0 0x3 <<
5744 <0x0 0x60000000 0x0 0xf <<
5745 <0x0 0x60000f20 0x0 0xa <<
5746 <0x0 0x60001000 0x0 0x4 <<
5747 <0x0 0x60200000 0x0 0x1 <<
5748 <0x0 0x01c13000 0x0 0x1 <<
5749 <0x0 0x60005000 0x0 0x2 <<
5750 reg-names = "parf", "dbi", "e <<
5751 "mmio", "dma"; <<
5752 <<
5753 clocks = <&gcc GCC_PCIE_1_AUX <<
5754 <&gcc GCC_PCIE_1_CFG <<
5755 <&gcc GCC_PCIE_1_MST <<
5756 <&gcc GCC_PCIE_1_SLV <<
5757 <&gcc GCC_PCIE_1_SLV <<
5758 <<
5759 clock-names = "aux", <<
5760 "cfg", <<
5761 "bus_master", <<
5762 "bus_slave", <<
5763 "slave_q2a"; <<
5764 <<
5765 interrupts = <GIC_SPI 518 IRQ <<
5766 <GIC_SPI 152 IRQ <<
5767 <GIC_SPI 474 IRQ <<
5768 <<
5769 interrupt-names = "global", " <<
5770 <<
5771 interconnects = <&pcie_anoc M <<
5772 <&gem_noc MAS <<
5773 interconnect-names = "pcie-me <<
5774 <<
5775 dma-coherent; <<
5776 iommus = <&pcie_smmu 0x80 0x7 <<
5777 resets = <&gcc GCC_PCIE_1_BCR <<
5778 reset-names = "core"; <<
5779 power-domains = <&gcc PCIE_1_ <<
5780 phys = <&pcie1_phy>; <<
5781 phy-names = "pciephy"; <<
5782 max-link-speed = <3>; /* FIXM <<
5783 num-lanes = <4>; <<
5784 2579
5785 status = "disabled"; 2580 status = "disabled";
5786 }; 2581 };
5787 2582
5788 pcie1_phy: phy@1c14000 { 2583 pcie1_phy: phy@1c14000 {
5789 compatible = "qcom,sa8775p-qm 2584 compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy";
5790 reg = <0x0 0x1c14000 0x0 0x40 2585 reg = <0x0 0x1c14000 0x0 0x4000>;
5791 2586
5792 clocks = <&gcc GCC_PCIE_1_AUX 2587 clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
5793 <&gcc GCC_PCIE_1_CFG 2588 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
5794 <&gcc GCC_PCIE_CLKRE 2589 <&gcc GCC_PCIE_CLKREF_EN>,
5795 <&gcc GCC_PCIE_1_PHY 2590 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
5796 <&gcc GCC_PCIE_1_PIP 2591 <&gcc GCC_PCIE_1_PIPE_CLK>,
5797 <&gcc GCC_PCIE_1_PIP 2592 <&gcc GCC_PCIE_1_PIPEDIV2_CLK>,
5798 <&gcc GCC_PCIE_1_PHY 2593 <&gcc GCC_PCIE_1_PHY_AUX_CLK>;
5799 2594
5800 clock-names = "aux", "cfg_ahb 2595 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe",
5801 "pipediv2", "ph 2596 "pipediv2", "phy_aux";
5802 2597
5803 assigned-clocks = <&gcc GCC_P 2598 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
5804 assigned-clock-rates = <10000 2599 assigned-clock-rates = <100000000>;
5805 2600
5806 resets = <&gcc GCC_PCIE_1_PHY 2601 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
5807 reset-names = "phy"; 2602 reset-names = "phy";
5808 2603
5809 #clock-cells = <0>; 2604 #clock-cells = <0>;
5810 clock-output-names = "pcie_1_ 2605 clock-output-names = "pcie_1_pipe_clk";
5811 2606
5812 #phy-cells = <0>; 2607 #phy-cells = <0>;
5813 2608
5814 status = "disabled"; 2609 status = "disabled";
5815 }; 2610 };
5816 }; 2611 };
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