1 // SPDX-License-Identifier: BSD-3-Clause 1 // SPDX-License-Identifier: BSD-3-Clause
2 /* 2 /*
3 * Copyright (c) 2023, Linaro Limited 3 * Copyright (c) 2023, Linaro Limited
4 */ 4 */
5 5
6 #include <dt-bindings/interconnect/qcom,icc.h> 6 #include <dt-bindings/interconnect/qcom,icc.h>
7 #include <dt-bindings/interrupt-controller/arm 7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/clock/qcom,rpmh.h> 8 #include <dt-bindings/clock/qcom,rpmh.h>
9 #include <dt-bindings/clock/qcom,sa8775p-gcc.h 9 #include <dt-bindings/clock/qcom,sa8775p-gcc.h>
10 #include <dt-bindings/clock/qcom,sa8775p-gpucc 10 #include <dt-bindings/clock/qcom,sa8775p-gpucc.h>
11 #include <dt-bindings/interconnect/qcom,sa8775 11 #include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h>
12 #include <dt-bindings/mailbox/qcom-ipcc.h> 12 #include <dt-bindings/mailbox/qcom-ipcc.h>
13 #include <dt-bindings/firmware/qcom,scm.h> <<
14 #include <dt-bindings/power/qcom,rpmhpd.h> <<
15 #include <dt-bindings/power/qcom-rpmpd.h> 13 #include <dt-bindings/power/qcom-rpmpd.h>
16 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 14 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
17 15
18 / { 16 / {
19 interrupt-parent = <&intc>; 17 interrupt-parent = <&intc>;
20 18
21 #address-cells = <2>; 19 #address-cells = <2>;
22 #size-cells = <2>; 20 #size-cells = <2>;
23 21
24 clocks { 22 clocks {
25 xo_board_clk: xo-board-clk { 23 xo_board_clk: xo-board-clk {
26 compatible = "fixed-cl 24 compatible = "fixed-clock";
27 #clock-cells = <0>; 25 #clock-cells = <0>;
28 }; 26 };
29 27
30 sleep_clk: sleep-clk { 28 sleep_clk: sleep-clk {
31 compatible = "fixed-cl 29 compatible = "fixed-clock";
32 #clock-cells = <0>; 30 #clock-cells = <0>;
33 }; 31 };
34 }; 32 };
35 33
36 cpus { 34 cpus {
37 #address-cells = <2>; 35 #address-cells = <2>;
38 #size-cells = <0>; 36 #size-cells = <0>;
39 37
40 CPU0: cpu@0 { 38 CPU0: cpu@0 {
41 device_type = "cpu"; 39 device_type = "cpu";
42 compatible = "qcom,kry 40 compatible = "qcom,kryo";
43 reg = <0x0 0x0>; 41 reg = <0x0 0x0>;
44 enable-method = "psci" 42 enable-method = "psci";
45 qcom,freq-domain = <&c 43 qcom,freq-domain = <&cpufreq_hw 0>;
46 next-level-cache = <&L 44 next-level-cache = <&L2_0>;
47 capacity-dmips-mhz = < <<
48 dynamic-power-coeffici <<
49 L2_0: l2-cache { 45 L2_0: l2-cache {
50 compatible = " 46 compatible = "cache";
51 cache-level = 47 cache-level = <2>;
52 cache-unified; 48 cache-unified;
53 next-level-cac 49 next-level-cache = <&L3_0>;
54 L3_0: l3-cache 50 L3_0: l3-cache {
55 compat 51 compatible = "cache";
56 cache- 52 cache-level = <3>;
57 cache- 53 cache-unified;
58 }; 54 };
59 }; 55 };
60 }; 56 };
61 57
62 CPU1: cpu@100 { 58 CPU1: cpu@100 {
63 device_type = "cpu"; 59 device_type = "cpu";
64 compatible = "qcom,kry 60 compatible = "qcom,kryo";
65 reg = <0x0 0x100>; 61 reg = <0x0 0x100>;
66 enable-method = "psci" 62 enable-method = "psci";
67 qcom,freq-domain = <&c 63 qcom,freq-domain = <&cpufreq_hw 0>;
68 next-level-cache = <&L 64 next-level-cache = <&L2_1>;
69 capacity-dmips-mhz = < <<
70 dynamic-power-coeffici <<
71 L2_1: l2-cache { 65 L2_1: l2-cache {
72 compatible = " 66 compatible = "cache";
73 cache-level = 67 cache-level = <2>;
74 cache-unified; 68 cache-unified;
75 next-level-cac 69 next-level-cache = <&L3_0>;
76 }; 70 };
77 }; 71 };
78 72
79 CPU2: cpu@200 { 73 CPU2: cpu@200 {
80 device_type = "cpu"; 74 device_type = "cpu";
81 compatible = "qcom,kry 75 compatible = "qcom,kryo";
82 reg = <0x0 0x200>; 76 reg = <0x0 0x200>;
83 enable-method = "psci" 77 enable-method = "psci";
84 qcom,freq-domain = <&c 78 qcom,freq-domain = <&cpufreq_hw 0>;
85 next-level-cache = <&L 79 next-level-cache = <&L2_2>;
86 capacity-dmips-mhz = < <<
87 dynamic-power-coeffici <<
88 L2_2: l2-cache { 80 L2_2: l2-cache {
89 compatible = " 81 compatible = "cache";
90 cache-level = 82 cache-level = <2>;
91 cache-unified; 83 cache-unified;
92 next-level-cac 84 next-level-cache = <&L3_0>;
93 }; 85 };
94 }; 86 };
95 87
96 CPU3: cpu@300 { 88 CPU3: cpu@300 {
97 device_type = "cpu"; 89 device_type = "cpu";
98 compatible = "qcom,kry 90 compatible = "qcom,kryo";
99 reg = <0x0 0x300>; 91 reg = <0x0 0x300>;
100 enable-method = "psci" 92 enable-method = "psci";
101 qcom,freq-domain = <&c 93 qcom,freq-domain = <&cpufreq_hw 0>;
102 next-level-cache = <&L 94 next-level-cache = <&L2_3>;
103 capacity-dmips-mhz = < <<
104 dynamic-power-coeffici <<
105 L2_3: l2-cache { 95 L2_3: l2-cache {
106 compatible = " 96 compatible = "cache";
107 cache-level = 97 cache-level = <2>;
108 cache-unified; 98 cache-unified;
109 next-level-cac 99 next-level-cache = <&L3_0>;
110 }; 100 };
111 }; 101 };
112 102
113 CPU4: cpu@10000 { 103 CPU4: cpu@10000 {
114 device_type = "cpu"; 104 device_type = "cpu";
115 compatible = "qcom,kry 105 compatible = "qcom,kryo";
116 reg = <0x0 0x10000>; 106 reg = <0x0 0x10000>;
117 enable-method = "psci" 107 enable-method = "psci";
118 qcom,freq-domain = <&c 108 qcom,freq-domain = <&cpufreq_hw 1>;
119 next-level-cache = <&L 109 next-level-cache = <&L2_4>;
120 capacity-dmips-mhz = < <<
121 dynamic-power-coeffici <<
122 L2_4: l2-cache { 110 L2_4: l2-cache {
123 compatible = " 111 compatible = "cache";
124 cache-level = 112 cache-level = <2>;
125 cache-unified; 113 cache-unified;
126 next-level-cac 114 next-level-cache = <&L3_1>;
127 L3_1: l3-cache 115 L3_1: l3-cache {
128 compat 116 compatible = "cache";
129 cache- 117 cache-level = <3>;
130 cache- 118 cache-unified;
131 }; 119 };
132 120
133 }; 121 };
134 }; 122 };
135 123
136 CPU5: cpu@10100 { 124 CPU5: cpu@10100 {
137 device_type = "cpu"; 125 device_type = "cpu";
138 compatible = "qcom,kry 126 compatible = "qcom,kryo";
139 reg = <0x0 0x10100>; 127 reg = <0x0 0x10100>;
140 enable-method = "psci" 128 enable-method = "psci";
141 qcom,freq-domain = <&c 129 qcom,freq-domain = <&cpufreq_hw 1>;
142 next-level-cache = <&L 130 next-level-cache = <&L2_5>;
143 capacity-dmips-mhz = < <<
144 dynamic-power-coeffici <<
145 L2_5: l2-cache { 131 L2_5: l2-cache {
146 compatible = " 132 compatible = "cache";
147 cache-level = 133 cache-level = <2>;
148 cache-unified; 134 cache-unified;
149 next-level-cac 135 next-level-cache = <&L3_1>;
150 }; 136 };
151 }; 137 };
152 138
153 CPU6: cpu@10200 { 139 CPU6: cpu@10200 {
154 device_type = "cpu"; 140 device_type = "cpu";
155 compatible = "qcom,kry 141 compatible = "qcom,kryo";
156 reg = <0x0 0x10200>; 142 reg = <0x0 0x10200>;
157 enable-method = "psci" 143 enable-method = "psci";
158 qcom,freq-domain = <&c 144 qcom,freq-domain = <&cpufreq_hw 1>;
159 next-level-cache = <&L 145 next-level-cache = <&L2_6>;
160 capacity-dmips-mhz = < <<
161 dynamic-power-coeffici <<
162 L2_6: l2-cache { 146 L2_6: l2-cache {
163 compatible = " 147 compatible = "cache";
164 cache-level = 148 cache-level = <2>;
165 cache-unified; 149 cache-unified;
166 next-level-cac 150 next-level-cache = <&L3_1>;
167 }; 151 };
168 }; 152 };
169 153
170 CPU7: cpu@10300 { 154 CPU7: cpu@10300 {
171 device_type = "cpu"; 155 device_type = "cpu";
172 compatible = "qcom,kry 156 compatible = "qcom,kryo";
173 reg = <0x0 0x10300>; 157 reg = <0x0 0x10300>;
174 enable-method = "psci" 158 enable-method = "psci";
175 qcom,freq-domain = <&c 159 qcom,freq-domain = <&cpufreq_hw 1>;
176 next-level-cache = <&L 160 next-level-cache = <&L2_7>;
177 capacity-dmips-mhz = < <<
178 dynamic-power-coeffici <<
179 L2_7: l2-cache { 161 L2_7: l2-cache {
180 compatible = " 162 compatible = "cache";
181 cache-level = 163 cache-level = <2>;
182 cache-unified; 164 cache-unified;
183 next-level-cac 165 next-level-cache = <&L3_1>;
184 }; 166 };
185 }; 167 };
186 168
187 cpu-map { 169 cpu-map {
188 cluster0 { 170 cluster0 {
189 core0 { 171 core0 {
190 cpu = 172 cpu = <&CPU0>;
191 }; 173 };
192 174
193 core1 { 175 core1 {
194 cpu = 176 cpu = <&CPU1>;
195 }; 177 };
196 178
197 core2 { 179 core2 {
198 cpu = 180 cpu = <&CPU2>;
199 }; 181 };
200 182
201 core3 { 183 core3 {
202 cpu = 184 cpu = <&CPU3>;
203 }; 185 };
204 }; 186 };
205 187
206 cluster1 { 188 cluster1 {
207 core0 { 189 core0 {
208 cpu = 190 cpu = <&CPU4>;
209 }; 191 };
210 192
211 core1 { 193 core1 {
212 cpu = 194 cpu = <&CPU5>;
213 }; 195 };
214 196
215 core2 { 197 core2 {
216 cpu = 198 cpu = <&CPU6>;
217 }; 199 };
218 200
219 core3 { 201 core3 {
220 cpu = 202 cpu = <&CPU7>;
221 }; 203 };
222 }; 204 };
223 }; 205 };
224 <<
225 idle-states { <<
226 entry-method = "psci"; <<
227 <<
228 GOLD_CPU_SLEEP_0: cpu- <<
229 compatible = " <<
230 idle-state-nam <<
231 arm,psci-suspe <<
232 entry-latency- <<
233 exit-latency-u <<
234 min-residency- <<
235 local-timer-st <<
236 }; <<
237 <<
238 GOLD_RAIL_CPU_SLEEP_0: <<
239 compatible = " <<
240 idle-state-nam <<
241 arm,psci-suspe <<
242 entry-latency- <<
243 exit-latency-u <<
244 min-residency- <<
245 local-timer-st <<
246 }; <<
247 }; <<
248 <<
249 domain-idle-states { <<
250 CLUSTER_SLEEP_GOLD: cl <<
251 compatible = " <<
252 arm,psci-suspe <<
253 entry-latency- <<
254 exit-latency-u <<
255 min-residency- <<
256 }; <<
257 <<
258 CLUSTER_SLEEP_APSS_RSC <<
259 compatible = " <<
260 arm,psci-suspe <<
261 entry-latency- <<
262 exit-latency-u <<
263 min-residency- <<
264 }; <<
265 }; <<
266 }; <<
267 <<
268 dummy-sink { <<
269 compatible = "arm,coresight-du <<
270 <<
271 in-ports { <<
272 port { <<
273 eud_in: endpoi <<
274 remote <<
275 <&swao <<
276 }; <<
277 }; <<
278 }; <<
279 }; 206 };
280 207
281 firmware { 208 firmware {
282 scm { 209 scm {
283 compatible = "qcom,scm 210 compatible = "qcom,scm-sa8775p", "qcom,scm";
284 memory-region = <&tz_f <<
285 }; 211 };
286 }; 212 };
287 213
288 aggre1_noc: interconnect-aggre1-noc { 214 aggre1_noc: interconnect-aggre1-noc {
289 compatible = "qcom,sa8775p-agg 215 compatible = "qcom,sa8775p-aggre1-noc";
290 #interconnect-cells = <2>; 216 #interconnect-cells = <2>;
291 qcom,bcm-voters = <&apps_bcm_v 217 qcom,bcm-voters = <&apps_bcm_voter>;
292 }; 218 };
293 219
294 aggre2_noc: interconnect-aggre2-noc { 220 aggre2_noc: interconnect-aggre2-noc {
295 compatible = "qcom,sa8775p-agg 221 compatible = "qcom,sa8775p-aggre2-noc";
296 #interconnect-cells = <2>; 222 #interconnect-cells = <2>;
297 qcom,bcm-voters = <&apps_bcm_v 223 qcom,bcm-voters = <&apps_bcm_voter>;
298 }; 224 };
299 225
300 clk_virt: interconnect-clk-virt { 226 clk_virt: interconnect-clk-virt {
301 compatible = "qcom,sa8775p-clk 227 compatible = "qcom,sa8775p-clk-virt";
302 #interconnect-cells = <2>; 228 #interconnect-cells = <2>;
303 qcom,bcm-voters = <&apps_bcm_v 229 qcom,bcm-voters = <&apps_bcm_voter>;
304 }; 230 };
305 231
306 config_noc: interconnect-config-noc { 232 config_noc: interconnect-config-noc {
307 compatible = "qcom,sa8775p-con 233 compatible = "qcom,sa8775p-config-noc";
308 #interconnect-cells = <2>; 234 #interconnect-cells = <2>;
309 qcom,bcm-voters = <&apps_bcm_v 235 qcom,bcm-voters = <&apps_bcm_voter>;
310 }; 236 };
311 237
312 dc_noc: interconnect-dc-noc { 238 dc_noc: interconnect-dc-noc {
313 compatible = "qcom,sa8775p-dc- 239 compatible = "qcom,sa8775p-dc-noc";
314 #interconnect-cells = <2>; 240 #interconnect-cells = <2>;
315 qcom,bcm-voters = <&apps_bcm_v 241 qcom,bcm-voters = <&apps_bcm_voter>;
316 }; 242 };
317 243
318 gem_noc: interconnect-gem-noc { 244 gem_noc: interconnect-gem-noc {
319 compatible = "qcom,sa8775p-gem 245 compatible = "qcom,sa8775p-gem-noc";
320 #interconnect-cells = <2>; 246 #interconnect-cells = <2>;
321 qcom,bcm-voters = <&apps_bcm_v 247 qcom,bcm-voters = <&apps_bcm_voter>;
322 }; 248 };
323 249
324 gpdsp_anoc: interconnect-gpdsp-anoc { 250 gpdsp_anoc: interconnect-gpdsp-anoc {
325 compatible = "qcom,sa8775p-gpd 251 compatible = "qcom,sa8775p-gpdsp-anoc";
326 #interconnect-cells = <2>; 252 #interconnect-cells = <2>;
327 qcom,bcm-voters = <&apps_bcm_v 253 qcom,bcm-voters = <&apps_bcm_voter>;
328 }; 254 };
329 255
330 lpass_ag_noc: interconnect-lpass-ag-no 256 lpass_ag_noc: interconnect-lpass-ag-noc {
331 compatible = "qcom,sa8775p-lpa 257 compatible = "qcom,sa8775p-lpass-ag-noc";
332 #interconnect-cells = <2>; 258 #interconnect-cells = <2>;
333 qcom,bcm-voters = <&apps_bcm_v 259 qcom,bcm-voters = <&apps_bcm_voter>;
334 }; 260 };
335 261
336 mc_virt: interconnect-mc-virt { 262 mc_virt: interconnect-mc-virt {
337 compatible = "qcom,sa8775p-mc- 263 compatible = "qcom,sa8775p-mc-virt";
338 #interconnect-cells = <2>; 264 #interconnect-cells = <2>;
339 qcom,bcm-voters = <&apps_bcm_v 265 qcom,bcm-voters = <&apps_bcm_voter>;
340 }; 266 };
341 267
342 mmss_noc: interconnect-mmss-noc { 268 mmss_noc: interconnect-mmss-noc {
343 compatible = "qcom,sa8775p-mms 269 compatible = "qcom,sa8775p-mmss-noc";
344 #interconnect-cells = <2>; 270 #interconnect-cells = <2>;
345 qcom,bcm-voters = <&apps_bcm_v 271 qcom,bcm-voters = <&apps_bcm_voter>;
346 }; 272 };
347 273
348 nspa_noc: interconnect-nspa-noc { 274 nspa_noc: interconnect-nspa-noc {
349 compatible = "qcom,sa8775p-nsp 275 compatible = "qcom,sa8775p-nspa-noc";
350 #interconnect-cells = <2>; 276 #interconnect-cells = <2>;
351 qcom,bcm-voters = <&apps_bcm_v 277 qcom,bcm-voters = <&apps_bcm_voter>;
352 }; 278 };
353 279
354 nspb_noc: interconnect-nspb-noc { 280 nspb_noc: interconnect-nspb-noc {
355 compatible = "qcom,sa8775p-nsp 281 compatible = "qcom,sa8775p-nspb-noc";
356 #interconnect-cells = <2>; 282 #interconnect-cells = <2>;
357 qcom,bcm-voters = <&apps_bcm_v 283 qcom,bcm-voters = <&apps_bcm_voter>;
358 }; 284 };
359 285
360 pcie_anoc: interconnect-pcie-anoc { 286 pcie_anoc: interconnect-pcie-anoc {
361 compatible = "qcom,sa8775p-pci 287 compatible = "qcom,sa8775p-pcie-anoc";
362 #interconnect-cells = <2>; 288 #interconnect-cells = <2>;
363 qcom,bcm-voters = <&apps_bcm_v 289 qcom,bcm-voters = <&apps_bcm_voter>;
364 }; 290 };
365 291
366 system_noc: interconnect-system-noc { 292 system_noc: interconnect-system-noc {
367 compatible = "qcom,sa8775p-sys 293 compatible = "qcom,sa8775p-system-noc";
368 #interconnect-cells = <2>; 294 #interconnect-cells = <2>;
369 qcom,bcm-voters = <&apps_bcm_v 295 qcom,bcm-voters = <&apps_bcm_voter>;
370 }; 296 };
371 297
372 /* Will be updated by the bootloader. 298 /* Will be updated by the bootloader. */
373 memory@80000000 { 299 memory@80000000 {
374 device_type = "memory"; 300 device_type = "memory";
375 reg = <0x0 0x80000000 0x0 0x0> 301 reg = <0x0 0x80000000 0x0 0x0>;
376 }; 302 };
377 303
378 qup_opp_table_100mhz: opp-table-qup100 304 qup_opp_table_100mhz: opp-table-qup100mhz {
379 compatible = "operating-points 305 compatible = "operating-points-v2";
380 306
381 opp-100000000 { 307 opp-100000000 {
382 opp-hz = /bits/ 64 <10 308 opp-hz = /bits/ 64 <100000000>;
383 required-opps = <&rpmh 309 required-opps = <&rpmhpd_opp_svs_l1>;
384 }; 310 };
385 }; 311 };
386 312
387 pmu { 313 pmu {
388 compatible = "arm,armv8-pmuv3" 314 compatible = "arm,armv8-pmuv3";
389 interrupts = <GIC_PPI 7 IRQ_TY 315 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
390 }; 316 };
391 317
392 psci { 318 psci {
393 compatible = "arm,psci-1.0"; 319 compatible = "arm,psci-1.0";
394 method = "smc"; 320 method = "smc";
395 <<
396 CPU_PD0: power-domain-cpu0 { <<
397 #power-domain-cells = <<
398 power-domains = <&CLUS <<
399 domain-idle-states = < <<
400 < <<
401 }; <<
402 <<
403 CPU_PD1: power-domain-cpu1 { <<
404 #power-domain-cells = <<
405 power-domains = <&CLUS <<
406 domain-idle-states = < <<
407 < <<
408 }; <<
409 <<
410 CPU_PD2: power-domain-cpu2 { <<
411 #power-domain-cells = <<
412 power-domains = <&CLUS <<
413 domain-idle-states = < <<
414 < <<
415 }; <<
416 <<
417 CPU_PD3: power-domain-cpu3 { <<
418 #power-domain-cells = <<
419 power-domains = <&CLUS <<
420 domain-idle-states = < <<
421 < <<
422 }; <<
423 <<
424 CPU_PD4: power-domain-cpu4 { <<
425 #power-domain-cells = <<
426 power-domains = <&CLUS <<
427 domain-idle-states = < <<
428 < <<
429 }; <<
430 <<
431 CPU_PD5: power-domain-cpu5 { <<
432 #power-domain-cells = <<
433 power-domains = <&CLUS <<
434 domain-idle-states = < <<
435 < <<
436 }; <<
437 <<
438 CPU_PD6: power-domain-cpu6 { <<
439 #power-domain-cells = <<
440 power-domains = <&CLUS <<
441 domain-idle-states = < <<
442 < <<
443 }; <<
444 <<
445 CPU_PD7: power-domain-cpu7 { <<
446 #power-domain-cells = <<
447 power-domains = <&CLUS <<
448 domain-idle-states = < <<
449 < <<
450 }; <<
451 <<
452 CLUSTER_0_PD: power-domain-clu <<
453 #power-domain-cells = <<
454 power-domains = <&CLUS <<
455 domain-idle-states = < <<
456 }; <<
457 <<
458 CLUSTER_1_PD: power-domain-clu <<
459 #power-domain-cells = <<
460 power-domains = <&CLUS <<
461 domain-idle-states = < <<
462 }; <<
463 <<
464 CLUSTER_2_PD: power-domain-clu <<
465 #power-domain-cells = <<
466 domain-idle-states = < <<
467 }; <<
468 }; 321 };
469 322
470 reserved-memory { 323 reserved-memory {
471 #address-cells = <2>; 324 #address-cells = <2>;
472 #size-cells = <2>; 325 #size-cells = <2>;
473 ranges; 326 ranges;
474 327
475 sail_ss_mem: sail-ss@80000000 328 sail_ss_mem: sail-ss@80000000 {
476 reg = <0x0 0x80000000 329 reg = <0x0 0x80000000 0x0 0x10000000>;
477 no-map; 330 no-map;
478 }; 331 };
479 332
480 hyp_mem: hyp@90000000 { 333 hyp_mem: hyp@90000000 {
481 reg = <0x0 0x90000000 334 reg = <0x0 0x90000000 0x0 0x600000>;
482 no-map; 335 no-map;
483 }; 336 };
484 337
485 xbl_boot_mem: xbl-boot@9060000 338 xbl_boot_mem: xbl-boot@90600000 {
486 reg = <0x0 0x90600000 339 reg = <0x0 0x90600000 0x0 0x200000>;
487 no-map; 340 no-map;
488 }; 341 };
489 342
490 aop_image_mem: aop-image@90800 343 aop_image_mem: aop-image@90800000 {
491 reg = <0x0 0x90800000 344 reg = <0x0 0x90800000 0x0 0x60000>;
492 no-map; 345 no-map;
493 }; 346 };
494 347
495 aop_cmd_db_mem: aop-cmd-db@908 348 aop_cmd_db_mem: aop-cmd-db@90860000 {
496 compatible = "qcom,cmd 349 compatible = "qcom,cmd-db";
497 reg = <0x0 0x90860000 350 reg = <0x0 0x90860000 0x0 0x20000>;
498 no-map; 351 no-map;
499 }; 352 };
500 353
501 uefi_log: uefi-log@908b0000 { 354 uefi_log: uefi-log@908b0000 {
502 reg = <0x0 0x908b0000 355 reg = <0x0 0x908b0000 0x0 0x10000>;
503 no-map; 356 no-map;
504 }; 357 };
505 358
506 ddr_training_checksum: ddr-tra 359 ddr_training_checksum: ddr-training-checksum@908c0000 {
507 reg = <0x0 0x908c0000 360 reg = <0x0 0x908c0000 0x0 0x1000>;
508 no-map; 361 no-map;
509 }; 362 };
510 363
511 reserved_mem: reserved@908f000 364 reserved_mem: reserved@908f0000 {
512 reg = <0x0 0x908f0000 365 reg = <0x0 0x908f0000 0x0 0xe000>;
513 no-map; 366 no-map;
514 }; 367 };
515 368
516 secdata_apss_mem: secdata-apss 369 secdata_apss_mem: secdata-apss@908fe000 {
517 reg = <0x0 0x908fe000 370 reg = <0x0 0x908fe000 0x0 0x2000>;
518 no-map; 371 no-map;
519 }; 372 };
520 373
521 smem_mem: smem@90900000 { 374 smem_mem: smem@90900000 {
522 compatible = "qcom,sme 375 compatible = "qcom,smem";
523 reg = <0x0 0x90900000 376 reg = <0x0 0x90900000 0x0 0x200000>;
524 no-map; 377 no-map;
525 hwlocks = <&tcsr_mutex 378 hwlocks = <&tcsr_mutex 3>;
526 }; 379 };
527 380
528 tz_sail_mailbox_mem: tz-sail-m 381 tz_sail_mailbox_mem: tz-sail-mailbox@90c00000 {
529 reg = <0x0 0x90c00000 382 reg = <0x0 0x90c00000 0x0 0x100000>;
530 no-map; 383 no-map;
531 }; 384 };
532 385
533 sail_mailbox_mem: sail-ss@90d0 386 sail_mailbox_mem: sail-ss@90d00000 {
534 reg = <0x0 0x90d00000 387 reg = <0x0 0x90d00000 0x0 0x100000>;
535 no-map; 388 no-map;
536 }; 389 };
537 390
538 sail_ota_mem: sail-ss@90e00000 391 sail_ota_mem: sail-ss@90e00000 {
539 reg = <0x0 0x90e00000 392 reg = <0x0 0x90e00000 0x0 0x300000>;
540 no-map; 393 no-map;
541 }; 394 };
542 395
543 aoss_backup_mem: aoss-backup@9 396 aoss_backup_mem: aoss-backup@91b00000 {
544 reg = <0x0 0x91b00000 397 reg = <0x0 0x91b00000 0x0 0x40000>;
545 no-map; 398 no-map;
546 }; 399 };
547 400
548 cpucp_backup_mem: cpucp-backup 401 cpucp_backup_mem: cpucp-backup@91b40000 {
549 reg = <0x0 0x91b40000 402 reg = <0x0 0x91b40000 0x0 0x40000>;
550 no-map; 403 no-map;
551 }; 404 };
552 405
553 tz_config_backup_mem: tz-confi 406 tz_config_backup_mem: tz-config-backup@91b80000 {
554 reg = <0x0 0x91b80000 407 reg = <0x0 0x91b80000 0x0 0x10000>;
555 no-map; 408 no-map;
556 }; 409 };
557 410
558 ddr_training_data_mem: ddr-tra 411 ddr_training_data_mem: ddr-training-data@91b90000 {
559 reg = <0x0 0x91b90000 412 reg = <0x0 0x91b90000 0x0 0x10000>;
560 no-map; 413 no-map;
561 }; 414 };
562 415
563 cdt_data_backup_mem: cdt-data- 416 cdt_data_backup_mem: cdt-data-backup@91ba0000 {
564 reg = <0x0 0x91ba0000 417 reg = <0x0 0x91ba0000 0x0 0x1000>;
565 no-map; 418 no-map;
566 }; 419 };
567 420
568 tz_ffi_mem: tz-ffi@91c00000 { <<
569 compatible = "shared-d <<
570 reg = <0x0 0x91c00000 <<
571 no-map; <<
572 }; <<
573 <<
574 lpass_machine_learning_mem: lp 421 lpass_machine_learning_mem: lpass-machine-learning@93b00000 {
575 reg = <0x0 0x93b00000 422 reg = <0x0 0x93b00000 0x0 0xf00000>;
576 no-map; 423 no-map;
577 }; 424 };
578 425
579 adsp_rpc_remote_heap_mem: adsp 426 adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@94a00000 {
580 reg = <0x0 0x94a00000 427 reg = <0x0 0x94a00000 0x0 0x800000>;
581 no-map; 428 no-map;
582 }; 429 };
583 430
584 pil_camera_mem: pil-camera@952 431 pil_camera_mem: pil-camera@95200000 {
585 reg = <0x0 0x95200000 432 reg = <0x0 0x95200000 0x0 0x500000>;
586 no-map; 433 no-map;
587 }; 434 };
588 435
589 pil_adsp_mem: pil-adsp@95c0000 436 pil_adsp_mem: pil-adsp@95c00000 {
590 reg = <0x0 0x95c00000 437 reg = <0x0 0x95c00000 0x0 0x1e00000>;
591 no-map; 438 no-map;
592 }; 439 };
593 440
594 pil_gdsp0_mem: pil-gdsp0@97b00 441 pil_gdsp0_mem: pil-gdsp0@97b00000 {
595 reg = <0x0 0x97b00000 442 reg = <0x0 0x97b00000 0x0 0x1e00000>;
596 no-map; 443 no-map;
597 }; 444 };
598 445
599 pil_gdsp1_mem: pil-gdsp1@99900 446 pil_gdsp1_mem: pil-gdsp1@99900000 {
600 reg = <0x0 0x99900000 447 reg = <0x0 0x99900000 0x0 0x1e00000>;
601 no-map; 448 no-map;
602 }; 449 };
603 450
604 pil_cdsp0_mem: pil-cdsp0@9b800 451 pil_cdsp0_mem: pil-cdsp0@9b800000 {
605 reg = <0x0 0x9b800000 452 reg = <0x0 0x9b800000 0x0 0x1e00000>;
606 no-map; 453 no-map;
607 }; 454 };
608 455
609 pil_gpu_mem: pil-gpu@9d600000 456 pil_gpu_mem: pil-gpu@9d600000 {
610 reg = <0x0 0x9d600000 457 reg = <0x0 0x9d600000 0x0 0x2000>;
611 no-map; 458 no-map;
612 }; 459 };
613 460
614 pil_cdsp1_mem: pil-cdsp1@9d700 461 pil_cdsp1_mem: pil-cdsp1@9d700000 {
615 reg = <0x0 0x9d700000 462 reg = <0x0 0x9d700000 0x0 0x1e00000>;
616 no-map; 463 no-map;
617 }; 464 };
618 465
619 pil_cvp_mem: pil-cvp@9f500000 466 pil_cvp_mem: pil-cvp@9f500000 {
620 reg = <0x0 0x9f500000 467 reg = <0x0 0x9f500000 0x0 0x700000>;
621 no-map; 468 no-map;
622 }; 469 };
623 470
624 pil_video_mem: pil-video@9fc00 471 pil_video_mem: pil-video@9fc00000 {
625 reg = <0x0 0x9fc00000 472 reg = <0x0 0x9fc00000 0x0 0x700000>;
626 no-map; 473 no-map;
627 }; 474 };
628 475
629 audio_mdf_mem: audio-mdf-regio 476 audio_mdf_mem: audio-mdf-region@ae000000 {
630 reg = <0x0 0xae000000 477 reg = <0x0 0xae000000 0x0 0x1000000>;
631 no-map; 478 no-map;
632 }; 479 };
633 480
634 firmware_mem: firmware-region@ 481 firmware_mem: firmware-region@b0000000 {
635 reg = <0x0 0xb0000000 482 reg = <0x0 0xb0000000 0x0 0x800000>;
636 no-map; 483 no-map;
637 }; 484 };
638 485
639 hyptz_reserved_mem: hyptz-rese 486 hyptz_reserved_mem: hyptz-reserved@beb00000 {
640 reg = <0x0 0xbeb00000 487 reg = <0x0 0xbeb00000 0x0 0x11500000>;
641 no-map; 488 no-map;
642 }; 489 };
643 490
644 scmi_mem: scmi-region@d0000000 491 scmi_mem: scmi-region@d0000000 {
645 reg = <0x0 0xd0000000 492 reg = <0x0 0xd0000000 0x0 0x40000>;
646 no-map; 493 no-map;
647 }; 494 };
648 495
649 firmware_logs_mem: firmware-lo 496 firmware_logs_mem: firmware-logs@d0040000 {
650 reg = <0x0 0xd0040000 497 reg = <0x0 0xd0040000 0x0 0x10000>;
651 no-map; 498 no-map;
652 }; 499 };
653 500
654 firmware_audio_mem: firmware-a 501 firmware_audio_mem: firmware-audio@d0050000 {
655 reg = <0x0 0xd0050000 502 reg = <0x0 0xd0050000 0x0 0x4000>;
656 no-map; 503 no-map;
657 }; 504 };
658 505
659 firmware_reserved_mem: firmwar 506 firmware_reserved_mem: firmware-reserved@d0054000 {
660 reg = <0x0 0xd0054000 507 reg = <0x0 0xd0054000 0x0 0x9c000>;
661 no-map; 508 no-map;
662 }; 509 };
663 510
664 firmware_quantum_test_mem: fir 511 firmware_quantum_test_mem: firmware-quantum-test@d00f0000 {
665 reg = <0x0 0xd00f0000 512 reg = <0x0 0xd00f0000 0x0 0x10000>;
666 no-map; 513 no-map;
667 }; 514 };
668 515
669 tags_mem: tags@d0100000 { 516 tags_mem: tags@d0100000 {
670 reg = <0x0 0xd0100000 517 reg = <0x0 0xd0100000 0x0 0x1200000>;
671 no-map; 518 no-map;
672 }; 519 };
673 520
674 qtee_mem: qtee@d1300000 { 521 qtee_mem: qtee@d1300000 {
675 reg = <0x0 0xd1300000 522 reg = <0x0 0xd1300000 0x0 0x500000>;
676 no-map; 523 no-map;
677 }; 524 };
678 525
679 deepsleep_backup_mem: deepslee 526 deepsleep_backup_mem: deepsleep-backup@d1800000 {
680 reg = <0x0 0xd1800000 527 reg = <0x0 0xd1800000 0x0 0x100000>;
681 no-map; 528 no-map;
682 }; 529 };
683 530
684 trusted_apps_mem: trusted-apps 531 trusted_apps_mem: trusted-apps@d1900000 {
685 reg = <0x0 0xd1900000 532 reg = <0x0 0xd1900000 0x0 0x3800000>;
686 no-map; 533 no-map;
687 }; 534 };
688 535
689 tz_stat_mem: tz-stat@db100000 536 tz_stat_mem: tz-stat@db100000 {
690 reg = <0x0 0xdb100000 537 reg = <0x0 0xdb100000 0x0 0x100000>;
691 no-map; 538 no-map;
692 }; 539 };
693 540
694 cpucp_fw_mem: cpucp-fw@db20000 541 cpucp_fw_mem: cpucp-fw@db200000 {
695 reg = <0x0 0xdb200000 542 reg = <0x0 0xdb200000 0x0 0x100000>;
696 no-map; 543 no-map;
697 }; 544 };
698 }; 545 };
699 546
700 smp2p-adsp { <<
701 compatible = "qcom,smp2p"; <<
702 qcom,smem = <443>, <429>; <<
703 interrupts-extended = <&ipcc I <<
704 I <<
705 I <<
706 mboxes = <&ipcc IPCC_CLIENT_LP <<
707 <<
708 qcom,local-pid = <0>; <<
709 qcom,remote-pid = <2>; <<
710 <<
711 smp2p_adsp_out: master-kernel <<
712 qcom,entry-name = "mas <<
713 #qcom,smem-state-cells <<
714 }; <<
715 <<
716 smp2p_adsp_in: slave-kernel { <<
717 qcom,entry-name = "sla <<
718 interrupt-controller; <<
719 #interrupt-cells = <2> <<
720 }; <<
721 }; <<
722 <<
723 smp2p-cdsp0 { <<
724 compatible = "qcom,smp2p"; <<
725 qcom,smem = <94>, <432>; <<
726 interrupts-extended = <&ipcc I <<
727 I <<
728 I <<
729 mboxes = <&ipcc IPCC_CLIENT_CD <<
730 <<
731 qcom,local-pid = <0>; <<
732 qcom,remote-pid = <5>; <<
733 <<
734 smp2p_cdsp0_out: master-kernel <<
735 qcom,entry-name = "mas <<
736 #qcom,smem-state-cells <<
737 }; <<
738 <<
739 smp2p_cdsp0_in: slave-kernel { <<
740 qcom,entry-name = "sla <<
741 interrupt-controller; <<
742 #interrupt-cells = <2> <<
743 }; <<
744 }; <<
745 <<
746 smp2p-cdsp1 { <<
747 compatible = "qcom,smp2p"; <<
748 qcom,smem = <617>, <616>; <<
749 interrupts-extended = <&ipcc I <<
750 I <<
751 I <<
752 mboxes = <&ipcc IPCC_CLIENT_NS <<
753 <<
754 qcom,local-pid = <0>; <<
755 qcom,remote-pid = <12>; <<
756 <<
757 smp2p_cdsp1_out: master-kernel <<
758 qcom,entry-name = "mas <<
759 #qcom,smem-state-cells <<
760 }; <<
761 <<
762 smp2p_cdsp1_in: slave-kernel { <<
763 qcom,entry-name = "sla <<
764 interrupt-controller; <<
765 #interrupt-cells = <2> <<
766 }; <<
767 }; <<
768 <<
769 smp2p-gpdsp0 { <<
770 compatible = "qcom,smp2p"; <<
771 qcom,smem = <617>, <616>; <<
772 interrupts-extended = <&ipcc I <<
773 I <<
774 I <<
775 mboxes = <&ipcc IPCC_CLIENT_GP <<
776 <<
777 qcom,local-pid = <0>; <<
778 qcom,remote-pid = <17>; <<
779 <<
780 smp2p_gpdsp0_out: master-kerne <<
781 qcom,entry-name = "mas <<
782 #qcom,smem-state-cells <<
783 }; <<
784 <<
785 smp2p_gpdsp0_in: slave-kernel <<
786 qcom,entry-name = "sla <<
787 interrupt-controller; <<
788 #interrupt-cells = <2> <<
789 }; <<
790 }; <<
791 <<
792 smp2p-gpdsp1 { <<
793 compatible = "qcom,smp2p"; <<
794 qcom,smem = <617>, <616>; <<
795 interrupts-extended = <&ipcc I <<
796 I <<
797 I <<
798 mboxes = <&ipcc IPCC_CLIENT_GP <<
799 <<
800 qcom,local-pid = <0>; <<
801 qcom,remote-pid = <18>; <<
802 <<
803 smp2p_gpdsp1_out: master-kerne <<
804 qcom,entry-name = "mas <<
805 #qcom,smem-state-cells <<
806 }; <<
807 <<
808 smp2p_gpdsp1_in: slave-kernel <<
809 qcom,entry-name = "sla <<
810 interrupt-controller; <<
811 #interrupt-cells = <2> <<
812 }; <<
813 }; <<
814 <<
815 soc: soc@0 { 547 soc: soc@0 {
816 compatible = "simple-bus"; 548 compatible = "simple-bus";
817 #address-cells = <2>; 549 #address-cells = <2>;
818 #size-cells = <2>; 550 #size-cells = <2>;
819 ranges = <0 0 0 0 0x10 0>; 551 ranges = <0 0 0 0 0x10 0>;
820 552
821 gcc: clock-controller@100000 { 553 gcc: clock-controller@100000 {
822 compatible = "qcom,sa8 554 compatible = "qcom,sa8775p-gcc";
823 reg = <0x0 0x00100000 555 reg = <0x0 0x00100000 0x0 0xc7018>;
824 #clock-cells = <1>; 556 #clock-cells = <1>;
825 #reset-cells = <1>; 557 #reset-cells = <1>;
826 #power-domain-cells = 558 #power-domain-cells = <1>;
827 clocks = <&rpmhcc RPMH 559 clocks = <&rpmhcc RPMH_CXO_CLK>,
828 <&sleep_clk>, 560 <&sleep_clk>,
829 <0>, 561 <0>,
830 <0>, 562 <0>,
831 <0>, 563 <0>,
832 <&usb_0_qmpph 564 <&usb_0_qmpphy>,
833 <&usb_1_qmpph 565 <&usb_1_qmpphy>,
834 <0>, 566 <0>,
835 <0>, 567 <0>,
836 <0>, 568 <0>,
837 <&pcie0_phy>, 569 <&pcie0_phy>,
838 <&pcie1_phy>, 570 <&pcie1_phy>,
839 <0>, 571 <0>,
840 <0>, 572 <0>,
841 <0>; 573 <0>;
842 power-domains = <&rpmh 574 power-domains = <&rpmhpd SA8775P_CX>;
843 }; 575 };
844 576
845 ipcc: mailbox@408000 { 577 ipcc: mailbox@408000 {
846 compatible = "qcom,sa8 578 compatible = "qcom,sa8775p-ipcc", "qcom,ipcc";
847 reg = <0x0 0x00408000 579 reg = <0x0 0x00408000 0x0 0x1000>;
848 interrupts = <GIC_SPI 580 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
849 interrupt-controller; 581 interrupt-controller;
850 #interrupt-cells = <3> 582 #interrupt-cells = <3>;
851 #mbox-cells = <2>; 583 #mbox-cells = <2>;
852 }; 584 };
853 585
854 qupv3_id_2: geniqup@8c0000 { 586 qupv3_id_2: geniqup@8c0000 {
855 compatible = "qcom,gen 587 compatible = "qcom,geni-se-qup";
856 reg = <0x0 0x008c0000 588 reg = <0x0 0x008c0000 0x0 0x6000>;
857 ranges; 589 ranges;
858 clocks = <&gcc GCC_QUP 590 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
859 <&gcc GCC_QUP 591 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
860 clock-names = "m-ahb", 592 clock-names = "m-ahb", "s-ahb";
861 iommus = <&apps_smmu 0 593 iommus = <&apps_smmu 0x5a3 0x0>;
862 #address-cells = <2>; 594 #address-cells = <2>;
863 #size-cells = <2>; 595 #size-cells = <2>;
864 status = "disabled"; 596 status = "disabled";
865 597
866 i2c14: i2c@880000 { 598 i2c14: i2c@880000 {
867 compatible = " 599 compatible = "qcom,geni-i2c";
868 reg = <0x0 0x8 600 reg = <0x0 0x880000 0x0 0x4000>;
869 #address-cells 601 #address-cells = <1>;
870 #size-cells = 602 #size-cells = <0>;
871 interrupts = < 603 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
872 clocks = <&gcc 604 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
873 clock-names = 605 clock-names = "se";
874 interconnects 606 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
875 607 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
876 608 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
877 609 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
878 610 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
879 611 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
880 interconnect-n 612 interconnect-names = "qup-core",
881 613 "qup-config",
882 614 "qup-memory";
883 power-domains 615 power-domains = <&rpmhpd SA8775P_CX>;
884 status = "disa 616 status = "disabled";
885 }; 617 };
886 618
887 spi14: spi@880000 { 619 spi14: spi@880000 {
888 compatible = " 620 compatible = "qcom,geni-spi";
889 reg = <0x0 0x8 621 reg = <0x0 0x880000 0x0 0x4000>;
890 #address-cells 622 #address-cells = <1>;
891 #size-cells = 623 #size-cells = <0>;
892 interrupts = < 624 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
893 clocks = <&gcc 625 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
894 clock-names = 626 clock-names = "se";
895 interconnects 627 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
896 628 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
897 629 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
898 630 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
899 631 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
900 632 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
901 interconnect-n 633 interconnect-names = "qup-core",
902 634 "qup-config",
903 635 "qup-memory";
904 power-domains 636 power-domains = <&rpmhpd SA8775P_CX>;
905 status = "disa 637 status = "disabled";
906 }; 638 };
907 639
908 i2c15: i2c@884000 { 640 i2c15: i2c@884000 {
909 compatible = " 641 compatible = "qcom,geni-i2c";
910 reg = <0x0 0x8 642 reg = <0x0 0x884000 0x0 0x4000>;
911 #address-cells 643 #address-cells = <1>;
912 #size-cells = 644 #size-cells = <0>;
913 interrupts = < 645 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
914 clocks = <&gcc 646 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
915 clock-names = 647 clock-names = "se";
916 interconnects 648 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
917 649 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
918 650 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
919 651 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
920 652 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
921 653 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
922 interconnect-n 654 interconnect-names = "qup-core",
923 655 "qup-config",
924 656 "qup-memory";
925 power-domains 657 power-domains = <&rpmhpd SA8775P_CX>;
926 status = "disa 658 status = "disabled";
927 }; 659 };
928 660
929 spi15: spi@884000 { 661 spi15: spi@884000 {
930 compatible = " 662 compatible = "qcom,geni-spi";
931 reg = <0x0 0x8 663 reg = <0x0 0x884000 0x0 0x4000>;
932 #address-cells 664 #address-cells = <1>;
933 #size-cells = 665 #size-cells = <0>;
934 interrupts = < 666 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
935 clocks = <&gcc 667 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
936 clock-names = 668 clock-names = "se";
937 interconnects 669 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
938 670 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
939 671 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
940 672 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
941 673 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
942 674 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
943 interconnect-n 675 interconnect-names = "qup-core",
944 676 "qup-config",
945 677 "qup-memory";
946 power-domains 678 power-domains = <&rpmhpd SA8775P_CX>;
947 status = "disa 679 status = "disabled";
948 }; 680 };
949 681
950 i2c16: i2c@888000 { 682 i2c16: i2c@888000 {
951 compatible = " 683 compatible = "qcom,geni-i2c";
952 reg = <0x0 0x8 684 reg = <0x0 0x888000 0x0 0x4000>;
953 #address-cells 685 #address-cells = <1>;
954 #size-cells = 686 #size-cells = <0>;
955 interrupts = < 687 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
956 clocks = <&gcc 688 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
957 clock-names = 689 clock-names = "se";
958 interconnects 690 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
959 691 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
960 692 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
961 693 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
962 694 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
963 695 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
964 interconnect-n 696 interconnect-names = "qup-core",
965 697 "qup-config",
966 698 "qup-memory";
967 power-domains 699 power-domains = <&rpmhpd SA8775P_CX>;
968 status = "disa 700 status = "disabled";
969 }; 701 };
970 702
971 spi16: spi@888000 { 703 spi16: spi@888000 {
972 compatible = " 704 compatible = "qcom,geni-spi";
973 reg = <0x0 0x0 705 reg = <0x0 0x00888000 0x0 0x4000>;
974 interrupts = < 706 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
975 clocks = <&gcc 707 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
976 clock-names = 708 clock-names = "se";
977 interconnects 709 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
978 710 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
979 711 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
980 712 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
981 713 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
982 714 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
983 interconnect-n 715 interconnect-names = "qup-core",
984 716 "qup-config",
985 717 "qup-memory";
986 power-domains 718 power-domains = <&rpmhpd SA8775P_CX>;
987 #address-cells 719 #address-cells = <1>;
988 #size-cells = 720 #size-cells = <0>;
989 status = "disa 721 status = "disabled";
990 }; 722 };
991 723
992 i2c17: i2c@88c000 { 724 i2c17: i2c@88c000 {
993 compatible = " 725 compatible = "qcom,geni-i2c";
994 reg = <0x0 0x8 726 reg = <0x0 0x88c000 0x0 0x4000>;
995 #address-cells 727 #address-cells = <1>;
996 #size-cells = 728 #size-cells = <0>;
997 interrupts = < 729 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
998 clocks = <&gcc 730 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
999 clock-names = 731 clock-names = "se";
1000 interconnects 732 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1001 733 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1002 734 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1003 735 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1004 736 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1005 737 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1006 interconnect- 738 interconnect-names = "qup-core",
1007 739 "qup-config",
1008 740 "qup-memory";
1009 power-domains 741 power-domains = <&rpmhpd SA8775P_CX>;
1010 status = "dis 742 status = "disabled";
1011 }; 743 };
1012 744
1013 spi17: spi@88c000 { 745 spi17: spi@88c000 {
1014 compatible = 746 compatible = "qcom,geni-spi";
1015 reg = <0x0 0x 747 reg = <0x0 0x88c000 0x0 0x4000>;
1016 #address-cell 748 #address-cells = <1>;
1017 #size-cells = 749 #size-cells = <0>;
1018 interrupts = 750 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1019 clocks = <&gc 751 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1020 clock-names = 752 clock-names = "se";
1021 interconnects 753 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1022 754 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1023 755 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1024 756 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1025 757 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1026 758 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1027 interconnect- 759 interconnect-names = "qup-core",
1028 760 "qup-config",
1029 761 "qup-memory";
1030 power-domains 762 power-domains = <&rpmhpd SA8775P_CX>;
1031 status = "dis 763 status = "disabled";
1032 }; 764 };
1033 765
1034 uart17: serial@88c000 766 uart17: serial@88c000 {
1035 compatible = 767 compatible = "qcom,geni-uart";
1036 reg = <0x0 0x 768 reg = <0x0 0x0088c000 0x0 0x4000>;
1037 interrupts = 769 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1038 clocks = <&gc 770 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1039 clock-names = 771 clock-names = "se";
1040 interconnects 772 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1041 773 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1042 774 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1043 775 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
1044 interconnect- 776 interconnect-names = "qup-core", "qup-config";
1045 power-domains 777 power-domains = <&rpmhpd SA8775P_CX>;
1046 status = "dis 778 status = "disabled";
1047 }; 779 };
1048 780
1049 i2c18: i2c@890000 { 781 i2c18: i2c@890000 {
1050 compatible = 782 compatible = "qcom,geni-i2c";
1051 reg = <0x0 0x 783 reg = <0x0 0x00890000 0x0 0x4000>;
1052 interrupts = 784 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1053 clocks = <&gc 785 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1054 clock-names = 786 clock-names = "se";
1055 interconnects 787 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1056 788 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1057 789 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1058 790 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1059 791 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1060 792 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1061 interconnect- 793 interconnect-names = "qup-core",
1062 794 "qup-config",
1063 795 "qup-memory";
1064 power-domains 796 power-domains = <&rpmhpd SA8775P_CX>;
1065 #address-cell 797 #address-cells = <1>;
1066 #size-cells = 798 #size-cells = <0>;
1067 status = "dis 799 status = "disabled";
1068 }; 800 };
1069 801
1070 spi18: spi@890000 { 802 spi18: spi@890000 {
1071 compatible = 803 compatible = "qcom,geni-spi";
1072 reg = <0x0 0x 804 reg = <0x0 0x890000 0x0 0x4000>;
1073 #address-cell 805 #address-cells = <1>;
1074 #size-cells = 806 #size-cells = <0>;
1075 interrupts = 807 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1076 clocks = <&gc 808 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1077 clock-names = 809 clock-names = "se";
1078 interconnects 810 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1079 811 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1080 812 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1081 813 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1082 814 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1083 815 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1084 interconnect- 816 interconnect-names = "qup-core",
1085 817 "qup-config",
1086 818 "qup-memory";
1087 power-domains 819 power-domains = <&rpmhpd SA8775P_CX>;
1088 status = "dis 820 status = "disabled";
1089 }; 821 };
1090 822
1091 i2c19: i2c@894000 { 823 i2c19: i2c@894000 {
1092 compatible = 824 compatible = "qcom,geni-i2c";
1093 reg = <0x0 0x 825 reg = <0x0 0x894000 0x0 0x4000>;
1094 #address-cell 826 #address-cells = <1>;
1095 #size-cells = 827 #size-cells = <0>;
1096 interrupts = 828 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1097 clocks = <&gc 829 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1098 clock-names = 830 clock-names = "se";
1099 interconnects 831 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1100 832 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1101 833 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1102 834 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1103 835 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1104 836 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1105 interconnect- 837 interconnect-names = "qup-core",
1106 838 "qup-config",
1107 839 "qup-memory";
1108 power-domains 840 power-domains = <&rpmhpd SA8775P_CX>;
1109 status = "dis 841 status = "disabled";
1110 }; 842 };
1111 843
1112 spi19: spi@894000 { 844 spi19: spi@894000 {
1113 compatible = 845 compatible = "qcom,geni-spi";
1114 reg = <0x0 0x 846 reg = <0x0 0x894000 0x0 0x4000>;
1115 #address-cell 847 #address-cells = <1>;
1116 #size-cells = 848 #size-cells = <0>;
1117 interrupts = 849 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1118 clocks = <&gc 850 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1119 clock-names = 851 clock-names = "se";
1120 interconnects 852 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1121 853 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1122 854 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1123 855 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1124 856 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1125 857 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1126 interconnect- 858 interconnect-names = "qup-core",
1127 859 "qup-config",
1128 860 "qup-memory";
1129 power-domains 861 power-domains = <&rpmhpd SA8775P_CX>;
1130 status = "dis 862 status = "disabled";
1131 }; 863 };
1132 864
1133 i2c20: i2c@898000 { 865 i2c20: i2c@898000 {
1134 compatible = 866 compatible = "qcom,geni-i2c";
1135 reg = <0x0 0x 867 reg = <0x0 0x898000 0x0 0x4000>;
1136 #address-cell 868 #address-cells = <1>;
1137 #size-cells = 869 #size-cells = <0>;
1138 interrupts = 870 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>;
1139 clocks = <&gc 871 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1140 clock-names = 872 clock-names = "se";
1141 interconnects 873 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1142 874 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1143 875 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1144 876 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1145 877 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1146 878 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1147 interconnect- 879 interconnect-names = "qup-core",
1148 880 "qup-config",
1149 881 "qup-memory";
1150 power-domains 882 power-domains = <&rpmhpd SA8775P_CX>;
1151 status = "dis 883 status = "disabled";
1152 }; 884 };
1153 885
1154 spi20: spi@898000 { 886 spi20: spi@898000 {
1155 compatible = 887 compatible = "qcom,geni-spi";
1156 reg = <0x0 0x 888 reg = <0x0 0x898000 0x0 0x4000>;
1157 #address-cell 889 #address-cells = <1>;
1158 #size-cells = 890 #size-cells = <0>;
1159 interrupts = 891 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>;
1160 clocks = <&gc 892 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1161 clock-names = 893 clock-names = "se";
1162 interconnects 894 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1163 895 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1164 896 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1165 897 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1166 898 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1167 899 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1168 interconnect- 900 interconnect-names = "qup-core",
1169 901 "qup-config",
1170 902 "qup-memory";
1171 power-domains 903 power-domains = <&rpmhpd SA8775P_CX>;
1172 status = "dis 904 status = "disabled";
1173 }; 905 };
1174 }; 906 };
1175 907
1176 qupv3_id_0: geniqup@9c0000 { 908 qupv3_id_0: geniqup@9c0000 {
1177 compatible = "qcom,ge 909 compatible = "qcom,geni-se-qup";
1178 reg = <0x0 0x9c0000 0 910 reg = <0x0 0x9c0000 0x0 0x6000>;
1179 #address-cells = <2>; 911 #address-cells = <2>;
1180 #size-cells = <2>; 912 #size-cells = <2>;
1181 ranges; 913 ranges;
1182 clock-names = "m-ahb" 914 clock-names = "m-ahb", "s-ahb";
1183 clocks = <&gcc GCC_QU 915 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1184 <&gcc GCC_QUP 916 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1185 iommus = <&apps_smmu 917 iommus = <&apps_smmu 0x403 0x0>;
1186 status = "disabled"; 918 status = "disabled";
1187 919
1188 i2c0: i2c@980000 { 920 i2c0: i2c@980000 {
1189 compatible = 921 compatible = "qcom,geni-i2c";
1190 reg = <0x0 0x 922 reg = <0x0 0x980000 0x0 0x4000>;
1191 #address-cell 923 #address-cells = <1>;
1192 #size-cells = 924 #size-cells = <0>;
1193 interrupts = 925 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>;
1194 clocks = <&gc 926 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1195 clock-names = 927 clock-names = "se";
1196 interconnects 928 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1197 929 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1198 930 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1199 931 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
1200 932 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
1201 933 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1202 interconnect- 934 interconnect-names = "qup-core",
1203 935 "qup-config",
1204 936 "qup-memory";
1205 power-domains 937 power-domains = <&rpmhpd SA8775P_CX>;
1206 status = "dis 938 status = "disabled";
1207 }; 939 };
1208 940
1209 spi0: spi@980000 { 941 spi0: spi@980000 {
1210 compatible = 942 compatible = "qcom,geni-spi";
1211 reg = <0x0 0x 943 reg = <0x0 0x980000 0x0 0x4000>;
1212 #address-cell 944 #address-cells = <1>;
1213 #size-cells = 945 #size-cells = <0>;
1214 interrupts = 946 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>;
1215 clocks = <&gc 947 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1216 clock-names = 948 clock-names = "se";
1217 interconnects 949 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1218 950 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1219 951 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1220 952 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
1221 953 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
1222 954 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1223 interconnect- 955 interconnect-names = "qup-core",
1224 956 "qup-config",
1225 957 "qup-memory";
1226 power-domains 958 power-domains = <&rpmhpd SA8775P_CX>;
1227 status = "dis 959 status = "disabled";
1228 }; 960 };
1229 961
1230 i2c1: i2c@984000 { 962 i2c1: i2c@984000 {
1231 compatible = 963 compatible = "qcom,geni-i2c";
1232 reg = <0x0 0x 964 reg = <0x0 0x984000 0x0 0x4000>;
1233 #address-cell 965 #address-cells = <1>;
1234 #size-cells = 966 #size-cells = <0>;
1235 interrupts = 967 interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;
1236 clocks = <&gc 968 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1237 clock-names = 969 clock-names = "se";
1238 interconnects 970 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1239 971 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1240 972 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1241 973 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
1242 974 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
1243 975 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1244 interconnect- 976 interconnect-names = "qup-core",
1245 977 "qup-config",
1246 978 "qup-memory";
1247 power-domains 979 power-domains = <&rpmhpd SA8775P_CX>;
1248 status = "dis 980 status = "disabled";
1249 }; 981 };
1250 982
1251 spi1: spi@984000 { 983 spi1: spi@984000 {
1252 compatible = 984 compatible = "qcom,geni-spi";
1253 reg = <0x0 0x 985 reg = <0x0 0x984000 0x0 0x4000>;
1254 #address-cell 986 #address-cells = <1>;
1255 #size-cells = 987 #size-cells = <0>;
1256 interrupts = 988 interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;
1257 clocks = <&gc 989 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1258 clock-names = 990 clock-names = "se";
1259 interconnects 991 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1260 992 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1261 993 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1262 994 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
1263 995 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
1264 996 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1265 interconnect- 997 interconnect-names = "qup-core",
1266 998 "qup-config",
1267 999 "qup-memory";
1268 power-domains 1000 power-domains = <&rpmhpd SA8775P_CX>;
1269 status = "dis 1001 status = "disabled";
1270 }; 1002 };
1271 1003
1272 i2c2: i2c@988000 { 1004 i2c2: i2c@988000 {
1273 compatible = 1005 compatible = "qcom,geni-i2c";
1274 reg = <0x0 0x 1006 reg = <0x0 0x988000 0x0 0x4000>;
1275 #address-cell 1007 #address-cells = <1>;
1276 #size-cells = 1008 #size-cells = <0>;
1277 interrupts = 1009 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>;
1278 clocks = <&gc 1010 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1279 clock-names = 1011 clock-names = "se";
1280 interconnects 1012 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1281 1013 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1282 1014 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1283 1015 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
1284 1016 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
1285 1017 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1286 interconnect- 1018 interconnect-names = "qup-core",
1287 1019 "qup-config",
1288 1020 "qup-memory";
1289 power-domains 1021 power-domains = <&rpmhpd SA8775P_CX>;
1290 status = "dis 1022 status = "disabled";
1291 }; 1023 };
1292 1024
1293 spi2: spi@988000 { 1025 spi2: spi@988000 {
1294 compatible = 1026 compatible = "qcom,geni-spi";
1295 reg = <0x0 0x 1027 reg = <0x0 0x988000 0x0 0x4000>;
1296 #address-cell 1028 #address-cells = <1>;
1297 #size-cells = 1029 #size-cells = <0>;
1298 interrupts = 1030 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>;
1299 clocks = <&gc 1031 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1300 clock-names = 1032 clock-names = "se";
1301 interconnects 1033 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1302 1034 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1303 1035 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1304 1036 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
1305 1037 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
1306 1038 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1307 interconnect- 1039 interconnect-names = "qup-core",
1308 1040 "qup-config",
1309 1041 "qup-memory";
1310 power-domains 1042 power-domains = <&rpmhpd SA8775P_CX>;
1311 status = "dis 1043 status = "disabled";
1312 }; 1044 };
1313 1045
1314 i2c3: i2c@98c000 { 1046 i2c3: i2c@98c000 {
1315 compatible = 1047 compatible = "qcom,geni-i2c";
1316 reg = <0x0 0x 1048 reg = <0x0 0x98c000 0x0 0x4000>;
1317 #address-cell 1049 #address-cells = <1>;
1318 #size-cells = 1050 #size-cells = <0>;
1319 interrupts = 1051 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>;
1320 clocks = <&gc 1052 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1321 clock-names = 1053 clock-names = "se";
1322 interconnects 1054 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1323 1055 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1324 1056 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1325 1057 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
1326 1058 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
1327 1059 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1328 interconnect- 1060 interconnect-names = "qup-core",
1329 1061 "qup-config",
1330 1062 "qup-memory";
1331 power-domains 1063 power-domains = <&rpmhpd SA8775P_CX>;
1332 status = "dis 1064 status = "disabled";
1333 }; 1065 };
1334 1066
1335 spi3: spi@98c000 { 1067 spi3: spi@98c000 {
1336 compatible = 1068 compatible = "qcom,geni-spi";
1337 reg = <0x0 0x 1069 reg = <0x0 0x98c000 0x0 0x4000>;
1338 #address-cell 1070 #address-cells = <1>;
1339 #size-cells = 1071 #size-cells = <0>;
1340 interrupts = 1072 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>;
1341 clocks = <&gc 1073 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1342 clock-names = 1074 clock-names = "se";
1343 interconnects 1075 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1344 1076 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1345 1077 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1346 1078 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
1347 1079 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
1348 1080 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1349 interconnect- 1081 interconnect-names = "qup-core",
1350 1082 "qup-config",
1351 1083 "qup-memory";
1352 power-domains 1084 power-domains = <&rpmhpd SA8775P_CX>;
1353 status = "dis 1085 status = "disabled";
1354 }; 1086 };
1355 1087
1356 i2c4: i2c@990000 { 1088 i2c4: i2c@990000 {
1357 compatible = 1089 compatible = "qcom,geni-i2c";
1358 reg = <0x0 0x 1090 reg = <0x0 0x990000 0x0 0x4000>;
1359 #address-cell 1091 #address-cells = <1>;
1360 #size-cells = 1092 #size-cells = <0>;
1361 interrupts = 1093 interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>;
1362 clocks = <&gc 1094 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1363 clock-names = 1095 clock-names = "se";
1364 interconnects 1096 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1365 1097 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1366 1098 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1367 1099 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
1368 1100 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
1369 1101 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1370 interconnect- 1102 interconnect-names = "qup-core",
1371 1103 "qup-config",
1372 1104 "qup-memory";
1373 power-domains 1105 power-domains = <&rpmhpd SA8775P_CX>;
1374 status = "dis 1106 status = "disabled";
1375 }; 1107 };
1376 1108
1377 spi4: spi@990000 { 1109 spi4: spi@990000 {
1378 compatible = 1110 compatible = "qcom,geni-spi";
1379 reg = <0x0 0x 1111 reg = <0x0 0x990000 0x0 0x4000>;
1380 #address-cell 1112 #address-cells = <1>;
1381 #size-cells = 1113 #size-cells = <0>;
1382 interrupts = 1114 interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>;
1383 clocks = <&gc 1115 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1384 clock-names = 1116 clock-names = "se";
1385 interconnects 1117 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1386 1118 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1387 1119 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1388 1120 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
1389 1121 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
1390 1122 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1391 interconnect- 1123 interconnect-names = "qup-core",
1392 1124 "qup-config",
1393 1125 "qup-memory";
1394 power-domains 1126 power-domains = <&rpmhpd SA8775P_CX>;
1395 status = "dis 1127 status = "disabled";
1396 }; 1128 };
1397 1129
1398 i2c5: i2c@994000 { 1130 i2c5: i2c@994000 {
1399 compatible = 1131 compatible = "qcom,geni-i2c";
1400 reg = <0x0 0x 1132 reg = <0x0 0x994000 0x0 0x4000>;
1401 #address-cell 1133 #address-cells = <1>;
1402 #size-cells = 1134 #size-cells = <0>;
1403 interrupts = 1135 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>;
1404 clocks = <&gc 1136 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1405 clock-names = 1137 clock-names = "se";
1406 interconnects 1138 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1407 1139 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1408 1140 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1409 1141 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
1410 1142 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
1411 1143 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1412 interconnect- 1144 interconnect-names = "qup-core",
1413 1145 "qup-config",
1414 1146 "qup-memory";
1415 power-domains 1147 power-domains = <&rpmhpd SA8775P_CX>;
1416 status = "dis 1148 status = "disabled";
1417 }; 1149 };
1418 1150
1419 spi5: spi@994000 { 1151 spi5: spi@994000 {
1420 compatible = 1152 compatible = "qcom,geni-spi";
1421 reg = <0x0 0x 1153 reg = <0x0 0x994000 0x0 0x4000>;
1422 #address-cell 1154 #address-cells = <1>;
1423 #size-cells = 1155 #size-cells = <0>;
1424 interrupts = 1156 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>;
1425 clocks = <&gc 1157 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1426 clock-names = 1158 clock-names = "se";
1427 interconnects 1159 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1428 1160 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1429 1161 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1430 1162 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
1431 1163 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
1432 1164 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1433 interconnect- 1165 interconnect-names = "qup-core",
1434 1166 "qup-config",
1435 1167 "qup-memory";
1436 power-domains 1168 power-domains = <&rpmhpd SA8775P_CX>;
1437 status = "dis 1169 status = "disabled";
1438 }; 1170 };
1439 1171
1440 uart5: serial@994000 1172 uart5: serial@994000 {
1441 compatible = 1173 compatible = "qcom,geni-uart";
1442 reg = <0x0 0x 1174 reg = <0x0 0x994000 0x0 0x4000>;
1443 interrupts = 1175 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>;
1444 clocks = <&gc 1176 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1445 clock-names = 1177 clock-names = "se";
1446 interconnects 1178 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1447 1179 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1448 1180 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1449 1181 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
1450 interconnect- 1182 interconnect-names = "qup-core", "qup-config";
1451 power-domains 1183 power-domains = <&rpmhpd SA8775P_CX>;
1452 status = "dis 1184 status = "disabled";
1453 }; 1185 };
1454 }; 1186 };
1455 1187
1456 qupv3_id_1: geniqup@ac0000 { 1188 qupv3_id_1: geniqup@ac0000 {
1457 compatible = "qcom,ge 1189 compatible = "qcom,geni-se-qup";
1458 reg = <0x0 0x00ac0000 1190 reg = <0x0 0x00ac0000 0x0 0x6000>;
1459 #address-cells = <2>; 1191 #address-cells = <2>;
1460 #size-cells = <2>; 1192 #size-cells = <2>;
1461 ranges; 1193 ranges;
1462 clock-names = "m-ahb" 1194 clock-names = "m-ahb", "s-ahb";
1463 clocks = <&gcc GCC_QU 1195 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1464 <&gcc GCC_QU 1196 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1465 iommus = <&apps_smmu 1197 iommus = <&apps_smmu 0x443 0x0>;
1466 status = "disabled"; 1198 status = "disabled";
1467 1199
1468 i2c7: i2c@a80000 { 1200 i2c7: i2c@a80000 {
1469 compatible = 1201 compatible = "qcom,geni-i2c";
1470 reg = <0x0 0x 1202 reg = <0x0 0xa80000 0x0 0x4000>;
1471 #address-cell 1203 #address-cells = <1>;
1472 #size-cells = 1204 #size-cells = <0>;
1473 interrupts = 1205 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1474 clocks = <&gc 1206 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1475 clock-names = 1207 clock-names = "se";
1476 interconnects 1208 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1477 1209 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1478 1210 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1479 1211 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1480 1212 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1481 1213 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1482 interconnect- 1214 interconnect-names = "qup-core",
1483 1215 "qup-config",
1484 1216 "qup-memory";
1485 power-domains 1217 power-domains = <&rpmhpd SA8775P_CX>;
1486 status = "dis 1218 status = "disabled";
1487 }; 1219 };
1488 1220
1489 spi7: spi@a80000 { 1221 spi7: spi@a80000 {
1490 compatible = 1222 compatible = "qcom,geni-spi";
1491 reg = <0x0 0x 1223 reg = <0x0 0xa80000 0x0 0x4000>;
1492 #address-cell 1224 #address-cells = <1>;
1493 #size-cells = 1225 #size-cells = <0>;
1494 interrupts = 1226 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1495 clocks = <&gc 1227 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1496 clock-names = 1228 clock-names = "se";
1497 interconnects 1229 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1498 1230 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1499 1231 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1500 1232 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1501 1233 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1502 1234 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1503 interconnect- 1235 interconnect-names = "qup-core",
1504 1236 "qup-config",
1505 1237 "qup-memory";
1506 power-domains 1238 power-domains = <&rpmhpd SA8775P_CX>;
1507 status = "dis 1239 status = "disabled";
1508 }; 1240 };
1509 1241
1510 i2c8: i2c@a84000 { 1242 i2c8: i2c@a84000 {
1511 compatible = 1243 compatible = "qcom,geni-i2c";
1512 reg = <0x0 0x 1244 reg = <0x0 0xa84000 0x0 0x4000>;
1513 #address-cell 1245 #address-cells = <1>;
1514 #size-cells = 1246 #size-cells = <0>;
1515 interrupts = 1247 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1516 clocks = <&gc 1248 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1517 clock-names = 1249 clock-names = "se";
1518 interconnects 1250 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1519 1251 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1520 1252 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1521 1253 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1522 1254 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1523 1255 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1524 interconnect- 1256 interconnect-names = "qup-core",
1525 1257 "qup-config",
1526 1258 "qup-memory";
1527 power-domains 1259 power-domains = <&rpmhpd SA8775P_CX>;
1528 status = "dis 1260 status = "disabled";
1529 }; 1261 };
1530 1262
1531 spi8: spi@a84000 { 1263 spi8: spi@a84000 {
1532 compatible = 1264 compatible = "qcom,geni-spi";
1533 reg = <0x0 0x 1265 reg = <0x0 0xa84000 0x0 0x4000>;
1534 #address-cell 1266 #address-cells = <1>;
1535 #size-cells = 1267 #size-cells = <0>;
1536 interrupts = 1268 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1537 clocks = <&gc 1269 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1538 clock-names = 1270 clock-names = "se";
1539 interconnects 1271 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1540 1272 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1541 1273 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1542 1274 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1543 1275 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1544 1276 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1545 interconnect- 1277 interconnect-names = "qup-core",
1546 1278 "qup-config",
1547 1279 "qup-memory";
1548 power-domains 1280 power-domains = <&rpmhpd SA8775P_CX>;
1549 status = "dis 1281 status = "disabled";
1550 }; 1282 };
1551 1283
1552 i2c9: i2c@a88000 { 1284 i2c9: i2c@a88000 {
1553 compatible = 1285 compatible = "qcom,geni-i2c";
1554 reg = <0x0 0x 1286 reg = <0x0 0xa88000 0x0 0x4000>;
1555 #address-cell 1287 #address-cells = <1>;
1556 #size-cells = 1288 #size-cells = <0>;
1557 interrupts = 1289 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1558 clocks = <&gc 1290 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1559 clock-names = 1291 clock-names = "se";
1560 interconnects 1292 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1561 1293 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1562 1294 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1563 1295 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1564 1296 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1565 1297 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1566 interconnect- 1298 interconnect-names = "qup-core",
1567 1299 "qup-config",
1568 1300 "qup-memory";
1569 power-domains 1301 power-domains = <&rpmhpd SA8775P_CX>;
1570 status = "dis 1302 status = "disabled";
1571 }; 1303 };
1572 1304
1573 spi9: spi@a88000 { 1305 spi9: spi@a88000 {
1574 compatible = 1306 compatible = "qcom,geni-spi";
1575 reg = <0x0 0x 1307 reg = <0x0 0xa88000 0x0 0x4000>;
1576 #address-cell 1308 #address-cells = <1>;
1577 #size-cells = 1309 #size-cells = <0>;
1578 interrupts = 1310 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1579 clocks = <&gc 1311 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1580 clock-names = 1312 clock-names = "se";
1581 interconnects 1313 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1582 1314 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1583 1315 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1584 1316 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1585 1317 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1586 1318 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1587 interconnect- 1319 interconnect-names = "qup-core",
1588 1320 "qup-config",
1589 1321 "qup-memory";
1590 power-domains 1322 power-domains = <&rpmhpd SA8775P_CX>;
1591 status = "dis 1323 status = "disabled";
1592 }; 1324 };
1593 1325
1594 uart9: serial@a88000 1326 uart9: serial@a88000 {
1595 compatible = 1327 compatible = "qcom,geni-uart";
1596 reg = <0x0 0x 1328 reg = <0x0 0xa88000 0x0 0x4000>;
1597 interrupts = 1329 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1598 clocks = <&gc 1330 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1599 clock-names = 1331 clock-names = "se";
1600 interconnects 1332 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1601 1333 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1602 1334 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1603 1335 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
1604 interconnect- 1336 interconnect-names = "qup-core", "qup-config";
1605 power-domains 1337 power-domains = <&rpmhpd SA8775P_CX>;
1606 status = "dis 1338 status = "disabled";
1607 }; 1339 };
1608 1340
1609 i2c10: i2c@a8c000 { 1341 i2c10: i2c@a8c000 {
1610 compatible = 1342 compatible = "qcom,geni-i2c";
1611 reg = <0x0 0x 1343 reg = <0x0 0xa8c000 0x0 0x4000>;
1612 #address-cell 1344 #address-cells = <1>;
1613 #size-cells = 1345 #size-cells = <0>;
1614 interrupts = 1346 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1615 clocks = <&gc 1347 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1616 clock-names = 1348 clock-names = "se";
1617 interconnects 1349 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1618 1350 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1619 1351 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1620 1352 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1621 1353 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1622 1354 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1623 interconnect- 1355 interconnect-names = "qup-core",
1624 1356 "qup-config",
1625 1357 "qup-memory";
1626 power-domains 1358 power-domains = <&rpmhpd SA8775P_CX>;
1627 status = "dis 1359 status = "disabled";
1628 }; 1360 };
1629 1361
1630 spi10: spi@a8c000 { 1362 spi10: spi@a8c000 {
1631 compatible = 1363 compatible = "qcom,geni-spi";
1632 reg = <0x0 0x 1364 reg = <0x0 0xa8c000 0x0 0x4000>;
1633 #address-cell 1365 #address-cells = <1>;
1634 #size-cells = 1366 #size-cells = <0>;
1635 interrupts = 1367 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1636 clocks = <&gc 1368 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1637 clock-names = 1369 clock-names = "se";
1638 interconnects 1370 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1639 1371 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1640 1372 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1641 1373 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1642 1374 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1643 1375 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1644 interconnect- 1376 interconnect-names = "qup-core",
1645 1377 "qup-config",
1646 1378 "qup-memory";
1647 power-domains 1379 power-domains = <&rpmhpd SA8775P_CX>;
1648 status = "dis 1380 status = "disabled";
1649 }; 1381 };
1650 1382
1651 uart10: serial@a8c000 1383 uart10: serial@a8c000 {
1652 compatible = 1384 compatible = "qcom,geni-uart";
1653 reg = <0x0 0x 1385 reg = <0x0 0x00a8c000 0x0 0x4000>;
1654 interrupts = 1386 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1655 clock-names = 1387 clock-names = "se";
1656 clocks = <&gc 1388 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1657 interconnect- 1389 interconnect-names = "qup-core", "qup-config";
1658 interconnects 1390 interconnects = <&clk_virt MASTER_QUP_CORE_1 0
1659 1391 &clk_virt SLAVE_QUP_CORE_1 0>,
1660 1392 <&gem_noc MASTER_APPSS_PROC 0
1661 1393 &config_noc SLAVE_QUP_1 0>;
1662 power-domains 1394 power-domains = <&rpmhpd SA8775P_CX>;
1663 operating-poi 1395 operating-points-v2 = <&qup_opp_table_100mhz>;
1664 status = "dis 1396 status = "disabled";
1665 }; 1397 };
1666 1398
1667 i2c11: i2c@a90000 { 1399 i2c11: i2c@a90000 {
1668 compatible = 1400 compatible = "qcom,geni-i2c";
1669 reg = <0x0 0x 1401 reg = <0x0 0xa90000 0x0 0x4000>;
1670 #address-cell 1402 #address-cells = <1>;
1671 #size-cells = 1403 #size-cells = <0>;
1672 interrupts = 1404 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1673 clocks = <&gc 1405 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1674 clock-names = 1406 clock-names = "se";
1675 interconnects 1407 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1676 1408 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1677 1409 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1678 1410 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1679 1411 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1680 1412 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1681 interconnect- 1413 interconnect-names = "qup-core",
1682 1414 "qup-config",
1683 1415 "qup-memory";
1684 power-domains 1416 power-domains = <&rpmhpd SA8775P_CX>;
1685 status = "dis 1417 status = "disabled";
1686 }; 1418 };
1687 1419
1688 spi11: spi@a90000 { 1420 spi11: spi@a90000 {
1689 compatible = 1421 compatible = "qcom,geni-spi";
1690 reg = <0x0 0x 1422 reg = <0x0 0xa90000 0x0 0x4000>;
1691 #address-cell 1423 #address-cells = <1>;
1692 #size-cells = 1424 #size-cells = <0>;
1693 interrupts = 1425 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1694 clocks = <&gc 1426 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1695 clock-names = 1427 clock-names = "se";
1696 interconnects 1428 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1697 1429 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1698 1430 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1699 1431 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1700 1432 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1701 1433 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1702 interconnect- 1434 interconnect-names = "qup-core",
1703 1435 "qup-config",
1704 1436 "qup-memory";
1705 power-domains 1437 power-domains = <&rpmhpd SA8775P_CX>;
1706 status = "dis 1438 status = "disabled";
1707 }; 1439 };
1708 1440
1709 i2c12: i2c@a94000 { 1441 i2c12: i2c@a94000 {
1710 compatible = 1442 compatible = "qcom,geni-i2c";
1711 reg = <0x0 0x 1443 reg = <0x0 0xa94000 0x0 0x4000>;
1712 #address-cell 1444 #address-cells = <1>;
1713 #size-cells = 1445 #size-cells = <0>;
1714 interrupts = 1446 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1715 clocks = <&gc 1447 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1716 clock-names = 1448 clock-names = "se";
1717 interconnects 1449 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1718 1450 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1719 1451 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1720 1452 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1721 1453 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1722 1454 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1723 interconnect- 1455 interconnect-names = "qup-core",
1724 1456 "qup-config",
1725 1457 "qup-memory";
1726 power-domains 1458 power-domains = <&rpmhpd SA8775P_CX>;
1727 status = "dis 1459 status = "disabled";
1728 }; 1460 };
1729 1461
1730 spi12: spi@a94000 { 1462 spi12: spi@a94000 {
1731 compatible = 1463 compatible = "qcom,geni-spi";
1732 reg = <0x0 0x 1464 reg = <0x0 0xa94000 0x0 0x4000>;
1733 #address-cell 1465 #address-cells = <1>;
1734 #size-cells = 1466 #size-cells = <0>;
1735 interrupts = 1467 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1736 clocks = <&gc 1468 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1737 clock-names = 1469 clock-names = "se";
1738 interconnects 1470 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1739 1471 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1740 1472 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1741 1473 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1742 1474 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1743 1475 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1744 interconnect- 1476 interconnect-names = "qup-core",
1745 1477 "qup-config",
1746 1478 "qup-memory";
1747 power-domains 1479 power-domains = <&rpmhpd SA8775P_CX>;
1748 status = "dis 1480 status = "disabled";
1749 }; 1481 };
1750 1482
1751 uart12: serial@a94000 1483 uart12: serial@a94000 {
1752 compatible = 1484 compatible = "qcom,geni-uart";
1753 reg = <0x0 0x 1485 reg = <0x0 0x00a94000 0x0 0x4000>;
1754 interrupts = 1486 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1755 clocks = <&gc 1487 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1756 clock-names = 1488 clock-names = "se";
1757 interconnects 1489 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1758 1490 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1759 1491 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1760 1492 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
1761 interconnect- 1493 interconnect-names = "qup-core", "qup-config";
1762 power-domains 1494 power-domains = <&rpmhpd SA8775P_CX>;
1763 status = "dis 1495 status = "disabled";
1764 }; 1496 };
1765 1497
1766 i2c13: i2c@a98000 { 1498 i2c13: i2c@a98000 {
1767 compatible = 1499 compatible = "qcom,geni-i2c";
1768 reg = <0x0 0x 1500 reg = <0x0 0xa98000 0x0 0x4000>;
1769 #address-cell 1501 #address-cells = <1>;
1770 #size-cells = 1502 #size-cells = <0>;
1771 interrupts = 1503 interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
1772 clocks = <&gc 1504 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1773 clock-names = 1505 clock-names = "se";
1774 interconnects 1506 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1775 1507 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1776 1508 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1777 1509 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1778 1510 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1779 1511 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1780 interconnect- 1512 interconnect-names = "qup-core",
1781 1513 "qup-config",
1782 1514 "qup-memory";
1783 power-domains 1515 power-domains = <&rpmhpd SA8775P_CX>;
1784 status = "dis 1516 status = "disabled";
1785 }; 1517 };
1786 }; 1518 };
1787 1519
1788 qupv3_id_3: geniqup@bc0000 { 1520 qupv3_id_3: geniqup@bc0000 {
1789 compatible = "qcom,ge 1521 compatible = "qcom,geni-se-qup";
1790 reg = <0x0 0xbc0000 0 1522 reg = <0x0 0xbc0000 0x0 0x6000>;
1791 #address-cells = <2>; 1523 #address-cells = <2>;
1792 #size-cells = <2>; 1524 #size-cells = <2>;
1793 ranges; 1525 ranges;
1794 clock-names = "m-ahb" 1526 clock-names = "m-ahb", "s-ahb";
1795 clocks = <&gcc GCC_QU 1527 clocks = <&gcc GCC_QUPV3_WRAP_3_M_AHB_CLK>,
1796 <&gcc GCC_QUP 1528 <&gcc GCC_QUPV3_WRAP_3_S_AHB_CLK>;
1797 iommus = <&apps_smmu 1529 iommus = <&apps_smmu 0x43 0x0>;
1798 status = "disabled"; 1530 status = "disabled";
1799 1531
1800 i2c21: i2c@b80000 { 1532 i2c21: i2c@b80000 {
1801 compatible = 1533 compatible = "qcom,geni-i2c";
1802 reg = <0x0 0x 1534 reg = <0x0 0xb80000 0x0 0x4000>;
1803 #address-cell 1535 #address-cells = <1>;
1804 #size-cells = 1536 #size-cells = <0>;
1805 interrupts = 1537 interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>;
1806 clocks = <&gc 1538 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>;
1807 clock-names = 1539 clock-names = "se";
1808 interconnects 1540 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS
1809 1541 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>,
1810 <& 1542 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1811 1543 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>,
1812 <& 1544 <&aggre1_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS
1813 1545 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1814 interconnect- 1546 interconnect-names = "qup-core",
1815 1547 "qup-config",
1816 1548 "qup-memory";
1817 power-domains 1549 power-domains = <&rpmhpd SA8775P_CX>;
1818 status = "dis 1550 status = "disabled";
1819 }; 1551 };
1820 1552
1821 spi21: spi@b80000 { 1553 spi21: spi@b80000 {
1822 compatible = 1554 compatible = "qcom,geni-spi";
1823 reg = <0x0 0x 1555 reg = <0x0 0xb80000 0x0 0x4000>;
1824 #address-cell 1556 #address-cells = <1>;
1825 #size-cells = 1557 #size-cells = <0>;
1826 interrupts = 1558 interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>;
1827 clocks = <&gc 1559 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>;
1828 clock-names = 1560 clock-names = "se";
1829 interconnects 1561 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS
1830 1562 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>,
1831 <& 1563 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1832 1564 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>,
1833 <& 1565 <&aggre1_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS
1834 1566 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1835 interconnect- 1567 interconnect-names = "qup-core",
1836 1568 "qup-config",
1837 1569 "qup-memory";
1838 power-domains 1570 power-domains = <&rpmhpd SA8775P_CX>;
1839 status = "dis 1571 status = "disabled";
1840 }; 1572 };
1841 }; 1573 };
1842 1574
1843 rng: rng@10d2000 { 1575 rng: rng@10d2000 {
1844 compatible = "qcom,sa 1576 compatible = "qcom,sa8775p-trng", "qcom,trng";
1845 reg = <0 0x010d2000 0 1577 reg = <0 0x010d2000 0 0x1000>;
1846 }; 1578 };
1847 1579
1848 ufs_mem_hc: ufs@1d84000 { 1580 ufs_mem_hc: ufs@1d84000 {
1849 compatible = "qcom,sa 1581 compatible = "qcom,sa8775p-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
1850 reg = <0x0 0x01d84000 1582 reg = <0x0 0x01d84000 0x0 0x3000>;
1851 interrupts = <GIC_SPI 1583 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
1852 phys = <&ufs_mem_phy> 1584 phys = <&ufs_mem_phy>;
1853 phy-names = "ufsphy"; 1585 phy-names = "ufsphy";
1854 lanes-per-direction = 1586 lanes-per-direction = <2>;
1855 #reset-cells = <1>; 1587 #reset-cells = <1>;
1856 resets = <&gcc GCC_UF 1588 resets = <&gcc GCC_UFS_PHY_BCR>;
1857 reset-names = "rst"; 1589 reset-names = "rst";
1858 power-domains = <&gcc 1590 power-domains = <&gcc UFS_PHY_GDSC>;
1859 required-opps = <&rpm 1591 required-opps = <&rpmhpd_opp_nom>;
1860 iommus = <&apps_smmu 1592 iommus = <&apps_smmu 0x100 0x0>;
1861 dma-coherent; 1593 dma-coherent;
1862 clocks = <&gcc GCC_UF 1594 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
1863 <&gcc GCC_AG 1595 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
1864 <&gcc GCC_UF 1596 <&gcc GCC_UFS_PHY_AHB_CLK>,
1865 <&gcc GCC_UF 1597 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
1866 <&rpmhcc RPM 1598 <&rpmhcc RPMH_CXO_CLK>,
1867 <&gcc GCC_UF 1599 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
1868 <&gcc GCC_UF 1600 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
1869 <&gcc GCC_UF 1601 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
1870 clock-names = "core_c 1602 clock-names = "core_clk",
1871 "bus_ag 1603 "bus_aggr_clk",
1872 "iface_ 1604 "iface_clk",
1873 "core_c 1605 "core_clk_unipro",
1874 "ref_cl 1606 "ref_clk",
1875 "tx_lan 1607 "tx_lane0_sync_clk",
1876 "rx_lan 1608 "rx_lane0_sync_clk",
1877 "rx_lan 1609 "rx_lane1_sync_clk";
1878 freq-table-hz = <7500 1610 freq-table-hz = <75000000 300000000>,
1879 <0 0> 1611 <0 0>,
1880 <0 0> 1612 <0 0>,
1881 <7500 1613 <75000000 300000000>,
1882 <0 0> 1614 <0 0>,
1883 <0 0> 1615 <0 0>,
1884 <0 0> 1616 <0 0>,
1885 <0 0> 1617 <0 0>;
1886 qcom,ice = <&ice>; 1618 qcom,ice = <&ice>;
1887 status = "disabled"; 1619 status = "disabled";
1888 }; 1620 };
1889 1621
1890 ufs_mem_phy: phy@1d87000 { 1622 ufs_mem_phy: phy@1d87000 {
1891 compatible = "qcom,sa 1623 compatible = "qcom,sa8775p-qmp-ufs-phy";
1892 reg = <0x0 0x01d87000 1624 reg = <0x0 0x01d87000 0x0 0xe10>;
1893 /* 1625 /*
1894 * Yes, GCC_EDP_REF_C 1626 * Yes, GCC_EDP_REF_CLKREF_EN is correct in qref. It
1895 * enables the CXO cl 1627 * enables the CXO clock to eDP *and* UFS PHY.
1896 */ 1628 */
1897 clocks = <&rpmhcc RPM 1629 clocks = <&rpmhcc RPMH_CXO_CLK>,
1898 <&gcc GCC_UF 1630 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
1899 <&gcc GCC_ED 1631 <&gcc GCC_EDP_REF_CLKREF_EN>;
1900 clock-names = "ref", 1632 clock-names = "ref", "ref_aux", "qref";
1901 power-domains = <&gcc 1633 power-domains = <&gcc UFS_PHY_GDSC>;
1902 resets = <&ufs_mem_hc 1634 resets = <&ufs_mem_hc 0>;
1903 reset-names = "ufsphy 1635 reset-names = "ufsphy";
1904 #phy-cells = <0>; 1636 #phy-cells = <0>;
1905 status = "disabled"; 1637 status = "disabled";
1906 }; 1638 };
1907 1639
1908 ice: crypto@1d88000 { 1640 ice: crypto@1d88000 {
1909 compatible = "qcom,sa 1641 compatible = "qcom,sa8775p-inline-crypto-engine",
1910 "qcom,in 1642 "qcom,inline-crypto-engine";
1911 reg = <0x0 0x01d88000 1643 reg = <0x0 0x01d88000 0x0 0x8000>;
1912 clocks = <&gcc GCC_UF 1644 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
1913 }; 1645 };
1914 1646
1915 stm: stm@4002000 { <<
1916 compatible = "arm,cor <<
1917 reg = <0x0 0x4002000 <<
1918 <0x0 0x1628 <<
1919 reg-names = "stm-base <<
1920 <<
1921 clocks = <&aoss_qmp>; <<
1922 clock-names = "apb_pc <<
1923 <<
1924 out-ports { <<
1925 port { <<
1926 stm_o <<
1927 <<
1928 <<
1929 }; <<
1930 }; <<
1931 }; <<
1932 }; <<
1933 <<
1934 tpdm@4003000 { <<
1935 compatible = "qcom,co <<
1936 reg = <0x0 0x4003000 <<
1937 <<
1938 clocks = <&aoss_qmp>; <<
1939 clock-names = "apb_pc <<
1940 <<
1941 qcom,cmb-element-bits <<
1942 qcom,cmb-msrs-num = < <<
1943 <<
1944 out-ports { <<
1945 port { <<
1946 qdss_ <<
1947 <<
1948 <<
1949 }; <<
1950 }; <<
1951 }; <<
1952 }; <<
1953 <<
1954 tpda@4004000 { <<
1955 compatible = "qcom,co <<
1956 reg = <0x0 0x4004000 <<
1957 <<
1958 clocks = <&aoss_qmp>; <<
1959 clock-names = "apb_pc <<
1960 <<
1961 out-ports { <<
1962 port { <<
1963 qdss_ <<
1964 <<
1965 <<
1966 }; <<
1967 }; <<
1968 }; <<
1969 <<
1970 in-ports { <<
1971 #address-cell <<
1972 #size-cells = <<
1973 <<
1974 port@0 { <<
1975 reg = <<
1976 qdss_ <<
1977 <<
1978 <<
1979 }; <<
1980 }; <<
1981 <<
1982 port@1 { <<
1983 reg = <<
1984 qdss_ <<
1985 <<
1986 <<
1987 }; <<
1988 }; <<
1989 }; <<
1990 }; <<
1991 <<
1992 tpdm@400f000 { <<
1993 compatible = "qcom,co <<
1994 reg = <0x0 0x400f000 <<
1995 <<
1996 clocks = <&aoss_qmp>; <<
1997 clock-names = "apb_pc <<
1998 <<
1999 qcom,cmb-element-bits <<
2000 qcom,cmb-msrs-num = < <<
2001 <<
2002 out-ports { <<
2003 port { <<
2004 qdss_ <<
2005 <<
2006 <<
2007 }; <<
2008 }; <<
2009 }; <<
2010 }; <<
2011 <<
2012 funnel@4041000 { <<
2013 compatible = "arm,cor <<
2014 reg = <0x0 0x4041000 <<
2015 <<
2016 clocks = <&aoss_qmp>; <<
2017 clock-names = "apb_pc <<
2018 <<
2019 out-ports { <<
2020 port { <<
2021 funne <<
2022 <<
2023 <<
2024 }; <<
2025 }; <<
2026 }; <<
2027 <<
2028 in-ports { <<
2029 #address-cell <<
2030 #size-cells = <<
2031 <<
2032 port@6 { <<
2033 reg = <<
2034 funne <<
2035 <<
2036 <<
2037 }; <<
2038 }; <<
2039 <<
2040 port@7 { <<
2041 reg = <<
2042 funne <<
2043 <<
2044 <<
2045 }; <<
2046 }; <<
2047 }; <<
2048 }; <<
2049 <<
2050 funnel@4042000 { <<
2051 compatible = "arm,cor <<
2052 reg = <0x0 0x4042000 <<
2053 <<
2054 clocks = <&aoss_qmp>; <<
2055 clock-names = "apb_pc <<
2056 <<
2057 out-ports { <<
2058 port { <<
2059 funne <<
2060 <<
2061 <<
2062 }; <<
2063 }; <<
2064 }; <<
2065 <<
2066 in-ports { <<
2067 #address-cell <<
2068 #size-cells = <<
2069 <<
2070 port@4 { <<
2071 reg = <<
2072 funne <<
2073 <<
2074 <<
2075 }; <<
2076 }; <<
2077 }; <<
2078 }; <<
2079 <<
2080 funnel@4045000 { <<
2081 compatible = "arm,cor <<
2082 reg = <0x0 0x4045000 <<
2083 <<
2084 clocks = <&aoss_qmp>; <<
2085 clock-names = "apb_pc <<
2086 <<
2087 out-ports { <<
2088 port { <<
2089 qdss_ <<
2090 <<
2091 <<
2092 }; <<
2093 }; <<
2094 }; <<
2095 <<
2096 in-ports { <<
2097 #address-cell <<
2098 #size-cells = <<
2099 <<
2100 port@0 { <<
2101 reg = <<
2102 qdss_ <<
2103 <<
2104 <<
2105 }; <<
2106 }; <<
2107 <<
2108 port@1 { <<
2109 reg = <<
2110 qdss_ <<
2111 <<
2112 <<
2113 }; <<
2114 }; <<
2115 }; <<
2116 }; <<
2117 <<
2118 funnel@4b04000 { <<
2119 compatible = "arm,cor <<
2120 reg = <0x0 0x4b04000 <<
2121 <<
2122 clocks = <&aoss_qmp>; <<
2123 clock-names = "apb_pc <<
2124 <<
2125 out-ports { <<
2126 port { <<
2127 aoss_ <<
2128 <<
2129 <<
2130 }; <<
2131 }; <<
2132 }; <<
2133 <<
2134 in-ports { <<
2135 #address-cell <<
2136 #size-cells = <<
2137 <<
2138 port@6 { <<
2139 reg = <<
2140 aoss_ <<
2141 <<
2142 <<
2143 }; <<
2144 }; <<
2145 <<
2146 port@7 { <<
2147 reg = <<
2148 aoss_ <<
2149 <<
2150 <<
2151 }; <<
2152 }; <<
2153 }; <<
2154 }; <<
2155 <<
2156 tmc_etf: tmc@4b05000 { <<
2157 compatible = "arm,cor <<
2158 reg = <0x0 0x4b05000 <<
2159 <<
2160 clocks = <&aoss_qmp>; <<
2161 clock-names = "apb_pc <<
2162 <<
2163 out-ports { <<
2164 port { <<
2165 etf0_ <<
2166 <<
2167 <<
2168 }; <<
2169 }; <<
2170 }; <<
2171 <<
2172 in-ports { <<
2173 port { <<
2174 etf0_ <<
2175 <<
2176 <<
2177 }; <<
2178 }; <<
2179 }; <<
2180 }; <<
2181 <<
2182 replicator@4b06000 { <<
2183 compatible = "arm,cor <<
2184 reg = <0x0 0x4b06000 <<
2185 <<
2186 clocks = <&aoss_qmp>; <<
2187 clock-names = "apb_pc <<
2188 <<
2189 out-ports { <<
2190 #address-cell <<
2191 #size-cells = <<
2192 <<
2193 port@1 { <<
2194 reg = <<
2195 swao_ <<
2196 <<
2197 <<
2198 }; <<
2199 }; <<
2200 }; <<
2201 <<
2202 in-ports { <<
2203 port { <<
2204 swao_ <<
2205 <<
2206 <<
2207 }; <<
2208 }; <<
2209 }; <<
2210 }; <<
2211 <<
2212 tpda@4b08000 { <<
2213 compatible = "qcom,co <<
2214 reg = <0x0 0x4b08000 <<
2215 <<
2216 clocks = <&aoss_qmp>; <<
2217 clock-names = "apb_pc <<
2218 <<
2219 out-ports { <<
2220 port { <<
2221 aoss_ <<
2222 <<
2223 <<
2224 }; <<
2225 }; <<
2226 }; <<
2227 <<
2228 in-ports { <<
2229 #address-cell <<
2230 #size-cells = <<
2231 <<
2232 port@0 { <<
2233 reg = <<
2234 aoss_ <<
2235 <<
2236 <<
2237 }; <<
2238 }; <<
2239 <<
2240 port@1 { <<
2241 reg = <<
2242 aoss_ <<
2243 <<
2244 <<
2245 }; <<
2246 }; <<
2247 <<
2248 port@2 { <<
2249 reg = <<
2250 aoss_ <<
2251 <<
2252 <<
2253 }; <<
2254 }; <<
2255 <<
2256 port@3 { <<
2257 reg = <<
2258 aoss_ <<
2259 <<
2260 <<
2261 }; <<
2262 }; <<
2263 <<
2264 port@4 { <<
2265 reg = <<
2266 aoss_ <<
2267 <<
2268 <<
2269 }; <<
2270 }; <<
2271 }; <<
2272 }; <<
2273 <<
2274 tpdm@4b09000 { <<
2275 compatible = "qcom,co <<
2276 reg = <0x0 0x4b09000 <<
2277 <<
2278 clocks = <&aoss_qmp>; <<
2279 clock-names = "apb_pc <<
2280 <<
2281 qcom,cmb-element-bits <<
2282 qcom,cmb-msrs-num = < <<
2283 <<
2284 out-ports { <<
2285 port { <<
2286 aoss_ <<
2287 <<
2288 <<
2289 }; <<
2290 }; <<
2291 }; <<
2292 }; <<
2293 <<
2294 tpdm@4b0a000 { <<
2295 compatible = "qcom,co <<
2296 reg = <0x0 0x4b0a000 <<
2297 <<
2298 clocks = <&aoss_qmp>; <<
2299 clock-names = "apb_pc <<
2300 <<
2301 qcom,cmb-element-bits <<
2302 qcom,cmb-msrs-num = < <<
2303 <<
2304 out-ports { <<
2305 port { <<
2306 aoss_ <<
2307 <<
2308 <<
2309 }; <<
2310 }; <<
2311 }; <<
2312 }; <<
2313 <<
2314 tpdm@4b0b000 { <<
2315 compatible = "qcom,co <<
2316 reg = <0x0 0x4b0b000 <<
2317 <<
2318 clocks = <&aoss_qmp>; <<
2319 clock-names = "apb_pc <<
2320 <<
2321 qcom,cmb-element-bits <<
2322 qcom,cmb-msrs-num = < <<
2323 <<
2324 out-ports { <<
2325 port { <<
2326 aoss_ <<
2327 <<
2328 <<
2329 }; <<
2330 }; <<
2331 }; <<
2332 }; <<
2333 <<
2334 tpdm@4b0c000 { <<
2335 compatible = "qcom,co <<
2336 reg = <0x0 0x4b0c000 <<
2337 <<
2338 clocks = <&aoss_qmp>; <<
2339 clock-names = "apb_pc <<
2340 <<
2341 qcom,cmb-element-bits <<
2342 qcom,cmb-msrs-num = < <<
2343 <<
2344 out-ports { <<
2345 port { <<
2346 aoss_ <<
2347 <<
2348 <<
2349 }; <<
2350 }; <<
2351 }; <<
2352 }; <<
2353 <<
2354 tpdm@4b0d000 { <<
2355 compatible = "qcom,co <<
2356 reg = <0x0 0x4b0d000 <<
2357 <<
2358 clocks = <&aoss_qmp>; <<
2359 clock-names = "apb_pc <<
2360 <<
2361 qcom,dsb-element-bits <<
2362 qcom,dsb-msrs-num = < <<
2363 <<
2364 out-ports { <<
2365 port { <<
2366 aoss_ <<
2367 <<
2368 <<
2369 }; <<
2370 }; <<
2371 }; <<
2372 }; <<
2373 <<
2374 aoss_cti: cti@4b13000 { <<
2375 compatible = "arm,cor <<
2376 reg = <0x0 0x4b13000 <<
2377 <<
2378 clocks = <&aoss_qmp>; <<
2379 clock-names = "apb_pc <<
2380 }; <<
2381 <<
2382 etm@6040000 { <<
2383 compatible = "arm,pri <<
2384 reg = <0x0 0x6040000 <<
2385 cpu = <&CPU0>; <<
2386 <<
2387 clocks = <&aoss_qmp>; <<
2388 clock-names = "apb_pc <<
2389 arm,coresight-loses-c <<
2390 qcom,skip-power-up; <<
2391 <<
2392 out-ports { <<
2393 port { <<
2394 etm0_ <<
2395 <<
2396 <<
2397 }; <<
2398 }; <<
2399 }; <<
2400 }; <<
2401 <<
2402 etm@6140000 { <<
2403 compatible = "arm,pri <<
2404 reg = <0x0 0x6140000 <<
2405 cpu = <&CPU1>; <<
2406 <<
2407 clocks = <&aoss_qmp>; <<
2408 clock-names = "apb_pc <<
2409 arm,coresight-loses-c <<
2410 qcom,skip-power-up; <<
2411 <<
2412 out-ports { <<
2413 port { <<
2414 etm1_ <<
2415 <<
2416 <<
2417 }; <<
2418 }; <<
2419 }; <<
2420 }; <<
2421 <<
2422 etm@6240000 { <<
2423 compatible = "arm,pri <<
2424 reg = <0x0 0x6240000 <<
2425 cpu = <&CPU2>; <<
2426 <<
2427 clocks = <&aoss_qmp>; <<
2428 clock-names = "apb_pc <<
2429 arm,coresight-loses-c <<
2430 qcom,skip-power-up; <<
2431 <<
2432 out-ports { <<
2433 port { <<
2434 etm2_ <<
2435 <<
2436 <<
2437 }; <<
2438 }; <<
2439 }; <<
2440 }; <<
2441 <<
2442 etm@6340000 { <<
2443 compatible = "arm,pri <<
2444 reg = <0x0 0x6340000 <<
2445 cpu = <&CPU3>; <<
2446 <<
2447 clocks = <&aoss_qmp>; <<
2448 clock-names = "apb_pc <<
2449 arm,coresight-loses-c <<
2450 qcom,skip-power-up; <<
2451 <<
2452 out-ports { <<
2453 port { <<
2454 etm3_ <<
2455 <<
2456 <<
2457 }; <<
2458 }; <<
2459 }; <<
2460 }; <<
2461 <<
2462 etm@6440000 { <<
2463 compatible = "arm,pri <<
2464 reg = <0x0 0x6440000 <<
2465 cpu = <&CPU4>; <<
2466 <<
2467 clocks = <&aoss_qmp>; <<
2468 clock-names = "apb_pc <<
2469 arm,coresight-loses-c <<
2470 qcom,skip-power-up; <<
2471 <<
2472 out-ports { <<
2473 port { <<
2474 etm4_ <<
2475 <<
2476 <<
2477 }; <<
2478 }; <<
2479 }; <<
2480 }; <<
2481 <<
2482 etm@6540000 { <<
2483 compatible = "arm,pri <<
2484 reg = <0x0 0x6540000 <<
2485 cpu = <&CPU5>; <<
2486 <<
2487 clocks = <&aoss_qmp>; <<
2488 clock-names = "apb_pc <<
2489 arm,coresight-loses-c <<
2490 qcom,skip-power-up; <<
2491 <<
2492 out-ports { <<
2493 port { <<
2494 etm5_ <<
2495 <<
2496 <<
2497 }; <<
2498 }; <<
2499 }; <<
2500 }; <<
2501 <<
2502 etm@6640000 { <<
2503 compatible = "arm,pri <<
2504 reg = <0x0 0x6640000 <<
2505 cpu = <&CPU6>; <<
2506 <<
2507 clocks = <&aoss_qmp>; <<
2508 clock-names = "apb_pc <<
2509 arm,coresight-loses-c <<
2510 qcom,skip-power-up; <<
2511 <<
2512 out-ports { <<
2513 port { <<
2514 etm6_ <<
2515 <<
2516 <<
2517 }; <<
2518 }; <<
2519 }; <<
2520 }; <<
2521 <<
2522 etm@6740000 { <<
2523 compatible = "arm,pri <<
2524 reg = <0x0 0x6740000 <<
2525 cpu = <&CPU7>; <<
2526 <<
2527 clocks = <&aoss_qmp>; <<
2528 clock-names = "apb_pc <<
2529 arm,coresight-loses-c <<
2530 qcom,skip-power-up; <<
2531 <<
2532 out-ports { <<
2533 port { <<
2534 etm7_ <<
2535 <<
2536 <<
2537 }; <<
2538 }; <<
2539 }; <<
2540 }; <<
2541 <<
2542 funnel@6800000 { <<
2543 compatible = "arm,cor <<
2544 reg = <0x0 0x6800000 <<
2545 <<
2546 clocks = <&aoss_qmp>; <<
2547 clock-names = "apb_pc <<
2548 <<
2549 out-ports { <<
2550 port { <<
2551 apss_ <<
2552 <<
2553 <<
2554 }; <<
2555 }; <<
2556 }; <<
2557 <<
2558 in-ports { <<
2559 #address-cell <<
2560 #size-cells = <<
2561 <<
2562 port@0 { <<
2563 reg = <<
2564 apss_ <<
2565 <<
2566 <<
2567 }; <<
2568 }; <<
2569 <<
2570 port@1 { <<
2571 reg = <<
2572 apss_ <<
2573 <<
2574 <<
2575 }; <<
2576 }; <<
2577 <<
2578 port@2 { <<
2579 reg = <<
2580 apss_ <<
2581 <<
2582 <<
2583 }; <<
2584 }; <<
2585 <<
2586 port@3 { <<
2587 reg = <<
2588 apss_ <<
2589 <<
2590 <<
2591 }; <<
2592 }; <<
2593 <<
2594 port@4 { <<
2595 reg = <<
2596 apss_ <<
2597 <<
2598 <<
2599 }; <<
2600 }; <<
2601 <<
2602 port@5 { <<
2603 reg = <<
2604 apss_ <<
2605 <<
2606 <<
2607 }; <<
2608 }; <<
2609 <<
2610 port@6 { <<
2611 reg = <<
2612 apss_ <<
2613 <<
2614 <<
2615 }; <<
2616 }; <<
2617 <<
2618 port@7 { <<
2619 reg = <<
2620 apss_ <<
2621 <<
2622 <<
2623 }; <<
2624 }; <<
2625 }; <<
2626 }; <<
2627 <<
2628 funnel@6810000 { <<
2629 compatible = "arm,cor <<
2630 reg = <0x0 0x6810000 <<
2631 <<
2632 clocks = <&aoss_qmp>; <<
2633 clock-names = "apb_pc <<
2634 <<
2635 out-ports { <<
2636 port { <<
2637 apss_ <<
2638 <<
2639 <<
2640 }; <<
2641 }; <<
2642 }; <<
2643 <<
2644 in-ports { <<
2645 #address-cell <<
2646 #size-cells = <<
2647 <<
2648 port@0 { <<
2649 reg = <<
2650 apss_ <<
2651 <<
2652 <<
2653 }; <<
2654 }; <<
2655 <<
2656 port@3 { <<
2657 reg = <<
2658 apss_ <<
2659 <<
2660 <<
2661 }; <<
2662 }; <<
2663 }; <<
2664 }; <<
2665 <<
2666 tpdm@6860000 { <<
2667 compatible = "qcom,co <<
2668 reg = <0x0 0x6860000 <<
2669 <<
2670 clocks = <&aoss_qmp>; <<
2671 clock-names = "apb_pc <<
2672 <<
2673 qcom,cmb-element-bits <<
2674 qcom,cmb-msrs-num = < <<
2675 <<
2676 out-ports { <<
2677 port { <<
2678 apss_ <<
2679 <<
2680 <<
2681 }; <<
2682 }; <<
2683 }; <<
2684 }; <<
2685 <<
2686 tpdm@6861000 { <<
2687 compatible = "qcom,co <<
2688 reg = <0x0 0x6861000 <<
2689 <<
2690 clocks = <&aoss_qmp>; <<
2691 clock-names = "apb_pc <<
2692 <<
2693 qcom,dsb-element-bits <<
2694 qcom,dsb-msrs-num = < <<
2695 <<
2696 out-ports { <<
2697 port { <<
2698 apss_ <<
2699 <<
2700 <<
2701 }; <<
2702 }; <<
2703 }; <<
2704 }; <<
2705 <<
2706 tpda@6863000 { <<
2707 compatible = "qcom,co <<
2708 reg = <0x0 0x6863000 <<
2709 <<
2710 clocks = <&aoss_qmp>; <<
2711 clock-names = "apb_pc <<
2712 <<
2713 out-ports { <<
2714 port { <<
2715 apss_ <<
2716 <<
2717 <<
2718 }; <<
2719 }; <<
2720 }; <<
2721 <<
2722 in-ports { <<
2723 #address-cell <<
2724 #size-cells = <<
2725 <<
2726 port@0 { <<
2727 reg = <<
2728 apss_ <<
2729 <<
2730 <<
2731 }; <<
2732 }; <<
2733 <<
2734 port@1 { <<
2735 reg = <<
2736 apss_ <<
2737 <<
2738 <<
2739 }; <<
2740 }; <<
2741 <<
2742 port@2 { <<
2743 reg = <<
2744 apss_ <<
2745 <<
2746 <<
2747 }; <<
2748 }; <<
2749 <<
2750 port@3 { <<
2751 reg = <<
2752 apss_ <<
2753 <<
2754 <<
2755 }; <<
2756 }; <<
2757 <<
2758 port@4 { <<
2759 reg = <<
2760 apss_ <<
2761 <<
2762 <<
2763 }; <<
2764 }; <<
2765 }; <<
2766 }; <<
2767 <<
2768 tpdm@68a0000 { <<
2769 compatible = "qcom,co <<
2770 reg = <0x0 0x68a0000 <<
2771 <<
2772 clocks = <&aoss_qmp>; <<
2773 clock-names = "apb_pc <<
2774 <<
2775 qcom,cmb-element-bits <<
2776 qcom,cmb-msrs-num = < <<
2777 <<
2778 out-ports { <<
2779 port { <<
2780 apss_ <<
2781 <<
2782 <<
2783 }; <<
2784 }; <<
2785 }; <<
2786 }; <<
2787 <<
2788 tpdm@68b0000 { <<
2789 compatible = "qcom,co <<
2790 reg = <0x0 0x68b0000 <<
2791 <<
2792 clocks = <&aoss_qmp>; <<
2793 clock-names = "apb_pc <<
2794 <<
2795 qcom,cmb-element-bits <<
2796 qcom,cmb-msrs-num = < <<
2797 <<
2798 out-ports { <<
2799 port { <<
2800 apss_ <<
2801 <<
2802 <<
2803 }; <<
2804 }; <<
2805 }; <<
2806 }; <<
2807 <<
2808 tpdm@68c0000 { <<
2809 compatible = "qcom,co <<
2810 reg = <0x0 0x68c0000 <<
2811 <<
2812 clocks = <&aoss_qmp>; <<
2813 clock-names = "apb_pc <<
2814 <<
2815 qcom,dsb-element-bits <<
2816 qcom,dsb-msrs-num = < <<
2817 <<
2818 out-ports { <<
2819 port { <<
2820 apss_ <<
2821 <<
2822 <<
2823 }; <<
2824 }; <<
2825 }; <<
2826 }; <<
2827 <<
2828 usb_0_hsphy: phy@88e4000 { 1647 usb_0_hsphy: phy@88e4000 {
2829 compatible = "qcom,sa 1648 compatible = "qcom,sa8775p-usb-hs-phy",
2830 "qcom,us 1649 "qcom,usb-snps-hs-5nm-phy";
2831 reg = <0 0x088e4000 0 1650 reg = <0 0x088e4000 0 0x120>;
2832 clocks = <&rpmhcc RPM 1651 clocks = <&rpmhcc RPMH_CXO_CLK>;
2833 clock-names = "ref"; 1652 clock-names = "ref";
2834 resets = <&gcc GCC_US 1653 resets = <&gcc GCC_USB2_PHY_PRIM_BCR>;
2835 1654
2836 #phy-cells = <0>; 1655 #phy-cells = <0>;
2837 1656
2838 status = "disabled"; 1657 status = "disabled";
2839 }; 1658 };
2840 1659
2841 usb_0_qmpphy: phy@88e8000 { 1660 usb_0_qmpphy: phy@88e8000 {
2842 compatible = "qcom,sa 1661 compatible = "qcom,sa8775p-qmp-usb3-uni-phy";
2843 reg = <0 0x088e8000 0 1662 reg = <0 0x088e8000 0 0x2000>;
2844 1663
2845 clocks = <&gcc GCC_US 1664 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2846 <&gcc GCC_US 1665 <&gcc GCC_USB_CLKREF_EN>,
2847 <&gcc GCC_US 1666 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
2848 <&gcc GCC_US 1667 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2849 clock-names = "aux", 1668 clock-names = "aux", "ref", "com_aux", "pipe";
2850 1669
2851 resets = <&gcc GCC_US 1670 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
2852 <&gcc GCC_US 1671 <&gcc GCC_USB3PHY_PHY_PRIM_BCR>;
2853 reset-names = "phy", 1672 reset-names = "phy", "phy_phy";
2854 1673
2855 power-domains = <&gcc 1674 power-domains = <&gcc USB30_PRIM_GDSC>;
2856 1675
2857 #clock-cells = <0>; 1676 #clock-cells = <0>;
2858 clock-output-names = 1677 clock-output-names = "usb3_prim_phy_pipe_clk_src";
2859 1678
2860 #phy-cells = <0>; 1679 #phy-cells = <0>;
2861 1680
2862 status = "disabled"; 1681 status = "disabled";
2863 }; 1682 };
2864 1683
2865 usb_0: usb@a6f8800 { 1684 usb_0: usb@a6f8800 {
2866 compatible = "qcom,sa 1685 compatible = "qcom,sa8775p-dwc3", "qcom,dwc3";
2867 reg = <0 0x0a6f8800 0 1686 reg = <0 0x0a6f8800 0 0x400>;
2868 #address-cells = <2>; 1687 #address-cells = <2>;
2869 #size-cells = <2>; 1688 #size-cells = <2>;
2870 ranges; 1689 ranges;
2871 1690
2872 clocks = <&gcc GCC_CF 1691 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
2873 <&gcc GCC_US 1692 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
2874 <&gcc GCC_AG 1693 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
2875 <&gcc GCC_US 1694 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
2876 <&gcc GCC_US 1695 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
2877 clock-names = "cfg_no 1696 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi";
2878 1697
2879 assigned-clocks = <&g 1698 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2880 <&g 1699 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
2881 assigned-clock-rates 1700 assigned-clock-rates = <19200000>, <200000000>;
2882 1701
2883 interrupts-extended = 1702 interrupts-extended = <&intc GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>,
2884 1703 <&intc GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
2885 1704 <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
2886 1705 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
2887 1706 <&pdc 12 IRQ_TYPE_LEVEL_HIGH>;
2888 interrupt-names = "pw 1707 interrupt-names = "pwr_event",
2889 "hs 1708 "hs_phy_irq",
2890 "dp 1709 "dp_hs_phy_irq",
2891 "dm 1710 "dm_hs_phy_irq",
2892 "ss 1711 "ss_phy_irq";
2893 1712
2894 power-domains = <&gcc 1713 power-domains = <&gcc USB30_PRIM_GDSC>;
2895 required-opps = <&rpm 1714 required-opps = <&rpmhpd_opp_nom>;
2896 1715
2897 resets = <&gcc GCC_US 1716 resets = <&gcc GCC_USB30_PRIM_BCR>;
2898 1717
2899 interconnects = <&agg 1718 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
2900 <&gem 1719 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
2901 interconnect-names = 1720 interconnect-names = "usb-ddr", "apps-usb";
2902 1721
2903 wakeup-source; 1722 wakeup-source;
2904 1723
2905 status = "disabled"; 1724 status = "disabled";
2906 1725
2907 usb_0_dwc3: usb@a6000 1726 usb_0_dwc3: usb@a600000 {
2908 compatible = 1727 compatible = "snps,dwc3";
2909 reg = <0 0x0a 1728 reg = <0 0x0a600000 0 0xe000>;
2910 interrupts = 1729 interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>;
2911 iommus = <&ap 1730 iommus = <&apps_smmu 0x080 0x0>;
2912 phys = <&usb_ 1731 phys = <&usb_0_hsphy>, <&usb_0_qmpphy>;
2913 phy-names = " 1732 phy-names = "usb2-phy", "usb3-phy";
2914 }; 1733 };
2915 }; 1734 };
2916 1735
2917 usb_1_hsphy: phy@88e6000 { 1736 usb_1_hsphy: phy@88e6000 {
2918 compatible = "qcom,sa 1737 compatible = "qcom,sa8775p-usb-hs-phy",
2919 "qcom,us 1738 "qcom,usb-snps-hs-5nm-phy";
2920 reg = <0 0x088e6000 0 1739 reg = <0 0x088e6000 0 0x120>;
2921 clocks = <&gcc GCC_US 1740 clocks = <&gcc GCC_USB_CLKREF_EN>;
2922 clock-names = "ref"; 1741 clock-names = "ref";
2923 resets = <&gcc GCC_US 1742 resets = <&gcc GCC_USB2_PHY_SEC_BCR>;
2924 1743
2925 #phy-cells = <0>; 1744 #phy-cells = <0>;
2926 1745
2927 status = "disabled"; 1746 status = "disabled";
2928 }; 1747 };
2929 1748
2930 usb_1_qmpphy: phy@88ea000 { 1749 usb_1_qmpphy: phy@88ea000 {
2931 compatible = "qcom,sa 1750 compatible = "qcom,sa8775p-qmp-usb3-uni-phy";
2932 reg = <0 0x088ea000 0 1751 reg = <0 0x088ea000 0 0x2000>;
2933 1752
2934 clocks = <&gcc GCC_US 1753 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
2935 <&gcc GCC_US 1754 <&gcc GCC_USB_CLKREF_EN>,
2936 <&gcc GCC_US 1755 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
2937 <&gcc GCC_US 1756 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
2938 clock-names = "aux", 1757 clock-names = "aux", "ref", "com_aux", "pipe";
2939 1758
2940 resets = <&gcc GCC_US 1759 resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
2941 <&gcc GCC_US 1760 <&gcc GCC_USB3PHY_PHY_SEC_BCR>;
2942 reset-names = "phy", 1761 reset-names = "phy", "phy_phy";
2943 1762
2944 power-domains = <&gcc 1763 power-domains = <&gcc USB30_SEC_GDSC>;
2945 1764
2946 #clock-cells = <0>; 1765 #clock-cells = <0>;
2947 clock-output-names = 1766 clock-output-names = "usb3_sec_phy_pipe_clk_src";
2948 1767
2949 #phy-cells = <0>; 1768 #phy-cells = <0>;
2950 1769
2951 status = "disabled"; 1770 status = "disabled";
2952 }; 1771 };
2953 1772
2954 usb_1: usb@a8f8800 { 1773 usb_1: usb@a8f8800 {
2955 compatible = "qcom,sa 1774 compatible = "qcom,sa8775p-dwc3", "qcom,dwc3";
2956 reg = <0 0x0a8f8800 0 1775 reg = <0 0x0a8f8800 0 0x400>;
2957 #address-cells = <2>; 1776 #address-cells = <2>;
2958 #size-cells = <2>; 1777 #size-cells = <2>;
2959 ranges; 1778 ranges;
2960 1779
2961 clocks = <&gcc GCC_CF 1780 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
2962 <&gcc GCC_US 1781 <&gcc GCC_USB30_SEC_MASTER_CLK>,
2963 <&gcc GCC_AG 1782 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
2964 <&gcc GCC_US 1783 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
2965 <&gcc GCC_US 1784 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>;
2966 clock-names = "cfg_no 1785 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi";
2967 1786
2968 assigned-clocks = <&g 1787 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2969 <&g 1788 <&gcc GCC_USB30_SEC_MASTER_CLK>;
2970 assigned-clock-rates 1789 assigned-clock-rates = <19200000>, <200000000>;
2971 1790
2972 interrupts-extended = 1791 interrupts-extended = <&intc GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
2973 1792 <&intc GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
2974 1793 <&pdc 8 IRQ_TYPE_EDGE_BOTH>,
2975 1794 <&pdc 7 IRQ_TYPE_EDGE_BOTH>,
2976 1795 <&pdc 13 IRQ_TYPE_LEVEL_HIGH>;
2977 interrupt-names = "pw 1796 interrupt-names = "pwr_event",
2978 "hs 1797 "hs_phy_irq",
2979 "dp 1798 "dp_hs_phy_irq",
2980 "dm 1799 "dm_hs_phy_irq",
2981 "ss 1800 "ss_phy_irq";
2982 1801
2983 power-domains = <&gcc 1802 power-domains = <&gcc USB30_SEC_GDSC>;
2984 required-opps = <&rpm 1803 required-opps = <&rpmhpd_opp_nom>;
2985 1804
2986 resets = <&gcc GCC_US 1805 resets = <&gcc GCC_USB30_SEC_BCR>;
2987 1806
2988 interconnects = <&agg 1807 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>,
2989 <&gem 1808 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
2990 interconnect-names = 1809 interconnect-names = "usb-ddr", "apps-usb";
2991 1810
2992 wakeup-source; 1811 wakeup-source;
2993 1812
2994 status = "disabled"; 1813 status = "disabled";
2995 1814
2996 usb_1_dwc3: usb@a8000 1815 usb_1_dwc3: usb@a800000 {
2997 compatible = 1816 compatible = "snps,dwc3";
2998 reg = <0 0x0a 1817 reg = <0 0x0a800000 0 0xe000>;
2999 interrupts = 1818 interrupts = <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>;
3000 iommus = <&ap 1819 iommus = <&apps_smmu 0x0a0 0x0>;
3001 phys = <&usb_ 1820 phys = <&usb_1_hsphy>, <&usb_1_qmpphy>;
3002 phy-names = " 1821 phy-names = "usb2-phy", "usb3-phy";
3003 }; 1822 };
3004 }; 1823 };
3005 1824
3006 usb_2_hsphy: phy@88e7000 { 1825 usb_2_hsphy: phy@88e7000 {
3007 compatible = "qcom,sa 1826 compatible = "qcom,sa8775p-usb-hs-phy",
3008 "qcom,us 1827 "qcom,usb-snps-hs-5nm-phy";
3009 reg = <0 0x088e7000 0 1828 reg = <0 0x088e7000 0 0x120>;
3010 clocks = <&gcc GCC_US 1829 clocks = <&gcc GCC_USB_CLKREF_EN>;
3011 clock-names = "ref"; 1830 clock-names = "ref";
3012 resets = <&gcc GCC_US 1831 resets = <&gcc GCC_USB3_PHY_TERT_BCR>;
3013 1832
3014 #phy-cells = <0>; 1833 #phy-cells = <0>;
3015 1834
3016 status = "disabled"; 1835 status = "disabled";
3017 }; 1836 };
3018 1837
3019 usb_2: usb@a4f8800 { 1838 usb_2: usb@a4f8800 {
3020 compatible = "qcom,sa 1839 compatible = "qcom,sa8775p-dwc3", "qcom,dwc3";
3021 reg = <0 0x0a4f8800 0 1840 reg = <0 0x0a4f8800 0 0x400>;
3022 #address-cells = <2>; 1841 #address-cells = <2>;
3023 #size-cells = <2>; 1842 #size-cells = <2>;
3024 ranges; 1843 ranges;
3025 1844
3026 clocks = <&gcc GCC_CF 1845 clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>,
3027 <&gcc GCC_US 1846 <&gcc GCC_USB20_MASTER_CLK>,
3028 <&gcc GCC_AG 1847 <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>,
3029 <&gcc GCC_US 1848 <&gcc GCC_USB20_SLEEP_CLK>,
3030 <&gcc GCC_US 1849 <&gcc GCC_USB20_MOCK_UTMI_CLK>;
3031 clock-names = "cfg_no 1850 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi";
3032 1851
3033 assigned-clocks = <&g 1852 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
3034 <&g 1853 <&gcc GCC_USB20_MASTER_CLK>;
3035 assigned-clock-rates 1854 assigned-clock-rates = <19200000>, <200000000>;
3036 1855
3037 interrupts-extended = 1856 interrupts-extended = <&intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
3038 1857 <&intc GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>,
3039 1858 <&pdc 10 IRQ_TYPE_EDGE_BOTH>,
3040 1859 <&pdc 9 IRQ_TYPE_EDGE_BOTH>;
3041 interrupt-names = "pw 1860 interrupt-names = "pwr_event",
3042 "hs 1861 "hs_phy_irq",
3043 "dp 1862 "dp_hs_phy_irq",
3044 "dm 1863 "dm_hs_phy_irq";
3045 1864
3046 power-domains = <&gcc 1865 power-domains = <&gcc USB20_PRIM_GDSC>;
3047 required-opps = <&rpm 1866 required-opps = <&rpmhpd_opp_nom>;
3048 1867
3049 resets = <&gcc GCC_US 1868 resets = <&gcc GCC_USB20_PRIM_BCR>;
3050 1869
3051 interconnects = <&agg 1870 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>,
3052 <&gem 1871 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB2 0>;
3053 interconnect-names = 1872 interconnect-names = "usb-ddr", "apps-usb";
3054 1873
3055 wakeup-source; 1874 wakeup-source;
3056 1875
3057 status = "disabled"; 1876 status = "disabled";
3058 1877
3059 usb_2_dwc3: usb@a4000 1878 usb_2_dwc3: usb@a400000 {
3060 compatible = 1879 compatible = "snps,dwc3";
3061 reg = <0 0x0a 1880 reg = <0 0x0a400000 0 0xe000>;
3062 interrupts = 1881 interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>;
3063 iommus = <&ap 1882 iommus = <&apps_smmu 0x020 0x0>;
3064 phys = <&usb_ 1883 phys = <&usb_2_hsphy>;
3065 phy-names = " 1884 phy-names = "usb2-phy";
3066 }; 1885 };
3067 }; 1886 };
3068 1887
3069 tcsr_mutex: hwlock@1f40000 { 1888 tcsr_mutex: hwlock@1f40000 {
3070 compatible = "qcom,tc 1889 compatible = "qcom,tcsr-mutex";
3071 reg = <0x0 0x01f40000 1890 reg = <0x0 0x01f40000 0x0 0x20000>;
3072 #hwlock-cells = <1>; 1891 #hwlock-cells = <1>;
3073 }; 1892 };
3074 1893
3075 gpucc: clock-controller@3d900 1894 gpucc: clock-controller@3d90000 {
3076 compatible = "qcom,sa 1895 compatible = "qcom,sa8775p-gpucc";
3077 reg = <0x0 0x03d90000 1896 reg = <0x0 0x03d90000 0x0 0xa000>;
3078 clocks = <&rpmhcc RPM 1897 clocks = <&rpmhcc RPMH_CXO_CLK>,
3079 <&gcc GCC_GP 1898 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
3080 <&gcc GCC_GP 1899 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
3081 clock-names = "bi_tcx 1900 clock-names = "bi_tcxo",
3082 "gcc_gp 1901 "gcc_gpu_gpll0_clk_src",
3083 "gcc_gp 1902 "gcc_gpu_gpll0_div_clk_src";
3084 #clock-cells = <1>; 1903 #clock-cells = <1>;
3085 #reset-cells = <1>; 1904 #reset-cells = <1>;
3086 #power-domain-cells = 1905 #power-domain-cells = <1>;
3087 }; 1906 };
3088 1907
3089 adreno_smmu: iommu@3da0000 { 1908 adreno_smmu: iommu@3da0000 {
3090 compatible = "qcom,sa 1909 compatible = "qcom,sa8775p-smmu-500", "qcom,adreno-smmu",
3091 "qcom,sm 1910 "qcom,smmu-500", "arm,mmu-500";
3092 reg = <0x0 0x03da0000 1911 reg = <0x0 0x03da0000 0x0 0x20000>;
3093 #iommu-cells = <2>; 1912 #iommu-cells = <2>;
3094 #global-interrupts = 1913 #global-interrupts = <2>;
3095 dma-coherent; 1914 dma-coherent;
3096 power-domains = <&gpu 1915 power-domains = <&gpucc GPU_CC_CX_GDSC>;
3097 clocks = <&gcc GCC_GP 1916 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
3098 <&gcc GCC_GP 1917 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
3099 <&gpucc GPU_ 1918 <&gpucc GPU_CC_AHB_CLK>,
3100 <&gpucc GPU_ 1919 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
3101 <&gpucc GPU_ 1920 <&gpucc GPU_CC_CX_GMU_CLK>,
3102 <&gpucc GPU_ 1921 <&gpucc GPU_CC_HUB_CX_INT_CLK>,
3103 <&gpucc GPU_ 1922 <&gpucc GPU_CC_HUB_AON_CLK>;
3104 clock-names = "gcc_gp 1923 clock-names = "gcc_gpu_memnoc_gfx_clk",
3105 "gcc_gp 1924 "gcc_gpu_snoc_dvm_gfx_clk",
3106 "gpu_cc 1925 "gpu_cc_ahb_clk",
3107 "gpu_cc 1926 "gpu_cc_hlos1_vote_gpu_smmu_clk",
3108 "gpu_cc 1927 "gpu_cc_cx_gmu_clk",
3109 "gpu_cc 1928 "gpu_cc_hub_cx_int_clk",
3110 "gpu_cc 1929 "gpu_cc_hub_aon_clk";
3111 interrupts = <GIC_SPI 1930 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
3112 <GIC_SPI 1931 <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
3113 <GIC_SPI 1932 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
3114 <GIC_SPI 1933 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
3115 <GIC_SPI 1934 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
3116 <GIC_SPI 1935 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
3117 <GIC_SPI 1936 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
3118 <GIC_SPI 1937 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
3119 <GIC_SPI 1938 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
3120 <GIC_SPI 1939 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
3121 <GIC_SPI 1940 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
3122 <GIC_SPI 1941 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>;
3123 }; 1942 };
3124 1943
3125 serdes0: phy@8901000 { 1944 serdes0: phy@8901000 {
3126 compatible = "qcom,sa 1945 compatible = "qcom,sa8775p-dwmac-sgmii-phy";
3127 reg = <0x0 0x08901000 1946 reg = <0x0 0x08901000 0x0 0xe10>;
3128 clocks = <&gcc GCC_SG 1947 clocks = <&gcc GCC_SGMI_CLKREF_EN>;
3129 clock-names = "sgmi_r 1948 clock-names = "sgmi_ref";
3130 #phy-cells = <0>; 1949 #phy-cells = <0>;
3131 status = "disabled"; 1950 status = "disabled";
3132 }; 1951 };
3133 1952
3134 serdes1: phy@8902000 { 1953 serdes1: phy@8902000 {
3135 compatible = "qcom,sa 1954 compatible = "qcom,sa8775p-dwmac-sgmii-phy";
3136 reg = <0x0 0x08902000 1955 reg = <0x0 0x08902000 0x0 0xe10>;
3137 clocks = <&gcc GCC_SG 1956 clocks = <&gcc GCC_SGMI_CLKREF_EN>;
3138 clock-names = "sgmi_r 1957 clock-names = "sgmi_ref";
3139 #phy-cells = <0>; 1958 #phy-cells = <0>;
3140 status = "disabled"; 1959 status = "disabled";
3141 }; 1960 };
3142 1961
3143 pmu@9091000 { <<
3144 compatible = "qcom,sa <<
3145 reg = <0x0 0x9091000 <<
3146 interrupts = <GIC_SPI <<
3147 interconnects = <&mc_ <<
3148 &mc_ <<
3149 <<
3150 operating-points-v2 = <<
3151 <<
3152 llcc_bwmon_opp_table: <<
3153 compatible = <<
3154 <<
3155 opp-0 { <<
3156 opp-p <<
3157 }; <<
3158 <<
3159 opp-1 { <<
3160 opp-p <<
3161 }; <<
3162 <<
3163 opp-2 { <<
3164 opp-p <<
3165 }; <<
3166 <<
3167 opp-3 { <<
3168 opp-p <<
3169 }; <<
3170 <<
3171 opp-4 { <<
3172 opp-p <<
3173 }; <<
3174 <<
3175 opp-5 { <<
3176 opp-p <<
3177 }; <<
3178 <<
3179 opp-6 { <<
3180 opp-p <<
3181 }; <<
3182 <<
3183 opp-7 { <<
3184 opp-p <<
3185 }; <<
3186 <<
3187 opp-8 { <<
3188 opp-p <<
3189 }; <<
3190 <<
3191 opp-9 { <<
3192 opp-p <<
3193 }; <<
3194 }; <<
3195 }; <<
3196 <<
3197 pmu@90b5400 { <<
3198 compatible = "qcom,sa <<
3199 reg = <0x0 0x90b5400 <<
3200 interrupts = <GIC_SPI <<
3201 interconnects = <&gem <<
3202 &gem <<
3203 <<
3204 operating-points-v2 = <<
3205 <<
3206 cpu_bwmon_opp_table: <<
3207 compatible = <<
3208 <<
3209 opp-0 { <<
3210 opp-p <<
3211 }; <<
3212 <<
3213 opp-1 { <<
3214 opp-p <<
3215 }; <<
3216 <<
3217 opp-2 { <<
3218 opp-p <<
3219 }; <<
3220 <<
3221 opp-3 { <<
3222 opp-p <<
3223 }; <<
3224 }; <<
3225 <<
3226 }; <<
3227 <<
3228 pmu@90b6400 { <<
3229 compatible = "qcom,sa <<
3230 reg = <0x0 0x90b6400 <<
3231 interrupts = <GIC_SPI <<
3232 interconnects = <&gem <<
3233 &gem <<
3234 <<
3235 operating-points-v2 = <<
3236 }; <<
3237 <<
3238 llcc: system-cache-controller <<
3239 compatible = "qcom,sa <<
3240 reg = <0x0 0x09200000 <<
3241 <0x0 0x09300000 <<
3242 <0x0 0x09400000 <<
3243 <0x0 0x09500000 <<
3244 <0x0 0x09600000 <<
3245 <0x0 0x09700000 <<
3246 <0x0 0x09a00000 <<
3247 reg-names = "llcc0_ba <<
3248 "llcc1_ba <<
3249 "llcc2_ba <<
3250 "llcc3_ba <<
3251 "llcc4_ba <<
3252 "llcc5_ba <<
3253 "llcc_bro <<
3254 interrupts = <GIC_SPI <<
3255 }; <<
3256 <<
3257 pdc: interrupt-controller@b22 1962 pdc: interrupt-controller@b220000 {
3258 compatible = "qcom,sa 1963 compatible = "qcom,sa8775p-pdc", "qcom,pdc";
3259 reg = <0x0 0x0b220000 1964 reg = <0x0 0x0b220000 0x0 0x30000>,
3260 <0x0 0x17c000f0 1965 <0x0 0x17c000f0 0x0 0x64>;
3261 qcom,pdc-ranges = <0 1966 qcom,pdc-ranges = <0 480 40>,
3262 <40 1967 <40 140 14>,
3263 <54 1968 <54 263 1>,
3264 <55 1969 <55 306 4>,
3265 <59 1970 <59 312 3>,
3266 <62 1971 <62 374 2>,
3267 <64 1972 <64 434 2>,
3268 <66 1973 <66 438 2>,
3269 <70 1974 <70 520 1>,
3270 <73 1975 <73 523 1>,
3271 <11 1976 <118 568 6>,
3272 <12 1977 <124 609 3>,
3273 <15 1978 <159 638 1>,
3274 <16 1979 <160 720 3>,
3275 <16 1980 <169 728 30>,
3276 <19 1981 <199 416 2>,
3277 <20 1982 <201 449 1>,
3278 <20 1983 <202 89 1>,
3279 <20 1984 <203 451 1>,
3280 <20 1985 <204 462 1>,
3281 <20 1986 <205 264 1>,
3282 <20 1987 <206 579 1>,
3283 <20 1988 <207 653 1>,
3284 <20 1989 <208 656 1>,
3285 <20 1990 <209 659 1>,
3286 <21 1991 <210 122 1>,
3287 <21 1992 <211 699 1>,
3288 <21 1993 <212 705 1>,
3289 <21 1994 <213 450 1>,
3290 <21 1995 <214 643 2>,
3291 <21 1996 <216 646 5>,
3292 <22 1997 <221 390 5>,
3293 <22 1998 <226 700 2>,
3294 <22 1999 <228 440 1>,
3295 <22 2000 <229 663 1>,
3296 <23 2001 <230 524 2>,
3297 <23 2002 <232 612 3>,
3298 <23 2003 <235 723 5>;
3299 #interrupt-cells = <2 2004 #interrupt-cells = <2>;
3300 interrupt-parent = <& 2005 interrupt-parent = <&intc>;
3301 interrupt-controller; 2006 interrupt-controller;
3302 }; 2007 };
3303 2008
3304 tsens2: thermal-sensor@c25100 2009 tsens2: thermal-sensor@c251000 {
3305 compatible = "qcom,sa 2010 compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2";
3306 reg = <0x0 0x0c251000 2011 reg = <0x0 0x0c251000 0x0 0x1ff>,
3307 <0x0 0x0c224000 2012 <0x0 0x0c224000 0x0 0x8>;
3308 interrupts = <GIC_SPI 2013 interrupts = <GIC_SPI 572 IRQ_TYPE_LEVEL_HIGH>,
3309 <GIC_SPI 2014 <GIC_SPI 609 IRQ_TYPE_LEVEL_HIGH>;
3310 #qcom,sensors = <13>; 2015 #qcom,sensors = <13>;
3311 interrupt-names = "up 2016 interrupt-names = "uplow", "critical";
3312 #thermal-sensor-cells 2017 #thermal-sensor-cells = <1>;
3313 }; 2018 };
3314 2019
3315 tsens3: thermal-sensor@c25200 2020 tsens3: thermal-sensor@c252000 {
3316 compatible = "qcom,sa 2021 compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2";
3317 reg = <0x0 0x0c252000 2022 reg = <0x0 0x0c252000 0x0 0x1ff>,
3318 <0x0 0x0c225000 2023 <0x0 0x0c225000 0x0 0x8>;
3319 interrupts = <GIC_SPI 2024 interrupts = <GIC_SPI 573 IRQ_TYPE_LEVEL_HIGH>,
3320 <GIC_SPI 2025 <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>;
3321 #qcom,sensors = <13>; 2026 #qcom,sensors = <13>;
3322 interrupt-names = "up 2027 interrupt-names = "uplow", "critical";
3323 #thermal-sensor-cells 2028 #thermal-sensor-cells = <1>;
3324 }; 2029 };
3325 2030
3326 tsens0: thermal-sensor@c26300 2031 tsens0: thermal-sensor@c263000 {
3327 compatible = "qcom,sa 2032 compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2";
3328 reg = <0x0 0x0c263000 2033 reg = <0x0 0x0c263000 0x0 0x1ff>,
3329 <0x0 0x0c222000 2034 <0x0 0x0c222000 0x0 0x8>;
3330 interrupts = <GIC_SPI 2035 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
3331 <GIC_SPI 2036 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
3332 #qcom,sensors = <12>; 2037 #qcom,sensors = <12>;
3333 interrupt-names = "up 2038 interrupt-names = "uplow", "critical";
3334 #thermal-sensor-cells 2039 #thermal-sensor-cells = <1>;
3335 }; 2040 };
3336 2041
3337 tsens1: thermal-sensor@c26500 2042 tsens1: thermal-sensor@c265000 {
3338 compatible = "qcom,sa 2043 compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2";
3339 reg = <0x0 0x0c265000 2044 reg = <0x0 0x0c265000 0x0 0x1ff>,
3340 <0x0 0x0c223000 2045 <0x0 0x0c223000 0x0 0x8>;
3341 interrupts = <GIC_SPI 2046 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
3342 <GIC_SPI 2047 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
3343 #qcom,sensors = <12>; 2048 #qcom,sensors = <12>;
3344 interrupt-names = "up 2049 interrupt-names = "uplow", "critical";
3345 #thermal-sensor-cells 2050 #thermal-sensor-cells = <1>;
3346 }; 2051 };
3347 2052
3348 aoss_qmp: power-management@c3 2053 aoss_qmp: power-management@c300000 {
3349 compatible = "qcom,sa 2054 compatible = "qcom,sa8775p-aoss-qmp", "qcom,aoss-qmp";
3350 reg = <0x0 0x0c300000 2055 reg = <0x0 0x0c300000 0x0 0x400>;
3351 interrupts-extended = 2056 interrupts-extended = <&ipcc IPCC_CLIENT_AOP
3352 2057 IPCC_MPROC_SIGNAL_GLINK_QMP
3353 2058 IRQ_TYPE_EDGE_RISING>;
3354 mboxes = <&ipcc IPCC_ 2059 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
3355 #clock-cells = <0>; 2060 #clock-cells = <0>;
3356 }; 2061 };
3357 2062
3358 sram@c3f0000 { 2063 sram@c3f0000 {
3359 compatible = "qcom,rp 2064 compatible = "qcom,rpmh-stats";
3360 reg = <0x0 0x0c3f0000 2065 reg = <0x0 0x0c3f0000 0x0 0x400>;
3361 }; 2066 };
3362 2067
3363 spmi_bus: spmi@c440000 { 2068 spmi_bus: spmi@c440000 {
3364 compatible = "qcom,sp 2069 compatible = "qcom,spmi-pmic-arb";
3365 reg = <0x0 0x0c440000 2070 reg = <0x0 0x0c440000 0x0 0x1100>,
3366 <0x0 0x0c600000 2071 <0x0 0x0c600000 0x0 0x2000000>,
3367 <0x0 0x0e600000 2072 <0x0 0x0e600000 0x0 0x100000>,
3368 <0x0 0x0e700000 2073 <0x0 0x0e700000 0x0 0xa0000>,
3369 <0x0 0x0c40a000 2074 <0x0 0x0c40a000 0x0 0x26000>;
3370 reg-names = "core", 2075 reg-names = "core",
3371 "chnls", 2076 "chnls",
3372 "obsrvr", 2077 "obsrvr",
3373 "intr", 2078 "intr",
3374 "cnfg"; 2079 "cnfg";
3375 qcom,channel = <0>; 2080 qcom,channel = <0>;
3376 qcom,ee = <0>; 2081 qcom,ee = <0>;
3377 interrupts-extended = 2082 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3378 interrupt-names = "pe 2083 interrupt-names = "periph_irq";
3379 interrupt-controller; 2084 interrupt-controller;
3380 #interrupt-cells = <4 2085 #interrupt-cells = <4>;
3381 #address-cells = <2>; 2086 #address-cells = <2>;
3382 #size-cells = <0>; 2087 #size-cells = <0>;
3383 }; 2088 };
3384 2089
3385 tlmm: pinctrl@f000000 { 2090 tlmm: pinctrl@f000000 {
3386 compatible = "qcom,sa 2091 compatible = "qcom,sa8775p-tlmm";
3387 reg = <0x0 0x0f000000 2092 reg = <0x0 0x0f000000 0x0 0x1000000>;
3388 interrupts = <GIC_SPI 2093 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
3389 gpio-controller; 2094 gpio-controller;
3390 #gpio-cells = <2>; 2095 #gpio-cells = <2>;
3391 interrupt-controller; 2096 interrupt-controller;
3392 #interrupt-cells = <2 2097 #interrupt-cells = <2>;
3393 gpio-ranges = <&tlmm 2098 gpio-ranges = <&tlmm 0 0 149>;
3394 wakeup-parent = <&pdc 2099 wakeup-parent = <&pdc>;
3395 }; 2100 };
3396 2101
3397 sram: sram@146d8000 { <<
3398 compatible = "qcom,sa <<
3399 reg = <0x0 0x146d8000 <<
3400 ranges = <0x0 0x0 0x1 <<
3401 <<
3402 #address-cells = <1>; <<
3403 #size-cells = <1>; <<
3404 <<
3405 pil-reloc@94c { <<
3406 compatible = <<
3407 reg = <0x94c <<
3408 }; <<
3409 }; <<
3410 <<
3411 apps_smmu: iommu@15000000 { 2102 apps_smmu: iommu@15000000 {
3412 compatible = "qcom,sa 2103 compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500";
3413 reg = <0x0 0x15000000 2104 reg = <0x0 0x15000000 0x0 0x100000>;
3414 #iommu-cells = <2>; 2105 #iommu-cells = <2>;
3415 #global-interrupts = 2106 #global-interrupts = <2>;
3416 dma-coherent; <<
3417 2107
3418 interrupts = <GIC_SPI 2108 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
3419 <GIC_SPI 2109 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
3420 <GIC_SPI 2110 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
3421 <GIC_SPI 2111 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
3422 <GIC_SPI 2112 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
3423 <GIC_SPI 2113 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
3424 <GIC_SPI 2114 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
3425 <GIC_SPI 2115 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
3426 <GIC_SPI 2116 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
3427 <GIC_SPI 2117 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
3428 <GIC_SPI 2118 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
3429 <GIC_SPI 2119 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
3430 <GIC_SPI 2120 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
3431 <GIC_SPI 2121 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
3432 <GIC_SPI 2122 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
3433 <GIC_SPI 2123 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
3434 <GIC_SPI 2124 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
3435 <GIC_SPI 2125 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
3436 <GIC_SPI 2126 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
3437 <GIC_SPI 2127 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
3438 <GIC_SPI 2128 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
3439 <GIC_SPI 2129 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
3440 <GIC_SPI 2130 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
3441 <GIC_SPI 2131 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
3442 <GIC_SPI 2132 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
3443 <GIC_SPI 2133 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
3444 <GIC_SPI 2134 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
3445 <GIC_SPI 2135 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
3446 <GIC_SPI 2136 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
3447 <GIC_SPI 2137 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
3448 <GIC_SPI 2138 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
3449 <GIC_SPI 2139 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
3450 <GIC_SPI 2140 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
3451 <GIC_SPI 2141 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
3452 <GIC_SPI 2142 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
3453 <GIC_SPI 2143 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
3454 <GIC_SPI 2144 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
3455 <GIC_SPI 2145 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
3456 <GIC_SPI 2146 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
3457 <GIC_SPI 2147 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
3458 <GIC_SPI 2148 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
3459 <GIC_SPI 2149 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
3460 <GIC_SPI 2150 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
3461 <GIC_SPI 2151 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
3462 <GIC_SPI 2152 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
3463 <GIC_SPI 2153 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
3464 <GIC_SPI 2154 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
3465 <GIC_SPI 2155 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
3466 <GIC_SPI 2156 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
3467 <GIC_SPI 2157 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
3468 <GIC_SPI 2158 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
3469 <GIC_SPI 2159 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
3470 <GIC_SPI 2160 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
3471 <GIC_SPI 2161 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
3472 <GIC_SPI 2162 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
3473 <GIC_SPI 2163 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
3474 <GIC_SPI 2164 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
3475 <GIC_SPI 2165 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
3476 <GIC_SPI 2166 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
3477 <GIC_SPI 2167 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
3478 <GIC_SPI 2168 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
3479 <GIC_SPI 2169 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
3480 <GIC_SPI 2170 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
3481 <GIC_SPI 2171 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
3482 <GIC_SPI 2172 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
3483 <GIC_SPI 2173 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
3484 <GIC_SPI 2174 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
3485 <GIC_SPI 2175 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
3486 <GIC_SPI 2176 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
3487 <GIC_SPI 2177 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
3488 <GIC_SPI 2178 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
3489 <GIC_SPI 2179 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
3490 <GIC_SPI 2180 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
3491 <GIC_SPI 2181 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
3492 <GIC_SPI 2182 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
3493 <GIC_SPI 2183 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
3494 <GIC_SPI 2184 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
3495 <GIC_SPI 2185 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
3496 <GIC_SPI 2186 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
3497 <GIC_SPI 2187 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
3498 <GIC_SPI 2188 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
3499 <GIC_SPI 2189 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>,
3500 <GIC_SPI 2190 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
3501 <GIC_SPI 2191 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
3502 <GIC_SPI 2192 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
3503 <GIC_SPI 2193 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
3504 <GIC_SPI 2194 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
3505 <GIC_SPI 2195 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
3506 <GIC_SPI 2196 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
3507 <GIC_SPI 2197 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
3508 <GIC_SPI 2198 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
3509 <GIC_SPI 2199 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
3510 <GIC_SPI 2200 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
3511 <GIC_SPI 2201 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
3512 <GIC_SPI 2202 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
3513 <GIC_SPI 2203 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
3514 <GIC_SPI 2204 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
3515 <GIC_SPI 2205 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
3516 <GIC_SPI 2206 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
3517 <GIC_SPI 2207 <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>,
3518 <GIC_SPI 2208 <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>,
3519 <GIC_SPI 2209 <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>,
3520 <GIC_SPI 2210 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
3521 <GIC_SPI 2211 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
3522 <GIC_SPI 2212 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
3523 <GIC_SPI 2213 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>,
3524 <GIC_SPI 2214 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>,
3525 <GIC_SPI 2215 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>,
3526 <GIC_SPI 2216 <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>,
3527 <GIC_SPI 2217 <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>,
3528 <GIC_SPI 2218 <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>,
3529 <GIC_SPI 2219 <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>,
3530 <GIC_SPI 2220 <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>,
3531 <GIC_SPI 2221 <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>,
3532 <GIC_SPI 2222 <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>,
3533 <GIC_SPI 2223 <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>,
3534 <GIC_SPI 2224 <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>,
3535 <GIC_SPI 2225 <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>,
3536 <GIC_SPI 2226 <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>,
3537 <GIC_SPI 2227 <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>,
3538 <GIC_SPI 2228 <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>,
3539 <GIC_SPI 2229 <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>,
3540 <GIC_SPI 2230 <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>,
3541 <GIC_SPI 2231 <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>,
3542 <GIC_SPI 2232 <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>,
3543 <GIC_SPI 2233 <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>,
3544 <GIC_SPI 2234 <GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>,
3545 <GIC_SPI 2235 <GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>,
3546 <GIC_SPI 2236 <GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>,
3547 <GIC_SPI 2237 <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>;
3548 }; 2238 };
3549 2239
3550 pcie_smmu: iommu@15200000 { 2240 pcie_smmu: iommu@15200000 {
3551 compatible = "qcom,sa 2241 compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500";
3552 reg = <0x0 0x15200000 2242 reg = <0x0 0x15200000 0x0 0x80000>;
3553 #iommu-cells = <2>; 2243 #iommu-cells = <2>;
3554 #global-interrupts = 2244 #global-interrupts = <2>;
3555 dma-coherent; <<
3556 2245
3557 interrupts = <GIC_SPI 2246 interrupts = <GIC_SPI 920 IRQ_TYPE_LEVEL_HIGH>,
3558 <GIC_SPI 2247 <GIC_SPI 921 IRQ_TYPE_LEVEL_HIGH>,
3559 <GIC_SPI 2248 <GIC_SPI 925 IRQ_TYPE_LEVEL_HIGH>,
3560 <GIC_SPI 2249 <GIC_SPI 926 IRQ_TYPE_LEVEL_HIGH>,
3561 <GIC_SPI 2250 <GIC_SPI 927 IRQ_TYPE_LEVEL_HIGH>,
3562 <GIC_SPI 2251 <GIC_SPI 928 IRQ_TYPE_LEVEL_HIGH>,
3563 <GIC_SPI 2252 <GIC_SPI 950 IRQ_TYPE_LEVEL_HIGH>,
3564 <GIC_SPI 2253 <GIC_SPI 951 IRQ_TYPE_LEVEL_HIGH>,
3565 <GIC_SPI 2254 <GIC_SPI 952 IRQ_TYPE_LEVEL_HIGH>,
3566 <GIC_SPI 2255 <GIC_SPI 953 IRQ_TYPE_LEVEL_HIGH>,
3567 <GIC_SPI 2256 <GIC_SPI 954 IRQ_TYPE_LEVEL_HIGH>,
3568 <GIC_SPI 2257 <GIC_SPI 955 IRQ_TYPE_LEVEL_HIGH>,
3569 <GIC_SPI 2258 <GIC_SPI 956 IRQ_TYPE_LEVEL_HIGH>,
3570 <GIC_SPI 2259 <GIC_SPI 957 IRQ_TYPE_LEVEL_HIGH>,
3571 <GIC_SPI 2260 <GIC_SPI 958 IRQ_TYPE_LEVEL_HIGH>,
3572 <GIC_SPI 2261 <GIC_SPI 885 IRQ_TYPE_LEVEL_HIGH>,
3573 <GIC_SPI 2262 <GIC_SPI 886 IRQ_TYPE_LEVEL_HIGH>,
3574 <GIC_SPI 2263 <GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>,
3575 <GIC_SPI 2264 <GIC_SPI 888 IRQ_TYPE_LEVEL_HIGH>,
3576 <GIC_SPI 2265 <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>,
3577 <GIC_SPI 2266 <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>,
3578 <GIC_SPI 2267 <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>,
3579 <GIC_SPI 2268 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
3580 <GIC_SPI 2269 <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
3581 <GIC_SPI 2270 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
3582 <GIC_SPI 2271 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
3583 <GIC_SPI 2272 <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>,
3584 <GIC_SPI 2273 <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>,
3585 <GIC_SPI 2274 <GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>,
3586 <GIC_SPI 2275 <GIC_SPI 843 IRQ_TYPE_LEVEL_HIGH>,
3587 <GIC_SPI 2276 <GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>,
3588 <GIC_SPI 2277 <GIC_SPI 845 IRQ_TYPE_LEVEL_HIGH>,
3589 <GIC_SPI 2278 <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>,
3590 <GIC_SPI 2279 <GIC_SPI 847 IRQ_TYPE_LEVEL_HIGH>,
3591 <GIC_SPI 2280 <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>,
3592 <GIC_SPI 2281 <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>,
3593 <GIC_SPI 2282 <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>,
3594 <GIC_SPI 2283 <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>,
3595 <GIC_SPI 2284 <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>,
3596 <GIC_SPI 2285 <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>,
3597 <GIC_SPI 2286 <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>,
3598 <GIC_SPI 2287 <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>,
3599 <GIC_SPI 2288 <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>,
3600 <GIC_SPI 2289 <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>,
3601 <GIC_SPI 2290 <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>,
3602 <GIC_SPI 2291 <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>,
3603 <GIC_SPI 2292 <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>,
3604 <GIC_SPI 2293 <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>,
3605 <GIC_SPI 2294 <GIC_SPI 814 IRQ_TYPE_LEVEL_HIGH>,
3606 <GIC_SPI 2295 <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>,
3607 <GIC_SPI 2296 <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>,
3608 <GIC_SPI 2297 <GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>,
3609 <GIC_SPI 2298 <GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>,
3610 <GIC_SPI 2299 <GIC_SPI 854 IRQ_TYPE_LEVEL_HIGH>,
3611 <GIC_SPI 2300 <GIC_SPI 855 IRQ_TYPE_LEVEL_HIGH>,
3612 <GIC_SPI 2301 <GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>,
3613 <GIC_SPI 2302 <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>,
3614 <GIC_SPI 2303 <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>,
3615 <GIC_SPI 2304 <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>,
3616 <GIC_SPI 2305 <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>,
3617 <GIC_SPI 2306 <GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>,
3618 <GIC_SPI 2307 <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>,
3619 <GIC_SPI 2308 <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>,
3620 <GIC_SPI 2309 <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>,
3621 <GIC_SPI 2310 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
3622 <GIC_SPI 2311 <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>;
3623 }; 2312 };
3624 2313
3625 intc: interrupt-controller@17 2314 intc: interrupt-controller@17a00000 {
3626 compatible = "arm,gic 2315 compatible = "arm,gic-v3";
3627 reg = <0x0 0x17a00000 2316 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
3628 <0x0 0x17a60000 2317 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
3629 interrupt-controller; 2318 interrupt-controller;
3630 #interrupt-cells = <3 2319 #interrupt-cells = <3>;
3631 interrupts = <GIC_PPI 2320 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3632 #redistributor-region 2321 #redistributor-regions = <1>;
3633 redistributor-stride 2322 redistributor-stride = <0x0 0x20000>;
3634 }; 2323 };
3635 2324
3636 watchdog@17c10000 { 2325 watchdog@17c10000 {
3637 compatible = "qcom,ap 2326 compatible = "qcom,apss-wdt-sa8775p", "qcom,kpss-wdt";
3638 reg = <0x0 0x17c10000 2327 reg = <0x0 0x17c10000 0x0 0x1000>;
3639 clocks = <&sleep_clk> 2328 clocks = <&sleep_clk>;
3640 interrupts = <GIC_SPI 2329 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
3641 }; 2330 };
3642 2331
3643 memtimer: timer@17c20000 { 2332 memtimer: timer@17c20000 {
3644 compatible = "arm,arm 2333 compatible = "arm,armv7-timer-mem";
3645 reg = <0x0 0x17c20000 2334 reg = <0x0 0x17c20000 0x0 0x1000>;
3646 ranges = <0x0 0x0 0x0 2335 ranges = <0x0 0x0 0x0 0x20000000>;
3647 #address-cells = <1>; 2336 #address-cells = <1>;
3648 #size-cells = <1>; 2337 #size-cells = <1>;
3649 2338
3650 frame@17c21000 { 2339 frame@17c21000 {
3651 reg = <0x17c2 2340 reg = <0x17c21000 0x1000>,
3652 <0x17c2 2341 <0x17c22000 0x1000>;
3653 interrupts = 2342 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
3654 2343 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
3655 frame-number 2344 frame-number = <0>;
3656 }; 2345 };
3657 2346
3658 frame@17c23000 { 2347 frame@17c23000 {
3659 reg = <0x17c2 2348 reg = <0x17c23000 0x1000>;
3660 interrupts = 2349 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
3661 frame-number 2350 frame-number = <1>;
3662 status = "dis 2351 status = "disabled";
3663 }; 2352 };
3664 2353
3665 frame@17c25000 { 2354 frame@17c25000 {
3666 reg = <0x17c2 2355 reg = <0x17c25000 0x1000>;
3667 interrupts = 2356 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
3668 frame-number 2357 frame-number = <2>;
3669 status = "dis 2358 status = "disabled";
3670 }; 2359 };
3671 2360
3672 frame@17c27000 { 2361 frame@17c27000 {
3673 reg = <0x17c2 2362 reg = <0x17c27000 0x1000>;
3674 interrupts = 2363 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3675 frame-number 2364 frame-number = <3>;
3676 status = "dis 2365 status = "disabled";
3677 }; 2366 };
3678 2367
3679 frame@17c29000 { 2368 frame@17c29000 {
3680 reg = <0x17c2 2369 reg = <0x17c29000 0x1000>;
3681 interrupts = 2370 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3682 frame-number 2371 frame-number = <4>;
3683 status = "dis 2372 status = "disabled";
3684 }; 2373 };
3685 2374
3686 frame@17c2b000 { 2375 frame@17c2b000 {
3687 reg = <0x17c2 2376 reg = <0x17c2b000 0x1000>;
3688 interrupts = 2377 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3689 frame-number 2378 frame-number = <5>;
3690 status = "dis 2379 status = "disabled";
3691 }; 2380 };
3692 2381
3693 frame@17c2d000 { 2382 frame@17c2d000 {
3694 reg = <0x17c2 2383 reg = <0x17c2d000 0x1000>;
3695 interrupts = 2384 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
3696 frame-number 2385 frame-number = <6>;
3697 status = "dis 2386 status = "disabled";
3698 }; 2387 };
3699 }; 2388 };
3700 2389
3701 apps_rsc: rsc@18200000 { 2390 apps_rsc: rsc@18200000 {
3702 compatible = "qcom,rp 2391 compatible = "qcom,rpmh-rsc";
3703 reg = <0x0 0x18200000 2392 reg = <0x0 0x18200000 0x0 0x10000>,
3704 <0x0 0x18210000 2393 <0x0 0x18210000 0x0 0x10000>,
3705 <0x0 0x18220000 2394 <0x0 0x18220000 0x0 0x10000>;
3706 reg-names = "drv-0", 2395 reg-names = "drv-0", "drv-1", "drv-2";
3707 interrupts = <GIC_SPI 2396 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
3708 <GIC_SPI 4 IRQ_ 2397 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
3709 <GIC_SPI 5 IRQ_ 2398 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
3710 qcom,tcs-offset = <0x 2399 qcom,tcs-offset = <0xd00>;
3711 qcom,drv-id = <2>; 2400 qcom,drv-id = <2>;
3712 qcom,tcs-config = <AC 2401 qcom,tcs-config = <ACTIVE_TCS 2>,
3713 <SL 2402 <SLEEP_TCS 3>,
3714 <WA 2403 <WAKE_TCS 3>,
3715 <CO 2404 <CONTROL_TCS 0>;
3716 label = "apps_rsc"; 2405 label = "apps_rsc";
3717 2406
3718 apps_bcm_voter: bcm-v 2407 apps_bcm_voter: bcm-voter {
3719 compatible = 2408 compatible = "qcom,bcm-voter";
3720 }; 2409 };
3721 2410
3722 rpmhcc: clock-control 2411 rpmhcc: clock-controller {
3723 compatible = 2412 compatible = "qcom,sa8775p-rpmh-clk";
3724 #clock-cells 2413 #clock-cells = <1>;
3725 clock-names = 2414 clock-names = "xo";
3726 clocks = <&xo 2415 clocks = <&xo_board_clk>;
3727 }; 2416 };
3728 2417
3729 rpmhpd: power-control 2418 rpmhpd: power-controller {
3730 compatible = 2419 compatible = "qcom,sa8775p-rpmhpd";
3731 #power-domain 2420 #power-domain-cells = <1>;
3732 operating-poi 2421 operating-points-v2 = <&rpmhpd_opp_table>;
3733 2422
3734 rpmhpd_opp_ta 2423 rpmhpd_opp_table: opp-table {
3735 compa 2424 compatible = "operating-points-v2";
3736 2425
3737 rpmhp 2426 rpmhpd_opp_ret: opp-0 {
3738 2427 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3739 }; 2428 };
3740 2429
3741 rpmhp 2430 rpmhpd_opp_min_svs: opp-1 {
3742 2431 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3743 }; 2432 };
3744 2433
3745 rpmhp 2434 rpmhpd_opp_low_svs: opp2 {
3746 2435 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3747 }; 2436 };
3748 2437
3749 rpmhp 2438 rpmhpd_opp_svs: opp3 {
3750 2439 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3751 }; 2440 };
3752 2441
3753 rpmhp 2442 rpmhpd_opp_svs_l1: opp-4 {
3754 2443 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3755 }; 2444 };
3756 2445
3757 rpmhp 2446 rpmhpd_opp_nom: opp-5 {
3758 2447 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3759 }; 2448 };
3760 2449
3761 rpmhp 2450 rpmhpd_opp_nom_l1: opp-6 {
3762 2451 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3763 }; 2452 };
3764 2453
3765 rpmhp 2454 rpmhpd_opp_nom_l2: opp-7 {
3766 2455 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3767 }; 2456 };
3768 2457
3769 rpmhp 2458 rpmhpd_opp_turbo: opp-8 {
3770 2459 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3771 }; 2460 };
3772 2461
3773 rpmhp 2462 rpmhpd_opp_turbo_l1: opp-9 {
3774 2463 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3775 }; 2464 };
3776 }; 2465 };
3777 }; 2466 };
3778 }; 2467 };
3779 2468
3780 cpufreq_hw: cpufreq@18591000 2469 cpufreq_hw: cpufreq@18591000 {
3781 compatible = "qcom,sa 2470 compatible = "qcom,sa8775p-cpufreq-epss",
3782 "qcom,cp 2471 "qcom,cpufreq-epss";
3783 reg = <0x0 0x18591000 2472 reg = <0x0 0x18591000 0x0 0x1000>,
3784 <0x0 0x18593000 2473 <0x0 0x18593000 0x0 0x1000>;
3785 reg-names = "freq-dom 2474 reg-names = "freq-domain0", "freq-domain1";
3786 2475
3787 clocks = <&rpmhcc RPM 2476 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
3788 clock-names = "xo", " 2477 clock-names = "xo", "alternate";
3789 2478
3790 #freq-domain-cells = 2479 #freq-domain-cells = <1>;
3791 }; 2480 };
3792 2481
3793 remoteproc_gpdsp0: remoteproc <<
3794 compatible = "qcom,sa <<
3795 reg = <0x0 0x20c00000 <<
3796 <<
3797 interrupts-extended = <<
3798 <<
3799 <<
3800 <<
3801 <<
3802 interrupt-names = "wd <<
3803 "ha <<
3804 <<
3805 clocks = <&rpmhcc RPM <<
3806 clock-names = "xo"; <<
3807 <<
3808 power-domains = <&rpm <<
3809 <&rpm <<
3810 power-domain-names = <<
3811 <<
3812 interconnects = <&gpd <<
3813 &con <<
3814 <<
3815 memory-region = <&pil <<
3816 <<
3817 qcom,qmp = <&aoss_qmp <<
3818 <<
3819 qcom,smem-states = <& <<
3820 qcom,smem-state-names <<
3821 <<
3822 status = "disabled"; <<
3823 <<
3824 glink-edge { <<
3825 interrupts-ex <<
3826 <<
3827 <<
3828 mboxes = <&ip <<
3829 <<
3830 <<
3831 label = "gpds <<
3832 qcom,remote-p <<
3833 }; <<
3834 }; <<
3835 <<
3836 remoteproc_gpdsp1: remoteproc <<
3837 compatible = "qcom,sa <<
3838 reg = <0x0 0x21c00000 <<
3839 <<
3840 interrupts-extended = <<
3841 <<
3842 <<
3843 <<
3844 <<
3845 interrupt-names = "wd <<
3846 "ha <<
3847 <<
3848 clocks = <&rpmhcc RPM <<
3849 clock-names = "xo"; <<
3850 <<
3851 power-domains = <&rpm <<
3852 <&rpm <<
3853 power-domain-names = <<
3854 <<
3855 interconnects = <&gpd <<
3856 &con <<
3857 <<
3858 memory-region = <&pil <<
3859 <<
3860 qcom,qmp = <&aoss_qmp <<
3861 <<
3862 qcom,smem-states = <& <<
3863 qcom,smem-state-names <<
3864 <<
3865 status = "disabled"; <<
3866 <<
3867 glink-edge { <<
3868 interrupts-ex <<
3869 <<
3870 <<
3871 mboxes = <&ip <<
3872 <<
3873 <<
3874 label = "gpds <<
3875 qcom,remote-p <<
3876 }; <<
3877 }; <<
3878 <<
3879 ethernet1: ethernet@23000000 2482 ethernet1: ethernet@23000000 {
3880 compatible = "qcom,sa 2483 compatible = "qcom,sa8775p-ethqos";
3881 reg = <0x0 0x23000000 2484 reg = <0x0 0x23000000 0x0 0x10000>,
3882 <0x0 0x23016000 2485 <0x0 0x23016000 0x0 0x100>;
3883 reg-names = "stmmacet 2486 reg-names = "stmmaceth", "rgmii";
3884 2487
3885 interrupts = <GIC_SPI 2488 interrupts = <GIC_SPI 929 IRQ_TYPE_LEVEL_HIGH>,
3886 <GIC_SPI 2489 <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>;
3887 interrupt-names = "ma 2490 interrupt-names = "macirq", "sfty";
3888 2491
3889 clocks = <&gcc GCC_EM 2492 clocks = <&gcc GCC_EMAC1_AXI_CLK>,
3890 <&gcc GCC_EM 2493 <&gcc GCC_EMAC1_SLV_AHB_CLK>,
3891 <&gcc GCC_EM 2494 <&gcc GCC_EMAC1_PTP_CLK>,
3892 <&gcc GCC_EM 2495 <&gcc GCC_EMAC1_PHY_AUX_CLK>;
3893 clock-names = "stmmac 2496 clock-names = "stmmaceth",
3894 "pclk", 2497 "pclk",
3895 "ptp_re 2498 "ptp_ref",
3896 "phyaux 2499 "phyaux";
3897 2500
3898 interconnects = <&agg <<
3899 &mc_ <<
3900 <&gem <<
3901 &con <<
3902 interconnect-names = <<
3903 <<
3904 power-domains = <&gcc 2501 power-domains = <&gcc EMAC1_GDSC>;
3905 2502
3906 phys = <&serdes1>; 2503 phys = <&serdes1>;
3907 phy-names = "serdes"; 2504 phy-names = "serdes";
3908 2505
3909 iommus = <&apps_smmu 2506 iommus = <&apps_smmu 0x140 0xf>;
3910 dma-coherent; <<
3911 2507
3912 snps,tso; 2508 snps,tso;
3913 snps,pbl = <32>; 2509 snps,pbl = <32>;
3914 rx-fifo-depth = <1638 2510 rx-fifo-depth = <16384>;
3915 tx-fifo-depth = <1638 2511 tx-fifo-depth = <16384>;
3916 2512
3917 status = "disabled"; 2513 status = "disabled";
3918 }; 2514 };
3919 2515
3920 ethernet0: ethernet@23040000 2516 ethernet0: ethernet@23040000 {
3921 compatible = "qcom,sa 2517 compatible = "qcom,sa8775p-ethqos";
3922 reg = <0x0 0x23040000 2518 reg = <0x0 0x23040000 0x0 0x10000>,
3923 <0x0 0x23056000 2519 <0x0 0x23056000 0x0 0x100>;
3924 reg-names = "stmmacet 2520 reg-names = "stmmaceth", "rgmii";
3925 2521
3926 interrupts = <GIC_SPI 2522 interrupts = <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>,
3927 <GIC_SPI 2523 <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>;
3928 interrupt-names = "ma 2524 interrupt-names = "macirq", "sfty";
3929 2525
3930 clocks = <&gcc GCC_EM 2526 clocks = <&gcc GCC_EMAC0_AXI_CLK>,
3931 <&gcc GCC_EM 2527 <&gcc GCC_EMAC0_SLV_AHB_CLK>,
3932 <&gcc GCC_EM 2528 <&gcc GCC_EMAC0_PTP_CLK>,
3933 <&gcc GCC_EM 2529 <&gcc GCC_EMAC0_PHY_AUX_CLK>;
3934 clock-names = "stmmac 2530 clock-names = "stmmaceth",
3935 "pclk", 2531 "pclk",
3936 "ptp_re 2532 "ptp_ref",
3937 "phyaux 2533 "phyaux";
3938 2534
3939 interconnects = <&agg <<
3940 &mc_ <<
3941 <&gem <<
3942 &con <<
3943 interconnect-names = <<
3944 <<
3945 power-domains = <&gcc 2535 power-domains = <&gcc EMAC0_GDSC>;
3946 2536
3947 phys = <&serdes0>; 2537 phys = <&serdes0>;
3948 phy-names = "serdes"; 2538 phy-names = "serdes";
3949 2539
3950 iommus = <&apps_smmu 2540 iommus = <&apps_smmu 0x120 0xf>;
3951 dma-coherent; <<
3952 2541
3953 snps,tso; 2542 snps,tso;
3954 snps,pbl = <32>; 2543 snps,pbl = <32>;
3955 rx-fifo-depth = <1638 2544 rx-fifo-depth = <16384>;
3956 tx-fifo-depth = <1638 2545 tx-fifo-depth = <16384>;
3957 2546
3958 status = "disabled"; 2547 status = "disabled";
3959 }; 2548 };
3960 <<
3961 remoteproc_cdsp0: remoteproc@ <<
3962 compatible = "qcom,sa <<
3963 reg = <0x0 0x26300000 <<
3964 <<
3965 interrupts-extended = <<
3966 <<
3967 <<
3968 <<
3969 <<
3970 interrupt-names = "wd <<
3971 "ha <<
3972 <<
3973 clocks = <&rpmhcc RPM <<
3974 clock-names = "xo"; <<
3975 <<
3976 power-domains = <&rpm <<
3977 <&rpm <<
3978 <&rpm <<
3979 power-domain-names = <<
3980 <<
3981 interconnects = <&nsp <<
3982 &mc_ <<
3983 <<
3984 memory-region = <&pil <<
3985 <<
3986 qcom,qmp = <&aoss_qmp <<
3987 <<
3988 qcom,smem-states = <& <<
3989 qcom,smem-state-names <<
3990 <<
3991 status = "disabled"; <<
3992 <<
3993 glink-edge { <<
3994 interrupts-ex <<
3995 <<
3996 <<
3997 mboxes = <&ip <<
3998 <<
3999 <<
4000 label = "cdsp <<
4001 qcom,remote-p <<
4002 <<
4003 fastrpc { <<
4004 compa <<
4005 qcom, <<
4006 label <<
4007 #addr <<
4008 #size <<
4009 <<
4010 compu <<
4011 <<
4012 <<
4013 <<
4014 <<
4015 <<
4016 <<
4017 <<
4018 <<
4019 <<
4020 <<
4021 <<
4022 <<
4023 <<
4024 }; <<
4025 <<
4026 compu <<
4027 <<
4028 <<
4029 <<
4030 <<
4031 <<
4032 <<
4033 <<
4034 <<
4035 <<
4036 <<
4037 <<
4038 <<
4039 <<
4040 }; <<
4041 <<
4042 compu <<
4043 <<
4044 <<
4045 <<
4046 <<
4047 <<
4048 <<
4049 <<
4050 <<
4051 <<
4052 <<
4053 <<
4054 <<
4055 <<
4056 }; <<
4057 <<
4058 compu <<
4059 <<
4060 <<
4061 <<
4062 <<
4063 <<
4064 <<
4065 <<
4066 <<
4067 <<
4068 <<
4069 <<
4070 <<
4071 <<
4072 }; <<
4073 <<
4074 compu <<
4075 <<
4076 <<
4077 <<
4078 <<
4079 <<
4080 <<
4081 <<
4082 <<
4083 <<
4084 <<
4085 <<
4086 <<
4087 <<
4088 }; <<
4089 <<
4090 compu <<
4091 <<
4092 <<
4093 <<
4094 <<
4095 <<
4096 <<
4097 <<
4098 <<
4099 <<
4100 <<
4101 <<
4102 <<
4103 <<
4104 }; <<
4105 <<
4106 compu <<
4107 <<
4108 <<
4109 <<
4110 <<
4111 <<
4112 <<
4113 <<
4114 <<
4115 <<
4116 <<
4117 <<
4118 <<
4119 <<
4120 }; <<
4121 <<
4122 compu <<
4123 <<
4124 <<
4125 <<
4126 <<
4127 <<
4128 <<
4129 <<
4130 <<
4131 <<
4132 <<
4133 <<
4134 <<
4135 <<
4136 }; <<
4137 <<
4138 compu <<
4139 <<
4140 <<
4141 <<
4142 <<
4143 <<
4144 <<
4145 <<
4146 <<
4147 <<
4148 <<
4149 <<
4150 <<
4151 <<
4152 }; <<
4153 <<
4154 compu <<
4155 <<
4156 <<
4157 <<
4158 <<
4159 <<
4160 <<
4161 <<
4162 <<
4163 <<
4164 <<
4165 <<
4166 <<
4167 <<
4168 }; <<
4169 <<
4170 compu <<
4171 <<
4172 <<
4173 <<
4174 <<
4175 <<
4176 <<
4177 <<
4178 <<
4179 <<
4180 <<
4181 <<
4182 <<
4183 <<
4184 }; <<
4185 }; <<
4186 }; <<
4187 }; <<
4188 <<
4189 remoteproc_cdsp1: remoteproc@ <<
4190 compatible = "qcom,sa <<
4191 reg = <0x0 0x2A300000 <<
4192 <<
4193 interrupts-extended = <<
4194 <<
4195 <<
4196 <<
4197 <<
4198 interrupt-names = "wd <<
4199 "ha <<
4200 <<
4201 clocks = <&rpmhcc RPM <<
4202 clock-names = "xo"; <<
4203 <<
4204 power-domains = <&rpm <<
4205 <&rpm <<
4206 <&rpm <<
4207 power-domain-names = <<
4208 <<
4209 interconnects = <&nsp <<
4210 &mc_ <<
4211 <<
4212 memory-region = <&pil <<
4213 <<
4214 qcom,qmp = <&aoss_qmp <<
4215 <<
4216 qcom,smem-states = <& <<
4217 qcom,smem-state-names <<
4218 <<
4219 status = "disabled"; <<
4220 <<
4221 glink-edge { <<
4222 interrupts-ex <<
4223 <<
4224 <<
4225 mboxes = <&ip <<
4226 <<
4227 <<
4228 label = "cdsp <<
4229 qcom,remote-p <<
4230 <<
4231 fastrpc { <<
4232 compa <<
4233 qcom, <<
4234 label <<
4235 #addr <<
4236 #size <<
4237 <<
4238 compu <<
4239 <<
4240 <<
4241 <<
4242 <<
4243 <<
4244 <<
4245 <<
4246 <<
4247 <<
4248 <<
4249 <<
4250 <<
4251 <<
4252 }; <<
4253 <<
4254 compu <<
4255 <<
4256 <<
4257 <<
4258 <<
4259 <<
4260 <<
4261 <<
4262 <<
4263 <<
4264 <<
4265 <<
4266 <<
4267 <<
4268 }; <<
4269 <<
4270 compu <<
4271 <<
4272 <<
4273 <<
4274 <<
4275 <<
4276 <<
4277 <<
4278 <<
4279 <<
4280 <<
4281 <<
4282 <<
4283 <<
4284 }; <<
4285 <<
4286 compu <<
4287 <<
4288 <<
4289 <<
4290 <<
4291 <<
4292 <<
4293 <<
4294 <<
4295 <<
4296 <<
4297 <<
4298 <<
4299 <<
4300 }; <<
4301 <<
4302 compu <<
4303 <<
4304 <<
4305 <<
4306 <<
4307 <<
4308 <<
4309 <<
4310 <<
4311 <<
4312 <<
4313 <<
4314 <<
4315 <<
4316 }; <<
4317 <<
4318 compu <<
4319 <<
4320 <<
4321 <<
4322 <<
4323 <<
4324 <<
4325 <<
4326 <<
4327 <<
4328 <<
4329 <<
4330 <<
4331 <<
4332 }; <<
4333 <<
4334 compu <<
4335 <<
4336 <<
4337 <<
4338 <<
4339 <<
4340 <<
4341 <<
4342 <<
4343 <<
4344 <<
4345 <<
4346 <<
4347 <<
4348 }; <<
4349 <<
4350 compu <<
4351 <<
4352 <<
4353 <<
4354 <<
4355 <<
4356 <<
4357 <<
4358 <<
4359 <<
4360 <<
4361 <<
4362 <<
4363 <<
4364 }; <<
4365 <<
4366 compu <<
4367 <<
4368 <<
4369 <<
4370 <<
4371 <<
4372 <<
4373 <<
4374 <<
4375 <<
4376 <<
4377 <<
4378 <<
4379 <<
4380 }; <<
4381 <<
4382 compu <<
4383 <<
4384 <<
4385 <<
4386 <<
4387 <<
4388 <<
4389 <<
4390 <<
4391 <<
4392 <<
4393 <<
4394 <<
4395 <<
4396 }; <<
4397 <<
4398 compu <<
4399 <<
4400 <<
4401 <<
4402 <<
4403 <<
4404 <<
4405 <<
4406 <<
4407 <<
4408 <<
4409 <<
4410 <<
4411 <<
4412 }; <<
4413 <<
4414 compu <<
4415 <<
4416 <<
4417 <<
4418 <<
4419 <<
4420 <<
4421 <<
4422 <<
4423 <<
4424 <<
4425 <<
4426 <<
4427 <<
4428 }; <<
4429 <<
4430 compu <<
4431 <<
4432 <<
4433 <<
4434 <<
4435 <<
4436 <<
4437 <<
4438 <<
4439 <<
4440 <<
4441 <<
4442 <<
4443 <<
4444 }; <<
4445 }; <<
4446 }; <<
4447 }; <<
4448 <<
4449 remoteproc_adsp: remoteproc@3 <<
4450 compatible = "qcom,sa <<
4451 reg = <0x0 0x30000000 <<
4452 <<
4453 interrupts-extended = <<
4454 <<
4455 <<
4456 <<
4457 <<
4458 interrupt-names = "wd <<
4459 "st <<
4460 <<
4461 clocks = <&rpmhcc RPM <<
4462 clock-names = "xo"; <<
4463 <<
4464 power-domains = <&rpm <<
4465 <&rpm <<
4466 power-domain-names = <<
4467 <<
4468 interconnects = <&lpa <<
4469 <<
4470 memory-region = <&pil <<
4471 <<
4472 qcom,qmp = <&aoss_qmp <<
4473 <<
4474 qcom,smem-states = <& <<
4475 qcom,smem-state-names <<
4476 <<
4477 status = "disabled"; <<
4478 <<
4479 remoteproc_adsp_glink <<
4480 interrupts-ex <<
4481 <<
4482 <<
4483 mboxes = <&ip <<
4484 <<
4485 <<
4486 label = "lpas <<
4487 qcom,remote-p <<
4488 <<
4489 fastrpc { <<
4490 compa <<
4491 qcom, <<
4492 label <<
4493 memor <<
4494 qcom, <<
4495 <<
4496 #addr <<
4497 #size <<
4498 <<
4499 compu <<
4500 <<
4501 <<
4502 <<
4503 <<
4504 }; <<
4505 <<
4506 compu <<
4507 <<
4508 <<
4509 <<
4510 <<
4511 }; <<
4512 <<
4513 compu <<
4514 <<
4515 <<
4516 <<
4517 <<
4518 <<
4519 }; <<
4520 }; <<
4521 }; <<
4522 }; <<
4523 }; 2549 };
4524 2550
4525 thermal-zones { 2551 thermal-zones {
4526 aoss-0-thermal { 2552 aoss-0-thermal {
>> 2553 polling-delay-passive = <0>;
>> 2554 polling-delay = <0>;
>> 2555
4527 thermal-sensors = <&t 2556 thermal-sensors = <&tsens0 0>;
4528 2557
4529 trips { 2558 trips {
4530 trip-point0 { 2559 trip-point0 {
4531 tempe 2560 temperature = <105000>;
4532 hyste 2561 hysteresis = <5000>;
4533 type 2562 type = "passive";
4534 }; 2563 };
4535 2564
4536 trip-point1 { 2565 trip-point1 {
4537 tempe 2566 temperature = <115000>;
4538 hyste 2567 hysteresis = <5000>;
4539 type 2568 type = "passive";
4540 }; 2569 };
4541 }; 2570 };
4542 }; 2571 };
4543 2572
4544 cpu-0-0-0-thermal { 2573 cpu-0-0-0-thermal {
4545 polling-delay-passive 2574 polling-delay-passive = <10>;
>> 2575 polling-delay = <0>;
4546 2576
4547 thermal-sensors = <&t 2577 thermal-sensors = <&tsens0 1>;
4548 2578
4549 trips { 2579 trips {
4550 trip-point0 { 2580 trip-point0 {
4551 tempe 2581 temperature = <105000>;
4552 hyste 2582 hysteresis = <5000>;
4553 type 2583 type = "passive";
4554 }; 2584 };
4555 2585
4556 trip-point1 { 2586 trip-point1 {
4557 tempe 2587 temperature = <115000>;
4558 hyste 2588 hysteresis = <5000>;
4559 type 2589 type = "passive";
4560 }; 2590 };
4561 }; 2591 };
4562 }; 2592 };
4563 2593
4564 cpu-0-1-0-thermal { 2594 cpu-0-1-0-thermal {
4565 polling-delay-passive 2595 polling-delay-passive = <10>;
>> 2596 polling-delay = <0>;
4566 2597
4567 thermal-sensors = <&t 2598 thermal-sensors = <&tsens0 2>;
4568 2599
4569 trips { 2600 trips {
4570 trip-point0 { 2601 trip-point0 {
4571 tempe 2602 temperature = <105000>;
4572 hyste 2603 hysteresis = <5000>;
4573 type 2604 type = "passive";
4574 }; 2605 };
4575 2606
4576 trip-point1 { 2607 trip-point1 {
4577 tempe 2608 temperature = <115000>;
4578 hyste 2609 hysteresis = <5000>;
4579 type 2610 type = "passive";
4580 }; 2611 };
4581 }; 2612 };
4582 }; 2613 };
4583 2614
4584 cpu-0-2-0-thermal { 2615 cpu-0-2-0-thermal {
4585 polling-delay-passive 2616 polling-delay-passive = <10>;
>> 2617 polling-delay = <0>;
4586 2618
4587 thermal-sensors = <&t 2619 thermal-sensors = <&tsens0 3>;
4588 2620
4589 trips { 2621 trips {
4590 trip-point0 { 2622 trip-point0 {
4591 tempe 2623 temperature = <105000>;
4592 hyste 2624 hysteresis = <5000>;
4593 type 2625 type = "passive";
4594 }; 2626 };
4595 2627
4596 trip-point1 { 2628 trip-point1 {
4597 tempe 2629 temperature = <115000>;
4598 hyste 2630 hysteresis = <5000>;
4599 type 2631 type = "passive";
4600 }; 2632 };
4601 }; 2633 };
4602 }; 2634 };
4603 2635
4604 cpu-0-3-0-thermal { 2636 cpu-0-3-0-thermal {
4605 polling-delay-passive 2637 polling-delay-passive = <10>;
>> 2638 polling-delay = <0>;
4606 2639
4607 thermal-sensors = <&t 2640 thermal-sensors = <&tsens0 4>;
4608 2641
4609 trips { 2642 trips {
4610 trip-point0 { 2643 trip-point0 {
4611 tempe 2644 temperature = <105000>;
4612 hyste 2645 hysteresis = <5000>;
4613 type 2646 type = "passive";
4614 }; 2647 };
4615 2648
4616 trip-point1 { 2649 trip-point1 {
4617 tempe 2650 temperature = <115000>;
4618 hyste 2651 hysteresis = <5000>;
4619 type 2652 type = "passive";
4620 }; 2653 };
4621 }; 2654 };
4622 }; 2655 };
4623 2656
4624 gpuss-0-thermal { 2657 gpuss-0-thermal {
4625 polling-delay-passive 2658 polling-delay-passive = <10>;
>> 2659 polling-delay = <0>;
4626 2660
4627 thermal-sensors = <&t 2661 thermal-sensors = <&tsens0 5>;
4628 2662
4629 trips { 2663 trips {
4630 trip-point0 { 2664 trip-point0 {
4631 tempe 2665 temperature = <105000>;
4632 hyste 2666 hysteresis = <5000>;
4633 type 2667 type = "passive";
4634 }; 2668 };
4635 2669
4636 trip-point1 { 2670 trip-point1 {
4637 tempe 2671 temperature = <115000>;
4638 hyste 2672 hysteresis = <5000>;
4639 type 2673 type = "passive";
4640 }; 2674 };
4641 }; 2675 };
4642 }; 2676 };
4643 2677
4644 gpuss-1-thermal { 2678 gpuss-1-thermal {
4645 polling-delay-passive 2679 polling-delay-passive = <10>;
>> 2680 polling-delay = <0>;
4646 2681
4647 thermal-sensors = <&t 2682 thermal-sensors = <&tsens0 6>;
4648 2683
4649 trips { 2684 trips {
4650 trip-point0 { 2685 trip-point0 {
4651 tempe 2686 temperature = <105000>;
4652 hyste 2687 hysteresis = <5000>;
4653 type 2688 type = "passive";
4654 }; 2689 };
4655 2690
4656 trip-point1 { 2691 trip-point1 {
4657 tempe 2692 temperature = <115000>;
4658 hyste 2693 hysteresis = <5000>;
4659 type 2694 type = "passive";
4660 }; 2695 };
4661 }; 2696 };
4662 }; 2697 };
4663 2698
4664 gpuss-2-thermal { 2699 gpuss-2-thermal {
4665 polling-delay-passive 2700 polling-delay-passive = <10>;
>> 2701 polling-delay = <0>;
4666 2702
4667 thermal-sensors = <&t 2703 thermal-sensors = <&tsens0 7>;
4668 2704
4669 trips { 2705 trips {
4670 trip-point0 { 2706 trip-point0 {
4671 tempe 2707 temperature = <105000>;
4672 hyste 2708 hysteresis = <5000>;
4673 type 2709 type = "passive";
4674 }; 2710 };
4675 2711
4676 trip-point1 { 2712 trip-point1 {
4677 tempe 2713 temperature = <115000>;
4678 hyste 2714 hysteresis = <5000>;
4679 type 2715 type = "passive";
4680 }; 2716 };
4681 }; 2717 };
4682 }; 2718 };
4683 2719
4684 audio-thermal { 2720 audio-thermal {
>> 2721 polling-delay-passive = <0>;
>> 2722 polling-delay = <0>;
>> 2723
4685 thermal-sensors = <&t 2724 thermal-sensors = <&tsens0 8>;
4686 2725
4687 trips { 2726 trips {
4688 trip-point0 { 2727 trip-point0 {
4689 tempe 2728 temperature = <105000>;
4690 hyste 2729 hysteresis = <5000>;
4691 type 2730 type = "passive";
4692 }; 2731 };
4693 2732
4694 trip-point1 { 2733 trip-point1 {
4695 tempe 2734 temperature = <115000>;
4696 hyste 2735 hysteresis = <5000>;
4697 type 2736 type = "passive";
4698 }; 2737 };
4699 }; 2738 };
4700 }; 2739 };
4701 2740
4702 camss-0-thermal { 2741 camss-0-thermal {
>> 2742 polling-delay-passive = <0>;
>> 2743 polling-delay = <0>;
>> 2744
4703 thermal-sensors = <&t 2745 thermal-sensors = <&tsens0 9>;
4704 2746
4705 trips { 2747 trips {
4706 trip-point0 { 2748 trip-point0 {
4707 tempe 2749 temperature = <105000>;
4708 hyste 2750 hysteresis = <5000>;
4709 type 2751 type = "passive";
4710 }; 2752 };
4711 2753
4712 trip-point1 { 2754 trip-point1 {
4713 tempe 2755 temperature = <115000>;
4714 hyste 2756 hysteresis = <5000>;
4715 type 2757 type = "passive";
4716 }; 2758 };
4717 }; 2759 };
4718 }; 2760 };
4719 2761
4720 pcie-0-thermal { 2762 pcie-0-thermal {
>> 2763 polling-delay-passive = <0>;
>> 2764 polling-delay = <0>;
>> 2765
4721 thermal-sensors = <&t 2766 thermal-sensors = <&tsens0 10>;
4722 2767
4723 trips { 2768 trips {
4724 trip-point0 { 2769 trip-point0 {
4725 tempe 2770 temperature = <105000>;
4726 hyste 2771 hysteresis = <5000>;
4727 type 2772 type = "passive";
4728 }; 2773 };
4729 2774
4730 trip-point1 { 2775 trip-point1 {
4731 tempe 2776 temperature = <115000>;
4732 hyste 2777 hysteresis = <5000>;
4733 type 2778 type = "passive";
4734 }; 2779 };
4735 }; 2780 };
4736 }; 2781 };
4737 2782
4738 cpuss-0-0-thermal { 2783 cpuss-0-0-thermal {
>> 2784 polling-delay-passive = <0>;
>> 2785 polling-delay = <0>;
>> 2786
4739 thermal-sensors = <&t 2787 thermal-sensors = <&tsens0 11>;
4740 2788
4741 trips { 2789 trips {
4742 trip-point0 { 2790 trip-point0 {
4743 tempe 2791 temperature = <105000>;
4744 hyste 2792 hysteresis = <5000>;
4745 type 2793 type = "passive";
4746 }; 2794 };
4747 2795
4748 trip-point1 { 2796 trip-point1 {
4749 tempe 2797 temperature = <115000>;
4750 hyste 2798 hysteresis = <5000>;
4751 type 2799 type = "passive";
4752 }; 2800 };
4753 }; 2801 };
4754 }; 2802 };
4755 2803
4756 aoss-1-thermal { 2804 aoss-1-thermal {
>> 2805 polling-delay-passive = <0>;
>> 2806 polling-delay = <0>;
>> 2807
4757 thermal-sensors = <&t 2808 thermal-sensors = <&tsens1 0>;
4758 2809
4759 trips { 2810 trips {
4760 trip-point0 { 2811 trip-point0 {
4761 tempe 2812 temperature = <105000>;
4762 hyste 2813 hysteresis = <5000>;
4763 type 2814 type = "passive";
4764 }; 2815 };
4765 2816
4766 trip-point1 { 2817 trip-point1 {
4767 tempe 2818 temperature = <115000>;
4768 hyste 2819 hysteresis = <5000>;
4769 type 2820 type = "passive";
4770 }; 2821 };
4771 }; 2822 };
4772 }; 2823 };
4773 2824
4774 cpu-0-0-1-thermal { 2825 cpu-0-0-1-thermal {
4775 polling-delay-passive 2826 polling-delay-passive = <10>;
>> 2827 polling-delay = <0>;
4776 2828
4777 thermal-sensors = <&t 2829 thermal-sensors = <&tsens1 1>;
4778 2830
4779 trips { 2831 trips {
4780 trip-point0 { 2832 trip-point0 {
4781 tempe 2833 temperature = <105000>;
4782 hyste 2834 hysteresis = <5000>;
4783 type 2835 type = "passive";
4784 }; 2836 };
4785 2837
4786 trip-point1 { 2838 trip-point1 {
4787 tempe 2839 temperature = <115000>;
4788 hyste 2840 hysteresis = <5000>;
4789 type 2841 type = "passive";
4790 }; 2842 };
4791 }; 2843 };
4792 }; 2844 };
4793 2845
4794 cpu-0-1-1-thermal { 2846 cpu-0-1-1-thermal {
4795 polling-delay-passive 2847 polling-delay-passive = <10>;
>> 2848 polling-delay = <0>;
4796 2849
4797 thermal-sensors = <&t 2850 thermal-sensors = <&tsens1 2>;
4798 2851
4799 trips { 2852 trips {
4800 trip-point0 { 2853 trip-point0 {
4801 tempe 2854 temperature = <105000>;
4802 hyste 2855 hysteresis = <5000>;
4803 type 2856 type = "passive";
4804 }; 2857 };
4805 2858
4806 trip-point1 { 2859 trip-point1 {
4807 tempe 2860 temperature = <115000>;
4808 hyste 2861 hysteresis = <5000>;
4809 type 2862 type = "passive";
4810 }; 2863 };
4811 }; 2864 };
4812 }; 2865 };
4813 2866
4814 cpu-0-2-1-thermal { 2867 cpu-0-2-1-thermal {
4815 polling-delay-passive 2868 polling-delay-passive = <10>;
>> 2869 polling-delay = <0>;
4816 2870
4817 thermal-sensors = <&t 2871 thermal-sensors = <&tsens1 3>;
4818 2872
4819 trips { 2873 trips {
4820 trip-point0 { 2874 trip-point0 {
4821 tempe 2875 temperature = <105000>;
4822 hyste 2876 hysteresis = <5000>;
4823 type 2877 type = "passive";
4824 }; 2878 };
4825 2879
4826 trip-point1 { 2880 trip-point1 {
4827 tempe 2881 temperature = <115000>;
4828 hyste 2882 hysteresis = <5000>;
4829 type 2883 type = "passive";
4830 }; 2884 };
4831 }; 2885 };
4832 }; 2886 };
4833 2887
4834 cpu-0-3-1-thermal { 2888 cpu-0-3-1-thermal {
4835 polling-delay-passive 2889 polling-delay-passive = <10>;
>> 2890 polling-delay = <0>;
4836 2891
4837 thermal-sensors = <&t 2892 thermal-sensors = <&tsens1 4>;
4838 2893
4839 trips { 2894 trips {
4840 trip-point0 { 2895 trip-point0 {
4841 tempe 2896 temperature = <105000>;
4842 hyste 2897 hysteresis = <5000>;
4843 type 2898 type = "passive";
4844 }; 2899 };
4845 2900
4846 trip-point1 { 2901 trip-point1 {
4847 tempe 2902 temperature = <115000>;
4848 hyste 2903 hysteresis = <5000>;
4849 type 2904 type = "passive";
4850 }; 2905 };
4851 }; 2906 };
4852 }; 2907 };
4853 2908
4854 gpuss-3-thermal { 2909 gpuss-3-thermal {
4855 polling-delay-passive 2910 polling-delay-passive = <10>;
>> 2911 polling-delay = <0>;
4856 2912
4857 thermal-sensors = <&t 2913 thermal-sensors = <&tsens1 5>;
4858 2914
4859 trips { 2915 trips {
4860 trip-point0 { 2916 trip-point0 {
4861 tempe 2917 temperature = <105000>;
4862 hyste 2918 hysteresis = <5000>;
4863 type 2919 type = "passive";
4864 }; 2920 };
4865 2921
4866 trip-point1 { 2922 trip-point1 {
4867 tempe 2923 temperature = <115000>;
4868 hyste 2924 hysteresis = <5000>;
4869 type 2925 type = "passive";
4870 }; 2926 };
4871 }; 2927 };
4872 }; 2928 };
4873 2929
4874 gpuss-4-thermal { 2930 gpuss-4-thermal {
4875 polling-delay-passive 2931 polling-delay-passive = <10>;
>> 2932 polling-delay = <0>;
4876 2933
4877 thermal-sensors = <&t 2934 thermal-sensors = <&tsens1 6>;
4878 2935
4879 trips { 2936 trips {
4880 trip-point0 { 2937 trip-point0 {
4881 tempe 2938 temperature = <105000>;
4882 hyste 2939 hysteresis = <5000>;
4883 type 2940 type = "passive";
4884 }; 2941 };
4885 2942
4886 trip-point1 { 2943 trip-point1 {
4887 tempe 2944 temperature = <115000>;
4888 hyste 2945 hysteresis = <5000>;
4889 type 2946 type = "passive";
4890 }; 2947 };
4891 }; 2948 };
4892 }; 2949 };
4893 2950
4894 gpuss-5-thermal { 2951 gpuss-5-thermal {
4895 polling-delay-passive 2952 polling-delay-passive = <10>;
>> 2953 polling-delay = <0>;
4896 2954
4897 thermal-sensors = <&t 2955 thermal-sensors = <&tsens1 7>;
4898 2956
4899 trips { 2957 trips {
4900 trip-point0 { 2958 trip-point0 {
4901 tempe 2959 temperature = <105000>;
4902 hyste 2960 hysteresis = <5000>;
4903 type 2961 type = "passive";
4904 }; 2962 };
4905 2963
4906 trip-point1 { 2964 trip-point1 {
4907 tempe 2965 temperature = <115000>;
4908 hyste 2966 hysteresis = <5000>;
4909 type 2967 type = "passive";
4910 }; 2968 };
4911 }; 2969 };
4912 }; 2970 };
4913 2971
4914 video-thermal { 2972 video-thermal {
>> 2973 polling-delay-passive = <0>;
>> 2974 polling-delay = <0>;
>> 2975
4915 thermal-sensors = <&t 2976 thermal-sensors = <&tsens1 8>;
4916 2977
4917 trips { 2978 trips {
4918 trip-point0 { 2979 trip-point0 {
4919 tempe 2980 temperature = <105000>;
4920 hyste 2981 hysteresis = <5000>;
4921 type 2982 type = "passive";
4922 }; 2983 };
4923 2984
4924 trip-point1 { 2985 trip-point1 {
4925 tempe 2986 temperature = <115000>;
4926 hyste 2987 hysteresis = <5000>;
4927 type 2988 type = "passive";
4928 }; 2989 };
4929 }; 2990 };
4930 }; 2991 };
4931 2992
4932 camss-1-thermal { 2993 camss-1-thermal {
>> 2994 polling-delay-passive = <0>;
>> 2995 polling-delay = <0>;
>> 2996
4933 thermal-sensors = <&t 2997 thermal-sensors = <&tsens1 9>;
4934 2998
4935 trips { 2999 trips {
4936 trip-point0 { 3000 trip-point0 {
4937 tempe 3001 temperature = <105000>;
4938 hyste 3002 hysteresis = <5000>;
4939 type 3003 type = "passive";
4940 }; 3004 };
4941 3005
4942 trip-point1 { 3006 trip-point1 {
4943 tempe 3007 temperature = <115000>;
4944 hyste 3008 hysteresis = <5000>;
4945 type 3009 type = "passive";
4946 }; 3010 };
4947 }; 3011 };
4948 }; 3012 };
4949 3013
4950 pcie-1-thermal { 3014 pcie-1-thermal {
>> 3015 polling-delay-passive = <0>;
>> 3016 polling-delay = <0>;
>> 3017
4951 thermal-sensors = <&t 3018 thermal-sensors = <&tsens1 10>;
4952 3019
4953 trips { 3020 trips {
4954 trip-point0 { 3021 trip-point0 {
4955 tempe 3022 temperature = <105000>;
4956 hyste 3023 hysteresis = <5000>;
4957 type 3024 type = "passive";
4958 }; 3025 };
4959 3026
4960 trip-point1 { 3027 trip-point1 {
4961 tempe 3028 temperature = <115000>;
4962 hyste 3029 hysteresis = <5000>;
4963 type 3030 type = "passive";
4964 }; 3031 };
4965 }; 3032 };
4966 }; 3033 };
4967 3034
4968 cpuss-0-1-thermal { 3035 cpuss-0-1-thermal {
>> 3036 polling-delay-passive = <0>;
>> 3037 polling-delay = <0>;
>> 3038
4969 thermal-sensors = <&t 3039 thermal-sensors = <&tsens1 11>;
4970 3040
4971 trips { 3041 trips {
4972 trip-point0 { 3042 trip-point0 {
4973 tempe 3043 temperature = <105000>;
4974 hyste 3044 hysteresis = <5000>;
4975 type 3045 type = "passive";
4976 }; 3046 };
4977 3047
4978 trip-point1 { 3048 trip-point1 {
4979 tempe 3049 temperature = <115000>;
4980 hyste 3050 hysteresis = <5000>;
4981 type 3051 type = "passive";
4982 }; 3052 };
4983 }; 3053 };
4984 }; 3054 };
4985 3055
4986 aoss-2-thermal { 3056 aoss-2-thermal {
>> 3057 polling-delay-passive = <0>;
>> 3058 polling-delay = <0>;
>> 3059
4987 thermal-sensors = <&t 3060 thermal-sensors = <&tsens2 0>;
4988 3061
4989 trips { 3062 trips {
4990 trip-point0 { 3063 trip-point0 {
4991 tempe 3064 temperature = <105000>;
4992 hyste 3065 hysteresis = <5000>;
4993 type 3066 type = "passive";
4994 }; 3067 };
4995 3068
4996 trip-point1 { 3069 trip-point1 {
4997 tempe 3070 temperature = <115000>;
4998 hyste 3071 hysteresis = <5000>;
4999 type 3072 type = "passive";
5000 }; 3073 };
5001 }; 3074 };
5002 }; 3075 };
5003 3076
5004 cpu-1-0-0-thermal { 3077 cpu-1-0-0-thermal {
5005 polling-delay-passive 3078 polling-delay-passive = <10>;
>> 3079 polling-delay = <0>;
5006 3080
5007 thermal-sensors = <&t 3081 thermal-sensors = <&tsens2 1>;
5008 3082
5009 trips { 3083 trips {
5010 trip-point0 { 3084 trip-point0 {
5011 tempe 3085 temperature = <105000>;
5012 hyste 3086 hysteresis = <5000>;
5013 type 3087 type = "passive";
5014 }; 3088 };
5015 3089
5016 trip-point1 { 3090 trip-point1 {
5017 tempe 3091 temperature = <115000>;
5018 hyste 3092 hysteresis = <5000>;
5019 type 3093 type = "passive";
5020 }; 3094 };
5021 }; 3095 };
5022 }; 3096 };
5023 3097
5024 cpu-1-1-0-thermal { 3098 cpu-1-1-0-thermal {
5025 polling-delay-passive 3099 polling-delay-passive = <10>;
>> 3100 polling-delay = <0>;
5026 3101
5027 thermal-sensors = <&t 3102 thermal-sensors = <&tsens2 2>;
5028 3103
5029 trips { 3104 trips {
5030 trip-point0 { 3105 trip-point0 {
5031 tempe 3106 temperature = <105000>;
5032 hyste 3107 hysteresis = <5000>;
5033 type 3108 type = "passive";
5034 }; 3109 };
5035 3110
5036 trip-point1 { 3111 trip-point1 {
5037 tempe 3112 temperature = <115000>;
5038 hyste 3113 hysteresis = <5000>;
5039 type 3114 type = "passive";
5040 }; 3115 };
5041 }; 3116 };
5042 }; 3117 };
5043 3118
5044 cpu-1-2-0-thermal { 3119 cpu-1-2-0-thermal {
5045 polling-delay-passive 3120 polling-delay-passive = <10>;
>> 3121 polling-delay = <0>;
5046 3122
5047 thermal-sensors = <&t 3123 thermal-sensors = <&tsens2 3>;
5048 3124
5049 trips { 3125 trips {
5050 trip-point0 { 3126 trip-point0 {
5051 tempe 3127 temperature = <105000>;
5052 hyste 3128 hysteresis = <5000>;
5053 type 3129 type = "passive";
5054 }; 3130 };
5055 3131
5056 trip-point1 { 3132 trip-point1 {
5057 tempe 3133 temperature = <115000>;
5058 hyste 3134 hysteresis = <5000>;
5059 type 3135 type = "passive";
5060 }; 3136 };
5061 }; 3137 };
5062 }; 3138 };
5063 3139
5064 cpu-1-3-0-thermal { 3140 cpu-1-3-0-thermal {
5065 polling-delay-passive 3141 polling-delay-passive = <10>;
>> 3142 polling-delay = <0>;
5066 3143
5067 thermal-sensors = <&t 3144 thermal-sensors = <&tsens2 4>;
5068 3145
5069 trips { 3146 trips {
5070 trip-point0 { 3147 trip-point0 {
5071 tempe 3148 temperature = <105000>;
5072 hyste 3149 hysteresis = <5000>;
5073 type 3150 type = "passive";
5074 }; 3151 };
5075 3152
5076 trip-point1 { 3153 trip-point1 {
5077 tempe 3154 temperature = <115000>;
5078 hyste 3155 hysteresis = <5000>;
5079 type 3156 type = "passive";
5080 }; 3157 };
5081 }; 3158 };
5082 }; 3159 };
5083 3160
5084 nsp-0-0-0-thermal { 3161 nsp-0-0-0-thermal {
5085 polling-delay-passive 3162 polling-delay-passive = <10>;
>> 3163 polling-delay = <0>;
5086 3164
5087 thermal-sensors = <&t 3165 thermal-sensors = <&tsens2 5>;
5088 3166
5089 trips { 3167 trips {
5090 trip-point0 { 3168 trip-point0 {
5091 tempe 3169 temperature = <105000>;
5092 hyste 3170 hysteresis = <5000>;
5093 type 3171 type = "passive";
5094 }; 3172 };
5095 3173
5096 trip-point1 { 3174 trip-point1 {
5097 tempe 3175 temperature = <115000>;
5098 hyste 3176 hysteresis = <5000>;
5099 type 3177 type = "passive";
5100 }; 3178 };
5101 }; 3179 };
5102 }; 3180 };
5103 3181
5104 nsp-0-1-0-thermal { 3182 nsp-0-1-0-thermal {
5105 polling-delay-passive 3183 polling-delay-passive = <10>;
>> 3184 polling-delay = <0>;
5106 3185
5107 thermal-sensors = <&t 3186 thermal-sensors = <&tsens2 6>;
5108 3187
5109 trips { 3188 trips {
5110 trip-point0 { 3189 trip-point0 {
5111 tempe 3190 temperature = <105000>;
5112 hyste 3191 hysteresis = <5000>;
5113 type 3192 type = "passive";
5114 }; 3193 };
5115 3194
5116 trip-point1 { 3195 trip-point1 {
5117 tempe 3196 temperature = <115000>;
5118 hyste 3197 hysteresis = <5000>;
5119 type 3198 type = "passive";
5120 }; 3199 };
5121 }; 3200 };
5122 }; 3201 };
5123 3202
5124 nsp-0-2-0-thermal { 3203 nsp-0-2-0-thermal {
5125 polling-delay-passive 3204 polling-delay-passive = <10>;
>> 3205 polling-delay = <0>;
5126 3206
5127 thermal-sensors = <&t 3207 thermal-sensors = <&tsens2 7>;
5128 3208
5129 trips { 3209 trips {
5130 trip-point0 { 3210 trip-point0 {
5131 tempe 3211 temperature = <105000>;
5132 hyste 3212 hysteresis = <5000>;
5133 type 3213 type = "passive";
5134 }; 3214 };
5135 3215
5136 trip-point1 { 3216 trip-point1 {
5137 tempe 3217 temperature = <115000>;
5138 hyste 3218 hysteresis = <5000>;
5139 type 3219 type = "passive";
5140 }; 3220 };
5141 }; 3221 };
5142 }; 3222 };
5143 3223
5144 nsp-1-0-0-thermal { 3224 nsp-1-0-0-thermal {
5145 polling-delay-passive 3225 polling-delay-passive = <10>;
>> 3226 polling-delay = <0>;
5146 3227
5147 thermal-sensors = <&t 3228 thermal-sensors = <&tsens2 8>;
5148 3229
5149 trips { 3230 trips {
5150 trip-point0 { 3231 trip-point0 {
5151 tempe 3232 temperature = <105000>;
5152 hyste 3233 hysteresis = <5000>;
5153 type 3234 type = "passive";
5154 }; 3235 };
5155 3236
5156 trip-point1 { 3237 trip-point1 {
5157 tempe 3238 temperature = <115000>;
5158 hyste 3239 hysteresis = <5000>;
5159 type 3240 type = "passive";
5160 }; 3241 };
5161 }; 3242 };
5162 }; 3243 };
5163 3244
5164 nsp-1-1-0-thermal { 3245 nsp-1-1-0-thermal {
5165 polling-delay-passive 3246 polling-delay-passive = <10>;
>> 3247 polling-delay = <0>;
5166 3248
5167 thermal-sensors = <&t 3249 thermal-sensors = <&tsens2 9>;
5168 3250
5169 trips { 3251 trips {
5170 trip-point0 { 3252 trip-point0 {
5171 tempe 3253 temperature = <105000>;
5172 hyste 3254 hysteresis = <5000>;
5173 type 3255 type = "passive";
5174 }; 3256 };
5175 3257
5176 trip-point1 { 3258 trip-point1 {
5177 tempe 3259 temperature = <115000>;
5178 hyste 3260 hysteresis = <5000>;
5179 type 3261 type = "passive";
5180 }; 3262 };
5181 }; 3263 };
5182 }; 3264 };
5183 3265
5184 nsp-1-2-0-thermal { 3266 nsp-1-2-0-thermal {
5185 polling-delay-passive 3267 polling-delay-passive = <10>;
>> 3268 polling-delay = <0>;
5186 3269
5187 thermal-sensors = <&t 3270 thermal-sensors = <&tsens2 10>;
5188 3271
5189 trips { 3272 trips {
5190 trip-point0 { 3273 trip-point0 {
5191 tempe 3274 temperature = <105000>;
5192 hyste 3275 hysteresis = <5000>;
5193 type 3276 type = "passive";
5194 }; 3277 };
5195 3278
5196 trip-point1 { 3279 trip-point1 {
5197 tempe 3280 temperature = <115000>;
5198 hyste 3281 hysteresis = <5000>;
5199 type 3282 type = "passive";
5200 }; 3283 };
5201 }; 3284 };
5202 }; 3285 };
5203 3286
5204 ddrss-0-thermal { 3287 ddrss-0-thermal {
>> 3288 polling-delay-passive = <0>;
>> 3289 polling-delay = <0>;
>> 3290
5205 thermal-sensors = <&t 3291 thermal-sensors = <&tsens2 11>;
5206 3292
5207 trips { 3293 trips {
5208 trip-point0 { 3294 trip-point0 {
5209 tempe 3295 temperature = <105000>;
5210 hyste 3296 hysteresis = <5000>;
5211 type 3297 type = "passive";
5212 }; 3298 };
5213 3299
5214 trip-point1 { 3300 trip-point1 {
5215 tempe 3301 temperature = <115000>;
5216 hyste 3302 hysteresis = <5000>;
5217 type 3303 type = "passive";
5218 }; 3304 };
5219 }; 3305 };
5220 }; 3306 };
5221 3307
5222 cpuss-1-0-thermal { 3308 cpuss-1-0-thermal {
>> 3309 polling-delay-passive = <0>;
>> 3310 polling-delay = <0>;
>> 3311
5223 thermal-sensors = <&t 3312 thermal-sensors = <&tsens2 12>;
5224 3313
5225 trips { 3314 trips {
5226 trip-point0 { 3315 trip-point0 {
5227 tempe 3316 temperature = <105000>;
5228 hyste 3317 hysteresis = <5000>;
5229 type 3318 type = "passive";
5230 }; 3319 };
5231 3320
5232 trip-point1 { 3321 trip-point1 {
5233 tempe 3322 temperature = <115000>;
5234 hyste 3323 hysteresis = <5000>;
5235 type 3324 type = "passive";
5236 }; 3325 };
5237 }; 3326 };
5238 }; 3327 };
5239 3328
5240 aoss-3-thermal { 3329 aoss-3-thermal {
>> 3330 polling-delay-passive = <0>;
>> 3331 polling-delay = <0>;
>> 3332
5241 thermal-sensors = <&t 3333 thermal-sensors = <&tsens3 0>;
5242 3334
5243 trips { 3335 trips {
5244 trip-point0 { 3336 trip-point0 {
5245 tempe 3337 temperature = <105000>;
5246 hyste 3338 hysteresis = <5000>;
5247 type 3339 type = "passive";
5248 }; 3340 };
5249 3341
5250 trip-point1 { 3342 trip-point1 {
5251 tempe 3343 temperature = <115000>;
5252 hyste 3344 hysteresis = <5000>;
5253 type 3345 type = "passive";
5254 }; 3346 };
5255 }; 3347 };
5256 }; 3348 };
5257 3349
5258 cpu-1-0-1-thermal { 3350 cpu-1-0-1-thermal {
5259 polling-delay-passive 3351 polling-delay-passive = <10>;
>> 3352 polling-delay = <0>;
5260 3353
5261 thermal-sensors = <&t 3354 thermal-sensors = <&tsens3 1>;
5262 3355
5263 trips { 3356 trips {
5264 trip-point0 { 3357 trip-point0 {
5265 tempe 3358 temperature = <105000>;
5266 hyste 3359 hysteresis = <5000>;
5267 type 3360 type = "passive";
5268 }; 3361 };
5269 3362
5270 trip-point1 { 3363 trip-point1 {
5271 tempe 3364 temperature = <115000>;
5272 hyste 3365 hysteresis = <5000>;
5273 type 3366 type = "passive";
5274 }; 3367 };
5275 }; 3368 };
5276 }; 3369 };
5277 3370
5278 cpu-1-1-1-thermal { 3371 cpu-1-1-1-thermal {
5279 polling-delay-passive 3372 polling-delay-passive = <10>;
>> 3373 polling-delay = <0>;
5280 3374
5281 thermal-sensors = <&t 3375 thermal-sensors = <&tsens3 2>;
5282 3376
5283 trips { 3377 trips {
5284 trip-point0 { 3378 trip-point0 {
5285 tempe 3379 temperature = <105000>;
5286 hyste 3380 hysteresis = <5000>;
5287 type 3381 type = "passive";
5288 }; 3382 };
5289 3383
5290 trip-point1 { 3384 trip-point1 {
5291 tempe 3385 temperature = <115000>;
5292 hyste 3386 hysteresis = <5000>;
5293 type 3387 type = "passive";
5294 }; 3388 };
5295 }; 3389 };
5296 }; 3390 };
5297 3391
5298 cpu-1-2-1-thermal { 3392 cpu-1-2-1-thermal {
5299 polling-delay-passive 3393 polling-delay-passive = <10>;
>> 3394 polling-delay = <0>;
5300 3395
5301 thermal-sensors = <&t 3396 thermal-sensors = <&tsens3 3>;
5302 3397
5303 trips { 3398 trips {
5304 trip-point0 { 3399 trip-point0 {
5305 tempe 3400 temperature = <105000>;
5306 hyste 3401 hysteresis = <5000>;
5307 type 3402 type = "passive";
5308 }; 3403 };
5309 3404
5310 trip-point1 { 3405 trip-point1 {
5311 tempe 3406 temperature = <115000>;
5312 hyste 3407 hysteresis = <5000>;
5313 type 3408 type = "passive";
5314 }; 3409 };
5315 }; 3410 };
5316 }; 3411 };
5317 3412
5318 cpu-1-3-1-thermal { 3413 cpu-1-3-1-thermal {
5319 polling-delay-passive 3414 polling-delay-passive = <10>;
>> 3415 polling-delay = <0>;
5320 3416
5321 thermal-sensors = <&t 3417 thermal-sensors = <&tsens3 4>;
5322 3418
5323 trips { 3419 trips {
5324 trip-point0 { 3420 trip-point0 {
5325 tempe 3421 temperature = <105000>;
5326 hyste 3422 hysteresis = <5000>;
5327 type 3423 type = "passive";
5328 }; 3424 };
5329 3425
5330 trip-point1 { 3426 trip-point1 {
5331 tempe 3427 temperature = <115000>;
5332 hyste 3428 hysteresis = <5000>;
5333 type 3429 type = "passive";
5334 }; 3430 };
5335 }; 3431 };
5336 }; 3432 };
5337 3433
5338 nsp-0-0-1-thermal { 3434 nsp-0-0-1-thermal {
5339 polling-delay-passive 3435 polling-delay-passive = <10>;
>> 3436 polling-delay = <0>;
5340 3437
5341 thermal-sensors = <&t 3438 thermal-sensors = <&tsens3 5>;
5342 3439
5343 trips { 3440 trips {
5344 trip-point0 { 3441 trip-point0 {
5345 tempe 3442 temperature = <105000>;
5346 hyste 3443 hysteresis = <5000>;
5347 type 3444 type = "passive";
5348 }; 3445 };
5349 3446
5350 trip-point1 { 3447 trip-point1 {
5351 tempe 3448 temperature = <115000>;
5352 hyste 3449 hysteresis = <5000>;
5353 type 3450 type = "passive";
5354 }; 3451 };
5355 }; 3452 };
5356 }; 3453 };
5357 3454
5358 nsp-0-1-1-thermal { 3455 nsp-0-1-1-thermal {
5359 polling-delay-passive 3456 polling-delay-passive = <10>;
>> 3457 polling-delay = <0>;
5360 3458
5361 thermal-sensors = <&t 3459 thermal-sensors = <&tsens3 6>;
5362 3460
5363 trips { 3461 trips {
5364 trip-point0 { 3462 trip-point0 {
5365 tempe 3463 temperature = <105000>;
5366 hyste 3464 hysteresis = <5000>;
5367 type 3465 type = "passive";
5368 }; 3466 };
5369 3467
5370 trip-point1 { 3468 trip-point1 {
5371 tempe 3469 temperature = <115000>;
5372 hyste 3470 hysteresis = <5000>;
5373 type 3471 type = "passive";
5374 }; 3472 };
5375 }; 3473 };
5376 }; 3474 };
5377 3475
5378 nsp-0-2-1-thermal { 3476 nsp-0-2-1-thermal {
5379 polling-delay-passive 3477 polling-delay-passive = <10>;
>> 3478 polling-delay = <0>;
5380 3479
5381 thermal-sensors = <&t 3480 thermal-sensors = <&tsens3 7>;
5382 3481
5383 trips { 3482 trips {
5384 trip-point0 { 3483 trip-point0 {
5385 tempe 3484 temperature = <105000>;
5386 hyste 3485 hysteresis = <5000>;
5387 type 3486 type = "passive";
5388 }; 3487 };
5389 3488
5390 trip-point1 { 3489 trip-point1 {
5391 tempe 3490 temperature = <115000>;
5392 hyste 3491 hysteresis = <5000>;
5393 type 3492 type = "passive";
5394 }; 3493 };
5395 }; 3494 };
5396 }; 3495 };
5397 3496
5398 nsp-1-0-1-thermal { 3497 nsp-1-0-1-thermal {
5399 polling-delay-passive 3498 polling-delay-passive = <10>;
>> 3499 polling-delay = <0>;
5400 3500
5401 thermal-sensors = <&t 3501 thermal-sensors = <&tsens3 8>;
5402 3502
5403 trips { 3503 trips {
5404 trip-point0 { 3504 trip-point0 {
5405 tempe 3505 temperature = <105000>;
5406 hyste 3506 hysteresis = <5000>;
5407 type 3507 type = "passive";
5408 }; 3508 };
5409 3509
5410 trip-point1 { 3510 trip-point1 {
5411 tempe 3511 temperature = <115000>;
5412 hyste 3512 hysteresis = <5000>;
5413 type 3513 type = "passive";
5414 }; 3514 };
5415 }; 3515 };
5416 }; 3516 };
5417 3517
5418 nsp-1-1-1-thermal { 3518 nsp-1-1-1-thermal {
5419 polling-delay-passive 3519 polling-delay-passive = <10>;
>> 3520 polling-delay = <0>;
5420 3521
5421 thermal-sensors = <&t 3522 thermal-sensors = <&tsens3 9>;
5422 3523
5423 trips { 3524 trips {
5424 trip-point0 { 3525 trip-point0 {
5425 tempe 3526 temperature = <105000>;
5426 hyste 3527 hysteresis = <5000>;
5427 type 3528 type = "passive";
5428 }; 3529 };
5429 3530
5430 trip-point1 { 3531 trip-point1 {
5431 tempe 3532 temperature = <115000>;
5432 hyste 3533 hysteresis = <5000>;
5433 type 3534 type = "passive";
5434 }; 3535 };
5435 }; 3536 };
5436 }; 3537 };
5437 3538
5438 nsp-1-2-1-thermal { 3539 nsp-1-2-1-thermal {
5439 polling-delay-passive 3540 polling-delay-passive = <10>;
>> 3541 polling-delay = <0>;
5440 3542
5441 thermal-sensors = <&t 3543 thermal-sensors = <&tsens3 10>;
5442 3544
5443 trips { 3545 trips {
5444 trip-point0 { 3546 trip-point0 {
5445 tempe 3547 temperature = <105000>;
5446 hyste 3548 hysteresis = <5000>;
5447 type 3549 type = "passive";
5448 }; 3550 };
5449 3551
5450 trip-point1 { 3552 trip-point1 {
5451 tempe 3553 temperature = <115000>;
5452 hyste 3554 hysteresis = <5000>;
5453 type 3555 type = "passive";
5454 }; 3556 };
5455 }; 3557 };
5456 }; 3558 };
5457 3559
5458 ddrss-1-thermal { 3560 ddrss-1-thermal {
>> 3561 polling-delay-passive = <0>;
>> 3562 polling-delay = <0>;
>> 3563
5459 thermal-sensors = <&t 3564 thermal-sensors = <&tsens3 11>;
5460 3565
5461 trips { 3566 trips {
5462 trip-point0 { 3567 trip-point0 {
5463 tempe 3568 temperature = <105000>;
5464 hyste 3569 hysteresis = <5000>;
5465 type 3570 type = "passive";
5466 }; 3571 };
5467 3572
5468 trip-point1 { 3573 trip-point1 {
5469 tempe 3574 temperature = <115000>;
5470 hyste 3575 hysteresis = <5000>;
5471 type 3576 type = "passive";
5472 }; 3577 };
5473 }; 3578 };
5474 }; 3579 };
5475 3580
5476 cpuss-1-1-thermal { 3581 cpuss-1-1-thermal {
>> 3582 polling-delay-passive = <0>;
>> 3583 polling-delay = <0>;
>> 3584
5477 thermal-sensors = <&t 3585 thermal-sensors = <&tsens3 12>;
5478 3586
5479 trips { 3587 trips {
5480 trip-point0 { 3588 trip-point0 {
5481 tempe 3589 temperature = <105000>;
5482 hyste 3590 hysteresis = <5000>;
5483 type 3591 type = "passive";
5484 }; 3592 };
5485 3593
5486 trip-point1 { 3594 trip-point1 {
5487 tempe 3595 temperature = <115000>;
5488 hyste 3596 hysteresis = <5000>;
5489 type 3597 type = "passive";
5490 }; 3598 };
5491 }; 3599 };
5492 }; 3600 };
5493 }; 3601 };
5494 3602
5495 arch_timer: timer { 3603 arch_timer: timer {
5496 compatible = "arm,armv8-timer 3604 compatible = "arm,armv8-timer";
5497 interrupts = <GIC_PPI 13 (GIC 3605 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5498 <GIC_PPI 14 (GIC 3606 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5499 <GIC_PPI 11 (GIC 3607 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5500 <GIC_PPI 10 (GIC 3608 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
5501 }; 3609 };
5502 3610
5503 pcie0: pcie@1c00000 { 3611 pcie0: pcie@1c00000 {
5504 compatible = "qcom,pcie-sa877 3612 compatible = "qcom,pcie-sa8775p";
5505 reg = <0x0 0x01c00000 0x0 0x3 3613 reg = <0x0 0x01c00000 0x0 0x3000>,
5506 <0x0 0x40000000 0x0 0xf 3614 <0x0 0x40000000 0x0 0xf20>,
5507 <0x0 0x40000f20 0x0 0xa 3615 <0x0 0x40000f20 0x0 0xa8>,
5508 <0x0 0x40001000 0x0 0x4 3616 <0x0 0x40001000 0x0 0x4000>,
5509 <0x0 0x40100000 0x0 0x1 3617 <0x0 0x40100000 0x0 0x100000>,
5510 <0x0 0x01c03000 0x0 0x1 3618 <0x0 0x01c03000 0x0 0x1000>;
5511 reg-names = "parf", "dbi", "e 3619 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
5512 device_type = "pci"; 3620 device_type = "pci";
5513 3621
5514 #address-cells = <3>; 3622 #address-cells = <3>;
5515 #size-cells = <2>; 3623 #size-cells = <2>;
5516 ranges = <0x01000000 0x0 0x00 3624 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
5517 <0x02000000 0x0 0x40 3625 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
5518 bus-range = <0x00 0xff>; 3626 bus-range = <0x00 0xff>;
5519 3627
5520 dma-coherent; 3628 dma-coherent;
5521 3629
5522 linux,pci-domain = <0>; 3630 linux,pci-domain = <0>;
5523 num-lanes = <2>; 3631 num-lanes = <2>;
5524 3632
5525 interrupts = <GIC_SPI 307 IRQ 3633 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
5526 <GIC_SPI 308 IRQ 3634 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
5527 <GIC_SPI 309 IRQ 3635 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
5528 <GIC_SPI 312 IRQ 3636 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
5529 <GIC_SPI 313 IRQ 3637 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
5530 <GIC_SPI 314 IRQ 3638 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
5531 <GIC_SPI 374 IRQ 3639 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
5532 <GIC_SPI 375 IRQ 3640 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
5533 interrupt-names = "msi0", "ms 3641 interrupt-names = "msi0", "msi1", "msi2", "msi3",
5534 "msi4", "ms 3642 "msi4", "msi5", "msi6", "msi7";
5535 #interrupt-cells = <1>; 3643 #interrupt-cells = <1>;
5536 interrupt-map-mask = <0 0 0 0 3644 interrupt-map-mask = <0 0 0 0x7>;
5537 interrupt-map = <0 0 0 1 &int 3645 interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
5538 <0 0 0 2 &int 3646 <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
5539 <0 0 0 3 &int 3647 <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
5540 <0 0 0 4 &int 3648 <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>;
5541 3649
5542 clocks = <&gcc GCC_PCIE_0_AUX 3650 clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
5543 <&gcc GCC_PCIE_0_CFG 3651 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
5544 <&gcc GCC_PCIE_0_MST 3652 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
5545 <&gcc GCC_PCIE_0_SLV 3653 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
5546 <&gcc GCC_PCIE_0_SLV 3654 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>;
5547 3655
5548 clock-names = "aux", 3656 clock-names = "aux",
5549 "cfg", 3657 "cfg",
5550 "bus_master", 3658 "bus_master",
5551 "bus_slave", 3659 "bus_slave",
5552 "slave_q2a"; 3660 "slave_q2a";
5553 3661
5554 assigned-clocks = <&gcc GCC_P 3662 assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>;
5555 assigned-clock-rates = <19200 3663 assigned-clock-rates = <19200000>;
5556 3664
5557 interconnects = <&pcie_anoc M 3665 interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>,
5558 <&gem_noc MAS 3666 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>;
5559 interconnect-names = "pcie-me 3667 interconnect-names = "pcie-mem", "cpu-pcie";
5560 3668
5561 iommu-map = <0x0 &pcie_smmu 0 3669 iommu-map = <0x0 &pcie_smmu 0x0000 0x1>,
5562 <0x100 &pcie_smmu 3670 <0x100 &pcie_smmu 0x0001 0x1>;
5563 3671
5564 resets = <&gcc GCC_PCIE_0_BCR 3672 resets = <&gcc GCC_PCIE_0_BCR>;
5565 reset-names = "pci"; 3673 reset-names = "pci";
5566 power-domains = <&gcc PCIE_0_ 3674 power-domains = <&gcc PCIE_0_GDSC>;
5567 3675
5568 phys = <&pcie0_phy>; 3676 phys = <&pcie0_phy>;
5569 phy-names = "pciephy"; 3677 phy-names = "pciephy";
5570 3678
5571 status = "disabled"; 3679 status = "disabled";
5572 <<
5573 pcie@0 { <<
5574 device_type = "pci"; <<
5575 reg = <0x0 0x0 0x0 0x <<
5576 bus-range = <0x01 0xf <<
5577 <<
5578 #address-cells = <3>; <<
5579 #size-cells = <2>; <<
5580 ranges; <<
5581 }; <<
5582 }; <<
5583 <<
5584 pcie0_ep: pcie-ep@1c00000 { <<
5585 compatible = "qcom,sa8775p-pc <<
5586 reg = <0x0 0x01c00000 0x0 0x3 <<
5587 <0x0 0x40000000 0x0 0xf <<
5588 <0x0 0x40000f20 0x0 0xa <<
5589 <0x0 0x40001000 0x0 0x4 <<
5590 <0x0 0x40200000 0x0 0x1 <<
5591 <0x0 0x01c03000 0x0 0x1 <<
5592 <0x0 0x40005000 0x0 0x2 <<
5593 reg-names = "parf", "dbi", "e <<
5594 "mmio", "dma"; <<
5595 <<
5596 clocks = <&gcc GCC_PCIE_0_AUX <<
5597 <&gcc GCC_PCIE_0_CFG_ <<
5598 <&gcc GCC_PCIE_0_MSTR <<
5599 <&gcc GCC_PCIE_0_SLV_ <<
5600 <&gcc GCC_PCIE_0_SLV_ <<
5601 <<
5602 clock-names = "aux", <<
5603 "cfg", <<
5604 "bus_master", <<
5605 "bus_slave", <<
5606 "slave_q2a"; <<
5607 <<
5608 interrupts = <GIC_SPI 306 IRQ <<
5609 <GIC_SPI 147 IRQ <<
5610 <GIC_SPI 630 IRQ <<
5611 <<
5612 interrupt-names = "global", " <<
5613 <<
5614 interconnects = <&pcie_anoc M <<
5615 <&gem_noc MAS <<
5616 interconnect-names = "pcie-me <<
5617 <<
5618 dma-coherent; <<
5619 iommus = <&pcie_smmu 0x0000 0 <<
5620 resets = <&gcc GCC_PCIE_0_BCR <<
5621 reset-names = "core"; <<
5622 power-domains = <&gcc PCIE_0_ <<
5623 phys = <&pcie0_phy>; <<
5624 phy-names = "pciephy"; <<
5625 max-link-speed = <3>; /* FIXM <<
5626 num-lanes = <2>; <<
5627 <<
5628 status = "disabled"; <<
5629 }; 3680 };
5630 3681
5631 pcie0_phy: phy@1c04000 { 3682 pcie0_phy: phy@1c04000 {
5632 compatible = "qcom,sa8775p-qm 3683 compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy";
5633 reg = <0x0 0x1c04000 0x0 0x20 3684 reg = <0x0 0x1c04000 0x0 0x2000>;
5634 3685
5635 clocks = <&gcc GCC_PCIE_0_AUX 3686 clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
5636 <&gcc GCC_PCIE_0_CFG 3687 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
5637 <&gcc GCC_PCIE_CLKRE 3688 <&gcc GCC_PCIE_CLKREF_EN>,
5638 <&gcc GCC_PCIE_0_PHY 3689 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
5639 <&gcc GCC_PCIE_0_PIP 3690 <&gcc GCC_PCIE_0_PIPE_CLK>,
5640 <&gcc GCC_PCIE_0_PIP 3691 <&gcc GCC_PCIE_0_PIPEDIV2_CLK>,
5641 <&gcc GCC_PCIE_0_PHY 3692 <&gcc GCC_PCIE_0_PHY_AUX_CLK>;
5642 3693
5643 clock-names = "aux", "cfg_ahb 3694 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe",
5644 "pipediv2", "ph 3695 "pipediv2", "phy_aux";
5645 3696
5646 assigned-clocks = <&gcc GCC_P 3697 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
5647 assigned-clock-rates = <10000 3698 assigned-clock-rates = <100000000>;
5648 3699
5649 resets = <&gcc GCC_PCIE_0_PHY 3700 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
5650 reset-names = "phy"; 3701 reset-names = "phy";
5651 3702
5652 #clock-cells = <0>; 3703 #clock-cells = <0>;
5653 clock-output-names = "pcie_0_ 3704 clock-output-names = "pcie_0_pipe_clk";
5654 3705
5655 #phy-cells = <0>; 3706 #phy-cells = <0>;
5656 3707
5657 status = "disabled"; 3708 status = "disabled";
5658 }; 3709 };
5659 3710
5660 pcie1: pcie@1c10000 { 3711 pcie1: pcie@1c10000 {
5661 compatible = "qcom,pcie-sa877 3712 compatible = "qcom,pcie-sa8775p";
5662 reg = <0x0 0x01c10000 0x0 0x3 3713 reg = <0x0 0x01c10000 0x0 0x3000>,
5663 <0x0 0x60000000 0x0 0xf 3714 <0x0 0x60000000 0x0 0xf20>,
5664 <0x0 0x60000f20 0x0 0xa 3715 <0x0 0x60000f20 0x0 0xa8>,
5665 <0x0 0x60001000 0x0 0x4 3716 <0x0 0x60001000 0x0 0x4000>,
5666 <0x0 0x60100000 0x0 0x1 3717 <0x0 0x60100000 0x0 0x100000>,
5667 <0x0 0x01c13000 0x0 0x1 3718 <0x0 0x01c13000 0x0 0x1000>;
5668 reg-names = "parf", "dbi", "e 3719 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
5669 device_type = "pci"; 3720 device_type = "pci";
5670 3721
5671 #address-cells = <3>; 3722 #address-cells = <3>;
5672 #size-cells = <2>; 3723 #size-cells = <2>;
5673 ranges = <0x01000000 0x0 0x00 3724 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
5674 <0x02000000 0x0 0x60 3725 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x1fd00000>;
5675 bus-range = <0x00 0xff>; 3726 bus-range = <0x00 0xff>;
5676 3727
5677 dma-coherent; 3728 dma-coherent;
5678 3729
5679 linux,pci-domain = <1>; 3730 linux,pci-domain = <1>;
5680 num-lanes = <4>; 3731 num-lanes = <4>;
5681 3732
5682 interrupts = <GIC_SPI 519 IRQ 3733 interrupts = <GIC_SPI 519 IRQ_TYPE_LEVEL_HIGH>,
5683 <GIC_SPI 140 IRQ 3734 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
5684 <GIC_SPI 141 IRQ 3735 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
5685 <GIC_SPI 142 IRQ 3736 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
5686 <GIC_SPI 143 IRQ 3737 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
5687 <GIC_SPI 144 IRQ 3738 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
5688 <GIC_SPI 145 IRQ 3739 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
5689 <GIC_SPI 146 IRQ 3740 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
5690 interrupt-names = "msi0", "ms 3741 interrupt-names = "msi0", "msi1", "msi2", "msi3",
5691 "msi4", "ms 3742 "msi4", "msi5", "msi6", "msi7";
5692 #interrupt-cells = <1>; 3743 #interrupt-cells = <1>;
5693 interrupt-map-mask = <0 0 0 0 3744 interrupt-map-mask = <0 0 0 0x7>;
5694 interrupt-map = <0 0 0 1 &int 3745 interrupt-map = <0 0 0 1 &intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
5695 <0 0 0 2 &int 3746 <0 0 0 2 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
5696 <0 0 0 3 &int 3747 <0 0 0 3 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
5697 <0 0 0 4 &int 3748 <0 0 0 4 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
5698 3749
5699 clocks = <&gcc GCC_PCIE_1_AUX 3750 clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
5700 <&gcc GCC_PCIE_1_CFG 3751 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
5701 <&gcc GCC_PCIE_1_MST 3752 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
5702 <&gcc GCC_PCIE_1_SLV 3753 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
5703 <&gcc GCC_PCIE_1_SLV 3754 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>;
5704 3755
5705 clock-names = "aux", 3756 clock-names = "aux",
5706 "cfg", 3757 "cfg",
5707 "bus_master", 3758 "bus_master",
5708 "bus_slave", 3759 "bus_slave",
5709 "slave_q2a"; 3760 "slave_q2a";
5710 3761
5711 assigned-clocks = <&gcc GCC_P 3762 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
5712 assigned-clock-rates = <19200 3763 assigned-clock-rates = <19200000>;
5713 3764
5714 interconnects = <&pcie_anoc M 3765 interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>,
5715 <&gem_noc MAS 3766 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>;
5716 interconnect-names = "pcie-me 3767 interconnect-names = "pcie-mem", "cpu-pcie";
5717 3768
5718 iommu-map = <0x0 &pcie_smmu 0 3769 iommu-map = <0x0 &pcie_smmu 0x0080 0x1>,
5719 <0x100 &pcie_smmu 3770 <0x100 &pcie_smmu 0x0081 0x1>;
5720 3771
5721 resets = <&gcc GCC_PCIE_1_BCR 3772 resets = <&gcc GCC_PCIE_1_BCR>;
5722 reset-names = "pci"; 3773 reset-names = "pci";
5723 power-domains = <&gcc PCIE_1_ 3774 power-domains = <&gcc PCIE_1_GDSC>;
5724 3775
5725 phys = <&pcie1_phy>; 3776 phys = <&pcie1_phy>;
5726 phy-names = "pciephy"; 3777 phy-names = "pciephy";
5727 <<
5728 status = "disabled"; <<
5729 <<
5730 pcie@0 { <<
5731 device_type = "pci"; <<
5732 reg = <0x0 0x0 0x0 0x <<
5733 bus-range = <0x01 0xf <<
5734 <<
5735 #address-cells = <3>; <<
5736 #size-cells = <2>; <<
5737 ranges; <<
5738 }; <<
5739 }; <<
5740 <<
5741 pcie1_ep: pcie-ep@1c10000 { <<
5742 compatible = "qcom,sa8775p-pc <<
5743 reg = <0x0 0x01c10000 0x0 0x3 <<
5744 <0x0 0x60000000 0x0 0xf <<
5745 <0x0 0x60000f20 0x0 0xa <<
5746 <0x0 0x60001000 0x0 0x4 <<
5747 <0x0 0x60200000 0x0 0x1 <<
5748 <0x0 0x01c13000 0x0 0x1 <<
5749 <0x0 0x60005000 0x0 0x2 <<
5750 reg-names = "parf", "dbi", "e <<
5751 "mmio", "dma"; <<
5752 <<
5753 clocks = <&gcc GCC_PCIE_1_AUX <<
5754 <&gcc GCC_PCIE_1_CFG <<
5755 <&gcc GCC_PCIE_1_MST <<
5756 <&gcc GCC_PCIE_1_SLV <<
5757 <&gcc GCC_PCIE_1_SLV <<
5758 <<
5759 clock-names = "aux", <<
5760 "cfg", <<
5761 "bus_master", <<
5762 "bus_slave", <<
5763 "slave_q2a"; <<
5764 <<
5765 interrupts = <GIC_SPI 518 IRQ <<
5766 <GIC_SPI 152 IRQ <<
5767 <GIC_SPI 474 IRQ <<
5768 <<
5769 interrupt-names = "global", " <<
5770 <<
5771 interconnects = <&pcie_anoc M <<
5772 <&gem_noc MAS <<
5773 interconnect-names = "pcie-me <<
5774 <<
5775 dma-coherent; <<
5776 iommus = <&pcie_smmu 0x80 0x7 <<
5777 resets = <&gcc GCC_PCIE_1_BCR <<
5778 reset-names = "core"; <<
5779 power-domains = <&gcc PCIE_1_ <<
5780 phys = <&pcie1_phy>; <<
5781 phy-names = "pciephy"; <<
5782 max-link-speed = <3>; /* FIXM <<
5783 num-lanes = <4>; <<
5784 3778
5785 status = "disabled"; 3779 status = "disabled";
5786 }; 3780 };
5787 3781
5788 pcie1_phy: phy@1c14000 { 3782 pcie1_phy: phy@1c14000 {
5789 compatible = "qcom,sa8775p-qm 3783 compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy";
5790 reg = <0x0 0x1c14000 0x0 0x40 3784 reg = <0x0 0x1c14000 0x0 0x4000>;
5791 3785
5792 clocks = <&gcc GCC_PCIE_1_AUX 3786 clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
5793 <&gcc GCC_PCIE_1_CFG 3787 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
5794 <&gcc GCC_PCIE_CLKRE 3788 <&gcc GCC_PCIE_CLKREF_EN>,
5795 <&gcc GCC_PCIE_1_PHY 3789 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
5796 <&gcc GCC_PCIE_1_PIP 3790 <&gcc GCC_PCIE_1_PIPE_CLK>,
5797 <&gcc GCC_PCIE_1_PIP 3791 <&gcc GCC_PCIE_1_PIPEDIV2_CLK>,
5798 <&gcc GCC_PCIE_1_PHY 3792 <&gcc GCC_PCIE_1_PHY_AUX_CLK>;
5799 3793
5800 clock-names = "aux", "cfg_ahb 3794 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe",
5801 "pipediv2", "ph 3795 "pipediv2", "phy_aux";
5802 3796
5803 assigned-clocks = <&gcc GCC_P 3797 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
5804 assigned-clock-rates = <10000 3798 assigned-clock-rates = <100000000>;
5805 3799
5806 resets = <&gcc GCC_PCIE_1_PHY 3800 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
5807 reset-names = "phy"; 3801 reset-names = "phy";
5808 3802
5809 #clock-cells = <0>; 3803 #clock-cells = <0>;
5810 clock-output-names = "pcie_1_ 3804 clock-output-names = "pcie_1_pipe_clk";
5811 3805
5812 #phy-cells = <0>; 3806 #phy-cells = <0>;
5813 3807
5814 status = "disabled"; 3808 status = "disabled";
5815 }; 3809 };
5816 }; 3810 };
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