1 // SPDX-License-Identifier: BSD-3-Clause 1 // SPDX-License-Identifier: BSD-3-Clause
2 /* 2 /*
3 * Copyright (c) 2023, Linaro Limited 3 * Copyright (c) 2023, Linaro Limited
4 */ 4 */
5 5
6 #include <dt-bindings/interconnect/qcom,icc.h> 6 #include <dt-bindings/interconnect/qcom,icc.h>
7 #include <dt-bindings/interrupt-controller/arm 7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/clock/qcom,rpmh.h> 8 #include <dt-bindings/clock/qcom,rpmh.h>
9 #include <dt-bindings/clock/qcom,sa8775p-gcc.h 9 #include <dt-bindings/clock/qcom,sa8775p-gcc.h>
10 #include <dt-bindings/clock/qcom,sa8775p-gpucc 10 #include <dt-bindings/clock/qcom,sa8775p-gpucc.h>
11 #include <dt-bindings/interconnect/qcom,sa8775 11 #include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h>
12 #include <dt-bindings/mailbox/qcom-ipcc.h> 12 #include <dt-bindings/mailbox/qcom-ipcc.h>
13 #include <dt-bindings/firmware/qcom,scm.h> 13 #include <dt-bindings/firmware/qcom,scm.h>
14 #include <dt-bindings/power/qcom,rpmhpd.h> 14 #include <dt-bindings/power/qcom,rpmhpd.h>
15 #include <dt-bindings/power/qcom-rpmpd.h> 15 #include <dt-bindings/power/qcom-rpmpd.h>
16 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 16 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
17 17
18 / { 18 / {
19 interrupt-parent = <&intc>; 19 interrupt-parent = <&intc>;
20 20
21 #address-cells = <2>; 21 #address-cells = <2>;
22 #size-cells = <2>; 22 #size-cells = <2>;
23 23
24 clocks { 24 clocks {
25 xo_board_clk: xo-board-clk { 25 xo_board_clk: xo-board-clk {
26 compatible = "fixed-cl 26 compatible = "fixed-clock";
27 #clock-cells = <0>; 27 #clock-cells = <0>;
28 }; 28 };
29 29
30 sleep_clk: sleep-clk { 30 sleep_clk: sleep-clk {
31 compatible = "fixed-cl 31 compatible = "fixed-clock";
32 #clock-cells = <0>; 32 #clock-cells = <0>;
33 }; 33 };
34 }; 34 };
35 35
36 cpus { 36 cpus {
37 #address-cells = <2>; 37 #address-cells = <2>;
38 #size-cells = <0>; 38 #size-cells = <0>;
39 39
40 CPU0: cpu@0 { 40 CPU0: cpu@0 {
41 device_type = "cpu"; 41 device_type = "cpu";
42 compatible = "qcom,kry 42 compatible = "qcom,kryo";
43 reg = <0x0 0x0>; 43 reg = <0x0 0x0>;
44 enable-method = "psci" 44 enable-method = "psci";
45 qcom,freq-domain = <&c 45 qcom,freq-domain = <&cpufreq_hw 0>;
46 next-level-cache = <&L 46 next-level-cache = <&L2_0>;
47 capacity-dmips-mhz = < 47 capacity-dmips-mhz = <1024>;
48 dynamic-power-coeffici 48 dynamic-power-coefficient = <100>;
49 L2_0: l2-cache { 49 L2_0: l2-cache {
50 compatible = " 50 compatible = "cache";
51 cache-level = 51 cache-level = <2>;
52 cache-unified; 52 cache-unified;
53 next-level-cac 53 next-level-cache = <&L3_0>;
54 L3_0: l3-cache 54 L3_0: l3-cache {
55 compat 55 compatible = "cache";
56 cache- 56 cache-level = <3>;
57 cache- 57 cache-unified;
58 }; 58 };
59 }; 59 };
60 }; 60 };
61 61
62 CPU1: cpu@100 { 62 CPU1: cpu@100 {
63 device_type = "cpu"; 63 device_type = "cpu";
64 compatible = "qcom,kry 64 compatible = "qcom,kryo";
65 reg = <0x0 0x100>; 65 reg = <0x0 0x100>;
66 enable-method = "psci" 66 enable-method = "psci";
67 qcom,freq-domain = <&c 67 qcom,freq-domain = <&cpufreq_hw 0>;
68 next-level-cache = <&L 68 next-level-cache = <&L2_1>;
69 capacity-dmips-mhz = < 69 capacity-dmips-mhz = <1024>;
70 dynamic-power-coeffici 70 dynamic-power-coefficient = <100>;
71 L2_1: l2-cache { 71 L2_1: l2-cache {
72 compatible = " 72 compatible = "cache";
73 cache-level = 73 cache-level = <2>;
74 cache-unified; 74 cache-unified;
75 next-level-cac 75 next-level-cache = <&L3_0>;
76 }; 76 };
77 }; 77 };
78 78
79 CPU2: cpu@200 { 79 CPU2: cpu@200 {
80 device_type = "cpu"; 80 device_type = "cpu";
81 compatible = "qcom,kry 81 compatible = "qcom,kryo";
82 reg = <0x0 0x200>; 82 reg = <0x0 0x200>;
83 enable-method = "psci" 83 enable-method = "psci";
84 qcom,freq-domain = <&c 84 qcom,freq-domain = <&cpufreq_hw 0>;
85 next-level-cache = <&L 85 next-level-cache = <&L2_2>;
86 capacity-dmips-mhz = < 86 capacity-dmips-mhz = <1024>;
87 dynamic-power-coeffici 87 dynamic-power-coefficient = <100>;
88 L2_2: l2-cache { 88 L2_2: l2-cache {
89 compatible = " 89 compatible = "cache";
90 cache-level = 90 cache-level = <2>;
91 cache-unified; 91 cache-unified;
92 next-level-cac 92 next-level-cache = <&L3_0>;
93 }; 93 };
94 }; 94 };
95 95
96 CPU3: cpu@300 { 96 CPU3: cpu@300 {
97 device_type = "cpu"; 97 device_type = "cpu";
98 compatible = "qcom,kry 98 compatible = "qcom,kryo";
99 reg = <0x0 0x300>; 99 reg = <0x0 0x300>;
100 enable-method = "psci" 100 enable-method = "psci";
101 qcom,freq-domain = <&c 101 qcom,freq-domain = <&cpufreq_hw 0>;
102 next-level-cache = <&L 102 next-level-cache = <&L2_3>;
103 capacity-dmips-mhz = < 103 capacity-dmips-mhz = <1024>;
104 dynamic-power-coeffici 104 dynamic-power-coefficient = <100>;
105 L2_3: l2-cache { 105 L2_3: l2-cache {
106 compatible = " 106 compatible = "cache";
107 cache-level = 107 cache-level = <2>;
108 cache-unified; 108 cache-unified;
109 next-level-cac 109 next-level-cache = <&L3_0>;
110 }; 110 };
111 }; 111 };
112 112
113 CPU4: cpu@10000 { 113 CPU4: cpu@10000 {
114 device_type = "cpu"; 114 device_type = "cpu";
115 compatible = "qcom,kry 115 compatible = "qcom,kryo";
116 reg = <0x0 0x10000>; 116 reg = <0x0 0x10000>;
117 enable-method = "psci" 117 enable-method = "psci";
118 qcom,freq-domain = <&c 118 qcom,freq-domain = <&cpufreq_hw 1>;
119 next-level-cache = <&L 119 next-level-cache = <&L2_4>;
120 capacity-dmips-mhz = < 120 capacity-dmips-mhz = <1024>;
121 dynamic-power-coeffici 121 dynamic-power-coefficient = <100>;
122 L2_4: l2-cache { 122 L2_4: l2-cache {
123 compatible = " 123 compatible = "cache";
124 cache-level = 124 cache-level = <2>;
125 cache-unified; 125 cache-unified;
126 next-level-cac 126 next-level-cache = <&L3_1>;
127 L3_1: l3-cache 127 L3_1: l3-cache {
128 compat 128 compatible = "cache";
129 cache- 129 cache-level = <3>;
130 cache- 130 cache-unified;
131 }; 131 };
132 132
133 }; 133 };
134 }; 134 };
135 135
136 CPU5: cpu@10100 { 136 CPU5: cpu@10100 {
137 device_type = "cpu"; 137 device_type = "cpu";
138 compatible = "qcom,kry 138 compatible = "qcom,kryo";
139 reg = <0x0 0x10100>; 139 reg = <0x0 0x10100>;
140 enable-method = "psci" 140 enable-method = "psci";
141 qcom,freq-domain = <&c 141 qcom,freq-domain = <&cpufreq_hw 1>;
142 next-level-cache = <&L 142 next-level-cache = <&L2_5>;
143 capacity-dmips-mhz = < 143 capacity-dmips-mhz = <1024>;
144 dynamic-power-coeffici 144 dynamic-power-coefficient = <100>;
145 L2_5: l2-cache { 145 L2_5: l2-cache {
146 compatible = " 146 compatible = "cache";
147 cache-level = 147 cache-level = <2>;
148 cache-unified; 148 cache-unified;
149 next-level-cac 149 next-level-cache = <&L3_1>;
150 }; 150 };
151 }; 151 };
152 152
153 CPU6: cpu@10200 { 153 CPU6: cpu@10200 {
154 device_type = "cpu"; 154 device_type = "cpu";
155 compatible = "qcom,kry 155 compatible = "qcom,kryo";
156 reg = <0x0 0x10200>; 156 reg = <0x0 0x10200>;
157 enable-method = "psci" 157 enable-method = "psci";
158 qcom,freq-domain = <&c 158 qcom,freq-domain = <&cpufreq_hw 1>;
159 next-level-cache = <&L 159 next-level-cache = <&L2_6>;
160 capacity-dmips-mhz = < 160 capacity-dmips-mhz = <1024>;
161 dynamic-power-coeffici 161 dynamic-power-coefficient = <100>;
162 L2_6: l2-cache { 162 L2_6: l2-cache {
163 compatible = " 163 compatible = "cache";
164 cache-level = 164 cache-level = <2>;
165 cache-unified; 165 cache-unified;
166 next-level-cac 166 next-level-cache = <&L3_1>;
167 }; 167 };
168 }; 168 };
169 169
170 CPU7: cpu@10300 { 170 CPU7: cpu@10300 {
171 device_type = "cpu"; 171 device_type = "cpu";
172 compatible = "qcom,kry 172 compatible = "qcom,kryo";
173 reg = <0x0 0x10300>; 173 reg = <0x0 0x10300>;
174 enable-method = "psci" 174 enable-method = "psci";
175 qcom,freq-domain = <&c 175 qcom,freq-domain = <&cpufreq_hw 1>;
176 next-level-cache = <&L 176 next-level-cache = <&L2_7>;
177 capacity-dmips-mhz = < 177 capacity-dmips-mhz = <1024>;
178 dynamic-power-coeffici 178 dynamic-power-coefficient = <100>;
179 L2_7: l2-cache { 179 L2_7: l2-cache {
180 compatible = " 180 compatible = "cache";
181 cache-level = 181 cache-level = <2>;
182 cache-unified; 182 cache-unified;
183 next-level-cac 183 next-level-cache = <&L3_1>;
184 }; 184 };
185 }; 185 };
186 186
187 cpu-map { 187 cpu-map {
188 cluster0 { 188 cluster0 {
189 core0 { 189 core0 {
190 cpu = 190 cpu = <&CPU0>;
191 }; 191 };
192 192
193 core1 { 193 core1 {
194 cpu = 194 cpu = <&CPU1>;
195 }; 195 };
196 196
197 core2 { 197 core2 {
198 cpu = 198 cpu = <&CPU2>;
199 }; 199 };
200 200
201 core3 { 201 core3 {
202 cpu = 202 cpu = <&CPU3>;
203 }; 203 };
204 }; 204 };
205 205
206 cluster1 { 206 cluster1 {
207 core0 { 207 core0 {
208 cpu = 208 cpu = <&CPU4>;
209 }; 209 };
210 210
211 core1 { 211 core1 {
212 cpu = 212 cpu = <&CPU5>;
213 }; 213 };
214 214
215 core2 { 215 core2 {
216 cpu = 216 cpu = <&CPU6>;
217 }; 217 };
218 218
219 core3 { 219 core3 {
220 cpu = 220 cpu = <&CPU7>;
221 }; 221 };
222 }; 222 };
223 }; 223 };
224 224
225 idle-states { 225 idle-states {
226 entry-method = "psci"; 226 entry-method = "psci";
227 227
228 GOLD_CPU_SLEEP_0: cpu- 228 GOLD_CPU_SLEEP_0: cpu-sleep-0 {
229 compatible = " 229 compatible = "arm,idle-state";
230 idle-state-nam 230 idle-state-name = "gold-power-collapse";
231 arm,psci-suspe 231 arm,psci-suspend-param = <0x40000003>;
232 entry-latency- 232 entry-latency-us = <549>;
233 exit-latency-u 233 exit-latency-us = <901>;
234 min-residency- 234 min-residency-us = <1774>;
235 local-timer-st 235 local-timer-stop;
236 }; 236 };
237 237
238 GOLD_RAIL_CPU_SLEEP_0: 238 GOLD_RAIL_CPU_SLEEP_0: cpu-sleep-1 {
239 compatible = " 239 compatible = "arm,idle-state";
240 idle-state-nam 240 idle-state-name = "gold-rail-power-collapse";
241 arm,psci-suspe 241 arm,psci-suspend-param = <0x40000004>;
242 entry-latency- 242 entry-latency-us = <702>;
243 exit-latency-u 243 exit-latency-us = <1061>;
244 min-residency- 244 min-residency-us = <4488>;
245 local-timer-st 245 local-timer-stop;
246 }; 246 };
247 }; 247 };
248 248
249 domain-idle-states { 249 domain-idle-states {
250 CLUSTER_SLEEP_GOLD: cl 250 CLUSTER_SLEEP_GOLD: cluster-sleep-0 {
251 compatible = " 251 compatible = "domain-idle-state";
252 arm,psci-suspe 252 arm,psci-suspend-param = <0x41000044>;
253 entry-latency- 253 entry-latency-us = <2752>;
254 exit-latency-u 254 exit-latency-us = <3048>;
255 min-residency- 255 min-residency-us = <6118>;
256 }; 256 };
257 257
258 CLUSTER_SLEEP_APSS_RSC 258 CLUSTER_SLEEP_APSS_RSC_PC: cluster-sleep-1 {
259 compatible = " 259 compatible = "domain-idle-state";
260 arm,psci-suspe 260 arm,psci-suspend-param = <0x42000144>;
261 entry-latency- 261 entry-latency-us = <3263>;
262 exit-latency-u 262 exit-latency-us = <6562>;
263 min-residency- 263 min-residency-us = <9987>;
264 }; 264 };
265 }; 265 };
266 }; 266 };
267 267
268 dummy-sink { 268 dummy-sink {
269 compatible = "arm,coresight-du 269 compatible = "arm,coresight-dummy-sink";
270 270
271 in-ports { 271 in-ports {
272 port { 272 port {
273 eud_in: endpoi 273 eud_in: endpoint {
274 remote 274 remote-endpoint =
275 <&swao 275 <&swao_rep_out1>;
276 }; 276 };
277 }; 277 };
278 }; 278 };
279 }; 279 };
280 280
281 firmware { 281 firmware {
282 scm { 282 scm {
283 compatible = "qcom,scm 283 compatible = "qcom,scm-sa8775p", "qcom,scm";
284 memory-region = <&tz_f 284 memory-region = <&tz_ffi_mem>;
285 }; 285 };
286 }; 286 };
287 287
288 aggre1_noc: interconnect-aggre1-noc { 288 aggre1_noc: interconnect-aggre1-noc {
289 compatible = "qcom,sa8775p-agg 289 compatible = "qcom,sa8775p-aggre1-noc";
290 #interconnect-cells = <2>; 290 #interconnect-cells = <2>;
291 qcom,bcm-voters = <&apps_bcm_v 291 qcom,bcm-voters = <&apps_bcm_voter>;
292 }; 292 };
293 293
294 aggre2_noc: interconnect-aggre2-noc { 294 aggre2_noc: interconnect-aggre2-noc {
295 compatible = "qcom,sa8775p-agg 295 compatible = "qcom,sa8775p-aggre2-noc";
296 #interconnect-cells = <2>; 296 #interconnect-cells = <2>;
297 qcom,bcm-voters = <&apps_bcm_v 297 qcom,bcm-voters = <&apps_bcm_voter>;
298 }; 298 };
299 299
300 clk_virt: interconnect-clk-virt { 300 clk_virt: interconnect-clk-virt {
301 compatible = "qcom,sa8775p-clk 301 compatible = "qcom,sa8775p-clk-virt";
302 #interconnect-cells = <2>; 302 #interconnect-cells = <2>;
303 qcom,bcm-voters = <&apps_bcm_v 303 qcom,bcm-voters = <&apps_bcm_voter>;
304 }; 304 };
305 305
306 config_noc: interconnect-config-noc { 306 config_noc: interconnect-config-noc {
307 compatible = "qcom,sa8775p-con 307 compatible = "qcom,sa8775p-config-noc";
308 #interconnect-cells = <2>; 308 #interconnect-cells = <2>;
309 qcom,bcm-voters = <&apps_bcm_v 309 qcom,bcm-voters = <&apps_bcm_voter>;
310 }; 310 };
311 311
312 dc_noc: interconnect-dc-noc { 312 dc_noc: interconnect-dc-noc {
313 compatible = "qcom,sa8775p-dc- 313 compatible = "qcom,sa8775p-dc-noc";
314 #interconnect-cells = <2>; 314 #interconnect-cells = <2>;
315 qcom,bcm-voters = <&apps_bcm_v 315 qcom,bcm-voters = <&apps_bcm_voter>;
316 }; 316 };
317 317
318 gem_noc: interconnect-gem-noc { 318 gem_noc: interconnect-gem-noc {
319 compatible = "qcom,sa8775p-gem 319 compatible = "qcom,sa8775p-gem-noc";
320 #interconnect-cells = <2>; 320 #interconnect-cells = <2>;
321 qcom,bcm-voters = <&apps_bcm_v 321 qcom,bcm-voters = <&apps_bcm_voter>;
322 }; 322 };
323 323
324 gpdsp_anoc: interconnect-gpdsp-anoc { 324 gpdsp_anoc: interconnect-gpdsp-anoc {
325 compatible = "qcom,sa8775p-gpd 325 compatible = "qcom,sa8775p-gpdsp-anoc";
326 #interconnect-cells = <2>; 326 #interconnect-cells = <2>;
327 qcom,bcm-voters = <&apps_bcm_v 327 qcom,bcm-voters = <&apps_bcm_voter>;
328 }; 328 };
329 329
330 lpass_ag_noc: interconnect-lpass-ag-no 330 lpass_ag_noc: interconnect-lpass-ag-noc {
331 compatible = "qcom,sa8775p-lpa 331 compatible = "qcom,sa8775p-lpass-ag-noc";
332 #interconnect-cells = <2>; 332 #interconnect-cells = <2>;
333 qcom,bcm-voters = <&apps_bcm_v 333 qcom,bcm-voters = <&apps_bcm_voter>;
334 }; 334 };
335 335
336 mc_virt: interconnect-mc-virt { 336 mc_virt: interconnect-mc-virt {
337 compatible = "qcom,sa8775p-mc- 337 compatible = "qcom,sa8775p-mc-virt";
338 #interconnect-cells = <2>; 338 #interconnect-cells = <2>;
339 qcom,bcm-voters = <&apps_bcm_v 339 qcom,bcm-voters = <&apps_bcm_voter>;
340 }; 340 };
341 341
342 mmss_noc: interconnect-mmss-noc { 342 mmss_noc: interconnect-mmss-noc {
343 compatible = "qcom,sa8775p-mms 343 compatible = "qcom,sa8775p-mmss-noc";
344 #interconnect-cells = <2>; 344 #interconnect-cells = <2>;
345 qcom,bcm-voters = <&apps_bcm_v 345 qcom,bcm-voters = <&apps_bcm_voter>;
346 }; 346 };
347 347
348 nspa_noc: interconnect-nspa-noc { 348 nspa_noc: interconnect-nspa-noc {
349 compatible = "qcom,sa8775p-nsp 349 compatible = "qcom,sa8775p-nspa-noc";
350 #interconnect-cells = <2>; 350 #interconnect-cells = <2>;
351 qcom,bcm-voters = <&apps_bcm_v 351 qcom,bcm-voters = <&apps_bcm_voter>;
352 }; 352 };
353 353
354 nspb_noc: interconnect-nspb-noc { 354 nspb_noc: interconnect-nspb-noc {
355 compatible = "qcom,sa8775p-nsp 355 compatible = "qcom,sa8775p-nspb-noc";
356 #interconnect-cells = <2>; 356 #interconnect-cells = <2>;
357 qcom,bcm-voters = <&apps_bcm_v 357 qcom,bcm-voters = <&apps_bcm_voter>;
358 }; 358 };
359 359
360 pcie_anoc: interconnect-pcie-anoc { 360 pcie_anoc: interconnect-pcie-anoc {
361 compatible = "qcom,sa8775p-pci 361 compatible = "qcom,sa8775p-pcie-anoc";
362 #interconnect-cells = <2>; 362 #interconnect-cells = <2>;
363 qcom,bcm-voters = <&apps_bcm_v 363 qcom,bcm-voters = <&apps_bcm_voter>;
364 }; 364 };
365 365
366 system_noc: interconnect-system-noc { 366 system_noc: interconnect-system-noc {
367 compatible = "qcom,sa8775p-sys 367 compatible = "qcom,sa8775p-system-noc";
368 #interconnect-cells = <2>; 368 #interconnect-cells = <2>;
369 qcom,bcm-voters = <&apps_bcm_v 369 qcom,bcm-voters = <&apps_bcm_voter>;
370 }; 370 };
371 371
372 /* Will be updated by the bootloader. 372 /* Will be updated by the bootloader. */
373 memory@80000000 { 373 memory@80000000 {
374 device_type = "memory"; 374 device_type = "memory";
375 reg = <0x0 0x80000000 0x0 0x0> 375 reg = <0x0 0x80000000 0x0 0x0>;
376 }; 376 };
377 377
378 qup_opp_table_100mhz: opp-table-qup100 378 qup_opp_table_100mhz: opp-table-qup100mhz {
379 compatible = "operating-points 379 compatible = "operating-points-v2";
380 380
381 opp-100000000 { 381 opp-100000000 {
382 opp-hz = /bits/ 64 <10 382 opp-hz = /bits/ 64 <100000000>;
383 required-opps = <&rpmh 383 required-opps = <&rpmhpd_opp_svs_l1>;
384 }; 384 };
385 }; 385 };
386 386
387 pmu { 387 pmu {
388 compatible = "arm,armv8-pmuv3" 388 compatible = "arm,armv8-pmuv3";
389 interrupts = <GIC_PPI 7 IRQ_TY 389 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
390 }; 390 };
391 391
392 psci { 392 psci {
393 compatible = "arm,psci-1.0"; 393 compatible = "arm,psci-1.0";
394 method = "smc"; 394 method = "smc";
395 395
396 CPU_PD0: power-domain-cpu0 { 396 CPU_PD0: power-domain-cpu0 {
397 #power-domain-cells = 397 #power-domain-cells = <0>;
398 power-domains = <&CLUS 398 power-domains = <&CLUSTER_0_PD>;
399 domain-idle-states = < 399 domain-idle-states = <&GOLD_CPU_SLEEP_0>,
400 < 400 <&GOLD_RAIL_CPU_SLEEP_0>;
401 }; 401 };
402 402
403 CPU_PD1: power-domain-cpu1 { 403 CPU_PD1: power-domain-cpu1 {
404 #power-domain-cells = 404 #power-domain-cells = <0>;
405 power-domains = <&CLUS 405 power-domains = <&CLUSTER_0_PD>;
406 domain-idle-states = < 406 domain-idle-states = <&GOLD_CPU_SLEEP_0>,
407 < 407 <&GOLD_RAIL_CPU_SLEEP_0>;
408 }; 408 };
409 409
410 CPU_PD2: power-domain-cpu2 { 410 CPU_PD2: power-domain-cpu2 {
411 #power-domain-cells = 411 #power-domain-cells = <0>;
412 power-domains = <&CLUS 412 power-domains = <&CLUSTER_0_PD>;
413 domain-idle-states = < 413 domain-idle-states = <&GOLD_CPU_SLEEP_0>,
414 < 414 <&GOLD_RAIL_CPU_SLEEP_0>;
415 }; 415 };
416 416
417 CPU_PD3: power-domain-cpu3 { 417 CPU_PD3: power-domain-cpu3 {
418 #power-domain-cells = 418 #power-domain-cells = <0>;
419 power-domains = <&CLUS 419 power-domains = <&CLUSTER_0_PD>;
420 domain-idle-states = < 420 domain-idle-states = <&GOLD_CPU_SLEEP_0>,
421 < 421 <&GOLD_RAIL_CPU_SLEEP_0>;
422 }; 422 };
423 423
424 CPU_PD4: power-domain-cpu4 { 424 CPU_PD4: power-domain-cpu4 {
425 #power-domain-cells = 425 #power-domain-cells = <0>;
426 power-domains = <&CLUS 426 power-domains = <&CLUSTER_1_PD>;
427 domain-idle-states = < 427 domain-idle-states = <&GOLD_CPU_SLEEP_0>,
428 < 428 <&GOLD_RAIL_CPU_SLEEP_0>;
429 }; 429 };
430 430
431 CPU_PD5: power-domain-cpu5 { 431 CPU_PD5: power-domain-cpu5 {
432 #power-domain-cells = 432 #power-domain-cells = <0>;
433 power-domains = <&CLUS 433 power-domains = <&CLUSTER_1_PD>;
434 domain-idle-states = < 434 domain-idle-states = <&GOLD_CPU_SLEEP_0>,
435 < 435 <&GOLD_RAIL_CPU_SLEEP_0>;
436 }; 436 };
437 437
438 CPU_PD6: power-domain-cpu6 { 438 CPU_PD6: power-domain-cpu6 {
439 #power-domain-cells = 439 #power-domain-cells = <0>;
440 power-domains = <&CLUS 440 power-domains = <&CLUSTER_1_PD>;
441 domain-idle-states = < 441 domain-idle-states = <&GOLD_CPU_SLEEP_0>,
442 < 442 <&GOLD_RAIL_CPU_SLEEP_0>;
443 }; 443 };
444 444
445 CPU_PD7: power-domain-cpu7 { 445 CPU_PD7: power-domain-cpu7 {
446 #power-domain-cells = 446 #power-domain-cells = <0>;
447 power-domains = <&CLUS 447 power-domains = <&CLUSTER_1_PD>;
448 domain-idle-states = < 448 domain-idle-states = <&GOLD_CPU_SLEEP_0>,
449 < 449 <&GOLD_RAIL_CPU_SLEEP_0>;
450 }; 450 };
451 451
452 CLUSTER_0_PD: power-domain-clu 452 CLUSTER_0_PD: power-domain-cluster0 {
453 #power-domain-cells = 453 #power-domain-cells = <0>;
454 power-domains = <&CLUS 454 power-domains = <&CLUSTER_2_PD>;
455 domain-idle-states = < 455 domain-idle-states = <&CLUSTER_SLEEP_GOLD>;
456 }; 456 };
457 457
458 CLUSTER_1_PD: power-domain-clu 458 CLUSTER_1_PD: power-domain-cluster1 {
459 #power-domain-cells = 459 #power-domain-cells = <0>;
460 power-domains = <&CLUS 460 power-domains = <&CLUSTER_2_PD>;
461 domain-idle-states = < 461 domain-idle-states = <&CLUSTER_SLEEP_GOLD>;
462 }; 462 };
463 463
464 CLUSTER_2_PD: power-domain-clu 464 CLUSTER_2_PD: power-domain-cluster2 {
465 #power-domain-cells = 465 #power-domain-cells = <0>;
466 domain-idle-states = < 466 domain-idle-states = <&CLUSTER_SLEEP_APSS_RSC_PC>;
467 }; 467 };
468 }; 468 };
469 469
470 reserved-memory { 470 reserved-memory {
471 #address-cells = <2>; 471 #address-cells = <2>;
472 #size-cells = <2>; 472 #size-cells = <2>;
473 ranges; 473 ranges;
474 474
475 sail_ss_mem: sail-ss@80000000 475 sail_ss_mem: sail-ss@80000000 {
476 reg = <0x0 0x80000000 476 reg = <0x0 0x80000000 0x0 0x10000000>;
477 no-map; 477 no-map;
478 }; 478 };
479 479
480 hyp_mem: hyp@90000000 { 480 hyp_mem: hyp@90000000 {
481 reg = <0x0 0x90000000 481 reg = <0x0 0x90000000 0x0 0x600000>;
482 no-map; 482 no-map;
483 }; 483 };
484 484
485 xbl_boot_mem: xbl-boot@9060000 485 xbl_boot_mem: xbl-boot@90600000 {
486 reg = <0x0 0x90600000 486 reg = <0x0 0x90600000 0x0 0x200000>;
487 no-map; 487 no-map;
488 }; 488 };
489 489
490 aop_image_mem: aop-image@90800 490 aop_image_mem: aop-image@90800000 {
491 reg = <0x0 0x90800000 491 reg = <0x0 0x90800000 0x0 0x60000>;
492 no-map; 492 no-map;
493 }; 493 };
494 494
495 aop_cmd_db_mem: aop-cmd-db@908 495 aop_cmd_db_mem: aop-cmd-db@90860000 {
496 compatible = "qcom,cmd 496 compatible = "qcom,cmd-db";
497 reg = <0x0 0x90860000 497 reg = <0x0 0x90860000 0x0 0x20000>;
498 no-map; 498 no-map;
499 }; 499 };
500 500
501 uefi_log: uefi-log@908b0000 { 501 uefi_log: uefi-log@908b0000 {
502 reg = <0x0 0x908b0000 502 reg = <0x0 0x908b0000 0x0 0x10000>;
503 no-map; 503 no-map;
504 }; 504 };
505 505
506 ddr_training_checksum: ddr-tra 506 ddr_training_checksum: ddr-training-checksum@908c0000 {
507 reg = <0x0 0x908c0000 507 reg = <0x0 0x908c0000 0x0 0x1000>;
508 no-map; 508 no-map;
509 }; 509 };
510 510
511 reserved_mem: reserved@908f000 511 reserved_mem: reserved@908f0000 {
512 reg = <0x0 0x908f0000 512 reg = <0x0 0x908f0000 0x0 0xe000>;
513 no-map; 513 no-map;
514 }; 514 };
515 515
516 secdata_apss_mem: secdata-apss 516 secdata_apss_mem: secdata-apss@908fe000 {
517 reg = <0x0 0x908fe000 517 reg = <0x0 0x908fe000 0x0 0x2000>;
518 no-map; 518 no-map;
519 }; 519 };
520 520
521 smem_mem: smem@90900000 { 521 smem_mem: smem@90900000 {
522 compatible = "qcom,sme 522 compatible = "qcom,smem";
523 reg = <0x0 0x90900000 523 reg = <0x0 0x90900000 0x0 0x200000>;
524 no-map; 524 no-map;
525 hwlocks = <&tcsr_mutex 525 hwlocks = <&tcsr_mutex 3>;
526 }; 526 };
527 527
528 tz_sail_mailbox_mem: tz-sail-m 528 tz_sail_mailbox_mem: tz-sail-mailbox@90c00000 {
529 reg = <0x0 0x90c00000 529 reg = <0x0 0x90c00000 0x0 0x100000>;
530 no-map; 530 no-map;
531 }; 531 };
532 532
533 sail_mailbox_mem: sail-ss@90d0 533 sail_mailbox_mem: sail-ss@90d00000 {
534 reg = <0x0 0x90d00000 534 reg = <0x0 0x90d00000 0x0 0x100000>;
535 no-map; 535 no-map;
536 }; 536 };
537 537
538 sail_ota_mem: sail-ss@90e00000 538 sail_ota_mem: sail-ss@90e00000 {
539 reg = <0x0 0x90e00000 539 reg = <0x0 0x90e00000 0x0 0x300000>;
540 no-map; 540 no-map;
541 }; 541 };
542 542
543 aoss_backup_mem: aoss-backup@9 543 aoss_backup_mem: aoss-backup@91b00000 {
544 reg = <0x0 0x91b00000 544 reg = <0x0 0x91b00000 0x0 0x40000>;
545 no-map; 545 no-map;
546 }; 546 };
547 547
548 cpucp_backup_mem: cpucp-backup 548 cpucp_backup_mem: cpucp-backup@91b40000 {
549 reg = <0x0 0x91b40000 549 reg = <0x0 0x91b40000 0x0 0x40000>;
550 no-map; 550 no-map;
551 }; 551 };
552 552
553 tz_config_backup_mem: tz-confi 553 tz_config_backup_mem: tz-config-backup@91b80000 {
554 reg = <0x0 0x91b80000 554 reg = <0x0 0x91b80000 0x0 0x10000>;
555 no-map; 555 no-map;
556 }; 556 };
557 557
558 ddr_training_data_mem: ddr-tra 558 ddr_training_data_mem: ddr-training-data@91b90000 {
559 reg = <0x0 0x91b90000 559 reg = <0x0 0x91b90000 0x0 0x10000>;
560 no-map; 560 no-map;
561 }; 561 };
562 562
563 cdt_data_backup_mem: cdt-data- 563 cdt_data_backup_mem: cdt-data-backup@91ba0000 {
564 reg = <0x0 0x91ba0000 564 reg = <0x0 0x91ba0000 0x0 0x1000>;
565 no-map; 565 no-map;
566 }; 566 };
567 567
568 tz_ffi_mem: tz-ffi@91c00000 { 568 tz_ffi_mem: tz-ffi@91c00000 {
569 compatible = "shared-d 569 compatible = "shared-dma-pool";
570 reg = <0x0 0x91c00000 570 reg = <0x0 0x91c00000 0x0 0x1400000>;
571 no-map; 571 no-map;
572 }; 572 };
573 573
574 lpass_machine_learning_mem: lp 574 lpass_machine_learning_mem: lpass-machine-learning@93b00000 {
575 reg = <0x0 0x93b00000 575 reg = <0x0 0x93b00000 0x0 0xf00000>;
576 no-map; 576 no-map;
577 }; 577 };
578 578
579 adsp_rpc_remote_heap_mem: adsp 579 adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@94a00000 {
580 reg = <0x0 0x94a00000 580 reg = <0x0 0x94a00000 0x0 0x800000>;
581 no-map; 581 no-map;
582 }; 582 };
583 583
584 pil_camera_mem: pil-camera@952 584 pil_camera_mem: pil-camera@95200000 {
585 reg = <0x0 0x95200000 585 reg = <0x0 0x95200000 0x0 0x500000>;
586 no-map; 586 no-map;
587 }; 587 };
588 588
589 pil_adsp_mem: pil-adsp@95c0000 589 pil_adsp_mem: pil-adsp@95c00000 {
590 reg = <0x0 0x95c00000 590 reg = <0x0 0x95c00000 0x0 0x1e00000>;
591 no-map; 591 no-map;
592 }; 592 };
593 593
594 pil_gdsp0_mem: pil-gdsp0@97b00 594 pil_gdsp0_mem: pil-gdsp0@97b00000 {
595 reg = <0x0 0x97b00000 595 reg = <0x0 0x97b00000 0x0 0x1e00000>;
596 no-map; 596 no-map;
597 }; 597 };
598 598
599 pil_gdsp1_mem: pil-gdsp1@99900 599 pil_gdsp1_mem: pil-gdsp1@99900000 {
600 reg = <0x0 0x99900000 600 reg = <0x0 0x99900000 0x0 0x1e00000>;
601 no-map; 601 no-map;
602 }; 602 };
603 603
604 pil_cdsp0_mem: pil-cdsp0@9b800 604 pil_cdsp0_mem: pil-cdsp0@9b800000 {
605 reg = <0x0 0x9b800000 605 reg = <0x0 0x9b800000 0x0 0x1e00000>;
606 no-map; 606 no-map;
607 }; 607 };
608 608
609 pil_gpu_mem: pil-gpu@9d600000 609 pil_gpu_mem: pil-gpu@9d600000 {
610 reg = <0x0 0x9d600000 610 reg = <0x0 0x9d600000 0x0 0x2000>;
611 no-map; 611 no-map;
612 }; 612 };
613 613
614 pil_cdsp1_mem: pil-cdsp1@9d700 614 pil_cdsp1_mem: pil-cdsp1@9d700000 {
615 reg = <0x0 0x9d700000 615 reg = <0x0 0x9d700000 0x0 0x1e00000>;
616 no-map; 616 no-map;
617 }; 617 };
618 618
619 pil_cvp_mem: pil-cvp@9f500000 619 pil_cvp_mem: pil-cvp@9f500000 {
620 reg = <0x0 0x9f500000 620 reg = <0x0 0x9f500000 0x0 0x700000>;
621 no-map; 621 no-map;
622 }; 622 };
623 623
624 pil_video_mem: pil-video@9fc00 624 pil_video_mem: pil-video@9fc00000 {
625 reg = <0x0 0x9fc00000 625 reg = <0x0 0x9fc00000 0x0 0x700000>;
626 no-map; 626 no-map;
627 }; 627 };
628 628
629 audio_mdf_mem: audio-mdf-regio 629 audio_mdf_mem: audio-mdf-region@ae000000 {
630 reg = <0x0 0xae000000 630 reg = <0x0 0xae000000 0x0 0x1000000>;
631 no-map; 631 no-map;
632 }; 632 };
633 633
634 firmware_mem: firmware-region@ 634 firmware_mem: firmware-region@b0000000 {
635 reg = <0x0 0xb0000000 635 reg = <0x0 0xb0000000 0x0 0x800000>;
636 no-map; 636 no-map;
637 }; 637 };
638 638
639 hyptz_reserved_mem: hyptz-rese 639 hyptz_reserved_mem: hyptz-reserved@beb00000 {
640 reg = <0x0 0xbeb00000 640 reg = <0x0 0xbeb00000 0x0 0x11500000>;
641 no-map; 641 no-map;
642 }; 642 };
643 643
644 scmi_mem: scmi-region@d0000000 644 scmi_mem: scmi-region@d0000000 {
645 reg = <0x0 0xd0000000 645 reg = <0x0 0xd0000000 0x0 0x40000>;
646 no-map; 646 no-map;
647 }; 647 };
648 648
649 firmware_logs_mem: firmware-lo 649 firmware_logs_mem: firmware-logs@d0040000 {
650 reg = <0x0 0xd0040000 650 reg = <0x0 0xd0040000 0x0 0x10000>;
651 no-map; 651 no-map;
652 }; 652 };
653 653
654 firmware_audio_mem: firmware-a 654 firmware_audio_mem: firmware-audio@d0050000 {
655 reg = <0x0 0xd0050000 655 reg = <0x0 0xd0050000 0x0 0x4000>;
656 no-map; 656 no-map;
657 }; 657 };
658 658
659 firmware_reserved_mem: firmwar 659 firmware_reserved_mem: firmware-reserved@d0054000 {
660 reg = <0x0 0xd0054000 660 reg = <0x0 0xd0054000 0x0 0x9c000>;
661 no-map; 661 no-map;
662 }; 662 };
663 663
664 firmware_quantum_test_mem: fir 664 firmware_quantum_test_mem: firmware-quantum-test@d00f0000 {
665 reg = <0x0 0xd00f0000 665 reg = <0x0 0xd00f0000 0x0 0x10000>;
666 no-map; 666 no-map;
667 }; 667 };
668 668
669 tags_mem: tags@d0100000 { 669 tags_mem: tags@d0100000 {
670 reg = <0x0 0xd0100000 670 reg = <0x0 0xd0100000 0x0 0x1200000>;
671 no-map; 671 no-map;
672 }; 672 };
673 673
674 qtee_mem: qtee@d1300000 { 674 qtee_mem: qtee@d1300000 {
675 reg = <0x0 0xd1300000 675 reg = <0x0 0xd1300000 0x0 0x500000>;
676 no-map; 676 no-map;
677 }; 677 };
678 678
679 deepsleep_backup_mem: deepslee 679 deepsleep_backup_mem: deepsleep-backup@d1800000 {
680 reg = <0x0 0xd1800000 680 reg = <0x0 0xd1800000 0x0 0x100000>;
681 no-map; 681 no-map;
682 }; 682 };
683 683
684 trusted_apps_mem: trusted-apps 684 trusted_apps_mem: trusted-apps@d1900000 {
685 reg = <0x0 0xd1900000 685 reg = <0x0 0xd1900000 0x0 0x3800000>;
686 no-map; 686 no-map;
687 }; 687 };
688 688
689 tz_stat_mem: tz-stat@db100000 689 tz_stat_mem: tz-stat@db100000 {
690 reg = <0x0 0xdb100000 690 reg = <0x0 0xdb100000 0x0 0x100000>;
691 no-map; 691 no-map;
692 }; 692 };
693 693
694 cpucp_fw_mem: cpucp-fw@db20000 694 cpucp_fw_mem: cpucp-fw@db200000 {
695 reg = <0x0 0xdb200000 695 reg = <0x0 0xdb200000 0x0 0x100000>;
696 no-map; 696 no-map;
697 }; 697 };
698 }; 698 };
699 699
700 smp2p-adsp { 700 smp2p-adsp {
701 compatible = "qcom,smp2p"; 701 compatible = "qcom,smp2p";
702 qcom,smem = <443>, <429>; 702 qcom,smem = <443>, <429>;
703 interrupts-extended = <&ipcc I 703 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
704 I 704 IPCC_MPROC_SIGNAL_SMP2P
705 I 705 IRQ_TYPE_EDGE_RISING>;
706 mboxes = <&ipcc IPCC_CLIENT_LP 706 mboxes = <&ipcc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_SMP2P>;
707 707
708 qcom,local-pid = <0>; 708 qcom,local-pid = <0>;
709 qcom,remote-pid = <2>; 709 qcom,remote-pid = <2>;
710 710
711 smp2p_adsp_out: master-kernel 711 smp2p_adsp_out: master-kernel {
712 qcom,entry-name = "mas 712 qcom,entry-name = "master-kernel";
713 #qcom,smem-state-cells 713 #qcom,smem-state-cells = <1>;
714 }; 714 };
715 715
716 smp2p_adsp_in: slave-kernel { 716 smp2p_adsp_in: slave-kernel {
717 qcom,entry-name = "sla 717 qcom,entry-name = "slave-kernel";
718 interrupt-controller; 718 interrupt-controller;
719 #interrupt-cells = <2> 719 #interrupt-cells = <2>;
720 }; 720 };
721 }; 721 };
722 722
723 smp2p-cdsp0 { 723 smp2p-cdsp0 {
724 compatible = "qcom,smp2p"; 724 compatible = "qcom,smp2p";
725 qcom,smem = <94>, <432>; 725 qcom,smem = <94>, <432>;
726 interrupts-extended = <&ipcc I 726 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
727 I 727 IPCC_MPROC_SIGNAL_SMP2P
728 I 728 IRQ_TYPE_EDGE_RISING>;
729 mboxes = <&ipcc IPCC_CLIENT_CD 729 mboxes = <&ipcc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P>;
730 730
731 qcom,local-pid = <0>; 731 qcom,local-pid = <0>;
732 qcom,remote-pid = <5>; 732 qcom,remote-pid = <5>;
733 733
734 smp2p_cdsp0_out: master-kernel 734 smp2p_cdsp0_out: master-kernel {
735 qcom,entry-name = "mas 735 qcom,entry-name = "master-kernel";
736 #qcom,smem-state-cells 736 #qcom,smem-state-cells = <1>;
737 }; 737 };
738 738
739 smp2p_cdsp0_in: slave-kernel { 739 smp2p_cdsp0_in: slave-kernel {
740 qcom,entry-name = "sla 740 qcom,entry-name = "slave-kernel";
741 interrupt-controller; 741 interrupt-controller;
742 #interrupt-cells = <2> 742 #interrupt-cells = <2>;
743 }; 743 };
744 }; 744 };
745 745
746 smp2p-cdsp1 { 746 smp2p-cdsp1 {
747 compatible = "qcom,smp2p"; 747 compatible = "qcom,smp2p";
748 qcom,smem = <617>, <616>; 748 qcom,smem = <617>, <616>;
749 interrupts-extended = <&ipcc I 749 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1
750 I 750 IPCC_MPROC_SIGNAL_SMP2P
751 I 751 IRQ_TYPE_EDGE_RISING>;
752 mboxes = <&ipcc IPCC_CLIENT_NS 752 mboxes = <&ipcc IPCC_CLIENT_NSP1 IPCC_MPROC_SIGNAL_SMP2P>;
753 753
754 qcom,local-pid = <0>; 754 qcom,local-pid = <0>;
755 qcom,remote-pid = <12>; 755 qcom,remote-pid = <12>;
756 756
757 smp2p_cdsp1_out: master-kernel 757 smp2p_cdsp1_out: master-kernel {
758 qcom,entry-name = "mas 758 qcom,entry-name = "master-kernel";
759 #qcom,smem-state-cells 759 #qcom,smem-state-cells = <1>;
760 }; 760 };
761 761
762 smp2p_cdsp1_in: slave-kernel { 762 smp2p_cdsp1_in: slave-kernel {
763 qcom,entry-name = "sla 763 qcom,entry-name = "slave-kernel";
764 interrupt-controller; 764 interrupt-controller;
765 #interrupt-cells = <2> 765 #interrupt-cells = <2>;
766 }; 766 };
767 }; 767 };
768 768
769 smp2p-gpdsp0 { 769 smp2p-gpdsp0 {
770 compatible = "qcom,smp2p"; 770 compatible = "qcom,smp2p";
771 qcom,smem = <617>, <616>; 771 qcom,smem = <617>, <616>;
772 interrupts-extended = <&ipcc I 772 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP0
773 I 773 IPCC_MPROC_SIGNAL_SMP2P
774 I 774 IRQ_TYPE_EDGE_RISING>;
775 mboxes = <&ipcc IPCC_CLIENT_GP 775 mboxes = <&ipcc IPCC_CLIENT_GPDSP0 IPCC_MPROC_SIGNAL_SMP2P>;
776 776
777 qcom,local-pid = <0>; 777 qcom,local-pid = <0>;
778 qcom,remote-pid = <17>; 778 qcom,remote-pid = <17>;
779 779
780 smp2p_gpdsp0_out: master-kerne 780 smp2p_gpdsp0_out: master-kernel {
781 qcom,entry-name = "mas 781 qcom,entry-name = "master-kernel";
782 #qcom,smem-state-cells 782 #qcom,smem-state-cells = <1>;
783 }; 783 };
784 784
785 smp2p_gpdsp0_in: slave-kernel 785 smp2p_gpdsp0_in: slave-kernel {
786 qcom,entry-name = "sla 786 qcom,entry-name = "slave-kernel";
787 interrupt-controller; 787 interrupt-controller;
788 #interrupt-cells = <2> 788 #interrupt-cells = <2>;
789 }; 789 };
790 }; 790 };
791 791
792 smp2p-gpdsp1 { 792 smp2p-gpdsp1 {
793 compatible = "qcom,smp2p"; 793 compatible = "qcom,smp2p";
794 qcom,smem = <617>, <616>; 794 qcom,smem = <617>, <616>;
795 interrupts-extended = <&ipcc I 795 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP1
796 I 796 IPCC_MPROC_SIGNAL_SMP2P
797 I 797 IRQ_TYPE_EDGE_RISING>;
798 mboxes = <&ipcc IPCC_CLIENT_GP 798 mboxes = <&ipcc IPCC_CLIENT_GPDSP1 IPCC_MPROC_SIGNAL_SMP2P>;
799 799
800 qcom,local-pid = <0>; 800 qcom,local-pid = <0>;
801 qcom,remote-pid = <18>; 801 qcom,remote-pid = <18>;
802 802
803 smp2p_gpdsp1_out: master-kerne 803 smp2p_gpdsp1_out: master-kernel {
804 qcom,entry-name = "mas 804 qcom,entry-name = "master-kernel";
805 #qcom,smem-state-cells 805 #qcom,smem-state-cells = <1>;
806 }; 806 };
807 807
808 smp2p_gpdsp1_in: slave-kernel 808 smp2p_gpdsp1_in: slave-kernel {
809 qcom,entry-name = "sla 809 qcom,entry-name = "slave-kernel";
810 interrupt-controller; 810 interrupt-controller;
811 #interrupt-cells = <2> 811 #interrupt-cells = <2>;
812 }; 812 };
813 }; 813 };
814 814
815 soc: soc@0 { 815 soc: soc@0 {
816 compatible = "simple-bus"; 816 compatible = "simple-bus";
817 #address-cells = <2>; 817 #address-cells = <2>;
818 #size-cells = <2>; 818 #size-cells = <2>;
819 ranges = <0 0 0 0 0x10 0>; 819 ranges = <0 0 0 0 0x10 0>;
820 820
821 gcc: clock-controller@100000 { 821 gcc: clock-controller@100000 {
822 compatible = "qcom,sa8 822 compatible = "qcom,sa8775p-gcc";
823 reg = <0x0 0x00100000 823 reg = <0x0 0x00100000 0x0 0xc7018>;
824 #clock-cells = <1>; 824 #clock-cells = <1>;
825 #reset-cells = <1>; 825 #reset-cells = <1>;
826 #power-domain-cells = 826 #power-domain-cells = <1>;
827 clocks = <&rpmhcc RPMH 827 clocks = <&rpmhcc RPMH_CXO_CLK>,
828 <&sleep_clk>, 828 <&sleep_clk>,
829 <0>, 829 <0>,
830 <0>, 830 <0>,
831 <0>, 831 <0>,
832 <&usb_0_qmpph 832 <&usb_0_qmpphy>,
833 <&usb_1_qmpph 833 <&usb_1_qmpphy>,
834 <0>, 834 <0>,
835 <0>, 835 <0>,
836 <0>, 836 <0>,
837 <&pcie0_phy>, 837 <&pcie0_phy>,
838 <&pcie1_phy>, 838 <&pcie1_phy>,
839 <0>, 839 <0>,
840 <0>, 840 <0>,
841 <0>; 841 <0>;
842 power-domains = <&rpmh 842 power-domains = <&rpmhpd SA8775P_CX>;
843 }; 843 };
844 844
845 ipcc: mailbox@408000 { 845 ipcc: mailbox@408000 {
846 compatible = "qcom,sa8 846 compatible = "qcom,sa8775p-ipcc", "qcom,ipcc";
847 reg = <0x0 0x00408000 847 reg = <0x0 0x00408000 0x0 0x1000>;
848 interrupts = <GIC_SPI 848 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
849 interrupt-controller; 849 interrupt-controller;
850 #interrupt-cells = <3> 850 #interrupt-cells = <3>;
851 #mbox-cells = <2>; 851 #mbox-cells = <2>;
852 }; 852 };
853 853
854 qupv3_id_2: geniqup@8c0000 { 854 qupv3_id_2: geniqup@8c0000 {
855 compatible = "qcom,gen 855 compatible = "qcom,geni-se-qup";
856 reg = <0x0 0x008c0000 856 reg = <0x0 0x008c0000 0x0 0x6000>;
857 ranges; 857 ranges;
858 clocks = <&gcc GCC_QUP 858 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
859 <&gcc GCC_QUP 859 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
860 clock-names = "m-ahb", 860 clock-names = "m-ahb", "s-ahb";
861 iommus = <&apps_smmu 0 861 iommus = <&apps_smmu 0x5a3 0x0>;
862 #address-cells = <2>; 862 #address-cells = <2>;
863 #size-cells = <2>; 863 #size-cells = <2>;
864 status = "disabled"; 864 status = "disabled";
865 865
866 i2c14: i2c@880000 { 866 i2c14: i2c@880000 {
867 compatible = " 867 compatible = "qcom,geni-i2c";
868 reg = <0x0 0x8 868 reg = <0x0 0x880000 0x0 0x4000>;
869 #address-cells 869 #address-cells = <1>;
870 #size-cells = 870 #size-cells = <0>;
871 interrupts = < 871 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
872 clocks = <&gcc 872 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
873 clock-names = 873 clock-names = "se";
874 interconnects 874 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
875 875 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
876 876 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
877 877 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
878 878 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
879 879 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
880 interconnect-n 880 interconnect-names = "qup-core",
881 881 "qup-config",
882 882 "qup-memory";
883 power-domains 883 power-domains = <&rpmhpd SA8775P_CX>;
884 status = "disa 884 status = "disabled";
885 }; 885 };
886 886
887 spi14: spi@880000 { 887 spi14: spi@880000 {
888 compatible = " 888 compatible = "qcom,geni-spi";
889 reg = <0x0 0x8 889 reg = <0x0 0x880000 0x0 0x4000>;
890 #address-cells 890 #address-cells = <1>;
891 #size-cells = 891 #size-cells = <0>;
892 interrupts = < 892 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
893 clocks = <&gcc 893 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
894 clock-names = 894 clock-names = "se";
895 interconnects 895 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
896 896 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
897 897 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
898 898 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
899 899 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
900 900 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
901 interconnect-n 901 interconnect-names = "qup-core",
902 902 "qup-config",
903 903 "qup-memory";
904 power-domains 904 power-domains = <&rpmhpd SA8775P_CX>;
905 status = "disa 905 status = "disabled";
906 }; 906 };
907 907
908 i2c15: i2c@884000 { 908 i2c15: i2c@884000 {
909 compatible = " 909 compatible = "qcom,geni-i2c";
910 reg = <0x0 0x8 910 reg = <0x0 0x884000 0x0 0x4000>;
911 #address-cells 911 #address-cells = <1>;
912 #size-cells = 912 #size-cells = <0>;
913 interrupts = < 913 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
914 clocks = <&gcc 914 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
915 clock-names = 915 clock-names = "se";
916 interconnects 916 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
917 917 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
918 918 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
919 919 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
920 920 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
921 921 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
922 interconnect-n 922 interconnect-names = "qup-core",
923 923 "qup-config",
924 924 "qup-memory";
925 power-domains 925 power-domains = <&rpmhpd SA8775P_CX>;
926 status = "disa 926 status = "disabled";
927 }; 927 };
928 928
929 spi15: spi@884000 { 929 spi15: spi@884000 {
930 compatible = " 930 compatible = "qcom,geni-spi";
931 reg = <0x0 0x8 931 reg = <0x0 0x884000 0x0 0x4000>;
932 #address-cells 932 #address-cells = <1>;
933 #size-cells = 933 #size-cells = <0>;
934 interrupts = < 934 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
935 clocks = <&gcc 935 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
936 clock-names = 936 clock-names = "se";
937 interconnects 937 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
938 938 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
939 939 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
940 940 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
941 941 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
942 942 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
943 interconnect-n 943 interconnect-names = "qup-core",
944 944 "qup-config",
945 945 "qup-memory";
946 power-domains 946 power-domains = <&rpmhpd SA8775P_CX>;
947 status = "disa 947 status = "disabled";
948 }; 948 };
949 949
950 i2c16: i2c@888000 { 950 i2c16: i2c@888000 {
951 compatible = " 951 compatible = "qcom,geni-i2c";
952 reg = <0x0 0x8 952 reg = <0x0 0x888000 0x0 0x4000>;
953 #address-cells 953 #address-cells = <1>;
954 #size-cells = 954 #size-cells = <0>;
955 interrupts = < 955 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
956 clocks = <&gcc 956 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
957 clock-names = 957 clock-names = "se";
958 interconnects 958 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
959 959 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
960 960 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
961 961 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
962 962 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
963 963 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
964 interconnect-n 964 interconnect-names = "qup-core",
965 965 "qup-config",
966 966 "qup-memory";
967 power-domains 967 power-domains = <&rpmhpd SA8775P_CX>;
968 status = "disa 968 status = "disabled";
969 }; 969 };
970 970
971 spi16: spi@888000 { 971 spi16: spi@888000 {
972 compatible = " 972 compatible = "qcom,geni-spi";
973 reg = <0x0 0x0 973 reg = <0x0 0x00888000 0x0 0x4000>;
974 interrupts = < 974 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
975 clocks = <&gcc 975 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
976 clock-names = 976 clock-names = "se";
977 interconnects 977 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
978 978 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
979 979 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
980 980 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
981 981 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
982 982 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
983 interconnect-n 983 interconnect-names = "qup-core",
984 984 "qup-config",
985 985 "qup-memory";
986 power-domains 986 power-domains = <&rpmhpd SA8775P_CX>;
987 #address-cells 987 #address-cells = <1>;
988 #size-cells = 988 #size-cells = <0>;
989 status = "disa 989 status = "disabled";
990 }; 990 };
991 991
992 i2c17: i2c@88c000 { 992 i2c17: i2c@88c000 {
993 compatible = " 993 compatible = "qcom,geni-i2c";
994 reg = <0x0 0x8 994 reg = <0x0 0x88c000 0x0 0x4000>;
995 #address-cells 995 #address-cells = <1>;
996 #size-cells = 996 #size-cells = <0>;
997 interrupts = < 997 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
998 clocks = <&gcc 998 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
999 clock-names = 999 clock-names = "se";
1000 interconnects 1000 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1001 1001 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1002 1002 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1003 1003 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1004 1004 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1005 1005 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1006 interconnect- 1006 interconnect-names = "qup-core",
1007 1007 "qup-config",
1008 1008 "qup-memory";
1009 power-domains 1009 power-domains = <&rpmhpd SA8775P_CX>;
1010 status = "dis 1010 status = "disabled";
1011 }; 1011 };
1012 1012
1013 spi17: spi@88c000 { 1013 spi17: spi@88c000 {
1014 compatible = 1014 compatible = "qcom,geni-spi";
1015 reg = <0x0 0x 1015 reg = <0x0 0x88c000 0x0 0x4000>;
1016 #address-cell 1016 #address-cells = <1>;
1017 #size-cells = 1017 #size-cells = <0>;
1018 interrupts = 1018 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1019 clocks = <&gc 1019 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1020 clock-names = 1020 clock-names = "se";
1021 interconnects 1021 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1022 1022 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1023 1023 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1024 1024 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1025 1025 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1026 1026 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1027 interconnect- 1027 interconnect-names = "qup-core",
1028 1028 "qup-config",
1029 1029 "qup-memory";
1030 power-domains 1030 power-domains = <&rpmhpd SA8775P_CX>;
1031 status = "dis 1031 status = "disabled";
1032 }; 1032 };
1033 1033
1034 uart17: serial@88c000 1034 uart17: serial@88c000 {
1035 compatible = 1035 compatible = "qcom,geni-uart";
1036 reg = <0x0 0x 1036 reg = <0x0 0x0088c000 0x0 0x4000>;
1037 interrupts = 1037 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1038 clocks = <&gc 1038 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1039 clock-names = 1039 clock-names = "se";
1040 interconnects 1040 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1041 1041 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1042 1042 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1043 1043 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
1044 interconnect- 1044 interconnect-names = "qup-core", "qup-config";
1045 power-domains 1045 power-domains = <&rpmhpd SA8775P_CX>;
1046 status = "dis 1046 status = "disabled";
1047 }; 1047 };
1048 1048
1049 i2c18: i2c@890000 { 1049 i2c18: i2c@890000 {
1050 compatible = 1050 compatible = "qcom,geni-i2c";
1051 reg = <0x0 0x 1051 reg = <0x0 0x00890000 0x0 0x4000>;
1052 interrupts = 1052 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1053 clocks = <&gc 1053 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1054 clock-names = 1054 clock-names = "se";
1055 interconnects 1055 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1056 1056 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1057 1057 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1058 1058 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1059 1059 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1060 1060 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1061 interconnect- 1061 interconnect-names = "qup-core",
1062 1062 "qup-config",
1063 1063 "qup-memory";
1064 power-domains 1064 power-domains = <&rpmhpd SA8775P_CX>;
1065 #address-cell 1065 #address-cells = <1>;
1066 #size-cells = 1066 #size-cells = <0>;
1067 status = "dis 1067 status = "disabled";
1068 }; 1068 };
1069 1069
1070 spi18: spi@890000 { 1070 spi18: spi@890000 {
1071 compatible = 1071 compatible = "qcom,geni-spi";
1072 reg = <0x0 0x 1072 reg = <0x0 0x890000 0x0 0x4000>;
1073 #address-cell 1073 #address-cells = <1>;
1074 #size-cells = 1074 #size-cells = <0>;
1075 interrupts = 1075 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1076 clocks = <&gc 1076 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1077 clock-names = 1077 clock-names = "se";
1078 interconnects 1078 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1079 1079 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1080 1080 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1081 1081 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1082 1082 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1083 1083 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1084 interconnect- 1084 interconnect-names = "qup-core",
1085 1085 "qup-config",
1086 1086 "qup-memory";
1087 power-domains 1087 power-domains = <&rpmhpd SA8775P_CX>;
1088 status = "dis 1088 status = "disabled";
1089 }; 1089 };
1090 1090
1091 i2c19: i2c@894000 { 1091 i2c19: i2c@894000 {
1092 compatible = 1092 compatible = "qcom,geni-i2c";
1093 reg = <0x0 0x 1093 reg = <0x0 0x894000 0x0 0x4000>;
1094 #address-cell 1094 #address-cells = <1>;
1095 #size-cells = 1095 #size-cells = <0>;
1096 interrupts = 1096 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1097 clocks = <&gc 1097 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1098 clock-names = 1098 clock-names = "se";
1099 interconnects 1099 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1100 1100 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1101 1101 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1102 1102 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1103 1103 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1104 1104 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1105 interconnect- 1105 interconnect-names = "qup-core",
1106 1106 "qup-config",
1107 1107 "qup-memory";
1108 power-domains 1108 power-domains = <&rpmhpd SA8775P_CX>;
1109 status = "dis 1109 status = "disabled";
1110 }; 1110 };
1111 1111
1112 spi19: spi@894000 { 1112 spi19: spi@894000 {
1113 compatible = 1113 compatible = "qcom,geni-spi";
1114 reg = <0x0 0x 1114 reg = <0x0 0x894000 0x0 0x4000>;
1115 #address-cell 1115 #address-cells = <1>;
1116 #size-cells = 1116 #size-cells = <0>;
1117 interrupts = 1117 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1118 clocks = <&gc 1118 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1119 clock-names = 1119 clock-names = "se";
1120 interconnects 1120 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1121 1121 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1122 1122 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1123 1123 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1124 1124 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1125 1125 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1126 interconnect- 1126 interconnect-names = "qup-core",
1127 1127 "qup-config",
1128 1128 "qup-memory";
1129 power-domains 1129 power-domains = <&rpmhpd SA8775P_CX>;
1130 status = "dis 1130 status = "disabled";
1131 }; 1131 };
1132 1132
1133 i2c20: i2c@898000 { 1133 i2c20: i2c@898000 {
1134 compatible = 1134 compatible = "qcom,geni-i2c";
1135 reg = <0x0 0x 1135 reg = <0x0 0x898000 0x0 0x4000>;
1136 #address-cell 1136 #address-cells = <1>;
1137 #size-cells = 1137 #size-cells = <0>;
1138 interrupts = 1138 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>;
1139 clocks = <&gc 1139 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1140 clock-names = 1140 clock-names = "se";
1141 interconnects 1141 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1142 1142 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1143 1143 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1144 1144 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1145 1145 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1146 1146 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1147 interconnect- 1147 interconnect-names = "qup-core",
1148 1148 "qup-config",
1149 1149 "qup-memory";
1150 power-domains 1150 power-domains = <&rpmhpd SA8775P_CX>;
1151 status = "dis 1151 status = "disabled";
1152 }; 1152 };
1153 1153
1154 spi20: spi@898000 { 1154 spi20: spi@898000 {
1155 compatible = 1155 compatible = "qcom,geni-spi";
1156 reg = <0x0 0x 1156 reg = <0x0 0x898000 0x0 0x4000>;
1157 #address-cell 1157 #address-cells = <1>;
1158 #size-cells = 1158 #size-cells = <0>;
1159 interrupts = 1159 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>;
1160 clocks = <&gc 1160 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1161 clock-names = 1161 clock-names = "se";
1162 interconnects 1162 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1163 1163 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1164 1164 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1165 1165 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1166 1166 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1167 1167 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1168 interconnect- 1168 interconnect-names = "qup-core",
1169 1169 "qup-config",
1170 1170 "qup-memory";
1171 power-domains 1171 power-domains = <&rpmhpd SA8775P_CX>;
1172 status = "dis 1172 status = "disabled";
1173 }; 1173 };
1174 }; 1174 };
1175 1175
1176 qupv3_id_0: geniqup@9c0000 { 1176 qupv3_id_0: geniqup@9c0000 {
1177 compatible = "qcom,ge 1177 compatible = "qcom,geni-se-qup";
1178 reg = <0x0 0x9c0000 0 1178 reg = <0x0 0x9c0000 0x0 0x6000>;
1179 #address-cells = <2>; 1179 #address-cells = <2>;
1180 #size-cells = <2>; 1180 #size-cells = <2>;
1181 ranges; 1181 ranges;
1182 clock-names = "m-ahb" 1182 clock-names = "m-ahb", "s-ahb";
1183 clocks = <&gcc GCC_QU 1183 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1184 <&gcc GCC_QUP 1184 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1185 iommus = <&apps_smmu 1185 iommus = <&apps_smmu 0x403 0x0>;
1186 status = "disabled"; 1186 status = "disabled";
1187 1187
1188 i2c0: i2c@980000 { 1188 i2c0: i2c@980000 {
1189 compatible = 1189 compatible = "qcom,geni-i2c";
1190 reg = <0x0 0x 1190 reg = <0x0 0x980000 0x0 0x4000>;
1191 #address-cell 1191 #address-cells = <1>;
1192 #size-cells = 1192 #size-cells = <0>;
1193 interrupts = 1193 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>;
1194 clocks = <&gc 1194 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1195 clock-names = 1195 clock-names = "se";
1196 interconnects 1196 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1197 1197 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1198 1198 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1199 1199 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
1200 1200 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
1201 1201 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1202 interconnect- 1202 interconnect-names = "qup-core",
1203 1203 "qup-config",
1204 1204 "qup-memory";
1205 power-domains 1205 power-domains = <&rpmhpd SA8775P_CX>;
1206 status = "dis 1206 status = "disabled";
1207 }; 1207 };
1208 1208
1209 spi0: spi@980000 { 1209 spi0: spi@980000 {
1210 compatible = 1210 compatible = "qcom,geni-spi";
1211 reg = <0x0 0x 1211 reg = <0x0 0x980000 0x0 0x4000>;
1212 #address-cell 1212 #address-cells = <1>;
1213 #size-cells = 1213 #size-cells = <0>;
1214 interrupts = 1214 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>;
1215 clocks = <&gc 1215 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1216 clock-names = 1216 clock-names = "se";
1217 interconnects 1217 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1218 1218 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1219 1219 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1220 1220 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
1221 1221 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
1222 1222 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1223 interconnect- 1223 interconnect-names = "qup-core",
1224 1224 "qup-config",
1225 1225 "qup-memory";
1226 power-domains 1226 power-domains = <&rpmhpd SA8775P_CX>;
1227 status = "dis 1227 status = "disabled";
1228 }; 1228 };
1229 1229
1230 i2c1: i2c@984000 { 1230 i2c1: i2c@984000 {
1231 compatible = 1231 compatible = "qcom,geni-i2c";
1232 reg = <0x0 0x 1232 reg = <0x0 0x984000 0x0 0x4000>;
1233 #address-cell 1233 #address-cells = <1>;
1234 #size-cells = 1234 #size-cells = <0>;
1235 interrupts = 1235 interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;
1236 clocks = <&gc 1236 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1237 clock-names = 1237 clock-names = "se";
1238 interconnects 1238 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1239 1239 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1240 1240 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1241 1241 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
1242 1242 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
1243 1243 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1244 interconnect- 1244 interconnect-names = "qup-core",
1245 1245 "qup-config",
1246 1246 "qup-memory";
1247 power-domains 1247 power-domains = <&rpmhpd SA8775P_CX>;
1248 status = "dis 1248 status = "disabled";
1249 }; 1249 };
1250 1250
1251 spi1: spi@984000 { 1251 spi1: spi@984000 {
1252 compatible = 1252 compatible = "qcom,geni-spi";
1253 reg = <0x0 0x 1253 reg = <0x0 0x984000 0x0 0x4000>;
1254 #address-cell 1254 #address-cells = <1>;
1255 #size-cells = 1255 #size-cells = <0>;
1256 interrupts = 1256 interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;
1257 clocks = <&gc 1257 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1258 clock-names = 1258 clock-names = "se";
1259 interconnects 1259 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1260 1260 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1261 1261 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1262 1262 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
1263 1263 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
1264 1264 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1265 interconnect- 1265 interconnect-names = "qup-core",
1266 1266 "qup-config",
1267 1267 "qup-memory";
1268 power-domains 1268 power-domains = <&rpmhpd SA8775P_CX>;
1269 status = "dis 1269 status = "disabled";
1270 }; 1270 };
1271 1271
1272 i2c2: i2c@988000 { 1272 i2c2: i2c@988000 {
1273 compatible = 1273 compatible = "qcom,geni-i2c";
1274 reg = <0x0 0x 1274 reg = <0x0 0x988000 0x0 0x4000>;
1275 #address-cell 1275 #address-cells = <1>;
1276 #size-cells = 1276 #size-cells = <0>;
1277 interrupts = 1277 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>;
1278 clocks = <&gc 1278 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1279 clock-names = 1279 clock-names = "se";
1280 interconnects 1280 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1281 1281 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1282 1282 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1283 1283 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
1284 1284 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
1285 1285 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1286 interconnect- 1286 interconnect-names = "qup-core",
1287 1287 "qup-config",
1288 1288 "qup-memory";
1289 power-domains 1289 power-domains = <&rpmhpd SA8775P_CX>;
1290 status = "dis 1290 status = "disabled";
1291 }; 1291 };
1292 1292
1293 spi2: spi@988000 { 1293 spi2: spi@988000 {
1294 compatible = 1294 compatible = "qcom,geni-spi";
1295 reg = <0x0 0x 1295 reg = <0x0 0x988000 0x0 0x4000>;
1296 #address-cell 1296 #address-cells = <1>;
1297 #size-cells = 1297 #size-cells = <0>;
1298 interrupts = 1298 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>;
1299 clocks = <&gc 1299 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1300 clock-names = 1300 clock-names = "se";
1301 interconnects 1301 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1302 1302 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1303 1303 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1304 1304 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
1305 1305 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
1306 1306 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1307 interconnect- 1307 interconnect-names = "qup-core",
1308 1308 "qup-config",
1309 1309 "qup-memory";
1310 power-domains 1310 power-domains = <&rpmhpd SA8775P_CX>;
1311 status = "dis 1311 status = "disabled";
1312 }; 1312 };
1313 1313
1314 i2c3: i2c@98c000 { 1314 i2c3: i2c@98c000 {
1315 compatible = 1315 compatible = "qcom,geni-i2c";
1316 reg = <0x0 0x 1316 reg = <0x0 0x98c000 0x0 0x4000>;
1317 #address-cell 1317 #address-cells = <1>;
1318 #size-cells = 1318 #size-cells = <0>;
1319 interrupts = 1319 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>;
1320 clocks = <&gc 1320 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1321 clock-names = 1321 clock-names = "se";
1322 interconnects 1322 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1323 1323 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1324 1324 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1325 1325 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
1326 1326 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
1327 1327 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1328 interconnect- 1328 interconnect-names = "qup-core",
1329 1329 "qup-config",
1330 1330 "qup-memory";
1331 power-domains 1331 power-domains = <&rpmhpd SA8775P_CX>;
1332 status = "dis 1332 status = "disabled";
1333 }; 1333 };
1334 1334
1335 spi3: spi@98c000 { 1335 spi3: spi@98c000 {
1336 compatible = 1336 compatible = "qcom,geni-spi";
1337 reg = <0x0 0x 1337 reg = <0x0 0x98c000 0x0 0x4000>;
1338 #address-cell 1338 #address-cells = <1>;
1339 #size-cells = 1339 #size-cells = <0>;
1340 interrupts = 1340 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>;
1341 clocks = <&gc 1341 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1342 clock-names = 1342 clock-names = "se";
1343 interconnects 1343 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1344 1344 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1345 1345 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1346 1346 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
1347 1347 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
1348 1348 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1349 interconnect- 1349 interconnect-names = "qup-core",
1350 1350 "qup-config",
1351 1351 "qup-memory";
1352 power-domains 1352 power-domains = <&rpmhpd SA8775P_CX>;
1353 status = "dis 1353 status = "disabled";
1354 }; 1354 };
1355 1355
1356 i2c4: i2c@990000 { 1356 i2c4: i2c@990000 {
1357 compatible = 1357 compatible = "qcom,geni-i2c";
1358 reg = <0x0 0x 1358 reg = <0x0 0x990000 0x0 0x4000>;
1359 #address-cell 1359 #address-cells = <1>;
1360 #size-cells = 1360 #size-cells = <0>;
1361 interrupts = 1361 interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>;
1362 clocks = <&gc 1362 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1363 clock-names = 1363 clock-names = "se";
1364 interconnects 1364 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1365 1365 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1366 1366 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1367 1367 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
1368 1368 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
1369 1369 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1370 interconnect- 1370 interconnect-names = "qup-core",
1371 1371 "qup-config",
1372 1372 "qup-memory";
1373 power-domains 1373 power-domains = <&rpmhpd SA8775P_CX>;
1374 status = "dis 1374 status = "disabled";
1375 }; 1375 };
1376 1376
1377 spi4: spi@990000 { 1377 spi4: spi@990000 {
1378 compatible = 1378 compatible = "qcom,geni-spi";
1379 reg = <0x0 0x 1379 reg = <0x0 0x990000 0x0 0x4000>;
1380 #address-cell 1380 #address-cells = <1>;
1381 #size-cells = 1381 #size-cells = <0>;
1382 interrupts = 1382 interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>;
1383 clocks = <&gc 1383 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1384 clock-names = 1384 clock-names = "se";
1385 interconnects 1385 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1386 1386 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1387 1387 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1388 1388 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
1389 1389 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
1390 1390 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1391 interconnect- 1391 interconnect-names = "qup-core",
1392 1392 "qup-config",
1393 1393 "qup-memory";
1394 power-domains 1394 power-domains = <&rpmhpd SA8775P_CX>;
1395 status = "dis 1395 status = "disabled";
1396 }; 1396 };
1397 1397
1398 i2c5: i2c@994000 { 1398 i2c5: i2c@994000 {
1399 compatible = 1399 compatible = "qcom,geni-i2c";
1400 reg = <0x0 0x 1400 reg = <0x0 0x994000 0x0 0x4000>;
1401 #address-cell 1401 #address-cells = <1>;
1402 #size-cells = 1402 #size-cells = <0>;
1403 interrupts = 1403 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>;
1404 clocks = <&gc 1404 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1405 clock-names = 1405 clock-names = "se";
1406 interconnects 1406 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1407 1407 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1408 1408 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1409 1409 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
1410 1410 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
1411 1411 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1412 interconnect- 1412 interconnect-names = "qup-core",
1413 1413 "qup-config",
1414 1414 "qup-memory";
1415 power-domains 1415 power-domains = <&rpmhpd SA8775P_CX>;
1416 status = "dis 1416 status = "disabled";
1417 }; 1417 };
1418 1418
1419 spi5: spi@994000 { 1419 spi5: spi@994000 {
1420 compatible = 1420 compatible = "qcom,geni-spi";
1421 reg = <0x0 0x 1421 reg = <0x0 0x994000 0x0 0x4000>;
1422 #address-cell 1422 #address-cells = <1>;
1423 #size-cells = 1423 #size-cells = <0>;
1424 interrupts = 1424 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>;
1425 clocks = <&gc 1425 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1426 clock-names = 1426 clock-names = "se";
1427 interconnects 1427 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1428 1428 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1429 1429 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1430 1430 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
1431 1431 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
1432 1432 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1433 interconnect- 1433 interconnect-names = "qup-core",
1434 1434 "qup-config",
1435 1435 "qup-memory";
1436 power-domains 1436 power-domains = <&rpmhpd SA8775P_CX>;
1437 status = "dis 1437 status = "disabled";
1438 }; 1438 };
1439 1439
1440 uart5: serial@994000 1440 uart5: serial@994000 {
1441 compatible = 1441 compatible = "qcom,geni-uart";
1442 reg = <0x0 0x 1442 reg = <0x0 0x994000 0x0 0x4000>;
1443 interrupts = 1443 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>;
1444 clocks = <&gc 1444 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1445 clock-names = 1445 clock-names = "se";
1446 interconnects 1446 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1447 1447 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1448 1448 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1449 1449 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
1450 interconnect- 1450 interconnect-names = "qup-core", "qup-config";
1451 power-domains 1451 power-domains = <&rpmhpd SA8775P_CX>;
1452 status = "dis 1452 status = "disabled";
1453 }; 1453 };
1454 }; 1454 };
1455 1455
1456 qupv3_id_1: geniqup@ac0000 { 1456 qupv3_id_1: geniqup@ac0000 {
1457 compatible = "qcom,ge 1457 compatible = "qcom,geni-se-qup";
1458 reg = <0x0 0x00ac0000 1458 reg = <0x0 0x00ac0000 0x0 0x6000>;
1459 #address-cells = <2>; 1459 #address-cells = <2>;
1460 #size-cells = <2>; 1460 #size-cells = <2>;
1461 ranges; 1461 ranges;
1462 clock-names = "m-ahb" 1462 clock-names = "m-ahb", "s-ahb";
1463 clocks = <&gcc GCC_QU 1463 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1464 <&gcc GCC_QU 1464 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1465 iommus = <&apps_smmu 1465 iommus = <&apps_smmu 0x443 0x0>;
1466 status = "disabled"; 1466 status = "disabled";
1467 1467
1468 i2c7: i2c@a80000 { 1468 i2c7: i2c@a80000 {
1469 compatible = 1469 compatible = "qcom,geni-i2c";
1470 reg = <0x0 0x 1470 reg = <0x0 0xa80000 0x0 0x4000>;
1471 #address-cell 1471 #address-cells = <1>;
1472 #size-cells = 1472 #size-cells = <0>;
1473 interrupts = 1473 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1474 clocks = <&gc 1474 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1475 clock-names = 1475 clock-names = "se";
1476 interconnects 1476 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1477 1477 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1478 1478 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1479 1479 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1480 1480 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1481 1481 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1482 interconnect- 1482 interconnect-names = "qup-core",
1483 1483 "qup-config",
1484 1484 "qup-memory";
1485 power-domains 1485 power-domains = <&rpmhpd SA8775P_CX>;
1486 status = "dis 1486 status = "disabled";
1487 }; 1487 };
1488 1488
1489 spi7: spi@a80000 { 1489 spi7: spi@a80000 {
1490 compatible = 1490 compatible = "qcom,geni-spi";
1491 reg = <0x0 0x 1491 reg = <0x0 0xa80000 0x0 0x4000>;
1492 #address-cell 1492 #address-cells = <1>;
1493 #size-cells = 1493 #size-cells = <0>;
1494 interrupts = 1494 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1495 clocks = <&gc 1495 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1496 clock-names = 1496 clock-names = "se";
1497 interconnects 1497 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1498 1498 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1499 1499 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1500 1500 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1501 1501 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1502 1502 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1503 interconnect- 1503 interconnect-names = "qup-core",
1504 1504 "qup-config",
1505 1505 "qup-memory";
1506 power-domains 1506 power-domains = <&rpmhpd SA8775P_CX>;
1507 status = "dis 1507 status = "disabled";
1508 }; 1508 };
1509 1509
1510 i2c8: i2c@a84000 { 1510 i2c8: i2c@a84000 {
1511 compatible = 1511 compatible = "qcom,geni-i2c";
1512 reg = <0x0 0x 1512 reg = <0x0 0xa84000 0x0 0x4000>;
1513 #address-cell 1513 #address-cells = <1>;
1514 #size-cells = 1514 #size-cells = <0>;
1515 interrupts = 1515 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1516 clocks = <&gc 1516 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1517 clock-names = 1517 clock-names = "se";
1518 interconnects 1518 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1519 1519 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1520 1520 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1521 1521 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1522 1522 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1523 1523 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1524 interconnect- 1524 interconnect-names = "qup-core",
1525 1525 "qup-config",
1526 1526 "qup-memory";
1527 power-domains 1527 power-domains = <&rpmhpd SA8775P_CX>;
1528 status = "dis 1528 status = "disabled";
1529 }; 1529 };
1530 1530
1531 spi8: spi@a84000 { 1531 spi8: spi@a84000 {
1532 compatible = 1532 compatible = "qcom,geni-spi";
1533 reg = <0x0 0x 1533 reg = <0x0 0xa84000 0x0 0x4000>;
1534 #address-cell 1534 #address-cells = <1>;
1535 #size-cells = 1535 #size-cells = <0>;
1536 interrupts = 1536 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1537 clocks = <&gc 1537 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1538 clock-names = 1538 clock-names = "se";
1539 interconnects 1539 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1540 1540 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1541 1541 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1542 1542 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1543 1543 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1544 1544 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1545 interconnect- 1545 interconnect-names = "qup-core",
1546 1546 "qup-config",
1547 1547 "qup-memory";
1548 power-domains 1548 power-domains = <&rpmhpd SA8775P_CX>;
1549 status = "dis 1549 status = "disabled";
1550 }; 1550 };
1551 1551
1552 i2c9: i2c@a88000 { 1552 i2c9: i2c@a88000 {
1553 compatible = 1553 compatible = "qcom,geni-i2c";
1554 reg = <0x0 0x 1554 reg = <0x0 0xa88000 0x0 0x4000>;
1555 #address-cell 1555 #address-cells = <1>;
1556 #size-cells = 1556 #size-cells = <0>;
1557 interrupts = 1557 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1558 clocks = <&gc 1558 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1559 clock-names = 1559 clock-names = "se";
1560 interconnects 1560 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1561 1561 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1562 1562 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1563 1563 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1564 1564 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1565 1565 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1566 interconnect- 1566 interconnect-names = "qup-core",
1567 1567 "qup-config",
1568 1568 "qup-memory";
1569 power-domains 1569 power-domains = <&rpmhpd SA8775P_CX>;
1570 status = "dis 1570 status = "disabled";
1571 }; 1571 };
1572 1572
1573 spi9: spi@a88000 { 1573 spi9: spi@a88000 {
1574 compatible = 1574 compatible = "qcom,geni-spi";
1575 reg = <0x0 0x 1575 reg = <0x0 0xa88000 0x0 0x4000>;
1576 #address-cell 1576 #address-cells = <1>;
1577 #size-cells = 1577 #size-cells = <0>;
1578 interrupts = 1578 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1579 clocks = <&gc 1579 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1580 clock-names = 1580 clock-names = "se";
1581 interconnects 1581 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1582 1582 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1583 1583 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1584 1584 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1585 1585 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1586 1586 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1587 interconnect- 1587 interconnect-names = "qup-core",
1588 1588 "qup-config",
1589 1589 "qup-memory";
1590 power-domains 1590 power-domains = <&rpmhpd SA8775P_CX>;
1591 status = "dis 1591 status = "disabled";
1592 }; 1592 };
1593 1593
1594 uart9: serial@a88000 1594 uart9: serial@a88000 {
1595 compatible = 1595 compatible = "qcom,geni-uart";
1596 reg = <0x0 0x 1596 reg = <0x0 0xa88000 0x0 0x4000>;
1597 interrupts = 1597 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1598 clocks = <&gc 1598 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1599 clock-names = 1599 clock-names = "se";
1600 interconnects 1600 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1601 1601 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1602 1602 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1603 1603 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
1604 interconnect- 1604 interconnect-names = "qup-core", "qup-config";
1605 power-domains 1605 power-domains = <&rpmhpd SA8775P_CX>;
1606 status = "dis 1606 status = "disabled";
1607 }; 1607 };
1608 1608
1609 i2c10: i2c@a8c000 { 1609 i2c10: i2c@a8c000 {
1610 compatible = 1610 compatible = "qcom,geni-i2c";
1611 reg = <0x0 0x 1611 reg = <0x0 0xa8c000 0x0 0x4000>;
1612 #address-cell 1612 #address-cells = <1>;
1613 #size-cells = 1613 #size-cells = <0>;
1614 interrupts = 1614 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1615 clocks = <&gc 1615 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1616 clock-names = 1616 clock-names = "se";
1617 interconnects 1617 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1618 1618 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1619 1619 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1620 1620 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1621 1621 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1622 1622 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1623 interconnect- 1623 interconnect-names = "qup-core",
1624 1624 "qup-config",
1625 1625 "qup-memory";
1626 power-domains 1626 power-domains = <&rpmhpd SA8775P_CX>;
1627 status = "dis 1627 status = "disabled";
1628 }; 1628 };
1629 1629
1630 spi10: spi@a8c000 { 1630 spi10: spi@a8c000 {
1631 compatible = 1631 compatible = "qcom,geni-spi";
1632 reg = <0x0 0x 1632 reg = <0x0 0xa8c000 0x0 0x4000>;
1633 #address-cell 1633 #address-cells = <1>;
1634 #size-cells = 1634 #size-cells = <0>;
1635 interrupts = 1635 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1636 clocks = <&gc 1636 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1637 clock-names = 1637 clock-names = "se";
1638 interconnects 1638 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1639 1639 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1640 1640 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1641 1641 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1642 1642 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1643 1643 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1644 interconnect- 1644 interconnect-names = "qup-core",
1645 1645 "qup-config",
1646 1646 "qup-memory";
1647 power-domains 1647 power-domains = <&rpmhpd SA8775P_CX>;
1648 status = "dis 1648 status = "disabled";
1649 }; 1649 };
1650 1650
1651 uart10: serial@a8c000 1651 uart10: serial@a8c000 {
1652 compatible = 1652 compatible = "qcom,geni-uart";
1653 reg = <0x0 0x 1653 reg = <0x0 0x00a8c000 0x0 0x4000>;
1654 interrupts = 1654 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1655 clock-names = 1655 clock-names = "se";
1656 clocks = <&gc 1656 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1657 interconnect- 1657 interconnect-names = "qup-core", "qup-config";
1658 interconnects 1658 interconnects = <&clk_virt MASTER_QUP_CORE_1 0
1659 1659 &clk_virt SLAVE_QUP_CORE_1 0>,
1660 1660 <&gem_noc MASTER_APPSS_PROC 0
1661 1661 &config_noc SLAVE_QUP_1 0>;
1662 power-domains 1662 power-domains = <&rpmhpd SA8775P_CX>;
1663 operating-poi 1663 operating-points-v2 = <&qup_opp_table_100mhz>;
1664 status = "dis 1664 status = "disabled";
1665 }; 1665 };
1666 1666
1667 i2c11: i2c@a90000 { 1667 i2c11: i2c@a90000 {
1668 compatible = 1668 compatible = "qcom,geni-i2c";
1669 reg = <0x0 0x 1669 reg = <0x0 0xa90000 0x0 0x4000>;
1670 #address-cell 1670 #address-cells = <1>;
1671 #size-cells = 1671 #size-cells = <0>;
1672 interrupts = 1672 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1673 clocks = <&gc 1673 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1674 clock-names = 1674 clock-names = "se";
1675 interconnects 1675 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1676 1676 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1677 1677 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1678 1678 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1679 1679 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1680 1680 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1681 interconnect- 1681 interconnect-names = "qup-core",
1682 1682 "qup-config",
1683 1683 "qup-memory";
1684 power-domains 1684 power-domains = <&rpmhpd SA8775P_CX>;
1685 status = "dis 1685 status = "disabled";
1686 }; 1686 };
1687 1687
1688 spi11: spi@a90000 { 1688 spi11: spi@a90000 {
1689 compatible = 1689 compatible = "qcom,geni-spi";
1690 reg = <0x0 0x 1690 reg = <0x0 0xa90000 0x0 0x4000>;
1691 #address-cell 1691 #address-cells = <1>;
1692 #size-cells = 1692 #size-cells = <0>;
1693 interrupts = 1693 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1694 clocks = <&gc 1694 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1695 clock-names = 1695 clock-names = "se";
1696 interconnects 1696 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1697 1697 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1698 1698 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1699 1699 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1700 1700 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1701 1701 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1702 interconnect- 1702 interconnect-names = "qup-core",
1703 1703 "qup-config",
1704 1704 "qup-memory";
1705 power-domains 1705 power-domains = <&rpmhpd SA8775P_CX>;
1706 status = "dis 1706 status = "disabled";
1707 }; 1707 };
1708 1708
1709 i2c12: i2c@a94000 { 1709 i2c12: i2c@a94000 {
1710 compatible = 1710 compatible = "qcom,geni-i2c";
1711 reg = <0x0 0x 1711 reg = <0x0 0xa94000 0x0 0x4000>;
1712 #address-cell 1712 #address-cells = <1>;
1713 #size-cells = 1713 #size-cells = <0>;
1714 interrupts = 1714 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1715 clocks = <&gc 1715 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1716 clock-names = 1716 clock-names = "se";
1717 interconnects 1717 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1718 1718 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1719 1719 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1720 1720 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1721 1721 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1722 1722 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1723 interconnect- 1723 interconnect-names = "qup-core",
1724 1724 "qup-config",
1725 1725 "qup-memory";
1726 power-domains 1726 power-domains = <&rpmhpd SA8775P_CX>;
1727 status = "dis 1727 status = "disabled";
1728 }; 1728 };
1729 1729
1730 spi12: spi@a94000 { 1730 spi12: spi@a94000 {
1731 compatible = 1731 compatible = "qcom,geni-spi";
1732 reg = <0x0 0x 1732 reg = <0x0 0xa94000 0x0 0x4000>;
1733 #address-cell 1733 #address-cells = <1>;
1734 #size-cells = 1734 #size-cells = <0>;
1735 interrupts = 1735 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1736 clocks = <&gc 1736 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1737 clock-names = 1737 clock-names = "se";
1738 interconnects 1738 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1739 1739 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1740 1740 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1741 1741 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1742 1742 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1743 1743 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1744 interconnect- 1744 interconnect-names = "qup-core",
1745 1745 "qup-config",
1746 1746 "qup-memory";
1747 power-domains 1747 power-domains = <&rpmhpd SA8775P_CX>;
1748 status = "dis 1748 status = "disabled";
1749 }; 1749 };
1750 1750
1751 uart12: serial@a94000 1751 uart12: serial@a94000 {
1752 compatible = 1752 compatible = "qcom,geni-uart";
1753 reg = <0x0 0x 1753 reg = <0x0 0x00a94000 0x0 0x4000>;
1754 interrupts = 1754 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1755 clocks = <&gc 1755 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1756 clock-names = 1756 clock-names = "se";
1757 interconnects 1757 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1758 1758 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1759 1759 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1760 1760 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
1761 interconnect- 1761 interconnect-names = "qup-core", "qup-config";
1762 power-domains 1762 power-domains = <&rpmhpd SA8775P_CX>;
1763 status = "dis 1763 status = "disabled";
1764 }; 1764 };
1765 1765
1766 i2c13: i2c@a98000 { 1766 i2c13: i2c@a98000 {
1767 compatible = 1767 compatible = "qcom,geni-i2c";
1768 reg = <0x0 0x 1768 reg = <0x0 0xa98000 0x0 0x4000>;
1769 #address-cell 1769 #address-cells = <1>;
1770 #size-cells = 1770 #size-cells = <0>;
1771 interrupts = 1771 interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
1772 clocks = <&gc 1772 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1773 clock-names = 1773 clock-names = "se";
1774 interconnects 1774 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1775 1775 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1776 1776 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1777 1777 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1778 1778 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1779 1779 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1780 interconnect- 1780 interconnect-names = "qup-core",
1781 1781 "qup-config",
1782 1782 "qup-memory";
1783 power-domains 1783 power-domains = <&rpmhpd SA8775P_CX>;
1784 status = "dis 1784 status = "disabled";
1785 }; 1785 };
1786 }; 1786 };
1787 1787
1788 qupv3_id_3: geniqup@bc0000 { 1788 qupv3_id_3: geniqup@bc0000 {
1789 compatible = "qcom,ge 1789 compatible = "qcom,geni-se-qup";
1790 reg = <0x0 0xbc0000 0 1790 reg = <0x0 0xbc0000 0x0 0x6000>;
1791 #address-cells = <2>; 1791 #address-cells = <2>;
1792 #size-cells = <2>; 1792 #size-cells = <2>;
1793 ranges; 1793 ranges;
1794 clock-names = "m-ahb" 1794 clock-names = "m-ahb", "s-ahb";
1795 clocks = <&gcc GCC_QU 1795 clocks = <&gcc GCC_QUPV3_WRAP_3_M_AHB_CLK>,
1796 <&gcc GCC_QUP 1796 <&gcc GCC_QUPV3_WRAP_3_S_AHB_CLK>;
1797 iommus = <&apps_smmu 1797 iommus = <&apps_smmu 0x43 0x0>;
1798 status = "disabled"; 1798 status = "disabled";
1799 1799
1800 i2c21: i2c@b80000 { 1800 i2c21: i2c@b80000 {
1801 compatible = 1801 compatible = "qcom,geni-i2c";
1802 reg = <0x0 0x 1802 reg = <0x0 0xb80000 0x0 0x4000>;
1803 #address-cell 1803 #address-cells = <1>;
1804 #size-cells = 1804 #size-cells = <0>;
1805 interrupts = 1805 interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>;
1806 clocks = <&gc 1806 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>;
1807 clock-names = 1807 clock-names = "se";
1808 interconnects 1808 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS
1809 1809 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>,
1810 <& 1810 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1811 1811 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>,
1812 <& 1812 <&aggre1_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS
1813 1813 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1814 interconnect- 1814 interconnect-names = "qup-core",
1815 1815 "qup-config",
1816 1816 "qup-memory";
1817 power-domains 1817 power-domains = <&rpmhpd SA8775P_CX>;
1818 status = "dis 1818 status = "disabled";
1819 }; 1819 };
1820 1820
1821 spi21: spi@b80000 { 1821 spi21: spi@b80000 {
1822 compatible = 1822 compatible = "qcom,geni-spi";
1823 reg = <0x0 0x 1823 reg = <0x0 0xb80000 0x0 0x4000>;
1824 #address-cell 1824 #address-cells = <1>;
1825 #size-cells = 1825 #size-cells = <0>;
1826 interrupts = 1826 interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>;
1827 clocks = <&gc 1827 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>;
1828 clock-names = 1828 clock-names = "se";
1829 interconnects 1829 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS
1830 1830 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>,
1831 <& 1831 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1832 1832 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>,
1833 <& 1833 <&aggre1_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS
1834 1834 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1835 interconnect- 1835 interconnect-names = "qup-core",
1836 1836 "qup-config",
1837 1837 "qup-memory";
1838 power-domains 1838 power-domains = <&rpmhpd SA8775P_CX>;
1839 status = "dis 1839 status = "disabled";
1840 }; 1840 };
1841 }; 1841 };
1842 1842
1843 rng: rng@10d2000 { 1843 rng: rng@10d2000 {
1844 compatible = "qcom,sa 1844 compatible = "qcom,sa8775p-trng", "qcom,trng";
1845 reg = <0 0x010d2000 0 1845 reg = <0 0x010d2000 0 0x1000>;
1846 }; 1846 };
1847 1847
1848 ufs_mem_hc: ufs@1d84000 { 1848 ufs_mem_hc: ufs@1d84000 {
1849 compatible = "qcom,sa 1849 compatible = "qcom,sa8775p-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
1850 reg = <0x0 0x01d84000 1850 reg = <0x0 0x01d84000 0x0 0x3000>;
1851 interrupts = <GIC_SPI 1851 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
1852 phys = <&ufs_mem_phy> 1852 phys = <&ufs_mem_phy>;
1853 phy-names = "ufsphy"; 1853 phy-names = "ufsphy";
1854 lanes-per-direction = 1854 lanes-per-direction = <2>;
1855 #reset-cells = <1>; 1855 #reset-cells = <1>;
1856 resets = <&gcc GCC_UF 1856 resets = <&gcc GCC_UFS_PHY_BCR>;
1857 reset-names = "rst"; 1857 reset-names = "rst";
1858 power-domains = <&gcc 1858 power-domains = <&gcc UFS_PHY_GDSC>;
1859 required-opps = <&rpm 1859 required-opps = <&rpmhpd_opp_nom>;
1860 iommus = <&apps_smmu 1860 iommus = <&apps_smmu 0x100 0x0>;
1861 dma-coherent; 1861 dma-coherent;
1862 clocks = <&gcc GCC_UF 1862 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
1863 <&gcc GCC_AG 1863 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
1864 <&gcc GCC_UF 1864 <&gcc GCC_UFS_PHY_AHB_CLK>,
1865 <&gcc GCC_UF 1865 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
1866 <&rpmhcc RPM 1866 <&rpmhcc RPMH_CXO_CLK>,
1867 <&gcc GCC_UF 1867 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
1868 <&gcc GCC_UF 1868 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
1869 <&gcc GCC_UF 1869 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
1870 clock-names = "core_c 1870 clock-names = "core_clk",
1871 "bus_ag 1871 "bus_aggr_clk",
1872 "iface_ 1872 "iface_clk",
1873 "core_c 1873 "core_clk_unipro",
1874 "ref_cl 1874 "ref_clk",
1875 "tx_lan 1875 "tx_lane0_sync_clk",
1876 "rx_lan 1876 "rx_lane0_sync_clk",
1877 "rx_lan 1877 "rx_lane1_sync_clk";
1878 freq-table-hz = <7500 1878 freq-table-hz = <75000000 300000000>,
1879 <0 0> 1879 <0 0>,
1880 <0 0> 1880 <0 0>,
1881 <7500 1881 <75000000 300000000>,
1882 <0 0> 1882 <0 0>,
1883 <0 0> 1883 <0 0>,
1884 <0 0> 1884 <0 0>,
1885 <0 0> 1885 <0 0>;
1886 qcom,ice = <&ice>; 1886 qcom,ice = <&ice>;
1887 status = "disabled"; 1887 status = "disabled";
1888 }; 1888 };
1889 1889
1890 ufs_mem_phy: phy@1d87000 { 1890 ufs_mem_phy: phy@1d87000 {
1891 compatible = "qcom,sa 1891 compatible = "qcom,sa8775p-qmp-ufs-phy";
1892 reg = <0x0 0x01d87000 1892 reg = <0x0 0x01d87000 0x0 0xe10>;
1893 /* 1893 /*
1894 * Yes, GCC_EDP_REF_C 1894 * Yes, GCC_EDP_REF_CLKREF_EN is correct in qref. It
1895 * enables the CXO cl 1895 * enables the CXO clock to eDP *and* UFS PHY.
1896 */ 1896 */
1897 clocks = <&rpmhcc RPM 1897 clocks = <&rpmhcc RPMH_CXO_CLK>,
1898 <&gcc GCC_UF 1898 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
1899 <&gcc GCC_ED 1899 <&gcc GCC_EDP_REF_CLKREF_EN>;
1900 clock-names = "ref", 1900 clock-names = "ref", "ref_aux", "qref";
1901 power-domains = <&gcc 1901 power-domains = <&gcc UFS_PHY_GDSC>;
1902 resets = <&ufs_mem_hc 1902 resets = <&ufs_mem_hc 0>;
1903 reset-names = "ufsphy 1903 reset-names = "ufsphy";
1904 #phy-cells = <0>; 1904 #phy-cells = <0>;
1905 status = "disabled"; 1905 status = "disabled";
1906 }; 1906 };
1907 1907
1908 ice: crypto@1d88000 { 1908 ice: crypto@1d88000 {
1909 compatible = "qcom,sa 1909 compatible = "qcom,sa8775p-inline-crypto-engine",
1910 "qcom,in 1910 "qcom,inline-crypto-engine";
1911 reg = <0x0 0x01d88000 1911 reg = <0x0 0x01d88000 0x0 0x8000>;
1912 clocks = <&gcc GCC_UF 1912 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
1913 }; 1913 };
1914 1914
1915 stm: stm@4002000 { 1915 stm: stm@4002000 {
1916 compatible = "arm,cor 1916 compatible = "arm,coresight-stm", "arm,primecell";
1917 reg = <0x0 0x4002000 1917 reg = <0x0 0x4002000 0x0 0x1000>,
1918 <0x0 0x1628 1918 <0x0 0x16280000 0x0 0x180000>;
1919 reg-names = "stm-base 1919 reg-names = "stm-base", "stm-stimulus-base";
1920 1920
1921 clocks = <&aoss_qmp>; 1921 clocks = <&aoss_qmp>;
1922 clock-names = "apb_pc 1922 clock-names = "apb_pclk";
1923 1923
1924 out-ports { 1924 out-ports {
1925 port { 1925 port {
1926 stm_o 1926 stm_out: endpoint {
1927 1927 remote-endpoint =
1928 1928 <&funnel0_in7>;
1929 }; 1929 };
1930 }; 1930 };
1931 }; 1931 };
1932 }; 1932 };
1933 1933
1934 tpdm@4003000 { 1934 tpdm@4003000 {
1935 compatible = "qcom,co 1935 compatible = "qcom,coresight-tpdm", "arm,primecell";
1936 reg = <0x0 0x4003000 1936 reg = <0x0 0x4003000 0x0 0x1000>;
1937 1937
1938 clocks = <&aoss_qmp>; 1938 clocks = <&aoss_qmp>;
1939 clock-names = "apb_pc 1939 clock-names = "apb_pclk";
1940 1940
1941 qcom,cmb-element-bits 1941 qcom,cmb-element-bits = <32>;
1942 qcom,cmb-msrs-num = < 1942 qcom,cmb-msrs-num = <32>;
1943 1943
1944 out-ports { 1944 out-ports {
1945 port { 1945 port {
1946 qdss_ 1946 qdss_tpdm0_out: endpoint {
1947 1947 remote-endpoint =
1948 1948 <&qdss_tpda_in0>;
1949 }; 1949 };
1950 }; 1950 };
1951 }; 1951 };
1952 }; 1952 };
1953 1953
1954 tpda@4004000 { 1954 tpda@4004000 {
1955 compatible = "qcom,co 1955 compatible = "qcom,coresight-tpda", "arm,primecell";
1956 reg = <0x0 0x4004000 1956 reg = <0x0 0x4004000 0x0 0x1000>;
1957 1957
1958 clocks = <&aoss_qmp>; 1958 clocks = <&aoss_qmp>;
1959 clock-names = "apb_pc 1959 clock-names = "apb_pclk";
1960 1960
1961 out-ports { 1961 out-ports {
1962 port { 1962 port {
1963 qdss_ 1963 qdss_tpda_out: endpoint {
1964 1964 remote-endpoint =
1965 1965 <&funnel0_in6>;
1966 }; 1966 };
1967 }; 1967 };
1968 }; 1968 };
1969 1969
1970 in-ports { 1970 in-ports {
1971 #address-cell 1971 #address-cells = <1>;
1972 #size-cells = 1972 #size-cells = <0>;
1973 1973
1974 port@0 { 1974 port@0 {
1975 reg = 1975 reg = <0>;
1976 qdss_ 1976 qdss_tpda_in0: endpoint {
1977 1977 remote-endpoint =
1978 1978 <&qdss_tpdm0_out>;
1979 }; 1979 };
1980 }; 1980 };
1981 1981
1982 port@1 { 1982 port@1 {
1983 reg = 1983 reg = <1>;
1984 qdss_ 1984 qdss_tpda_in1: endpoint {
1985 1985 remote-endpoint =
1986 1986 <&qdss_tpdm1_out>;
1987 }; 1987 };
1988 }; 1988 };
1989 }; 1989 };
1990 }; 1990 };
1991 1991
1992 tpdm@400f000 { 1992 tpdm@400f000 {
1993 compatible = "qcom,co 1993 compatible = "qcom,coresight-tpdm", "arm,primecell";
1994 reg = <0x0 0x400f000 1994 reg = <0x0 0x400f000 0x0 0x1000>;
1995 1995
1996 clocks = <&aoss_qmp>; 1996 clocks = <&aoss_qmp>;
1997 clock-names = "apb_pc 1997 clock-names = "apb_pclk";
1998 1998
1999 qcom,cmb-element-bits 1999 qcom,cmb-element-bits = <32>;
2000 qcom,cmb-msrs-num = < 2000 qcom,cmb-msrs-num = <32>;
2001 2001
2002 out-ports { 2002 out-ports {
2003 port { 2003 port {
2004 qdss_ 2004 qdss_tpdm1_out: endpoint {
2005 2005 remote-endpoint =
2006 2006 <&qdss_tpda_in1>;
2007 }; 2007 };
2008 }; 2008 };
2009 }; 2009 };
2010 }; 2010 };
2011 2011
2012 funnel@4041000 { 2012 funnel@4041000 {
2013 compatible = "arm,cor 2013 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2014 reg = <0x0 0x4041000 2014 reg = <0x0 0x4041000 0x0 0x1000>;
2015 2015
2016 clocks = <&aoss_qmp>; 2016 clocks = <&aoss_qmp>;
2017 clock-names = "apb_pc 2017 clock-names = "apb_pclk";
2018 2018
2019 out-ports { 2019 out-ports {
2020 port { 2020 port {
2021 funne 2021 funnel0_out: endpoint {
2022 2022 remote-endpoint =
2023 2023 <&qdss_funnel_in0>;
2024 }; 2024 };
2025 }; 2025 };
2026 }; 2026 };
2027 2027
2028 in-ports { 2028 in-ports {
2029 #address-cell 2029 #address-cells = <1>;
2030 #size-cells = 2030 #size-cells = <0>;
2031 2031
2032 port@6 { 2032 port@6 {
2033 reg = 2033 reg = <6>;
2034 funne 2034 funnel0_in6: endpoint {
2035 2035 remote-endpoint =
2036 2036 <&qdss_tpda_out>;
2037 }; 2037 };
2038 }; 2038 };
2039 2039
2040 port@7 { 2040 port@7 {
2041 reg = 2041 reg = <7>;
2042 funne 2042 funnel0_in7: endpoint {
2043 2043 remote-endpoint =
2044 2044 <&stm_out>;
2045 }; 2045 };
2046 }; 2046 };
2047 }; 2047 };
2048 }; 2048 };
2049 2049
2050 funnel@4042000 { 2050 funnel@4042000 {
2051 compatible = "arm,cor 2051 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2052 reg = <0x0 0x4042000 2052 reg = <0x0 0x4042000 0x0 0x1000>;
2053 2053
2054 clocks = <&aoss_qmp>; 2054 clocks = <&aoss_qmp>;
2055 clock-names = "apb_pc 2055 clock-names = "apb_pclk";
2056 2056
2057 out-ports { 2057 out-ports {
2058 port { 2058 port {
2059 funne 2059 funnel1_out: endpoint {
2060 2060 remote-endpoint =
2061 2061 <&qdss_funnel_in1>;
2062 }; 2062 };
2063 }; 2063 };
2064 }; 2064 };
2065 2065
2066 in-ports { 2066 in-ports {
2067 #address-cell 2067 #address-cells = <1>;
2068 #size-cells = 2068 #size-cells = <0>;
2069 2069
2070 port@4 { 2070 port@4 {
2071 reg = 2071 reg = <4>;
2072 funne 2072 funnel1_in4: endpoint {
2073 2073 remote-endpoint =
2074 2074 <&apss_funnel1_out>;
2075 }; 2075 };
2076 }; 2076 };
2077 }; 2077 };
2078 }; 2078 };
2079 2079
2080 funnel@4045000 { 2080 funnel@4045000 {
2081 compatible = "arm,cor 2081 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2082 reg = <0x0 0x4045000 2082 reg = <0x0 0x4045000 0x0 0x1000>;
2083 2083
2084 clocks = <&aoss_qmp>; 2084 clocks = <&aoss_qmp>;
2085 clock-names = "apb_pc 2085 clock-names = "apb_pclk";
2086 2086
2087 out-ports { 2087 out-ports {
2088 port { 2088 port {
2089 qdss_ 2089 qdss_funnel_out: endpoint {
2090 2090 remote-endpoint =
2091 2091 <&aoss_funnel_in7>;
2092 }; 2092 };
2093 }; 2093 };
2094 }; 2094 };
2095 2095
2096 in-ports { 2096 in-ports {
2097 #address-cell 2097 #address-cells = <1>;
2098 #size-cells = 2098 #size-cells = <0>;
2099 2099
2100 port@0 { 2100 port@0 {
2101 reg = 2101 reg = <0>;
2102 qdss_ 2102 qdss_funnel_in0: endpoint {
2103 2103 remote-endpoint =
2104 2104 <&funnel0_out>;
2105 }; 2105 };
2106 }; 2106 };
2107 2107
2108 port@1 { 2108 port@1 {
2109 reg = 2109 reg = <1>;
2110 qdss_ 2110 qdss_funnel_in1: endpoint {
2111 2111 remote-endpoint =
2112 2112 <&funnel1_out>;
2113 }; 2113 };
2114 }; 2114 };
2115 }; 2115 };
2116 }; 2116 };
2117 2117
2118 funnel@4b04000 { 2118 funnel@4b04000 {
2119 compatible = "arm,cor 2119 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2120 reg = <0x0 0x4b04000 2120 reg = <0x0 0x4b04000 0x0 0x1000>;
2121 2121
2122 clocks = <&aoss_qmp>; 2122 clocks = <&aoss_qmp>;
2123 clock-names = "apb_pc 2123 clock-names = "apb_pclk";
2124 2124
2125 out-ports { 2125 out-ports {
2126 port { 2126 port {
2127 aoss_ 2127 aoss_funnel_out: endpoint {
2128 2128 remote-endpoint =
2129 2129 <&etf0_in>;
2130 }; 2130 };
2131 }; 2131 };
2132 }; 2132 };
2133 2133
2134 in-ports { 2134 in-ports {
2135 #address-cell 2135 #address-cells = <1>;
2136 #size-cells = 2136 #size-cells = <0>;
2137 2137
2138 port@6 { 2138 port@6 {
2139 reg = 2139 reg = <6>;
2140 aoss_ 2140 aoss_funnel_in6: endpoint {
2141 2141 remote-endpoint =
2142 2142 <&aoss_tpda_out>;
2143 }; 2143 };
2144 }; 2144 };
2145 2145
2146 port@7 { 2146 port@7 {
2147 reg = 2147 reg = <7>;
2148 aoss_ 2148 aoss_funnel_in7: endpoint {
2149 2149 remote-endpoint =
2150 2150 <&qdss_funnel_out>;
2151 }; 2151 };
2152 }; 2152 };
2153 }; 2153 };
2154 }; 2154 };
2155 2155
2156 tmc_etf: tmc@4b05000 { 2156 tmc_etf: tmc@4b05000 {
2157 compatible = "arm,cor 2157 compatible = "arm,coresight-tmc", "arm,primecell";
2158 reg = <0x0 0x4b05000 2158 reg = <0x0 0x4b05000 0x0 0x1000>;
2159 2159
2160 clocks = <&aoss_qmp>; 2160 clocks = <&aoss_qmp>;
2161 clock-names = "apb_pc 2161 clock-names = "apb_pclk";
2162 2162
2163 out-ports { 2163 out-ports {
2164 port { 2164 port {
2165 etf0_ 2165 etf0_out: endpoint {
2166 2166 remote-endpoint =
2167 2167 <&swao_rep_in>;
2168 }; 2168 };
2169 }; 2169 };
2170 }; 2170 };
2171 2171
2172 in-ports { 2172 in-ports {
2173 port { 2173 port {
2174 etf0_ 2174 etf0_in: endpoint {
2175 2175 remote-endpoint =
2176 2176 <&aoss_funnel_out>;
2177 }; 2177 };
2178 }; 2178 };
2179 }; 2179 };
2180 }; 2180 };
2181 2181
2182 replicator@4b06000 { 2182 replicator@4b06000 {
2183 compatible = "arm,cor 2183 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2184 reg = <0x0 0x4b06000 2184 reg = <0x0 0x4b06000 0x0 0x1000>;
2185 2185
2186 clocks = <&aoss_qmp>; 2186 clocks = <&aoss_qmp>;
2187 clock-names = "apb_pc 2187 clock-names = "apb_pclk";
2188 2188
2189 out-ports { 2189 out-ports {
2190 #address-cell 2190 #address-cells = <1>;
2191 #size-cells = 2191 #size-cells = <0>;
2192 2192
2193 port@1 { 2193 port@1 {
2194 reg = 2194 reg = <1>;
2195 swao_ 2195 swao_rep_out1: endpoint {
2196 2196 remote-endpoint =
2197 2197 <&eud_in>;
2198 }; 2198 };
2199 }; 2199 };
2200 }; 2200 };
2201 2201
2202 in-ports { 2202 in-ports {
2203 port { 2203 port {
2204 swao_ 2204 swao_rep_in: endpoint {
2205 2205 remote-endpoint =
2206 2206 <&etf0_out>;
2207 }; 2207 };
2208 }; 2208 };
2209 }; 2209 };
2210 }; 2210 };
2211 2211
2212 tpda@4b08000 { 2212 tpda@4b08000 {
2213 compatible = "qcom,co 2213 compatible = "qcom,coresight-tpda", "arm,primecell";
2214 reg = <0x0 0x4b08000 2214 reg = <0x0 0x4b08000 0x0 0x1000>;
2215 2215
2216 clocks = <&aoss_qmp>; 2216 clocks = <&aoss_qmp>;
2217 clock-names = "apb_pc 2217 clock-names = "apb_pclk";
2218 2218
2219 out-ports { 2219 out-ports {
2220 port { 2220 port {
2221 aoss_ 2221 aoss_tpda_out: endpoint {
2222 2222 remote-endpoint =
2223 2223 <&aoss_funnel_in6>;
2224 }; 2224 };
2225 }; 2225 };
2226 }; 2226 };
2227 2227
2228 in-ports { 2228 in-ports {
2229 #address-cell 2229 #address-cells = <1>;
2230 #size-cells = 2230 #size-cells = <0>;
2231 2231
2232 port@0 { 2232 port@0 {
2233 reg = 2233 reg = <0>;
2234 aoss_ 2234 aoss_tpda_in0: endpoint {
2235 2235 remote-endpoint =
2236 2236 <&aoss_tpdm0_out>;
2237 }; 2237 };
2238 }; 2238 };
2239 2239
2240 port@1 { 2240 port@1 {
2241 reg = 2241 reg = <1>;
2242 aoss_ 2242 aoss_tpda_in1: endpoint {
2243 2243 remote-endpoint =
2244 2244 <&aoss_tpdm1_out>;
2245 }; 2245 };
2246 }; 2246 };
2247 2247
2248 port@2 { 2248 port@2 {
2249 reg = 2249 reg = <2>;
2250 aoss_ 2250 aoss_tpda_in2: endpoint {
2251 2251 remote-endpoint =
2252 2252 <&aoss_tpdm2_out>;
2253 }; 2253 };
2254 }; 2254 };
2255 2255
2256 port@3 { 2256 port@3 {
2257 reg = 2257 reg = <3>;
2258 aoss_ 2258 aoss_tpda_in3: endpoint {
2259 2259 remote-endpoint =
2260 2260 <&aoss_tpdm3_out>;
2261 }; 2261 };
2262 }; 2262 };
2263 2263
2264 port@4 { 2264 port@4 {
2265 reg = 2265 reg = <4>;
2266 aoss_ 2266 aoss_tpda_in4: endpoint {
2267 2267 remote-endpoint =
2268 2268 <&aoss_tpdm4_out>;
2269 }; 2269 };
2270 }; 2270 };
2271 }; 2271 };
2272 }; 2272 };
2273 2273
2274 tpdm@4b09000 { 2274 tpdm@4b09000 {
2275 compatible = "qcom,co 2275 compatible = "qcom,coresight-tpdm", "arm,primecell";
2276 reg = <0x0 0x4b09000 2276 reg = <0x0 0x4b09000 0x0 0x1000>;
2277 2277
2278 clocks = <&aoss_qmp>; 2278 clocks = <&aoss_qmp>;
2279 clock-names = "apb_pc 2279 clock-names = "apb_pclk";
2280 2280
2281 qcom,cmb-element-bits 2281 qcom,cmb-element-bits = <64>;
2282 qcom,cmb-msrs-num = < 2282 qcom,cmb-msrs-num = <32>;
2283 2283
2284 out-ports { 2284 out-ports {
2285 port { 2285 port {
2286 aoss_ 2286 aoss_tpdm0_out: endpoint {
2287 2287 remote-endpoint =
2288 2288 <&aoss_tpda_in0>;
2289 }; 2289 };
2290 }; 2290 };
2291 }; 2291 };
2292 }; 2292 };
2293 2293
2294 tpdm@4b0a000 { 2294 tpdm@4b0a000 {
2295 compatible = "qcom,co 2295 compatible = "qcom,coresight-tpdm", "arm,primecell";
2296 reg = <0x0 0x4b0a000 2296 reg = <0x0 0x4b0a000 0x0 0x1000>;
2297 2297
2298 clocks = <&aoss_qmp>; 2298 clocks = <&aoss_qmp>;
2299 clock-names = "apb_pc 2299 clock-names = "apb_pclk";
2300 2300
2301 qcom,cmb-element-bits 2301 qcom,cmb-element-bits = <64>;
2302 qcom,cmb-msrs-num = < 2302 qcom,cmb-msrs-num = <32>;
2303 2303
2304 out-ports { 2304 out-ports {
2305 port { 2305 port {
2306 aoss_ 2306 aoss_tpdm1_out: endpoint {
2307 2307 remote-endpoint =
2308 2308 <&aoss_tpda_in1>;
2309 }; 2309 };
2310 }; 2310 };
2311 }; 2311 };
2312 }; 2312 };
2313 2313
2314 tpdm@4b0b000 { 2314 tpdm@4b0b000 {
2315 compatible = "qcom,co 2315 compatible = "qcom,coresight-tpdm", "arm,primecell";
2316 reg = <0x0 0x4b0b000 2316 reg = <0x0 0x4b0b000 0x0 0x1000>;
2317 2317
2318 clocks = <&aoss_qmp>; 2318 clocks = <&aoss_qmp>;
2319 clock-names = "apb_pc 2319 clock-names = "apb_pclk";
2320 2320
2321 qcom,cmb-element-bits 2321 qcom,cmb-element-bits = <64>;
2322 qcom,cmb-msrs-num = < 2322 qcom,cmb-msrs-num = <32>;
2323 2323
2324 out-ports { 2324 out-ports {
2325 port { 2325 port {
2326 aoss_ 2326 aoss_tpdm2_out: endpoint {
2327 2327 remote-endpoint =
2328 2328 <&aoss_tpda_in2>;
2329 }; 2329 };
2330 }; 2330 };
2331 }; 2331 };
2332 }; 2332 };
2333 2333
2334 tpdm@4b0c000 { 2334 tpdm@4b0c000 {
2335 compatible = "qcom,co 2335 compatible = "qcom,coresight-tpdm", "arm,primecell";
2336 reg = <0x0 0x4b0c000 2336 reg = <0x0 0x4b0c000 0x0 0x1000>;
2337 2337
2338 clocks = <&aoss_qmp>; 2338 clocks = <&aoss_qmp>;
2339 clock-names = "apb_pc 2339 clock-names = "apb_pclk";
2340 2340
2341 qcom,cmb-element-bits 2341 qcom,cmb-element-bits = <64>;
2342 qcom,cmb-msrs-num = < 2342 qcom,cmb-msrs-num = <32>;
2343 2343
2344 out-ports { 2344 out-ports {
2345 port { 2345 port {
2346 aoss_ 2346 aoss_tpdm3_out: endpoint {
2347 2347 remote-endpoint =
2348 2348 <&aoss_tpda_in3>;
2349 }; 2349 };
2350 }; 2350 };
2351 }; 2351 };
2352 }; 2352 };
2353 2353
2354 tpdm@4b0d000 { 2354 tpdm@4b0d000 {
2355 compatible = "qcom,co 2355 compatible = "qcom,coresight-tpdm", "arm,primecell";
2356 reg = <0x0 0x4b0d000 2356 reg = <0x0 0x4b0d000 0x0 0x1000>;
2357 2357
2358 clocks = <&aoss_qmp>; 2358 clocks = <&aoss_qmp>;
2359 clock-names = "apb_pc 2359 clock-names = "apb_pclk";
2360 2360
2361 qcom,dsb-element-bits 2361 qcom,dsb-element-bits = <32>;
2362 qcom,dsb-msrs-num = < 2362 qcom,dsb-msrs-num = <32>;
2363 2363
2364 out-ports { 2364 out-ports {
2365 port { 2365 port {
2366 aoss_ 2366 aoss_tpdm4_out: endpoint {
2367 2367 remote-endpoint =
2368 2368 <&aoss_tpda_in4>;
2369 }; 2369 };
2370 }; 2370 };
2371 }; 2371 };
2372 }; 2372 };
2373 2373
2374 aoss_cti: cti@4b13000 { 2374 aoss_cti: cti@4b13000 {
2375 compatible = "arm,cor 2375 compatible = "arm,coresight-cti", "arm,primecell";
2376 reg = <0x0 0x4b13000 2376 reg = <0x0 0x4b13000 0x0 0x1000>;
2377 2377
2378 clocks = <&aoss_qmp>; 2378 clocks = <&aoss_qmp>;
2379 clock-names = "apb_pc 2379 clock-names = "apb_pclk";
2380 }; 2380 };
2381 2381
2382 etm@6040000 { 2382 etm@6040000 {
2383 compatible = "arm,pri 2383 compatible = "arm,primecell";
2384 reg = <0x0 0x6040000 2384 reg = <0x0 0x6040000 0x0 0x1000>;
2385 cpu = <&CPU0>; 2385 cpu = <&CPU0>;
2386 2386
2387 clocks = <&aoss_qmp>; 2387 clocks = <&aoss_qmp>;
2388 clock-names = "apb_pc 2388 clock-names = "apb_pclk";
2389 arm,coresight-loses-c 2389 arm,coresight-loses-context-with-cpu;
2390 qcom,skip-power-up; 2390 qcom,skip-power-up;
2391 2391
2392 out-ports { 2392 out-ports {
2393 port { 2393 port {
2394 etm0_ 2394 etm0_out: endpoint {
2395 2395 remote-endpoint =
2396 2396 <&apss_funnel0_in0>;
2397 }; 2397 };
2398 }; 2398 };
2399 }; 2399 };
2400 }; 2400 };
2401 2401
2402 etm@6140000 { 2402 etm@6140000 {
2403 compatible = "arm,pri 2403 compatible = "arm,primecell";
2404 reg = <0x0 0x6140000 2404 reg = <0x0 0x6140000 0x0 0x1000>;
2405 cpu = <&CPU1>; 2405 cpu = <&CPU1>;
2406 2406
2407 clocks = <&aoss_qmp>; 2407 clocks = <&aoss_qmp>;
2408 clock-names = "apb_pc 2408 clock-names = "apb_pclk";
2409 arm,coresight-loses-c 2409 arm,coresight-loses-context-with-cpu;
2410 qcom,skip-power-up; 2410 qcom,skip-power-up;
2411 2411
2412 out-ports { 2412 out-ports {
2413 port { 2413 port {
2414 etm1_ 2414 etm1_out: endpoint {
2415 2415 remote-endpoint =
2416 2416 <&apss_funnel0_in1>;
2417 }; 2417 };
2418 }; 2418 };
2419 }; 2419 };
2420 }; 2420 };
2421 2421
2422 etm@6240000 { 2422 etm@6240000 {
2423 compatible = "arm,pri 2423 compatible = "arm,primecell";
2424 reg = <0x0 0x6240000 2424 reg = <0x0 0x6240000 0x0 0x1000>;
2425 cpu = <&CPU2>; 2425 cpu = <&CPU2>;
2426 2426
2427 clocks = <&aoss_qmp>; 2427 clocks = <&aoss_qmp>;
2428 clock-names = "apb_pc 2428 clock-names = "apb_pclk";
2429 arm,coresight-loses-c 2429 arm,coresight-loses-context-with-cpu;
2430 qcom,skip-power-up; 2430 qcom,skip-power-up;
2431 2431
2432 out-ports { 2432 out-ports {
2433 port { 2433 port {
2434 etm2_ 2434 etm2_out: endpoint {
2435 2435 remote-endpoint =
2436 2436 <&apss_funnel0_in2>;
2437 }; 2437 };
2438 }; 2438 };
2439 }; 2439 };
2440 }; 2440 };
2441 2441
2442 etm@6340000 { 2442 etm@6340000 {
2443 compatible = "arm,pri 2443 compatible = "arm,primecell";
2444 reg = <0x0 0x6340000 2444 reg = <0x0 0x6340000 0x0 0x1000>;
2445 cpu = <&CPU3>; 2445 cpu = <&CPU3>;
2446 2446
2447 clocks = <&aoss_qmp>; 2447 clocks = <&aoss_qmp>;
2448 clock-names = "apb_pc 2448 clock-names = "apb_pclk";
2449 arm,coresight-loses-c 2449 arm,coresight-loses-context-with-cpu;
2450 qcom,skip-power-up; 2450 qcom,skip-power-up;
2451 2451
2452 out-ports { 2452 out-ports {
2453 port { 2453 port {
2454 etm3_ 2454 etm3_out: endpoint {
2455 2455 remote-endpoint =
2456 2456 <&apss_funnel0_in3>;
2457 }; 2457 };
2458 }; 2458 };
2459 }; 2459 };
2460 }; 2460 };
2461 2461
2462 etm@6440000 { 2462 etm@6440000 {
2463 compatible = "arm,pri 2463 compatible = "arm,primecell";
2464 reg = <0x0 0x6440000 2464 reg = <0x0 0x6440000 0x0 0x1000>;
2465 cpu = <&CPU4>; 2465 cpu = <&CPU4>;
2466 2466
2467 clocks = <&aoss_qmp>; 2467 clocks = <&aoss_qmp>;
2468 clock-names = "apb_pc 2468 clock-names = "apb_pclk";
2469 arm,coresight-loses-c 2469 arm,coresight-loses-context-with-cpu;
2470 qcom,skip-power-up; 2470 qcom,skip-power-up;
2471 2471
2472 out-ports { 2472 out-ports {
2473 port { 2473 port {
2474 etm4_ 2474 etm4_out: endpoint {
2475 2475 remote-endpoint =
2476 2476 <&apss_funnel0_in4>;
2477 }; 2477 };
2478 }; 2478 };
2479 }; 2479 };
2480 }; 2480 };
2481 2481
2482 etm@6540000 { 2482 etm@6540000 {
2483 compatible = "arm,pri 2483 compatible = "arm,primecell";
2484 reg = <0x0 0x6540000 2484 reg = <0x0 0x6540000 0x0 0x1000>;
2485 cpu = <&CPU5>; 2485 cpu = <&CPU5>;
2486 2486
2487 clocks = <&aoss_qmp>; 2487 clocks = <&aoss_qmp>;
2488 clock-names = "apb_pc 2488 clock-names = "apb_pclk";
2489 arm,coresight-loses-c 2489 arm,coresight-loses-context-with-cpu;
2490 qcom,skip-power-up; 2490 qcom,skip-power-up;
2491 2491
2492 out-ports { 2492 out-ports {
2493 port { 2493 port {
2494 etm5_ 2494 etm5_out: endpoint {
2495 2495 remote-endpoint =
2496 2496 <&apss_funnel0_in5>;
2497 }; 2497 };
2498 }; 2498 };
2499 }; 2499 };
2500 }; 2500 };
2501 2501
2502 etm@6640000 { 2502 etm@6640000 {
2503 compatible = "arm,pri 2503 compatible = "arm,primecell";
2504 reg = <0x0 0x6640000 2504 reg = <0x0 0x6640000 0x0 0x1000>;
2505 cpu = <&CPU6>; 2505 cpu = <&CPU6>;
2506 2506
2507 clocks = <&aoss_qmp>; 2507 clocks = <&aoss_qmp>;
2508 clock-names = "apb_pc 2508 clock-names = "apb_pclk";
2509 arm,coresight-loses-c 2509 arm,coresight-loses-context-with-cpu;
2510 qcom,skip-power-up; 2510 qcom,skip-power-up;
2511 2511
2512 out-ports { 2512 out-ports {
2513 port { 2513 port {
2514 etm6_ 2514 etm6_out: endpoint {
2515 2515 remote-endpoint =
2516 2516 <&apss_funnel0_in6>;
2517 }; 2517 };
2518 }; 2518 };
2519 }; 2519 };
2520 }; 2520 };
2521 2521
2522 etm@6740000 { 2522 etm@6740000 {
2523 compatible = "arm,pri 2523 compatible = "arm,primecell";
2524 reg = <0x0 0x6740000 2524 reg = <0x0 0x6740000 0x0 0x1000>;
2525 cpu = <&CPU7>; 2525 cpu = <&CPU7>;
2526 2526
2527 clocks = <&aoss_qmp>; 2527 clocks = <&aoss_qmp>;
2528 clock-names = "apb_pc 2528 clock-names = "apb_pclk";
2529 arm,coresight-loses-c 2529 arm,coresight-loses-context-with-cpu;
2530 qcom,skip-power-up; 2530 qcom,skip-power-up;
2531 2531
2532 out-ports { 2532 out-ports {
2533 port { 2533 port {
2534 etm7_ 2534 etm7_out: endpoint {
2535 2535 remote-endpoint =
2536 2536 <&apss_funnel0_in7>;
2537 }; 2537 };
2538 }; 2538 };
2539 }; 2539 };
2540 }; 2540 };
2541 2541
2542 funnel@6800000 { 2542 funnel@6800000 {
2543 compatible = "arm,cor 2543 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2544 reg = <0x0 0x6800000 2544 reg = <0x0 0x6800000 0x0 0x1000>;
2545 2545
2546 clocks = <&aoss_qmp>; 2546 clocks = <&aoss_qmp>;
2547 clock-names = "apb_pc 2547 clock-names = "apb_pclk";
2548 2548
2549 out-ports { 2549 out-ports {
2550 port { 2550 port {
2551 apss_ 2551 apss_funnel0_out: endpoint {
2552 2552 remote-endpoint =
2553 2553 <&apss_funnel1_in0>;
2554 }; 2554 };
2555 }; 2555 };
2556 }; 2556 };
2557 2557
2558 in-ports { 2558 in-ports {
2559 #address-cell 2559 #address-cells = <1>;
2560 #size-cells = 2560 #size-cells = <0>;
2561 2561
2562 port@0 { 2562 port@0 {
2563 reg = 2563 reg = <0>;
2564 apss_ 2564 apss_funnel0_in0: endpoint {
2565 2565 remote-endpoint =
2566 2566 <&etm0_out>;
2567 }; 2567 };
2568 }; 2568 };
2569 2569
2570 port@1 { 2570 port@1 {
2571 reg = 2571 reg = <1>;
2572 apss_ 2572 apss_funnel0_in1: endpoint {
2573 2573 remote-endpoint =
2574 2574 <&etm1_out>;
2575 }; 2575 };
2576 }; 2576 };
2577 2577
2578 port@2 { 2578 port@2 {
2579 reg = 2579 reg = <2>;
2580 apss_ 2580 apss_funnel0_in2: endpoint {
2581 2581 remote-endpoint =
2582 2582 <&etm2_out>;
2583 }; 2583 };
2584 }; 2584 };
2585 2585
2586 port@3 { 2586 port@3 {
2587 reg = 2587 reg = <3>;
2588 apss_ 2588 apss_funnel0_in3: endpoint {
2589 2589 remote-endpoint =
2590 2590 <&etm3_out>;
2591 }; 2591 };
2592 }; 2592 };
2593 2593
2594 port@4 { 2594 port@4 {
2595 reg = 2595 reg = <4>;
2596 apss_ 2596 apss_funnel0_in4: endpoint {
2597 2597 remote-endpoint =
2598 2598 <&etm4_out>;
2599 }; 2599 };
2600 }; 2600 };
2601 2601
2602 port@5 { 2602 port@5 {
2603 reg = 2603 reg = <5>;
2604 apss_ 2604 apss_funnel0_in5: endpoint {
2605 2605 remote-endpoint =
2606 2606 <&etm5_out>;
2607 }; 2607 };
2608 }; 2608 };
2609 2609
2610 port@6 { 2610 port@6 {
2611 reg = 2611 reg = <6>;
2612 apss_ 2612 apss_funnel0_in6: endpoint {
2613 2613 remote-endpoint =
2614 2614 <&etm6_out>;
2615 }; 2615 };
2616 }; 2616 };
2617 2617
2618 port@7 { 2618 port@7 {
2619 reg = 2619 reg = <7>;
2620 apss_ 2620 apss_funnel0_in7: endpoint {
2621 2621 remote-endpoint =
2622 2622 <&etm7_out>;
2623 }; 2623 };
2624 }; 2624 };
2625 }; 2625 };
2626 }; 2626 };
2627 2627
2628 funnel@6810000 { 2628 funnel@6810000 {
2629 compatible = "arm,cor 2629 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2630 reg = <0x0 0x6810000 2630 reg = <0x0 0x6810000 0x0 0x1000>;
2631 2631
2632 clocks = <&aoss_qmp>; 2632 clocks = <&aoss_qmp>;
2633 clock-names = "apb_pc 2633 clock-names = "apb_pclk";
2634 2634
2635 out-ports { 2635 out-ports {
2636 port { 2636 port {
2637 apss_ 2637 apss_funnel1_out: endpoint {
2638 2638 remote-endpoint =
2639 2639 <&funnel1_in4>;
2640 }; 2640 };
2641 }; 2641 };
2642 }; 2642 };
2643 2643
2644 in-ports { 2644 in-ports {
2645 #address-cell 2645 #address-cells = <1>;
2646 #size-cells = 2646 #size-cells = <0>;
2647 2647
2648 port@0 { 2648 port@0 {
2649 reg = 2649 reg = <0>;
2650 apss_ 2650 apss_funnel1_in0: endpoint {
2651 2651 remote-endpoint =
2652 2652 <&apss_funnel0_out>;
2653 }; 2653 };
2654 }; 2654 };
2655 2655
2656 port@3 { 2656 port@3 {
2657 reg = 2657 reg = <3>;
2658 apss_ 2658 apss_funnel1_in3: endpoint {
2659 2659 remote-endpoint =
2660 2660 <&apss_tpda_out>;
2661 }; 2661 };
2662 }; 2662 };
2663 }; 2663 };
2664 }; 2664 };
2665 2665
2666 tpdm@6860000 { 2666 tpdm@6860000 {
2667 compatible = "qcom,co 2667 compatible = "qcom,coresight-tpdm", "arm,primecell";
2668 reg = <0x0 0x6860000 2668 reg = <0x0 0x6860000 0x0 0x1000>;
2669 2669
2670 clocks = <&aoss_qmp>; 2670 clocks = <&aoss_qmp>;
2671 clock-names = "apb_pc 2671 clock-names = "apb_pclk";
2672 2672
2673 qcom,cmb-element-bits 2673 qcom,cmb-element-bits = <64>;
2674 qcom,cmb-msrs-num = < 2674 qcom,cmb-msrs-num = <32>;
2675 2675
2676 out-ports { 2676 out-ports {
2677 port { 2677 port {
2678 apss_ 2678 apss_tpdm3_out: endpoint {
2679 2679 remote-endpoint =
2680 2680 <&apss_tpda_in3>;
2681 }; 2681 };
2682 }; 2682 };
2683 }; 2683 };
2684 }; 2684 };
2685 2685
2686 tpdm@6861000 { 2686 tpdm@6861000 {
2687 compatible = "qcom,co 2687 compatible = "qcom,coresight-tpdm", "arm,primecell";
2688 reg = <0x0 0x6861000 2688 reg = <0x0 0x6861000 0x0 0x1000>;
2689 2689
2690 clocks = <&aoss_qmp>; 2690 clocks = <&aoss_qmp>;
2691 clock-names = "apb_pc 2691 clock-names = "apb_pclk";
2692 2692
2693 qcom,dsb-element-bits 2693 qcom,dsb-element-bits = <32>;
2694 qcom,dsb-msrs-num = < 2694 qcom,dsb-msrs-num = <32>;
2695 2695
2696 out-ports { 2696 out-ports {
2697 port { 2697 port {
2698 apss_ 2698 apss_tpdm4_out: endpoint {
2699 2699 remote-endpoint =
2700 2700 <&apss_tpda_in4>;
2701 }; 2701 };
2702 }; 2702 };
2703 }; 2703 };
2704 }; 2704 };
2705 2705
2706 tpda@6863000 { 2706 tpda@6863000 {
2707 compatible = "qcom,co 2707 compatible = "qcom,coresight-tpda", "arm,primecell";
2708 reg = <0x0 0x6863000 2708 reg = <0x0 0x6863000 0x0 0x1000>;
2709 2709
2710 clocks = <&aoss_qmp>; 2710 clocks = <&aoss_qmp>;
2711 clock-names = "apb_pc 2711 clock-names = "apb_pclk";
2712 2712
2713 out-ports { 2713 out-ports {
2714 port { 2714 port {
2715 apss_ 2715 apss_tpda_out: endpoint {
2716 2716 remote-endpoint =
2717 2717 <&apss_funnel1_in3>;
2718 }; 2718 };
2719 }; 2719 };
2720 }; 2720 };
2721 2721
2722 in-ports { 2722 in-ports {
2723 #address-cell 2723 #address-cells = <1>;
2724 #size-cells = 2724 #size-cells = <0>;
2725 2725
2726 port@0 { 2726 port@0 {
2727 reg = 2727 reg = <0>;
2728 apss_ 2728 apss_tpda_in0: endpoint {
2729 2729 remote-endpoint =
2730 2730 <&apss_tpdm0_out>;
2731 }; 2731 };
2732 }; 2732 };
2733 2733
2734 port@1 { 2734 port@1 {
2735 reg = 2735 reg = <1>;
2736 apss_ 2736 apss_tpda_in1: endpoint {
2737 2737 remote-endpoint =
2738 2738 <&apss_tpdm1_out>;
2739 }; 2739 };
2740 }; 2740 };
2741 2741
2742 port@2 { 2742 port@2 {
2743 reg = 2743 reg = <2>;
2744 apss_ 2744 apss_tpda_in2: endpoint {
2745 2745 remote-endpoint =
2746 2746 <&apss_tpdm2_out>;
2747 }; 2747 };
2748 }; 2748 };
2749 2749
2750 port@3 { 2750 port@3 {
2751 reg = 2751 reg = <3>;
2752 apss_ 2752 apss_tpda_in3: endpoint {
2753 2753 remote-endpoint =
2754 2754 <&apss_tpdm3_out>;
2755 }; 2755 };
2756 }; 2756 };
2757 2757
2758 port@4 { 2758 port@4 {
2759 reg = 2759 reg = <4>;
2760 apss_ 2760 apss_tpda_in4: endpoint {
2761 2761 remote-endpoint =
2762 2762 <&apss_tpdm4_out>;
2763 }; 2763 };
2764 }; 2764 };
2765 }; 2765 };
2766 }; 2766 };
2767 2767
2768 tpdm@68a0000 { 2768 tpdm@68a0000 {
2769 compatible = "qcom,co 2769 compatible = "qcom,coresight-tpdm", "arm,primecell";
2770 reg = <0x0 0x68a0000 2770 reg = <0x0 0x68a0000 0x0 0x1000>;
2771 2771
2772 clocks = <&aoss_qmp>; 2772 clocks = <&aoss_qmp>;
2773 clock-names = "apb_pc 2773 clock-names = "apb_pclk";
2774 2774
2775 qcom,cmb-element-bits 2775 qcom,cmb-element-bits = <32>;
2776 qcom,cmb-msrs-num = < 2776 qcom,cmb-msrs-num = <32>;
2777 2777
2778 out-ports { 2778 out-ports {
2779 port { 2779 port {
2780 apss_ 2780 apss_tpdm0_out: endpoint {
2781 2781 remote-endpoint =
2782 2782 <&apss_tpda_in0>;
2783 }; 2783 };
2784 }; 2784 };
2785 }; 2785 };
2786 }; 2786 };
2787 2787
2788 tpdm@68b0000 { 2788 tpdm@68b0000 {
2789 compatible = "qcom,co 2789 compatible = "qcom,coresight-tpdm", "arm,primecell";
2790 reg = <0x0 0x68b0000 2790 reg = <0x0 0x68b0000 0x0 0x1000>;
2791 2791
2792 clocks = <&aoss_qmp>; 2792 clocks = <&aoss_qmp>;
2793 clock-names = "apb_pc 2793 clock-names = "apb_pclk";
2794 2794
2795 qcom,cmb-element-bits 2795 qcom,cmb-element-bits = <32>;
2796 qcom,cmb-msrs-num = < 2796 qcom,cmb-msrs-num = <32>;
2797 2797
2798 out-ports { 2798 out-ports {
2799 port { 2799 port {
2800 apss_ 2800 apss_tpdm1_out: endpoint {
2801 2801 remote-endpoint =
2802 2802 <&apss_tpda_in1>;
2803 }; 2803 };
2804 }; 2804 };
2805 }; 2805 };
2806 }; 2806 };
2807 2807
2808 tpdm@68c0000 { 2808 tpdm@68c0000 {
2809 compatible = "qcom,co 2809 compatible = "qcom,coresight-tpdm", "arm,primecell";
2810 reg = <0x0 0x68c0000 2810 reg = <0x0 0x68c0000 0x0 0x1000>;
2811 2811
2812 clocks = <&aoss_qmp>; 2812 clocks = <&aoss_qmp>;
2813 clock-names = "apb_pc 2813 clock-names = "apb_pclk";
2814 2814
2815 qcom,dsb-element-bits 2815 qcom,dsb-element-bits = <32>;
2816 qcom,dsb-msrs-num = < 2816 qcom,dsb-msrs-num = <32>;
2817 2817
2818 out-ports { 2818 out-ports {
2819 port { 2819 port {
2820 apss_ 2820 apss_tpdm2_out: endpoint {
2821 2821 remote-endpoint =
2822 2822 <&apss_tpda_in2>;
2823 }; 2823 };
2824 }; 2824 };
2825 }; 2825 };
2826 }; 2826 };
2827 2827
2828 usb_0_hsphy: phy@88e4000 { 2828 usb_0_hsphy: phy@88e4000 {
2829 compatible = "qcom,sa 2829 compatible = "qcom,sa8775p-usb-hs-phy",
2830 "qcom,us 2830 "qcom,usb-snps-hs-5nm-phy";
2831 reg = <0 0x088e4000 0 2831 reg = <0 0x088e4000 0 0x120>;
2832 clocks = <&rpmhcc RPM 2832 clocks = <&rpmhcc RPMH_CXO_CLK>;
2833 clock-names = "ref"; 2833 clock-names = "ref";
2834 resets = <&gcc GCC_US 2834 resets = <&gcc GCC_USB2_PHY_PRIM_BCR>;
2835 2835
2836 #phy-cells = <0>; 2836 #phy-cells = <0>;
2837 2837
2838 status = "disabled"; 2838 status = "disabled";
2839 }; 2839 };
2840 2840
2841 usb_0_qmpphy: phy@88e8000 { 2841 usb_0_qmpphy: phy@88e8000 {
2842 compatible = "qcom,sa 2842 compatible = "qcom,sa8775p-qmp-usb3-uni-phy";
2843 reg = <0 0x088e8000 0 2843 reg = <0 0x088e8000 0 0x2000>;
2844 2844
2845 clocks = <&gcc GCC_US 2845 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2846 <&gcc GCC_US 2846 <&gcc GCC_USB_CLKREF_EN>,
2847 <&gcc GCC_US 2847 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
2848 <&gcc GCC_US 2848 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2849 clock-names = "aux", 2849 clock-names = "aux", "ref", "com_aux", "pipe";
2850 2850
2851 resets = <&gcc GCC_US 2851 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
2852 <&gcc GCC_US 2852 <&gcc GCC_USB3PHY_PHY_PRIM_BCR>;
2853 reset-names = "phy", 2853 reset-names = "phy", "phy_phy";
2854 2854
2855 power-domains = <&gcc 2855 power-domains = <&gcc USB30_PRIM_GDSC>;
2856 2856
2857 #clock-cells = <0>; 2857 #clock-cells = <0>;
2858 clock-output-names = 2858 clock-output-names = "usb3_prim_phy_pipe_clk_src";
2859 2859
2860 #phy-cells = <0>; 2860 #phy-cells = <0>;
2861 2861
2862 status = "disabled"; 2862 status = "disabled";
2863 }; 2863 };
2864 2864
2865 usb_0: usb@a6f8800 { 2865 usb_0: usb@a6f8800 {
2866 compatible = "qcom,sa 2866 compatible = "qcom,sa8775p-dwc3", "qcom,dwc3";
2867 reg = <0 0x0a6f8800 0 2867 reg = <0 0x0a6f8800 0 0x400>;
2868 #address-cells = <2>; 2868 #address-cells = <2>;
2869 #size-cells = <2>; 2869 #size-cells = <2>;
2870 ranges; 2870 ranges;
2871 2871
2872 clocks = <&gcc GCC_CF 2872 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
2873 <&gcc GCC_US 2873 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
2874 <&gcc GCC_AG 2874 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
2875 <&gcc GCC_US 2875 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
2876 <&gcc GCC_US 2876 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
2877 clock-names = "cfg_no 2877 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi";
2878 2878
2879 assigned-clocks = <&g 2879 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2880 <&g 2880 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
2881 assigned-clock-rates 2881 assigned-clock-rates = <19200000>, <200000000>;
2882 2882
2883 interrupts-extended = 2883 interrupts-extended = <&intc GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>,
2884 2884 <&intc GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
2885 2885 <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
2886 2886 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
2887 2887 <&pdc 12 IRQ_TYPE_LEVEL_HIGH>;
2888 interrupt-names = "pw 2888 interrupt-names = "pwr_event",
2889 "hs 2889 "hs_phy_irq",
2890 "dp 2890 "dp_hs_phy_irq",
2891 "dm 2891 "dm_hs_phy_irq",
2892 "ss 2892 "ss_phy_irq";
2893 2893
2894 power-domains = <&gcc 2894 power-domains = <&gcc USB30_PRIM_GDSC>;
2895 required-opps = <&rpm 2895 required-opps = <&rpmhpd_opp_nom>;
2896 2896
2897 resets = <&gcc GCC_US 2897 resets = <&gcc GCC_USB30_PRIM_BCR>;
2898 2898
2899 interconnects = <&agg 2899 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
2900 <&gem 2900 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
2901 interconnect-names = 2901 interconnect-names = "usb-ddr", "apps-usb";
2902 2902
2903 wakeup-source; 2903 wakeup-source;
2904 2904
2905 status = "disabled"; 2905 status = "disabled";
2906 2906
2907 usb_0_dwc3: usb@a6000 2907 usb_0_dwc3: usb@a600000 {
2908 compatible = 2908 compatible = "snps,dwc3";
2909 reg = <0 0x0a 2909 reg = <0 0x0a600000 0 0xe000>;
2910 interrupts = 2910 interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>;
2911 iommus = <&ap 2911 iommus = <&apps_smmu 0x080 0x0>;
2912 phys = <&usb_ 2912 phys = <&usb_0_hsphy>, <&usb_0_qmpphy>;
2913 phy-names = " 2913 phy-names = "usb2-phy", "usb3-phy";
2914 }; 2914 };
2915 }; 2915 };
2916 2916
2917 usb_1_hsphy: phy@88e6000 { 2917 usb_1_hsphy: phy@88e6000 {
2918 compatible = "qcom,sa 2918 compatible = "qcom,sa8775p-usb-hs-phy",
2919 "qcom,us 2919 "qcom,usb-snps-hs-5nm-phy";
2920 reg = <0 0x088e6000 0 2920 reg = <0 0x088e6000 0 0x120>;
2921 clocks = <&gcc GCC_US 2921 clocks = <&gcc GCC_USB_CLKREF_EN>;
2922 clock-names = "ref"; 2922 clock-names = "ref";
2923 resets = <&gcc GCC_US 2923 resets = <&gcc GCC_USB2_PHY_SEC_BCR>;
2924 2924
2925 #phy-cells = <0>; 2925 #phy-cells = <0>;
2926 2926
2927 status = "disabled"; 2927 status = "disabled";
2928 }; 2928 };
2929 2929
2930 usb_1_qmpphy: phy@88ea000 { 2930 usb_1_qmpphy: phy@88ea000 {
2931 compatible = "qcom,sa 2931 compatible = "qcom,sa8775p-qmp-usb3-uni-phy";
2932 reg = <0 0x088ea000 0 2932 reg = <0 0x088ea000 0 0x2000>;
2933 2933
2934 clocks = <&gcc GCC_US 2934 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
2935 <&gcc GCC_US 2935 <&gcc GCC_USB_CLKREF_EN>,
2936 <&gcc GCC_US 2936 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
2937 <&gcc GCC_US 2937 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
2938 clock-names = "aux", 2938 clock-names = "aux", "ref", "com_aux", "pipe";
2939 2939
2940 resets = <&gcc GCC_US 2940 resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
2941 <&gcc GCC_US 2941 <&gcc GCC_USB3PHY_PHY_SEC_BCR>;
2942 reset-names = "phy", 2942 reset-names = "phy", "phy_phy";
2943 2943
2944 power-domains = <&gcc 2944 power-domains = <&gcc USB30_SEC_GDSC>;
2945 2945
2946 #clock-cells = <0>; 2946 #clock-cells = <0>;
2947 clock-output-names = 2947 clock-output-names = "usb3_sec_phy_pipe_clk_src";
2948 2948
2949 #phy-cells = <0>; 2949 #phy-cells = <0>;
2950 2950
2951 status = "disabled"; 2951 status = "disabled";
2952 }; 2952 };
2953 2953
2954 usb_1: usb@a8f8800 { 2954 usb_1: usb@a8f8800 {
2955 compatible = "qcom,sa 2955 compatible = "qcom,sa8775p-dwc3", "qcom,dwc3";
2956 reg = <0 0x0a8f8800 0 2956 reg = <0 0x0a8f8800 0 0x400>;
2957 #address-cells = <2>; 2957 #address-cells = <2>;
2958 #size-cells = <2>; 2958 #size-cells = <2>;
2959 ranges; 2959 ranges;
2960 2960
2961 clocks = <&gcc GCC_CF 2961 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
2962 <&gcc GCC_US 2962 <&gcc GCC_USB30_SEC_MASTER_CLK>,
2963 <&gcc GCC_AG 2963 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
2964 <&gcc GCC_US 2964 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
2965 <&gcc GCC_US 2965 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>;
2966 clock-names = "cfg_no 2966 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi";
2967 2967
2968 assigned-clocks = <&g 2968 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2969 <&g 2969 <&gcc GCC_USB30_SEC_MASTER_CLK>;
2970 assigned-clock-rates 2970 assigned-clock-rates = <19200000>, <200000000>;
2971 2971
2972 interrupts-extended = 2972 interrupts-extended = <&intc GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
2973 2973 <&intc GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
2974 2974 <&pdc 8 IRQ_TYPE_EDGE_BOTH>,
2975 2975 <&pdc 7 IRQ_TYPE_EDGE_BOTH>,
2976 2976 <&pdc 13 IRQ_TYPE_LEVEL_HIGH>;
2977 interrupt-names = "pw 2977 interrupt-names = "pwr_event",
2978 "hs 2978 "hs_phy_irq",
2979 "dp 2979 "dp_hs_phy_irq",
2980 "dm 2980 "dm_hs_phy_irq",
2981 "ss 2981 "ss_phy_irq";
2982 2982
2983 power-domains = <&gcc 2983 power-domains = <&gcc USB30_SEC_GDSC>;
2984 required-opps = <&rpm 2984 required-opps = <&rpmhpd_opp_nom>;
2985 2985
2986 resets = <&gcc GCC_US 2986 resets = <&gcc GCC_USB30_SEC_BCR>;
2987 2987
2988 interconnects = <&agg 2988 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>,
2989 <&gem 2989 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
2990 interconnect-names = 2990 interconnect-names = "usb-ddr", "apps-usb";
2991 2991
2992 wakeup-source; 2992 wakeup-source;
2993 2993
2994 status = "disabled"; 2994 status = "disabled";
2995 2995
2996 usb_1_dwc3: usb@a8000 2996 usb_1_dwc3: usb@a800000 {
2997 compatible = 2997 compatible = "snps,dwc3";
2998 reg = <0 0x0a 2998 reg = <0 0x0a800000 0 0xe000>;
2999 interrupts = 2999 interrupts = <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>;
3000 iommus = <&ap 3000 iommus = <&apps_smmu 0x0a0 0x0>;
3001 phys = <&usb_ 3001 phys = <&usb_1_hsphy>, <&usb_1_qmpphy>;
3002 phy-names = " 3002 phy-names = "usb2-phy", "usb3-phy";
3003 }; 3003 };
3004 }; 3004 };
3005 3005
3006 usb_2_hsphy: phy@88e7000 { 3006 usb_2_hsphy: phy@88e7000 {
3007 compatible = "qcom,sa 3007 compatible = "qcom,sa8775p-usb-hs-phy",
3008 "qcom,us 3008 "qcom,usb-snps-hs-5nm-phy";
3009 reg = <0 0x088e7000 0 3009 reg = <0 0x088e7000 0 0x120>;
3010 clocks = <&gcc GCC_US 3010 clocks = <&gcc GCC_USB_CLKREF_EN>;
3011 clock-names = "ref"; 3011 clock-names = "ref";
3012 resets = <&gcc GCC_US 3012 resets = <&gcc GCC_USB3_PHY_TERT_BCR>;
3013 3013
3014 #phy-cells = <0>; 3014 #phy-cells = <0>;
3015 3015
3016 status = "disabled"; 3016 status = "disabled";
3017 }; 3017 };
3018 3018
3019 usb_2: usb@a4f8800 { 3019 usb_2: usb@a4f8800 {
3020 compatible = "qcom,sa 3020 compatible = "qcom,sa8775p-dwc3", "qcom,dwc3";
3021 reg = <0 0x0a4f8800 0 3021 reg = <0 0x0a4f8800 0 0x400>;
3022 #address-cells = <2>; 3022 #address-cells = <2>;
3023 #size-cells = <2>; 3023 #size-cells = <2>;
3024 ranges; 3024 ranges;
3025 3025
3026 clocks = <&gcc GCC_CF 3026 clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>,
3027 <&gcc GCC_US 3027 <&gcc GCC_USB20_MASTER_CLK>,
3028 <&gcc GCC_AG 3028 <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>,
3029 <&gcc GCC_US 3029 <&gcc GCC_USB20_SLEEP_CLK>,
3030 <&gcc GCC_US 3030 <&gcc GCC_USB20_MOCK_UTMI_CLK>;
3031 clock-names = "cfg_no 3031 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi";
3032 3032
3033 assigned-clocks = <&g 3033 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
3034 <&g 3034 <&gcc GCC_USB20_MASTER_CLK>;
3035 assigned-clock-rates 3035 assigned-clock-rates = <19200000>, <200000000>;
3036 3036
3037 interrupts-extended = 3037 interrupts-extended = <&intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
3038 3038 <&intc GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>,
3039 3039 <&pdc 10 IRQ_TYPE_EDGE_BOTH>,
3040 3040 <&pdc 9 IRQ_TYPE_EDGE_BOTH>;
3041 interrupt-names = "pw 3041 interrupt-names = "pwr_event",
3042 "hs 3042 "hs_phy_irq",
3043 "dp 3043 "dp_hs_phy_irq",
3044 "dm 3044 "dm_hs_phy_irq";
3045 3045
3046 power-domains = <&gcc 3046 power-domains = <&gcc USB20_PRIM_GDSC>;
3047 required-opps = <&rpm 3047 required-opps = <&rpmhpd_opp_nom>;
3048 3048
3049 resets = <&gcc GCC_US 3049 resets = <&gcc GCC_USB20_PRIM_BCR>;
3050 3050
3051 interconnects = <&agg 3051 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>,
3052 <&gem 3052 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB2 0>;
3053 interconnect-names = 3053 interconnect-names = "usb-ddr", "apps-usb";
3054 3054
3055 wakeup-source; 3055 wakeup-source;
3056 3056
3057 status = "disabled"; 3057 status = "disabled";
3058 3058
3059 usb_2_dwc3: usb@a4000 3059 usb_2_dwc3: usb@a400000 {
3060 compatible = 3060 compatible = "snps,dwc3";
3061 reg = <0 0x0a 3061 reg = <0 0x0a400000 0 0xe000>;
3062 interrupts = 3062 interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>;
3063 iommus = <&ap 3063 iommus = <&apps_smmu 0x020 0x0>;
3064 phys = <&usb_ 3064 phys = <&usb_2_hsphy>;
3065 phy-names = " 3065 phy-names = "usb2-phy";
3066 }; 3066 };
3067 }; 3067 };
3068 3068
3069 tcsr_mutex: hwlock@1f40000 { 3069 tcsr_mutex: hwlock@1f40000 {
3070 compatible = "qcom,tc 3070 compatible = "qcom,tcsr-mutex";
3071 reg = <0x0 0x01f40000 3071 reg = <0x0 0x01f40000 0x0 0x20000>;
3072 #hwlock-cells = <1>; 3072 #hwlock-cells = <1>;
3073 }; 3073 };
3074 3074
3075 gpucc: clock-controller@3d900 3075 gpucc: clock-controller@3d90000 {
3076 compatible = "qcom,sa 3076 compatible = "qcom,sa8775p-gpucc";
3077 reg = <0x0 0x03d90000 3077 reg = <0x0 0x03d90000 0x0 0xa000>;
3078 clocks = <&rpmhcc RPM 3078 clocks = <&rpmhcc RPMH_CXO_CLK>,
3079 <&gcc GCC_GP 3079 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
3080 <&gcc GCC_GP 3080 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
3081 clock-names = "bi_tcx 3081 clock-names = "bi_tcxo",
3082 "gcc_gp 3082 "gcc_gpu_gpll0_clk_src",
3083 "gcc_gp 3083 "gcc_gpu_gpll0_div_clk_src";
3084 #clock-cells = <1>; 3084 #clock-cells = <1>;
3085 #reset-cells = <1>; 3085 #reset-cells = <1>;
3086 #power-domain-cells = 3086 #power-domain-cells = <1>;
3087 }; 3087 };
3088 3088
3089 adreno_smmu: iommu@3da0000 { 3089 adreno_smmu: iommu@3da0000 {
3090 compatible = "qcom,sa 3090 compatible = "qcom,sa8775p-smmu-500", "qcom,adreno-smmu",
3091 "qcom,sm 3091 "qcom,smmu-500", "arm,mmu-500";
3092 reg = <0x0 0x03da0000 3092 reg = <0x0 0x03da0000 0x0 0x20000>;
3093 #iommu-cells = <2>; 3093 #iommu-cells = <2>;
3094 #global-interrupts = 3094 #global-interrupts = <2>;
3095 dma-coherent; 3095 dma-coherent;
3096 power-domains = <&gpu 3096 power-domains = <&gpucc GPU_CC_CX_GDSC>;
3097 clocks = <&gcc GCC_GP 3097 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
3098 <&gcc GCC_GP 3098 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
3099 <&gpucc GPU_ 3099 <&gpucc GPU_CC_AHB_CLK>,
3100 <&gpucc GPU_ 3100 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
3101 <&gpucc GPU_ 3101 <&gpucc GPU_CC_CX_GMU_CLK>,
3102 <&gpucc GPU_ 3102 <&gpucc GPU_CC_HUB_CX_INT_CLK>,
3103 <&gpucc GPU_ 3103 <&gpucc GPU_CC_HUB_AON_CLK>;
3104 clock-names = "gcc_gp 3104 clock-names = "gcc_gpu_memnoc_gfx_clk",
3105 "gcc_gp 3105 "gcc_gpu_snoc_dvm_gfx_clk",
3106 "gpu_cc 3106 "gpu_cc_ahb_clk",
3107 "gpu_cc 3107 "gpu_cc_hlos1_vote_gpu_smmu_clk",
3108 "gpu_cc 3108 "gpu_cc_cx_gmu_clk",
3109 "gpu_cc 3109 "gpu_cc_hub_cx_int_clk",
3110 "gpu_cc 3110 "gpu_cc_hub_aon_clk";
3111 interrupts = <GIC_SPI 3111 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
3112 <GIC_SPI 3112 <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
3113 <GIC_SPI 3113 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
3114 <GIC_SPI 3114 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
3115 <GIC_SPI 3115 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
3116 <GIC_SPI 3116 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
3117 <GIC_SPI 3117 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
3118 <GIC_SPI 3118 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
3119 <GIC_SPI 3119 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
3120 <GIC_SPI 3120 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
3121 <GIC_SPI 3121 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
3122 <GIC_SPI 3122 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>;
3123 }; 3123 };
3124 3124
3125 serdes0: phy@8901000 { 3125 serdes0: phy@8901000 {
3126 compatible = "qcom,sa 3126 compatible = "qcom,sa8775p-dwmac-sgmii-phy";
3127 reg = <0x0 0x08901000 3127 reg = <0x0 0x08901000 0x0 0xe10>;
3128 clocks = <&gcc GCC_SG 3128 clocks = <&gcc GCC_SGMI_CLKREF_EN>;
3129 clock-names = "sgmi_r 3129 clock-names = "sgmi_ref";
3130 #phy-cells = <0>; 3130 #phy-cells = <0>;
3131 status = "disabled"; 3131 status = "disabled";
3132 }; 3132 };
3133 3133
3134 serdes1: phy@8902000 { 3134 serdes1: phy@8902000 {
3135 compatible = "qcom,sa 3135 compatible = "qcom,sa8775p-dwmac-sgmii-phy";
3136 reg = <0x0 0x08902000 3136 reg = <0x0 0x08902000 0x0 0xe10>;
3137 clocks = <&gcc GCC_SG 3137 clocks = <&gcc GCC_SGMI_CLKREF_EN>;
3138 clock-names = "sgmi_r 3138 clock-names = "sgmi_ref";
3139 #phy-cells = <0>; 3139 #phy-cells = <0>;
3140 status = "disabled"; 3140 status = "disabled";
3141 }; 3141 };
3142 3142
3143 pmu@9091000 { 3143 pmu@9091000 {
3144 compatible = "qcom,sa 3144 compatible = "qcom,sa8775p-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
3145 reg = <0x0 0x9091000 3145 reg = <0x0 0x9091000 0x0 0x1000>;
3146 interrupts = <GIC_SPI 3146 interrupts = <GIC_SPI 620 IRQ_TYPE_LEVEL_HIGH>;
3147 interconnects = <&mc_ 3147 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
3148 &mc_ 3148 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>;
3149 3149
3150 operating-points-v2 = 3150 operating-points-v2 = <&llcc_bwmon_opp_table>;
3151 3151
3152 llcc_bwmon_opp_table: 3152 llcc_bwmon_opp_table: opp-table {
3153 compatible = 3153 compatible = "operating-points-v2";
3154 3154
3155 opp-0 { 3155 opp-0 {
3156 opp-p 3156 opp-peak-kBps = <762000>;
3157 }; 3157 };
3158 3158
3159 opp-1 { 3159 opp-1 {
3160 opp-p 3160 opp-peak-kBps = <1720000>;
3161 }; 3161 };
3162 3162
3163 opp-2 { 3163 opp-2 {
3164 opp-p 3164 opp-peak-kBps = <2086000>;
3165 }; 3165 };
3166 3166
3167 opp-3 { 3167 opp-3 {
3168 opp-p 3168 opp-peak-kBps = <2601000>;
3169 }; 3169 };
3170 3170
3171 opp-4 { 3171 opp-4 {
3172 opp-p 3172 opp-peak-kBps = <2929000>;
3173 }; 3173 };
3174 3174
3175 opp-5 { 3175 opp-5 {
3176 opp-p 3176 opp-peak-kBps = <5931000>;
3177 }; 3177 };
3178 3178
3179 opp-6 { 3179 opp-6 {
3180 opp-p 3180 opp-peak-kBps = <6515000>;
3181 }; 3181 };
3182 3182
3183 opp-7 { 3183 opp-7 {
3184 opp-p 3184 opp-peak-kBps = <7984000>;
3185 }; 3185 };
3186 3186
3187 opp-8 { 3187 opp-8 {
3188 opp-p 3188 opp-peak-kBps = <10437000>;
3189 }; 3189 };
3190 3190
3191 opp-9 { 3191 opp-9 {
3192 opp-p 3192 opp-peak-kBps = <12195000>;
3193 }; 3193 };
3194 }; 3194 };
3195 }; 3195 };
3196 3196
3197 pmu@90b5400 { 3197 pmu@90b5400 {
3198 compatible = "qcom,sa 3198 compatible = "qcom,sa8775p-cpu-bwmon", "qcom,sdm845-bwmon";
3199 reg = <0x0 0x90b5400 3199 reg = <0x0 0x90b5400 0x0 0x600>;
3200 interrupts = <GIC_SPI 3200 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
3201 interconnects = <&gem 3201 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
3202 &gem 3202 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>;
3203 3203
3204 operating-points-v2 = 3204 operating-points-v2 = <&cpu_bwmon_opp_table>;
3205 3205
3206 cpu_bwmon_opp_table: 3206 cpu_bwmon_opp_table: opp-table {
3207 compatible = 3207 compatible = "operating-points-v2";
3208 3208
3209 opp-0 { 3209 opp-0 {
3210 opp-p 3210 opp-peak-kBps = <9155000>;
3211 }; 3211 };
3212 3212
3213 opp-1 { 3213 opp-1 {
3214 opp-p 3214 opp-peak-kBps = <12298000>;
3215 }; 3215 };
3216 3216
3217 opp-2 { 3217 opp-2 {
3218 opp-p 3218 opp-peak-kBps = <14236000>;
3219 }; 3219 };
3220 3220
3221 opp-3 { 3221 opp-3 {
3222 opp-p 3222 opp-peak-kBps = <16265000>;
3223 }; 3223 };
3224 }; 3224 };
3225 3225
3226 }; 3226 };
3227 3227
3228 pmu@90b6400 { 3228 pmu@90b6400 {
3229 compatible = "qcom,sa 3229 compatible = "qcom,sa8775p-cpu-bwmon", "qcom,sdm845-bwmon";
3230 reg = <0x0 0x90b6400 3230 reg = <0x0 0x90b6400 0x0 0x600>;
3231 interrupts = <GIC_SPI 3231 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
3232 interconnects = <&gem 3232 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
3233 &gem 3233 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>;
3234 3234
3235 operating-points-v2 = 3235 operating-points-v2 = <&cpu_bwmon_opp_table>;
3236 }; 3236 };
3237 3237
3238 llcc: system-cache-controller 3238 llcc: system-cache-controller@9200000 {
3239 compatible = "qcom,sa 3239 compatible = "qcom,sa8775p-llcc";
3240 reg = <0x0 0x09200000 3240 reg = <0x0 0x09200000 0x0 0x80000>,
3241 <0x0 0x09300000 3241 <0x0 0x09300000 0x0 0x80000>,
3242 <0x0 0x09400000 3242 <0x0 0x09400000 0x0 0x80000>,
3243 <0x0 0x09500000 3243 <0x0 0x09500000 0x0 0x80000>,
3244 <0x0 0x09600000 3244 <0x0 0x09600000 0x0 0x80000>,
3245 <0x0 0x09700000 3245 <0x0 0x09700000 0x0 0x80000>,
3246 <0x0 0x09a00000 3246 <0x0 0x09a00000 0x0 0x80000>;
3247 reg-names = "llcc0_ba 3247 reg-names = "llcc0_base",
3248 "llcc1_ba 3248 "llcc1_base",
3249 "llcc2_ba 3249 "llcc2_base",
3250 "llcc3_ba 3250 "llcc3_base",
3251 "llcc4_ba 3251 "llcc4_base",
3252 "llcc5_ba 3252 "llcc5_base",
3253 "llcc_bro 3253 "llcc_broadcast_base";
3254 interrupts = <GIC_SPI 3254 interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
3255 }; 3255 };
3256 3256
3257 pdc: interrupt-controller@b22 3257 pdc: interrupt-controller@b220000 {
3258 compatible = "qcom,sa 3258 compatible = "qcom,sa8775p-pdc", "qcom,pdc";
3259 reg = <0x0 0x0b220000 3259 reg = <0x0 0x0b220000 0x0 0x30000>,
3260 <0x0 0x17c000f0 3260 <0x0 0x17c000f0 0x0 0x64>;
3261 qcom,pdc-ranges = <0 3261 qcom,pdc-ranges = <0 480 40>,
3262 <40 3262 <40 140 14>,
3263 <54 3263 <54 263 1>,
3264 <55 3264 <55 306 4>,
3265 <59 3265 <59 312 3>,
3266 <62 3266 <62 374 2>,
3267 <64 3267 <64 434 2>,
3268 <66 3268 <66 438 2>,
3269 <70 3269 <70 520 1>,
3270 <73 3270 <73 523 1>,
3271 <11 3271 <118 568 6>,
3272 <12 3272 <124 609 3>,
3273 <15 3273 <159 638 1>,
3274 <16 3274 <160 720 3>,
3275 <16 3275 <169 728 30>,
3276 <19 3276 <199 416 2>,
3277 <20 3277 <201 449 1>,
3278 <20 3278 <202 89 1>,
3279 <20 3279 <203 451 1>,
3280 <20 3280 <204 462 1>,
3281 <20 3281 <205 264 1>,
3282 <20 3282 <206 579 1>,
3283 <20 3283 <207 653 1>,
3284 <20 3284 <208 656 1>,
3285 <20 3285 <209 659 1>,
3286 <21 3286 <210 122 1>,
3287 <21 3287 <211 699 1>,
3288 <21 3288 <212 705 1>,
3289 <21 3289 <213 450 1>,
3290 <21 3290 <214 643 2>,
3291 <21 3291 <216 646 5>,
3292 <22 3292 <221 390 5>,
3293 <22 3293 <226 700 2>,
3294 <22 3294 <228 440 1>,
3295 <22 3295 <229 663 1>,
3296 <23 3296 <230 524 2>,
3297 <23 3297 <232 612 3>,
3298 <23 3298 <235 723 5>;
3299 #interrupt-cells = <2 3299 #interrupt-cells = <2>;
3300 interrupt-parent = <& 3300 interrupt-parent = <&intc>;
3301 interrupt-controller; 3301 interrupt-controller;
3302 }; 3302 };
3303 3303
3304 tsens2: thermal-sensor@c25100 3304 tsens2: thermal-sensor@c251000 {
3305 compatible = "qcom,sa 3305 compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2";
3306 reg = <0x0 0x0c251000 3306 reg = <0x0 0x0c251000 0x0 0x1ff>,
3307 <0x0 0x0c224000 3307 <0x0 0x0c224000 0x0 0x8>;
3308 interrupts = <GIC_SPI 3308 interrupts = <GIC_SPI 572 IRQ_TYPE_LEVEL_HIGH>,
3309 <GIC_SPI 3309 <GIC_SPI 609 IRQ_TYPE_LEVEL_HIGH>;
3310 #qcom,sensors = <13>; 3310 #qcom,sensors = <13>;
3311 interrupt-names = "up 3311 interrupt-names = "uplow", "critical";
3312 #thermal-sensor-cells 3312 #thermal-sensor-cells = <1>;
3313 }; 3313 };
3314 3314
3315 tsens3: thermal-sensor@c25200 3315 tsens3: thermal-sensor@c252000 {
3316 compatible = "qcom,sa 3316 compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2";
3317 reg = <0x0 0x0c252000 3317 reg = <0x0 0x0c252000 0x0 0x1ff>,
3318 <0x0 0x0c225000 3318 <0x0 0x0c225000 0x0 0x8>;
3319 interrupts = <GIC_SPI 3319 interrupts = <GIC_SPI 573 IRQ_TYPE_LEVEL_HIGH>,
3320 <GIC_SPI 3320 <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>;
3321 #qcom,sensors = <13>; 3321 #qcom,sensors = <13>;
3322 interrupt-names = "up 3322 interrupt-names = "uplow", "critical";
3323 #thermal-sensor-cells 3323 #thermal-sensor-cells = <1>;
3324 }; 3324 };
3325 3325
3326 tsens0: thermal-sensor@c26300 3326 tsens0: thermal-sensor@c263000 {
3327 compatible = "qcom,sa 3327 compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2";
3328 reg = <0x0 0x0c263000 3328 reg = <0x0 0x0c263000 0x0 0x1ff>,
3329 <0x0 0x0c222000 3329 <0x0 0x0c222000 0x0 0x8>;
3330 interrupts = <GIC_SPI 3330 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
3331 <GIC_SPI 3331 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
3332 #qcom,sensors = <12>; 3332 #qcom,sensors = <12>;
3333 interrupt-names = "up 3333 interrupt-names = "uplow", "critical";
3334 #thermal-sensor-cells 3334 #thermal-sensor-cells = <1>;
3335 }; 3335 };
3336 3336
3337 tsens1: thermal-sensor@c26500 3337 tsens1: thermal-sensor@c265000 {
3338 compatible = "qcom,sa 3338 compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2";
3339 reg = <0x0 0x0c265000 3339 reg = <0x0 0x0c265000 0x0 0x1ff>,
3340 <0x0 0x0c223000 3340 <0x0 0x0c223000 0x0 0x8>;
3341 interrupts = <GIC_SPI 3341 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
3342 <GIC_SPI 3342 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
3343 #qcom,sensors = <12>; 3343 #qcom,sensors = <12>;
3344 interrupt-names = "up 3344 interrupt-names = "uplow", "critical";
3345 #thermal-sensor-cells 3345 #thermal-sensor-cells = <1>;
3346 }; 3346 };
3347 3347
3348 aoss_qmp: power-management@c3 3348 aoss_qmp: power-management@c300000 {
3349 compatible = "qcom,sa 3349 compatible = "qcom,sa8775p-aoss-qmp", "qcom,aoss-qmp";
3350 reg = <0x0 0x0c300000 3350 reg = <0x0 0x0c300000 0x0 0x400>;
3351 interrupts-extended = 3351 interrupts-extended = <&ipcc IPCC_CLIENT_AOP
3352 3352 IPCC_MPROC_SIGNAL_GLINK_QMP
3353 3353 IRQ_TYPE_EDGE_RISING>;
3354 mboxes = <&ipcc IPCC_ 3354 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
3355 #clock-cells = <0>; 3355 #clock-cells = <0>;
3356 }; 3356 };
3357 3357
3358 sram@c3f0000 { 3358 sram@c3f0000 {
3359 compatible = "qcom,rp 3359 compatible = "qcom,rpmh-stats";
3360 reg = <0x0 0x0c3f0000 3360 reg = <0x0 0x0c3f0000 0x0 0x400>;
3361 }; 3361 };
3362 3362
3363 spmi_bus: spmi@c440000 { 3363 spmi_bus: spmi@c440000 {
3364 compatible = "qcom,sp 3364 compatible = "qcom,spmi-pmic-arb";
3365 reg = <0x0 0x0c440000 3365 reg = <0x0 0x0c440000 0x0 0x1100>,
3366 <0x0 0x0c600000 3366 <0x0 0x0c600000 0x0 0x2000000>,
3367 <0x0 0x0e600000 3367 <0x0 0x0e600000 0x0 0x100000>,
3368 <0x0 0x0e700000 3368 <0x0 0x0e700000 0x0 0xa0000>,
3369 <0x0 0x0c40a000 3369 <0x0 0x0c40a000 0x0 0x26000>;
3370 reg-names = "core", 3370 reg-names = "core",
3371 "chnls", 3371 "chnls",
3372 "obsrvr", 3372 "obsrvr",
3373 "intr", 3373 "intr",
3374 "cnfg"; 3374 "cnfg";
3375 qcom,channel = <0>; 3375 qcom,channel = <0>;
3376 qcom,ee = <0>; 3376 qcom,ee = <0>;
3377 interrupts-extended = 3377 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3378 interrupt-names = "pe 3378 interrupt-names = "periph_irq";
3379 interrupt-controller; 3379 interrupt-controller;
3380 #interrupt-cells = <4 3380 #interrupt-cells = <4>;
3381 #address-cells = <2>; 3381 #address-cells = <2>;
3382 #size-cells = <0>; 3382 #size-cells = <0>;
3383 }; 3383 };
3384 3384
3385 tlmm: pinctrl@f000000 { 3385 tlmm: pinctrl@f000000 {
3386 compatible = "qcom,sa 3386 compatible = "qcom,sa8775p-tlmm";
3387 reg = <0x0 0x0f000000 3387 reg = <0x0 0x0f000000 0x0 0x1000000>;
3388 interrupts = <GIC_SPI 3388 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
3389 gpio-controller; 3389 gpio-controller;
3390 #gpio-cells = <2>; 3390 #gpio-cells = <2>;
3391 interrupt-controller; 3391 interrupt-controller;
3392 #interrupt-cells = <2 3392 #interrupt-cells = <2>;
3393 gpio-ranges = <&tlmm 3393 gpio-ranges = <&tlmm 0 0 149>;
3394 wakeup-parent = <&pdc 3394 wakeup-parent = <&pdc>;
3395 }; 3395 };
3396 3396
3397 sram: sram@146d8000 { 3397 sram: sram@146d8000 {
3398 compatible = "qcom,sa 3398 compatible = "qcom,sa8775p-imem", "syscon", "simple-mfd";
3399 reg = <0x0 0x146d8000 3399 reg = <0x0 0x146d8000 0x0 0x1000>;
3400 ranges = <0x0 0x0 0x1 3400 ranges = <0x0 0x0 0x146d8000 0x1000>;
3401 3401
3402 #address-cells = <1>; 3402 #address-cells = <1>;
3403 #size-cells = <1>; 3403 #size-cells = <1>;
3404 3404
3405 pil-reloc@94c { 3405 pil-reloc@94c {
3406 compatible = 3406 compatible = "qcom,pil-reloc-info";
3407 reg = <0x94c 3407 reg = <0x94c 0xc8>;
3408 }; 3408 };
3409 }; 3409 };
3410 3410
3411 apps_smmu: iommu@15000000 { 3411 apps_smmu: iommu@15000000 {
3412 compatible = "qcom,sa 3412 compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500";
3413 reg = <0x0 0x15000000 3413 reg = <0x0 0x15000000 0x0 0x100000>;
3414 #iommu-cells = <2>; 3414 #iommu-cells = <2>;
3415 #global-interrupts = 3415 #global-interrupts = <2>;
3416 dma-coherent; 3416 dma-coherent;
3417 3417
3418 interrupts = <GIC_SPI 3418 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
3419 <GIC_SPI 3419 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
3420 <GIC_SPI 3420 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
3421 <GIC_SPI 3421 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
3422 <GIC_SPI 3422 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
3423 <GIC_SPI 3423 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
3424 <GIC_SPI 3424 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
3425 <GIC_SPI 3425 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
3426 <GIC_SPI 3426 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
3427 <GIC_SPI 3427 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
3428 <GIC_SPI 3428 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
3429 <GIC_SPI 3429 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
3430 <GIC_SPI 3430 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
3431 <GIC_SPI 3431 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
3432 <GIC_SPI 3432 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
3433 <GIC_SPI 3433 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
3434 <GIC_SPI 3434 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
3435 <GIC_SPI 3435 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
3436 <GIC_SPI 3436 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
3437 <GIC_SPI 3437 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
3438 <GIC_SPI 3438 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
3439 <GIC_SPI 3439 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
3440 <GIC_SPI 3440 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
3441 <GIC_SPI 3441 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
3442 <GIC_SPI 3442 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
3443 <GIC_SPI 3443 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
3444 <GIC_SPI 3444 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
3445 <GIC_SPI 3445 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
3446 <GIC_SPI 3446 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
3447 <GIC_SPI 3447 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
3448 <GIC_SPI 3448 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
3449 <GIC_SPI 3449 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
3450 <GIC_SPI 3450 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
3451 <GIC_SPI 3451 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
3452 <GIC_SPI 3452 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
3453 <GIC_SPI 3453 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
3454 <GIC_SPI 3454 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
3455 <GIC_SPI 3455 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
3456 <GIC_SPI 3456 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
3457 <GIC_SPI 3457 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
3458 <GIC_SPI 3458 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
3459 <GIC_SPI 3459 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
3460 <GIC_SPI 3460 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
3461 <GIC_SPI 3461 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
3462 <GIC_SPI 3462 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
3463 <GIC_SPI 3463 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
3464 <GIC_SPI 3464 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
3465 <GIC_SPI 3465 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
3466 <GIC_SPI 3466 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
3467 <GIC_SPI 3467 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
3468 <GIC_SPI 3468 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
3469 <GIC_SPI 3469 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
3470 <GIC_SPI 3470 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
3471 <GIC_SPI 3471 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
3472 <GIC_SPI 3472 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
3473 <GIC_SPI 3473 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
3474 <GIC_SPI 3474 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
3475 <GIC_SPI 3475 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
3476 <GIC_SPI 3476 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
3477 <GIC_SPI 3477 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
3478 <GIC_SPI 3478 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
3479 <GIC_SPI 3479 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
3480 <GIC_SPI 3480 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
3481 <GIC_SPI 3481 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
3482 <GIC_SPI 3482 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
3483 <GIC_SPI 3483 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
3484 <GIC_SPI 3484 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
3485 <GIC_SPI 3485 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
3486 <GIC_SPI 3486 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
3487 <GIC_SPI 3487 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
3488 <GIC_SPI 3488 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
3489 <GIC_SPI 3489 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
3490 <GIC_SPI 3490 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
3491 <GIC_SPI 3491 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
3492 <GIC_SPI 3492 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
3493 <GIC_SPI 3493 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
3494 <GIC_SPI 3494 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
3495 <GIC_SPI 3495 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
3496 <GIC_SPI 3496 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
3497 <GIC_SPI 3497 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
3498 <GIC_SPI 3498 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
3499 <GIC_SPI 3499 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>,
3500 <GIC_SPI 3500 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
3501 <GIC_SPI 3501 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
3502 <GIC_SPI 3502 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
3503 <GIC_SPI 3503 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
3504 <GIC_SPI 3504 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
3505 <GIC_SPI 3505 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
3506 <GIC_SPI 3506 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
3507 <GIC_SPI 3507 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
3508 <GIC_SPI 3508 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
3509 <GIC_SPI 3509 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
3510 <GIC_SPI 3510 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
3511 <GIC_SPI 3511 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
3512 <GIC_SPI 3512 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
3513 <GIC_SPI 3513 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
3514 <GIC_SPI 3514 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
3515 <GIC_SPI 3515 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
3516 <GIC_SPI 3516 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
3517 <GIC_SPI 3517 <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>,
3518 <GIC_SPI 3518 <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>,
3519 <GIC_SPI 3519 <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>,
3520 <GIC_SPI 3520 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
3521 <GIC_SPI 3521 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
3522 <GIC_SPI 3522 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
3523 <GIC_SPI 3523 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>,
3524 <GIC_SPI 3524 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>,
3525 <GIC_SPI 3525 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>,
3526 <GIC_SPI 3526 <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>,
3527 <GIC_SPI 3527 <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>,
3528 <GIC_SPI 3528 <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>,
3529 <GIC_SPI 3529 <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>,
3530 <GIC_SPI 3530 <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>,
3531 <GIC_SPI 3531 <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>,
3532 <GIC_SPI 3532 <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>,
3533 <GIC_SPI 3533 <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>,
3534 <GIC_SPI 3534 <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>,
3535 <GIC_SPI 3535 <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>,
3536 <GIC_SPI 3536 <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>,
3537 <GIC_SPI 3537 <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>,
3538 <GIC_SPI 3538 <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>,
3539 <GIC_SPI 3539 <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>,
3540 <GIC_SPI 3540 <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>,
3541 <GIC_SPI 3541 <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>,
3542 <GIC_SPI 3542 <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>,
3543 <GIC_SPI 3543 <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>,
3544 <GIC_SPI 3544 <GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>,
3545 <GIC_SPI 3545 <GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>,
3546 <GIC_SPI 3546 <GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>,
3547 <GIC_SPI 3547 <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>;
3548 }; 3548 };
3549 3549
3550 pcie_smmu: iommu@15200000 { 3550 pcie_smmu: iommu@15200000 {
3551 compatible = "qcom,sa 3551 compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500";
3552 reg = <0x0 0x15200000 3552 reg = <0x0 0x15200000 0x0 0x80000>;
3553 #iommu-cells = <2>; 3553 #iommu-cells = <2>;
3554 #global-interrupts = 3554 #global-interrupts = <2>;
3555 dma-coherent; 3555 dma-coherent;
3556 3556
3557 interrupts = <GIC_SPI 3557 interrupts = <GIC_SPI 920 IRQ_TYPE_LEVEL_HIGH>,
3558 <GIC_SPI 3558 <GIC_SPI 921 IRQ_TYPE_LEVEL_HIGH>,
3559 <GIC_SPI 3559 <GIC_SPI 925 IRQ_TYPE_LEVEL_HIGH>,
3560 <GIC_SPI 3560 <GIC_SPI 926 IRQ_TYPE_LEVEL_HIGH>,
3561 <GIC_SPI 3561 <GIC_SPI 927 IRQ_TYPE_LEVEL_HIGH>,
3562 <GIC_SPI 3562 <GIC_SPI 928 IRQ_TYPE_LEVEL_HIGH>,
3563 <GIC_SPI 3563 <GIC_SPI 950 IRQ_TYPE_LEVEL_HIGH>,
3564 <GIC_SPI 3564 <GIC_SPI 951 IRQ_TYPE_LEVEL_HIGH>,
3565 <GIC_SPI 3565 <GIC_SPI 952 IRQ_TYPE_LEVEL_HIGH>,
3566 <GIC_SPI 3566 <GIC_SPI 953 IRQ_TYPE_LEVEL_HIGH>,
3567 <GIC_SPI 3567 <GIC_SPI 954 IRQ_TYPE_LEVEL_HIGH>,
3568 <GIC_SPI 3568 <GIC_SPI 955 IRQ_TYPE_LEVEL_HIGH>,
3569 <GIC_SPI 3569 <GIC_SPI 956 IRQ_TYPE_LEVEL_HIGH>,
3570 <GIC_SPI 3570 <GIC_SPI 957 IRQ_TYPE_LEVEL_HIGH>,
3571 <GIC_SPI 3571 <GIC_SPI 958 IRQ_TYPE_LEVEL_HIGH>,
3572 <GIC_SPI 3572 <GIC_SPI 885 IRQ_TYPE_LEVEL_HIGH>,
3573 <GIC_SPI 3573 <GIC_SPI 886 IRQ_TYPE_LEVEL_HIGH>,
3574 <GIC_SPI 3574 <GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>,
3575 <GIC_SPI 3575 <GIC_SPI 888 IRQ_TYPE_LEVEL_HIGH>,
3576 <GIC_SPI 3576 <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>,
3577 <GIC_SPI 3577 <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>,
3578 <GIC_SPI 3578 <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>,
3579 <GIC_SPI 3579 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
3580 <GIC_SPI 3580 <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
3581 <GIC_SPI 3581 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
3582 <GIC_SPI 3582 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
3583 <GIC_SPI 3583 <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>,
3584 <GIC_SPI 3584 <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>,
3585 <GIC_SPI 3585 <GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>,
3586 <GIC_SPI 3586 <GIC_SPI 843 IRQ_TYPE_LEVEL_HIGH>,
3587 <GIC_SPI 3587 <GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>,
3588 <GIC_SPI 3588 <GIC_SPI 845 IRQ_TYPE_LEVEL_HIGH>,
3589 <GIC_SPI 3589 <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>,
3590 <GIC_SPI 3590 <GIC_SPI 847 IRQ_TYPE_LEVEL_HIGH>,
3591 <GIC_SPI 3591 <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>,
3592 <GIC_SPI 3592 <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>,
3593 <GIC_SPI 3593 <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>,
3594 <GIC_SPI 3594 <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>,
3595 <GIC_SPI 3595 <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>,
3596 <GIC_SPI 3596 <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>,
3597 <GIC_SPI 3597 <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>,
3598 <GIC_SPI 3598 <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>,
3599 <GIC_SPI 3599 <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>,
3600 <GIC_SPI 3600 <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>,
3601 <GIC_SPI 3601 <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>,
3602 <GIC_SPI 3602 <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>,
3603 <GIC_SPI 3603 <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>,
3604 <GIC_SPI 3604 <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>,
3605 <GIC_SPI 3605 <GIC_SPI 814 IRQ_TYPE_LEVEL_HIGH>,
3606 <GIC_SPI 3606 <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>,
3607 <GIC_SPI 3607 <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>,
3608 <GIC_SPI 3608 <GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>,
3609 <GIC_SPI 3609 <GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>,
3610 <GIC_SPI 3610 <GIC_SPI 854 IRQ_TYPE_LEVEL_HIGH>,
3611 <GIC_SPI 3611 <GIC_SPI 855 IRQ_TYPE_LEVEL_HIGH>,
3612 <GIC_SPI 3612 <GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>,
3613 <GIC_SPI 3613 <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>,
3614 <GIC_SPI 3614 <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>,
3615 <GIC_SPI 3615 <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>,
3616 <GIC_SPI 3616 <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>,
3617 <GIC_SPI 3617 <GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>,
3618 <GIC_SPI 3618 <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>,
3619 <GIC_SPI 3619 <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>,
3620 <GIC_SPI 3620 <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>,
3621 <GIC_SPI 3621 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
3622 <GIC_SPI 3622 <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>;
3623 }; 3623 };
3624 3624
3625 intc: interrupt-controller@17 3625 intc: interrupt-controller@17a00000 {
3626 compatible = "arm,gic 3626 compatible = "arm,gic-v3";
3627 reg = <0x0 0x17a00000 3627 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
3628 <0x0 0x17a60000 3628 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
3629 interrupt-controller; 3629 interrupt-controller;
3630 #interrupt-cells = <3 3630 #interrupt-cells = <3>;
3631 interrupts = <GIC_PPI 3631 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3632 #redistributor-region 3632 #redistributor-regions = <1>;
3633 redistributor-stride 3633 redistributor-stride = <0x0 0x20000>;
3634 }; 3634 };
3635 3635
3636 watchdog@17c10000 { 3636 watchdog@17c10000 {
3637 compatible = "qcom,ap 3637 compatible = "qcom,apss-wdt-sa8775p", "qcom,kpss-wdt";
3638 reg = <0x0 0x17c10000 3638 reg = <0x0 0x17c10000 0x0 0x1000>;
3639 clocks = <&sleep_clk> 3639 clocks = <&sleep_clk>;
3640 interrupts = <GIC_SPI 3640 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
3641 }; 3641 };
3642 3642
3643 memtimer: timer@17c20000 { 3643 memtimer: timer@17c20000 {
3644 compatible = "arm,arm 3644 compatible = "arm,armv7-timer-mem";
3645 reg = <0x0 0x17c20000 3645 reg = <0x0 0x17c20000 0x0 0x1000>;
3646 ranges = <0x0 0x0 0x0 3646 ranges = <0x0 0x0 0x0 0x20000000>;
3647 #address-cells = <1>; 3647 #address-cells = <1>;
3648 #size-cells = <1>; 3648 #size-cells = <1>;
3649 3649
3650 frame@17c21000 { 3650 frame@17c21000 {
3651 reg = <0x17c2 3651 reg = <0x17c21000 0x1000>,
3652 <0x17c2 3652 <0x17c22000 0x1000>;
3653 interrupts = 3653 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
3654 3654 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
3655 frame-number 3655 frame-number = <0>;
3656 }; 3656 };
3657 3657
3658 frame@17c23000 { 3658 frame@17c23000 {
3659 reg = <0x17c2 3659 reg = <0x17c23000 0x1000>;
3660 interrupts = 3660 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
3661 frame-number 3661 frame-number = <1>;
3662 status = "dis 3662 status = "disabled";
3663 }; 3663 };
3664 3664
3665 frame@17c25000 { 3665 frame@17c25000 {
3666 reg = <0x17c2 3666 reg = <0x17c25000 0x1000>;
3667 interrupts = 3667 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
3668 frame-number 3668 frame-number = <2>;
3669 status = "dis 3669 status = "disabled";
3670 }; 3670 };
3671 3671
3672 frame@17c27000 { 3672 frame@17c27000 {
3673 reg = <0x17c2 3673 reg = <0x17c27000 0x1000>;
3674 interrupts = 3674 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3675 frame-number 3675 frame-number = <3>;
3676 status = "dis 3676 status = "disabled";
3677 }; 3677 };
3678 3678
3679 frame@17c29000 { 3679 frame@17c29000 {
3680 reg = <0x17c2 3680 reg = <0x17c29000 0x1000>;
3681 interrupts = 3681 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3682 frame-number 3682 frame-number = <4>;
3683 status = "dis 3683 status = "disabled";
3684 }; 3684 };
3685 3685
3686 frame@17c2b000 { 3686 frame@17c2b000 {
3687 reg = <0x17c2 3687 reg = <0x17c2b000 0x1000>;
3688 interrupts = 3688 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3689 frame-number 3689 frame-number = <5>;
3690 status = "dis 3690 status = "disabled";
3691 }; 3691 };
3692 3692
3693 frame@17c2d000 { 3693 frame@17c2d000 {
3694 reg = <0x17c2 3694 reg = <0x17c2d000 0x1000>;
3695 interrupts = 3695 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
3696 frame-number 3696 frame-number = <6>;
3697 status = "dis 3697 status = "disabled";
3698 }; 3698 };
3699 }; 3699 };
3700 3700
3701 apps_rsc: rsc@18200000 { 3701 apps_rsc: rsc@18200000 {
3702 compatible = "qcom,rp 3702 compatible = "qcom,rpmh-rsc";
3703 reg = <0x0 0x18200000 3703 reg = <0x0 0x18200000 0x0 0x10000>,
3704 <0x0 0x18210000 3704 <0x0 0x18210000 0x0 0x10000>,
3705 <0x0 0x18220000 3705 <0x0 0x18220000 0x0 0x10000>;
3706 reg-names = "drv-0", 3706 reg-names = "drv-0", "drv-1", "drv-2";
3707 interrupts = <GIC_SPI 3707 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
3708 <GIC_SPI 4 IRQ_ 3708 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
3709 <GIC_SPI 5 IRQ_ 3709 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
3710 qcom,tcs-offset = <0x 3710 qcom,tcs-offset = <0xd00>;
3711 qcom,drv-id = <2>; 3711 qcom,drv-id = <2>;
3712 qcom,tcs-config = <AC 3712 qcom,tcs-config = <ACTIVE_TCS 2>,
3713 <SL 3713 <SLEEP_TCS 3>,
3714 <WA 3714 <WAKE_TCS 3>,
3715 <CO 3715 <CONTROL_TCS 0>;
3716 label = "apps_rsc"; 3716 label = "apps_rsc";
3717 3717
3718 apps_bcm_voter: bcm-v 3718 apps_bcm_voter: bcm-voter {
3719 compatible = 3719 compatible = "qcom,bcm-voter";
3720 }; 3720 };
3721 3721
3722 rpmhcc: clock-control 3722 rpmhcc: clock-controller {
3723 compatible = 3723 compatible = "qcom,sa8775p-rpmh-clk";
3724 #clock-cells 3724 #clock-cells = <1>;
3725 clock-names = 3725 clock-names = "xo";
3726 clocks = <&xo 3726 clocks = <&xo_board_clk>;
3727 }; 3727 };
3728 3728
3729 rpmhpd: power-control 3729 rpmhpd: power-controller {
3730 compatible = 3730 compatible = "qcom,sa8775p-rpmhpd";
3731 #power-domain 3731 #power-domain-cells = <1>;
3732 operating-poi 3732 operating-points-v2 = <&rpmhpd_opp_table>;
3733 3733
3734 rpmhpd_opp_ta 3734 rpmhpd_opp_table: opp-table {
3735 compa 3735 compatible = "operating-points-v2";
3736 3736
3737 rpmhp 3737 rpmhpd_opp_ret: opp-0 {
3738 3738 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3739 }; 3739 };
3740 3740
3741 rpmhp 3741 rpmhpd_opp_min_svs: opp-1 {
3742 3742 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3743 }; 3743 };
3744 3744
3745 rpmhp 3745 rpmhpd_opp_low_svs: opp2 {
3746 3746 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3747 }; 3747 };
3748 3748
3749 rpmhp 3749 rpmhpd_opp_svs: opp3 {
3750 3750 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3751 }; 3751 };
3752 3752
3753 rpmhp 3753 rpmhpd_opp_svs_l1: opp-4 {
3754 3754 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3755 }; 3755 };
3756 3756
3757 rpmhp 3757 rpmhpd_opp_nom: opp-5 {
3758 3758 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3759 }; 3759 };
3760 3760
3761 rpmhp 3761 rpmhpd_opp_nom_l1: opp-6 {
3762 3762 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3763 }; 3763 };
3764 3764
3765 rpmhp 3765 rpmhpd_opp_nom_l2: opp-7 {
3766 3766 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3767 }; 3767 };
3768 3768
3769 rpmhp 3769 rpmhpd_opp_turbo: opp-8 {
3770 3770 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3771 }; 3771 };
3772 3772
3773 rpmhp 3773 rpmhpd_opp_turbo_l1: opp-9 {
3774 3774 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3775 }; 3775 };
3776 }; 3776 };
3777 }; 3777 };
3778 }; 3778 };
3779 3779
3780 cpufreq_hw: cpufreq@18591000 3780 cpufreq_hw: cpufreq@18591000 {
3781 compatible = "qcom,sa 3781 compatible = "qcom,sa8775p-cpufreq-epss",
3782 "qcom,cp 3782 "qcom,cpufreq-epss";
3783 reg = <0x0 0x18591000 3783 reg = <0x0 0x18591000 0x0 0x1000>,
3784 <0x0 0x18593000 3784 <0x0 0x18593000 0x0 0x1000>;
3785 reg-names = "freq-dom 3785 reg-names = "freq-domain0", "freq-domain1";
3786 3786
3787 clocks = <&rpmhcc RPM 3787 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
3788 clock-names = "xo", " 3788 clock-names = "xo", "alternate";
3789 3789
3790 #freq-domain-cells = 3790 #freq-domain-cells = <1>;
3791 }; 3791 };
3792 3792
3793 remoteproc_gpdsp0: remoteproc 3793 remoteproc_gpdsp0: remoteproc@20c00000 {
3794 compatible = "qcom,sa 3794 compatible = "qcom,sa8775p-gpdsp0-pas";
3795 reg = <0x0 0x20c00000 3795 reg = <0x0 0x20c00000 0x0 0x10000>;
3796 3796
3797 interrupts-extended = 3797 interrupts-extended = <&intc GIC_SPI 768 IRQ_TYPE_EDGE_RISING>,
3798 3798 <&smp2p_gpdsp0_in 0 0>,
3799 3799 <&smp2p_gpdsp0_in 2 0>,
3800 3800 <&smp2p_gpdsp0_in 1 0>,
3801 3801 <&smp2p_gpdsp0_in 3 0>;
3802 interrupt-names = "wd 3802 interrupt-names = "wdog", "fatal", "ready",
3803 "ha 3803 "handover", "stop-ack";
3804 3804
3805 clocks = <&rpmhcc RPM 3805 clocks = <&rpmhcc RPMH_CXO_CLK>;
3806 clock-names = "xo"; 3806 clock-names = "xo";
3807 3807
3808 power-domains = <&rpm 3808 power-domains = <&rpmhpd RPMHPD_CX>,
3809 <&rpm 3809 <&rpmhpd RPMHPD_MXC>;
3810 power-domain-names = 3810 power-domain-names = "cx", "mxc";
3811 3811
3812 interconnects = <&gpd 3812 interconnects = <&gpdsp_anoc MASTER_DSP0 0
3813 &con 3813 &config_noc SLAVE_CLK_CTL 0>;
3814 3814
3815 memory-region = <&pil 3815 memory-region = <&pil_gdsp0_mem>;
3816 3816
3817 qcom,qmp = <&aoss_qmp 3817 qcom,qmp = <&aoss_qmp>;
3818 3818
3819 qcom,smem-states = <& 3819 qcom,smem-states = <&smp2p_gpdsp0_out 0>;
3820 qcom,smem-state-names 3820 qcom,smem-state-names = "stop";
3821 3821
3822 status = "disabled"; 3822 status = "disabled";
3823 3823
3824 glink-edge { 3824 glink-edge {
3825 interrupts-ex 3825 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP0
3826 3826 IPCC_MPROC_SIGNAL_GLINK_QMP
3827 3827 IRQ_TYPE_EDGE_RISING>;
3828 mboxes = <&ip 3828 mboxes = <&ipcc IPCC_CLIENT_GPDSP0
3829 3829 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3830 3830
3831 label = "gpds 3831 label = "gpdsp0";
3832 qcom,remote-p 3832 qcom,remote-pid = <17>;
3833 }; 3833 };
3834 }; 3834 };
3835 3835
3836 remoteproc_gpdsp1: remoteproc 3836 remoteproc_gpdsp1: remoteproc@21c00000 {
3837 compatible = "qcom,sa 3837 compatible = "qcom,sa8775p-gpdsp1-pas";
3838 reg = <0x0 0x21c00000 3838 reg = <0x0 0x21c00000 0x0 0x10000>;
3839 3839
3840 interrupts-extended = 3840 interrupts-extended = <&intc GIC_SPI 624 IRQ_TYPE_EDGE_RISING>,
3841 3841 <&smp2p_gpdsp1_in 0 0>,
3842 3842 <&smp2p_gpdsp1_in 2 0>,
3843 3843 <&smp2p_gpdsp1_in 1 0>,
3844 3844 <&smp2p_gpdsp1_in 3 0>;
3845 interrupt-names = "wd 3845 interrupt-names = "wdog", "fatal", "ready",
3846 "ha 3846 "handover", "stop-ack";
3847 3847
3848 clocks = <&rpmhcc RPM 3848 clocks = <&rpmhcc RPMH_CXO_CLK>;
3849 clock-names = "xo"; 3849 clock-names = "xo";
3850 3850
3851 power-domains = <&rpm 3851 power-domains = <&rpmhpd RPMHPD_CX>,
3852 <&rpm 3852 <&rpmhpd RPMHPD_MXC>;
3853 power-domain-names = 3853 power-domain-names = "cx", "mxc";
3854 3854
3855 interconnects = <&gpd 3855 interconnects = <&gpdsp_anoc MASTER_DSP1 0
3856 &con 3856 &config_noc SLAVE_CLK_CTL 0>;
3857 3857
3858 memory-region = <&pil 3858 memory-region = <&pil_gdsp1_mem>;
3859 3859
3860 qcom,qmp = <&aoss_qmp 3860 qcom,qmp = <&aoss_qmp>;
3861 3861
3862 qcom,smem-states = <& 3862 qcom,smem-states = <&smp2p_gpdsp1_out 0>;
3863 qcom,smem-state-names 3863 qcom,smem-state-names = "stop";
3864 3864
3865 status = "disabled"; 3865 status = "disabled";
3866 3866
3867 glink-edge { 3867 glink-edge {
3868 interrupts-ex 3868 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP1
3869 3869 IPCC_MPROC_SIGNAL_GLINK_QMP
3870 3870 IRQ_TYPE_EDGE_RISING>;
3871 mboxes = <&ip 3871 mboxes = <&ipcc IPCC_CLIENT_GPDSP1
3872 3872 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3873 3873
3874 label = "gpds 3874 label = "gpdsp1";
3875 qcom,remote-p 3875 qcom,remote-pid = <18>;
3876 }; 3876 };
3877 }; 3877 };
3878 3878
3879 ethernet1: ethernet@23000000 3879 ethernet1: ethernet@23000000 {
3880 compatible = "qcom,sa 3880 compatible = "qcom,sa8775p-ethqos";
3881 reg = <0x0 0x23000000 3881 reg = <0x0 0x23000000 0x0 0x10000>,
3882 <0x0 0x23016000 3882 <0x0 0x23016000 0x0 0x100>;
3883 reg-names = "stmmacet 3883 reg-names = "stmmaceth", "rgmii";
3884 3884
3885 interrupts = <GIC_SPI 3885 interrupts = <GIC_SPI 929 IRQ_TYPE_LEVEL_HIGH>,
3886 <GIC_SPI 3886 <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>;
3887 interrupt-names = "ma 3887 interrupt-names = "macirq", "sfty";
3888 3888
3889 clocks = <&gcc GCC_EM 3889 clocks = <&gcc GCC_EMAC1_AXI_CLK>,
3890 <&gcc GCC_EM 3890 <&gcc GCC_EMAC1_SLV_AHB_CLK>,
3891 <&gcc GCC_EM 3891 <&gcc GCC_EMAC1_PTP_CLK>,
3892 <&gcc GCC_EM 3892 <&gcc GCC_EMAC1_PHY_AUX_CLK>;
3893 clock-names = "stmmac 3893 clock-names = "stmmaceth",
3894 "pclk", 3894 "pclk",
3895 "ptp_re 3895 "ptp_ref",
3896 "phyaux 3896 "phyaux";
3897 3897
3898 interconnects = <&agg 3898 interconnects = <&aggre1_noc MASTER_EMAC_1 QCOM_ICC_TAG_ALWAYS
3899 &mc_ 3899 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
3900 <&gem 3900 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
3901 &con 3901 &config_noc SLAVE_EMAC1_CFG QCOM_ICC_TAG_ALWAYS>;
3902 interconnect-names = 3902 interconnect-names = "mac-mem", "cpu-mac";
3903 3903
3904 power-domains = <&gcc 3904 power-domains = <&gcc EMAC1_GDSC>;
3905 3905
3906 phys = <&serdes1>; 3906 phys = <&serdes1>;
3907 phy-names = "serdes"; 3907 phy-names = "serdes";
3908 3908
3909 iommus = <&apps_smmu 3909 iommus = <&apps_smmu 0x140 0xf>;
3910 dma-coherent; 3910 dma-coherent;
3911 3911
3912 snps,tso; 3912 snps,tso;
3913 snps,pbl = <32>; 3913 snps,pbl = <32>;
3914 rx-fifo-depth = <1638 3914 rx-fifo-depth = <16384>;
3915 tx-fifo-depth = <1638 3915 tx-fifo-depth = <16384>;
3916 3916
3917 status = "disabled"; 3917 status = "disabled";
3918 }; 3918 };
3919 3919
3920 ethernet0: ethernet@23040000 3920 ethernet0: ethernet@23040000 {
3921 compatible = "qcom,sa 3921 compatible = "qcom,sa8775p-ethqos";
3922 reg = <0x0 0x23040000 3922 reg = <0x0 0x23040000 0x0 0x10000>,
3923 <0x0 0x23056000 3923 <0x0 0x23056000 0x0 0x100>;
3924 reg-names = "stmmacet 3924 reg-names = "stmmaceth", "rgmii";
3925 3925
3926 interrupts = <GIC_SPI 3926 interrupts = <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>,
3927 <GIC_SPI 3927 <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>;
3928 interrupt-names = "ma 3928 interrupt-names = "macirq", "sfty";
3929 3929
3930 clocks = <&gcc GCC_EM 3930 clocks = <&gcc GCC_EMAC0_AXI_CLK>,
3931 <&gcc GCC_EM 3931 <&gcc GCC_EMAC0_SLV_AHB_CLK>,
3932 <&gcc GCC_EM 3932 <&gcc GCC_EMAC0_PTP_CLK>,
3933 <&gcc GCC_EM 3933 <&gcc GCC_EMAC0_PHY_AUX_CLK>;
3934 clock-names = "stmmac 3934 clock-names = "stmmaceth",
3935 "pclk", 3935 "pclk",
3936 "ptp_re 3936 "ptp_ref",
3937 "phyaux 3937 "phyaux";
3938 3938
3939 interconnects = <&agg 3939 interconnects = <&aggre1_noc MASTER_EMAC QCOM_ICC_TAG_ALWAYS
3940 &mc_ 3940 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
3941 <&gem 3941 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
3942 &con 3942 &config_noc SLAVE_EMAC_CFG QCOM_ICC_TAG_ALWAYS>;
3943 interconnect-names = 3943 interconnect-names = "mac-mem", "cpu-mac";
3944 3944
3945 power-domains = <&gcc 3945 power-domains = <&gcc EMAC0_GDSC>;
3946 3946
3947 phys = <&serdes0>; 3947 phys = <&serdes0>;
3948 phy-names = "serdes"; 3948 phy-names = "serdes";
3949 3949
3950 iommus = <&apps_smmu 3950 iommus = <&apps_smmu 0x120 0xf>;
3951 dma-coherent; 3951 dma-coherent;
3952 3952
3953 snps,tso; 3953 snps,tso;
3954 snps,pbl = <32>; 3954 snps,pbl = <32>;
3955 rx-fifo-depth = <1638 3955 rx-fifo-depth = <16384>;
3956 tx-fifo-depth = <1638 3956 tx-fifo-depth = <16384>;
3957 3957
3958 status = "disabled"; 3958 status = "disabled";
3959 }; 3959 };
3960 3960
3961 remoteproc_cdsp0: remoteproc@ 3961 remoteproc_cdsp0: remoteproc@26300000 {
3962 compatible = "qcom,sa 3962 compatible = "qcom,sa8775p-cdsp0-pas";
3963 reg = <0x0 0x26300000 3963 reg = <0x0 0x26300000 0x0 0x10000>;
3964 3964
3965 interrupts-extended = 3965 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
3966 3966 <&smp2p_cdsp0_in 0 IRQ_TYPE_EDGE_RISING>,
3967 3967 <&smp2p_cdsp0_in 2 IRQ_TYPE_EDGE_RISING>,
3968 3968 <&smp2p_cdsp0_in 1 IRQ_TYPE_EDGE_RISING>,
3969 3969 <&smp2p_cdsp0_in 3 IRQ_TYPE_EDGE_RISING>;
3970 interrupt-names = "wd 3970 interrupt-names = "wdog", "fatal", "ready",
3971 "ha 3971 "handover", "stop-ack";
3972 3972
3973 clocks = <&rpmhcc RPM 3973 clocks = <&rpmhcc RPMH_CXO_CLK>;
3974 clock-names = "xo"; 3974 clock-names = "xo";
3975 3975
3976 power-domains = <&rpm 3976 power-domains = <&rpmhpd RPMHPD_CX>,
3977 <&rpm 3977 <&rpmhpd RPMHPD_MXC>,
3978 <&rpm 3978 <&rpmhpd RPMHPD_NSP0>;
3979 power-domain-names = 3979 power-domain-names = "cx", "mxc", "nsp";
3980 3980
3981 interconnects = <&nsp 3981 interconnects = <&nspa_noc MASTER_CDSP_PROC 0
3982 &mc_ 3982 &mc_virt SLAVE_EBI1 0>;
3983 3983
3984 memory-region = <&pil 3984 memory-region = <&pil_cdsp0_mem>;
3985 3985
3986 qcom,qmp = <&aoss_qmp 3986 qcom,qmp = <&aoss_qmp>;
3987 3987
3988 qcom,smem-states = <& 3988 qcom,smem-states = <&smp2p_cdsp0_out 0>;
3989 qcom,smem-state-names 3989 qcom,smem-state-names = "stop";
3990 3990
3991 status = "disabled"; 3991 status = "disabled";
3992 3992
3993 glink-edge { 3993 glink-edge {
3994 interrupts-ex 3994 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
3995 3995 IPCC_MPROC_SIGNAL_GLINK_QMP
3996 3996 IRQ_TYPE_EDGE_RISING>;
3997 mboxes = <&ip 3997 mboxes = <&ipcc IPCC_CLIENT_CDSP
3998 3998 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3999 3999
4000 label = "cdsp 4000 label = "cdsp";
4001 qcom,remote-p 4001 qcom,remote-pid = <5>;
4002 4002
4003 fastrpc { 4003 fastrpc {
4004 compa 4004 compatible = "qcom,fastrpc";
4005 qcom, 4005 qcom,glink-channels = "fastrpcglink-apps-dsp";
4006 label 4006 label = "cdsp";
4007 #addr 4007 #address-cells = <1>;
4008 #size 4008 #size-cells = <0>;
4009 4009
4010 compu 4010 compute-cb@1 {
4011 4011 compatible = "qcom,fastrpc-compute-cb";
4012 4012 reg = <1>;
4013 4013 iommus = <&apps_smmu 0x2141 0x04a0>,
4014 4014 <&apps_smmu 0x2161 0x04a0>,
4015 4015 <&apps_smmu 0x2181 0x0400>,
4016 4016 <&apps_smmu 0x21c1 0x04a0>,
4017 4017 <&apps_smmu 0x21e1 0x04a0>,
4018 4018 <&apps_smmu 0x2541 0x04a0>,
4019 4019 <&apps_smmu 0x2561 0x04a0>,
4020 4020 <&apps_smmu 0x2581 0x0400>,
4021 4021 <&apps_smmu 0x25c1 0x04a0>,
4022 4022 <&apps_smmu 0x25e1 0x04a0>;
4023 4023 dma-coherent;
4024 }; 4024 };
4025 4025
4026 compu 4026 compute-cb@2 {
4027 4027 compatible = "qcom,fastrpc-compute-cb";
4028 4028 reg = <2>;
4029 4029 iommus = <&apps_smmu 0x2142 0x04a0>,
4030 4030 <&apps_smmu 0x2162 0x04a0>,
4031 4031 <&apps_smmu 0x2182 0x0400>,
4032 4032 <&apps_smmu 0x21c2 0x04a0>,
4033 4033 <&apps_smmu 0x21e2 0x04a0>,
4034 4034 <&apps_smmu 0x2542 0x04a0>,
4035 4035 <&apps_smmu 0x2562 0x04a0>,
4036 4036 <&apps_smmu 0x2582 0x0400>,
4037 4037 <&apps_smmu 0x25c2 0x04a0>,
4038 4038 <&apps_smmu 0x25e2 0x04a0>;
4039 4039 dma-coherent;
4040 }; 4040 };
4041 4041
4042 compu 4042 compute-cb@3 {
4043 4043 compatible = "qcom,fastrpc-compute-cb";
4044 4044 reg = <3>;
4045 4045 iommus = <&apps_smmu 0x2143 0x04a0>,
4046 4046 <&apps_smmu 0x2163 0x04a0>,
4047 4047 <&apps_smmu 0x2183 0x0400>,
4048 4048 <&apps_smmu 0x21c3 0x04a0>,
4049 4049 <&apps_smmu 0x21e3 0x04a0>,
4050 4050 <&apps_smmu 0x2543 0x04a0>,
4051 4051 <&apps_smmu 0x2563 0x04a0>,
4052 4052 <&apps_smmu 0x2583 0x0400>,
4053 4053 <&apps_smmu 0x25c3 0x04a0>,
4054 4054 <&apps_smmu 0x25e3 0x04a0>;
4055 4055 dma-coherent;
4056 }; 4056 };
4057 4057
4058 compu 4058 compute-cb@4 {
4059 4059 compatible = "qcom,fastrpc-compute-cb";
4060 4060 reg = <4>;
4061 4061 iommus = <&apps_smmu 0x2144 0x04a0>,
4062 4062 <&apps_smmu 0x2164 0x04a0>,
4063 4063 <&apps_smmu 0x2184 0x0400>,
4064 4064 <&apps_smmu 0x21c4 0x04a0>,
4065 4065 <&apps_smmu 0x21e4 0x04a0>,
4066 4066 <&apps_smmu 0x2544 0x04a0>,
4067 4067 <&apps_smmu 0x2564 0x04a0>,
4068 4068 <&apps_smmu 0x2584 0x0400>,
4069 4069 <&apps_smmu 0x25c4 0x04a0>,
4070 4070 <&apps_smmu 0x25e4 0x04a0>;
4071 4071 dma-coherent;
4072 }; 4072 };
4073 4073
4074 compu 4074 compute-cb@5 {
4075 4075 compatible = "qcom,fastrpc-compute-cb";
4076 4076 reg = <5>;
4077 4077 iommus = <&apps_smmu 0x2145 0x04a0>,
4078 4078 <&apps_smmu 0x2165 0x04a0>,
4079 4079 <&apps_smmu 0x2185 0x0400>,
4080 4080 <&apps_smmu 0x21c5 0x04a0>,
4081 4081 <&apps_smmu 0x21e5 0x04a0>,
4082 4082 <&apps_smmu 0x2545 0x04a0>,
4083 4083 <&apps_smmu 0x2565 0x04a0>,
4084 4084 <&apps_smmu 0x2585 0x0400>,
4085 4085 <&apps_smmu 0x25c5 0x04a0>,
4086 4086 <&apps_smmu 0x25e5 0x04a0>;
4087 4087 dma-coherent;
4088 }; 4088 };
4089 4089
4090 compu 4090 compute-cb@6 {
4091 4091 compatible = "qcom,fastrpc-compute-cb";
4092 4092 reg = <6>;
4093 4093 iommus = <&apps_smmu 0x2146 0x04a0>,
4094 4094 <&apps_smmu 0x2166 0x04a0>,
4095 4095 <&apps_smmu 0x2186 0x0400>,
4096 4096 <&apps_smmu 0x21c6 0x04a0>,
4097 4097 <&apps_smmu 0x21e6 0x04a0>,
4098 4098 <&apps_smmu 0x2546 0x04a0>,
4099 4099 <&apps_smmu 0x2566 0x04a0>,
4100 4100 <&apps_smmu 0x2586 0x0400>,
4101 4101 <&apps_smmu 0x25c6 0x04a0>,
4102 4102 <&apps_smmu 0x25e6 0x04a0>;
4103 4103 dma-coherent;
4104 }; 4104 };
4105 4105
4106 compu 4106 compute-cb@7 {
4107 4107 compatible = "qcom,fastrpc-compute-cb";
4108 4108 reg = <7>;
4109 4109 iommus = <&apps_smmu 0x2147 0x04a0>,
4110 4110 <&apps_smmu 0x2167 0x04a0>,
4111 4111 <&apps_smmu 0x2187 0x0400>,
4112 4112 <&apps_smmu 0x21c7 0x04a0>,
4113 4113 <&apps_smmu 0x21e7 0x04a0>,
4114 4114 <&apps_smmu 0x2547 0x04a0>,
4115 4115 <&apps_smmu 0x2567 0x04a0>,
4116 4116 <&apps_smmu 0x2587 0x0400>,
4117 4117 <&apps_smmu 0x25c7 0x04a0>,
4118 4118 <&apps_smmu 0x25e7 0x04a0>;
4119 4119 dma-coherent;
4120 }; 4120 };
4121 4121
4122 compu 4122 compute-cb@8 {
4123 4123 compatible = "qcom,fastrpc-compute-cb";
4124 4124 reg = <8>;
4125 4125 iommus = <&apps_smmu 0x2148 0x04a0>,
4126 4126 <&apps_smmu 0x2168 0x04a0>,
4127 4127 <&apps_smmu 0x2188 0x0400>,
4128 4128 <&apps_smmu 0x21c8 0x04a0>,
4129 4129 <&apps_smmu 0x21e8 0x04a0>,
4130 4130 <&apps_smmu 0x2548 0x04a0>,
4131 4131 <&apps_smmu 0x2568 0x04a0>,
4132 4132 <&apps_smmu 0x2588 0x0400>,
4133 4133 <&apps_smmu 0x25c8 0x04a0>,
4134 4134 <&apps_smmu 0x25e8 0x04a0>;
4135 4135 dma-coherent;
4136 }; 4136 };
4137 4137
4138 compu 4138 compute-cb@9 {
4139 4139 compatible = "qcom,fastrpc-compute-cb";
4140 4140 reg = <9>;
4141 4141 iommus = <&apps_smmu 0x2149 0x04a0>,
4142 4142 <&apps_smmu 0x2169 0x04a0>,
4143 4143 <&apps_smmu 0x2189 0x0400>,
4144 4144 <&apps_smmu 0x21c9 0x04a0>,
4145 4145 <&apps_smmu 0x21e9 0x04a0>,
4146 4146 <&apps_smmu 0x2549 0x04a0>,
4147 4147 <&apps_smmu 0x2569 0x04a0>,
4148 4148 <&apps_smmu 0x2589 0x0400>,
4149 4149 <&apps_smmu 0x25c9 0x04a0>,
4150 4150 <&apps_smmu 0x25e9 0x04a0>;
4151 4151 dma-coherent;
4152 }; 4152 };
4153 4153
4154 compu 4154 compute-cb@10 {
4155 4155 compatible = "qcom,fastrpc-compute-cb";
4156 4156 reg = <10>;
4157 4157 iommus = <&apps_smmu 0x214a 0x04a0>,
4158 4158 <&apps_smmu 0x216a 0x04a0>,
4159 4159 <&apps_smmu 0x218a 0x0400>,
4160 4160 <&apps_smmu 0x21ca 0x04a0>,
4161 4161 <&apps_smmu 0x21ea 0x04a0>,
4162 4162 <&apps_smmu 0x254a 0x04a0>,
4163 4163 <&apps_smmu 0x256a 0x04a0>,
4164 4164 <&apps_smmu 0x258a 0x0400>,
4165 4165 <&apps_smmu 0x25ca 0x04a0>,
4166 4166 <&apps_smmu 0x25ea 0x04a0>;
4167 4167 dma-coherent;
4168 }; 4168 };
4169 4169
4170 compu 4170 compute-cb@11 {
4171 4171 compatible = "qcom,fastrpc-compute-cb";
4172 4172 reg = <11>;
4173 4173 iommus = <&apps_smmu 0x214b 0x04a0>,
4174 4174 <&apps_smmu 0x216b 0x04a0>,
4175 4175 <&apps_smmu 0x218b 0x0400>,
4176 4176 <&apps_smmu 0x21cb 0x04a0>,
4177 4177 <&apps_smmu 0x21eb 0x04a0>,
4178 4178 <&apps_smmu 0x254b 0x04a0>,
4179 4179 <&apps_smmu 0x256b 0x04a0>,
4180 4180 <&apps_smmu 0x258b 0x0400>,
4181 4181 <&apps_smmu 0x25cb 0x04a0>,
4182 4182 <&apps_smmu 0x25eb 0x04a0>;
4183 4183 dma-coherent;
4184 }; 4184 };
4185 }; 4185 };
4186 }; 4186 };
4187 }; 4187 };
4188 4188
4189 remoteproc_cdsp1: remoteproc@ 4189 remoteproc_cdsp1: remoteproc@2a300000 {
4190 compatible = "qcom,sa 4190 compatible = "qcom,sa8775p-cdsp1-pas";
4191 reg = <0x0 0x2A300000 4191 reg = <0x0 0x2A300000 0x0 0x10000>;
4192 4192
4193 interrupts-extended = 4193 interrupts-extended = <&intc GIC_SPI 798 IRQ_TYPE_EDGE_RISING>,
4194 4194 <&smp2p_cdsp1_in 0 IRQ_TYPE_EDGE_RISING>,
4195 4195 <&smp2p_cdsp1_in 2 IRQ_TYPE_EDGE_RISING>,
4196 4196 <&smp2p_cdsp1_in 1 IRQ_TYPE_EDGE_RISING>,
4197 4197 <&smp2p_cdsp1_in 3 IRQ_TYPE_EDGE_RISING>;
4198 interrupt-names = "wd 4198 interrupt-names = "wdog", "fatal", "ready",
4199 "ha 4199 "handover", "stop-ack";
4200 4200
4201 clocks = <&rpmhcc RPM 4201 clocks = <&rpmhcc RPMH_CXO_CLK>;
4202 clock-names = "xo"; 4202 clock-names = "xo";
4203 4203
4204 power-domains = <&rpm 4204 power-domains = <&rpmhpd RPMHPD_CX>,
4205 <&rpm 4205 <&rpmhpd RPMHPD_MXC>,
4206 <&rpm 4206 <&rpmhpd RPMHPD_NSP1>;
4207 power-domain-names = 4207 power-domain-names = "cx", "mxc", "nsp";
4208 4208
4209 interconnects = <&nsp 4209 interconnects = <&nspb_noc MASTER_CDSP_PROC_B 0
4210 &mc_ 4210 &mc_virt SLAVE_EBI1 0>;
4211 4211
4212 memory-region = <&pil 4212 memory-region = <&pil_cdsp1_mem>;
4213 4213
4214 qcom,qmp = <&aoss_qmp 4214 qcom,qmp = <&aoss_qmp>;
4215 4215
4216 qcom,smem-states = <& 4216 qcom,smem-states = <&smp2p_cdsp1_out 0>;
4217 qcom,smem-state-names 4217 qcom,smem-state-names = "stop";
4218 4218
4219 status = "disabled"; 4219 status = "disabled";
4220 4220
4221 glink-edge { 4221 glink-edge {
4222 interrupts-ex 4222 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1
4223 4223 IPCC_MPROC_SIGNAL_GLINK_QMP
4224 4224 IRQ_TYPE_EDGE_RISING>;
4225 mboxes = <&ip 4225 mboxes = <&ipcc IPCC_CLIENT_NSP1
4226 4226 IPCC_MPROC_SIGNAL_GLINK_QMP>;
4227 4227
4228 label = "cdsp 4228 label = "cdsp";
4229 qcom,remote-p 4229 qcom,remote-pid = <12>;
4230 4230
4231 fastrpc { 4231 fastrpc {
4232 compa 4232 compatible = "qcom,fastrpc";
4233 qcom, 4233 qcom,glink-channels = "fastrpcglink-apps-dsp";
4234 label 4234 label = "cdsp1";
4235 #addr 4235 #address-cells = <1>;
4236 #size 4236 #size-cells = <0>;
4237 4237
4238 compu 4238 compute-cb@1 {
4239 4239 compatible = "qcom,fastrpc-compute-cb";
4240 4240 reg = <1>;
4241 4241 iommus = <&apps_smmu 0x2941 0x04a0>,
4242 4242 <&apps_smmu 0x2961 0x04a0>,
4243 4243 <&apps_smmu 0x2981 0x0400>,
4244 4244 <&apps_smmu 0x29c1 0x04a0>,
4245 4245 <&apps_smmu 0x29e1 0x04a0>,
4246 4246 <&apps_smmu 0x2d41 0x04a0>,
4247 4247 <&apps_smmu 0x2d61 0x04a0>,
4248 4248 <&apps_smmu 0x2d81 0x0400>,
4249 4249 <&apps_smmu 0x2dc1 0x04a0>,
4250 4250 <&apps_smmu 0x2de1 0x04a0>;
4251 4251 dma-coherent;
4252 }; 4252 };
4253 4253
4254 compu 4254 compute-cb@2 {
4255 4255 compatible = "qcom,fastrpc-compute-cb";
4256 4256 reg = <2>;
4257 4257 iommus = <&apps_smmu 0x2942 0x04a0>,
4258 4258 <&apps_smmu 0x2962 0x04a0>,
4259 4259 <&apps_smmu 0x2982 0x0400>,
4260 4260 <&apps_smmu 0x29c2 0x04a0>,
4261 4261 <&apps_smmu 0x29e2 0x04a0>,
4262 4262 <&apps_smmu 0x2d42 0x04a0>,
4263 4263 <&apps_smmu 0x2d62 0x04a0>,
4264 4264 <&apps_smmu 0x2d82 0x0400>,
4265 4265 <&apps_smmu 0x2dc2 0x04a0>,
4266 4266 <&apps_smmu 0x2de2 0x04a0>;
4267 4267 dma-coherent;
4268 }; 4268 };
4269 4269
4270 compu 4270 compute-cb@3 {
4271 4271 compatible = "qcom,fastrpc-compute-cb";
4272 4272 reg = <3>;
4273 4273 iommus = <&apps_smmu 0x2943 0x04a0>,
4274 4274 <&apps_smmu 0x2963 0x04a0>,
4275 4275 <&apps_smmu 0x2983 0x0400>,
4276 4276 <&apps_smmu 0x29c3 0x04a0>,
4277 4277 <&apps_smmu 0x29e3 0x04a0>,
4278 4278 <&apps_smmu 0x2d43 0x04a0>,
4279 4279 <&apps_smmu 0x2d63 0x04a0>,
4280 4280 <&apps_smmu 0x2d83 0x0400>,
4281 4281 <&apps_smmu 0x2dc3 0x04a0>,
4282 4282 <&apps_smmu 0x2de3 0x04a0>;
4283 4283 dma-coherent;
4284 }; 4284 };
4285 4285
4286 compu 4286 compute-cb@4 {
4287 4287 compatible = "qcom,fastrpc-compute-cb";
4288 4288 reg = <4>;
4289 4289 iommus = <&apps_smmu 0x2944 0x04a0>,
4290 4290 <&apps_smmu 0x2964 0x04a0>,
4291 4291 <&apps_smmu 0x2984 0x0400>,
4292 4292 <&apps_smmu 0x29c4 0x04a0>,
4293 4293 <&apps_smmu 0x29e4 0x04a0>,
4294 4294 <&apps_smmu 0x2d44 0x04a0>,
4295 4295 <&apps_smmu 0x2d64 0x04a0>,
4296 4296 <&apps_smmu 0x2d84 0x0400>,
4297 4297 <&apps_smmu 0x2dc4 0x04a0>,
4298 4298 <&apps_smmu 0x2de4 0x04a0>;
4299 4299 dma-coherent;
4300 }; 4300 };
4301 4301
4302 compu 4302 compute-cb@5 {
4303 4303 compatible = "qcom,fastrpc-compute-cb";
4304 4304 reg = <5>;
4305 4305 iommus = <&apps_smmu 0x2945 0x04a0>,
4306 4306 <&apps_smmu 0x2965 0x04a0>,
4307 4307 <&apps_smmu 0x2985 0x0400>,
4308 4308 <&apps_smmu 0x29c5 0x04a0>,
4309 4309 <&apps_smmu 0x29e5 0x04a0>,
4310 4310 <&apps_smmu 0x2d45 0x04a0>,
4311 4311 <&apps_smmu 0x2d65 0x04a0>,
4312 4312 <&apps_smmu 0x2d85 0x0400>,
4313 4313 <&apps_smmu 0x2dc5 0x04a0>,
4314 4314 <&apps_smmu 0x2de5 0x04a0>;
4315 4315 dma-coherent;
4316 }; 4316 };
4317 4317
4318 compu 4318 compute-cb@6 {
4319 4319 compatible = "qcom,fastrpc-compute-cb";
4320 4320 reg = <6>;
4321 4321 iommus = <&apps_smmu 0x2946 0x04a0>,
4322 4322 <&apps_smmu 0x2966 0x04a0>,
4323 4323 <&apps_smmu 0x2986 0x0400>,
4324 4324 <&apps_smmu 0x29c6 0x04a0>,
4325 4325 <&apps_smmu 0x29e6 0x04a0>,
4326 4326 <&apps_smmu 0x2d46 0x04a0>,
4327 4327 <&apps_smmu 0x2d66 0x04a0>,
4328 4328 <&apps_smmu 0x2d86 0x0400>,
4329 4329 <&apps_smmu 0x2dc6 0x04a0>,
4330 4330 <&apps_smmu 0x2de6 0x04a0>;
4331 4331 dma-coherent;
4332 }; 4332 };
4333 4333
4334 compu 4334 compute-cb@7 {
4335 4335 compatible = "qcom,fastrpc-compute-cb";
4336 4336 reg = <7>;
4337 4337 iommus = <&apps_smmu 0x2947 0x04a0>,
4338 4338 <&apps_smmu 0x2967 0x04a0>,
4339 4339 <&apps_smmu 0x2987 0x0400>,
4340 4340 <&apps_smmu 0x29c7 0x04a0>,
4341 4341 <&apps_smmu 0x29e7 0x04a0>,
4342 4342 <&apps_smmu 0x2d47 0x04a0>,
4343 4343 <&apps_smmu 0x2d67 0x04a0>,
4344 4344 <&apps_smmu 0x2d87 0x0400>,
4345 4345 <&apps_smmu 0x2dc7 0x04a0>,
4346 4346 <&apps_smmu 0x2de7 0x04a0>;
4347 4347 dma-coherent;
4348 }; 4348 };
4349 4349
4350 compu 4350 compute-cb@8 {
4351 4351 compatible = "qcom,fastrpc-compute-cb";
4352 4352 reg = <8>;
4353 4353 iommus = <&apps_smmu 0x2948 0x04a0>,
4354 4354 <&apps_smmu 0x2968 0x04a0>,
4355 4355 <&apps_smmu 0x2988 0x0400>,
4356 4356 <&apps_smmu 0x29c8 0x04a0>,
4357 4357 <&apps_smmu 0x29e8 0x04a0>,
4358 4358 <&apps_smmu 0x2d48 0x04a0>,
4359 4359 <&apps_smmu 0x2d68 0x04a0>,
4360 4360 <&apps_smmu 0x2d88 0x0400>,
4361 4361 <&apps_smmu 0x2dc8 0x04a0>,
4362 4362 <&apps_smmu 0x2de8 0x04a0>;
4363 4363 dma-coherent;
4364 }; 4364 };
4365 4365
4366 compu 4366 compute-cb@9 {
4367 4367 compatible = "qcom,fastrpc-compute-cb";
4368 4368 reg = <9>;
4369 4369 iommus = <&apps_smmu 0x2949 0x04a0>,
4370 4370 <&apps_smmu 0x2969 0x04a0>,
4371 4371 <&apps_smmu 0x2989 0x0400>,
4372 4372 <&apps_smmu 0x29c9 0x04a0>,
4373 4373 <&apps_smmu 0x29e9 0x04a0>,
4374 4374 <&apps_smmu 0x2d49 0x04a0>,
4375 4375 <&apps_smmu 0x2d69 0x04a0>,
4376 4376 <&apps_smmu 0x2d89 0x0400>,
4377 4377 <&apps_smmu 0x2dc9 0x04a0>,
4378 4378 <&apps_smmu 0x2de9 0x04a0>;
4379 4379 dma-coherent;
4380 }; 4380 };
4381 4381
4382 compu 4382 compute-cb@10 {
4383 4383 compatible = "qcom,fastrpc-compute-cb";
4384 4384 reg = <10>;
4385 4385 iommus = <&apps_smmu 0x294a 0x04a0>,
4386 4386 <&apps_smmu 0x296a 0x04a0>,
4387 4387 <&apps_smmu 0x298a 0x0400>,
4388 4388 <&apps_smmu 0x29ca 0x04a0>,
4389 4389 <&apps_smmu 0x29ea 0x04a0>,
4390 4390 <&apps_smmu 0x2d4a 0x04a0>,
4391 4391 <&apps_smmu 0x2d6a 0x04a0>,
4392 4392 <&apps_smmu 0x2d8a 0x0400>,
4393 4393 <&apps_smmu 0x2dca 0x04a0>,
4394 4394 <&apps_smmu 0x2dea 0x04a0>;
4395 4395 dma-coherent;
4396 }; 4396 };
4397 4397
4398 compu 4398 compute-cb@11 {
4399 4399 compatible = "qcom,fastrpc-compute-cb";
4400 4400 reg = <11>;
4401 4401 iommus = <&apps_smmu 0x294b 0x04a0>,
4402 4402 <&apps_smmu 0x296b 0x04a0>,
4403 4403 <&apps_smmu 0x298b 0x0400>,
4404 4404 <&apps_smmu 0x29cb 0x04a0>,
4405 4405 <&apps_smmu 0x29eb 0x04a0>,
4406 4406 <&apps_smmu 0x2d4b 0x04a0>,
4407 4407 <&apps_smmu 0x2d6b 0x04a0>,
4408 4408 <&apps_smmu 0x2d8b 0x0400>,
4409 4409 <&apps_smmu 0x2dcb 0x04a0>,
4410 4410 <&apps_smmu 0x2deb 0x04a0>;
4411 4411 dma-coherent;
4412 }; 4412 };
4413 4413
4414 compu 4414 compute-cb@12 {
4415 4415 compatible = "qcom,fastrpc-compute-cb";
4416 4416 reg = <12>;
4417 4417 iommus = <&apps_smmu 0x294c 0x04a0>,
4418 4418 <&apps_smmu 0x296c 0x04a0>,
4419 4419 <&apps_smmu 0x298c 0x0400>,
4420 4420 <&apps_smmu 0x29cc 0x04a0>,
4421 4421 <&apps_smmu 0x29ec 0x04a0>,
4422 4422 <&apps_smmu 0x2d4c 0x04a0>,
4423 4423 <&apps_smmu 0x2d6c 0x04a0>,
4424 4424 <&apps_smmu 0x2d8c 0x0400>,
4425 4425 <&apps_smmu 0x2dcc 0x04a0>,
4426 4426 <&apps_smmu 0x2dec 0x04a0>;
4427 4427 dma-coherent;
4428 }; 4428 };
4429 4429
4430 compu 4430 compute-cb@13 {
4431 4431 compatible = "qcom,fastrpc-compute-cb";
4432 4432 reg = <13>;
4433 4433 iommus = <&apps_smmu 0x294d 0x04a0>,
4434 4434 <&apps_smmu 0x296d 0x04a0>,
4435 4435 <&apps_smmu 0x298d 0x0400>,
4436 4436 <&apps_smmu 0x29Cd 0x04a0>,
4437 4437 <&apps_smmu 0x29ed 0x04a0>,
4438 4438 <&apps_smmu 0x2d4d 0x04a0>,
4439 4439 <&apps_smmu 0x2d6d 0x04a0>,
4440 4440 <&apps_smmu 0x2d8d 0x0400>,
4441 4441 <&apps_smmu 0x2dcd 0x04a0>,
4442 4442 <&apps_smmu 0x2ded 0x04a0>;
4443 4443 dma-coherent;
4444 }; 4444 };
4445 }; 4445 };
4446 }; 4446 };
4447 }; 4447 };
4448 4448
4449 remoteproc_adsp: remoteproc@3 4449 remoteproc_adsp: remoteproc@30000000 {
4450 compatible = "qcom,sa 4450 compatible = "qcom,sa8775p-adsp-pas";
4451 reg = <0x0 0x30000000 4451 reg = <0x0 0x30000000 0x0 0x100>;
4452 4452
4453 interrupts-extended = 4453 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
4454 4454 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
4455 4455 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
4456 4456 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
4457 4457 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
4458 interrupt-names = "wd 4458 interrupt-names = "wdog", "fatal", "ready", "handover",
4459 "st 4459 "stop-ack";
4460 4460
4461 clocks = <&rpmhcc RPM 4461 clocks = <&rpmhcc RPMH_CXO_CLK>;
4462 clock-names = "xo"; 4462 clock-names = "xo";
4463 4463
4464 power-domains = <&rpm 4464 power-domains = <&rpmhpd RPMHPD_LCX>,
4465 <&rpm 4465 <&rpmhpd RPMHPD_LMX>;
4466 power-domain-names = 4466 power-domain-names = "lcx", "lmx";
4467 4467
4468 interconnects = <&lpa 4468 interconnects = <&lpass_ag_noc MASTER_LPASS_PROC 0 &mc_virt SLAVE_EBI1 0>;
4469 4469
4470 memory-region = <&pil 4470 memory-region = <&pil_adsp_mem>;
4471 4471
4472 qcom,qmp = <&aoss_qmp 4472 qcom,qmp = <&aoss_qmp>;
4473 4473
4474 qcom,smem-states = <& 4474 qcom,smem-states = <&smp2p_adsp_out 0>;
4475 qcom,smem-state-names 4475 qcom,smem-state-names = "stop";
4476 4476
4477 status = "disabled"; 4477 status = "disabled";
4478 4478
4479 remoteproc_adsp_glink 4479 remoteproc_adsp_glink: glink-edge {
4480 interrupts-ex 4480 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
4481 4481 IPCC_MPROC_SIGNAL_GLINK_QMP
4482 4482 IRQ_TYPE_EDGE_RISING>;
4483 mboxes = <&ip 4483 mboxes = <&ipcc IPCC_CLIENT_LPASS
4484 4484 IPCC_MPROC_SIGNAL_GLINK_QMP>;
4485 4485
4486 label = "lpas 4486 label = "lpass";
4487 qcom,remote-p 4487 qcom,remote-pid = <2>;
4488 4488
4489 fastrpc { 4489 fastrpc {
4490 compa 4490 compatible = "qcom,fastrpc";
4491 qcom, 4491 qcom,glink-channels = "fastrpcglink-apps-dsp";
4492 label 4492 label = "adsp";
4493 memor 4493 memory-region = <&adsp_rpc_remote_heap_mem>;
4494 qcom, 4494 qcom,vmids = <QCOM_SCM_VMID_LPASS
4495 4495 QCOM_SCM_VMID_ADSP_HEAP>;
4496 #addr 4496 #address-cells = <1>;
4497 #size 4497 #size-cells = <0>;
4498 4498
4499 compu 4499 compute-cb@3 {
4500 4500 compatible = "qcom,fastrpc-compute-cb";
4501 4501 reg = <3>;
4502 4502 iommus = <&apps_smmu 0x3003 0x0>;
4503 4503 dma-coherent;
4504 }; 4504 };
4505 4505
4506 compu 4506 compute-cb@4 {
4507 4507 compatible = "qcom,fastrpc-compute-cb";
4508 4508 reg = <4>;
4509 4509 iommus = <&apps_smmu 0x3004 0x0>;
4510 4510 dma-coherent;
4511 }; 4511 };
4512 4512
4513 compu 4513 compute-cb@5 {
4514 4514 compatible = "qcom,fastrpc-compute-cb";
4515 4515 reg = <5>;
4516 4516 iommus = <&apps_smmu 0x3005 0x0>;
4517 4517 qcom,nsessions = <5>;
4518 4518 dma-coherent;
4519 }; 4519 };
4520 }; 4520 };
4521 }; 4521 };
4522 }; 4522 };
4523 }; 4523 };
4524 4524
4525 thermal-zones { 4525 thermal-zones {
4526 aoss-0-thermal { 4526 aoss-0-thermal {
4527 thermal-sensors = <&t 4527 thermal-sensors = <&tsens0 0>;
4528 4528
4529 trips { 4529 trips {
4530 trip-point0 { 4530 trip-point0 {
4531 tempe 4531 temperature = <105000>;
4532 hyste 4532 hysteresis = <5000>;
4533 type 4533 type = "passive";
4534 }; 4534 };
4535 4535
4536 trip-point1 { 4536 trip-point1 {
4537 tempe 4537 temperature = <115000>;
4538 hyste 4538 hysteresis = <5000>;
4539 type 4539 type = "passive";
4540 }; 4540 };
4541 }; 4541 };
4542 }; 4542 };
4543 4543
4544 cpu-0-0-0-thermal { 4544 cpu-0-0-0-thermal {
4545 polling-delay-passive 4545 polling-delay-passive = <10>;
4546 4546
4547 thermal-sensors = <&t 4547 thermal-sensors = <&tsens0 1>;
4548 4548
4549 trips { 4549 trips {
4550 trip-point0 { 4550 trip-point0 {
4551 tempe 4551 temperature = <105000>;
4552 hyste 4552 hysteresis = <5000>;
4553 type 4553 type = "passive";
4554 }; 4554 };
4555 4555
4556 trip-point1 { 4556 trip-point1 {
4557 tempe 4557 temperature = <115000>;
4558 hyste 4558 hysteresis = <5000>;
4559 type 4559 type = "passive";
4560 }; 4560 };
4561 }; 4561 };
4562 }; 4562 };
4563 4563
4564 cpu-0-1-0-thermal { 4564 cpu-0-1-0-thermal {
4565 polling-delay-passive 4565 polling-delay-passive = <10>;
4566 4566
4567 thermal-sensors = <&t 4567 thermal-sensors = <&tsens0 2>;
4568 4568
4569 trips { 4569 trips {
4570 trip-point0 { 4570 trip-point0 {
4571 tempe 4571 temperature = <105000>;
4572 hyste 4572 hysteresis = <5000>;
4573 type 4573 type = "passive";
4574 }; 4574 };
4575 4575
4576 trip-point1 { 4576 trip-point1 {
4577 tempe 4577 temperature = <115000>;
4578 hyste 4578 hysteresis = <5000>;
4579 type 4579 type = "passive";
4580 }; 4580 };
4581 }; 4581 };
4582 }; 4582 };
4583 4583
4584 cpu-0-2-0-thermal { 4584 cpu-0-2-0-thermal {
4585 polling-delay-passive 4585 polling-delay-passive = <10>;
4586 4586
4587 thermal-sensors = <&t 4587 thermal-sensors = <&tsens0 3>;
4588 4588
4589 trips { 4589 trips {
4590 trip-point0 { 4590 trip-point0 {
4591 tempe 4591 temperature = <105000>;
4592 hyste 4592 hysteresis = <5000>;
4593 type 4593 type = "passive";
4594 }; 4594 };
4595 4595
4596 trip-point1 { 4596 trip-point1 {
4597 tempe 4597 temperature = <115000>;
4598 hyste 4598 hysteresis = <5000>;
4599 type 4599 type = "passive";
4600 }; 4600 };
4601 }; 4601 };
4602 }; 4602 };
4603 4603
4604 cpu-0-3-0-thermal { 4604 cpu-0-3-0-thermal {
4605 polling-delay-passive 4605 polling-delay-passive = <10>;
4606 4606
4607 thermal-sensors = <&t 4607 thermal-sensors = <&tsens0 4>;
4608 4608
4609 trips { 4609 trips {
4610 trip-point0 { 4610 trip-point0 {
4611 tempe 4611 temperature = <105000>;
4612 hyste 4612 hysteresis = <5000>;
4613 type 4613 type = "passive";
4614 }; 4614 };
4615 4615
4616 trip-point1 { 4616 trip-point1 {
4617 tempe 4617 temperature = <115000>;
4618 hyste 4618 hysteresis = <5000>;
4619 type 4619 type = "passive";
4620 }; 4620 };
4621 }; 4621 };
4622 }; 4622 };
4623 4623
4624 gpuss-0-thermal { 4624 gpuss-0-thermal {
4625 polling-delay-passive 4625 polling-delay-passive = <10>;
4626 4626
4627 thermal-sensors = <&t 4627 thermal-sensors = <&tsens0 5>;
4628 4628
4629 trips { 4629 trips {
4630 trip-point0 { 4630 trip-point0 {
4631 tempe 4631 temperature = <105000>;
4632 hyste 4632 hysteresis = <5000>;
4633 type 4633 type = "passive";
4634 }; 4634 };
4635 4635
4636 trip-point1 { 4636 trip-point1 {
4637 tempe 4637 temperature = <115000>;
4638 hyste 4638 hysteresis = <5000>;
4639 type 4639 type = "passive";
4640 }; 4640 };
4641 }; 4641 };
4642 }; 4642 };
4643 4643
4644 gpuss-1-thermal { 4644 gpuss-1-thermal {
4645 polling-delay-passive 4645 polling-delay-passive = <10>;
4646 4646
4647 thermal-sensors = <&t 4647 thermal-sensors = <&tsens0 6>;
4648 4648
4649 trips { 4649 trips {
4650 trip-point0 { 4650 trip-point0 {
4651 tempe 4651 temperature = <105000>;
4652 hyste 4652 hysteresis = <5000>;
4653 type 4653 type = "passive";
4654 }; 4654 };
4655 4655
4656 trip-point1 { 4656 trip-point1 {
4657 tempe 4657 temperature = <115000>;
4658 hyste 4658 hysteresis = <5000>;
4659 type 4659 type = "passive";
4660 }; 4660 };
4661 }; 4661 };
4662 }; 4662 };
4663 4663
4664 gpuss-2-thermal { 4664 gpuss-2-thermal {
4665 polling-delay-passive 4665 polling-delay-passive = <10>;
4666 4666
4667 thermal-sensors = <&t 4667 thermal-sensors = <&tsens0 7>;
4668 4668
4669 trips { 4669 trips {
4670 trip-point0 { 4670 trip-point0 {
4671 tempe 4671 temperature = <105000>;
4672 hyste 4672 hysteresis = <5000>;
4673 type 4673 type = "passive";
4674 }; 4674 };
4675 4675
4676 trip-point1 { 4676 trip-point1 {
4677 tempe 4677 temperature = <115000>;
4678 hyste 4678 hysteresis = <5000>;
4679 type 4679 type = "passive";
4680 }; 4680 };
4681 }; 4681 };
4682 }; 4682 };
4683 4683
4684 audio-thermal { 4684 audio-thermal {
4685 thermal-sensors = <&t 4685 thermal-sensors = <&tsens0 8>;
4686 4686
4687 trips { 4687 trips {
4688 trip-point0 { 4688 trip-point0 {
4689 tempe 4689 temperature = <105000>;
4690 hyste 4690 hysteresis = <5000>;
4691 type 4691 type = "passive";
4692 }; 4692 };
4693 4693
4694 trip-point1 { 4694 trip-point1 {
4695 tempe 4695 temperature = <115000>;
4696 hyste 4696 hysteresis = <5000>;
4697 type 4697 type = "passive";
4698 }; 4698 };
4699 }; 4699 };
4700 }; 4700 };
4701 4701
4702 camss-0-thermal { 4702 camss-0-thermal {
4703 thermal-sensors = <&t 4703 thermal-sensors = <&tsens0 9>;
4704 4704
4705 trips { 4705 trips {
4706 trip-point0 { 4706 trip-point0 {
4707 tempe 4707 temperature = <105000>;
4708 hyste 4708 hysteresis = <5000>;
4709 type 4709 type = "passive";
4710 }; 4710 };
4711 4711
4712 trip-point1 { 4712 trip-point1 {
4713 tempe 4713 temperature = <115000>;
4714 hyste 4714 hysteresis = <5000>;
4715 type 4715 type = "passive";
4716 }; 4716 };
4717 }; 4717 };
4718 }; 4718 };
4719 4719
4720 pcie-0-thermal { 4720 pcie-0-thermal {
4721 thermal-sensors = <&t 4721 thermal-sensors = <&tsens0 10>;
4722 4722
4723 trips { 4723 trips {
4724 trip-point0 { 4724 trip-point0 {
4725 tempe 4725 temperature = <105000>;
4726 hyste 4726 hysteresis = <5000>;
4727 type 4727 type = "passive";
4728 }; 4728 };
4729 4729
4730 trip-point1 { 4730 trip-point1 {
4731 tempe 4731 temperature = <115000>;
4732 hyste 4732 hysteresis = <5000>;
4733 type 4733 type = "passive";
4734 }; 4734 };
4735 }; 4735 };
4736 }; 4736 };
4737 4737
4738 cpuss-0-0-thermal { 4738 cpuss-0-0-thermal {
4739 thermal-sensors = <&t 4739 thermal-sensors = <&tsens0 11>;
4740 4740
4741 trips { 4741 trips {
4742 trip-point0 { 4742 trip-point0 {
4743 tempe 4743 temperature = <105000>;
4744 hyste 4744 hysteresis = <5000>;
4745 type 4745 type = "passive";
4746 }; 4746 };
4747 4747
4748 trip-point1 { 4748 trip-point1 {
4749 tempe 4749 temperature = <115000>;
4750 hyste 4750 hysteresis = <5000>;
4751 type 4751 type = "passive";
4752 }; 4752 };
4753 }; 4753 };
4754 }; 4754 };
4755 4755
4756 aoss-1-thermal { 4756 aoss-1-thermal {
4757 thermal-sensors = <&t 4757 thermal-sensors = <&tsens1 0>;
4758 4758
4759 trips { 4759 trips {
4760 trip-point0 { 4760 trip-point0 {
4761 tempe 4761 temperature = <105000>;
4762 hyste 4762 hysteresis = <5000>;
4763 type 4763 type = "passive";
4764 }; 4764 };
4765 4765
4766 trip-point1 { 4766 trip-point1 {
4767 tempe 4767 temperature = <115000>;
4768 hyste 4768 hysteresis = <5000>;
4769 type 4769 type = "passive";
4770 }; 4770 };
4771 }; 4771 };
4772 }; 4772 };
4773 4773
4774 cpu-0-0-1-thermal { 4774 cpu-0-0-1-thermal {
4775 polling-delay-passive 4775 polling-delay-passive = <10>;
4776 4776
4777 thermal-sensors = <&t 4777 thermal-sensors = <&tsens1 1>;
4778 4778
4779 trips { 4779 trips {
4780 trip-point0 { 4780 trip-point0 {
4781 tempe 4781 temperature = <105000>;
4782 hyste 4782 hysteresis = <5000>;
4783 type 4783 type = "passive";
4784 }; 4784 };
4785 4785
4786 trip-point1 { 4786 trip-point1 {
4787 tempe 4787 temperature = <115000>;
4788 hyste 4788 hysteresis = <5000>;
4789 type 4789 type = "passive";
4790 }; 4790 };
4791 }; 4791 };
4792 }; 4792 };
4793 4793
4794 cpu-0-1-1-thermal { 4794 cpu-0-1-1-thermal {
4795 polling-delay-passive 4795 polling-delay-passive = <10>;
4796 4796
4797 thermal-sensors = <&t 4797 thermal-sensors = <&tsens1 2>;
4798 4798
4799 trips { 4799 trips {
4800 trip-point0 { 4800 trip-point0 {
4801 tempe 4801 temperature = <105000>;
4802 hyste 4802 hysteresis = <5000>;
4803 type 4803 type = "passive";
4804 }; 4804 };
4805 4805
4806 trip-point1 { 4806 trip-point1 {
4807 tempe 4807 temperature = <115000>;
4808 hyste 4808 hysteresis = <5000>;
4809 type 4809 type = "passive";
4810 }; 4810 };
4811 }; 4811 };
4812 }; 4812 };
4813 4813
4814 cpu-0-2-1-thermal { 4814 cpu-0-2-1-thermal {
4815 polling-delay-passive 4815 polling-delay-passive = <10>;
4816 4816
4817 thermal-sensors = <&t 4817 thermal-sensors = <&tsens1 3>;
4818 4818
4819 trips { 4819 trips {
4820 trip-point0 { 4820 trip-point0 {
4821 tempe 4821 temperature = <105000>;
4822 hyste 4822 hysteresis = <5000>;
4823 type 4823 type = "passive";
4824 }; 4824 };
4825 4825
4826 trip-point1 { 4826 trip-point1 {
4827 tempe 4827 temperature = <115000>;
4828 hyste 4828 hysteresis = <5000>;
4829 type 4829 type = "passive";
4830 }; 4830 };
4831 }; 4831 };
4832 }; 4832 };
4833 4833
4834 cpu-0-3-1-thermal { 4834 cpu-0-3-1-thermal {
4835 polling-delay-passive 4835 polling-delay-passive = <10>;
4836 4836
4837 thermal-sensors = <&t 4837 thermal-sensors = <&tsens1 4>;
4838 4838
4839 trips { 4839 trips {
4840 trip-point0 { 4840 trip-point0 {
4841 tempe 4841 temperature = <105000>;
4842 hyste 4842 hysteresis = <5000>;
4843 type 4843 type = "passive";
4844 }; 4844 };
4845 4845
4846 trip-point1 { 4846 trip-point1 {
4847 tempe 4847 temperature = <115000>;
4848 hyste 4848 hysteresis = <5000>;
4849 type 4849 type = "passive";
4850 }; 4850 };
4851 }; 4851 };
4852 }; 4852 };
4853 4853
4854 gpuss-3-thermal { 4854 gpuss-3-thermal {
4855 polling-delay-passive 4855 polling-delay-passive = <10>;
4856 4856
4857 thermal-sensors = <&t 4857 thermal-sensors = <&tsens1 5>;
4858 4858
4859 trips { 4859 trips {
4860 trip-point0 { 4860 trip-point0 {
4861 tempe 4861 temperature = <105000>;
4862 hyste 4862 hysteresis = <5000>;
4863 type 4863 type = "passive";
4864 }; 4864 };
4865 4865
4866 trip-point1 { 4866 trip-point1 {
4867 tempe 4867 temperature = <115000>;
4868 hyste 4868 hysteresis = <5000>;
4869 type 4869 type = "passive";
4870 }; 4870 };
4871 }; 4871 };
4872 }; 4872 };
4873 4873
4874 gpuss-4-thermal { 4874 gpuss-4-thermal {
4875 polling-delay-passive 4875 polling-delay-passive = <10>;
4876 4876
4877 thermal-sensors = <&t 4877 thermal-sensors = <&tsens1 6>;
4878 4878
4879 trips { 4879 trips {
4880 trip-point0 { 4880 trip-point0 {
4881 tempe 4881 temperature = <105000>;
4882 hyste 4882 hysteresis = <5000>;
4883 type 4883 type = "passive";
4884 }; 4884 };
4885 4885
4886 trip-point1 { 4886 trip-point1 {
4887 tempe 4887 temperature = <115000>;
4888 hyste 4888 hysteresis = <5000>;
4889 type 4889 type = "passive";
4890 }; 4890 };
4891 }; 4891 };
4892 }; 4892 };
4893 4893
4894 gpuss-5-thermal { 4894 gpuss-5-thermal {
4895 polling-delay-passive 4895 polling-delay-passive = <10>;
4896 4896
4897 thermal-sensors = <&t 4897 thermal-sensors = <&tsens1 7>;
4898 4898
4899 trips { 4899 trips {
4900 trip-point0 { 4900 trip-point0 {
4901 tempe 4901 temperature = <105000>;
4902 hyste 4902 hysteresis = <5000>;
4903 type 4903 type = "passive";
4904 }; 4904 };
4905 4905
4906 trip-point1 { 4906 trip-point1 {
4907 tempe 4907 temperature = <115000>;
4908 hyste 4908 hysteresis = <5000>;
4909 type 4909 type = "passive";
4910 }; 4910 };
4911 }; 4911 };
4912 }; 4912 };
4913 4913
4914 video-thermal { 4914 video-thermal {
4915 thermal-sensors = <&t 4915 thermal-sensors = <&tsens1 8>;
4916 4916
4917 trips { 4917 trips {
4918 trip-point0 { 4918 trip-point0 {
4919 tempe 4919 temperature = <105000>;
4920 hyste 4920 hysteresis = <5000>;
4921 type 4921 type = "passive";
4922 }; 4922 };
4923 4923
4924 trip-point1 { 4924 trip-point1 {
4925 tempe 4925 temperature = <115000>;
4926 hyste 4926 hysteresis = <5000>;
4927 type 4927 type = "passive";
4928 }; 4928 };
4929 }; 4929 };
4930 }; 4930 };
4931 4931
4932 camss-1-thermal { 4932 camss-1-thermal {
4933 thermal-sensors = <&t 4933 thermal-sensors = <&tsens1 9>;
4934 4934
4935 trips { 4935 trips {
4936 trip-point0 { 4936 trip-point0 {
4937 tempe 4937 temperature = <105000>;
4938 hyste 4938 hysteresis = <5000>;
4939 type 4939 type = "passive";
4940 }; 4940 };
4941 4941
4942 trip-point1 { 4942 trip-point1 {
4943 tempe 4943 temperature = <115000>;
4944 hyste 4944 hysteresis = <5000>;
4945 type 4945 type = "passive";
4946 }; 4946 };
4947 }; 4947 };
4948 }; 4948 };
4949 4949
4950 pcie-1-thermal { 4950 pcie-1-thermal {
4951 thermal-sensors = <&t 4951 thermal-sensors = <&tsens1 10>;
4952 4952
4953 trips { 4953 trips {
4954 trip-point0 { 4954 trip-point0 {
4955 tempe 4955 temperature = <105000>;
4956 hyste 4956 hysteresis = <5000>;
4957 type 4957 type = "passive";
4958 }; 4958 };
4959 4959
4960 trip-point1 { 4960 trip-point1 {
4961 tempe 4961 temperature = <115000>;
4962 hyste 4962 hysteresis = <5000>;
4963 type 4963 type = "passive";
4964 }; 4964 };
4965 }; 4965 };
4966 }; 4966 };
4967 4967
4968 cpuss-0-1-thermal { 4968 cpuss-0-1-thermal {
4969 thermal-sensors = <&t 4969 thermal-sensors = <&tsens1 11>;
4970 4970
4971 trips { 4971 trips {
4972 trip-point0 { 4972 trip-point0 {
4973 tempe 4973 temperature = <105000>;
4974 hyste 4974 hysteresis = <5000>;
4975 type 4975 type = "passive";
4976 }; 4976 };
4977 4977
4978 trip-point1 { 4978 trip-point1 {
4979 tempe 4979 temperature = <115000>;
4980 hyste 4980 hysteresis = <5000>;
4981 type 4981 type = "passive";
4982 }; 4982 };
4983 }; 4983 };
4984 }; 4984 };
4985 4985
4986 aoss-2-thermal { 4986 aoss-2-thermal {
4987 thermal-sensors = <&t 4987 thermal-sensors = <&tsens2 0>;
4988 4988
4989 trips { 4989 trips {
4990 trip-point0 { 4990 trip-point0 {
4991 tempe 4991 temperature = <105000>;
4992 hyste 4992 hysteresis = <5000>;
4993 type 4993 type = "passive";
4994 }; 4994 };
4995 4995
4996 trip-point1 { 4996 trip-point1 {
4997 tempe 4997 temperature = <115000>;
4998 hyste 4998 hysteresis = <5000>;
4999 type 4999 type = "passive";
5000 }; 5000 };
5001 }; 5001 };
5002 }; 5002 };
5003 5003
5004 cpu-1-0-0-thermal { 5004 cpu-1-0-0-thermal {
5005 polling-delay-passive 5005 polling-delay-passive = <10>;
5006 5006
5007 thermal-sensors = <&t 5007 thermal-sensors = <&tsens2 1>;
5008 5008
5009 trips { 5009 trips {
5010 trip-point0 { 5010 trip-point0 {
5011 tempe 5011 temperature = <105000>;
5012 hyste 5012 hysteresis = <5000>;
5013 type 5013 type = "passive";
5014 }; 5014 };
5015 5015
5016 trip-point1 { 5016 trip-point1 {
5017 tempe 5017 temperature = <115000>;
5018 hyste 5018 hysteresis = <5000>;
5019 type 5019 type = "passive";
5020 }; 5020 };
5021 }; 5021 };
5022 }; 5022 };
5023 5023
5024 cpu-1-1-0-thermal { 5024 cpu-1-1-0-thermal {
5025 polling-delay-passive 5025 polling-delay-passive = <10>;
5026 5026
5027 thermal-sensors = <&t 5027 thermal-sensors = <&tsens2 2>;
5028 5028
5029 trips { 5029 trips {
5030 trip-point0 { 5030 trip-point0 {
5031 tempe 5031 temperature = <105000>;
5032 hyste 5032 hysteresis = <5000>;
5033 type 5033 type = "passive";
5034 }; 5034 };
5035 5035
5036 trip-point1 { 5036 trip-point1 {
5037 tempe 5037 temperature = <115000>;
5038 hyste 5038 hysteresis = <5000>;
5039 type 5039 type = "passive";
5040 }; 5040 };
5041 }; 5041 };
5042 }; 5042 };
5043 5043
5044 cpu-1-2-0-thermal { 5044 cpu-1-2-0-thermal {
5045 polling-delay-passive 5045 polling-delay-passive = <10>;
5046 5046
5047 thermal-sensors = <&t 5047 thermal-sensors = <&tsens2 3>;
5048 5048
5049 trips { 5049 trips {
5050 trip-point0 { 5050 trip-point0 {
5051 tempe 5051 temperature = <105000>;
5052 hyste 5052 hysteresis = <5000>;
5053 type 5053 type = "passive";
5054 }; 5054 };
5055 5055
5056 trip-point1 { 5056 trip-point1 {
5057 tempe 5057 temperature = <115000>;
5058 hyste 5058 hysteresis = <5000>;
5059 type 5059 type = "passive";
5060 }; 5060 };
5061 }; 5061 };
5062 }; 5062 };
5063 5063
5064 cpu-1-3-0-thermal { 5064 cpu-1-3-0-thermal {
5065 polling-delay-passive 5065 polling-delay-passive = <10>;
5066 5066
5067 thermal-sensors = <&t 5067 thermal-sensors = <&tsens2 4>;
5068 5068
5069 trips { 5069 trips {
5070 trip-point0 { 5070 trip-point0 {
5071 tempe 5071 temperature = <105000>;
5072 hyste 5072 hysteresis = <5000>;
5073 type 5073 type = "passive";
5074 }; 5074 };
5075 5075
5076 trip-point1 { 5076 trip-point1 {
5077 tempe 5077 temperature = <115000>;
5078 hyste 5078 hysteresis = <5000>;
5079 type 5079 type = "passive";
5080 }; 5080 };
5081 }; 5081 };
5082 }; 5082 };
5083 5083
5084 nsp-0-0-0-thermal { 5084 nsp-0-0-0-thermal {
5085 polling-delay-passive 5085 polling-delay-passive = <10>;
5086 5086
5087 thermal-sensors = <&t 5087 thermal-sensors = <&tsens2 5>;
5088 5088
5089 trips { 5089 trips {
5090 trip-point0 { 5090 trip-point0 {
5091 tempe 5091 temperature = <105000>;
5092 hyste 5092 hysteresis = <5000>;
5093 type 5093 type = "passive";
5094 }; 5094 };
5095 5095
5096 trip-point1 { 5096 trip-point1 {
5097 tempe 5097 temperature = <115000>;
5098 hyste 5098 hysteresis = <5000>;
5099 type 5099 type = "passive";
5100 }; 5100 };
5101 }; 5101 };
5102 }; 5102 };
5103 5103
5104 nsp-0-1-0-thermal { 5104 nsp-0-1-0-thermal {
5105 polling-delay-passive 5105 polling-delay-passive = <10>;
5106 5106
5107 thermal-sensors = <&t 5107 thermal-sensors = <&tsens2 6>;
5108 5108
5109 trips { 5109 trips {
5110 trip-point0 { 5110 trip-point0 {
5111 tempe 5111 temperature = <105000>;
5112 hyste 5112 hysteresis = <5000>;
5113 type 5113 type = "passive";
5114 }; 5114 };
5115 5115
5116 trip-point1 { 5116 trip-point1 {
5117 tempe 5117 temperature = <115000>;
5118 hyste 5118 hysteresis = <5000>;
5119 type 5119 type = "passive";
5120 }; 5120 };
5121 }; 5121 };
5122 }; 5122 };
5123 5123
5124 nsp-0-2-0-thermal { 5124 nsp-0-2-0-thermal {
5125 polling-delay-passive 5125 polling-delay-passive = <10>;
5126 5126
5127 thermal-sensors = <&t 5127 thermal-sensors = <&tsens2 7>;
5128 5128
5129 trips { 5129 trips {
5130 trip-point0 { 5130 trip-point0 {
5131 tempe 5131 temperature = <105000>;
5132 hyste 5132 hysteresis = <5000>;
5133 type 5133 type = "passive";
5134 }; 5134 };
5135 5135
5136 trip-point1 { 5136 trip-point1 {
5137 tempe 5137 temperature = <115000>;
5138 hyste 5138 hysteresis = <5000>;
5139 type 5139 type = "passive";
5140 }; 5140 };
5141 }; 5141 };
5142 }; 5142 };
5143 5143
5144 nsp-1-0-0-thermal { 5144 nsp-1-0-0-thermal {
5145 polling-delay-passive 5145 polling-delay-passive = <10>;
5146 5146
5147 thermal-sensors = <&t 5147 thermal-sensors = <&tsens2 8>;
5148 5148
5149 trips { 5149 trips {
5150 trip-point0 { 5150 trip-point0 {
5151 tempe 5151 temperature = <105000>;
5152 hyste 5152 hysteresis = <5000>;
5153 type 5153 type = "passive";
5154 }; 5154 };
5155 5155
5156 trip-point1 { 5156 trip-point1 {
5157 tempe 5157 temperature = <115000>;
5158 hyste 5158 hysteresis = <5000>;
5159 type 5159 type = "passive";
5160 }; 5160 };
5161 }; 5161 };
5162 }; 5162 };
5163 5163
5164 nsp-1-1-0-thermal { 5164 nsp-1-1-0-thermal {
5165 polling-delay-passive 5165 polling-delay-passive = <10>;
5166 5166
5167 thermal-sensors = <&t 5167 thermal-sensors = <&tsens2 9>;
5168 5168
5169 trips { 5169 trips {
5170 trip-point0 { 5170 trip-point0 {
5171 tempe 5171 temperature = <105000>;
5172 hyste 5172 hysteresis = <5000>;
5173 type 5173 type = "passive";
5174 }; 5174 };
5175 5175
5176 trip-point1 { 5176 trip-point1 {
5177 tempe 5177 temperature = <115000>;
5178 hyste 5178 hysteresis = <5000>;
5179 type 5179 type = "passive";
5180 }; 5180 };
5181 }; 5181 };
5182 }; 5182 };
5183 5183
5184 nsp-1-2-0-thermal { 5184 nsp-1-2-0-thermal {
5185 polling-delay-passive 5185 polling-delay-passive = <10>;
5186 5186
5187 thermal-sensors = <&t 5187 thermal-sensors = <&tsens2 10>;
5188 5188
5189 trips { 5189 trips {
5190 trip-point0 { 5190 trip-point0 {
5191 tempe 5191 temperature = <105000>;
5192 hyste 5192 hysteresis = <5000>;
5193 type 5193 type = "passive";
5194 }; 5194 };
5195 5195
5196 trip-point1 { 5196 trip-point1 {
5197 tempe 5197 temperature = <115000>;
5198 hyste 5198 hysteresis = <5000>;
5199 type 5199 type = "passive";
5200 }; 5200 };
5201 }; 5201 };
5202 }; 5202 };
5203 5203
5204 ddrss-0-thermal { 5204 ddrss-0-thermal {
5205 thermal-sensors = <&t 5205 thermal-sensors = <&tsens2 11>;
5206 5206
5207 trips { 5207 trips {
5208 trip-point0 { 5208 trip-point0 {
5209 tempe 5209 temperature = <105000>;
5210 hyste 5210 hysteresis = <5000>;
5211 type 5211 type = "passive";
5212 }; 5212 };
5213 5213
5214 trip-point1 { 5214 trip-point1 {
5215 tempe 5215 temperature = <115000>;
5216 hyste 5216 hysteresis = <5000>;
5217 type 5217 type = "passive";
5218 }; 5218 };
5219 }; 5219 };
5220 }; 5220 };
5221 5221
5222 cpuss-1-0-thermal { 5222 cpuss-1-0-thermal {
5223 thermal-sensors = <&t 5223 thermal-sensors = <&tsens2 12>;
5224 5224
5225 trips { 5225 trips {
5226 trip-point0 { 5226 trip-point0 {
5227 tempe 5227 temperature = <105000>;
5228 hyste 5228 hysteresis = <5000>;
5229 type 5229 type = "passive";
5230 }; 5230 };
5231 5231
5232 trip-point1 { 5232 trip-point1 {
5233 tempe 5233 temperature = <115000>;
5234 hyste 5234 hysteresis = <5000>;
5235 type 5235 type = "passive";
5236 }; 5236 };
5237 }; 5237 };
5238 }; 5238 };
5239 5239
5240 aoss-3-thermal { 5240 aoss-3-thermal {
5241 thermal-sensors = <&t 5241 thermal-sensors = <&tsens3 0>;
5242 5242
5243 trips { 5243 trips {
5244 trip-point0 { 5244 trip-point0 {
5245 tempe 5245 temperature = <105000>;
5246 hyste 5246 hysteresis = <5000>;
5247 type 5247 type = "passive";
5248 }; 5248 };
5249 5249
5250 trip-point1 { 5250 trip-point1 {
5251 tempe 5251 temperature = <115000>;
5252 hyste 5252 hysteresis = <5000>;
5253 type 5253 type = "passive";
5254 }; 5254 };
5255 }; 5255 };
5256 }; 5256 };
5257 5257
5258 cpu-1-0-1-thermal { 5258 cpu-1-0-1-thermal {
5259 polling-delay-passive 5259 polling-delay-passive = <10>;
5260 5260
5261 thermal-sensors = <&t 5261 thermal-sensors = <&tsens3 1>;
5262 5262
5263 trips { 5263 trips {
5264 trip-point0 { 5264 trip-point0 {
5265 tempe 5265 temperature = <105000>;
5266 hyste 5266 hysteresis = <5000>;
5267 type 5267 type = "passive";
5268 }; 5268 };
5269 5269
5270 trip-point1 { 5270 trip-point1 {
5271 tempe 5271 temperature = <115000>;
5272 hyste 5272 hysteresis = <5000>;
5273 type 5273 type = "passive";
5274 }; 5274 };
5275 }; 5275 };
5276 }; 5276 };
5277 5277
5278 cpu-1-1-1-thermal { 5278 cpu-1-1-1-thermal {
5279 polling-delay-passive 5279 polling-delay-passive = <10>;
5280 5280
5281 thermal-sensors = <&t 5281 thermal-sensors = <&tsens3 2>;
5282 5282
5283 trips { 5283 trips {
5284 trip-point0 { 5284 trip-point0 {
5285 tempe 5285 temperature = <105000>;
5286 hyste 5286 hysteresis = <5000>;
5287 type 5287 type = "passive";
5288 }; 5288 };
5289 5289
5290 trip-point1 { 5290 trip-point1 {
5291 tempe 5291 temperature = <115000>;
5292 hyste 5292 hysteresis = <5000>;
5293 type 5293 type = "passive";
5294 }; 5294 };
5295 }; 5295 };
5296 }; 5296 };
5297 5297
5298 cpu-1-2-1-thermal { 5298 cpu-1-2-1-thermal {
5299 polling-delay-passive 5299 polling-delay-passive = <10>;
5300 5300
5301 thermal-sensors = <&t 5301 thermal-sensors = <&tsens3 3>;
5302 5302
5303 trips { 5303 trips {
5304 trip-point0 { 5304 trip-point0 {
5305 tempe 5305 temperature = <105000>;
5306 hyste 5306 hysteresis = <5000>;
5307 type 5307 type = "passive";
5308 }; 5308 };
5309 5309
5310 trip-point1 { 5310 trip-point1 {
5311 tempe 5311 temperature = <115000>;
5312 hyste 5312 hysteresis = <5000>;
5313 type 5313 type = "passive";
5314 }; 5314 };
5315 }; 5315 };
5316 }; 5316 };
5317 5317
5318 cpu-1-3-1-thermal { 5318 cpu-1-3-1-thermal {
5319 polling-delay-passive 5319 polling-delay-passive = <10>;
5320 5320
5321 thermal-sensors = <&t 5321 thermal-sensors = <&tsens3 4>;
5322 5322
5323 trips { 5323 trips {
5324 trip-point0 { 5324 trip-point0 {
5325 tempe 5325 temperature = <105000>;
5326 hyste 5326 hysteresis = <5000>;
5327 type 5327 type = "passive";
5328 }; 5328 };
5329 5329
5330 trip-point1 { 5330 trip-point1 {
5331 tempe 5331 temperature = <115000>;
5332 hyste 5332 hysteresis = <5000>;
5333 type 5333 type = "passive";
5334 }; 5334 };
5335 }; 5335 };
5336 }; 5336 };
5337 5337
5338 nsp-0-0-1-thermal { 5338 nsp-0-0-1-thermal {
5339 polling-delay-passive 5339 polling-delay-passive = <10>;
5340 5340
5341 thermal-sensors = <&t 5341 thermal-sensors = <&tsens3 5>;
5342 5342
5343 trips { 5343 trips {
5344 trip-point0 { 5344 trip-point0 {
5345 tempe 5345 temperature = <105000>;
5346 hyste 5346 hysteresis = <5000>;
5347 type 5347 type = "passive";
5348 }; 5348 };
5349 5349
5350 trip-point1 { 5350 trip-point1 {
5351 tempe 5351 temperature = <115000>;
5352 hyste 5352 hysteresis = <5000>;
5353 type 5353 type = "passive";
5354 }; 5354 };
5355 }; 5355 };
5356 }; 5356 };
5357 5357
5358 nsp-0-1-1-thermal { 5358 nsp-0-1-1-thermal {
5359 polling-delay-passive 5359 polling-delay-passive = <10>;
5360 5360
5361 thermal-sensors = <&t 5361 thermal-sensors = <&tsens3 6>;
5362 5362
5363 trips { 5363 trips {
5364 trip-point0 { 5364 trip-point0 {
5365 tempe 5365 temperature = <105000>;
5366 hyste 5366 hysteresis = <5000>;
5367 type 5367 type = "passive";
5368 }; 5368 };
5369 5369
5370 trip-point1 { 5370 trip-point1 {
5371 tempe 5371 temperature = <115000>;
5372 hyste 5372 hysteresis = <5000>;
5373 type 5373 type = "passive";
5374 }; 5374 };
5375 }; 5375 };
5376 }; 5376 };
5377 5377
5378 nsp-0-2-1-thermal { 5378 nsp-0-2-1-thermal {
5379 polling-delay-passive 5379 polling-delay-passive = <10>;
5380 5380
5381 thermal-sensors = <&t 5381 thermal-sensors = <&tsens3 7>;
5382 5382
5383 trips { 5383 trips {
5384 trip-point0 { 5384 trip-point0 {
5385 tempe 5385 temperature = <105000>;
5386 hyste 5386 hysteresis = <5000>;
5387 type 5387 type = "passive";
5388 }; 5388 };
5389 5389
5390 trip-point1 { 5390 trip-point1 {
5391 tempe 5391 temperature = <115000>;
5392 hyste 5392 hysteresis = <5000>;
5393 type 5393 type = "passive";
5394 }; 5394 };
5395 }; 5395 };
5396 }; 5396 };
5397 5397
5398 nsp-1-0-1-thermal { 5398 nsp-1-0-1-thermal {
5399 polling-delay-passive 5399 polling-delay-passive = <10>;
5400 5400
5401 thermal-sensors = <&t 5401 thermal-sensors = <&tsens3 8>;
5402 5402
5403 trips { 5403 trips {
5404 trip-point0 { 5404 trip-point0 {
5405 tempe 5405 temperature = <105000>;
5406 hyste 5406 hysteresis = <5000>;
5407 type 5407 type = "passive";
5408 }; 5408 };
5409 5409
5410 trip-point1 { 5410 trip-point1 {
5411 tempe 5411 temperature = <115000>;
5412 hyste 5412 hysteresis = <5000>;
5413 type 5413 type = "passive";
5414 }; 5414 };
5415 }; 5415 };
5416 }; 5416 };
5417 5417
5418 nsp-1-1-1-thermal { 5418 nsp-1-1-1-thermal {
5419 polling-delay-passive 5419 polling-delay-passive = <10>;
5420 5420
5421 thermal-sensors = <&t 5421 thermal-sensors = <&tsens3 9>;
5422 5422
5423 trips { 5423 trips {
5424 trip-point0 { 5424 trip-point0 {
5425 tempe 5425 temperature = <105000>;
5426 hyste 5426 hysteresis = <5000>;
5427 type 5427 type = "passive";
5428 }; 5428 };
5429 5429
5430 trip-point1 { 5430 trip-point1 {
5431 tempe 5431 temperature = <115000>;
5432 hyste 5432 hysteresis = <5000>;
5433 type 5433 type = "passive";
5434 }; 5434 };
5435 }; 5435 };
5436 }; 5436 };
5437 5437
5438 nsp-1-2-1-thermal { 5438 nsp-1-2-1-thermal {
5439 polling-delay-passive 5439 polling-delay-passive = <10>;
5440 5440
5441 thermal-sensors = <&t 5441 thermal-sensors = <&tsens3 10>;
5442 5442
5443 trips { 5443 trips {
5444 trip-point0 { 5444 trip-point0 {
5445 tempe 5445 temperature = <105000>;
5446 hyste 5446 hysteresis = <5000>;
5447 type 5447 type = "passive";
5448 }; 5448 };
5449 5449
5450 trip-point1 { 5450 trip-point1 {
5451 tempe 5451 temperature = <115000>;
5452 hyste 5452 hysteresis = <5000>;
5453 type 5453 type = "passive";
5454 }; 5454 };
5455 }; 5455 };
5456 }; 5456 };
5457 5457
5458 ddrss-1-thermal { 5458 ddrss-1-thermal {
5459 thermal-sensors = <&t 5459 thermal-sensors = <&tsens3 11>;
5460 5460
5461 trips { 5461 trips {
5462 trip-point0 { 5462 trip-point0 {
5463 tempe 5463 temperature = <105000>;
5464 hyste 5464 hysteresis = <5000>;
5465 type 5465 type = "passive";
5466 }; 5466 };
5467 5467
5468 trip-point1 { 5468 trip-point1 {
5469 tempe 5469 temperature = <115000>;
5470 hyste 5470 hysteresis = <5000>;
5471 type 5471 type = "passive";
5472 }; 5472 };
5473 }; 5473 };
5474 }; 5474 };
5475 5475
5476 cpuss-1-1-thermal { 5476 cpuss-1-1-thermal {
5477 thermal-sensors = <&t 5477 thermal-sensors = <&tsens3 12>;
5478 5478
5479 trips { 5479 trips {
5480 trip-point0 { 5480 trip-point0 {
5481 tempe 5481 temperature = <105000>;
5482 hyste 5482 hysteresis = <5000>;
5483 type 5483 type = "passive";
5484 }; 5484 };
5485 5485
5486 trip-point1 { 5486 trip-point1 {
5487 tempe 5487 temperature = <115000>;
5488 hyste 5488 hysteresis = <5000>;
5489 type 5489 type = "passive";
5490 }; 5490 };
5491 }; 5491 };
5492 }; 5492 };
5493 }; 5493 };
5494 5494
5495 arch_timer: timer { 5495 arch_timer: timer {
5496 compatible = "arm,armv8-timer 5496 compatible = "arm,armv8-timer";
5497 interrupts = <GIC_PPI 13 (GIC 5497 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5498 <GIC_PPI 14 (GIC 5498 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5499 <GIC_PPI 11 (GIC 5499 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5500 <GIC_PPI 10 (GIC 5500 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
5501 }; 5501 };
5502 5502
5503 pcie0: pcie@1c00000 { 5503 pcie0: pcie@1c00000 {
5504 compatible = "qcom,pcie-sa877 5504 compatible = "qcom,pcie-sa8775p";
5505 reg = <0x0 0x01c00000 0x0 0x3 5505 reg = <0x0 0x01c00000 0x0 0x3000>,
5506 <0x0 0x40000000 0x0 0xf 5506 <0x0 0x40000000 0x0 0xf20>,
5507 <0x0 0x40000f20 0x0 0xa 5507 <0x0 0x40000f20 0x0 0xa8>,
5508 <0x0 0x40001000 0x0 0x4 5508 <0x0 0x40001000 0x0 0x4000>,
5509 <0x0 0x40100000 0x0 0x1 5509 <0x0 0x40100000 0x0 0x100000>,
5510 <0x0 0x01c03000 0x0 0x1 5510 <0x0 0x01c03000 0x0 0x1000>;
5511 reg-names = "parf", "dbi", "e 5511 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
5512 device_type = "pci"; 5512 device_type = "pci";
5513 5513
5514 #address-cells = <3>; 5514 #address-cells = <3>;
5515 #size-cells = <2>; 5515 #size-cells = <2>;
5516 ranges = <0x01000000 0x0 0x00 5516 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
5517 <0x02000000 0x0 0x40 5517 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
5518 bus-range = <0x00 0xff>; 5518 bus-range = <0x00 0xff>;
5519 5519
5520 dma-coherent; 5520 dma-coherent;
5521 5521
5522 linux,pci-domain = <0>; 5522 linux,pci-domain = <0>;
5523 num-lanes = <2>; 5523 num-lanes = <2>;
5524 5524
5525 interrupts = <GIC_SPI 307 IRQ 5525 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
5526 <GIC_SPI 308 IRQ 5526 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
5527 <GIC_SPI 309 IRQ 5527 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
5528 <GIC_SPI 312 IRQ 5528 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
5529 <GIC_SPI 313 IRQ 5529 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
5530 <GIC_SPI 314 IRQ 5530 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
5531 <GIC_SPI 374 IRQ 5531 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
5532 <GIC_SPI 375 IRQ 5532 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
5533 interrupt-names = "msi0", "ms 5533 interrupt-names = "msi0", "msi1", "msi2", "msi3",
5534 "msi4", "ms 5534 "msi4", "msi5", "msi6", "msi7";
5535 #interrupt-cells = <1>; 5535 #interrupt-cells = <1>;
5536 interrupt-map-mask = <0 0 0 0 5536 interrupt-map-mask = <0 0 0 0x7>;
5537 interrupt-map = <0 0 0 1 &int 5537 interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
5538 <0 0 0 2 &int 5538 <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
5539 <0 0 0 3 &int 5539 <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
5540 <0 0 0 4 &int 5540 <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>;
5541 5541
5542 clocks = <&gcc GCC_PCIE_0_AUX 5542 clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
5543 <&gcc GCC_PCIE_0_CFG 5543 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
5544 <&gcc GCC_PCIE_0_MST 5544 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
5545 <&gcc GCC_PCIE_0_SLV 5545 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
5546 <&gcc GCC_PCIE_0_SLV 5546 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>;
5547 5547
5548 clock-names = "aux", 5548 clock-names = "aux",
5549 "cfg", 5549 "cfg",
5550 "bus_master", 5550 "bus_master",
5551 "bus_slave", 5551 "bus_slave",
5552 "slave_q2a"; 5552 "slave_q2a";
5553 5553
5554 assigned-clocks = <&gcc GCC_P 5554 assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>;
5555 assigned-clock-rates = <19200 5555 assigned-clock-rates = <19200000>;
5556 5556
5557 interconnects = <&pcie_anoc M 5557 interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>,
5558 <&gem_noc MAS 5558 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>;
5559 interconnect-names = "pcie-me 5559 interconnect-names = "pcie-mem", "cpu-pcie";
5560 5560
5561 iommu-map = <0x0 &pcie_smmu 0 5561 iommu-map = <0x0 &pcie_smmu 0x0000 0x1>,
5562 <0x100 &pcie_smmu 5562 <0x100 &pcie_smmu 0x0001 0x1>;
5563 5563
5564 resets = <&gcc GCC_PCIE_0_BCR 5564 resets = <&gcc GCC_PCIE_0_BCR>;
5565 reset-names = "pci"; 5565 reset-names = "pci";
5566 power-domains = <&gcc PCIE_0_ 5566 power-domains = <&gcc PCIE_0_GDSC>;
5567 5567
5568 phys = <&pcie0_phy>; 5568 phys = <&pcie0_phy>;
5569 phy-names = "pciephy"; 5569 phy-names = "pciephy";
5570 5570
5571 status = "disabled"; 5571 status = "disabled";
5572 5572
5573 pcie@0 { 5573 pcie@0 {
5574 device_type = "pci"; 5574 device_type = "pci";
5575 reg = <0x0 0x0 0x0 0x 5575 reg = <0x0 0x0 0x0 0x0 0x0>;
5576 bus-range = <0x01 0xf 5576 bus-range = <0x01 0xff>;
5577 5577
5578 #address-cells = <3>; 5578 #address-cells = <3>;
5579 #size-cells = <2>; 5579 #size-cells = <2>;
5580 ranges; 5580 ranges;
5581 }; 5581 };
5582 }; 5582 };
5583 5583
5584 pcie0_ep: pcie-ep@1c00000 { 5584 pcie0_ep: pcie-ep@1c00000 {
5585 compatible = "qcom,sa8775p-pc 5585 compatible = "qcom,sa8775p-pcie-ep";
5586 reg = <0x0 0x01c00000 0x0 0x3 5586 reg = <0x0 0x01c00000 0x0 0x3000>,
5587 <0x0 0x40000000 0x0 0xf 5587 <0x0 0x40000000 0x0 0xf20>,
5588 <0x0 0x40000f20 0x0 0xa 5588 <0x0 0x40000f20 0x0 0xa8>,
5589 <0x0 0x40001000 0x0 0x4 5589 <0x0 0x40001000 0x0 0x4000>,
5590 <0x0 0x40200000 0x0 0x1 5590 <0x0 0x40200000 0x0 0x100000>,
5591 <0x0 0x01c03000 0x0 0x1 5591 <0x0 0x01c03000 0x0 0x1000>,
5592 <0x0 0x40005000 0x0 0x2 5592 <0x0 0x40005000 0x0 0x2000>;
5593 reg-names = "parf", "dbi", "e 5593 reg-names = "parf", "dbi", "elbi", "atu", "addr_space",
5594 "mmio", "dma"; 5594 "mmio", "dma";
5595 5595
5596 clocks = <&gcc GCC_PCIE_0_AUX 5596 clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
5597 <&gcc GCC_PCIE_0_CFG_ 5597 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
5598 <&gcc GCC_PCIE_0_MSTR 5598 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
5599 <&gcc GCC_PCIE_0_SLV_ 5599 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
5600 <&gcc GCC_PCIE_0_SLV_ 5600 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>;
5601 5601
5602 clock-names = "aux", 5602 clock-names = "aux",
5603 "cfg", 5603 "cfg",
5604 "bus_master", 5604 "bus_master",
5605 "bus_slave", 5605 "bus_slave",
5606 "slave_q2a"; 5606 "slave_q2a";
5607 5607
5608 interrupts = <GIC_SPI 306 IRQ 5608 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
5609 <GIC_SPI 147 IRQ 5609 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
5610 <GIC_SPI 630 IRQ 5610 <GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH>;
5611 5611
5612 interrupt-names = "global", " 5612 interrupt-names = "global", "doorbell", "dma";
5613 5613
5614 interconnects = <&pcie_anoc M 5614 interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>,
5615 <&gem_noc MAS 5615 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>;
5616 interconnect-names = "pcie-me 5616 interconnect-names = "pcie-mem", "cpu-pcie";
5617 5617
5618 dma-coherent; 5618 dma-coherent;
5619 iommus = <&pcie_smmu 0x0000 0 5619 iommus = <&pcie_smmu 0x0000 0x7f>;
5620 resets = <&gcc GCC_PCIE_0_BCR 5620 resets = <&gcc GCC_PCIE_0_BCR>;
5621 reset-names = "core"; 5621 reset-names = "core";
5622 power-domains = <&gcc PCIE_0_ 5622 power-domains = <&gcc PCIE_0_GDSC>;
5623 phys = <&pcie0_phy>; 5623 phys = <&pcie0_phy>;
5624 phy-names = "pciephy"; 5624 phy-names = "pciephy";
5625 max-link-speed = <3>; /* FIXM 5625 max-link-speed = <3>; /* FIXME: Limiting the Gen speed due to stability issues */
5626 num-lanes = <2>; 5626 num-lanes = <2>;
5627 5627
5628 status = "disabled"; 5628 status = "disabled";
5629 }; 5629 };
5630 5630
5631 pcie0_phy: phy@1c04000 { 5631 pcie0_phy: phy@1c04000 {
5632 compatible = "qcom,sa8775p-qm 5632 compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy";
5633 reg = <0x0 0x1c04000 0x0 0x20 5633 reg = <0x0 0x1c04000 0x0 0x2000>;
5634 5634
5635 clocks = <&gcc GCC_PCIE_0_AUX 5635 clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
5636 <&gcc GCC_PCIE_0_CFG 5636 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
5637 <&gcc GCC_PCIE_CLKRE 5637 <&gcc GCC_PCIE_CLKREF_EN>,
5638 <&gcc GCC_PCIE_0_PHY 5638 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
5639 <&gcc GCC_PCIE_0_PIP 5639 <&gcc GCC_PCIE_0_PIPE_CLK>,
5640 <&gcc GCC_PCIE_0_PIP 5640 <&gcc GCC_PCIE_0_PIPEDIV2_CLK>,
5641 <&gcc GCC_PCIE_0_PHY 5641 <&gcc GCC_PCIE_0_PHY_AUX_CLK>;
5642 5642
5643 clock-names = "aux", "cfg_ahb 5643 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe",
5644 "pipediv2", "ph 5644 "pipediv2", "phy_aux";
5645 5645
5646 assigned-clocks = <&gcc GCC_P 5646 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
5647 assigned-clock-rates = <10000 5647 assigned-clock-rates = <100000000>;
5648 5648
5649 resets = <&gcc GCC_PCIE_0_PHY 5649 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
5650 reset-names = "phy"; 5650 reset-names = "phy";
5651 5651
5652 #clock-cells = <0>; 5652 #clock-cells = <0>;
5653 clock-output-names = "pcie_0_ 5653 clock-output-names = "pcie_0_pipe_clk";
5654 5654
5655 #phy-cells = <0>; 5655 #phy-cells = <0>;
5656 5656
5657 status = "disabled"; 5657 status = "disabled";
5658 }; 5658 };
5659 5659
5660 pcie1: pcie@1c10000 { 5660 pcie1: pcie@1c10000 {
5661 compatible = "qcom,pcie-sa877 5661 compatible = "qcom,pcie-sa8775p";
5662 reg = <0x0 0x01c10000 0x0 0x3 5662 reg = <0x0 0x01c10000 0x0 0x3000>,
5663 <0x0 0x60000000 0x0 0xf 5663 <0x0 0x60000000 0x0 0xf20>,
5664 <0x0 0x60000f20 0x0 0xa 5664 <0x0 0x60000f20 0x0 0xa8>,
5665 <0x0 0x60001000 0x0 0x4 5665 <0x0 0x60001000 0x0 0x4000>,
5666 <0x0 0x60100000 0x0 0x1 5666 <0x0 0x60100000 0x0 0x100000>,
5667 <0x0 0x01c13000 0x0 0x1 5667 <0x0 0x01c13000 0x0 0x1000>;
5668 reg-names = "parf", "dbi", "e 5668 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
5669 device_type = "pci"; 5669 device_type = "pci";
5670 5670
5671 #address-cells = <3>; 5671 #address-cells = <3>;
5672 #size-cells = <2>; 5672 #size-cells = <2>;
5673 ranges = <0x01000000 0x0 0x00 5673 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
5674 <0x02000000 0x0 0x60 5674 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x1fd00000>;
5675 bus-range = <0x00 0xff>; 5675 bus-range = <0x00 0xff>;
5676 5676
5677 dma-coherent; 5677 dma-coherent;
5678 5678
5679 linux,pci-domain = <1>; 5679 linux,pci-domain = <1>;
5680 num-lanes = <4>; 5680 num-lanes = <4>;
5681 5681
5682 interrupts = <GIC_SPI 519 IRQ 5682 interrupts = <GIC_SPI 519 IRQ_TYPE_LEVEL_HIGH>,
5683 <GIC_SPI 140 IRQ 5683 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
5684 <GIC_SPI 141 IRQ 5684 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
5685 <GIC_SPI 142 IRQ 5685 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
5686 <GIC_SPI 143 IRQ 5686 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
5687 <GIC_SPI 144 IRQ 5687 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
5688 <GIC_SPI 145 IRQ 5688 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
5689 <GIC_SPI 146 IRQ 5689 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
5690 interrupt-names = "msi0", "ms 5690 interrupt-names = "msi0", "msi1", "msi2", "msi3",
5691 "msi4", "ms 5691 "msi4", "msi5", "msi6", "msi7";
5692 #interrupt-cells = <1>; 5692 #interrupt-cells = <1>;
5693 interrupt-map-mask = <0 0 0 0 5693 interrupt-map-mask = <0 0 0 0x7>;
5694 interrupt-map = <0 0 0 1 &int 5694 interrupt-map = <0 0 0 1 &intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
5695 <0 0 0 2 &int 5695 <0 0 0 2 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
5696 <0 0 0 3 &int 5696 <0 0 0 3 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
5697 <0 0 0 4 &int 5697 <0 0 0 4 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
5698 5698
5699 clocks = <&gcc GCC_PCIE_1_AUX 5699 clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
5700 <&gcc GCC_PCIE_1_CFG 5700 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
5701 <&gcc GCC_PCIE_1_MST 5701 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
5702 <&gcc GCC_PCIE_1_SLV 5702 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
5703 <&gcc GCC_PCIE_1_SLV 5703 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>;
5704 5704
5705 clock-names = "aux", 5705 clock-names = "aux",
5706 "cfg", 5706 "cfg",
5707 "bus_master", 5707 "bus_master",
5708 "bus_slave", 5708 "bus_slave",
5709 "slave_q2a"; 5709 "slave_q2a";
5710 5710
5711 assigned-clocks = <&gcc GCC_P 5711 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
5712 assigned-clock-rates = <19200 5712 assigned-clock-rates = <19200000>;
5713 5713
5714 interconnects = <&pcie_anoc M 5714 interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>,
5715 <&gem_noc MAS 5715 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>;
5716 interconnect-names = "pcie-me 5716 interconnect-names = "pcie-mem", "cpu-pcie";
5717 5717
5718 iommu-map = <0x0 &pcie_smmu 0 5718 iommu-map = <0x0 &pcie_smmu 0x0080 0x1>,
5719 <0x100 &pcie_smmu 5719 <0x100 &pcie_smmu 0x0081 0x1>;
5720 5720
5721 resets = <&gcc GCC_PCIE_1_BCR 5721 resets = <&gcc GCC_PCIE_1_BCR>;
5722 reset-names = "pci"; 5722 reset-names = "pci";
5723 power-domains = <&gcc PCIE_1_ 5723 power-domains = <&gcc PCIE_1_GDSC>;
5724 5724
5725 phys = <&pcie1_phy>; 5725 phys = <&pcie1_phy>;
5726 phy-names = "pciephy"; 5726 phy-names = "pciephy";
5727 5727
5728 status = "disabled"; 5728 status = "disabled";
5729 5729
5730 pcie@0 { 5730 pcie@0 {
5731 device_type = "pci"; 5731 device_type = "pci";
5732 reg = <0x0 0x0 0x0 0x 5732 reg = <0x0 0x0 0x0 0x0 0x0>;
5733 bus-range = <0x01 0xf 5733 bus-range = <0x01 0xff>;
5734 5734
5735 #address-cells = <3>; 5735 #address-cells = <3>;
5736 #size-cells = <2>; 5736 #size-cells = <2>;
5737 ranges; 5737 ranges;
5738 }; 5738 };
5739 }; 5739 };
5740 5740
5741 pcie1_ep: pcie-ep@1c10000 { 5741 pcie1_ep: pcie-ep@1c10000 {
5742 compatible = "qcom,sa8775p-pc 5742 compatible = "qcom,sa8775p-pcie-ep";
5743 reg = <0x0 0x01c10000 0x0 0x3 5743 reg = <0x0 0x01c10000 0x0 0x3000>,
5744 <0x0 0x60000000 0x0 0xf 5744 <0x0 0x60000000 0x0 0xf20>,
5745 <0x0 0x60000f20 0x0 0xa 5745 <0x0 0x60000f20 0x0 0xa8>,
5746 <0x0 0x60001000 0x0 0x4 5746 <0x0 0x60001000 0x0 0x4000>,
5747 <0x0 0x60200000 0x0 0x1 5747 <0x0 0x60200000 0x0 0x100000>,
5748 <0x0 0x01c13000 0x0 0x1 5748 <0x0 0x01c13000 0x0 0x1000>,
5749 <0x0 0x60005000 0x0 0x2 5749 <0x0 0x60005000 0x0 0x2000>;
5750 reg-names = "parf", "dbi", "e 5750 reg-names = "parf", "dbi", "elbi", "atu", "addr_space",
5751 "mmio", "dma"; 5751 "mmio", "dma";
5752 5752
5753 clocks = <&gcc GCC_PCIE_1_AUX 5753 clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
5754 <&gcc GCC_PCIE_1_CFG 5754 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
5755 <&gcc GCC_PCIE_1_MST 5755 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
5756 <&gcc GCC_PCIE_1_SLV 5756 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
5757 <&gcc GCC_PCIE_1_SLV 5757 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>;
5758 5758
5759 clock-names = "aux", 5759 clock-names = "aux",
5760 "cfg", 5760 "cfg",
5761 "bus_master", 5761 "bus_master",
5762 "bus_slave", 5762 "bus_slave",
5763 "slave_q2a"; 5763 "slave_q2a";
5764 5764
5765 interrupts = <GIC_SPI 518 IRQ 5765 interrupts = <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>,
5766 <GIC_SPI 152 IRQ 5766 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
5767 <GIC_SPI 474 IRQ 5767 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
5768 5768
5769 interrupt-names = "global", " 5769 interrupt-names = "global", "doorbell", "dma";
5770 5770
5771 interconnects = <&pcie_anoc M 5771 interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>,
5772 <&gem_noc MAS 5772 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>;
5773 interconnect-names = "pcie-me 5773 interconnect-names = "pcie-mem", "cpu-pcie";
5774 5774
5775 dma-coherent; 5775 dma-coherent;
5776 iommus = <&pcie_smmu 0x80 0x7 5776 iommus = <&pcie_smmu 0x80 0x7f>;
5777 resets = <&gcc GCC_PCIE_1_BCR 5777 resets = <&gcc GCC_PCIE_1_BCR>;
5778 reset-names = "core"; 5778 reset-names = "core";
5779 power-domains = <&gcc PCIE_1_ 5779 power-domains = <&gcc PCIE_1_GDSC>;
5780 phys = <&pcie1_phy>; 5780 phys = <&pcie1_phy>;
5781 phy-names = "pciephy"; 5781 phy-names = "pciephy";
5782 max-link-speed = <3>; /* FIXM 5782 max-link-speed = <3>; /* FIXME: Limiting the Gen speed due to stability issues */
5783 num-lanes = <4>; 5783 num-lanes = <4>;
5784 5784
5785 status = "disabled"; 5785 status = "disabled";
5786 }; 5786 };
5787 5787
5788 pcie1_phy: phy@1c14000 { 5788 pcie1_phy: phy@1c14000 {
5789 compatible = "qcom,sa8775p-qm 5789 compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy";
5790 reg = <0x0 0x1c14000 0x0 0x40 5790 reg = <0x0 0x1c14000 0x0 0x4000>;
5791 5791
5792 clocks = <&gcc GCC_PCIE_1_AUX 5792 clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
5793 <&gcc GCC_PCIE_1_CFG 5793 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
5794 <&gcc GCC_PCIE_CLKRE 5794 <&gcc GCC_PCIE_CLKREF_EN>,
5795 <&gcc GCC_PCIE_1_PHY 5795 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
5796 <&gcc GCC_PCIE_1_PIP 5796 <&gcc GCC_PCIE_1_PIPE_CLK>,
5797 <&gcc GCC_PCIE_1_PIP 5797 <&gcc GCC_PCIE_1_PIPEDIV2_CLK>,
5798 <&gcc GCC_PCIE_1_PHY 5798 <&gcc GCC_PCIE_1_PHY_AUX_CLK>;
5799 5799
5800 clock-names = "aux", "cfg_ahb 5800 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe",
5801 "pipediv2", "ph 5801 "pipediv2", "phy_aux";
5802 5802
5803 assigned-clocks = <&gcc GCC_P 5803 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
5804 assigned-clock-rates = <10000 5804 assigned-clock-rates = <100000000>;
5805 5805
5806 resets = <&gcc GCC_PCIE_1_PHY 5806 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
5807 reset-names = "phy"; 5807 reset-names = "phy";
5808 5808
5809 #clock-cells = <0>; 5809 #clock-cells = <0>;
5810 clock-output-names = "pcie_1_ 5810 clock-output-names = "pcie_1_pipe_clk";
5811 5811
5812 #phy-cells = <0>; 5812 #phy-cells = <0>;
5813 5813
5814 status = "disabled"; 5814 status = "disabled";
5815 }; 5815 };
5816 }; 5816 };
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