1 // SPDX-License-Identifier: BSD-3-Clause
2 /*
3 * SC7180 SoC device tree source
4 *
5 * Copyright (c) 2019-2020, The Linux Foundati
6 */
7
8 #include <dt-bindings/clock/qcom,dispcc-sc7180
9 #include <dt-bindings/clock/qcom,gcc-sc7180.h>
10 #include <dt-bindings/clock/qcom,gpucc-sc7180.
11 #include <dt-bindings/clock/qcom,lpasscorecc-s
12 #include <dt-bindings/clock/qcom,rpmh.h>
13 #include <dt-bindings/clock/qcom,videocc-sc718
14 #include <dt-bindings/firmware/qcom,scm.h>
15 #include <dt-bindings/interconnect/qcom,icc.h>
16 #include <dt-bindings/interconnect/qcom,osm-l3
17 #include <dt-bindings/interconnect/qcom,sc7180
18 #include <dt-bindings/interrupt-controller/arm
19 #include <dt-bindings/phy/phy-qcom-qmp.h>
20 #include <dt-bindings/phy/phy-qcom-qusb2.h>
21 #include <dt-bindings/power/qcom-rpmpd.h>
22 #include <dt-bindings/reset/qcom,sdm845-aoss.h
23 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
24 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
25 #include <dt-bindings/soc/qcom,apr.h>
26 #include <dt-bindings/sound/qcom,q6afe.h>
27 #include <dt-bindings/thermal/thermal.h>
28
29 / {
30 interrupt-parent = <&intc>;
31
32 #address-cells = <2>;
33 #size-cells = <2>;
34
35 aliases {
36 mmc1 = &sdhc_1;
37 mmc2 = &sdhc_2;
38 i2c0 = &i2c0;
39 i2c1 = &i2c1;
40 i2c2 = &i2c2;
41 i2c3 = &i2c3;
42 i2c4 = &i2c4;
43 i2c5 = &i2c5;
44 i2c6 = &i2c6;
45 i2c7 = &i2c7;
46 i2c8 = &i2c8;
47 i2c9 = &i2c9;
48 i2c10 = &i2c10;
49 i2c11 = &i2c11;
50 spi0 = &spi0;
51 spi1 = &spi1;
52 spi3 = &spi3;
53 spi5 = &spi5;
54 spi6 = &spi6;
55 spi8 = &spi8;
56 spi10 = &spi10;
57 spi11 = &spi11;
58 };
59
60 chosen { };
61
62 clocks {
63 xo_board: xo-board {
64 compatible = "fixed-cl
65 clock-frequency = <384
66 #clock-cells = <0>;
67 };
68
69 sleep_clk: sleep-clk {
70 compatible = "fixed-cl
71 clock-frequency = <327
72 #clock-cells = <0>;
73 };
74 };
75
76 cpus {
77 #address-cells = <2>;
78 #size-cells = <0>;
79
80 CPU0: cpu@0 {
81 device_type = "cpu";
82 compatible = "qcom,kry
83 reg = <0x0 0x0>;
84 clocks = <&cpufreq_hw
85 enable-method = "psci"
86 power-domains = <&CPU_
87 power-domain-names = "
88 capacity-dmips-mhz = <
89 dynamic-power-coeffici
90 operating-points-v2 =
91 interconnects = <&gem_
92 <&osm_
93 next-level-cache = <&L
94 #cooling-cells = <2>;
95 qcom,freq-domain = <&c
96 L2_0: l2-cache {
97 compatible = "
98 cache-level =
99 cache-unified;
100 next-level-cac
101 L3_0: l3-cache
102 compat
103 cache-
104 cache-
105 };
106 };
107 };
108
109 CPU1: cpu@100 {
110 device_type = "cpu";
111 compatible = "qcom,kry
112 reg = <0x0 0x100>;
113 clocks = <&cpufreq_hw
114 enable-method = "psci"
115 power-domains = <&CPU_
116 power-domain-names = "
117 capacity-dmips-mhz = <
118 dynamic-power-coeffici
119 next-level-cache = <&L
120 operating-points-v2 =
121 interconnects = <&gem_
122 <&osm_
123 #cooling-cells = <2>;
124 qcom,freq-domain = <&c
125 L2_100: l2-cache {
126 compatible = "
127 cache-level =
128 cache-unified;
129 next-level-cac
130 };
131 };
132
133 CPU2: cpu@200 {
134 device_type = "cpu";
135 compatible = "qcom,kry
136 reg = <0x0 0x200>;
137 clocks = <&cpufreq_hw
138 enable-method = "psci"
139 power-domains = <&CPU_
140 power-domain-names = "
141 capacity-dmips-mhz = <
142 dynamic-power-coeffici
143 next-level-cache = <&L
144 operating-points-v2 =
145 interconnects = <&gem_
146 <&osm_
147 #cooling-cells = <2>;
148 qcom,freq-domain = <&c
149 L2_200: l2-cache {
150 compatible = "
151 cache-level =
152 cache-unified;
153 next-level-cac
154 };
155 };
156
157 CPU3: cpu@300 {
158 device_type = "cpu";
159 compatible = "qcom,kry
160 reg = <0x0 0x300>;
161 clocks = <&cpufreq_hw
162 enable-method = "psci"
163 power-domains = <&CPU_
164 power-domain-names = "
165 capacity-dmips-mhz = <
166 dynamic-power-coeffici
167 next-level-cache = <&L
168 operating-points-v2 =
169 interconnects = <&gem_
170 <&osm_
171 #cooling-cells = <2>;
172 qcom,freq-domain = <&c
173 L2_300: l2-cache {
174 compatible = "
175 cache-level =
176 cache-unified;
177 next-level-cac
178 };
179 };
180
181 CPU4: cpu@400 {
182 device_type = "cpu";
183 compatible = "qcom,kry
184 reg = <0x0 0x400>;
185 clocks = <&cpufreq_hw
186 enable-method = "psci"
187 power-domains = <&CPU_
188 power-domain-names = "
189 capacity-dmips-mhz = <
190 dynamic-power-coeffici
191 next-level-cache = <&L
192 operating-points-v2 =
193 interconnects = <&gem_
194 <&osm_
195 #cooling-cells = <2>;
196 qcom,freq-domain = <&c
197 L2_400: l2-cache {
198 compatible = "
199 cache-level =
200 cache-unified;
201 next-level-cac
202 };
203 };
204
205 CPU5: cpu@500 {
206 device_type = "cpu";
207 compatible = "qcom,kry
208 reg = <0x0 0x500>;
209 clocks = <&cpufreq_hw
210 enable-method = "psci"
211 power-domains = <&CPU_
212 power-domain-names = "
213 capacity-dmips-mhz = <
214 dynamic-power-coeffici
215 next-level-cache = <&L
216 operating-points-v2 =
217 interconnects = <&gem_
218 <&osm_
219 #cooling-cells = <2>;
220 qcom,freq-domain = <&c
221 L2_500: l2-cache {
222 compatible = "
223 cache-level =
224 cache-unified;
225 next-level-cac
226 };
227 };
228
229 CPU6: cpu@600 {
230 device_type = "cpu";
231 compatible = "qcom,kry
232 reg = <0x0 0x600>;
233 clocks = <&cpufreq_hw
234 enable-method = "psci"
235 power-domains = <&CPU_
236 power-domain-names = "
237 capacity-dmips-mhz = <
238 dynamic-power-coeffici
239 next-level-cache = <&L
240 operating-points-v2 =
241 interconnects = <&gem_
242 <&osm_
243 #cooling-cells = <2>;
244 qcom,freq-domain = <&c
245 L2_600: l2-cache {
246 compatible = "
247 cache-level =
248 cache-unified;
249 next-level-cac
250 };
251 };
252
253 CPU7: cpu@700 {
254 device_type = "cpu";
255 compatible = "qcom,kry
256 reg = <0x0 0x700>;
257 clocks = <&cpufreq_hw
258 enable-method = "psci"
259 power-domains = <&CPU_
260 power-domain-names = "
261 capacity-dmips-mhz = <
262 dynamic-power-coeffici
263 next-level-cache = <&L
264 operating-points-v2 =
265 interconnects = <&gem_
266 <&osm_
267 #cooling-cells = <2>;
268 qcom,freq-domain = <&c
269 L2_700: l2-cache {
270 compatible = "
271 cache-level =
272 cache-unified;
273 next-level-cac
274 };
275 };
276
277 cpu-map {
278 cluster0 {
279 core0 {
280 cpu =
281 };
282
283 core1 {
284 cpu =
285 };
286
287 core2 {
288 cpu =
289 };
290
291 core3 {
292 cpu =
293 };
294
295 core4 {
296 cpu =
297 };
298
299 core5 {
300 cpu =
301 };
302
303 core6 {
304 cpu =
305 };
306
307 core7 {
308 cpu =
309 };
310 };
311 };
312
313 idle_states: idle-states {
314 entry-method = "psci";
315
316 LITTLE_CPU_SLEEP_0: cp
317 compatible = "
318 idle-state-nam
319 arm,psci-suspe
320 entry-latency-
321 exit-latency-u
322 min-residency-
323 local-timer-st
324 };
325
326 LITTLE_CPU_SLEEP_1: cp
327 compatible = "
328 idle-state-nam
329 arm,psci-suspe
330 entry-latency-
331 exit-latency-u
332 min-residency-
333 local-timer-st
334 };
335
336 BIG_CPU_SLEEP_0: cpu-s
337 compatible = "
338 idle-state-nam
339 arm,psci-suspe
340 entry-latency-
341 exit-latency-u
342 min-residency-
343 local-timer-st
344 };
345
346 BIG_CPU_SLEEP_1: cpu-s
347 compatible = "
348 idle-state-nam
349 arm,psci-suspe
350 entry-latency-
351 exit-latency-u
352 min-residency-
353 local-timer-st
354 };
355 };
356
357 domain_idle_states: domain-idl
358 CLUSTER_SLEEP_PC: clus
359 compatible = "
360 idle-state-nam
361 arm,psci-suspe
362 entry-latency-
363 exit-latency-u
364 min-residency-
365 };
366
367 CLUSTER_SLEEP_CX_RET:
368 compatible = "
369 idle-state-nam
370 arm,psci-suspe
371 entry-latency-
372 exit-latency-u
373 min-residency-
374 };
375
376 CLUSTER_AOSS_SLEEP: cl
377 compatible = "
378 idle-state-nam
379 arm,psci-suspe
380 entry-latency-
381 exit-latency-u
382 min-residency-
383 };
384 };
385 };
386
387 firmware {
388 scm: scm {
389 compatible = "qcom,scm
390 };
391 };
392
393 memory@80000000 {
394 device_type = "memory";
395 /* We expect the bootloader to
396 reg = <0 0x80000000 0 0>;
397 };
398
399 cpu0_opp_table: opp-table-cpu0 {
400 compatible = "operating-points
401 opp-shared;
402
403 cpu0_opp1: opp-300000000 {
404 opp-hz = /bits/ 64 <30
405 opp-peak-kBps = <12000
406 };
407
408 cpu0_opp2: opp-576000000 {
409 opp-hz = /bits/ 64 <57
410 opp-peak-kBps = <12000
411 };
412
413 cpu0_opp3: opp-768000000 {
414 opp-hz = /bits/ 64 <76
415 opp-peak-kBps = <12000
416 };
417
418 cpu0_opp4: opp-1017600000 {
419 opp-hz = /bits/ 64 <10
420 opp-peak-kBps = <18040
421 };
422
423 cpu0_opp5: opp-1248000000 {
424 opp-hz = /bits/ 64 <12
425 opp-peak-kBps = <21880
426 };
427
428 cpu0_opp6: opp-1324800000 {
429 opp-hz = /bits/ 64 <13
430 opp-peak-kBps = <21880
431 };
432
433 cpu0_opp7: opp-1516800000 {
434 opp-hz = /bits/ 64 <15
435 opp-peak-kBps = <30720
436 };
437
438 cpu0_opp8: opp-1612800000 {
439 opp-hz = /bits/ 64 <16
440 opp-peak-kBps = <30720
441 };
442
443 cpu0_opp9: opp-1708800000 {
444 opp-hz = /bits/ 64 <17
445 opp-peak-kBps = <30720
446 };
447
448 cpu0_opp10: opp-1804800000 {
449 opp-hz = /bits/ 64 <18
450 opp-peak-kBps = <40680
451 };
452 };
453
454 cpu6_opp_table: opp-table-cpu6 {
455 compatible = "operating-points
456 opp-shared;
457
458 cpu6_opp1: opp-300000000 {
459 opp-hz = /bits/ 64 <30
460 opp-peak-kBps = <21880
461 };
462
463 cpu6_opp2: opp-652800000 {
464 opp-hz = /bits/ 64 <65
465 opp-peak-kBps = <21880
466 };
467
468 cpu6_opp3: opp-825600000 {
469 opp-hz = /bits/ 64 <82
470 opp-peak-kBps = <21880
471 };
472
473 cpu6_opp4: opp-979200000 {
474 opp-hz = /bits/ 64 <97
475 opp-peak-kBps = <21880
476 };
477
478 cpu6_opp5: opp-1113600000 {
479 opp-hz = /bits/ 64 <11
480 opp-peak-kBps = <21880
481 };
482
483 cpu6_opp6: opp-1267200000 {
484 opp-hz = /bits/ 64 <12
485 opp-peak-kBps = <40680
486 };
487
488 cpu6_opp7: opp-1555200000 {
489 opp-hz = /bits/ 64 <15
490 opp-peak-kBps = <40680
491 };
492
493 cpu6_opp8: opp-1708800000 {
494 opp-hz = /bits/ 64 <17
495 opp-peak-kBps = <62200
496 };
497
498 cpu6_opp9: opp-1843200000 {
499 opp-hz = /bits/ 64 <18
500 opp-peak-kBps = <62200
501 };
502
503 cpu6_opp10: opp-1900800000 {
504 opp-hz = /bits/ 64 <19
505 opp-peak-kBps = <62200
506 };
507
508 cpu6_opp11: opp-1996800000 {
509 opp-hz = /bits/ 64 <19
510 opp-peak-kBps = <62200
511 };
512
513 cpu6_opp12: opp-2112000000 {
514 opp-hz = /bits/ 64 <21
515 opp-peak-kBps = <62200
516 };
517
518 cpu6_opp13: opp-2208000000 {
519 opp-hz = /bits/ 64 <22
520 opp-peak-kBps = <72160
521 };
522
523 cpu6_opp14: opp-2323200000 {
524 opp-hz = /bits/ 64 <23
525 opp-peak-kBps = <72160
526 };
527
528 cpu6_opp15: opp-2400000000 {
529 opp-hz = /bits/ 64 <24
530 opp-peak-kBps = <85320
531 };
532
533 cpu6_opp16: opp-2553600000 {
534 opp-hz = /bits/ 64 <25
535 opp-peak-kBps = <85320
536 };
537 };
538
539 qspi_opp_table: opp-table-qspi {
540 compatible = "operating-points
541
542 opp-75000000 {
543 opp-hz = /bits/ 64 <75
544 required-opps = <&rpmh
545 };
546
547 opp-150000000 {
548 opp-hz = /bits/ 64 <15
549 required-opps = <&rpmh
550 };
551
552 opp-300000000 {
553 opp-hz = /bits/ 64 <30
554 required-opps = <&rpmh
555 };
556 };
557
558 qup_opp_table: opp-table-qup {
559 compatible = "operating-points
560
561 opp-75000000 {
562 opp-hz = /bits/ 64 <75
563 required-opps = <&rpmh
564 };
565
566 opp-100000000 {
567 opp-hz = /bits/ 64 <10
568 required-opps = <&rpmh
569 };
570
571 opp-128000000 {
572 opp-hz = /bits/ 64 <12
573 required-opps = <&rpmh
574 };
575 };
576
577 pmu {
578 compatible = "arm,armv8-pmuv3"
579 interrupts = <GIC_PPI 5 IRQ_TY
580 };
581
582 psci {
583 compatible = "arm,psci-1.0";
584 method = "smc";
585
586 CPU_PD0: cpu0 {
587 #power-domain-cells =
588 power-domains = <&CLUS
589 domain-idle-states = <
590 };
591
592 CPU_PD1: cpu1 {
593 #power-domain-cells =
594 power-domains = <&CLUS
595 domain-idle-states = <
596 };
597
598 CPU_PD2: cpu2 {
599 #power-domain-cells =
600 power-domains = <&CLUS
601 domain-idle-states = <
602 };
603
604 CPU_PD3: cpu3 {
605 #power-domain-cells =
606 power-domains = <&CLUS
607 domain-idle-states = <
608 };
609
610 CPU_PD4: cpu4 {
611 #power-domain-cells =
612 power-domains = <&CLUS
613 domain-idle-states = <
614 };
615
616 CPU_PD5: cpu5 {
617 #power-domain-cells =
618 power-domains = <&CLUS
619 domain-idle-states = <
620 };
621
622 CPU_PD6: cpu6 {
623 #power-domain-cells =
624 power-domains = <&CLUS
625 domain-idle-states = <
626 };
627
628 CPU_PD7: cpu7 {
629 #power-domain-cells =
630 power-domains = <&CLUS
631 domain-idle-states = <
632 };
633
634 CLUSTER_PD: cpu-cluster0 {
635 #power-domain-cells =
636 domain-idle-states = <
637
638
639 };
640 };
641
642 reserved_memory: reserved-memory {
643 #address-cells = <2>;
644 #size-cells = <2>;
645 ranges;
646
647 hyp_mem: memory@80000000 {
648 reg = <0x0 0x80000000
649 no-map;
650 };
651
652 xbl_mem: memory@80600000 {
653 reg = <0x0 0x80600000
654 no-map;
655 };
656
657 aop_mem: memory@80800000 {
658 reg = <0x0 0x80800000
659 no-map;
660 };
661
662 aop_cmd_db_mem: memory@8082000
663 reg = <0x0 0x80820000
664 compatible = "qcom,cmd
665 no-map;
666 };
667
668 sec_apps_mem: memory@808ff000
669 reg = <0x0 0x808ff000
670 no-map;
671 };
672
673 smem_mem: memory@80900000 {
674 reg = <0x0 0x80900000
675 no-map;
676 };
677
678 tz_mem: memory@80b00000 {
679 reg = <0x0 0x80b00000
680 no-map;
681 };
682
683 ipa_fw_mem: memory@8b700000 {
684 reg = <0 0x8b700000 0
685 no-map;
686 };
687
688 rmtfs_mem: memory@94600000 {
689 compatible = "qcom,rmt
690 reg = <0x0 0x94600000
691 no-map;
692
693 qcom,client-id = <1>;
694 qcom,vmid = <QCOM_SCM_
695 };
696 };
697
698 smem {
699 compatible = "qcom,smem";
700 memory-region = <&smem_mem>;
701 hwlocks = <&tcsr_mutex 3>;
702 };
703
704 smp2p-cdsp {
705 compatible = "qcom,smp2p";
706 qcom,smem = <94>, <432>;
707
708 interrupts = <GIC_SPI 576 IRQ_
709
710 mboxes = <&apss_shared 6>;
711
712 qcom,local-pid = <0>;
713 qcom,remote-pid = <5>;
714
715 cdsp_smp2p_out: master-kernel
716 qcom,entry-name = "mas
717 #qcom,smem-state-cells
718 };
719
720 cdsp_smp2p_in: slave-kernel {
721 qcom,entry-name = "sla
722
723 interrupt-controller;
724 #interrupt-cells = <2>
725 };
726 };
727
728 smp2p-lpass {
729 compatible = "qcom,smp2p";
730 qcom,smem = <443>, <429>;
731
732 interrupts = <GIC_SPI 158 IRQ_
733
734 mboxes = <&apss_shared 10>;
735
736 qcom,local-pid = <0>;
737 qcom,remote-pid = <2>;
738
739 adsp_smp2p_out: master-kernel
740 qcom,entry-name = "mas
741 #qcom,smem-state-cells
742 };
743
744 adsp_smp2p_in: slave-kernel {
745 qcom,entry-name = "sla
746
747 interrupt-controller;
748 #interrupt-cells = <2>
749 };
750 };
751
752 smp2p-mpss {
753 compatible = "qcom,smp2p";
754 qcom,smem = <435>, <428>;
755 interrupts = <GIC_SPI 451 IRQ_
756 mboxes = <&apss_shared 14>;
757 qcom,local-pid = <0>;
758 qcom,remote-pid = <1>;
759
760 modem_smp2p_out: master-kernel
761 qcom,entry-name = "mas
762 #qcom,smem-state-cells
763 };
764
765 modem_smp2p_in: slave-kernel {
766 qcom,entry-name = "sla
767 interrupt-controller;
768 #interrupt-cells = <2>
769 };
770
771 ipa_smp2p_out: ipa-ap-to-modem
772 qcom,entry-name = "ipa
773 #qcom,smem-state-cells
774 };
775
776 ipa_smp2p_in: ipa-modem-to-ap
777 qcom,entry-name = "ipa
778 interrupt-controller;
779 #interrupt-cells = <2>
780 };
781 };
782
783 soc: soc@0 {
784 #address-cells = <2>;
785 #size-cells = <2>;
786 ranges = <0 0 0 0 0x10 0>;
787 dma-ranges = <0 0 0 0 0x10 0>;
788 compatible = "simple-bus";
789
790 gcc: clock-controller@100000 {
791 compatible = "qcom,gcc
792 reg = <0 0x00100000 0
793 clocks = <&rpmhcc RPMH
794 <&rpmhcc RPMH
795 <&sleep_clk>;
796 clock-names = "bi_tcxo
797 #clock-cells = <1>;
798 #reset-cells = <1>;
799 #power-domain-cells =
800 power-domains = <&rpmh
801 };
802
803 qfprom: efuse@784000 {
804 compatible = "qcom,sc7
805 reg = <0 0x00784000 0
806 <0 0x00780000 0
807 <0 0x00782000 0
808 <0 0x00786000 0
809
810 clocks = <&gcc GCC_SEC
811 clock-names = "core";
812 #address-cells = <1>;
813 #size-cells = <1>;
814
815 qusb2p_hstx_trim: hstx
816 reg = <0x25b 0
817 bits = <1 3>;
818 };
819
820 gpu_speed_bin: gpu-spe
821 reg = <0x1d2 0
822 bits = <5 8>;
823 };
824 };
825
826 sdhc_1: mmc@7c4000 {
827 compatible = "qcom,sc7
828 reg = <0 0x007c4000 0
829 <0 0x007c5000
830 reg-names = "hc", "cqh
831
832 iommus = <&apps_smmu 0
833 interrupts = <GIC_SPI
834 <GIC_S
835 interrupt-names = "hc_
836
837 clocks = <&gcc GCC_SDC
838 <&gcc GCC_SDC
839 <&rpmhcc RPMH
840 clock-names = "iface",
841 interconnects = <&aggr
842 <&gem_
843 interconnect-names = "
844 power-domains = <&rpmh
845 operating-points-v2 =
846
847 bus-width = <8>;
848 non-removable;
849 supports-cqe;
850
851 mmc-ddr-1_8v;
852 mmc-hs200-1_8v;
853 mmc-hs400-1_8v;
854 mmc-hs400-enhanced-str
855
856 status = "disabled";
857
858 sdhc1_opp_table: opp-t
859 compatible = "
860
861 opp-100000000
862 opp-hz
863 requir
864 opp-pe
865 opp-av
866 };
867
868 opp-384000000
869 opp-hz
870 requir
871 opp-pe
872 opp-av
873 };
874 };
875 };
876
877 qupv3_id_0: geniqup@8c0000 {
878 compatible = "qcom,gen
879 reg = <0 0x008c0000 0
880 clock-names = "m-ahb",
881 clocks = <&gcc GCC_QUP
882 <&gcc GCC_QUP
883 #address-cells = <2>;
884 #size-cells = <2>;
885 ranges;
886 iommus = <&apps_smmu 0
887 status = "disabled";
888
889 i2c0: i2c@880000 {
890 compatible = "
891 reg = <0 0x008
892 clock-names =
893 clocks = <&gcc
894 pinctrl-names
895 pinctrl-0 = <&
896 interrupts = <
897 #address-cells
898 #size-cells =
899 interconnects
900
901
902 interconnect-n
903
904 power-domains
905 required-opps
906 status = "disa
907 };
908
909 spi0: spi@880000 {
910 compatible = "
911 reg = <0 0x008
912 clock-names =
913 clocks = <&gcc
914 pinctrl-names
915 pinctrl-0 = <&
916 interrupts = <
917 #address-cells
918 #size-cells =
919 power-domains
920 operating-poin
921 interconnects
922
923 interconnect-n
924 status = "disa
925 };
926
927 uart0: serial@880000 {
928 compatible = "
929 reg = <0 0x008
930 clock-names =
931 clocks = <&gcc
932 pinctrl-names
933 pinctrl-0 = <&
934 interrupts = <
935 power-domains
936 operating-poin
937 interconnects
938
939 interconnect-n
940 status = "disa
941 };
942
943 i2c1: i2c@884000 {
944 compatible = "
945 reg = <0 0x008
946 clock-names =
947 clocks = <&gcc
948 pinctrl-names
949 pinctrl-0 = <&
950 interrupts = <
951 #address-cells
952 #size-cells =
953 interconnects
954
955
956 interconnect-n
957
958 power-domains
959 required-opps
960 status = "disa
961 };
962
963 spi1: spi@884000 {
964 compatible = "
965 reg = <0 0x008
966 clock-names =
967 clocks = <&gcc
968 pinctrl-names
969 pinctrl-0 = <&
970 interrupts = <
971 #address-cells
972 #size-cells =
973 power-domains
974 operating-poin
975 interconnects
976
977 interconnect-n
978 status = "disa
979 };
980
981 uart1: serial@884000 {
982 compatible = "
983 reg = <0 0x008
984 clock-names =
985 clocks = <&gcc
986 pinctrl-names
987 pinctrl-0 = <&
988 interrupts = <
989 power-domains
990 operating-poin
991 interconnects
992
993 interconnect-n
994 status = "disa
995 };
996
997 i2c2: i2c@888000 {
998 compatible = "
999 reg = <0 0x008
1000 clock-names =
1001 clocks = <&gc
1002 pinctrl-names
1003 pinctrl-0 = <
1004 interrupts =
1005 #address-cell
1006 #size-cells =
1007 interconnects
1008
1009
1010 interconnect-
1011
1012 power-domains
1013 required-opps
1014 status = "dis
1015 };
1016
1017 uart2: serial@888000
1018 compatible =
1019 reg = <0 0x00
1020 clock-names =
1021 clocks = <&gc
1022 pinctrl-names
1023 pinctrl-0 = <
1024 interrupts =
1025 power-domains
1026 operating-poi
1027 interconnects
1028
1029 interconnect-
1030 status = "dis
1031 };
1032
1033 i2c3: i2c@88c000 {
1034 compatible =
1035 reg = <0 0x00
1036 clock-names =
1037 clocks = <&gc
1038 pinctrl-names
1039 pinctrl-0 = <
1040 interrupts =
1041 #address-cell
1042 #size-cells =
1043 interconnects
1044
1045
1046 interconnect-
1047
1048 power-domains
1049 required-opps
1050 status = "dis
1051 };
1052
1053 spi3: spi@88c000 {
1054 compatible =
1055 reg = <0 0x00
1056 clock-names =
1057 clocks = <&gc
1058 pinctrl-names
1059 pinctrl-0 = <
1060 interrupts =
1061 #address-cell
1062 #size-cells =
1063 power-domains
1064 operating-poi
1065 interconnects
1066
1067 interconnect-
1068 status = "dis
1069 };
1070
1071 uart3: serial@88c000
1072 compatible =
1073 reg = <0 0x00
1074 clock-names =
1075 clocks = <&gc
1076 pinctrl-names
1077 pinctrl-0 = <
1078 interrupts =
1079 power-domains
1080 operating-poi
1081 interconnects
1082
1083 interconnect-
1084 status = "dis
1085 };
1086
1087 i2c4: i2c@890000 {
1088 compatible =
1089 reg = <0 0x00
1090 clock-names =
1091 clocks = <&gc
1092 pinctrl-names
1093 pinctrl-0 = <
1094 interrupts =
1095 #address-cell
1096 #size-cells =
1097 interconnects
1098
1099
1100 interconnect-
1101
1102 power-domains
1103 required-opps
1104 status = "dis
1105 };
1106
1107 uart4: serial@890000
1108 compatible =
1109 reg = <0 0x00
1110 clock-names =
1111 clocks = <&gc
1112 pinctrl-names
1113 pinctrl-0 = <
1114 interrupts =
1115 power-domains
1116 operating-poi
1117 interconnects
1118
1119 interconnect-
1120 status = "dis
1121 };
1122
1123 i2c5: i2c@894000 {
1124 compatible =
1125 reg = <0 0x00
1126 clock-names =
1127 clocks = <&gc
1128 pinctrl-names
1129 pinctrl-0 = <
1130 interrupts =
1131 #address-cell
1132 #size-cells =
1133 interconnects
1134
1135
1136 interconnect-
1137
1138 power-domains
1139 required-opps
1140 status = "dis
1141 };
1142
1143 spi5: spi@894000 {
1144 compatible =
1145 reg = <0 0x00
1146 clock-names =
1147 clocks = <&gc
1148 pinctrl-names
1149 pinctrl-0 = <
1150 interrupts =
1151 #address-cell
1152 #size-cells =
1153 power-domains
1154 operating-poi
1155 interconnects
1156
1157 interconnect-
1158 status = "dis
1159 };
1160
1161 uart5: serial@894000
1162 compatible =
1163 reg = <0 0x00
1164 clock-names =
1165 clocks = <&gc
1166 pinctrl-names
1167 pinctrl-0 = <
1168 interrupts =
1169 power-domains
1170 operating-poi
1171 interconnects
1172
1173 interconnect-
1174 status = "dis
1175 };
1176 };
1177
1178 qupv3_id_1: geniqup@ac0000 {
1179 compatible = "qcom,ge
1180 reg = <0 0x00ac0000 0
1181 clock-names = "m-ahb"
1182 clocks = <&gcc GCC_QU
1183 <&gcc GCC_QU
1184 #address-cells = <2>;
1185 #size-cells = <2>;
1186 ranges;
1187 iommus = <&apps_smmu
1188 status = "disabled";
1189
1190 i2c6: i2c@a80000 {
1191 compatible =
1192 reg = <0 0x00
1193 clock-names =
1194 clocks = <&gc
1195 pinctrl-names
1196 pinctrl-0 = <
1197 interrupts =
1198 #address-cell
1199 #size-cells =
1200 interconnects
1201
1202
1203 interconnect-
1204
1205 power-domains
1206 required-opps
1207 status = "dis
1208 };
1209
1210 spi6: spi@a80000 {
1211 compatible =
1212 reg = <0 0x00
1213 clock-names =
1214 clocks = <&gc
1215 pinctrl-names
1216 pinctrl-0 = <
1217 interrupts =
1218 #address-cell
1219 #size-cells =
1220 power-domains
1221 operating-poi
1222 interconnects
1223
1224 interconnect-
1225 status = "dis
1226 };
1227
1228 uart6: serial@a80000
1229 compatible =
1230 reg = <0 0x00
1231 clock-names =
1232 clocks = <&gc
1233 pinctrl-names
1234 pinctrl-0 = <
1235 interrupts =
1236 power-domains
1237 operating-poi
1238 interconnects
1239
1240 interconnect-
1241 status = "dis
1242 };
1243
1244 i2c7: i2c@a84000 {
1245 compatible =
1246 reg = <0 0x00
1247 clock-names =
1248 clocks = <&gc
1249 pinctrl-names
1250 pinctrl-0 = <
1251 interrupts =
1252 #address-cell
1253 #size-cells =
1254 interconnects
1255
1256
1257 interconnect-
1258
1259 power-domains
1260 required-opps
1261 status = "dis
1262 };
1263
1264 uart7: serial@a84000
1265 compatible =
1266 reg = <0 0x00
1267 clock-names =
1268 clocks = <&gc
1269 pinctrl-names
1270 pinctrl-0 = <
1271 interrupts =
1272 power-domains
1273 operating-poi
1274 interconnects
1275
1276 interconnect-
1277 status = "dis
1278 };
1279
1280 i2c8: i2c@a88000 {
1281 compatible =
1282 reg = <0 0x00
1283 clock-names =
1284 clocks = <&gc
1285 pinctrl-names
1286 pinctrl-0 = <
1287 interrupts =
1288 #address-cell
1289 #size-cells =
1290 interconnects
1291
1292
1293 interconnect-
1294
1295 power-domains
1296 required-opps
1297 status = "dis
1298 };
1299
1300 spi8: spi@a88000 {
1301 compatible =
1302 reg = <0 0x00
1303 clock-names =
1304 clocks = <&gc
1305 pinctrl-names
1306 pinctrl-0 = <
1307 interrupts =
1308 #address-cell
1309 #size-cells =
1310 power-domains
1311 operating-poi
1312 interconnects
1313
1314 interconnect-
1315 status = "dis
1316 };
1317
1318 uart8: serial@a88000
1319 compatible =
1320 reg = <0 0x00
1321 clock-names =
1322 clocks = <&gc
1323 pinctrl-names
1324 pinctrl-0 = <
1325 interrupts =
1326 power-domains
1327 operating-poi
1328 interconnects
1329
1330 interconnect-
1331 status = "dis
1332 };
1333
1334 i2c9: i2c@a8c000 {
1335 compatible =
1336 reg = <0 0x00
1337 clock-names =
1338 clocks = <&gc
1339 pinctrl-names
1340 pinctrl-0 = <
1341 interrupts =
1342 #address-cell
1343 #size-cells =
1344 interconnects
1345
1346
1347 interconnect-
1348
1349 power-domains
1350 required-opps
1351 status = "dis
1352 };
1353
1354 uart9: serial@a8c000
1355 compatible =
1356 reg = <0 0x00
1357 clock-names =
1358 clocks = <&gc
1359 pinctrl-names
1360 pinctrl-0 = <
1361 interrupts =
1362 power-domains
1363 operating-poi
1364 interconnects
1365
1366 interconnect-
1367 status = "dis
1368 };
1369
1370 i2c10: i2c@a90000 {
1371 compatible =
1372 reg = <0 0x00
1373 clock-names =
1374 clocks = <&gc
1375 pinctrl-names
1376 pinctrl-0 = <
1377 interrupts =
1378 #address-cell
1379 #size-cells =
1380 interconnects
1381
1382
1383 interconnect-
1384
1385 power-domains
1386 required-opps
1387 status = "dis
1388 };
1389
1390 spi10: spi@a90000 {
1391 compatible =
1392 reg = <0 0x00
1393 clock-names =
1394 clocks = <&gc
1395 pinctrl-names
1396 pinctrl-0 = <
1397 interrupts =
1398 #address-cell
1399 #size-cells =
1400 power-domains
1401 operating-poi
1402 interconnects
1403
1404 interconnect-
1405 status = "dis
1406 };
1407
1408 uart10: serial@a90000
1409 compatible =
1410 reg = <0 0x00
1411 clock-names =
1412 clocks = <&gc
1413 pinctrl-names
1414 pinctrl-0 = <
1415 interrupts =
1416 power-domains
1417 operating-poi
1418 interconnects
1419
1420 interconnect-
1421 status = "dis
1422 };
1423
1424 i2c11: i2c@a94000 {
1425 compatible =
1426 reg = <0 0x00
1427 clock-names =
1428 clocks = <&gc
1429 pinctrl-names
1430 pinctrl-0 = <
1431 interrupts =
1432 #address-cell
1433 #size-cells =
1434 interconnects
1435
1436
1437 interconnect-
1438
1439 power-domains
1440 required-opps
1441 status = "dis
1442 };
1443
1444 spi11: spi@a94000 {
1445 compatible =
1446 reg = <0 0x00
1447 clock-names =
1448 clocks = <&gc
1449 pinctrl-names
1450 pinctrl-0 = <
1451 interrupts =
1452 #address-cell
1453 #size-cells =
1454 power-domains
1455 operating-poi
1456 interconnects
1457
1458 interconnect-
1459 status = "dis
1460 };
1461
1462 uart11: serial@a94000
1463 compatible =
1464 reg = <0 0x00
1465 clock-names =
1466 clocks = <&gc
1467 pinctrl-names
1468 pinctrl-0 = <
1469 interrupts =
1470 power-domains
1471 operating-poi
1472 interconnects
1473
1474 interconnect-
1475 status = "dis
1476 };
1477 };
1478
1479 config_noc: interconnect@1500
1480 compatible = "qcom,sc
1481 reg = <0 0x01500000 0
1482 #interconnect-cells =
1483 qcom,bcm-voters = <&a
1484 };
1485
1486 system_noc: interconnect@1620
1487 compatible = "qcom,sc
1488 reg = <0 0x01620000 0
1489 #interconnect-cells =
1490 qcom,bcm-voters = <&a
1491 };
1492
1493 mc_virt: interconnect@1638000
1494 compatible = "qcom,sc
1495 reg = <0 0x01638000 0
1496 #interconnect-cells =
1497 qcom,bcm-voters = <&a
1498 };
1499
1500 qup_virt: interconnect@165000
1501 compatible = "qcom,sc
1502 reg = <0 0x01650000 0
1503 #interconnect-cells =
1504 qcom,bcm-voters = <&a
1505 };
1506
1507 aggre1_noc: interconnect@16e0
1508 compatible = "qcom,sc
1509 reg = <0 0x016e0000 0
1510 #interconnect-cells =
1511 qcom,bcm-voters = <&a
1512 };
1513
1514 aggre2_noc: interconnect@1705
1515 compatible = "qcom,sc
1516 reg = <0 0x01705000 0
1517 #interconnect-cells =
1518 qcom,bcm-voters = <&a
1519 };
1520
1521 compute_noc: interconnect@170
1522 compatible = "qcom,sc
1523 reg = <0 0x0170e000 0
1524 #interconnect-cells =
1525 qcom,bcm-voters = <&a
1526 };
1527
1528 mmss_noc: interconnect@174000
1529 compatible = "qcom,sc
1530 reg = <0 0x01740000 0
1531 #interconnect-cells =
1532 qcom,bcm-voters = <&a
1533 };
1534
1535 ufs_mem_hc: ufshc@1d84000 {
1536 compatible = "qcom,sc
1537 "jedec,u
1538 reg = <0 0x01d84000 0
1539 interrupts = <GIC_SPI
1540 phys = <&ufs_mem_phy>
1541 phy-names = "ufsphy";
1542 lanes-per-direction =
1543 #reset-cells = <1>;
1544 resets = <&gcc GCC_UF
1545 reset-names = "rst";
1546
1547 power-domains = <&gcc
1548
1549 iommus = <&apps_smmu
1550
1551 clock-names = "core_c
1552 "bus_ag
1553 "iface_
1554 "core_c
1555 "ref_cl
1556 "tx_lan
1557 "rx_lan
1558 clocks = <&gcc GCC_UF
1559 <&gcc GCC_AG
1560 <&gcc GCC_UF
1561 <&gcc GCC_UF
1562 <&rpmhcc RPM
1563 <&gcc GCC_UF
1564 <&gcc GCC_UF
1565 freq-table-hz = <5000
1566 <0 0>
1567 <0 0>
1568 <3750
1569 <0 0>
1570 <0 0>
1571 <0 0>
1572
1573 interconnects = <&agg
1574 &mc_
1575 <&gem
1576 &con
1577 interconnect-names =
1578
1579 qcom,ice = <&ice>;
1580
1581 status = "disabled";
1582 };
1583
1584 ufs_mem_phy: phy@1d87000 {
1585 compatible = "qcom,sc
1586 reg = <0 0x01d87000 0
1587 clocks = <&rpmhcc RPM
1588 <&gcc GCC_UF
1589 <&gcc GCC_UF
1590 clock-names = "ref",
1591 "ref_au
1592 "qref";
1593 power-domains = <&gcc
1594 resets = <&ufs_mem_hc
1595 reset-names = "ufsphy
1596 #phy-cells = <0>;
1597 status = "disabled";
1598 };
1599
1600 ice: crypto@1d90000 {
1601 compatible = "qcom,sc
1602 "qcom,in
1603 reg = <0 0x01d90000 0
1604 clocks = <&gcc GCC_UF
1605 };
1606
1607 ipa: ipa@1e40000 {
1608 compatible = "qcom,sc
1609
1610 iommus = <&apps_smmu
1611 <&apps_smmu
1612 reg = <0 0x01e40000 0
1613 <0 0x01e47000 0
1614 <0 0x01e04000 0
1615 reg-names = "ipa-reg"
1616 "ipa-shar
1617 "gsi";
1618
1619 interrupts-extended =
1620
1621
1622
1623 interrupt-names = "ip
1624 "gs
1625 "ip
1626 "ip
1627
1628 clocks = <&rpmhcc RPM
1629 clock-names = "core";
1630
1631 interconnects = <&agg
1632 <&agg
1633 <&gem
1634 interconnect-names =
1635
1636
1637
1638 qcom,qmp = <&aoss_qmp
1639
1640 qcom,smem-states = <&
1641 <&
1642 qcom,smem-state-names
1643
1644
1645 status = "disabled";
1646 };
1647
1648 tcsr_mutex: hwlock@1f40000 {
1649 compatible = "qcom,tc
1650 reg = <0 0x01f40000 0
1651 #hwlock-cells = <1>;
1652 };
1653
1654 tcsr_regs_1: syscon@1f60000 {
1655 compatible = "qcom,sc
1656 reg = <0 0x01f60000 0
1657 };
1658
1659 tcsr_regs_2: syscon@1fc0000 {
1660 compatible = "qcom,sc
1661 reg = <0 0x01fc0000 0
1662 };
1663
1664 tlmm: pinctrl@3500000 {
1665 compatible = "qcom,sc
1666 reg = <0 0x03500000 0
1667 <0 0x03900000 0
1668 <0 0x03d00000 0
1669 reg-names = "west", "
1670 interrupts = <GIC_SPI
1671 gpio-controller;
1672 #gpio-cells = <2>;
1673 interrupt-controller;
1674 #interrupt-cells = <2
1675 gpio-ranges = <&tlmm
1676 wakeup-parent = <&pdc
1677
1678 dp_hot_plug_det: dp-h
1679 pins = "gpio1
1680 function = "d
1681 };
1682
1683 qspi_clk: qspi-clk-st
1684 pins = "gpio6
1685 function = "q
1686 };
1687
1688 qspi_cs0: qspi-cs0-st
1689 pins = "gpio6
1690 function = "q
1691 };
1692
1693 qspi_cs1: qspi-cs1-st
1694 pins = "gpio7
1695 function = "q
1696 };
1697
1698 qspi_data0: qspi-data
1699 pins = "gpio6
1700 function = "q
1701 };
1702
1703 qspi_data1: qspi-data
1704 pins = "gpio6
1705 function = "q
1706 };
1707
1708 qspi_data23: qspi-dat
1709 pins = "gpio6
1710 function = "q
1711 };
1712
1713 qup_i2c0_default: qup
1714 pins = "gpio3
1715 function = "q
1716 };
1717
1718 qup_i2c1_default: qup
1719 pins = "gpio0
1720 function = "q
1721 };
1722
1723 qup_i2c2_default: qup
1724 pins = "gpio1
1725 function = "q
1726 };
1727
1728 qup_i2c3_default: qup
1729 pins = "gpio3
1730 function = "q
1731 };
1732
1733 qup_i2c4_default: qup
1734 pins = "gpio1
1735 function = "q
1736 };
1737
1738 qup_i2c5_default: qup
1739 pins = "gpio2
1740 function = "q
1741 };
1742
1743 qup_i2c6_default: qup
1744 pins = "gpio5
1745 function = "q
1746 };
1747
1748 qup_i2c7_default: qup
1749 pins = "gpio6
1750 function = "q
1751 };
1752
1753 qup_i2c8_default: qup
1754 pins = "gpio4
1755 function = "q
1756 };
1757
1758 qup_i2c9_default: qup
1759 pins = "gpio4
1760 function = "q
1761 };
1762
1763 qup_i2c10_default: qu
1764 pins = "gpio8
1765 function = "q
1766 };
1767
1768 qup_i2c11_default: qu
1769 pins = "gpio5
1770 function = "q
1771 };
1772
1773 qup_spi0_spi: qup-spi
1774 pins = "gpio3
1775 function = "q
1776 };
1777
1778 qup_spi0_cs: qup-spi0
1779 pins = "gpio3
1780 function = "q
1781 };
1782
1783 qup_spi0_cs_gpio: qup
1784 pins = "gpio3
1785 function = "g
1786 };
1787
1788 qup_spi1_spi: qup-spi
1789 pins = "gpio0
1790 function = "q
1791 };
1792
1793 qup_spi1_cs: qup-spi1
1794 pins = "gpio3
1795 function = "q
1796 };
1797
1798 qup_spi1_cs_gpio: qup
1799 pins = "gpio3
1800 function = "g
1801 };
1802
1803 qup_spi3_spi: qup-spi
1804 pins = "gpio3
1805 function = "q
1806 };
1807
1808 qup_spi3_cs: qup-spi3
1809 pins = "gpio4
1810 function = "q
1811 };
1812
1813 qup_spi3_cs_gpio: qup
1814 pins = "gpio4
1815 function = "g
1816 };
1817
1818 qup_spi5_spi: qup-spi
1819 pins = "gpio2
1820 function = "q
1821 };
1822
1823 qup_spi5_cs: qup-spi5
1824 pins = "gpio2
1825 function = "q
1826 };
1827
1828 qup_spi5_cs_gpio: qup
1829 pins = "gpio2
1830 function = "g
1831 };
1832
1833 qup_spi6_spi: qup-spi
1834 pins = "gpio5
1835 function = "q
1836 };
1837
1838 qup_spi6_cs: qup-spi6
1839 pins = "gpio6
1840 function = "q
1841 };
1842
1843 qup_spi6_cs_gpio: qup
1844 pins = "gpio6
1845 function = "g
1846 };
1847
1848 qup_spi8_spi: qup-spi
1849 pins = "gpio4
1850 function = "q
1851 };
1852
1853 qup_spi8_cs: qup-spi8
1854 pins = "gpio4
1855 function = "q
1856 };
1857
1858 qup_spi8_cs_gpio: qup
1859 pins = "gpio4
1860 function = "g
1861 };
1862
1863 qup_spi10_spi: qup-sp
1864 pins = "gpio8
1865 function = "q
1866 };
1867
1868 qup_spi10_cs: qup-spi
1869 pins = "gpio8
1870 function = "q
1871 };
1872
1873 qup_spi10_cs_gpio: qu
1874 pins = "gpio8
1875 function = "g
1876 };
1877
1878 qup_spi11_spi: qup-sp
1879 pins = "gpio5
1880 function = "q
1881 };
1882
1883 qup_spi11_cs: qup-spi
1884 pins = "gpio5
1885 function = "q
1886 };
1887
1888 qup_spi11_cs_gpio: qu
1889 pins = "gpio5
1890 function = "g
1891 };
1892
1893 qup_uart0_default: qu
1894 qup_uart0_cts
1895 pins
1896 funct
1897 };
1898
1899 qup_uart0_rts
1900 pins
1901 funct
1902 };
1903
1904 qup_uart0_tx:
1905 pins
1906 funct
1907 };
1908
1909 qup_uart0_rx:
1910 pins
1911 funct
1912 };
1913 };
1914
1915 qup_uart1_default: qu
1916 qup_uart1_cts
1917 pins
1918 funct
1919 };
1920
1921 qup_uart1_rts
1922 pins
1923 funct
1924 };
1925
1926 qup_uart1_tx:
1927 pins
1928 funct
1929 };
1930
1931 qup_uart1_rx:
1932 pins
1933 funct
1934 };
1935 };
1936
1937 qup_uart2_default: qu
1938 qup_uart2_tx:
1939 pins
1940 funct
1941 };
1942
1943 qup_uart2_rx:
1944 pins
1945 funct
1946 };
1947 };
1948
1949 qup_uart3_default: qu
1950 qup_uart3_cts
1951 pins
1952 funct
1953 };
1954
1955 qup_uart3_rts
1956 pins
1957 funct
1958 };
1959
1960 qup_uart3_tx:
1961 pins
1962 funct
1963 };
1964
1965 qup_uart3_rx:
1966 pins
1967 funct
1968 };
1969 };
1970
1971 qup_uart4_default: qu
1972 qup_uart4_tx:
1973 pins
1974 funct
1975 };
1976
1977 qup_uart4_rx:
1978 pins
1979 funct
1980 };
1981 };
1982
1983 qup_uart5_default: qu
1984 qup_uart5_cts
1985 pins
1986 funct
1987 };
1988
1989 qup_uart5_rts
1990 pins
1991 funct
1992 };
1993
1994 qup_uart5_tx:
1995 pins
1996 funct
1997 };
1998
1999 qup_uart5_rx:
2000 pins
2001 funct
2002 };
2003 };
2004
2005 qup_uart6_default: qu
2006 qup_uart6_cts
2007 pins
2008 funct
2009 };
2010
2011 qup_uart6_rts
2012 pins
2013 funct
2014 };
2015
2016 qup_uart6_tx:
2017 pins
2018 funct
2019 };
2020
2021 qup_uart6_rx:
2022 pins
2023 funct
2024 };
2025 };
2026
2027 qup_uart7_default: qu
2028 qup_uart7_tx:
2029 pins
2030 funct
2031 };
2032
2033 qup_uart7_rx:
2034 pins
2035 funct
2036 };
2037 };
2038
2039 qup_uart8_default: qu
2040 qup_uart8_tx:
2041 pins
2042 funct
2043 };
2044
2045 qup_uart8_rx:
2046 pins
2047 funct
2048 };
2049 };
2050
2051 qup_uart9_default: qu
2052 qup_uart9_tx:
2053 pins
2054 funct
2055 };
2056
2057 qup_uart9_rx:
2058 pins
2059 funct
2060 };
2061 };
2062
2063 qup_uart10_default: q
2064 qup_uart10_ct
2065 pins
2066 funct
2067 };
2068
2069 qup_uart10_rt
2070 pins
2071 funct
2072 };
2073
2074 qup_uart10_tx
2075 pins
2076 funct
2077 };
2078
2079 qup_uart10_rx
2080 pins
2081 funct
2082 };
2083 };
2084
2085 qup_uart11_default: q
2086 qup_uart11_ct
2087 pins
2088 funct
2089 };
2090
2091 qup_uart11_rt
2092 pins
2093 funct
2094 };
2095
2096 qup_uart11_tx
2097 pins
2098 funct
2099 };
2100
2101 qup_uart11_rx
2102 pins
2103 funct
2104 };
2105 };
2106
2107 sec_mi2s_active: sec-
2108 pins = "gpio4
2109 function = "m
2110 };
2111
2112 pri_mi2s_active: pri-
2113 pins = "gpio5
2114 function = "m
2115 };
2116
2117 pri_mi2s_mclk_active:
2118 pins = "gpio5
2119 function = "l
2120 };
2121
2122 ter_mi2s_active: ter-
2123 pins = "gpio6
2124 function = "m
2125 };
2126 };
2127
2128 remoteproc_mpss: remoteproc@4
2129 compatible = "qcom,sc
2130 reg = <0 0x04080000 0
2131
2132 interrupts-extended =
2133
2134
2135
2136
2137
2138 interrupt-names = "wd
2139 "st
2140
2141 clocks = <&rpmhcc RPM
2142 clock-names = "xo";
2143
2144 power-domains = <&rpm
2145 <&rpm
2146 <&rpm
2147 power-domain-names =
2148
2149 memory-region = <&mps
2150
2151 qcom,qmp = <&aoss_qmp
2152
2153 qcom,smem-states = <&
2154 qcom,smem-state-names
2155
2156 status = "disabled";
2157
2158 glink-edge {
2159 interrupts =
2160 label = "mode
2161 qcom,remote-p
2162 mboxes = <&ap
2163 };
2164 };
2165
2166 gpu: gpu@5000000 {
2167 compatible = "qcom,ad
2168 reg = <0 0x05000000 0
2169 <0 0x05061000
2170 reg-names = "kgsl_3d0
2171 interrupts = <GIC_SPI
2172 iommus = <&adreno_smm
2173 operating-points-v2 =
2174 qcom,gmu = <&gmu>;
2175
2176 #cooling-cells = <2>;
2177
2178 nvmem-cells = <&gpu_s
2179 nvmem-cell-names = "s
2180
2181 interconnects = <&gem
2182 interconnect-names =
2183
2184 gpu_opp_table: opp-ta
2185 compatible =
2186
2187 opp-825000000
2188 opp-h
2189 opp-l
2190 opp-p
2191 opp-s
2192 };
2193
2194 opp-800000000
2195 opp-h
2196 opp-l
2197 opp-p
2198 opp-s
2199 };
2200
2201 opp-650000000
2202 opp-h
2203 opp-l
2204 opp-p
2205 opp-s
2206 };
2207
2208 opp-565000000
2209 opp-h
2210 opp-l
2211 opp-p
2212 opp-s
2213 };
2214
2215 opp-430000000
2216 opp-h
2217 opp-l
2218 opp-p
2219 opp-s
2220 };
2221
2222 opp-355000000
2223 opp-h
2224 opp-l
2225 opp-p
2226 opp-s
2227 };
2228
2229 opp-267000000
2230 opp-h
2231 opp-l
2232 opp-p
2233 opp-s
2234 };
2235
2236 opp-180000000
2237 opp-h
2238 opp-l
2239 opp-p
2240 opp-s
2241 };
2242 };
2243 };
2244
2245 adreno_smmu: iommu@5040000 {
2246 compatible = "qcom,sc
2247 reg = <0 0x05040000 0
2248 #iommu-cells = <1>;
2249 #global-interrupts =
2250 interrupts = <GIC_SPI
2251 <GIC_
2252 <GIC_
2253 <GIC_
2254 <GIC_
2255 <GIC_
2256 <GIC_
2257 <GIC_
2258 <GIC_
2259 <GIC_
2260
2261 clocks = <&gcc GCC_GP
2262 <&gcc GCC_GPU
2263 clock-names = "bus",
2264
2265 power-domains = <&gpu
2266 };
2267
2268 gmu: gmu@506a000 {
2269 compatible = "qcom,ad
2270 reg = <0 0x0506a000 0
2271 <0 0x0b490000
2272 reg-names = "gmu", "g
2273 interrupts = <GIC_SPI
2274 <GIC_SPI 3
2275 interrupt-names = "hf
2276 clocks = <&gpucc GPU_
2277 <&gpucc GPU_CC
2278 <&gcc GCC_DDRS
2279 <&gcc GCC_GPU_
2280 clock-names = "gmu",
2281 power-domains = <&gpu
2282 power-domain-names =
2283 iommus = <&adreno_smm
2284 operating-points-v2 =
2285
2286 gmu_opp_table: opp-ta
2287 compatible =
2288
2289 opp-200000000
2290 opp-h
2291 opp-l
2292 };
2293 };
2294 };
2295
2296 gpucc: clock-controller@50900
2297 compatible = "qcom,sc
2298 reg = <0 0x05090000 0
2299 clocks = <&rpmhcc RPM
2300 <&gcc GCC_GP
2301 <&gcc GCC_GP
2302 clock-names = "bi_tcx
2303 "gcc_gp
2304 "gcc_gp
2305 #clock-cells = <1>;
2306 #reset-cells = <1>;
2307 #power-domain-cells =
2308 };
2309
2310 dma@10a2000 {
2311 compatible = "qcom,sc
2312 reg = <0x0 0x010a2000
2313 <0x0 0x010ae000
2314 status = "disabled";
2315 };
2316
2317 stm@6002000 {
2318 compatible = "arm,cor
2319 reg = <0 0x06002000 0
2320 <0 0x16280000 0
2321 reg-names = "stm-base
2322
2323 clocks = <&aoss_qmp>;
2324 clock-names = "apb_pc
2325
2326 out-ports {
2327 port {
2328 stm_o
2329
2330 };
2331 };
2332 };
2333 };
2334
2335 funnel@6041000 {
2336 compatible = "arm,cor
2337 reg = <0 0x06041000 0
2338
2339 clocks = <&aoss_qmp>;
2340 clock-names = "apb_pc
2341
2342 out-ports {
2343 port {
2344 funne
2345
2346 };
2347 };
2348 };
2349
2350 in-ports {
2351 #address-cell
2352 #size-cells =
2353
2354 port@7 {
2355 reg =
2356 funne
2357
2358 };
2359 };
2360 };
2361 };
2362
2363 funnel@6042000 {
2364 compatible = "arm,cor
2365 reg = <0 0x06042000 0
2366
2367 clocks = <&aoss_qmp>;
2368 clock-names = "apb_pc
2369
2370 out-ports {
2371 port {
2372 funne
2373
2374 };
2375 };
2376 };
2377
2378 in-ports {
2379 #address-cell
2380 #size-cells =
2381
2382 port@4 {
2383 reg =
2384 funne
2385
2386 };
2387 };
2388 };
2389 };
2390
2391 funnel@6045000 {
2392 compatible = "arm,cor
2393 reg = <0 0x06045000 0
2394
2395 clocks = <&aoss_qmp>;
2396 clock-names = "apb_pc
2397
2398 out-ports {
2399 port {
2400 merge
2401
2402 };
2403 };
2404 };
2405
2406 in-ports {
2407 #address-cell
2408 #size-cells =
2409
2410 port@0 {
2411 reg =
2412 merge
2413
2414 };
2415 };
2416
2417 port@1 {
2418 reg =
2419 merge
2420
2421 };
2422 };
2423 };
2424 };
2425
2426 replicator@6046000 {
2427 compatible = "arm,cor
2428 reg = <0 0x06046000 0
2429
2430 clocks = <&aoss_qmp>;
2431 clock-names = "apb_pc
2432
2433 out-ports {
2434 port {
2435 repli
2436
2437 };
2438 };
2439 };
2440
2441 in-ports {
2442 port {
2443 repli
2444
2445 };
2446 };
2447 };
2448 };
2449
2450 etr@6048000 {
2451 compatible = "arm,cor
2452 reg = <0 0x06048000 0
2453 iommus = <&apps_smmu
2454
2455 clocks = <&aoss_qmp>;
2456 clock-names = "apb_pc
2457 arm,scatter-gather;
2458
2459 in-ports {
2460 port {
2461 etr_i
2462
2463 };
2464 };
2465 };
2466 };
2467
2468 funnel@6b04000 {
2469 compatible = "arm,cor
2470 reg = <0 0x06b04000 0
2471
2472 clocks = <&aoss_qmp>;
2473 clock-names = "apb_pc
2474
2475 out-ports {
2476 port {
2477 swao_
2478
2479 };
2480 };
2481 };
2482
2483 in-ports {
2484 #address-cell
2485 #size-cells =
2486
2487 port@7 {
2488 reg =
2489 swao_
2490
2491 };
2492 };
2493 };
2494 };
2495
2496 etf@6b05000 {
2497 compatible = "arm,cor
2498 reg = <0 0x06b05000 0
2499
2500 clocks = <&aoss_qmp>;
2501 clock-names = "apb_pc
2502
2503 out-ports {
2504 port {
2505 etf_o
2506
2507 };
2508 };
2509 };
2510
2511 in-ports {
2512 port {
2513 etf_i
2514
2515 };
2516 };
2517 };
2518 };
2519
2520 replicator@6b06000 {
2521 compatible = "arm,cor
2522 reg = <0 0x06b06000 0
2523
2524 clocks = <&aoss_qmp>;
2525 clock-names = "apb_pc
2526 qcom,replicator-loses
2527
2528 out-ports {
2529 port {
2530 swao_
2531
2532 };
2533 };
2534 };
2535
2536 in-ports {
2537 port {
2538 swao_
2539
2540 };
2541 };
2542 };
2543 };
2544
2545 etm@7040000 {
2546 compatible = "arm,cor
2547 reg = <0 0x07040000 0
2548
2549 cpu = <&CPU0>;
2550
2551 clocks = <&aoss_qmp>;
2552 clock-names = "apb_pc
2553 arm,coresight-loses-c
2554 qcom,skip-power-up;
2555
2556 out-ports {
2557 port {
2558 etm0_
2559
2560 };
2561 };
2562 };
2563 };
2564
2565 etm@7140000 {
2566 compatible = "arm,cor
2567 reg = <0 0x07140000 0
2568
2569 cpu = <&CPU1>;
2570
2571 clocks = <&aoss_qmp>;
2572 clock-names = "apb_pc
2573 arm,coresight-loses-c
2574 qcom,skip-power-up;
2575
2576 out-ports {
2577 port {
2578 etm1_
2579
2580 };
2581 };
2582 };
2583 };
2584
2585 etm@7240000 {
2586 compatible = "arm,cor
2587 reg = <0 0x07240000 0
2588
2589 cpu = <&CPU2>;
2590
2591 clocks = <&aoss_qmp>;
2592 clock-names = "apb_pc
2593 arm,coresight-loses-c
2594 qcom,skip-power-up;
2595
2596 out-ports {
2597 port {
2598 etm2_
2599
2600 };
2601 };
2602 };
2603 };
2604
2605 etm@7340000 {
2606 compatible = "arm,cor
2607 reg = <0 0x07340000 0
2608
2609 cpu = <&CPU3>;
2610
2611 clocks = <&aoss_qmp>;
2612 clock-names = "apb_pc
2613 arm,coresight-loses-c
2614 qcom,skip-power-up;
2615
2616 out-ports {
2617 port {
2618 etm3_
2619
2620 };
2621 };
2622 };
2623 };
2624
2625 etm@7440000 {
2626 compatible = "arm,cor
2627 reg = <0 0x07440000 0
2628
2629 cpu = <&CPU4>;
2630
2631 clocks = <&aoss_qmp>;
2632 clock-names = "apb_pc
2633 arm,coresight-loses-c
2634 qcom,skip-power-up;
2635
2636 out-ports {
2637 port {
2638 etm4_
2639
2640 };
2641 };
2642 };
2643 };
2644
2645 etm@7540000 {
2646 compatible = "arm,cor
2647 reg = <0 0x07540000 0
2648
2649 cpu = <&CPU5>;
2650
2651 clocks = <&aoss_qmp>;
2652 clock-names = "apb_pc
2653 arm,coresight-loses-c
2654 qcom,skip-power-up;
2655
2656 out-ports {
2657 port {
2658 etm5_
2659
2660 };
2661 };
2662 };
2663 };
2664
2665 etm@7640000 {
2666 compatible = "arm,cor
2667 reg = <0 0x07640000 0
2668
2669 cpu = <&CPU6>;
2670
2671 clocks = <&aoss_qmp>;
2672 clock-names = "apb_pc
2673 arm,coresight-loses-c
2674 qcom,skip-power-up;
2675
2676 out-ports {
2677 port {
2678 etm6_
2679
2680 };
2681 };
2682 };
2683 };
2684
2685 etm@7740000 {
2686 compatible = "arm,cor
2687 reg = <0 0x07740000 0
2688
2689 cpu = <&CPU7>;
2690
2691 clocks = <&aoss_qmp>;
2692 clock-names = "apb_pc
2693 arm,coresight-loses-c
2694 qcom,skip-power-up;
2695
2696 out-ports {
2697 port {
2698 etm7_
2699
2700 };
2701 };
2702 };
2703 };
2704
2705 funnel@7800000 { /* APSS Funn
2706 compatible = "arm,cor
2707 reg = <0 0x07800000 0
2708
2709 clocks = <&aoss_qmp>;
2710 clock-names = "apb_pc
2711
2712 out-ports {
2713 port {
2714 apss_
2715
2716 };
2717 };
2718 };
2719
2720 in-ports {
2721 #address-cell
2722 #size-cells =
2723
2724 port@0 {
2725 reg =
2726 apss_
2727
2728 };
2729 };
2730
2731 port@1 {
2732 reg =
2733 apss_
2734
2735 };
2736 };
2737
2738 port@2 {
2739 reg =
2740 apss_
2741
2742 };
2743 };
2744
2745 port@3 {
2746 reg =
2747 apss_
2748
2749 };
2750 };
2751
2752 port@4 {
2753 reg =
2754 apss_
2755
2756 };
2757 };
2758
2759 port@5 {
2760 reg =
2761 apss_
2762
2763 };
2764 };
2765
2766 port@6 {
2767 reg =
2768 apss_
2769
2770 };
2771 };
2772
2773 port@7 {
2774 reg =
2775 apss_
2776
2777 };
2778 };
2779 };
2780 };
2781
2782 funnel@7810000 {
2783 compatible = "arm,cor
2784 reg = <0 0x07810000 0
2785
2786 clocks = <&aoss_qmp>;
2787 clock-names = "apb_pc
2788
2789 out-ports {
2790 port {
2791 apss_
2792
2793 };
2794 };
2795 };
2796
2797 in-ports {
2798 port {
2799 apss_
2800
2801 };
2802 };
2803 };
2804 };
2805
2806 sdhc_2: mmc@8804000 {
2807 compatible = "qcom,sc
2808 reg = <0 0x08804000 0
2809
2810 iommus = <&apps_smmu
2811 interrupts = <GIC_SPI
2812 <GIC_
2813 interrupt-names = "hc
2814
2815 clocks = <&gcc GCC_SD
2816 <&gcc GCC_SD
2817 <&rpmhcc RPM
2818 clock-names = "iface"
2819
2820 interconnects = <&agg
2821 <&gem
2822 interconnect-names =
2823 power-domains = <&rpm
2824 operating-points-v2 =
2825
2826 bus-width = <4>;
2827
2828 status = "disabled";
2829
2830 sdhc2_opp_table: opp-
2831 compatible =
2832
2833 opp-100000000
2834 opp-h
2835 requi
2836 opp-p
2837 opp-a
2838 };
2839
2840 opp-202000000
2841 opp-h
2842 requi
2843 opp-p
2844 opp-a
2845 };
2846 };
2847 };
2848
2849 qspi: spi@88dc000 {
2850 compatible = "qcom,sc
2851 reg = <0 0x088dc000 0
2852 iommus = <&apps_smmu
2853 #address-cells = <1>;
2854 #size-cells = <0>;
2855 interrupts = <GIC_SPI
2856 clocks = <&gcc GCC_QS
2857 <&gcc GCC_QS
2858 clock-names = "iface"
2859 interconnects = <&gem
2860 &conf
2861 interconnect-names =
2862 power-domains = <&rpm
2863 operating-points-v2 =
2864 status = "disabled";
2865 };
2866
2867 usb_1_hsphy: phy@88e3000 {
2868 compatible = "qcom,sc
2869 reg = <0 0x088e3000 0
2870 status = "disabled";
2871 #phy-cells = <0>;
2872 clocks = <&gcc GCC_US
2873 <&rpmhcc RPM
2874 clock-names = "cfg_ah
2875 resets = <&gcc GCC_QU
2876
2877 nvmem-cells = <&qusb2
2878 };
2879
2880 usb_1_qmpphy: phy@88e8000 {
2881 compatible = "qcom,sc
2882 reg = <0 0x088e8000 0
2883 status = "disabled";
2884
2885 clocks = <&gcc GCC_US
2886 <&gcc GCC_US
2887 <&gcc GCC_US
2888 <&gcc GCC_US
2889 <&gcc GCC_US
2890 clock-names = "aux",
2891 "ref",
2892 "com_au
2893 "usb3_p
2894 "cfg_ah
2895
2896 resets = <&gcc GCC_US
2897 <&gcc GCC_US
2898 reset-names = "phy",
2899
2900 #clock-cells = <1>;
2901 #phy-cells = <1>;
2902 };
2903
2904 pmu@90b6300 {
2905 compatible = "qcom,sc
2906 reg = <0 0x090b6300 0
2907 interrupts = <GIC_SPI
2908
2909 interconnects = <&gem
2910 &gem
2911 operating-points-v2 =
2912
2913 cpu_bwmon_opp_table:
2914 compatible =
2915
2916 opp-0 {
2917 opp-p
2918 };
2919
2920 opp-1 {
2921 opp-p
2922 };
2923
2924 opp-2 {
2925 opp-p
2926 };
2927
2928 opp-3 {
2929 opp-p
2930 };
2931
2932 opp-4 {
2933 opp-p
2934 };
2935
2936 opp-5 {
2937 opp-p
2938 };
2939 };
2940 };
2941
2942 pmu@90cd000 {
2943 compatible = "qcom,sc
2944 reg = <0 0x090cd000 0
2945 interrupts = <GIC_SPI
2946
2947 interconnects = <&mc_
2948 &mc_
2949 operating-points-v2 =
2950
2951 llcc_bwmon_opp_table:
2952 compatible =
2953
2954 opp-0 {
2955 opp-p
2956 };
2957
2958 opp-1 {
2959 opp-p
2960 };
2961
2962 opp-2 {
2963 opp-p
2964 };
2965
2966 opp-3 {
2967 opp-p
2968 };
2969
2970 opp-4 {
2971 opp-p
2972 };
2973
2974 opp-5 {
2975 opp-p
2976 };
2977
2978 opp-6 {
2979 opp-p
2980 };
2981
2982 opp-7 {
2983 opp-p
2984 };
2985 };
2986 };
2987
2988 dc_noc: interconnect@9160000
2989 compatible = "qcom,sc
2990 reg = <0 0x09160000 0
2991 #interconnect-cells =
2992 qcom,bcm-voters = <&a
2993 };
2994
2995 system-cache-controller@92000
2996 compatible = "qcom,sc
2997 reg = <0 0x09200000 0
2998 reg-names = "llcc0_ba
2999 interrupts = <GIC_SPI
3000 };
3001
3002 gem_noc: interconnect@9680000
3003 compatible = "qcom,sc
3004 reg = <0 0x09680000 0
3005 #interconnect-cells =
3006 qcom,bcm-voters = <&a
3007 };
3008
3009 npu_noc: interconnect@9990000
3010 compatible = "qcom,sc
3011 reg = <0 0x09990000 0
3012 #interconnect-cells =
3013 qcom,bcm-voters = <&a
3014 };
3015
3016 usb_1: usb@a6f8800 {
3017 compatible = "qcom,sc
3018 reg = <0 0x0a6f8800 0
3019 status = "disabled";
3020 #address-cells = <2>;
3021 #size-cells = <2>;
3022 ranges;
3023 dma-ranges;
3024
3025 clocks = <&gcc GCC_CF
3026 <&gcc GCC_US
3027 <&gcc GCC_AG
3028 <&gcc GCC_US
3029 <&gcc GCC_US
3030 clock-names = "cfg_no
3031 "core",
3032 "iface"
3033 "sleep"
3034 "mock_u
3035
3036 assigned-clocks = <&g
3037 <&g
3038 assigned-clock-rates
3039
3040 interrupts-extended =
3041
3042
3043
3044
3045 interrupt-names = "pw
3046 "hs
3047 "dp
3048 "dm
3049 "ss
3050
3051 power-domains = <&gcc
3052 required-opps = <&rpm
3053
3054 resets = <&gcc GCC_US
3055
3056 interconnects = <&agg
3057 <&gem
3058 interconnect-names =
3059
3060 wakeup-source;
3061
3062 usb_1_dwc3: usb@a6000
3063 compatible =
3064 reg = <0 0x0a
3065 interrupts =
3066 iommus = <&ap
3067 snps,dis_u2_s
3068 snps,dis_enbl
3069 snps,parkmode
3070 phys = <&usb_
3071 phy-names = "
3072 maximum-speed
3073 };
3074 };
3075
3076 venus: video-codec@aa00000 {
3077 compatible = "qcom,sc
3078 reg = <0 0x0aa00000 0
3079 interrupts = <GIC_SPI
3080 power-domains = <&vid
3081 <&vid
3082 <&rpm
3083 power-domain-names =
3084 operating-points-v2 =
3085 clocks = <&videocc VI
3086 <&videocc VI
3087 <&videocc VI
3088 <&videocc VI
3089 <&videocc VI
3090 clock-names = "core",
3091 "vcodec
3092 iommus = <&apps_smmu
3093 memory-region = <&ven
3094 interconnects = <&mms
3095 <&gem
3096 interconnect-names =
3097
3098 video-decoder {
3099 compatible =
3100 };
3101
3102 video-encoder {
3103 compatible =
3104 };
3105
3106 venus_opp_table: opp-
3107 compatible =
3108
3109 opp-150000000
3110 opp-h
3111 requi
3112 };
3113
3114 opp-270000000
3115 opp-h
3116 requi
3117 };
3118
3119 opp-340000000
3120 opp-h
3121 requi
3122 };
3123
3124 opp-434000000
3125 opp-h
3126 requi
3127 };
3128
3129 opp-500000097
3130 opp-h
3131 requi
3132 };
3133 };
3134 };
3135
3136 videocc: clock-controller@ab0
3137 compatible = "qcom,sc
3138 reg = <0 0x0ab00000 0
3139 clocks = <&rpmhcc RPM
3140 clock-names = "bi_tcx
3141 #clock-cells = <1>;
3142 #reset-cells = <1>;
3143 #power-domain-cells =
3144 };
3145
3146 camnoc_virt: interconnect@ac0
3147 compatible = "qcom,sc
3148 reg = <0 0x0ac00000 0
3149 #interconnect-cells =
3150 qcom,bcm-voters = <&a
3151 };
3152
3153 camcc: clock-controller@ad000
3154 compatible = "qcom,sc
3155 reg = <0 0x0ad00000 0
3156 clocks = <&rpmhcc RPM
3157 <&gcc GCC_CAME
3158 <&gcc GCC_CAME
3159 clock-names = "bi_tcx
3160 #clock-cells = <1>;
3161 #reset-cells = <1>;
3162 #power-domain-cells =
3163 };
3164
3165 mdss: display-subsystem@ae000
3166 compatible = "qcom,sc
3167 reg = <0 0x0ae00000 0
3168 reg-names = "mdss";
3169
3170 power-domains = <&dis
3171
3172 clocks = <&gcc GCC_DI
3173 <&dispcc DIS
3174 <&dispcc DIS
3175 clock-names = "iface"
3176
3177 interrupts = <GIC_SPI
3178 interrupt-controller;
3179 #interrupt-cells = <1
3180
3181 interconnects = <&mms
3182 &mc_
3183 <&gem
3184 &con
3185 interconnect-names =
3186
3187
3188 iommus = <&apps_smmu
3189
3190 #address-cells = <2>;
3191 #size-cells = <2>;
3192 ranges;
3193
3194 status = "disabled";
3195
3196 mdp: display-controll
3197 compatible =
3198 reg = <0 0x0a
3199 <0 0x0a
3200 reg-names = "
3201
3202 clocks = <&gc
3203 <&di
3204 <&di
3205 <&di
3206 <&di
3207 <&di
3208 clock-names =
3209
3210 assigned-cloc
3211
3212
3213 assigned-cloc
3214
3215
3216 operating-poi
3217 power-domains
3218
3219 interrupt-par
3220 interrupts =
3221
3222 ports {
3223 #addr
3224 #size
3225
3226 port@
3227
3228
3229
3230
3231 };
3232
3233 port@
3234
3235
3236
3237
3238 };
3239 };
3240
3241 mdp_opp_table
3242 compa
3243
3244 opp-2
3245
3246
3247 };
3248
3249 opp-3
3250
3251
3252 };
3253
3254 opp-3
3255
3256
3257 };
3258
3259 opp-4
3260
3261
3262 };
3263 };
3264 };
3265
3266 mdss_dsi0: dsi@ae9400
3267 compatible =
3268
3269 reg = <0 0x0a
3270 reg-names = "
3271
3272 interrupt-par
3273 interrupts =
3274
3275 clocks = <&di
3276 <&di
3277 <&di
3278 <&di
3279 <&di
3280 <&gc
3281 clock-names =
3282
3283
3284
3285
3286
3287
3288 assigned-cloc
3289 assigned-cloc
3290
3291 operating-poi
3292 power-domains
3293
3294 phys = <&mdss
3295
3296 #address-cell
3297 #size-cells =
3298
3299 status = "dis
3300
3301 ports {
3302 #addr
3303 #size
3304
3305 port@
3306
3307
3308
3309
3310 };
3311
3312 port@
3313
3314
3315
3316 };
3317 };
3318
3319 dsi_opp_table
3320 compa
3321
3322 opp-1
3323
3324
3325 };
3326
3327 opp-3
3328
3329
3330 };
3331
3332 opp-3
3333
3334
3335 };
3336 };
3337 };
3338
3339 mdss_dsi0_phy: phy@ae
3340 compatible =
3341 reg = <0 0x0a
3342 <0 0x0a
3343 <0 0x0a
3344 reg-names = "
3345 "
3346 "
3347
3348 #clock-cells
3349 #phy-cells =
3350
3351 clocks = <&di
3352 <&rp
3353 clock-names =
3354
3355 status = "dis
3356 };
3357
3358 mdss_dp: displayport-
3359 compatible =
3360 status = "dis
3361
3362 reg = <0 0x0a
3363 <0 0x0a
3364 <0 0x0a
3365 <0 0x0a
3366 <0 0x0a
3367
3368 interrupt-par
3369 interrupts =
3370
3371 clocks = <&di
3372 <&di
3373 <&di
3374 <&di
3375 <&di
3376 clock-names =
3377
3378 assigned-cloc
3379
3380 assigned-cloc
3381
3382 phys = <&usb_
3383 phy-names = "
3384
3385 operating-poi
3386 power-domains
3387
3388 #sound-dai-ce
3389
3390 ports {
3391 #addr
3392 #size
3393 port@
3394
3395
3396
3397
3398 };
3399
3400 port@
3401
3402
3403 };
3404 };
3405
3406 dp_opp_table:
3407 compa
3408
3409 opp-1
3410
3411
3412 };
3413
3414 opp-2
3415
3416
3417 };
3418
3419 opp-5
3420
3421
3422 };
3423
3424 opp-8
3425
3426
3427 };
3428 };
3429 };
3430 };
3431
3432 dispcc: clock-controller@af00
3433 compatible = "qcom,sc
3434 reg = <0 0x0af00000 0
3435 clocks = <&rpmhcc RPM
3436 <&gcc GCC_DI
3437 <&mdss_dsi0_
3438 <&mdss_dsi0_
3439 <&usb_1_qmpp
3440 <&usb_1_qmpp
3441 clock-names = "bi_tcx
3442 "gcc_di
3443 "dsi0_p
3444 "dsi0_p
3445 "dp_phy
3446 "dp_phy
3447 #clock-cells = <1>;
3448 #reset-cells = <1>;
3449 #power-domain-cells =
3450 };
3451
3452 pdc: interrupt-controller@b22
3453 compatible = "qcom,sc
3454 reg = <0 0x0b220000 0
3455 qcom,pdc-ranges = <0
3456 #interrupt-cells = <2
3457 interrupt-parent = <&
3458 interrupt-controller;
3459 };
3460
3461 pdc_reset: reset-controller@b
3462 compatible = "qcom,sc
3463 reg = <0 0x0b2e0000 0
3464 #reset-cells = <1>;
3465 };
3466
3467 tsens0: thermal-sensor@c26300
3468 compatible = "qcom,sc
3469 reg = <0 0x0c263000 0
3470 <0 0x0c222000
3471 #qcom,sensors = <15>;
3472 interrupts = <GIC_SPI
3473 <GIC_SPI
3474 interrupt-names = "up
3475 #thermal-sensor-cells
3476 };
3477
3478 tsens1: thermal-sensor@c26500
3479 compatible = "qcom,sc
3480 reg = <0 0x0c265000 0
3481 <0 0x0c223000
3482 #qcom,sensors = <10>;
3483 interrupts = <GIC_SPI
3484 <GIC_SPI
3485 interrupt-names = "up
3486 #thermal-sensor-cells
3487 };
3488
3489 aoss_reset: reset-controller@
3490 compatible = "qcom,sc
3491 reg = <0 0x0c2a0000 0
3492 #reset-cells = <1>;
3493 };
3494
3495 aoss_qmp: power-management@c3
3496 compatible = "qcom,sc
3497 reg = <0 0x0c300000 0
3498 interrupts = <GIC_SPI
3499 mboxes = <&apss_share
3500
3501 #clock-cells = <0>;
3502 };
3503
3504 sram@c3f0000 {
3505 compatible = "qcom,rp
3506 reg = <0 0x0c3f0000 0
3507 };
3508
3509 spmi_bus: spmi@c440000 {
3510 compatible = "qcom,sp
3511 reg = <0 0x0c440000 0
3512 <0 0x0c600000 0
3513 <0 0x0e600000 0
3514 <0 0x0e700000 0
3515 <0 0x0c40a000 0
3516 reg-names = "core", "
3517 interrupt-names = "pe
3518 interrupts-extended =
3519 qcom,ee = <0>;
3520 qcom,channel = <0>;
3521 #address-cells = <2>;
3522 #size-cells = <0>;
3523 interrupt-controller;
3524 #interrupt-cells = <4
3525 };
3526
3527 sram@146aa000 {
3528 compatible = "qcom,sc
3529 reg = <0 0x146aa000 0
3530
3531 #address-cells = <1>;
3532 #size-cells = <1>;
3533
3534 ranges = <0 0 0x146aa
3535
3536 pil-reloc@94c {
3537 compatible =
3538 reg = <0x94c
3539 };
3540 };
3541
3542 apps_smmu: iommu@15000000 {
3543 compatible = "qcom,sc
3544 reg = <0 0x15000000 0
3545 #iommu-cells = <2>;
3546 #global-interrupts =
3547 interrupts = <GIC_SPI
3548 <GIC_SPI
3549 <GIC_SPI
3550 <GIC_SPI
3551 <GIC_SPI
3552 <GIC_SPI
3553 <GIC_SPI
3554 <GIC_SPI
3555 <GIC_SPI
3556 <GIC_SPI
3557 <GIC_SPI
3558 <GIC_SPI
3559 <GIC_SPI
3560 <GIC_SPI
3561 <GIC_SPI
3562 <GIC_SPI
3563 <GIC_SPI
3564 <GIC_SPI
3565 <GIC_SPI
3566 <GIC_SPI
3567 <GIC_SPI
3568 <GIC_SPI
3569 <GIC_SPI
3570 <GIC_SPI
3571 <GIC_SPI
3572 <GIC_SPI
3573 <GIC_SPI
3574 <GIC_SPI
3575 <GIC_SPI
3576 <GIC_SPI
3577 <GIC_SPI
3578 <GIC_SPI
3579 <GIC_SPI
3580 <GIC_SPI
3581 <GIC_SPI
3582 <GIC_SPI
3583 <GIC_SPI
3584 <GIC_SPI
3585 <GIC_SPI
3586 <GIC_SPI
3587 <GIC_SPI
3588 <GIC_SPI
3589 <GIC_SPI
3590 <GIC_SPI
3591 <GIC_SPI
3592 <GIC_SPI
3593 <GIC_SPI
3594 <GIC_SPI
3595 <GIC_SPI
3596 <GIC_SPI
3597 <GIC_SPI
3598 <GIC_SPI
3599 <GIC_SPI
3600 <GIC_SPI
3601 <GIC_SPI
3602 <GIC_SPI
3603 <GIC_SPI
3604 <GIC_SPI
3605 <GIC_SPI
3606 <GIC_SPI
3607 <GIC_SPI
3608 <GIC_SPI
3609 <GIC_SPI
3610 <GIC_SPI
3611 <GIC_SPI
3612 <GIC_SPI
3613 <GIC_SPI
3614 <GIC_SPI
3615 <GIC_SPI
3616 <GIC_SPI
3617 <GIC_SPI
3618 <GIC_SPI
3619 <GIC_SPI
3620 <GIC_SPI
3621 <GIC_SPI
3622 <GIC_SPI
3623 <GIC_SPI
3624 <GIC_SPI
3625 <GIC_SPI
3626 <GIC_SPI
3627 <GIC_SPI
3628 };
3629
3630 intc: interrupt-controller@17
3631 compatible = "arm,gic
3632 #address-cells = <2>;
3633 #size-cells = <2>;
3634 ranges;
3635 #interrupt-cells = <3
3636 interrupt-controller;
3637 reg = <0 0x17a00000 0
3638 <0 0x17a60000 0
3639 interrupts = <GIC_PPI
3640
3641 msi-controller@17a400
3642 compatible =
3643 msi-controlle
3644 #msi-cells =
3645 reg = <0 0x17
3646 status = "dis
3647 };
3648 };
3649
3650 apss_shared: mailbox@17c00000
3651 compatible = "qcom,sc
3652 "qcom,sd
3653 reg = <0 0x17c00000 0
3654 #mbox-cells = <1>;
3655 };
3656
3657 watchdog@17c10000 {
3658 compatible = "qcom,ap
3659 reg = <0 0x17c10000 0
3660 clocks = <&sleep_clk>
3661 interrupts = <GIC_SPI
3662 };
3663
3664 timer@17c20000 {
3665 #address-cells = <1>;
3666 #size-cells = <1>;
3667 ranges = <0 0 0 0x200
3668 compatible = "arm,arm
3669 reg = <0 0x17c20000 0
3670
3671 frame@17c21000 {
3672 frame-number
3673 interrupts =
3674
3675 reg = <0x17c2
3676 <0x17c2
3677 };
3678
3679 frame@17c23000 {
3680 frame-number
3681 interrupts =
3682 reg = <0x17c2
3683 status = "dis
3684 };
3685
3686 frame@17c25000 {
3687 frame-number
3688 interrupts =
3689 reg = <0x17c2
3690 status = "dis
3691 };
3692
3693 frame@17c27000 {
3694 frame-number
3695 interrupts =
3696 reg = <0x17c2
3697 status = "dis
3698 };
3699
3700 frame@17c29000 {
3701 frame-number
3702 interrupts =
3703 reg = <0x17c2
3704 status = "dis
3705 };
3706
3707 frame@17c2b000 {
3708 frame-number
3709 interrupts =
3710 reg = <0x17c2
3711 status = "dis
3712 };
3713
3714 frame@17c2d000 {
3715 frame-number
3716 interrupts =
3717 reg = <0x17c2
3718 status = "dis
3719 };
3720 };
3721
3722 apps_rsc: rsc@18200000 {
3723 compatible = "qcom,rp
3724 reg = <0 0x18200000 0
3725 <0 0x18210000 0
3726 <0 0x18220000 0
3727 reg-names = "drv-0",
3728 interrupts = <GIC_SPI
3729 <GIC_SPI
3730 <GIC_SPI
3731 qcom,tcs-offset = <0x
3732 qcom,drv-id = <2>;
3733 qcom,tcs-config = <AC
3734 <SL
3735 <WA
3736 <CO
3737 power-domains = <&CLU
3738
3739 rpmhcc: clock-control
3740 compatible =
3741 clocks = <&xo
3742 clock-names =
3743 #clock-cells
3744 };
3745
3746 rpmhpd: power-control
3747 compatible =
3748 #power-domain
3749 operating-poi
3750
3751 rpmhpd_opp_ta
3752 compa
3753
3754 rpmhp
3755
3756 };
3757
3758 rpmhp
3759
3760 };
3761
3762 rpmhp
3763
3764 };
3765
3766 rpmhp
3767
3768 };
3769
3770 rpmhp
3771
3772 };
3773
3774 rpmhp
3775
3776 };
3777
3778 rpmhp
3779
3780 };
3781
3782 rpmhp
3783
3784 };
3785
3786 rpmhp
3787
3788 };
3789
3790 rpmhp
3791
3792 };
3793
3794 rpmhp
3795
3796 };
3797 };
3798 };
3799
3800 apps_bcm_voter: bcm-v
3801 compatible =
3802 };
3803 };
3804
3805 osm_l3: interconnect@18321000
3806 compatible = "qcom,sc
3807 reg = <0 0x18321000 0
3808
3809 clocks = <&rpmhcc RPM
3810 clock-names = "xo", "
3811
3812 #interconnect-cells =
3813 };
3814
3815 cpufreq_hw: cpufreq@18323000
3816 compatible = "qcom,sc
3817 reg = <0 0x18323000 0
3818 reg-names = "freq-dom
3819
3820 clocks = <&rpmhcc RPM
3821 clock-names = "xo", "
3822
3823 #freq-domain-cells =
3824 #clock-cells = <1>;
3825 };
3826
3827 wifi: wifi@18800000 {
3828 compatible = "qcom,wc
3829 reg = <0 0x18800000 0
3830 reg-names = "membase"
3831 iommus = <&apps_smmu
3832 interrupts =
3833 <GIC_SPI 414
3834 <GIC_SPI 415
3835 <GIC_SPI 416
3836 <GIC_SPI 417
3837 <GIC_SPI 418
3838 <GIC_SPI 419
3839 <GIC_SPI 420
3840 <GIC_SPI 421
3841 <GIC_SPI 422
3842 <GIC_SPI 423
3843 <GIC_SPI 424
3844 <GIC_SPI 425
3845 memory-region = <&wla
3846 qcom,msa-fixed-perm;
3847 status = "disabled";
3848 };
3849
3850 remoteproc_adsp: remoteproc@6
3851 compatible = "qcom,sc
3852 reg = <0 0x62400000 0
3853
3854 interrupts-extended =
3855
3856
3857
3858
3859 interrupt-names = "wd
3860 "fa
3861 "re
3862 "ha
3863 "st
3864
3865 clocks = <&rpmhcc RPM
3866 clock-names = "xo";
3867
3868 power-domains = <&rpm
3869 <&rpm
3870 power-domain-names =
3871
3872 qcom,qmp = <&aoss_qmp
3873 qcom,smem-states = <&
3874 qcom,smem-state-names
3875
3876 status = "disabled";
3877
3878 glink-edge {
3879 interrupts =
3880 label = "lpas
3881 qcom,remote-p
3882 mboxes = <&ap
3883
3884 apr {
3885 compa
3886 qcom,
3887 qcom,
3888 #addr
3889 #size
3890
3891 servi
3892
3893
3894
3895 };
3896
3897 q6afe
3898
3899
3900
3901
3902
3903
3904
3905
3906
3907
3908
3909
3910
3911
3912
3913 };
3914
3915 q6asm
3916
3917
3918
3919
3920
3921
3922
3923
3924
3925
3926
3927 };
3928
3929 q6adm
3930
3931
3932
3933
3934
3935
3936
3937
3938 };
3939 };
3940
3941 fastrpc {
3942 compa
3943 qcom,
3944 label
3945 #addr
3946 #size
3947
3948 compu
3949
3950
3951
3952 };
3953
3954 compu
3955
3956
3957
3958 };
3959
3960 compu
3961
3962
3963
3964
3965 };
3966 };
3967 };
3968 };
3969
3970 lpasscc: clock-controller@62d
3971 compatible = "qcom,sc
3972 reg = <0 0x62d00000 0
3973 <0 0x62780000 0
3974 reg-names = "lpass_co
3975 clocks = <&gcc GCC_LP
3976 <&rpmhcc RPM
3977 clock-names = "iface"
3978 power-domains = <&lpa
3979 #clock-cells = <1>;
3980 #power-domain-cells =
3981
3982 status = "reserved";
3983 };
3984
3985 lpass_cpu: lpass@62d87000 {
3986 compatible = "qcom,sc
3987
3988 reg = <0 0x62d87000 0
3989 reg-names = "lpass-hd
3990
3991 iommus = <&apps_smmu
3992 <&apps_smmu 0
3993 <&apps_smmu 0
3994
3995 power-domains = <&lpa
3996 required-opps = <&rpm
3997
3998 status = "disabled";
3999
4000 clocks = <&gcc GCC_LP
4001 <&lpasscc LP
4002 <&lpasscc LP
4003 <&lpasscc LP
4004 <&lpasscc LP
4005 <&lpasscc LP
4006
4007 clock-names = "pcnoc-
4008 "mclk
4009 "mi2s
4010
4011
4012 #sound-dai-cells = <1
4013 #address-cells = <1>;
4014 #size-cells = <0>;
4015
4016 interrupts = <GIC_SPI
4017 <GIC_
4018 interrupt-names = "lp
4019 };
4020
4021 lpass_hm: clock-controller@63
4022 compatible = "qcom,sc
4023 reg = <0 0x63000000 0
4024 clocks = <&gcc GCC_LP
4025 <&rpmhcc RPM
4026 clock-names = "iface"
4027 power-domains = <&rpm
4028
4029 #clock-cells = <1>;
4030 #power-domain-cells =
4031
4032 status = "reserved";
4033 };
4034 };
4035
4036 thermal-zones {
4037 cpu0_thermal: cpu0-thermal {
4038 polling-delay-passive
4039
4040 thermal-sensors = <&t
4041 sustainable-power = <
4042
4043 trips {
4044 cpu0_alert0:
4045 tempe
4046 hyste
4047 type
4048 };
4049
4050 cpu0_alert1:
4051 tempe
4052 hyste
4053 type
4054 };
4055
4056 cpu0_crit: cp
4057 tempe
4058 hyste
4059 type
4060 };
4061 };
4062
4063 cooling-maps {
4064 map0 {
4065 trip
4066 cooli
4067
4068
4069
4070
4071
4072 };
4073 map1 {
4074 trip
4075 cooli
4076
4077
4078
4079
4080
4081 };
4082 };
4083 };
4084
4085 cpu1_thermal: cpu1-thermal {
4086 polling-delay-passive
4087
4088 thermal-sensors = <&t
4089 sustainable-power = <
4090
4091 trips {
4092 cpu1_alert0:
4093 tempe
4094 hyste
4095 type
4096 };
4097
4098 cpu1_alert1:
4099 tempe
4100 hyste
4101 type
4102 };
4103
4104 cpu1_crit: cp
4105 tempe
4106 hyste
4107 type
4108 };
4109 };
4110
4111 cooling-maps {
4112 map0 {
4113 trip
4114 cooli
4115
4116
4117
4118
4119
4120 };
4121 map1 {
4122 trip
4123 cooli
4124
4125
4126
4127
4128
4129 };
4130 };
4131 };
4132
4133 cpu2_thermal: cpu2-thermal {
4134 polling-delay-passive
4135
4136 thermal-sensors = <&t
4137 sustainable-power = <
4138
4139 trips {
4140 cpu2_alert0:
4141 tempe
4142 hyste
4143 type
4144 };
4145
4146 cpu2_alert1:
4147 tempe
4148 hyste
4149 type
4150 };
4151
4152 cpu2_crit: cp
4153 tempe
4154 hyste
4155 type
4156 };
4157 };
4158
4159 cooling-maps {
4160 map0 {
4161 trip
4162 cooli
4163
4164
4165
4166
4167
4168 };
4169 map1 {
4170 trip
4171 cooli
4172
4173
4174
4175
4176
4177 };
4178 };
4179 };
4180
4181 cpu3_thermal: cpu3-thermal {
4182 polling-delay-passive
4183
4184 thermal-sensors = <&t
4185 sustainable-power = <
4186
4187 trips {
4188 cpu3_alert0:
4189 tempe
4190 hyste
4191 type
4192 };
4193
4194 cpu3_alert1:
4195 tempe
4196 hyste
4197 type
4198 };
4199
4200 cpu3_crit: cp
4201 tempe
4202 hyste
4203 type
4204 };
4205 };
4206
4207 cooling-maps {
4208 map0 {
4209 trip
4210 cooli
4211
4212
4213
4214
4215
4216 };
4217 map1 {
4218 trip
4219 cooli
4220
4221
4222
4223
4224
4225 };
4226 };
4227 };
4228
4229 cpu4_thermal: cpu4-thermal {
4230 polling-delay-passive
4231
4232 thermal-sensors = <&t
4233 sustainable-power = <
4234
4235 trips {
4236 cpu4_alert0:
4237 tempe
4238 hyste
4239 type
4240 };
4241
4242 cpu4_alert1:
4243 tempe
4244 hyste
4245 type
4246 };
4247
4248 cpu4_crit: cp
4249 tempe
4250 hyste
4251 type
4252 };
4253 };
4254
4255 cooling-maps {
4256 map0 {
4257 trip
4258 cooli
4259
4260
4261
4262
4263
4264 };
4265 map1 {
4266 trip
4267 cooli
4268
4269
4270
4271
4272
4273 };
4274 };
4275 };
4276
4277 cpu5_thermal: cpu5-thermal {
4278 polling-delay-passive
4279
4280 thermal-sensors = <&t
4281 sustainable-power = <
4282
4283 trips {
4284 cpu5_alert0:
4285 tempe
4286 hyste
4287 type
4288 };
4289
4290 cpu5_alert1:
4291 tempe
4292 hyste
4293 type
4294 };
4295
4296 cpu5_crit: cp
4297 tempe
4298 hyste
4299 type
4300 };
4301 };
4302
4303 cooling-maps {
4304 map0 {
4305 trip
4306 cooli
4307
4308
4309
4310
4311
4312 };
4313 map1 {
4314 trip
4315 cooli
4316
4317
4318
4319
4320
4321 };
4322 };
4323 };
4324
4325 cpu6_thermal: cpu6-thermal {
4326 polling-delay-passive
4327
4328 thermal-sensors = <&t
4329 sustainable-power = <
4330
4331 trips {
4332 cpu6_alert0:
4333 tempe
4334 hyste
4335 type
4336 };
4337
4338 cpu6_alert1:
4339 tempe
4340 hyste
4341 type
4342 };
4343
4344 cpu6_crit: cp
4345 tempe
4346 hyste
4347 type
4348 };
4349 };
4350
4351 cooling-maps {
4352 map0 {
4353 trip
4354 cooli
4355
4356 };
4357 map1 {
4358 trip
4359 cooli
4360
4361 };
4362 };
4363 };
4364
4365 cpu7_thermal: cpu7-thermal {
4366 polling-delay-passive
4367
4368 thermal-sensors = <&t
4369 sustainable-power = <
4370
4371 trips {
4372 cpu7_alert0:
4373 tempe
4374 hyste
4375 type
4376 };
4377
4378 cpu7_alert1:
4379 tempe
4380 hyste
4381 type
4382 };
4383
4384 cpu7_crit: cp
4385 tempe
4386 hyste
4387 type
4388 };
4389 };
4390
4391 cooling-maps {
4392 map0 {
4393 trip
4394 cooli
4395
4396 };
4397 map1 {
4398 trip
4399 cooli
4400
4401 };
4402 };
4403 };
4404
4405 cpu8_thermal: cpu8-thermal {
4406 polling-delay-passive
4407
4408 thermal-sensors = <&t
4409 sustainable-power = <
4410
4411 trips {
4412 cpu8_alert0:
4413 tempe
4414 hyste
4415 type
4416 };
4417
4418 cpu8_alert1:
4419 tempe
4420 hyste
4421 type
4422 };
4423
4424 cpu8_crit: cp
4425 tempe
4426 hyste
4427 type
4428 };
4429 };
4430
4431 cooling-maps {
4432 map0 {
4433 trip
4434 cooli
4435
4436 };
4437 map1 {
4438 trip
4439 cooli
4440
4441 };
4442 };
4443 };
4444
4445 cpu9_thermal: cpu9-thermal {
4446 polling-delay-passive
4447
4448 thermal-sensors = <&t
4449 sustainable-power = <
4450
4451 trips {
4452 cpu9_alert0:
4453 tempe
4454 hyste
4455 type
4456 };
4457
4458 cpu9_alert1:
4459 tempe
4460 hyste
4461 type
4462 };
4463
4464 cpu9_crit: cp
4465 tempe
4466 hyste
4467 type
4468 };
4469 };
4470
4471 cooling-maps {
4472 map0 {
4473 trip
4474 cooli
4475
4476 };
4477 map1 {
4478 trip
4479 cooli
4480
4481 };
4482 };
4483 };
4484
4485 aoss0-thermal {
4486 polling-delay-passive
4487
4488 thermal-sensors = <&t
4489
4490 trips {
4491 aoss0_alert0:
4492 tempe
4493 hyste
4494 type
4495 };
4496
4497 aoss0_crit: a
4498 tempe
4499 hyste
4500 type
4501 };
4502 };
4503 };
4504
4505 cpuss0-thermal {
4506 polling-delay-passive
4507
4508 thermal-sensors = <&t
4509
4510 trips {
4511 cpuss0_alert0
4512 tempe
4513 hyste
4514 type
4515 };
4516 cpuss0_crit:
4517 tempe
4518 hyste
4519 type
4520 };
4521 };
4522 };
4523
4524 cpuss1-thermal {
4525 polling-delay-passive
4526
4527 thermal-sensors = <&t
4528
4529 trips {
4530 cpuss1_alert0
4531 tempe
4532 hyste
4533 type
4534 };
4535 cpuss1_crit:
4536 tempe
4537 hyste
4538 type
4539 };
4540 };
4541 };
4542
4543 gpuss0-thermal {
4544 polling-delay-passive
4545
4546 thermal-sensors = <&t
4547
4548 trips {
4549 gpuss0_alert0
4550 tempe
4551 hyste
4552 type
4553 };
4554
4555 gpuss0_crit:
4556 tempe
4557 hyste
4558 type
4559 };
4560 };
4561
4562 cooling-maps {
4563 map0 {
4564 trip
4565 cooli
4566 };
4567 };
4568 };
4569
4570 gpuss1-thermal {
4571 polling-delay-passive
4572
4573 thermal-sensors = <&t
4574
4575 trips {
4576 gpuss1_alert0
4577 tempe
4578 hyste
4579 type
4580 };
4581
4582 gpuss1_crit:
4583 tempe
4584 hyste
4585 type
4586 };
4587 };
4588
4589 cooling-maps {
4590 map0 {
4591 trip
4592 cooli
4593 };
4594 };
4595 };
4596
4597 aoss1-thermal {
4598 polling-delay-passive
4599
4600 thermal-sensors = <&t
4601
4602 trips {
4603 aoss1_alert0:
4604 tempe
4605 hyste
4606 type
4607 };
4608
4609 aoss1_crit: a
4610 tempe
4611 hyste
4612 type
4613 };
4614 };
4615 };
4616
4617 cwlan-thermal {
4618 polling-delay-passive
4619
4620 thermal-sensors = <&t
4621
4622 trips {
4623 cwlan_alert0:
4624 tempe
4625 hyste
4626 type
4627 };
4628
4629 cwlan_crit: c
4630 tempe
4631 hyste
4632 type
4633 };
4634 };
4635 };
4636
4637 audio-thermal {
4638 polling-delay-passive
4639
4640 thermal-sensors = <&t
4641
4642 trips {
4643 audio_alert0:
4644 tempe
4645 hyste
4646 type
4647 };
4648
4649 audio_crit: a
4650 tempe
4651 hyste
4652 type
4653 };
4654 };
4655 };
4656
4657 ddr-thermal {
4658 polling-delay-passive
4659
4660 thermal-sensors = <&t
4661
4662 trips {
4663 ddr_alert0: t
4664 tempe
4665 hyste
4666 type
4667 };
4668
4669 ddr_crit: ddr
4670 tempe
4671 hyste
4672 type
4673 };
4674 };
4675 };
4676
4677 q6-hvx-thermal {
4678 polling-delay-passive
4679
4680 thermal-sensors = <&t
4681
4682 trips {
4683 q6_hvx_alert0
4684 tempe
4685 hyste
4686 type
4687 };
4688
4689 q6_hvx_crit:
4690 tempe
4691 hyste
4692 type
4693 };
4694 };
4695 };
4696
4697 camera-thermal {
4698 polling-delay-passive
4699
4700 thermal-sensors = <&t
4701
4702 trips {
4703 camera_alert0
4704 tempe
4705 hyste
4706 type
4707 };
4708
4709 camera_crit:
4710 tempe
4711 hyste
4712 type
4713 };
4714 };
4715 };
4716
4717 mdm-core-thermal {
4718 polling-delay-passive
4719
4720 thermal-sensors = <&t
4721
4722 trips {
4723 mdm_alert0: t
4724 tempe
4725 hyste
4726 type
4727 };
4728
4729 mdm_crit: mdm
4730 tempe
4731 hyste
4732 type
4733 };
4734 };
4735 };
4736
4737 mdm-dsp-thermal {
4738 polling-delay-passive
4739
4740 thermal-sensors = <&t
4741
4742 trips {
4743 mdm_dsp_alert
4744 tempe
4745 hyste
4746 type
4747 };
4748
4749 mdm_dsp_crit:
4750 tempe
4751 hyste
4752 type
4753 };
4754 };
4755 };
4756
4757 npu-thermal {
4758 polling-delay-passive
4759
4760 thermal-sensors = <&t
4761
4762 trips {
4763 npu_alert0: t
4764 tempe
4765 hyste
4766 type
4767 };
4768
4769 npu_crit: npu
4770 tempe
4771 hyste
4772 type
4773 };
4774 };
4775 };
4776
4777 video-thermal {
4778 polling-delay-passive
4779
4780 thermal-sensors = <&t
4781
4782 trips {
4783 video_alert0:
4784 tempe
4785 hyste
4786 type
4787 };
4788
4789 video_crit: v
4790 tempe
4791 hyste
4792 type
4793 };
4794 };
4795 };
4796 };
4797
4798 timer {
4799 compatible = "arm,armv8-timer
4800 interrupts = <GIC_PPI 1 IRQ_T
4801 <GIC_PPI 2 IRQ_T
4802 <GIC_PPI 3 IRQ_T
4803 <GIC_PPI 0 IRQ_T
4804 };
4805 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.