1 // SPDX-License-Identifier: BSD-3-Clause 1 // SPDX-License-Identifier: BSD-3-Clause
2 /* 2 /*
3 * SC7180 SoC device tree source 3 * SC7180 SoC device tree source
4 * 4 *
5 * Copyright (c) 2019-2020, The Linux Foundati 5 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
6 */ 6 */
7 7
8 #include <dt-bindings/clock/qcom,dispcc-sc7180 8 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
9 #include <dt-bindings/clock/qcom,gcc-sc7180.h> 9 #include <dt-bindings/clock/qcom,gcc-sc7180.h>
10 #include <dt-bindings/clock/qcom,gpucc-sc7180. 10 #include <dt-bindings/clock/qcom,gpucc-sc7180.h>
11 #include <dt-bindings/clock/qcom,lpasscorecc-s 11 #include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h>
12 #include <dt-bindings/clock/qcom,rpmh.h> 12 #include <dt-bindings/clock/qcom,rpmh.h>
13 #include <dt-bindings/clock/qcom,videocc-sc718 13 #include <dt-bindings/clock/qcom,videocc-sc7180.h>
14 #include <dt-bindings/firmware/qcom,scm.h> <<
15 #include <dt-bindings/interconnect/qcom,icc.h> <<
16 #include <dt-bindings/interconnect/qcom,osm-l3 14 #include <dt-bindings/interconnect/qcom,osm-l3.h>
17 #include <dt-bindings/interconnect/qcom,sc7180 15 #include <dt-bindings/interconnect/qcom,sc7180.h>
18 #include <dt-bindings/interrupt-controller/arm 16 #include <dt-bindings/interrupt-controller/arm-gic.h>
19 #include <dt-bindings/phy/phy-qcom-qmp.h> <<
20 #include <dt-bindings/phy/phy-qcom-qusb2.h> 17 #include <dt-bindings/phy/phy-qcom-qusb2.h>
>> 18 #include <dt-bindings/power/qcom-aoss-qmp.h>
21 #include <dt-bindings/power/qcom-rpmpd.h> 19 #include <dt-bindings/power/qcom-rpmpd.h>
22 #include <dt-bindings/reset/qcom,sdm845-aoss.h 20 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
23 #include <dt-bindings/reset/qcom,sdm845-pdc.h> 21 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
24 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 22 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
25 #include <dt-bindings/soc/qcom,apr.h> <<
26 #include <dt-bindings/sound/qcom,q6afe.h> <<
27 #include <dt-bindings/thermal/thermal.h> 23 #include <dt-bindings/thermal/thermal.h>
28 24
29 / { 25 / {
30 interrupt-parent = <&intc>; 26 interrupt-parent = <&intc>;
31 27
32 #address-cells = <2>; 28 #address-cells = <2>;
33 #size-cells = <2>; 29 #size-cells = <2>;
34 30
>> 31 chosen { };
>> 32
35 aliases { 33 aliases {
36 mmc1 = &sdhc_1; 34 mmc1 = &sdhc_1;
37 mmc2 = &sdhc_2; 35 mmc2 = &sdhc_2;
38 i2c0 = &i2c0; 36 i2c0 = &i2c0;
39 i2c1 = &i2c1; 37 i2c1 = &i2c1;
40 i2c2 = &i2c2; 38 i2c2 = &i2c2;
41 i2c3 = &i2c3; 39 i2c3 = &i2c3;
42 i2c4 = &i2c4; 40 i2c4 = &i2c4;
43 i2c5 = &i2c5; 41 i2c5 = &i2c5;
44 i2c6 = &i2c6; 42 i2c6 = &i2c6;
45 i2c7 = &i2c7; 43 i2c7 = &i2c7;
46 i2c8 = &i2c8; 44 i2c8 = &i2c8;
47 i2c9 = &i2c9; 45 i2c9 = &i2c9;
48 i2c10 = &i2c10; 46 i2c10 = &i2c10;
49 i2c11 = &i2c11; 47 i2c11 = &i2c11;
50 spi0 = &spi0; 48 spi0 = &spi0;
51 spi1 = &spi1; 49 spi1 = &spi1;
52 spi3 = &spi3; 50 spi3 = &spi3;
53 spi5 = &spi5; 51 spi5 = &spi5;
54 spi6 = &spi6; 52 spi6 = &spi6;
55 spi8 = &spi8; 53 spi8 = &spi8;
56 spi10 = &spi10; 54 spi10 = &spi10;
57 spi11 = &spi11; 55 spi11 = &spi11;
58 }; 56 };
59 57
60 chosen { }; <<
61 <<
62 clocks { 58 clocks {
63 xo_board: xo-board { 59 xo_board: xo-board {
64 compatible = "fixed-cl 60 compatible = "fixed-clock";
65 clock-frequency = <384 61 clock-frequency = <38400000>;
66 #clock-cells = <0>; 62 #clock-cells = <0>;
67 }; 63 };
68 64
69 sleep_clk: sleep-clk { 65 sleep_clk: sleep-clk {
70 compatible = "fixed-cl 66 compatible = "fixed-clock";
71 clock-frequency = <327 67 clock-frequency = <32764>;
72 #clock-cells = <0>; 68 #clock-cells = <0>;
73 }; 69 };
74 }; 70 };
75 71
>> 72 reserved_memory: reserved-memory {
>> 73 #address-cells = <2>;
>> 74 #size-cells = <2>;
>> 75 ranges;
>> 76
>> 77 hyp_mem: memory@80000000 {
>> 78 reg = <0x0 0x80000000 0x0 0x600000>;
>> 79 no-map;
>> 80 };
>> 81
>> 82 xbl_mem: memory@80600000 {
>> 83 reg = <0x0 0x80600000 0x0 0x200000>;
>> 84 no-map;
>> 85 };
>> 86
>> 87 aop_mem: memory@80800000 {
>> 88 reg = <0x0 0x80800000 0x0 0x20000>;
>> 89 no-map;
>> 90 };
>> 91
>> 92 aop_cmd_db_mem: memory@80820000 {
>> 93 reg = <0x0 0x80820000 0x0 0x20000>;
>> 94 compatible = "qcom,cmd-db";
>> 95 no-map;
>> 96 };
>> 97
>> 98 sec_apps_mem: memory@808ff000 {
>> 99 reg = <0x0 0x808ff000 0x0 0x1000>;
>> 100 no-map;
>> 101 };
>> 102
>> 103 smem_mem: memory@80900000 {
>> 104 reg = <0x0 0x80900000 0x0 0x200000>;
>> 105 no-map;
>> 106 };
>> 107
>> 108 tz_mem: memory@80b00000 {
>> 109 reg = <0x0 0x80b00000 0x0 0x3900000>;
>> 110 no-map;
>> 111 };
>> 112
>> 113 rmtfs_mem: memory@84400000 {
>> 114 compatible = "qcom,rmtfs-mem";
>> 115 reg = <0x0 0x84400000 0x0 0x200000>;
>> 116 no-map;
>> 117
>> 118 qcom,client-id = <1>;
>> 119 qcom,vmid = <15>;
>> 120 };
>> 121 };
>> 122
76 cpus { 123 cpus {
77 #address-cells = <2>; 124 #address-cells = <2>;
78 #size-cells = <0>; 125 #size-cells = <0>;
79 126
80 CPU0: cpu@0 { 127 CPU0: cpu@0 {
81 device_type = "cpu"; 128 device_type = "cpu";
82 compatible = "qcom,kry 129 compatible = "qcom,kryo468";
83 reg = <0x0 0x0>; 130 reg = <0x0 0x0>;
84 clocks = <&cpufreq_hw <<
85 enable-method = "psci" 131 enable-method = "psci";
86 power-domains = <&CPU_ !! 132 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
87 power-domain-names = " !! 133 &LITTLE_CPU_SLEEP_1
88 capacity-dmips-mhz = < !! 134 &CLUSTER_SLEEP_0>;
89 dynamic-power-coeffici !! 135 capacity-dmips-mhz = <1024>;
>> 136 dynamic-power-coefficient = <100>;
90 operating-points-v2 = 137 operating-points-v2 = <&cpu0_opp_table>;
91 interconnects = <&gem_ 138 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
92 <&osm_ 139 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
93 next-level-cache = <&L 140 next-level-cache = <&L2_0>;
94 #cooling-cells = <2>; 141 #cooling-cells = <2>;
95 qcom,freq-domain = <&c 142 qcom,freq-domain = <&cpufreq_hw 0>;
96 L2_0: l2-cache { 143 L2_0: l2-cache {
97 compatible = " 144 compatible = "cache";
98 cache-level = <<
99 cache-unified; <<
100 next-level-cac 145 next-level-cache = <&L3_0>;
101 L3_0: l3-cache 146 L3_0: l3-cache {
102 compat 147 compatible = "cache";
103 cache- <<
104 cache- <<
105 }; 148 };
106 }; 149 };
107 }; 150 };
108 151
109 CPU1: cpu@100 { 152 CPU1: cpu@100 {
110 device_type = "cpu"; 153 device_type = "cpu";
111 compatible = "qcom,kry 154 compatible = "qcom,kryo468";
112 reg = <0x0 0x100>; 155 reg = <0x0 0x100>;
113 clocks = <&cpufreq_hw <<
114 enable-method = "psci" 156 enable-method = "psci";
115 power-domains = <&CPU_ !! 157 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
116 power-domain-names = " !! 158 &LITTLE_CPU_SLEEP_1
117 capacity-dmips-mhz = < !! 159 &CLUSTER_SLEEP_0>;
118 dynamic-power-coeffici !! 160 capacity-dmips-mhz = <1024>;
>> 161 dynamic-power-coefficient = <100>;
119 next-level-cache = <&L 162 next-level-cache = <&L2_100>;
120 operating-points-v2 = 163 operating-points-v2 = <&cpu0_opp_table>;
121 interconnects = <&gem_ 164 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
122 <&osm_ 165 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
123 #cooling-cells = <2>; 166 #cooling-cells = <2>;
124 qcom,freq-domain = <&c 167 qcom,freq-domain = <&cpufreq_hw 0>;
125 L2_100: l2-cache { 168 L2_100: l2-cache {
126 compatible = " 169 compatible = "cache";
127 cache-level = <<
128 cache-unified; <<
129 next-level-cac 170 next-level-cache = <&L3_0>;
130 }; 171 };
131 }; 172 };
132 173
133 CPU2: cpu@200 { 174 CPU2: cpu@200 {
134 device_type = "cpu"; 175 device_type = "cpu";
135 compatible = "qcom,kry 176 compatible = "qcom,kryo468";
136 reg = <0x0 0x200>; 177 reg = <0x0 0x200>;
137 clocks = <&cpufreq_hw <<
138 enable-method = "psci" 178 enable-method = "psci";
139 power-domains = <&CPU_ !! 179 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
140 power-domain-names = " !! 180 &LITTLE_CPU_SLEEP_1
141 capacity-dmips-mhz = < !! 181 &CLUSTER_SLEEP_0>;
142 dynamic-power-coeffici !! 182 capacity-dmips-mhz = <1024>;
>> 183 dynamic-power-coefficient = <100>;
143 next-level-cache = <&L 184 next-level-cache = <&L2_200>;
144 operating-points-v2 = 185 operating-points-v2 = <&cpu0_opp_table>;
145 interconnects = <&gem_ 186 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
146 <&osm_ 187 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
147 #cooling-cells = <2>; 188 #cooling-cells = <2>;
148 qcom,freq-domain = <&c 189 qcom,freq-domain = <&cpufreq_hw 0>;
149 L2_200: l2-cache { 190 L2_200: l2-cache {
150 compatible = " 191 compatible = "cache";
151 cache-level = <<
152 cache-unified; <<
153 next-level-cac 192 next-level-cache = <&L3_0>;
154 }; 193 };
155 }; 194 };
156 195
157 CPU3: cpu@300 { 196 CPU3: cpu@300 {
158 device_type = "cpu"; 197 device_type = "cpu";
159 compatible = "qcom,kry 198 compatible = "qcom,kryo468";
160 reg = <0x0 0x300>; 199 reg = <0x0 0x300>;
161 clocks = <&cpufreq_hw <<
162 enable-method = "psci" 200 enable-method = "psci";
163 power-domains = <&CPU_ !! 201 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
164 power-domain-names = " !! 202 &LITTLE_CPU_SLEEP_1
165 capacity-dmips-mhz = < !! 203 &CLUSTER_SLEEP_0>;
166 dynamic-power-coeffici !! 204 capacity-dmips-mhz = <1024>;
>> 205 dynamic-power-coefficient = <100>;
167 next-level-cache = <&L 206 next-level-cache = <&L2_300>;
168 operating-points-v2 = 207 operating-points-v2 = <&cpu0_opp_table>;
169 interconnects = <&gem_ 208 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
170 <&osm_ 209 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
171 #cooling-cells = <2>; 210 #cooling-cells = <2>;
172 qcom,freq-domain = <&c 211 qcom,freq-domain = <&cpufreq_hw 0>;
173 L2_300: l2-cache { 212 L2_300: l2-cache {
174 compatible = " 213 compatible = "cache";
175 cache-level = <<
176 cache-unified; <<
177 next-level-cac 214 next-level-cache = <&L3_0>;
178 }; 215 };
179 }; 216 };
180 217
181 CPU4: cpu@400 { 218 CPU4: cpu@400 {
182 device_type = "cpu"; 219 device_type = "cpu";
183 compatible = "qcom,kry 220 compatible = "qcom,kryo468";
184 reg = <0x0 0x400>; 221 reg = <0x0 0x400>;
185 clocks = <&cpufreq_hw <<
186 enable-method = "psci" 222 enable-method = "psci";
187 power-domains = <&CPU_ !! 223 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
188 power-domain-names = " !! 224 &LITTLE_CPU_SLEEP_1
189 capacity-dmips-mhz = < !! 225 &CLUSTER_SLEEP_0>;
190 dynamic-power-coeffici !! 226 capacity-dmips-mhz = <1024>;
>> 227 dynamic-power-coefficient = <100>;
191 next-level-cache = <&L 228 next-level-cache = <&L2_400>;
192 operating-points-v2 = 229 operating-points-v2 = <&cpu0_opp_table>;
193 interconnects = <&gem_ 230 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
194 <&osm_ 231 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
195 #cooling-cells = <2>; 232 #cooling-cells = <2>;
196 qcom,freq-domain = <&c 233 qcom,freq-domain = <&cpufreq_hw 0>;
197 L2_400: l2-cache { 234 L2_400: l2-cache {
198 compatible = " 235 compatible = "cache";
199 cache-level = <<
200 cache-unified; <<
201 next-level-cac 236 next-level-cache = <&L3_0>;
202 }; 237 };
203 }; 238 };
204 239
205 CPU5: cpu@500 { 240 CPU5: cpu@500 {
206 device_type = "cpu"; 241 device_type = "cpu";
207 compatible = "qcom,kry 242 compatible = "qcom,kryo468";
208 reg = <0x0 0x500>; 243 reg = <0x0 0x500>;
209 clocks = <&cpufreq_hw <<
210 enable-method = "psci" 244 enable-method = "psci";
211 power-domains = <&CPU_ !! 245 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
212 power-domain-names = " !! 246 &LITTLE_CPU_SLEEP_1
213 capacity-dmips-mhz = < !! 247 &CLUSTER_SLEEP_0>;
214 dynamic-power-coeffici !! 248 capacity-dmips-mhz = <1024>;
>> 249 dynamic-power-coefficient = <100>;
215 next-level-cache = <&L 250 next-level-cache = <&L2_500>;
216 operating-points-v2 = 251 operating-points-v2 = <&cpu0_opp_table>;
217 interconnects = <&gem_ 252 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
218 <&osm_ 253 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
219 #cooling-cells = <2>; 254 #cooling-cells = <2>;
220 qcom,freq-domain = <&c 255 qcom,freq-domain = <&cpufreq_hw 0>;
221 L2_500: l2-cache { 256 L2_500: l2-cache {
222 compatible = " 257 compatible = "cache";
223 cache-level = <<
224 cache-unified; <<
225 next-level-cac 258 next-level-cache = <&L3_0>;
226 }; 259 };
227 }; 260 };
228 261
229 CPU6: cpu@600 { 262 CPU6: cpu@600 {
230 device_type = "cpu"; 263 device_type = "cpu";
231 compatible = "qcom,kry 264 compatible = "qcom,kryo468";
232 reg = <0x0 0x600>; 265 reg = <0x0 0x600>;
233 clocks = <&cpufreq_hw <<
234 enable-method = "psci" 266 enable-method = "psci";
235 power-domains = <&CPU_ !! 267 cpu-idle-states = <&BIG_CPU_SLEEP_0
236 power-domain-names = " !! 268 &BIG_CPU_SLEEP_1
237 capacity-dmips-mhz = < !! 269 &CLUSTER_SLEEP_0>;
238 dynamic-power-coeffici !! 270 capacity-dmips-mhz = <1740>;
>> 271 dynamic-power-coefficient = <405>;
239 next-level-cache = <&L 272 next-level-cache = <&L2_600>;
240 operating-points-v2 = 273 operating-points-v2 = <&cpu6_opp_table>;
241 interconnects = <&gem_ 274 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
242 <&osm_ 275 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
243 #cooling-cells = <2>; 276 #cooling-cells = <2>;
244 qcom,freq-domain = <&c 277 qcom,freq-domain = <&cpufreq_hw 1>;
245 L2_600: l2-cache { 278 L2_600: l2-cache {
246 compatible = " 279 compatible = "cache";
247 cache-level = <<
248 cache-unified; <<
249 next-level-cac 280 next-level-cache = <&L3_0>;
250 }; 281 };
251 }; 282 };
252 283
253 CPU7: cpu@700 { 284 CPU7: cpu@700 {
254 device_type = "cpu"; 285 device_type = "cpu";
255 compatible = "qcom,kry 286 compatible = "qcom,kryo468";
256 reg = <0x0 0x700>; 287 reg = <0x0 0x700>;
257 clocks = <&cpufreq_hw <<
258 enable-method = "psci" 288 enable-method = "psci";
259 power-domains = <&CPU_ !! 289 cpu-idle-states = <&BIG_CPU_SLEEP_0
260 power-domain-names = " !! 290 &BIG_CPU_SLEEP_1
261 capacity-dmips-mhz = < !! 291 &CLUSTER_SLEEP_0>;
262 dynamic-power-coeffici !! 292 capacity-dmips-mhz = <1740>;
>> 293 dynamic-power-coefficient = <405>;
263 next-level-cache = <&L 294 next-level-cache = <&L2_700>;
264 operating-points-v2 = 295 operating-points-v2 = <&cpu6_opp_table>;
265 interconnects = <&gem_ 296 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
266 <&osm_ 297 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
267 #cooling-cells = <2>; 298 #cooling-cells = <2>;
268 qcom,freq-domain = <&c 299 qcom,freq-domain = <&cpufreq_hw 1>;
269 L2_700: l2-cache { 300 L2_700: l2-cache {
270 compatible = " 301 compatible = "cache";
271 cache-level = <<
272 cache-unified; <<
273 next-level-cac 302 next-level-cache = <&L3_0>;
274 }; 303 };
275 }; 304 };
276 305
277 cpu-map { 306 cpu-map {
278 cluster0 { 307 cluster0 {
279 core0 { 308 core0 {
280 cpu = 309 cpu = <&CPU0>;
281 }; 310 };
282 311
283 core1 { 312 core1 {
284 cpu = 313 cpu = <&CPU1>;
285 }; 314 };
286 315
287 core2 { 316 core2 {
288 cpu = 317 cpu = <&CPU2>;
289 }; 318 };
290 319
291 core3 { 320 core3 {
292 cpu = 321 cpu = <&CPU3>;
293 }; 322 };
294 323
295 core4 { 324 core4 {
296 cpu = 325 cpu = <&CPU4>;
297 }; 326 };
298 327
299 core5 { 328 core5 {
300 cpu = 329 cpu = <&CPU5>;
301 }; 330 };
302 331
303 core6 { 332 core6 {
304 cpu = 333 cpu = <&CPU6>;
305 }; 334 };
306 335
307 core7 { 336 core7 {
308 cpu = 337 cpu = <&CPU7>;
309 }; 338 };
310 }; 339 };
311 }; 340 };
312 341
313 idle_states: idle-states { !! 342 idle-states {
314 entry-method = "psci"; 343 entry-method = "psci";
315 344
316 LITTLE_CPU_SLEEP_0: cp 345 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
317 compatible = " 346 compatible = "arm,idle-state";
318 idle-state-nam 347 idle-state-name = "little-power-down";
319 arm,psci-suspe 348 arm,psci-suspend-param = <0x40000003>;
320 entry-latency- 349 entry-latency-us = <549>;
321 exit-latency-u 350 exit-latency-us = <901>;
322 min-residency- 351 min-residency-us = <1774>;
323 local-timer-st 352 local-timer-stop;
324 }; 353 };
325 354
326 LITTLE_CPU_SLEEP_1: cp 355 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
327 compatible = " 356 compatible = "arm,idle-state";
328 idle-state-nam 357 idle-state-name = "little-rail-power-down";
329 arm,psci-suspe 358 arm,psci-suspend-param = <0x40000004>;
330 entry-latency- 359 entry-latency-us = <702>;
331 exit-latency-u 360 exit-latency-us = <915>;
332 min-residency- 361 min-residency-us = <4001>;
333 local-timer-st 362 local-timer-stop;
334 }; 363 };
335 364
336 BIG_CPU_SLEEP_0: cpu-s 365 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
337 compatible = " 366 compatible = "arm,idle-state";
338 idle-state-nam 367 idle-state-name = "big-power-down";
339 arm,psci-suspe 368 arm,psci-suspend-param = <0x40000003>;
340 entry-latency- 369 entry-latency-us = <523>;
341 exit-latency-u 370 exit-latency-us = <1244>;
342 min-residency- 371 min-residency-us = <2207>;
343 local-timer-st 372 local-timer-stop;
344 }; 373 };
345 374
346 BIG_CPU_SLEEP_1: cpu-s 375 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
347 compatible = " 376 compatible = "arm,idle-state";
348 idle-state-nam 377 idle-state-name = "big-rail-power-down";
349 arm,psci-suspe 378 arm,psci-suspend-param = <0x40000004>;
350 entry-latency- 379 entry-latency-us = <526>;
351 exit-latency-u 380 exit-latency-us = <1854>;
352 min-residency- 381 min-residency-us = <5555>;
353 local-timer-st 382 local-timer-stop;
354 }; 383 };
355 }; <<
356 <<
357 domain_idle_states: domain-idl <<
358 CLUSTER_SLEEP_PC: clus <<
359 compatible = " <<
360 idle-state-nam <<
361 arm,psci-suspe <<
362 entry-latency- <<
363 exit-latency-u <<
364 min-residency- <<
365 }; <<
366 <<
367 CLUSTER_SLEEP_CX_RET: <<
368 compatible = " <<
369 idle-state-nam <<
370 arm,psci-suspe <<
371 entry-latency- <<
372 exit-latency-u <<
373 min-residency- <<
374 }; <<
375 384
376 CLUSTER_AOSS_SLEEP: cl !! 385 CLUSTER_SLEEP_0: cluster-sleep-0 {
377 compatible = " !! 386 compatible = "arm,idle-state";
378 idle-state-nam 387 idle-state-name = "cluster-power-down";
379 arm,psci-suspe !! 388 arm,psci-suspend-param = <0x40003444>;
380 entry-latency- 389 entry-latency-us = <3263>;
381 exit-latency-u 390 exit-latency-us = <6562>;
382 min-residency- !! 391 min-residency-us = <9926>;
>> 392 local-timer-stop;
383 }; 393 };
384 }; 394 };
385 }; 395 };
386 396
387 firmware { !! 397 cpu0_opp_table: cpu0_opp_table {
388 scm: scm { <<
389 compatible = "qcom,scm <<
390 }; <<
391 }; <<
392 <<
393 memory@80000000 { <<
394 device_type = "memory"; <<
395 /* We expect the bootloader to <<
396 reg = <0 0x80000000 0 0>; <<
397 }; <<
398 <<
399 cpu0_opp_table: opp-table-cpu0 { <<
400 compatible = "operating-points 398 compatible = "operating-points-v2";
401 opp-shared; 399 opp-shared;
402 400
403 cpu0_opp1: opp-300000000 { 401 cpu0_opp1: opp-300000000 {
404 opp-hz = /bits/ 64 <30 402 opp-hz = /bits/ 64 <300000000>;
405 opp-peak-kBps = <12000 403 opp-peak-kBps = <1200000 4800000>;
406 }; 404 };
407 405
408 cpu0_opp2: opp-576000000 { 406 cpu0_opp2: opp-576000000 {
409 opp-hz = /bits/ 64 <57 407 opp-hz = /bits/ 64 <576000000>;
410 opp-peak-kBps = <12000 408 opp-peak-kBps = <1200000 4800000>;
411 }; 409 };
412 410
413 cpu0_opp3: opp-768000000 { 411 cpu0_opp3: opp-768000000 {
414 opp-hz = /bits/ 64 <76 412 opp-hz = /bits/ 64 <768000000>;
415 opp-peak-kBps = <12000 413 opp-peak-kBps = <1200000 4800000>;
416 }; 414 };
417 415
418 cpu0_opp4: opp-1017600000 { 416 cpu0_opp4: opp-1017600000 {
419 opp-hz = /bits/ 64 <10 417 opp-hz = /bits/ 64 <1017600000>;
420 opp-peak-kBps = <18040 418 opp-peak-kBps = <1804000 8908800>;
421 }; 419 };
422 420
423 cpu0_opp5: opp-1248000000 { 421 cpu0_opp5: opp-1248000000 {
424 opp-hz = /bits/ 64 <12 422 opp-hz = /bits/ 64 <1248000000>;
425 opp-peak-kBps = <21880 423 opp-peak-kBps = <2188000 12902400>;
426 }; 424 };
427 425
428 cpu0_opp6: opp-1324800000 { 426 cpu0_opp6: opp-1324800000 {
429 opp-hz = /bits/ 64 <13 427 opp-hz = /bits/ 64 <1324800000>;
430 opp-peak-kBps = <21880 428 opp-peak-kBps = <2188000 12902400>;
431 }; 429 };
432 430
433 cpu0_opp7: opp-1516800000 { 431 cpu0_opp7: opp-1516800000 {
434 opp-hz = /bits/ 64 <15 432 opp-hz = /bits/ 64 <1516800000>;
435 opp-peak-kBps = <30720 433 opp-peak-kBps = <3072000 15052800>;
436 }; 434 };
437 435
438 cpu0_opp8: opp-1612800000 { 436 cpu0_opp8: opp-1612800000 {
439 opp-hz = /bits/ 64 <16 437 opp-hz = /bits/ 64 <1612800000>;
440 opp-peak-kBps = <30720 438 opp-peak-kBps = <3072000 15052800>;
441 }; 439 };
442 440
443 cpu0_opp9: opp-1708800000 { 441 cpu0_opp9: opp-1708800000 {
444 opp-hz = /bits/ 64 <17 442 opp-hz = /bits/ 64 <1708800000>;
445 opp-peak-kBps = <30720 443 opp-peak-kBps = <3072000 15052800>;
446 }; 444 };
447 445
448 cpu0_opp10: opp-1804800000 { 446 cpu0_opp10: opp-1804800000 {
449 opp-hz = /bits/ 64 <18 447 opp-hz = /bits/ 64 <1804800000>;
450 opp-peak-kBps = <40680 448 opp-peak-kBps = <4068000 22425600>;
451 }; 449 };
452 }; 450 };
453 451
454 cpu6_opp_table: opp-table-cpu6 { !! 452 cpu6_opp_table: cpu6_opp_table {
455 compatible = "operating-points 453 compatible = "operating-points-v2";
456 opp-shared; 454 opp-shared;
457 455
458 cpu6_opp1: opp-300000000 { 456 cpu6_opp1: opp-300000000 {
459 opp-hz = /bits/ 64 <30 457 opp-hz = /bits/ 64 <300000000>;
460 opp-peak-kBps = <21880 458 opp-peak-kBps = <2188000 8908800>;
461 }; 459 };
462 460
463 cpu6_opp2: opp-652800000 { 461 cpu6_opp2: opp-652800000 {
464 opp-hz = /bits/ 64 <65 462 opp-hz = /bits/ 64 <652800000>;
465 opp-peak-kBps = <21880 463 opp-peak-kBps = <2188000 8908800>;
466 }; 464 };
467 465
468 cpu6_opp3: opp-825600000 { 466 cpu6_opp3: opp-825600000 {
469 opp-hz = /bits/ 64 <82 467 opp-hz = /bits/ 64 <825600000>;
470 opp-peak-kBps = <21880 468 opp-peak-kBps = <2188000 8908800>;
471 }; 469 };
472 470
473 cpu6_opp4: opp-979200000 { 471 cpu6_opp4: opp-979200000 {
474 opp-hz = /bits/ 64 <97 472 opp-hz = /bits/ 64 <979200000>;
475 opp-peak-kBps = <21880 473 opp-peak-kBps = <2188000 8908800>;
476 }; 474 };
477 475
478 cpu6_opp5: opp-1113600000 { 476 cpu6_opp5: opp-1113600000 {
479 opp-hz = /bits/ 64 <11 477 opp-hz = /bits/ 64 <1113600000>;
480 opp-peak-kBps = <21880 478 opp-peak-kBps = <2188000 8908800>;
481 }; 479 };
482 480
483 cpu6_opp6: opp-1267200000 { 481 cpu6_opp6: opp-1267200000 {
484 opp-hz = /bits/ 64 <12 482 opp-hz = /bits/ 64 <1267200000>;
485 opp-peak-kBps = <40680 483 opp-peak-kBps = <4068000 12902400>;
486 }; 484 };
487 485
488 cpu6_opp7: opp-1555200000 { 486 cpu6_opp7: opp-1555200000 {
489 opp-hz = /bits/ 64 <15 487 opp-hz = /bits/ 64 <1555200000>;
490 opp-peak-kBps = <40680 488 opp-peak-kBps = <4068000 15052800>;
491 }; 489 };
492 490
493 cpu6_opp8: opp-1708800000 { 491 cpu6_opp8: opp-1708800000 {
494 opp-hz = /bits/ 64 <17 492 opp-hz = /bits/ 64 <1708800000>;
495 opp-peak-kBps = <62200 493 opp-peak-kBps = <6220000 19353600>;
496 }; 494 };
497 495
498 cpu6_opp9: opp-1843200000 { 496 cpu6_opp9: opp-1843200000 {
499 opp-hz = /bits/ 64 <18 497 opp-hz = /bits/ 64 <1843200000>;
500 opp-peak-kBps = <62200 498 opp-peak-kBps = <6220000 19353600>;
501 }; 499 };
502 500
503 cpu6_opp10: opp-1900800000 { 501 cpu6_opp10: opp-1900800000 {
504 opp-hz = /bits/ 64 <19 502 opp-hz = /bits/ 64 <1900800000>;
505 opp-peak-kBps = <62200 503 opp-peak-kBps = <6220000 22425600>;
506 }; 504 };
507 505
508 cpu6_opp11: opp-1996800000 { 506 cpu6_opp11: opp-1996800000 {
509 opp-hz = /bits/ 64 <19 507 opp-hz = /bits/ 64 <1996800000>;
510 opp-peak-kBps = <62200 508 opp-peak-kBps = <6220000 22425600>;
511 }; 509 };
512 510
513 cpu6_opp12: opp-2112000000 { 511 cpu6_opp12: opp-2112000000 {
514 opp-hz = /bits/ 64 <21 512 opp-hz = /bits/ 64 <2112000000>;
515 opp-peak-kBps = <62200 513 opp-peak-kBps = <6220000 22425600>;
516 }; 514 };
517 515
518 cpu6_opp13: opp-2208000000 { 516 cpu6_opp13: opp-2208000000 {
519 opp-hz = /bits/ 64 <22 517 opp-hz = /bits/ 64 <2208000000>;
520 opp-peak-kBps = <72160 518 opp-peak-kBps = <7216000 22425600>;
521 }; 519 };
522 520
523 cpu6_opp14: opp-2323200000 { 521 cpu6_opp14: opp-2323200000 {
524 opp-hz = /bits/ 64 <23 522 opp-hz = /bits/ 64 <2323200000>;
525 opp-peak-kBps = <72160 523 opp-peak-kBps = <7216000 22425600>;
526 }; 524 };
527 525
528 cpu6_opp15: opp-2400000000 { 526 cpu6_opp15: opp-2400000000 {
529 opp-hz = /bits/ 64 <24 527 opp-hz = /bits/ 64 <2400000000>;
530 opp-peak-kBps = <85320 528 opp-peak-kBps = <8532000 23347200>;
531 }; 529 };
532 530
533 cpu6_opp16: opp-2553600000 { 531 cpu6_opp16: opp-2553600000 {
534 opp-hz = /bits/ 64 <25 532 opp-hz = /bits/ 64 <2553600000>;
535 opp-peak-kBps = <85320 533 opp-peak-kBps = <8532000 23347200>;
536 }; 534 };
537 }; 535 };
538 536
539 qspi_opp_table: opp-table-qspi { !! 537 memory@80000000 {
540 compatible = "operating-points !! 538 device_type = "memory";
541 !! 539 /* We expect the bootloader to fill in the size */
542 opp-75000000 { !! 540 reg = <0 0x80000000 0 0>;
543 opp-hz = /bits/ 64 <75 <<
544 required-opps = <&rpmh <<
545 }; <<
546 <<
547 opp-150000000 { <<
548 opp-hz = /bits/ 64 <15 <<
549 required-opps = <&rpmh <<
550 }; <<
551 <<
552 opp-300000000 { <<
553 opp-hz = /bits/ 64 <30 <<
554 required-opps = <&rpmh <<
555 }; <<
556 }; <<
557 <<
558 qup_opp_table: opp-table-qup { <<
559 compatible = "operating-points <<
560 <<
561 opp-75000000 { <<
562 opp-hz = /bits/ 64 <75 <<
563 required-opps = <&rpmh <<
564 }; <<
565 <<
566 opp-100000000 { <<
567 opp-hz = /bits/ 64 <10 <<
568 required-opps = <&rpmh <<
569 }; <<
570 <<
571 opp-128000000 { <<
572 opp-hz = /bits/ 64 <12 <<
573 required-opps = <&rpmh <<
574 }; <<
575 }; 541 };
576 542
577 pmu { 543 pmu {
578 compatible = "arm,armv8-pmuv3" 544 compatible = "arm,armv8-pmuv3";
579 interrupts = <GIC_PPI 5 IRQ_TY 545 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
580 }; 546 };
581 547
582 psci { !! 548 firmware {
583 compatible = "arm,psci-1.0"; !! 549 scm {
584 method = "smc"; !! 550 compatible = "qcom,scm-sc7180", "qcom,scm";
585 <<
586 CPU_PD0: cpu0 { <<
587 #power-domain-cells = <<
588 power-domains = <&CLUS <<
589 domain-idle-states = < <<
590 }; <<
591 <<
592 CPU_PD1: cpu1 { <<
593 #power-domain-cells = <<
594 power-domains = <&CLUS <<
595 domain-idle-states = < <<
596 }; <<
597 <<
598 CPU_PD2: cpu2 { <<
599 #power-domain-cells = <<
600 power-domains = <&CLUS <<
601 domain-idle-states = < <<
602 }; <<
603 <<
604 CPU_PD3: cpu3 { <<
605 #power-domain-cells = <<
606 power-domains = <&CLUS <<
607 domain-idle-states = < <<
608 }; <<
609 <<
610 CPU_PD4: cpu4 { <<
611 #power-domain-cells = <<
612 power-domains = <&CLUS <<
613 domain-idle-states = < <<
614 }; <<
615 <<
616 CPU_PD5: cpu5 { <<
617 #power-domain-cells = <<
618 power-domains = <&CLUS <<
619 domain-idle-states = < <<
620 }; <<
621 <<
622 CPU_PD6: cpu6 { <<
623 #power-domain-cells = <<
624 power-domains = <&CLUS <<
625 domain-idle-states = < <<
626 }; <<
627 <<
628 CPU_PD7: cpu7 { <<
629 #power-domain-cells = <<
630 power-domains = <&CLUS <<
631 domain-idle-states = < <<
632 }; <<
633 <<
634 CLUSTER_PD: cpu-cluster0 { <<
635 #power-domain-cells = <<
636 domain-idle-states = < <<
637 <<
638 <<
639 }; 551 };
640 }; 552 };
641 553
642 reserved_memory: reserved-memory { !! 554 tcsr_mutex: hwlock {
643 #address-cells = <2>; !! 555 compatible = "qcom,tcsr-mutex";
644 #size-cells = <2>; !! 556 syscon = <&tcsr_mutex_regs 0 0x1000>;
645 ranges; !! 557 #hwlock-cells = <1>;
646 <<
647 hyp_mem: memory@80000000 { <<
648 reg = <0x0 0x80000000 <<
649 no-map; <<
650 }; <<
651 <<
652 xbl_mem: memory@80600000 { <<
653 reg = <0x0 0x80600000 <<
654 no-map; <<
655 }; <<
656 <<
657 aop_mem: memory@80800000 { <<
658 reg = <0x0 0x80800000 <<
659 no-map; <<
660 }; <<
661 <<
662 aop_cmd_db_mem: memory@8082000 <<
663 reg = <0x0 0x80820000 <<
664 compatible = "qcom,cmd <<
665 no-map; <<
666 }; <<
667 <<
668 sec_apps_mem: memory@808ff000 <<
669 reg = <0x0 0x808ff000 <<
670 no-map; <<
671 }; <<
672 <<
673 smem_mem: memory@80900000 { <<
674 reg = <0x0 0x80900000 <<
675 no-map; <<
676 }; <<
677 <<
678 tz_mem: memory@80b00000 { <<
679 reg = <0x0 0x80b00000 <<
680 no-map; <<
681 }; <<
682 <<
683 ipa_fw_mem: memory@8b700000 { <<
684 reg = <0 0x8b700000 0 <<
685 no-map; <<
686 }; <<
687 <<
688 rmtfs_mem: memory@94600000 { <<
689 compatible = "qcom,rmt <<
690 reg = <0x0 0x94600000 <<
691 no-map; <<
692 <<
693 qcom,client-id = <1>; <<
694 qcom,vmid = <QCOM_SCM_ <<
695 }; <<
696 }; 558 };
697 559
698 smem { 560 smem {
699 compatible = "qcom,smem"; 561 compatible = "qcom,smem";
700 memory-region = <&smem_mem>; 562 memory-region = <&smem_mem>;
701 hwlocks = <&tcsr_mutex 3>; 563 hwlocks = <&tcsr_mutex 3>;
702 }; 564 };
703 565
704 smp2p-cdsp { 566 smp2p-cdsp {
705 compatible = "qcom,smp2p"; 567 compatible = "qcom,smp2p";
706 qcom,smem = <94>, <432>; 568 qcom,smem = <94>, <432>;
707 569
708 interrupts = <GIC_SPI 576 IRQ_ 570 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
709 571
710 mboxes = <&apss_shared 6>; 572 mboxes = <&apss_shared 6>;
711 573
712 qcom,local-pid = <0>; 574 qcom,local-pid = <0>;
713 qcom,remote-pid = <5>; 575 qcom,remote-pid = <5>;
714 576
715 cdsp_smp2p_out: master-kernel 577 cdsp_smp2p_out: master-kernel {
716 qcom,entry-name = "mas 578 qcom,entry-name = "master-kernel";
717 #qcom,smem-state-cells 579 #qcom,smem-state-cells = <1>;
718 }; 580 };
719 581
720 cdsp_smp2p_in: slave-kernel { 582 cdsp_smp2p_in: slave-kernel {
721 qcom,entry-name = "sla 583 qcom,entry-name = "slave-kernel";
722 584
723 interrupt-controller; 585 interrupt-controller;
724 #interrupt-cells = <2> 586 #interrupt-cells = <2>;
725 }; 587 };
726 }; 588 };
727 589
728 smp2p-lpass { 590 smp2p-lpass {
729 compatible = "qcom,smp2p"; 591 compatible = "qcom,smp2p";
730 qcom,smem = <443>, <429>; 592 qcom,smem = <443>, <429>;
731 593
732 interrupts = <GIC_SPI 158 IRQ_ 594 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
733 595
734 mboxes = <&apss_shared 10>; 596 mboxes = <&apss_shared 10>;
735 597
736 qcom,local-pid = <0>; 598 qcom,local-pid = <0>;
737 qcom,remote-pid = <2>; 599 qcom,remote-pid = <2>;
738 600
739 adsp_smp2p_out: master-kernel 601 adsp_smp2p_out: master-kernel {
740 qcom,entry-name = "mas 602 qcom,entry-name = "master-kernel";
741 #qcom,smem-state-cells 603 #qcom,smem-state-cells = <1>;
742 }; 604 };
743 605
744 adsp_smp2p_in: slave-kernel { 606 adsp_smp2p_in: slave-kernel {
745 qcom,entry-name = "sla 607 qcom,entry-name = "slave-kernel";
746 608
747 interrupt-controller; 609 interrupt-controller;
748 #interrupt-cells = <2> 610 #interrupt-cells = <2>;
749 }; 611 };
750 }; 612 };
751 613
752 smp2p-mpss { 614 smp2p-mpss {
753 compatible = "qcom,smp2p"; 615 compatible = "qcom,smp2p";
754 qcom,smem = <435>, <428>; 616 qcom,smem = <435>, <428>;
755 interrupts = <GIC_SPI 451 IRQ_ 617 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
756 mboxes = <&apss_shared 14>; 618 mboxes = <&apss_shared 14>;
757 qcom,local-pid = <0>; 619 qcom,local-pid = <0>;
758 qcom,remote-pid = <1>; 620 qcom,remote-pid = <1>;
759 621
760 modem_smp2p_out: master-kernel 622 modem_smp2p_out: master-kernel {
761 qcom,entry-name = "mas 623 qcom,entry-name = "master-kernel";
762 #qcom,smem-state-cells 624 #qcom,smem-state-cells = <1>;
763 }; 625 };
764 626
765 modem_smp2p_in: slave-kernel { 627 modem_smp2p_in: slave-kernel {
766 qcom,entry-name = "sla 628 qcom,entry-name = "slave-kernel";
767 interrupt-controller; 629 interrupt-controller;
768 #interrupt-cells = <2> 630 #interrupt-cells = <2>;
769 }; 631 };
770 632
771 ipa_smp2p_out: ipa-ap-to-modem 633 ipa_smp2p_out: ipa-ap-to-modem {
772 qcom,entry-name = "ipa 634 qcom,entry-name = "ipa";
773 #qcom,smem-state-cells 635 #qcom,smem-state-cells = <1>;
774 }; 636 };
775 637
776 ipa_smp2p_in: ipa-modem-to-ap 638 ipa_smp2p_in: ipa-modem-to-ap {
777 qcom,entry-name = "ipa 639 qcom,entry-name = "ipa";
778 interrupt-controller; 640 interrupt-controller;
779 #interrupt-cells = <2> 641 #interrupt-cells = <2>;
780 }; 642 };
781 }; 643 };
782 644
>> 645 psci {
>> 646 compatible = "arm,psci-1.0";
>> 647 method = "smc";
>> 648 };
>> 649
783 soc: soc@0 { 650 soc: soc@0 {
784 #address-cells = <2>; 651 #address-cells = <2>;
785 #size-cells = <2>; 652 #size-cells = <2>;
786 ranges = <0 0 0 0 0x10 0>; 653 ranges = <0 0 0 0 0x10 0>;
787 dma-ranges = <0 0 0 0 0x10 0>; 654 dma-ranges = <0 0 0 0 0x10 0>;
788 compatible = "simple-bus"; 655 compatible = "simple-bus";
789 656
790 gcc: clock-controller@100000 { 657 gcc: clock-controller@100000 {
791 compatible = "qcom,gcc 658 compatible = "qcom,gcc-sc7180";
792 reg = <0 0x00100000 0 659 reg = <0 0x00100000 0 0x1f0000>;
793 clocks = <&rpmhcc RPMH 660 clocks = <&rpmhcc RPMH_CXO_CLK>,
794 <&rpmhcc RPMH 661 <&rpmhcc RPMH_CXO_CLK_A>,
795 <&sleep_clk>; 662 <&sleep_clk>;
796 clock-names = "bi_tcxo 663 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
797 #clock-cells = <1>; 664 #clock-cells = <1>;
798 #reset-cells = <1>; 665 #reset-cells = <1>;
799 #power-domain-cells = 666 #power-domain-cells = <1>;
800 power-domains = <&rpmh <<
801 }; 667 };
802 668
803 qfprom: efuse@784000 { 669 qfprom: efuse@784000 {
804 compatible = "qcom,sc7 670 compatible = "qcom,sc7180-qfprom", "qcom,qfprom";
805 reg = <0 0x00784000 0 !! 671 reg = <0 0x00784000 0 0x8ff>,
806 <0 0x00780000 0 672 <0 0x00780000 0 0x7a0>,
807 <0 0x00782000 0 673 <0 0x00782000 0 0x100>,
808 <0 0x00786000 0 674 <0 0x00786000 0 0x1fff>;
809 675
810 clocks = <&gcc GCC_SEC 676 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>;
811 clock-names = "core"; 677 clock-names = "core";
812 #address-cells = <1>; 678 #address-cells = <1>;
813 #size-cells = <1>; 679 #size-cells = <1>;
814 680
815 qusb2p_hstx_trim: hstx 681 qusb2p_hstx_trim: hstx-trim-primary@25b {
816 reg = <0x25b 0 682 reg = <0x25b 0x1>;
817 bits = <1 3>; 683 bits = <1 3>;
818 }; 684 };
819 <<
820 gpu_speed_bin: gpu-spe <<
821 reg = <0x1d2 0 <<
822 bits = <5 8>; <<
823 }; <<
824 }; 685 };
825 686
826 sdhc_1: mmc@7c4000 { !! 687 sdhc_1: sdhci@7c4000 {
827 compatible = "qcom,sc7 688 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
828 reg = <0 0x007c4000 0 !! 689 reg = <0 0x7c4000 0 0x1000>,
829 <0 0x007c5000 !! 690 <0 0x07c5000 0 0x1000>;
830 reg-names = "hc", "cqh 691 reg-names = "hc", "cqhci";
831 692
832 iommus = <&apps_smmu 0 693 iommus = <&apps_smmu 0x60 0x0>;
833 interrupts = <GIC_SPI 694 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
834 <GIC_S 695 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
835 interrupt-names = "hc_ 696 interrupt-names = "hc_irq", "pwr_irq";
836 697
837 clocks = <&gcc GCC_SDC !! 698 clocks = <&gcc GCC_SDCC1_APPS_CLK>,
838 <&gcc GCC_SDC !! 699 <&gcc GCC_SDCC1_AHB_CLK>;
839 <&rpmhcc RPMH !! 700 clock-names = "core", "iface";
840 clock-names = "iface", <<
841 interconnects = <&aggr 701 interconnects = <&aggre1_noc MASTER_EMMC 0 &mc_virt SLAVE_EBI1 0>,
842 <&gem_ 702 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_EMMC_CFG 0>;
843 interconnect-names = " 703 interconnect-names = "sdhc-ddr","cpu-sdhc";
844 power-domains = <&rpmh 704 power-domains = <&rpmhpd SC7180_CX>;
845 operating-points-v2 = 705 operating-points-v2 = <&sdhc1_opp_table>;
846 706
847 bus-width = <8>; 707 bus-width = <8>;
848 non-removable; 708 non-removable;
849 supports-cqe; 709 supports-cqe;
850 710
851 mmc-ddr-1_8v; 711 mmc-ddr-1_8v;
852 mmc-hs200-1_8v; 712 mmc-hs200-1_8v;
853 mmc-hs400-1_8v; 713 mmc-hs400-1_8v;
854 mmc-hs400-enhanced-str 714 mmc-hs400-enhanced-strobe;
855 715
856 status = "disabled"; 716 status = "disabled";
857 717
858 sdhc1_opp_table: opp-t !! 718 sdhc1_opp_table: sdhc1-opp-table {
859 compatible = " 719 compatible = "operating-points-v2";
860 720
861 opp-100000000 721 opp-100000000 {
862 opp-hz 722 opp-hz = /bits/ 64 <100000000>;
863 requir 723 required-opps = <&rpmhpd_opp_low_svs>;
864 opp-pe !! 724 opp-peak-kBps = <100000 100000>;
865 opp-av !! 725 opp-avg-kBps = <100000 50000>;
866 }; 726 };
867 727
868 opp-384000000 728 opp-384000000 {
869 opp-hz 729 opp-hz = /bits/ 64 <384000000>;
870 requir !! 730 required-opps = <&rpmhpd_opp_svs_l1>;
871 opp-pe !! 731 opp-peak-kBps = <600000 900000>;
872 opp-av !! 732 opp-avg-kBps = <261438 300000>;
873 }; 733 };
874 }; 734 };
875 }; 735 };
876 736
>> 737 qup_opp_table: qup-opp-table {
>> 738 compatible = "operating-points-v2";
>> 739
>> 740 opp-75000000 {
>> 741 opp-hz = /bits/ 64 <75000000>;
>> 742 required-opps = <&rpmhpd_opp_low_svs>;
>> 743 };
>> 744
>> 745 opp-100000000 {
>> 746 opp-hz = /bits/ 64 <100000000>;
>> 747 required-opps = <&rpmhpd_opp_svs>;
>> 748 };
>> 749
>> 750 opp-128000000 {
>> 751 opp-hz = /bits/ 64 <128000000>;
>> 752 required-opps = <&rpmhpd_opp_nom>;
>> 753 };
>> 754 };
>> 755
877 qupv3_id_0: geniqup@8c0000 { 756 qupv3_id_0: geniqup@8c0000 {
878 compatible = "qcom,gen 757 compatible = "qcom,geni-se-qup";
879 reg = <0 0x008c0000 0 758 reg = <0 0x008c0000 0 0x6000>;
880 clock-names = "m-ahb", 759 clock-names = "m-ahb", "s-ahb";
881 clocks = <&gcc GCC_QUP 760 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
882 <&gcc GCC_QUP 761 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
883 #address-cells = <2>; 762 #address-cells = <2>;
884 #size-cells = <2>; 763 #size-cells = <2>;
885 ranges; 764 ranges;
886 iommus = <&apps_smmu 0 765 iommus = <&apps_smmu 0x43 0x0>;
>> 766 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>;
>> 767 interconnect-names = "qup-core";
887 status = "disabled"; 768 status = "disabled";
888 769
889 i2c0: i2c@880000 { 770 i2c0: i2c@880000 {
890 compatible = " 771 compatible = "qcom,geni-i2c";
891 reg = <0 0x008 772 reg = <0 0x00880000 0 0x4000>;
892 clock-names = 773 clock-names = "se";
893 clocks = <&gcc 774 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
894 pinctrl-names 775 pinctrl-names = "default";
895 pinctrl-0 = <& 776 pinctrl-0 = <&qup_i2c0_default>;
896 interrupts = < 777 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
897 #address-cells 778 #address-cells = <1>;
898 #size-cells = 779 #size-cells = <0>;
899 interconnects 780 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
900 781 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
901 782 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
902 interconnect-n 783 interconnect-names = "qup-core", "qup-config",
903 784 "qup-memory";
904 power-domains <<
905 required-opps <<
906 status = "disa 785 status = "disabled";
907 }; 786 };
908 787
909 spi0: spi@880000 { 788 spi0: spi@880000 {
910 compatible = " 789 compatible = "qcom,geni-spi";
911 reg = <0 0x008 790 reg = <0 0x00880000 0 0x4000>;
912 clock-names = 791 clock-names = "se";
913 clocks = <&gcc 792 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
914 pinctrl-names 793 pinctrl-names = "default";
915 pinctrl-0 = <& !! 794 pinctrl-0 = <&qup_spi0_default>;
916 interrupts = < 795 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
917 #address-cells 796 #address-cells = <1>;
918 #size-cells = 797 #size-cells = <0>;
919 power-domains 798 power-domains = <&rpmhpd SC7180_CX>;
920 operating-poin 799 operating-points-v2 = <&qup_opp_table>;
921 interconnects 800 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
922 801 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
923 interconnect-n 802 interconnect-names = "qup-core", "qup-config";
924 status = "disa 803 status = "disabled";
925 }; 804 };
926 805
927 uart0: serial@880000 { 806 uart0: serial@880000 {
928 compatible = " 807 compatible = "qcom,geni-uart";
929 reg = <0 0x008 808 reg = <0 0x00880000 0 0x4000>;
930 clock-names = 809 clock-names = "se";
931 clocks = <&gcc 810 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
932 pinctrl-names 811 pinctrl-names = "default";
933 pinctrl-0 = <& 812 pinctrl-0 = <&qup_uart0_default>;
934 interrupts = < 813 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
935 power-domains 814 power-domains = <&rpmhpd SC7180_CX>;
936 operating-poin 815 operating-points-v2 = <&qup_opp_table>;
937 interconnects 816 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
938 817 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
939 interconnect-n 818 interconnect-names = "qup-core", "qup-config";
940 status = "disa 819 status = "disabled";
941 }; 820 };
942 821
943 i2c1: i2c@884000 { 822 i2c1: i2c@884000 {
944 compatible = " 823 compatible = "qcom,geni-i2c";
945 reg = <0 0x008 824 reg = <0 0x00884000 0 0x4000>;
946 clock-names = 825 clock-names = "se";
947 clocks = <&gcc 826 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
948 pinctrl-names 827 pinctrl-names = "default";
949 pinctrl-0 = <& 828 pinctrl-0 = <&qup_i2c1_default>;
950 interrupts = < 829 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
951 #address-cells 830 #address-cells = <1>;
952 #size-cells = 831 #size-cells = <0>;
953 interconnects 832 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
954 833 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
955 834 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
956 interconnect-n 835 interconnect-names = "qup-core", "qup-config",
957 836 "qup-memory";
958 power-domains <<
959 required-opps <<
960 status = "disa 837 status = "disabled";
961 }; 838 };
962 839
963 spi1: spi@884000 { 840 spi1: spi@884000 {
964 compatible = " 841 compatible = "qcom,geni-spi";
965 reg = <0 0x008 842 reg = <0 0x00884000 0 0x4000>;
966 clock-names = 843 clock-names = "se";
967 clocks = <&gcc 844 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
968 pinctrl-names 845 pinctrl-names = "default";
969 pinctrl-0 = <& !! 846 pinctrl-0 = <&qup_spi1_default>;
970 interrupts = < 847 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
971 #address-cells 848 #address-cells = <1>;
972 #size-cells = 849 #size-cells = <0>;
973 power-domains 850 power-domains = <&rpmhpd SC7180_CX>;
974 operating-poin 851 operating-points-v2 = <&qup_opp_table>;
975 interconnects 852 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
976 853 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
977 interconnect-n 854 interconnect-names = "qup-core", "qup-config";
978 status = "disa 855 status = "disabled";
979 }; 856 };
980 857
981 uart1: serial@884000 { 858 uart1: serial@884000 {
982 compatible = " 859 compatible = "qcom,geni-uart";
983 reg = <0 0x008 860 reg = <0 0x00884000 0 0x4000>;
984 clock-names = 861 clock-names = "se";
985 clocks = <&gcc 862 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
986 pinctrl-names 863 pinctrl-names = "default";
987 pinctrl-0 = <& 864 pinctrl-0 = <&qup_uart1_default>;
988 interrupts = < 865 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
989 power-domains 866 power-domains = <&rpmhpd SC7180_CX>;
990 operating-poin 867 operating-points-v2 = <&qup_opp_table>;
991 interconnects 868 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
992 869 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
993 interconnect-n 870 interconnect-names = "qup-core", "qup-config";
994 status = "disa 871 status = "disabled";
995 }; 872 };
996 873
997 i2c2: i2c@888000 { 874 i2c2: i2c@888000 {
998 compatible = " 875 compatible = "qcom,geni-i2c";
999 reg = <0 0x008 876 reg = <0 0x00888000 0 0x4000>;
1000 clock-names = 877 clock-names = "se";
1001 clocks = <&gc 878 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1002 pinctrl-names 879 pinctrl-names = "default";
1003 pinctrl-0 = < 880 pinctrl-0 = <&qup_i2c2_default>;
1004 interrupts = 881 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1005 #address-cell 882 #address-cells = <1>;
1006 #size-cells = 883 #size-cells = <0>;
1007 interconnects 884 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1008 885 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1009 886 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1010 interconnect- 887 interconnect-names = "qup-core", "qup-config",
1011 888 "qup-memory";
1012 power-domains <<
1013 required-opps <<
1014 status = "dis 889 status = "disabled";
1015 }; 890 };
1016 891
1017 uart2: serial@888000 892 uart2: serial@888000 {
1018 compatible = 893 compatible = "qcom,geni-uart";
1019 reg = <0 0x00 894 reg = <0 0x00888000 0 0x4000>;
1020 clock-names = 895 clock-names = "se";
1021 clocks = <&gc 896 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1022 pinctrl-names 897 pinctrl-names = "default";
1023 pinctrl-0 = < 898 pinctrl-0 = <&qup_uart2_default>;
1024 interrupts = 899 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1025 power-domains 900 power-domains = <&rpmhpd SC7180_CX>;
1026 operating-poi 901 operating-points-v2 = <&qup_opp_table>;
1027 interconnects 902 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1028 903 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1029 interconnect- 904 interconnect-names = "qup-core", "qup-config";
1030 status = "dis 905 status = "disabled";
1031 }; 906 };
1032 907
1033 i2c3: i2c@88c000 { 908 i2c3: i2c@88c000 {
1034 compatible = 909 compatible = "qcom,geni-i2c";
1035 reg = <0 0x00 910 reg = <0 0x0088c000 0 0x4000>;
1036 clock-names = 911 clock-names = "se";
1037 clocks = <&gc 912 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1038 pinctrl-names 913 pinctrl-names = "default";
1039 pinctrl-0 = < 914 pinctrl-0 = <&qup_i2c3_default>;
1040 interrupts = 915 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1041 #address-cell 916 #address-cells = <1>;
1042 #size-cells = 917 #size-cells = <0>;
1043 interconnects 918 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1044 919 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1045 920 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1046 interconnect- 921 interconnect-names = "qup-core", "qup-config",
1047 922 "qup-memory";
1048 power-domains <<
1049 required-opps <<
1050 status = "dis 923 status = "disabled";
1051 }; 924 };
1052 925
1053 spi3: spi@88c000 { 926 spi3: spi@88c000 {
1054 compatible = 927 compatible = "qcom,geni-spi";
1055 reg = <0 0x00 928 reg = <0 0x0088c000 0 0x4000>;
1056 clock-names = 929 clock-names = "se";
1057 clocks = <&gc 930 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1058 pinctrl-names 931 pinctrl-names = "default";
1059 pinctrl-0 = < !! 932 pinctrl-0 = <&qup_spi3_default>;
1060 interrupts = 933 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1061 #address-cell 934 #address-cells = <1>;
1062 #size-cells = 935 #size-cells = <0>;
1063 power-domains 936 power-domains = <&rpmhpd SC7180_CX>;
1064 operating-poi 937 operating-points-v2 = <&qup_opp_table>;
1065 interconnects 938 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1066 939 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1067 interconnect- 940 interconnect-names = "qup-core", "qup-config";
1068 status = "dis 941 status = "disabled";
1069 }; 942 };
1070 943
1071 uart3: serial@88c000 944 uart3: serial@88c000 {
1072 compatible = 945 compatible = "qcom,geni-uart";
1073 reg = <0 0x00 946 reg = <0 0x0088c000 0 0x4000>;
1074 clock-names = 947 clock-names = "se";
1075 clocks = <&gc 948 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1076 pinctrl-names 949 pinctrl-names = "default";
1077 pinctrl-0 = < 950 pinctrl-0 = <&qup_uart3_default>;
1078 interrupts = 951 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1079 power-domains 952 power-domains = <&rpmhpd SC7180_CX>;
1080 operating-poi 953 operating-points-v2 = <&qup_opp_table>;
1081 interconnects 954 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1082 955 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1083 interconnect- 956 interconnect-names = "qup-core", "qup-config";
1084 status = "dis 957 status = "disabled";
1085 }; 958 };
1086 959
1087 i2c4: i2c@890000 { 960 i2c4: i2c@890000 {
1088 compatible = 961 compatible = "qcom,geni-i2c";
1089 reg = <0 0x00 962 reg = <0 0x00890000 0 0x4000>;
1090 clock-names = 963 clock-names = "se";
1091 clocks = <&gc 964 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1092 pinctrl-names 965 pinctrl-names = "default";
1093 pinctrl-0 = < 966 pinctrl-0 = <&qup_i2c4_default>;
1094 interrupts = 967 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1095 #address-cell 968 #address-cells = <1>;
1096 #size-cells = 969 #size-cells = <0>;
1097 interconnects 970 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1098 971 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1099 972 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1100 interconnect- 973 interconnect-names = "qup-core", "qup-config",
1101 974 "qup-memory";
1102 power-domains <<
1103 required-opps <<
1104 status = "dis 975 status = "disabled";
1105 }; 976 };
1106 977
1107 uart4: serial@890000 978 uart4: serial@890000 {
1108 compatible = 979 compatible = "qcom,geni-uart";
1109 reg = <0 0x00 980 reg = <0 0x00890000 0 0x4000>;
1110 clock-names = 981 clock-names = "se";
1111 clocks = <&gc 982 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1112 pinctrl-names 983 pinctrl-names = "default";
1113 pinctrl-0 = < 984 pinctrl-0 = <&qup_uart4_default>;
1114 interrupts = 985 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1115 power-domains 986 power-domains = <&rpmhpd SC7180_CX>;
1116 operating-poi 987 operating-points-v2 = <&qup_opp_table>;
1117 interconnects 988 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1118 989 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1119 interconnect- 990 interconnect-names = "qup-core", "qup-config";
1120 status = "dis 991 status = "disabled";
1121 }; 992 };
1122 993
1123 i2c5: i2c@894000 { 994 i2c5: i2c@894000 {
1124 compatible = 995 compatible = "qcom,geni-i2c";
1125 reg = <0 0x00 996 reg = <0 0x00894000 0 0x4000>;
1126 clock-names = 997 clock-names = "se";
1127 clocks = <&gc 998 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1128 pinctrl-names 999 pinctrl-names = "default";
1129 pinctrl-0 = < 1000 pinctrl-0 = <&qup_i2c5_default>;
1130 interrupts = 1001 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1131 #address-cell 1002 #address-cells = <1>;
1132 #size-cells = 1003 #size-cells = <0>;
1133 interconnects 1004 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1134 1005 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1135 1006 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1136 interconnect- 1007 interconnect-names = "qup-core", "qup-config",
1137 1008 "qup-memory";
1138 power-domains <<
1139 required-opps <<
1140 status = "dis 1009 status = "disabled";
1141 }; 1010 };
1142 1011
1143 spi5: spi@894000 { 1012 spi5: spi@894000 {
1144 compatible = 1013 compatible = "qcom,geni-spi";
1145 reg = <0 0x00 1014 reg = <0 0x00894000 0 0x4000>;
1146 clock-names = 1015 clock-names = "se";
1147 clocks = <&gc 1016 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1148 pinctrl-names 1017 pinctrl-names = "default";
1149 pinctrl-0 = < !! 1018 pinctrl-0 = <&qup_spi5_default>;
1150 interrupts = 1019 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1151 #address-cell 1020 #address-cells = <1>;
1152 #size-cells = 1021 #size-cells = <0>;
1153 power-domains 1022 power-domains = <&rpmhpd SC7180_CX>;
1154 operating-poi 1023 operating-points-v2 = <&qup_opp_table>;
1155 interconnects 1024 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1156 1025 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1157 interconnect- 1026 interconnect-names = "qup-core", "qup-config";
1158 status = "dis 1027 status = "disabled";
1159 }; 1028 };
1160 1029
1161 uart5: serial@894000 1030 uart5: serial@894000 {
1162 compatible = 1031 compatible = "qcom,geni-uart";
1163 reg = <0 0x00 1032 reg = <0 0x00894000 0 0x4000>;
1164 clock-names = 1033 clock-names = "se";
1165 clocks = <&gc 1034 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1166 pinctrl-names 1035 pinctrl-names = "default";
1167 pinctrl-0 = < 1036 pinctrl-0 = <&qup_uart5_default>;
1168 interrupts = 1037 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1169 power-domains 1038 power-domains = <&rpmhpd SC7180_CX>;
1170 operating-poi 1039 operating-points-v2 = <&qup_opp_table>;
1171 interconnects 1040 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1172 1041 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1173 interconnect- 1042 interconnect-names = "qup-core", "qup-config";
1174 status = "dis 1043 status = "disabled";
1175 }; 1044 };
1176 }; 1045 };
1177 1046
1178 qupv3_id_1: geniqup@ac0000 { 1047 qupv3_id_1: geniqup@ac0000 {
1179 compatible = "qcom,ge 1048 compatible = "qcom,geni-se-qup";
1180 reg = <0 0x00ac0000 0 1049 reg = <0 0x00ac0000 0 0x6000>;
1181 clock-names = "m-ahb" 1050 clock-names = "m-ahb", "s-ahb";
1182 clocks = <&gcc GCC_QU 1051 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1183 <&gcc GCC_QU 1052 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1184 #address-cells = <2>; 1053 #address-cells = <2>;
1185 #size-cells = <2>; 1054 #size-cells = <2>;
1186 ranges; 1055 ranges;
1187 iommus = <&apps_smmu 1056 iommus = <&apps_smmu 0x4c3 0x0>;
>> 1057 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>;
>> 1058 interconnect-names = "qup-core";
1188 status = "disabled"; 1059 status = "disabled";
1189 1060
1190 i2c6: i2c@a80000 { 1061 i2c6: i2c@a80000 {
1191 compatible = 1062 compatible = "qcom,geni-i2c";
1192 reg = <0 0x00 1063 reg = <0 0x00a80000 0 0x4000>;
1193 clock-names = 1064 clock-names = "se";
1194 clocks = <&gc 1065 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1195 pinctrl-names 1066 pinctrl-names = "default";
1196 pinctrl-0 = < 1067 pinctrl-0 = <&qup_i2c6_default>;
1197 interrupts = 1068 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1198 #address-cell 1069 #address-cells = <1>;
1199 #size-cells = 1070 #size-cells = <0>;
1200 interconnects 1071 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1201 1072 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1202 1073 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1203 interconnect- 1074 interconnect-names = "qup-core", "qup-config",
1204 1075 "qup-memory";
1205 power-domains <<
1206 required-opps <<
1207 status = "dis 1076 status = "disabled";
1208 }; 1077 };
1209 1078
1210 spi6: spi@a80000 { 1079 spi6: spi@a80000 {
1211 compatible = 1080 compatible = "qcom,geni-spi";
1212 reg = <0 0x00 1081 reg = <0 0x00a80000 0 0x4000>;
1213 clock-names = 1082 clock-names = "se";
1214 clocks = <&gc 1083 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1215 pinctrl-names 1084 pinctrl-names = "default";
1216 pinctrl-0 = < !! 1085 pinctrl-0 = <&qup_spi6_default>;
1217 interrupts = 1086 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1218 #address-cell 1087 #address-cells = <1>;
1219 #size-cells = 1088 #size-cells = <0>;
1220 power-domains 1089 power-domains = <&rpmhpd SC7180_CX>;
1221 operating-poi 1090 operating-points-v2 = <&qup_opp_table>;
1222 interconnects 1091 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1223 1092 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1224 interconnect- 1093 interconnect-names = "qup-core", "qup-config";
1225 status = "dis 1094 status = "disabled";
1226 }; 1095 };
1227 1096
1228 uart6: serial@a80000 1097 uart6: serial@a80000 {
1229 compatible = 1098 compatible = "qcom,geni-uart";
1230 reg = <0 0x00 1099 reg = <0 0x00a80000 0 0x4000>;
1231 clock-names = 1100 clock-names = "se";
1232 clocks = <&gc 1101 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1233 pinctrl-names 1102 pinctrl-names = "default";
1234 pinctrl-0 = < 1103 pinctrl-0 = <&qup_uart6_default>;
1235 interrupts = 1104 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1236 power-domains 1105 power-domains = <&rpmhpd SC7180_CX>;
1237 operating-poi 1106 operating-points-v2 = <&qup_opp_table>;
1238 interconnects 1107 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1239 1108 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1240 interconnect- 1109 interconnect-names = "qup-core", "qup-config";
1241 status = "dis 1110 status = "disabled";
1242 }; 1111 };
1243 1112
1244 i2c7: i2c@a84000 { 1113 i2c7: i2c@a84000 {
1245 compatible = 1114 compatible = "qcom,geni-i2c";
1246 reg = <0 0x00 1115 reg = <0 0x00a84000 0 0x4000>;
1247 clock-names = 1116 clock-names = "se";
1248 clocks = <&gc 1117 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1249 pinctrl-names 1118 pinctrl-names = "default";
1250 pinctrl-0 = < 1119 pinctrl-0 = <&qup_i2c7_default>;
1251 interrupts = 1120 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1252 #address-cell 1121 #address-cells = <1>;
1253 #size-cells = 1122 #size-cells = <0>;
1254 interconnects 1123 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1255 1124 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1256 1125 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1257 interconnect- 1126 interconnect-names = "qup-core", "qup-config",
1258 1127 "qup-memory";
1259 power-domains <<
1260 required-opps <<
1261 status = "dis 1128 status = "disabled";
1262 }; 1129 };
1263 1130
1264 uart7: serial@a84000 1131 uart7: serial@a84000 {
1265 compatible = 1132 compatible = "qcom,geni-uart";
1266 reg = <0 0x00 1133 reg = <0 0x00a84000 0 0x4000>;
1267 clock-names = 1134 clock-names = "se";
1268 clocks = <&gc 1135 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1269 pinctrl-names 1136 pinctrl-names = "default";
1270 pinctrl-0 = < 1137 pinctrl-0 = <&qup_uart7_default>;
1271 interrupts = 1138 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1272 power-domains 1139 power-domains = <&rpmhpd SC7180_CX>;
1273 operating-poi 1140 operating-points-v2 = <&qup_opp_table>;
1274 interconnects 1141 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1275 1142 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1276 interconnect- 1143 interconnect-names = "qup-core", "qup-config";
1277 status = "dis 1144 status = "disabled";
1278 }; 1145 };
1279 1146
1280 i2c8: i2c@a88000 { 1147 i2c8: i2c@a88000 {
1281 compatible = 1148 compatible = "qcom,geni-i2c";
1282 reg = <0 0x00 1149 reg = <0 0x00a88000 0 0x4000>;
1283 clock-names = 1150 clock-names = "se";
1284 clocks = <&gc 1151 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1285 pinctrl-names 1152 pinctrl-names = "default";
1286 pinctrl-0 = < 1153 pinctrl-0 = <&qup_i2c8_default>;
1287 interrupts = 1154 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1288 #address-cell 1155 #address-cells = <1>;
1289 #size-cells = 1156 #size-cells = <0>;
1290 interconnects 1157 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1291 1158 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1292 1159 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1293 interconnect- 1160 interconnect-names = "qup-core", "qup-config",
1294 1161 "qup-memory";
1295 power-domains <<
1296 required-opps <<
1297 status = "dis 1162 status = "disabled";
1298 }; 1163 };
1299 1164
1300 spi8: spi@a88000 { 1165 spi8: spi@a88000 {
1301 compatible = 1166 compatible = "qcom,geni-spi";
1302 reg = <0 0x00 1167 reg = <0 0x00a88000 0 0x4000>;
1303 clock-names = 1168 clock-names = "se";
1304 clocks = <&gc 1169 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1305 pinctrl-names 1170 pinctrl-names = "default";
1306 pinctrl-0 = < !! 1171 pinctrl-0 = <&qup_spi8_default>;
1307 interrupts = 1172 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1308 #address-cell 1173 #address-cells = <1>;
1309 #size-cells = 1174 #size-cells = <0>;
1310 power-domains 1175 power-domains = <&rpmhpd SC7180_CX>;
1311 operating-poi 1176 operating-points-v2 = <&qup_opp_table>;
1312 interconnects 1177 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1313 1178 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1314 interconnect- 1179 interconnect-names = "qup-core", "qup-config";
1315 status = "dis 1180 status = "disabled";
1316 }; 1181 };
1317 1182
1318 uart8: serial@a88000 1183 uart8: serial@a88000 {
1319 compatible = 1184 compatible = "qcom,geni-debug-uart";
1320 reg = <0 0x00 1185 reg = <0 0x00a88000 0 0x4000>;
1321 clock-names = 1186 clock-names = "se";
1322 clocks = <&gc 1187 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1323 pinctrl-names 1188 pinctrl-names = "default";
1324 pinctrl-0 = < 1189 pinctrl-0 = <&qup_uart8_default>;
1325 interrupts = 1190 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1326 power-domains 1191 power-domains = <&rpmhpd SC7180_CX>;
1327 operating-poi 1192 operating-points-v2 = <&qup_opp_table>;
1328 interconnects 1193 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1329 1194 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1330 interconnect- 1195 interconnect-names = "qup-core", "qup-config";
1331 status = "dis 1196 status = "disabled";
1332 }; 1197 };
1333 1198
1334 i2c9: i2c@a8c000 { 1199 i2c9: i2c@a8c000 {
1335 compatible = 1200 compatible = "qcom,geni-i2c";
1336 reg = <0 0x00 1201 reg = <0 0x00a8c000 0 0x4000>;
1337 clock-names = 1202 clock-names = "se";
1338 clocks = <&gc 1203 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1339 pinctrl-names 1204 pinctrl-names = "default";
1340 pinctrl-0 = < 1205 pinctrl-0 = <&qup_i2c9_default>;
1341 interrupts = 1206 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1342 #address-cell 1207 #address-cells = <1>;
1343 #size-cells = 1208 #size-cells = <0>;
1344 interconnects 1209 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1345 1210 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1346 1211 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1347 interconnect- 1212 interconnect-names = "qup-core", "qup-config",
1348 1213 "qup-memory";
1349 power-domains <<
1350 required-opps <<
1351 status = "dis 1214 status = "disabled";
1352 }; 1215 };
1353 1216
1354 uart9: serial@a8c000 1217 uart9: serial@a8c000 {
1355 compatible = 1218 compatible = "qcom,geni-uart";
1356 reg = <0 0x00 1219 reg = <0 0x00a8c000 0 0x4000>;
1357 clock-names = 1220 clock-names = "se";
1358 clocks = <&gc 1221 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1359 pinctrl-names 1222 pinctrl-names = "default";
1360 pinctrl-0 = < 1223 pinctrl-0 = <&qup_uart9_default>;
1361 interrupts = 1224 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1362 power-domains 1225 power-domains = <&rpmhpd SC7180_CX>;
1363 operating-poi 1226 operating-points-v2 = <&qup_opp_table>;
1364 interconnects 1227 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1365 1228 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1366 interconnect- 1229 interconnect-names = "qup-core", "qup-config";
1367 status = "dis 1230 status = "disabled";
1368 }; 1231 };
1369 1232
1370 i2c10: i2c@a90000 { 1233 i2c10: i2c@a90000 {
1371 compatible = 1234 compatible = "qcom,geni-i2c";
1372 reg = <0 0x00 1235 reg = <0 0x00a90000 0 0x4000>;
1373 clock-names = 1236 clock-names = "se";
1374 clocks = <&gc 1237 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1375 pinctrl-names 1238 pinctrl-names = "default";
1376 pinctrl-0 = < 1239 pinctrl-0 = <&qup_i2c10_default>;
1377 interrupts = 1240 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1378 #address-cell 1241 #address-cells = <1>;
1379 #size-cells = 1242 #size-cells = <0>;
1380 interconnects 1243 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1381 1244 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1382 1245 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1383 interconnect- 1246 interconnect-names = "qup-core", "qup-config",
1384 1247 "qup-memory";
1385 power-domains <<
1386 required-opps <<
1387 status = "dis 1248 status = "disabled";
1388 }; 1249 };
1389 1250
1390 spi10: spi@a90000 { 1251 spi10: spi@a90000 {
1391 compatible = 1252 compatible = "qcom,geni-spi";
1392 reg = <0 0x00 1253 reg = <0 0x00a90000 0 0x4000>;
1393 clock-names = 1254 clock-names = "se";
1394 clocks = <&gc 1255 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1395 pinctrl-names 1256 pinctrl-names = "default";
1396 pinctrl-0 = < !! 1257 pinctrl-0 = <&qup_spi10_default>;
1397 interrupts = 1258 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1398 #address-cell 1259 #address-cells = <1>;
1399 #size-cells = 1260 #size-cells = <0>;
1400 power-domains 1261 power-domains = <&rpmhpd SC7180_CX>;
1401 operating-poi 1262 operating-points-v2 = <&qup_opp_table>;
1402 interconnects 1263 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1403 1264 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1404 interconnect- 1265 interconnect-names = "qup-core", "qup-config";
1405 status = "dis 1266 status = "disabled";
1406 }; 1267 };
1407 1268
1408 uart10: serial@a90000 1269 uart10: serial@a90000 {
1409 compatible = 1270 compatible = "qcom,geni-uart";
1410 reg = <0 0x00 1271 reg = <0 0x00a90000 0 0x4000>;
1411 clock-names = 1272 clock-names = "se";
1412 clocks = <&gc 1273 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1413 pinctrl-names 1274 pinctrl-names = "default";
1414 pinctrl-0 = < 1275 pinctrl-0 = <&qup_uart10_default>;
1415 interrupts = 1276 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1416 power-domains 1277 power-domains = <&rpmhpd SC7180_CX>;
1417 operating-poi 1278 operating-points-v2 = <&qup_opp_table>;
1418 interconnects 1279 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1419 1280 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1420 interconnect- 1281 interconnect-names = "qup-core", "qup-config";
1421 status = "dis 1282 status = "disabled";
1422 }; 1283 };
1423 1284
1424 i2c11: i2c@a94000 { 1285 i2c11: i2c@a94000 {
1425 compatible = 1286 compatible = "qcom,geni-i2c";
1426 reg = <0 0x00 1287 reg = <0 0x00a94000 0 0x4000>;
1427 clock-names = 1288 clock-names = "se";
1428 clocks = <&gc 1289 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1429 pinctrl-names 1290 pinctrl-names = "default";
1430 pinctrl-0 = < 1291 pinctrl-0 = <&qup_i2c11_default>;
1431 interrupts = 1292 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1432 #address-cell 1293 #address-cells = <1>;
1433 #size-cells = 1294 #size-cells = <0>;
1434 interconnects 1295 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1435 1296 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1436 1297 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1437 interconnect- 1298 interconnect-names = "qup-core", "qup-config",
1438 1299 "qup-memory";
1439 power-domains <<
1440 required-opps <<
1441 status = "dis 1300 status = "disabled";
1442 }; 1301 };
1443 1302
1444 spi11: spi@a94000 { 1303 spi11: spi@a94000 {
1445 compatible = 1304 compatible = "qcom,geni-spi";
1446 reg = <0 0x00 1305 reg = <0 0x00a94000 0 0x4000>;
1447 clock-names = 1306 clock-names = "se";
1448 clocks = <&gc 1307 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1449 pinctrl-names 1308 pinctrl-names = "default";
1450 pinctrl-0 = < !! 1309 pinctrl-0 = <&qup_spi11_default>;
1451 interrupts = 1310 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1452 #address-cell 1311 #address-cells = <1>;
1453 #size-cells = 1312 #size-cells = <0>;
1454 power-domains 1313 power-domains = <&rpmhpd SC7180_CX>;
1455 operating-poi 1314 operating-points-v2 = <&qup_opp_table>;
1456 interconnects 1315 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1457 1316 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1458 interconnect- 1317 interconnect-names = "qup-core", "qup-config";
1459 status = "dis 1318 status = "disabled";
1460 }; 1319 };
1461 1320
1462 uart11: serial@a94000 1321 uart11: serial@a94000 {
1463 compatible = 1322 compatible = "qcom,geni-uart";
1464 reg = <0 0x00 1323 reg = <0 0x00a94000 0 0x4000>;
1465 clock-names = 1324 clock-names = "se";
1466 clocks = <&gc 1325 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1467 pinctrl-names 1326 pinctrl-names = "default";
1468 pinctrl-0 = < 1327 pinctrl-0 = <&qup_uart11_default>;
1469 interrupts = 1328 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1470 power-domains 1329 power-domains = <&rpmhpd SC7180_CX>;
1471 operating-poi 1330 operating-points-v2 = <&qup_opp_table>;
1472 interconnects 1331 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1473 1332 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1474 interconnect- 1333 interconnect-names = "qup-core", "qup-config";
1475 status = "dis 1334 status = "disabled";
1476 }; 1335 };
1477 }; 1336 };
1478 1337
1479 config_noc: interconnect@1500 1338 config_noc: interconnect@1500000 {
1480 compatible = "qcom,sc 1339 compatible = "qcom,sc7180-config-noc";
1481 reg = <0 0x01500000 0 1340 reg = <0 0x01500000 0 0x28000>;
1482 #interconnect-cells = 1341 #interconnect-cells = <2>;
1483 qcom,bcm-voters = <&a 1342 qcom,bcm-voters = <&apps_bcm_voter>;
1484 }; 1343 };
1485 1344
1486 system_noc: interconnect@1620 1345 system_noc: interconnect@1620000 {
1487 compatible = "qcom,sc 1346 compatible = "qcom,sc7180-system-noc";
1488 reg = <0 0x01620000 0 1347 reg = <0 0x01620000 0 0x17080>;
1489 #interconnect-cells = 1348 #interconnect-cells = <2>;
1490 qcom,bcm-voters = <&a 1349 qcom,bcm-voters = <&apps_bcm_voter>;
1491 }; 1350 };
1492 1351
1493 mc_virt: interconnect@1638000 1352 mc_virt: interconnect@1638000 {
1494 compatible = "qcom,sc 1353 compatible = "qcom,sc7180-mc-virt";
1495 reg = <0 0x01638000 0 1354 reg = <0 0x01638000 0 0x1000>;
1496 #interconnect-cells = 1355 #interconnect-cells = <2>;
1497 qcom,bcm-voters = <&a 1356 qcom,bcm-voters = <&apps_bcm_voter>;
1498 }; 1357 };
1499 1358
1500 qup_virt: interconnect@165000 1359 qup_virt: interconnect@1650000 {
1501 compatible = "qcom,sc 1360 compatible = "qcom,sc7180-qup-virt";
1502 reg = <0 0x01650000 0 1361 reg = <0 0x01650000 0 0x1000>;
1503 #interconnect-cells = 1362 #interconnect-cells = <2>;
1504 qcom,bcm-voters = <&a 1363 qcom,bcm-voters = <&apps_bcm_voter>;
1505 }; 1364 };
1506 1365
1507 aggre1_noc: interconnect@16e0 1366 aggre1_noc: interconnect@16e0000 {
1508 compatible = "qcom,sc 1367 compatible = "qcom,sc7180-aggre1-noc";
1509 reg = <0 0x016e0000 0 1368 reg = <0 0x016e0000 0 0x15080>;
1510 #interconnect-cells = 1369 #interconnect-cells = <2>;
1511 qcom,bcm-voters = <&a 1370 qcom,bcm-voters = <&apps_bcm_voter>;
1512 }; 1371 };
1513 1372
1514 aggre2_noc: interconnect@1705 1373 aggre2_noc: interconnect@1705000 {
1515 compatible = "qcom,sc 1374 compatible = "qcom,sc7180-aggre2-noc";
1516 reg = <0 0x01705000 0 1375 reg = <0 0x01705000 0 0x9000>;
1517 #interconnect-cells = 1376 #interconnect-cells = <2>;
1518 qcom,bcm-voters = <&a 1377 qcom,bcm-voters = <&apps_bcm_voter>;
1519 }; 1378 };
1520 1379
1521 compute_noc: interconnect@170 1380 compute_noc: interconnect@170e000 {
1522 compatible = "qcom,sc 1381 compatible = "qcom,sc7180-compute-noc";
1523 reg = <0 0x0170e000 0 1382 reg = <0 0x0170e000 0 0x6000>;
1524 #interconnect-cells = 1383 #interconnect-cells = <2>;
1525 qcom,bcm-voters = <&a 1384 qcom,bcm-voters = <&apps_bcm_voter>;
1526 }; 1385 };
1527 1386
1528 mmss_noc: interconnect@174000 1387 mmss_noc: interconnect@1740000 {
1529 compatible = "qcom,sc 1388 compatible = "qcom,sc7180-mmss-noc";
1530 reg = <0 0x01740000 0 1389 reg = <0 0x01740000 0 0x1c100>;
1531 #interconnect-cells = 1390 #interconnect-cells = <2>;
1532 qcom,bcm-voters = <&a 1391 qcom,bcm-voters = <&apps_bcm_voter>;
1533 }; 1392 };
1534 1393
1535 ufs_mem_hc: ufshc@1d84000 { !! 1394 ipa_virt: interconnect@1e00000 {
1536 compatible = "qcom,sc !! 1395 compatible = "qcom,sc7180-ipa-virt";
1537 "jedec,u !! 1396 reg = <0 0x01e00000 0 0x1000>;
1538 reg = <0 0x01d84000 0 !! 1397 #interconnect-cells = <2>;
1539 interrupts = <GIC_SPI !! 1398 qcom,bcm-voters = <&apps_bcm_voter>;
1540 phys = <&ufs_mem_phy> <<
1541 phy-names = "ufsphy"; <<
1542 lanes-per-direction = <<
1543 #reset-cells = <1>; <<
1544 resets = <&gcc GCC_UF <<
1545 reset-names = "rst"; <<
1546 <<
1547 power-domains = <&gcc <<
1548 <<
1549 iommus = <&apps_smmu <<
1550 <<
1551 clock-names = "core_c <<
1552 "bus_ag <<
1553 "iface_ <<
1554 "core_c <<
1555 "ref_cl <<
1556 "tx_lan <<
1557 "rx_lan <<
1558 clocks = <&gcc GCC_UF <<
1559 <&gcc GCC_AG <<
1560 <&gcc GCC_UF <<
1561 <&gcc GCC_UF <<
1562 <&rpmhcc RPM <<
1563 <&gcc GCC_UF <<
1564 <&gcc GCC_UF <<
1565 freq-table-hz = <5000 <<
1566 <0 0> <<
1567 <0 0> <<
1568 <3750 <<
1569 <0 0> <<
1570 <0 0> <<
1571 <0 0> <<
1572 <<
1573 interconnects = <&agg <<
1574 &mc_ <<
1575 <&gem <<
1576 &con <<
1577 interconnect-names = <<
1578 <<
1579 qcom,ice = <&ice>; <<
1580 <<
1581 status = "disabled"; <<
1582 }; <<
1583 <<
1584 ufs_mem_phy: phy@1d87000 { <<
1585 compatible = "qcom,sc <<
1586 reg = <0 0x01d87000 0 <<
1587 clocks = <&rpmhcc RPM <<
1588 <&gcc GCC_UF <<
1589 <&gcc GCC_UF <<
1590 clock-names = "ref", <<
1591 "ref_au <<
1592 "qref"; <<
1593 power-domains = <&gcc <<
1594 resets = <&ufs_mem_hc <<
1595 reset-names = "ufsphy <<
1596 #phy-cells = <0>; <<
1597 status = "disabled"; <<
1598 }; <<
1599 <<
1600 ice: crypto@1d90000 { <<
1601 compatible = "qcom,sc <<
1602 "qcom,in <<
1603 reg = <0 0x01d90000 0 <<
1604 clocks = <&gcc GCC_UF <<
1605 }; 1399 };
1606 1400
1607 ipa: ipa@1e40000 { 1401 ipa: ipa@1e40000 {
1608 compatible = "qcom,sc 1402 compatible = "qcom,sc7180-ipa";
1609 1403
1610 iommus = <&apps_smmu 1404 iommus = <&apps_smmu 0x440 0x0>,
1611 <&apps_smmu 1405 <&apps_smmu 0x442 0x0>;
1612 reg = <0 0x01e40000 0 !! 1406 reg = <0 0x1e40000 0 0x7000>,
1613 <0 0x01e47000 0 !! 1407 <0 0x1e47000 0 0x2000>,
1614 <0 0x01e04000 0 !! 1408 <0 0x1e04000 0 0x2c000>;
1615 reg-names = "ipa-reg" 1409 reg-names = "ipa-reg",
1616 "ipa-shar 1410 "ipa-shared",
1617 "gsi"; 1411 "gsi";
1618 1412
1619 interrupts-extended = 1413 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
1620 1414 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
1621 1415 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1622 1416 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
1623 interrupt-names = "ip 1417 interrupt-names = "ipa",
1624 "gs 1418 "gsi",
1625 "ip 1419 "ipa-clock-query",
1626 "ip 1420 "ipa-setup-ready";
1627 1421
1628 clocks = <&rpmhcc RPM 1422 clocks = <&rpmhcc RPMH_IPA_CLK>;
1629 clock-names = "core"; 1423 clock-names = "core";
1630 1424
1631 interconnects = <&agg 1425 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
1632 <&agg 1426 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>,
1633 <&gem 1427 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
1634 interconnect-names = 1428 interconnect-names = "memory",
1635 1429 "imem",
1636 1430 "config";
1637 1431
1638 qcom,qmp = <&aoss_qmp <<
1639 <<
1640 qcom,smem-states = <& 1432 qcom,smem-states = <&ipa_smp2p_out 0>,
1641 <& 1433 <&ipa_smp2p_out 1>;
1642 qcom,smem-state-names 1434 qcom,smem-state-names = "ipa-clock-enabled-valid",
1643 1435 "ipa-clock-enabled";
1644 1436
1645 status = "disabled"; !! 1437 modem-remoteproc = <&remoteproc_mpss>;
1646 }; <<
1647 1438
1648 tcsr_mutex: hwlock@1f40000 { !! 1439 status = "disabled";
1649 compatible = "qcom,tc <<
1650 reg = <0 0x01f40000 0 <<
1651 #hwlock-cells = <1>; <<
1652 }; 1440 };
1653 1441
1654 tcsr_regs_1: syscon@1f60000 { !! 1442 tcsr_mutex_regs: syscon@1f40000 {
1655 compatible = "qcom,sc !! 1443 compatible = "syscon";
1656 reg = <0 0x01f60000 0 !! 1444 reg = <0 0x01f40000 0 0x40000>;
1657 }; 1445 };
1658 1446
1659 tcsr_regs_2: syscon@1fc0000 { !! 1447 tcsr_regs: syscon@1fc0000 {
1660 compatible = "qcom,sc !! 1448 compatible = "syscon";
1661 reg = <0 0x01fc0000 0 1449 reg = <0 0x01fc0000 0 0x40000>;
1662 }; 1450 };
1663 1451
1664 tlmm: pinctrl@3500000 { 1452 tlmm: pinctrl@3500000 {
1665 compatible = "qcom,sc 1453 compatible = "qcom,sc7180-pinctrl";
1666 reg = <0 0x03500000 0 1454 reg = <0 0x03500000 0 0x300000>,
1667 <0 0x03900000 0 1455 <0 0x03900000 0 0x300000>,
1668 <0 0x03d00000 0 1456 <0 0x03d00000 0 0x300000>;
1669 reg-names = "west", " 1457 reg-names = "west", "north", "south";
1670 interrupts = <GIC_SPI 1458 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1671 gpio-controller; 1459 gpio-controller;
1672 #gpio-cells = <2>; 1460 #gpio-cells = <2>;
1673 interrupt-controller; 1461 interrupt-controller;
1674 #interrupt-cells = <2 1462 #interrupt-cells = <2>;
1675 gpio-ranges = <&tlmm 1463 gpio-ranges = <&tlmm 0 0 120>;
1676 wakeup-parent = <&pdc 1464 wakeup-parent = <&pdc>;
1677 1465
1678 dp_hot_plug_det: dp-h !! 1466 dp_hot_plug_det: dp-hot-plug-det {
1679 pins = "gpio1 !! 1467 pinmux {
1680 function = "d !! 1468 pins = "gpio117";
1681 }; !! 1469 function = "dp_hot";
1682 !! 1470 };
1683 qspi_clk: qspi-clk-st <<
1684 pins = "gpio6 <<
1685 function = "q <<
1686 }; <<
1687 <<
1688 qspi_cs0: qspi-cs0-st <<
1689 pins = "gpio6 <<
1690 function = "q <<
1691 }; <<
1692 <<
1693 qspi_cs1: qspi-cs1-st <<
1694 pins = "gpio7 <<
1695 function = "q <<
1696 }; <<
1697 <<
1698 qspi_data0: qspi-data <<
1699 pins = "gpio6 <<
1700 function = "q <<
1701 }; <<
1702 <<
1703 qspi_data1: qspi-data <<
1704 pins = "gpio6 <<
1705 function = "q <<
1706 }; <<
1707 <<
1708 qspi_data23: qspi-dat <<
1709 pins = "gpio6 <<
1710 function = "q <<
1711 }; <<
1712 1471
1713 qup_i2c0_default: qup !! 1472 pinconf {
1714 pins = "gpio3 !! 1473 pins = "gpio117";
1715 function = "q !! 1474 bias-disable;
>> 1475 input-enable;
>> 1476 };
1716 }; 1477 };
1717 1478
1718 qup_i2c1_default: qup !! 1479 qspi_clk: qspi-clk {
1719 pins = "gpio0 !! 1480 pinmux {
1720 function = "q !! 1481 pins = "gpio63";
>> 1482 function = "qspi_clk";
>> 1483 };
1721 }; 1484 };
1722 1485
1723 qup_i2c2_default: qup !! 1486 qspi_cs0: qspi-cs0 {
1724 pins = "gpio1 !! 1487 pinmux {
1725 function = "q !! 1488 pins = "gpio68";
>> 1489 function = "qspi_cs";
>> 1490 };
1726 }; 1491 };
1727 1492
1728 qup_i2c3_default: qup !! 1493 qspi_cs1: qspi-cs1 {
1729 pins = "gpio3 !! 1494 pinmux {
1730 function = "q !! 1495 pins = "gpio72";
>> 1496 function = "qspi_cs";
>> 1497 };
1731 }; 1498 };
1732 1499
1733 qup_i2c4_default: qup !! 1500 qspi_data01: qspi-data01 {
1734 pins = "gpio1 !! 1501 pinmux-data {
1735 function = "q !! 1502 pins = "gpio64", "gpio65";
>> 1503 function = "qspi_data";
>> 1504 };
1736 }; 1505 };
1737 1506
1738 qup_i2c5_default: qup !! 1507 qspi_data12: qspi-data12 {
1739 pins = "gpio2 !! 1508 pinmux-data {
1740 function = "q !! 1509 pins = "gpio66", "gpio67";
>> 1510 function = "qspi_data";
>> 1511 };
1741 }; 1512 };
1742 1513
1743 qup_i2c6_default: qup !! 1514 qup_i2c0_default: qup-i2c0-default {
1744 pins = "gpio5 !! 1515 pinmux {
1745 function = "q !! 1516 pins = "gpio34", "gpio35";
>> 1517 function = "qup00";
>> 1518 };
1746 }; 1519 };
1747 1520
1748 qup_i2c7_default: qup !! 1521 qup_i2c1_default: qup-i2c1-default {
1749 pins = "gpio6 !! 1522 pinmux {
1750 function = "q !! 1523 pins = "gpio0", "gpio1";
>> 1524 function = "qup01";
>> 1525 };
1751 }; 1526 };
1752 1527
1753 qup_i2c8_default: qup !! 1528 qup_i2c2_default: qup-i2c2-default {
1754 pins = "gpio4 !! 1529 pinmux {
1755 function = "q !! 1530 pins = "gpio15", "gpio16";
>> 1531 function = "qup02_i2c";
>> 1532 };
1756 }; 1533 };
1757 1534
1758 qup_i2c9_default: qup !! 1535 qup_i2c3_default: qup-i2c3-default {
1759 pins = "gpio4 !! 1536 pinmux {
1760 function = "q !! 1537 pins = "gpio38", "gpio39";
>> 1538 function = "qup03";
>> 1539 };
1761 }; 1540 };
1762 1541
1763 qup_i2c10_default: qu !! 1542 qup_i2c4_default: qup-i2c4-default {
1764 pins = "gpio8 !! 1543 pinmux {
1765 function = "q !! 1544 pins = "gpio115", "gpio116";
>> 1545 function = "qup04_i2c";
>> 1546 };
1766 }; 1547 };
1767 1548
1768 qup_i2c11_default: qu !! 1549 qup_i2c5_default: qup-i2c5-default {
1769 pins = "gpio5 !! 1550 pinmux {
1770 function = "q !! 1551 pins = "gpio25", "gpio26";
>> 1552 function = "qup05";
>> 1553 };
1771 }; 1554 };
1772 1555
1773 qup_spi0_spi: qup-spi !! 1556 qup_i2c6_default: qup-i2c6-default {
1774 pins = "gpio3 !! 1557 pinmux {
1775 function = "q !! 1558 pins = "gpio59", "gpio60";
>> 1559 function = "qup10";
>> 1560 };
1776 }; 1561 };
1777 1562
1778 qup_spi0_cs: qup-spi0 !! 1563 qup_i2c7_default: qup-i2c7-default {
1779 pins = "gpio3 !! 1564 pinmux {
1780 function = "q !! 1565 pins = "gpio6", "gpio7";
>> 1566 function = "qup11_i2c";
>> 1567 };
1781 }; 1568 };
1782 1569
1783 qup_spi0_cs_gpio: qup !! 1570 qup_i2c8_default: qup-i2c8-default {
1784 pins = "gpio3 !! 1571 pinmux {
1785 function = "g !! 1572 pins = "gpio42", "gpio43";
>> 1573 function = "qup12";
>> 1574 };
1786 }; 1575 };
1787 1576
1788 qup_spi1_spi: qup-spi !! 1577 qup_i2c9_default: qup-i2c9-default {
1789 pins = "gpio0 !! 1578 pinmux {
1790 function = "q !! 1579 pins = "gpio46", "gpio47";
>> 1580 function = "qup13_i2c";
>> 1581 };
1791 }; 1582 };
1792 1583
1793 qup_spi1_cs: qup-spi1 !! 1584 qup_i2c10_default: qup-i2c10-default {
1794 pins = "gpio3 !! 1585 pinmux {
1795 function = "q !! 1586 pins = "gpio86", "gpio87";
>> 1587 function = "qup14";
>> 1588 };
1796 }; 1589 };
1797 1590
1798 qup_spi1_cs_gpio: qup !! 1591 qup_i2c11_default: qup-i2c11-default {
1799 pins = "gpio3 !! 1592 pinmux {
1800 function = "g !! 1593 pins = "gpio53", "gpio54";
>> 1594 function = "qup15";
>> 1595 };
1801 }; 1596 };
1802 1597
1803 qup_spi3_spi: qup-spi !! 1598 qup_spi0_default: qup-spi0-default {
1804 pins = "gpio3 !! 1599 pinmux {
1805 function = "q !! 1600 pins = "gpio34", "gpio35",
>> 1601 "gpio36", "gpio37";
>> 1602 function = "qup00";
>> 1603 };
1806 }; 1604 };
1807 1605
1808 qup_spi3_cs: qup-spi3 !! 1606 qup_spi0_cs_gpio: qup-spi0-cs-gpio {
1809 pins = "gpio4 !! 1607 pinmux {
1810 function = "q !! 1608 pins = "gpio34", "gpio35",
1811 }; !! 1609 "gpio36";
>> 1610 function = "qup00";
>> 1611 };
1812 1612
1813 qup_spi3_cs_gpio: qup !! 1613 pinmux-cs {
1814 pins = "gpio4 !! 1614 pins = "gpio37";
1815 function = "g !! 1615 function = "gpio";
>> 1616 };
1816 }; 1617 };
1817 1618
1818 qup_spi5_spi: qup-spi !! 1619 qup_spi1_default: qup-spi1-default {
1819 pins = "gpio2 !! 1620 pinmux {
1820 function = "q !! 1621 pins = "gpio0", "gpio1",
>> 1622 "gpio2", "gpio3";
>> 1623 function = "qup01";
>> 1624 };
1821 }; 1625 };
1822 1626
1823 qup_spi5_cs: qup-spi5 !! 1627 qup_spi1_cs_gpio: qup-spi1-cs-gpio {
1824 pins = "gpio2 !! 1628 pinmux {
1825 function = "q !! 1629 pins = "gpio0", "gpio1",
1826 }; !! 1630 "gpio2";
>> 1631 function = "qup01";
>> 1632 };
1827 1633
1828 qup_spi5_cs_gpio: qup !! 1634 pinmux-cs {
1829 pins = "gpio2 !! 1635 pins = "gpio3";
1830 function = "g !! 1636 function = "gpio";
>> 1637 };
1831 }; 1638 };
1832 1639
1833 qup_spi6_spi: qup-spi !! 1640 qup_spi3_default: qup-spi3-default {
1834 pins = "gpio5 !! 1641 pinmux {
1835 function = "q !! 1642 pins = "gpio38", "gpio39",
>> 1643 "gpio40", "gpio41";
>> 1644 function = "qup03";
>> 1645 };
1836 }; 1646 };
1837 1647
1838 qup_spi6_cs: qup-spi6 !! 1648 qup_spi3_cs_gpio: qup-spi3-cs-gpio {
1839 pins = "gpio6 !! 1649 pinmux {
1840 function = "q !! 1650 pins = "gpio38", "gpio39",
1841 }; !! 1651 "gpio40";
>> 1652 function = "qup03";
>> 1653 };
1842 1654
1843 qup_spi6_cs_gpio: qup !! 1655 pinmux-cs {
1844 pins = "gpio6 !! 1656 pins = "gpio41";
1845 function = "g !! 1657 function = "gpio";
>> 1658 };
1846 }; 1659 };
1847 1660
1848 qup_spi8_spi: qup-spi !! 1661 qup_spi5_default: qup-spi5-default {
1849 pins = "gpio4 !! 1662 pinmux {
1850 function = "q !! 1663 pins = "gpio25", "gpio26",
>> 1664 "gpio27", "gpio28";
>> 1665 function = "qup05";
>> 1666 };
1851 }; 1667 };
1852 1668
1853 qup_spi8_cs: qup-spi8 !! 1669 qup_spi5_cs_gpio: qup-spi5-cs-gpio {
1854 pins = "gpio4 !! 1670 pinmux {
1855 function = "q !! 1671 pins = "gpio25", "gpio26",
1856 }; !! 1672 "gpio27";
>> 1673 function = "qup05";
>> 1674 };
1857 1675
1858 qup_spi8_cs_gpio: qup !! 1676 pinmux-cs {
1859 pins = "gpio4 !! 1677 pins = "gpio28";
1860 function = "g !! 1678 function = "gpio";
>> 1679 };
1861 }; 1680 };
1862 1681
1863 qup_spi10_spi: qup-sp !! 1682 qup_spi6_default: qup-spi6-default {
1864 pins = "gpio8 !! 1683 pinmux {
1865 function = "q !! 1684 pins = "gpio59", "gpio60",
>> 1685 "gpio61", "gpio62";
>> 1686 function = "qup10";
>> 1687 };
1866 }; 1688 };
1867 1689
1868 qup_spi10_cs: qup-spi !! 1690 qup_spi6_cs_gpio: qup-spi6-cs-gpio {
1869 pins = "gpio8 !! 1691 pinmux {
1870 function = "q !! 1692 pins = "gpio59", "gpio60",
1871 }; !! 1693 "gpio61";
>> 1694 function = "qup10";
>> 1695 };
1872 1696
1873 qup_spi10_cs_gpio: qu !! 1697 pinmux-cs {
1874 pins = "gpio8 !! 1698 pins = "gpio62";
1875 function = "g !! 1699 function = "gpio";
>> 1700 };
1876 }; 1701 };
1877 1702
1878 qup_spi11_spi: qup-sp !! 1703 qup_spi8_default: qup-spi8-default {
1879 pins = "gpio5 !! 1704 pinmux {
1880 function = "q !! 1705 pins = "gpio42", "gpio43",
>> 1706 "gpio44", "gpio45";
>> 1707 function = "qup12";
>> 1708 };
1881 }; 1709 };
1882 1710
1883 qup_spi11_cs: qup-spi !! 1711 qup_spi8_cs_gpio: qup-spi8-cs-gpio {
1884 pins = "gpio5 !! 1712 pinmux {
1885 function = "q !! 1713 pins = "gpio42", "gpio43",
1886 }; !! 1714 "gpio44";
>> 1715 function = "qup12";
>> 1716 };
1887 1717
1888 qup_spi11_cs_gpio: qu !! 1718 pinmux-cs {
1889 pins = "gpio5 !! 1719 pins = "gpio45";
1890 function = "g !! 1720 function = "gpio";
>> 1721 };
1891 }; 1722 };
1892 1723
1893 qup_uart0_default: qu !! 1724 qup_spi10_default: qup-spi10-default {
1894 qup_uart0_cts !! 1725 pinmux {
1895 pins !! 1726 pins = "gpio86", "gpio87",
1896 funct !! 1727 "gpio88", "gpio89";
>> 1728 function = "qup14";
1897 }; 1729 };
>> 1730 };
1898 1731
1899 qup_uart0_rts !! 1732 qup_spi10_cs_gpio: qup-spi10-cs-gpio {
1900 pins !! 1733 pinmux {
1901 funct !! 1734 pins = "gpio86", "gpio87",
>> 1735 "gpio88";
>> 1736 function = "qup14";
1902 }; 1737 };
1903 1738
1904 qup_uart0_tx: !! 1739 pinmux-cs {
1905 pins !! 1740 pins = "gpio89";
1906 funct !! 1741 function = "gpio";
1907 }; 1742 };
>> 1743 };
1908 1744
1909 qup_uart0_rx: !! 1745 qup_spi11_default: qup-spi11-default {
1910 pins !! 1746 pinmux {
1911 funct !! 1747 pins = "gpio53", "gpio54",
>> 1748 "gpio55", "gpio56";
>> 1749 function = "qup15";
1912 }; 1750 };
1913 }; 1751 };
1914 1752
1915 qup_uart1_default: qu !! 1753 qup_spi11_cs_gpio: qup-spi11-cs-gpio {
1916 qup_uart1_cts !! 1754 pinmux {
1917 pins !! 1755 pins = "gpio53", "gpio54",
1918 funct !! 1756 "gpio55";
>> 1757 function = "qup15";
1919 }; 1758 };
1920 1759
1921 qup_uart1_rts !! 1760 pinmux-cs {
1922 pins !! 1761 pins = "gpio56";
1923 funct !! 1762 function = "gpio";
1924 }; 1763 };
>> 1764 };
1925 1765
1926 qup_uart1_tx: !! 1766 qup_uart0_default: qup-uart0-default {
1927 pins !! 1767 pinmux {
1928 funct !! 1768 pins = "gpio34", "gpio35",
>> 1769 "gpio36", "gpio37";
>> 1770 function = "qup00";
1929 }; 1771 };
>> 1772 };
1930 1773
1931 qup_uart1_rx: !! 1774 qup_uart1_default: qup-uart1-default {
1932 pins !! 1775 pinmux {
>> 1776 pins = "gpio0", "gpio1",
>> 1777 "gpio2", "gpio3";
1933 funct 1778 function = "qup01";
1934 }; 1779 };
1935 }; 1780 };
1936 1781
1937 qup_uart2_default: qu !! 1782 qup_uart2_default: qup-uart2-default {
1938 qup_uart2_tx: !! 1783 pinmux {
1939 pins !! 1784 pins = "gpio15", "gpio16";
1940 funct <<
1941 }; <<
1942 <<
1943 qup_uart2_rx: <<
1944 pins <<
1945 funct 1785 function = "qup02_uart";
1946 }; 1786 };
1947 }; 1787 };
1948 1788
1949 qup_uart3_default: qu !! 1789 qup_uart3_default: qup-uart3-default {
1950 qup_uart3_cts !! 1790 pinmux {
1951 pins !! 1791 pins = "gpio38", "gpio39",
1952 funct !! 1792 "gpio40", "gpio41";
1953 }; <<
1954 <<
1955 qup_uart3_rts <<
1956 pins <<
1957 funct 1793 function = "qup03";
1958 }; 1794 };
>> 1795 };
1959 1796
1960 qup_uart3_tx: !! 1797 qup_uart4_default: qup-uart4-default {
1961 pins !! 1798 pinmux {
1962 funct !! 1799 pins = "gpio115", "gpio116";
>> 1800 function = "qup04_uart";
1963 }; 1801 };
>> 1802 };
1964 1803
1965 qup_uart3_rx: !! 1804 qup_uart5_default: qup-uart5-default {
1966 pins !! 1805 pinmux {
1967 funct !! 1806 pins = "gpio25", "gpio26",
>> 1807 "gpio27", "gpio28";
>> 1808 function = "qup05";
1968 }; 1809 };
1969 }; 1810 };
1970 1811
1971 qup_uart4_default: qu !! 1812 qup_uart6_default: qup-uart6-default {
1972 qup_uart4_tx: !! 1813 pinmux {
1973 pins !! 1814 pins = "gpio59", "gpio60",
1974 funct !! 1815 "gpio61", "gpio62";
>> 1816 function = "qup10";
1975 }; 1817 };
>> 1818 };
1976 1819
1977 qup_uart4_rx: !! 1820 qup_uart7_default: qup-uart7-default {
1978 pins !! 1821 pinmux {
1979 funct !! 1822 pins = "gpio6", "gpio7";
>> 1823 function = "qup11_uart";
1980 }; 1824 };
1981 }; 1825 };
1982 1826
1983 qup_uart5_default: qu !! 1827 qup_uart8_default: qup-uart8-default {
1984 qup_uart5_cts !! 1828 pinmux {
1985 pins !! 1829 pins = "gpio44", "gpio45";
1986 funct !! 1830 function = "qup12";
1987 }; 1831 };
>> 1832 };
1988 1833
1989 qup_uart5_rts !! 1834 qup_uart9_default: qup-uart9-default {
1990 pins !! 1835 pinmux {
1991 funct !! 1836 pins = "gpio46", "gpio47";
>> 1837 function = "qup13_uart";
1992 }; 1838 };
>> 1839 };
1993 1840
1994 qup_uart5_tx: !! 1841 qup_uart10_default: qup-uart10-default {
1995 pins !! 1842 pinmux {
1996 funct !! 1843 pins = "gpio86", "gpio87",
>> 1844 "gpio88", "gpio89";
>> 1845 function = "qup14";
1997 }; 1846 };
>> 1847 };
1998 1848
1999 qup_uart5_rx: !! 1849 qup_uart11_default: qup-uart11-default {
2000 pins !! 1850 pinmux {
2001 funct !! 1851 pins = "gpio53", "gpio54",
>> 1852 "gpio55", "gpio56";
>> 1853 function = "qup15";
2002 }; 1854 };
2003 }; 1855 };
2004 1856
2005 qup_uart6_default: qu !! 1857 sec_mi2s_active: sec-mi2s-active {
2006 qup_uart6_cts !! 1858 pinmux {
2007 pins !! 1859 pins = "gpio49", "gpio50", "gpio51";
2008 funct !! 1860 function = "mi2s_1";
2009 }; 1861 };
2010 1862
2011 qup_uart6_rts !! 1863 pinconf {
2012 pins !! 1864 pins = "gpio49", "gpio50", "gpio51";
2013 funct !! 1865 drive-strength = <8>;
>> 1866 bias-pull-up;
2014 }; 1867 };
>> 1868 };
2015 1869
2016 qup_uart6_tx: !! 1870 pri_mi2s_active: pri-mi2s-active {
2017 pins !! 1871 pinmux {
2018 funct !! 1872 pins = "gpio53", "gpio54", "gpio55", "gpio56";
>> 1873 function = "mi2s_0";
2019 }; 1874 };
2020 1875
2021 qup_uart6_rx: !! 1876 pinconf {
2022 pins !! 1877 pins = "gpio53", "gpio54", "gpio55", "gpio56";
2023 funct !! 1878 drive-strength = <8>;
>> 1879 bias-pull-up;
2024 }; 1880 };
2025 }; 1881 };
2026 1882
2027 qup_uart7_default: qu !! 1883 pri_mi2s_mclk_active: pri-mi2s-mclk-active {
2028 qup_uart7_tx: !! 1884 pinmux {
2029 pins !! 1885 pins = "gpio57";
2030 funct !! 1886 function = "lpass_ext";
2031 }; 1887 };
2032 1888
2033 qup_uart7_rx: !! 1889 pinconf {
2034 pins !! 1890 pins = "gpio57";
2035 funct !! 1891 drive-strength = <8>;
>> 1892 bias-pull-up;
2036 }; 1893 };
2037 }; 1894 };
2038 1895
2039 qup_uart8_default: qu !! 1896 sdc1_on: sdc1-on {
2040 qup_uart8_tx: !! 1897 pinconf-clk {
2041 pins !! 1898 pins = "sdc1_clk";
2042 funct !! 1899 bias-disable;
>> 1900 drive-strength = <16>;
2043 }; 1901 };
2044 1902
2045 qup_uart8_rx: !! 1903 pinconf-cmd {
2046 pins !! 1904 pins = "sdc1_cmd";
2047 funct !! 1905 bias-pull-up;
>> 1906 drive-strength = <10>;
2048 }; 1907 };
2049 }; <<
2050 1908
2051 qup_uart9_default: qu !! 1909 pinconf-data {
2052 qup_uart9_tx: !! 1910 pins = "sdc1_data";
2053 pins !! 1911 bias-pull-up;
2054 funct !! 1912 drive-strength = <10>;
2055 }; 1913 };
2056 1914
2057 qup_uart9_rx: !! 1915 pinconf-rclk {
2058 pins !! 1916 pins = "sdc1_rclk";
2059 funct !! 1917 bias-pull-down;
2060 }; 1918 };
2061 }; 1919 };
2062 1920
2063 qup_uart10_default: q !! 1921 sdc1_off: sdc1-off {
2064 qup_uart10_ct !! 1922 pinconf-clk {
2065 pins !! 1923 pins = "sdc1_clk";
2066 funct !! 1924 bias-disable;
>> 1925 drive-strength = <2>;
2067 }; 1926 };
2068 1927
2069 qup_uart10_rt !! 1928 pinconf-cmd {
2070 pins !! 1929 pins = "sdc1_cmd";
2071 funct !! 1930 bias-pull-up;
>> 1931 drive-strength = <2>;
2072 }; 1932 };
2073 1933
2074 qup_uart10_tx !! 1934 pinconf-data {
2075 pins !! 1935 pins = "sdc1_data";
2076 funct !! 1936 bias-pull-up;
>> 1937 drive-strength = <2>;
2077 }; 1938 };
2078 1939
2079 qup_uart10_rx !! 1940 pinconf-rclk {
2080 pins !! 1941 pins = "sdc1_rclk";
2081 funct !! 1942 bias-pull-down;
2082 }; 1943 };
2083 }; 1944 };
2084 1945
2085 qup_uart11_default: q !! 1946 sdc2_on: sdc2-on {
2086 qup_uart11_ct !! 1947 pinconf-clk {
2087 pins !! 1948 pins = "sdc2_clk";
2088 funct !! 1949 bias-disable;
>> 1950 drive-strength = <16>;
2089 }; 1951 };
2090 1952
2091 qup_uart11_rt !! 1953 pinconf-cmd {
2092 pins !! 1954 pins = "sdc2_cmd";
2093 funct !! 1955 bias-pull-up;
>> 1956 drive-strength = <10>;
2094 }; 1957 };
2095 1958
2096 qup_uart11_tx !! 1959 pinconf-data {
2097 pins !! 1960 pins = "sdc2_data";
2098 funct !! 1961 bias-pull-up;
>> 1962 drive-strength = <10>;
2099 }; 1963 };
2100 1964
2101 qup_uart11_rx !! 1965 pinconf-sd-cd {
2102 pins !! 1966 pins = "gpio69";
2103 funct !! 1967 bias-pull-up;
>> 1968 drive-strength = <2>;
2104 }; 1969 };
2105 }; 1970 };
2106 1971
2107 sec_mi2s_active: sec- !! 1972 sdc2_off: sdc2-off {
2108 pins = "gpio4 !! 1973 pinconf-clk {
2109 function = "m !! 1974 pins = "sdc2_clk";
2110 }; !! 1975 bias-disable;
>> 1976 drive-strength = <2>;
>> 1977 };
2111 1978
2112 pri_mi2s_active: pri- !! 1979 pinconf-cmd {
2113 pins = "gpio5 !! 1980 pins = "sdc2_cmd";
2114 function = "m !! 1981 bias-pull-up;
2115 }; !! 1982 drive-strength = <2>;
>> 1983 };
2116 1984
2117 pri_mi2s_mclk_active: !! 1985 pinconf-data {
2118 pins = "gpio5 !! 1986 pins = "sdc2_data";
2119 function = "l !! 1987 bias-pull-up;
2120 }; !! 1988 drive-strength = <2>;
>> 1989 };
2121 1990
2122 ter_mi2s_active: ter- !! 1991 pinconf-sd-cd {
2123 pins = "gpio6 !! 1992 pins = "gpio69";
2124 function = "m !! 1993 bias-disable;
>> 1994 drive-strength = <2>;
>> 1995 };
2125 }; 1996 };
2126 }; 1997 };
2127 1998
2128 remoteproc_mpss: remoteproc@4 1999 remoteproc_mpss: remoteproc@4080000 {
2129 compatible = "qcom,sc 2000 compatible = "qcom,sc7180-mpss-pas";
2130 reg = <0 0x04080000 0 !! 2001 reg = <0 0x04080000 0 0x4040>, <0 0x04180000 0 0x48>;
>> 2002 reg-names = "qdsp6", "rmb";
2131 2003
2132 interrupts-extended = 2004 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
2133 2005 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2134 2006 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2135 2007 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2136 2008 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
2137 2009 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
2138 interrupt-names = "wd 2010 interrupt-names = "wdog", "fatal", "ready", "handover",
2139 "st 2011 "stop-ack", "shutdown-ack";
2140 2012
2141 clocks = <&rpmhcc RPM !! 2013 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
2142 clock-names = "xo"; !! 2014 <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>,
>> 2015 <&gcc GCC_MSS_NAV_AXI_CLK>,
>> 2016 <&gcc GCC_MSS_SNOC_AXI_CLK>,
>> 2017 <&gcc GCC_MSS_MFAB_AXIS_CLK>,
>> 2018 <&rpmhcc RPMH_CXO_CLK>;
>> 2019 clock-names = "iface", "bus", "nav", "snoc_axi",
>> 2020 "mnoc_axi", "xo";
2143 2021
2144 power-domains = <&rpm !! 2022 power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>,
>> 2023 <&rpmhpd SC7180_CX>,
2145 <&rpm 2024 <&rpmhpd SC7180_MX>,
2146 <&rpm 2025 <&rpmhpd SC7180_MSS>;
2147 power-domain-names = !! 2026 power-domain-names = "load_state", "cx", "mx", "mss";
2148 2027
2149 memory-region = <&mps 2028 memory-region = <&mpss_mem>;
2150 2029
2151 qcom,qmp = <&aoss_qmp <<
2152 <<
2153 qcom,smem-states = <& 2030 qcom,smem-states = <&modem_smp2p_out 0>;
2154 qcom,smem-state-names 2031 qcom,smem-state-names = "stop";
2155 2032
>> 2033 resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
>> 2034 <&pdc_reset PDC_MODEM_SYNC_RESET>;
>> 2035 reset-names = "mss_restart", "pdc_reset";
>> 2036
>> 2037 qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
>> 2038 qcom,spare-regs = <&tcsr_regs 0xb3e4>;
>> 2039
2156 status = "disabled"; 2040 status = "disabled";
2157 2041
2158 glink-edge { 2042 glink-edge {
2159 interrupts = 2043 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
2160 label = "mode 2044 label = "modem";
2161 qcom,remote-p 2045 qcom,remote-pid = <1>;
2162 mboxes = <&ap 2046 mboxes = <&apss_shared 12>;
2163 }; 2047 };
2164 }; 2048 };
2165 2049
2166 gpu: gpu@5000000 { 2050 gpu: gpu@5000000 {
2167 compatible = "qcom,ad 2051 compatible = "qcom,adreno-618.0", "qcom,adreno";
>> 2052 #stream-id-cells = <16>;
2168 reg = <0 0x05000000 0 2053 reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x1000>,
2169 <0 0x05061000 2054 <0 0x05061000 0 0x800>;
2170 reg-names = "kgsl_3d0 2055 reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc";
2171 interrupts = <GIC_SPI 2056 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2172 iommus = <&adreno_smm 2057 iommus = <&adreno_smmu 0>;
2173 operating-points-v2 = 2058 operating-points-v2 = <&gpu_opp_table>;
2174 qcom,gmu = <&gmu>; 2059 qcom,gmu = <&gmu>;
2175 2060
2176 #cooling-cells = <2>; 2061 #cooling-cells = <2>;
2177 2062
2178 nvmem-cells = <&gpu_s <<
2179 nvmem-cell-names = "s <<
2180 <<
2181 interconnects = <&gem 2063 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
2182 interconnect-names = 2064 interconnect-names = "gfx-mem";
2183 2065
2184 gpu_opp_table: opp-ta 2066 gpu_opp_table: opp-table {
2185 compatible = 2067 compatible = "operating-points-v2";
2186 2068
2187 opp-825000000 <<
2188 opp-h <<
2189 opp-l <<
2190 opp-p <<
2191 opp-s <<
2192 }; <<
2193 <<
2194 opp-800000000 2069 opp-800000000 {
2195 opp-h 2070 opp-hz = /bits/ 64 <800000000>;
2196 opp-l 2071 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2197 opp-p 2072 opp-peak-kBps = <8532000>;
2198 opp-s <<
2199 }; 2073 };
2200 2074
2201 opp-650000000 2075 opp-650000000 {
2202 opp-h 2076 opp-hz = /bits/ 64 <650000000>;
2203 opp-l 2077 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2204 opp-p 2078 opp-peak-kBps = <7216000>;
2205 opp-s <<
2206 }; 2079 };
2207 2080
2208 opp-565000000 2081 opp-565000000 {
2209 opp-h 2082 opp-hz = /bits/ 64 <565000000>;
2210 opp-l 2083 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2211 opp-p 2084 opp-peak-kBps = <5412000>;
2212 opp-s <<
2213 }; 2085 };
2214 2086
2215 opp-430000000 2087 opp-430000000 {
2216 opp-h 2088 opp-hz = /bits/ 64 <430000000>;
2217 opp-l 2089 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2218 opp-p 2090 opp-peak-kBps = <5412000>;
2219 opp-s <<
2220 }; 2091 };
2221 2092
2222 opp-355000000 2093 opp-355000000 {
2223 opp-h 2094 opp-hz = /bits/ 64 <355000000>;
2224 opp-l 2095 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2225 opp-p 2096 opp-peak-kBps = <3072000>;
2226 opp-s <<
2227 }; 2097 };
2228 2098
2229 opp-267000000 2099 opp-267000000 {
2230 opp-h 2100 opp-hz = /bits/ 64 <267000000>;
2231 opp-l 2101 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2232 opp-p 2102 opp-peak-kBps = <3072000>;
2233 opp-s <<
2234 }; 2103 };
2235 2104
2236 opp-180000000 2105 opp-180000000 {
2237 opp-h 2106 opp-hz = /bits/ 64 <180000000>;
2238 opp-l 2107 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2239 opp-p 2108 opp-peak-kBps = <1804000>;
2240 opp-s <<
2241 }; 2109 };
2242 }; 2110 };
2243 }; 2111 };
2244 2112
2245 adreno_smmu: iommu@5040000 { 2113 adreno_smmu: iommu@5040000 {
2246 compatible = "qcom,sc 2114 compatible = "qcom,sc7180-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
2247 reg = <0 0x05040000 0 2115 reg = <0 0x05040000 0 0x10000>;
2248 #iommu-cells = <1>; 2116 #iommu-cells = <1>;
2249 #global-interrupts = 2117 #global-interrupts = <2>;
2250 interrupts = <GIC_SPI 2118 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
2251 <GIC_ 2119 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
2252 <GIC_ 2120 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
2253 <GIC_ 2121 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
2254 <GIC_ 2122 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
2255 <GIC_ 2123 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
2256 <GIC_ 2124 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
2257 <GIC_ 2125 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
2258 <GIC_ 2126 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
2259 <GIC_ 2127 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
2260 2128
2261 clocks = <&gcc GCC_GP 2129 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2262 <&gcc GCC_GPU 2130 <&gcc GCC_GPU_CFG_AHB_CLK>;
2263 clock-names = "bus", 2131 clock-names = "bus", "iface";
2264 2132
2265 power-domains = <&gpu 2133 power-domains = <&gpucc CX_GDSC>;
2266 }; 2134 };
2267 2135
2268 gmu: gmu@506a000 { 2136 gmu: gmu@506a000 {
2269 compatible = "qcom,ad !! 2137 compatible="qcom,adreno-gmu-618.0", "qcom,adreno-gmu";
2270 reg = <0 0x0506a000 0 2138 reg = <0 0x0506a000 0 0x31000>, <0 0x0b290000 0 0x10000>,
2271 <0 0x0b490000 2139 <0 0x0b490000 0 0x10000>;
2272 reg-names = "gmu", "g 2140 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
2273 interrupts = <GIC_SPI 2141 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2274 <GIC_SPI 3 2142 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2275 interrupt-names = "hf 2143 interrupt-names = "hfi", "gmu";
2276 clocks = <&gpucc GPU_ 2144 clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
2277 <&gpucc GPU_CC 2145 <&gpucc GPU_CC_CXO_CLK>,
2278 <&gcc GCC_DDRS 2146 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2279 <&gcc GCC_GPU_ 2147 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
2280 clock-names = "gmu", 2148 clock-names = "gmu", "cxo", "axi", "memnoc";
2281 power-domains = <&gpu 2149 power-domains = <&gpucc CX_GDSC>, <&gpucc GX_GDSC>;
2282 power-domain-names = 2150 power-domain-names = "cx", "gx";
2283 iommus = <&adreno_smm 2151 iommus = <&adreno_smmu 5>;
2284 operating-points-v2 = 2152 operating-points-v2 = <&gmu_opp_table>;
2285 2153
2286 gmu_opp_table: opp-ta 2154 gmu_opp_table: opp-table {
2287 compatible = 2155 compatible = "operating-points-v2";
2288 2156
2289 opp-200000000 2157 opp-200000000 {
2290 opp-h 2158 opp-hz = /bits/ 64 <200000000>;
2291 opp-l 2159 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2292 }; 2160 };
2293 }; 2161 };
2294 }; 2162 };
2295 2163
2296 gpucc: clock-controller@50900 2164 gpucc: clock-controller@5090000 {
2297 compatible = "qcom,sc 2165 compatible = "qcom,sc7180-gpucc";
2298 reg = <0 0x05090000 0 2166 reg = <0 0x05090000 0 0x9000>;
2299 clocks = <&rpmhcc RPM 2167 clocks = <&rpmhcc RPMH_CXO_CLK>,
2300 <&gcc GCC_GP 2168 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2301 <&gcc GCC_GP 2169 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2302 clock-names = "bi_tcx 2170 clock-names = "bi_tcxo",
2303 "gcc_gp 2171 "gcc_gpu_gpll0_clk_src",
2304 "gcc_gp 2172 "gcc_gpu_gpll0_div_clk_src";
2305 #clock-cells = <1>; 2173 #clock-cells = <1>;
2306 #reset-cells = <1>; 2174 #reset-cells = <1>;
2307 #power-domain-cells = 2175 #power-domain-cells = <1>;
2308 }; 2176 };
2309 2177
2310 dma@10a2000 { <<
2311 compatible = "qcom,sc <<
2312 reg = <0x0 0x010a2000 <<
2313 <0x0 0x010ae000 <<
2314 status = "disabled"; <<
2315 }; <<
2316 <<
2317 stm@6002000 { 2178 stm@6002000 {
2318 compatible = "arm,cor 2179 compatible = "arm,coresight-stm", "arm,primecell";
2319 reg = <0 0x06002000 0 2180 reg = <0 0x06002000 0 0x1000>,
2320 <0 0x16280000 0 2181 <0 0x16280000 0 0x180000>;
2321 reg-names = "stm-base 2182 reg-names = "stm-base", "stm-stimulus-base";
2322 2183
2323 clocks = <&aoss_qmp>; 2184 clocks = <&aoss_qmp>;
2324 clock-names = "apb_pc 2185 clock-names = "apb_pclk";
2325 2186
2326 out-ports { 2187 out-ports {
2327 port { 2188 port {
2328 stm_o 2189 stm_out: endpoint {
2329 2190 remote-endpoint = <&funnel0_in7>;
2330 }; 2191 };
2331 }; 2192 };
2332 }; 2193 };
2333 }; 2194 };
2334 2195
2335 funnel@6041000 { 2196 funnel@6041000 {
2336 compatible = "arm,cor 2197 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2337 reg = <0 0x06041000 0 2198 reg = <0 0x06041000 0 0x1000>;
2338 2199
2339 clocks = <&aoss_qmp>; 2200 clocks = <&aoss_qmp>;
2340 clock-names = "apb_pc 2201 clock-names = "apb_pclk";
2341 2202
2342 out-ports { 2203 out-ports {
2343 port { 2204 port {
2344 funne 2205 funnel0_out: endpoint {
2345 2206 remote-endpoint = <&merge_funnel_in0>;
2346 }; 2207 };
2347 }; 2208 };
2348 }; 2209 };
2349 2210
2350 in-ports { 2211 in-ports {
2351 #address-cell 2212 #address-cells = <1>;
2352 #size-cells = 2213 #size-cells = <0>;
2353 2214
2354 port@7 { 2215 port@7 {
2355 reg = 2216 reg = <7>;
2356 funne 2217 funnel0_in7: endpoint {
2357 2218 remote-endpoint = <&stm_out>;
2358 }; 2219 };
2359 }; 2220 };
2360 }; 2221 };
2361 }; 2222 };
2362 2223
2363 funnel@6042000 { 2224 funnel@6042000 {
2364 compatible = "arm,cor 2225 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2365 reg = <0 0x06042000 0 2226 reg = <0 0x06042000 0 0x1000>;
2366 2227
2367 clocks = <&aoss_qmp>; 2228 clocks = <&aoss_qmp>;
2368 clock-names = "apb_pc 2229 clock-names = "apb_pclk";
2369 2230
2370 out-ports { 2231 out-ports {
2371 port { 2232 port {
2372 funne 2233 funnel1_out: endpoint {
2373 2234 remote-endpoint = <&merge_funnel_in1>;
2374 }; 2235 };
2375 }; 2236 };
2376 }; 2237 };
2377 2238
2378 in-ports { 2239 in-ports {
2379 #address-cell 2240 #address-cells = <1>;
2380 #size-cells = 2241 #size-cells = <0>;
2381 2242
2382 port@4 { 2243 port@4 {
2383 reg = 2244 reg = <4>;
2384 funne 2245 funnel1_in4: endpoint {
2385 2246 remote-endpoint = <&apss_merge_funnel_out>;
2386 }; 2247 };
2387 }; 2248 };
2388 }; 2249 };
2389 }; 2250 };
2390 2251
2391 funnel@6045000 { 2252 funnel@6045000 {
2392 compatible = "arm,cor 2253 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2393 reg = <0 0x06045000 0 2254 reg = <0 0x06045000 0 0x1000>;
2394 2255
2395 clocks = <&aoss_qmp>; 2256 clocks = <&aoss_qmp>;
2396 clock-names = "apb_pc 2257 clock-names = "apb_pclk";
2397 2258
2398 out-ports { 2259 out-ports {
2399 port { 2260 port {
2400 merge 2261 merge_funnel_out: endpoint {
2401 2262 remote-endpoint = <&swao_funnel_in>;
2402 }; 2263 };
2403 }; 2264 };
2404 }; 2265 };
2405 2266
2406 in-ports { 2267 in-ports {
2407 #address-cell 2268 #address-cells = <1>;
2408 #size-cells = 2269 #size-cells = <0>;
2409 2270
2410 port@0 { 2271 port@0 {
2411 reg = 2272 reg = <0>;
2412 merge 2273 merge_funnel_in0: endpoint {
2413 2274 remote-endpoint = <&funnel0_out>;
2414 }; 2275 };
2415 }; 2276 };
2416 2277
2417 port@1 { 2278 port@1 {
2418 reg = 2279 reg = <1>;
2419 merge 2280 merge_funnel_in1: endpoint {
2420 2281 remote-endpoint = <&funnel1_out>;
2421 }; 2282 };
2422 }; 2283 };
2423 }; 2284 };
2424 }; 2285 };
2425 2286
2426 replicator@6046000 { 2287 replicator@6046000 {
2427 compatible = "arm,cor 2288 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2428 reg = <0 0x06046000 0 2289 reg = <0 0x06046000 0 0x1000>;
2429 2290
2430 clocks = <&aoss_qmp>; 2291 clocks = <&aoss_qmp>;
2431 clock-names = "apb_pc 2292 clock-names = "apb_pclk";
2432 2293
2433 out-ports { 2294 out-ports {
2434 port { 2295 port {
2435 repli 2296 replicator_out: endpoint {
2436 2297 remote-endpoint = <&etr_in>;
2437 }; 2298 };
2438 }; 2299 };
2439 }; 2300 };
2440 2301
2441 in-ports { 2302 in-ports {
2442 port { 2303 port {
2443 repli 2304 replicator_in: endpoint {
2444 2305 remote-endpoint = <&swao_replicator_out>;
2445 }; 2306 };
2446 }; 2307 };
2447 }; 2308 };
2448 }; 2309 };
2449 2310
2450 etr@6048000 { 2311 etr@6048000 {
2451 compatible = "arm,cor 2312 compatible = "arm,coresight-tmc", "arm,primecell";
2452 reg = <0 0x06048000 0 2313 reg = <0 0x06048000 0 0x1000>;
2453 iommus = <&apps_smmu 2314 iommus = <&apps_smmu 0x04a0 0x20>;
2454 2315
2455 clocks = <&aoss_qmp>; 2316 clocks = <&aoss_qmp>;
2456 clock-names = "apb_pc 2317 clock-names = "apb_pclk";
2457 arm,scatter-gather; 2318 arm,scatter-gather;
2458 2319
2459 in-ports { 2320 in-ports {
2460 port { 2321 port {
2461 etr_i 2322 etr_in: endpoint {
2462 2323 remote-endpoint = <&replicator_out>;
2463 }; 2324 };
2464 }; 2325 };
2465 }; 2326 };
2466 }; 2327 };
2467 2328
2468 funnel@6b04000 { 2329 funnel@6b04000 {
2469 compatible = "arm,cor 2330 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2470 reg = <0 0x06b04000 0 2331 reg = <0 0x06b04000 0 0x1000>;
2471 2332
2472 clocks = <&aoss_qmp>; 2333 clocks = <&aoss_qmp>;
2473 clock-names = "apb_pc 2334 clock-names = "apb_pclk";
2474 2335
2475 out-ports { 2336 out-ports {
2476 port { 2337 port {
2477 swao_ 2338 swao_funnel_out: endpoint {
2478 2339 remote-endpoint = <&etf_in>;
2479 }; 2340 };
2480 }; 2341 };
2481 }; 2342 };
2482 2343
2483 in-ports { 2344 in-ports {
2484 #address-cell 2345 #address-cells = <1>;
2485 #size-cells = 2346 #size-cells = <0>;
2486 2347
2487 port@7 { 2348 port@7 {
2488 reg = 2349 reg = <7>;
2489 swao_ 2350 swao_funnel_in: endpoint {
2490 2351 remote-endpoint = <&merge_funnel_out>;
2491 }; 2352 };
2492 }; 2353 };
2493 }; 2354 };
2494 }; 2355 };
2495 2356
2496 etf@6b05000 { 2357 etf@6b05000 {
2497 compatible = "arm,cor 2358 compatible = "arm,coresight-tmc", "arm,primecell";
2498 reg = <0 0x06b05000 0 2359 reg = <0 0x06b05000 0 0x1000>;
2499 2360
2500 clocks = <&aoss_qmp>; 2361 clocks = <&aoss_qmp>;
2501 clock-names = "apb_pc 2362 clock-names = "apb_pclk";
2502 2363
2503 out-ports { 2364 out-ports {
2504 port { 2365 port {
2505 etf_o 2366 etf_out: endpoint {
2506 2367 remote-endpoint = <&swao_replicator_in>;
2507 }; 2368 };
2508 }; 2369 };
2509 }; 2370 };
2510 2371
2511 in-ports { 2372 in-ports {
2512 port { 2373 port {
2513 etf_i 2374 etf_in: endpoint {
2514 2375 remote-endpoint = <&swao_funnel_out>;
2515 }; 2376 };
2516 }; 2377 };
2517 }; 2378 };
2518 }; 2379 };
2519 2380
2520 replicator@6b06000 { 2381 replicator@6b06000 {
2521 compatible = "arm,cor 2382 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2522 reg = <0 0x06b06000 0 2383 reg = <0 0x06b06000 0 0x1000>;
2523 2384
2524 clocks = <&aoss_qmp>; 2385 clocks = <&aoss_qmp>;
2525 clock-names = "apb_pc 2386 clock-names = "apb_pclk";
2526 qcom,replicator-loses 2387 qcom,replicator-loses-context;
2527 2388
2528 out-ports { 2389 out-ports {
2529 port { 2390 port {
2530 swao_ 2391 swao_replicator_out: endpoint {
2531 2392 remote-endpoint = <&replicator_in>;
2532 }; 2393 };
2533 }; 2394 };
2534 }; 2395 };
2535 2396
2536 in-ports { 2397 in-ports {
2537 port { 2398 port {
2538 swao_ 2399 swao_replicator_in: endpoint {
2539 2400 remote-endpoint = <&etf_out>;
2540 }; 2401 };
2541 }; 2402 };
2542 }; 2403 };
2543 }; 2404 };
2544 2405
2545 etm@7040000 { 2406 etm@7040000 {
2546 compatible = "arm,cor 2407 compatible = "arm,coresight-etm4x", "arm,primecell";
2547 reg = <0 0x07040000 0 2408 reg = <0 0x07040000 0 0x1000>;
2548 2409
2549 cpu = <&CPU0>; 2410 cpu = <&CPU0>;
2550 2411
2551 clocks = <&aoss_qmp>; 2412 clocks = <&aoss_qmp>;
2552 clock-names = "apb_pc 2413 clock-names = "apb_pclk";
2553 arm,coresight-loses-c 2414 arm,coresight-loses-context-with-cpu;
2554 qcom,skip-power-up; 2415 qcom,skip-power-up;
2555 2416
2556 out-ports { 2417 out-ports {
2557 port { 2418 port {
2558 etm0_ 2419 etm0_out: endpoint {
2559 2420 remote-endpoint = <&apss_funnel_in0>;
2560 }; 2421 };
2561 }; 2422 };
2562 }; 2423 };
2563 }; 2424 };
2564 2425
2565 etm@7140000 { 2426 etm@7140000 {
2566 compatible = "arm,cor 2427 compatible = "arm,coresight-etm4x", "arm,primecell";
2567 reg = <0 0x07140000 0 2428 reg = <0 0x07140000 0 0x1000>;
2568 2429
2569 cpu = <&CPU1>; 2430 cpu = <&CPU1>;
2570 2431
2571 clocks = <&aoss_qmp>; 2432 clocks = <&aoss_qmp>;
2572 clock-names = "apb_pc 2433 clock-names = "apb_pclk";
2573 arm,coresight-loses-c 2434 arm,coresight-loses-context-with-cpu;
2574 qcom,skip-power-up; 2435 qcom,skip-power-up;
2575 2436
2576 out-ports { 2437 out-ports {
2577 port { 2438 port {
2578 etm1_ 2439 etm1_out: endpoint {
2579 2440 remote-endpoint = <&apss_funnel_in1>;
2580 }; 2441 };
2581 }; 2442 };
2582 }; 2443 };
2583 }; 2444 };
2584 2445
2585 etm@7240000 { 2446 etm@7240000 {
2586 compatible = "arm,cor 2447 compatible = "arm,coresight-etm4x", "arm,primecell";
2587 reg = <0 0x07240000 0 2448 reg = <0 0x07240000 0 0x1000>;
2588 2449
2589 cpu = <&CPU2>; 2450 cpu = <&CPU2>;
2590 2451
2591 clocks = <&aoss_qmp>; 2452 clocks = <&aoss_qmp>;
2592 clock-names = "apb_pc 2453 clock-names = "apb_pclk";
2593 arm,coresight-loses-c 2454 arm,coresight-loses-context-with-cpu;
2594 qcom,skip-power-up; 2455 qcom,skip-power-up;
2595 2456
2596 out-ports { 2457 out-ports {
2597 port { 2458 port {
2598 etm2_ 2459 etm2_out: endpoint {
2599 2460 remote-endpoint = <&apss_funnel_in2>;
2600 }; 2461 };
2601 }; 2462 };
2602 }; 2463 };
2603 }; 2464 };
2604 2465
2605 etm@7340000 { 2466 etm@7340000 {
2606 compatible = "arm,cor 2467 compatible = "arm,coresight-etm4x", "arm,primecell";
2607 reg = <0 0x07340000 0 2468 reg = <0 0x07340000 0 0x1000>;
2608 2469
2609 cpu = <&CPU3>; 2470 cpu = <&CPU3>;
2610 2471
2611 clocks = <&aoss_qmp>; 2472 clocks = <&aoss_qmp>;
2612 clock-names = "apb_pc 2473 clock-names = "apb_pclk";
2613 arm,coresight-loses-c 2474 arm,coresight-loses-context-with-cpu;
2614 qcom,skip-power-up; 2475 qcom,skip-power-up;
2615 2476
2616 out-ports { 2477 out-ports {
2617 port { 2478 port {
2618 etm3_ 2479 etm3_out: endpoint {
2619 2480 remote-endpoint = <&apss_funnel_in3>;
2620 }; 2481 };
2621 }; 2482 };
2622 }; 2483 };
2623 }; 2484 };
2624 2485
2625 etm@7440000 { 2486 etm@7440000 {
2626 compatible = "arm,cor 2487 compatible = "arm,coresight-etm4x", "arm,primecell";
2627 reg = <0 0x07440000 0 2488 reg = <0 0x07440000 0 0x1000>;
2628 2489
2629 cpu = <&CPU4>; 2490 cpu = <&CPU4>;
2630 2491
2631 clocks = <&aoss_qmp>; 2492 clocks = <&aoss_qmp>;
2632 clock-names = "apb_pc 2493 clock-names = "apb_pclk";
2633 arm,coresight-loses-c 2494 arm,coresight-loses-context-with-cpu;
2634 qcom,skip-power-up; 2495 qcom,skip-power-up;
2635 2496
2636 out-ports { 2497 out-ports {
2637 port { 2498 port {
2638 etm4_ 2499 etm4_out: endpoint {
2639 2500 remote-endpoint = <&apss_funnel_in4>;
2640 }; 2501 };
2641 }; 2502 };
2642 }; 2503 };
2643 }; 2504 };
2644 2505
2645 etm@7540000 { 2506 etm@7540000 {
2646 compatible = "arm,cor 2507 compatible = "arm,coresight-etm4x", "arm,primecell";
2647 reg = <0 0x07540000 0 2508 reg = <0 0x07540000 0 0x1000>;
2648 2509
2649 cpu = <&CPU5>; 2510 cpu = <&CPU5>;
2650 2511
2651 clocks = <&aoss_qmp>; 2512 clocks = <&aoss_qmp>;
2652 clock-names = "apb_pc 2513 clock-names = "apb_pclk";
2653 arm,coresight-loses-c 2514 arm,coresight-loses-context-with-cpu;
2654 qcom,skip-power-up; 2515 qcom,skip-power-up;
2655 2516
2656 out-ports { 2517 out-ports {
2657 port { 2518 port {
2658 etm5_ 2519 etm5_out: endpoint {
2659 2520 remote-endpoint = <&apss_funnel_in5>;
2660 }; 2521 };
2661 }; 2522 };
2662 }; 2523 };
2663 }; 2524 };
2664 2525
2665 etm@7640000 { 2526 etm@7640000 {
2666 compatible = "arm,cor 2527 compatible = "arm,coresight-etm4x", "arm,primecell";
2667 reg = <0 0x07640000 0 2528 reg = <0 0x07640000 0 0x1000>;
2668 2529
2669 cpu = <&CPU6>; 2530 cpu = <&CPU6>;
2670 2531
2671 clocks = <&aoss_qmp>; 2532 clocks = <&aoss_qmp>;
2672 clock-names = "apb_pc 2533 clock-names = "apb_pclk";
2673 arm,coresight-loses-c 2534 arm,coresight-loses-context-with-cpu;
2674 qcom,skip-power-up; 2535 qcom,skip-power-up;
2675 2536
2676 out-ports { 2537 out-ports {
2677 port { 2538 port {
2678 etm6_ 2539 etm6_out: endpoint {
2679 2540 remote-endpoint = <&apss_funnel_in6>;
2680 }; 2541 };
2681 }; 2542 };
2682 }; 2543 };
2683 }; 2544 };
2684 2545
2685 etm@7740000 { 2546 etm@7740000 {
2686 compatible = "arm,cor 2547 compatible = "arm,coresight-etm4x", "arm,primecell";
2687 reg = <0 0x07740000 0 2548 reg = <0 0x07740000 0 0x1000>;
2688 2549
2689 cpu = <&CPU7>; 2550 cpu = <&CPU7>;
2690 2551
2691 clocks = <&aoss_qmp>; 2552 clocks = <&aoss_qmp>;
2692 clock-names = "apb_pc 2553 clock-names = "apb_pclk";
2693 arm,coresight-loses-c 2554 arm,coresight-loses-context-with-cpu;
2694 qcom,skip-power-up; 2555 qcom,skip-power-up;
2695 2556
2696 out-ports { 2557 out-ports {
2697 port { 2558 port {
2698 etm7_ 2559 etm7_out: endpoint {
2699 2560 remote-endpoint = <&apss_funnel_in7>;
2700 }; 2561 };
2701 }; 2562 };
2702 }; 2563 };
2703 }; 2564 };
2704 2565
2705 funnel@7800000 { /* APSS Funn 2566 funnel@7800000 { /* APSS Funnel */
2706 compatible = "arm,cor 2567 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2707 reg = <0 0x07800000 0 2568 reg = <0 0x07800000 0 0x1000>;
2708 2569
2709 clocks = <&aoss_qmp>; 2570 clocks = <&aoss_qmp>;
2710 clock-names = "apb_pc 2571 clock-names = "apb_pclk";
2711 2572
2712 out-ports { 2573 out-ports {
2713 port { 2574 port {
2714 apss_ 2575 apss_funnel_out: endpoint {
2715 2576 remote-endpoint = <&apss_merge_funnel_in>;
2716 }; 2577 };
2717 }; 2578 };
2718 }; 2579 };
2719 2580
2720 in-ports { 2581 in-ports {
2721 #address-cell 2582 #address-cells = <1>;
2722 #size-cells = 2583 #size-cells = <0>;
2723 2584
2724 port@0 { 2585 port@0 {
2725 reg = 2586 reg = <0>;
2726 apss_ 2587 apss_funnel_in0: endpoint {
2727 2588 remote-endpoint = <&etm0_out>;
2728 }; 2589 };
2729 }; 2590 };
2730 2591
2731 port@1 { 2592 port@1 {
2732 reg = 2593 reg = <1>;
2733 apss_ 2594 apss_funnel_in1: endpoint {
2734 2595 remote-endpoint = <&etm1_out>;
2735 }; 2596 };
2736 }; 2597 };
2737 2598
2738 port@2 { 2599 port@2 {
2739 reg = 2600 reg = <2>;
2740 apss_ 2601 apss_funnel_in2: endpoint {
2741 2602 remote-endpoint = <&etm2_out>;
2742 }; 2603 };
2743 }; 2604 };
2744 2605
2745 port@3 { 2606 port@3 {
2746 reg = 2607 reg = <3>;
2747 apss_ 2608 apss_funnel_in3: endpoint {
2748 2609 remote-endpoint = <&etm3_out>;
2749 }; 2610 };
2750 }; 2611 };
2751 2612
2752 port@4 { 2613 port@4 {
2753 reg = 2614 reg = <4>;
2754 apss_ 2615 apss_funnel_in4: endpoint {
2755 2616 remote-endpoint = <&etm4_out>;
2756 }; 2617 };
2757 }; 2618 };
2758 2619
2759 port@5 { 2620 port@5 {
2760 reg = 2621 reg = <5>;
2761 apss_ 2622 apss_funnel_in5: endpoint {
2762 2623 remote-endpoint = <&etm5_out>;
2763 }; 2624 };
2764 }; 2625 };
2765 2626
2766 port@6 { 2627 port@6 {
2767 reg = 2628 reg = <6>;
2768 apss_ 2629 apss_funnel_in6: endpoint {
2769 2630 remote-endpoint = <&etm6_out>;
2770 }; 2631 };
2771 }; 2632 };
2772 2633
2773 port@7 { 2634 port@7 {
2774 reg = 2635 reg = <7>;
2775 apss_ 2636 apss_funnel_in7: endpoint {
2776 2637 remote-endpoint = <&etm7_out>;
2777 }; 2638 };
2778 }; 2639 };
2779 }; 2640 };
2780 }; 2641 };
2781 2642
2782 funnel@7810000 { 2643 funnel@7810000 {
2783 compatible = "arm,cor 2644 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2784 reg = <0 0x07810000 0 2645 reg = <0 0x07810000 0 0x1000>;
2785 2646
2786 clocks = <&aoss_qmp>; 2647 clocks = <&aoss_qmp>;
2787 clock-names = "apb_pc 2648 clock-names = "apb_pclk";
2788 2649
2789 out-ports { 2650 out-ports {
2790 port { 2651 port {
2791 apss_ 2652 apss_merge_funnel_out: endpoint {
2792 2653 remote-endpoint = <&funnel1_in4>;
2793 }; 2654 };
2794 }; 2655 };
2795 }; 2656 };
2796 2657
2797 in-ports { 2658 in-ports {
2798 port { 2659 port {
2799 apss_ 2660 apss_merge_funnel_in: endpoint {
2800 2661 remote-endpoint = <&apss_funnel_out>;
2801 }; 2662 };
2802 }; 2663 };
2803 }; 2664 };
2804 }; 2665 };
2805 2666
2806 sdhc_2: mmc@8804000 { !! 2667 sdhc_2: sdhci@8804000 {
2807 compatible = "qcom,sc 2668 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
2808 reg = <0 0x08804000 0 2669 reg = <0 0x08804000 0 0x1000>;
2809 2670
2810 iommus = <&apps_smmu 2671 iommus = <&apps_smmu 0x80 0>;
2811 interrupts = <GIC_SPI 2672 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
2812 <GIC_ 2673 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
2813 interrupt-names = "hc 2674 interrupt-names = "hc_irq", "pwr_irq";
2814 2675
2815 clocks = <&gcc GCC_SD !! 2676 clocks = <&gcc GCC_SDCC2_APPS_CLK>,
2816 <&gcc GCC_SD !! 2677 <&gcc GCC_SDCC2_AHB_CLK>;
2817 <&rpmhcc RPM !! 2678 clock-names = "core", "iface";
2818 clock-names = "iface" <<
2819 2679
2820 interconnects = <&agg 2680 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
2821 <&gem 2681 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
2822 interconnect-names = 2682 interconnect-names = "sdhc-ddr","cpu-sdhc";
2823 power-domains = <&rpm 2683 power-domains = <&rpmhpd SC7180_CX>;
2824 operating-points-v2 = 2684 operating-points-v2 = <&sdhc2_opp_table>;
2825 2685
2826 bus-width = <4>; 2686 bus-width = <4>;
2827 2687
2828 status = "disabled"; 2688 status = "disabled";
2829 2689
2830 sdhc2_opp_table: opp- !! 2690 sdhc2_opp_table: sdhc2-opp-table {
2831 compatible = 2691 compatible = "operating-points-v2";
2832 2692
2833 opp-100000000 2693 opp-100000000 {
2834 opp-h 2694 opp-hz = /bits/ 64 <100000000>;
2835 requi 2695 required-opps = <&rpmhpd_opp_low_svs>;
2836 opp-p !! 2696 opp-peak-kBps = <160000 100000>;
2837 opp-a !! 2697 opp-avg-kBps = <80000 50000>;
2838 }; 2698 };
2839 2699
2840 opp-202000000 2700 opp-202000000 {
2841 opp-h 2701 opp-hz = /bits/ 64 <202000000>;
2842 requi !! 2702 required-opps = <&rpmhpd_opp_svs_l1>;
2843 opp-p !! 2703 opp-peak-kBps = <200000 120000>;
2844 opp-a !! 2704 opp-avg-kBps = <100000 60000>;
2845 }; 2705 };
2846 }; 2706 };
2847 }; 2707 };
2848 2708
>> 2709 qspi_opp_table: qspi-opp-table {
>> 2710 compatible = "operating-points-v2";
>> 2711
>> 2712 opp-75000000 {
>> 2713 opp-hz = /bits/ 64 <75000000>;
>> 2714 required-opps = <&rpmhpd_opp_low_svs>;
>> 2715 };
>> 2716
>> 2717 opp-150000000 {
>> 2718 opp-hz = /bits/ 64 <150000000>;
>> 2719 required-opps = <&rpmhpd_opp_svs>;
>> 2720 };
>> 2721
>> 2722 opp-300000000 {
>> 2723 opp-hz = /bits/ 64 <300000000>;
>> 2724 required-opps = <&rpmhpd_opp_nom>;
>> 2725 };
>> 2726 };
>> 2727
2849 qspi: spi@88dc000 { 2728 qspi: spi@88dc000 {
2850 compatible = "qcom,sc !! 2729 compatible = "qcom,qspi-v1";
2851 reg = <0 0x088dc000 0 2730 reg = <0 0x088dc000 0 0x600>;
2852 iommus = <&apps_smmu <<
2853 #address-cells = <1>; 2731 #address-cells = <1>;
2854 #size-cells = <0>; 2732 #size-cells = <0>;
2855 interrupts = <GIC_SPI 2733 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
2856 clocks = <&gcc GCC_QS 2734 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
2857 <&gcc GCC_QS 2735 <&gcc GCC_QSPI_CORE_CLK>;
2858 clock-names = "iface" 2736 clock-names = "iface", "core";
2859 interconnects = <&gem 2737 interconnects = <&gem_noc MASTER_APPSS_PROC 0
2860 &conf 2738 &config_noc SLAVE_QSPI_0 0>;
2861 interconnect-names = 2739 interconnect-names = "qspi-config";
2862 power-domains = <&rpm 2740 power-domains = <&rpmhpd SC7180_CX>;
2863 operating-points-v2 = 2741 operating-points-v2 = <&qspi_opp_table>;
2864 status = "disabled"; 2742 status = "disabled";
2865 }; 2743 };
2866 2744
2867 usb_1_hsphy: phy@88e3000 { 2745 usb_1_hsphy: phy@88e3000 {
2868 compatible = "qcom,sc 2746 compatible = "qcom,sc7180-qusb2-phy", "qcom,qusb2-v2-phy";
2869 reg = <0 0x088e3000 0 2747 reg = <0 0x088e3000 0 0x400>;
2870 status = "disabled"; 2748 status = "disabled";
2871 #phy-cells = <0>; 2749 #phy-cells = <0>;
2872 clocks = <&gcc GCC_US 2750 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2873 <&rpmhcc RPM 2751 <&rpmhcc RPMH_CXO_CLK>;
2874 clock-names = "cfg_ah 2752 clock-names = "cfg_ahb", "ref";
2875 resets = <&gcc GCC_QU 2753 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2876 2754
2877 nvmem-cells = <&qusb2 2755 nvmem-cells = <&qusb2p_hstx_trim>;
2878 }; 2756 };
2879 2757
2880 usb_1_qmpphy: phy@88e8000 { !! 2758 usb_1_qmpphy: phy-wrapper@88e9000 {
2881 compatible = "qcom,sc !! 2759 compatible = "qcom,sc7180-qmp-usb3-phy";
2882 reg = <0 0x088e8000 0 !! 2760 reg = <0 0x088e9000 0 0x18c>,
>> 2761 <0 0x088e8000 0 0x38>;
>> 2762 reg-names = "reg-base", "dp_com";
2883 status = "disabled"; 2763 status = "disabled";
>> 2764 #clock-cells = <1>;
>> 2765 #address-cells = <2>;
>> 2766 #size-cells = <2>;
>> 2767 ranges;
2884 2768
2885 clocks = <&gcc GCC_US 2769 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
>> 2770 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2886 <&gcc GCC_US 2771 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
2887 <&gcc GCC_US !! 2772 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
2888 <&gcc GCC_US !! 2773 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
2889 <&gcc GCC_US <<
2890 clock-names = "aux", <<
2891 "ref", <<
2892 "com_au <<
2893 "usb3_p <<
2894 "cfg_ah <<
2895 2774
2896 resets = <&gcc GCC_US 2775 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
2897 <&gcc GCC_US 2776 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
2898 reset-names = "phy", 2777 reset-names = "phy", "common";
2899 2778
2900 #clock-cells = <1>; !! 2779 usb_1_ssphy: phy@88e9200 {
2901 #phy-cells = <1>; !! 2780 reg = <0 0x088e9200 0 0x128>,
2902 }; !! 2781 <0 0x088e9400 0 0x200>,
2903 !! 2782 <0 0x088e9c00 0 0x218>,
2904 pmu@90b6300 { !! 2783 <0 0x088e9600 0 0x128>,
2905 compatible = "qcom,sc !! 2784 <0 0x088e9800 0 0x200>,
2906 reg = <0 0x090b6300 0 !! 2785 <0 0x088e9a00 0 0x18>;
2907 interrupts = <GIC_SPI !! 2786 #clock-cells = <0>;
2908 !! 2787 #phy-cells = <0>;
2909 interconnects = <&gem !! 2788 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2910 &gem !! 2789 clock-names = "pipe0";
2911 operating-points-v2 = !! 2790 clock-output-names = "usb3_phy_pipe_clk_src";
2912 <<
2913 cpu_bwmon_opp_table: <<
2914 compatible = <<
2915 <<
2916 opp-0 { <<
2917 opp-p <<
2918 }; <<
2919 <<
2920 opp-1 { <<
2921 opp-p <<
2922 }; <<
2923 <<
2924 opp-2 { <<
2925 opp-p <<
2926 }; <<
2927 <<
2928 opp-3 { <<
2929 opp-p <<
2930 }; <<
2931 <<
2932 opp-4 { <<
2933 opp-p <<
2934 }; <<
2935 <<
2936 opp-5 { <<
2937 opp-p <<
2938 }; <<
2939 }; <<
2940 }; <<
2941 <<
2942 pmu@90cd000 { <<
2943 compatible = "qcom,sc <<
2944 reg = <0 0x090cd000 0 <<
2945 interrupts = <GIC_SPI <<
2946 <<
2947 interconnects = <&mc_ <<
2948 &mc_ <<
2949 operating-points-v2 = <<
2950 <<
2951 llcc_bwmon_opp_table: <<
2952 compatible = <<
2953 <<
2954 opp-0 { <<
2955 opp-p <<
2956 }; <<
2957 <<
2958 opp-1 { <<
2959 opp-p <<
2960 }; <<
2961 <<
2962 opp-2 { <<
2963 opp-p <<
2964 }; <<
2965 <<
2966 opp-3 { <<
2967 opp-p <<
2968 }; <<
2969 <<
2970 opp-4 { <<
2971 opp-p <<
2972 }; <<
2973 <<
2974 opp-5 { <<
2975 opp-p <<
2976 }; <<
2977 <<
2978 opp-6 { <<
2979 opp-p <<
2980 }; <<
2981 <<
2982 opp-7 { <<
2983 opp-p <<
2984 }; <<
2985 }; 2791 };
2986 }; 2792 };
2987 2793
2988 dc_noc: interconnect@9160000 2794 dc_noc: interconnect@9160000 {
2989 compatible = "qcom,sc 2795 compatible = "qcom,sc7180-dc-noc";
2990 reg = <0 0x09160000 0 2796 reg = <0 0x09160000 0 0x03200>;
2991 #interconnect-cells = 2797 #interconnect-cells = <2>;
2992 qcom,bcm-voters = <&a 2798 qcom,bcm-voters = <&apps_bcm_voter>;
2993 }; 2799 };
2994 2800
2995 system-cache-controller@92000 2801 system-cache-controller@9200000 {
2996 compatible = "qcom,sc 2802 compatible = "qcom,sc7180-llcc";
2997 reg = <0 0x09200000 0 2803 reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>;
2998 reg-names = "llcc0_ba !! 2804 reg-names = "llcc_base", "llcc_broadcast_base";
2999 interrupts = <GIC_SPI 2805 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
3000 }; 2806 };
3001 2807
3002 gem_noc: interconnect@9680000 2808 gem_noc: interconnect@9680000 {
3003 compatible = "qcom,sc 2809 compatible = "qcom,sc7180-gem-noc";
3004 reg = <0 0x09680000 0 2810 reg = <0 0x09680000 0 0x3e200>;
3005 #interconnect-cells = 2811 #interconnect-cells = <2>;
3006 qcom,bcm-voters = <&a 2812 qcom,bcm-voters = <&apps_bcm_voter>;
3007 }; 2813 };
3008 2814
3009 npu_noc: interconnect@9990000 2815 npu_noc: interconnect@9990000 {
3010 compatible = "qcom,sc 2816 compatible = "qcom,sc7180-npu-noc";
3011 reg = <0 0x09990000 0 2817 reg = <0 0x09990000 0 0x1600>;
3012 #interconnect-cells = 2818 #interconnect-cells = <2>;
3013 qcom,bcm-voters = <&a 2819 qcom,bcm-voters = <&apps_bcm_voter>;
3014 }; 2820 };
3015 2821
3016 usb_1: usb@a6f8800 { 2822 usb_1: usb@a6f8800 {
3017 compatible = "qcom,sc 2823 compatible = "qcom,sc7180-dwc3", "qcom,dwc3";
3018 reg = <0 0x0a6f8800 0 2824 reg = <0 0x0a6f8800 0 0x400>;
3019 status = "disabled"; 2825 status = "disabled";
3020 #address-cells = <2>; 2826 #address-cells = <2>;
3021 #size-cells = <2>; 2827 #size-cells = <2>;
3022 ranges; 2828 ranges;
3023 dma-ranges; 2829 dma-ranges;
3024 2830
3025 clocks = <&gcc GCC_CF 2831 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
3026 <&gcc GCC_US 2832 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
3027 <&gcc GCC_AG 2833 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
3028 <&gcc GCC_US !! 2834 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3029 <&gcc GCC_US !! 2835 <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
3030 clock-names = "cfg_no !! 2836 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
3031 "core", !! 2837 "sleep";
3032 "iface" <<
3033 "sleep" <<
3034 "mock_u <<
3035 2838
3036 assigned-clocks = <&g 2839 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3037 <&g 2840 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
3038 assigned-clock-rates 2841 assigned-clock-rates = <19200000>, <150000000>;
3039 2842
3040 interrupts-extended = !! 2843 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
3041 !! 2844 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
3042 !! 2845 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
3043 !! 2846 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
3044 !! 2847 interrupt-names = "hs_phy_irq", "ss_phy_irq",
3045 interrupt-names = "pw !! 2848 "dm_hs_phy_irq", "dp_hs_phy_irq";
3046 "hs <<
3047 "dp <<
3048 "dm <<
3049 "ss <<
3050 2849
3051 power-domains = <&gcc 2850 power-domains = <&gcc USB30_PRIM_GDSC>;
3052 required-opps = <&rpm <<
3053 2851
3054 resets = <&gcc GCC_US 2852 resets = <&gcc GCC_USB30_PRIM_BCR>;
3055 2853
3056 interconnects = <&agg 2854 interconnects = <&aggre2_noc MASTER_USB3 0 &mc_virt SLAVE_EBI1 0>,
3057 <&gem 2855 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3 0>;
3058 interconnect-names = 2856 interconnect-names = "usb-ddr", "apps-usb";
3059 2857
3060 wakeup-source; !! 2858 usb_1_dwc3: dwc3@a600000 {
3061 <<
3062 usb_1_dwc3: usb@a6000 <<
3063 compatible = 2859 compatible = "snps,dwc3";
3064 reg = <0 0x0a 2860 reg = <0 0x0a600000 0 0xe000>;
3065 interrupts = 2861 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
3066 iommus = <&ap 2862 iommus = <&apps_smmu 0x540 0>;
3067 snps,dis_u2_s 2863 snps,dis_u2_susphy_quirk;
3068 snps,dis_enbl 2864 snps,dis_enblslpm_quirk;
3069 snps,parkmode !! 2865 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
3070 phys = <&usb_ <<
3071 phy-names = " 2866 phy-names = "usb2-phy", "usb3-phy";
3072 maximum-speed 2867 maximum-speed = "super-speed";
3073 }; 2868 };
3074 }; 2869 };
3075 2870
3076 venus: video-codec@aa00000 { 2871 venus: video-codec@aa00000 {
3077 compatible = "qcom,sc 2872 compatible = "qcom,sc7180-venus";
3078 reg = <0 0x0aa00000 0 2873 reg = <0 0x0aa00000 0 0xff000>;
3079 interrupts = <GIC_SPI 2874 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
3080 power-domains = <&vid 2875 power-domains = <&videocc VENUS_GDSC>,
3081 <&vid 2876 <&videocc VCODEC0_GDSC>,
3082 <&rpm 2877 <&rpmhpd SC7180_CX>;
3083 power-domain-names = 2878 power-domain-names = "venus", "vcodec0", "cx";
3084 operating-points-v2 = 2879 operating-points-v2 = <&venus_opp_table>;
3085 clocks = <&videocc VI 2880 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
3086 <&videocc VI 2881 <&videocc VIDEO_CC_VENUS_AHB_CLK>,
3087 <&videocc VI 2882 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>,
3088 <&videocc VI 2883 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
3089 <&videocc VI 2884 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>;
3090 clock-names = "core", 2885 clock-names = "core", "iface", "bus",
3091 "vcodec 2886 "vcodec0_core", "vcodec0_bus";
3092 iommus = <&apps_smmu 2887 iommus = <&apps_smmu 0x0c00 0x60>;
3093 memory-region = <&ven 2888 memory-region = <&venus_mem>;
3094 interconnects = <&mms 2889 interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>,
3095 <&gem 2890 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>;
3096 interconnect-names = 2891 interconnect-names = "video-mem", "cpu-cfg";
3097 2892
3098 video-decoder { 2893 video-decoder {
3099 compatible = 2894 compatible = "venus-decoder";
3100 }; 2895 };
3101 2896
3102 video-encoder { 2897 video-encoder {
3103 compatible = 2898 compatible = "venus-encoder";
3104 }; 2899 };
3105 2900
3106 venus_opp_table: opp- !! 2901 venus_opp_table: venus-opp-table {
3107 compatible = 2902 compatible = "operating-points-v2";
3108 2903
3109 opp-150000000 2904 opp-150000000 {
3110 opp-h 2905 opp-hz = /bits/ 64 <150000000>;
3111 requi 2906 required-opps = <&rpmhpd_opp_low_svs>;
3112 }; 2907 };
3113 2908
3114 opp-270000000 2909 opp-270000000 {
3115 opp-h 2910 opp-hz = /bits/ 64 <270000000>;
3116 requi 2911 required-opps = <&rpmhpd_opp_svs>;
3117 }; 2912 };
3118 2913
3119 opp-340000000 2914 opp-340000000 {
3120 opp-h 2915 opp-hz = /bits/ 64 <340000000>;
3121 requi 2916 required-opps = <&rpmhpd_opp_svs_l1>;
3122 }; 2917 };
3123 2918
3124 opp-434000000 2919 opp-434000000 {
3125 opp-h 2920 opp-hz = /bits/ 64 <434000000>;
3126 requi 2921 required-opps = <&rpmhpd_opp_nom>;
3127 }; 2922 };
3128 2923
3129 opp-500000097 2924 opp-500000097 {
3130 opp-h 2925 opp-hz = /bits/ 64 <500000097>;
3131 requi 2926 required-opps = <&rpmhpd_opp_turbo>;
3132 }; 2927 };
3133 }; 2928 };
3134 }; 2929 };
3135 2930
3136 videocc: clock-controller@ab0 2931 videocc: clock-controller@ab00000 {
3137 compatible = "qcom,sc 2932 compatible = "qcom,sc7180-videocc";
3138 reg = <0 0x0ab00000 0 2933 reg = <0 0x0ab00000 0 0x10000>;
3139 clocks = <&rpmhcc RPM 2934 clocks = <&rpmhcc RPMH_CXO_CLK>;
3140 clock-names = "bi_tcx 2935 clock-names = "bi_tcxo";
3141 #clock-cells = <1>; 2936 #clock-cells = <1>;
3142 #reset-cells = <1>; 2937 #reset-cells = <1>;
3143 #power-domain-cells = 2938 #power-domain-cells = <1>;
3144 }; 2939 };
3145 2940
3146 camnoc_virt: interconnect@ac0 2941 camnoc_virt: interconnect@ac00000 {
3147 compatible = "qcom,sc 2942 compatible = "qcom,sc7180-camnoc-virt";
3148 reg = <0 0x0ac00000 0 2943 reg = <0 0x0ac00000 0 0x1000>;
3149 #interconnect-cells = 2944 #interconnect-cells = <2>;
3150 qcom,bcm-voters = <&a 2945 qcom,bcm-voters = <&apps_bcm_voter>;
3151 }; 2946 };
3152 2947
3153 camcc: clock-controller@ad000 2948 camcc: clock-controller@ad00000 {
3154 compatible = "qcom,sc 2949 compatible = "qcom,sc7180-camcc";
3155 reg = <0 0x0ad00000 0 2950 reg = <0 0x0ad00000 0 0x10000>;
3156 clocks = <&rpmhcc RPM 2951 clocks = <&rpmhcc RPMH_CXO_CLK>,
3157 <&gcc GCC_CAME 2952 <&gcc GCC_CAMERA_AHB_CLK>,
3158 <&gcc GCC_CAME 2953 <&gcc GCC_CAMERA_XO_CLK>;
3159 clock-names = "bi_tcx 2954 clock-names = "bi_tcxo", "iface", "xo";
3160 #clock-cells = <1>; 2955 #clock-cells = <1>;
3161 #reset-cells = <1>; 2956 #reset-cells = <1>;
3162 #power-domain-cells = 2957 #power-domain-cells = <1>;
3163 }; 2958 };
3164 2959
3165 mdss: display-subsystem@ae000 !! 2960 mdss: mdss@ae00000 {
3166 compatible = "qcom,sc 2961 compatible = "qcom,sc7180-mdss";
3167 reg = <0 0x0ae00000 0 2962 reg = <0 0x0ae00000 0 0x1000>;
3168 reg-names = "mdss"; 2963 reg-names = "mdss";
3169 2964
3170 power-domains = <&dis 2965 power-domains = <&dispcc MDSS_GDSC>;
3171 2966
3172 clocks = <&gcc GCC_DI 2967 clocks = <&gcc GCC_DISP_AHB_CLK>,
3173 <&dispcc DIS 2968 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3174 <&dispcc DIS 2969 <&dispcc DISP_CC_MDSS_MDP_CLK>;
3175 clock-names = "iface" 2970 clock-names = "iface", "ahb", "core";
3176 2971
>> 2972 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
>> 2973 assigned-clock-rates = <300000000>;
>> 2974
3177 interrupts = <GIC_SPI 2975 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
3178 interrupt-controller; 2976 interrupt-controller;
3179 #interrupt-cells = <1 2977 #interrupt-cells = <1>;
3180 2978
3181 interconnects = <&mms !! 2979 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>;
3182 &mc_ !! 2980 interconnect-names = "mdp0-mem";
3183 <&gem <<
3184 &con <<
3185 interconnect-names = <<
3186 <<
3187 2981
3188 iommus = <&apps_smmu 2982 iommus = <&apps_smmu 0x800 0x2>;
3189 2983
3190 #address-cells = <2>; 2984 #address-cells = <2>;
3191 #size-cells = <2>; 2985 #size-cells = <2>;
3192 ranges; 2986 ranges;
3193 2987
3194 status = "disabled"; 2988 status = "disabled";
3195 2989
3196 mdp: display-controll !! 2990 mdp: mdp@ae01000 {
3197 compatible = 2991 compatible = "qcom,sc7180-dpu";
3198 reg = <0 0x0a 2992 reg = <0 0x0ae01000 0 0x8f000>,
3199 <0 0x0a 2993 <0 0x0aeb0000 0 0x2008>;
3200 reg-names = " 2994 reg-names = "mdp", "vbif";
3201 2995
3202 clocks = <&gc 2996 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
3203 <&di 2997 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3204 <&di 2998 <&dispcc DISP_CC_MDSS_ROT_CLK>,
3205 <&di 2999 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
3206 <&di 3000 <&dispcc DISP_CC_MDSS_MDP_CLK>,
3207 <&di 3001 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3208 clock-names = 3002 clock-names = "bus", "iface", "rot", "lut", "core",
3209 3003 "vsync";
3210 assigned-cloc !! 3004 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
>> 3005 <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
3211 3006 <&dispcc DISP_CC_MDSS_ROT_CLK>,
3212 3007 <&dispcc DISP_CC_MDSS_AHB_CLK>;
3213 assigned-cloc !! 3008 assigned-clock-rates = <300000000>,
>> 3009 <19200000>,
3214 3010 <19200000>,
3215 3011 <19200000>;
3216 operating-poi 3012 operating-points-v2 = <&mdp_opp_table>;
3217 power-domains 3013 power-domains = <&rpmhpd SC7180_CX>;
3218 3014
3219 interrupt-par 3015 interrupt-parent = <&mdss>;
3220 interrupts = 3016 interrupts = <0>;
3221 3017
>> 3018 status = "disabled";
>> 3019
3222 ports { 3020 ports {
3223 #addr 3021 #address-cells = <1>;
3224 #size 3022 #size-cells = <0>;
3225 3023
3226 port@ 3024 port@0 {
3227 3025 reg = <0>;
3228 3026 dpu_intf1_out: endpoint {
3229 !! 3027 remote-endpoint = <&dsi0_in>;
3230 <<
3231 }; <<
3232 <<
3233 port@ <<
3234 <<
3235 <<
3236 <<
3237 3028 };
3238 }; 3029 };
3239 }; 3030 };
3240 3031
3241 mdp_opp_table !! 3032 mdp_opp_table: mdp-opp-table {
3242 compa 3033 compatible = "operating-points-v2";
3243 3034
3244 opp-2 3035 opp-200000000 {
3245 3036 opp-hz = /bits/ 64 <200000000>;
3246 3037 required-opps = <&rpmhpd_opp_low_svs>;
3247 }; 3038 };
3248 3039
3249 opp-3 3040 opp-300000000 {
3250 3041 opp-hz = /bits/ 64 <300000000>;
3251 3042 required-opps = <&rpmhpd_opp_svs>;
3252 }; 3043 };
3253 3044
3254 opp-3 3045 opp-345000000 {
3255 3046 opp-hz = /bits/ 64 <345000000>;
3256 3047 required-opps = <&rpmhpd_opp_svs_l1>;
3257 }; 3048 };
3258 3049
3259 opp-4 3050 opp-460000000 {
3260 3051 opp-hz = /bits/ 64 <460000000>;
3261 3052 required-opps = <&rpmhpd_opp_nom>;
3262 }; 3053 };
3263 }; 3054 };
>> 3055
3264 }; 3056 };
3265 3057
3266 mdss_dsi0: dsi@ae9400 !! 3058 dsi0: dsi@ae94000 {
3267 compatible = !! 3059 compatible = "qcom,mdss-dsi-ctrl";
3268 <<
3269 reg = <0 0x0a 3060 reg = <0 0x0ae94000 0 0x400>;
3270 reg-names = " 3061 reg-names = "dsi_ctrl";
3271 3062
3272 interrupt-par 3063 interrupt-parent = <&mdss>;
3273 interrupts = 3064 interrupts = <4>;
3274 3065
3275 clocks = <&di 3066 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
3276 <&di 3067 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
3277 <&di 3068 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
3278 <&di 3069 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
3279 <&di 3070 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3280 <&gc 3071 <&gcc GCC_DISP_HF_AXI_CLK>;
3281 clock-names = 3072 clock-names = "byte",
3282 3073 "byte_intf",
3283 3074 "pixel",
3284 3075 "core",
3285 3076 "iface",
3286 3077 "bus";
3287 3078
3288 assigned-cloc <<
3289 assigned-cloc <<
3290 <<
3291 operating-poi 3079 operating-points-v2 = <&dsi_opp_table>;
3292 power-domains 3080 power-domains = <&rpmhpd SC7180_CX>;
3293 3081
3294 phys = <&mdss !! 3082 phys = <&dsi_phy>;
>> 3083 phy-names = "dsi";
3295 3084
3296 #address-cell 3085 #address-cells = <1>;
3297 #size-cells = 3086 #size-cells = <0>;
3298 3087
3299 status = "dis 3088 status = "disabled";
3300 3089
3301 ports { 3090 ports {
3302 #addr 3091 #address-cells = <1>;
3303 #size 3092 #size-cells = <0>;
3304 3093
3305 port@ 3094 port@0 {
3306 3095 reg = <0>;
3307 !! 3096 dsi0_in: endpoint {
3308 3097 remote-endpoint = <&dpu_intf1_out>;
3309 3098 };
3310 }; 3099 };
3311 3100
3312 port@ 3101 port@1 {
3313 3102 reg = <1>;
3314 !! 3103 dsi0_out: endpoint {
3315 3104 };
3316 }; 3105 };
3317 }; 3106 };
3318 3107
3319 dsi_opp_table !! 3108 dsi_opp_table: dsi-opp-table {
3320 compa 3109 compatible = "operating-points-v2";
3321 3110
3322 opp-1 3111 opp-187500000 {
3323 3112 opp-hz = /bits/ 64 <187500000>;
3324 3113 required-opps = <&rpmhpd_opp_low_svs>;
3325 }; 3114 };
3326 3115
3327 opp-3 3116 opp-300000000 {
3328 3117 opp-hz = /bits/ 64 <300000000>;
3329 3118 required-opps = <&rpmhpd_opp_svs>;
3330 }; 3119 };
3331 3120
3332 opp-3 3121 opp-358000000 {
3333 3122 opp-hz = /bits/ 64 <358000000>;
3334 3123 required-opps = <&rpmhpd_opp_svs_l1>;
3335 }; 3124 };
3336 }; 3125 };
3337 }; 3126 };
3338 3127
3339 mdss_dsi0_phy: phy@ae !! 3128 dsi_phy: dsi-phy@ae94400 {
3340 compatible = 3129 compatible = "qcom,dsi-phy-10nm";
3341 reg = <0 0x0a 3130 reg = <0 0x0ae94400 0 0x200>,
3342 <0 0x0a 3131 <0 0x0ae94600 0 0x280>,
3343 <0 0x0a 3132 <0 0x0ae94a00 0 0x1e0>;
3344 reg-names = " 3133 reg-names = "dsi_phy",
3345 " 3134 "dsi_phy_lane",
3346 " 3135 "dsi_pll";
3347 3136
3348 #clock-cells 3137 #clock-cells = <1>;
3349 #phy-cells = 3138 #phy-cells = <0>;
3350 3139
3351 clocks = <&di 3140 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3352 <&rp 3141 <&rpmhcc RPMH_CXO_CLK>;
3353 clock-names = 3142 clock-names = "iface", "ref";
3354 3143
3355 status = "dis 3144 status = "disabled";
3356 }; 3145 };
3357 <<
3358 mdss_dp: displayport- <<
3359 compatible = <<
3360 status = "dis <<
3361 <<
3362 reg = <0 0x0a <<
3363 <0 0x0a <<
3364 <0 0x0a <<
3365 <0 0x0a <<
3366 <0 0x0a <<
3367 <<
3368 interrupt-par <<
3369 interrupts = <<
3370 <<
3371 clocks = <&di <<
3372 <&di <<
3373 <&di <<
3374 <&di <<
3375 <&di <<
3376 clock-names = <<
3377 <<
3378 assigned-cloc <<
3379 <<
3380 assigned-cloc <<
3381 <<
3382 phys = <&usb_ <<
3383 phy-names = " <<
3384 <<
3385 operating-poi <<
3386 power-domains <<
3387 <<
3388 #sound-dai-ce <<
3389 <<
3390 ports { <<
3391 #addr <<
3392 #size <<
3393 port@ <<
3394 <<
3395 <<
3396 <<
3397 <<
3398 }; <<
3399 <<
3400 port@ <<
3401 <<
3402 <<
3403 }; <<
3404 }; <<
3405 <<
3406 dp_opp_table: <<
3407 compa <<
3408 <<
3409 opp-1 <<
3410 <<
3411 <<
3412 }; <<
3413 <<
3414 opp-2 <<
3415 <<
3416 <<
3417 }; <<
3418 <<
3419 opp-5 <<
3420 <<
3421 <<
3422 }; <<
3423 <<
3424 opp-8 <<
3425 <<
3426 <<
3427 }; <<
3428 }; <<
3429 }; <<
3430 }; 3146 };
3431 3147
3432 dispcc: clock-controller@af00 3148 dispcc: clock-controller@af00000 {
3433 compatible = "qcom,sc 3149 compatible = "qcom,sc7180-dispcc";
3434 reg = <0 0x0af00000 0 3150 reg = <0 0x0af00000 0 0x200000>;
3435 clocks = <&rpmhcc RPM 3151 clocks = <&rpmhcc RPMH_CXO_CLK>,
3436 <&gcc GCC_DI 3152 <&gcc GCC_DISP_GPLL0_CLK_SRC>,
3437 <&mdss_dsi0_ !! 3153 <&dsi_phy 0>,
3438 <&mdss_dsi0_ !! 3154 <&dsi_phy 1>,
3439 <&usb_1_qmpp !! 3155 <0>,
3440 <&usb_1_qmpp !! 3156 <0>;
3441 clock-names = "bi_tcx 3157 clock-names = "bi_tcxo",
3442 "gcc_di 3158 "gcc_disp_gpll0_clk_src",
3443 "dsi0_p 3159 "dsi0_phy_pll_out_byteclk",
3444 "dsi0_p 3160 "dsi0_phy_pll_out_dsiclk",
3445 "dp_phy 3161 "dp_phy_pll_link_clk",
3446 "dp_phy 3162 "dp_phy_pll_vco_div_clk";
3447 #clock-cells = <1>; 3163 #clock-cells = <1>;
3448 #reset-cells = <1>; 3164 #reset-cells = <1>;
3449 #power-domain-cells = 3165 #power-domain-cells = <1>;
3450 }; 3166 };
3451 3167
3452 pdc: interrupt-controller@b22 3168 pdc: interrupt-controller@b220000 {
3453 compatible = "qcom,sc 3169 compatible = "qcom,sc7180-pdc", "qcom,pdc";
3454 reg = <0 0x0b220000 0 3170 reg = <0 0x0b220000 0 0x30000>;
3455 qcom,pdc-ranges = <0 3171 qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>;
3456 #interrupt-cells = <2 3172 #interrupt-cells = <2>;
3457 interrupt-parent = <& 3173 interrupt-parent = <&intc>;
3458 interrupt-controller; 3174 interrupt-controller;
3459 }; 3175 };
3460 3176
3461 pdc_reset: reset-controller@b 3177 pdc_reset: reset-controller@b2e0000 {
3462 compatible = "qcom,sc 3178 compatible = "qcom,sc7180-pdc-global", "qcom,sdm845-pdc-global";
3463 reg = <0 0x0b2e0000 0 3179 reg = <0 0x0b2e0000 0 0x20000>;
3464 #reset-cells = <1>; 3180 #reset-cells = <1>;
3465 }; 3181 };
3466 3182
3467 tsens0: thermal-sensor@c26300 3183 tsens0: thermal-sensor@c263000 {
3468 compatible = "qcom,sc 3184 compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
3469 reg = <0 0x0c263000 0 3185 reg = <0 0x0c263000 0 0x1ff>, /* TM */
3470 <0 0x0c222000 3186 <0 0x0c222000 0 0x1ff>; /* SROT */
3471 #qcom,sensors = <15>; 3187 #qcom,sensors = <15>;
3472 interrupts = <GIC_SPI 3188 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
3473 <GIC_SPI 3189 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
3474 interrupt-names = "up 3190 interrupt-names = "uplow","critical";
3475 #thermal-sensor-cells 3191 #thermal-sensor-cells = <1>;
3476 }; 3192 };
3477 3193
3478 tsens1: thermal-sensor@c26500 3194 tsens1: thermal-sensor@c265000 {
3479 compatible = "qcom,sc 3195 compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
3480 reg = <0 0x0c265000 0 3196 reg = <0 0x0c265000 0 0x1ff>, /* TM */
3481 <0 0x0c223000 3197 <0 0x0c223000 0 0x1ff>; /* SROT */
3482 #qcom,sensors = <10>; 3198 #qcom,sensors = <10>;
3483 interrupts = <GIC_SPI 3199 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
3484 <GIC_SPI 3200 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
3485 interrupt-names = "up 3201 interrupt-names = "uplow","critical";
3486 #thermal-sensor-cells 3202 #thermal-sensor-cells = <1>;
3487 }; 3203 };
3488 3204
3489 aoss_reset: reset-controller@ 3205 aoss_reset: reset-controller@c2a0000 {
3490 compatible = "qcom,sc 3206 compatible = "qcom,sc7180-aoss-cc", "qcom,sdm845-aoss-cc";
3491 reg = <0 0x0c2a0000 0 3207 reg = <0 0x0c2a0000 0 0x31000>;
3492 #reset-cells = <1>; 3208 #reset-cells = <1>;
3493 }; 3209 };
3494 3210
3495 aoss_qmp: power-management@c3 !! 3211 aoss_qmp: qmp@c300000 {
3496 compatible = "qcom,sc !! 3212 compatible = "qcom,sc7180-aoss-qmp";
3497 reg = <0 0x0c300000 0 !! 3213 reg = <0 0x0c300000 0 0x100000>;
3498 interrupts = <GIC_SPI 3214 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
3499 mboxes = <&apss_share 3215 mboxes = <&apss_shared 0>;
3500 3216
3501 #clock-cells = <0>; 3217 #clock-cells = <0>;
3502 }; !! 3218 #power-domain-cells = <1>;
3503 <<
3504 sram@c3f0000 { <<
3505 compatible = "qcom,rp <<
3506 reg = <0 0x0c3f0000 0 <<
3507 }; 3219 };
3508 3220
3509 spmi_bus: spmi@c440000 { 3221 spmi_bus: spmi@c440000 {
3510 compatible = "qcom,sp 3222 compatible = "qcom,spmi-pmic-arb";
3511 reg = <0 0x0c440000 0 3223 reg = <0 0x0c440000 0 0x1100>,
3512 <0 0x0c600000 0 3224 <0 0x0c600000 0 0x2000000>,
3513 <0 0x0e600000 0 3225 <0 0x0e600000 0 0x100000>,
3514 <0 0x0e700000 0 3226 <0 0x0e700000 0 0xa0000>,
3515 <0 0x0c40a000 0 3227 <0 0x0c40a000 0 0x26000>;
3516 reg-names = "core", " 3228 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3517 interrupt-names = "pe 3229 interrupt-names = "periph_irq";
3518 interrupts-extended = 3230 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3519 qcom,ee = <0>; 3231 qcom,ee = <0>;
3520 qcom,channel = <0>; 3232 qcom,channel = <0>;
3521 #address-cells = <2>; <<
3522 #size-cells = <0>; <<
3523 interrupt-controller; <<
3524 #interrupt-cells = <4 <<
3525 }; <<
3526 <<
3527 sram@146aa000 { <<
3528 compatible = "qcom,sc <<
3529 reg = <0 0x146aa000 0 <<
3530 <<
3531 #address-cells = <1>; 3233 #address-cells = <1>;
3532 #size-cells = <1>; 3234 #size-cells = <1>;
3533 !! 3235 interrupt-controller;
3534 ranges = <0 0 0x146aa !! 3236 #interrupt-cells = <4>;
3535 !! 3237 cell-index = <0>;
3536 pil-reloc@94c { <<
3537 compatible = <<
3538 reg = <0x94c <<
3539 }; <<
3540 }; 3238 };
3541 3239
3542 apps_smmu: iommu@15000000 { 3240 apps_smmu: iommu@15000000 {
3543 compatible = "qcom,sc 3241 compatible = "qcom,sc7180-smmu-500", "arm,mmu-500";
3544 reg = <0 0x15000000 0 3242 reg = <0 0x15000000 0 0x100000>;
3545 #iommu-cells = <2>; 3243 #iommu-cells = <2>;
3546 #global-interrupts = 3244 #global-interrupts = <1>;
3547 interrupts = <GIC_SPI 3245 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
3548 <GIC_SPI 3246 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
3549 <GIC_SPI 3247 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
3550 <GIC_SPI 3248 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
3551 <GIC_SPI 3249 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
3552 <GIC_SPI 3250 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
3553 <GIC_SPI 3251 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
3554 <GIC_SPI 3252 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
3555 <GIC_SPI 3253 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
3556 <GIC_SPI 3254 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
3557 <GIC_SPI 3255 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
3558 <GIC_SPI 3256 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
3559 <GIC_SPI 3257 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
3560 <GIC_SPI 3258 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
3561 <GIC_SPI 3259 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
3562 <GIC_SPI 3260 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
3563 <GIC_SPI 3261 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
3564 <GIC_SPI 3262 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
3565 <GIC_SPI 3263 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
3566 <GIC_SPI 3264 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
3567 <GIC_SPI 3265 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
3568 <GIC_SPI 3266 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
3569 <GIC_SPI 3267 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
3570 <GIC_SPI 3268 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
3571 <GIC_SPI 3269 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
3572 <GIC_SPI 3270 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
3573 <GIC_SPI 3271 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
3574 <GIC_SPI 3272 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
3575 <GIC_SPI 3273 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
3576 <GIC_SPI 3274 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
3577 <GIC_SPI 3275 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
3578 <GIC_SPI 3276 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
3579 <GIC_SPI 3277 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
3580 <GIC_SPI 3278 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
3581 <GIC_SPI 3279 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
3582 <GIC_SPI 3280 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
3583 <GIC_SPI 3281 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
3584 <GIC_SPI 3282 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
3585 <GIC_SPI 3283 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
3586 <GIC_SPI 3284 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
3587 <GIC_SPI 3285 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
3588 <GIC_SPI 3286 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
3589 <GIC_SPI 3287 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
3590 <GIC_SPI 3288 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
3591 <GIC_SPI 3289 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
3592 <GIC_SPI 3290 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
3593 <GIC_SPI 3291 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
3594 <GIC_SPI 3292 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
3595 <GIC_SPI 3293 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
3596 <GIC_SPI 3294 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
3597 <GIC_SPI 3295 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
3598 <GIC_SPI 3296 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
3599 <GIC_SPI 3297 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
3600 <GIC_SPI 3298 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
3601 <GIC_SPI 3299 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
3602 <GIC_SPI 3300 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
3603 <GIC_SPI 3301 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
3604 <GIC_SPI 3302 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
3605 <GIC_SPI 3303 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
3606 <GIC_SPI 3304 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
3607 <GIC_SPI 3305 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
3608 <GIC_SPI 3306 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
3609 <GIC_SPI 3307 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
3610 <GIC_SPI 3308 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
3611 <GIC_SPI 3309 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
3612 <GIC_SPI 3310 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
3613 <GIC_SPI 3311 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
3614 <GIC_SPI 3312 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
3615 <GIC_SPI 3313 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
3616 <GIC_SPI 3314 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
3617 <GIC_SPI 3315 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
3618 <GIC_SPI 3316 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
3619 <GIC_SPI 3317 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
3620 <GIC_SPI 3318 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
3621 <GIC_SPI 3319 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
3622 <GIC_SPI 3320 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
3623 <GIC_SPI 3321 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
3624 <GIC_SPI 3322 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
3625 <GIC_SPI 3323 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
3626 <GIC_SPI 3324 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
3627 <GIC_SPI 3325 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
3628 }; 3326 };
3629 3327
3630 intc: interrupt-controller@17 3328 intc: interrupt-controller@17a00000 {
3631 compatible = "arm,gic 3329 compatible = "arm,gic-v3";
3632 #address-cells = <2>; 3330 #address-cells = <2>;
3633 #size-cells = <2>; 3331 #size-cells = <2>;
3634 ranges; 3332 ranges;
3635 #interrupt-cells = <3 3333 #interrupt-cells = <3>;
3636 interrupt-controller; 3334 interrupt-controller;
3637 reg = <0 0x17a00000 0 3335 reg = <0 0x17a00000 0 0x10000>, /* GICD */
3638 <0 0x17a60000 0 3336 <0 0x17a60000 0 0x100000>; /* GICR * 8 */
3639 interrupts = <GIC_PPI 3337 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3640 3338
3641 msi-controller@17a400 3339 msi-controller@17a40000 {
3642 compatible = 3340 compatible = "arm,gic-v3-its";
3643 msi-controlle 3341 msi-controller;
3644 #msi-cells = 3342 #msi-cells = <1>;
3645 reg = <0 0x17 3343 reg = <0 0x17a40000 0 0x20000>;
3646 status = "dis 3344 status = "disabled";
3647 }; 3345 };
3648 }; 3346 };
3649 3347
3650 apss_shared: mailbox@17c00000 3348 apss_shared: mailbox@17c00000 {
3651 compatible = "qcom,sc !! 3349 compatible = "qcom,sc7180-apss-shared";
3652 "qcom,sd <<
3653 reg = <0 0x17c00000 0 3350 reg = <0 0x17c00000 0 0x10000>;
3654 #mbox-cells = <1>; 3351 #mbox-cells = <1>;
3655 }; 3352 };
3656 3353
3657 watchdog@17c10000 { 3354 watchdog@17c10000 {
3658 compatible = "qcom,ap 3355 compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt";
3659 reg = <0 0x17c10000 0 3356 reg = <0 0x17c10000 0 0x1000>;
3660 clocks = <&sleep_clk> 3357 clocks = <&sleep_clk>;
3661 interrupts = <GIC_SPI <<
3662 }; 3358 };
3663 3359
3664 timer@17c20000 { !! 3360 timer@17c20000{
3665 #address-cells = <1>; !! 3361 #address-cells = <2>;
3666 #size-cells = <1>; !! 3362 #size-cells = <2>;
3667 ranges = <0 0 0 0x200 !! 3363 ranges;
3668 compatible = "arm,arm 3364 compatible = "arm,armv7-timer-mem";
3669 reg = <0 0x17c20000 0 3365 reg = <0 0x17c20000 0 0x1000>;
3670 3366
3671 frame@17c21000 { 3367 frame@17c21000 {
3672 frame-number 3368 frame-number = <0>;
3673 interrupts = 3369 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
3674 3370 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
3675 reg = <0x17c2 !! 3371 reg = <0 0x17c21000 0 0x1000>,
3676 <0x17c2 !! 3372 <0 0x17c22000 0 0x1000>;
3677 }; 3373 };
3678 3374
3679 frame@17c23000 { 3375 frame@17c23000 {
3680 frame-number 3376 frame-number = <1>;
3681 interrupts = 3377 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
3682 reg = <0x17c2 !! 3378 reg = <0 0x17c23000 0 0x1000>;
3683 status = "dis 3379 status = "disabled";
3684 }; 3380 };
3685 3381
3686 frame@17c25000 { 3382 frame@17c25000 {
3687 frame-number 3383 frame-number = <2>;
3688 interrupts = 3384 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
3689 reg = <0x17c2 !! 3385 reg = <0 0x17c25000 0 0x1000>;
3690 status = "dis 3386 status = "disabled";
3691 }; 3387 };
3692 3388
3693 frame@17c27000 { 3389 frame@17c27000 {
3694 frame-number 3390 frame-number = <3>;
3695 interrupts = 3391 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3696 reg = <0x17c2 !! 3392 reg = <0 0x17c27000 0 0x1000>;
3697 status = "dis 3393 status = "disabled";
3698 }; 3394 };
3699 3395
3700 frame@17c29000 { 3396 frame@17c29000 {
3701 frame-number 3397 frame-number = <4>;
3702 interrupts = 3398 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3703 reg = <0x17c2 !! 3399 reg = <0 0x17c29000 0 0x1000>;
3704 status = "dis 3400 status = "disabled";
3705 }; 3401 };
3706 3402
3707 frame@17c2b000 { 3403 frame@17c2b000 {
3708 frame-number 3404 frame-number = <5>;
3709 interrupts = 3405 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3710 reg = <0x17c2 !! 3406 reg = <0 0x17c2b000 0 0x1000>;
3711 status = "dis 3407 status = "disabled";
3712 }; 3408 };
3713 3409
3714 frame@17c2d000 { 3410 frame@17c2d000 {
3715 frame-number 3411 frame-number = <6>;
3716 interrupts = 3412 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
3717 reg = <0x17c2 !! 3413 reg = <0 0x17c2d000 0 0x1000>;
3718 status = "dis 3414 status = "disabled";
3719 }; 3415 };
3720 }; 3416 };
3721 3417
3722 apps_rsc: rsc@18200000 { 3418 apps_rsc: rsc@18200000 {
3723 compatible = "qcom,rp 3419 compatible = "qcom,rpmh-rsc";
3724 reg = <0 0x18200000 0 3420 reg = <0 0x18200000 0 0x10000>,
3725 <0 0x18210000 0 3421 <0 0x18210000 0 0x10000>,
3726 <0 0x18220000 0 3422 <0 0x18220000 0 0x10000>;
3727 reg-names = "drv-0", 3423 reg-names = "drv-0", "drv-1", "drv-2";
3728 interrupts = <GIC_SPI 3424 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
3729 <GIC_SPI 3425 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
3730 <GIC_SPI 3426 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
3731 qcom,tcs-offset = <0x 3427 qcom,tcs-offset = <0xd00>;
3732 qcom,drv-id = <2>; 3428 qcom,drv-id = <2>;
3733 qcom,tcs-config = <AC 3429 qcom,tcs-config = <ACTIVE_TCS 2>,
3734 <SL 3430 <SLEEP_TCS 3>,
3735 <WA 3431 <WAKE_TCS 3>,
3736 <CO 3432 <CONTROL_TCS 1>;
3737 power-domains = <&CLU <<
3738 3433
3739 rpmhcc: clock-control 3434 rpmhcc: clock-controller {
3740 compatible = 3435 compatible = "qcom,sc7180-rpmh-clk";
3741 clocks = <&xo 3436 clocks = <&xo_board>;
3742 clock-names = 3437 clock-names = "xo";
3743 #clock-cells 3438 #clock-cells = <1>;
3744 }; 3439 };
3745 3440
3746 rpmhpd: power-control 3441 rpmhpd: power-controller {
3747 compatible = 3442 compatible = "qcom,sc7180-rpmhpd";
3748 #power-domain 3443 #power-domain-cells = <1>;
3749 operating-poi 3444 operating-points-v2 = <&rpmhpd_opp_table>;
3750 3445
3751 rpmhpd_opp_ta 3446 rpmhpd_opp_table: opp-table {
3752 compa 3447 compatible = "operating-points-v2";
3753 3448
3754 rpmhp 3449 rpmhpd_opp_ret: opp1 {
3755 3450 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3756 }; 3451 };
3757 3452
3758 rpmhp 3453 rpmhpd_opp_min_svs: opp2 {
3759 3454 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3760 }; 3455 };
3761 3456
3762 rpmhp 3457 rpmhpd_opp_low_svs: opp3 {
3763 3458 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3764 }; 3459 };
3765 3460
3766 rpmhp 3461 rpmhpd_opp_svs: opp4 {
3767 3462 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3768 }; 3463 };
3769 3464
3770 rpmhp 3465 rpmhpd_opp_svs_l1: opp5 {
3771 3466 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3772 }; 3467 };
3773 3468
3774 rpmhp 3469 rpmhpd_opp_svs_l2: opp6 {
3775 3470 opp-level = <224>;
3776 }; 3471 };
3777 3472
3778 rpmhp 3473 rpmhpd_opp_nom: opp7 {
3779 3474 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3780 }; 3475 };
3781 3476
3782 rpmhp 3477 rpmhpd_opp_nom_l1: opp8 {
3783 3478 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3784 }; 3479 };
3785 3480
3786 rpmhp 3481 rpmhpd_opp_nom_l2: opp9 {
3787 3482 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3788 }; 3483 };
3789 3484
3790 rpmhp 3485 rpmhpd_opp_turbo: opp10 {
3791 3486 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3792 }; 3487 };
3793 3488
3794 rpmhp 3489 rpmhpd_opp_turbo_l1: opp11 {
3795 3490 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3796 }; 3491 };
3797 }; 3492 };
3798 }; 3493 };
3799 3494
3800 apps_bcm_voter: bcm-v !! 3495 apps_bcm_voter: bcm_voter {
3801 compatible = 3496 compatible = "qcom,bcm-voter";
3802 }; 3497 };
3803 }; 3498 };
3804 3499
3805 osm_l3: interconnect@18321000 3500 osm_l3: interconnect@18321000 {
3806 compatible = "qcom,sc !! 3501 compatible = "qcom,sc7180-osm-l3";
3807 reg = <0 0x18321000 0 3502 reg = <0 0x18321000 0 0x1400>;
3808 3503
3809 clocks = <&rpmhcc RPM 3504 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3810 clock-names = "xo", " 3505 clock-names = "xo", "alternate";
3811 3506
3812 #interconnect-cells = 3507 #interconnect-cells = <1>;
3813 }; 3508 };
3814 3509
3815 cpufreq_hw: cpufreq@18323000 3510 cpufreq_hw: cpufreq@18323000 {
3816 compatible = "qcom,sc !! 3511 compatible = "qcom,cpufreq-hw";
3817 reg = <0 0x18323000 0 3512 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>;
3818 reg-names = "freq-dom 3513 reg-names = "freq-domain0", "freq-domain1";
3819 3514
3820 clocks = <&rpmhcc RPM 3515 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3821 clock-names = "xo", " 3516 clock-names = "xo", "alternate";
3822 3517
3823 #freq-domain-cells = 3518 #freq-domain-cells = <1>;
3824 #clock-cells = <1>; <<
3825 }; 3519 };
3826 3520
3827 wifi: wifi@18800000 { 3521 wifi: wifi@18800000 {
3828 compatible = "qcom,wc 3522 compatible = "qcom,wcn3990-wifi";
3829 reg = <0 0x18800000 0 3523 reg = <0 0x18800000 0 0x800000>;
3830 reg-names = "membase" 3524 reg-names = "membase";
3831 iommus = <&apps_smmu 3525 iommus = <&apps_smmu 0xc0 0x1>;
3832 interrupts = 3526 interrupts =
3833 <GIC_SPI 414 3527 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH /* CE0 */ >,
3834 <GIC_SPI 415 3528 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH /* CE1 */ >,
3835 <GIC_SPI 416 3529 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH /* CE2 */ >,
3836 <GIC_SPI 417 3530 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH /* CE3 */ >,
3837 <GIC_SPI 418 3531 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH /* CE4 */ >,
3838 <GIC_SPI 419 3532 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH /* CE5 */ >,
3839 <GIC_SPI 420 3533 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH /* CE6 */ >,
3840 <GIC_SPI 421 3534 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH /* CE7 */ >,
3841 <GIC_SPI 422 3535 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH /* CE8 */ >,
3842 <GIC_SPI 423 3536 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH /* CE9 */ >,
3843 <GIC_SPI 424 3537 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH /* CE10 */>,
3844 <GIC_SPI 425 3538 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH /* CE11 */>;
3845 memory-region = <&wla 3539 memory-region = <&wlan_mem>;
3846 qcom,msa-fixed-perm; 3540 qcom,msa-fixed-perm;
3847 status = "disabled"; 3541 status = "disabled";
3848 }; 3542 };
3849 3543
3850 remoteproc_adsp: remoteproc@6 <<
3851 compatible = "qcom,sc <<
3852 reg = <0 0x62400000 0 <<
3853 <<
3854 interrupts-extended = <<
3855 <<
3856 <<
3857 <<
3858 <<
3859 interrupt-names = "wd <<
3860 "fa <<
3861 "re <<
3862 "ha <<
3863 "st <<
3864 <<
3865 clocks = <&rpmhcc RPM <<
3866 clock-names = "xo"; <<
3867 <<
3868 power-domains = <&rpm <<
3869 <&rpm <<
3870 power-domain-names = <<
3871 <<
3872 qcom,qmp = <&aoss_qmp <<
3873 qcom,smem-states = <& <<
3874 qcom,smem-state-names <<
3875 <<
3876 status = "disabled"; <<
3877 <<
3878 glink-edge { <<
3879 interrupts = <<
3880 label = "lpas <<
3881 qcom,remote-p <<
3882 mboxes = <&ap <<
3883 <<
3884 apr { <<
3885 compa <<
3886 qcom, <<
3887 qcom, <<
3888 #addr <<
3889 #size <<
3890 <<
3891 servi <<
3892 <<
3893 <<
3894 <<
3895 }; <<
3896 <<
3897 q6afe <<
3898 <<
3899 <<
3900 <<
3901 <<
3902 <<
3903 <<
3904 <<
3905 <<
3906 <<
3907 <<
3908 <<
3909 <<
3910 <<
3911 <<
3912 <<
3913 }; <<
3914 <<
3915 q6asm <<
3916 <<
3917 <<
3918 <<
3919 <<
3920 <<
3921 <<
3922 <<
3923 <<
3924 <<
3925 <<
3926 <<
3927 }; <<
3928 <<
3929 q6adm <<
3930 <<
3931 <<
3932 <<
3933 <<
3934 <<
3935 <<
3936 <<
3937 <<
3938 }; <<
3939 }; <<
3940 <<
3941 fastrpc { <<
3942 compa <<
3943 qcom, <<
3944 label <<
3945 #addr <<
3946 #size <<
3947 <<
3948 compu <<
3949 <<
3950 <<
3951 <<
3952 }; <<
3953 <<
3954 compu <<
3955 <<
3956 <<
3957 <<
3958 }; <<
3959 <<
3960 compu <<
3961 <<
3962 <<
3963 <<
3964 <<
3965 }; <<
3966 }; <<
3967 }; <<
3968 }; <<
3969 <<
3970 lpasscc: clock-controller@62d 3544 lpasscc: clock-controller@62d00000 {
3971 compatible = "qcom,sc 3545 compatible = "qcom,sc7180-lpasscorecc";
3972 reg = <0 0x62d00000 0 3546 reg = <0 0x62d00000 0 0x50000>,
3973 <0 0x62780000 0 3547 <0 0x62780000 0 0x30000>;
3974 reg-names = "lpass_co 3548 reg-names = "lpass_core_cc", "lpass_audio_cc";
3975 clocks = <&gcc GCC_LP 3549 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>,
3976 <&rpmhcc RPM 3550 <&rpmhcc RPMH_CXO_CLK>;
3977 clock-names = "iface" 3551 clock-names = "iface", "bi_tcxo";
3978 power-domains = <&lpa 3552 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>;
3979 #clock-cells = <1>; 3553 #clock-cells = <1>;
3980 #power-domain-cells = 3554 #power-domain-cells = <1>;
3981 <<
3982 status = "reserved"; <<
3983 }; 3555 };
3984 3556
3985 lpass_cpu: lpass@62d87000 { !! 3557 lpass_cpu: lpass@62f00000 {
3986 compatible = "qcom,sc 3558 compatible = "qcom,sc7180-lpass-cpu";
3987 3559
3988 reg = <0 0x62d87000 0 !! 3560 reg = <0 0x62f00000 0 0x29000>;
3989 reg-names = "lpass-hd !! 3561 reg-names = "lpass-lpaif";
3990 3562
3991 iommus = <&apps_smmu !! 3563 iommus = <&apps_smmu 0x1020 0>;
3992 <&apps_smmu 0 <<
3993 <&apps_smmu 0 <<
3994 3564
3995 power-domains = <&lpa 3565 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>;
3996 required-opps = <&rpm <<
3997 <<
3998 status = "disabled"; <<
3999 3566
4000 clocks = <&gcc GCC_LP 3567 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>,
4001 <&lpasscc LP 3568 <&lpasscc LPASS_AUDIO_CORE_CORE_CLK>,
4002 <&lpasscc LP 3569 <&lpasscc LPASS_AUDIO_CORE_EXT_MCLK0_CLK>,
4003 <&lpasscc LP 3570 <&lpasscc LPASS_AUDIO_CORE_SYSNOC_MPORT_CORE_CLK>,
4004 <&lpasscc LP 3571 <&lpasscc LPASS_AUDIO_CORE_LPAIF_PRI_IBIT_CLK>,
4005 <&lpasscc LP 3572 <&lpasscc LPASS_AUDIO_CORE_LPAIF_SEC_IBIT_CLK>;
4006 3573
4007 clock-names = "pcnoc- 3574 clock-names = "pcnoc-sway-clk", "audio-core",
4008 "mclk 3575 "mclk0", "pcnoc-mport-clk",
4009 "mi2s 3576 "mi2s-bit-clk0", "mi2s-bit-clk1";
4010 3577
4011 3578
4012 #sound-dai-cells = <1 3579 #sound-dai-cells = <1>;
4013 #address-cells = <1>; 3580 #address-cells = <1>;
4014 #size-cells = <0>; 3581 #size-cells = <0>;
4015 3582
4016 interrupts = <GIC_SPI !! 3583 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
4017 <GIC_ !! 3584 interrupt-names = "lpass-irq-lpaif";
4018 interrupt-names = "lp <<
4019 }; 3585 };
4020 3586
4021 lpass_hm: clock-controller@63 3587 lpass_hm: clock-controller@63000000 {
4022 compatible = "qcom,sc 3588 compatible = "qcom,sc7180-lpasshm";
4023 reg = <0 0x63000000 0 3589 reg = <0 0x63000000 0 0x28>;
4024 clocks = <&gcc GCC_LP 3590 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>,
4025 <&rpmhcc RPM 3591 <&rpmhcc RPMH_CXO_CLK>;
4026 clock-names = "iface" 3592 clock-names = "iface", "bi_tcxo";
4027 power-domains = <&rpm <<
4028 <<
4029 #clock-cells = <1>; 3593 #clock-cells = <1>;
4030 #power-domain-cells = 3594 #power-domain-cells = <1>;
4031 <<
4032 status = "reserved"; <<
4033 }; 3595 };
4034 }; 3596 };
4035 3597
4036 thermal-zones { 3598 thermal-zones {
4037 cpu0_thermal: cpu0-thermal { !! 3599 cpu0-thermal {
4038 polling-delay-passive 3600 polling-delay-passive = <250>;
>> 3601 polling-delay = <0>;
4039 3602
4040 thermal-sensors = <&t 3603 thermal-sensors = <&tsens0 1>;
4041 sustainable-power = < !! 3604 sustainable-power = <768>;
4042 3605
4043 trips { 3606 trips {
4044 cpu0_alert0: 3607 cpu0_alert0: trip-point0 {
4045 tempe 3608 temperature = <90000>;
4046 hyste 3609 hysteresis = <2000>;
4047 type 3610 type = "passive";
4048 }; 3611 };
4049 3612
4050 cpu0_alert1: 3613 cpu0_alert1: trip-point1 {
4051 tempe 3614 temperature = <95000>;
4052 hyste 3615 hysteresis = <2000>;
4053 type 3616 type = "passive";
4054 }; 3617 };
4055 3618
4056 cpu0_crit: cp !! 3619 cpu0_crit: cpu_crit {
4057 tempe 3620 temperature = <110000>;
4058 hyste 3621 hysteresis = <1000>;
4059 type 3622 type = "critical";
4060 }; 3623 };
4061 }; 3624 };
4062 3625
4063 cooling-maps { 3626 cooling-maps {
4064 map0 { 3627 map0 {
4065 trip 3628 trip = <&cpu0_alert0>;
4066 cooli 3629 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4067 3630 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4068 3631 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4069 3632 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4070 3633 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4071 3634 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4072 }; 3635 };
4073 map1 { 3636 map1 {
4074 trip 3637 trip = <&cpu0_alert1>;
4075 cooli 3638 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4076 3639 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4077 3640 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4078 3641 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4079 3642 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4080 3643 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4081 }; 3644 };
4082 }; 3645 };
4083 }; 3646 };
4084 3647
4085 cpu1_thermal: cpu1-thermal { !! 3648 cpu1-thermal {
4086 polling-delay-passive 3649 polling-delay-passive = <250>;
>> 3650 polling-delay = <0>;
4087 3651
4088 thermal-sensors = <&t 3652 thermal-sensors = <&tsens0 2>;
4089 sustainable-power = < !! 3653 sustainable-power = <768>;
4090 3654
4091 trips { 3655 trips {
4092 cpu1_alert0: 3656 cpu1_alert0: trip-point0 {
4093 tempe 3657 temperature = <90000>;
4094 hyste 3658 hysteresis = <2000>;
4095 type 3659 type = "passive";
4096 }; 3660 };
4097 3661
4098 cpu1_alert1: 3662 cpu1_alert1: trip-point1 {
4099 tempe 3663 temperature = <95000>;
4100 hyste 3664 hysteresis = <2000>;
4101 type 3665 type = "passive";
4102 }; 3666 };
4103 3667
4104 cpu1_crit: cp !! 3668 cpu1_crit: cpu_crit {
4105 tempe 3669 temperature = <110000>;
4106 hyste 3670 hysteresis = <1000>;
4107 type 3671 type = "critical";
4108 }; 3672 };
4109 }; 3673 };
4110 3674
4111 cooling-maps { 3675 cooling-maps {
4112 map0 { 3676 map0 {
4113 trip 3677 trip = <&cpu1_alert0>;
4114 cooli 3678 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4115 3679 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4116 3680 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4117 3681 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4118 3682 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4119 3683 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4120 }; 3684 };
4121 map1 { 3685 map1 {
4122 trip 3686 trip = <&cpu1_alert1>;
4123 cooli 3687 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4124 3688 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4125 3689 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4126 3690 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4127 3691 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4128 3692 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4129 }; 3693 };
4130 }; 3694 };
4131 }; 3695 };
4132 3696
4133 cpu2_thermal: cpu2-thermal { !! 3697 cpu2-thermal {
4134 polling-delay-passive 3698 polling-delay-passive = <250>;
>> 3699 polling-delay = <0>;
4135 3700
4136 thermal-sensors = <&t 3701 thermal-sensors = <&tsens0 3>;
4137 sustainable-power = < !! 3702 sustainable-power = <768>;
4138 3703
4139 trips { 3704 trips {
4140 cpu2_alert0: 3705 cpu2_alert0: trip-point0 {
4141 tempe 3706 temperature = <90000>;
4142 hyste 3707 hysteresis = <2000>;
4143 type 3708 type = "passive";
4144 }; 3709 };
4145 3710
4146 cpu2_alert1: 3711 cpu2_alert1: trip-point1 {
4147 tempe 3712 temperature = <95000>;
4148 hyste 3713 hysteresis = <2000>;
4149 type 3714 type = "passive";
4150 }; 3715 };
4151 3716
4152 cpu2_crit: cp !! 3717 cpu2_crit: cpu_crit {
4153 tempe 3718 temperature = <110000>;
4154 hyste 3719 hysteresis = <1000>;
4155 type 3720 type = "critical";
4156 }; 3721 };
4157 }; 3722 };
4158 3723
4159 cooling-maps { 3724 cooling-maps {
4160 map0 { 3725 map0 {
4161 trip 3726 trip = <&cpu2_alert0>;
4162 cooli 3727 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4163 3728 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4164 3729 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4165 3730 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4166 3731 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4167 3732 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4168 }; 3733 };
4169 map1 { 3734 map1 {
4170 trip 3735 trip = <&cpu2_alert1>;
4171 cooli 3736 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4172 3737 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4173 3738 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4174 3739 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4175 3740 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4176 3741 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4177 }; 3742 };
4178 }; 3743 };
4179 }; 3744 };
4180 3745
4181 cpu3_thermal: cpu3-thermal { !! 3746 cpu3-thermal {
4182 polling-delay-passive 3747 polling-delay-passive = <250>;
>> 3748 polling-delay = <0>;
4183 3749
4184 thermal-sensors = <&t 3750 thermal-sensors = <&tsens0 4>;
4185 sustainable-power = < !! 3751 sustainable-power = <768>;
4186 3752
4187 trips { 3753 trips {
4188 cpu3_alert0: 3754 cpu3_alert0: trip-point0 {
4189 tempe 3755 temperature = <90000>;
4190 hyste 3756 hysteresis = <2000>;
4191 type 3757 type = "passive";
4192 }; 3758 };
4193 3759
4194 cpu3_alert1: 3760 cpu3_alert1: trip-point1 {
4195 tempe 3761 temperature = <95000>;
4196 hyste 3762 hysteresis = <2000>;
4197 type 3763 type = "passive";
4198 }; 3764 };
4199 3765
4200 cpu3_crit: cp !! 3766 cpu3_crit: cpu_crit {
4201 tempe 3767 temperature = <110000>;
4202 hyste 3768 hysteresis = <1000>;
4203 type 3769 type = "critical";
4204 }; 3770 };
4205 }; 3771 };
4206 3772
4207 cooling-maps { 3773 cooling-maps {
4208 map0 { 3774 map0 {
4209 trip 3775 trip = <&cpu3_alert0>;
4210 cooli 3776 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4211 3777 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4212 3778 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4213 3779 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4214 3780 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4215 3781 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4216 }; 3782 };
4217 map1 { 3783 map1 {
4218 trip 3784 trip = <&cpu3_alert1>;
4219 cooli 3785 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4220 3786 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4221 3787 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4222 3788 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4223 3789 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4224 3790 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4225 }; 3791 };
4226 }; 3792 };
4227 }; 3793 };
4228 3794
4229 cpu4_thermal: cpu4-thermal { !! 3795 cpu4-thermal {
4230 polling-delay-passive 3796 polling-delay-passive = <250>;
>> 3797 polling-delay = <0>;
4231 3798
4232 thermal-sensors = <&t 3799 thermal-sensors = <&tsens0 5>;
4233 sustainable-power = < !! 3800 sustainable-power = <768>;
4234 3801
4235 trips { 3802 trips {
4236 cpu4_alert0: 3803 cpu4_alert0: trip-point0 {
4237 tempe 3804 temperature = <90000>;
4238 hyste 3805 hysteresis = <2000>;
4239 type 3806 type = "passive";
4240 }; 3807 };
4241 3808
4242 cpu4_alert1: 3809 cpu4_alert1: trip-point1 {
4243 tempe 3810 temperature = <95000>;
4244 hyste 3811 hysteresis = <2000>;
4245 type 3812 type = "passive";
4246 }; 3813 };
4247 3814
4248 cpu4_crit: cp !! 3815 cpu4_crit: cpu_crit {
4249 tempe 3816 temperature = <110000>;
4250 hyste 3817 hysteresis = <1000>;
4251 type 3818 type = "critical";
4252 }; 3819 };
4253 }; 3820 };
4254 3821
4255 cooling-maps { 3822 cooling-maps {
4256 map0 { 3823 map0 {
4257 trip 3824 trip = <&cpu4_alert0>;
4258 cooli 3825 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4259 3826 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4260 3827 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4261 3828 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4262 3829 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4263 3830 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4264 }; 3831 };
4265 map1 { 3832 map1 {
4266 trip 3833 trip = <&cpu4_alert1>;
4267 cooli 3834 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4268 3835 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4269 3836 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4270 3837 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4271 3838 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4272 3839 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4273 }; 3840 };
4274 }; 3841 };
4275 }; 3842 };
4276 3843
4277 cpu5_thermal: cpu5-thermal { !! 3844 cpu5-thermal {
4278 polling-delay-passive 3845 polling-delay-passive = <250>;
>> 3846 polling-delay = <0>;
4279 3847
4280 thermal-sensors = <&t 3848 thermal-sensors = <&tsens0 6>;
4281 sustainable-power = < !! 3849 sustainable-power = <768>;
4282 3850
4283 trips { 3851 trips {
4284 cpu5_alert0: 3852 cpu5_alert0: trip-point0 {
4285 tempe 3853 temperature = <90000>;
4286 hyste 3854 hysteresis = <2000>;
4287 type 3855 type = "passive";
4288 }; 3856 };
4289 3857
4290 cpu5_alert1: 3858 cpu5_alert1: trip-point1 {
4291 tempe 3859 temperature = <95000>;
4292 hyste 3860 hysteresis = <2000>;
4293 type 3861 type = "passive";
4294 }; 3862 };
4295 3863
4296 cpu5_crit: cp !! 3864 cpu5_crit: cpu_crit {
4297 tempe 3865 temperature = <110000>;
4298 hyste 3866 hysteresis = <1000>;
4299 type 3867 type = "critical";
4300 }; 3868 };
4301 }; 3869 };
4302 3870
4303 cooling-maps { 3871 cooling-maps {
4304 map0 { 3872 map0 {
4305 trip 3873 trip = <&cpu5_alert0>;
4306 cooli 3874 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4307 3875 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4308 3876 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4309 3877 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4310 3878 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4311 3879 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4312 }; 3880 };
4313 map1 { 3881 map1 {
4314 trip 3882 trip = <&cpu5_alert1>;
4315 cooli 3883 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4316 3884 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4317 3885 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4318 3886 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4319 3887 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4320 3888 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4321 }; 3889 };
4322 }; 3890 };
4323 }; 3891 };
4324 3892
4325 cpu6_thermal: cpu6-thermal { !! 3893 cpu6-thermal {
4326 polling-delay-passive 3894 polling-delay-passive = <250>;
>> 3895 polling-delay = <0>;
4327 3896
4328 thermal-sensors = <&t 3897 thermal-sensors = <&tsens0 9>;
4329 sustainable-power = < !! 3898 sustainable-power = <1202>;
4330 3899
4331 trips { 3900 trips {
4332 cpu6_alert0: 3901 cpu6_alert0: trip-point0 {
4333 tempe 3902 temperature = <90000>;
4334 hyste 3903 hysteresis = <2000>;
4335 type 3904 type = "passive";
4336 }; 3905 };
4337 3906
4338 cpu6_alert1: 3907 cpu6_alert1: trip-point1 {
4339 tempe 3908 temperature = <95000>;
4340 hyste 3909 hysteresis = <2000>;
4341 type 3910 type = "passive";
4342 }; 3911 };
4343 3912
4344 cpu6_crit: cp !! 3913 cpu6_crit: cpu_crit {
4345 tempe 3914 temperature = <110000>;
4346 hyste 3915 hysteresis = <1000>;
4347 type 3916 type = "critical";
4348 }; 3917 };
4349 }; 3918 };
4350 3919
4351 cooling-maps { 3920 cooling-maps {
4352 map0 { 3921 map0 {
4353 trip 3922 trip = <&cpu6_alert0>;
4354 cooli 3923 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4355 3924 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4356 }; 3925 };
4357 map1 { 3926 map1 {
4358 trip 3927 trip = <&cpu6_alert1>;
4359 cooli 3928 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4360 3929 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4361 }; 3930 };
4362 }; 3931 };
4363 }; 3932 };
4364 3933
4365 cpu7_thermal: cpu7-thermal { !! 3934 cpu7-thermal {
4366 polling-delay-passive 3935 polling-delay-passive = <250>;
>> 3936 polling-delay = <0>;
4367 3937
4368 thermal-sensors = <&t 3938 thermal-sensors = <&tsens0 10>;
4369 sustainable-power = < !! 3939 sustainable-power = <1202>;
4370 3940
4371 trips { 3941 trips {
4372 cpu7_alert0: 3942 cpu7_alert0: trip-point0 {
4373 tempe 3943 temperature = <90000>;
4374 hyste 3944 hysteresis = <2000>;
4375 type 3945 type = "passive";
4376 }; 3946 };
4377 3947
4378 cpu7_alert1: 3948 cpu7_alert1: trip-point1 {
4379 tempe 3949 temperature = <95000>;
4380 hyste 3950 hysteresis = <2000>;
4381 type 3951 type = "passive";
4382 }; 3952 };
4383 3953
4384 cpu7_crit: cp !! 3954 cpu7_crit: cpu_crit {
4385 tempe 3955 temperature = <110000>;
4386 hyste 3956 hysteresis = <1000>;
4387 type 3957 type = "critical";
4388 }; 3958 };
4389 }; 3959 };
4390 3960
4391 cooling-maps { 3961 cooling-maps {
4392 map0 { 3962 map0 {
4393 trip 3963 trip = <&cpu7_alert0>;
4394 cooli 3964 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4395 3965 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4396 }; 3966 };
4397 map1 { 3967 map1 {
4398 trip 3968 trip = <&cpu7_alert1>;
4399 cooli 3969 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4400 3970 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4401 }; 3971 };
4402 }; 3972 };
4403 }; 3973 };
4404 3974
4405 cpu8_thermal: cpu8-thermal { !! 3975 cpu8-thermal {
4406 polling-delay-passive 3976 polling-delay-passive = <250>;
>> 3977 polling-delay = <0>;
4407 3978
4408 thermal-sensors = <&t 3979 thermal-sensors = <&tsens0 11>;
4409 sustainable-power = < !! 3980 sustainable-power = <1202>;
4410 3981
4411 trips { 3982 trips {
4412 cpu8_alert0: 3983 cpu8_alert0: trip-point0 {
4413 tempe 3984 temperature = <90000>;
4414 hyste 3985 hysteresis = <2000>;
4415 type 3986 type = "passive";
4416 }; 3987 };
4417 3988
4418 cpu8_alert1: 3989 cpu8_alert1: trip-point1 {
4419 tempe 3990 temperature = <95000>;
4420 hyste 3991 hysteresis = <2000>;
4421 type 3992 type = "passive";
4422 }; 3993 };
4423 3994
4424 cpu8_crit: cp !! 3995 cpu8_crit: cpu_crit {
4425 tempe 3996 temperature = <110000>;
4426 hyste 3997 hysteresis = <1000>;
4427 type 3998 type = "critical";
4428 }; 3999 };
4429 }; 4000 };
4430 4001
4431 cooling-maps { 4002 cooling-maps {
4432 map0 { 4003 map0 {
4433 trip 4004 trip = <&cpu8_alert0>;
4434 cooli 4005 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4435 4006 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4436 }; 4007 };
4437 map1 { 4008 map1 {
4438 trip 4009 trip = <&cpu8_alert1>;
4439 cooli 4010 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4440 4011 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4441 }; 4012 };
4442 }; 4013 };
4443 }; 4014 };
4444 4015
4445 cpu9_thermal: cpu9-thermal { !! 4016 cpu9-thermal {
4446 polling-delay-passive 4017 polling-delay-passive = <250>;
>> 4018 polling-delay = <0>;
4447 4019
4448 thermal-sensors = <&t 4020 thermal-sensors = <&tsens0 12>;
4449 sustainable-power = < !! 4021 sustainable-power = <1202>;
4450 4022
4451 trips { 4023 trips {
4452 cpu9_alert0: 4024 cpu9_alert0: trip-point0 {
4453 tempe 4025 temperature = <90000>;
4454 hyste 4026 hysteresis = <2000>;
4455 type 4027 type = "passive";
4456 }; 4028 };
4457 4029
4458 cpu9_alert1: 4030 cpu9_alert1: trip-point1 {
4459 tempe 4031 temperature = <95000>;
4460 hyste 4032 hysteresis = <2000>;
4461 type 4033 type = "passive";
4462 }; 4034 };
4463 4035
4464 cpu9_crit: cp !! 4036 cpu9_crit: cpu_crit {
4465 tempe 4037 temperature = <110000>;
4466 hyste 4038 hysteresis = <1000>;
4467 type 4039 type = "critical";
4468 }; 4040 };
4469 }; 4041 };
4470 4042
4471 cooling-maps { 4043 cooling-maps {
4472 map0 { 4044 map0 {
4473 trip 4045 trip = <&cpu9_alert0>;
4474 cooli 4046 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4475 4047 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4476 }; 4048 };
4477 map1 { 4049 map1 {
4478 trip 4050 trip = <&cpu9_alert1>;
4479 cooli 4051 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4480 4052 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4481 }; 4053 };
4482 }; 4054 };
4483 }; 4055 };
4484 4056
4485 aoss0-thermal { 4057 aoss0-thermal {
4486 polling-delay-passive 4058 polling-delay-passive = <250>;
>> 4059 polling-delay = <0>;
4487 4060
4488 thermal-sensors = <&t 4061 thermal-sensors = <&tsens0 0>;
4489 4062
4490 trips { 4063 trips {
4491 aoss0_alert0: 4064 aoss0_alert0: trip-point0 {
4492 tempe 4065 temperature = <90000>;
4493 hyste 4066 hysteresis = <2000>;
4494 type 4067 type = "hot";
4495 }; 4068 };
4496 4069
4497 aoss0_crit: a !! 4070 aoss0_crit: aoss0_crit {
4498 tempe 4071 temperature = <110000>;
4499 hyste 4072 hysteresis = <2000>;
4500 type 4073 type = "critical";
4501 }; 4074 };
4502 }; 4075 };
4503 }; 4076 };
4504 4077
4505 cpuss0-thermal { 4078 cpuss0-thermal {
4506 polling-delay-passive 4079 polling-delay-passive = <250>;
>> 4080 polling-delay = <0>;
4507 4081
4508 thermal-sensors = <&t 4082 thermal-sensors = <&tsens0 7>;
4509 4083
4510 trips { 4084 trips {
4511 cpuss0_alert0 4085 cpuss0_alert0: trip-point0 {
4512 tempe 4086 temperature = <90000>;
4513 hyste 4087 hysteresis = <2000>;
4514 type 4088 type = "hot";
4515 }; 4089 };
4516 cpuss0_crit: !! 4090 cpuss0_crit: cluster0_crit {
4517 tempe 4091 temperature = <110000>;
4518 hyste 4092 hysteresis = <2000>;
4519 type 4093 type = "critical";
4520 }; 4094 };
4521 }; 4095 };
4522 }; 4096 };
4523 4097
4524 cpuss1-thermal { 4098 cpuss1-thermal {
4525 polling-delay-passive 4099 polling-delay-passive = <250>;
>> 4100 polling-delay = <0>;
4526 4101
4527 thermal-sensors = <&t 4102 thermal-sensors = <&tsens0 8>;
4528 4103
4529 trips { 4104 trips {
4530 cpuss1_alert0 4105 cpuss1_alert0: trip-point0 {
4531 tempe 4106 temperature = <90000>;
4532 hyste 4107 hysteresis = <2000>;
4533 type 4108 type = "hot";
4534 }; 4109 };
4535 cpuss1_crit: !! 4110 cpuss1_crit: cluster0_crit {
4536 tempe 4111 temperature = <110000>;
4537 hyste 4112 hysteresis = <2000>;
4538 type 4113 type = "critical";
4539 }; 4114 };
4540 }; 4115 };
4541 }; 4116 };
4542 4117
4543 gpuss0-thermal { 4118 gpuss0-thermal {
4544 polling-delay-passive 4119 polling-delay-passive = <250>;
>> 4120 polling-delay = <0>;
4545 4121
4546 thermal-sensors = <&t 4122 thermal-sensors = <&tsens0 13>;
4547 4123
4548 trips { 4124 trips {
4549 gpuss0_alert0 4125 gpuss0_alert0: trip-point0 {
4550 tempe 4126 temperature = <95000>;
4551 hyste 4127 hysteresis = <2000>;
4552 type 4128 type = "passive";
4553 }; 4129 };
4554 4130
4555 gpuss0_crit: !! 4131 gpuss0_crit: gpuss0_crit {
4556 tempe 4132 temperature = <110000>;
4557 hyste 4133 hysteresis = <2000>;
4558 type 4134 type = "critical";
4559 }; 4135 };
4560 }; 4136 };
4561 4137
4562 cooling-maps { 4138 cooling-maps {
4563 map0 { 4139 map0 {
4564 trip 4140 trip = <&gpuss0_alert0>;
4565 cooli 4141 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4566 }; 4142 };
4567 }; 4143 };
4568 }; 4144 };
4569 4145
4570 gpuss1-thermal { 4146 gpuss1-thermal {
4571 polling-delay-passive 4147 polling-delay-passive = <250>;
>> 4148 polling-delay = <0>;
4572 4149
4573 thermal-sensors = <&t 4150 thermal-sensors = <&tsens0 14>;
4574 4151
4575 trips { 4152 trips {
4576 gpuss1_alert0 4153 gpuss1_alert0: trip-point0 {
4577 tempe 4154 temperature = <95000>;
4578 hyste 4155 hysteresis = <2000>;
4579 type 4156 type = "passive";
4580 }; 4157 };
4581 4158
4582 gpuss1_crit: !! 4159 gpuss1_crit: gpuss1_crit {
4583 tempe 4160 temperature = <110000>;
4584 hyste 4161 hysteresis = <2000>;
4585 type 4162 type = "critical";
4586 }; 4163 };
4587 }; 4164 };
4588 4165
4589 cooling-maps { 4166 cooling-maps {
4590 map0 { 4167 map0 {
4591 trip 4168 trip = <&gpuss1_alert0>;
4592 cooli 4169 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4593 }; 4170 };
4594 }; 4171 };
4595 }; 4172 };
4596 4173
4597 aoss1-thermal { 4174 aoss1-thermal {
4598 polling-delay-passive 4175 polling-delay-passive = <250>;
>> 4176 polling-delay = <0>;
4599 4177
4600 thermal-sensors = <&t 4178 thermal-sensors = <&tsens1 0>;
4601 4179
4602 trips { 4180 trips {
4603 aoss1_alert0: 4181 aoss1_alert0: trip-point0 {
4604 tempe 4182 temperature = <90000>;
4605 hyste 4183 hysteresis = <2000>;
4606 type 4184 type = "hot";
4607 }; 4185 };
4608 4186
4609 aoss1_crit: a !! 4187 aoss1_crit: aoss1_crit {
4610 tempe 4188 temperature = <110000>;
4611 hyste 4189 hysteresis = <2000>;
4612 type 4190 type = "critical";
4613 }; 4191 };
4614 }; 4192 };
4615 }; 4193 };
4616 4194
4617 cwlan-thermal { 4195 cwlan-thermal {
4618 polling-delay-passive 4196 polling-delay-passive = <250>;
>> 4197 polling-delay = <0>;
4619 4198
4620 thermal-sensors = <&t 4199 thermal-sensors = <&tsens1 1>;
4621 4200
4622 trips { 4201 trips {
4623 cwlan_alert0: 4202 cwlan_alert0: trip-point0 {
4624 tempe 4203 temperature = <90000>;
4625 hyste 4204 hysteresis = <2000>;
4626 type 4205 type = "hot";
4627 }; 4206 };
4628 4207
4629 cwlan_crit: c !! 4208 cwlan_crit: cwlan_crit {
4630 tempe 4209 temperature = <110000>;
4631 hyste 4210 hysteresis = <2000>;
4632 type 4211 type = "critical";
4633 }; 4212 };
4634 }; 4213 };
4635 }; 4214 };
4636 4215
4637 audio-thermal { 4216 audio-thermal {
4638 polling-delay-passive 4217 polling-delay-passive = <250>;
>> 4218 polling-delay = <0>;
4639 4219
4640 thermal-sensors = <&t 4220 thermal-sensors = <&tsens1 2>;
4641 4221
4642 trips { 4222 trips {
4643 audio_alert0: 4223 audio_alert0: trip-point0 {
4644 tempe 4224 temperature = <90000>;
4645 hyste 4225 hysteresis = <2000>;
4646 type 4226 type = "hot";
4647 }; 4227 };
4648 4228
4649 audio_crit: a !! 4229 audio_crit: audio_crit {
4650 tempe 4230 temperature = <110000>;
4651 hyste 4231 hysteresis = <2000>;
4652 type 4232 type = "critical";
4653 }; 4233 };
4654 }; 4234 };
4655 }; 4235 };
4656 4236
4657 ddr-thermal { 4237 ddr-thermal {
4658 polling-delay-passive 4238 polling-delay-passive = <250>;
>> 4239 polling-delay = <0>;
4659 4240
4660 thermal-sensors = <&t 4241 thermal-sensors = <&tsens1 3>;
4661 4242
4662 trips { 4243 trips {
4663 ddr_alert0: t 4244 ddr_alert0: trip-point0 {
4664 tempe 4245 temperature = <90000>;
4665 hyste 4246 hysteresis = <2000>;
4666 type 4247 type = "hot";
4667 }; 4248 };
4668 4249
4669 ddr_crit: ddr !! 4250 ddr_crit: ddr_crit {
4670 tempe 4251 temperature = <110000>;
4671 hyste 4252 hysteresis = <2000>;
4672 type 4253 type = "critical";
4673 }; 4254 };
4674 }; 4255 };
4675 }; 4256 };
4676 4257
4677 q6-hvx-thermal { 4258 q6-hvx-thermal {
4678 polling-delay-passive 4259 polling-delay-passive = <250>;
>> 4260 polling-delay = <0>;
4679 4261
4680 thermal-sensors = <&t 4262 thermal-sensors = <&tsens1 4>;
4681 4263
4682 trips { 4264 trips {
4683 q6_hvx_alert0 4265 q6_hvx_alert0: trip-point0 {
4684 tempe 4266 temperature = <90000>;
4685 hyste 4267 hysteresis = <2000>;
4686 type 4268 type = "hot";
4687 }; 4269 };
4688 4270
4689 q6_hvx_crit: !! 4271 q6_hvx_crit: q6_hvx_crit {
4690 tempe 4272 temperature = <110000>;
4691 hyste 4273 hysteresis = <2000>;
4692 type 4274 type = "critical";
4693 }; 4275 };
4694 }; 4276 };
4695 }; 4277 };
4696 4278
4697 camera-thermal { 4279 camera-thermal {
4698 polling-delay-passive 4280 polling-delay-passive = <250>;
>> 4281 polling-delay = <0>;
4699 4282
4700 thermal-sensors = <&t 4283 thermal-sensors = <&tsens1 5>;
4701 4284
4702 trips { 4285 trips {
4703 camera_alert0 4286 camera_alert0: trip-point0 {
4704 tempe 4287 temperature = <90000>;
4705 hyste 4288 hysteresis = <2000>;
4706 type 4289 type = "hot";
4707 }; 4290 };
4708 4291
4709 camera_crit: !! 4292 camera_crit: camera_crit {
4710 tempe 4293 temperature = <110000>;
4711 hyste 4294 hysteresis = <2000>;
4712 type 4295 type = "critical";
4713 }; 4296 };
4714 }; 4297 };
4715 }; 4298 };
4716 4299
4717 mdm-core-thermal { 4300 mdm-core-thermal {
4718 polling-delay-passive 4301 polling-delay-passive = <250>;
>> 4302 polling-delay = <0>;
4719 4303
4720 thermal-sensors = <&t 4304 thermal-sensors = <&tsens1 6>;
4721 4305
4722 trips { 4306 trips {
4723 mdm_alert0: t 4307 mdm_alert0: trip-point0 {
4724 tempe 4308 temperature = <90000>;
4725 hyste 4309 hysteresis = <2000>;
4726 type 4310 type = "hot";
4727 }; 4311 };
4728 4312
4729 mdm_crit: mdm !! 4313 mdm_crit: mdm_crit {
4730 tempe 4314 temperature = <110000>;
4731 hyste 4315 hysteresis = <2000>;
4732 type 4316 type = "critical";
4733 }; 4317 };
4734 }; 4318 };
4735 }; 4319 };
4736 4320
4737 mdm-dsp-thermal { 4321 mdm-dsp-thermal {
4738 polling-delay-passive 4322 polling-delay-passive = <250>;
>> 4323 polling-delay = <0>;
4739 4324
4740 thermal-sensors = <&t 4325 thermal-sensors = <&tsens1 7>;
4741 4326
4742 trips { 4327 trips {
4743 mdm_dsp_alert 4328 mdm_dsp_alert0: trip-point0 {
4744 tempe 4329 temperature = <90000>;
4745 hyste 4330 hysteresis = <2000>;
4746 type 4331 type = "hot";
4747 }; 4332 };
4748 4333
4749 mdm_dsp_crit: !! 4334 mdm_dsp_crit: mdm_dsp_crit {
4750 tempe 4335 temperature = <110000>;
4751 hyste 4336 hysteresis = <2000>;
4752 type 4337 type = "critical";
4753 }; 4338 };
4754 }; 4339 };
4755 }; 4340 };
4756 4341
4757 npu-thermal { 4342 npu-thermal {
4758 polling-delay-passive 4343 polling-delay-passive = <250>;
>> 4344 polling-delay = <0>;
4759 4345
4760 thermal-sensors = <&t 4346 thermal-sensors = <&tsens1 8>;
4761 4347
4762 trips { 4348 trips {
4763 npu_alert0: t 4349 npu_alert0: trip-point0 {
4764 tempe 4350 temperature = <90000>;
4765 hyste 4351 hysteresis = <2000>;
4766 type 4352 type = "hot";
4767 }; 4353 };
4768 4354
4769 npu_crit: npu !! 4355 npu_crit: npu_crit {
4770 tempe 4356 temperature = <110000>;
4771 hyste 4357 hysteresis = <2000>;
4772 type 4358 type = "critical";
4773 }; 4359 };
4774 }; 4360 };
4775 }; 4361 };
4776 4362
4777 video-thermal { 4363 video-thermal {
4778 polling-delay-passive 4364 polling-delay-passive = <250>;
>> 4365 polling-delay = <0>;
4779 4366
4780 thermal-sensors = <&t 4367 thermal-sensors = <&tsens1 9>;
4781 4368
4782 trips { 4369 trips {
4783 video_alert0: 4370 video_alert0: trip-point0 {
4784 tempe 4371 temperature = <90000>;
4785 hyste 4372 hysteresis = <2000>;
4786 type 4373 type = "hot";
4787 }; 4374 };
4788 4375
4789 video_crit: v !! 4376 video_crit: video_crit {
4790 tempe 4377 temperature = <110000>;
4791 hyste 4378 hysteresis = <2000>;
4792 type 4379 type = "critical";
4793 }; 4380 };
4794 }; 4381 };
4795 }; 4382 };
4796 }; 4383 };
4797 4384
4798 timer { 4385 timer {
4799 compatible = "arm,armv8-timer 4386 compatible = "arm,armv8-timer";
4800 interrupts = <GIC_PPI 1 IRQ_T 4387 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
4801 <GIC_PPI 2 IRQ_T 4388 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
4802 <GIC_PPI 3 IRQ_T 4389 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
4803 <GIC_PPI 0 IRQ_T 4390 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
4804 }; 4391 };
4805 }; 4392 };
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