1 // SPDX-License-Identifier: BSD-3-Clause 1 // SPDX-License-Identifier: BSD-3-Clause
2 /* 2 /*
3 * SC7180 SoC device tree source 3 * SC7180 SoC device tree source
4 * 4 *
5 * Copyright (c) 2019-2020, The Linux Foundati 5 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
6 */ 6 */
7 7
8 #include <dt-bindings/clock/qcom,dispcc-sc7180 8 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
9 #include <dt-bindings/clock/qcom,gcc-sc7180.h> 9 #include <dt-bindings/clock/qcom,gcc-sc7180.h>
10 #include <dt-bindings/clock/qcom,gpucc-sc7180. 10 #include <dt-bindings/clock/qcom,gpucc-sc7180.h>
11 #include <dt-bindings/clock/qcom,lpasscorecc-s 11 #include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h>
12 #include <dt-bindings/clock/qcom,rpmh.h> 12 #include <dt-bindings/clock/qcom,rpmh.h>
13 #include <dt-bindings/clock/qcom,videocc-sc718 13 #include <dt-bindings/clock/qcom,videocc-sc7180.h>
14 #include <dt-bindings/firmware/qcom,scm.h> <<
15 #include <dt-bindings/interconnect/qcom,icc.h> <<
16 #include <dt-bindings/interconnect/qcom,osm-l3 14 #include <dt-bindings/interconnect/qcom,osm-l3.h>
17 #include <dt-bindings/interconnect/qcom,sc7180 15 #include <dt-bindings/interconnect/qcom,sc7180.h>
18 #include <dt-bindings/interrupt-controller/arm 16 #include <dt-bindings/interrupt-controller/arm-gic.h>
19 #include <dt-bindings/phy/phy-qcom-qmp.h> <<
20 #include <dt-bindings/phy/phy-qcom-qusb2.h> 17 #include <dt-bindings/phy/phy-qcom-qusb2.h>
>> 18 #include <dt-bindings/power/qcom-aoss-qmp.h>
21 #include <dt-bindings/power/qcom-rpmpd.h> 19 #include <dt-bindings/power/qcom-rpmpd.h>
22 #include <dt-bindings/reset/qcom,sdm845-aoss.h 20 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
23 #include <dt-bindings/reset/qcom,sdm845-pdc.h> 21 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
24 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 22 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
25 #include <dt-bindings/soc/qcom,apr.h> <<
26 #include <dt-bindings/sound/qcom,q6afe.h> <<
27 #include <dt-bindings/thermal/thermal.h> 23 #include <dt-bindings/thermal/thermal.h>
28 24
29 / { 25 / {
30 interrupt-parent = <&intc>; 26 interrupt-parent = <&intc>;
31 27
32 #address-cells = <2>; 28 #address-cells = <2>;
33 #size-cells = <2>; 29 #size-cells = <2>;
34 30
>> 31 chosen { };
>> 32
35 aliases { 33 aliases {
36 mmc1 = &sdhc_1; 34 mmc1 = &sdhc_1;
37 mmc2 = &sdhc_2; 35 mmc2 = &sdhc_2;
38 i2c0 = &i2c0; 36 i2c0 = &i2c0;
39 i2c1 = &i2c1; 37 i2c1 = &i2c1;
40 i2c2 = &i2c2; 38 i2c2 = &i2c2;
41 i2c3 = &i2c3; 39 i2c3 = &i2c3;
42 i2c4 = &i2c4; 40 i2c4 = &i2c4;
43 i2c5 = &i2c5; 41 i2c5 = &i2c5;
44 i2c6 = &i2c6; 42 i2c6 = &i2c6;
45 i2c7 = &i2c7; 43 i2c7 = &i2c7;
46 i2c8 = &i2c8; 44 i2c8 = &i2c8;
47 i2c9 = &i2c9; 45 i2c9 = &i2c9;
48 i2c10 = &i2c10; 46 i2c10 = &i2c10;
49 i2c11 = &i2c11; 47 i2c11 = &i2c11;
50 spi0 = &spi0; 48 spi0 = &spi0;
51 spi1 = &spi1; 49 spi1 = &spi1;
52 spi3 = &spi3; 50 spi3 = &spi3;
53 spi5 = &spi5; 51 spi5 = &spi5;
54 spi6 = &spi6; 52 spi6 = &spi6;
55 spi8 = &spi8; 53 spi8 = &spi8;
56 spi10 = &spi10; 54 spi10 = &spi10;
57 spi11 = &spi11; 55 spi11 = &spi11;
58 }; 56 };
59 57
60 chosen { }; <<
61 <<
62 clocks { 58 clocks {
63 xo_board: xo-board { 59 xo_board: xo-board {
64 compatible = "fixed-cl 60 compatible = "fixed-clock";
65 clock-frequency = <384 61 clock-frequency = <38400000>;
66 #clock-cells = <0>; 62 #clock-cells = <0>;
67 }; 63 };
68 64
69 sleep_clk: sleep-clk { 65 sleep_clk: sleep-clk {
70 compatible = "fixed-cl 66 compatible = "fixed-clock";
71 clock-frequency = <327 67 clock-frequency = <32764>;
72 #clock-cells = <0>; 68 #clock-cells = <0>;
73 }; 69 };
74 }; 70 };
75 71
>> 72 reserved_memory: reserved-memory {
>> 73 #address-cells = <2>;
>> 74 #size-cells = <2>;
>> 75 ranges;
>> 76
>> 77 hyp_mem: memory@80000000 {
>> 78 reg = <0x0 0x80000000 0x0 0x600000>;
>> 79 no-map;
>> 80 };
>> 81
>> 82 xbl_mem: memory@80600000 {
>> 83 reg = <0x0 0x80600000 0x0 0x200000>;
>> 84 no-map;
>> 85 };
>> 86
>> 87 aop_mem: memory@80800000 {
>> 88 reg = <0x0 0x80800000 0x0 0x20000>;
>> 89 no-map;
>> 90 };
>> 91
>> 92 aop_cmd_db_mem: memory@80820000 {
>> 93 reg = <0x0 0x80820000 0x0 0x20000>;
>> 94 compatible = "qcom,cmd-db";
>> 95 no-map;
>> 96 };
>> 97
>> 98 sec_apps_mem: memory@808ff000 {
>> 99 reg = <0x0 0x808ff000 0x0 0x1000>;
>> 100 no-map;
>> 101 };
>> 102
>> 103 smem_mem: memory@80900000 {
>> 104 reg = <0x0 0x80900000 0x0 0x200000>;
>> 105 no-map;
>> 106 };
>> 107
>> 108 tz_mem: memory@80b00000 {
>> 109 reg = <0x0 0x80b00000 0x0 0x3900000>;
>> 110 no-map;
>> 111 };
>> 112
>> 113 rmtfs_mem: memory@84400000 {
>> 114 compatible = "qcom,rmtfs-mem";
>> 115 reg = <0x0 0x84400000 0x0 0x200000>;
>> 116 no-map;
>> 117
>> 118 qcom,client-id = <1>;
>> 119 qcom,vmid = <15>;
>> 120 };
>> 121 };
>> 122
76 cpus { 123 cpus {
77 #address-cells = <2>; 124 #address-cells = <2>;
78 #size-cells = <0>; 125 #size-cells = <0>;
79 126
80 CPU0: cpu@0 { 127 CPU0: cpu@0 {
81 device_type = "cpu"; 128 device_type = "cpu";
82 compatible = "qcom,kry 129 compatible = "qcom,kryo468";
83 reg = <0x0 0x0>; 130 reg = <0x0 0x0>;
84 clocks = <&cpufreq_hw <<
85 enable-method = "psci" 131 enable-method = "psci";
86 power-domains = <&CPU_ !! 132 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
87 power-domain-names = " !! 133 &LITTLE_CPU_SLEEP_1
88 capacity-dmips-mhz = < !! 134 &CLUSTER_SLEEP_0>;
89 dynamic-power-coeffici !! 135 capacity-dmips-mhz = <1024>;
>> 136 dynamic-power-coefficient = <100>;
90 operating-points-v2 = 137 operating-points-v2 = <&cpu0_opp_table>;
91 interconnects = <&gem_ 138 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
92 <&osm_ 139 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
93 next-level-cache = <&L 140 next-level-cache = <&L2_0>;
94 #cooling-cells = <2>; 141 #cooling-cells = <2>;
95 qcom,freq-domain = <&c 142 qcom,freq-domain = <&cpufreq_hw 0>;
96 L2_0: l2-cache { 143 L2_0: l2-cache {
97 compatible = " 144 compatible = "cache";
98 cache-level = <<
99 cache-unified; <<
100 next-level-cac 145 next-level-cache = <&L3_0>;
101 L3_0: l3-cache 146 L3_0: l3-cache {
102 compat 147 compatible = "cache";
103 cache- <<
104 cache- <<
105 }; 148 };
106 }; 149 };
107 }; 150 };
108 151
109 CPU1: cpu@100 { 152 CPU1: cpu@100 {
110 device_type = "cpu"; 153 device_type = "cpu";
111 compatible = "qcom,kry 154 compatible = "qcom,kryo468";
112 reg = <0x0 0x100>; 155 reg = <0x0 0x100>;
113 clocks = <&cpufreq_hw <<
114 enable-method = "psci" 156 enable-method = "psci";
115 power-domains = <&CPU_ !! 157 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
116 power-domain-names = " !! 158 &LITTLE_CPU_SLEEP_1
117 capacity-dmips-mhz = < !! 159 &CLUSTER_SLEEP_0>;
118 dynamic-power-coeffici !! 160 capacity-dmips-mhz = <1024>;
>> 161 dynamic-power-coefficient = <100>;
119 next-level-cache = <&L 162 next-level-cache = <&L2_100>;
120 operating-points-v2 = 163 operating-points-v2 = <&cpu0_opp_table>;
121 interconnects = <&gem_ 164 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
122 <&osm_ 165 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
123 #cooling-cells = <2>; 166 #cooling-cells = <2>;
124 qcom,freq-domain = <&c 167 qcom,freq-domain = <&cpufreq_hw 0>;
125 L2_100: l2-cache { 168 L2_100: l2-cache {
126 compatible = " 169 compatible = "cache";
127 cache-level = <<
128 cache-unified; <<
129 next-level-cac 170 next-level-cache = <&L3_0>;
130 }; 171 };
131 }; 172 };
132 173
133 CPU2: cpu@200 { 174 CPU2: cpu@200 {
134 device_type = "cpu"; 175 device_type = "cpu";
135 compatible = "qcom,kry 176 compatible = "qcom,kryo468";
136 reg = <0x0 0x200>; 177 reg = <0x0 0x200>;
137 clocks = <&cpufreq_hw <<
138 enable-method = "psci" 178 enable-method = "psci";
139 power-domains = <&CPU_ !! 179 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
140 power-domain-names = " !! 180 &LITTLE_CPU_SLEEP_1
141 capacity-dmips-mhz = < !! 181 &CLUSTER_SLEEP_0>;
142 dynamic-power-coeffici !! 182 capacity-dmips-mhz = <1024>;
>> 183 dynamic-power-coefficient = <100>;
143 next-level-cache = <&L 184 next-level-cache = <&L2_200>;
144 operating-points-v2 = 185 operating-points-v2 = <&cpu0_opp_table>;
145 interconnects = <&gem_ 186 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
146 <&osm_ 187 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
147 #cooling-cells = <2>; 188 #cooling-cells = <2>;
148 qcom,freq-domain = <&c 189 qcom,freq-domain = <&cpufreq_hw 0>;
149 L2_200: l2-cache { 190 L2_200: l2-cache {
150 compatible = " 191 compatible = "cache";
151 cache-level = <<
152 cache-unified; <<
153 next-level-cac 192 next-level-cache = <&L3_0>;
154 }; 193 };
155 }; 194 };
156 195
157 CPU3: cpu@300 { 196 CPU3: cpu@300 {
158 device_type = "cpu"; 197 device_type = "cpu";
159 compatible = "qcom,kry 198 compatible = "qcom,kryo468";
160 reg = <0x0 0x300>; 199 reg = <0x0 0x300>;
161 clocks = <&cpufreq_hw <<
162 enable-method = "psci" 200 enable-method = "psci";
163 power-domains = <&CPU_ !! 201 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
164 power-domain-names = " !! 202 &LITTLE_CPU_SLEEP_1
165 capacity-dmips-mhz = < !! 203 &CLUSTER_SLEEP_0>;
166 dynamic-power-coeffici !! 204 capacity-dmips-mhz = <1024>;
>> 205 dynamic-power-coefficient = <100>;
167 next-level-cache = <&L 206 next-level-cache = <&L2_300>;
168 operating-points-v2 = 207 operating-points-v2 = <&cpu0_opp_table>;
169 interconnects = <&gem_ 208 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
170 <&osm_ 209 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
171 #cooling-cells = <2>; 210 #cooling-cells = <2>;
172 qcom,freq-domain = <&c 211 qcom,freq-domain = <&cpufreq_hw 0>;
173 L2_300: l2-cache { 212 L2_300: l2-cache {
174 compatible = " 213 compatible = "cache";
175 cache-level = <<
176 cache-unified; <<
177 next-level-cac 214 next-level-cache = <&L3_0>;
178 }; 215 };
179 }; 216 };
180 217
181 CPU4: cpu@400 { 218 CPU4: cpu@400 {
182 device_type = "cpu"; 219 device_type = "cpu";
183 compatible = "qcom,kry 220 compatible = "qcom,kryo468";
184 reg = <0x0 0x400>; 221 reg = <0x0 0x400>;
185 clocks = <&cpufreq_hw <<
186 enable-method = "psci" 222 enable-method = "psci";
187 power-domains = <&CPU_ !! 223 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
188 power-domain-names = " !! 224 &LITTLE_CPU_SLEEP_1
189 capacity-dmips-mhz = < !! 225 &CLUSTER_SLEEP_0>;
190 dynamic-power-coeffici !! 226 capacity-dmips-mhz = <1024>;
>> 227 dynamic-power-coefficient = <100>;
191 next-level-cache = <&L 228 next-level-cache = <&L2_400>;
192 operating-points-v2 = 229 operating-points-v2 = <&cpu0_opp_table>;
193 interconnects = <&gem_ 230 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
194 <&osm_ 231 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
195 #cooling-cells = <2>; 232 #cooling-cells = <2>;
196 qcom,freq-domain = <&c 233 qcom,freq-domain = <&cpufreq_hw 0>;
197 L2_400: l2-cache { 234 L2_400: l2-cache {
198 compatible = " 235 compatible = "cache";
199 cache-level = <<
200 cache-unified; <<
201 next-level-cac 236 next-level-cache = <&L3_0>;
202 }; 237 };
203 }; 238 };
204 239
205 CPU5: cpu@500 { 240 CPU5: cpu@500 {
206 device_type = "cpu"; 241 device_type = "cpu";
207 compatible = "qcom,kry 242 compatible = "qcom,kryo468";
208 reg = <0x0 0x500>; 243 reg = <0x0 0x500>;
209 clocks = <&cpufreq_hw <<
210 enable-method = "psci" 244 enable-method = "psci";
211 power-domains = <&CPU_ !! 245 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
212 power-domain-names = " !! 246 &LITTLE_CPU_SLEEP_1
213 capacity-dmips-mhz = < !! 247 &CLUSTER_SLEEP_0>;
214 dynamic-power-coeffici !! 248 capacity-dmips-mhz = <1024>;
>> 249 dynamic-power-coefficient = <100>;
215 next-level-cache = <&L 250 next-level-cache = <&L2_500>;
216 operating-points-v2 = 251 operating-points-v2 = <&cpu0_opp_table>;
217 interconnects = <&gem_ 252 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
218 <&osm_ 253 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
219 #cooling-cells = <2>; 254 #cooling-cells = <2>;
220 qcom,freq-domain = <&c 255 qcom,freq-domain = <&cpufreq_hw 0>;
221 L2_500: l2-cache { 256 L2_500: l2-cache {
222 compatible = " 257 compatible = "cache";
223 cache-level = <<
224 cache-unified; <<
225 next-level-cac 258 next-level-cache = <&L3_0>;
226 }; 259 };
227 }; 260 };
228 261
229 CPU6: cpu@600 { 262 CPU6: cpu@600 {
230 device_type = "cpu"; 263 device_type = "cpu";
231 compatible = "qcom,kry 264 compatible = "qcom,kryo468";
232 reg = <0x0 0x600>; 265 reg = <0x0 0x600>;
233 clocks = <&cpufreq_hw <<
234 enable-method = "psci" 266 enable-method = "psci";
235 power-domains = <&CPU_ !! 267 cpu-idle-states = <&BIG_CPU_SLEEP_0
236 power-domain-names = " !! 268 &BIG_CPU_SLEEP_1
237 capacity-dmips-mhz = < !! 269 &CLUSTER_SLEEP_0>;
238 dynamic-power-coeffici !! 270 capacity-dmips-mhz = <1740>;
>> 271 dynamic-power-coefficient = <405>;
239 next-level-cache = <&L 272 next-level-cache = <&L2_600>;
240 operating-points-v2 = 273 operating-points-v2 = <&cpu6_opp_table>;
241 interconnects = <&gem_ 274 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
242 <&osm_ 275 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
243 #cooling-cells = <2>; 276 #cooling-cells = <2>;
244 qcom,freq-domain = <&c 277 qcom,freq-domain = <&cpufreq_hw 1>;
245 L2_600: l2-cache { 278 L2_600: l2-cache {
246 compatible = " 279 compatible = "cache";
247 cache-level = <<
248 cache-unified; <<
249 next-level-cac 280 next-level-cache = <&L3_0>;
250 }; 281 };
251 }; 282 };
252 283
253 CPU7: cpu@700 { 284 CPU7: cpu@700 {
254 device_type = "cpu"; 285 device_type = "cpu";
255 compatible = "qcom,kry 286 compatible = "qcom,kryo468";
256 reg = <0x0 0x700>; 287 reg = <0x0 0x700>;
257 clocks = <&cpufreq_hw <<
258 enable-method = "psci" 288 enable-method = "psci";
259 power-domains = <&CPU_ !! 289 cpu-idle-states = <&BIG_CPU_SLEEP_0
260 power-domain-names = " !! 290 &BIG_CPU_SLEEP_1
261 capacity-dmips-mhz = < !! 291 &CLUSTER_SLEEP_0>;
262 dynamic-power-coeffici !! 292 capacity-dmips-mhz = <1740>;
>> 293 dynamic-power-coefficient = <405>;
263 next-level-cache = <&L 294 next-level-cache = <&L2_700>;
264 operating-points-v2 = 295 operating-points-v2 = <&cpu6_opp_table>;
265 interconnects = <&gem_ 296 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
266 <&osm_ 297 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
267 #cooling-cells = <2>; 298 #cooling-cells = <2>;
268 qcom,freq-domain = <&c 299 qcom,freq-domain = <&cpufreq_hw 1>;
269 L2_700: l2-cache { 300 L2_700: l2-cache {
270 compatible = " 301 compatible = "cache";
271 cache-level = <<
272 cache-unified; <<
273 next-level-cac 302 next-level-cache = <&L3_0>;
274 }; 303 };
275 }; 304 };
276 305
277 cpu-map { 306 cpu-map {
278 cluster0 { 307 cluster0 {
279 core0 { 308 core0 {
280 cpu = 309 cpu = <&CPU0>;
281 }; 310 };
282 311
283 core1 { 312 core1 {
284 cpu = 313 cpu = <&CPU1>;
285 }; 314 };
286 315
287 core2 { 316 core2 {
288 cpu = 317 cpu = <&CPU2>;
289 }; 318 };
290 319
291 core3 { 320 core3 {
292 cpu = 321 cpu = <&CPU3>;
293 }; 322 };
294 323
295 core4 { 324 core4 {
296 cpu = 325 cpu = <&CPU4>;
297 }; 326 };
298 327
299 core5 { 328 core5 {
300 cpu = 329 cpu = <&CPU5>;
301 }; 330 };
302 331
303 core6 { 332 core6 {
304 cpu = 333 cpu = <&CPU6>;
305 }; 334 };
306 335
307 core7 { 336 core7 {
308 cpu = 337 cpu = <&CPU7>;
309 }; 338 };
310 }; 339 };
311 }; 340 };
312 341
313 idle_states: idle-states { !! 342 idle-states {
314 entry-method = "psci"; 343 entry-method = "psci";
315 344
316 LITTLE_CPU_SLEEP_0: cp 345 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
317 compatible = " 346 compatible = "arm,idle-state";
318 idle-state-nam 347 idle-state-name = "little-power-down";
319 arm,psci-suspe 348 arm,psci-suspend-param = <0x40000003>;
320 entry-latency- 349 entry-latency-us = <549>;
321 exit-latency-u 350 exit-latency-us = <901>;
322 min-residency- 351 min-residency-us = <1774>;
323 local-timer-st 352 local-timer-stop;
324 }; 353 };
325 354
326 LITTLE_CPU_SLEEP_1: cp 355 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
327 compatible = " 356 compatible = "arm,idle-state";
328 idle-state-nam 357 idle-state-name = "little-rail-power-down";
329 arm,psci-suspe 358 arm,psci-suspend-param = <0x40000004>;
330 entry-latency- 359 entry-latency-us = <702>;
331 exit-latency-u 360 exit-latency-us = <915>;
332 min-residency- 361 min-residency-us = <4001>;
333 local-timer-st 362 local-timer-stop;
334 }; 363 };
335 364
336 BIG_CPU_SLEEP_0: cpu-s 365 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
337 compatible = " 366 compatible = "arm,idle-state";
338 idle-state-nam 367 idle-state-name = "big-power-down";
339 arm,psci-suspe 368 arm,psci-suspend-param = <0x40000003>;
340 entry-latency- 369 entry-latency-us = <523>;
341 exit-latency-u 370 exit-latency-us = <1244>;
342 min-residency- 371 min-residency-us = <2207>;
343 local-timer-st 372 local-timer-stop;
344 }; 373 };
345 374
346 BIG_CPU_SLEEP_1: cpu-s 375 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
347 compatible = " 376 compatible = "arm,idle-state";
348 idle-state-nam 377 idle-state-name = "big-rail-power-down";
349 arm,psci-suspe 378 arm,psci-suspend-param = <0x40000004>;
350 entry-latency- 379 entry-latency-us = <526>;
351 exit-latency-u 380 exit-latency-us = <1854>;
352 min-residency- 381 min-residency-us = <5555>;
353 local-timer-st 382 local-timer-stop;
354 }; 383 };
355 }; <<
356 <<
357 domain_idle_states: domain-idl <<
358 CLUSTER_SLEEP_PC: clus <<
359 compatible = " <<
360 idle-state-nam <<
361 arm,psci-suspe <<
362 entry-latency- <<
363 exit-latency-u <<
364 min-residency- <<
365 }; <<
366 <<
367 CLUSTER_SLEEP_CX_RET: <<
368 compatible = " <<
369 idle-state-nam <<
370 arm,psci-suspe <<
371 entry-latency- <<
372 exit-latency-u <<
373 min-residency- <<
374 }; <<
375 384
376 CLUSTER_AOSS_SLEEP: cl !! 385 CLUSTER_SLEEP_0: cluster-sleep-0 {
377 compatible = " !! 386 compatible = "arm,idle-state";
378 idle-state-nam 387 idle-state-name = "cluster-power-down";
379 arm,psci-suspe !! 388 arm,psci-suspend-param = <0x40003444>;
380 entry-latency- 389 entry-latency-us = <3263>;
381 exit-latency-u 390 exit-latency-us = <6562>;
382 min-residency- !! 391 min-residency-us = <9926>;
>> 392 local-timer-stop;
383 }; 393 };
384 }; 394 };
385 }; 395 };
386 396
387 firmware { !! 397 cpu0_opp_table: cpu0_opp_table {
388 scm: scm { <<
389 compatible = "qcom,scm <<
390 }; <<
391 }; <<
392 <<
393 memory@80000000 { <<
394 device_type = "memory"; <<
395 /* We expect the bootloader to <<
396 reg = <0 0x80000000 0 0>; <<
397 }; <<
398 <<
399 cpu0_opp_table: opp-table-cpu0 { <<
400 compatible = "operating-points 398 compatible = "operating-points-v2";
401 opp-shared; 399 opp-shared;
402 400
403 cpu0_opp1: opp-300000000 { 401 cpu0_opp1: opp-300000000 {
404 opp-hz = /bits/ 64 <30 402 opp-hz = /bits/ 64 <300000000>;
405 opp-peak-kBps = <12000 403 opp-peak-kBps = <1200000 4800000>;
406 }; 404 };
407 405
408 cpu0_opp2: opp-576000000 { 406 cpu0_opp2: opp-576000000 {
409 opp-hz = /bits/ 64 <57 407 opp-hz = /bits/ 64 <576000000>;
410 opp-peak-kBps = <12000 408 opp-peak-kBps = <1200000 4800000>;
411 }; 409 };
412 410
413 cpu0_opp3: opp-768000000 { 411 cpu0_opp3: opp-768000000 {
414 opp-hz = /bits/ 64 <76 412 opp-hz = /bits/ 64 <768000000>;
415 opp-peak-kBps = <12000 413 opp-peak-kBps = <1200000 4800000>;
416 }; 414 };
417 415
418 cpu0_opp4: opp-1017600000 { 416 cpu0_opp4: opp-1017600000 {
419 opp-hz = /bits/ 64 <10 417 opp-hz = /bits/ 64 <1017600000>;
420 opp-peak-kBps = <18040 418 opp-peak-kBps = <1804000 8908800>;
421 }; 419 };
422 420
423 cpu0_opp5: opp-1248000000 { 421 cpu0_opp5: opp-1248000000 {
424 opp-hz = /bits/ 64 <12 422 opp-hz = /bits/ 64 <1248000000>;
425 opp-peak-kBps = <21880 423 opp-peak-kBps = <2188000 12902400>;
426 }; 424 };
427 425
428 cpu0_opp6: opp-1324800000 { 426 cpu0_opp6: opp-1324800000 {
429 opp-hz = /bits/ 64 <13 427 opp-hz = /bits/ 64 <1324800000>;
430 opp-peak-kBps = <21880 428 opp-peak-kBps = <2188000 12902400>;
431 }; 429 };
432 430
433 cpu0_opp7: opp-1516800000 { 431 cpu0_opp7: opp-1516800000 {
434 opp-hz = /bits/ 64 <15 432 opp-hz = /bits/ 64 <1516800000>;
435 opp-peak-kBps = <30720 433 opp-peak-kBps = <3072000 15052800>;
436 }; 434 };
437 435
438 cpu0_opp8: opp-1612800000 { 436 cpu0_opp8: opp-1612800000 {
439 opp-hz = /bits/ 64 <16 437 opp-hz = /bits/ 64 <1612800000>;
440 opp-peak-kBps = <30720 438 opp-peak-kBps = <3072000 15052800>;
441 }; 439 };
442 440
443 cpu0_opp9: opp-1708800000 { 441 cpu0_opp9: opp-1708800000 {
444 opp-hz = /bits/ 64 <17 442 opp-hz = /bits/ 64 <1708800000>;
445 opp-peak-kBps = <30720 443 opp-peak-kBps = <3072000 15052800>;
446 }; 444 };
447 445
448 cpu0_opp10: opp-1804800000 { 446 cpu0_opp10: opp-1804800000 {
449 opp-hz = /bits/ 64 <18 447 opp-hz = /bits/ 64 <1804800000>;
450 opp-peak-kBps = <40680 448 opp-peak-kBps = <4068000 22425600>;
451 }; 449 };
452 }; 450 };
453 451
454 cpu6_opp_table: opp-table-cpu6 { !! 452 cpu6_opp_table: cpu6_opp_table {
455 compatible = "operating-points 453 compatible = "operating-points-v2";
456 opp-shared; 454 opp-shared;
457 455
458 cpu6_opp1: opp-300000000 { 456 cpu6_opp1: opp-300000000 {
459 opp-hz = /bits/ 64 <30 457 opp-hz = /bits/ 64 <300000000>;
460 opp-peak-kBps = <21880 458 opp-peak-kBps = <2188000 8908800>;
461 }; 459 };
462 460
463 cpu6_opp2: opp-652800000 { 461 cpu6_opp2: opp-652800000 {
464 opp-hz = /bits/ 64 <65 462 opp-hz = /bits/ 64 <652800000>;
465 opp-peak-kBps = <21880 463 opp-peak-kBps = <2188000 8908800>;
466 }; 464 };
467 465
468 cpu6_opp3: opp-825600000 { 466 cpu6_opp3: opp-825600000 {
469 opp-hz = /bits/ 64 <82 467 opp-hz = /bits/ 64 <825600000>;
470 opp-peak-kBps = <21880 468 opp-peak-kBps = <2188000 8908800>;
471 }; 469 };
472 470
473 cpu6_opp4: opp-979200000 { 471 cpu6_opp4: opp-979200000 {
474 opp-hz = /bits/ 64 <97 472 opp-hz = /bits/ 64 <979200000>;
475 opp-peak-kBps = <21880 473 opp-peak-kBps = <2188000 8908800>;
476 }; 474 };
477 475
478 cpu6_opp5: opp-1113600000 { 476 cpu6_opp5: opp-1113600000 {
479 opp-hz = /bits/ 64 <11 477 opp-hz = /bits/ 64 <1113600000>;
480 opp-peak-kBps = <21880 478 opp-peak-kBps = <2188000 8908800>;
481 }; 479 };
482 480
483 cpu6_opp6: opp-1267200000 { 481 cpu6_opp6: opp-1267200000 {
484 opp-hz = /bits/ 64 <12 482 opp-hz = /bits/ 64 <1267200000>;
485 opp-peak-kBps = <40680 483 opp-peak-kBps = <4068000 12902400>;
486 }; 484 };
487 485
488 cpu6_opp7: opp-1555200000 { 486 cpu6_opp7: opp-1555200000 {
489 opp-hz = /bits/ 64 <15 487 opp-hz = /bits/ 64 <1555200000>;
490 opp-peak-kBps = <40680 488 opp-peak-kBps = <4068000 15052800>;
491 }; 489 };
492 490
493 cpu6_opp8: opp-1708800000 { 491 cpu6_opp8: opp-1708800000 {
494 opp-hz = /bits/ 64 <17 492 opp-hz = /bits/ 64 <1708800000>;
495 opp-peak-kBps = <62200 493 opp-peak-kBps = <6220000 19353600>;
496 }; 494 };
497 495
498 cpu6_opp9: opp-1843200000 { 496 cpu6_opp9: opp-1843200000 {
499 opp-hz = /bits/ 64 <18 497 opp-hz = /bits/ 64 <1843200000>;
500 opp-peak-kBps = <62200 498 opp-peak-kBps = <6220000 19353600>;
501 }; 499 };
502 500
503 cpu6_opp10: opp-1900800000 { 501 cpu6_opp10: opp-1900800000 {
504 opp-hz = /bits/ 64 <19 502 opp-hz = /bits/ 64 <1900800000>;
505 opp-peak-kBps = <62200 503 opp-peak-kBps = <6220000 22425600>;
506 }; 504 };
507 505
508 cpu6_opp11: opp-1996800000 { 506 cpu6_opp11: opp-1996800000 {
509 opp-hz = /bits/ 64 <19 507 opp-hz = /bits/ 64 <1996800000>;
510 opp-peak-kBps = <62200 508 opp-peak-kBps = <6220000 22425600>;
511 }; 509 };
512 510
513 cpu6_opp12: opp-2112000000 { 511 cpu6_opp12: opp-2112000000 {
514 opp-hz = /bits/ 64 <21 512 opp-hz = /bits/ 64 <2112000000>;
515 opp-peak-kBps = <62200 513 opp-peak-kBps = <6220000 22425600>;
516 }; 514 };
517 515
518 cpu6_opp13: opp-2208000000 { 516 cpu6_opp13: opp-2208000000 {
519 opp-hz = /bits/ 64 <22 517 opp-hz = /bits/ 64 <2208000000>;
520 opp-peak-kBps = <72160 518 opp-peak-kBps = <7216000 22425600>;
521 }; 519 };
522 520
523 cpu6_opp14: opp-2323200000 { 521 cpu6_opp14: opp-2323200000 {
524 opp-hz = /bits/ 64 <23 522 opp-hz = /bits/ 64 <2323200000>;
525 opp-peak-kBps = <72160 523 opp-peak-kBps = <7216000 22425600>;
526 }; 524 };
527 525
528 cpu6_opp15: opp-2400000000 { 526 cpu6_opp15: opp-2400000000 {
529 opp-hz = /bits/ 64 <24 527 opp-hz = /bits/ 64 <2400000000>;
530 opp-peak-kBps = <85320 528 opp-peak-kBps = <8532000 23347200>;
531 }; 529 };
532 530
533 cpu6_opp16: opp-2553600000 { 531 cpu6_opp16: opp-2553600000 {
534 opp-hz = /bits/ 64 <25 532 opp-hz = /bits/ 64 <2553600000>;
535 opp-peak-kBps = <85320 533 opp-peak-kBps = <8532000 23347200>;
536 }; 534 };
537 }; 535 };
538 536
539 qspi_opp_table: opp-table-qspi { !! 537 memory@80000000 {
540 compatible = "operating-points !! 538 device_type = "memory";
541 !! 539 /* We expect the bootloader to fill in the size */
542 opp-75000000 { !! 540 reg = <0 0x80000000 0 0>;
543 opp-hz = /bits/ 64 <75 <<
544 required-opps = <&rpmh <<
545 }; <<
546 <<
547 opp-150000000 { <<
548 opp-hz = /bits/ 64 <15 <<
549 required-opps = <&rpmh <<
550 }; <<
551 <<
552 opp-300000000 { <<
553 opp-hz = /bits/ 64 <30 <<
554 required-opps = <&rpmh <<
555 }; <<
556 }; <<
557 <<
558 qup_opp_table: opp-table-qup { <<
559 compatible = "operating-points <<
560 <<
561 opp-75000000 { <<
562 opp-hz = /bits/ 64 <75 <<
563 required-opps = <&rpmh <<
564 }; <<
565 <<
566 opp-100000000 { <<
567 opp-hz = /bits/ 64 <10 <<
568 required-opps = <&rpmh <<
569 }; <<
570 <<
571 opp-128000000 { <<
572 opp-hz = /bits/ 64 <12 <<
573 required-opps = <&rpmh <<
574 }; <<
575 }; 541 };
576 542
577 pmu { 543 pmu {
578 compatible = "arm,armv8-pmuv3" 544 compatible = "arm,armv8-pmuv3";
579 interrupts = <GIC_PPI 5 IRQ_TY 545 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
580 }; 546 };
581 547
582 psci { !! 548 firmware {
583 compatible = "arm,psci-1.0"; !! 549 scm {
584 method = "smc"; !! 550 compatible = "qcom,scm-sc7180", "qcom,scm";
585 <<
586 CPU_PD0: cpu0 { <<
587 #power-domain-cells = <<
588 power-domains = <&CLUS <<
589 domain-idle-states = < <<
590 }; <<
591 <<
592 CPU_PD1: cpu1 { <<
593 #power-domain-cells = <<
594 power-domains = <&CLUS <<
595 domain-idle-states = < <<
596 }; <<
597 <<
598 CPU_PD2: cpu2 { <<
599 #power-domain-cells = <<
600 power-domains = <&CLUS <<
601 domain-idle-states = < <<
602 }; <<
603 <<
604 CPU_PD3: cpu3 { <<
605 #power-domain-cells = <<
606 power-domains = <&CLUS <<
607 domain-idle-states = < <<
608 }; <<
609 <<
610 CPU_PD4: cpu4 { <<
611 #power-domain-cells = <<
612 power-domains = <&CLUS <<
613 domain-idle-states = < <<
614 }; <<
615 <<
616 CPU_PD5: cpu5 { <<
617 #power-domain-cells = <<
618 power-domains = <&CLUS <<
619 domain-idle-states = < <<
620 }; <<
621 <<
622 CPU_PD6: cpu6 { <<
623 #power-domain-cells = <<
624 power-domains = <&CLUS <<
625 domain-idle-states = < <<
626 }; <<
627 <<
628 CPU_PD7: cpu7 { <<
629 #power-domain-cells = <<
630 power-domains = <&CLUS <<
631 domain-idle-states = < <<
632 }; <<
633 <<
634 CLUSTER_PD: cpu-cluster0 { <<
635 #power-domain-cells = <<
636 domain-idle-states = < <<
637 <<
638 <<
639 }; 551 };
640 }; 552 };
641 553
642 reserved_memory: reserved-memory { !! 554 tcsr_mutex: hwlock {
643 #address-cells = <2>; !! 555 compatible = "qcom,tcsr-mutex";
644 #size-cells = <2>; !! 556 syscon = <&tcsr_mutex_regs 0 0x1000>;
645 ranges; !! 557 #hwlock-cells = <1>;
646 <<
647 hyp_mem: memory@80000000 { <<
648 reg = <0x0 0x80000000 <<
649 no-map; <<
650 }; <<
651 <<
652 xbl_mem: memory@80600000 { <<
653 reg = <0x0 0x80600000 <<
654 no-map; <<
655 }; <<
656 <<
657 aop_mem: memory@80800000 { <<
658 reg = <0x0 0x80800000 <<
659 no-map; <<
660 }; <<
661 <<
662 aop_cmd_db_mem: memory@8082000 <<
663 reg = <0x0 0x80820000 <<
664 compatible = "qcom,cmd <<
665 no-map; <<
666 }; <<
667 <<
668 sec_apps_mem: memory@808ff000 <<
669 reg = <0x0 0x808ff000 <<
670 no-map; <<
671 }; <<
672 <<
673 smem_mem: memory@80900000 { <<
674 reg = <0x0 0x80900000 <<
675 no-map; <<
676 }; <<
677 <<
678 tz_mem: memory@80b00000 { <<
679 reg = <0x0 0x80b00000 <<
680 no-map; <<
681 }; <<
682 <<
683 ipa_fw_mem: memory@8b700000 { <<
684 reg = <0 0x8b700000 0 <<
685 no-map; <<
686 }; <<
687 <<
688 rmtfs_mem: memory@94600000 { <<
689 compatible = "qcom,rmt <<
690 reg = <0x0 0x94600000 <<
691 no-map; <<
692 <<
693 qcom,client-id = <1>; <<
694 qcom,vmid = <QCOM_SCM_ <<
695 }; <<
696 }; 558 };
697 559
698 smem { 560 smem {
699 compatible = "qcom,smem"; 561 compatible = "qcom,smem";
700 memory-region = <&smem_mem>; 562 memory-region = <&smem_mem>;
701 hwlocks = <&tcsr_mutex 3>; 563 hwlocks = <&tcsr_mutex 3>;
702 }; 564 };
703 565
704 smp2p-cdsp { 566 smp2p-cdsp {
705 compatible = "qcom,smp2p"; 567 compatible = "qcom,smp2p";
706 qcom,smem = <94>, <432>; 568 qcom,smem = <94>, <432>;
707 569
708 interrupts = <GIC_SPI 576 IRQ_ 570 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
709 571
710 mboxes = <&apss_shared 6>; 572 mboxes = <&apss_shared 6>;
711 573
712 qcom,local-pid = <0>; 574 qcom,local-pid = <0>;
713 qcom,remote-pid = <5>; 575 qcom,remote-pid = <5>;
714 576
715 cdsp_smp2p_out: master-kernel 577 cdsp_smp2p_out: master-kernel {
716 qcom,entry-name = "mas 578 qcom,entry-name = "master-kernel";
717 #qcom,smem-state-cells 579 #qcom,smem-state-cells = <1>;
718 }; 580 };
719 581
720 cdsp_smp2p_in: slave-kernel { 582 cdsp_smp2p_in: slave-kernel {
721 qcom,entry-name = "sla 583 qcom,entry-name = "slave-kernel";
722 584
723 interrupt-controller; 585 interrupt-controller;
724 #interrupt-cells = <2> 586 #interrupt-cells = <2>;
725 }; 587 };
726 }; 588 };
727 589
728 smp2p-lpass { 590 smp2p-lpass {
729 compatible = "qcom,smp2p"; 591 compatible = "qcom,smp2p";
730 qcom,smem = <443>, <429>; 592 qcom,smem = <443>, <429>;
731 593
732 interrupts = <GIC_SPI 158 IRQ_ 594 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
733 595
734 mboxes = <&apss_shared 10>; 596 mboxes = <&apss_shared 10>;
735 597
736 qcom,local-pid = <0>; 598 qcom,local-pid = <0>;
737 qcom,remote-pid = <2>; 599 qcom,remote-pid = <2>;
738 600
739 adsp_smp2p_out: master-kernel 601 adsp_smp2p_out: master-kernel {
740 qcom,entry-name = "mas 602 qcom,entry-name = "master-kernel";
741 #qcom,smem-state-cells 603 #qcom,smem-state-cells = <1>;
742 }; 604 };
743 605
744 adsp_smp2p_in: slave-kernel { 606 adsp_smp2p_in: slave-kernel {
745 qcom,entry-name = "sla 607 qcom,entry-name = "slave-kernel";
746 608
747 interrupt-controller; 609 interrupt-controller;
748 #interrupt-cells = <2> 610 #interrupt-cells = <2>;
749 }; 611 };
750 }; 612 };
751 613
752 smp2p-mpss { 614 smp2p-mpss {
753 compatible = "qcom,smp2p"; 615 compatible = "qcom,smp2p";
754 qcom,smem = <435>, <428>; 616 qcom,smem = <435>, <428>;
755 interrupts = <GIC_SPI 451 IRQ_ 617 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
756 mboxes = <&apss_shared 14>; 618 mboxes = <&apss_shared 14>;
757 qcom,local-pid = <0>; 619 qcom,local-pid = <0>;
758 qcom,remote-pid = <1>; 620 qcom,remote-pid = <1>;
759 621
760 modem_smp2p_out: master-kernel 622 modem_smp2p_out: master-kernel {
761 qcom,entry-name = "mas 623 qcom,entry-name = "master-kernel";
762 #qcom,smem-state-cells 624 #qcom,smem-state-cells = <1>;
763 }; 625 };
764 626
765 modem_smp2p_in: slave-kernel { 627 modem_smp2p_in: slave-kernel {
766 qcom,entry-name = "sla 628 qcom,entry-name = "slave-kernel";
767 interrupt-controller; 629 interrupt-controller;
768 #interrupt-cells = <2> 630 #interrupt-cells = <2>;
769 }; 631 };
770 632
771 ipa_smp2p_out: ipa-ap-to-modem 633 ipa_smp2p_out: ipa-ap-to-modem {
772 qcom,entry-name = "ipa 634 qcom,entry-name = "ipa";
773 #qcom,smem-state-cells 635 #qcom,smem-state-cells = <1>;
774 }; 636 };
775 637
776 ipa_smp2p_in: ipa-modem-to-ap 638 ipa_smp2p_in: ipa-modem-to-ap {
777 qcom,entry-name = "ipa 639 qcom,entry-name = "ipa";
778 interrupt-controller; 640 interrupt-controller;
779 #interrupt-cells = <2> 641 #interrupt-cells = <2>;
780 }; 642 };
781 }; 643 };
782 644
>> 645 psci {
>> 646 compatible = "arm,psci-1.0";
>> 647 method = "smc";
>> 648 };
>> 649
783 soc: soc@0 { 650 soc: soc@0 {
784 #address-cells = <2>; 651 #address-cells = <2>;
785 #size-cells = <2>; 652 #size-cells = <2>;
786 ranges = <0 0 0 0 0x10 0>; 653 ranges = <0 0 0 0 0x10 0>;
787 dma-ranges = <0 0 0 0 0x10 0>; 654 dma-ranges = <0 0 0 0 0x10 0>;
788 compatible = "simple-bus"; 655 compatible = "simple-bus";
789 656
790 gcc: clock-controller@100000 { 657 gcc: clock-controller@100000 {
791 compatible = "qcom,gcc 658 compatible = "qcom,gcc-sc7180";
792 reg = <0 0x00100000 0 659 reg = <0 0x00100000 0 0x1f0000>;
793 clocks = <&rpmhcc RPMH 660 clocks = <&rpmhcc RPMH_CXO_CLK>,
794 <&rpmhcc RPMH 661 <&rpmhcc RPMH_CXO_CLK_A>,
795 <&sleep_clk>; 662 <&sleep_clk>;
796 clock-names = "bi_tcxo 663 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
797 #clock-cells = <1>; 664 #clock-cells = <1>;
798 #reset-cells = <1>; 665 #reset-cells = <1>;
799 #power-domain-cells = 666 #power-domain-cells = <1>;
800 power-domains = <&rpmh <<
801 }; 667 };
802 668
803 qfprom: efuse@784000 { 669 qfprom: efuse@784000 {
804 compatible = "qcom,sc7 670 compatible = "qcom,sc7180-qfprom", "qcom,qfprom";
805 reg = <0 0x00784000 0 !! 671 reg = <0 0x00784000 0 0x8ff>,
806 <0 0x00780000 0 672 <0 0x00780000 0 0x7a0>,
807 <0 0x00782000 0 673 <0 0x00782000 0 0x100>,
808 <0 0x00786000 0 674 <0 0x00786000 0 0x1fff>;
809 675
810 clocks = <&gcc GCC_SEC 676 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>;
811 clock-names = "core"; 677 clock-names = "core";
812 #address-cells = <1>; 678 #address-cells = <1>;
813 #size-cells = <1>; 679 #size-cells = <1>;
814 680
815 qusb2p_hstx_trim: hstx 681 qusb2p_hstx_trim: hstx-trim-primary@25b {
816 reg = <0x25b 0 682 reg = <0x25b 0x1>;
817 bits = <1 3>; 683 bits = <1 3>;
818 }; 684 };
819 685
820 gpu_speed_bin: gpu-spe !! 686 gpu_speed_bin: gpu_speed_bin@1d2 {
821 reg = <0x1d2 0 687 reg = <0x1d2 0x2>;
822 bits = <5 8>; 688 bits = <5 8>;
823 }; 689 };
824 }; 690 };
825 691
826 sdhc_1: mmc@7c4000 { !! 692 sdhc_1: sdhci@7c4000 {
827 compatible = "qcom,sc7 693 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
828 reg = <0 0x007c4000 0 !! 694 reg = <0 0x7c4000 0 0x1000>,
829 <0 0x007c5000 !! 695 <0 0x07c5000 0 0x1000>;
830 reg-names = "hc", "cqh 696 reg-names = "hc", "cqhci";
831 697
832 iommus = <&apps_smmu 0 698 iommus = <&apps_smmu 0x60 0x0>;
833 interrupts = <GIC_SPI 699 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
834 <GIC_S 700 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
835 interrupt-names = "hc_ 701 interrupt-names = "hc_irq", "pwr_irq";
836 702
837 clocks = <&gcc GCC_SDC !! 703 clocks = <&gcc GCC_SDCC1_APPS_CLK>,
838 <&gcc GCC_SDC !! 704 <&gcc GCC_SDCC1_AHB_CLK>;
839 <&rpmhcc RPMH !! 705 clock-names = "core", "iface";
840 clock-names = "iface", <<
841 interconnects = <&aggr 706 interconnects = <&aggre1_noc MASTER_EMMC 0 &mc_virt SLAVE_EBI1 0>,
842 <&gem_ 707 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_EMMC_CFG 0>;
843 interconnect-names = " 708 interconnect-names = "sdhc-ddr","cpu-sdhc";
844 power-domains = <&rpmh 709 power-domains = <&rpmhpd SC7180_CX>;
845 operating-points-v2 = 710 operating-points-v2 = <&sdhc1_opp_table>;
846 711
847 bus-width = <8>; 712 bus-width = <8>;
848 non-removable; 713 non-removable;
849 supports-cqe; 714 supports-cqe;
850 715
851 mmc-ddr-1_8v; 716 mmc-ddr-1_8v;
852 mmc-hs200-1_8v; 717 mmc-hs200-1_8v;
853 mmc-hs400-1_8v; 718 mmc-hs400-1_8v;
854 mmc-hs400-enhanced-str 719 mmc-hs400-enhanced-strobe;
855 720
856 status = "disabled"; 721 status = "disabled";
857 722
858 sdhc1_opp_table: opp-t !! 723 sdhc1_opp_table: sdhc1-opp-table {
859 compatible = " 724 compatible = "operating-points-v2";
860 725
861 opp-100000000 726 opp-100000000 {
862 opp-hz 727 opp-hz = /bits/ 64 <100000000>;
863 requir 728 required-opps = <&rpmhpd_opp_low_svs>;
864 opp-pe !! 729 opp-peak-kBps = <100000 100000>;
865 opp-av !! 730 opp-avg-kBps = <100000 50000>;
866 }; 731 };
867 732
868 opp-384000000 733 opp-384000000 {
869 opp-hz 734 opp-hz = /bits/ 64 <384000000>;
870 requir !! 735 required-opps = <&rpmhpd_opp_svs_l1>;
871 opp-pe !! 736 opp-peak-kBps = <600000 900000>;
872 opp-av !! 737 opp-avg-kBps = <261438 300000>;
873 }; 738 };
874 }; 739 };
875 }; 740 };
876 741
>> 742 qup_opp_table: qup-opp-table {
>> 743 compatible = "operating-points-v2";
>> 744
>> 745 opp-75000000 {
>> 746 opp-hz = /bits/ 64 <75000000>;
>> 747 required-opps = <&rpmhpd_opp_low_svs>;
>> 748 };
>> 749
>> 750 opp-100000000 {
>> 751 opp-hz = /bits/ 64 <100000000>;
>> 752 required-opps = <&rpmhpd_opp_svs>;
>> 753 };
>> 754
>> 755 opp-128000000 {
>> 756 opp-hz = /bits/ 64 <128000000>;
>> 757 required-opps = <&rpmhpd_opp_nom>;
>> 758 };
>> 759 };
>> 760
877 qupv3_id_0: geniqup@8c0000 { 761 qupv3_id_0: geniqup@8c0000 {
878 compatible = "qcom,gen 762 compatible = "qcom,geni-se-qup";
879 reg = <0 0x008c0000 0 763 reg = <0 0x008c0000 0 0x6000>;
880 clock-names = "m-ahb", 764 clock-names = "m-ahb", "s-ahb";
881 clocks = <&gcc GCC_QUP 765 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
882 <&gcc GCC_QUP 766 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
883 #address-cells = <2>; 767 #address-cells = <2>;
884 #size-cells = <2>; 768 #size-cells = <2>;
885 ranges; 769 ranges;
886 iommus = <&apps_smmu 0 770 iommus = <&apps_smmu 0x43 0x0>;
>> 771 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>;
>> 772 interconnect-names = "qup-core";
887 status = "disabled"; 773 status = "disabled";
888 774
889 i2c0: i2c@880000 { 775 i2c0: i2c@880000 {
890 compatible = " 776 compatible = "qcom,geni-i2c";
891 reg = <0 0x008 777 reg = <0 0x00880000 0 0x4000>;
892 clock-names = 778 clock-names = "se";
893 clocks = <&gcc 779 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
894 pinctrl-names 780 pinctrl-names = "default";
895 pinctrl-0 = <& 781 pinctrl-0 = <&qup_i2c0_default>;
896 interrupts = < 782 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
897 #address-cells 783 #address-cells = <1>;
898 #size-cells = 784 #size-cells = <0>;
899 interconnects 785 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
900 786 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
901 787 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
902 interconnect-n 788 interconnect-names = "qup-core", "qup-config",
903 789 "qup-memory";
904 power-domains <<
905 required-opps <<
906 status = "disa 790 status = "disabled";
907 }; 791 };
908 792
909 spi0: spi@880000 { 793 spi0: spi@880000 {
910 compatible = " 794 compatible = "qcom,geni-spi";
911 reg = <0 0x008 795 reg = <0 0x00880000 0 0x4000>;
912 clock-names = 796 clock-names = "se";
913 clocks = <&gcc 797 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
914 pinctrl-names 798 pinctrl-names = "default";
915 pinctrl-0 = <& !! 799 pinctrl-0 = <&qup_spi0_default>;
916 interrupts = < 800 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
917 #address-cells 801 #address-cells = <1>;
918 #size-cells = 802 #size-cells = <0>;
919 power-domains 803 power-domains = <&rpmhpd SC7180_CX>;
920 operating-poin 804 operating-points-v2 = <&qup_opp_table>;
921 interconnects 805 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
922 806 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
923 interconnect-n 807 interconnect-names = "qup-core", "qup-config";
924 status = "disa 808 status = "disabled";
925 }; 809 };
926 810
927 uart0: serial@880000 { 811 uart0: serial@880000 {
928 compatible = " 812 compatible = "qcom,geni-uart";
929 reg = <0 0x008 813 reg = <0 0x00880000 0 0x4000>;
930 clock-names = 814 clock-names = "se";
931 clocks = <&gcc 815 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
932 pinctrl-names 816 pinctrl-names = "default";
933 pinctrl-0 = <& 817 pinctrl-0 = <&qup_uart0_default>;
934 interrupts = < 818 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
935 power-domains 819 power-domains = <&rpmhpd SC7180_CX>;
936 operating-poin 820 operating-points-v2 = <&qup_opp_table>;
937 interconnects 821 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
938 822 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
939 interconnect-n 823 interconnect-names = "qup-core", "qup-config";
940 status = "disa 824 status = "disabled";
941 }; 825 };
942 826
943 i2c1: i2c@884000 { 827 i2c1: i2c@884000 {
944 compatible = " 828 compatible = "qcom,geni-i2c";
945 reg = <0 0x008 829 reg = <0 0x00884000 0 0x4000>;
946 clock-names = 830 clock-names = "se";
947 clocks = <&gcc 831 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
948 pinctrl-names 832 pinctrl-names = "default";
949 pinctrl-0 = <& 833 pinctrl-0 = <&qup_i2c1_default>;
950 interrupts = < 834 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
951 #address-cells 835 #address-cells = <1>;
952 #size-cells = 836 #size-cells = <0>;
953 interconnects 837 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
954 838 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
955 839 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
956 interconnect-n 840 interconnect-names = "qup-core", "qup-config",
957 841 "qup-memory";
958 power-domains <<
959 required-opps <<
960 status = "disa 842 status = "disabled";
961 }; 843 };
962 844
963 spi1: spi@884000 { 845 spi1: spi@884000 {
964 compatible = " 846 compatible = "qcom,geni-spi";
965 reg = <0 0x008 847 reg = <0 0x00884000 0 0x4000>;
966 clock-names = 848 clock-names = "se";
967 clocks = <&gcc 849 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
968 pinctrl-names 850 pinctrl-names = "default";
969 pinctrl-0 = <& !! 851 pinctrl-0 = <&qup_spi1_default>;
970 interrupts = < 852 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
971 #address-cells 853 #address-cells = <1>;
972 #size-cells = 854 #size-cells = <0>;
973 power-domains 855 power-domains = <&rpmhpd SC7180_CX>;
974 operating-poin 856 operating-points-v2 = <&qup_opp_table>;
975 interconnects 857 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
976 858 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
977 interconnect-n 859 interconnect-names = "qup-core", "qup-config";
978 status = "disa 860 status = "disabled";
979 }; 861 };
980 862
981 uart1: serial@884000 { 863 uart1: serial@884000 {
982 compatible = " 864 compatible = "qcom,geni-uart";
983 reg = <0 0x008 865 reg = <0 0x00884000 0 0x4000>;
984 clock-names = 866 clock-names = "se";
985 clocks = <&gcc 867 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
986 pinctrl-names 868 pinctrl-names = "default";
987 pinctrl-0 = <& 869 pinctrl-0 = <&qup_uart1_default>;
988 interrupts = < 870 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
989 power-domains 871 power-domains = <&rpmhpd SC7180_CX>;
990 operating-poin 872 operating-points-v2 = <&qup_opp_table>;
991 interconnects 873 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
992 874 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
993 interconnect-n 875 interconnect-names = "qup-core", "qup-config";
994 status = "disa 876 status = "disabled";
995 }; 877 };
996 878
997 i2c2: i2c@888000 { 879 i2c2: i2c@888000 {
998 compatible = " 880 compatible = "qcom,geni-i2c";
999 reg = <0 0x008 881 reg = <0 0x00888000 0 0x4000>;
1000 clock-names = 882 clock-names = "se";
1001 clocks = <&gc 883 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1002 pinctrl-names 884 pinctrl-names = "default";
1003 pinctrl-0 = < 885 pinctrl-0 = <&qup_i2c2_default>;
1004 interrupts = 886 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1005 #address-cell 887 #address-cells = <1>;
1006 #size-cells = 888 #size-cells = <0>;
1007 interconnects 889 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1008 890 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1009 891 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1010 interconnect- 892 interconnect-names = "qup-core", "qup-config",
1011 893 "qup-memory";
1012 power-domains <<
1013 required-opps <<
1014 status = "dis 894 status = "disabled";
1015 }; 895 };
1016 896
1017 uart2: serial@888000 897 uart2: serial@888000 {
1018 compatible = 898 compatible = "qcom,geni-uart";
1019 reg = <0 0x00 899 reg = <0 0x00888000 0 0x4000>;
1020 clock-names = 900 clock-names = "se";
1021 clocks = <&gc 901 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1022 pinctrl-names 902 pinctrl-names = "default";
1023 pinctrl-0 = < 903 pinctrl-0 = <&qup_uart2_default>;
1024 interrupts = 904 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1025 power-domains 905 power-domains = <&rpmhpd SC7180_CX>;
1026 operating-poi 906 operating-points-v2 = <&qup_opp_table>;
1027 interconnects 907 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1028 908 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1029 interconnect- 909 interconnect-names = "qup-core", "qup-config";
1030 status = "dis 910 status = "disabled";
1031 }; 911 };
1032 912
1033 i2c3: i2c@88c000 { 913 i2c3: i2c@88c000 {
1034 compatible = 914 compatible = "qcom,geni-i2c";
1035 reg = <0 0x00 915 reg = <0 0x0088c000 0 0x4000>;
1036 clock-names = 916 clock-names = "se";
1037 clocks = <&gc 917 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1038 pinctrl-names 918 pinctrl-names = "default";
1039 pinctrl-0 = < 919 pinctrl-0 = <&qup_i2c3_default>;
1040 interrupts = 920 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1041 #address-cell 921 #address-cells = <1>;
1042 #size-cells = 922 #size-cells = <0>;
1043 interconnects 923 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1044 924 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1045 925 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1046 interconnect- 926 interconnect-names = "qup-core", "qup-config",
1047 927 "qup-memory";
1048 power-domains <<
1049 required-opps <<
1050 status = "dis 928 status = "disabled";
1051 }; 929 };
1052 930
1053 spi3: spi@88c000 { 931 spi3: spi@88c000 {
1054 compatible = 932 compatible = "qcom,geni-spi";
1055 reg = <0 0x00 933 reg = <0 0x0088c000 0 0x4000>;
1056 clock-names = 934 clock-names = "se";
1057 clocks = <&gc 935 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1058 pinctrl-names 936 pinctrl-names = "default";
1059 pinctrl-0 = < !! 937 pinctrl-0 = <&qup_spi3_default>;
1060 interrupts = 938 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1061 #address-cell 939 #address-cells = <1>;
1062 #size-cells = 940 #size-cells = <0>;
1063 power-domains 941 power-domains = <&rpmhpd SC7180_CX>;
1064 operating-poi 942 operating-points-v2 = <&qup_opp_table>;
1065 interconnects 943 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1066 944 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1067 interconnect- 945 interconnect-names = "qup-core", "qup-config";
1068 status = "dis 946 status = "disabled";
1069 }; 947 };
1070 948
1071 uart3: serial@88c000 949 uart3: serial@88c000 {
1072 compatible = 950 compatible = "qcom,geni-uart";
1073 reg = <0 0x00 951 reg = <0 0x0088c000 0 0x4000>;
1074 clock-names = 952 clock-names = "se";
1075 clocks = <&gc 953 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1076 pinctrl-names 954 pinctrl-names = "default";
1077 pinctrl-0 = < 955 pinctrl-0 = <&qup_uart3_default>;
1078 interrupts = 956 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1079 power-domains 957 power-domains = <&rpmhpd SC7180_CX>;
1080 operating-poi 958 operating-points-v2 = <&qup_opp_table>;
1081 interconnects 959 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1082 960 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1083 interconnect- 961 interconnect-names = "qup-core", "qup-config";
1084 status = "dis 962 status = "disabled";
1085 }; 963 };
1086 964
1087 i2c4: i2c@890000 { 965 i2c4: i2c@890000 {
1088 compatible = 966 compatible = "qcom,geni-i2c";
1089 reg = <0 0x00 967 reg = <0 0x00890000 0 0x4000>;
1090 clock-names = 968 clock-names = "se";
1091 clocks = <&gc 969 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1092 pinctrl-names 970 pinctrl-names = "default";
1093 pinctrl-0 = < 971 pinctrl-0 = <&qup_i2c4_default>;
1094 interrupts = 972 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1095 #address-cell 973 #address-cells = <1>;
1096 #size-cells = 974 #size-cells = <0>;
1097 interconnects 975 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1098 976 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1099 977 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1100 interconnect- 978 interconnect-names = "qup-core", "qup-config",
1101 979 "qup-memory";
1102 power-domains <<
1103 required-opps <<
1104 status = "dis 980 status = "disabled";
1105 }; 981 };
1106 982
1107 uart4: serial@890000 983 uart4: serial@890000 {
1108 compatible = 984 compatible = "qcom,geni-uart";
1109 reg = <0 0x00 985 reg = <0 0x00890000 0 0x4000>;
1110 clock-names = 986 clock-names = "se";
1111 clocks = <&gc 987 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1112 pinctrl-names 988 pinctrl-names = "default";
1113 pinctrl-0 = < 989 pinctrl-0 = <&qup_uart4_default>;
1114 interrupts = 990 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1115 power-domains 991 power-domains = <&rpmhpd SC7180_CX>;
1116 operating-poi 992 operating-points-v2 = <&qup_opp_table>;
1117 interconnects 993 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1118 994 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1119 interconnect- 995 interconnect-names = "qup-core", "qup-config";
1120 status = "dis 996 status = "disabled";
1121 }; 997 };
1122 998
1123 i2c5: i2c@894000 { 999 i2c5: i2c@894000 {
1124 compatible = 1000 compatible = "qcom,geni-i2c";
1125 reg = <0 0x00 1001 reg = <0 0x00894000 0 0x4000>;
1126 clock-names = 1002 clock-names = "se";
1127 clocks = <&gc 1003 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1128 pinctrl-names 1004 pinctrl-names = "default";
1129 pinctrl-0 = < 1005 pinctrl-0 = <&qup_i2c5_default>;
1130 interrupts = 1006 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1131 #address-cell 1007 #address-cells = <1>;
1132 #size-cells = 1008 #size-cells = <0>;
1133 interconnects 1009 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1134 1010 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1135 1011 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1136 interconnect- 1012 interconnect-names = "qup-core", "qup-config",
1137 1013 "qup-memory";
1138 power-domains <<
1139 required-opps <<
1140 status = "dis 1014 status = "disabled";
1141 }; 1015 };
1142 1016
1143 spi5: spi@894000 { 1017 spi5: spi@894000 {
1144 compatible = 1018 compatible = "qcom,geni-spi";
1145 reg = <0 0x00 1019 reg = <0 0x00894000 0 0x4000>;
1146 clock-names = 1020 clock-names = "se";
1147 clocks = <&gc 1021 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1148 pinctrl-names 1022 pinctrl-names = "default";
1149 pinctrl-0 = < !! 1023 pinctrl-0 = <&qup_spi5_default>;
1150 interrupts = 1024 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1151 #address-cell 1025 #address-cells = <1>;
1152 #size-cells = 1026 #size-cells = <0>;
1153 power-domains 1027 power-domains = <&rpmhpd SC7180_CX>;
1154 operating-poi 1028 operating-points-v2 = <&qup_opp_table>;
1155 interconnects 1029 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1156 1030 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1157 interconnect- 1031 interconnect-names = "qup-core", "qup-config";
1158 status = "dis 1032 status = "disabled";
1159 }; 1033 };
1160 1034
1161 uart5: serial@894000 1035 uart5: serial@894000 {
1162 compatible = 1036 compatible = "qcom,geni-uart";
1163 reg = <0 0x00 1037 reg = <0 0x00894000 0 0x4000>;
1164 clock-names = 1038 clock-names = "se";
1165 clocks = <&gc 1039 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1166 pinctrl-names 1040 pinctrl-names = "default";
1167 pinctrl-0 = < 1041 pinctrl-0 = <&qup_uart5_default>;
1168 interrupts = 1042 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1169 power-domains 1043 power-domains = <&rpmhpd SC7180_CX>;
1170 operating-poi 1044 operating-points-v2 = <&qup_opp_table>;
1171 interconnects 1045 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1172 1046 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1173 interconnect- 1047 interconnect-names = "qup-core", "qup-config";
1174 status = "dis 1048 status = "disabled";
1175 }; 1049 };
1176 }; 1050 };
1177 1051
1178 qupv3_id_1: geniqup@ac0000 { 1052 qupv3_id_1: geniqup@ac0000 {
1179 compatible = "qcom,ge 1053 compatible = "qcom,geni-se-qup";
1180 reg = <0 0x00ac0000 0 1054 reg = <0 0x00ac0000 0 0x6000>;
1181 clock-names = "m-ahb" 1055 clock-names = "m-ahb", "s-ahb";
1182 clocks = <&gcc GCC_QU 1056 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1183 <&gcc GCC_QU 1057 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1184 #address-cells = <2>; 1058 #address-cells = <2>;
1185 #size-cells = <2>; 1059 #size-cells = <2>;
1186 ranges; 1060 ranges;
1187 iommus = <&apps_smmu 1061 iommus = <&apps_smmu 0x4c3 0x0>;
>> 1062 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>;
>> 1063 interconnect-names = "qup-core";
1188 status = "disabled"; 1064 status = "disabled";
1189 1065
1190 i2c6: i2c@a80000 { 1066 i2c6: i2c@a80000 {
1191 compatible = 1067 compatible = "qcom,geni-i2c";
1192 reg = <0 0x00 1068 reg = <0 0x00a80000 0 0x4000>;
1193 clock-names = 1069 clock-names = "se";
1194 clocks = <&gc 1070 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1195 pinctrl-names 1071 pinctrl-names = "default";
1196 pinctrl-0 = < 1072 pinctrl-0 = <&qup_i2c6_default>;
1197 interrupts = 1073 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1198 #address-cell 1074 #address-cells = <1>;
1199 #size-cells = 1075 #size-cells = <0>;
1200 interconnects 1076 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1201 1077 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1202 1078 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1203 interconnect- 1079 interconnect-names = "qup-core", "qup-config",
1204 1080 "qup-memory";
1205 power-domains <<
1206 required-opps <<
1207 status = "dis 1081 status = "disabled";
1208 }; 1082 };
1209 1083
1210 spi6: spi@a80000 { 1084 spi6: spi@a80000 {
1211 compatible = 1085 compatible = "qcom,geni-spi";
1212 reg = <0 0x00 1086 reg = <0 0x00a80000 0 0x4000>;
1213 clock-names = 1087 clock-names = "se";
1214 clocks = <&gc 1088 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1215 pinctrl-names 1089 pinctrl-names = "default";
1216 pinctrl-0 = < !! 1090 pinctrl-0 = <&qup_spi6_default>;
1217 interrupts = 1091 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1218 #address-cell 1092 #address-cells = <1>;
1219 #size-cells = 1093 #size-cells = <0>;
1220 power-domains 1094 power-domains = <&rpmhpd SC7180_CX>;
1221 operating-poi 1095 operating-points-v2 = <&qup_opp_table>;
1222 interconnects 1096 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1223 1097 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1224 interconnect- 1098 interconnect-names = "qup-core", "qup-config";
1225 status = "dis 1099 status = "disabled";
1226 }; 1100 };
1227 1101
1228 uart6: serial@a80000 1102 uart6: serial@a80000 {
1229 compatible = 1103 compatible = "qcom,geni-uart";
1230 reg = <0 0x00 1104 reg = <0 0x00a80000 0 0x4000>;
1231 clock-names = 1105 clock-names = "se";
1232 clocks = <&gc 1106 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1233 pinctrl-names 1107 pinctrl-names = "default";
1234 pinctrl-0 = < 1108 pinctrl-0 = <&qup_uart6_default>;
1235 interrupts = 1109 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1236 power-domains 1110 power-domains = <&rpmhpd SC7180_CX>;
1237 operating-poi 1111 operating-points-v2 = <&qup_opp_table>;
1238 interconnects 1112 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1239 1113 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1240 interconnect- 1114 interconnect-names = "qup-core", "qup-config";
1241 status = "dis 1115 status = "disabled";
1242 }; 1116 };
1243 1117
1244 i2c7: i2c@a84000 { 1118 i2c7: i2c@a84000 {
1245 compatible = 1119 compatible = "qcom,geni-i2c";
1246 reg = <0 0x00 1120 reg = <0 0x00a84000 0 0x4000>;
1247 clock-names = 1121 clock-names = "se";
1248 clocks = <&gc 1122 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1249 pinctrl-names 1123 pinctrl-names = "default";
1250 pinctrl-0 = < 1124 pinctrl-0 = <&qup_i2c7_default>;
1251 interrupts = 1125 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1252 #address-cell 1126 #address-cells = <1>;
1253 #size-cells = 1127 #size-cells = <0>;
1254 interconnects 1128 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1255 1129 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1256 1130 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1257 interconnect- 1131 interconnect-names = "qup-core", "qup-config",
1258 1132 "qup-memory";
1259 power-domains <<
1260 required-opps <<
1261 status = "dis 1133 status = "disabled";
1262 }; 1134 };
1263 1135
1264 uart7: serial@a84000 1136 uart7: serial@a84000 {
1265 compatible = 1137 compatible = "qcom,geni-uart";
1266 reg = <0 0x00 1138 reg = <0 0x00a84000 0 0x4000>;
1267 clock-names = 1139 clock-names = "se";
1268 clocks = <&gc 1140 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1269 pinctrl-names 1141 pinctrl-names = "default";
1270 pinctrl-0 = < 1142 pinctrl-0 = <&qup_uart7_default>;
1271 interrupts = 1143 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1272 power-domains 1144 power-domains = <&rpmhpd SC7180_CX>;
1273 operating-poi 1145 operating-points-v2 = <&qup_opp_table>;
1274 interconnects 1146 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1275 1147 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1276 interconnect- 1148 interconnect-names = "qup-core", "qup-config";
1277 status = "dis 1149 status = "disabled";
1278 }; 1150 };
1279 1151
1280 i2c8: i2c@a88000 { 1152 i2c8: i2c@a88000 {
1281 compatible = 1153 compatible = "qcom,geni-i2c";
1282 reg = <0 0x00 1154 reg = <0 0x00a88000 0 0x4000>;
1283 clock-names = 1155 clock-names = "se";
1284 clocks = <&gc 1156 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1285 pinctrl-names 1157 pinctrl-names = "default";
1286 pinctrl-0 = < 1158 pinctrl-0 = <&qup_i2c8_default>;
1287 interrupts = 1159 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1288 #address-cell 1160 #address-cells = <1>;
1289 #size-cells = 1161 #size-cells = <0>;
1290 interconnects 1162 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1291 1163 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1292 1164 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1293 interconnect- 1165 interconnect-names = "qup-core", "qup-config",
1294 1166 "qup-memory";
1295 power-domains <<
1296 required-opps <<
1297 status = "dis 1167 status = "disabled";
1298 }; 1168 };
1299 1169
1300 spi8: spi@a88000 { 1170 spi8: spi@a88000 {
1301 compatible = 1171 compatible = "qcom,geni-spi";
1302 reg = <0 0x00 1172 reg = <0 0x00a88000 0 0x4000>;
1303 clock-names = 1173 clock-names = "se";
1304 clocks = <&gc 1174 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1305 pinctrl-names 1175 pinctrl-names = "default";
1306 pinctrl-0 = < !! 1176 pinctrl-0 = <&qup_spi8_default>;
1307 interrupts = 1177 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1308 #address-cell 1178 #address-cells = <1>;
1309 #size-cells = 1179 #size-cells = <0>;
1310 power-domains 1180 power-domains = <&rpmhpd SC7180_CX>;
1311 operating-poi 1181 operating-points-v2 = <&qup_opp_table>;
1312 interconnects 1182 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1313 1183 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1314 interconnect- 1184 interconnect-names = "qup-core", "qup-config";
1315 status = "dis 1185 status = "disabled";
1316 }; 1186 };
1317 1187
1318 uart8: serial@a88000 1188 uart8: serial@a88000 {
1319 compatible = 1189 compatible = "qcom,geni-debug-uart";
1320 reg = <0 0x00 1190 reg = <0 0x00a88000 0 0x4000>;
1321 clock-names = 1191 clock-names = "se";
1322 clocks = <&gc 1192 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1323 pinctrl-names 1193 pinctrl-names = "default";
1324 pinctrl-0 = < 1194 pinctrl-0 = <&qup_uart8_default>;
1325 interrupts = 1195 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1326 power-domains 1196 power-domains = <&rpmhpd SC7180_CX>;
1327 operating-poi 1197 operating-points-v2 = <&qup_opp_table>;
1328 interconnects 1198 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1329 1199 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1330 interconnect- 1200 interconnect-names = "qup-core", "qup-config";
1331 status = "dis 1201 status = "disabled";
1332 }; 1202 };
1333 1203
1334 i2c9: i2c@a8c000 { 1204 i2c9: i2c@a8c000 {
1335 compatible = 1205 compatible = "qcom,geni-i2c";
1336 reg = <0 0x00 1206 reg = <0 0x00a8c000 0 0x4000>;
1337 clock-names = 1207 clock-names = "se";
1338 clocks = <&gc 1208 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1339 pinctrl-names 1209 pinctrl-names = "default";
1340 pinctrl-0 = < 1210 pinctrl-0 = <&qup_i2c9_default>;
1341 interrupts = 1211 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1342 #address-cell 1212 #address-cells = <1>;
1343 #size-cells = 1213 #size-cells = <0>;
1344 interconnects 1214 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1345 1215 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1346 1216 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1347 interconnect- 1217 interconnect-names = "qup-core", "qup-config",
1348 1218 "qup-memory";
1349 power-domains <<
1350 required-opps <<
1351 status = "dis 1219 status = "disabled";
1352 }; 1220 };
1353 1221
1354 uart9: serial@a8c000 1222 uart9: serial@a8c000 {
1355 compatible = 1223 compatible = "qcom,geni-uart";
1356 reg = <0 0x00 1224 reg = <0 0x00a8c000 0 0x4000>;
1357 clock-names = 1225 clock-names = "se";
1358 clocks = <&gc 1226 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1359 pinctrl-names 1227 pinctrl-names = "default";
1360 pinctrl-0 = < 1228 pinctrl-0 = <&qup_uart9_default>;
1361 interrupts = 1229 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1362 power-domains 1230 power-domains = <&rpmhpd SC7180_CX>;
1363 operating-poi 1231 operating-points-v2 = <&qup_opp_table>;
1364 interconnects 1232 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1365 1233 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1366 interconnect- 1234 interconnect-names = "qup-core", "qup-config";
1367 status = "dis 1235 status = "disabled";
1368 }; 1236 };
1369 1237
1370 i2c10: i2c@a90000 { 1238 i2c10: i2c@a90000 {
1371 compatible = 1239 compatible = "qcom,geni-i2c";
1372 reg = <0 0x00 1240 reg = <0 0x00a90000 0 0x4000>;
1373 clock-names = 1241 clock-names = "se";
1374 clocks = <&gc 1242 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1375 pinctrl-names 1243 pinctrl-names = "default";
1376 pinctrl-0 = < 1244 pinctrl-0 = <&qup_i2c10_default>;
1377 interrupts = 1245 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1378 #address-cell 1246 #address-cells = <1>;
1379 #size-cells = 1247 #size-cells = <0>;
1380 interconnects 1248 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1381 1249 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1382 1250 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1383 interconnect- 1251 interconnect-names = "qup-core", "qup-config",
1384 1252 "qup-memory";
1385 power-domains <<
1386 required-opps <<
1387 status = "dis 1253 status = "disabled";
1388 }; 1254 };
1389 1255
1390 spi10: spi@a90000 { 1256 spi10: spi@a90000 {
1391 compatible = 1257 compatible = "qcom,geni-spi";
1392 reg = <0 0x00 1258 reg = <0 0x00a90000 0 0x4000>;
1393 clock-names = 1259 clock-names = "se";
1394 clocks = <&gc 1260 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1395 pinctrl-names 1261 pinctrl-names = "default";
1396 pinctrl-0 = < !! 1262 pinctrl-0 = <&qup_spi10_default>;
1397 interrupts = 1263 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1398 #address-cell 1264 #address-cells = <1>;
1399 #size-cells = 1265 #size-cells = <0>;
1400 power-domains 1266 power-domains = <&rpmhpd SC7180_CX>;
1401 operating-poi 1267 operating-points-v2 = <&qup_opp_table>;
1402 interconnects 1268 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1403 1269 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1404 interconnect- 1270 interconnect-names = "qup-core", "qup-config";
1405 status = "dis 1271 status = "disabled";
1406 }; 1272 };
1407 1273
1408 uart10: serial@a90000 1274 uart10: serial@a90000 {
1409 compatible = 1275 compatible = "qcom,geni-uart";
1410 reg = <0 0x00 1276 reg = <0 0x00a90000 0 0x4000>;
1411 clock-names = 1277 clock-names = "se";
1412 clocks = <&gc 1278 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1413 pinctrl-names 1279 pinctrl-names = "default";
1414 pinctrl-0 = < 1280 pinctrl-0 = <&qup_uart10_default>;
1415 interrupts = 1281 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1416 power-domains 1282 power-domains = <&rpmhpd SC7180_CX>;
1417 operating-poi 1283 operating-points-v2 = <&qup_opp_table>;
1418 interconnects 1284 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1419 1285 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1420 interconnect- 1286 interconnect-names = "qup-core", "qup-config";
1421 status = "dis 1287 status = "disabled";
1422 }; 1288 };
1423 1289
1424 i2c11: i2c@a94000 { 1290 i2c11: i2c@a94000 {
1425 compatible = 1291 compatible = "qcom,geni-i2c";
1426 reg = <0 0x00 1292 reg = <0 0x00a94000 0 0x4000>;
1427 clock-names = 1293 clock-names = "se";
1428 clocks = <&gc 1294 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1429 pinctrl-names 1295 pinctrl-names = "default";
1430 pinctrl-0 = < 1296 pinctrl-0 = <&qup_i2c11_default>;
1431 interrupts = 1297 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1432 #address-cell 1298 #address-cells = <1>;
1433 #size-cells = 1299 #size-cells = <0>;
1434 interconnects 1300 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1435 1301 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1436 1302 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1437 interconnect- 1303 interconnect-names = "qup-core", "qup-config",
1438 1304 "qup-memory";
1439 power-domains <<
1440 required-opps <<
1441 status = "dis 1305 status = "disabled";
1442 }; 1306 };
1443 1307
1444 spi11: spi@a94000 { 1308 spi11: spi@a94000 {
1445 compatible = 1309 compatible = "qcom,geni-spi";
1446 reg = <0 0x00 1310 reg = <0 0x00a94000 0 0x4000>;
1447 clock-names = 1311 clock-names = "se";
1448 clocks = <&gc 1312 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1449 pinctrl-names 1313 pinctrl-names = "default";
1450 pinctrl-0 = < !! 1314 pinctrl-0 = <&qup_spi11_default>;
1451 interrupts = 1315 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1452 #address-cell 1316 #address-cells = <1>;
1453 #size-cells = 1317 #size-cells = <0>;
1454 power-domains 1318 power-domains = <&rpmhpd SC7180_CX>;
1455 operating-poi 1319 operating-points-v2 = <&qup_opp_table>;
1456 interconnects 1320 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1457 1321 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1458 interconnect- 1322 interconnect-names = "qup-core", "qup-config";
1459 status = "dis 1323 status = "disabled";
1460 }; 1324 };
1461 1325
1462 uart11: serial@a94000 1326 uart11: serial@a94000 {
1463 compatible = 1327 compatible = "qcom,geni-uart";
1464 reg = <0 0x00 1328 reg = <0 0x00a94000 0 0x4000>;
1465 clock-names = 1329 clock-names = "se";
1466 clocks = <&gc 1330 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1467 pinctrl-names 1331 pinctrl-names = "default";
1468 pinctrl-0 = < 1332 pinctrl-0 = <&qup_uart11_default>;
1469 interrupts = 1333 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1470 power-domains 1334 power-domains = <&rpmhpd SC7180_CX>;
1471 operating-poi 1335 operating-points-v2 = <&qup_opp_table>;
1472 interconnects 1336 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1473 1337 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1474 interconnect- 1338 interconnect-names = "qup-core", "qup-config";
1475 status = "dis 1339 status = "disabled";
1476 }; 1340 };
1477 }; 1341 };
1478 1342
1479 config_noc: interconnect@1500 1343 config_noc: interconnect@1500000 {
1480 compatible = "qcom,sc 1344 compatible = "qcom,sc7180-config-noc";
1481 reg = <0 0x01500000 0 1345 reg = <0 0x01500000 0 0x28000>;
1482 #interconnect-cells = 1346 #interconnect-cells = <2>;
1483 qcom,bcm-voters = <&a 1347 qcom,bcm-voters = <&apps_bcm_voter>;
1484 }; 1348 };
1485 1349
1486 system_noc: interconnect@1620 1350 system_noc: interconnect@1620000 {
1487 compatible = "qcom,sc 1351 compatible = "qcom,sc7180-system-noc";
1488 reg = <0 0x01620000 0 1352 reg = <0 0x01620000 0 0x17080>;
1489 #interconnect-cells = 1353 #interconnect-cells = <2>;
1490 qcom,bcm-voters = <&a 1354 qcom,bcm-voters = <&apps_bcm_voter>;
1491 }; 1355 };
1492 1356
1493 mc_virt: interconnect@1638000 1357 mc_virt: interconnect@1638000 {
1494 compatible = "qcom,sc 1358 compatible = "qcom,sc7180-mc-virt";
1495 reg = <0 0x01638000 0 1359 reg = <0 0x01638000 0 0x1000>;
1496 #interconnect-cells = 1360 #interconnect-cells = <2>;
1497 qcom,bcm-voters = <&a 1361 qcom,bcm-voters = <&apps_bcm_voter>;
1498 }; 1362 };
1499 1363
1500 qup_virt: interconnect@165000 1364 qup_virt: interconnect@1650000 {
1501 compatible = "qcom,sc 1365 compatible = "qcom,sc7180-qup-virt";
1502 reg = <0 0x01650000 0 1366 reg = <0 0x01650000 0 0x1000>;
1503 #interconnect-cells = 1367 #interconnect-cells = <2>;
1504 qcom,bcm-voters = <&a 1368 qcom,bcm-voters = <&apps_bcm_voter>;
1505 }; 1369 };
1506 1370
1507 aggre1_noc: interconnect@16e0 1371 aggre1_noc: interconnect@16e0000 {
1508 compatible = "qcom,sc 1372 compatible = "qcom,sc7180-aggre1-noc";
1509 reg = <0 0x016e0000 0 1373 reg = <0 0x016e0000 0 0x15080>;
1510 #interconnect-cells = 1374 #interconnect-cells = <2>;
1511 qcom,bcm-voters = <&a 1375 qcom,bcm-voters = <&apps_bcm_voter>;
1512 }; 1376 };
1513 1377
1514 aggre2_noc: interconnect@1705 1378 aggre2_noc: interconnect@1705000 {
1515 compatible = "qcom,sc 1379 compatible = "qcom,sc7180-aggre2-noc";
1516 reg = <0 0x01705000 0 1380 reg = <0 0x01705000 0 0x9000>;
1517 #interconnect-cells = 1381 #interconnect-cells = <2>;
1518 qcom,bcm-voters = <&a 1382 qcom,bcm-voters = <&apps_bcm_voter>;
1519 }; 1383 };
1520 1384
1521 compute_noc: interconnect@170 1385 compute_noc: interconnect@170e000 {
1522 compatible = "qcom,sc 1386 compatible = "qcom,sc7180-compute-noc";
1523 reg = <0 0x0170e000 0 1387 reg = <0 0x0170e000 0 0x6000>;
1524 #interconnect-cells = 1388 #interconnect-cells = <2>;
1525 qcom,bcm-voters = <&a 1389 qcom,bcm-voters = <&apps_bcm_voter>;
1526 }; 1390 };
1527 1391
1528 mmss_noc: interconnect@174000 1392 mmss_noc: interconnect@1740000 {
1529 compatible = "qcom,sc 1393 compatible = "qcom,sc7180-mmss-noc";
1530 reg = <0 0x01740000 0 1394 reg = <0 0x01740000 0 0x1c100>;
1531 #interconnect-cells = 1395 #interconnect-cells = <2>;
1532 qcom,bcm-voters = <&a 1396 qcom,bcm-voters = <&apps_bcm_voter>;
1533 }; 1397 };
1534 1398
1535 ufs_mem_hc: ufshc@1d84000 { !! 1399 ipa_virt: interconnect@1e00000 {
1536 compatible = "qcom,sc !! 1400 compatible = "qcom,sc7180-ipa-virt";
1537 "jedec,u !! 1401 reg = <0 0x01e00000 0 0x1000>;
1538 reg = <0 0x01d84000 0 !! 1402 #interconnect-cells = <2>;
1539 interrupts = <GIC_SPI !! 1403 qcom,bcm-voters = <&apps_bcm_voter>;
1540 phys = <&ufs_mem_phy> <<
1541 phy-names = "ufsphy"; <<
1542 lanes-per-direction = <<
1543 #reset-cells = <1>; <<
1544 resets = <&gcc GCC_UF <<
1545 reset-names = "rst"; <<
1546 <<
1547 power-domains = <&gcc <<
1548 <<
1549 iommus = <&apps_smmu <<
1550 <<
1551 clock-names = "core_c <<
1552 "bus_ag <<
1553 "iface_ <<
1554 "core_c <<
1555 "ref_cl <<
1556 "tx_lan <<
1557 "rx_lan <<
1558 clocks = <&gcc GCC_UF <<
1559 <&gcc GCC_AG <<
1560 <&gcc GCC_UF <<
1561 <&gcc GCC_UF <<
1562 <&rpmhcc RPM <<
1563 <&gcc GCC_UF <<
1564 <&gcc GCC_UF <<
1565 freq-table-hz = <5000 <<
1566 <0 0> <<
1567 <0 0> <<
1568 <3750 <<
1569 <0 0> <<
1570 <0 0> <<
1571 <0 0> <<
1572 <<
1573 interconnects = <&agg <<
1574 &mc_ <<
1575 <&gem <<
1576 &con <<
1577 interconnect-names = <<
1578 <<
1579 qcom,ice = <&ice>; <<
1580 <<
1581 status = "disabled"; <<
1582 }; <<
1583 <<
1584 ufs_mem_phy: phy@1d87000 { <<
1585 compatible = "qcom,sc <<
1586 reg = <0 0x01d87000 0 <<
1587 clocks = <&rpmhcc RPM <<
1588 <&gcc GCC_UF <<
1589 <&gcc GCC_UF <<
1590 clock-names = "ref", <<
1591 "ref_au <<
1592 "qref"; <<
1593 power-domains = <&gcc <<
1594 resets = <&ufs_mem_hc <<
1595 reset-names = "ufsphy <<
1596 #phy-cells = <0>; <<
1597 status = "disabled"; <<
1598 }; <<
1599 <<
1600 ice: crypto@1d90000 { <<
1601 compatible = "qcom,sc <<
1602 "qcom,in <<
1603 reg = <0 0x01d90000 0 <<
1604 clocks = <&gcc GCC_UF <<
1605 }; 1404 };
1606 1405
1607 ipa: ipa@1e40000 { 1406 ipa: ipa@1e40000 {
1608 compatible = "qcom,sc 1407 compatible = "qcom,sc7180-ipa";
1609 1408
1610 iommus = <&apps_smmu 1409 iommus = <&apps_smmu 0x440 0x0>,
1611 <&apps_smmu 1410 <&apps_smmu 0x442 0x0>;
1612 reg = <0 0x01e40000 0 !! 1411 reg = <0 0x1e40000 0 0x7000>,
1613 <0 0x01e47000 0 !! 1412 <0 0x1e47000 0 0x2000>,
1614 <0 0x01e04000 0 !! 1413 <0 0x1e04000 0 0x2c000>;
1615 reg-names = "ipa-reg" 1414 reg-names = "ipa-reg",
1616 "ipa-shar 1415 "ipa-shared",
1617 "gsi"; 1416 "gsi";
1618 1417
1619 interrupts-extended = 1418 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
1620 1419 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
1621 1420 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1622 1421 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
1623 interrupt-names = "ip 1422 interrupt-names = "ipa",
1624 "gs 1423 "gsi",
1625 "ip 1424 "ipa-clock-query",
1626 "ip 1425 "ipa-setup-ready";
1627 1426
1628 clocks = <&rpmhcc RPM 1427 clocks = <&rpmhcc RPMH_IPA_CLK>;
1629 clock-names = "core"; 1428 clock-names = "core";
1630 1429
1631 interconnects = <&agg 1430 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
1632 <&agg 1431 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>,
1633 <&gem 1432 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
1634 interconnect-names = 1433 interconnect-names = "memory",
1635 1434 "imem",
1636 1435 "config";
1637 1436
1638 qcom,qmp = <&aoss_qmp <<
1639 <<
1640 qcom,smem-states = <& 1437 qcom,smem-states = <&ipa_smp2p_out 0>,
1641 <& 1438 <&ipa_smp2p_out 1>;
1642 qcom,smem-state-names 1439 qcom,smem-state-names = "ipa-clock-enabled-valid",
1643 1440 "ipa-clock-enabled";
1644 1441
1645 status = "disabled"; 1442 status = "disabled";
1646 }; 1443 };
1647 1444
1648 tcsr_mutex: hwlock@1f40000 { !! 1445 tcsr_mutex_regs: syscon@1f40000 {
1649 compatible = "qcom,tc !! 1446 compatible = "syscon";
1650 reg = <0 0x01f40000 0 !! 1447 reg = <0 0x01f40000 0 0x40000>;
1651 #hwlock-cells = <1>; <<
1652 }; 1448 };
1653 1449
1654 tcsr_regs_1: syscon@1f60000 { !! 1450 tcsr_regs: syscon@1fc0000 {
1655 compatible = "qcom,sc !! 1451 compatible = "syscon";
1656 reg = <0 0x01f60000 0 <<
1657 }; <<
1658 <<
1659 tcsr_regs_2: syscon@1fc0000 { <<
1660 compatible = "qcom,sc <<
1661 reg = <0 0x01fc0000 0 1452 reg = <0 0x01fc0000 0 0x40000>;
1662 }; 1453 };
1663 1454
1664 tlmm: pinctrl@3500000 { 1455 tlmm: pinctrl@3500000 {
1665 compatible = "qcom,sc 1456 compatible = "qcom,sc7180-pinctrl";
1666 reg = <0 0x03500000 0 1457 reg = <0 0x03500000 0 0x300000>,
1667 <0 0x03900000 0 1458 <0 0x03900000 0 0x300000>,
1668 <0 0x03d00000 0 1459 <0 0x03d00000 0 0x300000>;
1669 reg-names = "west", " 1460 reg-names = "west", "north", "south";
1670 interrupts = <GIC_SPI 1461 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1671 gpio-controller; 1462 gpio-controller;
1672 #gpio-cells = <2>; 1463 #gpio-cells = <2>;
1673 interrupt-controller; 1464 interrupt-controller;
1674 #interrupt-cells = <2 1465 #interrupt-cells = <2>;
1675 gpio-ranges = <&tlmm 1466 gpio-ranges = <&tlmm 0 0 120>;
1676 wakeup-parent = <&pdc 1467 wakeup-parent = <&pdc>;
1677 1468
1678 dp_hot_plug_det: dp-h !! 1469 dp_hot_plug_det: dp-hot-plug-det {
1679 pins = "gpio1 !! 1470 pinmux {
1680 function = "d !! 1471 pins = "gpio117";
1681 }; !! 1472 function = "dp_hot";
1682 !! 1473 };
1683 qspi_clk: qspi-clk-st <<
1684 pins = "gpio6 <<
1685 function = "q <<
1686 }; <<
1687 <<
1688 qspi_cs0: qspi-cs0-st <<
1689 pins = "gpio6 <<
1690 function = "q <<
1691 }; <<
1692 <<
1693 qspi_cs1: qspi-cs1-st <<
1694 pins = "gpio7 <<
1695 function = "q <<
1696 }; <<
1697 <<
1698 qspi_data0: qspi-data <<
1699 pins = "gpio6 <<
1700 function = "q <<
1701 }; <<
1702 <<
1703 qspi_data1: qspi-data <<
1704 pins = "gpio6 <<
1705 function = "q <<
1706 }; <<
1707 <<
1708 qspi_data23: qspi-dat <<
1709 pins = "gpio6 <<
1710 function = "q <<
1711 }; <<
1712 <<
1713 qup_i2c0_default: qup <<
1714 pins = "gpio3 <<
1715 function = "q <<
1716 }; 1474 };
1717 1475
1718 qup_i2c1_default: qup !! 1476 qspi_clk: qspi-clk {
1719 pins = "gpio0 !! 1477 pinmux {
1720 function = "q !! 1478 pins = "gpio63";
>> 1479 function = "qspi_clk";
>> 1480 };
1721 }; 1481 };
1722 1482
1723 qup_i2c2_default: qup !! 1483 qspi_cs0: qspi-cs0 {
1724 pins = "gpio1 !! 1484 pinmux {
1725 function = "q !! 1485 pins = "gpio68";
>> 1486 function = "qspi_cs";
>> 1487 };
1726 }; 1488 };
1727 1489
1728 qup_i2c3_default: qup !! 1490 qspi_cs1: qspi-cs1 {
1729 pins = "gpio3 !! 1491 pinmux {
1730 function = "q !! 1492 pins = "gpio72";
>> 1493 function = "qspi_cs";
>> 1494 };
1731 }; 1495 };
1732 1496
1733 qup_i2c4_default: qup !! 1497 qspi_data01: qspi-data01 {
1734 pins = "gpio1 !! 1498 pinmux-data {
1735 function = "q !! 1499 pins = "gpio64", "gpio65";
>> 1500 function = "qspi_data";
>> 1501 };
1736 }; 1502 };
1737 1503
1738 qup_i2c5_default: qup !! 1504 qspi_data12: qspi-data12 {
1739 pins = "gpio2 !! 1505 pinmux-data {
1740 function = "q !! 1506 pins = "gpio66", "gpio67";
>> 1507 function = "qspi_data";
>> 1508 };
1741 }; 1509 };
1742 1510
1743 qup_i2c6_default: qup !! 1511 qup_i2c0_default: qup-i2c0-default {
1744 pins = "gpio5 !! 1512 pinmux {
1745 function = "q !! 1513 pins = "gpio34", "gpio35";
>> 1514 function = "qup00";
>> 1515 };
1746 }; 1516 };
1747 1517
1748 qup_i2c7_default: qup !! 1518 qup_i2c1_default: qup-i2c1-default {
1749 pins = "gpio6 !! 1519 pinmux {
1750 function = "q !! 1520 pins = "gpio0", "gpio1";
>> 1521 function = "qup01";
>> 1522 };
1751 }; 1523 };
1752 1524
1753 qup_i2c8_default: qup !! 1525 qup_i2c2_default: qup-i2c2-default {
1754 pins = "gpio4 !! 1526 pinmux {
1755 function = "q !! 1527 pins = "gpio15", "gpio16";
>> 1528 function = "qup02_i2c";
>> 1529 };
1756 }; 1530 };
1757 1531
1758 qup_i2c9_default: qup !! 1532 qup_i2c3_default: qup-i2c3-default {
1759 pins = "gpio4 !! 1533 pinmux {
1760 function = "q !! 1534 pins = "gpio38", "gpio39";
>> 1535 function = "qup03";
>> 1536 };
1761 }; 1537 };
1762 1538
1763 qup_i2c10_default: qu !! 1539 qup_i2c4_default: qup-i2c4-default {
1764 pins = "gpio8 !! 1540 pinmux {
1765 function = "q !! 1541 pins = "gpio115", "gpio116";
>> 1542 function = "qup04_i2c";
>> 1543 };
1766 }; 1544 };
1767 1545
1768 qup_i2c11_default: qu !! 1546 qup_i2c5_default: qup-i2c5-default {
1769 pins = "gpio5 !! 1547 pinmux {
1770 function = "q !! 1548 pins = "gpio25", "gpio26";
>> 1549 function = "qup05";
>> 1550 };
1771 }; 1551 };
1772 1552
1773 qup_spi0_spi: qup-spi !! 1553 qup_i2c6_default: qup-i2c6-default {
1774 pins = "gpio3 !! 1554 pinmux {
1775 function = "q !! 1555 pins = "gpio59", "gpio60";
>> 1556 function = "qup10";
>> 1557 };
1776 }; 1558 };
1777 1559
1778 qup_spi0_cs: qup-spi0 !! 1560 qup_i2c7_default: qup-i2c7-default {
1779 pins = "gpio3 !! 1561 pinmux {
1780 function = "q !! 1562 pins = "gpio6", "gpio7";
>> 1563 function = "qup11_i2c";
>> 1564 };
1781 }; 1565 };
1782 1566
1783 qup_spi0_cs_gpio: qup !! 1567 qup_i2c8_default: qup-i2c8-default {
1784 pins = "gpio3 !! 1568 pinmux {
1785 function = "g !! 1569 pins = "gpio42", "gpio43";
>> 1570 function = "qup12";
>> 1571 };
1786 }; 1572 };
1787 1573
1788 qup_spi1_spi: qup-spi !! 1574 qup_i2c9_default: qup-i2c9-default {
1789 pins = "gpio0 !! 1575 pinmux {
1790 function = "q !! 1576 pins = "gpio46", "gpio47";
>> 1577 function = "qup13_i2c";
>> 1578 };
1791 }; 1579 };
1792 1580
1793 qup_spi1_cs: qup-spi1 !! 1581 qup_i2c10_default: qup-i2c10-default {
1794 pins = "gpio3 !! 1582 pinmux {
1795 function = "q !! 1583 pins = "gpio86", "gpio87";
>> 1584 function = "qup14";
>> 1585 };
1796 }; 1586 };
1797 1587
1798 qup_spi1_cs_gpio: qup !! 1588 qup_i2c11_default: qup-i2c11-default {
1799 pins = "gpio3 !! 1589 pinmux {
1800 function = "g !! 1590 pins = "gpio53", "gpio54";
>> 1591 function = "qup15";
>> 1592 };
1801 }; 1593 };
1802 1594
1803 qup_spi3_spi: qup-spi !! 1595 qup_spi0_default: qup-spi0-default {
1804 pins = "gpio3 !! 1596 pinmux {
1805 function = "q !! 1597 pins = "gpio34", "gpio35",
>> 1598 "gpio36", "gpio37";
>> 1599 function = "qup00";
>> 1600 };
1806 }; 1601 };
1807 1602
1808 qup_spi3_cs: qup-spi3 !! 1603 qup_spi0_cs_gpio: qup-spi0-cs-gpio {
1809 pins = "gpio4 !! 1604 pinmux {
1810 function = "q !! 1605 pins = "gpio34", "gpio35",
1811 }; !! 1606 "gpio36";
>> 1607 function = "qup00";
>> 1608 };
1812 1609
1813 qup_spi3_cs_gpio: qup !! 1610 pinmux-cs {
1814 pins = "gpio4 !! 1611 pins = "gpio37";
1815 function = "g !! 1612 function = "gpio";
>> 1613 };
1816 }; 1614 };
1817 1615
1818 qup_spi5_spi: qup-spi !! 1616 qup_spi1_default: qup-spi1-default {
1819 pins = "gpio2 !! 1617 pinmux {
1820 function = "q !! 1618 pins = "gpio0", "gpio1",
>> 1619 "gpio2", "gpio3";
>> 1620 function = "qup01";
>> 1621 };
1821 }; 1622 };
1822 1623
1823 qup_spi5_cs: qup-spi5 !! 1624 qup_spi1_cs_gpio: qup-spi1-cs-gpio {
1824 pins = "gpio2 !! 1625 pinmux {
1825 function = "q !! 1626 pins = "gpio0", "gpio1",
1826 }; !! 1627 "gpio2";
>> 1628 function = "qup01";
>> 1629 };
1827 1630
1828 qup_spi5_cs_gpio: qup !! 1631 pinmux-cs {
1829 pins = "gpio2 !! 1632 pins = "gpio3";
1830 function = "g !! 1633 function = "gpio";
>> 1634 };
1831 }; 1635 };
1832 1636
1833 qup_spi6_spi: qup-spi !! 1637 qup_spi3_default: qup-spi3-default {
1834 pins = "gpio5 !! 1638 pinmux {
1835 function = "q !! 1639 pins = "gpio38", "gpio39",
>> 1640 "gpio40", "gpio41";
>> 1641 function = "qup03";
>> 1642 };
1836 }; 1643 };
1837 1644
1838 qup_spi6_cs: qup-spi6 !! 1645 qup_spi3_cs_gpio: qup-spi3-cs-gpio {
1839 pins = "gpio6 !! 1646 pinmux {
1840 function = "q !! 1647 pins = "gpio38", "gpio39",
1841 }; !! 1648 "gpio40";
>> 1649 function = "qup03";
>> 1650 };
1842 1651
1843 qup_spi6_cs_gpio: qup !! 1652 pinmux-cs {
1844 pins = "gpio6 !! 1653 pins = "gpio41";
1845 function = "g !! 1654 function = "gpio";
>> 1655 };
1846 }; 1656 };
1847 1657
1848 qup_spi8_spi: qup-spi !! 1658 qup_spi5_default: qup-spi5-default {
1849 pins = "gpio4 !! 1659 pinmux {
1850 function = "q !! 1660 pins = "gpio25", "gpio26",
>> 1661 "gpio27", "gpio28";
>> 1662 function = "qup05";
>> 1663 };
1851 }; 1664 };
1852 1665
1853 qup_spi8_cs: qup-spi8 !! 1666 qup_spi5_cs_gpio: qup-spi5-cs-gpio {
1854 pins = "gpio4 !! 1667 pinmux {
1855 function = "q !! 1668 pins = "gpio25", "gpio26",
1856 }; !! 1669 "gpio27";
>> 1670 function = "qup05";
>> 1671 };
1857 1672
1858 qup_spi8_cs_gpio: qup !! 1673 pinmux-cs {
1859 pins = "gpio4 !! 1674 pins = "gpio28";
1860 function = "g !! 1675 function = "gpio";
>> 1676 };
1861 }; 1677 };
1862 1678
1863 qup_spi10_spi: qup-sp !! 1679 qup_spi6_default: qup-spi6-default {
1864 pins = "gpio8 !! 1680 pinmux {
1865 function = "q !! 1681 pins = "gpio59", "gpio60",
>> 1682 "gpio61", "gpio62";
>> 1683 function = "qup10";
>> 1684 };
1866 }; 1685 };
1867 1686
1868 qup_spi10_cs: qup-spi !! 1687 qup_spi6_cs_gpio: qup-spi6-cs-gpio {
1869 pins = "gpio8 !! 1688 pinmux {
1870 function = "q !! 1689 pins = "gpio59", "gpio60",
1871 }; !! 1690 "gpio61";
>> 1691 function = "qup10";
>> 1692 };
1872 1693
1873 qup_spi10_cs_gpio: qu !! 1694 pinmux-cs {
1874 pins = "gpio8 !! 1695 pins = "gpio62";
1875 function = "g !! 1696 function = "gpio";
>> 1697 };
1876 }; 1698 };
1877 1699
1878 qup_spi11_spi: qup-sp !! 1700 qup_spi8_default: qup-spi8-default {
1879 pins = "gpio5 !! 1701 pinmux {
1880 function = "q !! 1702 pins = "gpio42", "gpio43",
>> 1703 "gpio44", "gpio45";
>> 1704 function = "qup12";
>> 1705 };
1881 }; 1706 };
1882 1707
1883 qup_spi11_cs: qup-spi !! 1708 qup_spi8_cs_gpio: qup-spi8-cs-gpio {
1884 pins = "gpio5 !! 1709 pinmux {
1885 function = "q !! 1710 pins = "gpio42", "gpio43",
1886 }; !! 1711 "gpio44";
>> 1712 function = "qup12";
>> 1713 };
1887 1714
1888 qup_spi11_cs_gpio: qu !! 1715 pinmux-cs {
1889 pins = "gpio5 !! 1716 pins = "gpio45";
1890 function = "g !! 1717 function = "gpio";
>> 1718 };
1891 }; 1719 };
1892 1720
1893 qup_uart0_default: qu !! 1721 qup_spi10_default: qup-spi10-default {
1894 qup_uart0_cts !! 1722 pinmux {
1895 pins !! 1723 pins = "gpio86", "gpio87",
1896 funct !! 1724 "gpio88", "gpio89";
>> 1725 function = "qup14";
1897 }; 1726 };
>> 1727 };
1898 1728
1899 qup_uart0_rts !! 1729 qup_spi10_cs_gpio: qup-spi10-cs-gpio {
1900 pins !! 1730 pinmux {
1901 funct !! 1731 pins = "gpio86", "gpio87",
>> 1732 "gpio88";
>> 1733 function = "qup14";
1902 }; 1734 };
1903 1735
1904 qup_uart0_tx: !! 1736 pinmux-cs {
1905 pins !! 1737 pins = "gpio89";
1906 funct !! 1738 function = "gpio";
1907 }; 1739 };
>> 1740 };
1908 1741
1909 qup_uart0_rx: !! 1742 qup_spi11_default: qup-spi11-default {
1910 pins !! 1743 pinmux {
1911 funct !! 1744 pins = "gpio53", "gpio54",
>> 1745 "gpio55", "gpio56";
>> 1746 function = "qup15";
1912 }; 1747 };
1913 }; 1748 };
1914 1749
1915 qup_uart1_default: qu !! 1750 qup_spi11_cs_gpio: qup-spi11-cs-gpio {
1916 qup_uart1_cts !! 1751 pinmux {
1917 pins !! 1752 pins = "gpio53", "gpio54",
1918 funct !! 1753 "gpio55";
>> 1754 function = "qup15";
1919 }; 1755 };
1920 1756
1921 qup_uart1_rts !! 1757 pinmux-cs {
1922 pins !! 1758 pins = "gpio56";
1923 funct !! 1759 function = "gpio";
1924 }; 1760 };
>> 1761 };
1925 1762
1926 qup_uart1_tx: !! 1763 qup_uart0_default: qup-uart0-default {
1927 pins !! 1764 pinmux {
1928 funct !! 1765 pins = "gpio34", "gpio35",
>> 1766 "gpio36", "gpio37";
>> 1767 function = "qup00";
1929 }; 1768 };
>> 1769 };
1930 1770
1931 qup_uart1_rx: !! 1771 qup_uart1_default: qup-uart1-default {
1932 pins !! 1772 pinmux {
>> 1773 pins = "gpio0", "gpio1",
>> 1774 "gpio2", "gpio3";
1933 funct 1775 function = "qup01";
1934 }; 1776 };
1935 }; 1777 };
1936 1778
1937 qup_uart2_default: qu !! 1779 qup_uart2_default: qup-uart2-default {
1938 qup_uart2_tx: !! 1780 pinmux {
1939 pins !! 1781 pins = "gpio15", "gpio16";
1940 funct <<
1941 }; <<
1942 <<
1943 qup_uart2_rx: <<
1944 pins <<
1945 funct 1782 function = "qup02_uart";
1946 }; 1783 };
1947 }; 1784 };
1948 1785
1949 qup_uart3_default: qu !! 1786 qup_uart3_default: qup-uart3-default {
1950 qup_uart3_cts !! 1787 pinmux {
1951 pins !! 1788 pins = "gpio38", "gpio39",
1952 funct !! 1789 "gpio40", "gpio41";
1953 }; <<
1954 <<
1955 qup_uart3_rts <<
1956 pins <<
1957 funct 1790 function = "qup03";
1958 }; 1791 };
>> 1792 };
1959 1793
1960 qup_uart3_tx: !! 1794 qup_uart4_default: qup-uart4-default {
1961 pins !! 1795 pinmux {
1962 funct !! 1796 pins = "gpio115", "gpio116";
>> 1797 function = "qup04_uart";
1963 }; 1798 };
>> 1799 };
1964 1800
1965 qup_uart3_rx: !! 1801 qup_uart5_default: qup-uart5-default {
1966 pins !! 1802 pinmux {
1967 funct !! 1803 pins = "gpio25", "gpio26",
>> 1804 "gpio27", "gpio28";
>> 1805 function = "qup05";
1968 }; 1806 };
1969 }; 1807 };
1970 1808
1971 qup_uart4_default: qu !! 1809 qup_uart6_default: qup-uart6-default {
1972 qup_uart4_tx: !! 1810 pinmux {
1973 pins !! 1811 pins = "gpio59", "gpio60",
1974 funct !! 1812 "gpio61", "gpio62";
>> 1813 function = "qup10";
1975 }; 1814 };
>> 1815 };
1976 1816
1977 qup_uart4_rx: !! 1817 qup_uart7_default: qup-uart7-default {
1978 pins !! 1818 pinmux {
1979 funct !! 1819 pins = "gpio6", "gpio7";
>> 1820 function = "qup11_uart";
1980 }; 1821 };
1981 }; 1822 };
1982 1823
1983 qup_uart5_default: qu !! 1824 qup_uart8_default: qup-uart8-default {
1984 qup_uart5_cts !! 1825 pinmux {
1985 pins !! 1826 pins = "gpio44", "gpio45";
1986 funct !! 1827 function = "qup12";
1987 }; 1828 };
>> 1829 };
1988 1830
1989 qup_uart5_rts !! 1831 qup_uart9_default: qup-uart9-default {
1990 pins !! 1832 pinmux {
1991 funct !! 1833 pins = "gpio46", "gpio47";
>> 1834 function = "qup13_uart";
1992 }; 1835 };
>> 1836 };
1993 1837
1994 qup_uart5_tx: !! 1838 qup_uart10_default: qup-uart10-default {
1995 pins !! 1839 pinmux {
1996 funct !! 1840 pins = "gpio86", "gpio87",
>> 1841 "gpio88", "gpio89";
>> 1842 function = "qup14";
1997 }; 1843 };
>> 1844 };
1998 1845
1999 qup_uart5_rx: !! 1846 qup_uart11_default: qup-uart11-default {
2000 pins !! 1847 pinmux {
2001 funct !! 1848 pins = "gpio53", "gpio54",
>> 1849 "gpio55", "gpio56";
>> 1850 function = "qup15";
2002 }; 1851 };
2003 }; 1852 };
2004 1853
2005 qup_uart6_default: qu !! 1854 sec_mi2s_active: sec-mi2s-active {
2006 qup_uart6_cts !! 1855 pinmux {
2007 pins !! 1856 pins = "gpio49", "gpio50", "gpio51";
2008 funct !! 1857 function = "mi2s_1";
2009 }; 1858 };
2010 1859
2011 qup_uart6_rts !! 1860 pinconf {
2012 pins !! 1861 pins = "gpio49", "gpio50", "gpio51";
2013 funct !! 1862 drive-strength = <8>;
>> 1863 bias-pull-up;
2014 }; 1864 };
>> 1865 };
2015 1866
2016 qup_uart6_tx: !! 1867 pri_mi2s_active: pri-mi2s-active {
2017 pins !! 1868 pinmux {
2018 funct !! 1869 pins = "gpio53", "gpio54", "gpio55", "gpio56";
>> 1870 function = "mi2s_0";
2019 }; 1871 };
2020 1872
2021 qup_uart6_rx: !! 1873 pinconf {
2022 pins !! 1874 pins = "gpio53", "gpio54", "gpio55", "gpio56";
2023 funct !! 1875 drive-strength = <8>;
>> 1876 bias-pull-up;
2024 }; 1877 };
2025 }; 1878 };
2026 1879
2027 qup_uart7_default: qu !! 1880 pri_mi2s_mclk_active: pri-mi2s-mclk-active {
2028 qup_uart7_tx: !! 1881 pinmux {
2029 pins !! 1882 pins = "gpio57";
2030 funct !! 1883 function = "lpass_ext";
2031 }; 1884 };
2032 1885
2033 qup_uart7_rx: !! 1886 pinconf {
2034 pins !! 1887 pins = "gpio57";
2035 funct !! 1888 drive-strength = <8>;
>> 1889 bias-pull-up;
2036 }; 1890 };
2037 }; 1891 };
2038 1892
2039 qup_uart8_default: qu !! 1893 sdc1_on: sdc1-on {
2040 qup_uart8_tx: !! 1894 pinconf-clk {
2041 pins !! 1895 pins = "sdc1_clk";
2042 funct !! 1896 bias-disable;
>> 1897 drive-strength = <16>;
2043 }; 1898 };
2044 1899
2045 qup_uart8_rx: !! 1900 pinconf-cmd {
2046 pins !! 1901 pins = "sdc1_cmd";
2047 funct !! 1902 bias-pull-up;
>> 1903 drive-strength = <10>;
2048 }; 1904 };
2049 }; <<
2050 1905
2051 qup_uart9_default: qu !! 1906 pinconf-data {
2052 qup_uart9_tx: !! 1907 pins = "sdc1_data";
2053 pins !! 1908 bias-pull-up;
2054 funct !! 1909 drive-strength = <10>;
2055 }; 1910 };
2056 1911
2057 qup_uart9_rx: !! 1912 pinconf-rclk {
2058 pins !! 1913 pins = "sdc1_rclk";
2059 funct !! 1914 bias-pull-down;
2060 }; 1915 };
2061 }; 1916 };
2062 1917
2063 qup_uart10_default: q !! 1918 sdc1_off: sdc1-off {
2064 qup_uart10_ct !! 1919 pinconf-clk {
2065 pins !! 1920 pins = "sdc1_clk";
2066 funct !! 1921 bias-disable;
>> 1922 drive-strength = <2>;
2067 }; 1923 };
2068 1924
2069 qup_uart10_rt !! 1925 pinconf-cmd {
2070 pins !! 1926 pins = "sdc1_cmd";
2071 funct !! 1927 bias-pull-up;
>> 1928 drive-strength = <2>;
2072 }; 1929 };
2073 1930
2074 qup_uart10_tx !! 1931 pinconf-data {
2075 pins !! 1932 pins = "sdc1_data";
2076 funct !! 1933 bias-pull-up;
>> 1934 drive-strength = <2>;
2077 }; 1935 };
2078 1936
2079 qup_uart10_rx !! 1937 pinconf-rclk {
2080 pins !! 1938 pins = "sdc1_rclk";
2081 funct !! 1939 bias-pull-down;
2082 }; 1940 };
2083 }; 1941 };
2084 1942
2085 qup_uart11_default: q !! 1943 sdc2_on: sdc2-on {
2086 qup_uart11_ct !! 1944 pinconf-clk {
2087 pins !! 1945 pins = "sdc2_clk";
2088 funct !! 1946 bias-disable;
>> 1947 drive-strength = <16>;
2089 }; 1948 };
2090 1949
2091 qup_uart11_rt !! 1950 pinconf-cmd {
2092 pins !! 1951 pins = "sdc2_cmd";
2093 funct !! 1952 bias-pull-up;
>> 1953 drive-strength = <10>;
2094 }; 1954 };
2095 1955
2096 qup_uart11_tx !! 1956 pinconf-data {
2097 pins !! 1957 pins = "sdc2_data";
2098 funct !! 1958 bias-pull-up;
>> 1959 drive-strength = <10>;
2099 }; 1960 };
2100 1961
2101 qup_uart11_rx !! 1962 pinconf-sd-cd {
2102 pins !! 1963 pins = "gpio69";
2103 funct !! 1964 bias-pull-up;
>> 1965 drive-strength = <2>;
2104 }; 1966 };
2105 }; 1967 };
2106 1968
2107 sec_mi2s_active: sec- !! 1969 sdc2_off: sdc2-off {
2108 pins = "gpio4 !! 1970 pinconf-clk {
2109 function = "m !! 1971 pins = "sdc2_clk";
2110 }; !! 1972 bias-disable;
>> 1973 drive-strength = <2>;
>> 1974 };
2111 1975
2112 pri_mi2s_active: pri- !! 1976 pinconf-cmd {
2113 pins = "gpio5 !! 1977 pins = "sdc2_cmd";
2114 function = "m !! 1978 bias-pull-up;
2115 }; !! 1979 drive-strength = <2>;
>> 1980 };
2116 1981
2117 pri_mi2s_mclk_active: !! 1982 pinconf-data {
2118 pins = "gpio5 !! 1983 pins = "sdc2_data";
2119 function = "l !! 1984 bias-pull-up;
2120 }; !! 1985 drive-strength = <2>;
>> 1986 };
2121 1987
2122 ter_mi2s_active: ter- !! 1988 pinconf-sd-cd {
2123 pins = "gpio6 !! 1989 pins = "gpio69";
2124 function = "m !! 1990 bias-disable;
>> 1991 drive-strength = <2>;
>> 1992 };
2125 }; 1993 };
2126 }; 1994 };
2127 1995
2128 remoteproc_mpss: remoteproc@4 1996 remoteproc_mpss: remoteproc@4080000 {
2129 compatible = "qcom,sc 1997 compatible = "qcom,sc7180-mpss-pas";
2130 reg = <0 0x04080000 0 !! 1998 reg = <0 0x04080000 0 0x4040>, <0 0x04180000 0 0x48>;
>> 1999 reg-names = "qdsp6", "rmb";
2131 2000
2132 interrupts-extended = 2001 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
2133 2002 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2134 2003 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2135 2004 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2136 2005 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
2137 2006 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
2138 interrupt-names = "wd 2007 interrupt-names = "wdog", "fatal", "ready", "handover",
2139 "st 2008 "stop-ack", "shutdown-ack";
2140 2009
2141 clocks = <&rpmhcc RPM !! 2010 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
2142 clock-names = "xo"; !! 2011 <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>,
>> 2012 <&gcc GCC_MSS_NAV_AXI_CLK>,
>> 2013 <&gcc GCC_MSS_SNOC_AXI_CLK>,
>> 2014 <&gcc GCC_MSS_MFAB_AXIS_CLK>,
>> 2015 <&rpmhcc RPMH_CXO_CLK>;
>> 2016 clock-names = "iface", "bus", "nav", "snoc_axi",
>> 2017 "mnoc_axi", "xo";
2143 2018
2144 power-domains = <&rpm !! 2019 power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>,
>> 2020 <&rpmhpd SC7180_CX>,
2145 <&rpm 2021 <&rpmhpd SC7180_MX>,
2146 <&rpm 2022 <&rpmhpd SC7180_MSS>;
2147 power-domain-names = !! 2023 power-domain-names = "load_state", "cx", "mx", "mss";
2148 2024
2149 memory-region = <&mps 2025 memory-region = <&mpss_mem>;
2150 2026
2151 qcom,qmp = <&aoss_qmp <<
2152 <<
2153 qcom,smem-states = <& 2027 qcom,smem-states = <&modem_smp2p_out 0>;
2154 qcom,smem-state-names 2028 qcom,smem-state-names = "stop";
2155 2029
>> 2030 resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
>> 2031 <&pdc_reset PDC_MODEM_SYNC_RESET>;
>> 2032 reset-names = "mss_restart", "pdc_reset";
>> 2033
>> 2034 qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
>> 2035 qcom,spare-regs = <&tcsr_regs 0xb3e4>;
>> 2036
2156 status = "disabled"; 2037 status = "disabled";
2157 2038
2158 glink-edge { 2039 glink-edge {
2159 interrupts = 2040 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
2160 label = "mode 2041 label = "modem";
2161 qcom,remote-p 2042 qcom,remote-pid = <1>;
2162 mboxes = <&ap 2043 mboxes = <&apss_shared 12>;
2163 }; 2044 };
2164 }; 2045 };
2165 2046
2166 gpu: gpu@5000000 { 2047 gpu: gpu@5000000 {
2167 compatible = "qcom,ad 2048 compatible = "qcom,adreno-618.0", "qcom,adreno";
>> 2049 #stream-id-cells = <16>;
2168 reg = <0 0x05000000 0 2050 reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x1000>,
2169 <0 0x05061000 2051 <0 0x05061000 0 0x800>;
2170 reg-names = "kgsl_3d0 2052 reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc";
2171 interrupts = <GIC_SPI 2053 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2172 iommus = <&adreno_smm 2054 iommus = <&adreno_smmu 0>;
2173 operating-points-v2 = 2055 operating-points-v2 = <&gpu_opp_table>;
2174 qcom,gmu = <&gmu>; 2056 qcom,gmu = <&gmu>;
2175 2057
2176 #cooling-cells = <2>; 2058 #cooling-cells = <2>;
2177 2059
2178 nvmem-cells = <&gpu_s 2060 nvmem-cells = <&gpu_speed_bin>;
2179 nvmem-cell-names = "s 2061 nvmem-cell-names = "speed_bin";
2180 2062
2181 interconnects = <&gem 2063 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
2182 interconnect-names = 2064 interconnect-names = "gfx-mem";
2183 2065
2184 gpu_opp_table: opp-ta 2066 gpu_opp_table: opp-table {
2185 compatible = 2067 compatible = "operating-points-v2";
2186 2068
2187 opp-825000000 2069 opp-825000000 {
2188 opp-h 2070 opp-hz = /bits/ 64 <825000000>;
2189 opp-l 2071 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2190 opp-p 2072 opp-peak-kBps = <8532000>;
2191 opp-s 2073 opp-supported-hw = <0x04>;
2192 }; 2074 };
2193 2075
2194 opp-800000000 2076 opp-800000000 {
2195 opp-h 2077 opp-hz = /bits/ 64 <800000000>;
2196 opp-l 2078 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2197 opp-p 2079 opp-peak-kBps = <8532000>;
2198 opp-s 2080 opp-supported-hw = <0x07>;
2199 }; 2081 };
2200 2082
2201 opp-650000000 2083 opp-650000000 {
2202 opp-h 2084 opp-hz = /bits/ 64 <650000000>;
2203 opp-l 2085 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2204 opp-p 2086 opp-peak-kBps = <7216000>;
2205 opp-s 2087 opp-supported-hw = <0x07>;
2206 }; 2088 };
2207 2089
2208 opp-565000000 2090 opp-565000000 {
2209 opp-h 2091 opp-hz = /bits/ 64 <565000000>;
2210 opp-l 2092 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2211 opp-p 2093 opp-peak-kBps = <5412000>;
2212 opp-s 2094 opp-supported-hw = <0x07>;
2213 }; 2095 };
2214 2096
2215 opp-430000000 2097 opp-430000000 {
2216 opp-h 2098 opp-hz = /bits/ 64 <430000000>;
2217 opp-l 2099 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2218 opp-p 2100 opp-peak-kBps = <5412000>;
2219 opp-s 2101 opp-supported-hw = <0x07>;
2220 }; 2102 };
2221 2103
2222 opp-355000000 2104 opp-355000000 {
2223 opp-h 2105 opp-hz = /bits/ 64 <355000000>;
2224 opp-l 2106 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2225 opp-p 2107 opp-peak-kBps = <3072000>;
2226 opp-s 2108 opp-supported-hw = <0x07>;
2227 }; 2109 };
2228 2110
2229 opp-267000000 2111 opp-267000000 {
2230 opp-h 2112 opp-hz = /bits/ 64 <267000000>;
2231 opp-l 2113 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2232 opp-p 2114 opp-peak-kBps = <3072000>;
2233 opp-s 2115 opp-supported-hw = <0x07>;
2234 }; 2116 };
2235 2117
2236 opp-180000000 2118 opp-180000000 {
2237 opp-h 2119 opp-hz = /bits/ 64 <180000000>;
2238 opp-l 2120 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2239 opp-p 2121 opp-peak-kBps = <1804000>;
2240 opp-s 2122 opp-supported-hw = <0x07>;
2241 }; 2123 };
2242 }; 2124 };
2243 }; 2125 };
2244 2126
2245 adreno_smmu: iommu@5040000 { 2127 adreno_smmu: iommu@5040000 {
2246 compatible = "qcom,sc 2128 compatible = "qcom,sc7180-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
2247 reg = <0 0x05040000 0 2129 reg = <0 0x05040000 0 0x10000>;
2248 #iommu-cells = <1>; 2130 #iommu-cells = <1>;
2249 #global-interrupts = 2131 #global-interrupts = <2>;
2250 interrupts = <GIC_SPI 2132 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
2251 <GIC_ 2133 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
2252 <GIC_ 2134 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
2253 <GIC_ 2135 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
2254 <GIC_ 2136 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
2255 <GIC_ 2137 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
2256 <GIC_ 2138 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
2257 <GIC_ 2139 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
2258 <GIC_ 2140 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
2259 <GIC_ 2141 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
2260 2142
2261 clocks = <&gcc GCC_GP 2143 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2262 <&gcc GCC_GPU 2144 <&gcc GCC_GPU_CFG_AHB_CLK>;
2263 clock-names = "bus", 2145 clock-names = "bus", "iface";
2264 2146
2265 power-domains = <&gpu 2147 power-domains = <&gpucc CX_GDSC>;
2266 }; 2148 };
2267 2149
2268 gmu: gmu@506a000 { 2150 gmu: gmu@506a000 {
2269 compatible = "qcom,ad !! 2151 compatible="qcom,adreno-gmu-618.0", "qcom,adreno-gmu";
2270 reg = <0 0x0506a000 0 2152 reg = <0 0x0506a000 0 0x31000>, <0 0x0b290000 0 0x10000>,
2271 <0 0x0b490000 2153 <0 0x0b490000 0 0x10000>;
2272 reg-names = "gmu", "g 2154 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
2273 interrupts = <GIC_SPI 2155 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2274 <GIC_SPI 3 2156 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2275 interrupt-names = "hf 2157 interrupt-names = "hfi", "gmu";
2276 clocks = <&gpucc GPU_ 2158 clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
2277 <&gpucc GPU_CC 2159 <&gpucc GPU_CC_CXO_CLK>,
2278 <&gcc GCC_DDRS 2160 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2279 <&gcc GCC_GPU_ 2161 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
2280 clock-names = "gmu", 2162 clock-names = "gmu", "cxo", "axi", "memnoc";
2281 power-domains = <&gpu 2163 power-domains = <&gpucc CX_GDSC>, <&gpucc GX_GDSC>;
2282 power-domain-names = 2164 power-domain-names = "cx", "gx";
2283 iommus = <&adreno_smm 2165 iommus = <&adreno_smmu 5>;
2284 operating-points-v2 = 2166 operating-points-v2 = <&gmu_opp_table>;
2285 2167
2286 gmu_opp_table: opp-ta 2168 gmu_opp_table: opp-table {
2287 compatible = 2169 compatible = "operating-points-v2";
2288 2170
2289 opp-200000000 2171 opp-200000000 {
2290 opp-h 2172 opp-hz = /bits/ 64 <200000000>;
2291 opp-l 2173 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2292 }; 2174 };
2293 }; 2175 };
2294 }; 2176 };
2295 2177
2296 gpucc: clock-controller@50900 2178 gpucc: clock-controller@5090000 {
2297 compatible = "qcom,sc 2179 compatible = "qcom,sc7180-gpucc";
2298 reg = <0 0x05090000 0 2180 reg = <0 0x05090000 0 0x9000>;
2299 clocks = <&rpmhcc RPM 2181 clocks = <&rpmhcc RPMH_CXO_CLK>,
2300 <&gcc GCC_GP 2182 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2301 <&gcc GCC_GP 2183 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2302 clock-names = "bi_tcx 2184 clock-names = "bi_tcxo",
2303 "gcc_gp 2185 "gcc_gpu_gpll0_clk_src",
2304 "gcc_gp 2186 "gcc_gpu_gpll0_div_clk_src";
2305 #clock-cells = <1>; 2187 #clock-cells = <1>;
2306 #reset-cells = <1>; 2188 #reset-cells = <1>;
2307 #power-domain-cells = 2189 #power-domain-cells = <1>;
2308 }; 2190 };
2309 2191
2310 dma@10a2000 { <<
2311 compatible = "qcom,sc <<
2312 reg = <0x0 0x010a2000 <<
2313 <0x0 0x010ae000 <<
2314 status = "disabled"; <<
2315 }; <<
2316 <<
2317 stm@6002000 { 2192 stm@6002000 {
2318 compatible = "arm,cor 2193 compatible = "arm,coresight-stm", "arm,primecell";
2319 reg = <0 0x06002000 0 2194 reg = <0 0x06002000 0 0x1000>,
2320 <0 0x16280000 0 2195 <0 0x16280000 0 0x180000>;
2321 reg-names = "stm-base 2196 reg-names = "stm-base", "stm-stimulus-base";
2322 2197
2323 clocks = <&aoss_qmp>; 2198 clocks = <&aoss_qmp>;
2324 clock-names = "apb_pc 2199 clock-names = "apb_pclk";
2325 2200
2326 out-ports { 2201 out-ports {
2327 port { 2202 port {
2328 stm_o 2203 stm_out: endpoint {
2329 2204 remote-endpoint = <&funnel0_in7>;
2330 }; 2205 };
2331 }; 2206 };
2332 }; 2207 };
2333 }; 2208 };
2334 2209
2335 funnel@6041000 { 2210 funnel@6041000 {
2336 compatible = "arm,cor 2211 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2337 reg = <0 0x06041000 0 2212 reg = <0 0x06041000 0 0x1000>;
2338 2213
2339 clocks = <&aoss_qmp>; 2214 clocks = <&aoss_qmp>;
2340 clock-names = "apb_pc 2215 clock-names = "apb_pclk";
2341 2216
2342 out-ports { 2217 out-ports {
2343 port { 2218 port {
2344 funne 2219 funnel0_out: endpoint {
2345 2220 remote-endpoint = <&merge_funnel_in0>;
2346 }; 2221 };
2347 }; 2222 };
2348 }; 2223 };
2349 2224
2350 in-ports { 2225 in-ports {
2351 #address-cell 2226 #address-cells = <1>;
2352 #size-cells = 2227 #size-cells = <0>;
2353 2228
2354 port@7 { 2229 port@7 {
2355 reg = 2230 reg = <7>;
2356 funne 2231 funnel0_in7: endpoint {
2357 2232 remote-endpoint = <&stm_out>;
2358 }; 2233 };
2359 }; 2234 };
2360 }; 2235 };
2361 }; 2236 };
2362 2237
2363 funnel@6042000 { 2238 funnel@6042000 {
2364 compatible = "arm,cor 2239 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2365 reg = <0 0x06042000 0 2240 reg = <0 0x06042000 0 0x1000>;
2366 2241
2367 clocks = <&aoss_qmp>; 2242 clocks = <&aoss_qmp>;
2368 clock-names = "apb_pc 2243 clock-names = "apb_pclk";
2369 2244
2370 out-ports { 2245 out-ports {
2371 port { 2246 port {
2372 funne 2247 funnel1_out: endpoint {
2373 2248 remote-endpoint = <&merge_funnel_in1>;
2374 }; 2249 };
2375 }; 2250 };
2376 }; 2251 };
2377 2252
2378 in-ports { 2253 in-ports {
2379 #address-cell 2254 #address-cells = <1>;
2380 #size-cells = 2255 #size-cells = <0>;
2381 2256
2382 port@4 { 2257 port@4 {
2383 reg = 2258 reg = <4>;
2384 funne 2259 funnel1_in4: endpoint {
2385 2260 remote-endpoint = <&apss_merge_funnel_out>;
2386 }; 2261 };
2387 }; 2262 };
2388 }; 2263 };
2389 }; 2264 };
2390 2265
2391 funnel@6045000 { 2266 funnel@6045000 {
2392 compatible = "arm,cor 2267 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2393 reg = <0 0x06045000 0 2268 reg = <0 0x06045000 0 0x1000>;
2394 2269
2395 clocks = <&aoss_qmp>; 2270 clocks = <&aoss_qmp>;
2396 clock-names = "apb_pc 2271 clock-names = "apb_pclk";
2397 2272
2398 out-ports { 2273 out-ports {
2399 port { 2274 port {
2400 merge 2275 merge_funnel_out: endpoint {
2401 2276 remote-endpoint = <&swao_funnel_in>;
2402 }; 2277 };
2403 }; 2278 };
2404 }; 2279 };
2405 2280
2406 in-ports { 2281 in-ports {
2407 #address-cell 2282 #address-cells = <1>;
2408 #size-cells = 2283 #size-cells = <0>;
2409 2284
2410 port@0 { 2285 port@0 {
2411 reg = 2286 reg = <0>;
2412 merge 2287 merge_funnel_in0: endpoint {
2413 2288 remote-endpoint = <&funnel0_out>;
2414 }; 2289 };
2415 }; 2290 };
2416 2291
2417 port@1 { 2292 port@1 {
2418 reg = 2293 reg = <1>;
2419 merge 2294 merge_funnel_in1: endpoint {
2420 2295 remote-endpoint = <&funnel1_out>;
2421 }; 2296 };
2422 }; 2297 };
2423 }; 2298 };
2424 }; 2299 };
2425 2300
2426 replicator@6046000 { 2301 replicator@6046000 {
2427 compatible = "arm,cor 2302 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2428 reg = <0 0x06046000 0 2303 reg = <0 0x06046000 0 0x1000>;
2429 2304
2430 clocks = <&aoss_qmp>; 2305 clocks = <&aoss_qmp>;
2431 clock-names = "apb_pc 2306 clock-names = "apb_pclk";
2432 2307
2433 out-ports { 2308 out-ports {
2434 port { 2309 port {
2435 repli 2310 replicator_out: endpoint {
2436 2311 remote-endpoint = <&etr_in>;
2437 }; 2312 };
2438 }; 2313 };
2439 }; 2314 };
2440 2315
2441 in-ports { 2316 in-ports {
2442 port { 2317 port {
2443 repli 2318 replicator_in: endpoint {
2444 2319 remote-endpoint = <&swao_replicator_out>;
2445 }; 2320 };
2446 }; 2321 };
2447 }; 2322 };
2448 }; 2323 };
2449 2324
2450 etr@6048000 { 2325 etr@6048000 {
2451 compatible = "arm,cor 2326 compatible = "arm,coresight-tmc", "arm,primecell";
2452 reg = <0 0x06048000 0 2327 reg = <0 0x06048000 0 0x1000>;
2453 iommus = <&apps_smmu 2328 iommus = <&apps_smmu 0x04a0 0x20>;
2454 2329
2455 clocks = <&aoss_qmp>; 2330 clocks = <&aoss_qmp>;
2456 clock-names = "apb_pc 2331 clock-names = "apb_pclk";
2457 arm,scatter-gather; 2332 arm,scatter-gather;
2458 2333
2459 in-ports { 2334 in-ports {
2460 port { 2335 port {
2461 etr_i 2336 etr_in: endpoint {
2462 2337 remote-endpoint = <&replicator_out>;
2463 }; 2338 };
2464 }; 2339 };
2465 }; 2340 };
2466 }; 2341 };
2467 2342
2468 funnel@6b04000 { 2343 funnel@6b04000 {
2469 compatible = "arm,cor 2344 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2470 reg = <0 0x06b04000 0 2345 reg = <0 0x06b04000 0 0x1000>;
2471 2346
2472 clocks = <&aoss_qmp>; 2347 clocks = <&aoss_qmp>;
2473 clock-names = "apb_pc 2348 clock-names = "apb_pclk";
2474 2349
2475 out-ports { 2350 out-ports {
2476 port { 2351 port {
2477 swao_ 2352 swao_funnel_out: endpoint {
2478 2353 remote-endpoint = <&etf_in>;
2479 }; 2354 };
2480 }; 2355 };
2481 }; 2356 };
2482 2357
2483 in-ports { 2358 in-ports {
2484 #address-cell 2359 #address-cells = <1>;
2485 #size-cells = 2360 #size-cells = <0>;
2486 2361
2487 port@7 { 2362 port@7 {
2488 reg = 2363 reg = <7>;
2489 swao_ 2364 swao_funnel_in: endpoint {
2490 2365 remote-endpoint = <&merge_funnel_out>;
2491 }; 2366 };
2492 }; 2367 };
2493 }; 2368 };
2494 }; 2369 };
2495 2370
2496 etf@6b05000 { 2371 etf@6b05000 {
2497 compatible = "arm,cor 2372 compatible = "arm,coresight-tmc", "arm,primecell";
2498 reg = <0 0x06b05000 0 2373 reg = <0 0x06b05000 0 0x1000>;
2499 2374
2500 clocks = <&aoss_qmp>; 2375 clocks = <&aoss_qmp>;
2501 clock-names = "apb_pc 2376 clock-names = "apb_pclk";
2502 2377
2503 out-ports { 2378 out-ports {
2504 port { 2379 port {
2505 etf_o 2380 etf_out: endpoint {
2506 2381 remote-endpoint = <&swao_replicator_in>;
2507 }; 2382 };
2508 }; 2383 };
2509 }; 2384 };
2510 2385
2511 in-ports { 2386 in-ports {
2512 port { 2387 port {
2513 etf_i 2388 etf_in: endpoint {
2514 2389 remote-endpoint = <&swao_funnel_out>;
2515 }; 2390 };
2516 }; 2391 };
2517 }; 2392 };
2518 }; 2393 };
2519 2394
2520 replicator@6b06000 { 2395 replicator@6b06000 {
2521 compatible = "arm,cor 2396 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2522 reg = <0 0x06b06000 0 2397 reg = <0 0x06b06000 0 0x1000>;
2523 2398
2524 clocks = <&aoss_qmp>; 2399 clocks = <&aoss_qmp>;
2525 clock-names = "apb_pc 2400 clock-names = "apb_pclk";
2526 qcom,replicator-loses 2401 qcom,replicator-loses-context;
2527 2402
2528 out-ports { 2403 out-ports {
2529 port { 2404 port {
2530 swao_ 2405 swao_replicator_out: endpoint {
2531 2406 remote-endpoint = <&replicator_in>;
2532 }; 2407 };
2533 }; 2408 };
2534 }; 2409 };
2535 2410
2536 in-ports { 2411 in-ports {
2537 port { 2412 port {
2538 swao_ 2413 swao_replicator_in: endpoint {
2539 2414 remote-endpoint = <&etf_out>;
2540 }; 2415 };
2541 }; 2416 };
2542 }; 2417 };
2543 }; 2418 };
2544 2419
2545 etm@7040000 { 2420 etm@7040000 {
2546 compatible = "arm,cor 2421 compatible = "arm,coresight-etm4x", "arm,primecell";
2547 reg = <0 0x07040000 0 2422 reg = <0 0x07040000 0 0x1000>;
2548 2423
2549 cpu = <&CPU0>; 2424 cpu = <&CPU0>;
2550 2425
2551 clocks = <&aoss_qmp>; 2426 clocks = <&aoss_qmp>;
2552 clock-names = "apb_pc 2427 clock-names = "apb_pclk";
2553 arm,coresight-loses-c 2428 arm,coresight-loses-context-with-cpu;
2554 qcom,skip-power-up; 2429 qcom,skip-power-up;
2555 2430
2556 out-ports { 2431 out-ports {
2557 port { 2432 port {
2558 etm0_ 2433 etm0_out: endpoint {
2559 2434 remote-endpoint = <&apss_funnel_in0>;
2560 }; 2435 };
2561 }; 2436 };
2562 }; 2437 };
2563 }; 2438 };
2564 2439
2565 etm@7140000 { 2440 etm@7140000 {
2566 compatible = "arm,cor 2441 compatible = "arm,coresight-etm4x", "arm,primecell";
2567 reg = <0 0x07140000 0 2442 reg = <0 0x07140000 0 0x1000>;
2568 2443
2569 cpu = <&CPU1>; 2444 cpu = <&CPU1>;
2570 2445
2571 clocks = <&aoss_qmp>; 2446 clocks = <&aoss_qmp>;
2572 clock-names = "apb_pc 2447 clock-names = "apb_pclk";
2573 arm,coresight-loses-c 2448 arm,coresight-loses-context-with-cpu;
2574 qcom,skip-power-up; 2449 qcom,skip-power-up;
2575 2450
2576 out-ports { 2451 out-ports {
2577 port { 2452 port {
2578 etm1_ 2453 etm1_out: endpoint {
2579 2454 remote-endpoint = <&apss_funnel_in1>;
2580 }; 2455 };
2581 }; 2456 };
2582 }; 2457 };
2583 }; 2458 };
2584 2459
2585 etm@7240000 { 2460 etm@7240000 {
2586 compatible = "arm,cor 2461 compatible = "arm,coresight-etm4x", "arm,primecell";
2587 reg = <0 0x07240000 0 2462 reg = <0 0x07240000 0 0x1000>;
2588 2463
2589 cpu = <&CPU2>; 2464 cpu = <&CPU2>;
2590 2465
2591 clocks = <&aoss_qmp>; 2466 clocks = <&aoss_qmp>;
2592 clock-names = "apb_pc 2467 clock-names = "apb_pclk";
2593 arm,coresight-loses-c 2468 arm,coresight-loses-context-with-cpu;
2594 qcom,skip-power-up; 2469 qcom,skip-power-up;
2595 2470
2596 out-ports { 2471 out-ports {
2597 port { 2472 port {
2598 etm2_ 2473 etm2_out: endpoint {
2599 2474 remote-endpoint = <&apss_funnel_in2>;
2600 }; 2475 };
2601 }; 2476 };
2602 }; 2477 };
2603 }; 2478 };
2604 2479
2605 etm@7340000 { 2480 etm@7340000 {
2606 compatible = "arm,cor 2481 compatible = "arm,coresight-etm4x", "arm,primecell";
2607 reg = <0 0x07340000 0 2482 reg = <0 0x07340000 0 0x1000>;
2608 2483
2609 cpu = <&CPU3>; 2484 cpu = <&CPU3>;
2610 2485
2611 clocks = <&aoss_qmp>; 2486 clocks = <&aoss_qmp>;
2612 clock-names = "apb_pc 2487 clock-names = "apb_pclk";
2613 arm,coresight-loses-c 2488 arm,coresight-loses-context-with-cpu;
2614 qcom,skip-power-up; 2489 qcom,skip-power-up;
2615 2490
2616 out-ports { 2491 out-ports {
2617 port { 2492 port {
2618 etm3_ 2493 etm3_out: endpoint {
2619 2494 remote-endpoint = <&apss_funnel_in3>;
2620 }; 2495 };
2621 }; 2496 };
2622 }; 2497 };
2623 }; 2498 };
2624 2499
2625 etm@7440000 { 2500 etm@7440000 {
2626 compatible = "arm,cor 2501 compatible = "arm,coresight-etm4x", "arm,primecell";
2627 reg = <0 0x07440000 0 2502 reg = <0 0x07440000 0 0x1000>;
2628 2503
2629 cpu = <&CPU4>; 2504 cpu = <&CPU4>;
2630 2505
2631 clocks = <&aoss_qmp>; 2506 clocks = <&aoss_qmp>;
2632 clock-names = "apb_pc 2507 clock-names = "apb_pclk";
2633 arm,coresight-loses-c 2508 arm,coresight-loses-context-with-cpu;
2634 qcom,skip-power-up; 2509 qcom,skip-power-up;
2635 2510
2636 out-ports { 2511 out-ports {
2637 port { 2512 port {
2638 etm4_ 2513 etm4_out: endpoint {
2639 2514 remote-endpoint = <&apss_funnel_in4>;
2640 }; 2515 };
2641 }; 2516 };
2642 }; 2517 };
2643 }; 2518 };
2644 2519
2645 etm@7540000 { 2520 etm@7540000 {
2646 compatible = "arm,cor 2521 compatible = "arm,coresight-etm4x", "arm,primecell";
2647 reg = <0 0x07540000 0 2522 reg = <0 0x07540000 0 0x1000>;
2648 2523
2649 cpu = <&CPU5>; 2524 cpu = <&CPU5>;
2650 2525
2651 clocks = <&aoss_qmp>; 2526 clocks = <&aoss_qmp>;
2652 clock-names = "apb_pc 2527 clock-names = "apb_pclk";
2653 arm,coresight-loses-c 2528 arm,coresight-loses-context-with-cpu;
2654 qcom,skip-power-up; 2529 qcom,skip-power-up;
2655 2530
2656 out-ports { 2531 out-ports {
2657 port { 2532 port {
2658 etm5_ 2533 etm5_out: endpoint {
2659 2534 remote-endpoint = <&apss_funnel_in5>;
2660 }; 2535 };
2661 }; 2536 };
2662 }; 2537 };
2663 }; 2538 };
2664 2539
2665 etm@7640000 { 2540 etm@7640000 {
2666 compatible = "arm,cor 2541 compatible = "arm,coresight-etm4x", "arm,primecell";
2667 reg = <0 0x07640000 0 2542 reg = <0 0x07640000 0 0x1000>;
2668 2543
2669 cpu = <&CPU6>; 2544 cpu = <&CPU6>;
2670 2545
2671 clocks = <&aoss_qmp>; 2546 clocks = <&aoss_qmp>;
2672 clock-names = "apb_pc 2547 clock-names = "apb_pclk";
2673 arm,coresight-loses-c 2548 arm,coresight-loses-context-with-cpu;
2674 qcom,skip-power-up; 2549 qcom,skip-power-up;
2675 2550
2676 out-ports { 2551 out-ports {
2677 port { 2552 port {
2678 etm6_ 2553 etm6_out: endpoint {
2679 2554 remote-endpoint = <&apss_funnel_in6>;
2680 }; 2555 };
2681 }; 2556 };
2682 }; 2557 };
2683 }; 2558 };
2684 2559
2685 etm@7740000 { 2560 etm@7740000 {
2686 compatible = "arm,cor 2561 compatible = "arm,coresight-etm4x", "arm,primecell";
2687 reg = <0 0x07740000 0 2562 reg = <0 0x07740000 0 0x1000>;
2688 2563
2689 cpu = <&CPU7>; 2564 cpu = <&CPU7>;
2690 2565
2691 clocks = <&aoss_qmp>; 2566 clocks = <&aoss_qmp>;
2692 clock-names = "apb_pc 2567 clock-names = "apb_pclk";
2693 arm,coresight-loses-c 2568 arm,coresight-loses-context-with-cpu;
2694 qcom,skip-power-up; 2569 qcom,skip-power-up;
2695 2570
2696 out-ports { 2571 out-ports {
2697 port { 2572 port {
2698 etm7_ 2573 etm7_out: endpoint {
2699 2574 remote-endpoint = <&apss_funnel_in7>;
2700 }; 2575 };
2701 }; 2576 };
2702 }; 2577 };
2703 }; 2578 };
2704 2579
2705 funnel@7800000 { /* APSS Funn 2580 funnel@7800000 { /* APSS Funnel */
2706 compatible = "arm,cor 2581 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2707 reg = <0 0x07800000 0 2582 reg = <0 0x07800000 0 0x1000>;
2708 2583
2709 clocks = <&aoss_qmp>; 2584 clocks = <&aoss_qmp>;
2710 clock-names = "apb_pc 2585 clock-names = "apb_pclk";
2711 2586
2712 out-ports { 2587 out-ports {
2713 port { 2588 port {
2714 apss_ 2589 apss_funnel_out: endpoint {
2715 2590 remote-endpoint = <&apss_merge_funnel_in>;
2716 }; 2591 };
2717 }; 2592 };
2718 }; 2593 };
2719 2594
2720 in-ports { 2595 in-ports {
2721 #address-cell 2596 #address-cells = <1>;
2722 #size-cells = 2597 #size-cells = <0>;
2723 2598
2724 port@0 { 2599 port@0 {
2725 reg = 2600 reg = <0>;
2726 apss_ 2601 apss_funnel_in0: endpoint {
2727 2602 remote-endpoint = <&etm0_out>;
2728 }; 2603 };
2729 }; 2604 };
2730 2605
2731 port@1 { 2606 port@1 {
2732 reg = 2607 reg = <1>;
2733 apss_ 2608 apss_funnel_in1: endpoint {
2734 2609 remote-endpoint = <&etm1_out>;
2735 }; 2610 };
2736 }; 2611 };
2737 2612
2738 port@2 { 2613 port@2 {
2739 reg = 2614 reg = <2>;
2740 apss_ 2615 apss_funnel_in2: endpoint {
2741 2616 remote-endpoint = <&etm2_out>;
2742 }; 2617 };
2743 }; 2618 };
2744 2619
2745 port@3 { 2620 port@3 {
2746 reg = 2621 reg = <3>;
2747 apss_ 2622 apss_funnel_in3: endpoint {
2748 2623 remote-endpoint = <&etm3_out>;
2749 }; 2624 };
2750 }; 2625 };
2751 2626
2752 port@4 { 2627 port@4 {
2753 reg = 2628 reg = <4>;
2754 apss_ 2629 apss_funnel_in4: endpoint {
2755 2630 remote-endpoint = <&etm4_out>;
2756 }; 2631 };
2757 }; 2632 };
2758 2633
2759 port@5 { 2634 port@5 {
2760 reg = 2635 reg = <5>;
2761 apss_ 2636 apss_funnel_in5: endpoint {
2762 2637 remote-endpoint = <&etm5_out>;
2763 }; 2638 };
2764 }; 2639 };
2765 2640
2766 port@6 { 2641 port@6 {
2767 reg = 2642 reg = <6>;
2768 apss_ 2643 apss_funnel_in6: endpoint {
2769 2644 remote-endpoint = <&etm6_out>;
2770 }; 2645 };
2771 }; 2646 };
2772 2647
2773 port@7 { 2648 port@7 {
2774 reg = 2649 reg = <7>;
2775 apss_ 2650 apss_funnel_in7: endpoint {
2776 2651 remote-endpoint = <&etm7_out>;
2777 }; 2652 };
2778 }; 2653 };
2779 }; 2654 };
2780 }; 2655 };
2781 2656
2782 funnel@7810000 { 2657 funnel@7810000 {
2783 compatible = "arm,cor 2658 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2784 reg = <0 0x07810000 0 2659 reg = <0 0x07810000 0 0x1000>;
2785 2660
2786 clocks = <&aoss_qmp>; 2661 clocks = <&aoss_qmp>;
2787 clock-names = "apb_pc 2662 clock-names = "apb_pclk";
2788 2663
2789 out-ports { 2664 out-ports {
2790 port { 2665 port {
2791 apss_ 2666 apss_merge_funnel_out: endpoint {
2792 2667 remote-endpoint = <&funnel1_in4>;
2793 }; 2668 };
2794 }; 2669 };
2795 }; 2670 };
2796 2671
2797 in-ports { 2672 in-ports {
2798 port { 2673 port {
2799 apss_ 2674 apss_merge_funnel_in: endpoint {
2800 2675 remote-endpoint = <&apss_funnel_out>;
2801 }; 2676 };
2802 }; 2677 };
2803 }; 2678 };
2804 }; 2679 };
2805 2680
2806 sdhc_2: mmc@8804000 { !! 2681 sdhc_2: sdhci@8804000 {
2807 compatible = "qcom,sc 2682 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
2808 reg = <0 0x08804000 0 2683 reg = <0 0x08804000 0 0x1000>;
2809 2684
2810 iommus = <&apps_smmu 2685 iommus = <&apps_smmu 0x80 0>;
2811 interrupts = <GIC_SPI 2686 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
2812 <GIC_ 2687 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
2813 interrupt-names = "hc 2688 interrupt-names = "hc_irq", "pwr_irq";
2814 2689
2815 clocks = <&gcc GCC_SD !! 2690 clocks = <&gcc GCC_SDCC2_APPS_CLK>,
2816 <&gcc GCC_SD !! 2691 <&gcc GCC_SDCC2_AHB_CLK>;
2817 <&rpmhcc RPM !! 2692 clock-names = "core", "iface";
2818 clock-names = "iface" <<
2819 2693
2820 interconnects = <&agg 2694 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
2821 <&gem 2695 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
2822 interconnect-names = 2696 interconnect-names = "sdhc-ddr","cpu-sdhc";
2823 power-domains = <&rpm 2697 power-domains = <&rpmhpd SC7180_CX>;
2824 operating-points-v2 = 2698 operating-points-v2 = <&sdhc2_opp_table>;
2825 2699
2826 bus-width = <4>; 2700 bus-width = <4>;
2827 2701
2828 status = "disabled"; 2702 status = "disabled";
2829 2703
2830 sdhc2_opp_table: opp- !! 2704 sdhc2_opp_table: sdhc2-opp-table {
2831 compatible = 2705 compatible = "operating-points-v2";
2832 2706
2833 opp-100000000 2707 opp-100000000 {
2834 opp-h 2708 opp-hz = /bits/ 64 <100000000>;
2835 requi 2709 required-opps = <&rpmhpd_opp_low_svs>;
2836 opp-p !! 2710 opp-peak-kBps = <160000 100000>;
2837 opp-a !! 2711 opp-avg-kBps = <80000 50000>;
2838 }; 2712 };
2839 2713
2840 opp-202000000 2714 opp-202000000 {
2841 opp-h 2715 opp-hz = /bits/ 64 <202000000>;
2842 requi !! 2716 required-opps = <&rpmhpd_opp_svs_l1>;
2843 opp-p !! 2717 opp-peak-kBps = <200000 120000>;
2844 opp-a !! 2718 opp-avg-kBps = <100000 60000>;
2845 }; 2719 };
2846 }; 2720 };
2847 }; 2721 };
2848 2722
>> 2723 qspi_opp_table: qspi-opp-table {
>> 2724 compatible = "operating-points-v2";
>> 2725
>> 2726 opp-75000000 {
>> 2727 opp-hz = /bits/ 64 <75000000>;
>> 2728 required-opps = <&rpmhpd_opp_low_svs>;
>> 2729 };
>> 2730
>> 2731 opp-150000000 {
>> 2732 opp-hz = /bits/ 64 <150000000>;
>> 2733 required-opps = <&rpmhpd_opp_svs>;
>> 2734 };
>> 2735
>> 2736 opp-300000000 {
>> 2737 opp-hz = /bits/ 64 <300000000>;
>> 2738 required-opps = <&rpmhpd_opp_nom>;
>> 2739 };
>> 2740 };
>> 2741
2849 qspi: spi@88dc000 { 2742 qspi: spi@88dc000 {
2850 compatible = "qcom,sc !! 2743 compatible = "qcom,qspi-v1";
2851 reg = <0 0x088dc000 0 2744 reg = <0 0x088dc000 0 0x600>;
2852 iommus = <&apps_smmu <<
2853 #address-cells = <1>; 2745 #address-cells = <1>;
2854 #size-cells = <0>; 2746 #size-cells = <0>;
2855 interrupts = <GIC_SPI 2747 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
2856 clocks = <&gcc GCC_QS 2748 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
2857 <&gcc GCC_QS 2749 <&gcc GCC_QSPI_CORE_CLK>;
2858 clock-names = "iface" 2750 clock-names = "iface", "core";
2859 interconnects = <&gem 2751 interconnects = <&gem_noc MASTER_APPSS_PROC 0
2860 &conf 2752 &config_noc SLAVE_QSPI_0 0>;
2861 interconnect-names = 2753 interconnect-names = "qspi-config";
2862 power-domains = <&rpm 2754 power-domains = <&rpmhpd SC7180_CX>;
2863 operating-points-v2 = 2755 operating-points-v2 = <&qspi_opp_table>;
2864 status = "disabled"; 2756 status = "disabled";
2865 }; 2757 };
2866 2758
2867 usb_1_hsphy: phy@88e3000 { 2759 usb_1_hsphy: phy@88e3000 {
2868 compatible = "qcom,sc 2760 compatible = "qcom,sc7180-qusb2-phy", "qcom,qusb2-v2-phy";
2869 reg = <0 0x088e3000 0 2761 reg = <0 0x088e3000 0 0x400>;
2870 status = "disabled"; 2762 status = "disabled";
2871 #phy-cells = <0>; 2763 #phy-cells = <0>;
2872 clocks = <&gcc GCC_US 2764 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2873 <&rpmhcc RPM 2765 <&rpmhcc RPMH_CXO_CLK>;
2874 clock-names = "cfg_ah 2766 clock-names = "cfg_ahb", "ref";
2875 resets = <&gcc GCC_QU 2767 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2876 2768
2877 nvmem-cells = <&qusb2 2769 nvmem-cells = <&qusb2p_hstx_trim>;
2878 }; 2770 };
2879 2771
2880 usb_1_qmpphy: phy@88e8000 { !! 2772 usb_1_qmpphy: phy-wrapper@88e9000 {
2881 compatible = "qcom,sc !! 2773 compatible = "qcom,sc7180-qmp-usb3-phy";
2882 reg = <0 0x088e8000 0 !! 2774 reg = <0 0x088e9000 0 0x18c>,
>> 2775 <0 0x088e8000 0 0x38>;
>> 2776 reg-names = "reg-base", "dp_com";
2883 status = "disabled"; 2777 status = "disabled";
>> 2778 #clock-cells = <1>;
>> 2779 #address-cells = <2>;
>> 2780 #size-cells = <2>;
>> 2781 ranges;
2884 2782
2885 clocks = <&gcc GCC_US 2783 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
>> 2784 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2886 <&gcc GCC_US 2785 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
2887 <&gcc GCC_US !! 2786 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
2888 <&gcc GCC_US !! 2787 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
2889 <&gcc GCC_US <<
2890 clock-names = "aux", <<
2891 "ref", <<
2892 "com_au <<
2893 "usb3_p <<
2894 "cfg_ah <<
2895 2788
2896 resets = <&gcc GCC_US 2789 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
2897 <&gcc GCC_US 2790 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
2898 reset-names = "phy", 2791 reset-names = "phy", "common";
2899 2792
2900 #clock-cells = <1>; !! 2793 usb_1_ssphy: phy@88e9200 {
2901 #phy-cells = <1>; !! 2794 reg = <0 0x088e9200 0 0x128>,
2902 }; !! 2795 <0 0x088e9400 0 0x200>,
2903 !! 2796 <0 0x088e9c00 0 0x218>,
2904 pmu@90b6300 { !! 2797 <0 0x088e9600 0 0x128>,
2905 compatible = "qcom,sc !! 2798 <0 0x088e9800 0 0x200>,
2906 reg = <0 0x090b6300 0 !! 2799 <0 0x088e9a00 0 0x18>;
2907 interrupts = <GIC_SPI !! 2800 #clock-cells = <0>;
2908 !! 2801 #phy-cells = <0>;
2909 interconnects = <&gem !! 2802 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2910 &gem !! 2803 clock-names = "pipe0";
2911 operating-points-v2 = !! 2804 clock-output-names = "usb3_phy_pipe_clk_src";
2912 <<
2913 cpu_bwmon_opp_table: <<
2914 compatible = <<
2915 <<
2916 opp-0 { <<
2917 opp-p <<
2918 }; <<
2919 <<
2920 opp-1 { <<
2921 opp-p <<
2922 }; <<
2923 <<
2924 opp-2 { <<
2925 opp-p <<
2926 }; <<
2927 <<
2928 opp-3 { <<
2929 opp-p <<
2930 }; <<
2931 <<
2932 opp-4 { <<
2933 opp-p <<
2934 }; <<
2935 <<
2936 opp-5 { <<
2937 opp-p <<
2938 }; <<
2939 }; <<
2940 }; <<
2941 <<
2942 pmu@90cd000 { <<
2943 compatible = "qcom,sc <<
2944 reg = <0 0x090cd000 0 <<
2945 interrupts = <GIC_SPI <<
2946 <<
2947 interconnects = <&mc_ <<
2948 &mc_ <<
2949 operating-points-v2 = <<
2950 <<
2951 llcc_bwmon_opp_table: <<
2952 compatible = <<
2953 <<
2954 opp-0 { <<
2955 opp-p <<
2956 }; <<
2957 <<
2958 opp-1 { <<
2959 opp-p <<
2960 }; <<
2961 <<
2962 opp-2 { <<
2963 opp-p <<
2964 }; <<
2965 <<
2966 opp-3 { <<
2967 opp-p <<
2968 }; <<
2969 <<
2970 opp-4 { <<
2971 opp-p <<
2972 }; <<
2973 <<
2974 opp-5 { <<
2975 opp-p <<
2976 }; <<
2977 <<
2978 opp-6 { <<
2979 opp-p <<
2980 }; <<
2981 <<
2982 opp-7 { <<
2983 opp-p <<
2984 }; <<
2985 }; 2805 };
2986 }; 2806 };
2987 2807
2988 dc_noc: interconnect@9160000 2808 dc_noc: interconnect@9160000 {
2989 compatible = "qcom,sc 2809 compatible = "qcom,sc7180-dc-noc";
2990 reg = <0 0x09160000 0 2810 reg = <0 0x09160000 0 0x03200>;
2991 #interconnect-cells = 2811 #interconnect-cells = <2>;
2992 qcom,bcm-voters = <&a 2812 qcom,bcm-voters = <&apps_bcm_voter>;
2993 }; 2813 };
2994 2814
2995 system-cache-controller@92000 2815 system-cache-controller@9200000 {
2996 compatible = "qcom,sc 2816 compatible = "qcom,sc7180-llcc";
2997 reg = <0 0x09200000 0 2817 reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>;
2998 reg-names = "llcc0_ba !! 2818 reg-names = "llcc_base", "llcc_broadcast_base";
2999 interrupts = <GIC_SPI 2819 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
3000 }; 2820 };
3001 2821
3002 gem_noc: interconnect@9680000 2822 gem_noc: interconnect@9680000 {
3003 compatible = "qcom,sc 2823 compatible = "qcom,sc7180-gem-noc";
3004 reg = <0 0x09680000 0 2824 reg = <0 0x09680000 0 0x3e200>;
3005 #interconnect-cells = 2825 #interconnect-cells = <2>;
3006 qcom,bcm-voters = <&a 2826 qcom,bcm-voters = <&apps_bcm_voter>;
3007 }; 2827 };
3008 2828
3009 npu_noc: interconnect@9990000 2829 npu_noc: interconnect@9990000 {
3010 compatible = "qcom,sc 2830 compatible = "qcom,sc7180-npu-noc";
3011 reg = <0 0x09990000 0 2831 reg = <0 0x09990000 0 0x1600>;
3012 #interconnect-cells = 2832 #interconnect-cells = <2>;
3013 qcom,bcm-voters = <&a 2833 qcom,bcm-voters = <&apps_bcm_voter>;
3014 }; 2834 };
3015 2835
3016 usb_1: usb@a6f8800 { 2836 usb_1: usb@a6f8800 {
3017 compatible = "qcom,sc 2837 compatible = "qcom,sc7180-dwc3", "qcom,dwc3";
3018 reg = <0 0x0a6f8800 0 2838 reg = <0 0x0a6f8800 0 0x400>;
3019 status = "disabled"; 2839 status = "disabled";
3020 #address-cells = <2>; 2840 #address-cells = <2>;
3021 #size-cells = <2>; 2841 #size-cells = <2>;
3022 ranges; 2842 ranges;
3023 dma-ranges; 2843 dma-ranges;
3024 2844
3025 clocks = <&gcc GCC_CF 2845 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
3026 <&gcc GCC_US 2846 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
3027 <&gcc GCC_AG 2847 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
3028 <&gcc GCC_US !! 2848 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3029 <&gcc GCC_US !! 2849 <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
3030 clock-names = "cfg_no !! 2850 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
3031 "core", !! 2851 "sleep";
3032 "iface" <<
3033 "sleep" <<
3034 "mock_u <<
3035 2852
3036 assigned-clocks = <&g 2853 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3037 <&g 2854 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
3038 assigned-clock-rates 2855 assigned-clock-rates = <19200000>, <150000000>;
3039 2856
3040 interrupts-extended = !! 2857 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
3041 !! 2858 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
3042 !! 2859 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
3043 !! 2860 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
3044 !! 2861 interrupt-names = "hs_phy_irq", "ss_phy_irq",
3045 interrupt-names = "pw !! 2862 "dm_hs_phy_irq", "dp_hs_phy_irq";
3046 "hs <<
3047 "dp <<
3048 "dm <<
3049 "ss <<
3050 2863
3051 power-domains = <&gcc 2864 power-domains = <&gcc USB30_PRIM_GDSC>;
3052 required-opps = <&rpm <<
3053 2865
3054 resets = <&gcc GCC_US 2866 resets = <&gcc GCC_USB30_PRIM_BCR>;
3055 2867
3056 interconnects = <&agg 2868 interconnects = <&aggre2_noc MASTER_USB3 0 &mc_virt SLAVE_EBI1 0>,
3057 <&gem 2869 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3 0>;
3058 interconnect-names = 2870 interconnect-names = "usb-ddr", "apps-usb";
3059 2871
3060 wakeup-source; !! 2872 usb_1_dwc3: dwc3@a600000 {
3061 <<
3062 usb_1_dwc3: usb@a6000 <<
3063 compatible = 2873 compatible = "snps,dwc3";
3064 reg = <0 0x0a 2874 reg = <0 0x0a600000 0 0xe000>;
3065 interrupts = 2875 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
3066 iommus = <&ap 2876 iommus = <&apps_smmu 0x540 0>;
3067 snps,dis_u2_s 2877 snps,dis_u2_susphy_quirk;
3068 snps,dis_enbl 2878 snps,dis_enblslpm_quirk;
3069 snps,parkmode !! 2879 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
3070 phys = <&usb_ <<
3071 phy-names = " 2880 phy-names = "usb2-phy", "usb3-phy";
3072 maximum-speed 2881 maximum-speed = "super-speed";
3073 }; 2882 };
3074 }; 2883 };
3075 2884
3076 venus: video-codec@aa00000 { 2885 venus: video-codec@aa00000 {
3077 compatible = "qcom,sc 2886 compatible = "qcom,sc7180-venus";
3078 reg = <0 0x0aa00000 0 2887 reg = <0 0x0aa00000 0 0xff000>;
3079 interrupts = <GIC_SPI 2888 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
3080 power-domains = <&vid 2889 power-domains = <&videocc VENUS_GDSC>,
3081 <&vid 2890 <&videocc VCODEC0_GDSC>,
3082 <&rpm 2891 <&rpmhpd SC7180_CX>;
3083 power-domain-names = 2892 power-domain-names = "venus", "vcodec0", "cx";
3084 operating-points-v2 = 2893 operating-points-v2 = <&venus_opp_table>;
3085 clocks = <&videocc VI 2894 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
3086 <&videocc VI 2895 <&videocc VIDEO_CC_VENUS_AHB_CLK>,
3087 <&videocc VI 2896 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>,
3088 <&videocc VI 2897 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
3089 <&videocc VI 2898 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>;
3090 clock-names = "core", 2899 clock-names = "core", "iface", "bus",
3091 "vcodec 2900 "vcodec0_core", "vcodec0_bus";
3092 iommus = <&apps_smmu 2901 iommus = <&apps_smmu 0x0c00 0x60>;
3093 memory-region = <&ven 2902 memory-region = <&venus_mem>;
3094 interconnects = <&mms 2903 interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>,
3095 <&gem 2904 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>;
3096 interconnect-names = 2905 interconnect-names = "video-mem", "cpu-cfg";
3097 2906
3098 video-decoder { 2907 video-decoder {
3099 compatible = 2908 compatible = "venus-decoder";
3100 }; 2909 };
3101 2910
3102 video-encoder { 2911 video-encoder {
3103 compatible = 2912 compatible = "venus-encoder";
3104 }; 2913 };
3105 2914
3106 venus_opp_table: opp- !! 2915 venus_opp_table: venus-opp-table {
3107 compatible = 2916 compatible = "operating-points-v2";
3108 2917
3109 opp-150000000 2918 opp-150000000 {
3110 opp-h 2919 opp-hz = /bits/ 64 <150000000>;
3111 requi 2920 required-opps = <&rpmhpd_opp_low_svs>;
3112 }; 2921 };
3113 2922
3114 opp-270000000 2923 opp-270000000 {
3115 opp-h 2924 opp-hz = /bits/ 64 <270000000>;
3116 requi 2925 required-opps = <&rpmhpd_opp_svs>;
3117 }; 2926 };
3118 2927
3119 opp-340000000 2928 opp-340000000 {
3120 opp-h 2929 opp-hz = /bits/ 64 <340000000>;
3121 requi 2930 required-opps = <&rpmhpd_opp_svs_l1>;
3122 }; 2931 };
3123 2932
3124 opp-434000000 2933 opp-434000000 {
3125 opp-h 2934 opp-hz = /bits/ 64 <434000000>;
3126 requi 2935 required-opps = <&rpmhpd_opp_nom>;
3127 }; 2936 };
3128 2937
3129 opp-500000097 2938 opp-500000097 {
3130 opp-h 2939 opp-hz = /bits/ 64 <500000097>;
3131 requi 2940 required-opps = <&rpmhpd_opp_turbo>;
3132 }; 2941 };
3133 }; 2942 };
3134 }; 2943 };
3135 2944
3136 videocc: clock-controller@ab0 2945 videocc: clock-controller@ab00000 {
3137 compatible = "qcom,sc 2946 compatible = "qcom,sc7180-videocc";
3138 reg = <0 0x0ab00000 0 2947 reg = <0 0x0ab00000 0 0x10000>;
3139 clocks = <&rpmhcc RPM 2948 clocks = <&rpmhcc RPMH_CXO_CLK>;
3140 clock-names = "bi_tcx 2949 clock-names = "bi_tcxo";
3141 #clock-cells = <1>; 2950 #clock-cells = <1>;
3142 #reset-cells = <1>; 2951 #reset-cells = <1>;
3143 #power-domain-cells = 2952 #power-domain-cells = <1>;
3144 }; 2953 };
3145 2954
3146 camnoc_virt: interconnect@ac0 2955 camnoc_virt: interconnect@ac00000 {
3147 compatible = "qcom,sc 2956 compatible = "qcom,sc7180-camnoc-virt";
3148 reg = <0 0x0ac00000 0 2957 reg = <0 0x0ac00000 0 0x1000>;
3149 #interconnect-cells = 2958 #interconnect-cells = <2>;
3150 qcom,bcm-voters = <&a 2959 qcom,bcm-voters = <&apps_bcm_voter>;
3151 }; 2960 };
3152 2961
3153 camcc: clock-controller@ad000 2962 camcc: clock-controller@ad00000 {
3154 compatible = "qcom,sc 2963 compatible = "qcom,sc7180-camcc";
3155 reg = <0 0x0ad00000 0 2964 reg = <0 0x0ad00000 0 0x10000>;
3156 clocks = <&rpmhcc RPM 2965 clocks = <&rpmhcc RPMH_CXO_CLK>,
3157 <&gcc GCC_CAME 2966 <&gcc GCC_CAMERA_AHB_CLK>,
3158 <&gcc GCC_CAME 2967 <&gcc GCC_CAMERA_XO_CLK>;
3159 clock-names = "bi_tcx 2968 clock-names = "bi_tcxo", "iface", "xo";
3160 #clock-cells = <1>; 2969 #clock-cells = <1>;
3161 #reset-cells = <1>; 2970 #reset-cells = <1>;
3162 #power-domain-cells = 2971 #power-domain-cells = <1>;
3163 }; 2972 };
3164 2973
3165 mdss: display-subsystem@ae000 !! 2974 mdss: mdss@ae00000 {
3166 compatible = "qcom,sc 2975 compatible = "qcom,sc7180-mdss";
3167 reg = <0 0x0ae00000 0 2976 reg = <0 0x0ae00000 0 0x1000>;
3168 reg-names = "mdss"; 2977 reg-names = "mdss";
3169 2978
3170 power-domains = <&dis 2979 power-domains = <&dispcc MDSS_GDSC>;
3171 2980
3172 clocks = <&gcc GCC_DI 2981 clocks = <&gcc GCC_DISP_AHB_CLK>,
3173 <&dispcc DIS 2982 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3174 <&dispcc DIS 2983 <&dispcc DISP_CC_MDSS_MDP_CLK>;
3175 clock-names = "iface" 2984 clock-names = "iface", "ahb", "core";
3176 2985
>> 2986 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
>> 2987 assigned-clock-rates = <300000000>;
>> 2988
3177 interrupts = <GIC_SPI 2989 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
3178 interrupt-controller; 2990 interrupt-controller;
3179 #interrupt-cells = <1 2991 #interrupt-cells = <1>;
3180 2992
3181 interconnects = <&mms !! 2993 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>;
3182 &mc_ !! 2994 interconnect-names = "mdp0-mem";
3183 <&gem <<
3184 &con <<
3185 interconnect-names = <<
3186 <<
3187 2995
3188 iommus = <&apps_smmu 2996 iommus = <&apps_smmu 0x800 0x2>;
3189 2997
3190 #address-cells = <2>; 2998 #address-cells = <2>;
3191 #size-cells = <2>; 2999 #size-cells = <2>;
3192 ranges; 3000 ranges;
3193 3001
3194 status = "disabled"; 3002 status = "disabled";
3195 3003
3196 mdp: display-controll !! 3004 mdp: mdp@ae01000 {
3197 compatible = 3005 compatible = "qcom,sc7180-dpu";
3198 reg = <0 0x0a 3006 reg = <0 0x0ae01000 0 0x8f000>,
3199 <0 0x0a 3007 <0 0x0aeb0000 0 0x2008>;
3200 reg-names = " 3008 reg-names = "mdp", "vbif";
3201 3009
3202 clocks = <&gc 3010 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
3203 <&di 3011 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3204 <&di 3012 <&dispcc DISP_CC_MDSS_ROT_CLK>,
3205 <&di 3013 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
3206 <&di 3014 <&dispcc DISP_CC_MDSS_MDP_CLK>,
3207 <&di 3015 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3208 clock-names = 3016 clock-names = "bus", "iface", "rot", "lut", "core",
3209 3017 "vsync";
3210 assigned-cloc !! 3018 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
>> 3019 <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
3211 3020 <&dispcc DISP_CC_MDSS_ROT_CLK>,
3212 3021 <&dispcc DISP_CC_MDSS_AHB_CLK>;
3213 assigned-cloc !! 3022 assigned-clock-rates = <300000000>,
>> 3023 <19200000>,
3214 3024 <19200000>,
3215 3025 <19200000>;
3216 operating-poi 3026 operating-points-v2 = <&mdp_opp_table>;
3217 power-domains 3027 power-domains = <&rpmhpd SC7180_CX>;
3218 3028
3219 interrupt-par 3029 interrupt-parent = <&mdss>;
3220 interrupts = 3030 interrupts = <0>;
3221 3031
>> 3032 status = "disabled";
>> 3033
3222 ports { 3034 ports {
3223 #addr 3035 #address-cells = <1>;
3224 #size 3036 #size-cells = <0>;
3225 3037
3226 port@ 3038 port@0 {
3227 3039 reg = <0>;
3228 3040 dpu_intf1_out: endpoint {
3229 !! 3041 remote-endpoint = <&dsi0_in>;
3230 <<
3231 }; <<
3232 <<
3233 port@ <<
3234 <<
3235 <<
3236 <<
3237 3042 };
3238 }; 3043 };
3239 }; 3044 };
3240 3045
3241 mdp_opp_table !! 3046 mdp_opp_table: mdp-opp-table {
3242 compa 3047 compatible = "operating-points-v2";
3243 3048
3244 opp-2 3049 opp-200000000 {
3245 3050 opp-hz = /bits/ 64 <200000000>;
3246 3051 required-opps = <&rpmhpd_opp_low_svs>;
3247 }; 3052 };
3248 3053
3249 opp-3 3054 opp-300000000 {
3250 3055 opp-hz = /bits/ 64 <300000000>;
3251 3056 required-opps = <&rpmhpd_opp_svs>;
3252 }; 3057 };
3253 3058
3254 opp-3 3059 opp-345000000 {
3255 3060 opp-hz = /bits/ 64 <345000000>;
3256 3061 required-opps = <&rpmhpd_opp_svs_l1>;
3257 }; 3062 };
3258 3063
3259 opp-4 3064 opp-460000000 {
3260 3065 opp-hz = /bits/ 64 <460000000>;
3261 3066 required-opps = <&rpmhpd_opp_nom>;
3262 }; 3067 };
3263 }; 3068 };
>> 3069
3264 }; 3070 };
3265 3071
3266 mdss_dsi0: dsi@ae9400 !! 3072 dsi0: dsi@ae94000 {
3267 compatible = !! 3073 compatible = "qcom,mdss-dsi-ctrl";
3268 <<
3269 reg = <0 0x0a 3074 reg = <0 0x0ae94000 0 0x400>;
3270 reg-names = " 3075 reg-names = "dsi_ctrl";
3271 3076
3272 interrupt-par 3077 interrupt-parent = <&mdss>;
3273 interrupts = 3078 interrupts = <4>;
3274 3079
3275 clocks = <&di 3080 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
3276 <&di 3081 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
3277 <&di 3082 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
3278 <&di 3083 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
3279 <&di 3084 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3280 <&gc 3085 <&gcc GCC_DISP_HF_AXI_CLK>;
3281 clock-names = 3086 clock-names = "byte",
3282 3087 "byte_intf",
3283 3088 "pixel",
3284 3089 "core",
3285 3090 "iface",
3286 3091 "bus";
3287 3092
3288 assigned-cloc <<
3289 assigned-cloc <<
3290 <<
3291 operating-poi 3093 operating-points-v2 = <&dsi_opp_table>;
3292 power-domains 3094 power-domains = <&rpmhpd SC7180_CX>;
3293 3095
3294 phys = <&mdss !! 3096 phys = <&dsi_phy>;
>> 3097 phy-names = "dsi";
3295 3098
3296 #address-cell 3099 #address-cells = <1>;
3297 #size-cells = 3100 #size-cells = <0>;
3298 3101
3299 status = "dis 3102 status = "disabled";
3300 3103
3301 ports { 3104 ports {
3302 #addr 3105 #address-cells = <1>;
3303 #size 3106 #size-cells = <0>;
3304 3107
3305 port@ 3108 port@0 {
3306 3109 reg = <0>;
3307 !! 3110 dsi0_in: endpoint {
3308 3111 remote-endpoint = <&dpu_intf1_out>;
3309 3112 };
3310 }; 3113 };
3311 3114
3312 port@ 3115 port@1 {
3313 3116 reg = <1>;
3314 !! 3117 dsi0_out: endpoint {
3315 3118 };
3316 }; 3119 };
3317 }; 3120 };
3318 3121
3319 dsi_opp_table !! 3122 dsi_opp_table: dsi-opp-table {
3320 compa 3123 compatible = "operating-points-v2";
3321 3124
3322 opp-1 3125 opp-187500000 {
3323 3126 opp-hz = /bits/ 64 <187500000>;
3324 3127 required-opps = <&rpmhpd_opp_low_svs>;
3325 }; 3128 };
3326 3129
3327 opp-3 3130 opp-300000000 {
3328 3131 opp-hz = /bits/ 64 <300000000>;
3329 3132 required-opps = <&rpmhpd_opp_svs>;
3330 }; 3133 };
3331 3134
3332 opp-3 3135 opp-358000000 {
3333 3136 opp-hz = /bits/ 64 <358000000>;
3334 3137 required-opps = <&rpmhpd_opp_svs_l1>;
3335 }; 3138 };
3336 }; 3139 };
3337 }; 3140 };
3338 3141
3339 mdss_dsi0_phy: phy@ae !! 3142 dsi_phy: dsi-phy@ae94400 {
3340 compatible = 3143 compatible = "qcom,dsi-phy-10nm";
3341 reg = <0 0x0a 3144 reg = <0 0x0ae94400 0 0x200>,
3342 <0 0x0a 3145 <0 0x0ae94600 0 0x280>,
3343 <0 0x0a 3146 <0 0x0ae94a00 0 0x1e0>;
3344 reg-names = " 3147 reg-names = "dsi_phy",
3345 " 3148 "dsi_phy_lane",
3346 " 3149 "dsi_pll";
3347 3150
3348 #clock-cells 3151 #clock-cells = <1>;
3349 #phy-cells = 3152 #phy-cells = <0>;
3350 3153
3351 clocks = <&di 3154 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3352 <&rp 3155 <&rpmhcc RPMH_CXO_CLK>;
3353 clock-names = 3156 clock-names = "iface", "ref";
3354 3157
3355 status = "dis 3158 status = "disabled";
3356 }; 3159 };
3357 <<
3358 mdss_dp: displayport- <<
3359 compatible = <<
3360 status = "dis <<
3361 <<
3362 reg = <0 0x0a <<
3363 <0 0x0a <<
3364 <0 0x0a <<
3365 <0 0x0a <<
3366 <0 0x0a <<
3367 <<
3368 interrupt-par <<
3369 interrupts = <<
3370 <<
3371 clocks = <&di <<
3372 <&di <<
3373 <&di <<
3374 <&di <<
3375 <&di <<
3376 clock-names = <<
3377 <<
3378 assigned-cloc <<
3379 <<
3380 assigned-cloc <<
3381 <<
3382 phys = <&usb_ <<
3383 phy-names = " <<
3384 <<
3385 operating-poi <<
3386 power-domains <<
3387 <<
3388 #sound-dai-ce <<
3389 <<
3390 ports { <<
3391 #addr <<
3392 #size <<
3393 port@ <<
3394 <<
3395 <<
3396 <<
3397 <<
3398 }; <<
3399 <<
3400 port@ <<
3401 <<
3402 <<
3403 }; <<
3404 }; <<
3405 <<
3406 dp_opp_table: <<
3407 compa <<
3408 <<
3409 opp-1 <<
3410 <<
3411 <<
3412 }; <<
3413 <<
3414 opp-2 <<
3415 <<
3416 <<
3417 }; <<
3418 <<
3419 opp-5 <<
3420 <<
3421 <<
3422 }; <<
3423 <<
3424 opp-8 <<
3425 <<
3426 <<
3427 }; <<
3428 }; <<
3429 }; <<
3430 }; 3160 };
3431 3161
3432 dispcc: clock-controller@af00 3162 dispcc: clock-controller@af00000 {
3433 compatible = "qcom,sc 3163 compatible = "qcom,sc7180-dispcc";
3434 reg = <0 0x0af00000 0 3164 reg = <0 0x0af00000 0 0x200000>;
3435 clocks = <&rpmhcc RPM 3165 clocks = <&rpmhcc RPMH_CXO_CLK>,
3436 <&gcc GCC_DI 3166 <&gcc GCC_DISP_GPLL0_CLK_SRC>,
3437 <&mdss_dsi0_ !! 3167 <&dsi_phy 0>,
3438 <&mdss_dsi0_ !! 3168 <&dsi_phy 1>,
3439 <&usb_1_qmpp !! 3169 <0>,
3440 <&usb_1_qmpp !! 3170 <0>;
3441 clock-names = "bi_tcx 3171 clock-names = "bi_tcxo",
3442 "gcc_di 3172 "gcc_disp_gpll0_clk_src",
3443 "dsi0_p 3173 "dsi0_phy_pll_out_byteclk",
3444 "dsi0_p 3174 "dsi0_phy_pll_out_dsiclk",
3445 "dp_phy 3175 "dp_phy_pll_link_clk",
3446 "dp_phy 3176 "dp_phy_pll_vco_div_clk";
3447 #clock-cells = <1>; 3177 #clock-cells = <1>;
3448 #reset-cells = <1>; 3178 #reset-cells = <1>;
3449 #power-domain-cells = 3179 #power-domain-cells = <1>;
3450 }; 3180 };
3451 3181
3452 pdc: interrupt-controller@b22 3182 pdc: interrupt-controller@b220000 {
3453 compatible = "qcom,sc 3183 compatible = "qcom,sc7180-pdc", "qcom,pdc";
3454 reg = <0 0x0b220000 0 3184 reg = <0 0x0b220000 0 0x30000>;
3455 qcom,pdc-ranges = <0 3185 qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>;
3456 #interrupt-cells = <2 3186 #interrupt-cells = <2>;
3457 interrupt-parent = <& 3187 interrupt-parent = <&intc>;
3458 interrupt-controller; 3188 interrupt-controller;
3459 }; 3189 };
3460 3190
3461 pdc_reset: reset-controller@b 3191 pdc_reset: reset-controller@b2e0000 {
3462 compatible = "qcom,sc 3192 compatible = "qcom,sc7180-pdc-global", "qcom,sdm845-pdc-global";
3463 reg = <0 0x0b2e0000 0 3193 reg = <0 0x0b2e0000 0 0x20000>;
3464 #reset-cells = <1>; 3194 #reset-cells = <1>;
3465 }; 3195 };
3466 3196
3467 tsens0: thermal-sensor@c26300 3197 tsens0: thermal-sensor@c263000 {
3468 compatible = "qcom,sc 3198 compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
3469 reg = <0 0x0c263000 0 3199 reg = <0 0x0c263000 0 0x1ff>, /* TM */
3470 <0 0x0c222000 3200 <0 0x0c222000 0 0x1ff>; /* SROT */
3471 #qcom,sensors = <15>; 3201 #qcom,sensors = <15>;
3472 interrupts = <GIC_SPI 3202 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
3473 <GIC_SPI 3203 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
3474 interrupt-names = "up 3204 interrupt-names = "uplow","critical";
3475 #thermal-sensor-cells 3205 #thermal-sensor-cells = <1>;
3476 }; 3206 };
3477 3207
3478 tsens1: thermal-sensor@c26500 3208 tsens1: thermal-sensor@c265000 {
3479 compatible = "qcom,sc 3209 compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
3480 reg = <0 0x0c265000 0 3210 reg = <0 0x0c265000 0 0x1ff>, /* TM */
3481 <0 0x0c223000 3211 <0 0x0c223000 0 0x1ff>; /* SROT */
3482 #qcom,sensors = <10>; 3212 #qcom,sensors = <10>;
3483 interrupts = <GIC_SPI 3213 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
3484 <GIC_SPI 3214 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
3485 interrupt-names = "up 3215 interrupt-names = "uplow","critical";
3486 #thermal-sensor-cells 3216 #thermal-sensor-cells = <1>;
3487 }; 3217 };
3488 3218
3489 aoss_reset: reset-controller@ 3219 aoss_reset: reset-controller@c2a0000 {
3490 compatible = "qcom,sc 3220 compatible = "qcom,sc7180-aoss-cc", "qcom,sdm845-aoss-cc";
3491 reg = <0 0x0c2a0000 0 3221 reg = <0 0x0c2a0000 0 0x31000>;
3492 #reset-cells = <1>; 3222 #reset-cells = <1>;
3493 }; 3223 };
3494 3224
3495 aoss_qmp: power-management@c3 !! 3225 aoss_qmp: qmp@c300000 {
3496 compatible = "qcom,sc !! 3226 compatible = "qcom,sc7180-aoss-qmp";
3497 reg = <0 0x0c300000 0 !! 3227 reg = <0 0x0c300000 0 0x100000>;
3498 interrupts = <GIC_SPI 3228 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
3499 mboxes = <&apss_share 3229 mboxes = <&apss_shared 0>;
3500 3230
3501 #clock-cells = <0>; 3231 #clock-cells = <0>;
3502 }; !! 3232 #power-domain-cells = <1>;
3503 <<
3504 sram@c3f0000 { <<
3505 compatible = "qcom,rp <<
3506 reg = <0 0x0c3f0000 0 <<
3507 }; 3233 };
3508 3234
3509 spmi_bus: spmi@c440000 { 3235 spmi_bus: spmi@c440000 {
3510 compatible = "qcom,sp 3236 compatible = "qcom,spmi-pmic-arb";
3511 reg = <0 0x0c440000 0 3237 reg = <0 0x0c440000 0 0x1100>,
3512 <0 0x0c600000 0 3238 <0 0x0c600000 0 0x2000000>,
3513 <0 0x0e600000 0 3239 <0 0x0e600000 0 0x100000>,
3514 <0 0x0e700000 0 3240 <0 0x0e700000 0 0xa0000>,
3515 <0 0x0c40a000 0 3241 <0 0x0c40a000 0 0x26000>;
3516 reg-names = "core", " 3242 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3517 interrupt-names = "pe 3243 interrupt-names = "periph_irq";
3518 interrupts-extended = 3244 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3519 qcom,ee = <0>; 3245 qcom,ee = <0>;
3520 qcom,channel = <0>; 3246 qcom,channel = <0>;
3521 #address-cells = <2>; <<
3522 #size-cells = <0>; <<
3523 interrupt-controller; <<
3524 #interrupt-cells = <4 <<
3525 }; <<
3526 <<
3527 sram@146aa000 { <<
3528 compatible = "qcom,sc <<
3529 reg = <0 0x146aa000 0 <<
3530 <<
3531 #address-cells = <1>; 3247 #address-cells = <1>;
3532 #size-cells = <1>; 3248 #size-cells = <1>;
3533 !! 3249 interrupt-controller;
3534 ranges = <0 0 0x146aa !! 3250 #interrupt-cells = <4>;
3535 !! 3251 cell-index = <0>;
3536 pil-reloc@94c { <<
3537 compatible = <<
3538 reg = <0x94c <<
3539 }; <<
3540 }; 3252 };
3541 3253
3542 apps_smmu: iommu@15000000 { 3254 apps_smmu: iommu@15000000 {
3543 compatible = "qcom,sc 3255 compatible = "qcom,sc7180-smmu-500", "arm,mmu-500";
3544 reg = <0 0x15000000 0 3256 reg = <0 0x15000000 0 0x100000>;
3545 #iommu-cells = <2>; 3257 #iommu-cells = <2>;
3546 #global-interrupts = 3258 #global-interrupts = <1>;
3547 interrupts = <GIC_SPI 3259 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
3548 <GIC_SPI 3260 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
3549 <GIC_SPI 3261 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
3550 <GIC_SPI 3262 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
3551 <GIC_SPI 3263 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
3552 <GIC_SPI 3264 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
3553 <GIC_SPI 3265 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
3554 <GIC_SPI 3266 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
3555 <GIC_SPI 3267 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
3556 <GIC_SPI 3268 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
3557 <GIC_SPI 3269 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
3558 <GIC_SPI 3270 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
3559 <GIC_SPI 3271 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
3560 <GIC_SPI 3272 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
3561 <GIC_SPI 3273 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
3562 <GIC_SPI 3274 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
3563 <GIC_SPI 3275 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
3564 <GIC_SPI 3276 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
3565 <GIC_SPI 3277 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
3566 <GIC_SPI 3278 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
3567 <GIC_SPI 3279 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
3568 <GIC_SPI 3280 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
3569 <GIC_SPI 3281 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
3570 <GIC_SPI 3282 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
3571 <GIC_SPI 3283 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
3572 <GIC_SPI 3284 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
3573 <GIC_SPI 3285 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
3574 <GIC_SPI 3286 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
3575 <GIC_SPI 3287 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
3576 <GIC_SPI 3288 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
3577 <GIC_SPI 3289 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
3578 <GIC_SPI 3290 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
3579 <GIC_SPI 3291 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
3580 <GIC_SPI 3292 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
3581 <GIC_SPI 3293 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
3582 <GIC_SPI 3294 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
3583 <GIC_SPI 3295 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
3584 <GIC_SPI 3296 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
3585 <GIC_SPI 3297 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
3586 <GIC_SPI 3298 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
3587 <GIC_SPI 3299 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
3588 <GIC_SPI 3300 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
3589 <GIC_SPI 3301 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
3590 <GIC_SPI 3302 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
3591 <GIC_SPI 3303 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
3592 <GIC_SPI 3304 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
3593 <GIC_SPI 3305 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
3594 <GIC_SPI 3306 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
3595 <GIC_SPI 3307 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
3596 <GIC_SPI 3308 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
3597 <GIC_SPI 3309 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
3598 <GIC_SPI 3310 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
3599 <GIC_SPI 3311 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
3600 <GIC_SPI 3312 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
3601 <GIC_SPI 3313 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
3602 <GIC_SPI 3314 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
3603 <GIC_SPI 3315 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
3604 <GIC_SPI 3316 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
3605 <GIC_SPI 3317 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
3606 <GIC_SPI 3318 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
3607 <GIC_SPI 3319 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
3608 <GIC_SPI 3320 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
3609 <GIC_SPI 3321 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
3610 <GIC_SPI 3322 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
3611 <GIC_SPI 3323 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
3612 <GIC_SPI 3324 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
3613 <GIC_SPI 3325 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
3614 <GIC_SPI 3326 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
3615 <GIC_SPI 3327 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
3616 <GIC_SPI 3328 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
3617 <GIC_SPI 3329 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
3618 <GIC_SPI 3330 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
3619 <GIC_SPI 3331 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
3620 <GIC_SPI 3332 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
3621 <GIC_SPI 3333 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
3622 <GIC_SPI 3334 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
3623 <GIC_SPI 3335 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
3624 <GIC_SPI 3336 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
3625 <GIC_SPI 3337 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
3626 <GIC_SPI 3338 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
3627 <GIC_SPI 3339 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
3628 }; 3340 };
3629 3341
3630 intc: interrupt-controller@17 3342 intc: interrupt-controller@17a00000 {
3631 compatible = "arm,gic 3343 compatible = "arm,gic-v3";
3632 #address-cells = <2>; 3344 #address-cells = <2>;
3633 #size-cells = <2>; 3345 #size-cells = <2>;
3634 ranges; 3346 ranges;
3635 #interrupt-cells = <3 3347 #interrupt-cells = <3>;
3636 interrupt-controller; 3348 interrupt-controller;
3637 reg = <0 0x17a00000 0 3349 reg = <0 0x17a00000 0 0x10000>, /* GICD */
3638 <0 0x17a60000 0 3350 <0 0x17a60000 0 0x100000>; /* GICR * 8 */
3639 interrupts = <GIC_PPI 3351 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3640 3352
3641 msi-controller@17a400 3353 msi-controller@17a40000 {
3642 compatible = 3354 compatible = "arm,gic-v3-its";
3643 msi-controlle 3355 msi-controller;
3644 #msi-cells = 3356 #msi-cells = <1>;
3645 reg = <0 0x17 3357 reg = <0 0x17a40000 0 0x20000>;
3646 status = "dis 3358 status = "disabled";
3647 }; 3359 };
3648 }; 3360 };
3649 3361
3650 apss_shared: mailbox@17c00000 3362 apss_shared: mailbox@17c00000 {
3651 compatible = "qcom,sc !! 3363 compatible = "qcom,sc7180-apss-shared";
3652 "qcom,sd <<
3653 reg = <0 0x17c00000 0 3364 reg = <0 0x17c00000 0 0x10000>;
3654 #mbox-cells = <1>; 3365 #mbox-cells = <1>;
3655 }; 3366 };
3656 3367
3657 watchdog@17c10000 { 3368 watchdog@17c10000 {
3658 compatible = "qcom,ap 3369 compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt";
3659 reg = <0 0x17c10000 0 3370 reg = <0 0x17c10000 0 0x1000>;
3660 clocks = <&sleep_clk> 3371 clocks = <&sleep_clk>;
3661 interrupts = <GIC_SPI !! 3372 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
3662 }; 3373 };
3663 3374
3664 timer@17c20000 { !! 3375 timer@17c20000{
3665 #address-cells = <1>; !! 3376 #address-cells = <2>;
3666 #size-cells = <1>; !! 3377 #size-cells = <2>;
3667 ranges = <0 0 0 0x200 !! 3378 ranges;
3668 compatible = "arm,arm 3379 compatible = "arm,armv7-timer-mem";
3669 reg = <0 0x17c20000 0 3380 reg = <0 0x17c20000 0 0x1000>;
3670 3381
3671 frame@17c21000 { 3382 frame@17c21000 {
3672 frame-number 3383 frame-number = <0>;
3673 interrupts = 3384 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
3674 3385 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
3675 reg = <0x17c2 !! 3386 reg = <0 0x17c21000 0 0x1000>,
3676 <0x17c2 !! 3387 <0 0x17c22000 0 0x1000>;
3677 }; 3388 };
3678 3389
3679 frame@17c23000 { 3390 frame@17c23000 {
3680 frame-number 3391 frame-number = <1>;
3681 interrupts = 3392 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
3682 reg = <0x17c2 !! 3393 reg = <0 0x17c23000 0 0x1000>;
3683 status = "dis 3394 status = "disabled";
3684 }; 3395 };
3685 3396
3686 frame@17c25000 { 3397 frame@17c25000 {
3687 frame-number 3398 frame-number = <2>;
3688 interrupts = 3399 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
3689 reg = <0x17c2 !! 3400 reg = <0 0x17c25000 0 0x1000>;
3690 status = "dis 3401 status = "disabled";
3691 }; 3402 };
3692 3403
3693 frame@17c27000 { 3404 frame@17c27000 {
3694 frame-number 3405 frame-number = <3>;
3695 interrupts = 3406 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3696 reg = <0x17c2 !! 3407 reg = <0 0x17c27000 0 0x1000>;
3697 status = "dis 3408 status = "disabled";
3698 }; 3409 };
3699 3410
3700 frame@17c29000 { 3411 frame@17c29000 {
3701 frame-number 3412 frame-number = <4>;
3702 interrupts = 3413 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3703 reg = <0x17c2 !! 3414 reg = <0 0x17c29000 0 0x1000>;
3704 status = "dis 3415 status = "disabled";
3705 }; 3416 };
3706 3417
3707 frame@17c2b000 { 3418 frame@17c2b000 {
3708 frame-number 3419 frame-number = <5>;
3709 interrupts = 3420 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3710 reg = <0x17c2 !! 3421 reg = <0 0x17c2b000 0 0x1000>;
3711 status = "dis 3422 status = "disabled";
3712 }; 3423 };
3713 3424
3714 frame@17c2d000 { 3425 frame@17c2d000 {
3715 frame-number 3426 frame-number = <6>;
3716 interrupts = 3427 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
3717 reg = <0x17c2 !! 3428 reg = <0 0x17c2d000 0 0x1000>;
3718 status = "dis 3429 status = "disabled";
3719 }; 3430 };
3720 }; 3431 };
3721 3432
3722 apps_rsc: rsc@18200000 { 3433 apps_rsc: rsc@18200000 {
3723 compatible = "qcom,rp 3434 compatible = "qcom,rpmh-rsc";
3724 reg = <0 0x18200000 0 3435 reg = <0 0x18200000 0 0x10000>,
3725 <0 0x18210000 0 3436 <0 0x18210000 0 0x10000>,
3726 <0 0x18220000 0 3437 <0 0x18220000 0 0x10000>;
3727 reg-names = "drv-0", 3438 reg-names = "drv-0", "drv-1", "drv-2";
3728 interrupts = <GIC_SPI 3439 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
3729 <GIC_SPI 3440 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
3730 <GIC_SPI 3441 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
3731 qcom,tcs-offset = <0x 3442 qcom,tcs-offset = <0xd00>;
3732 qcom,drv-id = <2>; 3443 qcom,drv-id = <2>;
3733 qcom,tcs-config = <AC 3444 qcom,tcs-config = <ACTIVE_TCS 2>,
3734 <SL 3445 <SLEEP_TCS 3>,
3735 <WA 3446 <WAKE_TCS 3>,
3736 <CO 3447 <CONTROL_TCS 1>;
3737 power-domains = <&CLU <<
3738 3448
3739 rpmhcc: clock-control 3449 rpmhcc: clock-controller {
3740 compatible = 3450 compatible = "qcom,sc7180-rpmh-clk";
3741 clocks = <&xo 3451 clocks = <&xo_board>;
3742 clock-names = 3452 clock-names = "xo";
3743 #clock-cells 3453 #clock-cells = <1>;
3744 }; 3454 };
3745 3455
3746 rpmhpd: power-control 3456 rpmhpd: power-controller {
3747 compatible = 3457 compatible = "qcom,sc7180-rpmhpd";
3748 #power-domain 3458 #power-domain-cells = <1>;
3749 operating-poi 3459 operating-points-v2 = <&rpmhpd_opp_table>;
3750 3460
3751 rpmhpd_opp_ta 3461 rpmhpd_opp_table: opp-table {
3752 compa 3462 compatible = "operating-points-v2";
3753 3463
3754 rpmhp 3464 rpmhpd_opp_ret: opp1 {
3755 3465 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3756 }; 3466 };
3757 3467
3758 rpmhp 3468 rpmhpd_opp_min_svs: opp2 {
3759 3469 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3760 }; 3470 };
3761 3471
3762 rpmhp 3472 rpmhpd_opp_low_svs: opp3 {
3763 3473 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3764 }; 3474 };
3765 3475
3766 rpmhp 3476 rpmhpd_opp_svs: opp4 {
3767 3477 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3768 }; 3478 };
3769 3479
3770 rpmhp 3480 rpmhpd_opp_svs_l1: opp5 {
3771 3481 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3772 }; 3482 };
3773 3483
3774 rpmhp 3484 rpmhpd_opp_svs_l2: opp6 {
3775 3485 opp-level = <224>;
3776 }; 3486 };
3777 3487
3778 rpmhp 3488 rpmhpd_opp_nom: opp7 {
3779 3489 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3780 }; 3490 };
3781 3491
3782 rpmhp 3492 rpmhpd_opp_nom_l1: opp8 {
3783 3493 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3784 }; 3494 };
3785 3495
3786 rpmhp 3496 rpmhpd_opp_nom_l2: opp9 {
3787 3497 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3788 }; 3498 };
3789 3499
3790 rpmhp 3500 rpmhpd_opp_turbo: opp10 {
3791 3501 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3792 }; 3502 };
3793 3503
3794 rpmhp 3504 rpmhpd_opp_turbo_l1: opp11 {
3795 3505 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3796 }; 3506 };
3797 }; 3507 };
3798 }; 3508 };
3799 3509
3800 apps_bcm_voter: bcm-v !! 3510 apps_bcm_voter: bcm_voter {
3801 compatible = 3511 compatible = "qcom,bcm-voter";
3802 }; 3512 };
3803 }; 3513 };
3804 3514
3805 osm_l3: interconnect@18321000 3515 osm_l3: interconnect@18321000 {
3806 compatible = "qcom,sc !! 3516 compatible = "qcom,sc7180-osm-l3";
3807 reg = <0 0x18321000 0 3517 reg = <0 0x18321000 0 0x1400>;
3808 3518
3809 clocks = <&rpmhcc RPM 3519 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3810 clock-names = "xo", " 3520 clock-names = "xo", "alternate";
3811 3521
3812 #interconnect-cells = 3522 #interconnect-cells = <1>;
3813 }; 3523 };
3814 3524
3815 cpufreq_hw: cpufreq@18323000 3525 cpufreq_hw: cpufreq@18323000 {
3816 compatible = "qcom,sc !! 3526 compatible = "qcom,cpufreq-hw";
3817 reg = <0 0x18323000 0 3527 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>;
3818 reg-names = "freq-dom 3528 reg-names = "freq-domain0", "freq-domain1";
3819 3529
3820 clocks = <&rpmhcc RPM 3530 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3821 clock-names = "xo", " 3531 clock-names = "xo", "alternate";
3822 3532
3823 #freq-domain-cells = 3533 #freq-domain-cells = <1>;
3824 #clock-cells = <1>; <<
3825 }; 3534 };
3826 3535
3827 wifi: wifi@18800000 { 3536 wifi: wifi@18800000 {
3828 compatible = "qcom,wc 3537 compatible = "qcom,wcn3990-wifi";
3829 reg = <0 0x18800000 0 3538 reg = <0 0x18800000 0 0x800000>;
3830 reg-names = "membase" 3539 reg-names = "membase";
3831 iommus = <&apps_smmu 3540 iommus = <&apps_smmu 0xc0 0x1>;
3832 interrupts = 3541 interrupts =
3833 <GIC_SPI 414 3542 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH /* CE0 */ >,
3834 <GIC_SPI 415 3543 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH /* CE1 */ >,
3835 <GIC_SPI 416 3544 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH /* CE2 */ >,
3836 <GIC_SPI 417 3545 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH /* CE3 */ >,
3837 <GIC_SPI 418 3546 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH /* CE4 */ >,
3838 <GIC_SPI 419 3547 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH /* CE5 */ >,
3839 <GIC_SPI 420 3548 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH /* CE6 */ >,
3840 <GIC_SPI 421 3549 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH /* CE7 */ >,
3841 <GIC_SPI 422 3550 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH /* CE8 */ >,
3842 <GIC_SPI 423 3551 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH /* CE9 */ >,
3843 <GIC_SPI 424 3552 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH /* CE10 */>,
3844 <GIC_SPI 425 3553 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH /* CE11 */>;
3845 memory-region = <&wla 3554 memory-region = <&wlan_mem>;
3846 qcom,msa-fixed-perm; 3555 qcom,msa-fixed-perm;
3847 status = "disabled"; 3556 status = "disabled";
3848 }; 3557 };
3849 3558
3850 remoteproc_adsp: remoteproc@6 <<
3851 compatible = "qcom,sc <<
3852 reg = <0 0x62400000 0 <<
3853 <<
3854 interrupts-extended = <<
3855 <<
3856 <<
3857 <<
3858 <<
3859 interrupt-names = "wd <<
3860 "fa <<
3861 "re <<
3862 "ha <<
3863 "st <<
3864 <<
3865 clocks = <&rpmhcc RPM <<
3866 clock-names = "xo"; <<
3867 <<
3868 power-domains = <&rpm <<
3869 <&rpm <<
3870 power-domain-names = <<
3871 <<
3872 qcom,qmp = <&aoss_qmp <<
3873 qcom,smem-states = <& <<
3874 qcom,smem-state-names <<
3875 <<
3876 status = "disabled"; <<
3877 <<
3878 glink-edge { <<
3879 interrupts = <<
3880 label = "lpas <<
3881 qcom,remote-p <<
3882 mboxes = <&ap <<
3883 <<
3884 apr { <<
3885 compa <<
3886 qcom, <<
3887 qcom, <<
3888 #addr <<
3889 #size <<
3890 <<
3891 servi <<
3892 <<
3893 <<
3894 <<
3895 }; <<
3896 <<
3897 q6afe <<
3898 <<
3899 <<
3900 <<
3901 <<
3902 <<
3903 <<
3904 <<
3905 <<
3906 <<
3907 <<
3908 <<
3909 <<
3910 <<
3911 <<
3912 <<
3913 }; <<
3914 <<
3915 q6asm <<
3916 <<
3917 <<
3918 <<
3919 <<
3920 <<
3921 <<
3922 <<
3923 <<
3924 <<
3925 <<
3926 <<
3927 }; <<
3928 <<
3929 q6adm <<
3930 <<
3931 <<
3932 <<
3933 <<
3934 <<
3935 <<
3936 <<
3937 <<
3938 }; <<
3939 }; <<
3940 <<
3941 fastrpc { <<
3942 compa <<
3943 qcom, <<
3944 label <<
3945 #addr <<
3946 #size <<
3947 <<
3948 compu <<
3949 <<
3950 <<
3951 <<
3952 }; <<
3953 <<
3954 compu <<
3955 <<
3956 <<
3957 <<
3958 }; <<
3959 <<
3960 compu <<
3961 <<
3962 <<
3963 <<
3964 <<
3965 }; <<
3966 }; <<
3967 }; <<
3968 }; <<
3969 <<
3970 lpasscc: clock-controller@62d 3559 lpasscc: clock-controller@62d00000 {
3971 compatible = "qcom,sc 3560 compatible = "qcom,sc7180-lpasscorecc";
3972 reg = <0 0x62d00000 0 3561 reg = <0 0x62d00000 0 0x50000>,
3973 <0 0x62780000 0 3562 <0 0x62780000 0 0x30000>;
3974 reg-names = "lpass_co 3563 reg-names = "lpass_core_cc", "lpass_audio_cc";
3975 clocks = <&gcc GCC_LP 3564 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>,
3976 <&rpmhcc RPM 3565 <&rpmhcc RPMH_CXO_CLK>;
3977 clock-names = "iface" 3566 clock-names = "iface", "bi_tcxo";
3978 power-domains = <&lpa 3567 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>;
3979 #clock-cells = <1>; 3568 #clock-cells = <1>;
3980 #power-domain-cells = 3569 #power-domain-cells = <1>;
3981 <<
3982 status = "reserved"; <<
3983 }; 3570 };
3984 3571
3985 lpass_cpu: lpass@62d87000 { !! 3572 lpass_cpu: lpass@62f00000 {
3986 compatible = "qcom,sc 3573 compatible = "qcom,sc7180-lpass-cpu";
3987 3574
3988 reg = <0 0x62d87000 0 !! 3575 reg = <0 0x62f00000 0 0x29000>;
3989 reg-names = "lpass-hd !! 3576 reg-names = "lpass-lpaif";
3990 3577
3991 iommus = <&apps_smmu !! 3578 iommus = <&apps_smmu 0x1020 0>;
3992 <&apps_smmu 0 <<
3993 <&apps_smmu 0 <<
3994 3579
3995 power-domains = <&lpa 3580 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>;
3996 required-opps = <&rpm <<
3997 <<
3998 status = "disabled"; <<
3999 3581
4000 clocks = <&gcc GCC_LP 3582 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>,
4001 <&lpasscc LP 3583 <&lpasscc LPASS_AUDIO_CORE_CORE_CLK>,
4002 <&lpasscc LP 3584 <&lpasscc LPASS_AUDIO_CORE_EXT_MCLK0_CLK>,
4003 <&lpasscc LP 3585 <&lpasscc LPASS_AUDIO_CORE_SYSNOC_MPORT_CORE_CLK>,
4004 <&lpasscc LP 3586 <&lpasscc LPASS_AUDIO_CORE_LPAIF_PRI_IBIT_CLK>,
4005 <&lpasscc LP 3587 <&lpasscc LPASS_AUDIO_CORE_LPAIF_SEC_IBIT_CLK>;
4006 3588
4007 clock-names = "pcnoc- 3589 clock-names = "pcnoc-sway-clk", "audio-core",
4008 "mclk 3590 "mclk0", "pcnoc-mport-clk",
4009 "mi2s 3591 "mi2s-bit-clk0", "mi2s-bit-clk1";
4010 3592
4011 3593
4012 #sound-dai-cells = <1 3594 #sound-dai-cells = <1>;
4013 #address-cells = <1>; 3595 #address-cells = <1>;
4014 #size-cells = <0>; 3596 #size-cells = <0>;
4015 3597
4016 interrupts = <GIC_SPI !! 3598 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
4017 <GIC_ !! 3599 interrupt-names = "lpass-irq-lpaif";
4018 interrupt-names = "lp <<
4019 }; 3600 };
4020 3601
4021 lpass_hm: clock-controller@63 3602 lpass_hm: clock-controller@63000000 {
4022 compatible = "qcom,sc 3603 compatible = "qcom,sc7180-lpasshm";
4023 reg = <0 0x63000000 0 3604 reg = <0 0x63000000 0 0x28>;
4024 clocks = <&gcc GCC_LP 3605 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>,
4025 <&rpmhcc RPM 3606 <&rpmhcc RPMH_CXO_CLK>;
4026 clock-names = "iface" 3607 clock-names = "iface", "bi_tcxo";
4027 power-domains = <&rpm <<
4028 <<
4029 #clock-cells = <1>; 3608 #clock-cells = <1>;
4030 #power-domain-cells = 3609 #power-domain-cells = <1>;
4031 <<
4032 status = "reserved"; <<
4033 }; 3610 };
4034 }; 3611 };
4035 3612
4036 thermal-zones { 3613 thermal-zones {
4037 cpu0_thermal: cpu0-thermal { 3614 cpu0_thermal: cpu0-thermal {
4038 polling-delay-passive 3615 polling-delay-passive = <250>;
>> 3616 polling-delay = <0>;
4039 3617
4040 thermal-sensors = <&t 3618 thermal-sensors = <&tsens0 1>;
4041 sustainable-power = < !! 3619 sustainable-power = <768>;
4042 3620
4043 trips { 3621 trips {
4044 cpu0_alert0: 3622 cpu0_alert0: trip-point0 {
4045 tempe 3623 temperature = <90000>;
4046 hyste 3624 hysteresis = <2000>;
4047 type 3625 type = "passive";
4048 }; 3626 };
4049 3627
4050 cpu0_alert1: 3628 cpu0_alert1: trip-point1 {
4051 tempe 3629 temperature = <95000>;
4052 hyste 3630 hysteresis = <2000>;
4053 type 3631 type = "passive";
4054 }; 3632 };
4055 3633
4056 cpu0_crit: cp !! 3634 cpu0_crit: cpu_crit {
4057 tempe 3635 temperature = <110000>;
4058 hyste 3636 hysteresis = <1000>;
4059 type 3637 type = "critical";
4060 }; 3638 };
4061 }; 3639 };
4062 3640
4063 cooling-maps { 3641 cooling-maps {
4064 map0 { 3642 map0 {
4065 trip 3643 trip = <&cpu0_alert0>;
4066 cooli 3644 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4067 3645 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4068 3646 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4069 3647 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4070 3648 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4071 3649 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4072 }; 3650 };
4073 map1 { 3651 map1 {
4074 trip 3652 trip = <&cpu0_alert1>;
4075 cooli 3653 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4076 3654 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4077 3655 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4078 3656 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4079 3657 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4080 3658 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4081 }; 3659 };
4082 }; 3660 };
4083 }; 3661 };
4084 3662
4085 cpu1_thermal: cpu1-thermal { 3663 cpu1_thermal: cpu1-thermal {
4086 polling-delay-passive 3664 polling-delay-passive = <250>;
>> 3665 polling-delay = <0>;
4087 3666
4088 thermal-sensors = <&t 3667 thermal-sensors = <&tsens0 2>;
4089 sustainable-power = < !! 3668 sustainable-power = <768>;
4090 3669
4091 trips { 3670 trips {
4092 cpu1_alert0: 3671 cpu1_alert0: trip-point0 {
4093 tempe 3672 temperature = <90000>;
4094 hyste 3673 hysteresis = <2000>;
4095 type 3674 type = "passive";
4096 }; 3675 };
4097 3676
4098 cpu1_alert1: 3677 cpu1_alert1: trip-point1 {
4099 tempe 3678 temperature = <95000>;
4100 hyste 3679 hysteresis = <2000>;
4101 type 3680 type = "passive";
4102 }; 3681 };
4103 3682
4104 cpu1_crit: cp !! 3683 cpu1_crit: cpu_crit {
4105 tempe 3684 temperature = <110000>;
4106 hyste 3685 hysteresis = <1000>;
4107 type 3686 type = "critical";
4108 }; 3687 };
4109 }; 3688 };
4110 3689
4111 cooling-maps { 3690 cooling-maps {
4112 map0 { 3691 map0 {
4113 trip 3692 trip = <&cpu1_alert0>;
4114 cooli 3693 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4115 3694 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4116 3695 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4117 3696 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4118 3697 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4119 3698 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4120 }; 3699 };
4121 map1 { 3700 map1 {
4122 trip 3701 trip = <&cpu1_alert1>;
4123 cooli 3702 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4124 3703 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4125 3704 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4126 3705 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4127 3706 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4128 3707 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4129 }; 3708 };
4130 }; 3709 };
4131 }; 3710 };
4132 3711
4133 cpu2_thermal: cpu2-thermal { 3712 cpu2_thermal: cpu2-thermal {
4134 polling-delay-passive 3713 polling-delay-passive = <250>;
>> 3714 polling-delay = <0>;
4135 3715
4136 thermal-sensors = <&t 3716 thermal-sensors = <&tsens0 3>;
4137 sustainable-power = < !! 3717 sustainable-power = <768>;
4138 3718
4139 trips { 3719 trips {
4140 cpu2_alert0: 3720 cpu2_alert0: trip-point0 {
4141 tempe 3721 temperature = <90000>;
4142 hyste 3722 hysteresis = <2000>;
4143 type 3723 type = "passive";
4144 }; 3724 };
4145 3725
4146 cpu2_alert1: 3726 cpu2_alert1: trip-point1 {
4147 tempe 3727 temperature = <95000>;
4148 hyste 3728 hysteresis = <2000>;
4149 type 3729 type = "passive";
4150 }; 3730 };
4151 3731
4152 cpu2_crit: cp !! 3732 cpu2_crit: cpu_crit {
4153 tempe 3733 temperature = <110000>;
4154 hyste 3734 hysteresis = <1000>;
4155 type 3735 type = "critical";
4156 }; 3736 };
4157 }; 3737 };
4158 3738
4159 cooling-maps { 3739 cooling-maps {
4160 map0 { 3740 map0 {
4161 trip 3741 trip = <&cpu2_alert0>;
4162 cooli 3742 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4163 3743 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4164 3744 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4165 3745 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4166 3746 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4167 3747 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4168 }; 3748 };
4169 map1 { 3749 map1 {
4170 trip 3750 trip = <&cpu2_alert1>;
4171 cooli 3751 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4172 3752 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4173 3753 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4174 3754 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4175 3755 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4176 3756 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4177 }; 3757 };
4178 }; 3758 };
4179 }; 3759 };
4180 3760
4181 cpu3_thermal: cpu3-thermal { 3761 cpu3_thermal: cpu3-thermal {
4182 polling-delay-passive 3762 polling-delay-passive = <250>;
>> 3763 polling-delay = <0>;
4183 3764
4184 thermal-sensors = <&t 3765 thermal-sensors = <&tsens0 4>;
4185 sustainable-power = < !! 3766 sustainable-power = <768>;
4186 3767
4187 trips { 3768 trips {
4188 cpu3_alert0: 3769 cpu3_alert0: trip-point0 {
4189 tempe 3770 temperature = <90000>;
4190 hyste 3771 hysteresis = <2000>;
4191 type 3772 type = "passive";
4192 }; 3773 };
4193 3774
4194 cpu3_alert1: 3775 cpu3_alert1: trip-point1 {
4195 tempe 3776 temperature = <95000>;
4196 hyste 3777 hysteresis = <2000>;
4197 type 3778 type = "passive";
4198 }; 3779 };
4199 3780
4200 cpu3_crit: cp !! 3781 cpu3_crit: cpu_crit {
4201 tempe 3782 temperature = <110000>;
4202 hyste 3783 hysteresis = <1000>;
4203 type 3784 type = "critical";
4204 }; 3785 };
4205 }; 3786 };
4206 3787
4207 cooling-maps { 3788 cooling-maps {
4208 map0 { 3789 map0 {
4209 trip 3790 trip = <&cpu3_alert0>;
4210 cooli 3791 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4211 3792 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4212 3793 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4213 3794 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4214 3795 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4215 3796 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4216 }; 3797 };
4217 map1 { 3798 map1 {
4218 trip 3799 trip = <&cpu3_alert1>;
4219 cooli 3800 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4220 3801 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4221 3802 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4222 3803 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4223 3804 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4224 3805 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4225 }; 3806 };
4226 }; 3807 };
4227 }; 3808 };
4228 3809
4229 cpu4_thermal: cpu4-thermal { 3810 cpu4_thermal: cpu4-thermal {
4230 polling-delay-passive 3811 polling-delay-passive = <250>;
>> 3812 polling-delay = <0>;
4231 3813
4232 thermal-sensors = <&t 3814 thermal-sensors = <&tsens0 5>;
4233 sustainable-power = < !! 3815 sustainable-power = <768>;
4234 3816
4235 trips { 3817 trips {
4236 cpu4_alert0: 3818 cpu4_alert0: trip-point0 {
4237 tempe 3819 temperature = <90000>;
4238 hyste 3820 hysteresis = <2000>;
4239 type 3821 type = "passive";
4240 }; 3822 };
4241 3823
4242 cpu4_alert1: 3824 cpu4_alert1: trip-point1 {
4243 tempe 3825 temperature = <95000>;
4244 hyste 3826 hysteresis = <2000>;
4245 type 3827 type = "passive";
4246 }; 3828 };
4247 3829
4248 cpu4_crit: cp !! 3830 cpu4_crit: cpu_crit {
4249 tempe 3831 temperature = <110000>;
4250 hyste 3832 hysteresis = <1000>;
4251 type 3833 type = "critical";
4252 }; 3834 };
4253 }; 3835 };
4254 3836
4255 cooling-maps { 3837 cooling-maps {
4256 map0 { 3838 map0 {
4257 trip 3839 trip = <&cpu4_alert0>;
4258 cooli 3840 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4259 3841 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4260 3842 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4261 3843 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4262 3844 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4263 3845 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4264 }; 3846 };
4265 map1 { 3847 map1 {
4266 trip 3848 trip = <&cpu4_alert1>;
4267 cooli 3849 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4268 3850 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4269 3851 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4270 3852 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4271 3853 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4272 3854 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4273 }; 3855 };
4274 }; 3856 };
4275 }; 3857 };
4276 3858
4277 cpu5_thermal: cpu5-thermal { 3859 cpu5_thermal: cpu5-thermal {
4278 polling-delay-passive 3860 polling-delay-passive = <250>;
>> 3861 polling-delay = <0>;
4279 3862
4280 thermal-sensors = <&t 3863 thermal-sensors = <&tsens0 6>;
4281 sustainable-power = < !! 3864 sustainable-power = <768>;
4282 3865
4283 trips { 3866 trips {
4284 cpu5_alert0: 3867 cpu5_alert0: trip-point0 {
4285 tempe 3868 temperature = <90000>;
4286 hyste 3869 hysteresis = <2000>;
4287 type 3870 type = "passive";
4288 }; 3871 };
4289 3872
4290 cpu5_alert1: 3873 cpu5_alert1: trip-point1 {
4291 tempe 3874 temperature = <95000>;
4292 hyste 3875 hysteresis = <2000>;
4293 type 3876 type = "passive";
4294 }; 3877 };
4295 3878
4296 cpu5_crit: cp !! 3879 cpu5_crit: cpu_crit {
4297 tempe 3880 temperature = <110000>;
4298 hyste 3881 hysteresis = <1000>;
4299 type 3882 type = "critical";
4300 }; 3883 };
4301 }; 3884 };
4302 3885
4303 cooling-maps { 3886 cooling-maps {
4304 map0 { 3887 map0 {
4305 trip 3888 trip = <&cpu5_alert0>;
4306 cooli 3889 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4307 3890 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4308 3891 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4309 3892 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4310 3893 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4311 3894 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4312 }; 3895 };
4313 map1 { 3896 map1 {
4314 trip 3897 trip = <&cpu5_alert1>;
4315 cooli 3898 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4316 3899 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4317 3900 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4318 3901 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4319 3902 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4320 3903 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4321 }; 3904 };
4322 }; 3905 };
4323 }; 3906 };
4324 3907
4325 cpu6_thermal: cpu6-thermal { 3908 cpu6_thermal: cpu6-thermal {
4326 polling-delay-passive 3909 polling-delay-passive = <250>;
>> 3910 polling-delay = <0>;
4327 3911
4328 thermal-sensors = <&t 3912 thermal-sensors = <&tsens0 9>;
4329 sustainable-power = < !! 3913 sustainable-power = <1202>;
4330 3914
4331 trips { 3915 trips {
4332 cpu6_alert0: 3916 cpu6_alert0: trip-point0 {
4333 tempe 3917 temperature = <90000>;
4334 hyste 3918 hysteresis = <2000>;
4335 type 3919 type = "passive";
4336 }; 3920 };
4337 3921
4338 cpu6_alert1: 3922 cpu6_alert1: trip-point1 {
4339 tempe 3923 temperature = <95000>;
4340 hyste 3924 hysteresis = <2000>;
4341 type 3925 type = "passive";
4342 }; 3926 };
4343 3927
4344 cpu6_crit: cp !! 3928 cpu6_crit: cpu_crit {
4345 tempe 3929 temperature = <110000>;
4346 hyste 3930 hysteresis = <1000>;
4347 type 3931 type = "critical";
4348 }; 3932 };
4349 }; 3933 };
4350 3934
4351 cooling-maps { 3935 cooling-maps {
4352 map0 { 3936 map0 {
4353 trip 3937 trip = <&cpu6_alert0>;
4354 cooli 3938 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4355 3939 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4356 }; 3940 };
4357 map1 { 3941 map1 {
4358 trip 3942 trip = <&cpu6_alert1>;
4359 cooli 3943 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4360 3944 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4361 }; 3945 };
4362 }; 3946 };
4363 }; 3947 };
4364 3948
4365 cpu7_thermal: cpu7-thermal { 3949 cpu7_thermal: cpu7-thermal {
4366 polling-delay-passive 3950 polling-delay-passive = <250>;
>> 3951 polling-delay = <0>;
4367 3952
4368 thermal-sensors = <&t 3953 thermal-sensors = <&tsens0 10>;
4369 sustainable-power = < !! 3954 sustainable-power = <1202>;
4370 3955
4371 trips { 3956 trips {
4372 cpu7_alert0: 3957 cpu7_alert0: trip-point0 {
4373 tempe 3958 temperature = <90000>;
4374 hyste 3959 hysteresis = <2000>;
4375 type 3960 type = "passive";
4376 }; 3961 };
4377 3962
4378 cpu7_alert1: 3963 cpu7_alert1: trip-point1 {
4379 tempe 3964 temperature = <95000>;
4380 hyste 3965 hysteresis = <2000>;
4381 type 3966 type = "passive";
4382 }; 3967 };
4383 3968
4384 cpu7_crit: cp !! 3969 cpu7_crit: cpu_crit {
4385 tempe 3970 temperature = <110000>;
4386 hyste 3971 hysteresis = <1000>;
4387 type 3972 type = "critical";
4388 }; 3973 };
4389 }; 3974 };
4390 3975
4391 cooling-maps { 3976 cooling-maps {
4392 map0 { 3977 map0 {
4393 trip 3978 trip = <&cpu7_alert0>;
4394 cooli 3979 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4395 3980 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4396 }; 3981 };
4397 map1 { 3982 map1 {
4398 trip 3983 trip = <&cpu7_alert1>;
4399 cooli 3984 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4400 3985 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4401 }; 3986 };
4402 }; 3987 };
4403 }; 3988 };
4404 3989
4405 cpu8_thermal: cpu8-thermal { 3990 cpu8_thermal: cpu8-thermal {
4406 polling-delay-passive 3991 polling-delay-passive = <250>;
>> 3992 polling-delay = <0>;
4407 3993
4408 thermal-sensors = <&t 3994 thermal-sensors = <&tsens0 11>;
4409 sustainable-power = < !! 3995 sustainable-power = <1202>;
4410 3996
4411 trips { 3997 trips {
4412 cpu8_alert0: 3998 cpu8_alert0: trip-point0 {
4413 tempe 3999 temperature = <90000>;
4414 hyste 4000 hysteresis = <2000>;
4415 type 4001 type = "passive";
4416 }; 4002 };
4417 4003
4418 cpu8_alert1: 4004 cpu8_alert1: trip-point1 {
4419 tempe 4005 temperature = <95000>;
4420 hyste 4006 hysteresis = <2000>;
4421 type 4007 type = "passive";
4422 }; 4008 };
4423 4009
4424 cpu8_crit: cp !! 4010 cpu8_crit: cpu_crit {
4425 tempe 4011 temperature = <110000>;
4426 hyste 4012 hysteresis = <1000>;
4427 type 4013 type = "critical";
4428 }; 4014 };
4429 }; 4015 };
4430 4016
4431 cooling-maps { 4017 cooling-maps {
4432 map0 { 4018 map0 {
4433 trip 4019 trip = <&cpu8_alert0>;
4434 cooli 4020 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4435 4021 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4436 }; 4022 };
4437 map1 { 4023 map1 {
4438 trip 4024 trip = <&cpu8_alert1>;
4439 cooli 4025 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4440 4026 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4441 }; 4027 };
4442 }; 4028 };
4443 }; 4029 };
4444 4030
4445 cpu9_thermal: cpu9-thermal { 4031 cpu9_thermal: cpu9-thermal {
4446 polling-delay-passive 4032 polling-delay-passive = <250>;
>> 4033 polling-delay = <0>;
4447 4034
4448 thermal-sensors = <&t 4035 thermal-sensors = <&tsens0 12>;
4449 sustainable-power = < !! 4036 sustainable-power = <1202>;
4450 4037
4451 trips { 4038 trips {
4452 cpu9_alert0: 4039 cpu9_alert0: trip-point0 {
4453 tempe 4040 temperature = <90000>;
4454 hyste 4041 hysteresis = <2000>;
4455 type 4042 type = "passive";
4456 }; 4043 };
4457 4044
4458 cpu9_alert1: 4045 cpu9_alert1: trip-point1 {
4459 tempe 4046 temperature = <95000>;
4460 hyste 4047 hysteresis = <2000>;
4461 type 4048 type = "passive";
4462 }; 4049 };
4463 4050
4464 cpu9_crit: cp !! 4051 cpu9_crit: cpu_crit {
4465 tempe 4052 temperature = <110000>;
4466 hyste 4053 hysteresis = <1000>;
4467 type 4054 type = "critical";
4468 }; 4055 };
4469 }; 4056 };
4470 4057
4471 cooling-maps { 4058 cooling-maps {
4472 map0 { 4059 map0 {
4473 trip 4060 trip = <&cpu9_alert0>;
4474 cooli 4061 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4475 4062 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4476 }; 4063 };
4477 map1 { 4064 map1 {
4478 trip 4065 trip = <&cpu9_alert1>;
4479 cooli 4066 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4480 4067 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4481 }; 4068 };
4482 }; 4069 };
4483 }; 4070 };
4484 4071
4485 aoss0-thermal { 4072 aoss0-thermal {
4486 polling-delay-passive 4073 polling-delay-passive = <250>;
>> 4074 polling-delay = <0>;
4487 4075
4488 thermal-sensors = <&t 4076 thermal-sensors = <&tsens0 0>;
4489 4077
4490 trips { 4078 trips {
4491 aoss0_alert0: 4079 aoss0_alert0: trip-point0 {
4492 tempe 4080 temperature = <90000>;
4493 hyste 4081 hysteresis = <2000>;
4494 type 4082 type = "hot";
4495 }; 4083 };
4496 4084
4497 aoss0_crit: a !! 4085 aoss0_crit: aoss0_crit {
4498 tempe 4086 temperature = <110000>;
4499 hyste 4087 hysteresis = <2000>;
4500 type 4088 type = "critical";
4501 }; 4089 };
4502 }; 4090 };
4503 }; 4091 };
4504 4092
4505 cpuss0-thermal { 4093 cpuss0-thermal {
4506 polling-delay-passive 4094 polling-delay-passive = <250>;
>> 4095 polling-delay = <0>;
4507 4096
4508 thermal-sensors = <&t 4097 thermal-sensors = <&tsens0 7>;
4509 4098
4510 trips { 4099 trips {
4511 cpuss0_alert0 4100 cpuss0_alert0: trip-point0 {
4512 tempe 4101 temperature = <90000>;
4513 hyste 4102 hysteresis = <2000>;
4514 type 4103 type = "hot";
4515 }; 4104 };
4516 cpuss0_crit: !! 4105 cpuss0_crit: cluster0_crit {
4517 tempe 4106 temperature = <110000>;
4518 hyste 4107 hysteresis = <2000>;
4519 type 4108 type = "critical";
4520 }; 4109 };
4521 }; 4110 };
4522 }; 4111 };
4523 4112
4524 cpuss1-thermal { 4113 cpuss1-thermal {
4525 polling-delay-passive 4114 polling-delay-passive = <250>;
>> 4115 polling-delay = <0>;
4526 4116
4527 thermal-sensors = <&t 4117 thermal-sensors = <&tsens0 8>;
4528 4118
4529 trips { 4119 trips {
4530 cpuss1_alert0 4120 cpuss1_alert0: trip-point0 {
4531 tempe 4121 temperature = <90000>;
4532 hyste 4122 hysteresis = <2000>;
4533 type 4123 type = "hot";
4534 }; 4124 };
4535 cpuss1_crit: !! 4125 cpuss1_crit: cluster0_crit {
4536 tempe 4126 temperature = <110000>;
4537 hyste 4127 hysteresis = <2000>;
4538 type 4128 type = "critical";
4539 }; 4129 };
4540 }; 4130 };
4541 }; 4131 };
4542 4132
4543 gpuss0-thermal { 4133 gpuss0-thermal {
4544 polling-delay-passive 4134 polling-delay-passive = <250>;
>> 4135 polling-delay = <0>;
4545 4136
4546 thermal-sensors = <&t 4137 thermal-sensors = <&tsens0 13>;
4547 4138
4548 trips { 4139 trips {
4549 gpuss0_alert0 4140 gpuss0_alert0: trip-point0 {
4550 tempe 4141 temperature = <95000>;
4551 hyste 4142 hysteresis = <2000>;
4552 type 4143 type = "passive";
4553 }; 4144 };
4554 4145
4555 gpuss0_crit: !! 4146 gpuss0_crit: gpuss0_crit {
4556 tempe 4147 temperature = <110000>;
4557 hyste 4148 hysteresis = <2000>;
4558 type 4149 type = "critical";
4559 }; 4150 };
4560 }; 4151 };
4561 4152
4562 cooling-maps { 4153 cooling-maps {
4563 map0 { 4154 map0 {
4564 trip 4155 trip = <&gpuss0_alert0>;
4565 cooli 4156 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4566 }; 4157 };
4567 }; 4158 };
4568 }; 4159 };
4569 4160
4570 gpuss1-thermal { 4161 gpuss1-thermal {
4571 polling-delay-passive 4162 polling-delay-passive = <250>;
>> 4163 polling-delay = <0>;
4572 4164
4573 thermal-sensors = <&t 4165 thermal-sensors = <&tsens0 14>;
4574 4166
4575 trips { 4167 trips {
4576 gpuss1_alert0 4168 gpuss1_alert0: trip-point0 {
4577 tempe 4169 temperature = <95000>;
4578 hyste 4170 hysteresis = <2000>;
4579 type 4171 type = "passive";
4580 }; 4172 };
4581 4173
4582 gpuss1_crit: !! 4174 gpuss1_crit: gpuss1_crit {
4583 tempe 4175 temperature = <110000>;
4584 hyste 4176 hysteresis = <2000>;
4585 type 4177 type = "critical";
4586 }; 4178 };
4587 }; 4179 };
4588 4180
4589 cooling-maps { 4181 cooling-maps {
4590 map0 { 4182 map0 {
4591 trip 4183 trip = <&gpuss1_alert0>;
4592 cooli 4184 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4593 }; 4185 };
4594 }; 4186 };
4595 }; 4187 };
4596 4188
4597 aoss1-thermal { 4189 aoss1-thermal {
4598 polling-delay-passive 4190 polling-delay-passive = <250>;
>> 4191 polling-delay = <0>;
4599 4192
4600 thermal-sensors = <&t 4193 thermal-sensors = <&tsens1 0>;
4601 4194
4602 trips { 4195 trips {
4603 aoss1_alert0: 4196 aoss1_alert0: trip-point0 {
4604 tempe 4197 temperature = <90000>;
4605 hyste 4198 hysteresis = <2000>;
4606 type 4199 type = "hot";
4607 }; 4200 };
4608 4201
4609 aoss1_crit: a !! 4202 aoss1_crit: aoss1_crit {
4610 tempe 4203 temperature = <110000>;
4611 hyste 4204 hysteresis = <2000>;
4612 type 4205 type = "critical";
4613 }; 4206 };
4614 }; 4207 };
4615 }; 4208 };
4616 4209
4617 cwlan-thermal { 4210 cwlan-thermal {
4618 polling-delay-passive 4211 polling-delay-passive = <250>;
>> 4212 polling-delay = <0>;
4619 4213
4620 thermal-sensors = <&t 4214 thermal-sensors = <&tsens1 1>;
4621 4215
4622 trips { 4216 trips {
4623 cwlan_alert0: 4217 cwlan_alert0: trip-point0 {
4624 tempe 4218 temperature = <90000>;
4625 hyste 4219 hysteresis = <2000>;
4626 type 4220 type = "hot";
4627 }; 4221 };
4628 4222
4629 cwlan_crit: c !! 4223 cwlan_crit: cwlan_crit {
4630 tempe 4224 temperature = <110000>;
4631 hyste 4225 hysteresis = <2000>;
4632 type 4226 type = "critical";
4633 }; 4227 };
4634 }; 4228 };
4635 }; 4229 };
4636 4230
4637 audio-thermal { 4231 audio-thermal {
4638 polling-delay-passive 4232 polling-delay-passive = <250>;
>> 4233 polling-delay = <0>;
4639 4234
4640 thermal-sensors = <&t 4235 thermal-sensors = <&tsens1 2>;
4641 4236
4642 trips { 4237 trips {
4643 audio_alert0: 4238 audio_alert0: trip-point0 {
4644 tempe 4239 temperature = <90000>;
4645 hyste 4240 hysteresis = <2000>;
4646 type 4241 type = "hot";
4647 }; 4242 };
4648 4243
4649 audio_crit: a !! 4244 audio_crit: audio_crit {
4650 tempe 4245 temperature = <110000>;
4651 hyste 4246 hysteresis = <2000>;
4652 type 4247 type = "critical";
4653 }; 4248 };
4654 }; 4249 };
4655 }; 4250 };
4656 4251
4657 ddr-thermal { 4252 ddr-thermal {
4658 polling-delay-passive 4253 polling-delay-passive = <250>;
>> 4254 polling-delay = <0>;
4659 4255
4660 thermal-sensors = <&t 4256 thermal-sensors = <&tsens1 3>;
4661 4257
4662 trips { 4258 trips {
4663 ddr_alert0: t 4259 ddr_alert0: trip-point0 {
4664 tempe 4260 temperature = <90000>;
4665 hyste 4261 hysteresis = <2000>;
4666 type 4262 type = "hot";
4667 }; 4263 };
4668 4264
4669 ddr_crit: ddr !! 4265 ddr_crit: ddr_crit {
4670 tempe 4266 temperature = <110000>;
4671 hyste 4267 hysteresis = <2000>;
4672 type 4268 type = "critical";
4673 }; 4269 };
4674 }; 4270 };
4675 }; 4271 };
4676 4272
4677 q6-hvx-thermal { 4273 q6-hvx-thermal {
4678 polling-delay-passive 4274 polling-delay-passive = <250>;
>> 4275 polling-delay = <0>;
4679 4276
4680 thermal-sensors = <&t 4277 thermal-sensors = <&tsens1 4>;
4681 4278
4682 trips { 4279 trips {
4683 q6_hvx_alert0 4280 q6_hvx_alert0: trip-point0 {
4684 tempe 4281 temperature = <90000>;
4685 hyste 4282 hysteresis = <2000>;
4686 type 4283 type = "hot";
4687 }; 4284 };
4688 4285
4689 q6_hvx_crit: !! 4286 q6_hvx_crit: q6_hvx_crit {
4690 tempe 4287 temperature = <110000>;
4691 hyste 4288 hysteresis = <2000>;
4692 type 4289 type = "critical";
4693 }; 4290 };
4694 }; 4291 };
4695 }; 4292 };
4696 4293
4697 camera-thermal { 4294 camera-thermal {
4698 polling-delay-passive 4295 polling-delay-passive = <250>;
>> 4296 polling-delay = <0>;
4699 4297
4700 thermal-sensors = <&t 4298 thermal-sensors = <&tsens1 5>;
4701 4299
4702 trips { 4300 trips {
4703 camera_alert0 4301 camera_alert0: trip-point0 {
4704 tempe 4302 temperature = <90000>;
4705 hyste 4303 hysteresis = <2000>;
4706 type 4304 type = "hot";
4707 }; 4305 };
4708 4306
4709 camera_crit: !! 4307 camera_crit: camera_crit {
4710 tempe 4308 temperature = <110000>;
4711 hyste 4309 hysteresis = <2000>;
4712 type 4310 type = "critical";
4713 }; 4311 };
4714 }; 4312 };
4715 }; 4313 };
4716 4314
4717 mdm-core-thermal { 4315 mdm-core-thermal {
4718 polling-delay-passive 4316 polling-delay-passive = <250>;
>> 4317 polling-delay = <0>;
4719 4318
4720 thermal-sensors = <&t 4319 thermal-sensors = <&tsens1 6>;
4721 4320
4722 trips { 4321 trips {
4723 mdm_alert0: t 4322 mdm_alert0: trip-point0 {
4724 tempe 4323 temperature = <90000>;
4725 hyste 4324 hysteresis = <2000>;
4726 type 4325 type = "hot";
4727 }; 4326 };
4728 4327
4729 mdm_crit: mdm !! 4328 mdm_crit: mdm_crit {
4730 tempe 4329 temperature = <110000>;
4731 hyste 4330 hysteresis = <2000>;
4732 type 4331 type = "critical";
4733 }; 4332 };
4734 }; 4333 };
4735 }; 4334 };
4736 4335
4737 mdm-dsp-thermal { 4336 mdm-dsp-thermal {
4738 polling-delay-passive 4337 polling-delay-passive = <250>;
>> 4338 polling-delay = <0>;
4739 4339
4740 thermal-sensors = <&t 4340 thermal-sensors = <&tsens1 7>;
4741 4341
4742 trips { 4342 trips {
4743 mdm_dsp_alert 4343 mdm_dsp_alert0: trip-point0 {
4744 tempe 4344 temperature = <90000>;
4745 hyste 4345 hysteresis = <2000>;
4746 type 4346 type = "hot";
4747 }; 4347 };
4748 4348
4749 mdm_dsp_crit: !! 4349 mdm_dsp_crit: mdm_dsp_crit {
4750 tempe 4350 temperature = <110000>;
4751 hyste 4351 hysteresis = <2000>;
4752 type 4352 type = "critical";
4753 }; 4353 };
4754 }; 4354 };
4755 }; 4355 };
4756 4356
4757 npu-thermal { 4357 npu-thermal {
4758 polling-delay-passive 4358 polling-delay-passive = <250>;
>> 4359 polling-delay = <0>;
4759 4360
4760 thermal-sensors = <&t 4361 thermal-sensors = <&tsens1 8>;
4761 4362
4762 trips { 4363 trips {
4763 npu_alert0: t 4364 npu_alert0: trip-point0 {
4764 tempe 4365 temperature = <90000>;
4765 hyste 4366 hysteresis = <2000>;
4766 type 4367 type = "hot";
4767 }; 4368 };
4768 4369
4769 npu_crit: npu !! 4370 npu_crit: npu_crit {
4770 tempe 4371 temperature = <110000>;
4771 hyste 4372 hysteresis = <2000>;
4772 type 4373 type = "critical";
4773 }; 4374 };
4774 }; 4375 };
4775 }; 4376 };
4776 4377
4777 video-thermal { 4378 video-thermal {
4778 polling-delay-passive 4379 polling-delay-passive = <250>;
>> 4380 polling-delay = <0>;
4779 4381
4780 thermal-sensors = <&t 4382 thermal-sensors = <&tsens1 9>;
4781 4383
4782 trips { 4384 trips {
4783 video_alert0: 4385 video_alert0: trip-point0 {
4784 tempe 4386 temperature = <90000>;
4785 hyste 4387 hysteresis = <2000>;
4786 type 4388 type = "hot";
4787 }; 4389 };
4788 4390
4789 video_crit: v !! 4391 video_crit: video_crit {
4790 tempe 4392 temperature = <110000>;
4791 hyste 4393 hysteresis = <2000>;
4792 type 4394 type = "critical";
4793 }; 4395 };
4794 }; 4396 };
4795 }; 4397 };
4796 }; 4398 };
4797 4399
4798 timer { 4400 timer {
4799 compatible = "arm,armv8-timer 4401 compatible = "arm,armv8-timer";
4800 interrupts = <GIC_PPI 1 IRQ_T 4402 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
4801 <GIC_PPI 2 IRQ_T 4403 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
4802 <GIC_PPI 3 IRQ_T 4404 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
4803 <GIC_PPI 0 IRQ_T 4405 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
4804 }; 4406 };
4805 }; 4407 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.