1 // SPDX-License-Identifier: BSD-3-Clause 1 // SPDX-License-Identifier: BSD-3-Clause
2 /* 2 /*
3 * SC7180 SoC device tree source 3 * SC7180 SoC device tree source
4 * 4 *
5 * Copyright (c) 2019-2020, The Linux Foundati 5 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
6 */ 6 */
7 7
8 #include <dt-bindings/clock/qcom,dispcc-sc7180 8 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
9 #include <dt-bindings/clock/qcom,gcc-sc7180.h> 9 #include <dt-bindings/clock/qcom,gcc-sc7180.h>
10 #include <dt-bindings/clock/qcom,gpucc-sc7180. 10 #include <dt-bindings/clock/qcom,gpucc-sc7180.h>
11 #include <dt-bindings/clock/qcom,lpasscorecc-s 11 #include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h>
12 #include <dt-bindings/clock/qcom,rpmh.h> 12 #include <dt-bindings/clock/qcom,rpmh.h>
13 #include <dt-bindings/clock/qcom,videocc-sc718 13 #include <dt-bindings/clock/qcom,videocc-sc7180.h>
14 #include <dt-bindings/firmware/qcom,scm.h> <<
15 #include <dt-bindings/interconnect/qcom,icc.h> <<
16 #include <dt-bindings/interconnect/qcom,osm-l3 14 #include <dt-bindings/interconnect/qcom,osm-l3.h>
17 #include <dt-bindings/interconnect/qcom,sc7180 15 #include <dt-bindings/interconnect/qcom,sc7180.h>
18 #include <dt-bindings/interrupt-controller/arm 16 #include <dt-bindings/interrupt-controller/arm-gic.h>
19 #include <dt-bindings/phy/phy-qcom-qmp.h> <<
20 #include <dt-bindings/phy/phy-qcom-qusb2.h> 17 #include <dt-bindings/phy/phy-qcom-qusb2.h>
>> 18 #include <dt-bindings/power/qcom-aoss-qmp.h>
21 #include <dt-bindings/power/qcom-rpmpd.h> 19 #include <dt-bindings/power/qcom-rpmpd.h>
22 #include <dt-bindings/reset/qcom,sdm845-aoss.h 20 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
23 #include <dt-bindings/reset/qcom,sdm845-pdc.h> 21 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
24 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 22 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
25 #include <dt-bindings/soc/qcom,apr.h> <<
26 #include <dt-bindings/sound/qcom,q6afe.h> <<
27 #include <dt-bindings/thermal/thermal.h> 23 #include <dt-bindings/thermal/thermal.h>
28 24
29 / { 25 / {
30 interrupt-parent = <&intc>; 26 interrupt-parent = <&intc>;
31 27
32 #address-cells = <2>; 28 #address-cells = <2>;
33 #size-cells = <2>; 29 #size-cells = <2>;
34 30
>> 31 chosen { };
>> 32
35 aliases { 33 aliases {
36 mmc1 = &sdhc_1; 34 mmc1 = &sdhc_1;
37 mmc2 = &sdhc_2; 35 mmc2 = &sdhc_2;
38 i2c0 = &i2c0; 36 i2c0 = &i2c0;
39 i2c1 = &i2c1; 37 i2c1 = &i2c1;
40 i2c2 = &i2c2; 38 i2c2 = &i2c2;
41 i2c3 = &i2c3; 39 i2c3 = &i2c3;
42 i2c4 = &i2c4; 40 i2c4 = &i2c4;
43 i2c5 = &i2c5; 41 i2c5 = &i2c5;
44 i2c6 = &i2c6; 42 i2c6 = &i2c6;
45 i2c7 = &i2c7; 43 i2c7 = &i2c7;
46 i2c8 = &i2c8; 44 i2c8 = &i2c8;
47 i2c9 = &i2c9; 45 i2c9 = &i2c9;
48 i2c10 = &i2c10; 46 i2c10 = &i2c10;
49 i2c11 = &i2c11; 47 i2c11 = &i2c11;
50 spi0 = &spi0; 48 spi0 = &spi0;
51 spi1 = &spi1; 49 spi1 = &spi1;
52 spi3 = &spi3; 50 spi3 = &spi3;
53 spi5 = &spi5; 51 spi5 = &spi5;
54 spi6 = &spi6; 52 spi6 = &spi6;
55 spi8 = &spi8; 53 spi8 = &spi8;
56 spi10 = &spi10; 54 spi10 = &spi10;
57 spi11 = &spi11; 55 spi11 = &spi11;
58 }; 56 };
59 57
60 chosen { }; <<
61 <<
62 clocks { 58 clocks {
63 xo_board: xo-board { 59 xo_board: xo-board {
64 compatible = "fixed-cl 60 compatible = "fixed-clock";
65 clock-frequency = <384 61 clock-frequency = <38400000>;
66 #clock-cells = <0>; 62 #clock-cells = <0>;
67 }; 63 };
68 64
69 sleep_clk: sleep-clk { 65 sleep_clk: sleep-clk {
70 compatible = "fixed-cl 66 compatible = "fixed-clock";
71 clock-frequency = <327 67 clock-frequency = <32764>;
72 #clock-cells = <0>; 68 #clock-cells = <0>;
73 }; 69 };
74 }; 70 };
75 71
>> 72 reserved_memory: reserved-memory {
>> 73 #address-cells = <2>;
>> 74 #size-cells = <2>;
>> 75 ranges;
>> 76
>> 77 hyp_mem: memory@80000000 {
>> 78 reg = <0x0 0x80000000 0x0 0x600000>;
>> 79 no-map;
>> 80 };
>> 81
>> 82 xbl_mem: memory@80600000 {
>> 83 reg = <0x0 0x80600000 0x0 0x200000>;
>> 84 no-map;
>> 85 };
>> 86
>> 87 aop_mem: memory@80800000 {
>> 88 reg = <0x0 0x80800000 0x0 0x20000>;
>> 89 no-map;
>> 90 };
>> 91
>> 92 aop_cmd_db_mem: memory@80820000 {
>> 93 reg = <0x0 0x80820000 0x0 0x20000>;
>> 94 compatible = "qcom,cmd-db";
>> 95 no-map;
>> 96 };
>> 97
>> 98 sec_apps_mem: memory@808ff000 {
>> 99 reg = <0x0 0x808ff000 0x0 0x1000>;
>> 100 no-map;
>> 101 };
>> 102
>> 103 smem_mem: memory@80900000 {
>> 104 reg = <0x0 0x80900000 0x0 0x200000>;
>> 105 no-map;
>> 106 };
>> 107
>> 108 tz_mem: memory@80b00000 {
>> 109 reg = <0x0 0x80b00000 0x0 0x3900000>;
>> 110 no-map;
>> 111 };
>> 112
>> 113 ipa_fw_mem: memory@8b700000 {
>> 114 reg = <0 0x8b700000 0 0x10000>;
>> 115 no-map;
>> 116 };
>> 117
>> 118 rmtfs_mem: memory@94600000 {
>> 119 compatible = "qcom,rmtfs-mem";
>> 120 reg = <0x0 0x94600000 0x0 0x200000>;
>> 121 no-map;
>> 122
>> 123 qcom,client-id = <1>;
>> 124 qcom,vmid = <15>;
>> 125 };
>> 126 };
>> 127
76 cpus { 128 cpus {
77 #address-cells = <2>; 129 #address-cells = <2>;
78 #size-cells = <0>; 130 #size-cells = <0>;
79 131
80 CPU0: cpu@0 { 132 CPU0: cpu@0 {
81 device_type = "cpu"; 133 device_type = "cpu";
82 compatible = "qcom,kry 134 compatible = "qcom,kryo468";
83 reg = <0x0 0x0>; 135 reg = <0x0 0x0>;
84 clocks = <&cpufreq_hw <<
85 enable-method = "psci" 136 enable-method = "psci";
86 power-domains = <&CPU_ !! 137 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
87 power-domain-names = " !! 138 &LITTLE_CPU_SLEEP_1
>> 139 &CLUSTER_SLEEP_0>;
88 capacity-dmips-mhz = < 140 capacity-dmips-mhz = <415>;
89 dynamic-power-coeffici 141 dynamic-power-coefficient = <137>;
90 operating-points-v2 = 142 operating-points-v2 = <&cpu0_opp_table>;
91 interconnects = <&gem_ 143 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
92 <&osm_ 144 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
93 next-level-cache = <&L 145 next-level-cache = <&L2_0>;
94 #cooling-cells = <2>; 146 #cooling-cells = <2>;
95 qcom,freq-domain = <&c 147 qcom,freq-domain = <&cpufreq_hw 0>;
96 L2_0: l2-cache { 148 L2_0: l2-cache {
97 compatible = " 149 compatible = "cache";
98 cache-level = <<
99 cache-unified; <<
100 next-level-cac 150 next-level-cache = <&L3_0>;
101 L3_0: l3-cache 151 L3_0: l3-cache {
102 compat 152 compatible = "cache";
103 cache- <<
104 cache- <<
105 }; 153 };
106 }; 154 };
107 }; 155 };
108 156
109 CPU1: cpu@100 { 157 CPU1: cpu@100 {
110 device_type = "cpu"; 158 device_type = "cpu";
111 compatible = "qcom,kry 159 compatible = "qcom,kryo468";
112 reg = <0x0 0x100>; 160 reg = <0x0 0x100>;
113 clocks = <&cpufreq_hw <<
114 enable-method = "psci" 161 enable-method = "psci";
115 power-domains = <&CPU_ !! 162 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
116 power-domain-names = " !! 163 &LITTLE_CPU_SLEEP_1
>> 164 &CLUSTER_SLEEP_0>;
117 capacity-dmips-mhz = < 165 capacity-dmips-mhz = <415>;
118 dynamic-power-coeffici 166 dynamic-power-coefficient = <137>;
119 next-level-cache = <&L 167 next-level-cache = <&L2_100>;
120 operating-points-v2 = 168 operating-points-v2 = <&cpu0_opp_table>;
121 interconnects = <&gem_ 169 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
122 <&osm_ 170 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
123 #cooling-cells = <2>; 171 #cooling-cells = <2>;
124 qcom,freq-domain = <&c 172 qcom,freq-domain = <&cpufreq_hw 0>;
125 L2_100: l2-cache { 173 L2_100: l2-cache {
126 compatible = " 174 compatible = "cache";
127 cache-level = <<
128 cache-unified; <<
129 next-level-cac 175 next-level-cache = <&L3_0>;
130 }; 176 };
131 }; 177 };
132 178
133 CPU2: cpu@200 { 179 CPU2: cpu@200 {
134 device_type = "cpu"; 180 device_type = "cpu";
135 compatible = "qcom,kry 181 compatible = "qcom,kryo468";
136 reg = <0x0 0x200>; 182 reg = <0x0 0x200>;
137 clocks = <&cpufreq_hw <<
138 enable-method = "psci" 183 enable-method = "psci";
139 power-domains = <&CPU_ !! 184 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
140 power-domain-names = " !! 185 &LITTLE_CPU_SLEEP_1
>> 186 &CLUSTER_SLEEP_0>;
141 capacity-dmips-mhz = < 187 capacity-dmips-mhz = <415>;
142 dynamic-power-coeffici 188 dynamic-power-coefficient = <137>;
143 next-level-cache = <&L 189 next-level-cache = <&L2_200>;
144 operating-points-v2 = 190 operating-points-v2 = <&cpu0_opp_table>;
145 interconnects = <&gem_ 191 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
146 <&osm_ 192 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
147 #cooling-cells = <2>; 193 #cooling-cells = <2>;
148 qcom,freq-domain = <&c 194 qcom,freq-domain = <&cpufreq_hw 0>;
149 L2_200: l2-cache { 195 L2_200: l2-cache {
150 compatible = " 196 compatible = "cache";
151 cache-level = <<
152 cache-unified; <<
153 next-level-cac 197 next-level-cache = <&L3_0>;
154 }; 198 };
155 }; 199 };
156 200
157 CPU3: cpu@300 { 201 CPU3: cpu@300 {
158 device_type = "cpu"; 202 device_type = "cpu";
159 compatible = "qcom,kry 203 compatible = "qcom,kryo468";
160 reg = <0x0 0x300>; 204 reg = <0x0 0x300>;
161 clocks = <&cpufreq_hw <<
162 enable-method = "psci" 205 enable-method = "psci";
163 power-domains = <&CPU_ !! 206 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
164 power-domain-names = " !! 207 &LITTLE_CPU_SLEEP_1
>> 208 &CLUSTER_SLEEP_0>;
165 capacity-dmips-mhz = < 209 capacity-dmips-mhz = <415>;
166 dynamic-power-coeffici 210 dynamic-power-coefficient = <137>;
167 next-level-cache = <&L 211 next-level-cache = <&L2_300>;
168 operating-points-v2 = 212 operating-points-v2 = <&cpu0_opp_table>;
169 interconnects = <&gem_ 213 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
170 <&osm_ 214 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
171 #cooling-cells = <2>; 215 #cooling-cells = <2>;
172 qcom,freq-domain = <&c 216 qcom,freq-domain = <&cpufreq_hw 0>;
173 L2_300: l2-cache { 217 L2_300: l2-cache {
174 compatible = " 218 compatible = "cache";
175 cache-level = <<
176 cache-unified; <<
177 next-level-cac 219 next-level-cache = <&L3_0>;
178 }; 220 };
179 }; 221 };
180 222
181 CPU4: cpu@400 { 223 CPU4: cpu@400 {
182 device_type = "cpu"; 224 device_type = "cpu";
183 compatible = "qcom,kry 225 compatible = "qcom,kryo468";
184 reg = <0x0 0x400>; 226 reg = <0x0 0x400>;
185 clocks = <&cpufreq_hw <<
186 enable-method = "psci" 227 enable-method = "psci";
187 power-domains = <&CPU_ !! 228 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
188 power-domain-names = " !! 229 &LITTLE_CPU_SLEEP_1
>> 230 &CLUSTER_SLEEP_0>;
189 capacity-dmips-mhz = < 231 capacity-dmips-mhz = <415>;
190 dynamic-power-coeffici 232 dynamic-power-coefficient = <137>;
191 next-level-cache = <&L 233 next-level-cache = <&L2_400>;
192 operating-points-v2 = 234 operating-points-v2 = <&cpu0_opp_table>;
193 interconnects = <&gem_ 235 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
194 <&osm_ 236 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
195 #cooling-cells = <2>; 237 #cooling-cells = <2>;
196 qcom,freq-domain = <&c 238 qcom,freq-domain = <&cpufreq_hw 0>;
197 L2_400: l2-cache { 239 L2_400: l2-cache {
198 compatible = " 240 compatible = "cache";
199 cache-level = <<
200 cache-unified; <<
201 next-level-cac 241 next-level-cache = <&L3_0>;
202 }; 242 };
203 }; 243 };
204 244
205 CPU5: cpu@500 { 245 CPU5: cpu@500 {
206 device_type = "cpu"; 246 device_type = "cpu";
207 compatible = "qcom,kry 247 compatible = "qcom,kryo468";
208 reg = <0x0 0x500>; 248 reg = <0x0 0x500>;
209 clocks = <&cpufreq_hw <<
210 enable-method = "psci" 249 enable-method = "psci";
211 power-domains = <&CPU_ !! 250 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
212 power-domain-names = " !! 251 &LITTLE_CPU_SLEEP_1
>> 252 &CLUSTER_SLEEP_0>;
213 capacity-dmips-mhz = < 253 capacity-dmips-mhz = <415>;
214 dynamic-power-coeffici 254 dynamic-power-coefficient = <137>;
215 next-level-cache = <&L 255 next-level-cache = <&L2_500>;
216 operating-points-v2 = 256 operating-points-v2 = <&cpu0_opp_table>;
217 interconnects = <&gem_ 257 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
218 <&osm_ 258 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
219 #cooling-cells = <2>; 259 #cooling-cells = <2>;
220 qcom,freq-domain = <&c 260 qcom,freq-domain = <&cpufreq_hw 0>;
221 L2_500: l2-cache { 261 L2_500: l2-cache {
222 compatible = " 262 compatible = "cache";
223 cache-level = <<
224 cache-unified; <<
225 next-level-cac 263 next-level-cache = <&L3_0>;
226 }; 264 };
227 }; 265 };
228 266
229 CPU6: cpu@600 { 267 CPU6: cpu@600 {
230 device_type = "cpu"; 268 device_type = "cpu";
231 compatible = "qcom,kry 269 compatible = "qcom,kryo468";
232 reg = <0x0 0x600>; 270 reg = <0x0 0x600>;
233 clocks = <&cpufreq_hw <<
234 enable-method = "psci" 271 enable-method = "psci";
235 power-domains = <&CPU_ !! 272 cpu-idle-states = <&BIG_CPU_SLEEP_0
236 power-domain-names = " !! 273 &BIG_CPU_SLEEP_1
>> 274 &CLUSTER_SLEEP_0>;
237 capacity-dmips-mhz = < 275 capacity-dmips-mhz = <1024>;
238 dynamic-power-coeffici 276 dynamic-power-coefficient = <480>;
239 next-level-cache = <&L 277 next-level-cache = <&L2_600>;
240 operating-points-v2 = 278 operating-points-v2 = <&cpu6_opp_table>;
241 interconnects = <&gem_ 279 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
242 <&osm_ 280 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
243 #cooling-cells = <2>; 281 #cooling-cells = <2>;
244 qcom,freq-domain = <&c 282 qcom,freq-domain = <&cpufreq_hw 1>;
245 L2_600: l2-cache { 283 L2_600: l2-cache {
246 compatible = " 284 compatible = "cache";
247 cache-level = <<
248 cache-unified; <<
249 next-level-cac 285 next-level-cache = <&L3_0>;
250 }; 286 };
251 }; 287 };
252 288
253 CPU7: cpu@700 { 289 CPU7: cpu@700 {
254 device_type = "cpu"; 290 device_type = "cpu";
255 compatible = "qcom,kry 291 compatible = "qcom,kryo468";
256 reg = <0x0 0x700>; 292 reg = <0x0 0x700>;
257 clocks = <&cpufreq_hw <<
258 enable-method = "psci" 293 enable-method = "psci";
259 power-domains = <&CPU_ !! 294 cpu-idle-states = <&BIG_CPU_SLEEP_0
260 power-domain-names = " !! 295 &BIG_CPU_SLEEP_1
>> 296 &CLUSTER_SLEEP_0>;
261 capacity-dmips-mhz = < 297 capacity-dmips-mhz = <1024>;
262 dynamic-power-coeffici 298 dynamic-power-coefficient = <480>;
263 next-level-cache = <&L 299 next-level-cache = <&L2_700>;
264 operating-points-v2 = 300 operating-points-v2 = <&cpu6_opp_table>;
265 interconnects = <&gem_ 301 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
266 <&osm_ 302 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
267 #cooling-cells = <2>; 303 #cooling-cells = <2>;
268 qcom,freq-domain = <&c 304 qcom,freq-domain = <&cpufreq_hw 1>;
269 L2_700: l2-cache { 305 L2_700: l2-cache {
270 compatible = " 306 compatible = "cache";
271 cache-level = <<
272 cache-unified; <<
273 next-level-cac 307 next-level-cache = <&L3_0>;
274 }; 308 };
275 }; 309 };
276 310
277 cpu-map { 311 cpu-map {
278 cluster0 { 312 cluster0 {
279 core0 { 313 core0 {
280 cpu = 314 cpu = <&CPU0>;
281 }; 315 };
282 316
283 core1 { 317 core1 {
284 cpu = 318 cpu = <&CPU1>;
285 }; 319 };
286 320
287 core2 { 321 core2 {
288 cpu = 322 cpu = <&CPU2>;
289 }; 323 };
290 324
291 core3 { 325 core3 {
292 cpu = 326 cpu = <&CPU3>;
293 }; 327 };
294 328
295 core4 { 329 core4 {
296 cpu = 330 cpu = <&CPU4>;
297 }; 331 };
298 332
299 core5 { 333 core5 {
300 cpu = 334 cpu = <&CPU5>;
301 }; 335 };
302 336
303 core6 { 337 core6 {
304 cpu = 338 cpu = <&CPU6>;
305 }; 339 };
306 340
307 core7 { 341 core7 {
308 cpu = 342 cpu = <&CPU7>;
309 }; 343 };
310 }; 344 };
311 }; 345 };
312 346
313 idle_states: idle-states { !! 347 idle-states {
314 entry-method = "psci"; 348 entry-method = "psci";
315 349
316 LITTLE_CPU_SLEEP_0: cp 350 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
317 compatible = " 351 compatible = "arm,idle-state";
318 idle-state-nam 352 idle-state-name = "little-power-down";
319 arm,psci-suspe 353 arm,psci-suspend-param = <0x40000003>;
320 entry-latency- 354 entry-latency-us = <549>;
321 exit-latency-u 355 exit-latency-us = <901>;
322 min-residency- 356 min-residency-us = <1774>;
323 local-timer-st 357 local-timer-stop;
324 }; 358 };
325 359
326 LITTLE_CPU_SLEEP_1: cp 360 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
327 compatible = " 361 compatible = "arm,idle-state";
328 idle-state-nam 362 idle-state-name = "little-rail-power-down";
329 arm,psci-suspe 363 arm,psci-suspend-param = <0x40000004>;
330 entry-latency- 364 entry-latency-us = <702>;
331 exit-latency-u 365 exit-latency-us = <915>;
332 min-residency- 366 min-residency-us = <4001>;
333 local-timer-st 367 local-timer-stop;
334 }; 368 };
335 369
336 BIG_CPU_SLEEP_0: cpu-s 370 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
337 compatible = " 371 compatible = "arm,idle-state";
338 idle-state-nam 372 idle-state-name = "big-power-down";
339 arm,psci-suspe 373 arm,psci-suspend-param = <0x40000003>;
340 entry-latency- 374 entry-latency-us = <523>;
341 exit-latency-u 375 exit-latency-us = <1244>;
342 min-residency- 376 min-residency-us = <2207>;
343 local-timer-st 377 local-timer-stop;
344 }; 378 };
345 379
346 BIG_CPU_SLEEP_1: cpu-s 380 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
347 compatible = " 381 compatible = "arm,idle-state";
348 idle-state-nam 382 idle-state-name = "big-rail-power-down";
349 arm,psci-suspe 383 arm,psci-suspend-param = <0x40000004>;
350 entry-latency- 384 entry-latency-us = <526>;
351 exit-latency-u 385 exit-latency-us = <1854>;
352 min-residency- 386 min-residency-us = <5555>;
353 local-timer-st 387 local-timer-stop;
354 }; 388 };
355 }; <<
356 389
357 domain_idle_states: domain-idl !! 390 CLUSTER_SLEEP_0: cluster-sleep-0 {
358 CLUSTER_SLEEP_PC: clus !! 391 compatible = "arm,idle-state";
359 compatible = " <<
360 idle-state-nam <<
361 arm,psci-suspe <<
362 entry-latency- <<
363 exit-latency-u <<
364 min-residency- <<
365 }; <<
366 <<
367 CLUSTER_SLEEP_CX_RET: <<
368 compatible = " <<
369 idle-state-nam <<
370 arm,psci-suspe <<
371 entry-latency- <<
372 exit-latency-u <<
373 min-residency- <<
374 }; <<
375 <<
376 CLUSTER_AOSS_SLEEP: cl <<
377 compatible = " <<
378 idle-state-nam 392 idle-state-name = "cluster-power-down";
379 arm,psci-suspe !! 393 arm,psci-suspend-param = <0x40003444>;
380 entry-latency- 394 entry-latency-us = <3263>;
381 exit-latency-u 395 exit-latency-us = <6562>;
382 min-residency- !! 396 min-residency-us = <9926>;
>> 397 local-timer-stop;
383 }; 398 };
384 }; 399 };
385 }; 400 };
386 401
387 firmware { !! 402 cpu0_opp_table: cpu0_opp_table {
388 scm: scm { <<
389 compatible = "qcom,scm <<
390 }; <<
391 }; <<
392 <<
393 memory@80000000 { <<
394 device_type = "memory"; <<
395 /* We expect the bootloader to <<
396 reg = <0 0x80000000 0 0>; <<
397 }; <<
398 <<
399 cpu0_opp_table: opp-table-cpu0 { <<
400 compatible = "operating-points 403 compatible = "operating-points-v2";
401 opp-shared; 404 opp-shared;
402 405
403 cpu0_opp1: opp-300000000 { 406 cpu0_opp1: opp-300000000 {
404 opp-hz = /bits/ 64 <30 407 opp-hz = /bits/ 64 <300000000>;
405 opp-peak-kBps = <12000 408 opp-peak-kBps = <1200000 4800000>;
406 }; 409 };
407 410
408 cpu0_opp2: opp-576000000 { 411 cpu0_opp2: opp-576000000 {
409 opp-hz = /bits/ 64 <57 412 opp-hz = /bits/ 64 <576000000>;
410 opp-peak-kBps = <12000 413 opp-peak-kBps = <1200000 4800000>;
411 }; 414 };
412 415
413 cpu0_opp3: opp-768000000 { 416 cpu0_opp3: opp-768000000 {
414 opp-hz = /bits/ 64 <76 417 opp-hz = /bits/ 64 <768000000>;
415 opp-peak-kBps = <12000 418 opp-peak-kBps = <1200000 4800000>;
416 }; 419 };
417 420
418 cpu0_opp4: opp-1017600000 { 421 cpu0_opp4: opp-1017600000 {
419 opp-hz = /bits/ 64 <10 422 opp-hz = /bits/ 64 <1017600000>;
420 opp-peak-kBps = <18040 423 opp-peak-kBps = <1804000 8908800>;
421 }; 424 };
422 425
423 cpu0_opp5: opp-1248000000 { 426 cpu0_opp5: opp-1248000000 {
424 opp-hz = /bits/ 64 <12 427 opp-hz = /bits/ 64 <1248000000>;
425 opp-peak-kBps = <21880 428 opp-peak-kBps = <2188000 12902400>;
426 }; 429 };
427 430
428 cpu0_opp6: opp-1324800000 { 431 cpu0_opp6: opp-1324800000 {
429 opp-hz = /bits/ 64 <13 432 opp-hz = /bits/ 64 <1324800000>;
430 opp-peak-kBps = <21880 433 opp-peak-kBps = <2188000 12902400>;
431 }; 434 };
432 435
433 cpu0_opp7: opp-1516800000 { 436 cpu0_opp7: opp-1516800000 {
434 opp-hz = /bits/ 64 <15 437 opp-hz = /bits/ 64 <1516800000>;
435 opp-peak-kBps = <30720 438 opp-peak-kBps = <3072000 15052800>;
436 }; 439 };
437 440
438 cpu0_opp8: opp-1612800000 { 441 cpu0_opp8: opp-1612800000 {
439 opp-hz = /bits/ 64 <16 442 opp-hz = /bits/ 64 <1612800000>;
440 opp-peak-kBps = <30720 443 opp-peak-kBps = <3072000 15052800>;
441 }; 444 };
442 445
443 cpu0_opp9: opp-1708800000 { 446 cpu0_opp9: opp-1708800000 {
444 opp-hz = /bits/ 64 <17 447 opp-hz = /bits/ 64 <1708800000>;
445 opp-peak-kBps = <30720 448 opp-peak-kBps = <3072000 15052800>;
446 }; 449 };
447 450
448 cpu0_opp10: opp-1804800000 { 451 cpu0_opp10: opp-1804800000 {
449 opp-hz = /bits/ 64 <18 452 opp-hz = /bits/ 64 <1804800000>;
450 opp-peak-kBps = <40680 453 opp-peak-kBps = <4068000 22425600>;
451 }; 454 };
452 }; 455 };
453 456
454 cpu6_opp_table: opp-table-cpu6 { !! 457 cpu6_opp_table: cpu6_opp_table {
455 compatible = "operating-points 458 compatible = "operating-points-v2";
456 opp-shared; 459 opp-shared;
457 460
458 cpu6_opp1: opp-300000000 { 461 cpu6_opp1: opp-300000000 {
459 opp-hz = /bits/ 64 <30 462 opp-hz = /bits/ 64 <300000000>;
460 opp-peak-kBps = <21880 463 opp-peak-kBps = <2188000 8908800>;
461 }; 464 };
462 465
463 cpu6_opp2: opp-652800000 { 466 cpu6_opp2: opp-652800000 {
464 opp-hz = /bits/ 64 <65 467 opp-hz = /bits/ 64 <652800000>;
465 opp-peak-kBps = <21880 468 opp-peak-kBps = <2188000 8908800>;
466 }; 469 };
467 470
468 cpu6_opp3: opp-825600000 { 471 cpu6_opp3: opp-825600000 {
469 opp-hz = /bits/ 64 <82 472 opp-hz = /bits/ 64 <825600000>;
470 opp-peak-kBps = <21880 473 opp-peak-kBps = <2188000 8908800>;
471 }; 474 };
472 475
473 cpu6_opp4: opp-979200000 { 476 cpu6_opp4: opp-979200000 {
474 opp-hz = /bits/ 64 <97 477 opp-hz = /bits/ 64 <979200000>;
475 opp-peak-kBps = <21880 478 opp-peak-kBps = <2188000 8908800>;
476 }; 479 };
477 480
478 cpu6_opp5: opp-1113600000 { 481 cpu6_opp5: opp-1113600000 {
479 opp-hz = /bits/ 64 <11 482 opp-hz = /bits/ 64 <1113600000>;
480 opp-peak-kBps = <21880 483 opp-peak-kBps = <2188000 8908800>;
481 }; 484 };
482 485
483 cpu6_opp6: opp-1267200000 { 486 cpu6_opp6: opp-1267200000 {
484 opp-hz = /bits/ 64 <12 487 opp-hz = /bits/ 64 <1267200000>;
485 opp-peak-kBps = <40680 488 opp-peak-kBps = <4068000 12902400>;
486 }; 489 };
487 490
488 cpu6_opp7: opp-1555200000 { 491 cpu6_opp7: opp-1555200000 {
489 opp-hz = /bits/ 64 <15 492 opp-hz = /bits/ 64 <1555200000>;
490 opp-peak-kBps = <40680 493 opp-peak-kBps = <4068000 15052800>;
491 }; 494 };
492 495
493 cpu6_opp8: opp-1708800000 { 496 cpu6_opp8: opp-1708800000 {
494 opp-hz = /bits/ 64 <17 497 opp-hz = /bits/ 64 <1708800000>;
495 opp-peak-kBps = <62200 498 opp-peak-kBps = <6220000 19353600>;
496 }; 499 };
497 500
498 cpu6_opp9: opp-1843200000 { 501 cpu6_opp9: opp-1843200000 {
499 opp-hz = /bits/ 64 <18 502 opp-hz = /bits/ 64 <1843200000>;
500 opp-peak-kBps = <62200 503 opp-peak-kBps = <6220000 19353600>;
501 }; 504 };
502 505
503 cpu6_opp10: opp-1900800000 { 506 cpu6_opp10: opp-1900800000 {
504 opp-hz = /bits/ 64 <19 507 opp-hz = /bits/ 64 <1900800000>;
505 opp-peak-kBps = <62200 508 opp-peak-kBps = <6220000 22425600>;
506 }; 509 };
507 510
508 cpu6_opp11: opp-1996800000 { 511 cpu6_opp11: opp-1996800000 {
509 opp-hz = /bits/ 64 <19 512 opp-hz = /bits/ 64 <1996800000>;
510 opp-peak-kBps = <62200 513 opp-peak-kBps = <6220000 22425600>;
511 }; 514 };
512 515
513 cpu6_opp12: opp-2112000000 { 516 cpu6_opp12: opp-2112000000 {
514 opp-hz = /bits/ 64 <21 517 opp-hz = /bits/ 64 <2112000000>;
515 opp-peak-kBps = <62200 518 opp-peak-kBps = <6220000 22425600>;
516 }; 519 };
517 520
518 cpu6_opp13: opp-2208000000 { 521 cpu6_opp13: opp-2208000000 {
519 opp-hz = /bits/ 64 <22 522 opp-hz = /bits/ 64 <2208000000>;
520 opp-peak-kBps = <72160 523 opp-peak-kBps = <7216000 22425600>;
521 }; 524 };
522 525
523 cpu6_opp14: opp-2323200000 { 526 cpu6_opp14: opp-2323200000 {
524 opp-hz = /bits/ 64 <23 527 opp-hz = /bits/ 64 <2323200000>;
525 opp-peak-kBps = <72160 528 opp-peak-kBps = <7216000 22425600>;
526 }; 529 };
527 530
528 cpu6_opp15: opp-2400000000 { 531 cpu6_opp15: opp-2400000000 {
529 opp-hz = /bits/ 64 <24 532 opp-hz = /bits/ 64 <2400000000>;
530 opp-peak-kBps = <85320 533 opp-peak-kBps = <8532000 23347200>;
531 }; 534 };
532 535
533 cpu6_opp16: opp-2553600000 { 536 cpu6_opp16: opp-2553600000 {
534 opp-hz = /bits/ 64 <25 537 opp-hz = /bits/ 64 <2553600000>;
535 opp-peak-kBps = <85320 538 opp-peak-kBps = <8532000 23347200>;
536 }; 539 };
537 }; 540 };
538 541
539 qspi_opp_table: opp-table-qspi { !! 542 memory@80000000 {
540 compatible = "operating-points !! 543 device_type = "memory";
541 !! 544 /* We expect the bootloader to fill in the size */
542 opp-75000000 { !! 545 reg = <0 0x80000000 0 0>;
543 opp-hz = /bits/ 64 <75 <<
544 required-opps = <&rpmh <<
545 }; <<
546 <<
547 opp-150000000 { <<
548 opp-hz = /bits/ 64 <15 <<
549 required-opps = <&rpmh <<
550 }; <<
551 <<
552 opp-300000000 { <<
553 opp-hz = /bits/ 64 <30 <<
554 required-opps = <&rpmh <<
555 }; <<
556 }; <<
557 <<
558 qup_opp_table: opp-table-qup { <<
559 compatible = "operating-points <<
560 <<
561 opp-75000000 { <<
562 opp-hz = /bits/ 64 <75 <<
563 required-opps = <&rpmh <<
564 }; <<
565 <<
566 opp-100000000 { <<
567 opp-hz = /bits/ 64 <10 <<
568 required-opps = <&rpmh <<
569 }; <<
570 <<
571 opp-128000000 { <<
572 opp-hz = /bits/ 64 <12 <<
573 required-opps = <&rpmh <<
574 }; <<
575 }; 546 };
576 547
577 pmu { 548 pmu {
578 compatible = "arm,armv8-pmuv3" 549 compatible = "arm,armv8-pmuv3";
579 interrupts = <GIC_PPI 5 IRQ_TY 550 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
580 }; 551 };
581 552
582 psci { !! 553 firmware {
583 compatible = "arm,psci-1.0"; !! 554 scm {
584 method = "smc"; !! 555 compatible = "qcom,scm-sc7180", "qcom,scm";
585 <<
586 CPU_PD0: cpu0 { <<
587 #power-domain-cells = <<
588 power-domains = <&CLUS <<
589 domain-idle-states = < <<
590 }; <<
591 <<
592 CPU_PD1: cpu1 { <<
593 #power-domain-cells = <<
594 power-domains = <&CLUS <<
595 domain-idle-states = < <<
596 }; <<
597 <<
598 CPU_PD2: cpu2 { <<
599 #power-domain-cells = <<
600 power-domains = <&CLUS <<
601 domain-idle-states = < <<
602 }; <<
603 <<
604 CPU_PD3: cpu3 { <<
605 #power-domain-cells = <<
606 power-domains = <&CLUS <<
607 domain-idle-states = < <<
608 }; <<
609 <<
610 CPU_PD4: cpu4 { <<
611 #power-domain-cells = <<
612 power-domains = <&CLUS <<
613 domain-idle-states = < <<
614 }; <<
615 <<
616 CPU_PD5: cpu5 { <<
617 #power-domain-cells = <<
618 power-domains = <&CLUS <<
619 domain-idle-states = < <<
620 }; <<
621 <<
622 CPU_PD6: cpu6 { <<
623 #power-domain-cells = <<
624 power-domains = <&CLUS <<
625 domain-idle-states = < <<
626 }; <<
627 <<
628 CPU_PD7: cpu7 { <<
629 #power-domain-cells = <<
630 power-domains = <&CLUS <<
631 domain-idle-states = < <<
632 }; <<
633 <<
634 CLUSTER_PD: cpu-cluster0 { <<
635 #power-domain-cells = <<
636 domain-idle-states = < <<
637 <<
638 <<
639 }; 556 };
640 }; 557 };
641 558
642 reserved_memory: reserved-memory { !! 559 tcsr_mutex: hwlock {
643 #address-cells = <2>; !! 560 compatible = "qcom,tcsr-mutex";
644 #size-cells = <2>; !! 561 syscon = <&tcsr_mutex_regs 0 0x1000>;
645 ranges; !! 562 #hwlock-cells = <1>;
646 <<
647 hyp_mem: memory@80000000 { <<
648 reg = <0x0 0x80000000 <<
649 no-map; <<
650 }; <<
651 <<
652 xbl_mem: memory@80600000 { <<
653 reg = <0x0 0x80600000 <<
654 no-map; <<
655 }; <<
656 <<
657 aop_mem: memory@80800000 { <<
658 reg = <0x0 0x80800000 <<
659 no-map; <<
660 }; <<
661 <<
662 aop_cmd_db_mem: memory@8082000 <<
663 reg = <0x0 0x80820000 <<
664 compatible = "qcom,cmd <<
665 no-map; <<
666 }; <<
667 <<
668 sec_apps_mem: memory@808ff000 <<
669 reg = <0x0 0x808ff000 <<
670 no-map; <<
671 }; <<
672 <<
673 smem_mem: memory@80900000 { <<
674 reg = <0x0 0x80900000 <<
675 no-map; <<
676 }; <<
677 <<
678 tz_mem: memory@80b00000 { <<
679 reg = <0x0 0x80b00000 <<
680 no-map; <<
681 }; <<
682 <<
683 ipa_fw_mem: memory@8b700000 { <<
684 reg = <0 0x8b700000 0 <<
685 no-map; <<
686 }; <<
687 <<
688 rmtfs_mem: memory@94600000 { <<
689 compatible = "qcom,rmt <<
690 reg = <0x0 0x94600000 <<
691 no-map; <<
692 <<
693 qcom,client-id = <1>; <<
694 qcom,vmid = <QCOM_SCM_ <<
695 }; <<
696 }; 563 };
697 564
698 smem { 565 smem {
699 compatible = "qcom,smem"; 566 compatible = "qcom,smem";
700 memory-region = <&smem_mem>; 567 memory-region = <&smem_mem>;
701 hwlocks = <&tcsr_mutex 3>; 568 hwlocks = <&tcsr_mutex 3>;
702 }; 569 };
703 570
704 smp2p-cdsp { 571 smp2p-cdsp {
705 compatible = "qcom,smp2p"; 572 compatible = "qcom,smp2p";
706 qcom,smem = <94>, <432>; 573 qcom,smem = <94>, <432>;
707 574
708 interrupts = <GIC_SPI 576 IRQ_ 575 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
709 576
710 mboxes = <&apss_shared 6>; 577 mboxes = <&apss_shared 6>;
711 578
712 qcom,local-pid = <0>; 579 qcom,local-pid = <0>;
713 qcom,remote-pid = <5>; 580 qcom,remote-pid = <5>;
714 581
715 cdsp_smp2p_out: master-kernel 582 cdsp_smp2p_out: master-kernel {
716 qcom,entry-name = "mas 583 qcom,entry-name = "master-kernel";
717 #qcom,smem-state-cells 584 #qcom,smem-state-cells = <1>;
718 }; 585 };
719 586
720 cdsp_smp2p_in: slave-kernel { 587 cdsp_smp2p_in: slave-kernel {
721 qcom,entry-name = "sla 588 qcom,entry-name = "slave-kernel";
722 589
723 interrupt-controller; 590 interrupt-controller;
724 #interrupt-cells = <2> 591 #interrupt-cells = <2>;
725 }; 592 };
726 }; 593 };
727 594
728 smp2p-lpass { 595 smp2p-lpass {
729 compatible = "qcom,smp2p"; 596 compatible = "qcom,smp2p";
730 qcom,smem = <443>, <429>; 597 qcom,smem = <443>, <429>;
731 598
732 interrupts = <GIC_SPI 158 IRQ_ 599 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
733 600
734 mboxes = <&apss_shared 10>; 601 mboxes = <&apss_shared 10>;
735 602
736 qcom,local-pid = <0>; 603 qcom,local-pid = <0>;
737 qcom,remote-pid = <2>; 604 qcom,remote-pid = <2>;
738 605
739 adsp_smp2p_out: master-kernel 606 adsp_smp2p_out: master-kernel {
740 qcom,entry-name = "mas 607 qcom,entry-name = "master-kernel";
741 #qcom,smem-state-cells 608 #qcom,smem-state-cells = <1>;
742 }; 609 };
743 610
744 adsp_smp2p_in: slave-kernel { 611 adsp_smp2p_in: slave-kernel {
745 qcom,entry-name = "sla 612 qcom,entry-name = "slave-kernel";
746 613
747 interrupt-controller; 614 interrupt-controller;
748 #interrupt-cells = <2> 615 #interrupt-cells = <2>;
749 }; 616 };
750 }; 617 };
751 618
752 smp2p-mpss { 619 smp2p-mpss {
753 compatible = "qcom,smp2p"; 620 compatible = "qcom,smp2p";
754 qcom,smem = <435>, <428>; 621 qcom,smem = <435>, <428>;
755 interrupts = <GIC_SPI 451 IRQ_ 622 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
756 mboxes = <&apss_shared 14>; 623 mboxes = <&apss_shared 14>;
757 qcom,local-pid = <0>; 624 qcom,local-pid = <0>;
758 qcom,remote-pid = <1>; 625 qcom,remote-pid = <1>;
759 626
760 modem_smp2p_out: master-kernel 627 modem_smp2p_out: master-kernel {
761 qcom,entry-name = "mas 628 qcom,entry-name = "master-kernel";
762 #qcom,smem-state-cells 629 #qcom,smem-state-cells = <1>;
763 }; 630 };
764 631
765 modem_smp2p_in: slave-kernel { 632 modem_smp2p_in: slave-kernel {
766 qcom,entry-name = "sla 633 qcom,entry-name = "slave-kernel";
767 interrupt-controller; 634 interrupt-controller;
768 #interrupt-cells = <2> 635 #interrupt-cells = <2>;
769 }; 636 };
770 637
771 ipa_smp2p_out: ipa-ap-to-modem 638 ipa_smp2p_out: ipa-ap-to-modem {
772 qcom,entry-name = "ipa 639 qcom,entry-name = "ipa";
773 #qcom,smem-state-cells 640 #qcom,smem-state-cells = <1>;
774 }; 641 };
775 642
776 ipa_smp2p_in: ipa-modem-to-ap 643 ipa_smp2p_in: ipa-modem-to-ap {
777 qcom,entry-name = "ipa 644 qcom,entry-name = "ipa";
778 interrupt-controller; 645 interrupt-controller;
779 #interrupt-cells = <2> 646 #interrupt-cells = <2>;
780 }; 647 };
781 }; 648 };
782 649
>> 650 psci {
>> 651 compatible = "arm,psci-1.0";
>> 652 method = "smc";
>> 653 };
>> 654
783 soc: soc@0 { 655 soc: soc@0 {
784 #address-cells = <2>; 656 #address-cells = <2>;
785 #size-cells = <2>; 657 #size-cells = <2>;
786 ranges = <0 0 0 0 0x10 0>; 658 ranges = <0 0 0 0 0x10 0>;
787 dma-ranges = <0 0 0 0 0x10 0>; 659 dma-ranges = <0 0 0 0 0x10 0>;
788 compatible = "simple-bus"; 660 compatible = "simple-bus";
789 661
790 gcc: clock-controller@100000 { 662 gcc: clock-controller@100000 {
791 compatible = "qcom,gcc 663 compatible = "qcom,gcc-sc7180";
792 reg = <0 0x00100000 0 664 reg = <0 0x00100000 0 0x1f0000>;
793 clocks = <&rpmhcc RPMH 665 clocks = <&rpmhcc RPMH_CXO_CLK>,
794 <&rpmhcc RPMH 666 <&rpmhcc RPMH_CXO_CLK_A>,
795 <&sleep_clk>; 667 <&sleep_clk>;
796 clock-names = "bi_tcxo 668 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
797 #clock-cells = <1>; 669 #clock-cells = <1>;
798 #reset-cells = <1>; 670 #reset-cells = <1>;
799 #power-domain-cells = 671 #power-domain-cells = <1>;
800 power-domains = <&rpmh <<
801 }; 672 };
802 673
803 qfprom: efuse@784000 { 674 qfprom: efuse@784000 {
804 compatible = "qcom,sc7 675 compatible = "qcom,sc7180-qfprom", "qcom,qfprom";
805 reg = <0 0x00784000 0 676 reg = <0 0x00784000 0 0x7a0>,
806 <0 0x00780000 0 677 <0 0x00780000 0 0x7a0>,
807 <0 0x00782000 0 678 <0 0x00782000 0 0x100>,
808 <0 0x00786000 0 679 <0 0x00786000 0 0x1fff>;
809 680
810 clocks = <&gcc GCC_SEC 681 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>;
811 clock-names = "core"; 682 clock-names = "core";
812 #address-cells = <1>; 683 #address-cells = <1>;
813 #size-cells = <1>; 684 #size-cells = <1>;
814 685
815 qusb2p_hstx_trim: hstx 686 qusb2p_hstx_trim: hstx-trim-primary@25b {
816 reg = <0x25b 0 687 reg = <0x25b 0x1>;
817 bits = <1 3>; 688 bits = <1 3>;
818 }; 689 };
819 690
820 gpu_speed_bin: gpu-spe !! 691 gpu_speed_bin: gpu_speed_bin@1d2 {
821 reg = <0x1d2 0 692 reg = <0x1d2 0x2>;
822 bits = <5 8>; 693 bits = <5 8>;
823 }; 694 };
824 }; 695 };
825 696
826 sdhc_1: mmc@7c4000 { !! 697 sdhc_1: sdhci@7c4000 {
827 compatible = "qcom,sc7 698 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
828 reg = <0 0x007c4000 0 !! 699 reg = <0 0x7c4000 0 0x1000>,
829 <0 0x007c5000 !! 700 <0 0x07c5000 0 0x1000>;
830 reg-names = "hc", "cqh 701 reg-names = "hc", "cqhci";
831 702
832 iommus = <&apps_smmu 0 703 iommus = <&apps_smmu 0x60 0x0>;
833 interrupts = <GIC_SPI 704 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
834 <GIC_S 705 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
835 interrupt-names = "hc_ 706 interrupt-names = "hc_irq", "pwr_irq";
836 707
837 clocks = <&gcc GCC_SDC !! 708 clocks = <&gcc GCC_SDCC1_APPS_CLK>,
838 <&gcc GCC_SDC !! 709 <&gcc GCC_SDCC1_AHB_CLK>,
839 <&rpmhcc RPMH 710 <&rpmhcc RPMH_CXO_CLK>;
840 clock-names = "iface", !! 711 clock-names = "core", "iface", "xo";
841 interconnects = <&aggr 712 interconnects = <&aggre1_noc MASTER_EMMC 0 &mc_virt SLAVE_EBI1 0>,
842 <&gem_ 713 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_EMMC_CFG 0>;
843 interconnect-names = " 714 interconnect-names = "sdhc-ddr","cpu-sdhc";
844 power-domains = <&rpmh 715 power-domains = <&rpmhpd SC7180_CX>;
845 operating-points-v2 = 716 operating-points-v2 = <&sdhc1_opp_table>;
846 717
847 bus-width = <8>; 718 bus-width = <8>;
848 non-removable; 719 non-removable;
849 supports-cqe; 720 supports-cqe;
850 721
851 mmc-ddr-1_8v; 722 mmc-ddr-1_8v;
852 mmc-hs200-1_8v; 723 mmc-hs200-1_8v;
853 mmc-hs400-1_8v; 724 mmc-hs400-1_8v;
854 mmc-hs400-enhanced-str 725 mmc-hs400-enhanced-strobe;
855 726
856 status = "disabled"; 727 status = "disabled";
857 728
858 sdhc1_opp_table: opp-t !! 729 sdhc1_opp_table: sdhc1-opp-table {
859 compatible = " 730 compatible = "operating-points-v2";
860 731
861 opp-100000000 732 opp-100000000 {
862 opp-hz 733 opp-hz = /bits/ 64 <100000000>;
863 requir 734 required-opps = <&rpmhpd_opp_low_svs>;
864 opp-pe 735 opp-peak-kBps = <1800000 600000>;
865 opp-av 736 opp-avg-kBps = <100000 0>;
866 }; 737 };
867 738
868 opp-384000000 739 opp-384000000 {
869 opp-hz 740 opp-hz = /bits/ 64 <384000000>;
870 requir 741 required-opps = <&rpmhpd_opp_nom>;
871 opp-pe 742 opp-peak-kBps = <5400000 1600000>;
872 opp-av 743 opp-avg-kBps = <390000 0>;
873 }; 744 };
874 }; 745 };
875 }; 746 };
876 747
>> 748 qup_opp_table: qup-opp-table {
>> 749 compatible = "operating-points-v2";
>> 750
>> 751 opp-75000000 {
>> 752 opp-hz = /bits/ 64 <75000000>;
>> 753 required-opps = <&rpmhpd_opp_low_svs>;
>> 754 };
>> 755
>> 756 opp-100000000 {
>> 757 opp-hz = /bits/ 64 <100000000>;
>> 758 required-opps = <&rpmhpd_opp_svs>;
>> 759 };
>> 760
>> 761 opp-128000000 {
>> 762 opp-hz = /bits/ 64 <128000000>;
>> 763 required-opps = <&rpmhpd_opp_nom>;
>> 764 };
>> 765 };
>> 766
877 qupv3_id_0: geniqup@8c0000 { 767 qupv3_id_0: geniqup@8c0000 {
878 compatible = "qcom,gen 768 compatible = "qcom,geni-se-qup";
879 reg = <0 0x008c0000 0 769 reg = <0 0x008c0000 0 0x6000>;
880 clock-names = "m-ahb", 770 clock-names = "m-ahb", "s-ahb";
881 clocks = <&gcc GCC_QUP 771 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
882 <&gcc GCC_QUP 772 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
883 #address-cells = <2>; 773 #address-cells = <2>;
884 #size-cells = <2>; 774 #size-cells = <2>;
885 ranges; 775 ranges;
886 iommus = <&apps_smmu 0 776 iommus = <&apps_smmu 0x43 0x0>;
887 status = "disabled"; 777 status = "disabled";
888 778
889 i2c0: i2c@880000 { 779 i2c0: i2c@880000 {
890 compatible = " 780 compatible = "qcom,geni-i2c";
891 reg = <0 0x008 781 reg = <0 0x00880000 0 0x4000>;
892 clock-names = 782 clock-names = "se";
893 clocks = <&gcc 783 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
894 pinctrl-names 784 pinctrl-names = "default";
895 pinctrl-0 = <& 785 pinctrl-0 = <&qup_i2c0_default>;
896 interrupts = < 786 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
897 #address-cells 787 #address-cells = <1>;
898 #size-cells = 788 #size-cells = <0>;
899 interconnects 789 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
900 790 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
901 791 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
902 interconnect-n 792 interconnect-names = "qup-core", "qup-config",
903 793 "qup-memory";
904 power-domains 794 power-domains = <&rpmhpd SC7180_CX>;
905 required-opps 795 required-opps = <&rpmhpd_opp_low_svs>;
906 status = "disa 796 status = "disabled";
907 }; 797 };
908 798
909 spi0: spi@880000 { 799 spi0: spi@880000 {
910 compatible = " 800 compatible = "qcom,geni-spi";
911 reg = <0 0x008 801 reg = <0 0x00880000 0 0x4000>;
912 clock-names = 802 clock-names = "se";
913 clocks = <&gcc 803 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
914 pinctrl-names 804 pinctrl-names = "default";
915 pinctrl-0 = <& !! 805 pinctrl-0 = <&qup_spi0_default>;
916 interrupts = < 806 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
917 #address-cells 807 #address-cells = <1>;
918 #size-cells = 808 #size-cells = <0>;
919 power-domains 809 power-domains = <&rpmhpd SC7180_CX>;
920 operating-poin 810 operating-points-v2 = <&qup_opp_table>;
921 interconnects 811 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
922 812 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
923 interconnect-n 813 interconnect-names = "qup-core", "qup-config";
924 status = "disa 814 status = "disabled";
925 }; 815 };
926 816
927 uart0: serial@880000 { 817 uart0: serial@880000 {
928 compatible = " 818 compatible = "qcom,geni-uart";
929 reg = <0 0x008 819 reg = <0 0x00880000 0 0x4000>;
930 clock-names = 820 clock-names = "se";
931 clocks = <&gcc 821 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
932 pinctrl-names 822 pinctrl-names = "default";
933 pinctrl-0 = <& 823 pinctrl-0 = <&qup_uart0_default>;
934 interrupts = < 824 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
935 power-domains 825 power-domains = <&rpmhpd SC7180_CX>;
936 operating-poin 826 operating-points-v2 = <&qup_opp_table>;
937 interconnects 827 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
938 828 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
939 interconnect-n 829 interconnect-names = "qup-core", "qup-config";
940 status = "disa 830 status = "disabled";
941 }; 831 };
942 832
943 i2c1: i2c@884000 { 833 i2c1: i2c@884000 {
944 compatible = " 834 compatible = "qcom,geni-i2c";
945 reg = <0 0x008 835 reg = <0 0x00884000 0 0x4000>;
946 clock-names = 836 clock-names = "se";
947 clocks = <&gcc 837 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
948 pinctrl-names 838 pinctrl-names = "default";
949 pinctrl-0 = <& 839 pinctrl-0 = <&qup_i2c1_default>;
950 interrupts = < 840 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
951 #address-cells 841 #address-cells = <1>;
952 #size-cells = 842 #size-cells = <0>;
953 interconnects 843 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
954 844 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
955 845 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
956 interconnect-n 846 interconnect-names = "qup-core", "qup-config",
957 847 "qup-memory";
958 power-domains 848 power-domains = <&rpmhpd SC7180_CX>;
959 required-opps 849 required-opps = <&rpmhpd_opp_low_svs>;
960 status = "disa 850 status = "disabled";
961 }; 851 };
962 852
963 spi1: spi@884000 { 853 spi1: spi@884000 {
964 compatible = " 854 compatible = "qcom,geni-spi";
965 reg = <0 0x008 855 reg = <0 0x00884000 0 0x4000>;
966 clock-names = 856 clock-names = "se";
967 clocks = <&gcc 857 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
968 pinctrl-names 858 pinctrl-names = "default";
969 pinctrl-0 = <& !! 859 pinctrl-0 = <&qup_spi1_default>;
970 interrupts = < 860 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
971 #address-cells 861 #address-cells = <1>;
972 #size-cells = 862 #size-cells = <0>;
973 power-domains 863 power-domains = <&rpmhpd SC7180_CX>;
974 operating-poin 864 operating-points-v2 = <&qup_opp_table>;
975 interconnects 865 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
976 866 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
977 interconnect-n 867 interconnect-names = "qup-core", "qup-config";
978 status = "disa 868 status = "disabled";
979 }; 869 };
980 870
981 uart1: serial@884000 { 871 uart1: serial@884000 {
982 compatible = " 872 compatible = "qcom,geni-uart";
983 reg = <0 0x008 873 reg = <0 0x00884000 0 0x4000>;
984 clock-names = 874 clock-names = "se";
985 clocks = <&gcc 875 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
986 pinctrl-names 876 pinctrl-names = "default";
987 pinctrl-0 = <& 877 pinctrl-0 = <&qup_uart1_default>;
988 interrupts = < 878 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
989 power-domains 879 power-domains = <&rpmhpd SC7180_CX>;
990 operating-poin 880 operating-points-v2 = <&qup_opp_table>;
991 interconnects 881 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
992 882 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
993 interconnect-n 883 interconnect-names = "qup-core", "qup-config";
994 status = "disa 884 status = "disabled";
995 }; 885 };
996 886
997 i2c2: i2c@888000 { 887 i2c2: i2c@888000 {
998 compatible = " 888 compatible = "qcom,geni-i2c";
999 reg = <0 0x008 889 reg = <0 0x00888000 0 0x4000>;
1000 clock-names = 890 clock-names = "se";
1001 clocks = <&gc 891 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1002 pinctrl-names 892 pinctrl-names = "default";
1003 pinctrl-0 = < 893 pinctrl-0 = <&qup_i2c2_default>;
1004 interrupts = 894 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1005 #address-cell 895 #address-cells = <1>;
1006 #size-cells = 896 #size-cells = <0>;
1007 interconnects 897 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1008 898 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1009 899 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1010 interconnect- 900 interconnect-names = "qup-core", "qup-config",
1011 901 "qup-memory";
1012 power-domains 902 power-domains = <&rpmhpd SC7180_CX>;
1013 required-opps 903 required-opps = <&rpmhpd_opp_low_svs>;
1014 status = "dis 904 status = "disabled";
1015 }; 905 };
1016 906
1017 uart2: serial@888000 907 uart2: serial@888000 {
1018 compatible = 908 compatible = "qcom,geni-uart";
1019 reg = <0 0x00 909 reg = <0 0x00888000 0 0x4000>;
1020 clock-names = 910 clock-names = "se";
1021 clocks = <&gc 911 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1022 pinctrl-names 912 pinctrl-names = "default";
1023 pinctrl-0 = < 913 pinctrl-0 = <&qup_uart2_default>;
1024 interrupts = 914 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1025 power-domains 915 power-domains = <&rpmhpd SC7180_CX>;
1026 operating-poi 916 operating-points-v2 = <&qup_opp_table>;
1027 interconnects 917 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1028 918 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1029 interconnect- 919 interconnect-names = "qup-core", "qup-config";
1030 status = "dis 920 status = "disabled";
1031 }; 921 };
1032 922
1033 i2c3: i2c@88c000 { 923 i2c3: i2c@88c000 {
1034 compatible = 924 compatible = "qcom,geni-i2c";
1035 reg = <0 0x00 925 reg = <0 0x0088c000 0 0x4000>;
1036 clock-names = 926 clock-names = "se";
1037 clocks = <&gc 927 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1038 pinctrl-names 928 pinctrl-names = "default";
1039 pinctrl-0 = < 929 pinctrl-0 = <&qup_i2c3_default>;
1040 interrupts = 930 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1041 #address-cell 931 #address-cells = <1>;
1042 #size-cells = 932 #size-cells = <0>;
1043 interconnects 933 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1044 934 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1045 935 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1046 interconnect- 936 interconnect-names = "qup-core", "qup-config",
1047 937 "qup-memory";
1048 power-domains 938 power-domains = <&rpmhpd SC7180_CX>;
1049 required-opps 939 required-opps = <&rpmhpd_opp_low_svs>;
1050 status = "dis 940 status = "disabled";
1051 }; 941 };
1052 942
1053 spi3: spi@88c000 { 943 spi3: spi@88c000 {
1054 compatible = 944 compatible = "qcom,geni-spi";
1055 reg = <0 0x00 945 reg = <0 0x0088c000 0 0x4000>;
1056 clock-names = 946 clock-names = "se";
1057 clocks = <&gc 947 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1058 pinctrl-names 948 pinctrl-names = "default";
1059 pinctrl-0 = < !! 949 pinctrl-0 = <&qup_spi3_default>;
1060 interrupts = 950 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1061 #address-cell 951 #address-cells = <1>;
1062 #size-cells = 952 #size-cells = <0>;
1063 power-domains 953 power-domains = <&rpmhpd SC7180_CX>;
1064 operating-poi 954 operating-points-v2 = <&qup_opp_table>;
1065 interconnects 955 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1066 956 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1067 interconnect- 957 interconnect-names = "qup-core", "qup-config";
1068 status = "dis 958 status = "disabled";
1069 }; 959 };
1070 960
1071 uart3: serial@88c000 961 uart3: serial@88c000 {
1072 compatible = 962 compatible = "qcom,geni-uart";
1073 reg = <0 0x00 963 reg = <0 0x0088c000 0 0x4000>;
1074 clock-names = 964 clock-names = "se";
1075 clocks = <&gc 965 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1076 pinctrl-names 966 pinctrl-names = "default";
1077 pinctrl-0 = < 967 pinctrl-0 = <&qup_uart3_default>;
1078 interrupts = 968 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1079 power-domains 969 power-domains = <&rpmhpd SC7180_CX>;
1080 operating-poi 970 operating-points-v2 = <&qup_opp_table>;
1081 interconnects 971 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1082 972 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1083 interconnect- 973 interconnect-names = "qup-core", "qup-config";
1084 status = "dis 974 status = "disabled";
1085 }; 975 };
1086 976
1087 i2c4: i2c@890000 { 977 i2c4: i2c@890000 {
1088 compatible = 978 compatible = "qcom,geni-i2c";
1089 reg = <0 0x00 979 reg = <0 0x00890000 0 0x4000>;
1090 clock-names = 980 clock-names = "se";
1091 clocks = <&gc 981 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1092 pinctrl-names 982 pinctrl-names = "default";
1093 pinctrl-0 = < 983 pinctrl-0 = <&qup_i2c4_default>;
1094 interrupts = 984 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1095 #address-cell 985 #address-cells = <1>;
1096 #size-cells = 986 #size-cells = <0>;
1097 interconnects 987 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1098 988 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1099 989 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1100 interconnect- 990 interconnect-names = "qup-core", "qup-config",
1101 991 "qup-memory";
1102 power-domains 992 power-domains = <&rpmhpd SC7180_CX>;
1103 required-opps 993 required-opps = <&rpmhpd_opp_low_svs>;
1104 status = "dis 994 status = "disabled";
1105 }; 995 };
1106 996
1107 uart4: serial@890000 997 uart4: serial@890000 {
1108 compatible = 998 compatible = "qcom,geni-uart";
1109 reg = <0 0x00 999 reg = <0 0x00890000 0 0x4000>;
1110 clock-names = 1000 clock-names = "se";
1111 clocks = <&gc 1001 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1112 pinctrl-names 1002 pinctrl-names = "default";
1113 pinctrl-0 = < 1003 pinctrl-0 = <&qup_uart4_default>;
1114 interrupts = 1004 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1115 power-domains 1005 power-domains = <&rpmhpd SC7180_CX>;
1116 operating-poi 1006 operating-points-v2 = <&qup_opp_table>;
1117 interconnects 1007 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1118 1008 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1119 interconnect- 1009 interconnect-names = "qup-core", "qup-config";
1120 status = "dis 1010 status = "disabled";
1121 }; 1011 };
1122 1012
1123 i2c5: i2c@894000 { 1013 i2c5: i2c@894000 {
1124 compatible = 1014 compatible = "qcom,geni-i2c";
1125 reg = <0 0x00 1015 reg = <0 0x00894000 0 0x4000>;
1126 clock-names = 1016 clock-names = "se";
1127 clocks = <&gc 1017 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1128 pinctrl-names 1018 pinctrl-names = "default";
1129 pinctrl-0 = < 1019 pinctrl-0 = <&qup_i2c5_default>;
1130 interrupts = 1020 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1131 #address-cell 1021 #address-cells = <1>;
1132 #size-cells = 1022 #size-cells = <0>;
1133 interconnects 1023 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1134 1024 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1135 1025 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1136 interconnect- 1026 interconnect-names = "qup-core", "qup-config",
1137 1027 "qup-memory";
1138 power-domains 1028 power-domains = <&rpmhpd SC7180_CX>;
1139 required-opps 1029 required-opps = <&rpmhpd_opp_low_svs>;
1140 status = "dis 1030 status = "disabled";
1141 }; 1031 };
1142 1032
1143 spi5: spi@894000 { 1033 spi5: spi@894000 {
1144 compatible = 1034 compatible = "qcom,geni-spi";
1145 reg = <0 0x00 1035 reg = <0 0x00894000 0 0x4000>;
1146 clock-names = 1036 clock-names = "se";
1147 clocks = <&gc 1037 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1148 pinctrl-names 1038 pinctrl-names = "default";
1149 pinctrl-0 = < !! 1039 pinctrl-0 = <&qup_spi5_default>;
1150 interrupts = 1040 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1151 #address-cell 1041 #address-cells = <1>;
1152 #size-cells = 1042 #size-cells = <0>;
1153 power-domains 1043 power-domains = <&rpmhpd SC7180_CX>;
1154 operating-poi 1044 operating-points-v2 = <&qup_opp_table>;
1155 interconnects 1045 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1156 1046 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1157 interconnect- 1047 interconnect-names = "qup-core", "qup-config";
1158 status = "dis 1048 status = "disabled";
1159 }; 1049 };
1160 1050
1161 uart5: serial@894000 1051 uart5: serial@894000 {
1162 compatible = 1052 compatible = "qcom,geni-uart";
1163 reg = <0 0x00 1053 reg = <0 0x00894000 0 0x4000>;
1164 clock-names = 1054 clock-names = "se";
1165 clocks = <&gc 1055 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1166 pinctrl-names 1056 pinctrl-names = "default";
1167 pinctrl-0 = < 1057 pinctrl-0 = <&qup_uart5_default>;
1168 interrupts = 1058 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1169 power-domains 1059 power-domains = <&rpmhpd SC7180_CX>;
1170 operating-poi 1060 operating-points-v2 = <&qup_opp_table>;
1171 interconnects 1061 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1172 1062 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1173 interconnect- 1063 interconnect-names = "qup-core", "qup-config";
1174 status = "dis 1064 status = "disabled";
1175 }; 1065 };
1176 }; 1066 };
1177 1067
1178 qupv3_id_1: geniqup@ac0000 { 1068 qupv3_id_1: geniqup@ac0000 {
1179 compatible = "qcom,ge 1069 compatible = "qcom,geni-se-qup";
1180 reg = <0 0x00ac0000 0 1070 reg = <0 0x00ac0000 0 0x6000>;
1181 clock-names = "m-ahb" 1071 clock-names = "m-ahb", "s-ahb";
1182 clocks = <&gcc GCC_QU 1072 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1183 <&gcc GCC_QU 1073 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1184 #address-cells = <2>; 1074 #address-cells = <2>;
1185 #size-cells = <2>; 1075 #size-cells = <2>;
1186 ranges; 1076 ranges;
1187 iommus = <&apps_smmu 1077 iommus = <&apps_smmu 0x4c3 0x0>;
1188 status = "disabled"; 1078 status = "disabled";
1189 1079
1190 i2c6: i2c@a80000 { 1080 i2c6: i2c@a80000 {
1191 compatible = 1081 compatible = "qcom,geni-i2c";
1192 reg = <0 0x00 1082 reg = <0 0x00a80000 0 0x4000>;
1193 clock-names = 1083 clock-names = "se";
1194 clocks = <&gc 1084 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1195 pinctrl-names 1085 pinctrl-names = "default";
1196 pinctrl-0 = < 1086 pinctrl-0 = <&qup_i2c6_default>;
1197 interrupts = 1087 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1198 #address-cell 1088 #address-cells = <1>;
1199 #size-cells = 1089 #size-cells = <0>;
1200 interconnects 1090 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1201 1091 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1202 1092 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1203 interconnect- 1093 interconnect-names = "qup-core", "qup-config",
1204 1094 "qup-memory";
1205 power-domains 1095 power-domains = <&rpmhpd SC7180_CX>;
1206 required-opps 1096 required-opps = <&rpmhpd_opp_low_svs>;
1207 status = "dis 1097 status = "disabled";
1208 }; 1098 };
1209 1099
1210 spi6: spi@a80000 { 1100 spi6: spi@a80000 {
1211 compatible = 1101 compatible = "qcom,geni-spi";
1212 reg = <0 0x00 1102 reg = <0 0x00a80000 0 0x4000>;
1213 clock-names = 1103 clock-names = "se";
1214 clocks = <&gc 1104 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1215 pinctrl-names 1105 pinctrl-names = "default";
1216 pinctrl-0 = < !! 1106 pinctrl-0 = <&qup_spi6_default>;
1217 interrupts = 1107 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1218 #address-cell 1108 #address-cells = <1>;
1219 #size-cells = 1109 #size-cells = <0>;
1220 power-domains 1110 power-domains = <&rpmhpd SC7180_CX>;
1221 operating-poi 1111 operating-points-v2 = <&qup_opp_table>;
1222 interconnects 1112 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1223 1113 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1224 interconnect- 1114 interconnect-names = "qup-core", "qup-config";
1225 status = "dis 1115 status = "disabled";
1226 }; 1116 };
1227 1117
1228 uart6: serial@a80000 1118 uart6: serial@a80000 {
1229 compatible = 1119 compatible = "qcom,geni-uart";
1230 reg = <0 0x00 1120 reg = <0 0x00a80000 0 0x4000>;
1231 clock-names = 1121 clock-names = "se";
1232 clocks = <&gc 1122 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1233 pinctrl-names 1123 pinctrl-names = "default";
1234 pinctrl-0 = < 1124 pinctrl-0 = <&qup_uart6_default>;
1235 interrupts = 1125 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1236 power-domains 1126 power-domains = <&rpmhpd SC7180_CX>;
1237 operating-poi 1127 operating-points-v2 = <&qup_opp_table>;
1238 interconnects 1128 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1239 1129 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1240 interconnect- 1130 interconnect-names = "qup-core", "qup-config";
1241 status = "dis 1131 status = "disabled";
1242 }; 1132 };
1243 1133
1244 i2c7: i2c@a84000 { 1134 i2c7: i2c@a84000 {
1245 compatible = 1135 compatible = "qcom,geni-i2c";
1246 reg = <0 0x00 1136 reg = <0 0x00a84000 0 0x4000>;
1247 clock-names = 1137 clock-names = "se";
1248 clocks = <&gc 1138 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1249 pinctrl-names 1139 pinctrl-names = "default";
1250 pinctrl-0 = < 1140 pinctrl-0 = <&qup_i2c7_default>;
1251 interrupts = 1141 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1252 #address-cell 1142 #address-cells = <1>;
1253 #size-cells = 1143 #size-cells = <0>;
1254 interconnects 1144 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1255 1145 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1256 1146 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1257 interconnect- 1147 interconnect-names = "qup-core", "qup-config",
1258 1148 "qup-memory";
1259 power-domains 1149 power-domains = <&rpmhpd SC7180_CX>;
1260 required-opps 1150 required-opps = <&rpmhpd_opp_low_svs>;
1261 status = "dis 1151 status = "disabled";
1262 }; 1152 };
1263 1153
1264 uart7: serial@a84000 1154 uart7: serial@a84000 {
1265 compatible = 1155 compatible = "qcom,geni-uart";
1266 reg = <0 0x00 1156 reg = <0 0x00a84000 0 0x4000>;
1267 clock-names = 1157 clock-names = "se";
1268 clocks = <&gc 1158 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1269 pinctrl-names 1159 pinctrl-names = "default";
1270 pinctrl-0 = < 1160 pinctrl-0 = <&qup_uart7_default>;
1271 interrupts = 1161 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1272 power-domains 1162 power-domains = <&rpmhpd SC7180_CX>;
1273 operating-poi 1163 operating-points-v2 = <&qup_opp_table>;
1274 interconnects 1164 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1275 1165 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1276 interconnect- 1166 interconnect-names = "qup-core", "qup-config";
1277 status = "dis 1167 status = "disabled";
1278 }; 1168 };
1279 1169
1280 i2c8: i2c@a88000 { 1170 i2c8: i2c@a88000 {
1281 compatible = 1171 compatible = "qcom,geni-i2c";
1282 reg = <0 0x00 1172 reg = <0 0x00a88000 0 0x4000>;
1283 clock-names = 1173 clock-names = "se";
1284 clocks = <&gc 1174 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1285 pinctrl-names 1175 pinctrl-names = "default";
1286 pinctrl-0 = < 1176 pinctrl-0 = <&qup_i2c8_default>;
1287 interrupts = 1177 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1288 #address-cell 1178 #address-cells = <1>;
1289 #size-cells = 1179 #size-cells = <0>;
1290 interconnects 1180 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1291 1181 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1292 1182 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1293 interconnect- 1183 interconnect-names = "qup-core", "qup-config",
1294 1184 "qup-memory";
1295 power-domains 1185 power-domains = <&rpmhpd SC7180_CX>;
1296 required-opps 1186 required-opps = <&rpmhpd_opp_low_svs>;
1297 status = "dis 1187 status = "disabled";
1298 }; 1188 };
1299 1189
1300 spi8: spi@a88000 { 1190 spi8: spi@a88000 {
1301 compatible = 1191 compatible = "qcom,geni-spi";
1302 reg = <0 0x00 1192 reg = <0 0x00a88000 0 0x4000>;
1303 clock-names = 1193 clock-names = "se";
1304 clocks = <&gc 1194 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1305 pinctrl-names 1195 pinctrl-names = "default";
1306 pinctrl-0 = < !! 1196 pinctrl-0 = <&qup_spi8_default>;
1307 interrupts = 1197 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1308 #address-cell 1198 #address-cells = <1>;
1309 #size-cells = 1199 #size-cells = <0>;
1310 power-domains 1200 power-domains = <&rpmhpd SC7180_CX>;
1311 operating-poi 1201 operating-points-v2 = <&qup_opp_table>;
1312 interconnects 1202 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1313 1203 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1314 interconnect- 1204 interconnect-names = "qup-core", "qup-config";
1315 status = "dis 1205 status = "disabled";
1316 }; 1206 };
1317 1207
1318 uart8: serial@a88000 1208 uart8: serial@a88000 {
1319 compatible = 1209 compatible = "qcom,geni-debug-uart";
1320 reg = <0 0x00 1210 reg = <0 0x00a88000 0 0x4000>;
1321 clock-names = 1211 clock-names = "se";
1322 clocks = <&gc 1212 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1323 pinctrl-names 1213 pinctrl-names = "default";
1324 pinctrl-0 = < 1214 pinctrl-0 = <&qup_uart8_default>;
1325 interrupts = 1215 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1326 power-domains 1216 power-domains = <&rpmhpd SC7180_CX>;
1327 operating-poi 1217 operating-points-v2 = <&qup_opp_table>;
1328 interconnects 1218 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1329 1219 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1330 interconnect- 1220 interconnect-names = "qup-core", "qup-config";
1331 status = "dis 1221 status = "disabled";
1332 }; 1222 };
1333 1223
1334 i2c9: i2c@a8c000 { 1224 i2c9: i2c@a8c000 {
1335 compatible = 1225 compatible = "qcom,geni-i2c";
1336 reg = <0 0x00 1226 reg = <0 0x00a8c000 0 0x4000>;
1337 clock-names = 1227 clock-names = "se";
1338 clocks = <&gc 1228 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1339 pinctrl-names 1229 pinctrl-names = "default";
1340 pinctrl-0 = < 1230 pinctrl-0 = <&qup_i2c9_default>;
1341 interrupts = 1231 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1342 #address-cell 1232 #address-cells = <1>;
1343 #size-cells = 1233 #size-cells = <0>;
1344 interconnects 1234 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1345 1235 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1346 1236 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1347 interconnect- 1237 interconnect-names = "qup-core", "qup-config",
1348 1238 "qup-memory";
1349 power-domains 1239 power-domains = <&rpmhpd SC7180_CX>;
1350 required-opps 1240 required-opps = <&rpmhpd_opp_low_svs>;
1351 status = "dis 1241 status = "disabled";
1352 }; 1242 };
1353 1243
1354 uart9: serial@a8c000 1244 uart9: serial@a8c000 {
1355 compatible = 1245 compatible = "qcom,geni-uart";
1356 reg = <0 0x00 1246 reg = <0 0x00a8c000 0 0x4000>;
1357 clock-names = 1247 clock-names = "se";
1358 clocks = <&gc 1248 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1359 pinctrl-names 1249 pinctrl-names = "default";
1360 pinctrl-0 = < 1250 pinctrl-0 = <&qup_uart9_default>;
1361 interrupts = 1251 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1362 power-domains 1252 power-domains = <&rpmhpd SC7180_CX>;
1363 operating-poi 1253 operating-points-v2 = <&qup_opp_table>;
1364 interconnects 1254 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1365 1255 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1366 interconnect- 1256 interconnect-names = "qup-core", "qup-config";
1367 status = "dis 1257 status = "disabled";
1368 }; 1258 };
1369 1259
1370 i2c10: i2c@a90000 { 1260 i2c10: i2c@a90000 {
1371 compatible = 1261 compatible = "qcom,geni-i2c";
1372 reg = <0 0x00 1262 reg = <0 0x00a90000 0 0x4000>;
1373 clock-names = 1263 clock-names = "se";
1374 clocks = <&gc 1264 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1375 pinctrl-names 1265 pinctrl-names = "default";
1376 pinctrl-0 = < 1266 pinctrl-0 = <&qup_i2c10_default>;
1377 interrupts = 1267 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1378 #address-cell 1268 #address-cells = <1>;
1379 #size-cells = 1269 #size-cells = <0>;
1380 interconnects 1270 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1381 1271 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1382 1272 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1383 interconnect- 1273 interconnect-names = "qup-core", "qup-config",
1384 1274 "qup-memory";
1385 power-domains 1275 power-domains = <&rpmhpd SC7180_CX>;
1386 required-opps 1276 required-opps = <&rpmhpd_opp_low_svs>;
1387 status = "dis 1277 status = "disabled";
1388 }; 1278 };
1389 1279
1390 spi10: spi@a90000 { 1280 spi10: spi@a90000 {
1391 compatible = 1281 compatible = "qcom,geni-spi";
1392 reg = <0 0x00 1282 reg = <0 0x00a90000 0 0x4000>;
1393 clock-names = 1283 clock-names = "se";
1394 clocks = <&gc 1284 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1395 pinctrl-names 1285 pinctrl-names = "default";
1396 pinctrl-0 = < !! 1286 pinctrl-0 = <&qup_spi10_default>;
1397 interrupts = 1287 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1398 #address-cell 1288 #address-cells = <1>;
1399 #size-cells = 1289 #size-cells = <0>;
1400 power-domains 1290 power-domains = <&rpmhpd SC7180_CX>;
1401 operating-poi 1291 operating-points-v2 = <&qup_opp_table>;
1402 interconnects 1292 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1403 1293 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1404 interconnect- 1294 interconnect-names = "qup-core", "qup-config";
1405 status = "dis 1295 status = "disabled";
1406 }; 1296 };
1407 1297
1408 uart10: serial@a90000 1298 uart10: serial@a90000 {
1409 compatible = 1299 compatible = "qcom,geni-uart";
1410 reg = <0 0x00 1300 reg = <0 0x00a90000 0 0x4000>;
1411 clock-names = 1301 clock-names = "se";
1412 clocks = <&gc 1302 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1413 pinctrl-names 1303 pinctrl-names = "default";
1414 pinctrl-0 = < 1304 pinctrl-0 = <&qup_uart10_default>;
1415 interrupts = 1305 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1416 power-domains 1306 power-domains = <&rpmhpd SC7180_CX>;
1417 operating-poi 1307 operating-points-v2 = <&qup_opp_table>;
1418 interconnects 1308 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1419 1309 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1420 interconnect- 1310 interconnect-names = "qup-core", "qup-config";
1421 status = "dis 1311 status = "disabled";
1422 }; 1312 };
1423 1313
1424 i2c11: i2c@a94000 { 1314 i2c11: i2c@a94000 {
1425 compatible = 1315 compatible = "qcom,geni-i2c";
1426 reg = <0 0x00 1316 reg = <0 0x00a94000 0 0x4000>;
1427 clock-names = 1317 clock-names = "se";
1428 clocks = <&gc 1318 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1429 pinctrl-names 1319 pinctrl-names = "default";
1430 pinctrl-0 = < 1320 pinctrl-0 = <&qup_i2c11_default>;
1431 interrupts = 1321 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1432 #address-cell 1322 #address-cells = <1>;
1433 #size-cells = 1323 #size-cells = <0>;
1434 interconnects 1324 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1435 1325 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1436 1326 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1437 interconnect- 1327 interconnect-names = "qup-core", "qup-config",
1438 1328 "qup-memory";
1439 power-domains 1329 power-domains = <&rpmhpd SC7180_CX>;
1440 required-opps 1330 required-opps = <&rpmhpd_opp_low_svs>;
1441 status = "dis 1331 status = "disabled";
1442 }; 1332 };
1443 1333
1444 spi11: spi@a94000 { 1334 spi11: spi@a94000 {
1445 compatible = 1335 compatible = "qcom,geni-spi";
1446 reg = <0 0x00 1336 reg = <0 0x00a94000 0 0x4000>;
1447 clock-names = 1337 clock-names = "se";
1448 clocks = <&gc 1338 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1449 pinctrl-names 1339 pinctrl-names = "default";
1450 pinctrl-0 = < !! 1340 pinctrl-0 = <&qup_spi11_default>;
1451 interrupts = 1341 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1452 #address-cell 1342 #address-cells = <1>;
1453 #size-cells = 1343 #size-cells = <0>;
1454 power-domains 1344 power-domains = <&rpmhpd SC7180_CX>;
1455 operating-poi 1345 operating-points-v2 = <&qup_opp_table>;
1456 interconnects 1346 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1457 1347 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1458 interconnect- 1348 interconnect-names = "qup-core", "qup-config";
1459 status = "dis 1349 status = "disabled";
1460 }; 1350 };
1461 1351
1462 uart11: serial@a94000 1352 uart11: serial@a94000 {
1463 compatible = 1353 compatible = "qcom,geni-uart";
1464 reg = <0 0x00 1354 reg = <0 0x00a94000 0 0x4000>;
1465 clock-names = 1355 clock-names = "se";
1466 clocks = <&gc 1356 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1467 pinctrl-names 1357 pinctrl-names = "default";
1468 pinctrl-0 = < 1358 pinctrl-0 = <&qup_uart11_default>;
1469 interrupts = 1359 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1470 power-domains 1360 power-domains = <&rpmhpd SC7180_CX>;
1471 operating-poi 1361 operating-points-v2 = <&qup_opp_table>;
1472 interconnects 1362 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1473 1363 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1474 interconnect- 1364 interconnect-names = "qup-core", "qup-config";
1475 status = "dis 1365 status = "disabled";
1476 }; 1366 };
1477 }; 1367 };
1478 1368
1479 config_noc: interconnect@1500 1369 config_noc: interconnect@1500000 {
1480 compatible = "qcom,sc 1370 compatible = "qcom,sc7180-config-noc";
1481 reg = <0 0x01500000 0 1371 reg = <0 0x01500000 0 0x28000>;
1482 #interconnect-cells = 1372 #interconnect-cells = <2>;
1483 qcom,bcm-voters = <&a 1373 qcom,bcm-voters = <&apps_bcm_voter>;
1484 }; 1374 };
1485 1375
1486 system_noc: interconnect@1620 1376 system_noc: interconnect@1620000 {
1487 compatible = "qcom,sc 1377 compatible = "qcom,sc7180-system-noc";
1488 reg = <0 0x01620000 0 1378 reg = <0 0x01620000 0 0x17080>;
1489 #interconnect-cells = 1379 #interconnect-cells = <2>;
1490 qcom,bcm-voters = <&a 1380 qcom,bcm-voters = <&apps_bcm_voter>;
1491 }; 1381 };
1492 1382
1493 mc_virt: interconnect@1638000 1383 mc_virt: interconnect@1638000 {
1494 compatible = "qcom,sc 1384 compatible = "qcom,sc7180-mc-virt";
1495 reg = <0 0x01638000 0 1385 reg = <0 0x01638000 0 0x1000>;
1496 #interconnect-cells = 1386 #interconnect-cells = <2>;
1497 qcom,bcm-voters = <&a 1387 qcom,bcm-voters = <&apps_bcm_voter>;
1498 }; 1388 };
1499 1389
1500 qup_virt: interconnect@165000 1390 qup_virt: interconnect@1650000 {
1501 compatible = "qcom,sc 1391 compatible = "qcom,sc7180-qup-virt";
1502 reg = <0 0x01650000 0 1392 reg = <0 0x01650000 0 0x1000>;
1503 #interconnect-cells = 1393 #interconnect-cells = <2>;
1504 qcom,bcm-voters = <&a 1394 qcom,bcm-voters = <&apps_bcm_voter>;
1505 }; 1395 };
1506 1396
1507 aggre1_noc: interconnect@16e0 1397 aggre1_noc: interconnect@16e0000 {
1508 compatible = "qcom,sc 1398 compatible = "qcom,sc7180-aggre1-noc";
1509 reg = <0 0x016e0000 0 1399 reg = <0 0x016e0000 0 0x15080>;
1510 #interconnect-cells = 1400 #interconnect-cells = <2>;
1511 qcom,bcm-voters = <&a 1401 qcom,bcm-voters = <&apps_bcm_voter>;
1512 }; 1402 };
1513 1403
1514 aggre2_noc: interconnect@1705 1404 aggre2_noc: interconnect@1705000 {
1515 compatible = "qcom,sc 1405 compatible = "qcom,sc7180-aggre2-noc";
1516 reg = <0 0x01705000 0 1406 reg = <0 0x01705000 0 0x9000>;
1517 #interconnect-cells = 1407 #interconnect-cells = <2>;
1518 qcom,bcm-voters = <&a 1408 qcom,bcm-voters = <&apps_bcm_voter>;
1519 }; 1409 };
1520 1410
1521 compute_noc: interconnect@170 1411 compute_noc: interconnect@170e000 {
1522 compatible = "qcom,sc 1412 compatible = "qcom,sc7180-compute-noc";
1523 reg = <0 0x0170e000 0 1413 reg = <0 0x0170e000 0 0x6000>;
1524 #interconnect-cells = 1414 #interconnect-cells = <2>;
1525 qcom,bcm-voters = <&a 1415 qcom,bcm-voters = <&apps_bcm_voter>;
1526 }; 1416 };
1527 1417
1528 mmss_noc: interconnect@174000 1418 mmss_noc: interconnect@1740000 {
1529 compatible = "qcom,sc 1419 compatible = "qcom,sc7180-mmss-noc";
1530 reg = <0 0x01740000 0 1420 reg = <0 0x01740000 0 0x1c100>;
1531 #interconnect-cells = 1421 #interconnect-cells = <2>;
1532 qcom,bcm-voters = <&a 1422 qcom,bcm-voters = <&apps_bcm_voter>;
1533 }; 1423 };
1534 1424
1535 ufs_mem_hc: ufshc@1d84000 { !! 1425 ipa_virt: interconnect@1e00000 {
1536 compatible = "qcom,sc !! 1426 compatible = "qcom,sc7180-ipa-virt";
1537 "jedec,u !! 1427 reg = <0 0x01e00000 0 0x1000>;
1538 reg = <0 0x01d84000 0 !! 1428 #interconnect-cells = <2>;
1539 interrupts = <GIC_SPI !! 1429 qcom,bcm-voters = <&apps_bcm_voter>;
1540 phys = <&ufs_mem_phy> <<
1541 phy-names = "ufsphy"; <<
1542 lanes-per-direction = <<
1543 #reset-cells = <1>; <<
1544 resets = <&gcc GCC_UF <<
1545 reset-names = "rst"; <<
1546 <<
1547 power-domains = <&gcc <<
1548 <<
1549 iommus = <&apps_smmu <<
1550 <<
1551 clock-names = "core_c <<
1552 "bus_ag <<
1553 "iface_ <<
1554 "core_c <<
1555 "ref_cl <<
1556 "tx_lan <<
1557 "rx_lan <<
1558 clocks = <&gcc GCC_UF <<
1559 <&gcc GCC_AG <<
1560 <&gcc GCC_UF <<
1561 <&gcc GCC_UF <<
1562 <&rpmhcc RPM <<
1563 <&gcc GCC_UF <<
1564 <&gcc GCC_UF <<
1565 freq-table-hz = <5000 <<
1566 <0 0> <<
1567 <0 0> <<
1568 <3750 <<
1569 <0 0> <<
1570 <0 0> <<
1571 <0 0> <<
1572 <<
1573 interconnects = <&agg <<
1574 &mc_ <<
1575 <&gem <<
1576 &con <<
1577 interconnect-names = <<
1578 <<
1579 qcom,ice = <&ice>; <<
1580 <<
1581 status = "disabled"; <<
1582 }; <<
1583 <<
1584 ufs_mem_phy: phy@1d87000 { <<
1585 compatible = "qcom,sc <<
1586 reg = <0 0x01d87000 0 <<
1587 clocks = <&rpmhcc RPM <<
1588 <&gcc GCC_UF <<
1589 <&gcc GCC_UF <<
1590 clock-names = "ref", <<
1591 "ref_au <<
1592 "qref"; <<
1593 power-domains = <&gcc <<
1594 resets = <&ufs_mem_hc <<
1595 reset-names = "ufsphy <<
1596 #phy-cells = <0>; <<
1597 status = "disabled"; <<
1598 }; <<
1599 <<
1600 ice: crypto@1d90000 { <<
1601 compatible = "qcom,sc <<
1602 "qcom,in <<
1603 reg = <0 0x01d90000 0 <<
1604 clocks = <&gcc GCC_UF <<
1605 }; 1430 };
1606 1431
1607 ipa: ipa@1e40000 { 1432 ipa: ipa@1e40000 {
1608 compatible = "qcom,sc 1433 compatible = "qcom,sc7180-ipa";
1609 1434
1610 iommus = <&apps_smmu 1435 iommus = <&apps_smmu 0x440 0x0>,
1611 <&apps_smmu 1436 <&apps_smmu 0x442 0x0>;
1612 reg = <0 0x01e40000 0 !! 1437 reg = <0 0x1e40000 0 0x7000>,
1613 <0 0x01e47000 0 !! 1438 <0 0x1e47000 0 0x2000>,
1614 <0 0x01e04000 0 !! 1439 <0 0x1e04000 0 0x2c000>;
1615 reg-names = "ipa-reg" 1440 reg-names = "ipa-reg",
1616 "ipa-shar 1441 "ipa-shared",
1617 "gsi"; 1442 "gsi";
1618 1443
1619 interrupts-extended = 1444 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
1620 1445 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
1621 1446 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1622 1447 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
1623 interrupt-names = "ip 1448 interrupt-names = "ipa",
1624 "gs 1449 "gsi",
1625 "ip 1450 "ipa-clock-query",
1626 "ip 1451 "ipa-setup-ready";
1627 1452
1628 clocks = <&rpmhcc RPM 1453 clocks = <&rpmhcc RPMH_IPA_CLK>;
1629 clock-names = "core"; 1454 clock-names = "core";
1630 1455
1631 interconnects = <&agg 1456 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
1632 <&agg 1457 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>,
1633 <&gem 1458 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
1634 interconnect-names = 1459 interconnect-names = "memory",
1635 1460 "imem",
1636 1461 "config";
1637 1462
1638 qcom,qmp = <&aoss_qmp 1463 qcom,qmp = <&aoss_qmp>;
1639 1464
1640 qcom,smem-states = <& 1465 qcom,smem-states = <&ipa_smp2p_out 0>,
1641 <& 1466 <&ipa_smp2p_out 1>;
1642 qcom,smem-state-names 1467 qcom,smem-state-names = "ipa-clock-enabled-valid",
1643 1468 "ipa-clock-enabled";
1644 1469
1645 status = "disabled"; 1470 status = "disabled";
1646 }; 1471 };
1647 1472
1648 tcsr_mutex: hwlock@1f40000 { !! 1473 tcsr_mutex_regs: syscon@1f40000 {
1649 compatible = "qcom,tc !! 1474 compatible = "syscon";
1650 reg = <0 0x01f40000 0 !! 1475 reg = <0 0x01f40000 0 0x40000>;
1651 #hwlock-cells = <1>; <<
1652 }; 1476 };
1653 1477
1654 tcsr_regs_1: syscon@1f60000 { !! 1478 tcsr_regs: syscon@1fc0000 {
1655 compatible = "qcom,sc !! 1479 compatible = "syscon";
1656 reg = <0 0x01f60000 0 <<
1657 }; <<
1658 <<
1659 tcsr_regs_2: syscon@1fc0000 { <<
1660 compatible = "qcom,sc <<
1661 reg = <0 0x01fc0000 0 1480 reg = <0 0x01fc0000 0 0x40000>;
1662 }; 1481 };
1663 1482
1664 tlmm: pinctrl@3500000 { 1483 tlmm: pinctrl@3500000 {
1665 compatible = "qcom,sc 1484 compatible = "qcom,sc7180-pinctrl";
1666 reg = <0 0x03500000 0 1485 reg = <0 0x03500000 0 0x300000>,
1667 <0 0x03900000 0 1486 <0 0x03900000 0 0x300000>,
1668 <0 0x03d00000 0 1487 <0 0x03d00000 0 0x300000>;
1669 reg-names = "west", " 1488 reg-names = "west", "north", "south";
1670 interrupts = <GIC_SPI 1489 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1671 gpio-controller; 1490 gpio-controller;
1672 #gpio-cells = <2>; 1491 #gpio-cells = <2>;
1673 interrupt-controller; 1492 interrupt-controller;
1674 #interrupt-cells = <2 1493 #interrupt-cells = <2>;
1675 gpio-ranges = <&tlmm 1494 gpio-ranges = <&tlmm 0 0 120>;
1676 wakeup-parent = <&pdc 1495 wakeup-parent = <&pdc>;
1677 1496
1678 dp_hot_plug_det: dp-h !! 1497 dp_hot_plug_det: dp-hot-plug-det {
1679 pins = "gpio1 !! 1498 pinmux {
1680 function = "d !! 1499 pins = "gpio117";
1681 }; !! 1500 function = "dp_hot";
1682 !! 1501 };
1683 qspi_clk: qspi-clk-st <<
1684 pins = "gpio6 <<
1685 function = "q <<
1686 }; <<
1687 <<
1688 qspi_cs0: qspi-cs0-st <<
1689 pins = "gpio6 <<
1690 function = "q <<
1691 }; <<
1692 <<
1693 qspi_cs1: qspi-cs1-st <<
1694 pins = "gpio7 <<
1695 function = "q <<
1696 }; <<
1697 <<
1698 qspi_data0: qspi-data <<
1699 pins = "gpio6 <<
1700 function = "q <<
1701 }; <<
1702 <<
1703 qspi_data1: qspi-data <<
1704 pins = "gpio6 <<
1705 function = "q <<
1706 }; <<
1707 <<
1708 qspi_data23: qspi-dat <<
1709 pins = "gpio6 <<
1710 function = "q <<
1711 }; <<
1712 <<
1713 qup_i2c0_default: qup <<
1714 pins = "gpio3 <<
1715 function = "q <<
1716 }; <<
1717 <<
1718 qup_i2c1_default: qup <<
1719 pins = "gpio0 <<
1720 function = "q <<
1721 }; <<
1722 <<
1723 qup_i2c2_default: qup <<
1724 pins = "gpio1 <<
1725 function = "q <<
1726 }; <<
1727 <<
1728 qup_i2c3_default: qup <<
1729 pins = "gpio3 <<
1730 function = "q <<
1731 }; <<
1732 <<
1733 qup_i2c4_default: qup <<
1734 pins = "gpio1 <<
1735 function = "q <<
1736 }; <<
1737 <<
1738 qup_i2c5_default: qup <<
1739 pins = "gpio2 <<
1740 function = "q <<
1741 }; <<
1742 <<
1743 qup_i2c6_default: qup <<
1744 pins = "gpio5 <<
1745 function = "q <<
1746 }; <<
1747 <<
1748 qup_i2c7_default: qup <<
1749 pins = "gpio6 <<
1750 function = "q <<
1751 }; <<
1752 <<
1753 qup_i2c8_default: qup <<
1754 pins = "gpio4 <<
1755 function = "q <<
1756 }; <<
1757 <<
1758 qup_i2c9_default: qup <<
1759 pins = "gpio4 <<
1760 function = "q <<
1761 }; <<
1762 <<
1763 qup_i2c10_default: qu <<
1764 pins = "gpio8 <<
1765 function = "q <<
1766 }; <<
1767 <<
1768 qup_i2c11_default: qu <<
1769 pins = "gpio5 <<
1770 function = "q <<
1771 }; <<
1772 <<
1773 qup_spi0_spi: qup-spi <<
1774 pins = "gpio3 <<
1775 function = "q <<
1776 }; <<
1777 <<
1778 qup_spi0_cs: qup-spi0 <<
1779 pins = "gpio3 <<
1780 function = "q <<
1781 }; <<
1782 <<
1783 qup_spi0_cs_gpio: qup <<
1784 pins = "gpio3 <<
1785 function = "g <<
1786 }; <<
1787 <<
1788 qup_spi1_spi: qup-spi <<
1789 pins = "gpio0 <<
1790 function = "q <<
1791 }; <<
1792 <<
1793 qup_spi1_cs: qup-spi1 <<
1794 pins = "gpio3 <<
1795 function = "q <<
1796 }; <<
1797 <<
1798 qup_spi1_cs_gpio: qup <<
1799 pins = "gpio3 <<
1800 function = "g <<
1801 }; <<
1802 <<
1803 qup_spi3_spi: qup-spi <<
1804 pins = "gpio3 <<
1805 function = "q <<
1806 }; <<
1807 <<
1808 qup_spi3_cs: qup-spi3 <<
1809 pins = "gpio4 <<
1810 function = "q <<
1811 }; 1502 };
1812 1503
1813 qup_spi3_cs_gpio: qup !! 1504 qspi_clk: qspi-clk {
1814 pins = "gpio4 !! 1505 pinmux {
1815 function = "g !! 1506 pins = "gpio63";
>> 1507 function = "qspi_clk";
>> 1508 };
1816 }; 1509 };
1817 1510
1818 qup_spi5_spi: qup-spi !! 1511 qspi_cs0: qspi-cs0 {
1819 pins = "gpio2 !! 1512 pinmux {
1820 function = "q !! 1513 pins = "gpio68";
>> 1514 function = "qspi_cs";
>> 1515 };
1821 }; 1516 };
1822 1517
1823 qup_spi5_cs: qup-spi5 !! 1518 qspi_cs1: qspi-cs1 {
1824 pins = "gpio2 !! 1519 pinmux {
1825 function = "q !! 1520 pins = "gpio72";
>> 1521 function = "qspi_cs";
>> 1522 };
1826 }; 1523 };
1827 1524
1828 qup_spi5_cs_gpio: qup !! 1525 qspi_data01: qspi-data01 {
1829 pins = "gpio2 !! 1526 pinmux-data {
1830 function = "g !! 1527 pins = "gpio64", "gpio65";
>> 1528 function = "qspi_data";
>> 1529 };
1831 }; 1530 };
1832 1531
1833 qup_spi6_spi: qup-spi !! 1532 qspi_data12: qspi-data12 {
1834 pins = "gpio5 !! 1533 pinmux-data {
1835 function = "q !! 1534 pins = "gpio66", "gpio67";
>> 1535 function = "qspi_data";
>> 1536 };
1836 }; 1537 };
1837 1538
1838 qup_spi6_cs: qup-spi6 !! 1539 qup_i2c0_default: qup-i2c0-default {
1839 pins = "gpio6 !! 1540 pinmux {
1840 function = "q !! 1541 pins = "gpio34", "gpio35";
>> 1542 function = "qup00";
>> 1543 };
1841 }; 1544 };
1842 1545
1843 qup_spi6_cs_gpio: qup !! 1546 qup_i2c1_default: qup-i2c1-default {
1844 pins = "gpio6 !! 1547 pinmux {
1845 function = "g !! 1548 pins = "gpio0", "gpio1";
>> 1549 function = "qup01";
>> 1550 };
1846 }; 1551 };
1847 1552
1848 qup_spi8_spi: qup-spi !! 1553 qup_i2c2_default: qup-i2c2-default {
1849 pins = "gpio4 !! 1554 pinmux {
1850 function = "q !! 1555 pins = "gpio15", "gpio16";
>> 1556 function = "qup02_i2c";
>> 1557 };
1851 }; 1558 };
1852 1559
1853 qup_spi8_cs: qup-spi8 !! 1560 qup_i2c3_default: qup-i2c3-default {
1854 pins = "gpio4 !! 1561 pinmux {
1855 function = "q !! 1562 pins = "gpio38", "gpio39";
>> 1563 function = "qup03";
>> 1564 };
1856 }; 1565 };
1857 1566
1858 qup_spi8_cs_gpio: qup !! 1567 qup_i2c4_default: qup-i2c4-default {
1859 pins = "gpio4 !! 1568 pinmux {
1860 function = "g !! 1569 pins = "gpio115", "gpio116";
>> 1570 function = "qup04_i2c";
>> 1571 };
1861 }; 1572 };
1862 1573
1863 qup_spi10_spi: qup-sp !! 1574 qup_i2c5_default: qup-i2c5-default {
1864 pins = "gpio8 !! 1575 pinmux {
1865 function = "q !! 1576 pins = "gpio25", "gpio26";
>> 1577 function = "qup05";
>> 1578 };
1866 }; 1579 };
1867 1580
1868 qup_spi10_cs: qup-spi !! 1581 qup_i2c6_default: qup-i2c6-default {
1869 pins = "gpio8 !! 1582 pinmux {
1870 function = "q !! 1583 pins = "gpio59", "gpio60";
>> 1584 function = "qup10";
>> 1585 };
1871 }; 1586 };
1872 1587
1873 qup_spi10_cs_gpio: qu !! 1588 qup_i2c7_default: qup-i2c7-default {
1874 pins = "gpio8 !! 1589 pinmux {
1875 function = "g !! 1590 pins = "gpio6", "gpio7";
>> 1591 function = "qup11_i2c";
>> 1592 };
1876 }; 1593 };
1877 1594
1878 qup_spi11_spi: qup-sp !! 1595 qup_i2c8_default: qup-i2c8-default {
1879 pins = "gpio5 !! 1596 pinmux {
1880 function = "q !! 1597 pins = "gpio42", "gpio43";
>> 1598 function = "qup12";
>> 1599 };
1881 }; 1600 };
1882 1601
1883 qup_spi11_cs: qup-spi !! 1602 qup_i2c9_default: qup-i2c9-default {
1884 pins = "gpio5 !! 1603 pinmux {
1885 function = "q !! 1604 pins = "gpio46", "gpio47";
>> 1605 function = "qup13_i2c";
>> 1606 };
1886 }; 1607 };
1887 1608
1888 qup_spi11_cs_gpio: qu !! 1609 qup_i2c10_default: qup-i2c10-default {
1889 pins = "gpio5 !! 1610 pinmux {
1890 function = "g !! 1611 pins = "gpio86", "gpio87";
>> 1612 function = "qup14";
>> 1613 };
1891 }; 1614 };
1892 1615
1893 qup_uart0_default: qu !! 1616 qup_i2c11_default: qup-i2c11-default {
1894 qup_uart0_cts !! 1617 pinmux {
1895 pins !! 1618 pins = "gpio53", "gpio54";
1896 funct !! 1619 function = "qup15";
1897 }; 1620 };
>> 1621 };
1898 1622
1899 qup_uart0_rts !! 1623 qup_spi0_default: qup-spi0-default {
1900 pins !! 1624 pinmux {
>> 1625 pins = "gpio34", "gpio35",
>> 1626 "gpio36", "gpio37";
1901 funct 1627 function = "qup00";
1902 }; 1628 };
>> 1629 };
1903 1630
1904 qup_uart0_tx: !! 1631 qup_spi0_cs_gpio: qup-spi0-cs-gpio {
1905 pins !! 1632 pinmux {
>> 1633 pins = "gpio34", "gpio35",
>> 1634 "gpio36";
1906 funct 1635 function = "qup00";
1907 }; 1636 };
1908 1637
1909 qup_uart0_rx: !! 1638 pinmux-cs {
1910 pins 1639 pins = "gpio37";
1911 funct !! 1640 function = "gpio";
1912 }; 1641 };
1913 }; 1642 };
1914 1643
1915 qup_uart1_default: qu !! 1644 qup_spi1_default: qup-spi1-default {
1916 qup_uart1_cts !! 1645 pinmux {
1917 pins !! 1646 pins = "gpio0", "gpio1",
>> 1647 "gpio2", "gpio3";
1918 funct 1648 function = "qup01";
1919 }; 1649 };
>> 1650 };
1920 1651
1921 qup_uart1_rts !! 1652 qup_spi1_cs_gpio: qup-spi1-cs-gpio {
1922 pins !! 1653 pinmux {
>> 1654 pins = "gpio0", "gpio1",
>> 1655 "gpio2";
1923 funct 1656 function = "qup01";
1924 }; 1657 };
1925 1658
1926 qup_uart1_tx: !! 1659 pinmux-cs {
1927 pins !! 1660 pins = "gpio3";
1928 funct !! 1661 function = "gpio";
1929 }; 1662 };
>> 1663 };
1930 1664
1931 qup_uart1_rx: !! 1665 qup_spi3_default: qup-spi3-default {
1932 pins !! 1666 pinmux {
1933 funct !! 1667 pins = "gpio38", "gpio39",
>> 1668 "gpio40", "gpio41";
>> 1669 function = "qup03";
1934 }; 1670 };
1935 }; 1671 };
1936 1672
1937 qup_uart2_default: qu !! 1673 qup_spi3_cs_gpio: qup-spi3-cs-gpio {
1938 qup_uart2_tx: !! 1674 pinmux {
1939 pins !! 1675 pins = "gpio38", "gpio39",
1940 funct !! 1676 "gpio40";
>> 1677 function = "qup03";
1941 }; 1678 };
1942 1679
1943 qup_uart2_rx: !! 1680 pinmux-cs {
1944 pins !! 1681 pins = "gpio41";
1945 funct !! 1682 function = "gpio";
1946 }; 1683 };
1947 }; 1684 };
1948 1685
1949 qup_uart3_default: qu !! 1686 qup_spi5_default: qup-spi5-default {
1950 qup_uart3_cts !! 1687 pinmux {
1951 pins !! 1688 pins = "gpio25", "gpio26",
1952 funct !! 1689 "gpio27", "gpio28";
>> 1690 function = "qup05";
1953 }; 1691 };
>> 1692 };
1954 1693
1955 qup_uart3_rts !! 1694 qup_spi5_cs_gpio: qup-spi5-cs-gpio {
1956 pins !! 1695 pinmux {
1957 funct !! 1696 pins = "gpio25", "gpio26",
>> 1697 "gpio27";
>> 1698 function = "qup05";
1958 }; 1699 };
1959 1700
1960 qup_uart3_tx: !! 1701 pinmux-cs {
1961 pins !! 1702 pins = "gpio28";
1962 funct !! 1703 function = "gpio";
1963 }; 1704 };
>> 1705 };
1964 1706
1965 qup_uart3_rx: !! 1707 qup_spi6_default: qup-spi6-default {
1966 pins !! 1708 pinmux {
1967 funct !! 1709 pins = "gpio59", "gpio60",
>> 1710 "gpio61", "gpio62";
>> 1711 function = "qup10";
1968 }; 1712 };
1969 }; 1713 };
1970 1714
1971 qup_uart4_default: qu !! 1715 qup_spi6_cs_gpio: qup-spi6-cs-gpio {
1972 qup_uart4_tx: !! 1716 pinmux {
1973 pins !! 1717 pins = "gpio59", "gpio60",
1974 funct !! 1718 "gpio61";
>> 1719 function = "qup10";
1975 }; 1720 };
1976 1721
1977 qup_uart4_rx: !! 1722 pinmux-cs {
1978 pins !! 1723 pins = "gpio62";
1979 funct !! 1724 function = "gpio";
1980 }; 1725 };
1981 }; 1726 };
1982 1727
1983 qup_uart5_default: qu !! 1728 qup_spi8_default: qup-spi8-default {
1984 qup_uart5_cts !! 1729 pinmux {
1985 pins !! 1730 pins = "gpio42", "gpio43",
1986 funct !! 1731 "gpio44", "gpio45";
1987 }; !! 1732 function = "qup12";
1988 <<
1989 qup_uart5_rts <<
1990 pins <<
1991 funct <<
1992 }; 1733 };
>> 1734 };
1993 1735
1994 qup_uart5_tx: !! 1736 qup_spi8_cs_gpio: qup-spi8-cs-gpio {
1995 pins !! 1737 pinmux {
1996 funct !! 1738 pins = "gpio42", "gpio43",
>> 1739 "gpio44";
>> 1740 function = "qup12";
1997 }; 1741 };
1998 1742
1999 qup_uart5_rx: !! 1743 pinmux-cs {
2000 pins !! 1744 pins = "gpio45";
2001 funct !! 1745 function = "gpio";
2002 }; 1746 };
2003 }; 1747 };
2004 1748
2005 qup_uart6_default: qu !! 1749 qup_spi10_default: qup-spi10-default {
2006 qup_uart6_cts !! 1750 pinmux {
2007 pins !! 1751 pins = "gpio86", "gpio87",
2008 funct !! 1752 "gpio88", "gpio89";
>> 1753 function = "qup14";
2009 }; 1754 };
>> 1755 };
2010 1756
2011 qup_uart6_rts !! 1757 qup_spi10_cs_gpio: qup-spi10-cs-gpio {
2012 pins !! 1758 pinmux {
2013 funct !! 1759 pins = "gpio86", "gpio87",
>> 1760 "gpio88";
>> 1761 function = "qup14";
2014 }; 1762 };
2015 1763
2016 qup_uart6_tx: !! 1764 pinmux-cs {
2017 pins !! 1765 pins = "gpio89";
2018 funct !! 1766 function = "gpio";
2019 }; 1767 };
>> 1768 };
2020 1769
2021 qup_uart6_rx: !! 1770 qup_spi11_default: qup-spi11-default {
2022 pins !! 1771 pinmux {
2023 funct !! 1772 pins = "gpio53", "gpio54",
>> 1773 "gpio55", "gpio56";
>> 1774 function = "qup15";
2024 }; 1775 };
2025 }; 1776 };
2026 1777
2027 qup_uart7_default: qu !! 1778 qup_spi11_cs_gpio: qup-spi11-cs-gpio {
2028 qup_uart7_tx: !! 1779 pinmux {
2029 pins !! 1780 pins = "gpio53", "gpio54",
2030 funct !! 1781 "gpio55";
>> 1782 function = "qup15";
2031 }; 1783 };
2032 1784
2033 qup_uart7_rx: !! 1785 pinmux-cs {
2034 pins !! 1786 pins = "gpio56";
2035 funct !! 1787 function = "gpio";
2036 }; 1788 };
2037 }; 1789 };
2038 1790
2039 qup_uart8_default: qu !! 1791 qup_uart0_default: qup-uart0-default {
2040 qup_uart8_tx: !! 1792 pinmux {
2041 pins !! 1793 pins = "gpio34", "gpio35",
2042 funct !! 1794 "gpio36", "gpio37";
>> 1795 function = "qup00";
2043 }; 1796 };
>> 1797 };
2044 1798
2045 qup_uart8_rx: !! 1799 qup_uart1_default: qup-uart1-default {
2046 pins !! 1800 pinmux {
2047 funct !! 1801 pins = "gpio0", "gpio1",
>> 1802 "gpio2", "gpio3";
>> 1803 function = "qup01";
2048 }; 1804 };
2049 }; 1805 };
2050 1806
2051 qup_uart9_default: qu !! 1807 qup_uart2_default: qup-uart2-default {
2052 qup_uart9_tx: !! 1808 pinmux {
2053 pins !! 1809 pins = "gpio15", "gpio16";
2054 funct !! 1810 function = "qup02_uart";
2055 }; 1811 };
>> 1812 };
2056 1813
2057 qup_uart9_rx: !! 1814 qup_uart3_default: qup-uart3-default {
2058 pins !! 1815 pinmux {
2059 funct !! 1816 pins = "gpio38", "gpio39",
>> 1817 "gpio40", "gpio41";
>> 1818 function = "qup03";
2060 }; 1819 };
2061 }; 1820 };
2062 1821
2063 qup_uart10_default: q !! 1822 qup_uart4_default: qup-uart4-default {
2064 qup_uart10_ct !! 1823 pinmux {
2065 pins !! 1824 pins = "gpio115", "gpio116";
2066 funct !! 1825 function = "qup04_uart";
2067 }; 1826 };
>> 1827 };
2068 1828
2069 qup_uart10_rt !! 1829 qup_uart5_default: qup-uart5-default {
2070 pins !! 1830 pinmux {
2071 funct !! 1831 pins = "gpio25", "gpio26",
>> 1832 "gpio27", "gpio28";
>> 1833 function = "qup05";
2072 }; 1834 };
>> 1835 };
2073 1836
2074 qup_uart10_tx !! 1837 qup_uart6_default: qup-uart6-default {
2075 pins !! 1838 pinmux {
2076 funct !! 1839 pins = "gpio59", "gpio60",
>> 1840 "gpio61", "gpio62";
>> 1841 function = "qup10";
2077 }; 1842 };
>> 1843 };
2078 1844
2079 qup_uart10_rx !! 1845 qup_uart7_default: qup-uart7-default {
2080 pins !! 1846 pinmux {
2081 funct !! 1847 pins = "gpio6", "gpio7";
>> 1848 function = "qup11_uart";
2082 }; 1849 };
2083 }; 1850 };
2084 1851
2085 qup_uart11_default: q !! 1852 qup_uart8_default: qup-uart8-default {
2086 qup_uart11_ct !! 1853 pinmux {
2087 pins !! 1854 pins = "gpio44", "gpio45";
2088 funct !! 1855 function = "qup12";
2089 }; 1856 };
>> 1857 };
2090 1858
2091 qup_uart11_rt !! 1859 qup_uart9_default: qup-uart9-default {
2092 pins !! 1860 pinmux {
2093 funct !! 1861 pins = "gpio46", "gpio47";
>> 1862 function = "qup13_uart";
2094 }; 1863 };
>> 1864 };
2095 1865
2096 qup_uart11_tx !! 1866 qup_uart10_default: qup-uart10-default {
2097 pins !! 1867 pinmux {
2098 funct !! 1868 pins = "gpio86", "gpio87",
>> 1869 "gpio88", "gpio89";
>> 1870 function = "qup14";
2099 }; 1871 };
>> 1872 };
2100 1873
2101 qup_uart11_rx !! 1874 qup_uart11_default: qup-uart11-default {
2102 pins !! 1875 pinmux {
>> 1876 pins = "gpio53", "gpio54",
>> 1877 "gpio55", "gpio56";
2103 funct 1878 function = "qup15";
2104 }; 1879 };
2105 }; 1880 };
2106 1881
2107 sec_mi2s_active: sec- !! 1882 sec_mi2s_active: sec-mi2s-active {
2108 pins = "gpio4 !! 1883 pinmux {
2109 function = "m !! 1884 pins = "gpio49", "gpio50", "gpio51";
2110 }; !! 1885 function = "mi2s_1";
2111 !! 1886 };
2112 pri_mi2s_active: pri- <<
2113 pins = "gpio5 <<
2114 function = "m <<
2115 }; 1887 };
2116 1888
2117 pri_mi2s_mclk_active: !! 1889 pri_mi2s_active: pri-mi2s-active {
2118 pins = "gpio5 !! 1890 pinmux {
2119 function = "l !! 1891 pins = "gpio53", "gpio54", "gpio55", "gpio56";
>> 1892 function = "mi2s_0";
>> 1893 };
2120 }; 1894 };
2121 1895
2122 ter_mi2s_active: ter- !! 1896 pri_mi2s_mclk_active: pri-mi2s-mclk-active {
2123 pins = "gpio6 !! 1897 pinmux {
2124 function = "m !! 1898 pins = "gpio57";
>> 1899 function = "lpass_ext";
>> 1900 };
2125 }; 1901 };
2126 }; 1902 };
2127 1903
2128 remoteproc_mpss: remoteproc@4 1904 remoteproc_mpss: remoteproc@4080000 {
2129 compatible = "qcom,sc 1905 compatible = "qcom,sc7180-mpss-pas";
2130 reg = <0 0x04080000 0 !! 1906 reg = <0 0x04080000 0 0x4040>, <0 0x04180000 0 0x48>;
>> 1907 reg-names = "qdsp6", "rmb";
2131 1908
2132 interrupts-extended = 1909 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
2133 1910 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2134 1911 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2135 1912 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2136 1913 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
2137 1914 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
2138 interrupt-names = "wd 1915 interrupt-names = "wdog", "fatal", "ready", "handover",
2139 "st 1916 "stop-ack", "shutdown-ack";
2140 1917
2141 clocks = <&rpmhcc RPM !! 1918 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
2142 clock-names = "xo"; !! 1919 <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>,
>> 1920 <&gcc GCC_MSS_NAV_AXI_CLK>,
>> 1921 <&gcc GCC_MSS_SNOC_AXI_CLK>,
>> 1922 <&gcc GCC_MSS_MFAB_AXIS_CLK>,
>> 1923 <&rpmhcc RPMH_CXO_CLK>;
>> 1924 clock-names = "iface", "bus", "nav", "snoc_axi",
>> 1925 "mnoc_axi", "xo";
2143 1926
2144 power-domains = <&rpm !! 1927 power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>,
>> 1928 <&rpmhpd SC7180_CX>,
2145 <&rpm 1929 <&rpmhpd SC7180_MX>,
2146 <&rpm 1930 <&rpmhpd SC7180_MSS>;
2147 power-domain-names = !! 1931 power-domain-names = "load_state", "cx", "mx", "mss";
2148 1932
2149 memory-region = <&mps 1933 memory-region = <&mpss_mem>;
2150 1934
2151 qcom,qmp = <&aoss_qmp <<
2152 <<
2153 qcom,smem-states = <& 1935 qcom,smem-states = <&modem_smp2p_out 0>;
2154 qcom,smem-state-names 1936 qcom,smem-state-names = "stop";
2155 1937
>> 1938 resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
>> 1939 <&pdc_reset PDC_MODEM_SYNC_RESET>;
>> 1940 reset-names = "mss_restart", "pdc_reset";
>> 1941
>> 1942 qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
>> 1943 qcom,spare-regs = <&tcsr_regs 0xb3e4>;
>> 1944
2156 status = "disabled"; 1945 status = "disabled";
2157 1946
2158 glink-edge { 1947 glink-edge {
2159 interrupts = 1948 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
2160 label = "mode 1949 label = "modem";
2161 qcom,remote-p 1950 qcom,remote-pid = <1>;
2162 mboxes = <&ap 1951 mboxes = <&apss_shared 12>;
2163 }; 1952 };
2164 }; 1953 };
2165 1954
2166 gpu: gpu@5000000 { 1955 gpu: gpu@5000000 {
2167 compatible = "qcom,ad 1956 compatible = "qcom,adreno-618.0", "qcom,adreno";
>> 1957 #stream-id-cells = <16>;
2168 reg = <0 0x05000000 0 1958 reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x1000>,
2169 <0 0x05061000 1959 <0 0x05061000 0 0x800>;
2170 reg-names = "kgsl_3d0 1960 reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc";
2171 interrupts = <GIC_SPI 1961 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2172 iommus = <&adreno_smm 1962 iommus = <&adreno_smmu 0>;
2173 operating-points-v2 = 1963 operating-points-v2 = <&gpu_opp_table>;
2174 qcom,gmu = <&gmu>; 1964 qcom,gmu = <&gmu>;
2175 1965
2176 #cooling-cells = <2>; 1966 #cooling-cells = <2>;
2177 1967
2178 nvmem-cells = <&gpu_s 1968 nvmem-cells = <&gpu_speed_bin>;
2179 nvmem-cell-names = "s 1969 nvmem-cell-names = "speed_bin";
2180 1970
2181 interconnects = <&gem 1971 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
2182 interconnect-names = 1972 interconnect-names = "gfx-mem";
2183 1973
2184 gpu_opp_table: opp-ta 1974 gpu_opp_table: opp-table {
2185 compatible = 1975 compatible = "operating-points-v2";
2186 1976
2187 opp-825000000 1977 opp-825000000 {
2188 opp-h 1978 opp-hz = /bits/ 64 <825000000>;
2189 opp-l 1979 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2190 opp-p 1980 opp-peak-kBps = <8532000>;
2191 opp-s 1981 opp-supported-hw = <0x04>;
2192 }; 1982 };
2193 1983
2194 opp-800000000 1984 opp-800000000 {
2195 opp-h 1985 opp-hz = /bits/ 64 <800000000>;
2196 opp-l 1986 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2197 opp-p 1987 opp-peak-kBps = <8532000>;
2198 opp-s 1988 opp-supported-hw = <0x07>;
2199 }; 1989 };
2200 1990
2201 opp-650000000 1991 opp-650000000 {
2202 opp-h 1992 opp-hz = /bits/ 64 <650000000>;
2203 opp-l 1993 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2204 opp-p 1994 opp-peak-kBps = <7216000>;
2205 opp-s 1995 opp-supported-hw = <0x07>;
2206 }; 1996 };
2207 1997
2208 opp-565000000 1998 opp-565000000 {
2209 opp-h 1999 opp-hz = /bits/ 64 <565000000>;
2210 opp-l 2000 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2211 opp-p 2001 opp-peak-kBps = <5412000>;
2212 opp-s 2002 opp-supported-hw = <0x07>;
2213 }; 2003 };
2214 2004
2215 opp-430000000 2005 opp-430000000 {
2216 opp-h 2006 opp-hz = /bits/ 64 <430000000>;
2217 opp-l 2007 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2218 opp-p 2008 opp-peak-kBps = <5412000>;
2219 opp-s 2009 opp-supported-hw = <0x07>;
2220 }; 2010 };
2221 2011
2222 opp-355000000 2012 opp-355000000 {
2223 opp-h 2013 opp-hz = /bits/ 64 <355000000>;
2224 opp-l 2014 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2225 opp-p 2015 opp-peak-kBps = <3072000>;
2226 opp-s 2016 opp-supported-hw = <0x07>;
2227 }; 2017 };
2228 2018
2229 opp-267000000 2019 opp-267000000 {
2230 opp-h 2020 opp-hz = /bits/ 64 <267000000>;
2231 opp-l 2021 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2232 opp-p 2022 opp-peak-kBps = <3072000>;
2233 opp-s 2023 opp-supported-hw = <0x07>;
2234 }; 2024 };
2235 2025
2236 opp-180000000 2026 opp-180000000 {
2237 opp-h 2027 opp-hz = /bits/ 64 <180000000>;
2238 opp-l 2028 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2239 opp-p 2029 opp-peak-kBps = <1804000>;
2240 opp-s 2030 opp-supported-hw = <0x07>;
2241 }; 2031 };
2242 }; 2032 };
2243 }; 2033 };
2244 2034
2245 adreno_smmu: iommu@5040000 { 2035 adreno_smmu: iommu@5040000 {
2246 compatible = "qcom,sc 2036 compatible = "qcom,sc7180-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
2247 reg = <0 0x05040000 0 2037 reg = <0 0x05040000 0 0x10000>;
2248 #iommu-cells = <1>; 2038 #iommu-cells = <1>;
2249 #global-interrupts = 2039 #global-interrupts = <2>;
2250 interrupts = <GIC_SPI 2040 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
2251 <GIC_ 2041 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
2252 <GIC_ 2042 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
2253 <GIC_ 2043 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
2254 <GIC_ 2044 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
2255 <GIC_ 2045 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
2256 <GIC_ 2046 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
2257 <GIC_ 2047 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
2258 <GIC_ 2048 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
2259 <GIC_ 2049 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
2260 2050
2261 clocks = <&gcc GCC_GP 2051 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2262 <&gcc GCC_GPU 2052 <&gcc GCC_GPU_CFG_AHB_CLK>;
2263 clock-names = "bus", 2053 clock-names = "bus", "iface";
2264 2054
2265 power-domains = <&gpu 2055 power-domains = <&gpucc CX_GDSC>;
2266 }; 2056 };
2267 2057
2268 gmu: gmu@506a000 { 2058 gmu: gmu@506a000 {
2269 compatible = "qcom,ad !! 2059 compatible="qcom,adreno-gmu-618.0", "qcom,adreno-gmu";
2270 reg = <0 0x0506a000 0 2060 reg = <0 0x0506a000 0 0x31000>, <0 0x0b290000 0 0x10000>,
2271 <0 0x0b490000 2061 <0 0x0b490000 0 0x10000>;
2272 reg-names = "gmu", "g 2062 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
2273 interrupts = <GIC_SPI 2063 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2274 <GIC_SPI 3 2064 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2275 interrupt-names = "hf 2065 interrupt-names = "hfi", "gmu";
2276 clocks = <&gpucc GPU_ 2066 clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
2277 <&gpucc GPU_CC 2067 <&gpucc GPU_CC_CXO_CLK>,
2278 <&gcc GCC_DDRS 2068 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2279 <&gcc GCC_GPU_ 2069 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
2280 clock-names = "gmu", 2070 clock-names = "gmu", "cxo", "axi", "memnoc";
2281 power-domains = <&gpu 2071 power-domains = <&gpucc CX_GDSC>, <&gpucc GX_GDSC>;
2282 power-domain-names = 2072 power-domain-names = "cx", "gx";
2283 iommus = <&adreno_smm 2073 iommus = <&adreno_smmu 5>;
2284 operating-points-v2 = 2074 operating-points-v2 = <&gmu_opp_table>;
2285 2075
2286 gmu_opp_table: opp-ta 2076 gmu_opp_table: opp-table {
2287 compatible = 2077 compatible = "operating-points-v2";
2288 2078
2289 opp-200000000 2079 opp-200000000 {
2290 opp-h 2080 opp-hz = /bits/ 64 <200000000>;
2291 opp-l 2081 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2292 }; 2082 };
2293 }; 2083 };
2294 }; 2084 };
2295 2085
2296 gpucc: clock-controller@50900 2086 gpucc: clock-controller@5090000 {
2297 compatible = "qcom,sc 2087 compatible = "qcom,sc7180-gpucc";
2298 reg = <0 0x05090000 0 2088 reg = <0 0x05090000 0 0x9000>;
2299 clocks = <&rpmhcc RPM 2089 clocks = <&rpmhcc RPMH_CXO_CLK>,
2300 <&gcc GCC_GP 2090 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2301 <&gcc GCC_GP 2091 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2302 clock-names = "bi_tcx 2092 clock-names = "bi_tcxo",
2303 "gcc_gp 2093 "gcc_gpu_gpll0_clk_src",
2304 "gcc_gp 2094 "gcc_gpu_gpll0_div_clk_src";
2305 #clock-cells = <1>; 2095 #clock-cells = <1>;
2306 #reset-cells = <1>; 2096 #reset-cells = <1>;
2307 #power-domain-cells = 2097 #power-domain-cells = <1>;
2308 }; 2098 };
2309 2099
2310 dma@10a2000 { <<
2311 compatible = "qcom,sc <<
2312 reg = <0x0 0x010a2000 <<
2313 <0x0 0x010ae000 <<
2314 status = "disabled"; <<
2315 }; <<
2316 <<
2317 stm@6002000 { 2100 stm@6002000 {
2318 compatible = "arm,cor 2101 compatible = "arm,coresight-stm", "arm,primecell";
2319 reg = <0 0x06002000 0 2102 reg = <0 0x06002000 0 0x1000>,
2320 <0 0x16280000 0 2103 <0 0x16280000 0 0x180000>;
2321 reg-names = "stm-base 2104 reg-names = "stm-base", "stm-stimulus-base";
2322 2105
2323 clocks = <&aoss_qmp>; 2106 clocks = <&aoss_qmp>;
2324 clock-names = "apb_pc 2107 clock-names = "apb_pclk";
2325 2108
2326 out-ports { 2109 out-ports {
2327 port { 2110 port {
2328 stm_o 2111 stm_out: endpoint {
2329 2112 remote-endpoint = <&funnel0_in7>;
2330 }; 2113 };
2331 }; 2114 };
2332 }; 2115 };
2333 }; 2116 };
2334 2117
2335 funnel@6041000 { 2118 funnel@6041000 {
2336 compatible = "arm,cor 2119 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2337 reg = <0 0x06041000 0 2120 reg = <0 0x06041000 0 0x1000>;
2338 2121
2339 clocks = <&aoss_qmp>; 2122 clocks = <&aoss_qmp>;
2340 clock-names = "apb_pc 2123 clock-names = "apb_pclk";
2341 2124
2342 out-ports { 2125 out-ports {
2343 port { 2126 port {
2344 funne 2127 funnel0_out: endpoint {
2345 2128 remote-endpoint = <&merge_funnel_in0>;
2346 }; 2129 };
2347 }; 2130 };
2348 }; 2131 };
2349 2132
2350 in-ports { 2133 in-ports {
2351 #address-cell 2134 #address-cells = <1>;
2352 #size-cells = 2135 #size-cells = <0>;
2353 2136
2354 port@7 { 2137 port@7 {
2355 reg = 2138 reg = <7>;
2356 funne 2139 funnel0_in7: endpoint {
2357 2140 remote-endpoint = <&stm_out>;
2358 }; 2141 };
2359 }; 2142 };
2360 }; 2143 };
2361 }; 2144 };
2362 2145
2363 funnel@6042000 { 2146 funnel@6042000 {
2364 compatible = "arm,cor 2147 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2365 reg = <0 0x06042000 0 2148 reg = <0 0x06042000 0 0x1000>;
2366 2149
2367 clocks = <&aoss_qmp>; 2150 clocks = <&aoss_qmp>;
2368 clock-names = "apb_pc 2151 clock-names = "apb_pclk";
2369 2152
2370 out-ports { 2153 out-ports {
2371 port { 2154 port {
2372 funne 2155 funnel1_out: endpoint {
2373 2156 remote-endpoint = <&merge_funnel_in1>;
2374 }; 2157 };
2375 }; 2158 };
2376 }; 2159 };
2377 2160
2378 in-ports { 2161 in-ports {
2379 #address-cell 2162 #address-cells = <1>;
2380 #size-cells = 2163 #size-cells = <0>;
2381 2164
2382 port@4 { 2165 port@4 {
2383 reg = 2166 reg = <4>;
2384 funne 2167 funnel1_in4: endpoint {
2385 2168 remote-endpoint = <&apss_merge_funnel_out>;
2386 }; 2169 };
2387 }; 2170 };
2388 }; 2171 };
2389 }; 2172 };
2390 2173
2391 funnel@6045000 { 2174 funnel@6045000 {
2392 compatible = "arm,cor 2175 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2393 reg = <0 0x06045000 0 2176 reg = <0 0x06045000 0 0x1000>;
2394 2177
2395 clocks = <&aoss_qmp>; 2178 clocks = <&aoss_qmp>;
2396 clock-names = "apb_pc 2179 clock-names = "apb_pclk";
2397 2180
2398 out-ports { 2181 out-ports {
2399 port { 2182 port {
2400 merge 2183 merge_funnel_out: endpoint {
2401 2184 remote-endpoint = <&swao_funnel_in>;
2402 }; 2185 };
2403 }; 2186 };
2404 }; 2187 };
2405 2188
2406 in-ports { 2189 in-ports {
2407 #address-cell 2190 #address-cells = <1>;
2408 #size-cells = 2191 #size-cells = <0>;
2409 2192
2410 port@0 { 2193 port@0 {
2411 reg = 2194 reg = <0>;
2412 merge 2195 merge_funnel_in0: endpoint {
2413 2196 remote-endpoint = <&funnel0_out>;
2414 }; 2197 };
2415 }; 2198 };
2416 2199
2417 port@1 { 2200 port@1 {
2418 reg = 2201 reg = <1>;
2419 merge 2202 merge_funnel_in1: endpoint {
2420 2203 remote-endpoint = <&funnel1_out>;
2421 }; 2204 };
2422 }; 2205 };
2423 }; 2206 };
2424 }; 2207 };
2425 2208
2426 replicator@6046000 { 2209 replicator@6046000 {
2427 compatible = "arm,cor 2210 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2428 reg = <0 0x06046000 0 2211 reg = <0 0x06046000 0 0x1000>;
2429 2212
2430 clocks = <&aoss_qmp>; 2213 clocks = <&aoss_qmp>;
2431 clock-names = "apb_pc 2214 clock-names = "apb_pclk";
2432 2215
2433 out-ports { 2216 out-ports {
2434 port { 2217 port {
2435 repli 2218 replicator_out: endpoint {
2436 2219 remote-endpoint = <&etr_in>;
2437 }; 2220 };
2438 }; 2221 };
2439 }; 2222 };
2440 2223
2441 in-ports { 2224 in-ports {
2442 port { 2225 port {
2443 repli 2226 replicator_in: endpoint {
2444 2227 remote-endpoint = <&swao_replicator_out>;
2445 }; 2228 };
2446 }; 2229 };
2447 }; 2230 };
2448 }; 2231 };
2449 2232
2450 etr@6048000 { 2233 etr@6048000 {
2451 compatible = "arm,cor 2234 compatible = "arm,coresight-tmc", "arm,primecell";
2452 reg = <0 0x06048000 0 2235 reg = <0 0x06048000 0 0x1000>;
2453 iommus = <&apps_smmu 2236 iommus = <&apps_smmu 0x04a0 0x20>;
2454 2237
2455 clocks = <&aoss_qmp>; 2238 clocks = <&aoss_qmp>;
2456 clock-names = "apb_pc 2239 clock-names = "apb_pclk";
2457 arm,scatter-gather; 2240 arm,scatter-gather;
2458 2241
2459 in-ports { 2242 in-ports {
2460 port { 2243 port {
2461 etr_i 2244 etr_in: endpoint {
2462 2245 remote-endpoint = <&replicator_out>;
2463 }; 2246 };
2464 }; 2247 };
2465 }; 2248 };
2466 }; 2249 };
2467 2250
2468 funnel@6b04000 { 2251 funnel@6b04000 {
2469 compatible = "arm,cor 2252 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2470 reg = <0 0x06b04000 0 2253 reg = <0 0x06b04000 0 0x1000>;
2471 2254
2472 clocks = <&aoss_qmp>; 2255 clocks = <&aoss_qmp>;
2473 clock-names = "apb_pc 2256 clock-names = "apb_pclk";
2474 2257
2475 out-ports { 2258 out-ports {
2476 port { 2259 port {
2477 swao_ 2260 swao_funnel_out: endpoint {
2478 2261 remote-endpoint = <&etf_in>;
2479 }; 2262 };
2480 }; 2263 };
2481 }; 2264 };
2482 2265
2483 in-ports { 2266 in-ports {
2484 #address-cell 2267 #address-cells = <1>;
2485 #size-cells = 2268 #size-cells = <0>;
2486 2269
2487 port@7 { 2270 port@7 {
2488 reg = 2271 reg = <7>;
2489 swao_ 2272 swao_funnel_in: endpoint {
2490 2273 remote-endpoint = <&merge_funnel_out>;
2491 }; 2274 };
2492 }; 2275 };
2493 }; 2276 };
2494 }; 2277 };
2495 2278
2496 etf@6b05000 { 2279 etf@6b05000 {
2497 compatible = "arm,cor 2280 compatible = "arm,coresight-tmc", "arm,primecell";
2498 reg = <0 0x06b05000 0 2281 reg = <0 0x06b05000 0 0x1000>;
2499 2282
2500 clocks = <&aoss_qmp>; 2283 clocks = <&aoss_qmp>;
2501 clock-names = "apb_pc 2284 clock-names = "apb_pclk";
2502 2285
2503 out-ports { 2286 out-ports {
2504 port { 2287 port {
2505 etf_o 2288 etf_out: endpoint {
2506 2289 remote-endpoint = <&swao_replicator_in>;
2507 }; 2290 };
2508 }; 2291 };
2509 }; 2292 };
2510 2293
2511 in-ports { 2294 in-ports {
2512 port { 2295 port {
2513 etf_i 2296 etf_in: endpoint {
2514 2297 remote-endpoint = <&swao_funnel_out>;
2515 }; 2298 };
2516 }; 2299 };
2517 }; 2300 };
2518 }; 2301 };
2519 2302
2520 replicator@6b06000 { 2303 replicator@6b06000 {
2521 compatible = "arm,cor 2304 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2522 reg = <0 0x06b06000 0 2305 reg = <0 0x06b06000 0 0x1000>;
2523 2306
2524 clocks = <&aoss_qmp>; 2307 clocks = <&aoss_qmp>;
2525 clock-names = "apb_pc 2308 clock-names = "apb_pclk";
2526 qcom,replicator-loses 2309 qcom,replicator-loses-context;
2527 2310
2528 out-ports { 2311 out-ports {
2529 port { 2312 port {
2530 swao_ 2313 swao_replicator_out: endpoint {
2531 2314 remote-endpoint = <&replicator_in>;
2532 }; 2315 };
2533 }; 2316 };
2534 }; 2317 };
2535 2318
2536 in-ports { 2319 in-ports {
2537 port { 2320 port {
2538 swao_ 2321 swao_replicator_in: endpoint {
2539 2322 remote-endpoint = <&etf_out>;
2540 }; 2323 };
2541 }; 2324 };
2542 }; 2325 };
2543 }; 2326 };
2544 2327
2545 etm@7040000 { 2328 etm@7040000 {
2546 compatible = "arm,cor 2329 compatible = "arm,coresight-etm4x", "arm,primecell";
2547 reg = <0 0x07040000 0 2330 reg = <0 0x07040000 0 0x1000>;
2548 2331
2549 cpu = <&CPU0>; 2332 cpu = <&CPU0>;
2550 2333
2551 clocks = <&aoss_qmp>; 2334 clocks = <&aoss_qmp>;
2552 clock-names = "apb_pc 2335 clock-names = "apb_pclk";
2553 arm,coresight-loses-c 2336 arm,coresight-loses-context-with-cpu;
2554 qcom,skip-power-up; 2337 qcom,skip-power-up;
2555 2338
2556 out-ports { 2339 out-ports {
2557 port { 2340 port {
2558 etm0_ 2341 etm0_out: endpoint {
2559 2342 remote-endpoint = <&apss_funnel_in0>;
2560 }; 2343 };
2561 }; 2344 };
2562 }; 2345 };
2563 }; 2346 };
2564 2347
2565 etm@7140000 { 2348 etm@7140000 {
2566 compatible = "arm,cor 2349 compatible = "arm,coresight-etm4x", "arm,primecell";
2567 reg = <0 0x07140000 0 2350 reg = <0 0x07140000 0 0x1000>;
2568 2351
2569 cpu = <&CPU1>; 2352 cpu = <&CPU1>;
2570 2353
2571 clocks = <&aoss_qmp>; 2354 clocks = <&aoss_qmp>;
2572 clock-names = "apb_pc 2355 clock-names = "apb_pclk";
2573 arm,coresight-loses-c 2356 arm,coresight-loses-context-with-cpu;
2574 qcom,skip-power-up; 2357 qcom,skip-power-up;
2575 2358
2576 out-ports { 2359 out-ports {
2577 port { 2360 port {
2578 etm1_ 2361 etm1_out: endpoint {
2579 2362 remote-endpoint = <&apss_funnel_in1>;
2580 }; 2363 };
2581 }; 2364 };
2582 }; 2365 };
2583 }; 2366 };
2584 2367
2585 etm@7240000 { 2368 etm@7240000 {
2586 compatible = "arm,cor 2369 compatible = "arm,coresight-etm4x", "arm,primecell";
2587 reg = <0 0x07240000 0 2370 reg = <0 0x07240000 0 0x1000>;
2588 2371
2589 cpu = <&CPU2>; 2372 cpu = <&CPU2>;
2590 2373
2591 clocks = <&aoss_qmp>; 2374 clocks = <&aoss_qmp>;
2592 clock-names = "apb_pc 2375 clock-names = "apb_pclk";
2593 arm,coresight-loses-c 2376 arm,coresight-loses-context-with-cpu;
2594 qcom,skip-power-up; 2377 qcom,skip-power-up;
2595 2378
2596 out-ports { 2379 out-ports {
2597 port { 2380 port {
2598 etm2_ 2381 etm2_out: endpoint {
2599 2382 remote-endpoint = <&apss_funnel_in2>;
2600 }; 2383 };
2601 }; 2384 };
2602 }; 2385 };
2603 }; 2386 };
2604 2387
2605 etm@7340000 { 2388 etm@7340000 {
2606 compatible = "arm,cor 2389 compatible = "arm,coresight-etm4x", "arm,primecell";
2607 reg = <0 0x07340000 0 2390 reg = <0 0x07340000 0 0x1000>;
2608 2391
2609 cpu = <&CPU3>; 2392 cpu = <&CPU3>;
2610 2393
2611 clocks = <&aoss_qmp>; 2394 clocks = <&aoss_qmp>;
2612 clock-names = "apb_pc 2395 clock-names = "apb_pclk";
2613 arm,coresight-loses-c 2396 arm,coresight-loses-context-with-cpu;
2614 qcom,skip-power-up; 2397 qcom,skip-power-up;
2615 2398
2616 out-ports { 2399 out-ports {
2617 port { 2400 port {
2618 etm3_ 2401 etm3_out: endpoint {
2619 2402 remote-endpoint = <&apss_funnel_in3>;
2620 }; 2403 };
2621 }; 2404 };
2622 }; 2405 };
2623 }; 2406 };
2624 2407
2625 etm@7440000 { 2408 etm@7440000 {
2626 compatible = "arm,cor 2409 compatible = "arm,coresight-etm4x", "arm,primecell";
2627 reg = <0 0x07440000 0 2410 reg = <0 0x07440000 0 0x1000>;
2628 2411
2629 cpu = <&CPU4>; 2412 cpu = <&CPU4>;
2630 2413
2631 clocks = <&aoss_qmp>; 2414 clocks = <&aoss_qmp>;
2632 clock-names = "apb_pc 2415 clock-names = "apb_pclk";
2633 arm,coresight-loses-c 2416 arm,coresight-loses-context-with-cpu;
2634 qcom,skip-power-up; 2417 qcom,skip-power-up;
2635 2418
2636 out-ports { 2419 out-ports {
2637 port { 2420 port {
2638 etm4_ 2421 etm4_out: endpoint {
2639 2422 remote-endpoint = <&apss_funnel_in4>;
2640 }; 2423 };
2641 }; 2424 };
2642 }; 2425 };
2643 }; 2426 };
2644 2427
2645 etm@7540000 { 2428 etm@7540000 {
2646 compatible = "arm,cor 2429 compatible = "arm,coresight-etm4x", "arm,primecell";
2647 reg = <0 0x07540000 0 2430 reg = <0 0x07540000 0 0x1000>;
2648 2431
2649 cpu = <&CPU5>; 2432 cpu = <&CPU5>;
2650 2433
2651 clocks = <&aoss_qmp>; 2434 clocks = <&aoss_qmp>;
2652 clock-names = "apb_pc 2435 clock-names = "apb_pclk";
2653 arm,coresight-loses-c 2436 arm,coresight-loses-context-with-cpu;
2654 qcom,skip-power-up; 2437 qcom,skip-power-up;
2655 2438
2656 out-ports { 2439 out-ports {
2657 port { 2440 port {
2658 etm5_ 2441 etm5_out: endpoint {
2659 2442 remote-endpoint = <&apss_funnel_in5>;
2660 }; 2443 };
2661 }; 2444 };
2662 }; 2445 };
2663 }; 2446 };
2664 2447
2665 etm@7640000 { 2448 etm@7640000 {
2666 compatible = "arm,cor 2449 compatible = "arm,coresight-etm4x", "arm,primecell";
2667 reg = <0 0x07640000 0 2450 reg = <0 0x07640000 0 0x1000>;
2668 2451
2669 cpu = <&CPU6>; 2452 cpu = <&CPU6>;
2670 2453
2671 clocks = <&aoss_qmp>; 2454 clocks = <&aoss_qmp>;
2672 clock-names = "apb_pc 2455 clock-names = "apb_pclk";
2673 arm,coresight-loses-c 2456 arm,coresight-loses-context-with-cpu;
2674 qcom,skip-power-up; 2457 qcom,skip-power-up;
2675 2458
2676 out-ports { 2459 out-ports {
2677 port { 2460 port {
2678 etm6_ 2461 etm6_out: endpoint {
2679 2462 remote-endpoint = <&apss_funnel_in6>;
2680 }; 2463 };
2681 }; 2464 };
2682 }; 2465 };
2683 }; 2466 };
2684 2467
2685 etm@7740000 { 2468 etm@7740000 {
2686 compatible = "arm,cor 2469 compatible = "arm,coresight-etm4x", "arm,primecell";
2687 reg = <0 0x07740000 0 2470 reg = <0 0x07740000 0 0x1000>;
2688 2471
2689 cpu = <&CPU7>; 2472 cpu = <&CPU7>;
2690 2473
2691 clocks = <&aoss_qmp>; 2474 clocks = <&aoss_qmp>;
2692 clock-names = "apb_pc 2475 clock-names = "apb_pclk";
2693 arm,coresight-loses-c 2476 arm,coresight-loses-context-with-cpu;
2694 qcom,skip-power-up; 2477 qcom,skip-power-up;
2695 2478
2696 out-ports { 2479 out-ports {
2697 port { 2480 port {
2698 etm7_ 2481 etm7_out: endpoint {
2699 2482 remote-endpoint = <&apss_funnel_in7>;
2700 }; 2483 };
2701 }; 2484 };
2702 }; 2485 };
2703 }; 2486 };
2704 2487
2705 funnel@7800000 { /* APSS Funn 2488 funnel@7800000 { /* APSS Funnel */
2706 compatible = "arm,cor 2489 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2707 reg = <0 0x07800000 0 2490 reg = <0 0x07800000 0 0x1000>;
2708 2491
2709 clocks = <&aoss_qmp>; 2492 clocks = <&aoss_qmp>;
2710 clock-names = "apb_pc 2493 clock-names = "apb_pclk";
2711 2494
2712 out-ports { 2495 out-ports {
2713 port { 2496 port {
2714 apss_ 2497 apss_funnel_out: endpoint {
2715 2498 remote-endpoint = <&apss_merge_funnel_in>;
2716 }; 2499 };
2717 }; 2500 };
2718 }; 2501 };
2719 2502
2720 in-ports { 2503 in-ports {
2721 #address-cell 2504 #address-cells = <1>;
2722 #size-cells = 2505 #size-cells = <0>;
2723 2506
2724 port@0 { 2507 port@0 {
2725 reg = 2508 reg = <0>;
2726 apss_ 2509 apss_funnel_in0: endpoint {
2727 2510 remote-endpoint = <&etm0_out>;
2728 }; 2511 };
2729 }; 2512 };
2730 2513
2731 port@1 { 2514 port@1 {
2732 reg = 2515 reg = <1>;
2733 apss_ 2516 apss_funnel_in1: endpoint {
2734 2517 remote-endpoint = <&etm1_out>;
2735 }; 2518 };
2736 }; 2519 };
2737 2520
2738 port@2 { 2521 port@2 {
2739 reg = 2522 reg = <2>;
2740 apss_ 2523 apss_funnel_in2: endpoint {
2741 2524 remote-endpoint = <&etm2_out>;
2742 }; 2525 };
2743 }; 2526 };
2744 2527
2745 port@3 { 2528 port@3 {
2746 reg = 2529 reg = <3>;
2747 apss_ 2530 apss_funnel_in3: endpoint {
2748 2531 remote-endpoint = <&etm3_out>;
2749 }; 2532 };
2750 }; 2533 };
2751 2534
2752 port@4 { 2535 port@4 {
2753 reg = 2536 reg = <4>;
2754 apss_ 2537 apss_funnel_in4: endpoint {
2755 2538 remote-endpoint = <&etm4_out>;
2756 }; 2539 };
2757 }; 2540 };
2758 2541
2759 port@5 { 2542 port@5 {
2760 reg = 2543 reg = <5>;
2761 apss_ 2544 apss_funnel_in5: endpoint {
2762 2545 remote-endpoint = <&etm5_out>;
2763 }; 2546 };
2764 }; 2547 };
2765 2548
2766 port@6 { 2549 port@6 {
2767 reg = 2550 reg = <6>;
2768 apss_ 2551 apss_funnel_in6: endpoint {
2769 2552 remote-endpoint = <&etm6_out>;
2770 }; 2553 };
2771 }; 2554 };
2772 2555
2773 port@7 { 2556 port@7 {
2774 reg = 2557 reg = <7>;
2775 apss_ 2558 apss_funnel_in7: endpoint {
2776 2559 remote-endpoint = <&etm7_out>;
2777 }; 2560 };
2778 }; 2561 };
2779 }; 2562 };
2780 }; 2563 };
2781 2564
2782 funnel@7810000 { 2565 funnel@7810000 {
2783 compatible = "arm,cor 2566 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2784 reg = <0 0x07810000 0 2567 reg = <0 0x07810000 0 0x1000>;
2785 2568
2786 clocks = <&aoss_qmp>; 2569 clocks = <&aoss_qmp>;
2787 clock-names = "apb_pc 2570 clock-names = "apb_pclk";
2788 2571
2789 out-ports { 2572 out-ports {
2790 port { 2573 port {
2791 apss_ 2574 apss_merge_funnel_out: endpoint {
2792 2575 remote-endpoint = <&funnel1_in4>;
2793 }; 2576 };
2794 }; 2577 };
2795 }; 2578 };
2796 2579
2797 in-ports { 2580 in-ports {
2798 port { 2581 port {
2799 apss_ 2582 apss_merge_funnel_in: endpoint {
2800 2583 remote-endpoint = <&apss_funnel_out>;
2801 }; 2584 };
2802 }; 2585 };
2803 }; 2586 };
2804 }; 2587 };
2805 2588
2806 sdhc_2: mmc@8804000 { !! 2589 sdhc_2: sdhci@8804000 {
2807 compatible = "qcom,sc 2590 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
2808 reg = <0 0x08804000 0 2591 reg = <0 0x08804000 0 0x1000>;
2809 2592
2810 iommus = <&apps_smmu 2593 iommus = <&apps_smmu 0x80 0>;
2811 interrupts = <GIC_SPI 2594 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
2812 <GIC_ 2595 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
2813 interrupt-names = "hc 2596 interrupt-names = "hc_irq", "pwr_irq";
2814 2597
2815 clocks = <&gcc GCC_SD !! 2598 clocks = <&gcc GCC_SDCC2_APPS_CLK>,
2816 <&gcc GCC_SD !! 2599 <&gcc GCC_SDCC2_AHB_CLK>,
2817 <&rpmhcc RPM 2600 <&rpmhcc RPMH_CXO_CLK>;
2818 clock-names = "iface" !! 2601 clock-names = "core", "iface", "xo";
2819 2602
2820 interconnects = <&agg 2603 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
2821 <&gem 2604 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
2822 interconnect-names = 2605 interconnect-names = "sdhc-ddr","cpu-sdhc";
2823 power-domains = <&rpm 2606 power-domains = <&rpmhpd SC7180_CX>;
2824 operating-points-v2 = 2607 operating-points-v2 = <&sdhc2_opp_table>;
2825 2608
2826 bus-width = <4>; 2609 bus-width = <4>;
2827 2610
2828 status = "disabled"; 2611 status = "disabled";
2829 2612
2830 sdhc2_opp_table: opp- !! 2613 sdhc2_opp_table: sdhc2-opp-table {
2831 compatible = 2614 compatible = "operating-points-v2";
2832 2615
2833 opp-100000000 2616 opp-100000000 {
2834 opp-h 2617 opp-hz = /bits/ 64 <100000000>;
2835 requi 2618 required-opps = <&rpmhpd_opp_low_svs>;
2836 opp-p 2619 opp-peak-kBps = <1800000 600000>;
2837 opp-a 2620 opp-avg-kBps = <100000 0>;
2838 }; 2621 };
2839 2622
2840 opp-202000000 2623 opp-202000000 {
2841 opp-h 2624 opp-hz = /bits/ 64 <202000000>;
2842 requi 2625 required-opps = <&rpmhpd_opp_nom>;
2843 opp-p 2626 opp-peak-kBps = <5400000 1600000>;
2844 opp-a 2627 opp-avg-kBps = <200000 0>;
2845 }; 2628 };
2846 }; 2629 };
2847 }; 2630 };
2848 2631
>> 2632 qspi_opp_table: qspi-opp-table {
>> 2633 compatible = "operating-points-v2";
>> 2634
>> 2635 opp-75000000 {
>> 2636 opp-hz = /bits/ 64 <75000000>;
>> 2637 required-opps = <&rpmhpd_opp_low_svs>;
>> 2638 };
>> 2639
>> 2640 opp-150000000 {
>> 2641 opp-hz = /bits/ 64 <150000000>;
>> 2642 required-opps = <&rpmhpd_opp_svs>;
>> 2643 };
>> 2644
>> 2645 opp-300000000 {
>> 2646 opp-hz = /bits/ 64 <300000000>;
>> 2647 required-opps = <&rpmhpd_opp_nom>;
>> 2648 };
>> 2649 };
>> 2650
2849 qspi: spi@88dc000 { 2651 qspi: spi@88dc000 {
2850 compatible = "qcom,sc !! 2652 compatible = "qcom,qspi-v1";
2851 reg = <0 0x088dc000 0 2653 reg = <0 0x088dc000 0 0x600>;
2852 iommus = <&apps_smmu <<
2853 #address-cells = <1>; 2654 #address-cells = <1>;
2854 #size-cells = <0>; 2655 #size-cells = <0>;
2855 interrupts = <GIC_SPI 2656 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
2856 clocks = <&gcc GCC_QS 2657 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
2857 <&gcc GCC_QS 2658 <&gcc GCC_QSPI_CORE_CLK>;
2858 clock-names = "iface" 2659 clock-names = "iface", "core";
2859 interconnects = <&gem 2660 interconnects = <&gem_noc MASTER_APPSS_PROC 0
2860 &conf 2661 &config_noc SLAVE_QSPI_0 0>;
2861 interconnect-names = 2662 interconnect-names = "qspi-config";
2862 power-domains = <&rpm 2663 power-domains = <&rpmhpd SC7180_CX>;
2863 operating-points-v2 = 2664 operating-points-v2 = <&qspi_opp_table>;
2864 status = "disabled"; 2665 status = "disabled";
2865 }; 2666 };
2866 2667
2867 usb_1_hsphy: phy@88e3000 { 2668 usb_1_hsphy: phy@88e3000 {
2868 compatible = "qcom,sc 2669 compatible = "qcom,sc7180-qusb2-phy", "qcom,qusb2-v2-phy";
2869 reg = <0 0x088e3000 0 2670 reg = <0 0x088e3000 0 0x400>;
2870 status = "disabled"; 2671 status = "disabled";
2871 #phy-cells = <0>; 2672 #phy-cells = <0>;
2872 clocks = <&gcc GCC_US 2673 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2873 <&rpmhcc RPM 2674 <&rpmhcc RPMH_CXO_CLK>;
2874 clock-names = "cfg_ah 2675 clock-names = "cfg_ahb", "ref";
2875 resets = <&gcc GCC_QU 2676 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2876 2677
2877 nvmem-cells = <&qusb2 2678 nvmem-cells = <&qusb2p_hstx_trim>;
2878 }; 2679 };
2879 2680
2880 usb_1_qmpphy: phy@88e8000 { !! 2681 usb_1_qmpphy: phy-wrapper@88e9000 {
2881 compatible = "qcom,sc 2682 compatible = "qcom,sc7180-qmp-usb3-dp-phy";
2882 reg = <0 0x088e8000 0 !! 2683 reg = <0 0x088e9000 0 0x18c>,
>> 2684 <0 0x088e8000 0 0x3c>,
>> 2685 <0 0x088ea000 0 0x18c>;
2883 status = "disabled"; 2686 status = "disabled";
>> 2687 #address-cells = <2>;
>> 2688 #size-cells = <2>;
>> 2689 ranges;
2884 2690
2885 clocks = <&gcc GCC_US 2691 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
>> 2692 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2886 <&gcc GCC_US 2693 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
2887 <&gcc GCC_US !! 2694 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
2888 <&gcc GCC_US !! 2695 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
2889 <&gcc GCC_US <<
2890 clock-names = "aux", <<
2891 "ref", <<
2892 "com_au <<
2893 "usb3_p <<
2894 "cfg_ah <<
2895 2696
2896 resets = <&gcc GCC_US 2697 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
2897 <&gcc GCC_US 2698 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
2898 reset-names = "phy", 2699 reset-names = "phy", "common";
2899 2700
2900 #clock-cells = <1>; !! 2701 usb_1_ssphy: usb3-phy@88e9200 {
2901 #phy-cells = <1>; !! 2702 reg = <0 0x088e9200 0 0x128>,
2902 }; !! 2703 <0 0x088e9400 0 0x200>,
2903 !! 2704 <0 0x088e9c00 0 0x218>,
2904 pmu@90b6300 { !! 2705 <0 0x088e9600 0 0x128>,
2905 compatible = "qcom,sc !! 2706 <0 0x088e9800 0 0x200>,
2906 reg = <0 0x090b6300 0 !! 2707 <0 0x088e9a00 0 0x18>;
2907 interrupts = <GIC_SPI !! 2708 #clock-cells = <0>;
2908 !! 2709 #phy-cells = <0>;
2909 interconnects = <&gem !! 2710 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2910 &gem !! 2711 clock-names = "pipe0";
2911 operating-points-v2 = !! 2712 clock-output-names = "usb3_phy_pipe_clk_src";
2912 <<
2913 cpu_bwmon_opp_table: <<
2914 compatible = <<
2915 <<
2916 opp-0 { <<
2917 opp-p <<
2918 }; <<
2919 <<
2920 opp-1 { <<
2921 opp-p <<
2922 }; <<
2923 <<
2924 opp-2 { <<
2925 opp-p <<
2926 }; <<
2927 <<
2928 opp-3 { <<
2929 opp-p <<
2930 }; <<
2931 <<
2932 opp-4 { <<
2933 opp-p <<
2934 }; <<
2935 <<
2936 opp-5 { <<
2937 opp-p <<
2938 }; <<
2939 }; 2713 };
2940 }; <<
2941 <<
2942 pmu@90cd000 { <<
2943 compatible = "qcom,sc <<
2944 reg = <0 0x090cd000 0 <<
2945 interrupts = <GIC_SPI <<
2946 2714
2947 interconnects = <&mc_ !! 2715 dp_phy: dp-phy@88ea200 {
2948 &mc_ !! 2716 reg = <0 0x088ea200 0 0x200>,
2949 operating-points-v2 = !! 2717 <0 0x088ea400 0 0x200>,
2950 !! 2718 <0 0x088eaa00 0 0x200>,
2951 llcc_bwmon_opp_table: !! 2719 <0 0x088ea600 0 0x200>,
2952 compatible = !! 2720 <0 0x088ea800 0 0x200>;
2953 !! 2721 #clock-cells = <1>;
2954 opp-0 { !! 2722 #phy-cells = <0>;
2955 opp-p <<
2956 }; <<
2957 <<
2958 opp-1 { <<
2959 opp-p <<
2960 }; <<
2961 <<
2962 opp-2 { <<
2963 opp-p <<
2964 }; <<
2965 <<
2966 opp-3 { <<
2967 opp-p <<
2968 }; <<
2969 <<
2970 opp-4 { <<
2971 opp-p <<
2972 }; <<
2973 <<
2974 opp-5 { <<
2975 opp-p <<
2976 }; <<
2977 <<
2978 opp-6 { <<
2979 opp-p <<
2980 }; <<
2981 <<
2982 opp-7 { <<
2983 opp-p <<
2984 }; <<
2985 }; 2723 };
2986 }; 2724 };
2987 2725
2988 dc_noc: interconnect@9160000 2726 dc_noc: interconnect@9160000 {
2989 compatible = "qcom,sc 2727 compatible = "qcom,sc7180-dc-noc";
2990 reg = <0 0x09160000 0 2728 reg = <0 0x09160000 0 0x03200>;
2991 #interconnect-cells = 2729 #interconnect-cells = <2>;
2992 qcom,bcm-voters = <&a 2730 qcom,bcm-voters = <&apps_bcm_voter>;
2993 }; 2731 };
2994 2732
2995 system-cache-controller@92000 2733 system-cache-controller@9200000 {
2996 compatible = "qcom,sc 2734 compatible = "qcom,sc7180-llcc";
2997 reg = <0 0x09200000 0 2735 reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>;
2998 reg-names = "llcc0_ba !! 2736 reg-names = "llcc_base", "llcc_broadcast_base";
2999 interrupts = <GIC_SPI 2737 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
3000 }; 2738 };
3001 2739
3002 gem_noc: interconnect@9680000 2740 gem_noc: interconnect@9680000 {
3003 compatible = "qcom,sc 2741 compatible = "qcom,sc7180-gem-noc";
3004 reg = <0 0x09680000 0 2742 reg = <0 0x09680000 0 0x3e200>;
3005 #interconnect-cells = 2743 #interconnect-cells = <2>;
3006 qcom,bcm-voters = <&a 2744 qcom,bcm-voters = <&apps_bcm_voter>;
3007 }; 2745 };
3008 2746
3009 npu_noc: interconnect@9990000 2747 npu_noc: interconnect@9990000 {
3010 compatible = "qcom,sc 2748 compatible = "qcom,sc7180-npu-noc";
3011 reg = <0 0x09990000 0 2749 reg = <0 0x09990000 0 0x1600>;
3012 #interconnect-cells = 2750 #interconnect-cells = <2>;
3013 qcom,bcm-voters = <&a 2751 qcom,bcm-voters = <&apps_bcm_voter>;
3014 }; 2752 };
3015 2753
3016 usb_1: usb@a6f8800 { 2754 usb_1: usb@a6f8800 {
3017 compatible = "qcom,sc 2755 compatible = "qcom,sc7180-dwc3", "qcom,dwc3";
3018 reg = <0 0x0a6f8800 0 2756 reg = <0 0x0a6f8800 0 0x400>;
3019 status = "disabled"; 2757 status = "disabled";
3020 #address-cells = <2>; 2758 #address-cells = <2>;
3021 #size-cells = <2>; 2759 #size-cells = <2>;
3022 ranges; 2760 ranges;
3023 dma-ranges; 2761 dma-ranges;
3024 2762
3025 clocks = <&gcc GCC_CF 2763 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
3026 <&gcc GCC_US 2764 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
3027 <&gcc GCC_AG 2765 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
3028 <&gcc GCC_US !! 2766 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3029 <&gcc GCC_US !! 2767 <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
3030 clock-names = "cfg_no !! 2768 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
3031 "core", !! 2769 "sleep";
3032 "iface" <<
3033 "sleep" <<
3034 "mock_u <<
3035 2770
3036 assigned-clocks = <&g 2771 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3037 <&g 2772 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
3038 assigned-clock-rates 2773 assigned-clock-rates = <19200000>, <150000000>;
3039 2774
3040 interrupts-extended = !! 2775 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
3041 !! 2776 <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
3042 <<
3043 2777 <&pdc 8 IRQ_TYPE_EDGE_BOTH>,
3044 !! 2778 <&pdc 9 IRQ_TYPE_EDGE_BOTH>;
3045 interrupt-names = "pw !! 2779 interrupt-names = "hs_phy_irq", "ss_phy_irq",
3046 "hs !! 2780 "dm_hs_phy_irq", "dp_hs_phy_irq";
3047 "dp <<
3048 "dm <<
3049 "ss <<
3050 2781
3051 power-domains = <&gcc 2782 power-domains = <&gcc USB30_PRIM_GDSC>;
3052 required-opps = <&rpm <<
3053 2783
3054 resets = <&gcc GCC_US 2784 resets = <&gcc GCC_USB30_PRIM_BCR>;
3055 2785
3056 interconnects = <&agg 2786 interconnects = <&aggre2_noc MASTER_USB3 0 &mc_virt SLAVE_EBI1 0>,
3057 <&gem 2787 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3 0>;
3058 interconnect-names = 2788 interconnect-names = "usb-ddr", "apps-usb";
3059 2789
3060 wakeup-source; !! 2790 usb_1_dwc3: dwc3@a600000 {
3061 <<
3062 usb_1_dwc3: usb@a6000 <<
3063 compatible = 2791 compatible = "snps,dwc3";
3064 reg = <0 0x0a 2792 reg = <0 0x0a600000 0 0xe000>;
3065 interrupts = 2793 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
3066 iommus = <&ap 2794 iommus = <&apps_smmu 0x540 0>;
3067 snps,dis_u2_s 2795 snps,dis_u2_susphy_quirk;
3068 snps,dis_enbl 2796 snps,dis_enblslpm_quirk;
3069 snps,parkmode !! 2797 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
3070 phys = <&usb_ <<
3071 phy-names = " 2798 phy-names = "usb2-phy", "usb3-phy";
3072 maximum-speed 2799 maximum-speed = "super-speed";
3073 }; 2800 };
3074 }; 2801 };
3075 2802
3076 venus: video-codec@aa00000 { 2803 venus: video-codec@aa00000 {
3077 compatible = "qcom,sc 2804 compatible = "qcom,sc7180-venus";
3078 reg = <0 0x0aa00000 0 2805 reg = <0 0x0aa00000 0 0xff000>;
3079 interrupts = <GIC_SPI 2806 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
3080 power-domains = <&vid 2807 power-domains = <&videocc VENUS_GDSC>,
3081 <&vid 2808 <&videocc VCODEC0_GDSC>,
3082 <&rpm 2809 <&rpmhpd SC7180_CX>;
3083 power-domain-names = 2810 power-domain-names = "venus", "vcodec0", "cx";
3084 operating-points-v2 = 2811 operating-points-v2 = <&venus_opp_table>;
3085 clocks = <&videocc VI 2812 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
3086 <&videocc VI 2813 <&videocc VIDEO_CC_VENUS_AHB_CLK>,
3087 <&videocc VI 2814 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>,
3088 <&videocc VI 2815 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
3089 <&videocc VI 2816 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>;
3090 clock-names = "core", 2817 clock-names = "core", "iface", "bus",
3091 "vcodec 2818 "vcodec0_core", "vcodec0_bus";
3092 iommus = <&apps_smmu 2819 iommus = <&apps_smmu 0x0c00 0x60>;
3093 memory-region = <&ven 2820 memory-region = <&venus_mem>;
3094 interconnects = <&mms 2821 interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>,
3095 <&gem 2822 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>;
3096 interconnect-names = 2823 interconnect-names = "video-mem", "cpu-cfg";
3097 2824
3098 video-decoder { 2825 video-decoder {
3099 compatible = 2826 compatible = "venus-decoder";
3100 }; 2827 };
3101 2828
3102 video-encoder { 2829 video-encoder {
3103 compatible = 2830 compatible = "venus-encoder";
3104 }; 2831 };
3105 2832
3106 venus_opp_table: opp- !! 2833 venus_opp_table: venus-opp-table {
3107 compatible = 2834 compatible = "operating-points-v2";
3108 2835
3109 opp-150000000 2836 opp-150000000 {
3110 opp-h 2837 opp-hz = /bits/ 64 <150000000>;
3111 requi 2838 required-opps = <&rpmhpd_opp_low_svs>;
3112 }; 2839 };
3113 2840
3114 opp-270000000 2841 opp-270000000 {
3115 opp-h 2842 opp-hz = /bits/ 64 <270000000>;
3116 requi 2843 required-opps = <&rpmhpd_opp_svs>;
3117 }; 2844 };
3118 2845
3119 opp-340000000 2846 opp-340000000 {
3120 opp-h 2847 opp-hz = /bits/ 64 <340000000>;
3121 requi 2848 required-opps = <&rpmhpd_opp_svs_l1>;
3122 }; 2849 };
3123 2850
3124 opp-434000000 2851 opp-434000000 {
3125 opp-h 2852 opp-hz = /bits/ 64 <434000000>;
3126 requi 2853 required-opps = <&rpmhpd_opp_nom>;
3127 }; 2854 };
3128 2855
3129 opp-500000097 2856 opp-500000097 {
3130 opp-h 2857 opp-hz = /bits/ 64 <500000097>;
3131 requi 2858 required-opps = <&rpmhpd_opp_turbo>;
3132 }; 2859 };
3133 }; 2860 };
3134 }; 2861 };
3135 2862
3136 videocc: clock-controller@ab0 2863 videocc: clock-controller@ab00000 {
3137 compatible = "qcom,sc 2864 compatible = "qcom,sc7180-videocc";
3138 reg = <0 0x0ab00000 0 2865 reg = <0 0x0ab00000 0 0x10000>;
3139 clocks = <&rpmhcc RPM 2866 clocks = <&rpmhcc RPMH_CXO_CLK>;
3140 clock-names = "bi_tcx 2867 clock-names = "bi_tcxo";
3141 #clock-cells = <1>; 2868 #clock-cells = <1>;
3142 #reset-cells = <1>; 2869 #reset-cells = <1>;
3143 #power-domain-cells = 2870 #power-domain-cells = <1>;
3144 }; 2871 };
3145 2872
3146 camnoc_virt: interconnect@ac0 2873 camnoc_virt: interconnect@ac00000 {
3147 compatible = "qcom,sc 2874 compatible = "qcom,sc7180-camnoc-virt";
3148 reg = <0 0x0ac00000 0 2875 reg = <0 0x0ac00000 0 0x1000>;
3149 #interconnect-cells = 2876 #interconnect-cells = <2>;
3150 qcom,bcm-voters = <&a 2877 qcom,bcm-voters = <&apps_bcm_voter>;
3151 }; 2878 };
3152 2879
3153 camcc: clock-controller@ad000 2880 camcc: clock-controller@ad00000 {
3154 compatible = "qcom,sc 2881 compatible = "qcom,sc7180-camcc";
3155 reg = <0 0x0ad00000 0 2882 reg = <0 0x0ad00000 0 0x10000>;
3156 clocks = <&rpmhcc RPM 2883 clocks = <&rpmhcc RPMH_CXO_CLK>,
3157 <&gcc GCC_CAME 2884 <&gcc GCC_CAMERA_AHB_CLK>,
3158 <&gcc GCC_CAME 2885 <&gcc GCC_CAMERA_XO_CLK>;
3159 clock-names = "bi_tcx 2886 clock-names = "bi_tcxo", "iface", "xo";
3160 #clock-cells = <1>; 2887 #clock-cells = <1>;
3161 #reset-cells = <1>; 2888 #reset-cells = <1>;
3162 #power-domain-cells = 2889 #power-domain-cells = <1>;
3163 }; 2890 };
3164 2891
3165 mdss: display-subsystem@ae000 !! 2892 mdss: mdss@ae00000 {
3166 compatible = "qcom,sc 2893 compatible = "qcom,sc7180-mdss";
3167 reg = <0 0x0ae00000 0 2894 reg = <0 0x0ae00000 0 0x1000>;
3168 reg-names = "mdss"; 2895 reg-names = "mdss";
3169 2896
3170 power-domains = <&dis 2897 power-domains = <&dispcc MDSS_GDSC>;
3171 2898
3172 clocks = <&gcc GCC_DI 2899 clocks = <&gcc GCC_DISP_AHB_CLK>,
3173 <&dispcc DIS 2900 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3174 <&dispcc DIS 2901 <&dispcc DISP_CC_MDSS_MDP_CLK>;
3175 clock-names = "iface" 2902 clock-names = "iface", "ahb", "core";
3176 2903
>> 2904 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
>> 2905 assigned-clock-rates = <300000000>;
>> 2906
3177 interrupts = <GIC_SPI 2907 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
3178 interrupt-controller; 2908 interrupt-controller;
3179 #interrupt-cells = <1 2909 #interrupt-cells = <1>;
3180 2910
3181 interconnects = <&mms !! 2911 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>;
3182 &mc_ !! 2912 interconnect-names = "mdp0-mem";
3183 <&gem <<
3184 &con <<
3185 interconnect-names = <<
3186 <<
3187 2913
3188 iommus = <&apps_smmu 2914 iommus = <&apps_smmu 0x800 0x2>;
3189 2915
3190 #address-cells = <2>; 2916 #address-cells = <2>;
3191 #size-cells = <2>; 2917 #size-cells = <2>;
3192 ranges; 2918 ranges;
3193 2919
3194 status = "disabled"; 2920 status = "disabled";
3195 2921
3196 mdp: display-controll !! 2922 mdp: mdp@ae01000 {
3197 compatible = 2923 compatible = "qcom,sc7180-dpu";
3198 reg = <0 0x0a 2924 reg = <0 0x0ae01000 0 0x8f000>,
3199 <0 0x0a 2925 <0 0x0aeb0000 0 0x2008>;
3200 reg-names = " 2926 reg-names = "mdp", "vbif";
3201 2927
3202 clocks = <&gc 2928 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
3203 <&di 2929 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3204 <&di 2930 <&dispcc DISP_CC_MDSS_ROT_CLK>,
3205 <&di 2931 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
3206 <&di 2932 <&dispcc DISP_CC_MDSS_MDP_CLK>,
3207 <&di 2933 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3208 clock-names = 2934 clock-names = "bus", "iface", "rot", "lut", "core",
3209 2935 "vsync";
3210 assigned-cloc !! 2936 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
>> 2937 <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
3211 2938 <&dispcc DISP_CC_MDSS_ROT_CLK>,
3212 2939 <&dispcc DISP_CC_MDSS_AHB_CLK>;
3213 assigned-cloc !! 2940 assigned-clock-rates = <300000000>,
>> 2941 <19200000>,
3214 2942 <19200000>,
3215 2943 <19200000>;
3216 operating-poi 2944 operating-points-v2 = <&mdp_opp_table>;
3217 power-domains 2945 power-domains = <&rpmhpd SC7180_CX>;
3218 2946
3219 interrupt-par 2947 interrupt-parent = <&mdss>;
3220 interrupts = 2948 interrupts = <0>;
3221 2949
>> 2950 status = "disabled";
>> 2951
3222 ports { 2952 ports {
3223 #addr 2953 #address-cells = <1>;
3224 #size 2954 #size-cells = <0>;
3225 2955
3226 port@ 2956 port@0 {
3227 2957 reg = <0>;
3228 2958 dpu_intf1_out: endpoint {
3229 !! 2959 remote-endpoint = <&dsi0_in>;
3230 2960 };
3231 }; 2961 };
3232 2962
3233 port@ 2963 port@2 {
3234 2964 reg = <2>;
3235 2965 dpu_intf0_out: endpoint {
3236 2966 remote-endpoint = <&dp_in>;
3237 2967 };
3238 }; 2968 };
3239 }; 2969 };
3240 2970
3241 mdp_opp_table !! 2971 mdp_opp_table: mdp-opp-table {
3242 compa 2972 compatible = "operating-points-v2";
3243 2973
3244 opp-2 2974 opp-200000000 {
3245 2975 opp-hz = /bits/ 64 <200000000>;
3246 2976 required-opps = <&rpmhpd_opp_low_svs>;
3247 }; 2977 };
3248 2978
3249 opp-3 2979 opp-300000000 {
3250 2980 opp-hz = /bits/ 64 <300000000>;
3251 2981 required-opps = <&rpmhpd_opp_svs>;
3252 }; 2982 };
3253 2983
3254 opp-3 2984 opp-345000000 {
3255 2985 opp-hz = /bits/ 64 <345000000>;
3256 2986 required-opps = <&rpmhpd_opp_svs_l1>;
3257 }; 2987 };
3258 2988
3259 opp-4 2989 opp-460000000 {
3260 2990 opp-hz = /bits/ 64 <460000000>;
3261 2991 required-opps = <&rpmhpd_opp_nom>;
3262 }; 2992 };
3263 }; 2993 };
>> 2994
3264 }; 2995 };
3265 2996
3266 mdss_dsi0: dsi@ae9400 !! 2997 dsi0: dsi@ae94000 {
3267 compatible = !! 2998 compatible = "qcom,mdss-dsi-ctrl";
3268 <<
3269 reg = <0 0x0a 2999 reg = <0 0x0ae94000 0 0x400>;
3270 reg-names = " 3000 reg-names = "dsi_ctrl";
3271 3001
3272 interrupt-par 3002 interrupt-parent = <&mdss>;
3273 interrupts = 3003 interrupts = <4>;
3274 3004
3275 clocks = <&di 3005 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
3276 <&di 3006 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
3277 <&di 3007 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
3278 <&di 3008 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
3279 <&di 3009 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3280 <&gc 3010 <&gcc GCC_DISP_HF_AXI_CLK>;
3281 clock-names = 3011 clock-names = "byte",
3282 3012 "byte_intf",
3283 3013 "pixel",
3284 3014 "core",
3285 3015 "iface",
3286 3016 "bus";
3287 3017
3288 assigned-cloc 3018 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
3289 assigned-cloc !! 3019 assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>;
3290 3020
3291 operating-poi 3021 operating-points-v2 = <&dsi_opp_table>;
3292 power-domains 3022 power-domains = <&rpmhpd SC7180_CX>;
3293 3023
3294 phys = <&mdss !! 3024 phys = <&dsi_phy>;
>> 3025 phy-names = "dsi";
3295 3026
3296 #address-cell 3027 #address-cells = <1>;
3297 #size-cells = 3028 #size-cells = <0>;
3298 3029
3299 status = "dis 3030 status = "disabled";
3300 3031
3301 ports { 3032 ports {
3302 #addr 3033 #address-cells = <1>;
3303 #size 3034 #size-cells = <0>;
3304 3035
3305 port@ 3036 port@0 {
3306 3037 reg = <0>;
3307 !! 3038 dsi0_in: endpoint {
3308 3039 remote-endpoint = <&dpu_intf1_out>;
3309 3040 };
3310 }; 3041 };
3311 3042
3312 port@ 3043 port@1 {
3313 3044 reg = <1>;
3314 !! 3045 dsi0_out: endpoint {
3315 3046 };
3316 }; 3047 };
3317 }; 3048 };
3318 3049
3319 dsi_opp_table !! 3050 dsi_opp_table: dsi-opp-table {
3320 compa 3051 compatible = "operating-points-v2";
3321 3052
3322 opp-1 3053 opp-187500000 {
3323 3054 opp-hz = /bits/ 64 <187500000>;
3324 3055 required-opps = <&rpmhpd_opp_low_svs>;
3325 }; 3056 };
3326 3057
3327 opp-3 3058 opp-300000000 {
3328 3059 opp-hz = /bits/ 64 <300000000>;
3329 3060 required-opps = <&rpmhpd_opp_svs>;
3330 }; 3061 };
3331 3062
3332 opp-3 3063 opp-358000000 {
3333 3064 opp-hz = /bits/ 64 <358000000>;
3334 3065 required-opps = <&rpmhpd_opp_svs_l1>;
3335 }; 3066 };
3336 }; 3067 };
3337 }; 3068 };
3338 3069
3339 mdss_dsi0_phy: phy@ae !! 3070 dsi_phy: dsi-phy@ae94400 {
3340 compatible = 3071 compatible = "qcom,dsi-phy-10nm";
3341 reg = <0 0x0a 3072 reg = <0 0x0ae94400 0 0x200>,
3342 <0 0x0a 3073 <0 0x0ae94600 0 0x280>,
3343 <0 0x0a 3074 <0 0x0ae94a00 0 0x1e0>;
3344 reg-names = " 3075 reg-names = "dsi_phy",
3345 " 3076 "dsi_phy_lane",
3346 " 3077 "dsi_pll";
3347 3078
3348 #clock-cells 3079 #clock-cells = <1>;
3349 #phy-cells = 3080 #phy-cells = <0>;
3350 3081
3351 clocks = <&di 3082 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3352 <&rp 3083 <&rpmhcc RPMH_CXO_CLK>;
3353 clock-names = 3084 clock-names = "iface", "ref";
3354 3085
3355 status = "dis 3086 status = "disabled";
3356 }; 3087 };
3357 3088
3358 mdss_dp: displayport- 3089 mdss_dp: displayport-controller@ae90000 {
3359 compatible = 3090 compatible = "qcom,sc7180-dp";
3360 status = "dis 3091 status = "disabled";
3361 3092
3362 reg = <0 0x0a !! 3093 reg = <0 0x0ae90000 0 0x1400>;
3363 <0 0x0a <<
3364 <0 0x0a <<
3365 <0 0x0a <<
3366 <0 0x0a <<
3367 3094
3368 interrupt-par 3095 interrupt-parent = <&mdss>;
3369 interrupts = 3096 interrupts = <12>;
3370 3097
3371 clocks = <&di 3098 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3372 <&di 3099 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
3373 <&di 3100 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
3374 <&di 3101 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
3375 <&di 3102 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
3376 clock-names = 3103 clock-names = "core_iface", "core_aux", "ctrl_link",
3377 3104 "ctrl_link_iface", "stream_pixel";
>> 3105 #clock-cells = <1>;
3378 assigned-cloc 3106 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
3379 3107 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
3380 assigned-cloc !! 3108 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
3381 !! 3109 phys = <&dp_phy>;
3382 phys = <&usb_ <<
3383 phy-names = " 3110 phy-names = "dp";
3384 3111
3385 operating-poi 3112 operating-points-v2 = <&dp_opp_table>;
3386 power-domains 3113 power-domains = <&rpmhpd SC7180_CX>;
3387 3114
3388 #sound-dai-ce 3115 #sound-dai-cells = <0>;
3389 3116
3390 ports { 3117 ports {
3391 #addr 3118 #address-cells = <1>;
3392 #size 3119 #size-cells = <0>;
3393 port@ 3120 port@0 {
3394 3121 reg = <0>;
3395 3122 dp_in: endpoint {
3396 3123 remote-endpoint = <&dpu_intf0_out>;
3397 3124 };
3398 }; 3125 };
3399 3126
3400 port@ 3127 port@1 {
3401 3128 reg = <1>;
3402 !! 3129 dp_out: endpoint { };
3403 }; 3130 };
3404 }; 3131 };
3405 3132
3406 dp_opp_table: 3133 dp_opp_table: opp-table {
3407 compa 3134 compatible = "operating-points-v2";
3408 3135
3409 opp-1 3136 opp-160000000 {
3410 3137 opp-hz = /bits/ 64 <160000000>;
3411 3138 required-opps = <&rpmhpd_opp_low_svs>;
3412 }; 3139 };
3413 3140
3414 opp-2 3141 opp-270000000 {
3415 3142 opp-hz = /bits/ 64 <270000000>;
3416 3143 required-opps = <&rpmhpd_opp_svs>;
3417 }; 3144 };
3418 3145
3419 opp-5 3146 opp-540000000 {
3420 3147 opp-hz = /bits/ 64 <540000000>;
3421 3148 required-opps = <&rpmhpd_opp_svs_l1>;
3422 }; 3149 };
3423 3150
3424 opp-8 3151 opp-810000000 {
3425 3152 opp-hz = /bits/ 64 <810000000>;
3426 3153 required-opps = <&rpmhpd_opp_nom>;
3427 }; 3154 };
3428 }; 3155 };
3429 }; 3156 };
3430 }; 3157 };
3431 3158
3432 dispcc: clock-controller@af00 3159 dispcc: clock-controller@af00000 {
3433 compatible = "qcom,sc 3160 compatible = "qcom,sc7180-dispcc";
3434 reg = <0 0x0af00000 0 3161 reg = <0 0x0af00000 0 0x200000>;
3435 clocks = <&rpmhcc RPM 3162 clocks = <&rpmhcc RPMH_CXO_CLK>,
3436 <&gcc GCC_DI 3163 <&gcc GCC_DISP_GPLL0_CLK_SRC>,
3437 <&mdss_dsi0_ !! 3164 <&dsi_phy 0>,
3438 <&mdss_dsi0_ !! 3165 <&dsi_phy 1>,
3439 <&usb_1_qmpp !! 3166 <&dp_phy 0>,
3440 <&usb_1_qmpp !! 3167 <&dp_phy 1>;
3441 clock-names = "bi_tcx 3168 clock-names = "bi_tcxo",
3442 "gcc_di 3169 "gcc_disp_gpll0_clk_src",
3443 "dsi0_p 3170 "dsi0_phy_pll_out_byteclk",
3444 "dsi0_p 3171 "dsi0_phy_pll_out_dsiclk",
3445 "dp_phy 3172 "dp_phy_pll_link_clk",
3446 "dp_phy 3173 "dp_phy_pll_vco_div_clk";
3447 #clock-cells = <1>; 3174 #clock-cells = <1>;
3448 #reset-cells = <1>; 3175 #reset-cells = <1>;
3449 #power-domain-cells = 3176 #power-domain-cells = <1>;
3450 }; 3177 };
3451 3178
3452 pdc: interrupt-controller@b22 3179 pdc: interrupt-controller@b220000 {
3453 compatible = "qcom,sc 3180 compatible = "qcom,sc7180-pdc", "qcom,pdc";
3454 reg = <0 0x0b220000 0 3181 reg = <0 0x0b220000 0 0x30000>;
3455 qcom,pdc-ranges = <0 3182 qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>;
3456 #interrupt-cells = <2 3183 #interrupt-cells = <2>;
3457 interrupt-parent = <& 3184 interrupt-parent = <&intc>;
3458 interrupt-controller; 3185 interrupt-controller;
3459 }; 3186 };
3460 3187
3461 pdc_reset: reset-controller@b 3188 pdc_reset: reset-controller@b2e0000 {
3462 compatible = "qcom,sc 3189 compatible = "qcom,sc7180-pdc-global", "qcom,sdm845-pdc-global";
3463 reg = <0 0x0b2e0000 0 3190 reg = <0 0x0b2e0000 0 0x20000>;
3464 #reset-cells = <1>; 3191 #reset-cells = <1>;
3465 }; 3192 };
3466 3193
3467 tsens0: thermal-sensor@c26300 3194 tsens0: thermal-sensor@c263000 {
3468 compatible = "qcom,sc 3195 compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
3469 reg = <0 0x0c263000 0 3196 reg = <0 0x0c263000 0 0x1ff>, /* TM */
3470 <0 0x0c222000 3197 <0 0x0c222000 0 0x1ff>; /* SROT */
3471 #qcom,sensors = <15>; 3198 #qcom,sensors = <15>;
3472 interrupts = <GIC_SPI 3199 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
3473 <GIC_SPI 3200 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
3474 interrupt-names = "up 3201 interrupt-names = "uplow","critical";
3475 #thermal-sensor-cells 3202 #thermal-sensor-cells = <1>;
3476 }; 3203 };
3477 3204
3478 tsens1: thermal-sensor@c26500 3205 tsens1: thermal-sensor@c265000 {
3479 compatible = "qcom,sc 3206 compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
3480 reg = <0 0x0c265000 0 3207 reg = <0 0x0c265000 0 0x1ff>, /* TM */
3481 <0 0x0c223000 3208 <0 0x0c223000 0 0x1ff>; /* SROT */
3482 #qcom,sensors = <10>; 3209 #qcom,sensors = <10>;
3483 interrupts = <GIC_SPI 3210 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
3484 <GIC_SPI 3211 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
3485 interrupt-names = "up 3212 interrupt-names = "uplow","critical";
3486 #thermal-sensor-cells 3213 #thermal-sensor-cells = <1>;
3487 }; 3214 };
3488 3215
3489 aoss_reset: reset-controller@ 3216 aoss_reset: reset-controller@c2a0000 {
3490 compatible = "qcom,sc 3217 compatible = "qcom,sc7180-aoss-cc", "qcom,sdm845-aoss-cc";
3491 reg = <0 0x0c2a0000 0 3218 reg = <0 0x0c2a0000 0 0x31000>;
3492 #reset-cells = <1>; 3219 #reset-cells = <1>;
3493 }; 3220 };
3494 3221
3495 aoss_qmp: power-management@c3 !! 3222 aoss_qmp: power-controller@c300000 {
3496 compatible = "qcom,sc !! 3223 compatible = "qcom,sc7180-aoss-qmp";
3497 reg = <0 0x0c300000 0 !! 3224 reg = <0 0x0c300000 0 0x100000>;
3498 interrupts = <GIC_SPI 3225 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
3499 mboxes = <&apss_share 3226 mboxes = <&apss_shared 0>;
3500 3227
3501 #clock-cells = <0>; 3228 #clock-cells = <0>;
3502 }; !! 3229 #power-domain-cells = <1>;
3503 <<
3504 sram@c3f0000 { <<
3505 compatible = "qcom,rp <<
3506 reg = <0 0x0c3f0000 0 <<
3507 }; 3230 };
3508 3231
3509 spmi_bus: spmi@c440000 { 3232 spmi_bus: spmi@c440000 {
3510 compatible = "qcom,sp 3233 compatible = "qcom,spmi-pmic-arb";
3511 reg = <0 0x0c440000 0 3234 reg = <0 0x0c440000 0 0x1100>,
3512 <0 0x0c600000 0 3235 <0 0x0c600000 0 0x2000000>,
3513 <0 0x0e600000 0 3236 <0 0x0e600000 0 0x100000>,
3514 <0 0x0e700000 0 3237 <0 0x0e700000 0 0xa0000>,
3515 <0 0x0c40a000 0 3238 <0 0x0c40a000 0 0x26000>;
3516 reg-names = "core", " 3239 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3517 interrupt-names = "pe 3240 interrupt-names = "periph_irq";
3518 interrupts-extended = 3241 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3519 qcom,ee = <0>; 3242 qcom,ee = <0>;
3520 qcom,channel = <0>; 3243 qcom,channel = <0>;
3521 #address-cells = <2>; 3244 #address-cells = <2>;
3522 #size-cells = <0>; 3245 #size-cells = <0>;
3523 interrupt-controller; 3246 interrupt-controller;
3524 #interrupt-cells = <4 3247 #interrupt-cells = <4>;
3525 }; !! 3248 cell-index = <0>;
3526 <<
3527 sram@146aa000 { <<
3528 compatible = "qcom,sc <<
3529 reg = <0 0x146aa000 0 <<
3530 <<
3531 #address-cells = <1>; <<
3532 #size-cells = <1>; <<
3533 <<
3534 ranges = <0 0 0x146aa <<
3535 <<
3536 pil-reloc@94c { <<
3537 compatible = <<
3538 reg = <0x94c <<
3539 }; <<
3540 }; 3249 };
3541 3250
3542 apps_smmu: iommu@15000000 { 3251 apps_smmu: iommu@15000000 {
3543 compatible = "qcom,sc 3252 compatible = "qcom,sc7180-smmu-500", "arm,mmu-500";
3544 reg = <0 0x15000000 0 3253 reg = <0 0x15000000 0 0x100000>;
3545 #iommu-cells = <2>; 3254 #iommu-cells = <2>;
3546 #global-interrupts = 3255 #global-interrupts = <1>;
3547 interrupts = <GIC_SPI 3256 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
3548 <GIC_SPI 3257 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
3549 <GIC_SPI 3258 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
3550 <GIC_SPI 3259 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
3551 <GIC_SPI 3260 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
3552 <GIC_SPI 3261 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
3553 <GIC_SPI 3262 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
3554 <GIC_SPI 3263 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
3555 <GIC_SPI 3264 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
3556 <GIC_SPI 3265 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
3557 <GIC_SPI 3266 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
3558 <GIC_SPI 3267 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
3559 <GIC_SPI 3268 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
3560 <GIC_SPI 3269 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
3561 <GIC_SPI 3270 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
3562 <GIC_SPI 3271 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
3563 <GIC_SPI 3272 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
3564 <GIC_SPI 3273 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
3565 <GIC_SPI 3274 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
3566 <GIC_SPI 3275 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
3567 <GIC_SPI 3276 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
3568 <GIC_SPI 3277 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
3569 <GIC_SPI 3278 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
3570 <GIC_SPI 3279 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
3571 <GIC_SPI 3280 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
3572 <GIC_SPI 3281 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
3573 <GIC_SPI 3282 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
3574 <GIC_SPI 3283 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
3575 <GIC_SPI 3284 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
3576 <GIC_SPI 3285 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
3577 <GIC_SPI 3286 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
3578 <GIC_SPI 3287 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
3579 <GIC_SPI 3288 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
3580 <GIC_SPI 3289 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
3581 <GIC_SPI 3290 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
3582 <GIC_SPI 3291 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
3583 <GIC_SPI 3292 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
3584 <GIC_SPI 3293 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
3585 <GIC_SPI 3294 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
3586 <GIC_SPI 3295 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
3587 <GIC_SPI 3296 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
3588 <GIC_SPI 3297 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
3589 <GIC_SPI 3298 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
3590 <GIC_SPI 3299 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
3591 <GIC_SPI 3300 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
3592 <GIC_SPI 3301 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
3593 <GIC_SPI 3302 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
3594 <GIC_SPI 3303 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
3595 <GIC_SPI 3304 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
3596 <GIC_SPI 3305 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
3597 <GIC_SPI 3306 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
3598 <GIC_SPI 3307 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
3599 <GIC_SPI 3308 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
3600 <GIC_SPI 3309 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
3601 <GIC_SPI 3310 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
3602 <GIC_SPI 3311 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
3603 <GIC_SPI 3312 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
3604 <GIC_SPI 3313 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
3605 <GIC_SPI 3314 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
3606 <GIC_SPI 3315 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
3607 <GIC_SPI 3316 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
3608 <GIC_SPI 3317 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
3609 <GIC_SPI 3318 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
3610 <GIC_SPI 3319 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
3611 <GIC_SPI 3320 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
3612 <GIC_SPI 3321 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
3613 <GIC_SPI 3322 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
3614 <GIC_SPI 3323 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
3615 <GIC_SPI 3324 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
3616 <GIC_SPI 3325 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
3617 <GIC_SPI 3326 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
3618 <GIC_SPI 3327 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
3619 <GIC_SPI 3328 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
3620 <GIC_SPI 3329 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
3621 <GIC_SPI 3330 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
3622 <GIC_SPI 3331 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
3623 <GIC_SPI 3332 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
3624 <GIC_SPI 3333 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
3625 <GIC_SPI 3334 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
3626 <GIC_SPI 3335 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
3627 <GIC_SPI 3336 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
3628 }; 3337 };
3629 3338
3630 intc: interrupt-controller@17 3339 intc: interrupt-controller@17a00000 {
3631 compatible = "arm,gic 3340 compatible = "arm,gic-v3";
3632 #address-cells = <2>; 3341 #address-cells = <2>;
3633 #size-cells = <2>; 3342 #size-cells = <2>;
3634 ranges; 3343 ranges;
3635 #interrupt-cells = <3 3344 #interrupt-cells = <3>;
3636 interrupt-controller; 3345 interrupt-controller;
3637 reg = <0 0x17a00000 0 3346 reg = <0 0x17a00000 0 0x10000>, /* GICD */
3638 <0 0x17a60000 0 3347 <0 0x17a60000 0 0x100000>; /* GICR * 8 */
3639 interrupts = <GIC_PPI 3348 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3640 3349
3641 msi-controller@17a400 3350 msi-controller@17a40000 {
3642 compatible = 3351 compatible = "arm,gic-v3-its";
3643 msi-controlle 3352 msi-controller;
3644 #msi-cells = 3353 #msi-cells = <1>;
3645 reg = <0 0x17 3354 reg = <0 0x17a40000 0 0x20000>;
3646 status = "dis 3355 status = "disabled";
3647 }; 3356 };
3648 }; 3357 };
3649 3358
3650 apss_shared: mailbox@17c00000 3359 apss_shared: mailbox@17c00000 {
3651 compatible = "qcom,sc !! 3360 compatible = "qcom,sc7180-apss-shared";
3652 "qcom,sd <<
3653 reg = <0 0x17c00000 0 3361 reg = <0 0x17c00000 0 0x10000>;
3654 #mbox-cells = <1>; 3362 #mbox-cells = <1>;
3655 }; 3363 };
3656 3364
3657 watchdog@17c10000 { 3365 watchdog@17c10000 {
3658 compatible = "qcom,ap 3366 compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt";
3659 reg = <0 0x17c10000 0 3367 reg = <0 0x17c10000 0 0x1000>;
3660 clocks = <&sleep_clk> 3368 clocks = <&sleep_clk>;
3661 interrupts = <GIC_SPI 3369 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
3662 }; 3370 };
3663 3371
3664 timer@17c20000 { !! 3372 timer@17c20000{
3665 #address-cells = <1>; !! 3373 #address-cells = <2>;
3666 #size-cells = <1>; !! 3374 #size-cells = <2>;
3667 ranges = <0 0 0 0x200 !! 3375 ranges;
3668 compatible = "arm,arm 3376 compatible = "arm,armv7-timer-mem";
3669 reg = <0 0x17c20000 0 3377 reg = <0 0x17c20000 0 0x1000>;
3670 3378
3671 frame@17c21000 { 3379 frame@17c21000 {
3672 frame-number 3380 frame-number = <0>;
3673 interrupts = 3381 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
3674 3382 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
3675 reg = <0x17c2 !! 3383 reg = <0 0x17c21000 0 0x1000>,
3676 <0x17c2 !! 3384 <0 0x17c22000 0 0x1000>;
3677 }; 3385 };
3678 3386
3679 frame@17c23000 { 3387 frame@17c23000 {
3680 frame-number 3388 frame-number = <1>;
3681 interrupts = 3389 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
3682 reg = <0x17c2 !! 3390 reg = <0 0x17c23000 0 0x1000>;
3683 status = "dis 3391 status = "disabled";
3684 }; 3392 };
3685 3393
3686 frame@17c25000 { 3394 frame@17c25000 {
3687 frame-number 3395 frame-number = <2>;
3688 interrupts = 3396 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
3689 reg = <0x17c2 !! 3397 reg = <0 0x17c25000 0 0x1000>;
3690 status = "dis 3398 status = "disabled";
3691 }; 3399 };
3692 3400
3693 frame@17c27000 { 3401 frame@17c27000 {
3694 frame-number 3402 frame-number = <3>;
3695 interrupts = 3403 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3696 reg = <0x17c2 !! 3404 reg = <0 0x17c27000 0 0x1000>;
3697 status = "dis 3405 status = "disabled";
3698 }; 3406 };
3699 3407
3700 frame@17c29000 { 3408 frame@17c29000 {
3701 frame-number 3409 frame-number = <4>;
3702 interrupts = 3410 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3703 reg = <0x17c2 !! 3411 reg = <0 0x17c29000 0 0x1000>;
3704 status = "dis 3412 status = "disabled";
3705 }; 3413 };
3706 3414
3707 frame@17c2b000 { 3415 frame@17c2b000 {
3708 frame-number 3416 frame-number = <5>;
3709 interrupts = 3417 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3710 reg = <0x17c2 !! 3418 reg = <0 0x17c2b000 0 0x1000>;
3711 status = "dis 3419 status = "disabled";
3712 }; 3420 };
3713 3421
3714 frame@17c2d000 { 3422 frame@17c2d000 {
3715 frame-number 3423 frame-number = <6>;
3716 interrupts = 3424 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
3717 reg = <0x17c2 !! 3425 reg = <0 0x17c2d000 0 0x1000>;
3718 status = "dis 3426 status = "disabled";
3719 }; 3427 };
3720 }; 3428 };
3721 3429
3722 apps_rsc: rsc@18200000 { 3430 apps_rsc: rsc@18200000 {
3723 compatible = "qcom,rp 3431 compatible = "qcom,rpmh-rsc";
3724 reg = <0 0x18200000 0 3432 reg = <0 0x18200000 0 0x10000>,
3725 <0 0x18210000 0 3433 <0 0x18210000 0 0x10000>,
3726 <0 0x18220000 0 3434 <0 0x18220000 0 0x10000>;
3727 reg-names = "drv-0", 3435 reg-names = "drv-0", "drv-1", "drv-2";
3728 interrupts = <GIC_SPI 3436 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
3729 <GIC_SPI 3437 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
3730 <GIC_SPI 3438 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
3731 qcom,tcs-offset = <0x 3439 qcom,tcs-offset = <0xd00>;
3732 qcom,drv-id = <2>; 3440 qcom,drv-id = <2>;
3733 qcom,tcs-config = <AC 3441 qcom,tcs-config = <ACTIVE_TCS 2>,
3734 <SL 3442 <SLEEP_TCS 3>,
3735 <WA 3443 <WAKE_TCS 3>,
3736 <CO 3444 <CONTROL_TCS 1>;
3737 power-domains = <&CLU <<
3738 3445
3739 rpmhcc: clock-control 3446 rpmhcc: clock-controller {
3740 compatible = 3447 compatible = "qcom,sc7180-rpmh-clk";
3741 clocks = <&xo 3448 clocks = <&xo_board>;
3742 clock-names = 3449 clock-names = "xo";
3743 #clock-cells 3450 #clock-cells = <1>;
3744 }; 3451 };
3745 3452
3746 rpmhpd: power-control 3453 rpmhpd: power-controller {
3747 compatible = 3454 compatible = "qcom,sc7180-rpmhpd";
3748 #power-domain 3455 #power-domain-cells = <1>;
3749 operating-poi 3456 operating-points-v2 = <&rpmhpd_opp_table>;
3750 3457
3751 rpmhpd_opp_ta 3458 rpmhpd_opp_table: opp-table {
3752 compa 3459 compatible = "operating-points-v2";
3753 3460
3754 rpmhp 3461 rpmhpd_opp_ret: opp1 {
3755 3462 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3756 }; 3463 };
3757 3464
3758 rpmhp 3465 rpmhpd_opp_min_svs: opp2 {
3759 3466 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3760 }; 3467 };
3761 3468
3762 rpmhp 3469 rpmhpd_opp_low_svs: opp3 {
3763 3470 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3764 }; 3471 };
3765 3472
3766 rpmhp 3473 rpmhpd_opp_svs: opp4 {
3767 3474 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3768 }; 3475 };
3769 3476
3770 rpmhp 3477 rpmhpd_opp_svs_l1: opp5 {
3771 3478 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3772 }; 3479 };
3773 3480
3774 rpmhp 3481 rpmhpd_opp_svs_l2: opp6 {
3775 3482 opp-level = <224>;
3776 }; 3483 };
3777 3484
3778 rpmhp 3485 rpmhpd_opp_nom: opp7 {
3779 3486 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3780 }; 3487 };
3781 3488
3782 rpmhp 3489 rpmhpd_opp_nom_l1: opp8 {
3783 3490 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3784 }; 3491 };
3785 3492
3786 rpmhp 3493 rpmhpd_opp_nom_l2: opp9 {
3787 3494 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3788 }; 3495 };
3789 3496
3790 rpmhp 3497 rpmhpd_opp_turbo: opp10 {
3791 3498 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3792 }; 3499 };
3793 3500
3794 rpmhp 3501 rpmhpd_opp_turbo_l1: opp11 {
3795 3502 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3796 }; 3503 };
3797 }; 3504 };
3798 }; 3505 };
3799 3506
3800 apps_bcm_voter: bcm-v !! 3507 apps_bcm_voter: bcm_voter {
3801 compatible = 3508 compatible = "qcom,bcm-voter";
3802 }; 3509 };
3803 }; 3510 };
3804 3511
3805 osm_l3: interconnect@18321000 3512 osm_l3: interconnect@18321000 {
3806 compatible = "qcom,sc !! 3513 compatible = "qcom,sc7180-osm-l3";
3807 reg = <0 0x18321000 0 3514 reg = <0 0x18321000 0 0x1400>;
3808 3515
3809 clocks = <&rpmhcc RPM 3516 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3810 clock-names = "xo", " 3517 clock-names = "xo", "alternate";
3811 3518
3812 #interconnect-cells = 3519 #interconnect-cells = <1>;
3813 }; 3520 };
3814 3521
3815 cpufreq_hw: cpufreq@18323000 3522 cpufreq_hw: cpufreq@18323000 {
3816 compatible = "qcom,sc !! 3523 compatible = "qcom,cpufreq-hw";
3817 reg = <0 0x18323000 0 3524 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>;
3818 reg-names = "freq-dom 3525 reg-names = "freq-domain0", "freq-domain1";
3819 3526
3820 clocks = <&rpmhcc RPM 3527 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3821 clock-names = "xo", " 3528 clock-names = "xo", "alternate";
3822 3529
3823 #freq-domain-cells = 3530 #freq-domain-cells = <1>;
3824 #clock-cells = <1>; <<
3825 }; 3531 };
3826 3532
3827 wifi: wifi@18800000 { 3533 wifi: wifi@18800000 {
3828 compatible = "qcom,wc 3534 compatible = "qcom,wcn3990-wifi";
3829 reg = <0 0x18800000 0 3535 reg = <0 0x18800000 0 0x800000>;
3830 reg-names = "membase" 3536 reg-names = "membase";
3831 iommus = <&apps_smmu 3537 iommus = <&apps_smmu 0xc0 0x1>;
3832 interrupts = 3538 interrupts =
3833 <GIC_SPI 414 3539 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH /* CE0 */ >,
3834 <GIC_SPI 415 3540 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH /* CE1 */ >,
3835 <GIC_SPI 416 3541 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH /* CE2 */ >,
3836 <GIC_SPI 417 3542 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH /* CE3 */ >,
3837 <GIC_SPI 418 3543 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH /* CE4 */ >,
3838 <GIC_SPI 419 3544 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH /* CE5 */ >,
3839 <GIC_SPI 420 3545 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH /* CE6 */ >,
3840 <GIC_SPI 421 3546 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH /* CE7 */ >,
3841 <GIC_SPI 422 3547 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH /* CE8 */ >,
3842 <GIC_SPI 423 3548 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH /* CE9 */ >,
3843 <GIC_SPI 424 3549 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH /* CE10 */>,
3844 <GIC_SPI 425 3550 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH /* CE11 */>;
3845 memory-region = <&wla 3551 memory-region = <&wlan_mem>;
3846 qcom,msa-fixed-perm; 3552 qcom,msa-fixed-perm;
3847 status = "disabled"; 3553 status = "disabled";
3848 }; 3554 };
3849 3555
3850 remoteproc_adsp: remoteproc@6 <<
3851 compatible = "qcom,sc <<
3852 reg = <0 0x62400000 0 <<
3853 <<
3854 interrupts-extended = <<
3855 <<
3856 <<
3857 <<
3858 <<
3859 interrupt-names = "wd <<
3860 "fa <<
3861 "re <<
3862 "ha <<
3863 "st <<
3864 <<
3865 clocks = <&rpmhcc RPM <<
3866 clock-names = "xo"; <<
3867 <<
3868 power-domains = <&rpm <<
3869 <&rpm <<
3870 power-domain-names = <<
3871 <<
3872 qcom,qmp = <&aoss_qmp <<
3873 qcom,smem-states = <& <<
3874 qcom,smem-state-names <<
3875 <<
3876 status = "disabled"; <<
3877 <<
3878 glink-edge { <<
3879 interrupts = <<
3880 label = "lpas <<
3881 qcom,remote-p <<
3882 mboxes = <&ap <<
3883 <<
3884 apr { <<
3885 compa <<
3886 qcom, <<
3887 qcom, <<
3888 #addr <<
3889 #size <<
3890 <<
3891 servi <<
3892 <<
3893 <<
3894 <<
3895 }; <<
3896 <<
3897 q6afe <<
3898 <<
3899 <<
3900 <<
3901 <<
3902 <<
3903 <<
3904 <<
3905 <<
3906 <<
3907 <<
3908 <<
3909 <<
3910 <<
3911 <<
3912 <<
3913 }; <<
3914 <<
3915 q6asm <<
3916 <<
3917 <<
3918 <<
3919 <<
3920 <<
3921 <<
3922 <<
3923 <<
3924 <<
3925 <<
3926 <<
3927 }; <<
3928 <<
3929 q6adm <<
3930 <<
3931 <<
3932 <<
3933 <<
3934 <<
3935 <<
3936 <<
3937 <<
3938 }; <<
3939 }; <<
3940 <<
3941 fastrpc { <<
3942 compa <<
3943 qcom, <<
3944 label <<
3945 #addr <<
3946 #size <<
3947 <<
3948 compu <<
3949 <<
3950 <<
3951 <<
3952 }; <<
3953 <<
3954 compu <<
3955 <<
3956 <<
3957 <<
3958 }; <<
3959 <<
3960 compu <<
3961 <<
3962 <<
3963 <<
3964 <<
3965 }; <<
3966 }; <<
3967 }; <<
3968 }; <<
3969 <<
3970 lpasscc: clock-controller@62d 3556 lpasscc: clock-controller@62d00000 {
3971 compatible = "qcom,sc 3557 compatible = "qcom,sc7180-lpasscorecc";
3972 reg = <0 0x62d00000 0 3558 reg = <0 0x62d00000 0 0x50000>,
3973 <0 0x62780000 0 3559 <0 0x62780000 0 0x30000>;
3974 reg-names = "lpass_co 3560 reg-names = "lpass_core_cc", "lpass_audio_cc";
3975 clocks = <&gcc GCC_LP 3561 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>,
3976 <&rpmhcc RPM 3562 <&rpmhcc RPMH_CXO_CLK>;
3977 clock-names = "iface" 3563 clock-names = "iface", "bi_tcxo";
3978 power-domains = <&lpa 3564 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>;
3979 #clock-cells = <1>; 3565 #clock-cells = <1>;
3980 #power-domain-cells = 3566 #power-domain-cells = <1>;
3981 <<
3982 status = "reserved"; <<
3983 }; 3567 };
3984 3568
3985 lpass_cpu: lpass@62d87000 { 3569 lpass_cpu: lpass@62d87000 {
3986 compatible = "qcom,sc 3570 compatible = "qcom,sc7180-lpass-cpu";
3987 3571
3988 reg = <0 0x62d87000 0 3572 reg = <0 0x62d87000 0 0x68000>, <0 0x62f00000 0 0x29000>;
3989 reg-names = "lpass-hd !! 3573 reg-names = "lpass-hdmiif", "lpass-lpaif";
3990 3574
3991 iommus = <&apps_smmu 3575 iommus = <&apps_smmu 0x1020 0>,
3992 <&apps_smmu 0 3576 <&apps_smmu 0x1021 0>,
3993 <&apps_smmu 0 3577 <&apps_smmu 0x1032 0>;
3994 3578
3995 power-domains = <&lpa 3579 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>;
3996 required-opps = <&rpm <<
3997 3580
3998 status = "disabled"; 3581 status = "disabled";
3999 3582
4000 clocks = <&gcc GCC_LP 3583 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>,
4001 <&lpasscc LP 3584 <&lpasscc LPASS_AUDIO_CORE_CORE_CLK>,
4002 <&lpasscc LP 3585 <&lpasscc LPASS_AUDIO_CORE_EXT_MCLK0_CLK>,
4003 <&lpasscc LP 3586 <&lpasscc LPASS_AUDIO_CORE_SYSNOC_MPORT_CORE_CLK>,
4004 <&lpasscc LP 3587 <&lpasscc LPASS_AUDIO_CORE_LPAIF_PRI_IBIT_CLK>,
4005 <&lpasscc LP 3588 <&lpasscc LPASS_AUDIO_CORE_LPAIF_SEC_IBIT_CLK>;
4006 3589
4007 clock-names = "pcnoc- 3590 clock-names = "pcnoc-sway-clk", "audio-core",
4008 "mclk 3591 "mclk0", "pcnoc-mport-clk",
4009 "mi2s 3592 "mi2s-bit-clk0", "mi2s-bit-clk1";
4010 3593
4011 3594
4012 #sound-dai-cells = <1 3595 #sound-dai-cells = <1>;
4013 #address-cells = <1>; 3596 #address-cells = <1>;
4014 #size-cells = <0>; 3597 #size-cells = <0>;
4015 3598
4016 interrupts = <GIC_SPI 3599 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
4017 <GIC_ 3600 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
4018 interrupt-names = "lp 3601 interrupt-names = "lpass-irq-lpaif", "lpass-irq-hdmi";
4019 }; 3602 };
4020 3603
4021 lpass_hm: clock-controller@63 3604 lpass_hm: clock-controller@63000000 {
4022 compatible = "qcom,sc 3605 compatible = "qcom,sc7180-lpasshm";
4023 reg = <0 0x63000000 0 3606 reg = <0 0x63000000 0 0x28>;
4024 clocks = <&gcc GCC_LP 3607 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>,
4025 <&rpmhcc RPM 3608 <&rpmhcc RPMH_CXO_CLK>;
4026 clock-names = "iface" 3609 clock-names = "iface", "bi_tcxo";
4027 power-domains = <&rpm <<
4028 <<
4029 #clock-cells = <1>; 3610 #clock-cells = <1>;
4030 #power-domain-cells = 3611 #power-domain-cells = <1>;
4031 <<
4032 status = "reserved"; <<
4033 }; 3612 };
4034 }; 3613 };
4035 3614
4036 thermal-zones { 3615 thermal-zones {
4037 cpu0_thermal: cpu0-thermal { 3616 cpu0_thermal: cpu0-thermal {
4038 polling-delay-passive 3617 polling-delay-passive = <250>;
>> 3618 polling-delay = <0>;
4039 3619
4040 thermal-sensors = <&t 3620 thermal-sensors = <&tsens0 1>;
4041 sustainable-power = < 3621 sustainable-power = <1052>;
4042 3622
4043 trips { 3623 trips {
4044 cpu0_alert0: 3624 cpu0_alert0: trip-point0 {
4045 tempe 3625 temperature = <90000>;
4046 hyste 3626 hysteresis = <2000>;
4047 type 3627 type = "passive";
4048 }; 3628 };
4049 3629
4050 cpu0_alert1: 3630 cpu0_alert1: trip-point1 {
4051 tempe 3631 temperature = <95000>;
4052 hyste 3632 hysteresis = <2000>;
4053 type 3633 type = "passive";
4054 }; 3634 };
4055 3635
4056 cpu0_crit: cp !! 3636 cpu0_crit: cpu_crit {
4057 tempe 3637 temperature = <110000>;
4058 hyste 3638 hysteresis = <1000>;
4059 type 3639 type = "critical";
4060 }; 3640 };
4061 }; 3641 };
4062 3642
4063 cooling-maps { 3643 cooling-maps {
4064 map0 { 3644 map0 {
4065 trip 3645 trip = <&cpu0_alert0>;
4066 cooli 3646 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4067 3647 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4068 3648 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4069 3649 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4070 3650 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4071 3651 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4072 }; 3652 };
4073 map1 { 3653 map1 {
4074 trip 3654 trip = <&cpu0_alert1>;
4075 cooli 3655 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4076 3656 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4077 3657 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4078 3658 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4079 3659 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4080 3660 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4081 }; 3661 };
4082 }; 3662 };
4083 }; 3663 };
4084 3664
4085 cpu1_thermal: cpu1-thermal { 3665 cpu1_thermal: cpu1-thermal {
4086 polling-delay-passive 3666 polling-delay-passive = <250>;
>> 3667 polling-delay = <0>;
4087 3668
4088 thermal-sensors = <&t 3669 thermal-sensors = <&tsens0 2>;
4089 sustainable-power = < 3670 sustainable-power = <1052>;
4090 3671
4091 trips { 3672 trips {
4092 cpu1_alert0: 3673 cpu1_alert0: trip-point0 {
4093 tempe 3674 temperature = <90000>;
4094 hyste 3675 hysteresis = <2000>;
4095 type 3676 type = "passive";
4096 }; 3677 };
4097 3678
4098 cpu1_alert1: 3679 cpu1_alert1: trip-point1 {
4099 tempe 3680 temperature = <95000>;
4100 hyste 3681 hysteresis = <2000>;
4101 type 3682 type = "passive";
4102 }; 3683 };
4103 3684
4104 cpu1_crit: cp !! 3685 cpu1_crit: cpu_crit {
4105 tempe 3686 temperature = <110000>;
4106 hyste 3687 hysteresis = <1000>;
4107 type 3688 type = "critical";
4108 }; 3689 };
4109 }; 3690 };
4110 3691
4111 cooling-maps { 3692 cooling-maps {
4112 map0 { 3693 map0 {
4113 trip 3694 trip = <&cpu1_alert0>;
4114 cooli 3695 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4115 3696 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4116 3697 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4117 3698 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4118 3699 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4119 3700 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4120 }; 3701 };
4121 map1 { 3702 map1 {
4122 trip 3703 trip = <&cpu1_alert1>;
4123 cooli 3704 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4124 3705 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4125 3706 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4126 3707 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4127 3708 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4128 3709 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4129 }; 3710 };
4130 }; 3711 };
4131 }; 3712 };
4132 3713
4133 cpu2_thermal: cpu2-thermal { 3714 cpu2_thermal: cpu2-thermal {
4134 polling-delay-passive 3715 polling-delay-passive = <250>;
>> 3716 polling-delay = <0>;
4135 3717
4136 thermal-sensors = <&t 3718 thermal-sensors = <&tsens0 3>;
4137 sustainable-power = < 3719 sustainable-power = <1052>;
4138 3720
4139 trips { 3721 trips {
4140 cpu2_alert0: 3722 cpu2_alert0: trip-point0 {
4141 tempe 3723 temperature = <90000>;
4142 hyste 3724 hysteresis = <2000>;
4143 type 3725 type = "passive";
4144 }; 3726 };
4145 3727
4146 cpu2_alert1: 3728 cpu2_alert1: trip-point1 {
4147 tempe 3729 temperature = <95000>;
4148 hyste 3730 hysteresis = <2000>;
4149 type 3731 type = "passive";
4150 }; 3732 };
4151 3733
4152 cpu2_crit: cp !! 3734 cpu2_crit: cpu_crit {
4153 tempe 3735 temperature = <110000>;
4154 hyste 3736 hysteresis = <1000>;
4155 type 3737 type = "critical";
4156 }; 3738 };
4157 }; 3739 };
4158 3740
4159 cooling-maps { 3741 cooling-maps {
4160 map0 { 3742 map0 {
4161 trip 3743 trip = <&cpu2_alert0>;
4162 cooli 3744 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4163 3745 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4164 3746 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4165 3747 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4166 3748 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4167 3749 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4168 }; 3750 };
4169 map1 { 3751 map1 {
4170 trip 3752 trip = <&cpu2_alert1>;
4171 cooli 3753 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4172 3754 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4173 3755 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4174 3756 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4175 3757 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4176 3758 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4177 }; 3759 };
4178 }; 3760 };
4179 }; 3761 };
4180 3762
4181 cpu3_thermal: cpu3-thermal { 3763 cpu3_thermal: cpu3-thermal {
4182 polling-delay-passive 3764 polling-delay-passive = <250>;
>> 3765 polling-delay = <0>;
4183 3766
4184 thermal-sensors = <&t 3767 thermal-sensors = <&tsens0 4>;
4185 sustainable-power = < 3768 sustainable-power = <1052>;
4186 3769
4187 trips { 3770 trips {
4188 cpu3_alert0: 3771 cpu3_alert0: trip-point0 {
4189 tempe 3772 temperature = <90000>;
4190 hyste 3773 hysteresis = <2000>;
4191 type 3774 type = "passive";
4192 }; 3775 };
4193 3776
4194 cpu3_alert1: 3777 cpu3_alert1: trip-point1 {
4195 tempe 3778 temperature = <95000>;
4196 hyste 3779 hysteresis = <2000>;
4197 type 3780 type = "passive";
4198 }; 3781 };
4199 3782
4200 cpu3_crit: cp !! 3783 cpu3_crit: cpu_crit {
4201 tempe 3784 temperature = <110000>;
4202 hyste 3785 hysteresis = <1000>;
4203 type 3786 type = "critical";
4204 }; 3787 };
4205 }; 3788 };
4206 3789
4207 cooling-maps { 3790 cooling-maps {
4208 map0 { 3791 map0 {
4209 trip 3792 trip = <&cpu3_alert0>;
4210 cooli 3793 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4211 3794 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4212 3795 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4213 3796 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4214 3797 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4215 3798 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4216 }; 3799 };
4217 map1 { 3800 map1 {
4218 trip 3801 trip = <&cpu3_alert1>;
4219 cooli 3802 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4220 3803 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4221 3804 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4222 3805 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4223 3806 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4224 3807 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4225 }; 3808 };
4226 }; 3809 };
4227 }; 3810 };
4228 3811
4229 cpu4_thermal: cpu4-thermal { 3812 cpu4_thermal: cpu4-thermal {
4230 polling-delay-passive 3813 polling-delay-passive = <250>;
>> 3814 polling-delay = <0>;
4231 3815
4232 thermal-sensors = <&t 3816 thermal-sensors = <&tsens0 5>;
4233 sustainable-power = < 3817 sustainable-power = <1052>;
4234 3818
4235 trips { 3819 trips {
4236 cpu4_alert0: 3820 cpu4_alert0: trip-point0 {
4237 tempe 3821 temperature = <90000>;
4238 hyste 3822 hysteresis = <2000>;
4239 type 3823 type = "passive";
4240 }; 3824 };
4241 3825
4242 cpu4_alert1: 3826 cpu4_alert1: trip-point1 {
4243 tempe 3827 temperature = <95000>;
4244 hyste 3828 hysteresis = <2000>;
4245 type 3829 type = "passive";
4246 }; 3830 };
4247 3831
4248 cpu4_crit: cp !! 3832 cpu4_crit: cpu_crit {
4249 tempe 3833 temperature = <110000>;
4250 hyste 3834 hysteresis = <1000>;
4251 type 3835 type = "critical";
4252 }; 3836 };
4253 }; 3837 };
4254 3838
4255 cooling-maps { 3839 cooling-maps {
4256 map0 { 3840 map0 {
4257 trip 3841 trip = <&cpu4_alert0>;
4258 cooli 3842 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4259 3843 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4260 3844 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4261 3845 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4262 3846 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4263 3847 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4264 }; 3848 };
4265 map1 { 3849 map1 {
4266 trip 3850 trip = <&cpu4_alert1>;
4267 cooli 3851 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4268 3852 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4269 3853 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4270 3854 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4271 3855 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4272 3856 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4273 }; 3857 };
4274 }; 3858 };
4275 }; 3859 };
4276 3860
4277 cpu5_thermal: cpu5-thermal { 3861 cpu5_thermal: cpu5-thermal {
4278 polling-delay-passive 3862 polling-delay-passive = <250>;
>> 3863 polling-delay = <0>;
4279 3864
4280 thermal-sensors = <&t 3865 thermal-sensors = <&tsens0 6>;
4281 sustainable-power = < 3866 sustainable-power = <1052>;
4282 3867
4283 trips { 3868 trips {
4284 cpu5_alert0: 3869 cpu5_alert0: trip-point0 {
4285 tempe 3870 temperature = <90000>;
4286 hyste 3871 hysteresis = <2000>;
4287 type 3872 type = "passive";
4288 }; 3873 };
4289 3874
4290 cpu5_alert1: 3875 cpu5_alert1: trip-point1 {
4291 tempe 3876 temperature = <95000>;
4292 hyste 3877 hysteresis = <2000>;
4293 type 3878 type = "passive";
4294 }; 3879 };
4295 3880
4296 cpu5_crit: cp !! 3881 cpu5_crit: cpu_crit {
4297 tempe 3882 temperature = <110000>;
4298 hyste 3883 hysteresis = <1000>;
4299 type 3884 type = "critical";
4300 }; 3885 };
4301 }; 3886 };
4302 3887
4303 cooling-maps { 3888 cooling-maps {
4304 map0 { 3889 map0 {
4305 trip 3890 trip = <&cpu5_alert0>;
4306 cooli 3891 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4307 3892 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4308 3893 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4309 3894 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4310 3895 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4311 3896 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4312 }; 3897 };
4313 map1 { 3898 map1 {
4314 trip 3899 trip = <&cpu5_alert1>;
4315 cooli 3900 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4316 3901 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4317 3902 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4318 3903 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4319 3904 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4320 3905 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4321 }; 3906 };
4322 }; 3907 };
4323 }; 3908 };
4324 3909
4325 cpu6_thermal: cpu6-thermal { 3910 cpu6_thermal: cpu6-thermal {
4326 polling-delay-passive 3911 polling-delay-passive = <250>;
>> 3912 polling-delay = <0>;
4327 3913
4328 thermal-sensors = <&t 3914 thermal-sensors = <&tsens0 9>;
4329 sustainable-power = < 3915 sustainable-power = <1425>;
4330 3916
4331 trips { 3917 trips {
4332 cpu6_alert0: 3918 cpu6_alert0: trip-point0 {
4333 tempe 3919 temperature = <90000>;
4334 hyste 3920 hysteresis = <2000>;
4335 type 3921 type = "passive";
4336 }; 3922 };
4337 3923
4338 cpu6_alert1: 3924 cpu6_alert1: trip-point1 {
4339 tempe 3925 temperature = <95000>;
4340 hyste 3926 hysteresis = <2000>;
4341 type 3927 type = "passive";
4342 }; 3928 };
4343 3929
4344 cpu6_crit: cp !! 3930 cpu6_crit: cpu_crit {
4345 tempe 3931 temperature = <110000>;
4346 hyste 3932 hysteresis = <1000>;
4347 type 3933 type = "critical";
4348 }; 3934 };
4349 }; 3935 };
4350 3936
4351 cooling-maps { 3937 cooling-maps {
4352 map0 { 3938 map0 {
4353 trip 3939 trip = <&cpu6_alert0>;
4354 cooli 3940 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4355 3941 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4356 }; 3942 };
4357 map1 { 3943 map1 {
4358 trip 3944 trip = <&cpu6_alert1>;
4359 cooli 3945 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4360 3946 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4361 }; 3947 };
4362 }; 3948 };
4363 }; 3949 };
4364 3950
4365 cpu7_thermal: cpu7-thermal { 3951 cpu7_thermal: cpu7-thermal {
4366 polling-delay-passive 3952 polling-delay-passive = <250>;
>> 3953 polling-delay = <0>;
4367 3954
4368 thermal-sensors = <&t 3955 thermal-sensors = <&tsens0 10>;
4369 sustainable-power = < 3956 sustainable-power = <1425>;
4370 3957
4371 trips { 3958 trips {
4372 cpu7_alert0: 3959 cpu7_alert0: trip-point0 {
4373 tempe 3960 temperature = <90000>;
4374 hyste 3961 hysteresis = <2000>;
4375 type 3962 type = "passive";
4376 }; 3963 };
4377 3964
4378 cpu7_alert1: 3965 cpu7_alert1: trip-point1 {
4379 tempe 3966 temperature = <95000>;
4380 hyste 3967 hysteresis = <2000>;
4381 type 3968 type = "passive";
4382 }; 3969 };
4383 3970
4384 cpu7_crit: cp !! 3971 cpu7_crit: cpu_crit {
4385 tempe 3972 temperature = <110000>;
4386 hyste 3973 hysteresis = <1000>;
4387 type 3974 type = "critical";
4388 }; 3975 };
4389 }; 3976 };
4390 3977
4391 cooling-maps { 3978 cooling-maps {
4392 map0 { 3979 map0 {
4393 trip 3980 trip = <&cpu7_alert0>;
4394 cooli 3981 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4395 3982 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4396 }; 3983 };
4397 map1 { 3984 map1 {
4398 trip 3985 trip = <&cpu7_alert1>;
4399 cooli 3986 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4400 3987 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4401 }; 3988 };
4402 }; 3989 };
4403 }; 3990 };
4404 3991
4405 cpu8_thermal: cpu8-thermal { 3992 cpu8_thermal: cpu8-thermal {
4406 polling-delay-passive 3993 polling-delay-passive = <250>;
>> 3994 polling-delay = <0>;
4407 3995
4408 thermal-sensors = <&t 3996 thermal-sensors = <&tsens0 11>;
4409 sustainable-power = < 3997 sustainable-power = <1425>;
4410 3998
4411 trips { 3999 trips {
4412 cpu8_alert0: 4000 cpu8_alert0: trip-point0 {
4413 tempe 4001 temperature = <90000>;
4414 hyste 4002 hysteresis = <2000>;
4415 type 4003 type = "passive";
4416 }; 4004 };
4417 4005
4418 cpu8_alert1: 4006 cpu8_alert1: trip-point1 {
4419 tempe 4007 temperature = <95000>;
4420 hyste 4008 hysteresis = <2000>;
4421 type 4009 type = "passive";
4422 }; 4010 };
4423 4011
4424 cpu8_crit: cp !! 4012 cpu8_crit: cpu_crit {
4425 tempe 4013 temperature = <110000>;
4426 hyste 4014 hysteresis = <1000>;
4427 type 4015 type = "critical";
4428 }; 4016 };
4429 }; 4017 };
4430 4018
4431 cooling-maps { 4019 cooling-maps {
4432 map0 { 4020 map0 {
4433 trip 4021 trip = <&cpu8_alert0>;
4434 cooli 4022 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4435 4023 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4436 }; 4024 };
4437 map1 { 4025 map1 {
4438 trip 4026 trip = <&cpu8_alert1>;
4439 cooli 4027 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4440 4028 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4441 }; 4029 };
4442 }; 4030 };
4443 }; 4031 };
4444 4032
4445 cpu9_thermal: cpu9-thermal { 4033 cpu9_thermal: cpu9-thermal {
4446 polling-delay-passive 4034 polling-delay-passive = <250>;
>> 4035 polling-delay = <0>;
4447 4036
4448 thermal-sensors = <&t 4037 thermal-sensors = <&tsens0 12>;
4449 sustainable-power = < 4038 sustainable-power = <1425>;
4450 4039
4451 trips { 4040 trips {
4452 cpu9_alert0: 4041 cpu9_alert0: trip-point0 {
4453 tempe 4042 temperature = <90000>;
4454 hyste 4043 hysteresis = <2000>;
4455 type 4044 type = "passive";
4456 }; 4045 };
4457 4046
4458 cpu9_alert1: 4047 cpu9_alert1: trip-point1 {
4459 tempe 4048 temperature = <95000>;
4460 hyste 4049 hysteresis = <2000>;
4461 type 4050 type = "passive";
4462 }; 4051 };
4463 4052
4464 cpu9_crit: cp !! 4053 cpu9_crit: cpu_crit {
4465 tempe 4054 temperature = <110000>;
4466 hyste 4055 hysteresis = <1000>;
4467 type 4056 type = "critical";
4468 }; 4057 };
4469 }; 4058 };
4470 4059
4471 cooling-maps { 4060 cooling-maps {
4472 map0 { 4061 map0 {
4473 trip 4062 trip = <&cpu9_alert0>;
4474 cooli 4063 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4475 4064 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4476 }; 4065 };
4477 map1 { 4066 map1 {
4478 trip 4067 trip = <&cpu9_alert1>;
4479 cooli 4068 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4480 4069 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4481 }; 4070 };
4482 }; 4071 };
4483 }; 4072 };
4484 4073
4485 aoss0-thermal { 4074 aoss0-thermal {
4486 polling-delay-passive 4075 polling-delay-passive = <250>;
>> 4076 polling-delay = <0>;
4487 4077
4488 thermal-sensors = <&t 4078 thermal-sensors = <&tsens0 0>;
4489 4079
4490 trips { 4080 trips {
4491 aoss0_alert0: 4081 aoss0_alert0: trip-point0 {
4492 tempe 4082 temperature = <90000>;
4493 hyste 4083 hysteresis = <2000>;
4494 type 4084 type = "hot";
4495 }; 4085 };
4496 4086
4497 aoss0_crit: a !! 4087 aoss0_crit: aoss0_crit {
4498 tempe 4088 temperature = <110000>;
4499 hyste 4089 hysteresis = <2000>;
4500 type 4090 type = "critical";
4501 }; 4091 };
4502 }; 4092 };
4503 }; 4093 };
4504 4094
4505 cpuss0-thermal { 4095 cpuss0-thermal {
4506 polling-delay-passive 4096 polling-delay-passive = <250>;
>> 4097 polling-delay = <0>;
4507 4098
4508 thermal-sensors = <&t 4099 thermal-sensors = <&tsens0 7>;
4509 4100
4510 trips { 4101 trips {
4511 cpuss0_alert0 4102 cpuss0_alert0: trip-point0 {
4512 tempe 4103 temperature = <90000>;
4513 hyste 4104 hysteresis = <2000>;
4514 type 4105 type = "hot";
4515 }; 4106 };
4516 cpuss0_crit: !! 4107 cpuss0_crit: cluster0_crit {
4517 tempe 4108 temperature = <110000>;
4518 hyste 4109 hysteresis = <2000>;
4519 type 4110 type = "critical";
4520 }; 4111 };
4521 }; 4112 };
4522 }; 4113 };
4523 4114
4524 cpuss1-thermal { 4115 cpuss1-thermal {
4525 polling-delay-passive 4116 polling-delay-passive = <250>;
>> 4117 polling-delay = <0>;
4526 4118
4527 thermal-sensors = <&t 4119 thermal-sensors = <&tsens0 8>;
4528 4120
4529 trips { 4121 trips {
4530 cpuss1_alert0 4122 cpuss1_alert0: trip-point0 {
4531 tempe 4123 temperature = <90000>;
4532 hyste 4124 hysteresis = <2000>;
4533 type 4125 type = "hot";
4534 }; 4126 };
4535 cpuss1_crit: !! 4127 cpuss1_crit: cluster0_crit {
4536 tempe 4128 temperature = <110000>;
4537 hyste 4129 hysteresis = <2000>;
4538 type 4130 type = "critical";
4539 }; 4131 };
4540 }; 4132 };
4541 }; 4133 };
4542 4134
4543 gpuss0-thermal { 4135 gpuss0-thermal {
4544 polling-delay-passive 4136 polling-delay-passive = <250>;
>> 4137 polling-delay = <0>;
4545 4138
4546 thermal-sensors = <&t 4139 thermal-sensors = <&tsens0 13>;
4547 4140
4548 trips { 4141 trips {
4549 gpuss0_alert0 4142 gpuss0_alert0: trip-point0 {
4550 tempe 4143 temperature = <95000>;
4551 hyste 4144 hysteresis = <2000>;
4552 type 4145 type = "passive";
4553 }; 4146 };
4554 4147
4555 gpuss0_crit: !! 4148 gpuss0_crit: gpuss0_crit {
4556 tempe 4149 temperature = <110000>;
4557 hyste 4150 hysteresis = <2000>;
4558 type 4151 type = "critical";
4559 }; 4152 };
4560 }; 4153 };
4561 4154
4562 cooling-maps { 4155 cooling-maps {
4563 map0 { 4156 map0 {
4564 trip 4157 trip = <&gpuss0_alert0>;
4565 cooli 4158 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4566 }; 4159 };
4567 }; 4160 };
4568 }; 4161 };
4569 4162
4570 gpuss1-thermal { 4163 gpuss1-thermal {
4571 polling-delay-passive 4164 polling-delay-passive = <250>;
>> 4165 polling-delay = <0>;
4572 4166
4573 thermal-sensors = <&t 4167 thermal-sensors = <&tsens0 14>;
4574 4168
4575 trips { 4169 trips {
4576 gpuss1_alert0 4170 gpuss1_alert0: trip-point0 {
4577 tempe 4171 temperature = <95000>;
4578 hyste 4172 hysteresis = <2000>;
4579 type 4173 type = "passive";
4580 }; 4174 };
4581 4175
4582 gpuss1_crit: !! 4176 gpuss1_crit: gpuss1_crit {
4583 tempe 4177 temperature = <110000>;
4584 hyste 4178 hysteresis = <2000>;
4585 type 4179 type = "critical";
4586 }; 4180 };
4587 }; 4181 };
4588 4182
4589 cooling-maps { 4183 cooling-maps {
4590 map0 { 4184 map0 {
4591 trip 4185 trip = <&gpuss1_alert0>;
4592 cooli 4186 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4593 }; 4187 };
4594 }; 4188 };
4595 }; 4189 };
4596 4190
4597 aoss1-thermal { 4191 aoss1-thermal {
4598 polling-delay-passive 4192 polling-delay-passive = <250>;
>> 4193 polling-delay = <0>;
4599 4194
4600 thermal-sensors = <&t 4195 thermal-sensors = <&tsens1 0>;
4601 4196
4602 trips { 4197 trips {
4603 aoss1_alert0: 4198 aoss1_alert0: trip-point0 {
4604 tempe 4199 temperature = <90000>;
4605 hyste 4200 hysteresis = <2000>;
4606 type 4201 type = "hot";
4607 }; 4202 };
4608 4203
4609 aoss1_crit: a !! 4204 aoss1_crit: aoss1_crit {
4610 tempe 4205 temperature = <110000>;
4611 hyste 4206 hysteresis = <2000>;
4612 type 4207 type = "critical";
4613 }; 4208 };
4614 }; 4209 };
4615 }; 4210 };
4616 4211
4617 cwlan-thermal { 4212 cwlan-thermal {
4618 polling-delay-passive 4213 polling-delay-passive = <250>;
>> 4214 polling-delay = <0>;
4619 4215
4620 thermal-sensors = <&t 4216 thermal-sensors = <&tsens1 1>;
4621 4217
4622 trips { 4218 trips {
4623 cwlan_alert0: 4219 cwlan_alert0: trip-point0 {
4624 tempe 4220 temperature = <90000>;
4625 hyste 4221 hysteresis = <2000>;
4626 type 4222 type = "hot";
4627 }; 4223 };
4628 4224
4629 cwlan_crit: c !! 4225 cwlan_crit: cwlan_crit {
4630 tempe 4226 temperature = <110000>;
4631 hyste 4227 hysteresis = <2000>;
4632 type 4228 type = "critical";
4633 }; 4229 };
4634 }; 4230 };
4635 }; 4231 };
4636 4232
4637 audio-thermal { 4233 audio-thermal {
4638 polling-delay-passive 4234 polling-delay-passive = <250>;
>> 4235 polling-delay = <0>;
4639 4236
4640 thermal-sensors = <&t 4237 thermal-sensors = <&tsens1 2>;
4641 4238
4642 trips { 4239 trips {
4643 audio_alert0: 4240 audio_alert0: trip-point0 {
4644 tempe 4241 temperature = <90000>;
4645 hyste 4242 hysteresis = <2000>;
4646 type 4243 type = "hot";
4647 }; 4244 };
4648 4245
4649 audio_crit: a !! 4246 audio_crit: audio_crit {
4650 tempe 4247 temperature = <110000>;
4651 hyste 4248 hysteresis = <2000>;
4652 type 4249 type = "critical";
4653 }; 4250 };
4654 }; 4251 };
4655 }; 4252 };
4656 4253
4657 ddr-thermal { 4254 ddr-thermal {
4658 polling-delay-passive 4255 polling-delay-passive = <250>;
>> 4256 polling-delay = <0>;
4659 4257
4660 thermal-sensors = <&t 4258 thermal-sensors = <&tsens1 3>;
4661 4259
4662 trips { 4260 trips {
4663 ddr_alert0: t 4261 ddr_alert0: trip-point0 {
4664 tempe 4262 temperature = <90000>;
4665 hyste 4263 hysteresis = <2000>;
4666 type 4264 type = "hot";
4667 }; 4265 };
4668 4266
4669 ddr_crit: ddr !! 4267 ddr_crit: ddr_crit {
4670 tempe 4268 temperature = <110000>;
4671 hyste 4269 hysteresis = <2000>;
4672 type 4270 type = "critical";
4673 }; 4271 };
4674 }; 4272 };
4675 }; 4273 };
4676 4274
4677 q6-hvx-thermal { 4275 q6-hvx-thermal {
4678 polling-delay-passive 4276 polling-delay-passive = <250>;
>> 4277 polling-delay = <0>;
4679 4278
4680 thermal-sensors = <&t 4279 thermal-sensors = <&tsens1 4>;
4681 4280
4682 trips { 4281 trips {
4683 q6_hvx_alert0 4282 q6_hvx_alert0: trip-point0 {
4684 tempe 4283 temperature = <90000>;
4685 hyste 4284 hysteresis = <2000>;
4686 type 4285 type = "hot";
4687 }; 4286 };
4688 4287
4689 q6_hvx_crit: !! 4288 q6_hvx_crit: q6_hvx_crit {
4690 tempe 4289 temperature = <110000>;
4691 hyste 4290 hysteresis = <2000>;
4692 type 4291 type = "critical";
4693 }; 4292 };
4694 }; 4293 };
4695 }; 4294 };
4696 4295
4697 camera-thermal { 4296 camera-thermal {
4698 polling-delay-passive 4297 polling-delay-passive = <250>;
>> 4298 polling-delay = <0>;
4699 4299
4700 thermal-sensors = <&t 4300 thermal-sensors = <&tsens1 5>;
4701 4301
4702 trips { 4302 trips {
4703 camera_alert0 4303 camera_alert0: trip-point0 {
4704 tempe 4304 temperature = <90000>;
4705 hyste 4305 hysteresis = <2000>;
4706 type 4306 type = "hot";
4707 }; 4307 };
4708 4308
4709 camera_crit: !! 4309 camera_crit: camera_crit {
4710 tempe 4310 temperature = <110000>;
4711 hyste 4311 hysteresis = <2000>;
4712 type 4312 type = "critical";
4713 }; 4313 };
4714 }; 4314 };
4715 }; 4315 };
4716 4316
4717 mdm-core-thermal { 4317 mdm-core-thermal {
4718 polling-delay-passive 4318 polling-delay-passive = <250>;
>> 4319 polling-delay = <0>;
4719 4320
4720 thermal-sensors = <&t 4321 thermal-sensors = <&tsens1 6>;
4721 4322
4722 trips { 4323 trips {
4723 mdm_alert0: t 4324 mdm_alert0: trip-point0 {
4724 tempe 4325 temperature = <90000>;
4725 hyste 4326 hysteresis = <2000>;
4726 type 4327 type = "hot";
4727 }; 4328 };
4728 4329
4729 mdm_crit: mdm !! 4330 mdm_crit: mdm_crit {
4730 tempe 4331 temperature = <110000>;
4731 hyste 4332 hysteresis = <2000>;
4732 type 4333 type = "critical";
4733 }; 4334 };
4734 }; 4335 };
4735 }; 4336 };
4736 4337
4737 mdm-dsp-thermal { 4338 mdm-dsp-thermal {
4738 polling-delay-passive 4339 polling-delay-passive = <250>;
>> 4340 polling-delay = <0>;
4739 4341
4740 thermal-sensors = <&t 4342 thermal-sensors = <&tsens1 7>;
4741 4343
4742 trips { 4344 trips {
4743 mdm_dsp_alert 4345 mdm_dsp_alert0: trip-point0 {
4744 tempe 4346 temperature = <90000>;
4745 hyste 4347 hysteresis = <2000>;
4746 type 4348 type = "hot";
4747 }; 4349 };
4748 4350
4749 mdm_dsp_crit: !! 4351 mdm_dsp_crit: mdm_dsp_crit {
4750 tempe 4352 temperature = <110000>;
4751 hyste 4353 hysteresis = <2000>;
4752 type 4354 type = "critical";
4753 }; 4355 };
4754 }; 4356 };
4755 }; 4357 };
4756 4358
4757 npu-thermal { 4359 npu-thermal {
4758 polling-delay-passive 4360 polling-delay-passive = <250>;
>> 4361 polling-delay = <0>;
4759 4362
4760 thermal-sensors = <&t 4363 thermal-sensors = <&tsens1 8>;
4761 4364
4762 trips { 4365 trips {
4763 npu_alert0: t 4366 npu_alert0: trip-point0 {
4764 tempe 4367 temperature = <90000>;
4765 hyste 4368 hysteresis = <2000>;
4766 type 4369 type = "hot";
4767 }; 4370 };
4768 4371
4769 npu_crit: npu !! 4372 npu_crit: npu_crit {
4770 tempe 4373 temperature = <110000>;
4771 hyste 4374 hysteresis = <2000>;
4772 type 4375 type = "critical";
4773 }; 4376 };
4774 }; 4377 };
4775 }; 4378 };
4776 4379
4777 video-thermal { 4380 video-thermal {
4778 polling-delay-passive 4381 polling-delay-passive = <250>;
>> 4382 polling-delay = <0>;
4779 4383
4780 thermal-sensors = <&t 4384 thermal-sensors = <&tsens1 9>;
4781 4385
4782 trips { 4386 trips {
4783 video_alert0: 4387 video_alert0: trip-point0 {
4784 tempe 4388 temperature = <90000>;
4785 hyste 4389 hysteresis = <2000>;
4786 type 4390 type = "hot";
4787 }; 4391 };
4788 4392
4789 video_crit: v !! 4393 video_crit: video_crit {
4790 tempe 4394 temperature = <110000>;
4791 hyste 4395 hysteresis = <2000>;
4792 type 4396 type = "critical";
4793 }; 4397 };
4794 }; 4398 };
4795 }; 4399 };
4796 }; 4400 };
4797 4401
4798 timer { 4402 timer {
4799 compatible = "arm,armv8-timer 4403 compatible = "arm,armv8-timer";
4800 interrupts = <GIC_PPI 1 IRQ_T 4404 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
4801 <GIC_PPI 2 IRQ_T 4405 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
4802 <GIC_PPI 3 IRQ_T 4406 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
4803 <GIC_PPI 0 IRQ_T 4407 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
4804 }; 4408 };
4805 }; 4409 };
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