1 // SPDX-License-Identifier: BSD-3-Clause 1 // SPDX-License-Identifier: BSD-3-Clause
2 /* 2 /*
3 * SC7180 SoC device tree source 3 * SC7180 SoC device tree source
4 * 4 *
5 * Copyright (c) 2019-2020, The Linux Foundati 5 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
6 */ 6 */
7 7
8 #include <dt-bindings/clock/qcom,dispcc-sc7180 8 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
9 #include <dt-bindings/clock/qcom,gcc-sc7180.h> 9 #include <dt-bindings/clock/qcom,gcc-sc7180.h>
10 #include <dt-bindings/clock/qcom,gpucc-sc7180. 10 #include <dt-bindings/clock/qcom,gpucc-sc7180.h>
11 #include <dt-bindings/clock/qcom,lpasscorecc-s 11 #include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h>
12 #include <dt-bindings/clock/qcom,rpmh.h> 12 #include <dt-bindings/clock/qcom,rpmh.h>
13 #include <dt-bindings/clock/qcom,videocc-sc718 13 #include <dt-bindings/clock/qcom,videocc-sc7180.h>
14 #include <dt-bindings/firmware/qcom,scm.h> <<
15 #include <dt-bindings/interconnect/qcom,icc.h> <<
16 #include <dt-bindings/interconnect/qcom,osm-l3 14 #include <dt-bindings/interconnect/qcom,osm-l3.h>
17 #include <dt-bindings/interconnect/qcom,sc7180 15 #include <dt-bindings/interconnect/qcom,sc7180.h>
18 #include <dt-bindings/interrupt-controller/arm 16 #include <dt-bindings/interrupt-controller/arm-gic.h>
19 #include <dt-bindings/phy/phy-qcom-qmp.h> <<
20 #include <dt-bindings/phy/phy-qcom-qusb2.h> 17 #include <dt-bindings/phy/phy-qcom-qusb2.h>
21 #include <dt-bindings/power/qcom-rpmpd.h> 18 #include <dt-bindings/power/qcom-rpmpd.h>
22 #include <dt-bindings/reset/qcom,sdm845-aoss.h 19 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
23 #include <dt-bindings/reset/qcom,sdm845-pdc.h> 20 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
24 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 21 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
25 #include <dt-bindings/soc/qcom,apr.h> <<
26 #include <dt-bindings/sound/qcom,q6afe.h> <<
27 #include <dt-bindings/thermal/thermal.h> 22 #include <dt-bindings/thermal/thermal.h>
28 23
29 / { 24 / {
30 interrupt-parent = <&intc>; 25 interrupt-parent = <&intc>;
31 26
32 #address-cells = <2>; 27 #address-cells = <2>;
33 #size-cells = <2>; 28 #size-cells = <2>;
34 29
>> 30 chosen { };
>> 31
35 aliases { 32 aliases {
36 mmc1 = &sdhc_1; 33 mmc1 = &sdhc_1;
37 mmc2 = &sdhc_2; 34 mmc2 = &sdhc_2;
38 i2c0 = &i2c0; 35 i2c0 = &i2c0;
39 i2c1 = &i2c1; 36 i2c1 = &i2c1;
40 i2c2 = &i2c2; 37 i2c2 = &i2c2;
41 i2c3 = &i2c3; 38 i2c3 = &i2c3;
42 i2c4 = &i2c4; 39 i2c4 = &i2c4;
43 i2c5 = &i2c5; 40 i2c5 = &i2c5;
44 i2c6 = &i2c6; 41 i2c6 = &i2c6;
45 i2c7 = &i2c7; 42 i2c7 = &i2c7;
46 i2c8 = &i2c8; 43 i2c8 = &i2c8;
47 i2c9 = &i2c9; 44 i2c9 = &i2c9;
48 i2c10 = &i2c10; 45 i2c10 = &i2c10;
49 i2c11 = &i2c11; 46 i2c11 = &i2c11;
50 spi0 = &spi0; 47 spi0 = &spi0;
51 spi1 = &spi1; 48 spi1 = &spi1;
52 spi3 = &spi3; 49 spi3 = &spi3;
53 spi5 = &spi5; 50 spi5 = &spi5;
54 spi6 = &spi6; 51 spi6 = &spi6;
55 spi8 = &spi8; 52 spi8 = &spi8;
56 spi10 = &spi10; 53 spi10 = &spi10;
57 spi11 = &spi11; 54 spi11 = &spi11;
58 }; 55 };
59 56
60 chosen { }; <<
61 <<
62 clocks { 57 clocks {
63 xo_board: xo-board { 58 xo_board: xo-board {
64 compatible = "fixed-cl 59 compatible = "fixed-clock";
65 clock-frequency = <384 60 clock-frequency = <38400000>;
66 #clock-cells = <0>; 61 #clock-cells = <0>;
67 }; 62 };
68 63
69 sleep_clk: sleep-clk { 64 sleep_clk: sleep-clk {
70 compatible = "fixed-cl 65 compatible = "fixed-clock";
71 clock-frequency = <327 66 clock-frequency = <32764>;
72 #clock-cells = <0>; 67 #clock-cells = <0>;
73 }; 68 };
74 }; 69 };
75 70
>> 71 reserved_memory: reserved-memory {
>> 72 #address-cells = <2>;
>> 73 #size-cells = <2>;
>> 74 ranges;
>> 75
>> 76 hyp_mem: memory@80000000 {
>> 77 reg = <0x0 0x80000000 0x0 0x600000>;
>> 78 no-map;
>> 79 };
>> 80
>> 81 xbl_mem: memory@80600000 {
>> 82 reg = <0x0 0x80600000 0x0 0x200000>;
>> 83 no-map;
>> 84 };
>> 85
>> 86 aop_mem: memory@80800000 {
>> 87 reg = <0x0 0x80800000 0x0 0x20000>;
>> 88 no-map;
>> 89 };
>> 90
>> 91 aop_cmd_db_mem: memory@80820000 {
>> 92 reg = <0x0 0x80820000 0x0 0x20000>;
>> 93 compatible = "qcom,cmd-db";
>> 94 no-map;
>> 95 };
>> 96
>> 97 sec_apps_mem: memory@808ff000 {
>> 98 reg = <0x0 0x808ff000 0x0 0x1000>;
>> 99 no-map;
>> 100 };
>> 101
>> 102 smem_mem: memory@80900000 {
>> 103 reg = <0x0 0x80900000 0x0 0x200000>;
>> 104 no-map;
>> 105 };
>> 106
>> 107 tz_mem: memory@80b00000 {
>> 108 reg = <0x0 0x80b00000 0x0 0x3900000>;
>> 109 no-map;
>> 110 };
>> 111
>> 112 ipa_fw_mem: memory@8b700000 {
>> 113 reg = <0 0x8b700000 0 0x10000>;
>> 114 no-map;
>> 115 };
>> 116
>> 117 rmtfs_mem: memory@94600000 {
>> 118 compatible = "qcom,rmtfs-mem";
>> 119 reg = <0x0 0x94600000 0x0 0x200000>;
>> 120 no-map;
>> 121
>> 122 qcom,client-id = <1>;
>> 123 qcom,vmid = <15>;
>> 124 };
>> 125 };
>> 126
76 cpus { 127 cpus {
77 #address-cells = <2>; 128 #address-cells = <2>;
78 #size-cells = <0>; 129 #size-cells = <0>;
79 130
80 CPU0: cpu@0 { 131 CPU0: cpu@0 {
81 device_type = "cpu"; 132 device_type = "cpu";
82 compatible = "qcom,kry 133 compatible = "qcom,kryo468";
83 reg = <0x0 0x0>; 134 reg = <0x0 0x0>;
84 clocks = <&cpufreq_hw <<
85 enable-method = "psci" 135 enable-method = "psci";
86 power-domains = <&CPU_ !! 136 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
87 power-domain-names = " !! 137 &LITTLE_CPU_SLEEP_1
>> 138 &CLUSTER_SLEEP_0>;
88 capacity-dmips-mhz = < 139 capacity-dmips-mhz = <415>;
89 dynamic-power-coeffici 140 dynamic-power-coefficient = <137>;
90 operating-points-v2 = 141 operating-points-v2 = <&cpu0_opp_table>;
91 interconnects = <&gem_ 142 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
92 <&osm_ 143 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
93 next-level-cache = <&L 144 next-level-cache = <&L2_0>;
94 #cooling-cells = <2>; 145 #cooling-cells = <2>;
95 qcom,freq-domain = <&c 146 qcom,freq-domain = <&cpufreq_hw 0>;
96 L2_0: l2-cache { 147 L2_0: l2-cache {
97 compatible = " 148 compatible = "cache";
98 cache-level = <<
99 cache-unified; <<
100 next-level-cac 149 next-level-cache = <&L3_0>;
101 L3_0: l3-cache 150 L3_0: l3-cache {
102 compat 151 compatible = "cache";
103 cache- <<
104 cache- <<
105 }; 152 };
106 }; 153 };
107 }; 154 };
108 155
109 CPU1: cpu@100 { 156 CPU1: cpu@100 {
110 device_type = "cpu"; 157 device_type = "cpu";
111 compatible = "qcom,kry 158 compatible = "qcom,kryo468";
112 reg = <0x0 0x100>; 159 reg = <0x0 0x100>;
113 clocks = <&cpufreq_hw <<
114 enable-method = "psci" 160 enable-method = "psci";
115 power-domains = <&CPU_ !! 161 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
116 power-domain-names = " !! 162 &LITTLE_CPU_SLEEP_1
>> 163 &CLUSTER_SLEEP_0>;
117 capacity-dmips-mhz = < 164 capacity-dmips-mhz = <415>;
118 dynamic-power-coeffici 165 dynamic-power-coefficient = <137>;
119 next-level-cache = <&L 166 next-level-cache = <&L2_100>;
120 operating-points-v2 = 167 operating-points-v2 = <&cpu0_opp_table>;
121 interconnects = <&gem_ 168 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
122 <&osm_ 169 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
123 #cooling-cells = <2>; 170 #cooling-cells = <2>;
124 qcom,freq-domain = <&c 171 qcom,freq-domain = <&cpufreq_hw 0>;
125 L2_100: l2-cache { 172 L2_100: l2-cache {
126 compatible = " 173 compatible = "cache";
127 cache-level = <<
128 cache-unified; <<
129 next-level-cac 174 next-level-cache = <&L3_0>;
130 }; 175 };
131 }; 176 };
132 177
133 CPU2: cpu@200 { 178 CPU2: cpu@200 {
134 device_type = "cpu"; 179 device_type = "cpu";
135 compatible = "qcom,kry 180 compatible = "qcom,kryo468";
136 reg = <0x0 0x200>; 181 reg = <0x0 0x200>;
137 clocks = <&cpufreq_hw <<
138 enable-method = "psci" 182 enable-method = "psci";
139 power-domains = <&CPU_ !! 183 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
140 power-domain-names = " !! 184 &LITTLE_CPU_SLEEP_1
>> 185 &CLUSTER_SLEEP_0>;
141 capacity-dmips-mhz = < 186 capacity-dmips-mhz = <415>;
142 dynamic-power-coeffici 187 dynamic-power-coefficient = <137>;
143 next-level-cache = <&L 188 next-level-cache = <&L2_200>;
144 operating-points-v2 = 189 operating-points-v2 = <&cpu0_opp_table>;
145 interconnects = <&gem_ 190 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
146 <&osm_ 191 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
147 #cooling-cells = <2>; 192 #cooling-cells = <2>;
148 qcom,freq-domain = <&c 193 qcom,freq-domain = <&cpufreq_hw 0>;
149 L2_200: l2-cache { 194 L2_200: l2-cache {
150 compatible = " 195 compatible = "cache";
151 cache-level = <<
152 cache-unified; <<
153 next-level-cac 196 next-level-cache = <&L3_0>;
154 }; 197 };
155 }; 198 };
156 199
157 CPU3: cpu@300 { 200 CPU3: cpu@300 {
158 device_type = "cpu"; 201 device_type = "cpu";
159 compatible = "qcom,kry 202 compatible = "qcom,kryo468";
160 reg = <0x0 0x300>; 203 reg = <0x0 0x300>;
161 clocks = <&cpufreq_hw <<
162 enable-method = "psci" 204 enable-method = "psci";
163 power-domains = <&CPU_ !! 205 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
164 power-domain-names = " !! 206 &LITTLE_CPU_SLEEP_1
>> 207 &CLUSTER_SLEEP_0>;
165 capacity-dmips-mhz = < 208 capacity-dmips-mhz = <415>;
166 dynamic-power-coeffici 209 dynamic-power-coefficient = <137>;
167 next-level-cache = <&L 210 next-level-cache = <&L2_300>;
168 operating-points-v2 = 211 operating-points-v2 = <&cpu0_opp_table>;
169 interconnects = <&gem_ 212 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
170 <&osm_ 213 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
171 #cooling-cells = <2>; 214 #cooling-cells = <2>;
172 qcom,freq-domain = <&c 215 qcom,freq-domain = <&cpufreq_hw 0>;
173 L2_300: l2-cache { 216 L2_300: l2-cache {
174 compatible = " 217 compatible = "cache";
175 cache-level = <<
176 cache-unified; <<
177 next-level-cac 218 next-level-cache = <&L3_0>;
178 }; 219 };
179 }; 220 };
180 221
181 CPU4: cpu@400 { 222 CPU4: cpu@400 {
182 device_type = "cpu"; 223 device_type = "cpu";
183 compatible = "qcom,kry 224 compatible = "qcom,kryo468";
184 reg = <0x0 0x400>; 225 reg = <0x0 0x400>;
185 clocks = <&cpufreq_hw <<
186 enable-method = "psci" 226 enable-method = "psci";
187 power-domains = <&CPU_ !! 227 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
188 power-domain-names = " !! 228 &LITTLE_CPU_SLEEP_1
>> 229 &CLUSTER_SLEEP_0>;
189 capacity-dmips-mhz = < 230 capacity-dmips-mhz = <415>;
190 dynamic-power-coeffici 231 dynamic-power-coefficient = <137>;
191 next-level-cache = <&L 232 next-level-cache = <&L2_400>;
192 operating-points-v2 = 233 operating-points-v2 = <&cpu0_opp_table>;
193 interconnects = <&gem_ 234 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
194 <&osm_ 235 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
195 #cooling-cells = <2>; 236 #cooling-cells = <2>;
196 qcom,freq-domain = <&c 237 qcom,freq-domain = <&cpufreq_hw 0>;
197 L2_400: l2-cache { 238 L2_400: l2-cache {
198 compatible = " 239 compatible = "cache";
199 cache-level = <<
200 cache-unified; <<
201 next-level-cac 240 next-level-cache = <&L3_0>;
202 }; 241 };
203 }; 242 };
204 243
205 CPU5: cpu@500 { 244 CPU5: cpu@500 {
206 device_type = "cpu"; 245 device_type = "cpu";
207 compatible = "qcom,kry 246 compatible = "qcom,kryo468";
208 reg = <0x0 0x500>; 247 reg = <0x0 0x500>;
209 clocks = <&cpufreq_hw <<
210 enable-method = "psci" 248 enable-method = "psci";
211 power-domains = <&CPU_ !! 249 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
212 power-domain-names = " !! 250 &LITTLE_CPU_SLEEP_1
>> 251 &CLUSTER_SLEEP_0>;
213 capacity-dmips-mhz = < 252 capacity-dmips-mhz = <415>;
214 dynamic-power-coeffici 253 dynamic-power-coefficient = <137>;
215 next-level-cache = <&L 254 next-level-cache = <&L2_500>;
216 operating-points-v2 = 255 operating-points-v2 = <&cpu0_opp_table>;
217 interconnects = <&gem_ 256 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
218 <&osm_ 257 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
219 #cooling-cells = <2>; 258 #cooling-cells = <2>;
220 qcom,freq-domain = <&c 259 qcom,freq-domain = <&cpufreq_hw 0>;
221 L2_500: l2-cache { 260 L2_500: l2-cache {
222 compatible = " 261 compatible = "cache";
223 cache-level = <<
224 cache-unified; <<
225 next-level-cac 262 next-level-cache = <&L3_0>;
226 }; 263 };
227 }; 264 };
228 265
229 CPU6: cpu@600 { 266 CPU6: cpu@600 {
230 device_type = "cpu"; 267 device_type = "cpu";
231 compatible = "qcom,kry 268 compatible = "qcom,kryo468";
232 reg = <0x0 0x600>; 269 reg = <0x0 0x600>;
233 clocks = <&cpufreq_hw <<
234 enable-method = "psci" 270 enable-method = "psci";
235 power-domains = <&CPU_ !! 271 cpu-idle-states = <&BIG_CPU_SLEEP_0
236 power-domain-names = " !! 272 &BIG_CPU_SLEEP_1
>> 273 &CLUSTER_SLEEP_0>;
237 capacity-dmips-mhz = < 274 capacity-dmips-mhz = <1024>;
238 dynamic-power-coeffici 275 dynamic-power-coefficient = <480>;
239 next-level-cache = <&L 276 next-level-cache = <&L2_600>;
240 operating-points-v2 = 277 operating-points-v2 = <&cpu6_opp_table>;
241 interconnects = <&gem_ 278 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
242 <&osm_ 279 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
243 #cooling-cells = <2>; 280 #cooling-cells = <2>;
244 qcom,freq-domain = <&c 281 qcom,freq-domain = <&cpufreq_hw 1>;
245 L2_600: l2-cache { 282 L2_600: l2-cache {
246 compatible = " 283 compatible = "cache";
247 cache-level = <<
248 cache-unified; <<
249 next-level-cac 284 next-level-cache = <&L3_0>;
250 }; 285 };
251 }; 286 };
252 287
253 CPU7: cpu@700 { 288 CPU7: cpu@700 {
254 device_type = "cpu"; 289 device_type = "cpu";
255 compatible = "qcom,kry 290 compatible = "qcom,kryo468";
256 reg = <0x0 0x700>; 291 reg = <0x0 0x700>;
257 clocks = <&cpufreq_hw <<
258 enable-method = "psci" 292 enable-method = "psci";
259 power-domains = <&CPU_ !! 293 cpu-idle-states = <&BIG_CPU_SLEEP_0
260 power-domain-names = " !! 294 &BIG_CPU_SLEEP_1
>> 295 &CLUSTER_SLEEP_0>;
261 capacity-dmips-mhz = < 296 capacity-dmips-mhz = <1024>;
262 dynamic-power-coeffici 297 dynamic-power-coefficient = <480>;
263 next-level-cache = <&L 298 next-level-cache = <&L2_700>;
264 operating-points-v2 = 299 operating-points-v2 = <&cpu6_opp_table>;
265 interconnects = <&gem_ 300 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
266 <&osm_ 301 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
267 #cooling-cells = <2>; 302 #cooling-cells = <2>;
268 qcom,freq-domain = <&c 303 qcom,freq-domain = <&cpufreq_hw 1>;
269 L2_700: l2-cache { 304 L2_700: l2-cache {
270 compatible = " 305 compatible = "cache";
271 cache-level = <<
272 cache-unified; <<
273 next-level-cac 306 next-level-cache = <&L3_0>;
274 }; 307 };
275 }; 308 };
276 309
277 cpu-map { 310 cpu-map {
278 cluster0 { 311 cluster0 {
279 core0 { 312 core0 {
280 cpu = 313 cpu = <&CPU0>;
281 }; 314 };
282 315
283 core1 { 316 core1 {
284 cpu = 317 cpu = <&CPU1>;
285 }; 318 };
286 319
287 core2 { 320 core2 {
288 cpu = 321 cpu = <&CPU2>;
289 }; 322 };
290 323
291 core3 { 324 core3 {
292 cpu = 325 cpu = <&CPU3>;
293 }; 326 };
294 327
295 core4 { 328 core4 {
296 cpu = 329 cpu = <&CPU4>;
297 }; 330 };
298 331
299 core5 { 332 core5 {
300 cpu = 333 cpu = <&CPU5>;
301 }; 334 };
302 335
303 core6 { 336 core6 {
304 cpu = 337 cpu = <&CPU6>;
305 }; 338 };
306 339
307 core7 { 340 core7 {
308 cpu = 341 cpu = <&CPU7>;
309 }; 342 };
310 }; 343 };
311 }; 344 };
312 345
313 idle_states: idle-states { !! 346 idle-states {
314 entry-method = "psci"; 347 entry-method = "psci";
315 348
316 LITTLE_CPU_SLEEP_0: cp 349 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
317 compatible = " 350 compatible = "arm,idle-state";
318 idle-state-nam 351 idle-state-name = "little-power-down";
319 arm,psci-suspe 352 arm,psci-suspend-param = <0x40000003>;
320 entry-latency- 353 entry-latency-us = <549>;
321 exit-latency-u 354 exit-latency-us = <901>;
322 min-residency- 355 min-residency-us = <1774>;
323 local-timer-st 356 local-timer-stop;
324 }; 357 };
325 358
326 LITTLE_CPU_SLEEP_1: cp 359 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
327 compatible = " 360 compatible = "arm,idle-state";
328 idle-state-nam 361 idle-state-name = "little-rail-power-down";
329 arm,psci-suspe 362 arm,psci-suspend-param = <0x40000004>;
330 entry-latency- 363 entry-latency-us = <702>;
331 exit-latency-u 364 exit-latency-us = <915>;
332 min-residency- 365 min-residency-us = <4001>;
333 local-timer-st 366 local-timer-stop;
334 }; 367 };
335 368
336 BIG_CPU_SLEEP_0: cpu-s 369 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
337 compatible = " 370 compatible = "arm,idle-state";
338 idle-state-nam 371 idle-state-name = "big-power-down";
339 arm,psci-suspe 372 arm,psci-suspend-param = <0x40000003>;
340 entry-latency- 373 entry-latency-us = <523>;
341 exit-latency-u 374 exit-latency-us = <1244>;
342 min-residency- 375 min-residency-us = <2207>;
343 local-timer-st 376 local-timer-stop;
344 }; 377 };
345 378
346 BIG_CPU_SLEEP_1: cpu-s 379 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
347 compatible = " 380 compatible = "arm,idle-state";
348 idle-state-nam 381 idle-state-name = "big-rail-power-down";
349 arm,psci-suspe 382 arm,psci-suspend-param = <0x40000004>;
350 entry-latency- 383 entry-latency-us = <526>;
351 exit-latency-u 384 exit-latency-us = <1854>;
352 min-residency- 385 min-residency-us = <5555>;
353 local-timer-st 386 local-timer-stop;
354 }; 387 };
355 }; <<
356 <<
357 domain_idle_states: domain-idl <<
358 CLUSTER_SLEEP_PC: clus <<
359 compatible = " <<
360 idle-state-nam <<
361 arm,psci-suspe <<
362 entry-latency- <<
363 exit-latency-u <<
364 min-residency- <<
365 }; <<
366 <<
367 CLUSTER_SLEEP_CX_RET: <<
368 compatible = " <<
369 idle-state-nam <<
370 arm,psci-suspe <<
371 entry-latency- <<
372 exit-latency-u <<
373 min-residency- <<
374 }; <<
375 388
376 CLUSTER_AOSS_SLEEP: cl !! 389 CLUSTER_SLEEP_0: cluster-sleep-0 {
377 compatible = " !! 390 compatible = "arm,idle-state";
378 idle-state-nam 391 idle-state-name = "cluster-power-down";
379 arm,psci-suspe !! 392 arm,psci-suspend-param = <0x40003444>;
380 entry-latency- 393 entry-latency-us = <3263>;
381 exit-latency-u 394 exit-latency-us = <6562>;
382 min-residency- !! 395 min-residency-us = <9926>;
>> 396 local-timer-stop;
383 }; 397 };
384 }; 398 };
385 }; 399 };
386 400
387 firmware { !! 401 cpu0_opp_table: cpu0_opp_table {
388 scm: scm { <<
389 compatible = "qcom,scm <<
390 }; <<
391 }; <<
392 <<
393 memory@80000000 { <<
394 device_type = "memory"; <<
395 /* We expect the bootloader to <<
396 reg = <0 0x80000000 0 0>; <<
397 }; <<
398 <<
399 cpu0_opp_table: opp-table-cpu0 { <<
400 compatible = "operating-points 402 compatible = "operating-points-v2";
401 opp-shared; 403 opp-shared;
402 404
403 cpu0_opp1: opp-300000000 { 405 cpu0_opp1: opp-300000000 {
404 opp-hz = /bits/ 64 <30 406 opp-hz = /bits/ 64 <300000000>;
405 opp-peak-kBps = <12000 407 opp-peak-kBps = <1200000 4800000>;
406 }; 408 };
407 409
408 cpu0_opp2: opp-576000000 { 410 cpu0_opp2: opp-576000000 {
409 opp-hz = /bits/ 64 <57 411 opp-hz = /bits/ 64 <576000000>;
410 opp-peak-kBps = <12000 412 opp-peak-kBps = <1200000 4800000>;
411 }; 413 };
412 414
413 cpu0_opp3: opp-768000000 { 415 cpu0_opp3: opp-768000000 {
414 opp-hz = /bits/ 64 <76 416 opp-hz = /bits/ 64 <768000000>;
415 opp-peak-kBps = <12000 417 opp-peak-kBps = <1200000 4800000>;
416 }; 418 };
417 419
418 cpu0_opp4: opp-1017600000 { 420 cpu0_opp4: opp-1017600000 {
419 opp-hz = /bits/ 64 <10 421 opp-hz = /bits/ 64 <1017600000>;
420 opp-peak-kBps = <18040 422 opp-peak-kBps = <1804000 8908800>;
421 }; 423 };
422 424
423 cpu0_opp5: opp-1248000000 { 425 cpu0_opp5: opp-1248000000 {
424 opp-hz = /bits/ 64 <12 426 opp-hz = /bits/ 64 <1248000000>;
425 opp-peak-kBps = <21880 427 opp-peak-kBps = <2188000 12902400>;
426 }; 428 };
427 429
428 cpu0_opp6: opp-1324800000 { 430 cpu0_opp6: opp-1324800000 {
429 opp-hz = /bits/ 64 <13 431 opp-hz = /bits/ 64 <1324800000>;
430 opp-peak-kBps = <21880 432 opp-peak-kBps = <2188000 12902400>;
431 }; 433 };
432 434
433 cpu0_opp7: opp-1516800000 { 435 cpu0_opp7: opp-1516800000 {
434 opp-hz = /bits/ 64 <15 436 opp-hz = /bits/ 64 <1516800000>;
435 opp-peak-kBps = <30720 437 opp-peak-kBps = <3072000 15052800>;
436 }; 438 };
437 439
438 cpu0_opp8: opp-1612800000 { 440 cpu0_opp8: opp-1612800000 {
439 opp-hz = /bits/ 64 <16 441 opp-hz = /bits/ 64 <1612800000>;
440 opp-peak-kBps = <30720 442 opp-peak-kBps = <3072000 15052800>;
441 }; 443 };
442 444
443 cpu0_opp9: opp-1708800000 { 445 cpu0_opp9: opp-1708800000 {
444 opp-hz = /bits/ 64 <17 446 opp-hz = /bits/ 64 <1708800000>;
445 opp-peak-kBps = <30720 447 opp-peak-kBps = <3072000 15052800>;
446 }; 448 };
447 449
448 cpu0_opp10: opp-1804800000 { 450 cpu0_opp10: opp-1804800000 {
449 opp-hz = /bits/ 64 <18 451 opp-hz = /bits/ 64 <1804800000>;
450 opp-peak-kBps = <40680 452 opp-peak-kBps = <4068000 22425600>;
451 }; 453 };
452 }; 454 };
453 455
454 cpu6_opp_table: opp-table-cpu6 { !! 456 cpu6_opp_table: cpu6_opp_table {
455 compatible = "operating-points 457 compatible = "operating-points-v2";
456 opp-shared; 458 opp-shared;
457 459
458 cpu6_opp1: opp-300000000 { 460 cpu6_opp1: opp-300000000 {
459 opp-hz = /bits/ 64 <30 461 opp-hz = /bits/ 64 <300000000>;
460 opp-peak-kBps = <21880 462 opp-peak-kBps = <2188000 8908800>;
461 }; 463 };
462 464
463 cpu6_opp2: opp-652800000 { 465 cpu6_opp2: opp-652800000 {
464 opp-hz = /bits/ 64 <65 466 opp-hz = /bits/ 64 <652800000>;
465 opp-peak-kBps = <21880 467 opp-peak-kBps = <2188000 8908800>;
466 }; 468 };
467 469
468 cpu6_opp3: opp-825600000 { 470 cpu6_opp3: opp-825600000 {
469 opp-hz = /bits/ 64 <82 471 opp-hz = /bits/ 64 <825600000>;
470 opp-peak-kBps = <21880 472 opp-peak-kBps = <2188000 8908800>;
471 }; 473 };
472 474
473 cpu6_opp4: opp-979200000 { 475 cpu6_opp4: opp-979200000 {
474 opp-hz = /bits/ 64 <97 476 opp-hz = /bits/ 64 <979200000>;
475 opp-peak-kBps = <21880 477 opp-peak-kBps = <2188000 8908800>;
476 }; 478 };
477 479
478 cpu6_opp5: opp-1113600000 { 480 cpu6_opp5: opp-1113600000 {
479 opp-hz = /bits/ 64 <11 481 opp-hz = /bits/ 64 <1113600000>;
480 opp-peak-kBps = <21880 482 opp-peak-kBps = <2188000 8908800>;
481 }; 483 };
482 484
483 cpu6_opp6: opp-1267200000 { 485 cpu6_opp6: opp-1267200000 {
484 opp-hz = /bits/ 64 <12 486 opp-hz = /bits/ 64 <1267200000>;
485 opp-peak-kBps = <40680 487 opp-peak-kBps = <4068000 12902400>;
486 }; 488 };
487 489
488 cpu6_opp7: opp-1555200000 { 490 cpu6_opp7: opp-1555200000 {
489 opp-hz = /bits/ 64 <15 491 opp-hz = /bits/ 64 <1555200000>;
490 opp-peak-kBps = <40680 492 opp-peak-kBps = <4068000 15052800>;
491 }; 493 };
492 494
493 cpu6_opp8: opp-1708800000 { 495 cpu6_opp8: opp-1708800000 {
494 opp-hz = /bits/ 64 <17 496 opp-hz = /bits/ 64 <1708800000>;
495 opp-peak-kBps = <62200 497 opp-peak-kBps = <6220000 19353600>;
496 }; 498 };
497 499
498 cpu6_opp9: opp-1843200000 { 500 cpu6_opp9: opp-1843200000 {
499 opp-hz = /bits/ 64 <18 501 opp-hz = /bits/ 64 <1843200000>;
500 opp-peak-kBps = <62200 502 opp-peak-kBps = <6220000 19353600>;
501 }; 503 };
502 504
503 cpu6_opp10: opp-1900800000 { 505 cpu6_opp10: opp-1900800000 {
504 opp-hz = /bits/ 64 <19 506 opp-hz = /bits/ 64 <1900800000>;
505 opp-peak-kBps = <62200 507 opp-peak-kBps = <6220000 22425600>;
506 }; 508 };
507 509
508 cpu6_opp11: opp-1996800000 { 510 cpu6_opp11: opp-1996800000 {
509 opp-hz = /bits/ 64 <19 511 opp-hz = /bits/ 64 <1996800000>;
510 opp-peak-kBps = <62200 512 opp-peak-kBps = <6220000 22425600>;
511 }; 513 };
512 514
513 cpu6_opp12: opp-2112000000 { 515 cpu6_opp12: opp-2112000000 {
514 opp-hz = /bits/ 64 <21 516 opp-hz = /bits/ 64 <2112000000>;
515 opp-peak-kBps = <62200 517 opp-peak-kBps = <6220000 22425600>;
516 }; 518 };
517 519
518 cpu6_opp13: opp-2208000000 { 520 cpu6_opp13: opp-2208000000 {
519 opp-hz = /bits/ 64 <22 521 opp-hz = /bits/ 64 <2208000000>;
520 opp-peak-kBps = <72160 522 opp-peak-kBps = <7216000 22425600>;
521 }; 523 };
522 524
523 cpu6_opp14: opp-2323200000 { 525 cpu6_opp14: opp-2323200000 {
524 opp-hz = /bits/ 64 <23 526 opp-hz = /bits/ 64 <2323200000>;
525 opp-peak-kBps = <72160 527 opp-peak-kBps = <7216000 22425600>;
526 }; 528 };
527 529
528 cpu6_opp15: opp-2400000000 { 530 cpu6_opp15: opp-2400000000 {
529 opp-hz = /bits/ 64 <24 531 opp-hz = /bits/ 64 <2400000000>;
530 opp-peak-kBps = <85320 532 opp-peak-kBps = <8532000 23347200>;
531 }; 533 };
532 534
533 cpu6_opp16: opp-2553600000 { 535 cpu6_opp16: opp-2553600000 {
534 opp-hz = /bits/ 64 <25 536 opp-hz = /bits/ 64 <2553600000>;
535 opp-peak-kBps = <85320 537 opp-peak-kBps = <8532000 23347200>;
536 }; 538 };
537 }; 539 };
538 540
539 qspi_opp_table: opp-table-qspi { !! 541 memory@80000000 {
540 compatible = "operating-points !! 542 device_type = "memory";
541 !! 543 /* We expect the bootloader to fill in the size */
542 opp-75000000 { !! 544 reg = <0 0x80000000 0 0>;
543 opp-hz = /bits/ 64 <75 <<
544 required-opps = <&rpmh <<
545 }; <<
546 <<
547 opp-150000000 { <<
548 opp-hz = /bits/ 64 <15 <<
549 required-opps = <&rpmh <<
550 }; <<
551 <<
552 opp-300000000 { <<
553 opp-hz = /bits/ 64 <30 <<
554 required-opps = <&rpmh <<
555 }; <<
556 }; <<
557 <<
558 qup_opp_table: opp-table-qup { <<
559 compatible = "operating-points <<
560 <<
561 opp-75000000 { <<
562 opp-hz = /bits/ 64 <75 <<
563 required-opps = <&rpmh <<
564 }; <<
565 <<
566 opp-100000000 { <<
567 opp-hz = /bits/ 64 <10 <<
568 required-opps = <&rpmh <<
569 }; <<
570 <<
571 opp-128000000 { <<
572 opp-hz = /bits/ 64 <12 <<
573 required-opps = <&rpmh <<
574 }; <<
575 }; 545 };
576 546
577 pmu { 547 pmu {
578 compatible = "arm,armv8-pmuv3" 548 compatible = "arm,armv8-pmuv3";
579 interrupts = <GIC_PPI 5 IRQ_TY 549 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
580 }; 550 };
581 551
582 psci { !! 552 firmware {
583 compatible = "arm,psci-1.0"; !! 553 scm {
584 method = "smc"; !! 554 compatible = "qcom,scm-sc7180", "qcom,scm";
585 <<
586 CPU_PD0: cpu0 { <<
587 #power-domain-cells = <<
588 power-domains = <&CLUS <<
589 domain-idle-states = < <<
590 }; <<
591 <<
592 CPU_PD1: cpu1 { <<
593 #power-domain-cells = <<
594 power-domains = <&CLUS <<
595 domain-idle-states = < <<
596 }; <<
597 <<
598 CPU_PD2: cpu2 { <<
599 #power-domain-cells = <<
600 power-domains = <&CLUS <<
601 domain-idle-states = < <<
602 }; <<
603 <<
604 CPU_PD3: cpu3 { <<
605 #power-domain-cells = <<
606 power-domains = <&CLUS <<
607 domain-idle-states = < <<
608 }; <<
609 <<
610 CPU_PD4: cpu4 { <<
611 #power-domain-cells = <<
612 power-domains = <&CLUS <<
613 domain-idle-states = < <<
614 }; <<
615 <<
616 CPU_PD5: cpu5 { <<
617 #power-domain-cells = <<
618 power-domains = <&CLUS <<
619 domain-idle-states = < <<
620 }; <<
621 <<
622 CPU_PD6: cpu6 { <<
623 #power-domain-cells = <<
624 power-domains = <&CLUS <<
625 domain-idle-states = < <<
626 }; <<
627 <<
628 CPU_PD7: cpu7 { <<
629 #power-domain-cells = <<
630 power-domains = <&CLUS <<
631 domain-idle-states = < <<
632 }; <<
633 <<
634 CLUSTER_PD: cpu-cluster0 { <<
635 #power-domain-cells = <<
636 domain-idle-states = < <<
637 <<
638 <<
639 }; 555 };
640 }; 556 };
641 557
642 reserved_memory: reserved-memory { !! 558 tcsr_mutex: hwlock {
643 #address-cells = <2>; !! 559 compatible = "qcom,tcsr-mutex";
644 #size-cells = <2>; !! 560 syscon = <&tcsr_mutex_regs 0 0x1000>;
645 ranges; !! 561 #hwlock-cells = <1>;
646 <<
647 hyp_mem: memory@80000000 { <<
648 reg = <0x0 0x80000000 <<
649 no-map; <<
650 }; <<
651 <<
652 xbl_mem: memory@80600000 { <<
653 reg = <0x0 0x80600000 <<
654 no-map; <<
655 }; <<
656 <<
657 aop_mem: memory@80800000 { <<
658 reg = <0x0 0x80800000 <<
659 no-map; <<
660 }; <<
661 <<
662 aop_cmd_db_mem: memory@8082000 <<
663 reg = <0x0 0x80820000 <<
664 compatible = "qcom,cmd <<
665 no-map; <<
666 }; <<
667 <<
668 sec_apps_mem: memory@808ff000 <<
669 reg = <0x0 0x808ff000 <<
670 no-map; <<
671 }; <<
672 <<
673 smem_mem: memory@80900000 { <<
674 reg = <0x0 0x80900000 <<
675 no-map; <<
676 }; <<
677 <<
678 tz_mem: memory@80b00000 { <<
679 reg = <0x0 0x80b00000 <<
680 no-map; <<
681 }; <<
682 <<
683 ipa_fw_mem: memory@8b700000 { <<
684 reg = <0 0x8b700000 0 <<
685 no-map; <<
686 }; <<
687 <<
688 rmtfs_mem: memory@94600000 { <<
689 compatible = "qcom,rmt <<
690 reg = <0x0 0x94600000 <<
691 no-map; <<
692 <<
693 qcom,client-id = <1>; <<
694 qcom,vmid = <QCOM_SCM_ <<
695 }; <<
696 }; 562 };
697 563
698 smem { 564 smem {
699 compatible = "qcom,smem"; 565 compatible = "qcom,smem";
700 memory-region = <&smem_mem>; 566 memory-region = <&smem_mem>;
701 hwlocks = <&tcsr_mutex 3>; 567 hwlocks = <&tcsr_mutex 3>;
702 }; 568 };
703 569
704 smp2p-cdsp { 570 smp2p-cdsp {
705 compatible = "qcom,smp2p"; 571 compatible = "qcom,smp2p";
706 qcom,smem = <94>, <432>; 572 qcom,smem = <94>, <432>;
707 573
708 interrupts = <GIC_SPI 576 IRQ_ 574 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
709 575
710 mboxes = <&apss_shared 6>; 576 mboxes = <&apss_shared 6>;
711 577
712 qcom,local-pid = <0>; 578 qcom,local-pid = <0>;
713 qcom,remote-pid = <5>; 579 qcom,remote-pid = <5>;
714 580
715 cdsp_smp2p_out: master-kernel 581 cdsp_smp2p_out: master-kernel {
716 qcom,entry-name = "mas 582 qcom,entry-name = "master-kernel";
717 #qcom,smem-state-cells 583 #qcom,smem-state-cells = <1>;
718 }; 584 };
719 585
720 cdsp_smp2p_in: slave-kernel { 586 cdsp_smp2p_in: slave-kernel {
721 qcom,entry-name = "sla 587 qcom,entry-name = "slave-kernel";
722 588
723 interrupt-controller; 589 interrupt-controller;
724 #interrupt-cells = <2> 590 #interrupt-cells = <2>;
725 }; 591 };
726 }; 592 };
727 593
728 smp2p-lpass { 594 smp2p-lpass {
729 compatible = "qcom,smp2p"; 595 compatible = "qcom,smp2p";
730 qcom,smem = <443>, <429>; 596 qcom,smem = <443>, <429>;
731 597
732 interrupts = <GIC_SPI 158 IRQ_ 598 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
733 599
734 mboxes = <&apss_shared 10>; 600 mboxes = <&apss_shared 10>;
735 601
736 qcom,local-pid = <0>; 602 qcom,local-pid = <0>;
737 qcom,remote-pid = <2>; 603 qcom,remote-pid = <2>;
738 604
739 adsp_smp2p_out: master-kernel 605 adsp_smp2p_out: master-kernel {
740 qcom,entry-name = "mas 606 qcom,entry-name = "master-kernel";
741 #qcom,smem-state-cells 607 #qcom,smem-state-cells = <1>;
742 }; 608 };
743 609
744 adsp_smp2p_in: slave-kernel { 610 adsp_smp2p_in: slave-kernel {
745 qcom,entry-name = "sla 611 qcom,entry-name = "slave-kernel";
746 612
747 interrupt-controller; 613 interrupt-controller;
748 #interrupt-cells = <2> 614 #interrupt-cells = <2>;
749 }; 615 };
750 }; 616 };
751 617
752 smp2p-mpss { 618 smp2p-mpss {
753 compatible = "qcom,smp2p"; 619 compatible = "qcom,smp2p";
754 qcom,smem = <435>, <428>; 620 qcom,smem = <435>, <428>;
755 interrupts = <GIC_SPI 451 IRQ_ 621 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
756 mboxes = <&apss_shared 14>; 622 mboxes = <&apss_shared 14>;
757 qcom,local-pid = <0>; 623 qcom,local-pid = <0>;
758 qcom,remote-pid = <1>; 624 qcom,remote-pid = <1>;
759 625
760 modem_smp2p_out: master-kernel 626 modem_smp2p_out: master-kernel {
761 qcom,entry-name = "mas 627 qcom,entry-name = "master-kernel";
762 #qcom,smem-state-cells 628 #qcom,smem-state-cells = <1>;
763 }; 629 };
764 630
765 modem_smp2p_in: slave-kernel { 631 modem_smp2p_in: slave-kernel {
766 qcom,entry-name = "sla 632 qcom,entry-name = "slave-kernel";
767 interrupt-controller; 633 interrupt-controller;
768 #interrupt-cells = <2> 634 #interrupt-cells = <2>;
769 }; 635 };
770 636
771 ipa_smp2p_out: ipa-ap-to-modem 637 ipa_smp2p_out: ipa-ap-to-modem {
772 qcom,entry-name = "ipa 638 qcom,entry-name = "ipa";
773 #qcom,smem-state-cells 639 #qcom,smem-state-cells = <1>;
774 }; 640 };
775 641
776 ipa_smp2p_in: ipa-modem-to-ap 642 ipa_smp2p_in: ipa-modem-to-ap {
777 qcom,entry-name = "ipa 643 qcom,entry-name = "ipa";
778 interrupt-controller; 644 interrupt-controller;
779 #interrupt-cells = <2> 645 #interrupt-cells = <2>;
780 }; 646 };
781 }; 647 };
782 648
>> 649 psci {
>> 650 compatible = "arm,psci-1.0";
>> 651 method = "smc";
>> 652 };
>> 653
783 soc: soc@0 { 654 soc: soc@0 {
784 #address-cells = <2>; 655 #address-cells = <2>;
785 #size-cells = <2>; 656 #size-cells = <2>;
786 ranges = <0 0 0 0 0x10 0>; 657 ranges = <0 0 0 0 0x10 0>;
787 dma-ranges = <0 0 0 0 0x10 0>; 658 dma-ranges = <0 0 0 0 0x10 0>;
788 compatible = "simple-bus"; 659 compatible = "simple-bus";
789 660
790 gcc: clock-controller@100000 { 661 gcc: clock-controller@100000 {
791 compatible = "qcom,gcc 662 compatible = "qcom,gcc-sc7180";
792 reg = <0 0x00100000 0 663 reg = <0 0x00100000 0 0x1f0000>;
793 clocks = <&rpmhcc RPMH 664 clocks = <&rpmhcc RPMH_CXO_CLK>,
794 <&rpmhcc RPMH 665 <&rpmhcc RPMH_CXO_CLK_A>,
795 <&sleep_clk>; 666 <&sleep_clk>;
796 clock-names = "bi_tcxo 667 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
797 #clock-cells = <1>; 668 #clock-cells = <1>;
798 #reset-cells = <1>; 669 #reset-cells = <1>;
799 #power-domain-cells = 670 #power-domain-cells = <1>;
800 power-domains = <&rpmh <<
801 }; 671 };
802 672
803 qfprom: efuse@784000 { 673 qfprom: efuse@784000 {
804 compatible = "qcom,sc7 674 compatible = "qcom,sc7180-qfprom", "qcom,qfprom";
805 reg = <0 0x00784000 0 675 reg = <0 0x00784000 0 0x7a0>,
806 <0 0x00780000 0 676 <0 0x00780000 0 0x7a0>,
807 <0 0x00782000 0 677 <0 0x00782000 0 0x100>,
808 <0 0x00786000 0 678 <0 0x00786000 0 0x1fff>;
809 679
810 clocks = <&gcc GCC_SEC 680 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>;
811 clock-names = "core"; 681 clock-names = "core";
812 #address-cells = <1>; 682 #address-cells = <1>;
813 #size-cells = <1>; 683 #size-cells = <1>;
814 684
815 qusb2p_hstx_trim: hstx 685 qusb2p_hstx_trim: hstx-trim-primary@25b {
816 reg = <0x25b 0 686 reg = <0x25b 0x1>;
817 bits = <1 3>; 687 bits = <1 3>;
818 }; 688 };
819 689
820 gpu_speed_bin: gpu-spe !! 690 gpu_speed_bin: gpu_speed_bin@1d2 {
821 reg = <0x1d2 0 691 reg = <0x1d2 0x2>;
822 bits = <5 8>; 692 bits = <5 8>;
823 }; 693 };
824 }; 694 };
825 695
826 sdhc_1: mmc@7c4000 { !! 696 sdhc_1: sdhci@7c4000 {
827 compatible = "qcom,sc7 697 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
828 reg = <0 0x007c4000 0 !! 698 reg = <0 0x7c4000 0 0x1000>,
829 <0 0x007c5000 !! 699 <0 0x07c5000 0 0x1000>;
830 reg-names = "hc", "cqh 700 reg-names = "hc", "cqhci";
831 701
832 iommus = <&apps_smmu 0 702 iommus = <&apps_smmu 0x60 0x0>;
833 interrupts = <GIC_SPI 703 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
834 <GIC_S 704 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
835 interrupt-names = "hc_ 705 interrupt-names = "hc_irq", "pwr_irq";
836 706
837 clocks = <&gcc GCC_SDC !! 707 clocks = <&gcc GCC_SDCC1_APPS_CLK>,
838 <&gcc GCC_SDC !! 708 <&gcc GCC_SDCC1_AHB_CLK>,
839 <&rpmhcc RPMH 709 <&rpmhcc RPMH_CXO_CLK>;
840 clock-names = "iface", !! 710 clock-names = "core", "iface", "xo";
841 interconnects = <&aggr 711 interconnects = <&aggre1_noc MASTER_EMMC 0 &mc_virt SLAVE_EBI1 0>,
842 <&gem_ 712 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_EMMC_CFG 0>;
843 interconnect-names = " 713 interconnect-names = "sdhc-ddr","cpu-sdhc";
844 power-domains = <&rpmh 714 power-domains = <&rpmhpd SC7180_CX>;
845 operating-points-v2 = 715 operating-points-v2 = <&sdhc1_opp_table>;
846 716
847 bus-width = <8>; 717 bus-width = <8>;
848 non-removable; 718 non-removable;
849 supports-cqe; 719 supports-cqe;
850 720
851 mmc-ddr-1_8v; 721 mmc-ddr-1_8v;
852 mmc-hs200-1_8v; 722 mmc-hs200-1_8v;
853 mmc-hs400-1_8v; 723 mmc-hs400-1_8v;
854 mmc-hs400-enhanced-str 724 mmc-hs400-enhanced-strobe;
855 725
856 status = "disabled"; 726 status = "disabled";
857 727
858 sdhc1_opp_table: opp-t !! 728 sdhc1_opp_table: sdhc1-opp-table {
859 compatible = " 729 compatible = "operating-points-v2";
860 730
861 opp-100000000 731 opp-100000000 {
862 opp-hz 732 opp-hz = /bits/ 64 <100000000>;
863 requir 733 required-opps = <&rpmhpd_opp_low_svs>;
864 opp-pe 734 opp-peak-kBps = <1800000 600000>;
865 opp-av 735 opp-avg-kBps = <100000 0>;
866 }; 736 };
867 737
868 opp-384000000 738 opp-384000000 {
869 opp-hz 739 opp-hz = /bits/ 64 <384000000>;
870 requir 740 required-opps = <&rpmhpd_opp_nom>;
871 opp-pe 741 opp-peak-kBps = <5400000 1600000>;
872 opp-av 742 opp-avg-kBps = <390000 0>;
873 }; 743 };
874 }; 744 };
875 }; 745 };
876 746
>> 747 qup_opp_table: qup-opp-table {
>> 748 compatible = "operating-points-v2";
>> 749
>> 750 opp-75000000 {
>> 751 opp-hz = /bits/ 64 <75000000>;
>> 752 required-opps = <&rpmhpd_opp_low_svs>;
>> 753 };
>> 754
>> 755 opp-100000000 {
>> 756 opp-hz = /bits/ 64 <100000000>;
>> 757 required-opps = <&rpmhpd_opp_svs>;
>> 758 };
>> 759
>> 760 opp-128000000 {
>> 761 opp-hz = /bits/ 64 <128000000>;
>> 762 required-opps = <&rpmhpd_opp_nom>;
>> 763 };
>> 764 };
>> 765
877 qupv3_id_0: geniqup@8c0000 { 766 qupv3_id_0: geniqup@8c0000 {
878 compatible = "qcom,gen 767 compatible = "qcom,geni-se-qup";
879 reg = <0 0x008c0000 0 768 reg = <0 0x008c0000 0 0x6000>;
880 clock-names = "m-ahb", 769 clock-names = "m-ahb", "s-ahb";
881 clocks = <&gcc GCC_QUP 770 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
882 <&gcc GCC_QUP 771 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
883 #address-cells = <2>; 772 #address-cells = <2>;
884 #size-cells = <2>; 773 #size-cells = <2>;
885 ranges; 774 ranges;
886 iommus = <&apps_smmu 0 775 iommus = <&apps_smmu 0x43 0x0>;
887 status = "disabled"; 776 status = "disabled";
888 777
889 i2c0: i2c@880000 { 778 i2c0: i2c@880000 {
890 compatible = " 779 compatible = "qcom,geni-i2c";
891 reg = <0 0x008 780 reg = <0 0x00880000 0 0x4000>;
892 clock-names = 781 clock-names = "se";
893 clocks = <&gcc 782 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
894 pinctrl-names 783 pinctrl-names = "default";
895 pinctrl-0 = <& 784 pinctrl-0 = <&qup_i2c0_default>;
896 interrupts = < 785 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
897 #address-cells 786 #address-cells = <1>;
898 #size-cells = 787 #size-cells = <0>;
899 interconnects 788 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
900 789 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
901 790 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
902 interconnect-n 791 interconnect-names = "qup-core", "qup-config",
903 792 "qup-memory";
904 power-domains 793 power-domains = <&rpmhpd SC7180_CX>;
905 required-opps 794 required-opps = <&rpmhpd_opp_low_svs>;
906 status = "disa 795 status = "disabled";
907 }; 796 };
908 797
909 spi0: spi@880000 { 798 spi0: spi@880000 {
910 compatible = " 799 compatible = "qcom,geni-spi";
911 reg = <0 0x008 800 reg = <0 0x00880000 0 0x4000>;
912 clock-names = 801 clock-names = "se";
913 clocks = <&gcc 802 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
914 pinctrl-names 803 pinctrl-names = "default";
915 pinctrl-0 = <& !! 804 pinctrl-0 = <&qup_spi0_default>;
916 interrupts = < 805 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
917 #address-cells 806 #address-cells = <1>;
918 #size-cells = 807 #size-cells = <0>;
919 power-domains 808 power-domains = <&rpmhpd SC7180_CX>;
920 operating-poin 809 operating-points-v2 = <&qup_opp_table>;
921 interconnects 810 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
922 811 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
923 interconnect-n 812 interconnect-names = "qup-core", "qup-config";
924 status = "disa 813 status = "disabled";
925 }; 814 };
926 815
927 uart0: serial@880000 { 816 uart0: serial@880000 {
928 compatible = " 817 compatible = "qcom,geni-uart";
929 reg = <0 0x008 818 reg = <0 0x00880000 0 0x4000>;
930 clock-names = 819 clock-names = "se";
931 clocks = <&gcc 820 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
932 pinctrl-names 821 pinctrl-names = "default";
933 pinctrl-0 = <& 822 pinctrl-0 = <&qup_uart0_default>;
934 interrupts = < 823 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
935 power-domains 824 power-domains = <&rpmhpd SC7180_CX>;
936 operating-poin 825 operating-points-v2 = <&qup_opp_table>;
937 interconnects 826 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
938 827 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
939 interconnect-n 828 interconnect-names = "qup-core", "qup-config";
940 status = "disa 829 status = "disabled";
941 }; 830 };
942 831
943 i2c1: i2c@884000 { 832 i2c1: i2c@884000 {
944 compatible = " 833 compatible = "qcom,geni-i2c";
945 reg = <0 0x008 834 reg = <0 0x00884000 0 0x4000>;
946 clock-names = 835 clock-names = "se";
947 clocks = <&gcc 836 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
948 pinctrl-names 837 pinctrl-names = "default";
949 pinctrl-0 = <& 838 pinctrl-0 = <&qup_i2c1_default>;
950 interrupts = < 839 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
951 #address-cells 840 #address-cells = <1>;
952 #size-cells = 841 #size-cells = <0>;
953 interconnects 842 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
954 843 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
955 844 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
956 interconnect-n 845 interconnect-names = "qup-core", "qup-config",
957 846 "qup-memory";
958 power-domains 847 power-domains = <&rpmhpd SC7180_CX>;
959 required-opps 848 required-opps = <&rpmhpd_opp_low_svs>;
960 status = "disa 849 status = "disabled";
961 }; 850 };
962 851
963 spi1: spi@884000 { 852 spi1: spi@884000 {
964 compatible = " 853 compatible = "qcom,geni-spi";
965 reg = <0 0x008 854 reg = <0 0x00884000 0 0x4000>;
966 clock-names = 855 clock-names = "se";
967 clocks = <&gcc 856 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
968 pinctrl-names 857 pinctrl-names = "default";
969 pinctrl-0 = <& !! 858 pinctrl-0 = <&qup_spi1_default>;
970 interrupts = < 859 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
971 #address-cells 860 #address-cells = <1>;
972 #size-cells = 861 #size-cells = <0>;
973 power-domains 862 power-domains = <&rpmhpd SC7180_CX>;
974 operating-poin 863 operating-points-v2 = <&qup_opp_table>;
975 interconnects 864 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
976 865 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
977 interconnect-n 866 interconnect-names = "qup-core", "qup-config";
978 status = "disa 867 status = "disabled";
979 }; 868 };
980 869
981 uart1: serial@884000 { 870 uart1: serial@884000 {
982 compatible = " 871 compatible = "qcom,geni-uart";
983 reg = <0 0x008 872 reg = <0 0x00884000 0 0x4000>;
984 clock-names = 873 clock-names = "se";
985 clocks = <&gcc 874 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
986 pinctrl-names 875 pinctrl-names = "default";
987 pinctrl-0 = <& 876 pinctrl-0 = <&qup_uart1_default>;
988 interrupts = < 877 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
989 power-domains 878 power-domains = <&rpmhpd SC7180_CX>;
990 operating-poin 879 operating-points-v2 = <&qup_opp_table>;
991 interconnects 880 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
992 881 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
993 interconnect-n 882 interconnect-names = "qup-core", "qup-config";
994 status = "disa 883 status = "disabled";
995 }; 884 };
996 885
997 i2c2: i2c@888000 { 886 i2c2: i2c@888000 {
998 compatible = " 887 compatible = "qcom,geni-i2c";
999 reg = <0 0x008 888 reg = <0 0x00888000 0 0x4000>;
1000 clock-names = 889 clock-names = "se";
1001 clocks = <&gc 890 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1002 pinctrl-names 891 pinctrl-names = "default";
1003 pinctrl-0 = < 892 pinctrl-0 = <&qup_i2c2_default>;
1004 interrupts = 893 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1005 #address-cell 894 #address-cells = <1>;
1006 #size-cells = 895 #size-cells = <0>;
1007 interconnects 896 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1008 897 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1009 898 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1010 interconnect- 899 interconnect-names = "qup-core", "qup-config",
1011 900 "qup-memory";
1012 power-domains 901 power-domains = <&rpmhpd SC7180_CX>;
1013 required-opps 902 required-opps = <&rpmhpd_opp_low_svs>;
1014 status = "dis 903 status = "disabled";
1015 }; 904 };
1016 905
1017 uart2: serial@888000 906 uart2: serial@888000 {
1018 compatible = 907 compatible = "qcom,geni-uart";
1019 reg = <0 0x00 908 reg = <0 0x00888000 0 0x4000>;
1020 clock-names = 909 clock-names = "se";
1021 clocks = <&gc 910 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1022 pinctrl-names 911 pinctrl-names = "default";
1023 pinctrl-0 = < 912 pinctrl-0 = <&qup_uart2_default>;
1024 interrupts = 913 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1025 power-domains 914 power-domains = <&rpmhpd SC7180_CX>;
1026 operating-poi 915 operating-points-v2 = <&qup_opp_table>;
1027 interconnects 916 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1028 917 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1029 interconnect- 918 interconnect-names = "qup-core", "qup-config";
1030 status = "dis 919 status = "disabled";
1031 }; 920 };
1032 921
1033 i2c3: i2c@88c000 { 922 i2c3: i2c@88c000 {
1034 compatible = 923 compatible = "qcom,geni-i2c";
1035 reg = <0 0x00 924 reg = <0 0x0088c000 0 0x4000>;
1036 clock-names = 925 clock-names = "se";
1037 clocks = <&gc 926 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1038 pinctrl-names 927 pinctrl-names = "default";
1039 pinctrl-0 = < 928 pinctrl-0 = <&qup_i2c3_default>;
1040 interrupts = 929 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1041 #address-cell 930 #address-cells = <1>;
1042 #size-cells = 931 #size-cells = <0>;
1043 interconnects 932 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1044 933 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1045 934 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1046 interconnect- 935 interconnect-names = "qup-core", "qup-config",
1047 936 "qup-memory";
1048 power-domains 937 power-domains = <&rpmhpd SC7180_CX>;
1049 required-opps 938 required-opps = <&rpmhpd_opp_low_svs>;
1050 status = "dis 939 status = "disabled";
1051 }; 940 };
1052 941
1053 spi3: spi@88c000 { 942 spi3: spi@88c000 {
1054 compatible = 943 compatible = "qcom,geni-spi";
1055 reg = <0 0x00 944 reg = <0 0x0088c000 0 0x4000>;
1056 clock-names = 945 clock-names = "se";
1057 clocks = <&gc 946 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1058 pinctrl-names 947 pinctrl-names = "default";
1059 pinctrl-0 = < !! 948 pinctrl-0 = <&qup_spi3_default>;
1060 interrupts = 949 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1061 #address-cell 950 #address-cells = <1>;
1062 #size-cells = 951 #size-cells = <0>;
1063 power-domains 952 power-domains = <&rpmhpd SC7180_CX>;
1064 operating-poi 953 operating-points-v2 = <&qup_opp_table>;
1065 interconnects 954 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1066 955 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1067 interconnect- 956 interconnect-names = "qup-core", "qup-config";
1068 status = "dis 957 status = "disabled";
1069 }; 958 };
1070 959
1071 uart3: serial@88c000 960 uart3: serial@88c000 {
1072 compatible = 961 compatible = "qcom,geni-uart";
1073 reg = <0 0x00 962 reg = <0 0x0088c000 0 0x4000>;
1074 clock-names = 963 clock-names = "se";
1075 clocks = <&gc 964 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1076 pinctrl-names 965 pinctrl-names = "default";
1077 pinctrl-0 = < 966 pinctrl-0 = <&qup_uart3_default>;
1078 interrupts = 967 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1079 power-domains 968 power-domains = <&rpmhpd SC7180_CX>;
1080 operating-poi 969 operating-points-v2 = <&qup_opp_table>;
1081 interconnects 970 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1082 971 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1083 interconnect- 972 interconnect-names = "qup-core", "qup-config";
1084 status = "dis 973 status = "disabled";
1085 }; 974 };
1086 975
1087 i2c4: i2c@890000 { 976 i2c4: i2c@890000 {
1088 compatible = 977 compatible = "qcom,geni-i2c";
1089 reg = <0 0x00 978 reg = <0 0x00890000 0 0x4000>;
1090 clock-names = 979 clock-names = "se";
1091 clocks = <&gc 980 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1092 pinctrl-names 981 pinctrl-names = "default";
1093 pinctrl-0 = < 982 pinctrl-0 = <&qup_i2c4_default>;
1094 interrupts = 983 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1095 #address-cell 984 #address-cells = <1>;
1096 #size-cells = 985 #size-cells = <0>;
1097 interconnects 986 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1098 987 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1099 988 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1100 interconnect- 989 interconnect-names = "qup-core", "qup-config",
1101 990 "qup-memory";
1102 power-domains 991 power-domains = <&rpmhpd SC7180_CX>;
1103 required-opps 992 required-opps = <&rpmhpd_opp_low_svs>;
1104 status = "dis 993 status = "disabled";
1105 }; 994 };
1106 995
1107 uart4: serial@890000 996 uart4: serial@890000 {
1108 compatible = 997 compatible = "qcom,geni-uart";
1109 reg = <0 0x00 998 reg = <0 0x00890000 0 0x4000>;
1110 clock-names = 999 clock-names = "se";
1111 clocks = <&gc 1000 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1112 pinctrl-names 1001 pinctrl-names = "default";
1113 pinctrl-0 = < 1002 pinctrl-0 = <&qup_uart4_default>;
1114 interrupts = 1003 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1115 power-domains 1004 power-domains = <&rpmhpd SC7180_CX>;
1116 operating-poi 1005 operating-points-v2 = <&qup_opp_table>;
1117 interconnects 1006 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1118 1007 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1119 interconnect- 1008 interconnect-names = "qup-core", "qup-config";
1120 status = "dis 1009 status = "disabled";
1121 }; 1010 };
1122 1011
1123 i2c5: i2c@894000 { 1012 i2c5: i2c@894000 {
1124 compatible = 1013 compatible = "qcom,geni-i2c";
1125 reg = <0 0x00 1014 reg = <0 0x00894000 0 0x4000>;
1126 clock-names = 1015 clock-names = "se";
1127 clocks = <&gc 1016 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1128 pinctrl-names 1017 pinctrl-names = "default";
1129 pinctrl-0 = < 1018 pinctrl-0 = <&qup_i2c5_default>;
1130 interrupts = 1019 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1131 #address-cell 1020 #address-cells = <1>;
1132 #size-cells = 1021 #size-cells = <0>;
1133 interconnects 1022 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1134 1023 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1135 1024 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1136 interconnect- 1025 interconnect-names = "qup-core", "qup-config",
1137 1026 "qup-memory";
1138 power-domains 1027 power-domains = <&rpmhpd SC7180_CX>;
1139 required-opps 1028 required-opps = <&rpmhpd_opp_low_svs>;
1140 status = "dis 1029 status = "disabled";
1141 }; 1030 };
1142 1031
1143 spi5: spi@894000 { 1032 spi5: spi@894000 {
1144 compatible = 1033 compatible = "qcom,geni-spi";
1145 reg = <0 0x00 1034 reg = <0 0x00894000 0 0x4000>;
1146 clock-names = 1035 clock-names = "se";
1147 clocks = <&gc 1036 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1148 pinctrl-names 1037 pinctrl-names = "default";
1149 pinctrl-0 = < !! 1038 pinctrl-0 = <&qup_spi5_default>;
1150 interrupts = 1039 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1151 #address-cell 1040 #address-cells = <1>;
1152 #size-cells = 1041 #size-cells = <0>;
1153 power-domains 1042 power-domains = <&rpmhpd SC7180_CX>;
1154 operating-poi 1043 operating-points-v2 = <&qup_opp_table>;
1155 interconnects 1044 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1156 1045 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1157 interconnect- 1046 interconnect-names = "qup-core", "qup-config";
1158 status = "dis 1047 status = "disabled";
1159 }; 1048 };
1160 1049
1161 uart5: serial@894000 1050 uart5: serial@894000 {
1162 compatible = 1051 compatible = "qcom,geni-uart";
1163 reg = <0 0x00 1052 reg = <0 0x00894000 0 0x4000>;
1164 clock-names = 1053 clock-names = "se";
1165 clocks = <&gc 1054 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1166 pinctrl-names 1055 pinctrl-names = "default";
1167 pinctrl-0 = < 1056 pinctrl-0 = <&qup_uart5_default>;
1168 interrupts = 1057 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1169 power-domains 1058 power-domains = <&rpmhpd SC7180_CX>;
1170 operating-poi 1059 operating-points-v2 = <&qup_opp_table>;
1171 interconnects 1060 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1172 1061 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1173 interconnect- 1062 interconnect-names = "qup-core", "qup-config";
1174 status = "dis 1063 status = "disabled";
1175 }; 1064 };
1176 }; 1065 };
1177 1066
1178 qupv3_id_1: geniqup@ac0000 { 1067 qupv3_id_1: geniqup@ac0000 {
1179 compatible = "qcom,ge 1068 compatible = "qcom,geni-se-qup";
1180 reg = <0 0x00ac0000 0 1069 reg = <0 0x00ac0000 0 0x6000>;
1181 clock-names = "m-ahb" 1070 clock-names = "m-ahb", "s-ahb";
1182 clocks = <&gcc GCC_QU 1071 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1183 <&gcc GCC_QU 1072 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1184 #address-cells = <2>; 1073 #address-cells = <2>;
1185 #size-cells = <2>; 1074 #size-cells = <2>;
1186 ranges; 1075 ranges;
1187 iommus = <&apps_smmu 1076 iommus = <&apps_smmu 0x4c3 0x0>;
1188 status = "disabled"; 1077 status = "disabled";
1189 1078
1190 i2c6: i2c@a80000 { 1079 i2c6: i2c@a80000 {
1191 compatible = 1080 compatible = "qcom,geni-i2c";
1192 reg = <0 0x00 1081 reg = <0 0x00a80000 0 0x4000>;
1193 clock-names = 1082 clock-names = "se";
1194 clocks = <&gc 1083 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1195 pinctrl-names 1084 pinctrl-names = "default";
1196 pinctrl-0 = < 1085 pinctrl-0 = <&qup_i2c6_default>;
1197 interrupts = 1086 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1198 #address-cell 1087 #address-cells = <1>;
1199 #size-cells = 1088 #size-cells = <0>;
1200 interconnects 1089 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1201 1090 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1202 1091 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1203 interconnect- 1092 interconnect-names = "qup-core", "qup-config",
1204 1093 "qup-memory";
1205 power-domains 1094 power-domains = <&rpmhpd SC7180_CX>;
1206 required-opps 1095 required-opps = <&rpmhpd_opp_low_svs>;
1207 status = "dis 1096 status = "disabled";
1208 }; 1097 };
1209 1098
1210 spi6: spi@a80000 { 1099 spi6: spi@a80000 {
1211 compatible = 1100 compatible = "qcom,geni-spi";
1212 reg = <0 0x00 1101 reg = <0 0x00a80000 0 0x4000>;
1213 clock-names = 1102 clock-names = "se";
1214 clocks = <&gc 1103 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1215 pinctrl-names 1104 pinctrl-names = "default";
1216 pinctrl-0 = < !! 1105 pinctrl-0 = <&qup_spi6_default>;
1217 interrupts = 1106 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1218 #address-cell 1107 #address-cells = <1>;
1219 #size-cells = 1108 #size-cells = <0>;
1220 power-domains 1109 power-domains = <&rpmhpd SC7180_CX>;
1221 operating-poi 1110 operating-points-v2 = <&qup_opp_table>;
1222 interconnects 1111 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1223 1112 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1224 interconnect- 1113 interconnect-names = "qup-core", "qup-config";
1225 status = "dis 1114 status = "disabled";
1226 }; 1115 };
1227 1116
1228 uart6: serial@a80000 1117 uart6: serial@a80000 {
1229 compatible = 1118 compatible = "qcom,geni-uart";
1230 reg = <0 0x00 1119 reg = <0 0x00a80000 0 0x4000>;
1231 clock-names = 1120 clock-names = "se";
1232 clocks = <&gc 1121 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1233 pinctrl-names 1122 pinctrl-names = "default";
1234 pinctrl-0 = < 1123 pinctrl-0 = <&qup_uart6_default>;
1235 interrupts = 1124 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1236 power-domains 1125 power-domains = <&rpmhpd SC7180_CX>;
1237 operating-poi 1126 operating-points-v2 = <&qup_opp_table>;
1238 interconnects 1127 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1239 1128 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1240 interconnect- 1129 interconnect-names = "qup-core", "qup-config";
1241 status = "dis 1130 status = "disabled";
1242 }; 1131 };
1243 1132
1244 i2c7: i2c@a84000 { 1133 i2c7: i2c@a84000 {
1245 compatible = 1134 compatible = "qcom,geni-i2c";
1246 reg = <0 0x00 1135 reg = <0 0x00a84000 0 0x4000>;
1247 clock-names = 1136 clock-names = "se";
1248 clocks = <&gc 1137 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1249 pinctrl-names 1138 pinctrl-names = "default";
1250 pinctrl-0 = < 1139 pinctrl-0 = <&qup_i2c7_default>;
1251 interrupts = 1140 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1252 #address-cell 1141 #address-cells = <1>;
1253 #size-cells = 1142 #size-cells = <0>;
1254 interconnects 1143 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1255 1144 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1256 1145 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1257 interconnect- 1146 interconnect-names = "qup-core", "qup-config",
1258 1147 "qup-memory";
1259 power-domains 1148 power-domains = <&rpmhpd SC7180_CX>;
1260 required-opps 1149 required-opps = <&rpmhpd_opp_low_svs>;
1261 status = "dis 1150 status = "disabled";
1262 }; 1151 };
1263 1152
1264 uart7: serial@a84000 1153 uart7: serial@a84000 {
1265 compatible = 1154 compatible = "qcom,geni-uart";
1266 reg = <0 0x00 1155 reg = <0 0x00a84000 0 0x4000>;
1267 clock-names = 1156 clock-names = "se";
1268 clocks = <&gc 1157 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1269 pinctrl-names 1158 pinctrl-names = "default";
1270 pinctrl-0 = < 1159 pinctrl-0 = <&qup_uart7_default>;
1271 interrupts = 1160 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1272 power-domains 1161 power-domains = <&rpmhpd SC7180_CX>;
1273 operating-poi 1162 operating-points-v2 = <&qup_opp_table>;
1274 interconnects 1163 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1275 1164 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1276 interconnect- 1165 interconnect-names = "qup-core", "qup-config";
1277 status = "dis 1166 status = "disabled";
1278 }; 1167 };
1279 1168
1280 i2c8: i2c@a88000 { 1169 i2c8: i2c@a88000 {
1281 compatible = 1170 compatible = "qcom,geni-i2c";
1282 reg = <0 0x00 1171 reg = <0 0x00a88000 0 0x4000>;
1283 clock-names = 1172 clock-names = "se";
1284 clocks = <&gc 1173 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1285 pinctrl-names 1174 pinctrl-names = "default";
1286 pinctrl-0 = < 1175 pinctrl-0 = <&qup_i2c8_default>;
1287 interrupts = 1176 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1288 #address-cell 1177 #address-cells = <1>;
1289 #size-cells = 1178 #size-cells = <0>;
1290 interconnects 1179 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1291 1180 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1292 1181 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1293 interconnect- 1182 interconnect-names = "qup-core", "qup-config",
1294 1183 "qup-memory";
1295 power-domains 1184 power-domains = <&rpmhpd SC7180_CX>;
1296 required-opps 1185 required-opps = <&rpmhpd_opp_low_svs>;
1297 status = "dis 1186 status = "disabled";
1298 }; 1187 };
1299 1188
1300 spi8: spi@a88000 { 1189 spi8: spi@a88000 {
1301 compatible = 1190 compatible = "qcom,geni-spi";
1302 reg = <0 0x00 1191 reg = <0 0x00a88000 0 0x4000>;
1303 clock-names = 1192 clock-names = "se";
1304 clocks = <&gc 1193 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1305 pinctrl-names 1194 pinctrl-names = "default";
1306 pinctrl-0 = < !! 1195 pinctrl-0 = <&qup_spi8_default>;
1307 interrupts = 1196 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1308 #address-cell 1197 #address-cells = <1>;
1309 #size-cells = 1198 #size-cells = <0>;
1310 power-domains 1199 power-domains = <&rpmhpd SC7180_CX>;
1311 operating-poi 1200 operating-points-v2 = <&qup_opp_table>;
1312 interconnects 1201 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1313 1202 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1314 interconnect- 1203 interconnect-names = "qup-core", "qup-config";
1315 status = "dis 1204 status = "disabled";
1316 }; 1205 };
1317 1206
1318 uart8: serial@a88000 1207 uart8: serial@a88000 {
1319 compatible = 1208 compatible = "qcom,geni-debug-uart";
1320 reg = <0 0x00 1209 reg = <0 0x00a88000 0 0x4000>;
1321 clock-names = 1210 clock-names = "se";
1322 clocks = <&gc 1211 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1323 pinctrl-names 1212 pinctrl-names = "default";
1324 pinctrl-0 = < 1213 pinctrl-0 = <&qup_uart8_default>;
1325 interrupts = 1214 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1326 power-domains 1215 power-domains = <&rpmhpd SC7180_CX>;
1327 operating-poi 1216 operating-points-v2 = <&qup_opp_table>;
1328 interconnects 1217 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1329 1218 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1330 interconnect- 1219 interconnect-names = "qup-core", "qup-config";
1331 status = "dis 1220 status = "disabled";
1332 }; 1221 };
1333 1222
1334 i2c9: i2c@a8c000 { 1223 i2c9: i2c@a8c000 {
1335 compatible = 1224 compatible = "qcom,geni-i2c";
1336 reg = <0 0x00 1225 reg = <0 0x00a8c000 0 0x4000>;
1337 clock-names = 1226 clock-names = "se";
1338 clocks = <&gc 1227 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1339 pinctrl-names 1228 pinctrl-names = "default";
1340 pinctrl-0 = < 1229 pinctrl-0 = <&qup_i2c9_default>;
1341 interrupts = 1230 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1342 #address-cell 1231 #address-cells = <1>;
1343 #size-cells = 1232 #size-cells = <0>;
1344 interconnects 1233 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1345 1234 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1346 1235 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1347 interconnect- 1236 interconnect-names = "qup-core", "qup-config",
1348 1237 "qup-memory";
1349 power-domains 1238 power-domains = <&rpmhpd SC7180_CX>;
1350 required-opps 1239 required-opps = <&rpmhpd_opp_low_svs>;
1351 status = "dis 1240 status = "disabled";
1352 }; 1241 };
1353 1242
1354 uart9: serial@a8c000 1243 uart9: serial@a8c000 {
1355 compatible = 1244 compatible = "qcom,geni-uart";
1356 reg = <0 0x00 1245 reg = <0 0x00a8c000 0 0x4000>;
1357 clock-names = 1246 clock-names = "se";
1358 clocks = <&gc 1247 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1359 pinctrl-names 1248 pinctrl-names = "default";
1360 pinctrl-0 = < 1249 pinctrl-0 = <&qup_uart9_default>;
1361 interrupts = 1250 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1362 power-domains 1251 power-domains = <&rpmhpd SC7180_CX>;
1363 operating-poi 1252 operating-points-v2 = <&qup_opp_table>;
1364 interconnects 1253 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1365 1254 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1366 interconnect- 1255 interconnect-names = "qup-core", "qup-config";
1367 status = "dis 1256 status = "disabled";
1368 }; 1257 };
1369 1258
1370 i2c10: i2c@a90000 { 1259 i2c10: i2c@a90000 {
1371 compatible = 1260 compatible = "qcom,geni-i2c";
1372 reg = <0 0x00 1261 reg = <0 0x00a90000 0 0x4000>;
1373 clock-names = 1262 clock-names = "se";
1374 clocks = <&gc 1263 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1375 pinctrl-names 1264 pinctrl-names = "default";
1376 pinctrl-0 = < 1265 pinctrl-0 = <&qup_i2c10_default>;
1377 interrupts = 1266 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1378 #address-cell 1267 #address-cells = <1>;
1379 #size-cells = 1268 #size-cells = <0>;
1380 interconnects 1269 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1381 1270 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1382 1271 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1383 interconnect- 1272 interconnect-names = "qup-core", "qup-config",
1384 1273 "qup-memory";
1385 power-domains 1274 power-domains = <&rpmhpd SC7180_CX>;
1386 required-opps 1275 required-opps = <&rpmhpd_opp_low_svs>;
1387 status = "dis 1276 status = "disabled";
1388 }; 1277 };
1389 1278
1390 spi10: spi@a90000 { 1279 spi10: spi@a90000 {
1391 compatible = 1280 compatible = "qcom,geni-spi";
1392 reg = <0 0x00 1281 reg = <0 0x00a90000 0 0x4000>;
1393 clock-names = 1282 clock-names = "se";
1394 clocks = <&gc 1283 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1395 pinctrl-names 1284 pinctrl-names = "default";
1396 pinctrl-0 = < !! 1285 pinctrl-0 = <&qup_spi10_default>;
1397 interrupts = 1286 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1398 #address-cell 1287 #address-cells = <1>;
1399 #size-cells = 1288 #size-cells = <0>;
1400 power-domains 1289 power-domains = <&rpmhpd SC7180_CX>;
1401 operating-poi 1290 operating-points-v2 = <&qup_opp_table>;
1402 interconnects 1291 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1403 1292 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1404 interconnect- 1293 interconnect-names = "qup-core", "qup-config";
1405 status = "dis 1294 status = "disabled";
1406 }; 1295 };
1407 1296
1408 uart10: serial@a90000 1297 uart10: serial@a90000 {
1409 compatible = 1298 compatible = "qcom,geni-uart";
1410 reg = <0 0x00 1299 reg = <0 0x00a90000 0 0x4000>;
1411 clock-names = 1300 clock-names = "se";
1412 clocks = <&gc 1301 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1413 pinctrl-names 1302 pinctrl-names = "default";
1414 pinctrl-0 = < 1303 pinctrl-0 = <&qup_uart10_default>;
1415 interrupts = 1304 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1416 power-domains 1305 power-domains = <&rpmhpd SC7180_CX>;
1417 operating-poi 1306 operating-points-v2 = <&qup_opp_table>;
1418 interconnects 1307 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1419 1308 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1420 interconnect- 1309 interconnect-names = "qup-core", "qup-config";
1421 status = "dis 1310 status = "disabled";
1422 }; 1311 };
1423 1312
1424 i2c11: i2c@a94000 { 1313 i2c11: i2c@a94000 {
1425 compatible = 1314 compatible = "qcom,geni-i2c";
1426 reg = <0 0x00 1315 reg = <0 0x00a94000 0 0x4000>;
1427 clock-names = 1316 clock-names = "se";
1428 clocks = <&gc 1317 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1429 pinctrl-names 1318 pinctrl-names = "default";
1430 pinctrl-0 = < 1319 pinctrl-0 = <&qup_i2c11_default>;
1431 interrupts = 1320 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1432 #address-cell 1321 #address-cells = <1>;
1433 #size-cells = 1322 #size-cells = <0>;
1434 interconnects 1323 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1435 1324 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1436 1325 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1437 interconnect- 1326 interconnect-names = "qup-core", "qup-config",
1438 1327 "qup-memory";
1439 power-domains 1328 power-domains = <&rpmhpd SC7180_CX>;
1440 required-opps 1329 required-opps = <&rpmhpd_opp_low_svs>;
1441 status = "dis 1330 status = "disabled";
1442 }; 1331 };
1443 1332
1444 spi11: spi@a94000 { 1333 spi11: spi@a94000 {
1445 compatible = 1334 compatible = "qcom,geni-spi";
1446 reg = <0 0x00 1335 reg = <0 0x00a94000 0 0x4000>;
1447 clock-names = 1336 clock-names = "se";
1448 clocks = <&gc 1337 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1449 pinctrl-names 1338 pinctrl-names = "default";
1450 pinctrl-0 = < !! 1339 pinctrl-0 = <&qup_spi11_default>;
1451 interrupts = 1340 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1452 #address-cell 1341 #address-cells = <1>;
1453 #size-cells = 1342 #size-cells = <0>;
1454 power-domains 1343 power-domains = <&rpmhpd SC7180_CX>;
1455 operating-poi 1344 operating-points-v2 = <&qup_opp_table>;
1456 interconnects 1345 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1457 1346 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1458 interconnect- 1347 interconnect-names = "qup-core", "qup-config";
1459 status = "dis 1348 status = "disabled";
1460 }; 1349 };
1461 1350
1462 uart11: serial@a94000 1351 uart11: serial@a94000 {
1463 compatible = 1352 compatible = "qcom,geni-uart";
1464 reg = <0 0x00 1353 reg = <0 0x00a94000 0 0x4000>;
1465 clock-names = 1354 clock-names = "se";
1466 clocks = <&gc 1355 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1467 pinctrl-names 1356 pinctrl-names = "default";
1468 pinctrl-0 = < 1357 pinctrl-0 = <&qup_uart11_default>;
1469 interrupts = 1358 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1470 power-domains 1359 power-domains = <&rpmhpd SC7180_CX>;
1471 operating-poi 1360 operating-points-v2 = <&qup_opp_table>;
1472 interconnects 1361 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1473 1362 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1474 interconnect- 1363 interconnect-names = "qup-core", "qup-config";
1475 status = "dis 1364 status = "disabled";
1476 }; 1365 };
1477 }; 1366 };
1478 1367
1479 config_noc: interconnect@1500 1368 config_noc: interconnect@1500000 {
1480 compatible = "qcom,sc 1369 compatible = "qcom,sc7180-config-noc";
1481 reg = <0 0x01500000 0 1370 reg = <0 0x01500000 0 0x28000>;
1482 #interconnect-cells = 1371 #interconnect-cells = <2>;
1483 qcom,bcm-voters = <&a 1372 qcom,bcm-voters = <&apps_bcm_voter>;
1484 }; 1373 };
1485 1374
1486 system_noc: interconnect@1620 1375 system_noc: interconnect@1620000 {
1487 compatible = "qcom,sc 1376 compatible = "qcom,sc7180-system-noc";
1488 reg = <0 0x01620000 0 1377 reg = <0 0x01620000 0 0x17080>;
1489 #interconnect-cells = 1378 #interconnect-cells = <2>;
1490 qcom,bcm-voters = <&a 1379 qcom,bcm-voters = <&apps_bcm_voter>;
1491 }; 1380 };
1492 1381
1493 mc_virt: interconnect@1638000 1382 mc_virt: interconnect@1638000 {
1494 compatible = "qcom,sc 1383 compatible = "qcom,sc7180-mc-virt";
1495 reg = <0 0x01638000 0 1384 reg = <0 0x01638000 0 0x1000>;
1496 #interconnect-cells = 1385 #interconnect-cells = <2>;
1497 qcom,bcm-voters = <&a 1386 qcom,bcm-voters = <&apps_bcm_voter>;
1498 }; 1387 };
1499 1388
1500 qup_virt: interconnect@165000 1389 qup_virt: interconnect@1650000 {
1501 compatible = "qcom,sc 1390 compatible = "qcom,sc7180-qup-virt";
1502 reg = <0 0x01650000 0 1391 reg = <0 0x01650000 0 0x1000>;
1503 #interconnect-cells = 1392 #interconnect-cells = <2>;
1504 qcom,bcm-voters = <&a 1393 qcom,bcm-voters = <&apps_bcm_voter>;
1505 }; 1394 };
1506 1395
1507 aggre1_noc: interconnect@16e0 1396 aggre1_noc: interconnect@16e0000 {
1508 compatible = "qcom,sc 1397 compatible = "qcom,sc7180-aggre1-noc";
1509 reg = <0 0x016e0000 0 1398 reg = <0 0x016e0000 0 0x15080>;
1510 #interconnect-cells = 1399 #interconnect-cells = <2>;
1511 qcom,bcm-voters = <&a 1400 qcom,bcm-voters = <&apps_bcm_voter>;
1512 }; 1401 };
1513 1402
1514 aggre2_noc: interconnect@1705 1403 aggre2_noc: interconnect@1705000 {
1515 compatible = "qcom,sc 1404 compatible = "qcom,sc7180-aggre2-noc";
1516 reg = <0 0x01705000 0 1405 reg = <0 0x01705000 0 0x9000>;
1517 #interconnect-cells = 1406 #interconnect-cells = <2>;
1518 qcom,bcm-voters = <&a 1407 qcom,bcm-voters = <&apps_bcm_voter>;
1519 }; 1408 };
1520 1409
1521 compute_noc: interconnect@170 1410 compute_noc: interconnect@170e000 {
1522 compatible = "qcom,sc 1411 compatible = "qcom,sc7180-compute-noc";
1523 reg = <0 0x0170e000 0 1412 reg = <0 0x0170e000 0 0x6000>;
1524 #interconnect-cells = 1413 #interconnect-cells = <2>;
1525 qcom,bcm-voters = <&a 1414 qcom,bcm-voters = <&apps_bcm_voter>;
1526 }; 1415 };
1527 1416
1528 mmss_noc: interconnect@174000 1417 mmss_noc: interconnect@1740000 {
1529 compatible = "qcom,sc 1418 compatible = "qcom,sc7180-mmss-noc";
1530 reg = <0 0x01740000 0 1419 reg = <0 0x01740000 0 0x1c100>;
1531 #interconnect-cells = 1420 #interconnect-cells = <2>;
1532 qcom,bcm-voters = <&a 1421 qcom,bcm-voters = <&apps_bcm_voter>;
1533 }; 1422 };
1534 1423
1535 ufs_mem_hc: ufshc@1d84000 { !! 1424 ipa_virt: interconnect@1e00000 {
1536 compatible = "qcom,sc !! 1425 compatible = "qcom,sc7180-ipa-virt";
1537 "jedec,u !! 1426 reg = <0 0x01e00000 0 0x1000>;
1538 reg = <0 0x01d84000 0 !! 1427 #interconnect-cells = <2>;
1539 interrupts = <GIC_SPI !! 1428 qcom,bcm-voters = <&apps_bcm_voter>;
1540 phys = <&ufs_mem_phy> <<
1541 phy-names = "ufsphy"; <<
1542 lanes-per-direction = <<
1543 #reset-cells = <1>; <<
1544 resets = <&gcc GCC_UF <<
1545 reset-names = "rst"; <<
1546 <<
1547 power-domains = <&gcc <<
1548 <<
1549 iommus = <&apps_smmu <<
1550 <<
1551 clock-names = "core_c <<
1552 "bus_ag <<
1553 "iface_ <<
1554 "core_c <<
1555 "ref_cl <<
1556 "tx_lan <<
1557 "rx_lan <<
1558 clocks = <&gcc GCC_UF <<
1559 <&gcc GCC_AG <<
1560 <&gcc GCC_UF <<
1561 <&gcc GCC_UF <<
1562 <&rpmhcc RPM <<
1563 <&gcc GCC_UF <<
1564 <&gcc GCC_UF <<
1565 freq-table-hz = <5000 <<
1566 <0 0> <<
1567 <0 0> <<
1568 <3750 <<
1569 <0 0> <<
1570 <0 0> <<
1571 <0 0> <<
1572 <<
1573 interconnects = <&agg <<
1574 &mc_ <<
1575 <&gem <<
1576 &con <<
1577 interconnect-names = <<
1578 <<
1579 qcom,ice = <&ice>; <<
1580 <<
1581 status = "disabled"; <<
1582 }; <<
1583 <<
1584 ufs_mem_phy: phy@1d87000 { <<
1585 compatible = "qcom,sc <<
1586 reg = <0 0x01d87000 0 <<
1587 clocks = <&rpmhcc RPM <<
1588 <&gcc GCC_UF <<
1589 <&gcc GCC_UF <<
1590 clock-names = "ref", <<
1591 "ref_au <<
1592 "qref"; <<
1593 power-domains = <&gcc <<
1594 resets = <&ufs_mem_hc <<
1595 reset-names = "ufsphy <<
1596 #phy-cells = <0>; <<
1597 status = "disabled"; <<
1598 }; <<
1599 <<
1600 ice: crypto@1d90000 { <<
1601 compatible = "qcom,sc <<
1602 "qcom,in <<
1603 reg = <0 0x01d90000 0 <<
1604 clocks = <&gcc GCC_UF <<
1605 }; 1429 };
1606 1430
1607 ipa: ipa@1e40000 { 1431 ipa: ipa@1e40000 {
1608 compatible = "qcom,sc 1432 compatible = "qcom,sc7180-ipa";
1609 1433
1610 iommus = <&apps_smmu 1434 iommus = <&apps_smmu 0x440 0x0>,
1611 <&apps_smmu 1435 <&apps_smmu 0x442 0x0>;
1612 reg = <0 0x01e40000 0 !! 1436 reg = <0 0x1e40000 0 0x7000>,
1613 <0 0x01e47000 0 !! 1437 <0 0x1e47000 0 0x2000>,
1614 <0 0x01e04000 0 !! 1438 <0 0x1e04000 0 0x2c000>;
1615 reg-names = "ipa-reg" 1439 reg-names = "ipa-reg",
1616 "ipa-shar 1440 "ipa-shared",
1617 "gsi"; 1441 "gsi";
1618 1442
1619 interrupts-extended = 1443 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
1620 1444 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
1621 1445 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1622 1446 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
1623 interrupt-names = "ip 1447 interrupt-names = "ipa",
1624 "gs 1448 "gsi",
1625 "ip 1449 "ipa-clock-query",
1626 "ip 1450 "ipa-setup-ready";
1627 1451
1628 clocks = <&rpmhcc RPM 1452 clocks = <&rpmhcc RPMH_IPA_CLK>;
1629 clock-names = "core"; 1453 clock-names = "core";
1630 1454
1631 interconnects = <&agg 1455 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
1632 <&agg 1456 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>,
1633 <&gem 1457 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
1634 interconnect-names = 1458 interconnect-names = "memory",
1635 1459 "imem",
1636 1460 "config";
1637 1461
1638 qcom,qmp = <&aoss_qmp <<
1639 <<
1640 qcom,smem-states = <& 1462 qcom,smem-states = <&ipa_smp2p_out 0>,
1641 <& 1463 <&ipa_smp2p_out 1>;
1642 qcom,smem-state-names 1464 qcom,smem-state-names = "ipa-clock-enabled-valid",
1643 1465 "ipa-clock-enabled";
1644 1466
1645 status = "disabled"; 1467 status = "disabled";
1646 }; 1468 };
1647 1469
1648 tcsr_mutex: hwlock@1f40000 { !! 1470 tcsr_mutex_regs: syscon@1f40000 {
1649 compatible = "qcom,tc !! 1471 compatible = "syscon";
1650 reg = <0 0x01f40000 0 !! 1472 reg = <0 0x01f40000 0 0x40000>;
1651 #hwlock-cells = <1>; <<
1652 }; <<
1653 <<
1654 tcsr_regs_1: syscon@1f60000 { <<
1655 compatible = "qcom,sc <<
1656 reg = <0 0x01f60000 0 <<
1657 }; 1473 };
1658 1474
1659 tcsr_regs_2: syscon@1fc0000 { !! 1475 tcsr_regs: syscon@1fc0000 {
1660 compatible = "qcom,sc !! 1476 compatible = "syscon";
1661 reg = <0 0x01fc0000 0 1477 reg = <0 0x01fc0000 0 0x40000>;
1662 }; 1478 };
1663 1479
1664 tlmm: pinctrl@3500000 { 1480 tlmm: pinctrl@3500000 {
1665 compatible = "qcom,sc 1481 compatible = "qcom,sc7180-pinctrl";
1666 reg = <0 0x03500000 0 1482 reg = <0 0x03500000 0 0x300000>,
1667 <0 0x03900000 0 1483 <0 0x03900000 0 0x300000>,
1668 <0 0x03d00000 0 1484 <0 0x03d00000 0 0x300000>;
1669 reg-names = "west", " 1485 reg-names = "west", "north", "south";
1670 interrupts = <GIC_SPI 1486 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1671 gpio-controller; 1487 gpio-controller;
1672 #gpio-cells = <2>; 1488 #gpio-cells = <2>;
1673 interrupt-controller; 1489 interrupt-controller;
1674 #interrupt-cells = <2 1490 #interrupt-cells = <2>;
1675 gpio-ranges = <&tlmm 1491 gpio-ranges = <&tlmm 0 0 120>;
1676 wakeup-parent = <&pdc 1492 wakeup-parent = <&pdc>;
1677 1493
1678 dp_hot_plug_det: dp-h !! 1494 dp_hot_plug_det: dp-hot-plug-det {
1679 pins = "gpio1 !! 1495 pinmux {
1680 function = "d !! 1496 pins = "gpio117";
1681 }; !! 1497 function = "dp_hot";
1682 !! 1498 };
1683 qspi_clk: qspi-clk-st <<
1684 pins = "gpio6 <<
1685 function = "q <<
1686 }; <<
1687 <<
1688 qspi_cs0: qspi-cs0-st <<
1689 pins = "gpio6 <<
1690 function = "q <<
1691 }; <<
1692 <<
1693 qspi_cs1: qspi-cs1-st <<
1694 pins = "gpio7 <<
1695 function = "q <<
1696 }; <<
1697 <<
1698 qspi_data0: qspi-data <<
1699 pins = "gpio6 <<
1700 function = "q <<
1701 }; <<
1702 <<
1703 qspi_data1: qspi-data <<
1704 pins = "gpio6 <<
1705 function = "q <<
1706 }; <<
1707 <<
1708 qspi_data23: qspi-dat <<
1709 pins = "gpio6 <<
1710 function = "q <<
1711 }; <<
1712 <<
1713 qup_i2c0_default: qup <<
1714 pins = "gpio3 <<
1715 function = "q <<
1716 }; <<
1717 <<
1718 qup_i2c1_default: qup <<
1719 pins = "gpio0 <<
1720 function = "q <<
1721 }; <<
1722 <<
1723 qup_i2c2_default: qup <<
1724 pins = "gpio1 <<
1725 function = "q <<
1726 }; <<
1727 <<
1728 qup_i2c3_default: qup <<
1729 pins = "gpio3 <<
1730 function = "q <<
1731 }; <<
1732 <<
1733 qup_i2c4_default: qup <<
1734 pins = "gpio1 <<
1735 function = "q <<
1736 }; <<
1737 <<
1738 qup_i2c5_default: qup <<
1739 pins = "gpio2 <<
1740 function = "q <<
1741 }; <<
1742 <<
1743 qup_i2c6_default: qup <<
1744 pins = "gpio5 <<
1745 function = "q <<
1746 }; <<
1747 <<
1748 qup_i2c7_default: qup <<
1749 pins = "gpio6 <<
1750 function = "q <<
1751 }; <<
1752 <<
1753 qup_i2c8_default: qup <<
1754 pins = "gpio4 <<
1755 function = "q <<
1756 }; <<
1757 <<
1758 qup_i2c9_default: qup <<
1759 pins = "gpio4 <<
1760 function = "q <<
1761 }; <<
1762 <<
1763 qup_i2c10_default: qu <<
1764 pins = "gpio8 <<
1765 function = "q <<
1766 }; <<
1767 <<
1768 qup_i2c11_default: qu <<
1769 pins = "gpio5 <<
1770 function = "q <<
1771 }; <<
1772 <<
1773 qup_spi0_spi: qup-spi <<
1774 pins = "gpio3 <<
1775 function = "q <<
1776 }; <<
1777 <<
1778 qup_spi0_cs: qup-spi0 <<
1779 pins = "gpio3 <<
1780 function = "q <<
1781 }; <<
1782 <<
1783 qup_spi0_cs_gpio: qup <<
1784 pins = "gpio3 <<
1785 function = "g <<
1786 }; <<
1787 <<
1788 qup_spi1_spi: qup-spi <<
1789 pins = "gpio0 <<
1790 function = "q <<
1791 }; <<
1792 <<
1793 qup_spi1_cs: qup-spi1 <<
1794 pins = "gpio3 <<
1795 function = "q <<
1796 }; <<
1797 <<
1798 qup_spi1_cs_gpio: qup <<
1799 pins = "gpio3 <<
1800 function = "g <<
1801 }; <<
1802 <<
1803 qup_spi3_spi: qup-spi <<
1804 pins = "gpio3 <<
1805 function = "q <<
1806 }; <<
1807 <<
1808 qup_spi3_cs: qup-spi3 <<
1809 pins = "gpio4 <<
1810 function = "q <<
1811 }; 1499 };
1812 1500
1813 qup_spi3_cs_gpio: qup !! 1501 qspi_clk: qspi-clk {
1814 pins = "gpio4 !! 1502 pinmux {
1815 function = "g !! 1503 pins = "gpio63";
>> 1504 function = "qspi_clk";
>> 1505 };
1816 }; 1506 };
1817 1507
1818 qup_spi5_spi: qup-spi !! 1508 qspi_cs0: qspi-cs0 {
1819 pins = "gpio2 !! 1509 pinmux {
1820 function = "q !! 1510 pins = "gpio68";
>> 1511 function = "qspi_cs";
>> 1512 };
1821 }; 1513 };
1822 1514
1823 qup_spi5_cs: qup-spi5 !! 1515 qspi_cs1: qspi-cs1 {
1824 pins = "gpio2 !! 1516 pinmux {
1825 function = "q !! 1517 pins = "gpio72";
>> 1518 function = "qspi_cs";
>> 1519 };
1826 }; 1520 };
1827 1521
1828 qup_spi5_cs_gpio: qup !! 1522 qspi_data01: qspi-data01 {
1829 pins = "gpio2 !! 1523 pinmux-data {
1830 function = "g !! 1524 pins = "gpio64", "gpio65";
>> 1525 function = "qspi_data";
>> 1526 };
1831 }; 1527 };
1832 1528
1833 qup_spi6_spi: qup-spi !! 1529 qspi_data12: qspi-data12 {
1834 pins = "gpio5 !! 1530 pinmux-data {
1835 function = "q !! 1531 pins = "gpio66", "gpio67";
>> 1532 function = "qspi_data";
>> 1533 };
1836 }; 1534 };
1837 1535
1838 qup_spi6_cs: qup-spi6 !! 1536 qup_i2c0_default: qup-i2c0-default {
1839 pins = "gpio6 !! 1537 pinmux {
1840 function = "q !! 1538 pins = "gpio34", "gpio35";
>> 1539 function = "qup00";
>> 1540 };
1841 }; 1541 };
1842 1542
1843 qup_spi6_cs_gpio: qup !! 1543 qup_i2c1_default: qup-i2c1-default {
1844 pins = "gpio6 !! 1544 pinmux {
1845 function = "g !! 1545 pins = "gpio0", "gpio1";
>> 1546 function = "qup01";
>> 1547 };
1846 }; 1548 };
1847 1549
1848 qup_spi8_spi: qup-spi !! 1550 qup_i2c2_default: qup-i2c2-default {
1849 pins = "gpio4 !! 1551 pinmux {
1850 function = "q !! 1552 pins = "gpio15", "gpio16";
>> 1553 function = "qup02_i2c";
>> 1554 };
1851 }; 1555 };
1852 1556
1853 qup_spi8_cs: qup-spi8 !! 1557 qup_i2c3_default: qup-i2c3-default {
1854 pins = "gpio4 !! 1558 pinmux {
1855 function = "q !! 1559 pins = "gpio38", "gpio39";
>> 1560 function = "qup03";
>> 1561 };
1856 }; 1562 };
1857 1563
1858 qup_spi8_cs_gpio: qup !! 1564 qup_i2c4_default: qup-i2c4-default {
1859 pins = "gpio4 !! 1565 pinmux {
1860 function = "g !! 1566 pins = "gpio115", "gpio116";
>> 1567 function = "qup04_i2c";
>> 1568 };
1861 }; 1569 };
1862 1570
1863 qup_spi10_spi: qup-sp !! 1571 qup_i2c5_default: qup-i2c5-default {
1864 pins = "gpio8 !! 1572 pinmux {
1865 function = "q !! 1573 pins = "gpio25", "gpio26";
>> 1574 function = "qup05";
>> 1575 };
1866 }; 1576 };
1867 1577
1868 qup_spi10_cs: qup-spi !! 1578 qup_i2c6_default: qup-i2c6-default {
1869 pins = "gpio8 !! 1579 pinmux {
1870 function = "q !! 1580 pins = "gpio59", "gpio60";
>> 1581 function = "qup10";
>> 1582 };
1871 }; 1583 };
1872 1584
1873 qup_spi10_cs_gpio: qu !! 1585 qup_i2c7_default: qup-i2c7-default {
1874 pins = "gpio8 !! 1586 pinmux {
1875 function = "g !! 1587 pins = "gpio6", "gpio7";
>> 1588 function = "qup11_i2c";
>> 1589 };
1876 }; 1590 };
1877 1591
1878 qup_spi11_spi: qup-sp !! 1592 qup_i2c8_default: qup-i2c8-default {
1879 pins = "gpio5 !! 1593 pinmux {
1880 function = "q !! 1594 pins = "gpio42", "gpio43";
>> 1595 function = "qup12";
>> 1596 };
1881 }; 1597 };
1882 1598
1883 qup_spi11_cs: qup-spi !! 1599 qup_i2c9_default: qup-i2c9-default {
1884 pins = "gpio5 !! 1600 pinmux {
1885 function = "q !! 1601 pins = "gpio46", "gpio47";
>> 1602 function = "qup13_i2c";
>> 1603 };
1886 }; 1604 };
1887 1605
1888 qup_spi11_cs_gpio: qu !! 1606 qup_i2c10_default: qup-i2c10-default {
1889 pins = "gpio5 !! 1607 pinmux {
1890 function = "g !! 1608 pins = "gpio86", "gpio87";
>> 1609 function = "qup14";
>> 1610 };
1891 }; 1611 };
1892 1612
1893 qup_uart0_default: qu !! 1613 qup_i2c11_default: qup-i2c11-default {
1894 qup_uart0_cts !! 1614 pinmux {
1895 pins !! 1615 pins = "gpio53", "gpio54";
1896 funct !! 1616 function = "qup15";
1897 }; 1617 };
>> 1618 };
1898 1619
1899 qup_uart0_rts !! 1620 qup_spi0_default: qup-spi0-default {
1900 pins !! 1621 pinmux {
>> 1622 pins = "gpio34", "gpio35",
>> 1623 "gpio36", "gpio37";
1901 funct 1624 function = "qup00";
1902 }; 1625 };
>> 1626 };
1903 1627
1904 qup_uart0_tx: !! 1628 qup_spi0_cs_gpio: qup-spi0-cs-gpio {
1905 pins !! 1629 pinmux {
>> 1630 pins = "gpio34", "gpio35",
>> 1631 "gpio36";
1906 funct 1632 function = "qup00";
1907 }; 1633 };
1908 1634
1909 qup_uart0_rx: !! 1635 pinmux-cs {
1910 pins 1636 pins = "gpio37";
1911 funct !! 1637 function = "gpio";
1912 }; 1638 };
1913 }; 1639 };
1914 1640
1915 qup_uart1_default: qu !! 1641 qup_spi1_default: qup-spi1-default {
1916 qup_uart1_cts !! 1642 pinmux {
1917 pins !! 1643 pins = "gpio0", "gpio1",
>> 1644 "gpio2", "gpio3";
1918 funct 1645 function = "qup01";
1919 }; 1646 };
>> 1647 };
1920 1648
1921 qup_uart1_rts !! 1649 qup_spi1_cs_gpio: qup-spi1-cs-gpio {
1922 pins !! 1650 pinmux {
>> 1651 pins = "gpio0", "gpio1",
>> 1652 "gpio2";
1923 funct 1653 function = "qup01";
1924 }; 1654 };
1925 1655
1926 qup_uart1_tx: !! 1656 pinmux-cs {
1927 pins !! 1657 pins = "gpio3";
1928 funct !! 1658 function = "gpio";
1929 }; 1659 };
>> 1660 };
1930 1661
1931 qup_uart1_rx: !! 1662 qup_spi3_default: qup-spi3-default {
1932 pins !! 1663 pinmux {
1933 funct !! 1664 pins = "gpio38", "gpio39",
>> 1665 "gpio40", "gpio41";
>> 1666 function = "qup03";
1934 }; 1667 };
1935 }; 1668 };
1936 1669
1937 qup_uart2_default: qu !! 1670 qup_spi3_cs_gpio: qup-spi3-cs-gpio {
1938 qup_uart2_tx: !! 1671 pinmux {
1939 pins !! 1672 pins = "gpio38", "gpio39",
1940 funct !! 1673 "gpio40";
>> 1674 function = "qup03";
1941 }; 1675 };
1942 1676
1943 qup_uart2_rx: !! 1677 pinmux-cs {
1944 pins !! 1678 pins = "gpio41";
1945 funct !! 1679 function = "gpio";
1946 }; 1680 };
1947 }; 1681 };
1948 1682
1949 qup_uart3_default: qu !! 1683 qup_spi5_default: qup-spi5-default {
1950 qup_uart3_cts !! 1684 pinmux {
1951 pins !! 1685 pins = "gpio25", "gpio26",
1952 funct !! 1686 "gpio27", "gpio28";
>> 1687 function = "qup05";
1953 }; 1688 };
>> 1689 };
1954 1690
1955 qup_uart3_rts !! 1691 qup_spi5_cs_gpio: qup-spi5-cs-gpio {
1956 pins !! 1692 pinmux {
1957 funct !! 1693 pins = "gpio25", "gpio26",
>> 1694 "gpio27";
>> 1695 function = "qup05";
1958 }; 1696 };
1959 1697
1960 qup_uart3_tx: !! 1698 pinmux-cs {
1961 pins !! 1699 pins = "gpio28";
1962 funct !! 1700 function = "gpio";
1963 }; 1701 };
>> 1702 };
1964 1703
1965 qup_uart3_rx: !! 1704 qup_spi6_default: qup-spi6-default {
1966 pins !! 1705 pinmux {
1967 funct !! 1706 pins = "gpio59", "gpio60",
>> 1707 "gpio61", "gpio62";
>> 1708 function = "qup10";
1968 }; 1709 };
1969 }; 1710 };
1970 1711
1971 qup_uart4_default: qu !! 1712 qup_spi6_cs_gpio: qup-spi6-cs-gpio {
1972 qup_uart4_tx: !! 1713 pinmux {
1973 pins !! 1714 pins = "gpio59", "gpio60",
1974 funct !! 1715 "gpio61";
>> 1716 function = "qup10";
1975 }; 1717 };
1976 1718
1977 qup_uart4_rx: !! 1719 pinmux-cs {
1978 pins !! 1720 pins = "gpio62";
1979 funct !! 1721 function = "gpio";
1980 }; 1722 };
1981 }; 1723 };
1982 1724
1983 qup_uart5_default: qu !! 1725 qup_spi8_default: qup-spi8-default {
1984 qup_uart5_cts !! 1726 pinmux {
1985 pins !! 1727 pins = "gpio42", "gpio43",
1986 funct !! 1728 "gpio44", "gpio45";
1987 }; !! 1729 function = "qup12";
1988 <<
1989 qup_uart5_rts <<
1990 pins <<
1991 funct <<
1992 }; 1730 };
>> 1731 };
1993 1732
1994 qup_uart5_tx: !! 1733 qup_spi8_cs_gpio: qup-spi8-cs-gpio {
1995 pins !! 1734 pinmux {
1996 funct !! 1735 pins = "gpio42", "gpio43",
>> 1736 "gpio44";
>> 1737 function = "qup12";
1997 }; 1738 };
1998 1739
1999 qup_uart5_rx: !! 1740 pinmux-cs {
2000 pins !! 1741 pins = "gpio45";
2001 funct !! 1742 function = "gpio";
2002 }; 1743 };
2003 }; 1744 };
2004 1745
2005 qup_uart6_default: qu !! 1746 qup_spi10_default: qup-spi10-default {
2006 qup_uart6_cts !! 1747 pinmux {
2007 pins !! 1748 pins = "gpio86", "gpio87",
2008 funct !! 1749 "gpio88", "gpio89";
>> 1750 function = "qup14";
2009 }; 1751 };
>> 1752 };
2010 1753
2011 qup_uart6_rts !! 1754 qup_spi10_cs_gpio: qup-spi10-cs-gpio {
2012 pins !! 1755 pinmux {
2013 funct !! 1756 pins = "gpio86", "gpio87",
>> 1757 "gpio88";
>> 1758 function = "qup14";
2014 }; 1759 };
2015 1760
2016 qup_uart6_tx: !! 1761 pinmux-cs {
2017 pins !! 1762 pins = "gpio89";
2018 funct !! 1763 function = "gpio";
2019 }; 1764 };
>> 1765 };
2020 1766
2021 qup_uart6_rx: !! 1767 qup_spi11_default: qup-spi11-default {
2022 pins !! 1768 pinmux {
2023 funct !! 1769 pins = "gpio53", "gpio54",
>> 1770 "gpio55", "gpio56";
>> 1771 function = "qup15";
2024 }; 1772 };
2025 }; 1773 };
2026 1774
2027 qup_uart7_default: qu !! 1775 qup_spi11_cs_gpio: qup-spi11-cs-gpio {
2028 qup_uart7_tx: !! 1776 pinmux {
2029 pins !! 1777 pins = "gpio53", "gpio54",
2030 funct !! 1778 "gpio55";
>> 1779 function = "qup15";
2031 }; 1780 };
2032 1781
2033 qup_uart7_rx: !! 1782 pinmux-cs {
2034 pins !! 1783 pins = "gpio56";
2035 funct !! 1784 function = "gpio";
2036 }; 1785 };
2037 }; 1786 };
2038 1787
2039 qup_uart8_default: qu !! 1788 qup_uart0_default: qup-uart0-default {
2040 qup_uart8_tx: !! 1789 pinmux {
2041 pins !! 1790 pins = "gpio34", "gpio35",
2042 funct !! 1791 "gpio36", "gpio37";
>> 1792 function = "qup00";
2043 }; 1793 };
>> 1794 };
2044 1795
2045 qup_uart8_rx: !! 1796 qup_uart1_default: qup-uart1-default {
2046 pins !! 1797 pinmux {
2047 funct !! 1798 pins = "gpio0", "gpio1",
>> 1799 "gpio2", "gpio3";
>> 1800 function = "qup01";
2048 }; 1801 };
2049 }; 1802 };
2050 1803
2051 qup_uart9_default: qu !! 1804 qup_uart2_default: qup-uart2-default {
2052 qup_uart9_tx: !! 1805 pinmux {
2053 pins !! 1806 pins = "gpio15", "gpio16";
2054 funct !! 1807 function = "qup02_uart";
2055 }; 1808 };
>> 1809 };
2056 1810
2057 qup_uart9_rx: !! 1811 qup_uart3_default: qup-uart3-default {
2058 pins !! 1812 pinmux {
2059 funct !! 1813 pins = "gpio38", "gpio39",
>> 1814 "gpio40", "gpio41";
>> 1815 function = "qup03";
2060 }; 1816 };
2061 }; 1817 };
2062 1818
2063 qup_uart10_default: q !! 1819 qup_uart4_default: qup-uart4-default {
2064 qup_uart10_ct !! 1820 pinmux {
2065 pins !! 1821 pins = "gpio115", "gpio116";
2066 funct !! 1822 function = "qup04_uart";
2067 }; 1823 };
>> 1824 };
2068 1825
2069 qup_uart10_rt !! 1826 qup_uart5_default: qup-uart5-default {
2070 pins !! 1827 pinmux {
2071 funct !! 1828 pins = "gpio25", "gpio26",
>> 1829 "gpio27", "gpio28";
>> 1830 function = "qup05";
2072 }; 1831 };
>> 1832 };
2073 1833
2074 qup_uart10_tx !! 1834 qup_uart6_default: qup-uart6-default {
2075 pins !! 1835 pinmux {
2076 funct !! 1836 pins = "gpio59", "gpio60",
>> 1837 "gpio61", "gpio62";
>> 1838 function = "qup10";
2077 }; 1839 };
>> 1840 };
2078 1841
2079 qup_uart10_rx !! 1842 qup_uart7_default: qup-uart7-default {
2080 pins !! 1843 pinmux {
2081 funct !! 1844 pins = "gpio6", "gpio7";
>> 1845 function = "qup11_uart";
2082 }; 1846 };
2083 }; 1847 };
2084 1848
2085 qup_uart11_default: q !! 1849 qup_uart8_default: qup-uart8-default {
2086 qup_uart11_ct !! 1850 pinmux {
2087 pins !! 1851 pins = "gpio44", "gpio45";
2088 funct !! 1852 function = "qup12";
2089 }; 1853 };
>> 1854 };
2090 1855
2091 qup_uart11_rt !! 1856 qup_uart9_default: qup-uart9-default {
2092 pins !! 1857 pinmux {
2093 funct !! 1858 pins = "gpio46", "gpio47";
>> 1859 function = "qup13_uart";
2094 }; 1860 };
>> 1861 };
2095 1862
2096 qup_uart11_tx !! 1863 qup_uart10_default: qup-uart10-default {
2097 pins !! 1864 pinmux {
2098 funct !! 1865 pins = "gpio86", "gpio87",
>> 1866 "gpio88", "gpio89";
>> 1867 function = "qup14";
2099 }; 1868 };
>> 1869 };
2100 1870
2101 qup_uart11_rx !! 1871 qup_uart11_default: qup-uart11-default {
2102 pins !! 1872 pinmux {
>> 1873 pins = "gpio53", "gpio54",
>> 1874 "gpio55", "gpio56";
2103 funct 1875 function = "qup15";
2104 }; 1876 };
2105 }; 1877 };
2106 1878
2107 sec_mi2s_active: sec- !! 1879 sec_mi2s_active: sec-mi2s-active {
2108 pins = "gpio4 !! 1880 pinmux {
2109 function = "m !! 1881 pins = "gpio49", "gpio50", "gpio51";
2110 }; !! 1882 function = "mi2s_1";
2111 !! 1883 };
2112 pri_mi2s_active: pri- <<
2113 pins = "gpio5 <<
2114 function = "m <<
2115 }; 1884 };
2116 1885
2117 pri_mi2s_mclk_active: !! 1886 pri_mi2s_active: pri-mi2s-active {
2118 pins = "gpio5 !! 1887 pinmux {
2119 function = "l !! 1888 pins = "gpio53", "gpio54", "gpio55", "gpio56";
>> 1889 function = "mi2s_0";
>> 1890 };
2120 }; 1891 };
2121 1892
2122 ter_mi2s_active: ter- !! 1893 pri_mi2s_mclk_active: pri-mi2s-mclk-active {
2123 pins = "gpio6 !! 1894 pinmux {
2124 function = "m !! 1895 pins = "gpio57";
>> 1896 function = "lpass_ext";
>> 1897 };
2125 }; 1898 };
2126 }; 1899 };
2127 1900
2128 remoteproc_mpss: remoteproc@4 1901 remoteproc_mpss: remoteproc@4080000 {
2129 compatible = "qcom,sc 1902 compatible = "qcom,sc7180-mpss-pas";
2130 reg = <0 0x04080000 0 !! 1903 reg = <0 0x04080000 0 0x4040>, <0 0x04180000 0 0x48>;
>> 1904 reg-names = "qdsp6", "rmb";
2131 1905
2132 interrupts-extended = 1906 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
2133 1907 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2134 1908 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2135 1909 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2136 1910 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
2137 1911 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
2138 interrupt-names = "wd 1912 interrupt-names = "wdog", "fatal", "ready", "handover",
2139 "st 1913 "stop-ack", "shutdown-ack";
2140 1914
2141 clocks = <&rpmhcc RPM !! 1915 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
2142 clock-names = "xo"; !! 1916 <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>,
>> 1917 <&gcc GCC_MSS_NAV_AXI_CLK>,
>> 1918 <&gcc GCC_MSS_SNOC_AXI_CLK>,
>> 1919 <&gcc GCC_MSS_MFAB_AXIS_CLK>,
>> 1920 <&rpmhcc RPMH_CXO_CLK>;
>> 1921 clock-names = "iface", "bus", "nav", "snoc_axi",
>> 1922 "mnoc_axi", "xo";
2143 1923
2144 power-domains = <&rpm 1924 power-domains = <&rpmhpd SC7180_CX>,
2145 <&rpm 1925 <&rpmhpd SC7180_MX>,
2146 <&rpm 1926 <&rpmhpd SC7180_MSS>;
2147 power-domain-names = 1927 power-domain-names = "cx", "mx", "mss";
2148 1928
2149 memory-region = <&mps 1929 memory-region = <&mpss_mem>;
2150 1930
2151 qcom,qmp = <&aoss_qmp 1931 qcom,qmp = <&aoss_qmp>;
2152 1932
2153 qcom,smem-states = <& 1933 qcom,smem-states = <&modem_smp2p_out 0>;
2154 qcom,smem-state-names 1934 qcom,smem-state-names = "stop";
2155 1935
>> 1936 resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
>> 1937 <&pdc_reset PDC_MODEM_SYNC_RESET>;
>> 1938 reset-names = "mss_restart", "pdc_reset";
>> 1939
>> 1940 qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
>> 1941 qcom,spare-regs = <&tcsr_regs 0xb3e4>;
>> 1942
2156 status = "disabled"; 1943 status = "disabled";
2157 1944
2158 glink-edge { 1945 glink-edge {
2159 interrupts = 1946 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
2160 label = "mode 1947 label = "modem";
2161 qcom,remote-p 1948 qcom,remote-pid = <1>;
2162 mboxes = <&ap 1949 mboxes = <&apss_shared 12>;
2163 }; 1950 };
2164 }; 1951 };
2165 1952
2166 gpu: gpu@5000000 { 1953 gpu: gpu@5000000 {
2167 compatible = "qcom,ad 1954 compatible = "qcom,adreno-618.0", "qcom,adreno";
>> 1955 #stream-id-cells = <16>;
2168 reg = <0 0x05000000 0 1956 reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x1000>,
2169 <0 0x05061000 1957 <0 0x05061000 0 0x800>;
2170 reg-names = "kgsl_3d0 1958 reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc";
2171 interrupts = <GIC_SPI 1959 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2172 iommus = <&adreno_smm 1960 iommus = <&adreno_smmu 0>;
2173 operating-points-v2 = 1961 operating-points-v2 = <&gpu_opp_table>;
2174 qcom,gmu = <&gmu>; 1962 qcom,gmu = <&gmu>;
2175 1963
2176 #cooling-cells = <2>; 1964 #cooling-cells = <2>;
2177 1965
2178 nvmem-cells = <&gpu_s 1966 nvmem-cells = <&gpu_speed_bin>;
2179 nvmem-cell-names = "s 1967 nvmem-cell-names = "speed_bin";
2180 1968
2181 interconnects = <&gem 1969 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
2182 interconnect-names = 1970 interconnect-names = "gfx-mem";
2183 1971
2184 gpu_opp_table: opp-ta 1972 gpu_opp_table: opp-table {
2185 compatible = 1973 compatible = "operating-points-v2";
2186 1974
2187 opp-825000000 1975 opp-825000000 {
2188 opp-h 1976 opp-hz = /bits/ 64 <825000000>;
2189 opp-l 1977 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2190 opp-p 1978 opp-peak-kBps = <8532000>;
2191 opp-s 1979 opp-supported-hw = <0x04>;
2192 }; 1980 };
2193 1981
2194 opp-800000000 1982 opp-800000000 {
2195 opp-h 1983 opp-hz = /bits/ 64 <800000000>;
2196 opp-l 1984 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2197 opp-p 1985 opp-peak-kBps = <8532000>;
2198 opp-s 1986 opp-supported-hw = <0x07>;
2199 }; 1987 };
2200 1988
2201 opp-650000000 1989 opp-650000000 {
2202 opp-h 1990 opp-hz = /bits/ 64 <650000000>;
2203 opp-l 1991 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2204 opp-p 1992 opp-peak-kBps = <7216000>;
2205 opp-s 1993 opp-supported-hw = <0x07>;
2206 }; 1994 };
2207 1995
2208 opp-565000000 1996 opp-565000000 {
2209 opp-h 1997 opp-hz = /bits/ 64 <565000000>;
2210 opp-l 1998 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2211 opp-p 1999 opp-peak-kBps = <5412000>;
2212 opp-s 2000 opp-supported-hw = <0x07>;
2213 }; 2001 };
2214 2002
2215 opp-430000000 2003 opp-430000000 {
2216 opp-h 2004 opp-hz = /bits/ 64 <430000000>;
2217 opp-l 2005 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2218 opp-p 2006 opp-peak-kBps = <5412000>;
2219 opp-s 2007 opp-supported-hw = <0x07>;
2220 }; 2008 };
2221 2009
2222 opp-355000000 2010 opp-355000000 {
2223 opp-h 2011 opp-hz = /bits/ 64 <355000000>;
2224 opp-l 2012 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2225 opp-p 2013 opp-peak-kBps = <3072000>;
2226 opp-s 2014 opp-supported-hw = <0x07>;
2227 }; 2015 };
2228 2016
2229 opp-267000000 2017 opp-267000000 {
2230 opp-h 2018 opp-hz = /bits/ 64 <267000000>;
2231 opp-l 2019 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2232 opp-p 2020 opp-peak-kBps = <3072000>;
2233 opp-s 2021 opp-supported-hw = <0x07>;
2234 }; 2022 };
2235 2023
2236 opp-180000000 2024 opp-180000000 {
2237 opp-h 2025 opp-hz = /bits/ 64 <180000000>;
2238 opp-l 2026 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2239 opp-p 2027 opp-peak-kBps = <1804000>;
2240 opp-s 2028 opp-supported-hw = <0x07>;
2241 }; 2029 };
2242 }; 2030 };
2243 }; 2031 };
2244 2032
2245 adreno_smmu: iommu@5040000 { 2033 adreno_smmu: iommu@5040000 {
2246 compatible = "qcom,sc 2034 compatible = "qcom,sc7180-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
2247 reg = <0 0x05040000 0 2035 reg = <0 0x05040000 0 0x10000>;
2248 #iommu-cells = <1>; 2036 #iommu-cells = <1>;
2249 #global-interrupts = 2037 #global-interrupts = <2>;
2250 interrupts = <GIC_SPI 2038 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
2251 <GIC_ 2039 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
2252 <GIC_ 2040 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
2253 <GIC_ 2041 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
2254 <GIC_ 2042 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
2255 <GIC_ 2043 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
2256 <GIC_ 2044 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
2257 <GIC_ 2045 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
2258 <GIC_ 2046 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
2259 <GIC_ 2047 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
2260 2048
2261 clocks = <&gcc GCC_GP 2049 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2262 <&gcc GCC_GPU 2050 <&gcc GCC_GPU_CFG_AHB_CLK>;
2263 clock-names = "bus", 2051 clock-names = "bus", "iface";
2264 2052
2265 power-domains = <&gpu 2053 power-domains = <&gpucc CX_GDSC>;
2266 }; 2054 };
2267 2055
2268 gmu: gmu@506a000 { 2056 gmu: gmu@506a000 {
2269 compatible = "qcom,ad !! 2057 compatible="qcom,adreno-gmu-618.0", "qcom,adreno-gmu";
2270 reg = <0 0x0506a000 0 2058 reg = <0 0x0506a000 0 0x31000>, <0 0x0b290000 0 0x10000>,
2271 <0 0x0b490000 2059 <0 0x0b490000 0 0x10000>;
2272 reg-names = "gmu", "g 2060 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
2273 interrupts = <GIC_SPI 2061 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2274 <GIC_SPI 3 2062 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2275 interrupt-names = "hf 2063 interrupt-names = "hfi", "gmu";
2276 clocks = <&gpucc GPU_ 2064 clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
2277 <&gpucc GPU_CC 2065 <&gpucc GPU_CC_CXO_CLK>,
2278 <&gcc GCC_DDRS 2066 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2279 <&gcc GCC_GPU_ 2067 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
2280 clock-names = "gmu", 2068 clock-names = "gmu", "cxo", "axi", "memnoc";
2281 power-domains = <&gpu 2069 power-domains = <&gpucc CX_GDSC>, <&gpucc GX_GDSC>;
2282 power-domain-names = 2070 power-domain-names = "cx", "gx";
2283 iommus = <&adreno_smm 2071 iommus = <&adreno_smmu 5>;
2284 operating-points-v2 = 2072 operating-points-v2 = <&gmu_opp_table>;
2285 2073
2286 gmu_opp_table: opp-ta 2074 gmu_opp_table: opp-table {
2287 compatible = 2075 compatible = "operating-points-v2";
2288 2076
2289 opp-200000000 2077 opp-200000000 {
2290 opp-h 2078 opp-hz = /bits/ 64 <200000000>;
2291 opp-l 2079 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2292 }; 2080 };
2293 }; 2081 };
2294 }; 2082 };
2295 2083
2296 gpucc: clock-controller@50900 2084 gpucc: clock-controller@5090000 {
2297 compatible = "qcom,sc 2085 compatible = "qcom,sc7180-gpucc";
2298 reg = <0 0x05090000 0 2086 reg = <0 0x05090000 0 0x9000>;
2299 clocks = <&rpmhcc RPM 2087 clocks = <&rpmhcc RPMH_CXO_CLK>,
2300 <&gcc GCC_GP 2088 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2301 <&gcc GCC_GP 2089 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2302 clock-names = "bi_tcx 2090 clock-names = "bi_tcxo",
2303 "gcc_gp 2091 "gcc_gpu_gpll0_clk_src",
2304 "gcc_gp 2092 "gcc_gpu_gpll0_div_clk_src";
2305 #clock-cells = <1>; 2093 #clock-cells = <1>;
2306 #reset-cells = <1>; 2094 #reset-cells = <1>;
2307 #power-domain-cells = 2095 #power-domain-cells = <1>;
2308 }; 2096 };
2309 2097
2310 dma@10a2000 { <<
2311 compatible = "qcom,sc <<
2312 reg = <0x0 0x010a2000 <<
2313 <0x0 0x010ae000 <<
2314 status = "disabled"; <<
2315 }; <<
2316 <<
2317 stm@6002000 { 2098 stm@6002000 {
2318 compatible = "arm,cor 2099 compatible = "arm,coresight-stm", "arm,primecell";
2319 reg = <0 0x06002000 0 2100 reg = <0 0x06002000 0 0x1000>,
2320 <0 0x16280000 0 2101 <0 0x16280000 0 0x180000>;
2321 reg-names = "stm-base 2102 reg-names = "stm-base", "stm-stimulus-base";
2322 2103
2323 clocks = <&aoss_qmp>; 2104 clocks = <&aoss_qmp>;
2324 clock-names = "apb_pc 2105 clock-names = "apb_pclk";
2325 2106
2326 out-ports { 2107 out-ports {
2327 port { 2108 port {
2328 stm_o 2109 stm_out: endpoint {
2329 2110 remote-endpoint = <&funnel0_in7>;
2330 }; 2111 };
2331 }; 2112 };
2332 }; 2113 };
2333 }; 2114 };
2334 2115
2335 funnel@6041000 { 2116 funnel@6041000 {
2336 compatible = "arm,cor 2117 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2337 reg = <0 0x06041000 0 2118 reg = <0 0x06041000 0 0x1000>;
2338 2119
2339 clocks = <&aoss_qmp>; 2120 clocks = <&aoss_qmp>;
2340 clock-names = "apb_pc 2121 clock-names = "apb_pclk";
2341 2122
2342 out-ports { 2123 out-ports {
2343 port { 2124 port {
2344 funne 2125 funnel0_out: endpoint {
2345 2126 remote-endpoint = <&merge_funnel_in0>;
2346 }; 2127 };
2347 }; 2128 };
2348 }; 2129 };
2349 2130
2350 in-ports { 2131 in-ports {
2351 #address-cell 2132 #address-cells = <1>;
2352 #size-cells = 2133 #size-cells = <0>;
2353 2134
2354 port@7 { 2135 port@7 {
2355 reg = 2136 reg = <7>;
2356 funne 2137 funnel0_in7: endpoint {
2357 2138 remote-endpoint = <&stm_out>;
2358 }; 2139 };
2359 }; 2140 };
2360 }; 2141 };
2361 }; 2142 };
2362 2143
2363 funnel@6042000 { 2144 funnel@6042000 {
2364 compatible = "arm,cor 2145 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2365 reg = <0 0x06042000 0 2146 reg = <0 0x06042000 0 0x1000>;
2366 2147
2367 clocks = <&aoss_qmp>; 2148 clocks = <&aoss_qmp>;
2368 clock-names = "apb_pc 2149 clock-names = "apb_pclk";
2369 2150
2370 out-ports { 2151 out-ports {
2371 port { 2152 port {
2372 funne 2153 funnel1_out: endpoint {
2373 2154 remote-endpoint = <&merge_funnel_in1>;
2374 }; 2155 };
2375 }; 2156 };
2376 }; 2157 };
2377 2158
2378 in-ports { 2159 in-ports {
2379 #address-cell 2160 #address-cells = <1>;
2380 #size-cells = 2161 #size-cells = <0>;
2381 2162
2382 port@4 { 2163 port@4 {
2383 reg = 2164 reg = <4>;
2384 funne 2165 funnel1_in4: endpoint {
2385 2166 remote-endpoint = <&apss_merge_funnel_out>;
2386 }; 2167 };
2387 }; 2168 };
2388 }; 2169 };
2389 }; 2170 };
2390 2171
2391 funnel@6045000 { 2172 funnel@6045000 {
2392 compatible = "arm,cor 2173 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2393 reg = <0 0x06045000 0 2174 reg = <0 0x06045000 0 0x1000>;
2394 2175
2395 clocks = <&aoss_qmp>; 2176 clocks = <&aoss_qmp>;
2396 clock-names = "apb_pc 2177 clock-names = "apb_pclk";
2397 2178
2398 out-ports { 2179 out-ports {
2399 port { 2180 port {
2400 merge 2181 merge_funnel_out: endpoint {
2401 2182 remote-endpoint = <&swao_funnel_in>;
2402 }; 2183 };
2403 }; 2184 };
2404 }; 2185 };
2405 2186
2406 in-ports { 2187 in-ports {
2407 #address-cell 2188 #address-cells = <1>;
2408 #size-cells = 2189 #size-cells = <0>;
2409 2190
2410 port@0 { 2191 port@0 {
2411 reg = 2192 reg = <0>;
2412 merge 2193 merge_funnel_in0: endpoint {
2413 2194 remote-endpoint = <&funnel0_out>;
2414 }; 2195 };
2415 }; 2196 };
2416 2197
2417 port@1 { 2198 port@1 {
2418 reg = 2199 reg = <1>;
2419 merge 2200 merge_funnel_in1: endpoint {
2420 2201 remote-endpoint = <&funnel1_out>;
2421 }; 2202 };
2422 }; 2203 };
2423 }; 2204 };
2424 }; 2205 };
2425 2206
2426 replicator@6046000 { 2207 replicator@6046000 {
2427 compatible = "arm,cor 2208 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2428 reg = <0 0x06046000 0 2209 reg = <0 0x06046000 0 0x1000>;
2429 2210
2430 clocks = <&aoss_qmp>; 2211 clocks = <&aoss_qmp>;
2431 clock-names = "apb_pc 2212 clock-names = "apb_pclk";
2432 2213
2433 out-ports { 2214 out-ports {
2434 port { 2215 port {
2435 repli 2216 replicator_out: endpoint {
2436 2217 remote-endpoint = <&etr_in>;
2437 }; 2218 };
2438 }; 2219 };
2439 }; 2220 };
2440 2221
2441 in-ports { 2222 in-ports {
2442 port { 2223 port {
2443 repli 2224 replicator_in: endpoint {
2444 2225 remote-endpoint = <&swao_replicator_out>;
2445 }; 2226 };
2446 }; 2227 };
2447 }; 2228 };
2448 }; 2229 };
2449 2230
2450 etr@6048000 { 2231 etr@6048000 {
2451 compatible = "arm,cor 2232 compatible = "arm,coresight-tmc", "arm,primecell";
2452 reg = <0 0x06048000 0 2233 reg = <0 0x06048000 0 0x1000>;
2453 iommus = <&apps_smmu 2234 iommus = <&apps_smmu 0x04a0 0x20>;
2454 2235
2455 clocks = <&aoss_qmp>; 2236 clocks = <&aoss_qmp>;
2456 clock-names = "apb_pc 2237 clock-names = "apb_pclk";
2457 arm,scatter-gather; 2238 arm,scatter-gather;
2458 2239
2459 in-ports { 2240 in-ports {
2460 port { 2241 port {
2461 etr_i 2242 etr_in: endpoint {
2462 2243 remote-endpoint = <&replicator_out>;
2463 }; 2244 };
2464 }; 2245 };
2465 }; 2246 };
2466 }; 2247 };
2467 2248
2468 funnel@6b04000 { 2249 funnel@6b04000 {
2469 compatible = "arm,cor 2250 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2470 reg = <0 0x06b04000 0 2251 reg = <0 0x06b04000 0 0x1000>;
2471 2252
2472 clocks = <&aoss_qmp>; 2253 clocks = <&aoss_qmp>;
2473 clock-names = "apb_pc 2254 clock-names = "apb_pclk";
2474 2255
2475 out-ports { 2256 out-ports {
2476 port { 2257 port {
2477 swao_ 2258 swao_funnel_out: endpoint {
2478 2259 remote-endpoint = <&etf_in>;
2479 }; 2260 };
2480 }; 2261 };
2481 }; 2262 };
2482 2263
2483 in-ports { 2264 in-ports {
2484 #address-cell 2265 #address-cells = <1>;
2485 #size-cells = 2266 #size-cells = <0>;
2486 2267
2487 port@7 { 2268 port@7 {
2488 reg = 2269 reg = <7>;
2489 swao_ 2270 swao_funnel_in: endpoint {
2490 2271 remote-endpoint = <&merge_funnel_out>;
2491 }; 2272 };
2492 }; 2273 };
2493 }; 2274 };
2494 }; 2275 };
2495 2276
2496 etf@6b05000 { 2277 etf@6b05000 {
2497 compatible = "arm,cor 2278 compatible = "arm,coresight-tmc", "arm,primecell";
2498 reg = <0 0x06b05000 0 2279 reg = <0 0x06b05000 0 0x1000>;
2499 2280
2500 clocks = <&aoss_qmp>; 2281 clocks = <&aoss_qmp>;
2501 clock-names = "apb_pc 2282 clock-names = "apb_pclk";
2502 2283
2503 out-ports { 2284 out-ports {
2504 port { 2285 port {
2505 etf_o 2286 etf_out: endpoint {
2506 2287 remote-endpoint = <&swao_replicator_in>;
2507 }; 2288 };
2508 }; 2289 };
2509 }; 2290 };
2510 2291
2511 in-ports { 2292 in-ports {
2512 port { 2293 port {
2513 etf_i 2294 etf_in: endpoint {
2514 2295 remote-endpoint = <&swao_funnel_out>;
2515 }; 2296 };
2516 }; 2297 };
2517 }; 2298 };
2518 }; 2299 };
2519 2300
2520 replicator@6b06000 { 2301 replicator@6b06000 {
2521 compatible = "arm,cor 2302 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2522 reg = <0 0x06b06000 0 2303 reg = <0 0x06b06000 0 0x1000>;
2523 2304
2524 clocks = <&aoss_qmp>; 2305 clocks = <&aoss_qmp>;
2525 clock-names = "apb_pc 2306 clock-names = "apb_pclk";
2526 qcom,replicator-loses 2307 qcom,replicator-loses-context;
2527 2308
2528 out-ports { 2309 out-ports {
2529 port { 2310 port {
2530 swao_ 2311 swao_replicator_out: endpoint {
2531 2312 remote-endpoint = <&replicator_in>;
2532 }; 2313 };
2533 }; 2314 };
2534 }; 2315 };
2535 2316
2536 in-ports { 2317 in-ports {
2537 port { 2318 port {
2538 swao_ 2319 swao_replicator_in: endpoint {
2539 2320 remote-endpoint = <&etf_out>;
2540 }; 2321 };
2541 }; 2322 };
2542 }; 2323 };
2543 }; 2324 };
2544 2325
2545 etm@7040000 { 2326 etm@7040000 {
2546 compatible = "arm,cor 2327 compatible = "arm,coresight-etm4x", "arm,primecell";
2547 reg = <0 0x07040000 0 2328 reg = <0 0x07040000 0 0x1000>;
2548 2329
2549 cpu = <&CPU0>; 2330 cpu = <&CPU0>;
2550 2331
2551 clocks = <&aoss_qmp>; 2332 clocks = <&aoss_qmp>;
2552 clock-names = "apb_pc 2333 clock-names = "apb_pclk";
2553 arm,coresight-loses-c 2334 arm,coresight-loses-context-with-cpu;
2554 qcom,skip-power-up; 2335 qcom,skip-power-up;
2555 2336
2556 out-ports { 2337 out-ports {
2557 port { 2338 port {
2558 etm0_ 2339 etm0_out: endpoint {
2559 2340 remote-endpoint = <&apss_funnel_in0>;
2560 }; 2341 };
2561 }; 2342 };
2562 }; 2343 };
2563 }; 2344 };
2564 2345
2565 etm@7140000 { 2346 etm@7140000 {
2566 compatible = "arm,cor 2347 compatible = "arm,coresight-etm4x", "arm,primecell";
2567 reg = <0 0x07140000 0 2348 reg = <0 0x07140000 0 0x1000>;
2568 2349
2569 cpu = <&CPU1>; 2350 cpu = <&CPU1>;
2570 2351
2571 clocks = <&aoss_qmp>; 2352 clocks = <&aoss_qmp>;
2572 clock-names = "apb_pc 2353 clock-names = "apb_pclk";
2573 arm,coresight-loses-c 2354 arm,coresight-loses-context-with-cpu;
2574 qcom,skip-power-up; 2355 qcom,skip-power-up;
2575 2356
2576 out-ports { 2357 out-ports {
2577 port { 2358 port {
2578 etm1_ 2359 etm1_out: endpoint {
2579 2360 remote-endpoint = <&apss_funnel_in1>;
2580 }; 2361 };
2581 }; 2362 };
2582 }; 2363 };
2583 }; 2364 };
2584 2365
2585 etm@7240000 { 2366 etm@7240000 {
2586 compatible = "arm,cor 2367 compatible = "arm,coresight-etm4x", "arm,primecell";
2587 reg = <0 0x07240000 0 2368 reg = <0 0x07240000 0 0x1000>;
2588 2369
2589 cpu = <&CPU2>; 2370 cpu = <&CPU2>;
2590 2371
2591 clocks = <&aoss_qmp>; 2372 clocks = <&aoss_qmp>;
2592 clock-names = "apb_pc 2373 clock-names = "apb_pclk";
2593 arm,coresight-loses-c 2374 arm,coresight-loses-context-with-cpu;
2594 qcom,skip-power-up; 2375 qcom,skip-power-up;
2595 2376
2596 out-ports { 2377 out-ports {
2597 port { 2378 port {
2598 etm2_ 2379 etm2_out: endpoint {
2599 2380 remote-endpoint = <&apss_funnel_in2>;
2600 }; 2381 };
2601 }; 2382 };
2602 }; 2383 };
2603 }; 2384 };
2604 2385
2605 etm@7340000 { 2386 etm@7340000 {
2606 compatible = "arm,cor 2387 compatible = "arm,coresight-etm4x", "arm,primecell";
2607 reg = <0 0x07340000 0 2388 reg = <0 0x07340000 0 0x1000>;
2608 2389
2609 cpu = <&CPU3>; 2390 cpu = <&CPU3>;
2610 2391
2611 clocks = <&aoss_qmp>; 2392 clocks = <&aoss_qmp>;
2612 clock-names = "apb_pc 2393 clock-names = "apb_pclk";
2613 arm,coresight-loses-c 2394 arm,coresight-loses-context-with-cpu;
2614 qcom,skip-power-up; 2395 qcom,skip-power-up;
2615 2396
2616 out-ports { 2397 out-ports {
2617 port { 2398 port {
2618 etm3_ 2399 etm3_out: endpoint {
2619 2400 remote-endpoint = <&apss_funnel_in3>;
2620 }; 2401 };
2621 }; 2402 };
2622 }; 2403 };
2623 }; 2404 };
2624 2405
2625 etm@7440000 { 2406 etm@7440000 {
2626 compatible = "arm,cor 2407 compatible = "arm,coresight-etm4x", "arm,primecell";
2627 reg = <0 0x07440000 0 2408 reg = <0 0x07440000 0 0x1000>;
2628 2409
2629 cpu = <&CPU4>; 2410 cpu = <&CPU4>;
2630 2411
2631 clocks = <&aoss_qmp>; 2412 clocks = <&aoss_qmp>;
2632 clock-names = "apb_pc 2413 clock-names = "apb_pclk";
2633 arm,coresight-loses-c 2414 arm,coresight-loses-context-with-cpu;
2634 qcom,skip-power-up; 2415 qcom,skip-power-up;
2635 2416
2636 out-ports { 2417 out-ports {
2637 port { 2418 port {
2638 etm4_ 2419 etm4_out: endpoint {
2639 2420 remote-endpoint = <&apss_funnel_in4>;
2640 }; 2421 };
2641 }; 2422 };
2642 }; 2423 };
2643 }; 2424 };
2644 2425
2645 etm@7540000 { 2426 etm@7540000 {
2646 compatible = "arm,cor 2427 compatible = "arm,coresight-etm4x", "arm,primecell";
2647 reg = <0 0x07540000 0 2428 reg = <0 0x07540000 0 0x1000>;
2648 2429
2649 cpu = <&CPU5>; 2430 cpu = <&CPU5>;
2650 2431
2651 clocks = <&aoss_qmp>; 2432 clocks = <&aoss_qmp>;
2652 clock-names = "apb_pc 2433 clock-names = "apb_pclk";
2653 arm,coresight-loses-c 2434 arm,coresight-loses-context-with-cpu;
2654 qcom,skip-power-up; 2435 qcom,skip-power-up;
2655 2436
2656 out-ports { 2437 out-ports {
2657 port { 2438 port {
2658 etm5_ 2439 etm5_out: endpoint {
2659 2440 remote-endpoint = <&apss_funnel_in5>;
2660 }; 2441 };
2661 }; 2442 };
2662 }; 2443 };
2663 }; 2444 };
2664 2445
2665 etm@7640000 { 2446 etm@7640000 {
2666 compatible = "arm,cor 2447 compatible = "arm,coresight-etm4x", "arm,primecell";
2667 reg = <0 0x07640000 0 2448 reg = <0 0x07640000 0 0x1000>;
2668 2449
2669 cpu = <&CPU6>; 2450 cpu = <&CPU6>;
2670 2451
2671 clocks = <&aoss_qmp>; 2452 clocks = <&aoss_qmp>;
2672 clock-names = "apb_pc 2453 clock-names = "apb_pclk";
2673 arm,coresight-loses-c 2454 arm,coresight-loses-context-with-cpu;
2674 qcom,skip-power-up; 2455 qcom,skip-power-up;
2675 2456
2676 out-ports { 2457 out-ports {
2677 port { 2458 port {
2678 etm6_ 2459 etm6_out: endpoint {
2679 2460 remote-endpoint = <&apss_funnel_in6>;
2680 }; 2461 };
2681 }; 2462 };
2682 }; 2463 };
2683 }; 2464 };
2684 2465
2685 etm@7740000 { 2466 etm@7740000 {
2686 compatible = "arm,cor 2467 compatible = "arm,coresight-etm4x", "arm,primecell";
2687 reg = <0 0x07740000 0 2468 reg = <0 0x07740000 0 0x1000>;
2688 2469
2689 cpu = <&CPU7>; 2470 cpu = <&CPU7>;
2690 2471
2691 clocks = <&aoss_qmp>; 2472 clocks = <&aoss_qmp>;
2692 clock-names = "apb_pc 2473 clock-names = "apb_pclk";
2693 arm,coresight-loses-c 2474 arm,coresight-loses-context-with-cpu;
2694 qcom,skip-power-up; 2475 qcom,skip-power-up;
2695 2476
2696 out-ports { 2477 out-ports {
2697 port { 2478 port {
2698 etm7_ 2479 etm7_out: endpoint {
2699 2480 remote-endpoint = <&apss_funnel_in7>;
2700 }; 2481 };
2701 }; 2482 };
2702 }; 2483 };
2703 }; 2484 };
2704 2485
2705 funnel@7800000 { /* APSS Funn 2486 funnel@7800000 { /* APSS Funnel */
2706 compatible = "arm,cor 2487 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2707 reg = <0 0x07800000 0 2488 reg = <0 0x07800000 0 0x1000>;
2708 2489
2709 clocks = <&aoss_qmp>; 2490 clocks = <&aoss_qmp>;
2710 clock-names = "apb_pc 2491 clock-names = "apb_pclk";
2711 2492
2712 out-ports { 2493 out-ports {
2713 port { 2494 port {
2714 apss_ 2495 apss_funnel_out: endpoint {
2715 2496 remote-endpoint = <&apss_merge_funnel_in>;
2716 }; 2497 };
2717 }; 2498 };
2718 }; 2499 };
2719 2500
2720 in-ports { 2501 in-ports {
2721 #address-cell 2502 #address-cells = <1>;
2722 #size-cells = 2503 #size-cells = <0>;
2723 2504
2724 port@0 { 2505 port@0 {
2725 reg = 2506 reg = <0>;
2726 apss_ 2507 apss_funnel_in0: endpoint {
2727 2508 remote-endpoint = <&etm0_out>;
2728 }; 2509 };
2729 }; 2510 };
2730 2511
2731 port@1 { 2512 port@1 {
2732 reg = 2513 reg = <1>;
2733 apss_ 2514 apss_funnel_in1: endpoint {
2734 2515 remote-endpoint = <&etm1_out>;
2735 }; 2516 };
2736 }; 2517 };
2737 2518
2738 port@2 { 2519 port@2 {
2739 reg = 2520 reg = <2>;
2740 apss_ 2521 apss_funnel_in2: endpoint {
2741 2522 remote-endpoint = <&etm2_out>;
2742 }; 2523 };
2743 }; 2524 };
2744 2525
2745 port@3 { 2526 port@3 {
2746 reg = 2527 reg = <3>;
2747 apss_ 2528 apss_funnel_in3: endpoint {
2748 2529 remote-endpoint = <&etm3_out>;
2749 }; 2530 };
2750 }; 2531 };
2751 2532
2752 port@4 { 2533 port@4 {
2753 reg = 2534 reg = <4>;
2754 apss_ 2535 apss_funnel_in4: endpoint {
2755 2536 remote-endpoint = <&etm4_out>;
2756 }; 2537 };
2757 }; 2538 };
2758 2539
2759 port@5 { 2540 port@5 {
2760 reg = 2541 reg = <5>;
2761 apss_ 2542 apss_funnel_in5: endpoint {
2762 2543 remote-endpoint = <&etm5_out>;
2763 }; 2544 };
2764 }; 2545 };
2765 2546
2766 port@6 { 2547 port@6 {
2767 reg = 2548 reg = <6>;
2768 apss_ 2549 apss_funnel_in6: endpoint {
2769 2550 remote-endpoint = <&etm6_out>;
2770 }; 2551 };
2771 }; 2552 };
2772 2553
2773 port@7 { 2554 port@7 {
2774 reg = 2555 reg = <7>;
2775 apss_ 2556 apss_funnel_in7: endpoint {
2776 2557 remote-endpoint = <&etm7_out>;
2777 }; 2558 };
2778 }; 2559 };
2779 }; 2560 };
2780 }; 2561 };
2781 2562
2782 funnel@7810000 { 2563 funnel@7810000 {
2783 compatible = "arm,cor 2564 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2784 reg = <0 0x07810000 0 2565 reg = <0 0x07810000 0 0x1000>;
2785 2566
2786 clocks = <&aoss_qmp>; 2567 clocks = <&aoss_qmp>;
2787 clock-names = "apb_pc 2568 clock-names = "apb_pclk";
2788 2569
2789 out-ports { 2570 out-ports {
2790 port { 2571 port {
2791 apss_ 2572 apss_merge_funnel_out: endpoint {
2792 2573 remote-endpoint = <&funnel1_in4>;
2793 }; 2574 };
2794 }; 2575 };
2795 }; 2576 };
2796 2577
2797 in-ports { 2578 in-ports {
2798 port { 2579 port {
2799 apss_ 2580 apss_merge_funnel_in: endpoint {
2800 2581 remote-endpoint = <&apss_funnel_out>;
2801 }; 2582 };
2802 }; 2583 };
2803 }; 2584 };
2804 }; 2585 };
2805 2586
2806 sdhc_2: mmc@8804000 { !! 2587 sdhc_2: sdhci@8804000 {
2807 compatible = "qcom,sc 2588 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
2808 reg = <0 0x08804000 0 2589 reg = <0 0x08804000 0 0x1000>;
2809 2590
2810 iommus = <&apps_smmu 2591 iommus = <&apps_smmu 0x80 0>;
2811 interrupts = <GIC_SPI 2592 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
2812 <GIC_ 2593 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
2813 interrupt-names = "hc 2594 interrupt-names = "hc_irq", "pwr_irq";
2814 2595
2815 clocks = <&gcc GCC_SD !! 2596 clocks = <&gcc GCC_SDCC2_APPS_CLK>,
2816 <&gcc GCC_SD !! 2597 <&gcc GCC_SDCC2_AHB_CLK>,
2817 <&rpmhcc RPM 2598 <&rpmhcc RPMH_CXO_CLK>;
2818 clock-names = "iface" !! 2599 clock-names = "core", "iface", "xo";
2819 2600
2820 interconnects = <&agg 2601 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
2821 <&gem 2602 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
2822 interconnect-names = 2603 interconnect-names = "sdhc-ddr","cpu-sdhc";
2823 power-domains = <&rpm 2604 power-domains = <&rpmhpd SC7180_CX>;
2824 operating-points-v2 = 2605 operating-points-v2 = <&sdhc2_opp_table>;
2825 2606
2826 bus-width = <4>; 2607 bus-width = <4>;
2827 2608
2828 status = "disabled"; 2609 status = "disabled";
2829 2610
2830 sdhc2_opp_table: opp- !! 2611 sdhc2_opp_table: sdhc2-opp-table {
2831 compatible = 2612 compatible = "operating-points-v2";
2832 2613
2833 opp-100000000 2614 opp-100000000 {
2834 opp-h 2615 opp-hz = /bits/ 64 <100000000>;
2835 requi 2616 required-opps = <&rpmhpd_opp_low_svs>;
2836 opp-p 2617 opp-peak-kBps = <1800000 600000>;
2837 opp-a 2618 opp-avg-kBps = <100000 0>;
2838 }; 2619 };
2839 2620
2840 opp-202000000 2621 opp-202000000 {
2841 opp-h 2622 opp-hz = /bits/ 64 <202000000>;
2842 requi 2623 required-opps = <&rpmhpd_opp_nom>;
2843 opp-p 2624 opp-peak-kBps = <5400000 1600000>;
2844 opp-a 2625 opp-avg-kBps = <200000 0>;
2845 }; 2626 };
2846 }; 2627 };
2847 }; 2628 };
2848 2629
>> 2630 qspi_opp_table: qspi-opp-table {
>> 2631 compatible = "operating-points-v2";
>> 2632
>> 2633 opp-75000000 {
>> 2634 opp-hz = /bits/ 64 <75000000>;
>> 2635 required-opps = <&rpmhpd_opp_low_svs>;
>> 2636 };
>> 2637
>> 2638 opp-150000000 {
>> 2639 opp-hz = /bits/ 64 <150000000>;
>> 2640 required-opps = <&rpmhpd_opp_svs>;
>> 2641 };
>> 2642
>> 2643 opp-300000000 {
>> 2644 opp-hz = /bits/ 64 <300000000>;
>> 2645 required-opps = <&rpmhpd_opp_nom>;
>> 2646 };
>> 2647 };
>> 2648
2849 qspi: spi@88dc000 { 2649 qspi: spi@88dc000 {
2850 compatible = "qcom,sc 2650 compatible = "qcom,sc7180-qspi", "qcom,qspi-v1";
2851 reg = <0 0x088dc000 0 2651 reg = <0 0x088dc000 0 0x600>;
2852 iommus = <&apps_smmu <<
2853 #address-cells = <1>; 2652 #address-cells = <1>;
2854 #size-cells = <0>; 2653 #size-cells = <0>;
2855 interrupts = <GIC_SPI 2654 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
2856 clocks = <&gcc GCC_QS 2655 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
2857 <&gcc GCC_QS 2656 <&gcc GCC_QSPI_CORE_CLK>;
2858 clock-names = "iface" 2657 clock-names = "iface", "core";
2859 interconnects = <&gem 2658 interconnects = <&gem_noc MASTER_APPSS_PROC 0
2860 &conf 2659 &config_noc SLAVE_QSPI_0 0>;
2861 interconnect-names = 2660 interconnect-names = "qspi-config";
2862 power-domains = <&rpm 2661 power-domains = <&rpmhpd SC7180_CX>;
2863 operating-points-v2 = 2662 operating-points-v2 = <&qspi_opp_table>;
2864 status = "disabled"; 2663 status = "disabled";
2865 }; 2664 };
2866 2665
2867 usb_1_hsphy: phy@88e3000 { 2666 usb_1_hsphy: phy@88e3000 {
2868 compatible = "qcom,sc 2667 compatible = "qcom,sc7180-qusb2-phy", "qcom,qusb2-v2-phy";
2869 reg = <0 0x088e3000 0 2668 reg = <0 0x088e3000 0 0x400>;
2870 status = "disabled"; 2669 status = "disabled";
2871 #phy-cells = <0>; 2670 #phy-cells = <0>;
2872 clocks = <&gcc GCC_US 2671 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2873 <&rpmhcc RPM 2672 <&rpmhcc RPMH_CXO_CLK>;
2874 clock-names = "cfg_ah 2673 clock-names = "cfg_ahb", "ref";
2875 resets = <&gcc GCC_QU 2674 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2876 2675
2877 nvmem-cells = <&qusb2 2676 nvmem-cells = <&qusb2p_hstx_trim>;
2878 }; 2677 };
2879 2678
2880 usb_1_qmpphy: phy@88e8000 { !! 2679 usb_1_qmpphy: phy-wrapper@88e9000 {
2881 compatible = "qcom,sc 2680 compatible = "qcom,sc7180-qmp-usb3-dp-phy";
2882 reg = <0 0x088e8000 0 !! 2681 reg = <0 0x088e9000 0 0x18c>,
>> 2682 <0 0x088e8000 0 0x3c>,
>> 2683 <0 0x088ea000 0 0x18c>;
2883 status = "disabled"; 2684 status = "disabled";
>> 2685 #address-cells = <2>;
>> 2686 #size-cells = <2>;
>> 2687 ranges;
2884 2688
2885 clocks = <&gcc GCC_US 2689 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
>> 2690 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2886 <&gcc GCC_US 2691 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
2887 <&gcc GCC_US !! 2692 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
2888 <&gcc GCC_US !! 2693 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
2889 <&gcc GCC_US <<
2890 clock-names = "aux", <<
2891 "ref", <<
2892 "com_au <<
2893 "usb3_p <<
2894 "cfg_ah <<
2895 2694
2896 resets = <&gcc GCC_US 2695 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
2897 <&gcc GCC_US 2696 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
2898 reset-names = "phy", 2697 reset-names = "phy", "common";
2899 2698
2900 #clock-cells = <1>; !! 2699 usb_1_ssphy: usb3-phy@88e9200 {
2901 #phy-cells = <1>; !! 2700 reg = <0 0x088e9200 0 0x128>,
2902 }; !! 2701 <0 0x088e9400 0 0x200>,
2903 !! 2702 <0 0x088e9c00 0 0x218>,
2904 pmu@90b6300 { !! 2703 <0 0x088e9600 0 0x128>,
2905 compatible = "qcom,sc !! 2704 <0 0x088e9800 0 0x200>,
2906 reg = <0 0x090b6300 0 !! 2705 <0 0x088e9a00 0 0x18>;
2907 interrupts = <GIC_SPI !! 2706 #clock-cells = <0>;
2908 !! 2707 #phy-cells = <0>;
2909 interconnects = <&gem !! 2708 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2910 &gem !! 2709 clock-names = "pipe0";
2911 operating-points-v2 = !! 2710 clock-output-names = "usb3_phy_pipe_clk_src";
2912 <<
2913 cpu_bwmon_opp_table: <<
2914 compatible = <<
2915 <<
2916 opp-0 { <<
2917 opp-p <<
2918 }; <<
2919 <<
2920 opp-1 { <<
2921 opp-p <<
2922 }; <<
2923 <<
2924 opp-2 { <<
2925 opp-p <<
2926 }; <<
2927 <<
2928 opp-3 { <<
2929 opp-p <<
2930 }; <<
2931 <<
2932 opp-4 { <<
2933 opp-p <<
2934 }; <<
2935 <<
2936 opp-5 { <<
2937 opp-p <<
2938 }; <<
2939 }; 2711 };
2940 }; <<
2941 <<
2942 pmu@90cd000 { <<
2943 compatible = "qcom,sc <<
2944 reg = <0 0x090cd000 0 <<
2945 interrupts = <GIC_SPI <<
2946 <<
2947 interconnects = <&mc_ <<
2948 &mc_ <<
2949 operating-points-v2 = <<
2950 <<
2951 llcc_bwmon_opp_table: <<
2952 compatible = <<
2953 <<
2954 opp-0 { <<
2955 opp-p <<
2956 }; <<
2957 <<
2958 opp-1 { <<
2959 opp-p <<
2960 }; <<
2961 <<
2962 opp-2 { <<
2963 opp-p <<
2964 }; <<
2965 <<
2966 opp-3 { <<
2967 opp-p <<
2968 }; <<
2969 <<
2970 opp-4 { <<
2971 opp-p <<
2972 }; <<
2973 2712
2974 opp-5 { !! 2713 dp_phy: dp-phy@88ea200 {
2975 opp-p !! 2714 reg = <0 0x088ea200 0 0x200>,
2976 }; !! 2715 <0 0x088ea400 0 0x200>,
2977 !! 2716 <0 0x088eaa00 0 0x200>,
2978 opp-6 { !! 2717 <0 0x088ea600 0 0x200>,
2979 opp-p !! 2718 <0 0x088ea800 0 0x200>;
2980 }; !! 2719 #clock-cells = <1>;
2981 !! 2720 #phy-cells = <0>;
2982 opp-7 { <<
2983 opp-p <<
2984 }; <<
2985 }; 2721 };
2986 }; 2722 };
2987 2723
2988 dc_noc: interconnect@9160000 2724 dc_noc: interconnect@9160000 {
2989 compatible = "qcom,sc 2725 compatible = "qcom,sc7180-dc-noc";
2990 reg = <0 0x09160000 0 2726 reg = <0 0x09160000 0 0x03200>;
2991 #interconnect-cells = 2727 #interconnect-cells = <2>;
2992 qcom,bcm-voters = <&a 2728 qcom,bcm-voters = <&apps_bcm_voter>;
2993 }; 2729 };
2994 2730
2995 system-cache-controller@92000 2731 system-cache-controller@9200000 {
2996 compatible = "qcom,sc 2732 compatible = "qcom,sc7180-llcc";
2997 reg = <0 0x09200000 0 2733 reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>;
2998 reg-names = "llcc0_ba !! 2734 reg-names = "llcc_base", "llcc_broadcast_base";
2999 interrupts = <GIC_SPI 2735 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
3000 }; 2736 };
3001 2737
3002 gem_noc: interconnect@9680000 2738 gem_noc: interconnect@9680000 {
3003 compatible = "qcom,sc 2739 compatible = "qcom,sc7180-gem-noc";
3004 reg = <0 0x09680000 0 2740 reg = <0 0x09680000 0 0x3e200>;
3005 #interconnect-cells = 2741 #interconnect-cells = <2>;
3006 qcom,bcm-voters = <&a 2742 qcom,bcm-voters = <&apps_bcm_voter>;
3007 }; 2743 };
3008 2744
3009 npu_noc: interconnect@9990000 2745 npu_noc: interconnect@9990000 {
3010 compatible = "qcom,sc 2746 compatible = "qcom,sc7180-npu-noc";
3011 reg = <0 0x09990000 0 2747 reg = <0 0x09990000 0 0x1600>;
3012 #interconnect-cells = 2748 #interconnect-cells = <2>;
3013 qcom,bcm-voters = <&a 2749 qcom,bcm-voters = <&apps_bcm_voter>;
3014 }; 2750 };
3015 2751
3016 usb_1: usb@a6f8800 { 2752 usb_1: usb@a6f8800 {
3017 compatible = "qcom,sc 2753 compatible = "qcom,sc7180-dwc3", "qcom,dwc3";
3018 reg = <0 0x0a6f8800 0 2754 reg = <0 0x0a6f8800 0 0x400>;
3019 status = "disabled"; 2755 status = "disabled";
3020 #address-cells = <2>; 2756 #address-cells = <2>;
3021 #size-cells = <2>; 2757 #size-cells = <2>;
3022 ranges; 2758 ranges;
3023 dma-ranges; 2759 dma-ranges;
3024 2760
3025 clocks = <&gcc GCC_CF 2761 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
3026 <&gcc GCC_US 2762 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
3027 <&gcc GCC_AG 2763 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
3028 <&gcc GCC_US !! 2764 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3029 <&gcc GCC_US !! 2765 <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
3030 clock-names = "cfg_no !! 2766 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
3031 "core", !! 2767 "sleep";
3032 "iface" <<
3033 "sleep" <<
3034 "mock_u <<
3035 2768
3036 assigned-clocks = <&g 2769 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3037 <&g 2770 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
3038 assigned-clock-rates 2771 assigned-clock-rates = <19200000>, <150000000>;
3039 2772
3040 interrupts-extended = !! 2773 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
3041 !! 2774 <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
3042 !! 2775 <&pdc 8 IRQ_TYPE_LEVEL_HIGH>,
3043 !! 2776 <&pdc 9 IRQ_TYPE_LEVEL_HIGH>;
3044 !! 2777 interrupt-names = "hs_phy_irq", "ss_phy_irq",
3045 interrupt-names = "pw !! 2778 "dm_hs_phy_irq", "dp_hs_phy_irq";
3046 "hs <<
3047 "dp <<
3048 "dm <<
3049 "ss <<
3050 2779
3051 power-domains = <&gcc 2780 power-domains = <&gcc USB30_PRIM_GDSC>;
3052 required-opps = <&rpm <<
3053 2781
3054 resets = <&gcc GCC_US 2782 resets = <&gcc GCC_USB30_PRIM_BCR>;
3055 2783
3056 interconnects = <&agg 2784 interconnects = <&aggre2_noc MASTER_USB3 0 &mc_virt SLAVE_EBI1 0>,
3057 <&gem 2785 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3 0>;
3058 interconnect-names = 2786 interconnect-names = "usb-ddr", "apps-usb";
3059 2787
3060 wakeup-source; !! 2788 usb_1_dwc3: dwc3@a600000 {
3061 <<
3062 usb_1_dwc3: usb@a6000 <<
3063 compatible = 2789 compatible = "snps,dwc3";
3064 reg = <0 0x0a 2790 reg = <0 0x0a600000 0 0xe000>;
3065 interrupts = 2791 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
3066 iommus = <&ap 2792 iommus = <&apps_smmu 0x540 0>;
3067 snps,dis_u2_s 2793 snps,dis_u2_susphy_quirk;
3068 snps,dis_enbl 2794 snps,dis_enblslpm_quirk;
3069 snps,parkmode !! 2795 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
3070 phys = <&usb_ <<
3071 phy-names = " 2796 phy-names = "usb2-phy", "usb3-phy";
3072 maximum-speed 2797 maximum-speed = "super-speed";
3073 }; 2798 };
3074 }; 2799 };
3075 2800
3076 venus: video-codec@aa00000 { 2801 venus: video-codec@aa00000 {
3077 compatible = "qcom,sc 2802 compatible = "qcom,sc7180-venus";
3078 reg = <0 0x0aa00000 0 2803 reg = <0 0x0aa00000 0 0xff000>;
3079 interrupts = <GIC_SPI 2804 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
3080 power-domains = <&vid 2805 power-domains = <&videocc VENUS_GDSC>,
3081 <&vid 2806 <&videocc VCODEC0_GDSC>,
3082 <&rpm 2807 <&rpmhpd SC7180_CX>;
3083 power-domain-names = 2808 power-domain-names = "venus", "vcodec0", "cx";
3084 operating-points-v2 = 2809 operating-points-v2 = <&venus_opp_table>;
3085 clocks = <&videocc VI 2810 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
3086 <&videocc VI 2811 <&videocc VIDEO_CC_VENUS_AHB_CLK>,
3087 <&videocc VI 2812 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>,
3088 <&videocc VI 2813 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
3089 <&videocc VI 2814 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>;
3090 clock-names = "core", 2815 clock-names = "core", "iface", "bus",
3091 "vcodec 2816 "vcodec0_core", "vcodec0_bus";
3092 iommus = <&apps_smmu 2817 iommus = <&apps_smmu 0x0c00 0x60>;
3093 memory-region = <&ven 2818 memory-region = <&venus_mem>;
3094 interconnects = <&mms 2819 interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>,
3095 <&gem 2820 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>;
3096 interconnect-names = 2821 interconnect-names = "video-mem", "cpu-cfg";
3097 2822
3098 video-decoder { 2823 video-decoder {
3099 compatible = 2824 compatible = "venus-decoder";
3100 }; 2825 };
3101 2826
3102 video-encoder { 2827 video-encoder {
3103 compatible = 2828 compatible = "venus-encoder";
3104 }; 2829 };
3105 2830
3106 venus_opp_table: opp- !! 2831 venus_opp_table: venus-opp-table {
3107 compatible = 2832 compatible = "operating-points-v2";
3108 2833
3109 opp-150000000 2834 opp-150000000 {
3110 opp-h 2835 opp-hz = /bits/ 64 <150000000>;
3111 requi 2836 required-opps = <&rpmhpd_opp_low_svs>;
3112 }; 2837 };
3113 2838
3114 opp-270000000 2839 opp-270000000 {
3115 opp-h 2840 opp-hz = /bits/ 64 <270000000>;
3116 requi 2841 required-opps = <&rpmhpd_opp_svs>;
3117 }; 2842 };
3118 2843
3119 opp-340000000 2844 opp-340000000 {
3120 opp-h 2845 opp-hz = /bits/ 64 <340000000>;
3121 requi 2846 required-opps = <&rpmhpd_opp_svs_l1>;
3122 }; 2847 };
3123 2848
3124 opp-434000000 2849 opp-434000000 {
3125 opp-h 2850 opp-hz = /bits/ 64 <434000000>;
3126 requi 2851 required-opps = <&rpmhpd_opp_nom>;
3127 }; 2852 };
3128 2853
3129 opp-500000097 2854 opp-500000097 {
3130 opp-h 2855 opp-hz = /bits/ 64 <500000097>;
3131 requi 2856 required-opps = <&rpmhpd_opp_turbo>;
3132 }; 2857 };
3133 }; 2858 };
3134 }; 2859 };
3135 2860
3136 videocc: clock-controller@ab0 2861 videocc: clock-controller@ab00000 {
3137 compatible = "qcom,sc 2862 compatible = "qcom,sc7180-videocc";
3138 reg = <0 0x0ab00000 0 2863 reg = <0 0x0ab00000 0 0x10000>;
3139 clocks = <&rpmhcc RPM 2864 clocks = <&rpmhcc RPMH_CXO_CLK>;
3140 clock-names = "bi_tcx 2865 clock-names = "bi_tcxo";
3141 #clock-cells = <1>; 2866 #clock-cells = <1>;
3142 #reset-cells = <1>; 2867 #reset-cells = <1>;
3143 #power-domain-cells = 2868 #power-domain-cells = <1>;
3144 }; 2869 };
3145 2870
3146 camnoc_virt: interconnect@ac0 2871 camnoc_virt: interconnect@ac00000 {
3147 compatible = "qcom,sc 2872 compatible = "qcom,sc7180-camnoc-virt";
3148 reg = <0 0x0ac00000 0 2873 reg = <0 0x0ac00000 0 0x1000>;
3149 #interconnect-cells = 2874 #interconnect-cells = <2>;
3150 qcom,bcm-voters = <&a 2875 qcom,bcm-voters = <&apps_bcm_voter>;
3151 }; 2876 };
3152 2877
3153 camcc: clock-controller@ad000 2878 camcc: clock-controller@ad00000 {
3154 compatible = "qcom,sc 2879 compatible = "qcom,sc7180-camcc";
3155 reg = <0 0x0ad00000 0 2880 reg = <0 0x0ad00000 0 0x10000>;
3156 clocks = <&rpmhcc RPM 2881 clocks = <&rpmhcc RPMH_CXO_CLK>,
3157 <&gcc GCC_CAME 2882 <&gcc GCC_CAMERA_AHB_CLK>,
3158 <&gcc GCC_CAME 2883 <&gcc GCC_CAMERA_XO_CLK>;
3159 clock-names = "bi_tcx 2884 clock-names = "bi_tcxo", "iface", "xo";
3160 #clock-cells = <1>; 2885 #clock-cells = <1>;
3161 #reset-cells = <1>; 2886 #reset-cells = <1>;
3162 #power-domain-cells = 2887 #power-domain-cells = <1>;
3163 }; 2888 };
3164 2889
3165 mdss: display-subsystem@ae000 !! 2890 mdss: mdss@ae00000 {
3166 compatible = "qcom,sc 2891 compatible = "qcom,sc7180-mdss";
3167 reg = <0 0x0ae00000 0 2892 reg = <0 0x0ae00000 0 0x1000>;
3168 reg-names = "mdss"; 2893 reg-names = "mdss";
3169 2894
3170 power-domains = <&dis 2895 power-domains = <&dispcc MDSS_GDSC>;
3171 2896
3172 clocks = <&gcc GCC_DI 2897 clocks = <&gcc GCC_DISP_AHB_CLK>,
3173 <&dispcc DIS 2898 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3174 <&dispcc DIS 2899 <&dispcc DISP_CC_MDSS_MDP_CLK>;
3175 clock-names = "iface" 2900 clock-names = "iface", "ahb", "core";
3176 2901
>> 2902 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
>> 2903 assigned-clock-rates = <300000000>;
>> 2904
3177 interrupts = <GIC_SPI 2905 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
3178 interrupt-controller; 2906 interrupt-controller;
3179 #interrupt-cells = <1 2907 #interrupt-cells = <1>;
3180 2908
3181 interconnects = <&mms !! 2909 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>;
3182 &mc_ !! 2910 interconnect-names = "mdp0-mem";
3183 <&gem <<
3184 &con <<
3185 interconnect-names = <<
3186 <<
3187 2911
3188 iommus = <&apps_smmu 2912 iommus = <&apps_smmu 0x800 0x2>;
3189 2913
3190 #address-cells = <2>; 2914 #address-cells = <2>;
3191 #size-cells = <2>; 2915 #size-cells = <2>;
3192 ranges; 2916 ranges;
3193 2917
3194 status = "disabled"; 2918 status = "disabled";
3195 2919
3196 mdp: display-controll !! 2920 mdp: mdp@ae01000 {
3197 compatible = 2921 compatible = "qcom,sc7180-dpu";
3198 reg = <0 0x0a 2922 reg = <0 0x0ae01000 0 0x8f000>,
3199 <0 0x0a 2923 <0 0x0aeb0000 0 0x2008>;
3200 reg-names = " 2924 reg-names = "mdp", "vbif";
3201 2925
3202 clocks = <&gc 2926 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
3203 <&di 2927 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3204 <&di 2928 <&dispcc DISP_CC_MDSS_ROT_CLK>,
3205 <&di 2929 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
3206 <&di 2930 <&dispcc DISP_CC_MDSS_MDP_CLK>,
3207 <&di 2931 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3208 clock-names = 2932 clock-names = "bus", "iface", "rot", "lut", "core",
3209 2933 "vsync";
3210 assigned-cloc !! 2934 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
>> 2935 <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
3211 2936 <&dispcc DISP_CC_MDSS_ROT_CLK>,
3212 2937 <&dispcc DISP_CC_MDSS_AHB_CLK>;
3213 assigned-cloc !! 2938 assigned-clock-rates = <300000000>,
>> 2939 <19200000>,
3214 2940 <19200000>,
3215 2941 <19200000>;
3216 operating-poi 2942 operating-points-v2 = <&mdp_opp_table>;
3217 power-domains 2943 power-domains = <&rpmhpd SC7180_CX>;
3218 2944
3219 interrupt-par 2945 interrupt-parent = <&mdss>;
3220 interrupts = 2946 interrupts = <0>;
3221 2947
>> 2948 status = "disabled";
>> 2949
3222 ports { 2950 ports {
3223 #addr 2951 #address-cells = <1>;
3224 #size 2952 #size-cells = <0>;
3225 2953
3226 port@ 2954 port@0 {
3227 2955 reg = <0>;
3228 2956 dpu_intf1_out: endpoint {
3229 !! 2957 remote-endpoint = <&dsi0_in>;
3230 2958 };
3231 }; 2959 };
3232 2960
3233 port@ 2961 port@2 {
3234 2962 reg = <2>;
3235 2963 dpu_intf0_out: endpoint {
3236 2964 remote-endpoint = <&dp_in>;
3237 2965 };
3238 }; 2966 };
3239 }; 2967 };
3240 2968
3241 mdp_opp_table !! 2969 mdp_opp_table: mdp-opp-table {
3242 compa 2970 compatible = "operating-points-v2";
3243 2971
3244 opp-2 2972 opp-200000000 {
3245 2973 opp-hz = /bits/ 64 <200000000>;
3246 2974 required-opps = <&rpmhpd_opp_low_svs>;
3247 }; 2975 };
3248 2976
3249 opp-3 2977 opp-300000000 {
3250 2978 opp-hz = /bits/ 64 <300000000>;
3251 2979 required-opps = <&rpmhpd_opp_svs>;
3252 }; 2980 };
3253 2981
3254 opp-3 2982 opp-345000000 {
3255 2983 opp-hz = /bits/ 64 <345000000>;
3256 2984 required-opps = <&rpmhpd_opp_svs_l1>;
3257 }; 2985 };
3258 2986
3259 opp-4 2987 opp-460000000 {
3260 2988 opp-hz = /bits/ 64 <460000000>;
3261 2989 required-opps = <&rpmhpd_opp_nom>;
3262 }; 2990 };
3263 }; 2991 };
>> 2992
3264 }; 2993 };
3265 2994
3266 mdss_dsi0: dsi@ae9400 !! 2995 dsi0: dsi@ae94000 {
3267 compatible = !! 2996 compatible = "qcom,mdss-dsi-ctrl";
3268 <<
3269 reg = <0 0x0a 2997 reg = <0 0x0ae94000 0 0x400>;
3270 reg-names = " 2998 reg-names = "dsi_ctrl";
3271 2999
3272 interrupt-par 3000 interrupt-parent = <&mdss>;
3273 interrupts = 3001 interrupts = <4>;
3274 3002
3275 clocks = <&di 3003 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
3276 <&di 3004 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
3277 <&di 3005 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
3278 <&di 3006 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
3279 <&di 3007 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3280 <&gc 3008 <&gcc GCC_DISP_HF_AXI_CLK>;
3281 clock-names = 3009 clock-names = "byte",
3282 3010 "byte_intf",
3283 3011 "pixel",
3284 3012 "core",
3285 3013 "iface",
3286 3014 "bus";
3287 3015
3288 assigned-cloc 3016 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
3289 assigned-cloc !! 3017 assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>;
3290 3018
3291 operating-poi 3019 operating-points-v2 = <&dsi_opp_table>;
3292 power-domains 3020 power-domains = <&rpmhpd SC7180_CX>;
3293 3021
3294 phys = <&mdss !! 3022 phys = <&dsi_phy>;
>> 3023 phy-names = "dsi";
3295 3024
3296 #address-cell 3025 #address-cells = <1>;
3297 #size-cells = 3026 #size-cells = <0>;
3298 3027
3299 status = "dis 3028 status = "disabled";
3300 3029
3301 ports { 3030 ports {
3302 #addr 3031 #address-cells = <1>;
3303 #size 3032 #size-cells = <0>;
3304 3033
3305 port@ 3034 port@0 {
3306 3035 reg = <0>;
3307 !! 3036 dsi0_in: endpoint {
3308 3037 remote-endpoint = <&dpu_intf1_out>;
3309 3038 };
3310 }; 3039 };
3311 3040
3312 port@ 3041 port@1 {
3313 3042 reg = <1>;
3314 !! 3043 dsi0_out: endpoint {
3315 3044 };
3316 }; 3045 };
3317 }; 3046 };
3318 3047
3319 dsi_opp_table !! 3048 dsi_opp_table: dsi-opp-table {
3320 compa 3049 compatible = "operating-points-v2";
3321 3050
3322 opp-1 3051 opp-187500000 {
3323 3052 opp-hz = /bits/ 64 <187500000>;
3324 3053 required-opps = <&rpmhpd_opp_low_svs>;
3325 }; 3054 };
3326 3055
3327 opp-3 3056 opp-300000000 {
3328 3057 opp-hz = /bits/ 64 <300000000>;
3329 3058 required-opps = <&rpmhpd_opp_svs>;
3330 }; 3059 };
3331 3060
3332 opp-3 3061 opp-358000000 {
3333 3062 opp-hz = /bits/ 64 <358000000>;
3334 3063 required-opps = <&rpmhpd_opp_svs_l1>;
3335 }; 3064 };
3336 }; 3065 };
3337 }; 3066 };
3338 3067
3339 mdss_dsi0_phy: phy@ae !! 3068 dsi_phy: dsi-phy@ae94400 {
3340 compatible = 3069 compatible = "qcom,dsi-phy-10nm";
3341 reg = <0 0x0a 3070 reg = <0 0x0ae94400 0 0x200>,
3342 <0 0x0a 3071 <0 0x0ae94600 0 0x280>,
3343 <0 0x0a 3072 <0 0x0ae94a00 0 0x1e0>;
3344 reg-names = " 3073 reg-names = "dsi_phy",
3345 " 3074 "dsi_phy_lane",
3346 " 3075 "dsi_pll";
3347 3076
3348 #clock-cells 3077 #clock-cells = <1>;
3349 #phy-cells = 3078 #phy-cells = <0>;
3350 3079
3351 clocks = <&di 3080 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3352 <&rp 3081 <&rpmhcc RPMH_CXO_CLK>;
3353 clock-names = 3082 clock-names = "iface", "ref";
3354 3083
3355 status = "dis 3084 status = "disabled";
3356 }; 3085 };
3357 3086
3358 mdss_dp: displayport- 3087 mdss_dp: displayport-controller@ae90000 {
3359 compatible = 3088 compatible = "qcom,sc7180-dp";
3360 status = "dis 3089 status = "disabled";
3361 3090
3362 reg = <0 0x0a !! 3091 reg = <0 0x0ae90000 0 0x1400>;
3363 <0 0x0a <<
3364 <0 0x0a <<
3365 <0 0x0a <<
3366 <0 0x0a <<
3367 3092
3368 interrupt-par 3093 interrupt-parent = <&mdss>;
3369 interrupts = 3094 interrupts = <12>;
3370 3095
3371 clocks = <&di 3096 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3372 <&di 3097 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
3373 <&di 3098 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
3374 <&di 3099 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
3375 <&di 3100 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
3376 clock-names = 3101 clock-names = "core_iface", "core_aux", "ctrl_link",
3377 3102 "ctrl_link_iface", "stream_pixel";
>> 3103 #clock-cells = <1>;
3378 assigned-cloc 3104 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
3379 3105 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
3380 assigned-cloc !! 3106 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
3381 !! 3107 phys = <&dp_phy>;
3382 phys = <&usb_ <<
3383 phy-names = " 3108 phy-names = "dp";
3384 3109
3385 operating-poi 3110 operating-points-v2 = <&dp_opp_table>;
3386 power-domains 3111 power-domains = <&rpmhpd SC7180_CX>;
3387 3112
3388 #sound-dai-ce 3113 #sound-dai-cells = <0>;
3389 3114
3390 ports { 3115 ports {
3391 #addr 3116 #address-cells = <1>;
3392 #size 3117 #size-cells = <0>;
3393 port@ 3118 port@0 {
3394 3119 reg = <0>;
3395 3120 dp_in: endpoint {
3396 3121 remote-endpoint = <&dpu_intf0_out>;
3397 3122 };
3398 }; 3123 };
3399 3124
3400 port@ 3125 port@1 {
3401 3126 reg = <1>;
3402 !! 3127 dp_out: endpoint { };
3403 }; 3128 };
3404 }; 3129 };
3405 3130
3406 dp_opp_table: 3131 dp_opp_table: opp-table {
3407 compa 3132 compatible = "operating-points-v2";
3408 3133
3409 opp-1 3134 opp-160000000 {
3410 3135 opp-hz = /bits/ 64 <160000000>;
3411 3136 required-opps = <&rpmhpd_opp_low_svs>;
3412 }; 3137 };
3413 3138
3414 opp-2 3139 opp-270000000 {
3415 3140 opp-hz = /bits/ 64 <270000000>;
3416 3141 required-opps = <&rpmhpd_opp_svs>;
3417 }; 3142 };
3418 3143
3419 opp-5 3144 opp-540000000 {
3420 3145 opp-hz = /bits/ 64 <540000000>;
3421 3146 required-opps = <&rpmhpd_opp_svs_l1>;
3422 }; 3147 };
3423 3148
3424 opp-8 3149 opp-810000000 {
3425 3150 opp-hz = /bits/ 64 <810000000>;
3426 3151 required-opps = <&rpmhpd_opp_nom>;
3427 }; 3152 };
3428 }; 3153 };
3429 }; 3154 };
3430 }; 3155 };
3431 3156
3432 dispcc: clock-controller@af00 3157 dispcc: clock-controller@af00000 {
3433 compatible = "qcom,sc 3158 compatible = "qcom,sc7180-dispcc";
3434 reg = <0 0x0af00000 0 3159 reg = <0 0x0af00000 0 0x200000>;
3435 clocks = <&rpmhcc RPM 3160 clocks = <&rpmhcc RPMH_CXO_CLK>,
3436 <&gcc GCC_DI 3161 <&gcc GCC_DISP_GPLL0_CLK_SRC>,
3437 <&mdss_dsi0_ !! 3162 <&dsi_phy 0>,
3438 <&mdss_dsi0_ !! 3163 <&dsi_phy 1>,
3439 <&usb_1_qmpp !! 3164 <&dp_phy 0>,
3440 <&usb_1_qmpp !! 3165 <&dp_phy 1>;
3441 clock-names = "bi_tcx 3166 clock-names = "bi_tcxo",
3442 "gcc_di 3167 "gcc_disp_gpll0_clk_src",
3443 "dsi0_p 3168 "dsi0_phy_pll_out_byteclk",
3444 "dsi0_p 3169 "dsi0_phy_pll_out_dsiclk",
3445 "dp_phy 3170 "dp_phy_pll_link_clk",
3446 "dp_phy 3171 "dp_phy_pll_vco_div_clk";
3447 #clock-cells = <1>; 3172 #clock-cells = <1>;
3448 #reset-cells = <1>; 3173 #reset-cells = <1>;
3449 #power-domain-cells = 3174 #power-domain-cells = <1>;
3450 }; 3175 };
3451 3176
3452 pdc: interrupt-controller@b22 3177 pdc: interrupt-controller@b220000 {
3453 compatible = "qcom,sc 3178 compatible = "qcom,sc7180-pdc", "qcom,pdc";
3454 reg = <0 0x0b220000 0 3179 reg = <0 0x0b220000 0 0x30000>;
3455 qcom,pdc-ranges = <0 3180 qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>;
3456 #interrupt-cells = <2 3181 #interrupt-cells = <2>;
3457 interrupt-parent = <& 3182 interrupt-parent = <&intc>;
3458 interrupt-controller; 3183 interrupt-controller;
3459 }; 3184 };
3460 3185
3461 pdc_reset: reset-controller@b 3186 pdc_reset: reset-controller@b2e0000 {
3462 compatible = "qcom,sc 3187 compatible = "qcom,sc7180-pdc-global", "qcom,sdm845-pdc-global";
3463 reg = <0 0x0b2e0000 0 3188 reg = <0 0x0b2e0000 0 0x20000>;
3464 #reset-cells = <1>; 3189 #reset-cells = <1>;
3465 }; 3190 };
3466 3191
3467 tsens0: thermal-sensor@c26300 3192 tsens0: thermal-sensor@c263000 {
3468 compatible = "qcom,sc 3193 compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
3469 reg = <0 0x0c263000 0 3194 reg = <0 0x0c263000 0 0x1ff>, /* TM */
3470 <0 0x0c222000 3195 <0 0x0c222000 0 0x1ff>; /* SROT */
3471 #qcom,sensors = <15>; 3196 #qcom,sensors = <15>;
3472 interrupts = <GIC_SPI 3197 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
3473 <GIC_SPI 3198 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
3474 interrupt-names = "up 3199 interrupt-names = "uplow","critical";
3475 #thermal-sensor-cells 3200 #thermal-sensor-cells = <1>;
3476 }; 3201 };
3477 3202
3478 tsens1: thermal-sensor@c26500 3203 tsens1: thermal-sensor@c265000 {
3479 compatible = "qcom,sc 3204 compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
3480 reg = <0 0x0c265000 0 3205 reg = <0 0x0c265000 0 0x1ff>, /* TM */
3481 <0 0x0c223000 3206 <0 0x0c223000 0 0x1ff>; /* SROT */
3482 #qcom,sensors = <10>; 3207 #qcom,sensors = <10>;
3483 interrupts = <GIC_SPI 3208 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
3484 <GIC_SPI 3209 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
3485 interrupt-names = "up 3210 interrupt-names = "uplow","critical";
3486 #thermal-sensor-cells 3211 #thermal-sensor-cells = <1>;
3487 }; 3212 };
3488 3213
3489 aoss_reset: reset-controller@ 3214 aoss_reset: reset-controller@c2a0000 {
3490 compatible = "qcom,sc 3215 compatible = "qcom,sc7180-aoss-cc", "qcom,sdm845-aoss-cc";
3491 reg = <0 0x0c2a0000 0 3216 reg = <0 0x0c2a0000 0 0x31000>;
3492 #reset-cells = <1>; 3217 #reset-cells = <1>;
3493 }; 3218 };
3494 3219
3495 aoss_qmp: power-management@c3 !! 3220 aoss_qmp: power-controller@c300000 {
3496 compatible = "qcom,sc !! 3221 compatible = "qcom,sc7180-aoss-qmp";
3497 reg = <0 0x0c300000 0 3222 reg = <0 0x0c300000 0 0x400>;
3498 interrupts = <GIC_SPI 3223 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
3499 mboxes = <&apss_share 3224 mboxes = <&apss_shared 0>;
3500 3225
3501 #clock-cells = <0>; 3226 #clock-cells = <0>;
3502 }; 3227 };
3503 3228
3504 sram@c3f0000 { 3229 sram@c3f0000 {
3505 compatible = "qcom,rp 3230 compatible = "qcom,rpmh-stats";
3506 reg = <0 0x0c3f0000 0 3231 reg = <0 0x0c3f0000 0 0x400>;
3507 }; 3232 };
3508 3233
3509 spmi_bus: spmi@c440000 { 3234 spmi_bus: spmi@c440000 {
3510 compatible = "qcom,sp 3235 compatible = "qcom,spmi-pmic-arb";
3511 reg = <0 0x0c440000 0 3236 reg = <0 0x0c440000 0 0x1100>,
3512 <0 0x0c600000 0 3237 <0 0x0c600000 0 0x2000000>,
3513 <0 0x0e600000 0 3238 <0 0x0e600000 0 0x100000>,
3514 <0 0x0e700000 0 3239 <0 0x0e700000 0 0xa0000>,
3515 <0 0x0c40a000 0 3240 <0 0x0c40a000 0 0x26000>;
3516 reg-names = "core", " 3241 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3517 interrupt-names = "pe 3242 interrupt-names = "periph_irq";
3518 interrupts-extended = 3243 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3519 qcom,ee = <0>; 3244 qcom,ee = <0>;
3520 qcom,channel = <0>; 3245 qcom,channel = <0>;
3521 #address-cells = <2>; !! 3246 #address-cells = <1>;
3522 #size-cells = <0>; !! 3247 #size-cells = <1>;
3523 interrupt-controller; 3248 interrupt-controller;
3524 #interrupt-cells = <4 3249 #interrupt-cells = <4>;
>> 3250 cell-index = <0>;
3525 }; 3251 };
3526 3252
3527 sram@146aa000 { !! 3253 imem@146aa000 {
3528 compatible = "qcom,sc !! 3254 compatible = "simple-mfd";
3529 reg = <0 0x146aa000 0 3255 reg = <0 0x146aa000 0 0x2000>;
3530 3256
3531 #address-cells = <1>; 3257 #address-cells = <1>;
3532 #size-cells = <1>; 3258 #size-cells = <1>;
3533 3259
3534 ranges = <0 0 0x146aa 3260 ranges = <0 0 0x146aa000 0x2000>;
3535 3261
3536 pil-reloc@94c { 3262 pil-reloc@94c {
3537 compatible = 3263 compatible = "qcom,pil-reloc-info";
3538 reg = <0x94c 3264 reg = <0x94c 0xc8>;
3539 }; 3265 };
3540 }; 3266 };
3541 3267
3542 apps_smmu: iommu@15000000 { 3268 apps_smmu: iommu@15000000 {
3543 compatible = "qcom,sc 3269 compatible = "qcom,sc7180-smmu-500", "arm,mmu-500";
3544 reg = <0 0x15000000 0 3270 reg = <0 0x15000000 0 0x100000>;
3545 #iommu-cells = <2>; 3271 #iommu-cells = <2>;
3546 #global-interrupts = 3272 #global-interrupts = <1>;
3547 interrupts = <GIC_SPI 3273 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
3548 <GIC_SPI 3274 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
3549 <GIC_SPI 3275 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
3550 <GIC_SPI 3276 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
3551 <GIC_SPI 3277 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
3552 <GIC_SPI 3278 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
3553 <GIC_SPI 3279 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
3554 <GIC_SPI 3280 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
3555 <GIC_SPI 3281 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
3556 <GIC_SPI 3282 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
3557 <GIC_SPI 3283 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
3558 <GIC_SPI 3284 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
3559 <GIC_SPI 3285 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
3560 <GIC_SPI 3286 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
3561 <GIC_SPI 3287 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
3562 <GIC_SPI 3288 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
3563 <GIC_SPI 3289 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
3564 <GIC_SPI 3290 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
3565 <GIC_SPI 3291 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
3566 <GIC_SPI 3292 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
3567 <GIC_SPI 3293 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
3568 <GIC_SPI 3294 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
3569 <GIC_SPI 3295 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
3570 <GIC_SPI 3296 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
3571 <GIC_SPI 3297 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
3572 <GIC_SPI 3298 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
3573 <GIC_SPI 3299 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
3574 <GIC_SPI 3300 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
3575 <GIC_SPI 3301 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
3576 <GIC_SPI 3302 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
3577 <GIC_SPI 3303 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
3578 <GIC_SPI 3304 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
3579 <GIC_SPI 3305 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
3580 <GIC_SPI 3306 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
3581 <GIC_SPI 3307 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
3582 <GIC_SPI 3308 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
3583 <GIC_SPI 3309 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
3584 <GIC_SPI 3310 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
3585 <GIC_SPI 3311 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
3586 <GIC_SPI 3312 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
3587 <GIC_SPI 3313 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
3588 <GIC_SPI 3314 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
3589 <GIC_SPI 3315 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
3590 <GIC_SPI 3316 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
3591 <GIC_SPI 3317 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
3592 <GIC_SPI 3318 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
3593 <GIC_SPI 3319 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
3594 <GIC_SPI 3320 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
3595 <GIC_SPI 3321 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
3596 <GIC_SPI 3322 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
3597 <GIC_SPI 3323 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
3598 <GIC_SPI 3324 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
3599 <GIC_SPI 3325 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
3600 <GIC_SPI 3326 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
3601 <GIC_SPI 3327 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
3602 <GIC_SPI 3328 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
3603 <GIC_SPI 3329 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
3604 <GIC_SPI 3330 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
3605 <GIC_SPI 3331 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
3606 <GIC_SPI 3332 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
3607 <GIC_SPI 3333 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
3608 <GIC_SPI 3334 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
3609 <GIC_SPI 3335 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
3610 <GIC_SPI 3336 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
3611 <GIC_SPI 3337 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
3612 <GIC_SPI 3338 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
3613 <GIC_SPI 3339 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
3614 <GIC_SPI 3340 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
3615 <GIC_SPI 3341 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
3616 <GIC_SPI 3342 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
3617 <GIC_SPI 3343 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
3618 <GIC_SPI 3344 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
3619 <GIC_SPI 3345 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
3620 <GIC_SPI 3346 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
3621 <GIC_SPI 3347 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
3622 <GIC_SPI 3348 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
3623 <GIC_SPI 3349 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
3624 <GIC_SPI 3350 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
3625 <GIC_SPI 3351 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
3626 <GIC_SPI 3352 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
3627 <GIC_SPI 3353 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
3628 }; 3354 };
3629 3355
3630 intc: interrupt-controller@17 3356 intc: interrupt-controller@17a00000 {
3631 compatible = "arm,gic 3357 compatible = "arm,gic-v3";
3632 #address-cells = <2>; 3358 #address-cells = <2>;
3633 #size-cells = <2>; 3359 #size-cells = <2>;
3634 ranges; 3360 ranges;
3635 #interrupt-cells = <3 3361 #interrupt-cells = <3>;
3636 interrupt-controller; 3362 interrupt-controller;
3637 reg = <0 0x17a00000 0 3363 reg = <0 0x17a00000 0 0x10000>, /* GICD */
3638 <0 0x17a60000 0 3364 <0 0x17a60000 0 0x100000>; /* GICR * 8 */
3639 interrupts = <GIC_PPI 3365 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3640 3366
3641 msi-controller@17a400 3367 msi-controller@17a40000 {
3642 compatible = 3368 compatible = "arm,gic-v3-its";
3643 msi-controlle 3369 msi-controller;
3644 #msi-cells = 3370 #msi-cells = <1>;
3645 reg = <0 0x17 3371 reg = <0 0x17a40000 0 0x20000>;
3646 status = "dis 3372 status = "disabled";
3647 }; 3373 };
3648 }; 3374 };
3649 3375
3650 apss_shared: mailbox@17c00000 3376 apss_shared: mailbox@17c00000 {
3651 compatible = "qcom,sc !! 3377 compatible = "qcom,sc7180-apss-shared";
3652 "qcom,sd <<
3653 reg = <0 0x17c00000 0 3378 reg = <0 0x17c00000 0 0x10000>;
3654 #mbox-cells = <1>; 3379 #mbox-cells = <1>;
3655 }; 3380 };
3656 3381
3657 watchdog@17c10000 { 3382 watchdog@17c10000 {
3658 compatible = "qcom,ap 3383 compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt";
3659 reg = <0 0x17c10000 0 3384 reg = <0 0x17c10000 0 0x1000>;
3660 clocks = <&sleep_clk> 3385 clocks = <&sleep_clk>;
3661 interrupts = <GIC_SPI !! 3386 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
3662 }; 3387 };
3663 3388
3664 timer@17c20000 { !! 3389 timer@17c20000{
3665 #address-cells = <1>; !! 3390 #address-cells = <2>;
3666 #size-cells = <1>; !! 3391 #size-cells = <2>;
3667 ranges = <0 0 0 0x200 !! 3392 ranges;
3668 compatible = "arm,arm 3393 compatible = "arm,armv7-timer-mem";
3669 reg = <0 0x17c20000 0 3394 reg = <0 0x17c20000 0 0x1000>;
3670 3395
3671 frame@17c21000 { 3396 frame@17c21000 {
3672 frame-number 3397 frame-number = <0>;
3673 interrupts = 3398 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
3674 3399 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
3675 reg = <0x17c2 !! 3400 reg = <0 0x17c21000 0 0x1000>,
3676 <0x17c2 !! 3401 <0 0x17c22000 0 0x1000>;
3677 }; 3402 };
3678 3403
3679 frame@17c23000 { 3404 frame@17c23000 {
3680 frame-number 3405 frame-number = <1>;
3681 interrupts = 3406 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
3682 reg = <0x17c2 !! 3407 reg = <0 0x17c23000 0 0x1000>;
3683 status = "dis 3408 status = "disabled";
3684 }; 3409 };
3685 3410
3686 frame@17c25000 { 3411 frame@17c25000 {
3687 frame-number 3412 frame-number = <2>;
3688 interrupts = 3413 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
3689 reg = <0x17c2 !! 3414 reg = <0 0x17c25000 0 0x1000>;
3690 status = "dis 3415 status = "disabled";
3691 }; 3416 };
3692 3417
3693 frame@17c27000 { 3418 frame@17c27000 {
3694 frame-number 3419 frame-number = <3>;
3695 interrupts = 3420 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3696 reg = <0x17c2 !! 3421 reg = <0 0x17c27000 0 0x1000>;
3697 status = "dis 3422 status = "disabled";
3698 }; 3423 };
3699 3424
3700 frame@17c29000 { 3425 frame@17c29000 {
3701 frame-number 3426 frame-number = <4>;
3702 interrupts = 3427 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3703 reg = <0x17c2 !! 3428 reg = <0 0x17c29000 0 0x1000>;
3704 status = "dis 3429 status = "disabled";
3705 }; 3430 };
3706 3431
3707 frame@17c2b000 { 3432 frame@17c2b000 {
3708 frame-number 3433 frame-number = <5>;
3709 interrupts = 3434 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3710 reg = <0x17c2 !! 3435 reg = <0 0x17c2b000 0 0x1000>;
3711 status = "dis 3436 status = "disabled";
3712 }; 3437 };
3713 3438
3714 frame@17c2d000 { 3439 frame@17c2d000 {
3715 frame-number 3440 frame-number = <6>;
3716 interrupts = 3441 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
3717 reg = <0x17c2 !! 3442 reg = <0 0x17c2d000 0 0x1000>;
3718 status = "dis 3443 status = "disabled";
3719 }; 3444 };
3720 }; 3445 };
3721 3446
3722 apps_rsc: rsc@18200000 { 3447 apps_rsc: rsc@18200000 {
3723 compatible = "qcom,rp 3448 compatible = "qcom,rpmh-rsc";
3724 reg = <0 0x18200000 0 3449 reg = <0 0x18200000 0 0x10000>,
3725 <0 0x18210000 0 3450 <0 0x18210000 0 0x10000>,
3726 <0 0x18220000 0 3451 <0 0x18220000 0 0x10000>;
3727 reg-names = "drv-0", 3452 reg-names = "drv-0", "drv-1", "drv-2";
3728 interrupts = <GIC_SPI 3453 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
3729 <GIC_SPI 3454 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
3730 <GIC_SPI 3455 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
3731 qcom,tcs-offset = <0x 3456 qcom,tcs-offset = <0xd00>;
3732 qcom,drv-id = <2>; 3457 qcom,drv-id = <2>;
3733 qcom,tcs-config = <AC 3458 qcom,tcs-config = <ACTIVE_TCS 2>,
3734 <SL 3459 <SLEEP_TCS 3>,
3735 <WA 3460 <WAKE_TCS 3>,
3736 <CO 3461 <CONTROL_TCS 1>;
3737 power-domains = <&CLU <<
3738 3462
3739 rpmhcc: clock-control 3463 rpmhcc: clock-controller {
3740 compatible = 3464 compatible = "qcom,sc7180-rpmh-clk";
3741 clocks = <&xo 3465 clocks = <&xo_board>;
3742 clock-names = 3466 clock-names = "xo";
3743 #clock-cells 3467 #clock-cells = <1>;
3744 }; 3468 };
3745 3469
3746 rpmhpd: power-control 3470 rpmhpd: power-controller {
3747 compatible = 3471 compatible = "qcom,sc7180-rpmhpd";
3748 #power-domain 3472 #power-domain-cells = <1>;
3749 operating-poi 3473 operating-points-v2 = <&rpmhpd_opp_table>;
3750 3474
3751 rpmhpd_opp_ta 3475 rpmhpd_opp_table: opp-table {
3752 compa 3476 compatible = "operating-points-v2";
3753 3477
3754 rpmhp 3478 rpmhpd_opp_ret: opp1 {
3755 3479 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3756 }; 3480 };
3757 3481
3758 rpmhp 3482 rpmhpd_opp_min_svs: opp2 {
3759 3483 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3760 }; 3484 };
3761 3485
3762 rpmhp 3486 rpmhpd_opp_low_svs: opp3 {
3763 3487 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3764 }; 3488 };
3765 3489
3766 rpmhp 3490 rpmhpd_opp_svs: opp4 {
3767 3491 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3768 }; 3492 };
3769 3493
3770 rpmhp 3494 rpmhpd_opp_svs_l1: opp5 {
3771 3495 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3772 }; 3496 };
3773 3497
3774 rpmhp 3498 rpmhpd_opp_svs_l2: opp6 {
3775 3499 opp-level = <224>;
3776 }; 3500 };
3777 3501
3778 rpmhp 3502 rpmhpd_opp_nom: opp7 {
3779 3503 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3780 }; 3504 };
3781 3505
3782 rpmhp 3506 rpmhpd_opp_nom_l1: opp8 {
3783 3507 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3784 }; 3508 };
3785 3509
3786 rpmhp 3510 rpmhpd_opp_nom_l2: opp9 {
3787 3511 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3788 }; 3512 };
3789 3513
3790 rpmhp 3514 rpmhpd_opp_turbo: opp10 {
3791 3515 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3792 }; 3516 };
3793 3517
3794 rpmhp 3518 rpmhpd_opp_turbo_l1: opp11 {
3795 3519 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3796 }; 3520 };
3797 }; 3521 };
3798 }; 3522 };
3799 3523
3800 apps_bcm_voter: bcm-v !! 3524 apps_bcm_voter: bcm_voter {
3801 compatible = 3525 compatible = "qcom,bcm-voter";
3802 }; 3526 };
3803 }; 3527 };
3804 3528
3805 osm_l3: interconnect@18321000 3529 osm_l3: interconnect@18321000 {
3806 compatible = "qcom,sc !! 3530 compatible = "qcom,sc7180-osm-l3";
3807 reg = <0 0x18321000 0 3531 reg = <0 0x18321000 0 0x1400>;
3808 3532
3809 clocks = <&rpmhcc RPM 3533 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3810 clock-names = "xo", " 3534 clock-names = "xo", "alternate";
3811 3535
3812 #interconnect-cells = 3536 #interconnect-cells = <1>;
3813 }; 3537 };
3814 3538
3815 cpufreq_hw: cpufreq@18323000 3539 cpufreq_hw: cpufreq@18323000 {
3816 compatible = "qcom,sc !! 3540 compatible = "qcom,cpufreq-hw";
3817 reg = <0 0x18323000 0 3541 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>;
3818 reg-names = "freq-dom 3542 reg-names = "freq-domain0", "freq-domain1";
3819 3543
3820 clocks = <&rpmhcc RPM 3544 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3821 clock-names = "xo", " 3545 clock-names = "xo", "alternate";
3822 3546
3823 #freq-domain-cells = 3547 #freq-domain-cells = <1>;
3824 #clock-cells = <1>; <<
3825 }; 3548 };
3826 3549
3827 wifi: wifi@18800000 { 3550 wifi: wifi@18800000 {
3828 compatible = "qcom,wc 3551 compatible = "qcom,wcn3990-wifi";
3829 reg = <0 0x18800000 0 3552 reg = <0 0x18800000 0 0x800000>;
3830 reg-names = "membase" 3553 reg-names = "membase";
3831 iommus = <&apps_smmu 3554 iommus = <&apps_smmu 0xc0 0x1>;
3832 interrupts = 3555 interrupts =
3833 <GIC_SPI 414 3556 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH /* CE0 */ >,
3834 <GIC_SPI 415 3557 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH /* CE1 */ >,
3835 <GIC_SPI 416 3558 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH /* CE2 */ >,
3836 <GIC_SPI 417 3559 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH /* CE3 */ >,
3837 <GIC_SPI 418 3560 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH /* CE4 */ >,
3838 <GIC_SPI 419 3561 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH /* CE5 */ >,
3839 <GIC_SPI 420 3562 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH /* CE6 */ >,
3840 <GIC_SPI 421 3563 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH /* CE7 */ >,
3841 <GIC_SPI 422 3564 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH /* CE8 */ >,
3842 <GIC_SPI 423 3565 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH /* CE9 */ >,
3843 <GIC_SPI 424 3566 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH /* CE10 */>,
3844 <GIC_SPI 425 3567 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH /* CE11 */>;
3845 memory-region = <&wla 3568 memory-region = <&wlan_mem>;
3846 qcom,msa-fixed-perm; 3569 qcom,msa-fixed-perm;
3847 status = "disabled"; 3570 status = "disabled";
3848 }; 3571 };
3849 3572
3850 remoteproc_adsp: remoteproc@6 <<
3851 compatible = "qcom,sc <<
3852 reg = <0 0x62400000 0 <<
3853 <<
3854 interrupts-extended = <<
3855 <<
3856 <<
3857 <<
3858 <<
3859 interrupt-names = "wd <<
3860 "fa <<
3861 "re <<
3862 "ha <<
3863 "st <<
3864 <<
3865 clocks = <&rpmhcc RPM <<
3866 clock-names = "xo"; <<
3867 <<
3868 power-domains = <&rpm <<
3869 <&rpm <<
3870 power-domain-names = <<
3871 <<
3872 qcom,qmp = <&aoss_qmp <<
3873 qcom,smem-states = <& <<
3874 qcom,smem-state-names <<
3875 <<
3876 status = "disabled"; <<
3877 <<
3878 glink-edge { <<
3879 interrupts = <<
3880 label = "lpas <<
3881 qcom,remote-p <<
3882 mboxes = <&ap <<
3883 <<
3884 apr { <<
3885 compa <<
3886 qcom, <<
3887 qcom, <<
3888 #addr <<
3889 #size <<
3890 <<
3891 servi <<
3892 <<
3893 <<
3894 <<
3895 }; <<
3896 <<
3897 q6afe <<
3898 <<
3899 <<
3900 <<
3901 <<
3902 <<
3903 <<
3904 <<
3905 <<
3906 <<
3907 <<
3908 <<
3909 <<
3910 <<
3911 <<
3912 <<
3913 }; <<
3914 <<
3915 q6asm <<
3916 <<
3917 <<
3918 <<
3919 <<
3920 <<
3921 <<
3922 <<
3923 <<
3924 <<
3925 <<
3926 <<
3927 }; <<
3928 <<
3929 q6adm <<
3930 <<
3931 <<
3932 <<
3933 <<
3934 <<
3935 <<
3936 <<
3937 <<
3938 }; <<
3939 }; <<
3940 <<
3941 fastrpc { <<
3942 compa <<
3943 qcom, <<
3944 label <<
3945 #addr <<
3946 #size <<
3947 <<
3948 compu <<
3949 <<
3950 <<
3951 <<
3952 }; <<
3953 <<
3954 compu <<
3955 <<
3956 <<
3957 <<
3958 }; <<
3959 <<
3960 compu <<
3961 <<
3962 <<
3963 <<
3964 <<
3965 }; <<
3966 }; <<
3967 }; <<
3968 }; <<
3969 <<
3970 lpasscc: clock-controller@62d 3573 lpasscc: clock-controller@62d00000 {
3971 compatible = "qcom,sc 3574 compatible = "qcom,sc7180-lpasscorecc";
3972 reg = <0 0x62d00000 0 3575 reg = <0 0x62d00000 0 0x50000>,
3973 <0 0x62780000 0 3576 <0 0x62780000 0 0x30000>;
3974 reg-names = "lpass_co 3577 reg-names = "lpass_core_cc", "lpass_audio_cc";
3975 clocks = <&gcc GCC_LP 3578 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>,
3976 <&rpmhcc RPM 3579 <&rpmhcc RPMH_CXO_CLK>;
3977 clock-names = "iface" 3580 clock-names = "iface", "bi_tcxo";
3978 power-domains = <&lpa 3581 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>;
3979 #clock-cells = <1>; 3582 #clock-cells = <1>;
3980 #power-domain-cells = 3583 #power-domain-cells = <1>;
3981 <<
3982 status = "reserved"; <<
3983 }; 3584 };
3984 3585
3985 lpass_cpu: lpass@62d87000 { 3586 lpass_cpu: lpass@62d87000 {
3986 compatible = "qcom,sc 3587 compatible = "qcom,sc7180-lpass-cpu";
3987 3588
3988 reg = <0 0x62d87000 0 3589 reg = <0 0x62d87000 0 0x68000>, <0 0x62f00000 0 0x29000>;
3989 reg-names = "lpass-hd !! 3590 reg-names = "lpass-hdmiif", "lpass-lpaif";
3990 3591
3991 iommus = <&apps_smmu 3592 iommus = <&apps_smmu 0x1020 0>,
3992 <&apps_smmu 0 3593 <&apps_smmu 0x1021 0>,
3993 <&apps_smmu 0 3594 <&apps_smmu 0x1032 0>;
3994 3595
3995 power-domains = <&lpa 3596 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>;
3996 required-opps = <&rpm <<
3997 3597
3998 status = "disabled"; 3598 status = "disabled";
3999 3599
4000 clocks = <&gcc GCC_LP 3600 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>,
4001 <&lpasscc LP 3601 <&lpasscc LPASS_AUDIO_CORE_CORE_CLK>,
4002 <&lpasscc LP 3602 <&lpasscc LPASS_AUDIO_CORE_EXT_MCLK0_CLK>,
4003 <&lpasscc LP 3603 <&lpasscc LPASS_AUDIO_CORE_SYSNOC_MPORT_CORE_CLK>,
4004 <&lpasscc LP 3604 <&lpasscc LPASS_AUDIO_CORE_LPAIF_PRI_IBIT_CLK>,
4005 <&lpasscc LP 3605 <&lpasscc LPASS_AUDIO_CORE_LPAIF_SEC_IBIT_CLK>;
4006 3606
4007 clock-names = "pcnoc- 3607 clock-names = "pcnoc-sway-clk", "audio-core",
4008 "mclk 3608 "mclk0", "pcnoc-mport-clk",
4009 "mi2s 3609 "mi2s-bit-clk0", "mi2s-bit-clk1";
4010 3610
4011 3611
4012 #sound-dai-cells = <1 3612 #sound-dai-cells = <1>;
4013 #address-cells = <1>; 3613 #address-cells = <1>;
4014 #size-cells = <0>; 3614 #size-cells = <0>;
4015 3615
4016 interrupts = <GIC_SPI 3616 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
4017 <GIC_ 3617 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
4018 interrupt-names = "lp 3618 interrupt-names = "lpass-irq-lpaif", "lpass-irq-hdmi";
4019 }; 3619 };
4020 3620
4021 lpass_hm: clock-controller@63 3621 lpass_hm: clock-controller@63000000 {
4022 compatible = "qcom,sc 3622 compatible = "qcom,sc7180-lpasshm";
4023 reg = <0 0x63000000 0 3623 reg = <0 0x63000000 0 0x28>;
4024 clocks = <&gcc GCC_LP 3624 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>,
4025 <&rpmhcc RPM 3625 <&rpmhcc RPMH_CXO_CLK>;
4026 clock-names = "iface" 3626 clock-names = "iface", "bi_tcxo";
4027 power-domains = <&rpm <<
4028 <<
4029 #clock-cells = <1>; 3627 #clock-cells = <1>;
4030 #power-domain-cells = 3628 #power-domain-cells = <1>;
4031 <<
4032 status = "reserved"; <<
4033 }; 3629 };
4034 }; 3630 };
4035 3631
4036 thermal-zones { 3632 thermal-zones {
4037 cpu0_thermal: cpu0-thermal { 3633 cpu0_thermal: cpu0-thermal {
4038 polling-delay-passive 3634 polling-delay-passive = <250>;
>> 3635 polling-delay = <0>;
4039 3636
4040 thermal-sensors = <&t 3637 thermal-sensors = <&tsens0 1>;
4041 sustainable-power = < 3638 sustainable-power = <1052>;
4042 3639
4043 trips { 3640 trips {
4044 cpu0_alert0: 3641 cpu0_alert0: trip-point0 {
4045 tempe 3642 temperature = <90000>;
4046 hyste 3643 hysteresis = <2000>;
4047 type 3644 type = "passive";
4048 }; 3645 };
4049 3646
4050 cpu0_alert1: 3647 cpu0_alert1: trip-point1 {
4051 tempe 3648 temperature = <95000>;
4052 hyste 3649 hysteresis = <2000>;
4053 type 3650 type = "passive";
4054 }; 3651 };
4055 3652
4056 cpu0_crit: cp !! 3653 cpu0_crit: cpu_crit {
4057 tempe 3654 temperature = <110000>;
4058 hyste 3655 hysteresis = <1000>;
4059 type 3656 type = "critical";
4060 }; 3657 };
4061 }; 3658 };
4062 3659
4063 cooling-maps { 3660 cooling-maps {
4064 map0 { 3661 map0 {
4065 trip 3662 trip = <&cpu0_alert0>;
4066 cooli 3663 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4067 3664 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4068 3665 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4069 3666 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4070 3667 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4071 3668 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4072 }; 3669 };
4073 map1 { 3670 map1 {
4074 trip 3671 trip = <&cpu0_alert1>;
4075 cooli 3672 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4076 3673 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4077 3674 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4078 3675 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4079 3676 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4080 3677 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4081 }; 3678 };
4082 }; 3679 };
4083 }; 3680 };
4084 3681
4085 cpu1_thermal: cpu1-thermal { 3682 cpu1_thermal: cpu1-thermal {
4086 polling-delay-passive 3683 polling-delay-passive = <250>;
>> 3684 polling-delay = <0>;
4087 3685
4088 thermal-sensors = <&t 3686 thermal-sensors = <&tsens0 2>;
4089 sustainable-power = < 3687 sustainable-power = <1052>;
4090 3688
4091 trips { 3689 trips {
4092 cpu1_alert0: 3690 cpu1_alert0: trip-point0 {
4093 tempe 3691 temperature = <90000>;
4094 hyste 3692 hysteresis = <2000>;
4095 type 3693 type = "passive";
4096 }; 3694 };
4097 3695
4098 cpu1_alert1: 3696 cpu1_alert1: trip-point1 {
4099 tempe 3697 temperature = <95000>;
4100 hyste 3698 hysteresis = <2000>;
4101 type 3699 type = "passive";
4102 }; 3700 };
4103 3701
4104 cpu1_crit: cp !! 3702 cpu1_crit: cpu_crit {
4105 tempe 3703 temperature = <110000>;
4106 hyste 3704 hysteresis = <1000>;
4107 type 3705 type = "critical";
4108 }; 3706 };
4109 }; 3707 };
4110 3708
4111 cooling-maps { 3709 cooling-maps {
4112 map0 { 3710 map0 {
4113 trip 3711 trip = <&cpu1_alert0>;
4114 cooli 3712 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4115 3713 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4116 3714 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4117 3715 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4118 3716 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4119 3717 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4120 }; 3718 };
4121 map1 { 3719 map1 {
4122 trip 3720 trip = <&cpu1_alert1>;
4123 cooli 3721 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4124 3722 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4125 3723 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4126 3724 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4127 3725 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4128 3726 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4129 }; 3727 };
4130 }; 3728 };
4131 }; 3729 };
4132 3730
4133 cpu2_thermal: cpu2-thermal { 3731 cpu2_thermal: cpu2-thermal {
4134 polling-delay-passive 3732 polling-delay-passive = <250>;
>> 3733 polling-delay = <0>;
4135 3734
4136 thermal-sensors = <&t 3735 thermal-sensors = <&tsens0 3>;
4137 sustainable-power = < 3736 sustainable-power = <1052>;
4138 3737
4139 trips { 3738 trips {
4140 cpu2_alert0: 3739 cpu2_alert0: trip-point0 {
4141 tempe 3740 temperature = <90000>;
4142 hyste 3741 hysteresis = <2000>;
4143 type 3742 type = "passive";
4144 }; 3743 };
4145 3744
4146 cpu2_alert1: 3745 cpu2_alert1: trip-point1 {
4147 tempe 3746 temperature = <95000>;
4148 hyste 3747 hysteresis = <2000>;
4149 type 3748 type = "passive";
4150 }; 3749 };
4151 3750
4152 cpu2_crit: cp !! 3751 cpu2_crit: cpu_crit {
4153 tempe 3752 temperature = <110000>;
4154 hyste 3753 hysteresis = <1000>;
4155 type 3754 type = "critical";
4156 }; 3755 };
4157 }; 3756 };
4158 3757
4159 cooling-maps { 3758 cooling-maps {
4160 map0 { 3759 map0 {
4161 trip 3760 trip = <&cpu2_alert0>;
4162 cooli 3761 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4163 3762 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4164 3763 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4165 3764 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4166 3765 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4167 3766 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4168 }; 3767 };
4169 map1 { 3768 map1 {
4170 trip 3769 trip = <&cpu2_alert1>;
4171 cooli 3770 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4172 3771 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4173 3772 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4174 3773 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4175 3774 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4176 3775 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4177 }; 3776 };
4178 }; 3777 };
4179 }; 3778 };
4180 3779
4181 cpu3_thermal: cpu3-thermal { 3780 cpu3_thermal: cpu3-thermal {
4182 polling-delay-passive 3781 polling-delay-passive = <250>;
>> 3782 polling-delay = <0>;
4183 3783
4184 thermal-sensors = <&t 3784 thermal-sensors = <&tsens0 4>;
4185 sustainable-power = < 3785 sustainable-power = <1052>;
4186 3786
4187 trips { 3787 trips {
4188 cpu3_alert0: 3788 cpu3_alert0: trip-point0 {
4189 tempe 3789 temperature = <90000>;
4190 hyste 3790 hysteresis = <2000>;
4191 type 3791 type = "passive";
4192 }; 3792 };
4193 3793
4194 cpu3_alert1: 3794 cpu3_alert1: trip-point1 {
4195 tempe 3795 temperature = <95000>;
4196 hyste 3796 hysteresis = <2000>;
4197 type 3797 type = "passive";
4198 }; 3798 };
4199 3799
4200 cpu3_crit: cp !! 3800 cpu3_crit: cpu_crit {
4201 tempe 3801 temperature = <110000>;
4202 hyste 3802 hysteresis = <1000>;
4203 type 3803 type = "critical";
4204 }; 3804 };
4205 }; 3805 };
4206 3806
4207 cooling-maps { 3807 cooling-maps {
4208 map0 { 3808 map0 {
4209 trip 3809 trip = <&cpu3_alert0>;
4210 cooli 3810 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4211 3811 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4212 3812 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4213 3813 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4214 3814 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4215 3815 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4216 }; 3816 };
4217 map1 { 3817 map1 {
4218 trip 3818 trip = <&cpu3_alert1>;
4219 cooli 3819 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4220 3820 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4221 3821 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4222 3822 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4223 3823 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4224 3824 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4225 }; 3825 };
4226 }; 3826 };
4227 }; 3827 };
4228 3828
4229 cpu4_thermal: cpu4-thermal { 3829 cpu4_thermal: cpu4-thermal {
4230 polling-delay-passive 3830 polling-delay-passive = <250>;
>> 3831 polling-delay = <0>;
4231 3832
4232 thermal-sensors = <&t 3833 thermal-sensors = <&tsens0 5>;
4233 sustainable-power = < 3834 sustainable-power = <1052>;
4234 3835
4235 trips { 3836 trips {
4236 cpu4_alert0: 3837 cpu4_alert0: trip-point0 {
4237 tempe 3838 temperature = <90000>;
4238 hyste 3839 hysteresis = <2000>;
4239 type 3840 type = "passive";
4240 }; 3841 };
4241 3842
4242 cpu4_alert1: 3843 cpu4_alert1: trip-point1 {
4243 tempe 3844 temperature = <95000>;
4244 hyste 3845 hysteresis = <2000>;
4245 type 3846 type = "passive";
4246 }; 3847 };
4247 3848
4248 cpu4_crit: cp !! 3849 cpu4_crit: cpu_crit {
4249 tempe 3850 temperature = <110000>;
4250 hyste 3851 hysteresis = <1000>;
4251 type 3852 type = "critical";
4252 }; 3853 };
4253 }; 3854 };
4254 3855
4255 cooling-maps { 3856 cooling-maps {
4256 map0 { 3857 map0 {
4257 trip 3858 trip = <&cpu4_alert0>;
4258 cooli 3859 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4259 3860 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4260 3861 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4261 3862 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4262 3863 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4263 3864 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4264 }; 3865 };
4265 map1 { 3866 map1 {
4266 trip 3867 trip = <&cpu4_alert1>;
4267 cooli 3868 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4268 3869 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4269 3870 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4270 3871 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4271 3872 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4272 3873 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4273 }; 3874 };
4274 }; 3875 };
4275 }; 3876 };
4276 3877
4277 cpu5_thermal: cpu5-thermal { 3878 cpu5_thermal: cpu5-thermal {
4278 polling-delay-passive 3879 polling-delay-passive = <250>;
>> 3880 polling-delay = <0>;
4279 3881
4280 thermal-sensors = <&t 3882 thermal-sensors = <&tsens0 6>;
4281 sustainable-power = < 3883 sustainable-power = <1052>;
4282 3884
4283 trips { 3885 trips {
4284 cpu5_alert0: 3886 cpu5_alert0: trip-point0 {
4285 tempe 3887 temperature = <90000>;
4286 hyste 3888 hysteresis = <2000>;
4287 type 3889 type = "passive";
4288 }; 3890 };
4289 3891
4290 cpu5_alert1: 3892 cpu5_alert1: trip-point1 {
4291 tempe 3893 temperature = <95000>;
4292 hyste 3894 hysteresis = <2000>;
4293 type 3895 type = "passive";
4294 }; 3896 };
4295 3897
4296 cpu5_crit: cp !! 3898 cpu5_crit: cpu_crit {
4297 tempe 3899 temperature = <110000>;
4298 hyste 3900 hysteresis = <1000>;
4299 type 3901 type = "critical";
4300 }; 3902 };
4301 }; 3903 };
4302 3904
4303 cooling-maps { 3905 cooling-maps {
4304 map0 { 3906 map0 {
4305 trip 3907 trip = <&cpu5_alert0>;
4306 cooli 3908 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4307 3909 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4308 3910 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4309 3911 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4310 3912 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4311 3913 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4312 }; 3914 };
4313 map1 { 3915 map1 {
4314 trip 3916 trip = <&cpu5_alert1>;
4315 cooli 3917 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4316 3918 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4317 3919 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4318 3920 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4319 3921 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4320 3922 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4321 }; 3923 };
4322 }; 3924 };
4323 }; 3925 };
4324 3926
4325 cpu6_thermal: cpu6-thermal { 3927 cpu6_thermal: cpu6-thermal {
4326 polling-delay-passive 3928 polling-delay-passive = <250>;
>> 3929 polling-delay = <0>;
4327 3930
4328 thermal-sensors = <&t 3931 thermal-sensors = <&tsens0 9>;
4329 sustainable-power = < 3932 sustainable-power = <1425>;
4330 3933
4331 trips { 3934 trips {
4332 cpu6_alert0: 3935 cpu6_alert0: trip-point0 {
4333 tempe 3936 temperature = <90000>;
4334 hyste 3937 hysteresis = <2000>;
4335 type 3938 type = "passive";
4336 }; 3939 };
4337 3940
4338 cpu6_alert1: 3941 cpu6_alert1: trip-point1 {
4339 tempe 3942 temperature = <95000>;
4340 hyste 3943 hysteresis = <2000>;
4341 type 3944 type = "passive";
4342 }; 3945 };
4343 3946
4344 cpu6_crit: cp !! 3947 cpu6_crit: cpu_crit {
4345 tempe 3948 temperature = <110000>;
4346 hyste 3949 hysteresis = <1000>;
4347 type 3950 type = "critical";
4348 }; 3951 };
4349 }; 3952 };
4350 3953
4351 cooling-maps { 3954 cooling-maps {
4352 map0 { 3955 map0 {
4353 trip 3956 trip = <&cpu6_alert0>;
4354 cooli 3957 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4355 3958 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4356 }; 3959 };
4357 map1 { 3960 map1 {
4358 trip 3961 trip = <&cpu6_alert1>;
4359 cooli 3962 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4360 3963 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4361 }; 3964 };
4362 }; 3965 };
4363 }; 3966 };
4364 3967
4365 cpu7_thermal: cpu7-thermal { 3968 cpu7_thermal: cpu7-thermal {
4366 polling-delay-passive 3969 polling-delay-passive = <250>;
>> 3970 polling-delay = <0>;
4367 3971
4368 thermal-sensors = <&t 3972 thermal-sensors = <&tsens0 10>;
4369 sustainable-power = < 3973 sustainable-power = <1425>;
4370 3974
4371 trips { 3975 trips {
4372 cpu7_alert0: 3976 cpu7_alert0: trip-point0 {
4373 tempe 3977 temperature = <90000>;
4374 hyste 3978 hysteresis = <2000>;
4375 type 3979 type = "passive";
4376 }; 3980 };
4377 3981
4378 cpu7_alert1: 3982 cpu7_alert1: trip-point1 {
4379 tempe 3983 temperature = <95000>;
4380 hyste 3984 hysteresis = <2000>;
4381 type 3985 type = "passive";
4382 }; 3986 };
4383 3987
4384 cpu7_crit: cp !! 3988 cpu7_crit: cpu_crit {
4385 tempe 3989 temperature = <110000>;
4386 hyste 3990 hysteresis = <1000>;
4387 type 3991 type = "critical";
4388 }; 3992 };
4389 }; 3993 };
4390 3994
4391 cooling-maps { 3995 cooling-maps {
4392 map0 { 3996 map0 {
4393 trip 3997 trip = <&cpu7_alert0>;
4394 cooli 3998 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4395 3999 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4396 }; 4000 };
4397 map1 { 4001 map1 {
4398 trip 4002 trip = <&cpu7_alert1>;
4399 cooli 4003 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4400 4004 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4401 }; 4005 };
4402 }; 4006 };
4403 }; 4007 };
4404 4008
4405 cpu8_thermal: cpu8-thermal { 4009 cpu8_thermal: cpu8-thermal {
4406 polling-delay-passive 4010 polling-delay-passive = <250>;
>> 4011 polling-delay = <0>;
4407 4012
4408 thermal-sensors = <&t 4013 thermal-sensors = <&tsens0 11>;
4409 sustainable-power = < 4014 sustainable-power = <1425>;
4410 4015
4411 trips { 4016 trips {
4412 cpu8_alert0: 4017 cpu8_alert0: trip-point0 {
4413 tempe 4018 temperature = <90000>;
4414 hyste 4019 hysteresis = <2000>;
4415 type 4020 type = "passive";
4416 }; 4021 };
4417 4022
4418 cpu8_alert1: 4023 cpu8_alert1: trip-point1 {
4419 tempe 4024 temperature = <95000>;
4420 hyste 4025 hysteresis = <2000>;
4421 type 4026 type = "passive";
4422 }; 4027 };
4423 4028
4424 cpu8_crit: cp !! 4029 cpu8_crit: cpu_crit {
4425 tempe 4030 temperature = <110000>;
4426 hyste 4031 hysteresis = <1000>;
4427 type 4032 type = "critical";
4428 }; 4033 };
4429 }; 4034 };
4430 4035
4431 cooling-maps { 4036 cooling-maps {
4432 map0 { 4037 map0 {
4433 trip 4038 trip = <&cpu8_alert0>;
4434 cooli 4039 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4435 4040 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4436 }; 4041 };
4437 map1 { 4042 map1 {
4438 trip 4043 trip = <&cpu8_alert1>;
4439 cooli 4044 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4440 4045 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4441 }; 4046 };
4442 }; 4047 };
4443 }; 4048 };
4444 4049
4445 cpu9_thermal: cpu9-thermal { 4050 cpu9_thermal: cpu9-thermal {
4446 polling-delay-passive 4051 polling-delay-passive = <250>;
>> 4052 polling-delay = <0>;
4447 4053
4448 thermal-sensors = <&t 4054 thermal-sensors = <&tsens0 12>;
4449 sustainable-power = < 4055 sustainable-power = <1425>;
4450 4056
4451 trips { 4057 trips {
4452 cpu9_alert0: 4058 cpu9_alert0: trip-point0 {
4453 tempe 4059 temperature = <90000>;
4454 hyste 4060 hysteresis = <2000>;
4455 type 4061 type = "passive";
4456 }; 4062 };
4457 4063
4458 cpu9_alert1: 4064 cpu9_alert1: trip-point1 {
4459 tempe 4065 temperature = <95000>;
4460 hyste 4066 hysteresis = <2000>;
4461 type 4067 type = "passive";
4462 }; 4068 };
4463 4069
4464 cpu9_crit: cp !! 4070 cpu9_crit: cpu_crit {
4465 tempe 4071 temperature = <110000>;
4466 hyste 4072 hysteresis = <1000>;
4467 type 4073 type = "critical";
4468 }; 4074 };
4469 }; 4075 };
4470 4076
4471 cooling-maps { 4077 cooling-maps {
4472 map0 { 4078 map0 {
4473 trip 4079 trip = <&cpu9_alert0>;
4474 cooli 4080 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4475 4081 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4476 }; 4082 };
4477 map1 { 4083 map1 {
4478 trip 4084 trip = <&cpu9_alert1>;
4479 cooli 4085 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4480 4086 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4481 }; 4087 };
4482 }; 4088 };
4483 }; 4089 };
4484 4090
4485 aoss0-thermal { 4091 aoss0-thermal {
4486 polling-delay-passive 4092 polling-delay-passive = <250>;
>> 4093 polling-delay = <0>;
4487 4094
4488 thermal-sensors = <&t 4095 thermal-sensors = <&tsens0 0>;
4489 4096
4490 trips { 4097 trips {
4491 aoss0_alert0: 4098 aoss0_alert0: trip-point0 {
4492 tempe 4099 temperature = <90000>;
4493 hyste 4100 hysteresis = <2000>;
4494 type 4101 type = "hot";
4495 }; 4102 };
4496 4103
4497 aoss0_crit: a !! 4104 aoss0_crit: aoss0_crit {
4498 tempe 4105 temperature = <110000>;
4499 hyste 4106 hysteresis = <2000>;
4500 type 4107 type = "critical";
4501 }; 4108 };
4502 }; 4109 };
4503 }; 4110 };
4504 4111
4505 cpuss0-thermal { 4112 cpuss0-thermal {
4506 polling-delay-passive 4113 polling-delay-passive = <250>;
>> 4114 polling-delay = <0>;
4507 4115
4508 thermal-sensors = <&t 4116 thermal-sensors = <&tsens0 7>;
4509 4117
4510 trips { 4118 trips {
4511 cpuss0_alert0 4119 cpuss0_alert0: trip-point0 {
4512 tempe 4120 temperature = <90000>;
4513 hyste 4121 hysteresis = <2000>;
4514 type 4122 type = "hot";
4515 }; 4123 };
4516 cpuss0_crit: !! 4124 cpuss0_crit: cluster0_crit {
4517 tempe 4125 temperature = <110000>;
4518 hyste 4126 hysteresis = <2000>;
4519 type 4127 type = "critical";
4520 }; 4128 };
4521 }; 4129 };
4522 }; 4130 };
4523 4131
4524 cpuss1-thermal { 4132 cpuss1-thermal {
4525 polling-delay-passive 4133 polling-delay-passive = <250>;
>> 4134 polling-delay = <0>;
4526 4135
4527 thermal-sensors = <&t 4136 thermal-sensors = <&tsens0 8>;
4528 4137
4529 trips { 4138 trips {
4530 cpuss1_alert0 4139 cpuss1_alert0: trip-point0 {
4531 tempe 4140 temperature = <90000>;
4532 hyste 4141 hysteresis = <2000>;
4533 type 4142 type = "hot";
4534 }; 4143 };
4535 cpuss1_crit: !! 4144 cpuss1_crit: cluster0_crit {
4536 tempe 4145 temperature = <110000>;
4537 hyste 4146 hysteresis = <2000>;
4538 type 4147 type = "critical";
4539 }; 4148 };
4540 }; 4149 };
4541 }; 4150 };
4542 4151
4543 gpuss0-thermal { 4152 gpuss0-thermal {
4544 polling-delay-passive 4153 polling-delay-passive = <250>;
>> 4154 polling-delay = <0>;
4545 4155
4546 thermal-sensors = <&t 4156 thermal-sensors = <&tsens0 13>;
4547 4157
4548 trips { 4158 trips {
4549 gpuss0_alert0 4159 gpuss0_alert0: trip-point0 {
4550 tempe 4160 temperature = <95000>;
4551 hyste 4161 hysteresis = <2000>;
4552 type 4162 type = "passive";
4553 }; 4163 };
4554 4164
4555 gpuss0_crit: !! 4165 gpuss0_crit: gpuss0_crit {
4556 tempe 4166 temperature = <110000>;
4557 hyste 4167 hysteresis = <2000>;
4558 type 4168 type = "critical";
4559 }; 4169 };
4560 }; 4170 };
4561 4171
4562 cooling-maps { 4172 cooling-maps {
4563 map0 { 4173 map0 {
4564 trip 4174 trip = <&gpuss0_alert0>;
4565 cooli 4175 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4566 }; 4176 };
4567 }; 4177 };
4568 }; 4178 };
4569 4179
4570 gpuss1-thermal { 4180 gpuss1-thermal {
4571 polling-delay-passive 4181 polling-delay-passive = <250>;
>> 4182 polling-delay = <0>;
4572 4183
4573 thermal-sensors = <&t 4184 thermal-sensors = <&tsens0 14>;
4574 4185
4575 trips { 4186 trips {
4576 gpuss1_alert0 4187 gpuss1_alert0: trip-point0 {
4577 tempe 4188 temperature = <95000>;
4578 hyste 4189 hysteresis = <2000>;
4579 type 4190 type = "passive";
4580 }; 4191 };
4581 4192
4582 gpuss1_crit: !! 4193 gpuss1_crit: gpuss1_crit {
4583 tempe 4194 temperature = <110000>;
4584 hyste 4195 hysteresis = <2000>;
4585 type 4196 type = "critical";
4586 }; 4197 };
4587 }; 4198 };
4588 4199
4589 cooling-maps { 4200 cooling-maps {
4590 map0 { 4201 map0 {
4591 trip 4202 trip = <&gpuss1_alert0>;
4592 cooli 4203 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4593 }; 4204 };
4594 }; 4205 };
4595 }; 4206 };
4596 4207
4597 aoss1-thermal { 4208 aoss1-thermal {
4598 polling-delay-passive 4209 polling-delay-passive = <250>;
>> 4210 polling-delay = <0>;
4599 4211
4600 thermal-sensors = <&t 4212 thermal-sensors = <&tsens1 0>;
4601 4213
4602 trips { 4214 trips {
4603 aoss1_alert0: 4215 aoss1_alert0: trip-point0 {
4604 tempe 4216 temperature = <90000>;
4605 hyste 4217 hysteresis = <2000>;
4606 type 4218 type = "hot";
4607 }; 4219 };
4608 4220
4609 aoss1_crit: a !! 4221 aoss1_crit: aoss1_crit {
4610 tempe 4222 temperature = <110000>;
4611 hyste 4223 hysteresis = <2000>;
4612 type 4224 type = "critical";
4613 }; 4225 };
4614 }; 4226 };
4615 }; 4227 };
4616 4228
4617 cwlan-thermal { 4229 cwlan-thermal {
4618 polling-delay-passive 4230 polling-delay-passive = <250>;
>> 4231 polling-delay = <0>;
4619 4232
4620 thermal-sensors = <&t 4233 thermal-sensors = <&tsens1 1>;
4621 4234
4622 trips { 4235 trips {
4623 cwlan_alert0: 4236 cwlan_alert0: trip-point0 {
4624 tempe 4237 temperature = <90000>;
4625 hyste 4238 hysteresis = <2000>;
4626 type 4239 type = "hot";
4627 }; 4240 };
4628 4241
4629 cwlan_crit: c !! 4242 cwlan_crit: cwlan_crit {
4630 tempe 4243 temperature = <110000>;
4631 hyste 4244 hysteresis = <2000>;
4632 type 4245 type = "critical";
4633 }; 4246 };
4634 }; 4247 };
4635 }; 4248 };
4636 4249
4637 audio-thermal { 4250 audio-thermal {
4638 polling-delay-passive 4251 polling-delay-passive = <250>;
>> 4252 polling-delay = <0>;
4639 4253
4640 thermal-sensors = <&t 4254 thermal-sensors = <&tsens1 2>;
4641 4255
4642 trips { 4256 trips {
4643 audio_alert0: 4257 audio_alert0: trip-point0 {
4644 tempe 4258 temperature = <90000>;
4645 hyste 4259 hysteresis = <2000>;
4646 type 4260 type = "hot";
4647 }; 4261 };
4648 4262
4649 audio_crit: a !! 4263 audio_crit: audio_crit {
4650 tempe 4264 temperature = <110000>;
4651 hyste 4265 hysteresis = <2000>;
4652 type 4266 type = "critical";
4653 }; 4267 };
4654 }; 4268 };
4655 }; 4269 };
4656 4270
4657 ddr-thermal { 4271 ddr-thermal {
4658 polling-delay-passive 4272 polling-delay-passive = <250>;
>> 4273 polling-delay = <0>;
4659 4274
4660 thermal-sensors = <&t 4275 thermal-sensors = <&tsens1 3>;
4661 4276
4662 trips { 4277 trips {
4663 ddr_alert0: t 4278 ddr_alert0: trip-point0 {
4664 tempe 4279 temperature = <90000>;
4665 hyste 4280 hysteresis = <2000>;
4666 type 4281 type = "hot";
4667 }; 4282 };
4668 4283
4669 ddr_crit: ddr !! 4284 ddr_crit: ddr_crit {
4670 tempe 4285 temperature = <110000>;
4671 hyste 4286 hysteresis = <2000>;
4672 type 4287 type = "critical";
4673 }; 4288 };
4674 }; 4289 };
4675 }; 4290 };
4676 4291
4677 q6-hvx-thermal { 4292 q6-hvx-thermal {
4678 polling-delay-passive 4293 polling-delay-passive = <250>;
>> 4294 polling-delay = <0>;
4679 4295
4680 thermal-sensors = <&t 4296 thermal-sensors = <&tsens1 4>;
4681 4297
4682 trips { 4298 trips {
4683 q6_hvx_alert0 4299 q6_hvx_alert0: trip-point0 {
4684 tempe 4300 temperature = <90000>;
4685 hyste 4301 hysteresis = <2000>;
4686 type 4302 type = "hot";
4687 }; 4303 };
4688 4304
4689 q6_hvx_crit: !! 4305 q6_hvx_crit: q6_hvx_crit {
4690 tempe 4306 temperature = <110000>;
4691 hyste 4307 hysteresis = <2000>;
4692 type 4308 type = "critical";
4693 }; 4309 };
4694 }; 4310 };
4695 }; 4311 };
4696 4312
4697 camera-thermal { 4313 camera-thermal {
4698 polling-delay-passive 4314 polling-delay-passive = <250>;
>> 4315 polling-delay = <0>;
4699 4316
4700 thermal-sensors = <&t 4317 thermal-sensors = <&tsens1 5>;
4701 4318
4702 trips { 4319 trips {
4703 camera_alert0 4320 camera_alert0: trip-point0 {
4704 tempe 4321 temperature = <90000>;
4705 hyste 4322 hysteresis = <2000>;
4706 type 4323 type = "hot";
4707 }; 4324 };
4708 4325
4709 camera_crit: !! 4326 camera_crit: camera_crit {
4710 tempe 4327 temperature = <110000>;
4711 hyste 4328 hysteresis = <2000>;
4712 type 4329 type = "critical";
4713 }; 4330 };
4714 }; 4331 };
4715 }; 4332 };
4716 4333
4717 mdm-core-thermal { 4334 mdm-core-thermal {
4718 polling-delay-passive 4335 polling-delay-passive = <250>;
>> 4336 polling-delay = <0>;
4719 4337
4720 thermal-sensors = <&t 4338 thermal-sensors = <&tsens1 6>;
4721 4339
4722 trips { 4340 trips {
4723 mdm_alert0: t 4341 mdm_alert0: trip-point0 {
4724 tempe 4342 temperature = <90000>;
4725 hyste 4343 hysteresis = <2000>;
4726 type 4344 type = "hot";
4727 }; 4345 };
4728 4346
4729 mdm_crit: mdm !! 4347 mdm_crit: mdm_crit {
4730 tempe 4348 temperature = <110000>;
4731 hyste 4349 hysteresis = <2000>;
4732 type 4350 type = "critical";
4733 }; 4351 };
4734 }; 4352 };
4735 }; 4353 };
4736 4354
4737 mdm-dsp-thermal { 4355 mdm-dsp-thermal {
4738 polling-delay-passive 4356 polling-delay-passive = <250>;
>> 4357 polling-delay = <0>;
4739 4358
4740 thermal-sensors = <&t 4359 thermal-sensors = <&tsens1 7>;
4741 4360
4742 trips { 4361 trips {
4743 mdm_dsp_alert 4362 mdm_dsp_alert0: trip-point0 {
4744 tempe 4363 temperature = <90000>;
4745 hyste 4364 hysteresis = <2000>;
4746 type 4365 type = "hot";
4747 }; 4366 };
4748 4367
4749 mdm_dsp_crit: !! 4368 mdm_dsp_crit: mdm_dsp_crit {
4750 tempe 4369 temperature = <110000>;
4751 hyste 4370 hysteresis = <2000>;
4752 type 4371 type = "critical";
4753 }; 4372 };
4754 }; 4373 };
4755 }; 4374 };
4756 4375
4757 npu-thermal { 4376 npu-thermal {
4758 polling-delay-passive 4377 polling-delay-passive = <250>;
>> 4378 polling-delay = <0>;
4759 4379
4760 thermal-sensors = <&t 4380 thermal-sensors = <&tsens1 8>;
4761 4381
4762 trips { 4382 trips {
4763 npu_alert0: t 4383 npu_alert0: trip-point0 {
4764 tempe 4384 temperature = <90000>;
4765 hyste 4385 hysteresis = <2000>;
4766 type 4386 type = "hot";
4767 }; 4387 };
4768 4388
4769 npu_crit: npu !! 4389 npu_crit: npu_crit {
4770 tempe 4390 temperature = <110000>;
4771 hyste 4391 hysteresis = <2000>;
4772 type 4392 type = "critical";
4773 }; 4393 };
4774 }; 4394 };
4775 }; 4395 };
4776 4396
4777 video-thermal { 4397 video-thermal {
4778 polling-delay-passive 4398 polling-delay-passive = <250>;
>> 4399 polling-delay = <0>;
4779 4400
4780 thermal-sensors = <&t 4401 thermal-sensors = <&tsens1 9>;
4781 4402
4782 trips { 4403 trips {
4783 video_alert0: 4404 video_alert0: trip-point0 {
4784 tempe 4405 temperature = <90000>;
4785 hyste 4406 hysteresis = <2000>;
4786 type 4407 type = "hot";
4787 }; 4408 };
4788 4409
4789 video_crit: v !! 4410 video_crit: video_crit {
4790 tempe 4411 temperature = <110000>;
4791 hyste 4412 hysteresis = <2000>;
4792 type 4413 type = "critical";
4793 }; 4414 };
4794 }; 4415 };
4795 }; 4416 };
4796 }; 4417 };
4797 4418
4798 timer { 4419 timer {
4799 compatible = "arm,armv8-timer 4420 compatible = "arm,armv8-timer";
4800 interrupts = <GIC_PPI 1 IRQ_T 4421 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
4801 <GIC_PPI 2 IRQ_T 4422 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
4802 <GIC_PPI 3 IRQ_T 4423 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
4803 <GIC_PPI 0 IRQ_T 4424 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
4804 }; 4425 };
4805 }; 4426 };
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