1 // SPDX-License-Identifier: BSD-3-Clause 1 // SPDX-License-Identifier: BSD-3-Clause
2 /* 2 /*
3 * SC7180 SoC device tree source 3 * SC7180 SoC device tree source
4 * 4 *
5 * Copyright (c) 2019-2020, The Linux Foundati !! 5 * Copyright (c) 2019, The Linux Foundation. All rights reserved.
6 */ 6 */
7 7
8 #include <dt-bindings/clock/qcom,dispcc-sc7180 8 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
9 #include <dt-bindings/clock/qcom,gcc-sc7180.h> 9 #include <dt-bindings/clock/qcom,gcc-sc7180.h>
10 #include <dt-bindings/clock/qcom,gpucc-sc7180. 10 #include <dt-bindings/clock/qcom,gpucc-sc7180.h>
11 #include <dt-bindings/clock/qcom,lpasscorecc-s <<
12 #include <dt-bindings/clock/qcom,rpmh.h> 11 #include <dt-bindings/clock/qcom,rpmh.h>
13 #include <dt-bindings/clock/qcom,videocc-sc718 12 #include <dt-bindings/clock/qcom,videocc-sc7180.h>
14 #include <dt-bindings/firmware/qcom,scm.h> <<
15 #include <dt-bindings/interconnect/qcom,icc.h> <<
16 #include <dt-bindings/interconnect/qcom,osm-l3 <<
17 #include <dt-bindings/interconnect/qcom,sc7180 13 #include <dt-bindings/interconnect/qcom,sc7180.h>
18 #include <dt-bindings/interrupt-controller/arm 14 #include <dt-bindings/interrupt-controller/arm-gic.h>
19 #include <dt-bindings/phy/phy-qcom-qmp.h> <<
20 #include <dt-bindings/phy/phy-qcom-qusb2.h> 15 #include <dt-bindings/phy/phy-qcom-qusb2.h>
>> 16 #include <dt-bindings/power/qcom-aoss-qmp.h>
21 #include <dt-bindings/power/qcom-rpmpd.h> 17 #include <dt-bindings/power/qcom-rpmpd.h>
22 #include <dt-bindings/reset/qcom,sdm845-aoss.h 18 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
23 #include <dt-bindings/reset/qcom,sdm845-pdc.h> 19 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
24 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 20 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
25 #include <dt-bindings/soc/qcom,apr.h> <<
26 #include <dt-bindings/sound/qcom,q6afe.h> <<
27 #include <dt-bindings/thermal/thermal.h> 21 #include <dt-bindings/thermal/thermal.h>
28 22
29 / { 23 / {
30 interrupt-parent = <&intc>; 24 interrupt-parent = <&intc>;
31 25
32 #address-cells = <2>; 26 #address-cells = <2>;
33 #size-cells = <2>; 27 #size-cells = <2>;
34 28
>> 29 chosen { };
>> 30
35 aliases { 31 aliases {
36 mmc1 = &sdhc_1; <<
37 mmc2 = &sdhc_2; <<
38 i2c0 = &i2c0; 32 i2c0 = &i2c0;
39 i2c1 = &i2c1; 33 i2c1 = &i2c1;
40 i2c2 = &i2c2; 34 i2c2 = &i2c2;
41 i2c3 = &i2c3; 35 i2c3 = &i2c3;
42 i2c4 = &i2c4; 36 i2c4 = &i2c4;
43 i2c5 = &i2c5; 37 i2c5 = &i2c5;
44 i2c6 = &i2c6; 38 i2c6 = &i2c6;
45 i2c7 = &i2c7; 39 i2c7 = &i2c7;
46 i2c8 = &i2c8; 40 i2c8 = &i2c8;
47 i2c9 = &i2c9; 41 i2c9 = &i2c9;
48 i2c10 = &i2c10; 42 i2c10 = &i2c10;
49 i2c11 = &i2c11; 43 i2c11 = &i2c11;
50 spi0 = &spi0; 44 spi0 = &spi0;
51 spi1 = &spi1; 45 spi1 = &spi1;
52 spi3 = &spi3; 46 spi3 = &spi3;
53 spi5 = &spi5; 47 spi5 = &spi5;
54 spi6 = &spi6; 48 spi6 = &spi6;
55 spi8 = &spi8; 49 spi8 = &spi8;
56 spi10 = &spi10; 50 spi10 = &spi10;
57 spi11 = &spi11; 51 spi11 = &spi11;
58 }; 52 };
59 53
60 chosen { }; <<
61 <<
62 clocks { 54 clocks {
63 xo_board: xo-board { 55 xo_board: xo-board {
64 compatible = "fixed-cl 56 compatible = "fixed-clock";
65 clock-frequency = <384 57 clock-frequency = <38400000>;
66 #clock-cells = <0>; 58 #clock-cells = <0>;
67 }; 59 };
68 60
69 sleep_clk: sleep-clk { 61 sleep_clk: sleep-clk {
70 compatible = "fixed-cl 62 compatible = "fixed-clock";
71 clock-frequency = <327 63 clock-frequency = <32764>;
72 #clock-cells = <0>; 64 #clock-cells = <0>;
73 }; 65 };
74 }; 66 };
75 67
>> 68 reserved_memory: reserved-memory {
>> 69 #address-cells = <2>;
>> 70 #size-cells = <2>;
>> 71 ranges;
>> 72
>> 73 hyp_mem: memory@80000000 {
>> 74 reg = <0x0 0x80000000 0x0 0x600000>;
>> 75 no-map;
>> 76 };
>> 77
>> 78 xbl_mem: memory@80600000 {
>> 79 reg = <0x0 0x80600000 0x0 0x200000>;
>> 80 no-map;
>> 81 };
>> 82
>> 83 aop_mem: memory@80800000 {
>> 84 reg = <0x0 0x80800000 0x0 0x20000>;
>> 85 no-map;
>> 86 };
>> 87
>> 88 aop_cmd_db_mem: memory@80820000 {
>> 89 reg = <0x0 0x80820000 0x0 0x20000>;
>> 90 compatible = "qcom,cmd-db";
>> 91 no-map;
>> 92 };
>> 93
>> 94 sec_apps_mem: memory@808ff000 {
>> 95 reg = <0x0 0x808ff000 0x0 0x1000>;
>> 96 no-map;
>> 97 };
>> 98
>> 99 smem_mem: memory@80900000 {
>> 100 reg = <0x0 0x80900000 0x0 0x200000>;
>> 101 no-map;
>> 102 };
>> 103
>> 104 tz_mem: memory@80b00000 {
>> 105 reg = <0x0 0x80b00000 0x0 0x3900000>;
>> 106 no-map;
>> 107 };
>> 108
>> 109 rmtfs_mem: memory@84400000 {
>> 110 compatible = "qcom,rmtfs-mem";
>> 111 reg = <0x0 0x84400000 0x0 0x200000>;
>> 112 no-map;
>> 113
>> 114 qcom,client-id = <1>;
>> 115 qcom,vmid = <15>;
>> 116 };
>> 117 };
>> 118
76 cpus { 119 cpus {
77 #address-cells = <2>; 120 #address-cells = <2>;
78 #size-cells = <0>; 121 #size-cells = <0>;
79 122
80 CPU0: cpu@0 { 123 CPU0: cpu@0 {
81 device_type = "cpu"; 124 device_type = "cpu";
82 compatible = "qcom,kry 125 compatible = "qcom,kryo468";
83 reg = <0x0 0x0>; 126 reg = <0x0 0x0>;
84 clocks = <&cpufreq_hw <<
85 enable-method = "psci" 127 enable-method = "psci";
86 power-domains = <&CPU_ !! 128 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
87 power-domain-names = " !! 129 &LITTLE_CPU_SLEEP_1
88 capacity-dmips-mhz = < !! 130 &CLUSTER_SLEEP_0>;
89 dynamic-power-coeffici !! 131 capacity-dmips-mhz = <1024>;
90 operating-points-v2 = !! 132 dynamic-power-coefficient = <100>;
91 interconnects = <&gem_ <<
92 <&osm_ <<
93 next-level-cache = <&L 133 next-level-cache = <&L2_0>;
94 #cooling-cells = <2>; 134 #cooling-cells = <2>;
95 qcom,freq-domain = <&c 135 qcom,freq-domain = <&cpufreq_hw 0>;
96 L2_0: l2-cache { 136 L2_0: l2-cache {
97 compatible = " 137 compatible = "cache";
98 cache-level = <<
99 cache-unified; <<
100 next-level-cac 138 next-level-cache = <&L3_0>;
101 L3_0: l3-cache 139 L3_0: l3-cache {
102 compat 140 compatible = "cache";
103 cache- <<
104 cache- <<
105 }; 141 };
106 }; 142 };
107 }; 143 };
108 144
109 CPU1: cpu@100 { 145 CPU1: cpu@100 {
110 device_type = "cpu"; 146 device_type = "cpu";
111 compatible = "qcom,kry 147 compatible = "qcom,kryo468";
112 reg = <0x0 0x100>; 148 reg = <0x0 0x100>;
113 clocks = <&cpufreq_hw <<
114 enable-method = "psci" 149 enable-method = "psci";
115 power-domains = <&CPU_ !! 150 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
116 power-domain-names = " !! 151 &LITTLE_CPU_SLEEP_1
117 capacity-dmips-mhz = < !! 152 &CLUSTER_SLEEP_0>;
118 dynamic-power-coeffici !! 153 capacity-dmips-mhz = <1024>;
>> 154 dynamic-power-coefficient = <100>;
119 next-level-cache = <&L 155 next-level-cache = <&L2_100>;
120 operating-points-v2 = <<
121 interconnects = <&gem_ <<
122 <&osm_ <<
123 #cooling-cells = <2>; 156 #cooling-cells = <2>;
124 qcom,freq-domain = <&c 157 qcom,freq-domain = <&cpufreq_hw 0>;
125 L2_100: l2-cache { 158 L2_100: l2-cache {
126 compatible = " 159 compatible = "cache";
127 cache-level = <<
128 cache-unified; <<
129 next-level-cac 160 next-level-cache = <&L3_0>;
130 }; 161 };
131 }; 162 };
132 163
133 CPU2: cpu@200 { 164 CPU2: cpu@200 {
134 device_type = "cpu"; 165 device_type = "cpu";
135 compatible = "qcom,kry 166 compatible = "qcom,kryo468";
136 reg = <0x0 0x200>; 167 reg = <0x0 0x200>;
137 clocks = <&cpufreq_hw <<
138 enable-method = "psci" 168 enable-method = "psci";
139 power-domains = <&CPU_ !! 169 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
140 power-domain-names = " !! 170 &LITTLE_CPU_SLEEP_1
141 capacity-dmips-mhz = < !! 171 &CLUSTER_SLEEP_0>;
142 dynamic-power-coeffici !! 172 capacity-dmips-mhz = <1024>;
>> 173 dynamic-power-coefficient = <100>;
143 next-level-cache = <&L 174 next-level-cache = <&L2_200>;
144 operating-points-v2 = <<
145 interconnects = <&gem_ <<
146 <&osm_ <<
147 #cooling-cells = <2>; 175 #cooling-cells = <2>;
148 qcom,freq-domain = <&c 176 qcom,freq-domain = <&cpufreq_hw 0>;
149 L2_200: l2-cache { 177 L2_200: l2-cache {
150 compatible = " 178 compatible = "cache";
151 cache-level = <<
152 cache-unified; <<
153 next-level-cac 179 next-level-cache = <&L3_0>;
154 }; 180 };
155 }; 181 };
156 182
157 CPU3: cpu@300 { 183 CPU3: cpu@300 {
158 device_type = "cpu"; 184 device_type = "cpu";
159 compatible = "qcom,kry 185 compatible = "qcom,kryo468";
160 reg = <0x0 0x300>; 186 reg = <0x0 0x300>;
161 clocks = <&cpufreq_hw <<
162 enable-method = "psci" 187 enable-method = "psci";
163 power-domains = <&CPU_ !! 188 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
164 power-domain-names = " !! 189 &LITTLE_CPU_SLEEP_1
165 capacity-dmips-mhz = < !! 190 &CLUSTER_SLEEP_0>;
166 dynamic-power-coeffici !! 191 capacity-dmips-mhz = <1024>;
>> 192 dynamic-power-coefficient = <100>;
167 next-level-cache = <&L 193 next-level-cache = <&L2_300>;
168 operating-points-v2 = <<
169 interconnects = <&gem_ <<
170 <&osm_ <<
171 #cooling-cells = <2>; 194 #cooling-cells = <2>;
172 qcom,freq-domain = <&c 195 qcom,freq-domain = <&cpufreq_hw 0>;
173 L2_300: l2-cache { 196 L2_300: l2-cache {
174 compatible = " 197 compatible = "cache";
175 cache-level = <<
176 cache-unified; <<
177 next-level-cac 198 next-level-cache = <&L3_0>;
178 }; 199 };
179 }; 200 };
180 201
181 CPU4: cpu@400 { 202 CPU4: cpu@400 {
182 device_type = "cpu"; 203 device_type = "cpu";
183 compatible = "qcom,kry 204 compatible = "qcom,kryo468";
184 reg = <0x0 0x400>; 205 reg = <0x0 0x400>;
185 clocks = <&cpufreq_hw <<
186 enable-method = "psci" 206 enable-method = "psci";
187 power-domains = <&CPU_ !! 207 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
188 power-domain-names = " !! 208 &LITTLE_CPU_SLEEP_1
189 capacity-dmips-mhz = < !! 209 &CLUSTER_SLEEP_0>;
190 dynamic-power-coeffici !! 210 capacity-dmips-mhz = <1024>;
>> 211 dynamic-power-coefficient = <100>;
191 next-level-cache = <&L 212 next-level-cache = <&L2_400>;
192 operating-points-v2 = <<
193 interconnects = <&gem_ <<
194 <&osm_ <<
195 #cooling-cells = <2>; 213 #cooling-cells = <2>;
196 qcom,freq-domain = <&c 214 qcom,freq-domain = <&cpufreq_hw 0>;
197 L2_400: l2-cache { 215 L2_400: l2-cache {
198 compatible = " 216 compatible = "cache";
199 cache-level = <<
200 cache-unified; <<
201 next-level-cac 217 next-level-cache = <&L3_0>;
202 }; 218 };
203 }; 219 };
204 220
205 CPU5: cpu@500 { 221 CPU5: cpu@500 {
206 device_type = "cpu"; 222 device_type = "cpu";
207 compatible = "qcom,kry 223 compatible = "qcom,kryo468";
208 reg = <0x0 0x500>; 224 reg = <0x0 0x500>;
209 clocks = <&cpufreq_hw <<
210 enable-method = "psci" 225 enable-method = "psci";
211 power-domains = <&CPU_ !! 226 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
212 power-domain-names = " !! 227 &LITTLE_CPU_SLEEP_1
213 capacity-dmips-mhz = < !! 228 &CLUSTER_SLEEP_0>;
214 dynamic-power-coeffici !! 229 capacity-dmips-mhz = <1024>;
>> 230 dynamic-power-coefficient = <100>;
215 next-level-cache = <&L 231 next-level-cache = <&L2_500>;
216 operating-points-v2 = <<
217 interconnects = <&gem_ <<
218 <&osm_ <<
219 #cooling-cells = <2>; 232 #cooling-cells = <2>;
220 qcom,freq-domain = <&c 233 qcom,freq-domain = <&cpufreq_hw 0>;
221 L2_500: l2-cache { 234 L2_500: l2-cache {
222 compatible = " 235 compatible = "cache";
223 cache-level = <<
224 cache-unified; <<
225 next-level-cac 236 next-level-cache = <&L3_0>;
226 }; 237 };
227 }; 238 };
228 239
229 CPU6: cpu@600 { 240 CPU6: cpu@600 {
230 device_type = "cpu"; 241 device_type = "cpu";
231 compatible = "qcom,kry 242 compatible = "qcom,kryo468";
232 reg = <0x0 0x600>; 243 reg = <0x0 0x600>;
233 clocks = <&cpufreq_hw <<
234 enable-method = "psci" 244 enable-method = "psci";
235 power-domains = <&CPU_ !! 245 cpu-idle-states = <&BIG_CPU_SLEEP_0
236 power-domain-names = " !! 246 &BIG_CPU_SLEEP_1
237 capacity-dmips-mhz = < !! 247 &CLUSTER_SLEEP_0>;
238 dynamic-power-coeffici !! 248 capacity-dmips-mhz = <1740>;
>> 249 dynamic-power-coefficient = <405>;
239 next-level-cache = <&L 250 next-level-cache = <&L2_600>;
240 operating-points-v2 = <<
241 interconnects = <&gem_ <<
242 <&osm_ <<
243 #cooling-cells = <2>; 251 #cooling-cells = <2>;
244 qcom,freq-domain = <&c 252 qcom,freq-domain = <&cpufreq_hw 1>;
245 L2_600: l2-cache { 253 L2_600: l2-cache {
246 compatible = " 254 compatible = "cache";
247 cache-level = <<
248 cache-unified; <<
249 next-level-cac 255 next-level-cache = <&L3_0>;
250 }; 256 };
251 }; 257 };
252 258
253 CPU7: cpu@700 { 259 CPU7: cpu@700 {
254 device_type = "cpu"; 260 device_type = "cpu";
255 compatible = "qcom,kry 261 compatible = "qcom,kryo468";
256 reg = <0x0 0x700>; 262 reg = <0x0 0x700>;
257 clocks = <&cpufreq_hw <<
258 enable-method = "psci" 263 enable-method = "psci";
259 power-domains = <&CPU_ !! 264 cpu-idle-states = <&BIG_CPU_SLEEP_0
260 power-domain-names = " !! 265 &BIG_CPU_SLEEP_1
261 capacity-dmips-mhz = < !! 266 &CLUSTER_SLEEP_0>;
262 dynamic-power-coeffici !! 267 capacity-dmips-mhz = <1740>;
>> 268 dynamic-power-coefficient = <405>;
263 next-level-cache = <&L 269 next-level-cache = <&L2_700>;
264 operating-points-v2 = <<
265 interconnects = <&gem_ <<
266 <&osm_ <<
267 #cooling-cells = <2>; 270 #cooling-cells = <2>;
268 qcom,freq-domain = <&c 271 qcom,freq-domain = <&cpufreq_hw 1>;
269 L2_700: l2-cache { 272 L2_700: l2-cache {
270 compatible = " 273 compatible = "cache";
271 cache-level = <<
272 cache-unified; <<
273 next-level-cac 274 next-level-cache = <&L3_0>;
274 }; 275 };
275 }; 276 };
276 277
277 cpu-map { 278 cpu-map {
278 cluster0 { 279 cluster0 {
279 core0 { 280 core0 {
280 cpu = 281 cpu = <&CPU0>;
281 }; 282 };
282 283
283 core1 { 284 core1 {
284 cpu = 285 cpu = <&CPU1>;
285 }; 286 };
286 287
287 core2 { 288 core2 {
288 cpu = 289 cpu = <&CPU2>;
289 }; 290 };
290 291
291 core3 { 292 core3 {
292 cpu = 293 cpu = <&CPU3>;
293 }; 294 };
294 295
295 core4 { 296 core4 {
296 cpu = 297 cpu = <&CPU4>;
297 }; 298 };
298 299
299 core5 { 300 core5 {
300 cpu = 301 cpu = <&CPU5>;
301 }; 302 };
302 303
303 core6 { 304 core6 {
304 cpu = 305 cpu = <&CPU6>;
305 }; 306 };
306 307
307 core7 { 308 core7 {
308 cpu = 309 cpu = <&CPU7>;
309 }; 310 };
310 }; 311 };
311 }; 312 };
312 313
313 idle_states: idle-states { !! 314 idle-states {
314 entry-method = "psci"; 315 entry-method = "psci";
315 316
316 LITTLE_CPU_SLEEP_0: cp 317 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
317 compatible = " 318 compatible = "arm,idle-state";
318 idle-state-nam 319 idle-state-name = "little-power-down";
319 arm,psci-suspe 320 arm,psci-suspend-param = <0x40000003>;
320 entry-latency- 321 entry-latency-us = <549>;
321 exit-latency-u 322 exit-latency-us = <901>;
322 min-residency- 323 min-residency-us = <1774>;
323 local-timer-st 324 local-timer-stop;
324 }; 325 };
325 326
326 LITTLE_CPU_SLEEP_1: cp 327 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
327 compatible = " 328 compatible = "arm,idle-state";
328 idle-state-nam 329 idle-state-name = "little-rail-power-down";
329 arm,psci-suspe 330 arm,psci-suspend-param = <0x40000004>;
330 entry-latency- 331 entry-latency-us = <702>;
331 exit-latency-u 332 exit-latency-us = <915>;
332 min-residency- 333 min-residency-us = <4001>;
333 local-timer-st 334 local-timer-stop;
334 }; 335 };
335 336
336 BIG_CPU_SLEEP_0: cpu-s 337 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
337 compatible = " 338 compatible = "arm,idle-state";
338 idle-state-nam 339 idle-state-name = "big-power-down";
339 arm,psci-suspe 340 arm,psci-suspend-param = <0x40000003>;
340 entry-latency- 341 entry-latency-us = <523>;
341 exit-latency-u 342 exit-latency-us = <1244>;
342 min-residency- 343 min-residency-us = <2207>;
343 local-timer-st 344 local-timer-stop;
344 }; 345 };
345 346
346 BIG_CPU_SLEEP_1: cpu-s 347 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
347 compatible = " 348 compatible = "arm,idle-state";
348 idle-state-nam 349 idle-state-name = "big-rail-power-down";
349 arm,psci-suspe 350 arm,psci-suspend-param = <0x40000004>;
350 entry-latency- 351 entry-latency-us = <526>;
351 exit-latency-u 352 exit-latency-us = <1854>;
352 min-residency- 353 min-residency-us = <5555>;
353 local-timer-st 354 local-timer-stop;
354 }; 355 };
355 }; <<
356 <<
357 domain_idle_states: domain-idl <<
358 CLUSTER_SLEEP_PC: clus <<
359 compatible = " <<
360 idle-state-nam <<
361 arm,psci-suspe <<
362 entry-latency- <<
363 exit-latency-u <<
364 min-residency- <<
365 }; <<
366 <<
367 CLUSTER_SLEEP_CX_RET: <<
368 compatible = " <<
369 idle-state-nam <<
370 arm,psci-suspe <<
371 entry-latency- <<
372 exit-latency-u <<
373 min-residency- <<
374 }; <<
375 356
376 CLUSTER_AOSS_SLEEP: cl !! 357 CLUSTER_SLEEP_0: cluster-sleep-0 {
377 compatible = " !! 358 compatible = "arm,idle-state";
378 idle-state-nam 359 idle-state-name = "cluster-power-down";
379 arm,psci-suspe !! 360 arm,psci-suspend-param = <0x40003444>;
380 entry-latency- 361 entry-latency-us = <3263>;
381 exit-latency-u 362 exit-latency-us = <6562>;
382 min-residency- !! 363 min-residency-us = <9926>;
>> 364 local-timer-stop;
383 }; 365 };
384 }; 366 };
385 }; 367 };
386 368
387 firmware { <<
388 scm: scm { <<
389 compatible = "qcom,scm <<
390 }; <<
391 }; <<
392 <<
393 memory@80000000 { 369 memory@80000000 {
394 device_type = "memory"; 370 device_type = "memory";
395 /* We expect the bootloader to 371 /* We expect the bootloader to fill in the size */
396 reg = <0 0x80000000 0 0>; 372 reg = <0 0x80000000 0 0>;
397 }; 373 };
398 374
399 cpu0_opp_table: opp-table-cpu0 { <<
400 compatible = "operating-points <<
401 opp-shared; <<
402 <<
403 cpu0_opp1: opp-300000000 { <<
404 opp-hz = /bits/ 64 <30 <<
405 opp-peak-kBps = <12000 <<
406 }; <<
407 <<
408 cpu0_opp2: opp-576000000 { <<
409 opp-hz = /bits/ 64 <57 <<
410 opp-peak-kBps = <12000 <<
411 }; <<
412 <<
413 cpu0_opp3: opp-768000000 { <<
414 opp-hz = /bits/ 64 <76 <<
415 opp-peak-kBps = <12000 <<
416 }; <<
417 <<
418 cpu0_opp4: opp-1017600000 { <<
419 opp-hz = /bits/ 64 <10 <<
420 opp-peak-kBps = <18040 <<
421 }; <<
422 <<
423 cpu0_opp5: opp-1248000000 { <<
424 opp-hz = /bits/ 64 <12 <<
425 opp-peak-kBps = <21880 <<
426 }; <<
427 <<
428 cpu0_opp6: opp-1324800000 { <<
429 opp-hz = /bits/ 64 <13 <<
430 opp-peak-kBps = <21880 <<
431 }; <<
432 <<
433 cpu0_opp7: opp-1516800000 { <<
434 opp-hz = /bits/ 64 <15 <<
435 opp-peak-kBps = <30720 <<
436 }; <<
437 <<
438 cpu0_opp8: opp-1612800000 { <<
439 opp-hz = /bits/ 64 <16 <<
440 opp-peak-kBps = <30720 <<
441 }; <<
442 <<
443 cpu0_opp9: opp-1708800000 { <<
444 opp-hz = /bits/ 64 <17 <<
445 opp-peak-kBps = <30720 <<
446 }; <<
447 <<
448 cpu0_opp10: opp-1804800000 { <<
449 opp-hz = /bits/ 64 <18 <<
450 opp-peak-kBps = <40680 <<
451 }; <<
452 }; <<
453 <<
454 cpu6_opp_table: opp-table-cpu6 { <<
455 compatible = "operating-points <<
456 opp-shared; <<
457 <<
458 cpu6_opp1: opp-300000000 { <<
459 opp-hz = /bits/ 64 <30 <<
460 opp-peak-kBps = <21880 <<
461 }; <<
462 <<
463 cpu6_opp2: opp-652800000 { <<
464 opp-hz = /bits/ 64 <65 <<
465 opp-peak-kBps = <21880 <<
466 }; <<
467 <<
468 cpu6_opp3: opp-825600000 { <<
469 opp-hz = /bits/ 64 <82 <<
470 opp-peak-kBps = <21880 <<
471 }; <<
472 <<
473 cpu6_opp4: opp-979200000 { <<
474 opp-hz = /bits/ 64 <97 <<
475 opp-peak-kBps = <21880 <<
476 }; <<
477 <<
478 cpu6_opp5: opp-1113600000 { <<
479 opp-hz = /bits/ 64 <11 <<
480 opp-peak-kBps = <21880 <<
481 }; <<
482 <<
483 cpu6_opp6: opp-1267200000 { <<
484 opp-hz = /bits/ 64 <12 <<
485 opp-peak-kBps = <40680 <<
486 }; <<
487 <<
488 cpu6_opp7: opp-1555200000 { <<
489 opp-hz = /bits/ 64 <15 <<
490 opp-peak-kBps = <40680 <<
491 }; <<
492 <<
493 cpu6_opp8: opp-1708800000 { <<
494 opp-hz = /bits/ 64 <17 <<
495 opp-peak-kBps = <62200 <<
496 }; <<
497 <<
498 cpu6_opp9: opp-1843200000 { <<
499 opp-hz = /bits/ 64 <18 <<
500 opp-peak-kBps = <62200 <<
501 }; <<
502 <<
503 cpu6_opp10: opp-1900800000 { <<
504 opp-hz = /bits/ 64 <19 <<
505 opp-peak-kBps = <62200 <<
506 }; <<
507 <<
508 cpu6_opp11: opp-1996800000 { <<
509 opp-hz = /bits/ 64 <19 <<
510 opp-peak-kBps = <62200 <<
511 }; <<
512 <<
513 cpu6_opp12: opp-2112000000 { <<
514 opp-hz = /bits/ 64 <21 <<
515 opp-peak-kBps = <62200 <<
516 }; <<
517 <<
518 cpu6_opp13: opp-2208000000 { <<
519 opp-hz = /bits/ 64 <22 <<
520 opp-peak-kBps = <72160 <<
521 }; <<
522 <<
523 cpu6_opp14: opp-2323200000 { <<
524 opp-hz = /bits/ 64 <23 <<
525 opp-peak-kBps = <72160 <<
526 }; <<
527 <<
528 cpu6_opp15: opp-2400000000 { <<
529 opp-hz = /bits/ 64 <24 <<
530 opp-peak-kBps = <85320 <<
531 }; <<
532 <<
533 cpu6_opp16: opp-2553600000 { <<
534 opp-hz = /bits/ 64 <25 <<
535 opp-peak-kBps = <85320 <<
536 }; <<
537 }; <<
538 <<
539 qspi_opp_table: opp-table-qspi { <<
540 compatible = "operating-points <<
541 <<
542 opp-75000000 { <<
543 opp-hz = /bits/ 64 <75 <<
544 required-opps = <&rpmh <<
545 }; <<
546 <<
547 opp-150000000 { <<
548 opp-hz = /bits/ 64 <15 <<
549 required-opps = <&rpmh <<
550 }; <<
551 <<
552 opp-300000000 { <<
553 opp-hz = /bits/ 64 <30 <<
554 required-opps = <&rpmh <<
555 }; <<
556 }; <<
557 <<
558 qup_opp_table: opp-table-qup { <<
559 compatible = "operating-points <<
560 <<
561 opp-75000000 { <<
562 opp-hz = /bits/ 64 <75 <<
563 required-opps = <&rpmh <<
564 }; <<
565 <<
566 opp-100000000 { <<
567 opp-hz = /bits/ 64 <10 <<
568 required-opps = <&rpmh <<
569 }; <<
570 <<
571 opp-128000000 { <<
572 opp-hz = /bits/ 64 <12 <<
573 required-opps = <&rpmh <<
574 }; <<
575 }; <<
576 <<
577 pmu { 375 pmu {
578 compatible = "arm,armv8-pmuv3" 376 compatible = "arm,armv8-pmuv3";
579 interrupts = <GIC_PPI 5 IRQ_TY 377 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
580 }; 378 };
581 379
582 psci { !! 380 firmware {
583 compatible = "arm,psci-1.0"; !! 381 scm {
584 method = "smc"; !! 382 compatible = "qcom,scm-sc7180", "qcom,scm";
585 <<
586 CPU_PD0: cpu0 { <<
587 #power-domain-cells = <<
588 power-domains = <&CLUS <<
589 domain-idle-states = < <<
590 }; <<
591 <<
592 CPU_PD1: cpu1 { <<
593 #power-domain-cells = <<
594 power-domains = <&CLUS <<
595 domain-idle-states = < <<
596 }; <<
597 <<
598 CPU_PD2: cpu2 { <<
599 #power-domain-cells = <<
600 power-domains = <&CLUS <<
601 domain-idle-states = < <<
602 }; <<
603 <<
604 CPU_PD3: cpu3 { <<
605 #power-domain-cells = <<
606 power-domains = <&CLUS <<
607 domain-idle-states = < <<
608 }; <<
609 <<
610 CPU_PD4: cpu4 { <<
611 #power-domain-cells = <<
612 power-domains = <&CLUS <<
613 domain-idle-states = < <<
614 }; <<
615 <<
616 CPU_PD5: cpu5 { <<
617 #power-domain-cells = <<
618 power-domains = <&CLUS <<
619 domain-idle-states = < <<
620 }; <<
621 <<
622 CPU_PD6: cpu6 { <<
623 #power-domain-cells = <<
624 power-domains = <&CLUS <<
625 domain-idle-states = < <<
626 }; <<
627 <<
628 CPU_PD7: cpu7 { <<
629 #power-domain-cells = <<
630 power-domains = <&CLUS <<
631 domain-idle-states = < <<
632 }; <<
633 <<
634 CLUSTER_PD: cpu-cluster0 { <<
635 #power-domain-cells = <<
636 domain-idle-states = < <<
637 <<
638 <<
639 }; 383 };
640 }; 384 };
641 385
642 reserved_memory: reserved-memory { !! 386 tcsr_mutex: hwlock {
643 #address-cells = <2>; !! 387 compatible = "qcom,tcsr-mutex";
644 #size-cells = <2>; !! 388 syscon = <&tcsr_mutex_regs 0 0x1000>;
645 ranges; !! 389 #hwlock-cells = <1>;
646 <<
647 hyp_mem: memory@80000000 { <<
648 reg = <0x0 0x80000000 <<
649 no-map; <<
650 }; <<
651 <<
652 xbl_mem: memory@80600000 { <<
653 reg = <0x0 0x80600000 <<
654 no-map; <<
655 }; <<
656 <<
657 aop_mem: memory@80800000 { <<
658 reg = <0x0 0x80800000 <<
659 no-map; <<
660 }; <<
661 <<
662 aop_cmd_db_mem: memory@8082000 <<
663 reg = <0x0 0x80820000 <<
664 compatible = "qcom,cmd <<
665 no-map; <<
666 }; <<
667 <<
668 sec_apps_mem: memory@808ff000 <<
669 reg = <0x0 0x808ff000 <<
670 no-map; <<
671 }; <<
672 <<
673 smem_mem: memory@80900000 { <<
674 reg = <0x0 0x80900000 <<
675 no-map; <<
676 }; <<
677 <<
678 tz_mem: memory@80b00000 { <<
679 reg = <0x0 0x80b00000 <<
680 no-map; <<
681 }; <<
682 <<
683 ipa_fw_mem: memory@8b700000 { <<
684 reg = <0 0x8b700000 0 <<
685 no-map; <<
686 }; <<
687 <<
688 rmtfs_mem: memory@94600000 { <<
689 compatible = "qcom,rmt <<
690 reg = <0x0 0x94600000 <<
691 no-map; <<
692 <<
693 qcom,client-id = <1>; <<
694 qcom,vmid = <QCOM_SCM_ <<
695 }; <<
696 }; 390 };
697 391
698 smem { 392 smem {
699 compatible = "qcom,smem"; 393 compatible = "qcom,smem";
700 memory-region = <&smem_mem>; 394 memory-region = <&smem_mem>;
701 hwlocks = <&tcsr_mutex 3>; 395 hwlocks = <&tcsr_mutex 3>;
702 }; 396 };
703 397
704 smp2p-cdsp { 398 smp2p-cdsp {
705 compatible = "qcom,smp2p"; 399 compatible = "qcom,smp2p";
706 qcom,smem = <94>, <432>; 400 qcom,smem = <94>, <432>;
707 401
708 interrupts = <GIC_SPI 576 IRQ_ 402 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
709 403
710 mboxes = <&apss_shared 6>; 404 mboxes = <&apss_shared 6>;
711 405
712 qcom,local-pid = <0>; 406 qcom,local-pid = <0>;
713 qcom,remote-pid = <5>; 407 qcom,remote-pid = <5>;
714 408
715 cdsp_smp2p_out: master-kernel 409 cdsp_smp2p_out: master-kernel {
716 qcom,entry-name = "mas 410 qcom,entry-name = "master-kernel";
717 #qcom,smem-state-cells 411 #qcom,smem-state-cells = <1>;
718 }; 412 };
719 413
720 cdsp_smp2p_in: slave-kernel { 414 cdsp_smp2p_in: slave-kernel {
721 qcom,entry-name = "sla 415 qcom,entry-name = "slave-kernel";
722 416
723 interrupt-controller; 417 interrupt-controller;
724 #interrupt-cells = <2> 418 #interrupt-cells = <2>;
725 }; 419 };
726 }; 420 };
727 421
728 smp2p-lpass { 422 smp2p-lpass {
729 compatible = "qcom,smp2p"; 423 compatible = "qcom,smp2p";
730 qcom,smem = <443>, <429>; 424 qcom,smem = <443>, <429>;
731 425
732 interrupts = <GIC_SPI 158 IRQ_ 426 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
733 427
734 mboxes = <&apss_shared 10>; 428 mboxes = <&apss_shared 10>;
735 429
736 qcom,local-pid = <0>; 430 qcom,local-pid = <0>;
737 qcom,remote-pid = <2>; 431 qcom,remote-pid = <2>;
738 432
739 adsp_smp2p_out: master-kernel 433 adsp_smp2p_out: master-kernel {
740 qcom,entry-name = "mas 434 qcom,entry-name = "master-kernel";
741 #qcom,smem-state-cells 435 #qcom,smem-state-cells = <1>;
742 }; 436 };
743 437
744 adsp_smp2p_in: slave-kernel { 438 adsp_smp2p_in: slave-kernel {
745 qcom,entry-name = "sla 439 qcom,entry-name = "slave-kernel";
746 440
747 interrupt-controller; 441 interrupt-controller;
748 #interrupt-cells = <2> 442 #interrupt-cells = <2>;
749 }; 443 };
750 }; 444 };
751 445
752 smp2p-mpss { 446 smp2p-mpss {
753 compatible = "qcom,smp2p"; 447 compatible = "qcom,smp2p";
754 qcom,smem = <435>, <428>; 448 qcom,smem = <435>, <428>;
755 interrupts = <GIC_SPI 451 IRQ_ 449 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
756 mboxes = <&apss_shared 14>; 450 mboxes = <&apss_shared 14>;
757 qcom,local-pid = <0>; 451 qcom,local-pid = <0>;
758 qcom,remote-pid = <1>; 452 qcom,remote-pid = <1>;
759 453
760 modem_smp2p_out: master-kernel 454 modem_smp2p_out: master-kernel {
761 qcom,entry-name = "mas 455 qcom,entry-name = "master-kernel";
762 #qcom,smem-state-cells 456 #qcom,smem-state-cells = <1>;
763 }; 457 };
764 458
765 modem_smp2p_in: slave-kernel { 459 modem_smp2p_in: slave-kernel {
766 qcom,entry-name = "sla 460 qcom,entry-name = "slave-kernel";
767 interrupt-controller; 461 interrupt-controller;
768 #interrupt-cells = <2> 462 #interrupt-cells = <2>;
769 }; 463 };
770 464
771 ipa_smp2p_out: ipa-ap-to-modem 465 ipa_smp2p_out: ipa-ap-to-modem {
772 qcom,entry-name = "ipa 466 qcom,entry-name = "ipa";
773 #qcom,smem-state-cells 467 #qcom,smem-state-cells = <1>;
774 }; 468 };
775 469
776 ipa_smp2p_in: ipa-modem-to-ap 470 ipa_smp2p_in: ipa-modem-to-ap {
777 qcom,entry-name = "ipa 471 qcom,entry-name = "ipa";
778 interrupt-controller; 472 interrupt-controller;
779 #interrupt-cells = <2> 473 #interrupt-cells = <2>;
780 }; 474 };
781 }; 475 };
782 476
>> 477 psci {
>> 478 compatible = "arm,psci-1.0";
>> 479 method = "smc";
>> 480 };
>> 481
783 soc: soc@0 { 482 soc: soc@0 {
784 #address-cells = <2>; 483 #address-cells = <2>;
785 #size-cells = <2>; 484 #size-cells = <2>;
786 ranges = <0 0 0 0 0x10 0>; 485 ranges = <0 0 0 0 0x10 0>;
787 dma-ranges = <0 0 0 0 0x10 0>; 486 dma-ranges = <0 0 0 0 0x10 0>;
788 compatible = "simple-bus"; 487 compatible = "simple-bus";
789 488
790 gcc: clock-controller@100000 { 489 gcc: clock-controller@100000 {
791 compatible = "qcom,gcc 490 compatible = "qcom,gcc-sc7180";
792 reg = <0 0x00100000 0 491 reg = <0 0x00100000 0 0x1f0000>;
793 clocks = <&rpmhcc RPMH 492 clocks = <&rpmhcc RPMH_CXO_CLK>,
794 <&rpmhcc RPMH 493 <&rpmhcc RPMH_CXO_CLK_A>,
795 <&sleep_clk>; 494 <&sleep_clk>;
796 clock-names = "bi_tcxo 495 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
797 #clock-cells = <1>; 496 #clock-cells = <1>;
798 #reset-cells = <1>; 497 #reset-cells = <1>;
799 #power-domain-cells = 498 #power-domain-cells = <1>;
800 power-domains = <&rpmh <<
801 }; 499 };
802 500
803 qfprom: efuse@784000 { !! 501 qfprom@784000 {
804 compatible = "qcom,sc7 !! 502 compatible = "qcom,qfprom";
805 reg = <0 0x00784000 0 !! 503 reg = <0 0x00784000 0 0x8ff>;
806 <0 0x00780000 0 <<
807 <0 0x00782000 0 <<
808 <0 0x00786000 0 <<
809 <<
810 clocks = <&gcc GCC_SEC <<
811 clock-names = "core"; <<
812 #address-cells = <1>; 504 #address-cells = <1>;
813 #size-cells = <1>; 505 #size-cells = <1>;
814 506
815 qusb2p_hstx_trim: hstx 507 qusb2p_hstx_trim: hstx-trim-primary@25b {
816 reg = <0x25b 0 508 reg = <0x25b 0x1>;
817 bits = <1 3>; 509 bits = <1 3>;
818 }; 510 };
819 <<
820 gpu_speed_bin: gpu-spe <<
821 reg = <0x1d2 0 <<
822 bits = <5 8>; <<
823 }; <<
824 }; 511 };
825 512
826 sdhc_1: mmc@7c4000 { !! 513 sdhc_1: sdhci@7c4000 {
827 compatible = "qcom,sc7 514 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
828 reg = <0 0x007c4000 0 !! 515 reg = <0 0x7c4000 0 0x1000>,
829 <0 0x007c5000 !! 516 <0 0x07c5000 0 0x1000>;
830 reg-names = "hc", "cqh 517 reg-names = "hc", "cqhci";
831 518
832 iommus = <&apps_smmu 0 519 iommus = <&apps_smmu 0x60 0x0>;
833 interrupts = <GIC_SPI 520 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
834 <GIC_S 521 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
835 interrupt-names = "hc_ 522 interrupt-names = "hc_irq", "pwr_irq";
836 523
837 clocks = <&gcc GCC_SDC !! 524 clocks = <&gcc GCC_SDCC1_APPS_CLK>,
838 <&gcc GCC_SDC !! 525 <&gcc GCC_SDCC1_AHB_CLK>;
839 <&rpmhcc RPMH !! 526 clock-names = "core", "iface";
840 clock-names = "iface", <<
841 interconnects = <&aggr <<
842 <&gem_ <<
843 interconnect-names = " <<
844 power-domains = <&rpmh <<
845 operating-points-v2 = <<
846 527
847 bus-width = <8>; 528 bus-width = <8>;
848 non-removable; 529 non-removable;
849 supports-cqe; 530 supports-cqe;
850 531
851 mmc-ddr-1_8v; 532 mmc-ddr-1_8v;
852 mmc-hs200-1_8v; 533 mmc-hs200-1_8v;
853 mmc-hs400-1_8v; 534 mmc-hs400-1_8v;
854 mmc-hs400-enhanced-str 535 mmc-hs400-enhanced-strobe;
855 536
856 status = "disabled"; 537 status = "disabled";
857 <<
858 sdhc1_opp_table: opp-t <<
859 compatible = " <<
860 <<
861 opp-100000000 <<
862 opp-hz <<
863 requir <<
864 opp-pe <<
865 opp-av <<
866 }; <<
867 <<
868 opp-384000000 <<
869 opp-hz <<
870 requir <<
871 opp-pe <<
872 opp-av <<
873 }; <<
874 }; <<
875 }; 538 };
876 539
877 qupv3_id_0: geniqup@8c0000 { 540 qupv3_id_0: geniqup@8c0000 {
878 compatible = "qcom,gen 541 compatible = "qcom,geni-se-qup";
879 reg = <0 0x008c0000 0 542 reg = <0 0x008c0000 0 0x6000>;
880 clock-names = "m-ahb", 543 clock-names = "m-ahb", "s-ahb";
881 clocks = <&gcc GCC_QUP 544 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
882 <&gcc GCC_QUP 545 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
883 #address-cells = <2>; 546 #address-cells = <2>;
884 #size-cells = <2>; 547 #size-cells = <2>;
885 ranges; 548 ranges;
886 iommus = <&apps_smmu 0 549 iommus = <&apps_smmu 0x43 0x0>;
887 status = "disabled"; 550 status = "disabled";
888 551
889 i2c0: i2c@880000 { 552 i2c0: i2c@880000 {
890 compatible = " 553 compatible = "qcom,geni-i2c";
891 reg = <0 0x008 554 reg = <0 0x00880000 0 0x4000>;
892 clock-names = 555 clock-names = "se";
893 clocks = <&gcc 556 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
894 pinctrl-names 557 pinctrl-names = "default";
895 pinctrl-0 = <& 558 pinctrl-0 = <&qup_i2c0_default>;
896 interrupts = < 559 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
897 #address-cells 560 #address-cells = <1>;
898 #size-cells = 561 #size-cells = <0>;
899 interconnects <<
900 <<
901 <<
902 interconnect-n <<
903 <<
904 power-domains <<
905 required-opps <<
906 status = "disa 562 status = "disabled";
907 }; 563 };
908 564
909 spi0: spi@880000 { 565 spi0: spi@880000 {
910 compatible = " 566 compatible = "qcom,geni-spi";
911 reg = <0 0x008 567 reg = <0 0x00880000 0 0x4000>;
912 clock-names = 568 clock-names = "se";
913 clocks = <&gcc 569 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
914 pinctrl-names 570 pinctrl-names = "default";
915 pinctrl-0 = <& !! 571 pinctrl-0 = <&qup_spi0_default>;
916 interrupts = < 572 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
917 #address-cells 573 #address-cells = <1>;
918 #size-cells = 574 #size-cells = <0>;
919 power-domains <<
920 operating-poin <<
921 interconnects <<
922 <<
923 interconnect-n <<
924 status = "disa 575 status = "disabled";
925 }; 576 };
926 577
927 uart0: serial@880000 { 578 uart0: serial@880000 {
928 compatible = " 579 compatible = "qcom,geni-uart";
929 reg = <0 0x008 580 reg = <0 0x00880000 0 0x4000>;
930 clock-names = 581 clock-names = "se";
931 clocks = <&gcc 582 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
932 pinctrl-names 583 pinctrl-names = "default";
933 pinctrl-0 = <& 584 pinctrl-0 = <&qup_uart0_default>;
934 interrupts = < 585 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
935 power-domains <<
936 operating-poin <<
937 interconnects <<
938 <<
939 interconnect-n <<
940 status = "disa 586 status = "disabled";
941 }; 587 };
942 588
943 i2c1: i2c@884000 { 589 i2c1: i2c@884000 {
944 compatible = " 590 compatible = "qcom,geni-i2c";
945 reg = <0 0x008 591 reg = <0 0x00884000 0 0x4000>;
946 clock-names = 592 clock-names = "se";
947 clocks = <&gcc 593 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
948 pinctrl-names 594 pinctrl-names = "default";
949 pinctrl-0 = <& 595 pinctrl-0 = <&qup_i2c1_default>;
950 interrupts = < 596 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
951 #address-cells 597 #address-cells = <1>;
952 #size-cells = 598 #size-cells = <0>;
953 interconnects <<
954 <<
955 <<
956 interconnect-n <<
957 <<
958 power-domains <<
959 required-opps <<
960 status = "disa 599 status = "disabled";
961 }; 600 };
962 601
963 spi1: spi@884000 { 602 spi1: spi@884000 {
964 compatible = " 603 compatible = "qcom,geni-spi";
965 reg = <0 0x008 604 reg = <0 0x00884000 0 0x4000>;
966 clock-names = 605 clock-names = "se";
967 clocks = <&gcc 606 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
968 pinctrl-names 607 pinctrl-names = "default";
969 pinctrl-0 = <& !! 608 pinctrl-0 = <&qup_spi1_default>;
970 interrupts = < 609 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
971 #address-cells 610 #address-cells = <1>;
972 #size-cells = 611 #size-cells = <0>;
973 power-domains <<
974 operating-poin <<
975 interconnects <<
976 <<
977 interconnect-n <<
978 status = "disa 612 status = "disabled";
979 }; 613 };
980 614
981 uart1: serial@884000 { 615 uart1: serial@884000 {
982 compatible = " 616 compatible = "qcom,geni-uart";
983 reg = <0 0x008 617 reg = <0 0x00884000 0 0x4000>;
984 clock-names = 618 clock-names = "se";
985 clocks = <&gcc 619 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
986 pinctrl-names 620 pinctrl-names = "default";
987 pinctrl-0 = <& 621 pinctrl-0 = <&qup_uart1_default>;
988 interrupts = < 622 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
989 power-domains <<
990 operating-poin <<
991 interconnects <<
992 <<
993 interconnect-n <<
994 status = "disa 623 status = "disabled";
995 }; 624 };
996 625
997 i2c2: i2c@888000 { 626 i2c2: i2c@888000 {
998 compatible = " 627 compatible = "qcom,geni-i2c";
999 reg = <0 0x008 628 reg = <0 0x00888000 0 0x4000>;
1000 clock-names = 629 clock-names = "se";
1001 clocks = <&gc 630 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1002 pinctrl-names 631 pinctrl-names = "default";
1003 pinctrl-0 = < 632 pinctrl-0 = <&qup_i2c2_default>;
1004 interrupts = 633 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1005 #address-cell 634 #address-cells = <1>;
1006 #size-cells = 635 #size-cells = <0>;
1007 interconnects <<
1008 <<
1009 <<
1010 interconnect- <<
1011 <<
1012 power-domains <<
1013 required-opps <<
1014 status = "dis 636 status = "disabled";
1015 }; 637 };
1016 638
1017 uart2: serial@888000 639 uart2: serial@888000 {
1018 compatible = 640 compatible = "qcom,geni-uart";
1019 reg = <0 0x00 641 reg = <0 0x00888000 0 0x4000>;
1020 clock-names = 642 clock-names = "se";
1021 clocks = <&gc 643 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1022 pinctrl-names 644 pinctrl-names = "default";
1023 pinctrl-0 = < 645 pinctrl-0 = <&qup_uart2_default>;
1024 interrupts = 646 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1025 power-domains <<
1026 operating-poi <<
1027 interconnects <<
1028 <<
1029 interconnect- <<
1030 status = "dis 647 status = "disabled";
1031 }; 648 };
1032 649
1033 i2c3: i2c@88c000 { 650 i2c3: i2c@88c000 {
1034 compatible = 651 compatible = "qcom,geni-i2c";
1035 reg = <0 0x00 652 reg = <0 0x0088c000 0 0x4000>;
1036 clock-names = 653 clock-names = "se";
1037 clocks = <&gc 654 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1038 pinctrl-names 655 pinctrl-names = "default";
1039 pinctrl-0 = < 656 pinctrl-0 = <&qup_i2c3_default>;
1040 interrupts = 657 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1041 #address-cell 658 #address-cells = <1>;
1042 #size-cells = 659 #size-cells = <0>;
1043 interconnects <<
1044 <<
1045 <<
1046 interconnect- <<
1047 <<
1048 power-domains <<
1049 required-opps <<
1050 status = "dis 660 status = "disabled";
1051 }; 661 };
1052 662
1053 spi3: spi@88c000 { 663 spi3: spi@88c000 {
1054 compatible = 664 compatible = "qcom,geni-spi";
1055 reg = <0 0x00 665 reg = <0 0x0088c000 0 0x4000>;
1056 clock-names = 666 clock-names = "se";
1057 clocks = <&gc 667 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1058 pinctrl-names 668 pinctrl-names = "default";
1059 pinctrl-0 = < !! 669 pinctrl-0 = <&qup_spi3_default>;
1060 interrupts = 670 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1061 #address-cell 671 #address-cells = <1>;
1062 #size-cells = 672 #size-cells = <0>;
1063 power-domains <<
1064 operating-poi <<
1065 interconnects <<
1066 <<
1067 interconnect- <<
1068 status = "dis 673 status = "disabled";
1069 }; 674 };
1070 675
1071 uart3: serial@88c000 676 uart3: serial@88c000 {
1072 compatible = 677 compatible = "qcom,geni-uart";
1073 reg = <0 0x00 678 reg = <0 0x0088c000 0 0x4000>;
1074 clock-names = 679 clock-names = "se";
1075 clocks = <&gc 680 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1076 pinctrl-names 681 pinctrl-names = "default";
1077 pinctrl-0 = < 682 pinctrl-0 = <&qup_uart3_default>;
1078 interrupts = 683 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1079 power-domains <<
1080 operating-poi <<
1081 interconnects <<
1082 <<
1083 interconnect- <<
1084 status = "dis 684 status = "disabled";
1085 }; 685 };
1086 686
1087 i2c4: i2c@890000 { 687 i2c4: i2c@890000 {
1088 compatible = 688 compatible = "qcom,geni-i2c";
1089 reg = <0 0x00 689 reg = <0 0x00890000 0 0x4000>;
1090 clock-names = 690 clock-names = "se";
1091 clocks = <&gc 691 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1092 pinctrl-names 692 pinctrl-names = "default";
1093 pinctrl-0 = < 693 pinctrl-0 = <&qup_i2c4_default>;
1094 interrupts = 694 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1095 #address-cell 695 #address-cells = <1>;
1096 #size-cells = 696 #size-cells = <0>;
1097 interconnects <<
1098 <<
1099 <<
1100 interconnect- <<
1101 <<
1102 power-domains <<
1103 required-opps <<
1104 status = "dis 697 status = "disabled";
1105 }; 698 };
1106 699
1107 uart4: serial@890000 700 uart4: serial@890000 {
1108 compatible = 701 compatible = "qcom,geni-uart";
1109 reg = <0 0x00 702 reg = <0 0x00890000 0 0x4000>;
1110 clock-names = 703 clock-names = "se";
1111 clocks = <&gc 704 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1112 pinctrl-names 705 pinctrl-names = "default";
1113 pinctrl-0 = < 706 pinctrl-0 = <&qup_uart4_default>;
1114 interrupts = 707 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1115 power-domains <<
1116 operating-poi <<
1117 interconnects <<
1118 <<
1119 interconnect- <<
1120 status = "dis 708 status = "disabled";
1121 }; 709 };
1122 710
1123 i2c5: i2c@894000 { 711 i2c5: i2c@894000 {
1124 compatible = 712 compatible = "qcom,geni-i2c";
1125 reg = <0 0x00 713 reg = <0 0x00894000 0 0x4000>;
1126 clock-names = 714 clock-names = "se";
1127 clocks = <&gc 715 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1128 pinctrl-names 716 pinctrl-names = "default";
1129 pinctrl-0 = < 717 pinctrl-0 = <&qup_i2c5_default>;
1130 interrupts = 718 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1131 #address-cell 719 #address-cells = <1>;
1132 #size-cells = 720 #size-cells = <0>;
1133 interconnects <<
1134 <<
1135 <<
1136 interconnect- <<
1137 <<
1138 power-domains <<
1139 required-opps <<
1140 status = "dis 721 status = "disabled";
1141 }; 722 };
1142 723
1143 spi5: spi@894000 { 724 spi5: spi@894000 {
1144 compatible = 725 compatible = "qcom,geni-spi";
1145 reg = <0 0x00 726 reg = <0 0x00894000 0 0x4000>;
1146 clock-names = 727 clock-names = "se";
1147 clocks = <&gc 728 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1148 pinctrl-names 729 pinctrl-names = "default";
1149 pinctrl-0 = < !! 730 pinctrl-0 = <&qup_spi5_default>;
1150 interrupts = 731 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1151 #address-cell 732 #address-cells = <1>;
1152 #size-cells = 733 #size-cells = <0>;
1153 power-domains <<
1154 operating-poi <<
1155 interconnects <<
1156 <<
1157 interconnect- <<
1158 status = "dis 734 status = "disabled";
1159 }; 735 };
1160 736
1161 uart5: serial@894000 737 uart5: serial@894000 {
1162 compatible = 738 compatible = "qcom,geni-uart";
1163 reg = <0 0x00 739 reg = <0 0x00894000 0 0x4000>;
1164 clock-names = 740 clock-names = "se";
1165 clocks = <&gc 741 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1166 pinctrl-names 742 pinctrl-names = "default";
1167 pinctrl-0 = < 743 pinctrl-0 = <&qup_uart5_default>;
1168 interrupts = 744 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1169 power-domains <<
1170 operating-poi <<
1171 interconnects <<
1172 <<
1173 interconnect- <<
1174 status = "dis 745 status = "disabled";
1175 }; 746 };
1176 }; 747 };
1177 748
1178 qupv3_id_1: geniqup@ac0000 { 749 qupv3_id_1: geniqup@ac0000 {
1179 compatible = "qcom,ge 750 compatible = "qcom,geni-se-qup";
1180 reg = <0 0x00ac0000 0 751 reg = <0 0x00ac0000 0 0x6000>;
1181 clock-names = "m-ahb" 752 clock-names = "m-ahb", "s-ahb";
1182 clocks = <&gcc GCC_QU 753 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1183 <&gcc GCC_QU 754 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1184 #address-cells = <2>; 755 #address-cells = <2>;
1185 #size-cells = <2>; 756 #size-cells = <2>;
1186 ranges; 757 ranges;
1187 iommus = <&apps_smmu 758 iommus = <&apps_smmu 0x4c3 0x0>;
1188 status = "disabled"; 759 status = "disabled";
1189 760
1190 i2c6: i2c@a80000 { 761 i2c6: i2c@a80000 {
1191 compatible = 762 compatible = "qcom,geni-i2c";
1192 reg = <0 0x00 763 reg = <0 0x00a80000 0 0x4000>;
1193 clock-names = 764 clock-names = "se";
1194 clocks = <&gc 765 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1195 pinctrl-names 766 pinctrl-names = "default";
1196 pinctrl-0 = < 767 pinctrl-0 = <&qup_i2c6_default>;
1197 interrupts = 768 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1198 #address-cell 769 #address-cells = <1>;
1199 #size-cells = 770 #size-cells = <0>;
1200 interconnects <<
1201 <<
1202 <<
1203 interconnect- <<
1204 <<
1205 power-domains <<
1206 required-opps <<
1207 status = "dis 771 status = "disabled";
1208 }; 772 };
1209 773
1210 spi6: spi@a80000 { 774 spi6: spi@a80000 {
1211 compatible = 775 compatible = "qcom,geni-spi";
1212 reg = <0 0x00 776 reg = <0 0x00a80000 0 0x4000>;
1213 clock-names = 777 clock-names = "se";
1214 clocks = <&gc 778 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1215 pinctrl-names 779 pinctrl-names = "default";
1216 pinctrl-0 = < !! 780 pinctrl-0 = <&qup_spi6_default>;
1217 interrupts = 781 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1218 #address-cell 782 #address-cells = <1>;
1219 #size-cells = 783 #size-cells = <0>;
1220 power-domains <<
1221 operating-poi <<
1222 interconnects <<
1223 <<
1224 interconnect- <<
1225 status = "dis 784 status = "disabled";
1226 }; 785 };
1227 786
1228 uart6: serial@a80000 787 uart6: serial@a80000 {
1229 compatible = 788 compatible = "qcom,geni-uart";
1230 reg = <0 0x00 789 reg = <0 0x00a80000 0 0x4000>;
1231 clock-names = 790 clock-names = "se";
1232 clocks = <&gc 791 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1233 pinctrl-names 792 pinctrl-names = "default";
1234 pinctrl-0 = < 793 pinctrl-0 = <&qup_uart6_default>;
1235 interrupts = 794 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1236 power-domains <<
1237 operating-poi <<
1238 interconnects <<
1239 <<
1240 interconnect- <<
1241 status = "dis 795 status = "disabled";
1242 }; 796 };
1243 797
1244 i2c7: i2c@a84000 { 798 i2c7: i2c@a84000 {
1245 compatible = 799 compatible = "qcom,geni-i2c";
1246 reg = <0 0x00 800 reg = <0 0x00a84000 0 0x4000>;
1247 clock-names = 801 clock-names = "se";
1248 clocks = <&gc 802 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1249 pinctrl-names 803 pinctrl-names = "default";
1250 pinctrl-0 = < 804 pinctrl-0 = <&qup_i2c7_default>;
1251 interrupts = 805 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1252 #address-cell 806 #address-cells = <1>;
1253 #size-cells = 807 #size-cells = <0>;
1254 interconnects <<
1255 <<
1256 <<
1257 interconnect- <<
1258 <<
1259 power-domains <<
1260 required-opps <<
1261 status = "dis 808 status = "disabled";
1262 }; 809 };
1263 810
1264 uart7: serial@a84000 811 uart7: serial@a84000 {
1265 compatible = 812 compatible = "qcom,geni-uart";
1266 reg = <0 0x00 813 reg = <0 0x00a84000 0 0x4000>;
1267 clock-names = 814 clock-names = "se";
1268 clocks = <&gc 815 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1269 pinctrl-names 816 pinctrl-names = "default";
1270 pinctrl-0 = < 817 pinctrl-0 = <&qup_uart7_default>;
1271 interrupts = 818 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1272 power-domains <<
1273 operating-poi <<
1274 interconnects <<
1275 <<
1276 interconnect- <<
1277 status = "dis 819 status = "disabled";
1278 }; 820 };
1279 821
1280 i2c8: i2c@a88000 { 822 i2c8: i2c@a88000 {
1281 compatible = 823 compatible = "qcom,geni-i2c";
1282 reg = <0 0x00 824 reg = <0 0x00a88000 0 0x4000>;
1283 clock-names = 825 clock-names = "se";
1284 clocks = <&gc 826 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1285 pinctrl-names 827 pinctrl-names = "default";
1286 pinctrl-0 = < 828 pinctrl-0 = <&qup_i2c8_default>;
1287 interrupts = 829 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1288 #address-cell 830 #address-cells = <1>;
1289 #size-cells = 831 #size-cells = <0>;
1290 interconnects <<
1291 <<
1292 <<
1293 interconnect- <<
1294 <<
1295 power-domains <<
1296 required-opps <<
1297 status = "dis 832 status = "disabled";
1298 }; 833 };
1299 834
1300 spi8: spi@a88000 { 835 spi8: spi@a88000 {
1301 compatible = 836 compatible = "qcom,geni-spi";
1302 reg = <0 0x00 837 reg = <0 0x00a88000 0 0x4000>;
1303 clock-names = 838 clock-names = "se";
1304 clocks = <&gc 839 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1305 pinctrl-names 840 pinctrl-names = "default";
1306 pinctrl-0 = < !! 841 pinctrl-0 = <&qup_spi8_default>;
1307 interrupts = 842 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1308 #address-cell 843 #address-cells = <1>;
1309 #size-cells = 844 #size-cells = <0>;
1310 power-domains <<
1311 operating-poi <<
1312 interconnects <<
1313 <<
1314 interconnect- <<
1315 status = "dis 845 status = "disabled";
1316 }; 846 };
1317 847
1318 uart8: serial@a88000 848 uart8: serial@a88000 {
1319 compatible = 849 compatible = "qcom,geni-debug-uart";
1320 reg = <0 0x00 850 reg = <0 0x00a88000 0 0x4000>;
1321 clock-names = 851 clock-names = "se";
1322 clocks = <&gc 852 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1323 pinctrl-names 853 pinctrl-names = "default";
1324 pinctrl-0 = < 854 pinctrl-0 = <&qup_uart8_default>;
1325 interrupts = 855 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1326 power-domains <<
1327 operating-poi <<
1328 interconnects <<
1329 <<
1330 interconnect- <<
1331 status = "dis 856 status = "disabled";
1332 }; 857 };
1333 858
1334 i2c9: i2c@a8c000 { 859 i2c9: i2c@a8c000 {
1335 compatible = 860 compatible = "qcom,geni-i2c";
1336 reg = <0 0x00 861 reg = <0 0x00a8c000 0 0x4000>;
1337 clock-names = 862 clock-names = "se";
1338 clocks = <&gc 863 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1339 pinctrl-names 864 pinctrl-names = "default";
1340 pinctrl-0 = < 865 pinctrl-0 = <&qup_i2c9_default>;
1341 interrupts = 866 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1342 #address-cell 867 #address-cells = <1>;
1343 #size-cells = 868 #size-cells = <0>;
1344 interconnects <<
1345 <<
1346 <<
1347 interconnect- <<
1348 <<
1349 power-domains <<
1350 required-opps <<
1351 status = "dis 869 status = "disabled";
1352 }; 870 };
1353 871
1354 uart9: serial@a8c000 872 uart9: serial@a8c000 {
1355 compatible = 873 compatible = "qcom,geni-uart";
1356 reg = <0 0x00 874 reg = <0 0x00a8c000 0 0x4000>;
1357 clock-names = 875 clock-names = "se";
1358 clocks = <&gc 876 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1359 pinctrl-names 877 pinctrl-names = "default";
1360 pinctrl-0 = < 878 pinctrl-0 = <&qup_uart9_default>;
1361 interrupts = 879 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1362 power-domains <<
1363 operating-poi <<
1364 interconnects <<
1365 <<
1366 interconnect- <<
1367 status = "dis 880 status = "disabled";
1368 }; 881 };
1369 882
1370 i2c10: i2c@a90000 { 883 i2c10: i2c@a90000 {
1371 compatible = 884 compatible = "qcom,geni-i2c";
1372 reg = <0 0x00 885 reg = <0 0x00a90000 0 0x4000>;
1373 clock-names = 886 clock-names = "se";
1374 clocks = <&gc 887 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1375 pinctrl-names 888 pinctrl-names = "default";
1376 pinctrl-0 = < 889 pinctrl-0 = <&qup_i2c10_default>;
1377 interrupts = 890 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1378 #address-cell 891 #address-cells = <1>;
1379 #size-cells = 892 #size-cells = <0>;
1380 interconnects <<
1381 <<
1382 <<
1383 interconnect- <<
1384 <<
1385 power-domains <<
1386 required-opps <<
1387 status = "dis 893 status = "disabled";
1388 }; 894 };
1389 895
1390 spi10: spi@a90000 { 896 spi10: spi@a90000 {
1391 compatible = 897 compatible = "qcom,geni-spi";
1392 reg = <0 0x00 898 reg = <0 0x00a90000 0 0x4000>;
1393 clock-names = 899 clock-names = "se";
1394 clocks = <&gc 900 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1395 pinctrl-names 901 pinctrl-names = "default";
1396 pinctrl-0 = < !! 902 pinctrl-0 = <&qup_spi10_default>;
1397 interrupts = 903 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1398 #address-cell 904 #address-cells = <1>;
1399 #size-cells = 905 #size-cells = <0>;
1400 power-domains <<
1401 operating-poi <<
1402 interconnects <<
1403 <<
1404 interconnect- <<
1405 status = "dis 906 status = "disabled";
1406 }; 907 };
1407 908
1408 uart10: serial@a90000 909 uart10: serial@a90000 {
1409 compatible = 910 compatible = "qcom,geni-uart";
1410 reg = <0 0x00 911 reg = <0 0x00a90000 0 0x4000>;
1411 clock-names = 912 clock-names = "se";
1412 clocks = <&gc 913 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1413 pinctrl-names 914 pinctrl-names = "default";
1414 pinctrl-0 = < 915 pinctrl-0 = <&qup_uart10_default>;
1415 interrupts = 916 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1416 power-domains <<
1417 operating-poi <<
1418 interconnects <<
1419 <<
1420 interconnect- <<
1421 status = "dis 917 status = "disabled";
1422 }; 918 };
1423 919
1424 i2c11: i2c@a94000 { 920 i2c11: i2c@a94000 {
1425 compatible = 921 compatible = "qcom,geni-i2c";
1426 reg = <0 0x00 922 reg = <0 0x00a94000 0 0x4000>;
1427 clock-names = 923 clock-names = "se";
1428 clocks = <&gc 924 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1429 pinctrl-names 925 pinctrl-names = "default";
1430 pinctrl-0 = < 926 pinctrl-0 = <&qup_i2c11_default>;
1431 interrupts = 927 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1432 #address-cell 928 #address-cells = <1>;
1433 #size-cells = 929 #size-cells = <0>;
1434 interconnects <<
1435 <<
1436 <<
1437 interconnect- <<
1438 <<
1439 power-domains <<
1440 required-opps <<
1441 status = "dis 930 status = "disabled";
1442 }; 931 };
1443 932
1444 spi11: spi@a94000 { 933 spi11: spi@a94000 {
1445 compatible = 934 compatible = "qcom,geni-spi";
1446 reg = <0 0x00 935 reg = <0 0x00a94000 0 0x4000>;
1447 clock-names = 936 clock-names = "se";
1448 clocks = <&gc 937 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1449 pinctrl-names 938 pinctrl-names = "default";
1450 pinctrl-0 = < !! 939 pinctrl-0 = <&qup_spi11_default>;
1451 interrupts = 940 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1452 #address-cell 941 #address-cells = <1>;
1453 #size-cells = 942 #size-cells = <0>;
1454 power-domains <<
1455 operating-poi <<
1456 interconnects <<
1457 <<
1458 interconnect- <<
1459 status = "dis 943 status = "disabled";
1460 }; 944 };
1461 945
1462 uart11: serial@a94000 946 uart11: serial@a94000 {
1463 compatible = 947 compatible = "qcom,geni-uart";
1464 reg = <0 0x00 948 reg = <0 0x00a94000 0 0x4000>;
1465 clock-names = 949 clock-names = "se";
1466 clocks = <&gc 950 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1467 pinctrl-names 951 pinctrl-names = "default";
1468 pinctrl-0 = < 952 pinctrl-0 = <&qup_uart11_default>;
1469 interrupts = 953 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1470 power-domains <<
1471 operating-poi <<
1472 interconnects <<
1473 <<
1474 interconnect- <<
1475 status = "dis 954 status = "disabled";
1476 }; 955 };
1477 }; 956 };
1478 957
1479 config_noc: interconnect@1500 958 config_noc: interconnect@1500000 {
1480 compatible = "qcom,sc 959 compatible = "qcom,sc7180-config-noc";
1481 reg = <0 0x01500000 0 960 reg = <0 0x01500000 0 0x28000>;
1482 #interconnect-cells = !! 961 #interconnect-cells = <1>;
1483 qcom,bcm-voters = <&a 962 qcom,bcm-voters = <&apps_bcm_voter>;
1484 }; 963 };
1485 964
1486 system_noc: interconnect@1620 965 system_noc: interconnect@1620000 {
1487 compatible = "qcom,sc 966 compatible = "qcom,sc7180-system-noc";
1488 reg = <0 0x01620000 0 967 reg = <0 0x01620000 0 0x17080>;
1489 #interconnect-cells = !! 968 #interconnect-cells = <1>;
1490 qcom,bcm-voters = <&a 969 qcom,bcm-voters = <&apps_bcm_voter>;
1491 }; 970 };
1492 971
1493 mc_virt: interconnect@1638000 972 mc_virt: interconnect@1638000 {
1494 compatible = "qcom,sc 973 compatible = "qcom,sc7180-mc-virt";
1495 reg = <0 0x01638000 0 974 reg = <0 0x01638000 0 0x1000>;
1496 #interconnect-cells = !! 975 #interconnect-cells = <1>;
1497 qcom,bcm-voters = <&a 976 qcom,bcm-voters = <&apps_bcm_voter>;
1498 }; 977 };
1499 978
1500 qup_virt: interconnect@165000 979 qup_virt: interconnect@1650000 {
1501 compatible = "qcom,sc 980 compatible = "qcom,sc7180-qup-virt";
1502 reg = <0 0x01650000 0 981 reg = <0 0x01650000 0 0x1000>;
1503 #interconnect-cells = !! 982 #interconnect-cells = <1>;
1504 qcom,bcm-voters = <&a 983 qcom,bcm-voters = <&apps_bcm_voter>;
1505 }; 984 };
1506 985
1507 aggre1_noc: interconnect@16e0 986 aggre1_noc: interconnect@16e0000 {
1508 compatible = "qcom,sc 987 compatible = "qcom,sc7180-aggre1-noc";
1509 reg = <0 0x016e0000 0 988 reg = <0 0x016e0000 0 0x15080>;
1510 #interconnect-cells = !! 989 #interconnect-cells = <1>;
1511 qcom,bcm-voters = <&a 990 qcom,bcm-voters = <&apps_bcm_voter>;
1512 }; 991 };
1513 992
1514 aggre2_noc: interconnect@1705 993 aggre2_noc: interconnect@1705000 {
1515 compatible = "qcom,sc 994 compatible = "qcom,sc7180-aggre2-noc";
1516 reg = <0 0x01705000 0 995 reg = <0 0x01705000 0 0x9000>;
1517 #interconnect-cells = !! 996 #interconnect-cells = <1>;
1518 qcom,bcm-voters = <&a 997 qcom,bcm-voters = <&apps_bcm_voter>;
1519 }; 998 };
1520 999
1521 compute_noc: interconnect@170 1000 compute_noc: interconnect@170e000 {
1522 compatible = "qcom,sc 1001 compatible = "qcom,sc7180-compute-noc";
1523 reg = <0 0x0170e000 0 1002 reg = <0 0x0170e000 0 0x6000>;
1524 #interconnect-cells = !! 1003 #interconnect-cells = <1>;
1525 qcom,bcm-voters = <&a 1004 qcom,bcm-voters = <&apps_bcm_voter>;
1526 }; 1005 };
1527 1006
1528 mmss_noc: interconnect@174000 1007 mmss_noc: interconnect@1740000 {
1529 compatible = "qcom,sc 1008 compatible = "qcom,sc7180-mmss-noc";
1530 reg = <0 0x01740000 0 1009 reg = <0 0x01740000 0 0x1c100>;
1531 #interconnect-cells = !! 1010 #interconnect-cells = <1>;
1532 qcom,bcm-voters = <&a 1011 qcom,bcm-voters = <&apps_bcm_voter>;
1533 }; 1012 };
1534 1013
1535 ufs_mem_hc: ufshc@1d84000 { !! 1014 ipa_virt: interconnect@1e00000 {
1536 compatible = "qcom,sc !! 1015 compatible = "qcom,sc7180-ipa-virt";
1537 "jedec,u !! 1016 reg = <0 0x01e00000 0 0x1000>;
1538 reg = <0 0x01d84000 0 !! 1017 #interconnect-cells = <1>;
1539 interrupts = <GIC_SPI !! 1018 qcom,bcm-voters = <&apps_bcm_voter>;
1540 phys = <&ufs_mem_phy> <<
1541 phy-names = "ufsphy"; <<
1542 lanes-per-direction = <<
1543 #reset-cells = <1>; <<
1544 resets = <&gcc GCC_UF <<
1545 reset-names = "rst"; <<
1546 <<
1547 power-domains = <&gcc <<
1548 <<
1549 iommus = <&apps_smmu <<
1550 <<
1551 clock-names = "core_c <<
1552 "bus_ag <<
1553 "iface_ <<
1554 "core_c <<
1555 "ref_cl <<
1556 "tx_lan <<
1557 "rx_lan <<
1558 clocks = <&gcc GCC_UF <<
1559 <&gcc GCC_AG <<
1560 <&gcc GCC_UF <<
1561 <&gcc GCC_UF <<
1562 <&rpmhcc RPM <<
1563 <&gcc GCC_UF <<
1564 <&gcc GCC_UF <<
1565 freq-table-hz = <5000 <<
1566 <0 0> <<
1567 <0 0> <<
1568 <3750 <<
1569 <0 0> <<
1570 <0 0> <<
1571 <0 0> <<
1572 <<
1573 interconnects = <&agg <<
1574 &mc_ <<
1575 <&gem <<
1576 &con <<
1577 interconnect-names = <<
1578 <<
1579 qcom,ice = <&ice>; <<
1580 <<
1581 status = "disabled"; <<
1582 }; <<
1583 <<
1584 ufs_mem_phy: phy@1d87000 { <<
1585 compatible = "qcom,sc <<
1586 reg = <0 0x01d87000 0 <<
1587 clocks = <&rpmhcc RPM <<
1588 <&gcc GCC_UF <<
1589 <&gcc GCC_UF <<
1590 clock-names = "ref", <<
1591 "ref_au <<
1592 "qref"; <<
1593 power-domains = <&gcc <<
1594 resets = <&ufs_mem_hc <<
1595 reset-names = "ufsphy <<
1596 #phy-cells = <0>; <<
1597 status = "disabled"; <<
1598 }; <<
1599 <<
1600 ice: crypto@1d90000 { <<
1601 compatible = "qcom,sc <<
1602 "qcom,in <<
1603 reg = <0 0x01d90000 0 <<
1604 clocks = <&gcc GCC_UF <<
1605 }; 1019 };
1606 1020
1607 ipa: ipa@1e40000 { 1021 ipa: ipa@1e40000 {
1608 compatible = "qcom,sc 1022 compatible = "qcom,sc7180-ipa";
1609 1023
1610 iommus = <&apps_smmu !! 1024 iommus = <&apps_smmu 0x440 0x3>;
1611 <&apps_smmu !! 1025 reg = <0 0x1e40000 0 0x7000>,
1612 reg = <0 0x01e40000 0 !! 1026 <0 0x1e47000 0 0x2000>,
1613 <0 0x01e47000 0 !! 1027 <0 0x1e04000 0 0x2c000>;
1614 <0 0x01e04000 0 <<
1615 reg-names = "ipa-reg" 1028 reg-names = "ipa-reg",
1616 "ipa-shar 1029 "ipa-shared",
1617 "gsi"; 1030 "gsi";
1618 1031
1619 interrupts-extended = !! 1032 interrupts-extended = <&intc 0 311 IRQ_TYPE_EDGE_RISING>,
1620 !! 1033 <&intc 0 432 IRQ_TYPE_LEVEL_HIGH>,
1621 1034 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1622 1035 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
1623 interrupt-names = "ip 1036 interrupt-names = "ipa",
1624 "gs 1037 "gsi",
1625 "ip 1038 "ipa-clock-query",
1626 "ip 1039 "ipa-setup-ready";
1627 1040
1628 clocks = <&rpmhcc RPM 1041 clocks = <&rpmhcc RPMH_IPA_CLK>;
1629 clock-names = "core"; 1042 clock-names = "core";
1630 1043
1631 interconnects = <&agg !! 1044 interconnects = <&aggre2_noc MASTER_IPA &mc_virt SLAVE_EBI1>,
1632 <&agg !! 1045 <&aggre2_noc MASTER_IPA &system_noc SLAVE_IMEM>,
1633 <&gem !! 1046 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_IPA_CFG>;
1634 interconnect-names = 1047 interconnect-names = "memory",
1635 1048 "imem",
1636 1049 "config";
1637 1050
1638 qcom,qmp = <&aoss_qmp <<
1639 <<
1640 qcom,smem-states = <& 1051 qcom,smem-states = <&ipa_smp2p_out 0>,
1641 <& 1052 <&ipa_smp2p_out 1>;
1642 qcom,smem-state-names 1053 qcom,smem-state-names = "ipa-clock-enabled-valid",
1643 1054 "ipa-clock-enabled";
1644 1055
1645 status = "disabled"; !! 1056 modem-remoteproc = <&remoteproc_mpss>;
1646 }; <<
1647 1057
1648 tcsr_mutex: hwlock@1f40000 { !! 1058 status = "disabled";
1649 compatible = "qcom,tc <<
1650 reg = <0 0x01f40000 0 <<
1651 #hwlock-cells = <1>; <<
1652 }; 1059 };
1653 1060
1654 tcsr_regs_1: syscon@1f60000 { !! 1061 tcsr_mutex_regs: syscon@1f40000 {
1655 compatible = "qcom,sc !! 1062 compatible = "syscon";
1656 reg = <0 0x01f60000 0 !! 1063 reg = <0 0x01f40000 0 0x40000>;
1657 }; 1064 };
1658 1065
1659 tcsr_regs_2: syscon@1fc0000 { !! 1066 tcsr_regs: syscon@1fc0000 {
1660 compatible = "qcom,sc !! 1067 compatible = "syscon";
1661 reg = <0 0x01fc0000 0 1068 reg = <0 0x01fc0000 0 0x40000>;
1662 }; 1069 };
1663 1070
1664 tlmm: pinctrl@3500000 { 1071 tlmm: pinctrl@3500000 {
1665 compatible = "qcom,sc 1072 compatible = "qcom,sc7180-pinctrl";
1666 reg = <0 0x03500000 0 1073 reg = <0 0x03500000 0 0x300000>,
1667 <0 0x03900000 0 1074 <0 0x03900000 0 0x300000>,
1668 <0 0x03d00000 0 1075 <0 0x03d00000 0 0x300000>;
1669 reg-names = "west", " 1076 reg-names = "west", "north", "south";
1670 interrupts = <GIC_SPI 1077 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1671 gpio-controller; 1078 gpio-controller;
1672 #gpio-cells = <2>; 1079 #gpio-cells = <2>;
1673 interrupt-controller; 1080 interrupt-controller;
1674 #interrupt-cells = <2 1081 #interrupt-cells = <2>;
1675 gpio-ranges = <&tlmm 1082 gpio-ranges = <&tlmm 0 0 120>;
1676 wakeup-parent = <&pdc 1083 wakeup-parent = <&pdc>;
1677 1084
1678 dp_hot_plug_det: dp-h !! 1085 qspi_clk: qspi-clk {
1679 pins = "gpio1 !! 1086 pinmux {
1680 function = "d !! 1087 pins = "gpio63";
1681 }; !! 1088 function = "qspi_clk";
1682 !! 1089 };
1683 qspi_clk: qspi-clk-st <<
1684 pins = "gpio6 <<
1685 function = "q <<
1686 }; <<
1687 <<
1688 qspi_cs0: qspi-cs0-st <<
1689 pins = "gpio6 <<
1690 function = "q <<
1691 }; <<
1692 <<
1693 qspi_cs1: qspi-cs1-st <<
1694 pins = "gpio7 <<
1695 function = "q <<
1696 }; <<
1697 <<
1698 qspi_data0: qspi-data <<
1699 pins = "gpio6 <<
1700 function = "q <<
1701 }; <<
1702 <<
1703 qspi_data1: qspi-data <<
1704 pins = "gpio6 <<
1705 function = "q <<
1706 }; <<
1707 <<
1708 qspi_data23: qspi-dat <<
1709 pins = "gpio6 <<
1710 function = "q <<
1711 }; <<
1712 <<
1713 qup_i2c0_default: qup <<
1714 pins = "gpio3 <<
1715 function = "q <<
1716 }; <<
1717 <<
1718 qup_i2c1_default: qup <<
1719 pins = "gpio0 <<
1720 function = "q <<
1721 }; <<
1722 <<
1723 qup_i2c2_default: qup <<
1724 pins = "gpio1 <<
1725 function = "q <<
1726 }; <<
1727 <<
1728 qup_i2c3_default: qup <<
1729 pins = "gpio3 <<
1730 function = "q <<
1731 }; <<
1732 <<
1733 qup_i2c4_default: qup <<
1734 pins = "gpio1 <<
1735 function = "q <<
1736 }; <<
1737 <<
1738 qup_i2c5_default: qup <<
1739 pins = "gpio2 <<
1740 function = "q <<
1741 }; <<
1742 <<
1743 qup_i2c6_default: qup <<
1744 pins = "gpio5 <<
1745 function = "q <<
1746 }; <<
1747 <<
1748 qup_i2c7_default: qup <<
1749 pins = "gpio6 <<
1750 function = "q <<
1751 }; <<
1752 <<
1753 qup_i2c8_default: qup <<
1754 pins = "gpio4 <<
1755 function = "q <<
1756 }; <<
1757 <<
1758 qup_i2c9_default: qup <<
1759 pins = "gpio4 <<
1760 function = "q <<
1761 }; <<
1762 <<
1763 qup_i2c10_default: qu <<
1764 pins = "gpio8 <<
1765 function = "q <<
1766 }; <<
1767 <<
1768 qup_i2c11_default: qu <<
1769 pins = "gpio5 <<
1770 function = "q <<
1771 }; <<
1772 <<
1773 qup_spi0_spi: qup-spi <<
1774 pins = "gpio3 <<
1775 function = "q <<
1776 }; <<
1777 <<
1778 qup_spi0_cs: qup-spi0 <<
1779 pins = "gpio3 <<
1780 function = "q <<
1781 }; <<
1782 <<
1783 qup_spi0_cs_gpio: qup <<
1784 pins = "gpio3 <<
1785 function = "g <<
1786 }; 1090 };
1787 1091
1788 qup_spi1_spi: qup-spi !! 1092 qspi_cs0: qspi-cs0 {
1789 pins = "gpio0 !! 1093 pinmux {
1790 function = "q !! 1094 pins = "gpio68";
>> 1095 function = "qspi_cs";
>> 1096 };
1791 }; 1097 };
1792 1098
1793 qup_spi1_cs: qup-spi1 !! 1099 qspi_cs1: qspi-cs1 {
1794 pins = "gpio3 !! 1100 pinmux {
1795 function = "q !! 1101 pins = "gpio72";
>> 1102 function = "qspi_cs";
>> 1103 };
1796 }; 1104 };
1797 1105
1798 qup_spi1_cs_gpio: qup !! 1106 qspi_data01: qspi-data01 {
1799 pins = "gpio3 !! 1107 pinmux-data {
1800 function = "g !! 1108 pins = "gpio64", "gpio65";
>> 1109 function = "qspi_data";
>> 1110 };
1801 }; 1111 };
1802 1112
1803 qup_spi3_spi: qup-spi !! 1113 qspi_data12: qspi-data12 {
1804 pins = "gpio3 !! 1114 pinmux-data {
1805 function = "q !! 1115 pins = "gpio66", "gpio67";
>> 1116 function = "qspi_data";
>> 1117 };
1806 }; 1118 };
1807 1119
1808 qup_spi3_cs: qup-spi3 !! 1120 qup_i2c0_default: qup-i2c0-default {
1809 pins = "gpio4 !! 1121 pinmux {
1810 function = "q !! 1122 pins = "gpio34", "gpio35";
>> 1123 function = "qup00";
>> 1124 };
1811 }; 1125 };
1812 1126
1813 qup_spi3_cs_gpio: qup !! 1127 qup_i2c1_default: qup-i2c1-default {
1814 pins = "gpio4 !! 1128 pinmux {
1815 function = "g !! 1129 pins = "gpio0", "gpio1";
>> 1130 function = "qup01";
>> 1131 };
1816 }; 1132 };
1817 1133
1818 qup_spi5_spi: qup-spi !! 1134 qup_i2c2_default: qup-i2c2-default {
1819 pins = "gpio2 !! 1135 pinmux {
1820 function = "q !! 1136 pins = "gpio15", "gpio16";
>> 1137 function = "qup02_i2c";
>> 1138 };
1821 }; 1139 };
1822 1140
1823 qup_spi5_cs: qup-spi5 !! 1141 qup_i2c3_default: qup-i2c3-default {
1824 pins = "gpio2 !! 1142 pinmux {
1825 function = "q !! 1143 pins = "gpio38", "gpio39";
>> 1144 function = "qup03";
>> 1145 };
1826 }; 1146 };
1827 1147
1828 qup_spi5_cs_gpio: qup !! 1148 qup_i2c4_default: qup-i2c4-default {
1829 pins = "gpio2 !! 1149 pinmux {
1830 function = "g !! 1150 pins = "gpio115", "gpio116";
>> 1151 function = "qup04_i2c";
>> 1152 };
1831 }; 1153 };
1832 1154
1833 qup_spi6_spi: qup-spi !! 1155 qup_i2c5_default: qup-i2c5-default {
1834 pins = "gpio5 !! 1156 pinmux {
1835 function = "q !! 1157 pins = "gpio25", "gpio26";
>> 1158 function = "qup05";
>> 1159 };
1836 }; 1160 };
1837 1161
1838 qup_spi6_cs: qup-spi6 !! 1162 qup_i2c6_default: qup-i2c6-default {
1839 pins = "gpio6 !! 1163 pinmux {
1840 function = "q !! 1164 pins = "gpio59", "gpio60";
>> 1165 function = "qup10";
>> 1166 };
1841 }; 1167 };
1842 1168
1843 qup_spi6_cs_gpio: qup !! 1169 qup_i2c7_default: qup-i2c7-default {
1844 pins = "gpio6 !! 1170 pinmux {
1845 function = "g !! 1171 pins = "gpio6", "gpio7";
>> 1172 function = "qup11_i2c";
>> 1173 };
1846 }; 1174 };
1847 1175
1848 qup_spi8_spi: qup-spi !! 1176 qup_i2c8_default: qup-i2c8-default {
1849 pins = "gpio4 !! 1177 pinmux {
1850 function = "q !! 1178 pins = "gpio42", "gpio43";
>> 1179 function = "qup12";
>> 1180 };
1851 }; 1181 };
1852 1182
1853 qup_spi8_cs: qup-spi8 !! 1183 qup_i2c9_default: qup-i2c9-default {
1854 pins = "gpio4 !! 1184 pinmux {
1855 function = "q !! 1185 pins = "gpio46", "gpio47";
>> 1186 function = "qup13_i2c";
>> 1187 };
1856 }; 1188 };
1857 1189
1858 qup_spi8_cs_gpio: qup !! 1190 qup_i2c10_default: qup-i2c10-default {
1859 pins = "gpio4 !! 1191 pinmux {
1860 function = "g !! 1192 pins = "gpio86", "gpio87";
>> 1193 function = "qup14";
>> 1194 };
1861 }; 1195 };
1862 1196
1863 qup_spi10_spi: qup-sp !! 1197 qup_i2c11_default: qup-i2c11-default {
1864 pins = "gpio8 !! 1198 pinmux {
1865 function = "q !! 1199 pins = "gpio53", "gpio54";
>> 1200 function = "qup15";
>> 1201 };
1866 }; 1202 };
1867 1203
1868 qup_spi10_cs: qup-spi !! 1204 qup_spi0_default: qup-spi0-default {
1869 pins = "gpio8 !! 1205 pinmux {
1870 function = "q !! 1206 pins = "gpio34", "gpio35",
>> 1207 "gpio36", "gpio37";
>> 1208 function = "qup00";
>> 1209 };
1871 }; 1210 };
1872 1211
1873 qup_spi10_cs_gpio: qu !! 1212 qup_spi1_default: qup-spi1-default {
1874 pins = "gpio8 !! 1213 pinmux {
1875 function = "g !! 1214 pins = "gpio0", "gpio1",
>> 1215 "gpio2", "gpio3";
>> 1216 function = "qup01";
>> 1217 };
1876 }; 1218 };
1877 1219
1878 qup_spi11_spi: qup-sp !! 1220 qup_spi3_default: qup-spi3-default {
1879 pins = "gpio5 !! 1221 pinmux {
1880 function = "q !! 1222 pins = "gpio38", "gpio39",
>> 1223 "gpio40", "gpio41";
>> 1224 function = "qup03";
>> 1225 };
1881 }; 1226 };
1882 1227
1883 qup_spi11_cs: qup-spi !! 1228 qup_spi5_default: qup-spi5-default {
1884 pins = "gpio5 !! 1229 pinmux {
1885 function = "q !! 1230 pins = "gpio25", "gpio26",
>> 1231 "gpio27", "gpio28";
>> 1232 function = "qup05";
>> 1233 };
1886 }; 1234 };
1887 1235
1888 qup_spi11_cs_gpio: qu !! 1236 qup_spi6_default: qup-spi6-default {
1889 pins = "gpio5 !! 1237 pinmux {
1890 function = "g !! 1238 pins = "gpio59", "gpio60",
>> 1239 "gpio61", "gpio62";
>> 1240 function = "qup10";
>> 1241 };
1891 }; 1242 };
1892 1243
1893 qup_uart0_default: qu !! 1244 qup_spi8_default: qup-spi8-default {
1894 qup_uart0_cts !! 1245 pinmux {
1895 pins !! 1246 pins = "gpio42", "gpio43",
1896 funct !! 1247 "gpio44", "gpio45";
>> 1248 function = "qup12";
1897 }; 1249 };
>> 1250 };
1898 1251
1899 qup_uart0_rts !! 1252 qup_spi10_default: qup-spi10-default {
1900 pins !! 1253 pinmux {
1901 funct !! 1254 pins = "gpio86", "gpio87",
>> 1255 "gpio88", "gpio89";
>> 1256 function = "qup14";
1902 }; 1257 };
>> 1258 };
1903 1259
1904 qup_uart0_tx: !! 1260 qup_spi11_default: qup-spi11-default {
1905 pins !! 1261 pinmux {
1906 funct !! 1262 pins = "gpio53", "gpio54",
>> 1263 "gpio55", "gpio56";
>> 1264 function = "qup15";
1907 }; 1265 };
>> 1266 };
1908 1267
1909 qup_uart0_rx: !! 1268 qup_uart0_default: qup-uart0-default {
1910 pins !! 1269 pinmux {
>> 1270 pins = "gpio34", "gpio35",
>> 1271 "gpio36", "gpio37";
1911 funct 1272 function = "qup00";
1912 }; 1273 };
1913 }; 1274 };
1914 1275
1915 qup_uart1_default: qu !! 1276 qup_uart1_default: qup-uart1-default {
1916 qup_uart1_cts !! 1277 pinmux {
1917 pins !! 1278 pins = "gpio0", "gpio1",
1918 funct !! 1279 "gpio2", "gpio3";
1919 }; <<
1920 <<
1921 qup_uart1_rts <<
1922 pins <<
1923 funct <<
1924 }; <<
1925 <<
1926 qup_uart1_tx: <<
1927 pins <<
1928 funct <<
1929 }; <<
1930 <<
1931 qup_uart1_rx: <<
1932 pins <<
1933 funct 1280 function = "qup01";
1934 }; 1281 };
1935 }; 1282 };
1936 1283
1937 qup_uart2_default: qu !! 1284 qup_uart2_default: qup-uart2-default {
1938 qup_uart2_tx: !! 1285 pinmux {
1939 pins !! 1286 pins = "gpio15", "gpio16";
1940 funct <<
1941 }; <<
1942 <<
1943 qup_uart2_rx: <<
1944 pins <<
1945 funct 1287 function = "qup02_uart";
1946 }; 1288 };
1947 }; 1289 };
1948 1290
1949 qup_uart3_default: qu !! 1291 qup_uart3_default: qup-uart3-default {
1950 qup_uart3_cts !! 1292 pinmux {
1951 pins !! 1293 pins = "gpio38", "gpio39",
1952 funct !! 1294 "gpio40", "gpio41";
1953 }; <<
1954 <<
1955 qup_uart3_rts <<
1956 pins <<
1957 funct <<
1958 }; <<
1959 <<
1960 qup_uart3_tx: <<
1961 pins <<
1962 funct <<
1963 }; <<
1964 <<
1965 qup_uart3_rx: <<
1966 pins <<
1967 funct 1295 function = "qup03";
1968 }; 1296 };
1969 }; 1297 };
1970 1298
1971 qup_uart4_default: qu !! 1299 qup_uart4_default: qup-uart4-default {
1972 qup_uart4_tx: !! 1300 pinmux {
1973 pins !! 1301 pins = "gpio115", "gpio116";
1974 funct <<
1975 }; <<
1976 <<
1977 qup_uart4_rx: <<
1978 pins <<
1979 funct 1302 function = "qup04_uart";
1980 }; 1303 };
1981 }; 1304 };
1982 1305
1983 qup_uart5_default: qu !! 1306 qup_uart5_default: qup-uart5-default {
1984 qup_uart5_cts !! 1307 pinmux {
1985 pins !! 1308 pins = "gpio25", "gpio26",
1986 funct !! 1309 "gpio27", "gpio28";
1987 }; <<
1988 <<
1989 qup_uart5_rts <<
1990 pins <<
1991 funct <<
1992 }; <<
1993 <<
1994 qup_uart5_tx: <<
1995 pins <<
1996 funct <<
1997 }; <<
1998 <<
1999 qup_uart5_rx: <<
2000 pins <<
2001 funct 1310 function = "qup05";
2002 }; 1311 };
2003 }; 1312 };
2004 1313
2005 qup_uart6_default: qu !! 1314 qup_uart6_default: qup-uart6-default {
2006 qup_uart6_cts !! 1315 pinmux {
2007 pins !! 1316 pins = "gpio59", "gpio60",
2008 funct !! 1317 "gpio61", "gpio62";
2009 }; <<
2010 <<
2011 qup_uart6_rts <<
2012 pins <<
2013 funct <<
2014 }; <<
2015 <<
2016 qup_uart6_tx: <<
2017 pins <<
2018 funct <<
2019 }; <<
2020 <<
2021 qup_uart6_rx: <<
2022 pins <<
2023 funct 1318 function = "qup10";
2024 }; 1319 };
2025 }; 1320 };
2026 1321
2027 qup_uart7_default: qu !! 1322 qup_uart7_default: qup-uart7-default {
2028 qup_uart7_tx: !! 1323 pinmux {
2029 pins !! 1324 pins = "gpio6", "gpio7";
2030 funct <<
2031 }; <<
2032 <<
2033 qup_uart7_rx: <<
2034 pins <<
2035 funct 1325 function = "qup11_uart";
2036 }; 1326 };
2037 }; 1327 };
2038 1328
2039 qup_uart8_default: qu !! 1329 qup_uart8_default: qup-uart8-default {
2040 qup_uart8_tx: !! 1330 pinmux {
2041 pins !! 1331 pins = "gpio44", "gpio45";
2042 funct 1332 function = "qup12";
2043 }; 1333 };
>> 1334 };
2044 1335
2045 qup_uart8_rx: !! 1336 qup_uart9_default: qup-uart9-default {
2046 pins !! 1337 pinmux {
2047 funct !! 1338 pins = "gpio46", "gpio47";
>> 1339 function = "qup13_uart";
2048 }; 1340 };
2049 }; 1341 };
2050 1342
2051 qup_uart9_default: qu !! 1343 qup_uart10_default: qup-uart10-default {
2052 qup_uart9_tx: !! 1344 pinmux {
2053 pins !! 1345 pins = "gpio86", "gpio87",
2054 funct !! 1346 "gpio88", "gpio89";
>> 1347 function = "qup14";
2055 }; 1348 };
>> 1349 };
2056 1350
2057 qup_uart9_rx: !! 1351 qup_uart11_default: qup-uart11-default {
2058 pins !! 1352 pinmux {
2059 funct !! 1353 pins = "gpio53", "gpio54",
>> 1354 "gpio55", "gpio56";
>> 1355 function = "qup15";
2060 }; 1356 };
2061 }; 1357 };
2062 1358
2063 qup_uart10_default: q !! 1359 sdc1_on: sdc1-on {
2064 qup_uart10_ct !! 1360 pinconf-clk {
2065 pins !! 1361 pins = "sdc1_clk";
2066 funct !! 1362 bias-disable;
>> 1363 drive-strength = <16>;
2067 }; 1364 };
2068 1365
2069 qup_uart10_rt !! 1366 pinconf-cmd {
2070 pins !! 1367 pins = "sdc1_cmd";
2071 funct !! 1368 bias-pull-up;
>> 1369 drive-strength = <10>;
2072 }; 1370 };
2073 1371
2074 qup_uart10_tx !! 1372 pinconf-data {
2075 pins !! 1373 pins = "sdc1_data";
2076 funct !! 1374 bias-pull-up;
>> 1375 drive-strength = <10>;
2077 }; 1376 };
2078 1377
2079 qup_uart10_rx !! 1378 pinconf-rclk {
2080 pins !! 1379 pins = "sdc1_rclk";
2081 funct !! 1380 bias-pull-down;
2082 }; 1381 };
2083 }; 1382 };
2084 1383
2085 qup_uart11_default: q !! 1384 sdc1_off: sdc1-off {
2086 qup_uart11_ct !! 1385 pinconf-clk {
2087 pins !! 1386 pins = "sdc1_clk";
2088 funct !! 1387 bias-disable;
>> 1388 drive-strength = <2>;
2089 }; 1389 };
2090 1390
2091 qup_uart11_rt !! 1391 pinconf-cmd {
2092 pins !! 1392 pins = "sdc1_cmd";
2093 funct !! 1393 bias-pull-up;
>> 1394 drive-strength = <2>;
2094 }; 1395 };
2095 1396
2096 qup_uart11_tx !! 1397 pinconf-data {
2097 pins !! 1398 pins = "sdc1_data";
2098 funct !! 1399 bias-pull-up;
>> 1400 drive-strength = <2>;
2099 }; 1401 };
2100 1402
2101 qup_uart11_rx !! 1403 pinconf-rclk {
2102 pins !! 1404 pins = "sdc1_rclk";
2103 funct !! 1405 bias-pull-down;
2104 }; 1406 };
2105 }; 1407 };
2106 1408
2107 sec_mi2s_active: sec- !! 1409 sdc2_on: sdc2-on {
2108 pins = "gpio4 !! 1410 pinconf-clk {
2109 function = "m !! 1411 pins = "sdc2_clk";
2110 }; !! 1412 bias-disable;
>> 1413 drive-strength = <16>;
>> 1414 };
2111 1415
2112 pri_mi2s_active: pri- !! 1416 pinconf-cmd {
2113 pins = "gpio5 !! 1417 pins = "sdc2_cmd";
2114 function = "m !! 1418 bias-pull-up;
2115 }; !! 1419 drive-strength = <10>;
>> 1420 };
2116 1421
2117 pri_mi2s_mclk_active: !! 1422 pinconf-data {
2118 pins = "gpio5 !! 1423 pins = "sdc2_data";
2119 function = "l !! 1424 bias-pull-up;
2120 }; !! 1425 drive-strength = <10>;
>> 1426 };
2121 1427
2122 ter_mi2s_active: ter- !! 1428 pinconf-sd-cd {
2123 pins = "gpio6 !! 1429 pins = "gpio69";
2124 function = "m !! 1430 bias-pull-up;
>> 1431 drive-strength = <2>;
>> 1432 };
2125 }; 1433 };
2126 }; <<
2127 <<
2128 remoteproc_mpss: remoteproc@4 <<
2129 compatible = "qcom,sc <<
2130 reg = <0 0x04080000 0 <<
2131 <<
2132 interrupts-extended = <<
2133 <<
2134 <<
2135 <<
2136 <<
2137 <<
2138 interrupt-names = "wd <<
2139 "st <<
2140 1434
2141 clocks = <&rpmhcc RPM !! 1435 sdc2_off: sdc2-off {
2142 clock-names = "xo"; !! 1436 pinconf-clk {
2143 !! 1437 pins = "sdc2_clk";
2144 power-domains = <&rpm !! 1438 bias-disable;
2145 <&rpm !! 1439 drive-strength = <2>;
2146 <&rpm !! 1440 };
2147 power-domain-names = <<
2148 <<
2149 memory-region = <&mps <<
2150 <<
2151 qcom,qmp = <&aoss_qmp <<
2152 1441
2153 qcom,smem-states = <& !! 1442 pinconf-cmd {
2154 qcom,smem-state-names !! 1443 pins = "sdc2_cmd";
>> 1444 bias-pull-up;
>> 1445 drive-strength = <2>;
>> 1446 };
2155 1447
2156 status = "disabled"; !! 1448 pinconf-data {
>> 1449 pins = "sdc2_data";
>> 1450 bias-pull-up;
>> 1451 drive-strength = <2>;
>> 1452 };
2157 1453
2158 glink-edge { !! 1454 pinconf-sd-cd {
2159 interrupts = !! 1455 pins = "gpio69";
2160 label = "mode !! 1456 bias-disable;
2161 qcom,remote-p !! 1457 drive-strength = <2>;
2162 mboxes = <&ap !! 1458 };
2163 }; 1459 };
2164 }; 1460 };
2165 1461
2166 gpu: gpu@5000000 { 1462 gpu: gpu@5000000 {
2167 compatible = "qcom,ad 1463 compatible = "qcom,adreno-618.0", "qcom,adreno";
>> 1464 #stream-id-cells = <16>;
2168 reg = <0 0x05000000 0 1465 reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x1000>,
2169 <0 0x05061000 1466 <0 0x05061000 0 0x800>;
2170 reg-names = "kgsl_3d0 1467 reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc";
2171 interrupts = <GIC_SPI 1468 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2172 iommus = <&adreno_smm 1469 iommus = <&adreno_smmu 0>;
2173 operating-points-v2 = 1470 operating-points-v2 = <&gpu_opp_table>;
2174 qcom,gmu = <&gmu>; 1471 qcom,gmu = <&gmu>;
2175 1472
2176 #cooling-cells = <2>; <<
2177 <<
2178 nvmem-cells = <&gpu_s <<
2179 nvmem-cell-names = "s <<
2180 <<
2181 interconnects = <&gem <<
2182 interconnect-names = <<
2183 <<
2184 gpu_opp_table: opp-ta 1473 gpu_opp_table: opp-table {
2185 compatible = 1474 compatible = "operating-points-v2";
2186 1475
2187 opp-825000000 <<
2188 opp-h <<
2189 opp-l <<
2190 opp-p <<
2191 opp-s <<
2192 }; <<
2193 <<
2194 opp-800000000 1476 opp-800000000 {
2195 opp-h 1477 opp-hz = /bits/ 64 <800000000>;
2196 opp-l 1478 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2197 opp-p <<
2198 opp-s <<
2199 }; 1479 };
2200 1480
2201 opp-650000000 1481 opp-650000000 {
2202 opp-h 1482 opp-hz = /bits/ 64 <650000000>;
2203 opp-l 1483 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2204 opp-p <<
2205 opp-s <<
2206 }; 1484 };
2207 1485
2208 opp-565000000 1486 opp-565000000 {
2209 opp-h 1487 opp-hz = /bits/ 64 <565000000>;
2210 opp-l 1488 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2211 opp-p <<
2212 opp-s <<
2213 }; 1489 };
2214 1490
2215 opp-430000000 1491 opp-430000000 {
2216 opp-h 1492 opp-hz = /bits/ 64 <430000000>;
2217 opp-l 1493 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2218 opp-p <<
2219 opp-s <<
2220 }; 1494 };
2221 1495
2222 opp-355000000 1496 opp-355000000 {
2223 opp-h 1497 opp-hz = /bits/ 64 <355000000>;
2224 opp-l 1498 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2225 opp-p <<
2226 opp-s <<
2227 }; 1499 };
2228 1500
2229 opp-267000000 1501 opp-267000000 {
2230 opp-h 1502 opp-hz = /bits/ 64 <267000000>;
2231 opp-l 1503 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2232 opp-p <<
2233 opp-s <<
2234 }; 1504 };
2235 1505
2236 opp-180000000 1506 opp-180000000 {
2237 opp-h 1507 opp-hz = /bits/ 64 <180000000>;
2238 opp-l 1508 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2239 opp-p <<
2240 opp-s <<
2241 }; 1509 };
2242 }; 1510 };
2243 }; 1511 };
2244 1512
2245 adreno_smmu: iommu@5040000 { 1513 adreno_smmu: iommu@5040000 {
2246 compatible = "qcom,sc !! 1514 compatible = "qcom,sc7180-smmu-v2", "qcom,smmu-v2";
2247 reg = <0 0x05040000 0 1515 reg = <0 0x05040000 0 0x10000>;
2248 #iommu-cells = <1>; 1516 #iommu-cells = <1>;
2249 #global-interrupts = 1517 #global-interrupts = <2>;
2250 interrupts = <GIC_SPI 1518 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
2251 <GIC_ 1519 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
2252 <GIC_ 1520 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
2253 <GIC_ 1521 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
2254 <GIC_ 1522 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
2255 <GIC_ 1523 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
2256 <GIC_ 1524 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
2257 <GIC_ 1525 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
2258 <GIC_ 1526 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
2259 <GIC_ 1527 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
2260 1528
2261 clocks = <&gcc GCC_GP 1529 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2262 <&gcc GCC_GPU 1530 <&gcc GCC_GPU_CFG_AHB_CLK>;
2263 clock-names = "bus", 1531 clock-names = "bus", "iface";
2264 1532
2265 power-domains = <&gpu 1533 power-domains = <&gpucc CX_GDSC>;
2266 }; 1534 };
2267 1535
2268 gmu: gmu@506a000 { 1536 gmu: gmu@506a000 {
2269 compatible = "qcom,ad !! 1537 compatible="qcom,adreno-gmu-618.0", "qcom,adreno-gmu";
2270 reg = <0 0x0506a000 0 1538 reg = <0 0x0506a000 0 0x31000>, <0 0x0b290000 0 0x10000>,
2271 <0 0x0b490000 1539 <0 0x0b490000 0 0x10000>;
2272 reg-names = "gmu", "g 1540 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
2273 interrupts = <GIC_SPI 1541 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2274 <GIC_SPI 3 1542 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2275 interrupt-names = "hf 1543 interrupt-names = "hfi", "gmu";
2276 clocks = <&gpucc GPU_ 1544 clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
2277 <&gpucc GPU_CC 1545 <&gpucc GPU_CC_CXO_CLK>,
2278 <&gcc GCC_DDRS 1546 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2279 <&gcc GCC_GPU_ 1547 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
2280 clock-names = "gmu", 1548 clock-names = "gmu", "cxo", "axi", "memnoc";
2281 power-domains = <&gpu 1549 power-domains = <&gpucc CX_GDSC>, <&gpucc GX_GDSC>;
2282 power-domain-names = 1550 power-domain-names = "cx", "gx";
2283 iommus = <&adreno_smm 1551 iommus = <&adreno_smmu 5>;
2284 operating-points-v2 = 1552 operating-points-v2 = <&gmu_opp_table>;
2285 1553
2286 gmu_opp_table: opp-ta 1554 gmu_opp_table: opp-table {
2287 compatible = 1555 compatible = "operating-points-v2";
2288 1556
2289 opp-200000000 1557 opp-200000000 {
2290 opp-h 1558 opp-hz = /bits/ 64 <200000000>;
2291 opp-l 1559 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2292 }; 1560 };
2293 }; 1561 };
2294 }; 1562 };
2295 1563
2296 gpucc: clock-controller@50900 1564 gpucc: clock-controller@5090000 {
2297 compatible = "qcom,sc 1565 compatible = "qcom,sc7180-gpucc";
2298 reg = <0 0x05090000 0 1566 reg = <0 0x05090000 0 0x9000>;
2299 clocks = <&rpmhcc RPM 1567 clocks = <&rpmhcc RPMH_CXO_CLK>,
2300 <&gcc GCC_GP 1568 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2301 <&gcc GCC_GP 1569 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2302 clock-names = "bi_tcx 1570 clock-names = "bi_tcxo",
2303 "gcc_gp 1571 "gcc_gpu_gpll0_clk_src",
2304 "gcc_gp 1572 "gcc_gpu_gpll0_div_clk_src";
2305 #clock-cells = <1>; 1573 #clock-cells = <1>;
2306 #reset-cells = <1>; 1574 #reset-cells = <1>;
2307 #power-domain-cells = 1575 #power-domain-cells = <1>;
2308 }; 1576 };
2309 1577
2310 dma@10a2000 { <<
2311 compatible = "qcom,sc <<
2312 reg = <0x0 0x010a2000 <<
2313 <0x0 0x010ae000 <<
2314 status = "disabled"; <<
2315 }; <<
2316 <<
2317 stm@6002000 { 1578 stm@6002000 {
2318 compatible = "arm,cor 1579 compatible = "arm,coresight-stm", "arm,primecell";
2319 reg = <0 0x06002000 0 1580 reg = <0 0x06002000 0 0x1000>,
2320 <0 0x16280000 0 1581 <0 0x16280000 0 0x180000>;
2321 reg-names = "stm-base 1582 reg-names = "stm-base", "stm-stimulus-base";
2322 1583
2323 clocks = <&aoss_qmp>; 1584 clocks = <&aoss_qmp>;
2324 clock-names = "apb_pc 1585 clock-names = "apb_pclk";
2325 1586
2326 out-ports { 1587 out-ports {
2327 port { 1588 port {
2328 stm_o 1589 stm_out: endpoint {
2329 1590 remote-endpoint = <&funnel0_in7>;
2330 }; 1591 };
2331 }; 1592 };
2332 }; 1593 };
2333 }; 1594 };
2334 1595
2335 funnel@6041000 { 1596 funnel@6041000 {
2336 compatible = "arm,cor 1597 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2337 reg = <0 0x06041000 0 1598 reg = <0 0x06041000 0 0x1000>;
2338 1599
2339 clocks = <&aoss_qmp>; 1600 clocks = <&aoss_qmp>;
2340 clock-names = "apb_pc 1601 clock-names = "apb_pclk";
2341 1602
2342 out-ports { 1603 out-ports {
2343 port { 1604 port {
2344 funne 1605 funnel0_out: endpoint {
2345 1606 remote-endpoint = <&merge_funnel_in0>;
2346 }; 1607 };
2347 }; 1608 };
2348 }; 1609 };
2349 1610
2350 in-ports { 1611 in-ports {
2351 #address-cell 1612 #address-cells = <1>;
2352 #size-cells = 1613 #size-cells = <0>;
2353 1614
2354 port@7 { 1615 port@7 {
2355 reg = 1616 reg = <7>;
2356 funne 1617 funnel0_in7: endpoint {
2357 1618 remote-endpoint = <&stm_out>;
2358 }; 1619 };
2359 }; 1620 };
2360 }; 1621 };
2361 }; 1622 };
2362 1623
2363 funnel@6042000 { 1624 funnel@6042000 {
2364 compatible = "arm,cor 1625 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2365 reg = <0 0x06042000 0 1626 reg = <0 0x06042000 0 0x1000>;
2366 1627
2367 clocks = <&aoss_qmp>; 1628 clocks = <&aoss_qmp>;
2368 clock-names = "apb_pc 1629 clock-names = "apb_pclk";
2369 1630
2370 out-ports { 1631 out-ports {
2371 port { 1632 port {
2372 funne 1633 funnel1_out: endpoint {
2373 1634 remote-endpoint = <&merge_funnel_in1>;
2374 }; 1635 };
2375 }; 1636 };
2376 }; 1637 };
2377 1638
2378 in-ports { 1639 in-ports {
2379 #address-cell 1640 #address-cells = <1>;
2380 #size-cells = 1641 #size-cells = <0>;
2381 1642
2382 port@4 { 1643 port@4 {
2383 reg = 1644 reg = <4>;
2384 funne 1645 funnel1_in4: endpoint {
2385 1646 remote-endpoint = <&apss_merge_funnel_out>;
2386 }; 1647 };
2387 }; 1648 };
2388 }; 1649 };
2389 }; 1650 };
2390 1651
2391 funnel@6045000 { 1652 funnel@6045000 {
2392 compatible = "arm,cor 1653 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2393 reg = <0 0x06045000 0 1654 reg = <0 0x06045000 0 0x1000>;
2394 1655
2395 clocks = <&aoss_qmp>; 1656 clocks = <&aoss_qmp>;
2396 clock-names = "apb_pc 1657 clock-names = "apb_pclk";
2397 1658
2398 out-ports { 1659 out-ports {
2399 port { 1660 port {
2400 merge 1661 merge_funnel_out: endpoint {
2401 1662 remote-endpoint = <&swao_funnel_in>;
2402 }; 1663 };
2403 }; 1664 };
2404 }; 1665 };
2405 1666
2406 in-ports { 1667 in-ports {
2407 #address-cell 1668 #address-cells = <1>;
2408 #size-cells = 1669 #size-cells = <0>;
2409 1670
2410 port@0 { 1671 port@0 {
2411 reg = 1672 reg = <0>;
2412 merge 1673 merge_funnel_in0: endpoint {
2413 1674 remote-endpoint = <&funnel0_out>;
2414 }; 1675 };
2415 }; 1676 };
2416 1677
2417 port@1 { 1678 port@1 {
2418 reg = 1679 reg = <1>;
2419 merge 1680 merge_funnel_in1: endpoint {
2420 1681 remote-endpoint = <&funnel1_out>;
2421 }; 1682 };
2422 }; 1683 };
2423 }; 1684 };
2424 }; 1685 };
2425 1686
2426 replicator@6046000 { 1687 replicator@6046000 {
2427 compatible = "arm,cor 1688 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2428 reg = <0 0x06046000 0 1689 reg = <0 0x06046000 0 0x1000>;
2429 1690
2430 clocks = <&aoss_qmp>; 1691 clocks = <&aoss_qmp>;
2431 clock-names = "apb_pc 1692 clock-names = "apb_pclk";
2432 1693
2433 out-ports { 1694 out-ports {
2434 port { 1695 port {
2435 repli 1696 replicator_out: endpoint {
2436 1697 remote-endpoint = <&etr_in>;
2437 }; 1698 };
2438 }; 1699 };
2439 }; 1700 };
2440 1701
2441 in-ports { 1702 in-ports {
2442 port { 1703 port {
2443 repli 1704 replicator_in: endpoint {
2444 1705 remote-endpoint = <&swao_replicator_out>;
2445 }; 1706 };
2446 }; 1707 };
2447 }; 1708 };
2448 }; 1709 };
2449 1710
2450 etr@6048000 { 1711 etr@6048000 {
2451 compatible = "arm,cor 1712 compatible = "arm,coresight-tmc", "arm,primecell";
2452 reg = <0 0x06048000 0 1713 reg = <0 0x06048000 0 0x1000>;
2453 iommus = <&apps_smmu <<
2454 1714
2455 clocks = <&aoss_qmp>; 1715 clocks = <&aoss_qmp>;
2456 clock-names = "apb_pc 1716 clock-names = "apb_pclk";
2457 arm,scatter-gather; 1717 arm,scatter-gather;
2458 1718
2459 in-ports { 1719 in-ports {
2460 port { 1720 port {
2461 etr_i 1721 etr_in: endpoint {
2462 1722 remote-endpoint = <&replicator_out>;
2463 }; 1723 };
2464 }; 1724 };
2465 }; 1725 };
2466 }; 1726 };
2467 1727
2468 funnel@6b04000 { 1728 funnel@6b04000 {
2469 compatible = "arm,cor 1729 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2470 reg = <0 0x06b04000 0 1730 reg = <0 0x06b04000 0 0x1000>;
2471 1731
2472 clocks = <&aoss_qmp>; 1732 clocks = <&aoss_qmp>;
2473 clock-names = "apb_pc 1733 clock-names = "apb_pclk";
2474 1734
2475 out-ports { 1735 out-ports {
2476 port { 1736 port {
2477 swao_ 1737 swao_funnel_out: endpoint {
2478 1738 remote-endpoint = <&etf_in>;
2479 }; 1739 };
2480 }; 1740 };
2481 }; 1741 };
2482 1742
2483 in-ports { 1743 in-ports {
2484 #address-cell 1744 #address-cells = <1>;
2485 #size-cells = 1745 #size-cells = <0>;
2486 1746
2487 port@7 { 1747 port@7 {
2488 reg = 1748 reg = <7>;
2489 swao_ 1749 swao_funnel_in: endpoint {
2490 1750 remote-endpoint = <&merge_funnel_out>;
2491 }; 1751 };
2492 }; 1752 };
2493 }; 1753 };
2494 }; 1754 };
2495 1755
2496 etf@6b05000 { 1756 etf@6b05000 {
2497 compatible = "arm,cor 1757 compatible = "arm,coresight-tmc", "arm,primecell";
2498 reg = <0 0x06b05000 0 1758 reg = <0 0x06b05000 0 0x1000>;
2499 1759
2500 clocks = <&aoss_qmp>; 1760 clocks = <&aoss_qmp>;
2501 clock-names = "apb_pc 1761 clock-names = "apb_pclk";
2502 1762
2503 out-ports { 1763 out-ports {
2504 port { 1764 port {
2505 etf_o 1765 etf_out: endpoint {
2506 1766 remote-endpoint = <&swao_replicator_in>;
2507 }; 1767 };
2508 }; 1768 };
2509 }; 1769 };
2510 1770
2511 in-ports { 1771 in-ports {
2512 port { 1772 port {
2513 etf_i 1773 etf_in: endpoint {
2514 1774 remote-endpoint = <&swao_funnel_out>;
2515 }; 1775 };
2516 }; 1776 };
2517 }; 1777 };
2518 }; 1778 };
2519 1779
2520 replicator@6b06000 { 1780 replicator@6b06000 {
2521 compatible = "arm,cor 1781 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2522 reg = <0 0x06b06000 0 1782 reg = <0 0x06b06000 0 0x1000>;
2523 1783
2524 clocks = <&aoss_qmp>; 1784 clocks = <&aoss_qmp>;
2525 clock-names = "apb_pc 1785 clock-names = "apb_pclk";
2526 qcom,replicator-loses <<
2527 1786
2528 out-ports { 1787 out-ports {
2529 port { 1788 port {
2530 swao_ 1789 swao_replicator_out: endpoint {
2531 1790 remote-endpoint = <&replicator_in>;
2532 }; 1791 };
2533 }; 1792 };
2534 }; 1793 };
2535 1794
2536 in-ports { 1795 in-ports {
2537 port { 1796 port {
2538 swao_ 1797 swao_replicator_in: endpoint {
2539 1798 remote-endpoint = <&etf_out>;
2540 }; 1799 };
2541 }; 1800 };
2542 }; 1801 };
2543 }; 1802 };
2544 1803
2545 etm@7040000 { 1804 etm@7040000 {
2546 compatible = "arm,cor 1805 compatible = "arm,coresight-etm4x", "arm,primecell";
2547 reg = <0 0x07040000 0 1806 reg = <0 0x07040000 0 0x1000>;
2548 1807
2549 cpu = <&CPU0>; 1808 cpu = <&CPU0>;
2550 1809
2551 clocks = <&aoss_qmp>; 1810 clocks = <&aoss_qmp>;
2552 clock-names = "apb_pc 1811 clock-names = "apb_pclk";
2553 arm,coresight-loses-c 1812 arm,coresight-loses-context-with-cpu;
2554 qcom,skip-power-up; <<
2555 1813
2556 out-ports { 1814 out-ports {
2557 port { 1815 port {
2558 etm0_ 1816 etm0_out: endpoint {
2559 1817 remote-endpoint = <&apss_funnel_in0>;
2560 }; 1818 };
2561 }; 1819 };
2562 }; 1820 };
2563 }; 1821 };
2564 1822
2565 etm@7140000 { 1823 etm@7140000 {
2566 compatible = "arm,cor 1824 compatible = "arm,coresight-etm4x", "arm,primecell";
2567 reg = <0 0x07140000 0 1825 reg = <0 0x07140000 0 0x1000>;
2568 1826
2569 cpu = <&CPU1>; 1827 cpu = <&CPU1>;
2570 1828
2571 clocks = <&aoss_qmp>; 1829 clocks = <&aoss_qmp>;
2572 clock-names = "apb_pc 1830 clock-names = "apb_pclk";
2573 arm,coresight-loses-c 1831 arm,coresight-loses-context-with-cpu;
2574 qcom,skip-power-up; <<
2575 1832
2576 out-ports { 1833 out-ports {
2577 port { 1834 port {
2578 etm1_ 1835 etm1_out: endpoint {
2579 1836 remote-endpoint = <&apss_funnel_in1>;
2580 }; 1837 };
2581 }; 1838 };
2582 }; 1839 };
2583 }; 1840 };
2584 1841
2585 etm@7240000 { 1842 etm@7240000 {
2586 compatible = "arm,cor 1843 compatible = "arm,coresight-etm4x", "arm,primecell";
2587 reg = <0 0x07240000 0 1844 reg = <0 0x07240000 0 0x1000>;
2588 1845
2589 cpu = <&CPU2>; 1846 cpu = <&CPU2>;
2590 1847
2591 clocks = <&aoss_qmp>; 1848 clocks = <&aoss_qmp>;
2592 clock-names = "apb_pc 1849 clock-names = "apb_pclk";
2593 arm,coresight-loses-c 1850 arm,coresight-loses-context-with-cpu;
2594 qcom,skip-power-up; <<
2595 1851
2596 out-ports { 1852 out-ports {
2597 port { 1853 port {
2598 etm2_ 1854 etm2_out: endpoint {
2599 1855 remote-endpoint = <&apss_funnel_in2>;
2600 }; 1856 };
2601 }; 1857 };
2602 }; 1858 };
2603 }; 1859 };
2604 1860
2605 etm@7340000 { 1861 etm@7340000 {
2606 compatible = "arm,cor 1862 compatible = "arm,coresight-etm4x", "arm,primecell";
2607 reg = <0 0x07340000 0 1863 reg = <0 0x07340000 0 0x1000>;
2608 1864
2609 cpu = <&CPU3>; 1865 cpu = <&CPU3>;
2610 1866
2611 clocks = <&aoss_qmp>; 1867 clocks = <&aoss_qmp>;
2612 clock-names = "apb_pc 1868 clock-names = "apb_pclk";
2613 arm,coresight-loses-c 1869 arm,coresight-loses-context-with-cpu;
2614 qcom,skip-power-up; <<
2615 1870
2616 out-ports { 1871 out-ports {
2617 port { 1872 port {
2618 etm3_ 1873 etm3_out: endpoint {
2619 1874 remote-endpoint = <&apss_funnel_in3>;
2620 }; 1875 };
2621 }; 1876 };
2622 }; 1877 };
2623 }; 1878 };
2624 1879
2625 etm@7440000 { 1880 etm@7440000 {
2626 compatible = "arm,cor 1881 compatible = "arm,coresight-etm4x", "arm,primecell";
2627 reg = <0 0x07440000 0 1882 reg = <0 0x07440000 0 0x1000>;
2628 1883
2629 cpu = <&CPU4>; 1884 cpu = <&CPU4>;
2630 1885
2631 clocks = <&aoss_qmp>; 1886 clocks = <&aoss_qmp>;
2632 clock-names = "apb_pc 1887 clock-names = "apb_pclk";
2633 arm,coresight-loses-c 1888 arm,coresight-loses-context-with-cpu;
2634 qcom,skip-power-up; <<
2635 1889
2636 out-ports { 1890 out-ports {
2637 port { 1891 port {
2638 etm4_ 1892 etm4_out: endpoint {
2639 1893 remote-endpoint = <&apss_funnel_in4>;
2640 }; 1894 };
2641 }; 1895 };
2642 }; 1896 };
2643 }; 1897 };
2644 1898
2645 etm@7540000 { 1899 etm@7540000 {
2646 compatible = "arm,cor 1900 compatible = "arm,coresight-etm4x", "arm,primecell";
2647 reg = <0 0x07540000 0 1901 reg = <0 0x07540000 0 0x1000>;
2648 1902
2649 cpu = <&CPU5>; 1903 cpu = <&CPU5>;
2650 1904
2651 clocks = <&aoss_qmp>; 1905 clocks = <&aoss_qmp>;
2652 clock-names = "apb_pc 1906 clock-names = "apb_pclk";
2653 arm,coresight-loses-c 1907 arm,coresight-loses-context-with-cpu;
2654 qcom,skip-power-up; <<
2655 1908
2656 out-ports { 1909 out-ports {
2657 port { 1910 port {
2658 etm5_ 1911 etm5_out: endpoint {
2659 1912 remote-endpoint = <&apss_funnel_in5>;
2660 }; 1913 };
2661 }; 1914 };
2662 }; 1915 };
2663 }; 1916 };
2664 1917
2665 etm@7640000 { 1918 etm@7640000 {
2666 compatible = "arm,cor 1919 compatible = "arm,coresight-etm4x", "arm,primecell";
2667 reg = <0 0x07640000 0 1920 reg = <0 0x07640000 0 0x1000>;
2668 1921
2669 cpu = <&CPU6>; 1922 cpu = <&CPU6>;
2670 1923
2671 clocks = <&aoss_qmp>; 1924 clocks = <&aoss_qmp>;
2672 clock-names = "apb_pc 1925 clock-names = "apb_pclk";
2673 arm,coresight-loses-c 1926 arm,coresight-loses-context-with-cpu;
2674 qcom,skip-power-up; <<
2675 1927
2676 out-ports { 1928 out-ports {
2677 port { 1929 port {
2678 etm6_ 1930 etm6_out: endpoint {
2679 1931 remote-endpoint = <&apss_funnel_in6>;
2680 }; 1932 };
2681 }; 1933 };
2682 }; 1934 };
2683 }; 1935 };
2684 1936
2685 etm@7740000 { 1937 etm@7740000 {
2686 compatible = "arm,cor 1938 compatible = "arm,coresight-etm4x", "arm,primecell";
2687 reg = <0 0x07740000 0 1939 reg = <0 0x07740000 0 0x1000>;
2688 1940
2689 cpu = <&CPU7>; 1941 cpu = <&CPU7>;
2690 1942
2691 clocks = <&aoss_qmp>; 1943 clocks = <&aoss_qmp>;
2692 clock-names = "apb_pc 1944 clock-names = "apb_pclk";
2693 arm,coresight-loses-c 1945 arm,coresight-loses-context-with-cpu;
2694 qcom,skip-power-up; <<
2695 1946
2696 out-ports { 1947 out-ports {
2697 port { 1948 port {
2698 etm7_ 1949 etm7_out: endpoint {
2699 1950 remote-endpoint = <&apss_funnel_in7>;
2700 }; 1951 };
2701 }; 1952 };
2702 }; 1953 };
2703 }; 1954 };
2704 1955
2705 funnel@7800000 { /* APSS Funn 1956 funnel@7800000 { /* APSS Funnel */
2706 compatible = "arm,cor 1957 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2707 reg = <0 0x07800000 0 1958 reg = <0 0x07800000 0 0x1000>;
2708 1959
2709 clocks = <&aoss_qmp>; 1960 clocks = <&aoss_qmp>;
2710 clock-names = "apb_pc 1961 clock-names = "apb_pclk";
2711 1962
2712 out-ports { 1963 out-ports {
2713 port { 1964 port {
2714 apss_ 1965 apss_funnel_out: endpoint {
2715 1966 remote-endpoint = <&apss_merge_funnel_in>;
2716 }; 1967 };
2717 }; 1968 };
2718 }; 1969 };
2719 1970
2720 in-ports { 1971 in-ports {
2721 #address-cell 1972 #address-cells = <1>;
2722 #size-cells = 1973 #size-cells = <0>;
2723 1974
2724 port@0 { 1975 port@0 {
2725 reg = 1976 reg = <0>;
2726 apss_ 1977 apss_funnel_in0: endpoint {
2727 1978 remote-endpoint = <&etm0_out>;
2728 }; 1979 };
2729 }; 1980 };
2730 1981
2731 port@1 { 1982 port@1 {
2732 reg = 1983 reg = <1>;
2733 apss_ 1984 apss_funnel_in1: endpoint {
2734 1985 remote-endpoint = <&etm1_out>;
2735 }; 1986 };
2736 }; 1987 };
2737 1988
2738 port@2 { 1989 port@2 {
2739 reg = 1990 reg = <2>;
2740 apss_ 1991 apss_funnel_in2: endpoint {
2741 1992 remote-endpoint = <&etm2_out>;
2742 }; 1993 };
2743 }; 1994 };
2744 1995
2745 port@3 { 1996 port@3 {
2746 reg = 1997 reg = <3>;
2747 apss_ 1998 apss_funnel_in3: endpoint {
2748 1999 remote-endpoint = <&etm3_out>;
2749 }; 2000 };
2750 }; 2001 };
2751 2002
2752 port@4 { 2003 port@4 {
2753 reg = 2004 reg = <4>;
2754 apss_ 2005 apss_funnel_in4: endpoint {
2755 2006 remote-endpoint = <&etm4_out>;
2756 }; 2007 };
2757 }; 2008 };
2758 2009
2759 port@5 { 2010 port@5 {
2760 reg = 2011 reg = <5>;
2761 apss_ 2012 apss_funnel_in5: endpoint {
2762 2013 remote-endpoint = <&etm5_out>;
2763 }; 2014 };
2764 }; 2015 };
2765 2016
2766 port@6 { 2017 port@6 {
2767 reg = 2018 reg = <6>;
2768 apss_ 2019 apss_funnel_in6: endpoint {
2769 2020 remote-endpoint = <&etm6_out>;
2770 }; 2021 };
2771 }; 2022 };
2772 2023
2773 port@7 { 2024 port@7 {
2774 reg = 2025 reg = <7>;
2775 apss_ 2026 apss_funnel_in7: endpoint {
2776 2027 remote-endpoint = <&etm7_out>;
2777 }; 2028 };
2778 }; 2029 };
2779 }; 2030 };
2780 }; 2031 };
2781 2032
2782 funnel@7810000 { 2033 funnel@7810000 {
2783 compatible = "arm,cor 2034 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2784 reg = <0 0x07810000 0 2035 reg = <0 0x07810000 0 0x1000>;
2785 2036
2786 clocks = <&aoss_qmp>; 2037 clocks = <&aoss_qmp>;
2787 clock-names = "apb_pc 2038 clock-names = "apb_pclk";
2788 2039
2789 out-ports { 2040 out-ports {
2790 port { 2041 port {
2791 apss_ 2042 apss_merge_funnel_out: endpoint {
2792 2043 remote-endpoint = <&funnel1_in4>;
2793 }; 2044 };
2794 }; 2045 };
2795 }; 2046 };
2796 2047
2797 in-ports { 2048 in-ports {
2798 port { 2049 port {
2799 apss_ 2050 apss_merge_funnel_in: endpoint {
2800 2051 remote-endpoint = <&apss_funnel_out>;
2801 }; 2052 };
2802 }; 2053 };
2803 }; 2054 };
2804 }; 2055 };
2805 2056
2806 sdhc_2: mmc@8804000 { !! 2057 remoteproc_mpss: remoteproc@4080000 {
>> 2058 compatible = "qcom,sc7180-mpss-pas";
>> 2059 reg = <0 0x04080000 0 0x4040>, <0 0x04180000 0 0x48>;
>> 2060 reg-names = "qdsp6", "rmb";
>> 2061
>> 2062 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
>> 2063 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
>> 2064 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
>> 2065 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
>> 2066 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
>> 2067 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
>> 2068 interrupt-names = "wdog", "fatal", "ready", "handover",
>> 2069 "stop-ack", "shutdown-ack";
>> 2070
>> 2071 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
>> 2072 <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>,
>> 2073 <&gcc GCC_MSS_NAV_AXI_CLK>,
>> 2074 <&gcc GCC_MSS_SNOC_AXI_CLK>,
>> 2075 <&gcc GCC_MSS_MFAB_AXIS_CLK>,
>> 2076 <&rpmhcc RPMH_CXO_CLK>;
>> 2077 clock-names = "iface", "bus", "nav", "snoc_axi",
>> 2078 "mnoc_axi", "xo";
>> 2079
>> 2080 power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>,
>> 2081 <&rpmhpd SC7180_CX>,
>> 2082 <&rpmhpd SC7180_MX>,
>> 2083 <&rpmhpd SC7180_MSS>;
>> 2084 power-domain-names = "load_state", "cx", "mx", "mss";
>> 2085
>> 2086 memory-region = <&mpss_mem>;
>> 2087
>> 2088 qcom,smem-states = <&modem_smp2p_out 0>;
>> 2089 qcom,smem-state-names = "stop";
>> 2090
>> 2091 resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
>> 2092 <&pdc_reset PDC_MODEM_SYNC_RESET>;
>> 2093 reset-names = "mss_restart", "pdc_reset";
>> 2094
>> 2095 qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
>> 2096 qcom,spare-regs = <&tcsr_regs 0xb3e4>;
>> 2097
>> 2098 status = "disabled";
>> 2099
>> 2100 glink-edge {
>> 2101 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
>> 2102 label = "modem";
>> 2103 qcom,remote-pid = <1>;
>> 2104 mboxes = <&apss_shared 12>;
>> 2105 };
>> 2106 };
>> 2107
>> 2108 sdhc_2: sdhci@8804000 {
2807 compatible = "qcom,sc 2109 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
2808 reg = <0 0x08804000 0 2110 reg = <0 0x08804000 0 0x1000>;
2809 2111
2810 iommus = <&apps_smmu 2112 iommus = <&apps_smmu 0x80 0>;
2811 interrupts = <GIC_SPI 2113 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
2812 <GIC_ 2114 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
2813 interrupt-names = "hc 2115 interrupt-names = "hc_irq", "pwr_irq";
2814 2116
2815 clocks = <&gcc GCC_SD !! 2117 clocks = <&gcc GCC_SDCC2_APPS_CLK>,
2816 <&gcc GCC_SD !! 2118 <&gcc GCC_SDCC2_AHB_CLK>;
2817 <&rpmhcc RPM !! 2119 clock-names = "core", "iface";
2818 clock-names = "iface" <<
2819 <<
2820 interconnects = <&agg <<
2821 <&gem <<
2822 interconnect-names = <<
2823 power-domains = <&rpm <<
2824 operating-points-v2 = <<
2825 2120
2826 bus-width = <4>; 2121 bus-width = <4>;
2827 2122
2828 status = "disabled"; 2123 status = "disabled";
2829 <<
2830 sdhc2_opp_table: opp- <<
2831 compatible = <<
2832 <<
2833 opp-100000000 <<
2834 opp-h <<
2835 requi <<
2836 opp-p <<
2837 opp-a <<
2838 }; <<
2839 <<
2840 opp-202000000 <<
2841 opp-h <<
2842 requi <<
2843 opp-p <<
2844 opp-a <<
2845 }; <<
2846 }; <<
2847 }; 2124 };
2848 2125
2849 qspi: spi@88dc000 { 2126 qspi: spi@88dc000 {
2850 compatible = "qcom,sc !! 2127 compatible = "qcom,qspi-v1";
2851 reg = <0 0x088dc000 0 2128 reg = <0 0x088dc000 0 0x600>;
2852 iommus = <&apps_smmu <<
2853 #address-cells = <1>; 2129 #address-cells = <1>;
2854 #size-cells = <0>; 2130 #size-cells = <0>;
2855 interrupts = <GIC_SPI 2131 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
2856 clocks = <&gcc GCC_QS 2132 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
2857 <&gcc GCC_QS 2133 <&gcc GCC_QSPI_CORE_CLK>;
2858 clock-names = "iface" 2134 clock-names = "iface", "core";
2859 interconnects = <&gem <<
2860 &conf <<
2861 interconnect-names = <<
2862 power-domains = <&rpm <<
2863 operating-points-v2 = <<
2864 status = "disabled"; 2135 status = "disabled";
2865 }; 2136 };
2866 2137
2867 usb_1_hsphy: phy@88e3000 { 2138 usb_1_hsphy: phy@88e3000 {
2868 compatible = "qcom,sc 2139 compatible = "qcom,sc7180-qusb2-phy", "qcom,qusb2-v2-phy";
2869 reg = <0 0x088e3000 0 2140 reg = <0 0x088e3000 0 0x400>;
2870 status = "disabled"; 2141 status = "disabled";
2871 #phy-cells = <0>; 2142 #phy-cells = <0>;
2872 clocks = <&gcc GCC_US 2143 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2873 <&rpmhcc RPM 2144 <&rpmhcc RPMH_CXO_CLK>;
2874 clock-names = "cfg_ah 2145 clock-names = "cfg_ahb", "ref";
2875 resets = <&gcc GCC_QU 2146 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2876 2147
2877 nvmem-cells = <&qusb2 2148 nvmem-cells = <&qusb2p_hstx_trim>;
2878 }; 2149 };
2879 2150
2880 usb_1_qmpphy: phy@88e8000 { !! 2151 usb_1_qmpphy: phy-wrapper@88e9000 {
2881 compatible = "qcom,sc !! 2152 compatible = "qcom,sc7180-qmp-usb3-phy";
2882 reg = <0 0x088e8000 0 !! 2153 reg = <0 0x088e9000 0 0x18c>,
>> 2154 <0 0x088e8000 0 0x38>;
>> 2155 reg-names = "reg-base", "dp_com";
2883 status = "disabled"; 2156 status = "disabled";
>> 2157 #clock-cells = <1>;
>> 2158 #address-cells = <2>;
>> 2159 #size-cells = <2>;
>> 2160 ranges;
2884 2161
2885 clocks = <&gcc GCC_US 2162 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
>> 2163 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2886 <&gcc GCC_US 2164 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
2887 <&gcc GCC_US !! 2165 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
2888 <&gcc GCC_US !! 2166 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
2889 <&gcc GCC_US <<
2890 clock-names = "aux", <<
2891 "ref", <<
2892 "com_au <<
2893 "usb3_p <<
2894 "cfg_ah <<
2895 2167
2896 resets = <&gcc GCC_US 2168 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
2897 <&gcc GCC_US 2169 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
2898 reset-names = "phy", 2170 reset-names = "phy", "common";
2899 2171
2900 #clock-cells = <1>; !! 2172 usb_1_ssphy: phy@88e9200 {
2901 #phy-cells = <1>; !! 2173 reg = <0 0x088e9200 0 0x128>,
2902 }; !! 2174 <0 0x088e9400 0 0x200>,
2903 !! 2175 <0 0x088e9c00 0 0x218>,
2904 pmu@90b6300 { !! 2176 <0 0x088e9600 0 0x128>,
2905 compatible = "qcom,sc !! 2177 <0 0x088e9800 0 0x200>,
2906 reg = <0 0x090b6300 0 !! 2178 <0 0x088e9a00 0 0x18>;
2907 interrupts = <GIC_SPI !! 2179 #clock-cells = <0>;
2908 !! 2180 #phy-cells = <0>;
2909 interconnects = <&gem !! 2181 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2910 &gem !! 2182 clock-names = "pipe0";
2911 operating-points-v2 = !! 2183 clock-output-names = "usb3_phy_pipe_clk_src";
2912 <<
2913 cpu_bwmon_opp_table: <<
2914 compatible = <<
2915 <<
2916 opp-0 { <<
2917 opp-p <<
2918 }; <<
2919 <<
2920 opp-1 { <<
2921 opp-p <<
2922 }; <<
2923 <<
2924 opp-2 { <<
2925 opp-p <<
2926 }; <<
2927 <<
2928 opp-3 { <<
2929 opp-p <<
2930 }; <<
2931 <<
2932 opp-4 { <<
2933 opp-p <<
2934 }; <<
2935 <<
2936 opp-5 { <<
2937 opp-p <<
2938 }; <<
2939 }; <<
2940 }; <<
2941 <<
2942 pmu@90cd000 { <<
2943 compatible = "qcom,sc <<
2944 reg = <0 0x090cd000 0 <<
2945 interrupts = <GIC_SPI <<
2946 <<
2947 interconnects = <&mc_ <<
2948 &mc_ <<
2949 operating-points-v2 = <<
2950 <<
2951 llcc_bwmon_opp_table: <<
2952 compatible = <<
2953 <<
2954 opp-0 { <<
2955 opp-p <<
2956 }; <<
2957 <<
2958 opp-1 { <<
2959 opp-p <<
2960 }; <<
2961 <<
2962 opp-2 { <<
2963 opp-p <<
2964 }; <<
2965 <<
2966 opp-3 { <<
2967 opp-p <<
2968 }; <<
2969 <<
2970 opp-4 { <<
2971 opp-p <<
2972 }; <<
2973 <<
2974 opp-5 { <<
2975 opp-p <<
2976 }; <<
2977 <<
2978 opp-6 { <<
2979 opp-p <<
2980 }; <<
2981 <<
2982 opp-7 { <<
2983 opp-p <<
2984 }; <<
2985 }; 2184 };
2986 }; 2185 };
2987 2186
2988 dc_noc: interconnect@9160000 2187 dc_noc: interconnect@9160000 {
2989 compatible = "qcom,sc 2188 compatible = "qcom,sc7180-dc-noc";
2990 reg = <0 0x09160000 0 2189 reg = <0 0x09160000 0 0x03200>;
2991 #interconnect-cells = !! 2190 #interconnect-cells = <1>;
2992 qcom,bcm-voters = <&a 2191 qcom,bcm-voters = <&apps_bcm_voter>;
2993 }; 2192 };
2994 2193
2995 system-cache-controller@92000 2194 system-cache-controller@9200000 {
2996 compatible = "qcom,sc 2195 compatible = "qcom,sc7180-llcc";
2997 reg = <0 0x09200000 0 2196 reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>;
2998 reg-names = "llcc0_ba !! 2197 reg-names = "llcc_base", "llcc_broadcast_base";
2999 interrupts = <GIC_SPI 2198 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
3000 }; 2199 };
3001 2200
3002 gem_noc: interconnect@9680000 2201 gem_noc: interconnect@9680000 {
3003 compatible = "qcom,sc 2202 compatible = "qcom,sc7180-gem-noc";
3004 reg = <0 0x09680000 0 2203 reg = <0 0x09680000 0 0x3e200>;
3005 #interconnect-cells = !! 2204 #interconnect-cells = <1>;
3006 qcom,bcm-voters = <&a 2205 qcom,bcm-voters = <&apps_bcm_voter>;
3007 }; 2206 };
3008 2207
3009 npu_noc: interconnect@9990000 2208 npu_noc: interconnect@9990000 {
3010 compatible = "qcom,sc 2209 compatible = "qcom,sc7180-npu-noc";
3011 reg = <0 0x09990000 0 2210 reg = <0 0x09990000 0 0x1600>;
3012 #interconnect-cells = !! 2211 #interconnect-cells = <1>;
3013 qcom,bcm-voters = <&a 2212 qcom,bcm-voters = <&apps_bcm_voter>;
3014 }; 2213 };
3015 2214
3016 usb_1: usb@a6f8800 { 2215 usb_1: usb@a6f8800 {
3017 compatible = "qcom,sc 2216 compatible = "qcom,sc7180-dwc3", "qcom,dwc3";
3018 reg = <0 0x0a6f8800 0 2217 reg = <0 0x0a6f8800 0 0x400>;
3019 status = "disabled"; 2218 status = "disabled";
3020 #address-cells = <2>; 2219 #address-cells = <2>;
3021 #size-cells = <2>; 2220 #size-cells = <2>;
3022 ranges; 2221 ranges;
3023 dma-ranges; 2222 dma-ranges;
3024 2223
3025 clocks = <&gcc GCC_CF 2224 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
3026 <&gcc GCC_US 2225 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
3027 <&gcc GCC_AG 2226 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
3028 <&gcc GCC_US !! 2227 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3029 <&gcc GCC_US !! 2228 <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
3030 clock-names = "cfg_no !! 2229 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
3031 "core", !! 2230 "sleep";
3032 "iface" <<
3033 "sleep" <<
3034 "mock_u <<
3035 2231
3036 assigned-clocks = <&g 2232 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3037 <&g 2233 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
3038 assigned-clock-rates 2234 assigned-clock-rates = <19200000>, <150000000>;
3039 2235
3040 interrupts-extended = !! 2236 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
3041 !! 2237 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
3042 !! 2238 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
3043 !! 2239 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
3044 !! 2240 interrupt-names = "hs_phy_irq", "ss_phy_irq",
3045 interrupt-names = "pw !! 2241 "dm_hs_phy_irq", "dp_hs_phy_irq";
3046 "hs <<
3047 "dp <<
3048 "dm <<
3049 "ss <<
3050 2242
3051 power-domains = <&gcc 2243 power-domains = <&gcc USB30_PRIM_GDSC>;
3052 required-opps = <&rpm <<
3053 2244
3054 resets = <&gcc GCC_US 2245 resets = <&gcc GCC_USB30_PRIM_BCR>;
3055 2246
3056 interconnects = <&agg !! 2247 interconnects = <&aggre2_noc MASTER_USB3 &mc_virt SLAVE_EBI1>,
3057 <&gem !! 2248 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3>;
3058 interconnect-names = 2249 interconnect-names = "usb-ddr", "apps-usb";
3059 2250
3060 wakeup-source; !! 2251 usb_1_dwc3: dwc3@a600000 {
3061 <<
3062 usb_1_dwc3: usb@a6000 <<
3063 compatible = 2252 compatible = "snps,dwc3";
3064 reg = <0 0x0a 2253 reg = <0 0x0a600000 0 0xe000>;
3065 interrupts = 2254 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
3066 iommus = <&ap 2255 iommus = <&apps_smmu 0x540 0>;
3067 snps,dis_u2_s 2256 snps,dis_u2_susphy_quirk;
3068 snps,dis_enbl 2257 snps,dis_enblslpm_quirk;
3069 snps,parkmode !! 2258 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
3070 phys = <&usb_ <<
3071 phy-names = " 2259 phy-names = "usb2-phy", "usb3-phy";
3072 maximum-speed <<
3073 }; 2260 };
3074 }; 2261 };
3075 2262
3076 venus: video-codec@aa00000 { 2263 venus: video-codec@aa00000 {
3077 compatible = "qcom,sc 2264 compatible = "qcom,sc7180-venus";
3078 reg = <0 0x0aa00000 0 2265 reg = <0 0x0aa00000 0 0xff000>;
3079 interrupts = <GIC_SPI 2266 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
3080 power-domains = <&vid 2267 power-domains = <&videocc VENUS_GDSC>,
3081 <&vid !! 2268 <&videocc VCODEC0_GDSC>;
3082 <&rpm !! 2269 power-domain-names = "venus", "vcodec0";
3083 power-domain-names = <<
3084 operating-points-v2 = <<
3085 clocks = <&videocc VI 2270 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
3086 <&videocc VI 2271 <&videocc VIDEO_CC_VENUS_AHB_CLK>,
3087 <&videocc VI 2272 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>,
3088 <&videocc VI 2273 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
3089 <&videocc VI 2274 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>;
3090 clock-names = "core", 2275 clock-names = "core", "iface", "bus",
3091 "vcodec 2276 "vcodec0_core", "vcodec0_bus";
3092 iommus = <&apps_smmu 2277 iommus = <&apps_smmu 0x0c00 0x60>;
3093 memory-region = <&ven 2278 memory-region = <&venus_mem>;
3094 interconnects = <&mms !! 2279 interconnects = <&mmss_noc MASTER_VIDEO_P0 &mc_virt SLAVE_EBI1>,
3095 <&gem !! 2280 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_VENUS_CFG>;
3096 interconnect-names = 2281 interconnect-names = "video-mem", "cpu-cfg";
3097 2282
3098 video-decoder { 2283 video-decoder {
3099 compatible = 2284 compatible = "venus-decoder";
3100 }; 2285 };
3101 2286
3102 video-encoder { 2287 video-encoder {
3103 compatible = 2288 compatible = "venus-encoder";
3104 }; 2289 };
3105 <<
3106 venus_opp_table: opp- <<
3107 compatible = <<
3108 <<
3109 opp-150000000 <<
3110 opp-h <<
3111 requi <<
3112 }; <<
3113 <<
3114 opp-270000000 <<
3115 opp-h <<
3116 requi <<
3117 }; <<
3118 <<
3119 opp-340000000 <<
3120 opp-h <<
3121 requi <<
3122 }; <<
3123 <<
3124 opp-434000000 <<
3125 opp-h <<
3126 requi <<
3127 }; <<
3128 <<
3129 opp-500000097 <<
3130 opp-h <<
3131 requi <<
3132 }; <<
3133 }; <<
3134 }; 2290 };
3135 2291
3136 videocc: clock-controller@ab0 2292 videocc: clock-controller@ab00000 {
3137 compatible = "qcom,sc 2293 compatible = "qcom,sc7180-videocc";
3138 reg = <0 0x0ab00000 0 2294 reg = <0 0x0ab00000 0 0x10000>;
3139 clocks = <&rpmhcc RPM 2295 clocks = <&rpmhcc RPMH_CXO_CLK>;
3140 clock-names = "bi_tcx 2296 clock-names = "bi_tcxo";
3141 #clock-cells = <1>; 2297 #clock-cells = <1>;
3142 #reset-cells = <1>; 2298 #reset-cells = <1>;
3143 #power-domain-cells = 2299 #power-domain-cells = <1>;
3144 }; 2300 };
3145 2301
3146 camnoc_virt: interconnect@ac0 2302 camnoc_virt: interconnect@ac00000 {
3147 compatible = "qcom,sc 2303 compatible = "qcom,sc7180-camnoc-virt";
3148 reg = <0 0x0ac00000 0 2304 reg = <0 0x0ac00000 0 0x1000>;
3149 #interconnect-cells = !! 2305 #interconnect-cells = <1>;
3150 qcom,bcm-voters = <&a 2306 qcom,bcm-voters = <&apps_bcm_voter>;
3151 }; 2307 };
3152 2308
3153 camcc: clock-controller@ad000 !! 2309 mdss: mdss@ae00000 {
3154 compatible = "qcom,sc <<
3155 reg = <0 0x0ad00000 0 <<
3156 clocks = <&rpmhcc RPM <<
3157 <&gcc GCC_CAME <<
3158 <&gcc GCC_CAME <<
3159 clock-names = "bi_tcx <<
3160 #clock-cells = <1>; <<
3161 #reset-cells = <1>; <<
3162 #power-domain-cells = <<
3163 }; <<
3164 <<
3165 mdss: display-subsystem@ae000 <<
3166 compatible = "qcom,sc 2310 compatible = "qcom,sc7180-mdss";
3167 reg = <0 0x0ae00000 0 2311 reg = <0 0x0ae00000 0 0x1000>;
3168 reg-names = "mdss"; 2312 reg-names = "mdss";
3169 2313
3170 power-domains = <&dis 2314 power-domains = <&dispcc MDSS_GDSC>;
3171 2315
3172 clocks = <&gcc GCC_DI 2316 clocks = <&gcc GCC_DISP_AHB_CLK>,
>> 2317 <&gcc GCC_DISP_HF_AXI_CLK>,
3173 <&dispcc DIS 2318 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3174 <&dispcc DIS 2319 <&dispcc DISP_CC_MDSS_MDP_CLK>;
3175 clock-names = "iface" !! 2320 clock-names = "iface", "bus", "ahb", "core";
>> 2321
>> 2322 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
>> 2323 assigned-clock-rates = <300000000>;
3176 2324
3177 interrupts = <GIC_SPI 2325 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
3178 interrupt-controller; 2326 interrupt-controller;
3179 #interrupt-cells = <1 2327 #interrupt-cells = <1>;
3180 2328
3181 interconnects = <&mms <<
3182 &mc_ <<
3183 <&gem <<
3184 &con <<
3185 interconnect-names = <<
3186 <<
3187 <<
3188 iommus = <&apps_smmu 2329 iommus = <&apps_smmu 0x800 0x2>;
3189 2330
3190 #address-cells = <2>; 2331 #address-cells = <2>;
3191 #size-cells = <2>; 2332 #size-cells = <2>;
3192 ranges; 2333 ranges;
3193 2334
3194 status = "disabled"; 2335 status = "disabled";
3195 2336
3196 mdp: display-controll !! 2337 mdp: mdp@ae01000 {
3197 compatible = 2338 compatible = "qcom,sc7180-dpu";
3198 reg = <0 0x0a 2339 reg = <0 0x0ae01000 0 0x8f000>,
3199 <0 0x0a 2340 <0 0x0aeb0000 0 0x2008>;
3200 reg-names = " 2341 reg-names = "mdp", "vbif";
3201 2342
3202 clocks = <&gc !! 2343 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3203 <&di <<
3204 <&di 2344 <&dispcc DISP_CC_MDSS_ROT_CLK>,
3205 <&di 2345 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
3206 <&di 2346 <&dispcc DISP_CC_MDSS_MDP_CLK>,
3207 <&di 2347 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3208 clock-names = !! 2348 clock-names = "iface", "rot", "lut", "core",
3209 2349 "vsync";
3210 assigned-cloc !! 2350 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
>> 2351 <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
3211 2352 <&dispcc DISP_CC_MDSS_ROT_CLK>,
3212 2353 <&dispcc DISP_CC_MDSS_AHB_CLK>;
3213 assigned-cloc !! 2354 assigned-clock-rates = <300000000>,
>> 2355 <19200000>,
3214 2356 <19200000>,
3215 2357 <19200000>;
3216 operating-poi <<
3217 power-domains <<
3218 2358
3219 interrupt-par 2359 interrupt-parent = <&mdss>;
3220 interrupts = 2360 interrupts = <0>;
3221 2361
>> 2362 status = "disabled";
>> 2363
3222 ports { 2364 ports {
3223 #addr 2365 #address-cells = <1>;
3224 #size 2366 #size-cells = <0>;
3225 2367
3226 port@ 2368 port@0 {
3227 2369 reg = <0>;
3228 2370 dpu_intf1_out: endpoint {
3229 !! 2371 remote-endpoint = <&dsi0_in>;
3230 <<
3231 }; <<
3232 <<
3233 port@ <<
3234 <<
3235 <<
3236 <<
3237 2372 };
3238 }; 2373 };
3239 }; 2374 };
3240 <<
3241 mdp_opp_table <<
3242 compa <<
3243 <<
3244 opp-2 <<
3245 <<
3246 <<
3247 }; <<
3248 <<
3249 opp-3 <<
3250 <<
3251 <<
3252 }; <<
3253 <<
3254 opp-3 <<
3255 <<
3256 <<
3257 }; <<
3258 <<
3259 opp-4 <<
3260 <<
3261 <<
3262 }; <<
3263 }; <<
3264 }; 2375 };
3265 2376
3266 mdss_dsi0: dsi@ae9400 !! 2377 dsi0: dsi@ae94000 {
3267 compatible = !! 2378 compatible = "qcom,mdss-dsi-ctrl";
3268 <<
3269 reg = <0 0x0a 2379 reg = <0 0x0ae94000 0 0x400>;
3270 reg-names = " 2380 reg-names = "dsi_ctrl";
3271 2381
3272 interrupt-par 2382 interrupt-parent = <&mdss>;
3273 interrupts = 2383 interrupts = <4>;
3274 2384
3275 clocks = <&di 2385 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
3276 <&di 2386 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
3277 <&di 2387 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
3278 <&di 2388 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
3279 <&di 2389 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3280 <&gc 2390 <&gcc GCC_DISP_HF_AXI_CLK>;
3281 clock-names = 2391 clock-names = "byte",
3282 2392 "byte_intf",
3283 2393 "pixel",
3284 2394 "core",
3285 2395 "iface",
3286 2396 "bus";
3287 2397
3288 assigned-cloc !! 2398 phys = <&dsi_phy>;
3289 assigned-cloc !! 2399 phy-names = "dsi";
3290 <<
3291 operating-poi <<
3292 power-domains <<
3293 <<
3294 phys = <&mdss <<
3295 2400
3296 #address-cell 2401 #address-cells = <1>;
3297 #size-cells = 2402 #size-cells = <0>;
3298 2403
3299 status = "dis 2404 status = "disabled";
3300 2405
3301 ports { 2406 ports {
3302 #addr 2407 #address-cells = <1>;
3303 #size 2408 #size-cells = <0>;
3304 2409
3305 port@ 2410 port@0 {
3306 2411 reg = <0>;
3307 !! 2412 dsi0_in: endpoint {
3308 2413 remote-endpoint = <&dpu_intf1_out>;
3309 2414 };
3310 }; 2415 };
3311 2416
3312 port@ 2417 port@1 {
3313 2418 reg = <1>;
3314 !! 2419 dsi0_out: endpoint {
3315 2420 };
3316 }; 2421 };
3317 }; 2422 };
3318 <<
3319 dsi_opp_table <<
3320 compa <<
3321 <<
3322 opp-1 <<
3323 <<
3324 <<
3325 }; <<
3326 <<
3327 opp-3 <<
3328 <<
3329 <<
3330 }; <<
3331 <<
3332 opp-3 <<
3333 <<
3334 <<
3335 }; <<
3336 }; <<
3337 }; 2423 };
3338 2424
3339 mdss_dsi0_phy: phy@ae !! 2425 dsi_phy: dsi-phy@ae94400 {
3340 compatible = 2426 compatible = "qcom,dsi-phy-10nm";
3341 reg = <0 0x0a 2427 reg = <0 0x0ae94400 0 0x200>,
3342 <0 0x0a 2428 <0 0x0ae94600 0 0x280>,
3343 <0 0x0a 2429 <0 0x0ae94a00 0 0x1e0>;
3344 reg-names = " 2430 reg-names = "dsi_phy",
3345 " 2431 "dsi_phy_lane",
3346 " 2432 "dsi_pll";
3347 2433
3348 #clock-cells 2434 #clock-cells = <1>;
3349 #phy-cells = 2435 #phy-cells = <0>;
3350 2436
3351 clocks = <&di 2437 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3352 <&rp 2438 <&rpmhcc RPMH_CXO_CLK>;
3353 clock-names = 2439 clock-names = "iface", "ref";
3354 2440
3355 status = "dis 2441 status = "disabled";
3356 }; 2442 };
3357 <<
3358 mdss_dp: displayport- <<
3359 compatible = <<
3360 status = "dis <<
3361 <<
3362 reg = <0 0x0a <<
3363 <0 0x0a <<
3364 <0 0x0a <<
3365 <0 0x0a <<
3366 <0 0x0a <<
3367 <<
3368 interrupt-par <<
3369 interrupts = <<
3370 <<
3371 clocks = <&di <<
3372 <&di <<
3373 <&di <<
3374 <&di <<
3375 <&di <<
3376 clock-names = <<
3377 <<
3378 assigned-cloc <<
3379 <<
3380 assigned-cloc <<
3381 <<
3382 phys = <&usb_ <<
3383 phy-names = " <<
3384 <<
3385 operating-poi <<
3386 power-domains <<
3387 <<
3388 #sound-dai-ce <<
3389 <<
3390 ports { <<
3391 #addr <<
3392 #size <<
3393 port@ <<
3394 <<
3395 <<
3396 <<
3397 <<
3398 }; <<
3399 <<
3400 port@ <<
3401 <<
3402 <<
3403 }; <<
3404 }; <<
3405 <<
3406 dp_opp_table: <<
3407 compa <<
3408 <<
3409 opp-1 <<
3410 <<
3411 <<
3412 }; <<
3413 <<
3414 opp-2 <<
3415 <<
3416 <<
3417 }; <<
3418 <<
3419 opp-5 <<
3420 <<
3421 <<
3422 }; <<
3423 <<
3424 opp-8 <<
3425 <<
3426 <<
3427 }; <<
3428 }; <<
3429 }; <<
3430 }; 2443 };
3431 2444
3432 dispcc: clock-controller@af00 2445 dispcc: clock-controller@af00000 {
3433 compatible = "qcom,sc 2446 compatible = "qcom,sc7180-dispcc";
3434 reg = <0 0x0af00000 0 2447 reg = <0 0x0af00000 0 0x200000>;
3435 clocks = <&rpmhcc RPM 2448 clocks = <&rpmhcc RPMH_CXO_CLK>,
3436 <&gcc GCC_DI 2449 <&gcc GCC_DISP_GPLL0_CLK_SRC>,
3437 <&mdss_dsi0_ !! 2450 <&dsi_phy 0>,
3438 <&mdss_dsi0_ !! 2451 <&dsi_phy 1>,
3439 <&usb_1_qmpp !! 2452 <0>,
3440 <&usb_1_qmpp !! 2453 <0>;
3441 clock-names = "bi_tcx 2454 clock-names = "bi_tcxo",
3442 "gcc_di 2455 "gcc_disp_gpll0_clk_src",
3443 "dsi0_p 2456 "dsi0_phy_pll_out_byteclk",
3444 "dsi0_p 2457 "dsi0_phy_pll_out_dsiclk",
3445 "dp_phy 2458 "dp_phy_pll_link_clk",
3446 "dp_phy 2459 "dp_phy_pll_vco_div_clk";
3447 #clock-cells = <1>; 2460 #clock-cells = <1>;
3448 #reset-cells = <1>; 2461 #reset-cells = <1>;
3449 #power-domain-cells = 2462 #power-domain-cells = <1>;
3450 }; 2463 };
3451 2464
3452 pdc: interrupt-controller@b22 2465 pdc: interrupt-controller@b220000 {
3453 compatible = "qcom,sc 2466 compatible = "qcom,sc7180-pdc", "qcom,pdc";
3454 reg = <0 0x0b220000 0 2467 reg = <0 0x0b220000 0 0x30000>;
3455 qcom,pdc-ranges = <0 2468 qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>;
3456 #interrupt-cells = <2 2469 #interrupt-cells = <2>;
3457 interrupt-parent = <& 2470 interrupt-parent = <&intc>;
3458 interrupt-controller; 2471 interrupt-controller;
3459 }; 2472 };
3460 2473
3461 pdc_reset: reset-controller@b 2474 pdc_reset: reset-controller@b2e0000 {
3462 compatible = "qcom,sc 2475 compatible = "qcom,sc7180-pdc-global", "qcom,sdm845-pdc-global";
3463 reg = <0 0x0b2e0000 0 2476 reg = <0 0x0b2e0000 0 0x20000>;
3464 #reset-cells = <1>; 2477 #reset-cells = <1>;
3465 }; 2478 };
3466 2479
3467 tsens0: thermal-sensor@c26300 2480 tsens0: thermal-sensor@c263000 {
3468 compatible = "qcom,sc 2481 compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
3469 reg = <0 0x0c263000 0 2482 reg = <0 0x0c263000 0 0x1ff>, /* TM */
3470 <0 0x0c222000 2483 <0 0x0c222000 0 0x1ff>; /* SROT */
3471 #qcom,sensors = <15>; 2484 #qcom,sensors = <15>;
3472 interrupts = <GIC_SPI 2485 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
3473 <GIC_SPI 2486 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
3474 interrupt-names = "up 2487 interrupt-names = "uplow","critical";
3475 #thermal-sensor-cells 2488 #thermal-sensor-cells = <1>;
3476 }; 2489 };
3477 2490
3478 tsens1: thermal-sensor@c26500 2491 tsens1: thermal-sensor@c265000 {
3479 compatible = "qcom,sc 2492 compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
3480 reg = <0 0x0c265000 0 2493 reg = <0 0x0c265000 0 0x1ff>, /* TM */
3481 <0 0x0c223000 2494 <0 0x0c223000 0 0x1ff>; /* SROT */
3482 #qcom,sensors = <10>; 2495 #qcom,sensors = <10>;
3483 interrupts = <GIC_SPI 2496 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
3484 <GIC_SPI 2497 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
3485 interrupt-names = "up 2498 interrupt-names = "uplow","critical";
3486 #thermal-sensor-cells 2499 #thermal-sensor-cells = <1>;
3487 }; 2500 };
3488 2501
3489 aoss_reset: reset-controller@ 2502 aoss_reset: reset-controller@c2a0000 {
3490 compatible = "qcom,sc 2503 compatible = "qcom,sc7180-aoss-cc", "qcom,sdm845-aoss-cc";
3491 reg = <0 0x0c2a0000 0 2504 reg = <0 0x0c2a0000 0 0x31000>;
3492 #reset-cells = <1>; 2505 #reset-cells = <1>;
3493 }; 2506 };
3494 2507
3495 aoss_qmp: power-management@c3 !! 2508 aoss_qmp: qmp@c300000 {
3496 compatible = "qcom,sc !! 2509 compatible = "qcom,sc7180-aoss-qmp";
3497 reg = <0 0x0c300000 0 !! 2510 reg = <0 0x0c300000 0 0x100000>;
3498 interrupts = <GIC_SPI 2511 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
3499 mboxes = <&apss_share 2512 mboxes = <&apss_shared 0>;
3500 2513
3501 #clock-cells = <0>; 2514 #clock-cells = <0>;
3502 }; !! 2515 #power-domain-cells = <1>;
3503 <<
3504 sram@c3f0000 { <<
3505 compatible = "qcom,rp <<
3506 reg = <0 0x0c3f0000 0 <<
3507 }; 2516 };
3508 2517
3509 spmi_bus: spmi@c440000 { 2518 spmi_bus: spmi@c440000 {
3510 compatible = "qcom,sp 2519 compatible = "qcom,spmi-pmic-arb";
3511 reg = <0 0x0c440000 0 2520 reg = <0 0x0c440000 0 0x1100>,
3512 <0 0x0c600000 0 2521 <0 0x0c600000 0 0x2000000>,
3513 <0 0x0e600000 0 2522 <0 0x0e600000 0 0x100000>,
3514 <0 0x0e700000 0 2523 <0 0x0e700000 0 0xa0000>,
3515 <0 0x0c40a000 0 2524 <0 0x0c40a000 0 0x26000>;
3516 reg-names = "core", " 2525 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3517 interrupt-names = "pe 2526 interrupt-names = "periph_irq";
3518 interrupts-extended = 2527 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3519 qcom,ee = <0>; 2528 qcom,ee = <0>;
3520 qcom,channel = <0>; 2529 qcom,channel = <0>;
3521 #address-cells = <2>; <<
3522 #size-cells = <0>; <<
3523 interrupt-controller; <<
3524 #interrupt-cells = <4 <<
3525 }; <<
3526 <<
3527 sram@146aa000 { <<
3528 compatible = "qcom,sc <<
3529 reg = <0 0x146aa000 0 <<
3530 <<
3531 #address-cells = <1>; 2530 #address-cells = <1>;
3532 #size-cells = <1>; 2531 #size-cells = <1>;
3533 !! 2532 interrupt-controller;
3534 ranges = <0 0 0x146aa !! 2533 #interrupt-cells = <4>;
3535 !! 2534 cell-index = <0>;
3536 pil-reloc@94c { <<
3537 compatible = <<
3538 reg = <0x94c <<
3539 }; <<
3540 }; 2535 };
3541 2536
3542 apps_smmu: iommu@15000000 { 2537 apps_smmu: iommu@15000000 {
3543 compatible = "qcom,sc 2538 compatible = "qcom,sc7180-smmu-500", "arm,mmu-500";
3544 reg = <0 0x15000000 0 2539 reg = <0 0x15000000 0 0x100000>;
3545 #iommu-cells = <2>; 2540 #iommu-cells = <2>;
3546 #global-interrupts = 2541 #global-interrupts = <1>;
3547 interrupts = <GIC_SPI 2542 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
3548 <GIC_SPI 2543 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
3549 <GIC_SPI 2544 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
3550 <GIC_SPI 2545 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
3551 <GIC_SPI 2546 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
3552 <GIC_SPI 2547 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
3553 <GIC_SPI 2548 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
3554 <GIC_SPI 2549 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
3555 <GIC_SPI 2550 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
3556 <GIC_SPI 2551 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
3557 <GIC_SPI 2552 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
3558 <GIC_SPI 2553 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
3559 <GIC_SPI 2554 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
3560 <GIC_SPI 2555 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
3561 <GIC_SPI 2556 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
3562 <GIC_SPI 2557 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
3563 <GIC_SPI 2558 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
3564 <GIC_SPI 2559 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
3565 <GIC_SPI 2560 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
3566 <GIC_SPI 2561 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
3567 <GIC_SPI 2562 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
3568 <GIC_SPI 2563 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
3569 <GIC_SPI 2564 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
3570 <GIC_SPI 2565 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
3571 <GIC_SPI 2566 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
3572 <GIC_SPI 2567 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
3573 <GIC_SPI 2568 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
3574 <GIC_SPI 2569 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
3575 <GIC_SPI 2570 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
3576 <GIC_SPI 2571 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
3577 <GIC_SPI 2572 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
3578 <GIC_SPI 2573 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
3579 <GIC_SPI 2574 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
3580 <GIC_SPI 2575 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
3581 <GIC_SPI 2576 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
3582 <GIC_SPI 2577 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
3583 <GIC_SPI 2578 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
3584 <GIC_SPI 2579 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
3585 <GIC_SPI 2580 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
3586 <GIC_SPI 2581 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
3587 <GIC_SPI 2582 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
3588 <GIC_SPI 2583 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
3589 <GIC_SPI 2584 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
3590 <GIC_SPI 2585 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
3591 <GIC_SPI 2586 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
3592 <GIC_SPI 2587 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
3593 <GIC_SPI 2588 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
3594 <GIC_SPI 2589 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
3595 <GIC_SPI 2590 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
3596 <GIC_SPI 2591 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
3597 <GIC_SPI 2592 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
3598 <GIC_SPI 2593 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
3599 <GIC_SPI 2594 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
3600 <GIC_SPI 2595 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
3601 <GIC_SPI 2596 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
3602 <GIC_SPI 2597 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
3603 <GIC_SPI 2598 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
3604 <GIC_SPI 2599 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
3605 <GIC_SPI 2600 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
3606 <GIC_SPI 2601 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
3607 <GIC_SPI 2602 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
3608 <GIC_SPI 2603 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
3609 <GIC_SPI 2604 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
3610 <GIC_SPI 2605 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
3611 <GIC_SPI 2606 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
3612 <GIC_SPI 2607 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
3613 <GIC_SPI 2608 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
3614 <GIC_SPI 2609 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
3615 <GIC_SPI 2610 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
3616 <GIC_SPI 2611 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
3617 <GIC_SPI 2612 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
3618 <GIC_SPI 2613 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
3619 <GIC_SPI 2614 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
3620 <GIC_SPI 2615 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
3621 <GIC_SPI 2616 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
3622 <GIC_SPI 2617 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
3623 <GIC_SPI 2618 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
3624 <GIC_SPI 2619 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
3625 <GIC_SPI 2620 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
3626 <GIC_SPI 2621 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
3627 <GIC_SPI 2622 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
3628 }; 2623 };
3629 2624
3630 intc: interrupt-controller@17 2625 intc: interrupt-controller@17a00000 {
3631 compatible = "arm,gic 2626 compatible = "arm,gic-v3";
3632 #address-cells = <2>; 2627 #address-cells = <2>;
3633 #size-cells = <2>; 2628 #size-cells = <2>;
3634 ranges; 2629 ranges;
3635 #interrupt-cells = <3 2630 #interrupt-cells = <3>;
3636 interrupt-controller; 2631 interrupt-controller;
3637 reg = <0 0x17a00000 0 2632 reg = <0 0x17a00000 0 0x10000>, /* GICD */
3638 <0 0x17a60000 0 2633 <0 0x17a60000 0 0x100000>; /* GICR * 8 */
3639 interrupts = <GIC_PPI 2634 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3640 2635
3641 msi-controller@17a400 2636 msi-controller@17a40000 {
3642 compatible = 2637 compatible = "arm,gic-v3-its";
3643 msi-controlle 2638 msi-controller;
3644 #msi-cells = 2639 #msi-cells = <1>;
3645 reg = <0 0x17 2640 reg = <0 0x17a40000 0 0x20000>;
3646 status = "dis 2641 status = "disabled";
3647 }; 2642 };
3648 }; 2643 };
3649 2644
3650 apss_shared: mailbox@17c00000 2645 apss_shared: mailbox@17c00000 {
3651 compatible = "qcom,sc !! 2646 compatible = "qcom,sc7180-apss-shared";
3652 "qcom,sd <<
3653 reg = <0 0x17c00000 0 2647 reg = <0 0x17c00000 0 0x10000>;
3654 #mbox-cells = <1>; 2648 #mbox-cells = <1>;
3655 }; 2649 };
3656 2650
3657 watchdog@17c10000 { 2651 watchdog@17c10000 {
3658 compatible = "qcom,ap 2652 compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt";
3659 reg = <0 0x17c10000 0 2653 reg = <0 0x17c10000 0 0x1000>;
3660 clocks = <&sleep_clk> 2654 clocks = <&sleep_clk>;
3661 interrupts = <GIC_SPI <<
3662 }; 2655 };
3663 2656
3664 timer@17c20000 { !! 2657 timer@17c20000{
3665 #address-cells = <1>; !! 2658 #address-cells = <2>;
3666 #size-cells = <1>; !! 2659 #size-cells = <2>;
3667 ranges = <0 0 0 0x200 !! 2660 ranges;
3668 compatible = "arm,arm 2661 compatible = "arm,armv7-timer-mem";
3669 reg = <0 0x17c20000 0 2662 reg = <0 0x17c20000 0 0x1000>;
3670 2663
3671 frame@17c21000 { 2664 frame@17c21000 {
3672 frame-number 2665 frame-number = <0>;
3673 interrupts = 2666 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
3674 2667 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
3675 reg = <0x17c2 !! 2668 reg = <0 0x17c21000 0 0x1000>,
3676 <0x17c2 !! 2669 <0 0x17c22000 0 0x1000>;
3677 }; 2670 };
3678 2671
3679 frame@17c23000 { 2672 frame@17c23000 {
3680 frame-number 2673 frame-number = <1>;
3681 interrupts = 2674 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
3682 reg = <0x17c2 !! 2675 reg = <0 0x17c23000 0 0x1000>;
3683 status = "dis 2676 status = "disabled";
3684 }; 2677 };
3685 2678
3686 frame@17c25000 { 2679 frame@17c25000 {
3687 frame-number 2680 frame-number = <2>;
3688 interrupts = 2681 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
3689 reg = <0x17c2 !! 2682 reg = <0 0x17c25000 0 0x1000>;
3690 status = "dis 2683 status = "disabled";
3691 }; 2684 };
3692 2685
3693 frame@17c27000 { 2686 frame@17c27000 {
3694 frame-number 2687 frame-number = <3>;
3695 interrupts = 2688 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3696 reg = <0x17c2 !! 2689 reg = <0 0x17c27000 0 0x1000>;
3697 status = "dis 2690 status = "disabled";
3698 }; 2691 };
3699 2692
3700 frame@17c29000 { 2693 frame@17c29000 {
3701 frame-number 2694 frame-number = <4>;
3702 interrupts = 2695 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3703 reg = <0x17c2 !! 2696 reg = <0 0x17c29000 0 0x1000>;
3704 status = "dis 2697 status = "disabled";
3705 }; 2698 };
3706 2699
3707 frame@17c2b000 { 2700 frame@17c2b000 {
3708 frame-number 2701 frame-number = <5>;
3709 interrupts = 2702 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3710 reg = <0x17c2 !! 2703 reg = <0 0x17c2b000 0 0x1000>;
3711 status = "dis 2704 status = "disabled";
3712 }; 2705 };
3713 2706
3714 frame@17c2d000 { 2707 frame@17c2d000 {
3715 frame-number 2708 frame-number = <6>;
3716 interrupts = 2709 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
3717 reg = <0x17c2 !! 2710 reg = <0 0x17c2d000 0 0x1000>;
3718 status = "dis 2711 status = "disabled";
3719 }; 2712 };
3720 }; 2713 };
3721 2714
3722 apps_rsc: rsc@18200000 { 2715 apps_rsc: rsc@18200000 {
3723 compatible = "qcom,rp 2716 compatible = "qcom,rpmh-rsc";
3724 reg = <0 0x18200000 0 2717 reg = <0 0x18200000 0 0x10000>,
3725 <0 0x18210000 0 2718 <0 0x18210000 0 0x10000>,
3726 <0 0x18220000 0 2719 <0 0x18220000 0 0x10000>;
3727 reg-names = "drv-0", 2720 reg-names = "drv-0", "drv-1", "drv-2";
3728 interrupts = <GIC_SPI 2721 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
3729 <GIC_SPI 2722 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
3730 <GIC_SPI 2723 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
3731 qcom,tcs-offset = <0x 2724 qcom,tcs-offset = <0xd00>;
3732 qcom,drv-id = <2>; 2725 qcom,drv-id = <2>;
3733 qcom,tcs-config = <AC 2726 qcom,tcs-config = <ACTIVE_TCS 2>,
3734 <SL 2727 <SLEEP_TCS 3>,
3735 <WA 2728 <WAKE_TCS 3>,
3736 <CO 2729 <CONTROL_TCS 1>;
3737 power-domains = <&CLU <<
3738 2730
3739 rpmhcc: clock-control 2731 rpmhcc: clock-controller {
3740 compatible = 2732 compatible = "qcom,sc7180-rpmh-clk";
3741 clocks = <&xo 2733 clocks = <&xo_board>;
3742 clock-names = 2734 clock-names = "xo";
3743 #clock-cells 2735 #clock-cells = <1>;
3744 }; 2736 };
3745 2737
3746 rpmhpd: power-control 2738 rpmhpd: power-controller {
3747 compatible = 2739 compatible = "qcom,sc7180-rpmhpd";
3748 #power-domain 2740 #power-domain-cells = <1>;
3749 operating-poi 2741 operating-points-v2 = <&rpmhpd_opp_table>;
3750 2742
3751 rpmhpd_opp_ta 2743 rpmhpd_opp_table: opp-table {
3752 compa 2744 compatible = "operating-points-v2";
3753 2745
3754 rpmhp 2746 rpmhpd_opp_ret: opp1 {
3755 2747 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3756 }; 2748 };
3757 2749
3758 rpmhp 2750 rpmhpd_opp_min_svs: opp2 {
3759 2751 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3760 }; 2752 };
3761 2753
3762 rpmhp 2754 rpmhpd_opp_low_svs: opp3 {
3763 2755 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3764 }; 2756 };
3765 2757
3766 rpmhp 2758 rpmhpd_opp_svs: opp4 {
3767 2759 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3768 }; 2760 };
3769 2761
3770 rpmhp 2762 rpmhpd_opp_svs_l1: opp5 {
3771 2763 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3772 }; 2764 };
3773 2765
3774 rpmhp 2766 rpmhpd_opp_svs_l2: opp6 {
3775 2767 opp-level = <224>;
3776 }; 2768 };
3777 2769
3778 rpmhp 2770 rpmhpd_opp_nom: opp7 {
3779 2771 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3780 }; 2772 };
3781 2773
3782 rpmhp 2774 rpmhpd_opp_nom_l1: opp8 {
3783 2775 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3784 }; 2776 };
3785 2777
3786 rpmhp 2778 rpmhpd_opp_nom_l2: opp9 {
3787 2779 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3788 }; 2780 };
3789 2781
3790 rpmhp 2782 rpmhpd_opp_turbo: opp10 {
3791 2783 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3792 }; 2784 };
3793 2785
3794 rpmhp 2786 rpmhpd_opp_turbo_l1: opp11 {
3795 2787 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3796 }; 2788 };
3797 }; 2789 };
3798 }; 2790 };
3799 2791
3800 apps_bcm_voter: bcm-v !! 2792 apps_bcm_voter: bcm_voter {
3801 compatible = 2793 compatible = "qcom,bcm-voter";
3802 }; 2794 };
3803 }; 2795 };
3804 2796
3805 osm_l3: interconnect@18321000 2797 osm_l3: interconnect@18321000 {
3806 compatible = "qcom,sc !! 2798 compatible = "qcom,sc7180-osm-l3";
3807 reg = <0 0x18321000 0 2799 reg = <0 0x18321000 0 0x1400>;
3808 2800
3809 clocks = <&rpmhcc RPM 2801 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3810 clock-names = "xo", " 2802 clock-names = "xo", "alternate";
3811 2803
3812 #interconnect-cells = 2804 #interconnect-cells = <1>;
3813 }; 2805 };
3814 2806
3815 cpufreq_hw: cpufreq@18323000 2807 cpufreq_hw: cpufreq@18323000 {
3816 compatible = "qcom,sc !! 2808 compatible = "qcom,cpufreq-hw";
3817 reg = <0 0x18323000 0 2809 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>;
3818 reg-names = "freq-dom 2810 reg-names = "freq-domain0", "freq-domain1";
3819 2811
3820 clocks = <&rpmhcc RPM 2812 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3821 clock-names = "xo", " 2813 clock-names = "xo", "alternate";
3822 2814
3823 #freq-domain-cells = 2815 #freq-domain-cells = <1>;
3824 #clock-cells = <1>; <<
3825 }; <<
3826 <<
3827 wifi: wifi@18800000 { <<
3828 compatible = "qcom,wc <<
3829 reg = <0 0x18800000 0 <<
3830 reg-names = "membase" <<
3831 iommus = <&apps_smmu <<
3832 interrupts = <<
3833 <GIC_SPI 414 <<
3834 <GIC_SPI 415 <<
3835 <GIC_SPI 416 <<
3836 <GIC_SPI 417 <<
3837 <GIC_SPI 418 <<
3838 <GIC_SPI 419 <<
3839 <GIC_SPI 420 <<
3840 <GIC_SPI 421 <<
3841 <GIC_SPI 422 <<
3842 <GIC_SPI 423 <<
3843 <GIC_SPI 424 <<
3844 <GIC_SPI 425 <<
3845 memory-region = <&wla <<
3846 qcom,msa-fixed-perm; <<
3847 status = "disabled"; <<
3848 }; <<
3849 <<
3850 remoteproc_adsp: remoteproc@6 <<
3851 compatible = "qcom,sc <<
3852 reg = <0 0x62400000 0 <<
3853 <<
3854 interrupts-extended = <<
3855 <<
3856 <<
3857 <<
3858 <<
3859 interrupt-names = "wd <<
3860 "fa <<
3861 "re <<
3862 "ha <<
3863 "st <<
3864 <<
3865 clocks = <&rpmhcc RPM <<
3866 clock-names = "xo"; <<
3867 <<
3868 power-domains = <&rpm <<
3869 <&rpm <<
3870 power-domain-names = <<
3871 <<
3872 qcom,qmp = <&aoss_qmp <<
3873 qcom,smem-states = <& <<
3874 qcom,smem-state-names <<
3875 <<
3876 status = "disabled"; <<
3877 <<
3878 glink-edge { <<
3879 interrupts = <<
3880 label = "lpas <<
3881 qcom,remote-p <<
3882 mboxes = <&ap <<
3883 <<
3884 apr { <<
3885 compa <<
3886 qcom, <<
3887 qcom, <<
3888 #addr <<
3889 #size <<
3890 <<
3891 servi <<
3892 <<
3893 <<
3894 <<
3895 }; <<
3896 <<
3897 q6afe <<
3898 <<
3899 <<
3900 <<
3901 <<
3902 <<
3903 <<
3904 <<
3905 <<
3906 <<
3907 <<
3908 <<
3909 <<
3910 <<
3911 <<
3912 <<
3913 }; <<
3914 <<
3915 q6asm <<
3916 <<
3917 <<
3918 <<
3919 <<
3920 <<
3921 <<
3922 <<
3923 <<
3924 <<
3925 <<
3926 <<
3927 }; <<
3928 <<
3929 q6adm <<
3930 <<
3931 <<
3932 <<
3933 <<
3934 <<
3935 <<
3936 <<
3937 <<
3938 }; <<
3939 }; <<
3940 <<
3941 fastrpc { <<
3942 compa <<
3943 qcom, <<
3944 label <<
3945 #addr <<
3946 #size <<
3947 <<
3948 compu <<
3949 <<
3950 <<
3951 <<
3952 }; <<
3953 <<
3954 compu <<
3955 <<
3956 <<
3957 <<
3958 }; <<
3959 <<
3960 compu <<
3961 <<
3962 <<
3963 <<
3964 <<
3965 }; <<
3966 }; <<
3967 }; <<
3968 }; <<
3969 <<
3970 lpasscc: clock-controller@62d <<
3971 compatible = "qcom,sc <<
3972 reg = <0 0x62d00000 0 <<
3973 <0 0x62780000 0 <<
3974 reg-names = "lpass_co <<
3975 clocks = <&gcc GCC_LP <<
3976 <&rpmhcc RPM <<
3977 clock-names = "iface" <<
3978 power-domains = <&lpa <<
3979 #clock-cells = <1>; <<
3980 #power-domain-cells = <<
3981 <<
3982 status = "reserved"; <<
3983 }; <<
3984 <<
3985 lpass_cpu: lpass@62d87000 { <<
3986 compatible = "qcom,sc <<
3987 <<
3988 reg = <0 0x62d87000 0 <<
3989 reg-names = "lpass-hd <<
3990 <<
3991 iommus = <&apps_smmu <<
3992 <&apps_smmu 0 <<
3993 <&apps_smmu 0 <<
3994 <<
3995 power-domains = <&lpa <<
3996 required-opps = <&rpm <<
3997 <<
3998 status = "disabled"; <<
3999 <<
4000 clocks = <&gcc GCC_LP <<
4001 <&lpasscc LP <<
4002 <&lpasscc LP <<
4003 <&lpasscc LP <<
4004 <&lpasscc LP <<
4005 <&lpasscc LP <<
4006 <<
4007 clock-names = "pcnoc- <<
4008 "mclk <<
4009 "mi2s <<
4010 <<
4011 <<
4012 #sound-dai-cells = <1 <<
4013 #address-cells = <1>; <<
4014 #size-cells = <0>; <<
4015 <<
4016 interrupts = <GIC_SPI <<
4017 <GIC_ <<
4018 interrupt-names = "lp <<
4019 }; <<
4020 <<
4021 lpass_hm: clock-controller@63 <<
4022 compatible = "qcom,sc <<
4023 reg = <0 0x63000000 0 <<
4024 clocks = <&gcc GCC_LP <<
4025 <&rpmhcc RPM <<
4026 clock-names = "iface" <<
4027 power-domains = <&rpm <<
4028 <<
4029 #clock-cells = <1>; <<
4030 #power-domain-cells = <<
4031 <<
4032 status = "reserved"; <<
4033 }; 2816 };
4034 }; 2817 };
4035 2818
4036 thermal-zones { 2819 thermal-zones {
4037 cpu0_thermal: cpu0-thermal { !! 2820 cpu0-thermal {
4038 polling-delay-passive !! 2821 polling-delay-passive = <0>;
>> 2822 polling-delay = <0>;
4039 2823
4040 thermal-sensors = <&t 2824 thermal-sensors = <&tsens0 1>;
4041 sustainable-power = < <<
4042 2825
4043 trips { 2826 trips {
4044 cpu0_alert0: 2827 cpu0_alert0: trip-point0 {
4045 tempe 2828 temperature = <90000>;
4046 hyste 2829 hysteresis = <2000>;
4047 type 2830 type = "passive";
4048 }; 2831 };
4049 2832
4050 cpu0_alert1: 2833 cpu0_alert1: trip-point1 {
4051 tempe 2834 temperature = <95000>;
4052 hyste 2835 hysteresis = <2000>;
4053 type 2836 type = "passive";
4054 }; 2837 };
4055 2838
4056 cpu0_crit: cp !! 2839 cpu0_crit: cpu_crit {
4057 tempe 2840 temperature = <110000>;
4058 hyste 2841 hysteresis = <1000>;
4059 type 2842 type = "critical";
4060 }; 2843 };
4061 }; 2844 };
4062 2845
4063 cooling-maps { 2846 cooling-maps {
4064 map0 { 2847 map0 {
4065 trip 2848 trip = <&cpu0_alert0>;
4066 cooli 2849 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4067 2850 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4068 2851 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4069 2852 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4070 2853 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4071 2854 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4072 }; 2855 };
4073 map1 { 2856 map1 {
4074 trip 2857 trip = <&cpu0_alert1>;
4075 cooli 2858 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4076 2859 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4077 2860 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4078 2861 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4079 2862 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4080 2863 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4081 }; 2864 };
4082 }; 2865 };
4083 }; 2866 };
4084 2867
4085 cpu1_thermal: cpu1-thermal { !! 2868 cpu1-thermal {
4086 polling-delay-passive !! 2869 polling-delay-passive = <0>;
>> 2870 polling-delay = <0>;
4087 2871
4088 thermal-sensors = <&t 2872 thermal-sensors = <&tsens0 2>;
4089 sustainable-power = < <<
4090 2873
4091 trips { 2874 trips {
4092 cpu1_alert0: 2875 cpu1_alert0: trip-point0 {
4093 tempe 2876 temperature = <90000>;
4094 hyste 2877 hysteresis = <2000>;
4095 type 2878 type = "passive";
4096 }; 2879 };
4097 2880
4098 cpu1_alert1: 2881 cpu1_alert1: trip-point1 {
4099 tempe 2882 temperature = <95000>;
4100 hyste 2883 hysteresis = <2000>;
4101 type 2884 type = "passive";
4102 }; 2885 };
4103 2886
4104 cpu1_crit: cp !! 2887 cpu1_crit: cpu_crit {
4105 tempe 2888 temperature = <110000>;
4106 hyste 2889 hysteresis = <1000>;
4107 type 2890 type = "critical";
4108 }; 2891 };
4109 }; 2892 };
4110 2893
4111 cooling-maps { 2894 cooling-maps {
4112 map0 { 2895 map0 {
4113 trip 2896 trip = <&cpu1_alert0>;
4114 cooli 2897 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4115 2898 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4116 2899 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4117 2900 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4118 2901 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4119 2902 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4120 }; 2903 };
4121 map1 { 2904 map1 {
4122 trip 2905 trip = <&cpu1_alert1>;
4123 cooli 2906 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4124 2907 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4125 2908 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4126 2909 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4127 2910 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4128 2911 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4129 }; 2912 };
4130 }; 2913 };
4131 }; 2914 };
4132 2915
4133 cpu2_thermal: cpu2-thermal { !! 2916 cpu2-thermal {
4134 polling-delay-passive !! 2917 polling-delay-passive = <0>;
>> 2918 polling-delay = <0>;
4135 2919
4136 thermal-sensors = <&t 2920 thermal-sensors = <&tsens0 3>;
4137 sustainable-power = < <<
4138 2921
4139 trips { 2922 trips {
4140 cpu2_alert0: 2923 cpu2_alert0: trip-point0 {
4141 tempe 2924 temperature = <90000>;
4142 hyste 2925 hysteresis = <2000>;
4143 type 2926 type = "passive";
4144 }; 2927 };
4145 2928
4146 cpu2_alert1: 2929 cpu2_alert1: trip-point1 {
4147 tempe 2930 temperature = <95000>;
4148 hyste 2931 hysteresis = <2000>;
4149 type 2932 type = "passive";
4150 }; 2933 };
4151 2934
4152 cpu2_crit: cp !! 2935 cpu2_crit: cpu_crit {
4153 tempe 2936 temperature = <110000>;
4154 hyste 2937 hysteresis = <1000>;
4155 type 2938 type = "critical";
4156 }; 2939 };
4157 }; 2940 };
4158 2941
4159 cooling-maps { 2942 cooling-maps {
4160 map0 { 2943 map0 {
4161 trip 2944 trip = <&cpu2_alert0>;
4162 cooli 2945 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4163 2946 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4164 2947 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4165 2948 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4166 2949 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4167 2950 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4168 }; 2951 };
4169 map1 { 2952 map1 {
4170 trip 2953 trip = <&cpu2_alert1>;
4171 cooli 2954 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4172 2955 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4173 2956 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4174 2957 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4175 2958 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4176 2959 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4177 }; 2960 };
4178 }; 2961 };
4179 }; 2962 };
4180 2963
4181 cpu3_thermal: cpu3-thermal { !! 2964 cpu3-thermal {
4182 polling-delay-passive !! 2965 polling-delay-passive = <0>;
>> 2966 polling-delay = <0>;
4183 2967
4184 thermal-sensors = <&t 2968 thermal-sensors = <&tsens0 4>;
4185 sustainable-power = < <<
4186 2969
4187 trips { 2970 trips {
4188 cpu3_alert0: 2971 cpu3_alert0: trip-point0 {
4189 tempe 2972 temperature = <90000>;
4190 hyste 2973 hysteresis = <2000>;
4191 type 2974 type = "passive";
4192 }; 2975 };
4193 2976
4194 cpu3_alert1: 2977 cpu3_alert1: trip-point1 {
4195 tempe 2978 temperature = <95000>;
4196 hyste 2979 hysteresis = <2000>;
4197 type 2980 type = "passive";
4198 }; 2981 };
4199 2982
4200 cpu3_crit: cp !! 2983 cpu3_crit: cpu_crit {
4201 tempe 2984 temperature = <110000>;
4202 hyste 2985 hysteresis = <1000>;
4203 type 2986 type = "critical";
4204 }; 2987 };
4205 }; 2988 };
4206 2989
4207 cooling-maps { 2990 cooling-maps {
4208 map0 { 2991 map0 {
4209 trip 2992 trip = <&cpu3_alert0>;
4210 cooli 2993 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4211 2994 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4212 2995 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4213 2996 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4214 2997 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4215 2998 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4216 }; 2999 };
4217 map1 { 3000 map1 {
4218 trip 3001 trip = <&cpu3_alert1>;
4219 cooli 3002 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4220 3003 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4221 3004 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4222 3005 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4223 3006 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4224 3007 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4225 }; 3008 };
4226 }; 3009 };
4227 }; 3010 };
4228 3011
4229 cpu4_thermal: cpu4-thermal { !! 3012 cpu4-thermal {
4230 polling-delay-passive !! 3013 polling-delay-passive = <0>;
>> 3014 polling-delay = <0>;
4231 3015
4232 thermal-sensors = <&t 3016 thermal-sensors = <&tsens0 5>;
4233 sustainable-power = < <<
4234 3017
4235 trips { 3018 trips {
4236 cpu4_alert0: 3019 cpu4_alert0: trip-point0 {
4237 tempe 3020 temperature = <90000>;
4238 hyste 3021 hysteresis = <2000>;
4239 type 3022 type = "passive";
4240 }; 3023 };
4241 3024
4242 cpu4_alert1: 3025 cpu4_alert1: trip-point1 {
4243 tempe 3026 temperature = <95000>;
4244 hyste 3027 hysteresis = <2000>;
4245 type 3028 type = "passive";
4246 }; 3029 };
4247 3030
4248 cpu4_crit: cp !! 3031 cpu4_crit: cpu_crit {
4249 tempe 3032 temperature = <110000>;
4250 hyste 3033 hysteresis = <1000>;
4251 type 3034 type = "critical";
4252 }; 3035 };
4253 }; 3036 };
4254 3037
4255 cooling-maps { 3038 cooling-maps {
4256 map0 { 3039 map0 {
4257 trip 3040 trip = <&cpu4_alert0>;
4258 cooli 3041 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4259 3042 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4260 3043 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4261 3044 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4262 3045 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4263 3046 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4264 }; 3047 };
4265 map1 { 3048 map1 {
4266 trip 3049 trip = <&cpu4_alert1>;
4267 cooli 3050 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4268 3051 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4269 3052 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4270 3053 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4271 3054 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4272 3055 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4273 }; 3056 };
4274 }; 3057 };
4275 }; 3058 };
4276 3059
4277 cpu5_thermal: cpu5-thermal { !! 3060 cpu5-thermal {
4278 polling-delay-passive !! 3061 polling-delay-passive = <0>;
>> 3062 polling-delay = <0>;
4279 3063
4280 thermal-sensors = <&t 3064 thermal-sensors = <&tsens0 6>;
4281 sustainable-power = < <<
4282 3065
4283 trips { 3066 trips {
4284 cpu5_alert0: 3067 cpu5_alert0: trip-point0 {
4285 tempe 3068 temperature = <90000>;
4286 hyste 3069 hysteresis = <2000>;
4287 type 3070 type = "passive";
4288 }; 3071 };
4289 3072
4290 cpu5_alert1: 3073 cpu5_alert1: trip-point1 {
4291 tempe 3074 temperature = <95000>;
4292 hyste 3075 hysteresis = <2000>;
4293 type 3076 type = "passive";
4294 }; 3077 };
4295 3078
4296 cpu5_crit: cp !! 3079 cpu5_crit: cpu_crit {
4297 tempe 3080 temperature = <110000>;
4298 hyste 3081 hysteresis = <1000>;
4299 type 3082 type = "critical";
4300 }; 3083 };
4301 }; 3084 };
4302 3085
4303 cooling-maps { 3086 cooling-maps {
4304 map0 { 3087 map0 {
4305 trip 3088 trip = <&cpu5_alert0>;
4306 cooli 3089 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4307 3090 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4308 3091 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4309 3092 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4310 3093 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4311 3094 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4312 }; 3095 };
4313 map1 { 3096 map1 {
4314 trip 3097 trip = <&cpu5_alert1>;
4315 cooli 3098 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4316 3099 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4317 3100 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4318 3101 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4319 3102 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4320 3103 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4321 }; 3104 };
4322 }; 3105 };
4323 }; 3106 };
4324 3107
4325 cpu6_thermal: cpu6-thermal { !! 3108 cpu6-thermal {
4326 polling-delay-passive !! 3109 polling-delay-passive = <0>;
>> 3110 polling-delay = <0>;
4327 3111
4328 thermal-sensors = <&t 3112 thermal-sensors = <&tsens0 9>;
4329 sustainable-power = < <<
4330 3113
4331 trips { 3114 trips {
4332 cpu6_alert0: 3115 cpu6_alert0: trip-point0 {
4333 tempe 3116 temperature = <90000>;
4334 hyste 3117 hysteresis = <2000>;
4335 type 3118 type = "passive";
4336 }; 3119 };
4337 3120
4338 cpu6_alert1: 3121 cpu6_alert1: trip-point1 {
4339 tempe 3122 temperature = <95000>;
4340 hyste 3123 hysteresis = <2000>;
4341 type 3124 type = "passive";
4342 }; 3125 };
4343 3126
4344 cpu6_crit: cp !! 3127 cpu6_crit: cpu_crit {
4345 tempe 3128 temperature = <110000>;
4346 hyste 3129 hysteresis = <1000>;
4347 type 3130 type = "critical";
4348 }; 3131 };
4349 }; 3132 };
4350 3133
4351 cooling-maps { 3134 cooling-maps {
4352 map0 { 3135 map0 {
4353 trip 3136 trip = <&cpu6_alert0>;
4354 cooli 3137 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4355 3138 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4356 }; 3139 };
4357 map1 { 3140 map1 {
4358 trip 3141 trip = <&cpu6_alert1>;
4359 cooli 3142 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4360 3143 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4361 }; 3144 };
4362 }; 3145 };
4363 }; 3146 };
4364 3147
4365 cpu7_thermal: cpu7-thermal { !! 3148 cpu7-thermal {
4366 polling-delay-passive !! 3149 polling-delay-passive = <0>;
>> 3150 polling-delay = <0>;
4367 3151
4368 thermal-sensors = <&t 3152 thermal-sensors = <&tsens0 10>;
4369 sustainable-power = < <<
4370 3153
4371 trips { 3154 trips {
4372 cpu7_alert0: 3155 cpu7_alert0: trip-point0 {
4373 tempe 3156 temperature = <90000>;
4374 hyste 3157 hysteresis = <2000>;
4375 type 3158 type = "passive";
4376 }; 3159 };
4377 3160
4378 cpu7_alert1: 3161 cpu7_alert1: trip-point1 {
4379 tempe 3162 temperature = <95000>;
4380 hyste 3163 hysteresis = <2000>;
4381 type 3164 type = "passive";
4382 }; 3165 };
4383 3166
4384 cpu7_crit: cp !! 3167 cpu7_crit: cpu_crit {
4385 tempe 3168 temperature = <110000>;
4386 hyste 3169 hysteresis = <1000>;
4387 type 3170 type = "critical";
4388 }; 3171 };
4389 }; 3172 };
4390 3173
4391 cooling-maps { 3174 cooling-maps {
4392 map0 { 3175 map0 {
4393 trip 3176 trip = <&cpu7_alert0>;
4394 cooli 3177 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4395 3178 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4396 }; 3179 };
4397 map1 { 3180 map1 {
4398 trip 3181 trip = <&cpu7_alert1>;
4399 cooli 3182 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4400 3183 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4401 }; 3184 };
4402 }; 3185 };
4403 }; 3186 };
4404 3187
4405 cpu8_thermal: cpu8-thermal { !! 3188 cpu8-thermal {
4406 polling-delay-passive !! 3189 polling-delay-passive = <0>;
>> 3190 polling-delay = <0>;
4407 3191
4408 thermal-sensors = <&t 3192 thermal-sensors = <&tsens0 11>;
4409 sustainable-power = < <<
4410 3193
4411 trips { 3194 trips {
4412 cpu8_alert0: 3195 cpu8_alert0: trip-point0 {
4413 tempe 3196 temperature = <90000>;
4414 hyste 3197 hysteresis = <2000>;
4415 type 3198 type = "passive";
4416 }; 3199 };
4417 3200
4418 cpu8_alert1: 3201 cpu8_alert1: trip-point1 {
4419 tempe 3202 temperature = <95000>;
4420 hyste 3203 hysteresis = <2000>;
4421 type 3204 type = "passive";
4422 }; 3205 };
4423 3206
4424 cpu8_crit: cp !! 3207 cpu8_crit: cpu_crit {
4425 tempe 3208 temperature = <110000>;
4426 hyste 3209 hysteresis = <1000>;
4427 type 3210 type = "critical";
4428 }; 3211 };
4429 }; 3212 };
4430 3213
4431 cooling-maps { 3214 cooling-maps {
4432 map0 { 3215 map0 {
4433 trip 3216 trip = <&cpu8_alert0>;
4434 cooli 3217 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4435 3218 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4436 }; 3219 };
4437 map1 { 3220 map1 {
4438 trip 3221 trip = <&cpu8_alert1>;
4439 cooli 3222 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4440 3223 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4441 }; 3224 };
4442 }; 3225 };
4443 }; 3226 };
4444 3227
4445 cpu9_thermal: cpu9-thermal { !! 3228 cpu9-thermal {
4446 polling-delay-passive !! 3229 polling-delay-passive = <0>;
>> 3230 polling-delay = <0>;
4447 3231
4448 thermal-sensors = <&t 3232 thermal-sensors = <&tsens0 12>;
4449 sustainable-power = < <<
4450 3233
4451 trips { 3234 trips {
4452 cpu9_alert0: 3235 cpu9_alert0: trip-point0 {
4453 tempe 3236 temperature = <90000>;
4454 hyste 3237 hysteresis = <2000>;
4455 type 3238 type = "passive";
4456 }; 3239 };
4457 3240
4458 cpu9_alert1: 3241 cpu9_alert1: trip-point1 {
4459 tempe 3242 temperature = <95000>;
4460 hyste 3243 hysteresis = <2000>;
4461 type 3244 type = "passive";
4462 }; 3245 };
4463 3246
4464 cpu9_crit: cp !! 3247 cpu9_crit: cpu_crit {
4465 tempe 3248 temperature = <110000>;
4466 hyste 3249 hysteresis = <1000>;
4467 type 3250 type = "critical";
4468 }; 3251 };
4469 }; 3252 };
4470 3253
4471 cooling-maps { 3254 cooling-maps {
4472 map0 { 3255 map0 {
4473 trip 3256 trip = <&cpu9_alert0>;
4474 cooli 3257 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4475 3258 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4476 }; 3259 };
4477 map1 { 3260 map1 {
4478 trip 3261 trip = <&cpu9_alert1>;
4479 cooli 3262 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4480 3263 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4481 }; 3264 };
4482 }; 3265 };
4483 }; 3266 };
4484 3267
4485 aoss0-thermal { 3268 aoss0-thermal {
4486 polling-delay-passive !! 3269 polling-delay-passive = <0>;
>> 3270 polling-delay = <0>;
4487 3271
4488 thermal-sensors = <&t 3272 thermal-sensors = <&tsens0 0>;
4489 3273
4490 trips { 3274 trips {
4491 aoss0_alert0: 3275 aoss0_alert0: trip-point0 {
4492 tempe 3276 temperature = <90000>;
4493 hyste 3277 hysteresis = <2000>;
4494 type 3278 type = "hot";
4495 }; 3279 };
4496 3280
4497 aoss0_crit: a !! 3281 aoss0_crit: aoss0_crit {
4498 tempe 3282 temperature = <110000>;
4499 hyste 3283 hysteresis = <2000>;
4500 type 3284 type = "critical";
4501 }; 3285 };
4502 }; 3286 };
4503 }; 3287 };
4504 3288
4505 cpuss0-thermal { 3289 cpuss0-thermal {
4506 polling-delay-passive !! 3290 polling-delay-passive = <0>;
>> 3291 polling-delay = <0>;
4507 3292
4508 thermal-sensors = <&t 3293 thermal-sensors = <&tsens0 7>;
4509 3294
4510 trips { 3295 trips {
4511 cpuss0_alert0 3296 cpuss0_alert0: trip-point0 {
4512 tempe 3297 temperature = <90000>;
4513 hyste 3298 hysteresis = <2000>;
4514 type 3299 type = "hot";
4515 }; 3300 };
4516 cpuss0_crit: !! 3301 cpuss0_crit: cluster0_crit {
4517 tempe 3302 temperature = <110000>;
4518 hyste 3303 hysteresis = <2000>;
4519 type 3304 type = "critical";
4520 }; 3305 };
4521 }; 3306 };
4522 }; 3307 };
4523 3308
4524 cpuss1-thermal { 3309 cpuss1-thermal {
4525 polling-delay-passive !! 3310 polling-delay-passive = <0>;
>> 3311 polling-delay = <0>;
4526 3312
4527 thermal-sensors = <&t 3313 thermal-sensors = <&tsens0 8>;
4528 3314
4529 trips { 3315 trips {
4530 cpuss1_alert0 3316 cpuss1_alert0: trip-point0 {
4531 tempe 3317 temperature = <90000>;
4532 hyste 3318 hysteresis = <2000>;
4533 type 3319 type = "hot";
4534 }; 3320 };
4535 cpuss1_crit: !! 3321 cpuss1_crit: cluster0_crit {
4536 tempe 3322 temperature = <110000>;
4537 hyste 3323 hysteresis = <2000>;
4538 type 3324 type = "critical";
4539 }; 3325 };
4540 }; 3326 };
4541 }; 3327 };
4542 3328
4543 gpuss0-thermal { 3329 gpuss0-thermal {
4544 polling-delay-passive !! 3330 polling-delay-passive = <0>;
>> 3331 polling-delay = <0>;
4545 3332
4546 thermal-sensors = <&t 3333 thermal-sensors = <&tsens0 13>;
4547 3334
4548 trips { 3335 trips {
4549 gpuss0_alert0 3336 gpuss0_alert0: trip-point0 {
4550 tempe !! 3337 temperature = <90000>;
4551 hyste 3338 hysteresis = <2000>;
4552 type !! 3339 type = "hot";
4553 }; 3340 };
4554 3341
4555 gpuss0_crit: !! 3342 gpuss0_crit: gpuss0_crit {
4556 tempe 3343 temperature = <110000>;
4557 hyste 3344 hysteresis = <2000>;
4558 type 3345 type = "critical";
4559 }; 3346 };
4560 }; 3347 };
4561 <<
4562 cooling-maps { <<
4563 map0 { <<
4564 trip <<
4565 cooli <<
4566 }; <<
4567 }; <<
4568 }; 3348 };
4569 3349
4570 gpuss1-thermal { 3350 gpuss1-thermal {
4571 polling-delay-passive !! 3351 polling-delay-passive = <0>;
>> 3352 polling-delay = <0>;
4572 3353
4573 thermal-sensors = <&t 3354 thermal-sensors = <&tsens0 14>;
4574 3355
4575 trips { 3356 trips {
4576 gpuss1_alert0 3357 gpuss1_alert0: trip-point0 {
4577 tempe !! 3358 temperature = <90000>;
4578 hyste 3359 hysteresis = <2000>;
4579 type !! 3360 type = "hot";
4580 }; 3361 };
4581 3362
4582 gpuss1_crit: !! 3363 gpuss1_crit: gpuss1_crit {
4583 tempe 3364 temperature = <110000>;
4584 hyste 3365 hysteresis = <2000>;
4585 type 3366 type = "critical";
4586 }; 3367 };
4587 }; 3368 };
4588 <<
4589 cooling-maps { <<
4590 map0 { <<
4591 trip <<
4592 cooli <<
4593 }; <<
4594 }; <<
4595 }; 3369 };
4596 3370
4597 aoss1-thermal { 3371 aoss1-thermal {
4598 polling-delay-passive !! 3372 polling-delay-passive = <0>;
>> 3373 polling-delay = <0>;
4599 3374
4600 thermal-sensors = <&t 3375 thermal-sensors = <&tsens1 0>;
4601 3376
4602 trips { 3377 trips {
4603 aoss1_alert0: 3378 aoss1_alert0: trip-point0 {
4604 tempe 3379 temperature = <90000>;
4605 hyste 3380 hysteresis = <2000>;
4606 type 3381 type = "hot";
4607 }; 3382 };
4608 3383
4609 aoss1_crit: a !! 3384 aoss1_crit: aoss1_crit {
4610 tempe 3385 temperature = <110000>;
4611 hyste 3386 hysteresis = <2000>;
4612 type 3387 type = "critical";
4613 }; 3388 };
4614 }; 3389 };
4615 }; 3390 };
4616 3391
4617 cwlan-thermal { 3392 cwlan-thermal {
4618 polling-delay-passive !! 3393 polling-delay-passive = <0>;
>> 3394 polling-delay = <0>;
4619 3395
4620 thermal-sensors = <&t 3396 thermal-sensors = <&tsens1 1>;
4621 3397
4622 trips { 3398 trips {
4623 cwlan_alert0: 3399 cwlan_alert0: trip-point0 {
4624 tempe 3400 temperature = <90000>;
4625 hyste 3401 hysteresis = <2000>;
4626 type 3402 type = "hot";
4627 }; 3403 };
4628 3404
4629 cwlan_crit: c !! 3405 cwlan_crit: cwlan_crit {
4630 tempe 3406 temperature = <110000>;
4631 hyste 3407 hysteresis = <2000>;
4632 type 3408 type = "critical";
4633 }; 3409 };
4634 }; 3410 };
4635 }; 3411 };
4636 3412
4637 audio-thermal { 3413 audio-thermal {
4638 polling-delay-passive !! 3414 polling-delay-passive = <0>;
>> 3415 polling-delay = <0>;
4639 3416
4640 thermal-sensors = <&t 3417 thermal-sensors = <&tsens1 2>;
4641 3418
4642 trips { 3419 trips {
4643 audio_alert0: 3420 audio_alert0: trip-point0 {
4644 tempe 3421 temperature = <90000>;
4645 hyste 3422 hysteresis = <2000>;
4646 type 3423 type = "hot";
4647 }; 3424 };
4648 3425
4649 audio_crit: a !! 3426 audio_crit: audio_crit {
4650 tempe 3427 temperature = <110000>;
4651 hyste 3428 hysteresis = <2000>;
4652 type 3429 type = "critical";
4653 }; 3430 };
4654 }; 3431 };
4655 }; 3432 };
4656 3433
4657 ddr-thermal { 3434 ddr-thermal {
4658 polling-delay-passive !! 3435 polling-delay-passive = <0>;
>> 3436 polling-delay = <0>;
4659 3437
4660 thermal-sensors = <&t 3438 thermal-sensors = <&tsens1 3>;
4661 3439
4662 trips { 3440 trips {
4663 ddr_alert0: t 3441 ddr_alert0: trip-point0 {
4664 tempe 3442 temperature = <90000>;
4665 hyste 3443 hysteresis = <2000>;
4666 type 3444 type = "hot";
4667 }; 3445 };
4668 3446
4669 ddr_crit: ddr !! 3447 ddr_crit: ddr_crit {
4670 tempe 3448 temperature = <110000>;
4671 hyste 3449 hysteresis = <2000>;
4672 type 3450 type = "critical";
4673 }; 3451 };
4674 }; 3452 };
4675 }; 3453 };
4676 3454
4677 q6-hvx-thermal { 3455 q6-hvx-thermal {
4678 polling-delay-passive !! 3456 polling-delay-passive = <0>;
>> 3457 polling-delay = <0>;
4679 3458
4680 thermal-sensors = <&t 3459 thermal-sensors = <&tsens1 4>;
4681 3460
4682 trips { 3461 trips {
4683 q6_hvx_alert0 3462 q6_hvx_alert0: trip-point0 {
4684 tempe 3463 temperature = <90000>;
4685 hyste 3464 hysteresis = <2000>;
4686 type 3465 type = "hot";
4687 }; 3466 };
4688 3467
4689 q6_hvx_crit: !! 3468 q6_hvx_crit: q6_hvx_crit {
4690 tempe 3469 temperature = <110000>;
4691 hyste 3470 hysteresis = <2000>;
4692 type 3471 type = "critical";
4693 }; 3472 };
4694 }; 3473 };
4695 }; 3474 };
4696 3475
4697 camera-thermal { 3476 camera-thermal {
4698 polling-delay-passive !! 3477 polling-delay-passive = <0>;
>> 3478 polling-delay = <0>;
4699 3479
4700 thermal-sensors = <&t 3480 thermal-sensors = <&tsens1 5>;
4701 3481
4702 trips { 3482 trips {
4703 camera_alert0 3483 camera_alert0: trip-point0 {
4704 tempe 3484 temperature = <90000>;
4705 hyste 3485 hysteresis = <2000>;
4706 type 3486 type = "hot";
4707 }; 3487 };
4708 3488
4709 camera_crit: !! 3489 camera_crit: camera_crit {
4710 tempe 3490 temperature = <110000>;
4711 hyste 3491 hysteresis = <2000>;
4712 type 3492 type = "critical";
4713 }; 3493 };
4714 }; 3494 };
4715 }; 3495 };
4716 3496
4717 mdm-core-thermal { 3497 mdm-core-thermal {
4718 polling-delay-passive !! 3498 polling-delay-passive = <0>;
>> 3499 polling-delay = <0>;
4719 3500
4720 thermal-sensors = <&t 3501 thermal-sensors = <&tsens1 6>;
4721 3502
4722 trips { 3503 trips {
4723 mdm_alert0: t 3504 mdm_alert0: trip-point0 {
4724 tempe 3505 temperature = <90000>;
4725 hyste 3506 hysteresis = <2000>;
4726 type 3507 type = "hot";
4727 }; 3508 };
4728 3509
4729 mdm_crit: mdm !! 3510 mdm_crit: mdm_crit {
4730 tempe 3511 temperature = <110000>;
4731 hyste 3512 hysteresis = <2000>;
4732 type 3513 type = "critical";
4733 }; 3514 };
4734 }; 3515 };
4735 }; 3516 };
4736 3517
4737 mdm-dsp-thermal { 3518 mdm-dsp-thermal {
4738 polling-delay-passive !! 3519 polling-delay-passive = <0>;
>> 3520 polling-delay = <0>;
4739 3521
4740 thermal-sensors = <&t 3522 thermal-sensors = <&tsens1 7>;
4741 3523
4742 trips { 3524 trips {
4743 mdm_dsp_alert 3525 mdm_dsp_alert0: trip-point0 {
4744 tempe 3526 temperature = <90000>;
4745 hyste 3527 hysteresis = <2000>;
4746 type 3528 type = "hot";
4747 }; 3529 };
4748 3530
4749 mdm_dsp_crit: !! 3531 mdm_dsp_crit: mdm_dsp_crit {
4750 tempe 3532 temperature = <110000>;
4751 hyste 3533 hysteresis = <2000>;
4752 type 3534 type = "critical";
4753 }; 3535 };
4754 }; 3536 };
4755 }; 3537 };
4756 3538
4757 npu-thermal { 3539 npu-thermal {
4758 polling-delay-passive !! 3540 polling-delay-passive = <0>;
>> 3541 polling-delay = <0>;
4759 3542
4760 thermal-sensors = <&t 3543 thermal-sensors = <&tsens1 8>;
4761 3544
4762 trips { 3545 trips {
4763 npu_alert0: t 3546 npu_alert0: trip-point0 {
4764 tempe 3547 temperature = <90000>;
4765 hyste 3548 hysteresis = <2000>;
4766 type 3549 type = "hot";
4767 }; 3550 };
4768 3551
4769 npu_crit: npu !! 3552 npu_crit: npu_crit {
4770 tempe 3553 temperature = <110000>;
4771 hyste 3554 hysteresis = <2000>;
4772 type 3555 type = "critical";
4773 }; 3556 };
4774 }; 3557 };
4775 }; 3558 };
4776 3559
4777 video-thermal { 3560 video-thermal {
4778 polling-delay-passive !! 3561 polling-delay-passive = <0>;
>> 3562 polling-delay = <0>;
4779 3563
4780 thermal-sensors = <&t 3564 thermal-sensors = <&tsens1 9>;
4781 3565
4782 trips { 3566 trips {
4783 video_alert0: 3567 video_alert0: trip-point0 {
4784 tempe 3568 temperature = <90000>;
4785 hyste 3569 hysteresis = <2000>;
4786 type 3570 type = "hot";
4787 }; 3571 };
4788 3572
4789 video_crit: v !! 3573 video_crit: video_crit {
4790 tempe 3574 temperature = <110000>;
4791 hyste 3575 hysteresis = <2000>;
4792 type 3576 type = "critical";
4793 }; 3577 };
4794 }; 3578 };
4795 }; 3579 };
4796 }; 3580 };
4797 3581
4798 timer { 3582 timer {
4799 compatible = "arm,armv8-timer 3583 compatible = "arm,armv8-timer";
4800 interrupts = <GIC_PPI 1 IRQ_T 3584 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
4801 <GIC_PPI 2 IRQ_T 3585 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
4802 <GIC_PPI 3 IRQ_T 3586 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
4803 <GIC_PPI 0 IRQ_T 3587 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
4804 }; 3588 };
4805 }; 3589 };
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