1 // SPDX-License-Identifier: BSD-3-Clause 1 // SPDX-License-Identifier: BSD-3-Clause
2 /* 2 /*
3 * SC7180 SoC device tree source 3 * SC7180 SoC device tree source
4 * 4 *
5 * Copyright (c) 2019-2020, The Linux Foundati !! 5 * Copyright (c) 2019, The Linux Foundation. All rights reserved.
6 */ 6 */
7 7
8 #include <dt-bindings/clock/qcom,dispcc-sc7180 8 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
9 #include <dt-bindings/clock/qcom,gcc-sc7180.h> 9 #include <dt-bindings/clock/qcom,gcc-sc7180.h>
10 #include <dt-bindings/clock/qcom,gpucc-sc7180. 10 #include <dt-bindings/clock/qcom,gpucc-sc7180.h>
11 #include <dt-bindings/clock/qcom,lpasscorecc-s <<
12 #include <dt-bindings/clock/qcom,rpmh.h> 11 #include <dt-bindings/clock/qcom,rpmh.h>
13 #include <dt-bindings/clock/qcom,videocc-sc718 12 #include <dt-bindings/clock/qcom,videocc-sc7180.h>
14 #include <dt-bindings/firmware/qcom,scm.h> <<
15 #include <dt-bindings/interconnect/qcom,icc.h> <<
16 #include <dt-bindings/interconnect/qcom,osm-l3 13 #include <dt-bindings/interconnect/qcom,osm-l3.h>
17 #include <dt-bindings/interconnect/qcom,sc7180 14 #include <dt-bindings/interconnect/qcom,sc7180.h>
18 #include <dt-bindings/interrupt-controller/arm 15 #include <dt-bindings/interrupt-controller/arm-gic.h>
19 #include <dt-bindings/phy/phy-qcom-qmp.h> <<
20 #include <dt-bindings/phy/phy-qcom-qusb2.h> 16 #include <dt-bindings/phy/phy-qcom-qusb2.h>
>> 17 #include <dt-bindings/power/qcom-aoss-qmp.h>
21 #include <dt-bindings/power/qcom-rpmpd.h> 18 #include <dt-bindings/power/qcom-rpmpd.h>
22 #include <dt-bindings/reset/qcom,sdm845-aoss.h 19 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
23 #include <dt-bindings/reset/qcom,sdm845-pdc.h> 20 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
24 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 21 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
25 #include <dt-bindings/soc/qcom,apr.h> <<
26 #include <dt-bindings/sound/qcom,q6afe.h> <<
27 #include <dt-bindings/thermal/thermal.h> 22 #include <dt-bindings/thermal/thermal.h>
28 23
29 / { 24 / {
30 interrupt-parent = <&intc>; 25 interrupt-parent = <&intc>;
31 26
32 #address-cells = <2>; 27 #address-cells = <2>;
33 #size-cells = <2>; 28 #size-cells = <2>;
34 29
>> 30 chosen { };
>> 31
35 aliases { 32 aliases {
36 mmc1 = &sdhc_1; <<
37 mmc2 = &sdhc_2; <<
38 i2c0 = &i2c0; 33 i2c0 = &i2c0;
39 i2c1 = &i2c1; 34 i2c1 = &i2c1;
40 i2c2 = &i2c2; 35 i2c2 = &i2c2;
41 i2c3 = &i2c3; 36 i2c3 = &i2c3;
42 i2c4 = &i2c4; 37 i2c4 = &i2c4;
43 i2c5 = &i2c5; 38 i2c5 = &i2c5;
44 i2c6 = &i2c6; 39 i2c6 = &i2c6;
45 i2c7 = &i2c7; 40 i2c7 = &i2c7;
46 i2c8 = &i2c8; 41 i2c8 = &i2c8;
47 i2c9 = &i2c9; 42 i2c9 = &i2c9;
48 i2c10 = &i2c10; 43 i2c10 = &i2c10;
49 i2c11 = &i2c11; 44 i2c11 = &i2c11;
50 spi0 = &spi0; 45 spi0 = &spi0;
51 spi1 = &spi1; 46 spi1 = &spi1;
52 spi3 = &spi3; 47 spi3 = &spi3;
53 spi5 = &spi5; 48 spi5 = &spi5;
54 spi6 = &spi6; 49 spi6 = &spi6;
55 spi8 = &spi8; 50 spi8 = &spi8;
56 spi10 = &spi10; 51 spi10 = &spi10;
57 spi11 = &spi11; 52 spi11 = &spi11;
58 }; 53 };
59 54
60 chosen { }; <<
61 <<
62 clocks { 55 clocks {
63 xo_board: xo-board { 56 xo_board: xo-board {
64 compatible = "fixed-cl 57 compatible = "fixed-clock";
65 clock-frequency = <384 58 clock-frequency = <38400000>;
66 #clock-cells = <0>; 59 #clock-cells = <0>;
67 }; 60 };
68 61
69 sleep_clk: sleep-clk { 62 sleep_clk: sleep-clk {
70 compatible = "fixed-cl 63 compatible = "fixed-clock";
71 clock-frequency = <327 64 clock-frequency = <32764>;
72 #clock-cells = <0>; 65 #clock-cells = <0>;
73 }; 66 };
74 }; 67 };
75 68
>> 69 reserved_memory: reserved-memory {
>> 70 #address-cells = <2>;
>> 71 #size-cells = <2>;
>> 72 ranges;
>> 73
>> 74 hyp_mem: memory@80000000 {
>> 75 reg = <0x0 0x80000000 0x0 0x600000>;
>> 76 no-map;
>> 77 };
>> 78
>> 79 xbl_mem: memory@80600000 {
>> 80 reg = <0x0 0x80600000 0x0 0x200000>;
>> 81 no-map;
>> 82 };
>> 83
>> 84 aop_mem: memory@80800000 {
>> 85 reg = <0x0 0x80800000 0x0 0x20000>;
>> 86 no-map;
>> 87 };
>> 88
>> 89 aop_cmd_db_mem: memory@80820000 {
>> 90 reg = <0x0 0x80820000 0x0 0x20000>;
>> 91 compatible = "qcom,cmd-db";
>> 92 no-map;
>> 93 };
>> 94
>> 95 sec_apps_mem: memory@808ff000 {
>> 96 reg = <0x0 0x808ff000 0x0 0x1000>;
>> 97 no-map;
>> 98 };
>> 99
>> 100 smem_mem: memory@80900000 {
>> 101 reg = <0x0 0x80900000 0x0 0x200000>;
>> 102 no-map;
>> 103 };
>> 104
>> 105 tz_mem: memory@80b00000 {
>> 106 reg = <0x0 0x80b00000 0x0 0x3900000>;
>> 107 no-map;
>> 108 };
>> 109
>> 110 rmtfs_mem: memory@84400000 {
>> 111 compatible = "qcom,rmtfs-mem";
>> 112 reg = <0x0 0x84400000 0x0 0x200000>;
>> 113 no-map;
>> 114
>> 115 qcom,client-id = <1>;
>> 116 qcom,vmid = <15>;
>> 117 };
>> 118 };
>> 119
76 cpus { 120 cpus {
77 #address-cells = <2>; 121 #address-cells = <2>;
78 #size-cells = <0>; 122 #size-cells = <0>;
79 123
80 CPU0: cpu@0 { 124 CPU0: cpu@0 {
81 device_type = "cpu"; 125 device_type = "cpu";
82 compatible = "qcom,kry 126 compatible = "qcom,kryo468";
83 reg = <0x0 0x0>; 127 reg = <0x0 0x0>;
84 clocks = <&cpufreq_hw <<
85 enable-method = "psci" 128 enable-method = "psci";
86 power-domains = <&CPU_ !! 129 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
87 power-domain-names = " !! 130 &LITTLE_CPU_SLEEP_1
88 capacity-dmips-mhz = < !! 131 &CLUSTER_SLEEP_0>;
89 dynamic-power-coeffici !! 132 capacity-dmips-mhz = <1024>;
>> 133 dynamic-power-coefficient = <100>;
90 operating-points-v2 = 134 operating-points-v2 = <&cpu0_opp_table>;
91 interconnects = <&gem_ !! 135 interconnects = <&gem_noc MASTER_APPSS_PROC &mc_virt SLAVE_EBI1>,
92 <&osm_ 136 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
93 next-level-cache = <&L 137 next-level-cache = <&L2_0>;
94 #cooling-cells = <2>; 138 #cooling-cells = <2>;
95 qcom,freq-domain = <&c 139 qcom,freq-domain = <&cpufreq_hw 0>;
96 L2_0: l2-cache { 140 L2_0: l2-cache {
97 compatible = " 141 compatible = "cache";
98 cache-level = <<
99 cache-unified; <<
100 next-level-cac 142 next-level-cache = <&L3_0>;
101 L3_0: l3-cache 143 L3_0: l3-cache {
102 compat 144 compatible = "cache";
103 cache- <<
104 cache- <<
105 }; 145 };
106 }; 146 };
107 }; 147 };
108 148
109 CPU1: cpu@100 { 149 CPU1: cpu@100 {
110 device_type = "cpu"; 150 device_type = "cpu";
111 compatible = "qcom,kry 151 compatible = "qcom,kryo468";
112 reg = <0x0 0x100>; 152 reg = <0x0 0x100>;
113 clocks = <&cpufreq_hw <<
114 enable-method = "psci" 153 enable-method = "psci";
115 power-domains = <&CPU_ !! 154 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
116 power-domain-names = " !! 155 &LITTLE_CPU_SLEEP_1
117 capacity-dmips-mhz = < !! 156 &CLUSTER_SLEEP_0>;
118 dynamic-power-coeffici !! 157 capacity-dmips-mhz = <1024>;
>> 158 dynamic-power-coefficient = <100>;
119 next-level-cache = <&L 159 next-level-cache = <&L2_100>;
120 operating-points-v2 = 160 operating-points-v2 = <&cpu0_opp_table>;
121 interconnects = <&gem_ !! 161 interconnects = <&gem_noc MASTER_APPSS_PROC &mc_virt SLAVE_EBI1>,
122 <&osm_ 162 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
123 #cooling-cells = <2>; 163 #cooling-cells = <2>;
124 qcom,freq-domain = <&c 164 qcom,freq-domain = <&cpufreq_hw 0>;
125 L2_100: l2-cache { 165 L2_100: l2-cache {
126 compatible = " 166 compatible = "cache";
127 cache-level = <<
128 cache-unified; <<
129 next-level-cac 167 next-level-cache = <&L3_0>;
130 }; 168 };
131 }; 169 };
132 170
133 CPU2: cpu@200 { 171 CPU2: cpu@200 {
134 device_type = "cpu"; 172 device_type = "cpu";
135 compatible = "qcom,kry 173 compatible = "qcom,kryo468";
136 reg = <0x0 0x200>; 174 reg = <0x0 0x200>;
137 clocks = <&cpufreq_hw <<
138 enable-method = "psci" 175 enable-method = "psci";
139 power-domains = <&CPU_ !! 176 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
140 power-domain-names = " !! 177 &LITTLE_CPU_SLEEP_1
141 capacity-dmips-mhz = < !! 178 &CLUSTER_SLEEP_0>;
142 dynamic-power-coeffici !! 179 capacity-dmips-mhz = <1024>;
>> 180 dynamic-power-coefficient = <100>;
143 next-level-cache = <&L 181 next-level-cache = <&L2_200>;
144 operating-points-v2 = 182 operating-points-v2 = <&cpu0_opp_table>;
145 interconnects = <&gem_ !! 183 interconnects = <&gem_noc MASTER_APPSS_PROC &mc_virt SLAVE_EBI1>,
146 <&osm_ 184 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
147 #cooling-cells = <2>; 185 #cooling-cells = <2>;
148 qcom,freq-domain = <&c 186 qcom,freq-domain = <&cpufreq_hw 0>;
149 L2_200: l2-cache { 187 L2_200: l2-cache {
150 compatible = " 188 compatible = "cache";
151 cache-level = <<
152 cache-unified; <<
153 next-level-cac 189 next-level-cache = <&L3_0>;
154 }; 190 };
155 }; 191 };
156 192
157 CPU3: cpu@300 { 193 CPU3: cpu@300 {
158 device_type = "cpu"; 194 device_type = "cpu";
159 compatible = "qcom,kry 195 compatible = "qcom,kryo468";
160 reg = <0x0 0x300>; 196 reg = <0x0 0x300>;
161 clocks = <&cpufreq_hw <<
162 enable-method = "psci" 197 enable-method = "psci";
163 power-domains = <&CPU_ !! 198 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
164 power-domain-names = " !! 199 &LITTLE_CPU_SLEEP_1
165 capacity-dmips-mhz = < !! 200 &CLUSTER_SLEEP_0>;
166 dynamic-power-coeffici !! 201 capacity-dmips-mhz = <1024>;
>> 202 dynamic-power-coefficient = <100>;
167 next-level-cache = <&L 203 next-level-cache = <&L2_300>;
168 operating-points-v2 = 204 operating-points-v2 = <&cpu0_opp_table>;
169 interconnects = <&gem_ !! 205 interconnects = <&gem_noc MASTER_APPSS_PROC &mc_virt SLAVE_EBI1>,
170 <&osm_ 206 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
171 #cooling-cells = <2>; 207 #cooling-cells = <2>;
172 qcom,freq-domain = <&c 208 qcom,freq-domain = <&cpufreq_hw 0>;
173 L2_300: l2-cache { 209 L2_300: l2-cache {
174 compatible = " 210 compatible = "cache";
175 cache-level = <<
176 cache-unified; <<
177 next-level-cac 211 next-level-cache = <&L3_0>;
178 }; 212 };
179 }; 213 };
180 214
181 CPU4: cpu@400 { 215 CPU4: cpu@400 {
182 device_type = "cpu"; 216 device_type = "cpu";
183 compatible = "qcom,kry 217 compatible = "qcom,kryo468";
184 reg = <0x0 0x400>; 218 reg = <0x0 0x400>;
185 clocks = <&cpufreq_hw <<
186 enable-method = "psci" 219 enable-method = "psci";
187 power-domains = <&CPU_ !! 220 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
188 power-domain-names = " !! 221 &LITTLE_CPU_SLEEP_1
189 capacity-dmips-mhz = < !! 222 &CLUSTER_SLEEP_0>;
190 dynamic-power-coeffici !! 223 capacity-dmips-mhz = <1024>;
>> 224 dynamic-power-coefficient = <100>;
191 next-level-cache = <&L 225 next-level-cache = <&L2_400>;
192 operating-points-v2 = 226 operating-points-v2 = <&cpu0_opp_table>;
193 interconnects = <&gem_ !! 227 interconnects = <&gem_noc MASTER_APPSS_PROC &mc_virt SLAVE_EBI1>,
194 <&osm_ 228 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
195 #cooling-cells = <2>; 229 #cooling-cells = <2>;
196 qcom,freq-domain = <&c 230 qcom,freq-domain = <&cpufreq_hw 0>;
197 L2_400: l2-cache { 231 L2_400: l2-cache {
198 compatible = " 232 compatible = "cache";
199 cache-level = <<
200 cache-unified; <<
201 next-level-cac 233 next-level-cache = <&L3_0>;
202 }; 234 };
203 }; 235 };
204 236
205 CPU5: cpu@500 { 237 CPU5: cpu@500 {
206 device_type = "cpu"; 238 device_type = "cpu";
207 compatible = "qcom,kry 239 compatible = "qcom,kryo468";
208 reg = <0x0 0x500>; 240 reg = <0x0 0x500>;
209 clocks = <&cpufreq_hw <<
210 enable-method = "psci" 241 enable-method = "psci";
211 power-domains = <&CPU_ !! 242 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
212 power-domain-names = " !! 243 &LITTLE_CPU_SLEEP_1
213 capacity-dmips-mhz = < !! 244 &CLUSTER_SLEEP_0>;
214 dynamic-power-coeffici !! 245 capacity-dmips-mhz = <1024>;
>> 246 dynamic-power-coefficient = <100>;
215 next-level-cache = <&L 247 next-level-cache = <&L2_500>;
216 operating-points-v2 = 248 operating-points-v2 = <&cpu0_opp_table>;
217 interconnects = <&gem_ !! 249 interconnects = <&gem_noc MASTER_APPSS_PROC &mc_virt SLAVE_EBI1>,
218 <&osm_ 250 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
219 #cooling-cells = <2>; 251 #cooling-cells = <2>;
220 qcom,freq-domain = <&c 252 qcom,freq-domain = <&cpufreq_hw 0>;
221 L2_500: l2-cache { 253 L2_500: l2-cache {
222 compatible = " 254 compatible = "cache";
223 cache-level = <<
224 cache-unified; <<
225 next-level-cac 255 next-level-cache = <&L3_0>;
226 }; 256 };
227 }; 257 };
228 258
229 CPU6: cpu@600 { 259 CPU6: cpu@600 {
230 device_type = "cpu"; 260 device_type = "cpu";
231 compatible = "qcom,kry 261 compatible = "qcom,kryo468";
232 reg = <0x0 0x600>; 262 reg = <0x0 0x600>;
233 clocks = <&cpufreq_hw <<
234 enable-method = "psci" 263 enable-method = "psci";
235 power-domains = <&CPU_ !! 264 cpu-idle-states = <&BIG_CPU_SLEEP_0
236 power-domain-names = " !! 265 &BIG_CPU_SLEEP_1
237 capacity-dmips-mhz = < !! 266 &CLUSTER_SLEEP_0>;
238 dynamic-power-coeffici !! 267 capacity-dmips-mhz = <1740>;
>> 268 dynamic-power-coefficient = <405>;
239 next-level-cache = <&L 269 next-level-cache = <&L2_600>;
240 operating-points-v2 = 270 operating-points-v2 = <&cpu6_opp_table>;
241 interconnects = <&gem_ !! 271 interconnects = <&gem_noc MASTER_APPSS_PROC &mc_virt SLAVE_EBI1>,
242 <&osm_ 272 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
243 #cooling-cells = <2>; 273 #cooling-cells = <2>;
244 qcom,freq-domain = <&c 274 qcom,freq-domain = <&cpufreq_hw 1>;
245 L2_600: l2-cache { 275 L2_600: l2-cache {
246 compatible = " 276 compatible = "cache";
247 cache-level = <<
248 cache-unified; <<
249 next-level-cac 277 next-level-cache = <&L3_0>;
250 }; 278 };
251 }; 279 };
252 280
253 CPU7: cpu@700 { 281 CPU7: cpu@700 {
254 device_type = "cpu"; 282 device_type = "cpu";
255 compatible = "qcom,kry 283 compatible = "qcom,kryo468";
256 reg = <0x0 0x700>; 284 reg = <0x0 0x700>;
257 clocks = <&cpufreq_hw <<
258 enable-method = "psci" 285 enable-method = "psci";
259 power-domains = <&CPU_ !! 286 cpu-idle-states = <&BIG_CPU_SLEEP_0
260 power-domain-names = " !! 287 &BIG_CPU_SLEEP_1
261 capacity-dmips-mhz = < !! 288 &CLUSTER_SLEEP_0>;
262 dynamic-power-coeffici !! 289 capacity-dmips-mhz = <1740>;
>> 290 dynamic-power-coefficient = <405>;
263 next-level-cache = <&L 291 next-level-cache = <&L2_700>;
264 operating-points-v2 = 292 operating-points-v2 = <&cpu6_opp_table>;
265 interconnects = <&gem_ !! 293 interconnects = <&gem_noc MASTER_APPSS_PROC &mc_virt SLAVE_EBI1>,
266 <&osm_ 294 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
267 #cooling-cells = <2>; 295 #cooling-cells = <2>;
268 qcom,freq-domain = <&c 296 qcom,freq-domain = <&cpufreq_hw 1>;
269 L2_700: l2-cache { 297 L2_700: l2-cache {
270 compatible = " 298 compatible = "cache";
271 cache-level = <<
272 cache-unified; <<
273 next-level-cac 299 next-level-cache = <&L3_0>;
274 }; 300 };
275 }; 301 };
276 302
277 cpu-map { 303 cpu-map {
278 cluster0 { 304 cluster0 {
279 core0 { 305 core0 {
280 cpu = 306 cpu = <&CPU0>;
281 }; 307 };
282 308
283 core1 { 309 core1 {
284 cpu = 310 cpu = <&CPU1>;
285 }; 311 };
286 312
287 core2 { 313 core2 {
288 cpu = 314 cpu = <&CPU2>;
289 }; 315 };
290 316
291 core3 { 317 core3 {
292 cpu = 318 cpu = <&CPU3>;
293 }; 319 };
294 320
295 core4 { 321 core4 {
296 cpu = 322 cpu = <&CPU4>;
297 }; 323 };
298 324
299 core5 { 325 core5 {
300 cpu = 326 cpu = <&CPU5>;
301 }; 327 };
302 328
303 core6 { 329 core6 {
304 cpu = 330 cpu = <&CPU6>;
305 }; 331 };
306 332
307 core7 { 333 core7 {
308 cpu = 334 cpu = <&CPU7>;
309 }; 335 };
310 }; 336 };
311 }; 337 };
312 338
313 idle_states: idle-states { !! 339 idle-states {
314 entry-method = "psci"; 340 entry-method = "psci";
315 341
316 LITTLE_CPU_SLEEP_0: cp 342 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
317 compatible = " 343 compatible = "arm,idle-state";
318 idle-state-nam 344 idle-state-name = "little-power-down";
319 arm,psci-suspe 345 arm,psci-suspend-param = <0x40000003>;
320 entry-latency- 346 entry-latency-us = <549>;
321 exit-latency-u 347 exit-latency-us = <901>;
322 min-residency- 348 min-residency-us = <1774>;
323 local-timer-st 349 local-timer-stop;
324 }; 350 };
325 351
326 LITTLE_CPU_SLEEP_1: cp 352 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
327 compatible = " 353 compatible = "arm,idle-state";
328 idle-state-nam 354 idle-state-name = "little-rail-power-down";
329 arm,psci-suspe 355 arm,psci-suspend-param = <0x40000004>;
330 entry-latency- 356 entry-latency-us = <702>;
331 exit-latency-u 357 exit-latency-us = <915>;
332 min-residency- 358 min-residency-us = <4001>;
333 local-timer-st 359 local-timer-stop;
334 }; 360 };
335 361
336 BIG_CPU_SLEEP_0: cpu-s 362 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
337 compatible = " 363 compatible = "arm,idle-state";
338 idle-state-nam 364 idle-state-name = "big-power-down";
339 arm,psci-suspe 365 arm,psci-suspend-param = <0x40000003>;
340 entry-latency- 366 entry-latency-us = <523>;
341 exit-latency-u 367 exit-latency-us = <1244>;
342 min-residency- 368 min-residency-us = <2207>;
343 local-timer-st 369 local-timer-stop;
344 }; 370 };
345 371
346 BIG_CPU_SLEEP_1: cpu-s 372 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
347 compatible = " 373 compatible = "arm,idle-state";
348 idle-state-nam 374 idle-state-name = "big-rail-power-down";
349 arm,psci-suspe 375 arm,psci-suspend-param = <0x40000004>;
350 entry-latency- 376 entry-latency-us = <526>;
351 exit-latency-u 377 exit-latency-us = <1854>;
352 min-residency- 378 min-residency-us = <5555>;
353 local-timer-st 379 local-timer-stop;
354 }; 380 };
355 }; <<
356 <<
357 domain_idle_states: domain-idl <<
358 CLUSTER_SLEEP_PC: clus <<
359 compatible = " <<
360 idle-state-nam <<
361 arm,psci-suspe <<
362 entry-latency- <<
363 exit-latency-u <<
364 min-residency- <<
365 }; <<
366 <<
367 CLUSTER_SLEEP_CX_RET: <<
368 compatible = " <<
369 idle-state-nam <<
370 arm,psci-suspe <<
371 entry-latency- <<
372 exit-latency-u <<
373 min-residency- <<
374 }; <<
375 381
376 CLUSTER_AOSS_SLEEP: cl !! 382 CLUSTER_SLEEP_0: cluster-sleep-0 {
377 compatible = " !! 383 compatible = "arm,idle-state";
378 idle-state-nam 384 idle-state-name = "cluster-power-down";
379 arm,psci-suspe !! 385 arm,psci-suspend-param = <0x40003444>;
380 entry-latency- 386 entry-latency-us = <3263>;
381 exit-latency-u 387 exit-latency-us = <6562>;
382 min-residency- !! 388 min-residency-us = <9926>;
>> 389 local-timer-stop;
383 }; 390 };
384 }; 391 };
385 }; 392 };
386 393
387 firmware { !! 394 cpu0_opp_table: cpu0_opp_table {
388 scm: scm { <<
389 compatible = "qcom,scm <<
390 }; <<
391 }; <<
392 <<
393 memory@80000000 { <<
394 device_type = "memory"; <<
395 /* We expect the bootloader to <<
396 reg = <0 0x80000000 0 0>; <<
397 }; <<
398 <<
399 cpu0_opp_table: opp-table-cpu0 { <<
400 compatible = "operating-points 395 compatible = "operating-points-v2";
401 opp-shared; 396 opp-shared;
402 397
403 cpu0_opp1: opp-300000000 { 398 cpu0_opp1: opp-300000000 {
404 opp-hz = /bits/ 64 <30 399 opp-hz = /bits/ 64 <300000000>;
405 opp-peak-kBps = <12000 400 opp-peak-kBps = <1200000 4800000>;
406 }; 401 };
407 402
408 cpu0_opp2: opp-576000000 { 403 cpu0_opp2: opp-576000000 {
409 opp-hz = /bits/ 64 <57 404 opp-hz = /bits/ 64 <576000000>;
410 opp-peak-kBps = <12000 405 opp-peak-kBps = <1200000 4800000>;
411 }; 406 };
412 407
413 cpu0_opp3: opp-768000000 { 408 cpu0_opp3: opp-768000000 {
414 opp-hz = /bits/ 64 <76 409 opp-hz = /bits/ 64 <768000000>;
415 opp-peak-kBps = <12000 410 opp-peak-kBps = <1200000 4800000>;
416 }; 411 };
417 412
418 cpu0_opp4: opp-1017600000 { 413 cpu0_opp4: opp-1017600000 {
419 opp-hz = /bits/ 64 <10 414 opp-hz = /bits/ 64 <1017600000>;
420 opp-peak-kBps = <18040 415 opp-peak-kBps = <1804000 8908800>;
421 }; 416 };
422 417
423 cpu0_opp5: opp-1248000000 { 418 cpu0_opp5: opp-1248000000 {
424 opp-hz = /bits/ 64 <12 419 opp-hz = /bits/ 64 <1248000000>;
425 opp-peak-kBps = <21880 420 opp-peak-kBps = <2188000 12902400>;
426 }; 421 };
427 422
428 cpu0_opp6: opp-1324800000 { 423 cpu0_opp6: opp-1324800000 {
429 opp-hz = /bits/ 64 <13 424 opp-hz = /bits/ 64 <1324800000>;
430 opp-peak-kBps = <21880 425 opp-peak-kBps = <2188000 12902400>;
431 }; 426 };
432 427
433 cpu0_opp7: opp-1516800000 { 428 cpu0_opp7: opp-1516800000 {
434 opp-hz = /bits/ 64 <15 429 opp-hz = /bits/ 64 <1516800000>;
435 opp-peak-kBps = <30720 430 opp-peak-kBps = <3072000 15052800>;
436 }; 431 };
437 432
438 cpu0_opp8: opp-1612800000 { 433 cpu0_opp8: opp-1612800000 {
439 opp-hz = /bits/ 64 <16 434 opp-hz = /bits/ 64 <1612800000>;
440 opp-peak-kBps = <30720 435 opp-peak-kBps = <3072000 15052800>;
441 }; 436 };
442 437
443 cpu0_opp9: opp-1708800000 { 438 cpu0_opp9: opp-1708800000 {
444 opp-hz = /bits/ 64 <17 439 opp-hz = /bits/ 64 <1708800000>;
445 opp-peak-kBps = <30720 440 opp-peak-kBps = <3072000 15052800>;
446 }; 441 };
447 442
448 cpu0_opp10: opp-1804800000 { 443 cpu0_opp10: opp-1804800000 {
449 opp-hz = /bits/ 64 <18 444 opp-hz = /bits/ 64 <1804800000>;
450 opp-peak-kBps = <40680 445 opp-peak-kBps = <4068000 22425600>;
451 }; 446 };
452 }; 447 };
453 448
454 cpu6_opp_table: opp-table-cpu6 { !! 449 cpu6_opp_table: cpu6_opp_table {
455 compatible = "operating-points 450 compatible = "operating-points-v2";
456 opp-shared; 451 opp-shared;
457 452
458 cpu6_opp1: opp-300000000 { 453 cpu6_opp1: opp-300000000 {
459 opp-hz = /bits/ 64 <30 454 opp-hz = /bits/ 64 <300000000>;
460 opp-peak-kBps = <21880 455 opp-peak-kBps = <2188000 8908800>;
461 }; 456 };
462 457
463 cpu6_opp2: opp-652800000 { 458 cpu6_opp2: opp-652800000 {
464 opp-hz = /bits/ 64 <65 459 opp-hz = /bits/ 64 <652800000>;
465 opp-peak-kBps = <21880 460 opp-peak-kBps = <2188000 8908800>;
466 }; 461 };
467 462
468 cpu6_opp3: opp-825600000 { 463 cpu6_opp3: opp-825600000 {
469 opp-hz = /bits/ 64 <82 464 opp-hz = /bits/ 64 <825600000>;
470 opp-peak-kBps = <21880 465 opp-peak-kBps = <2188000 8908800>;
471 }; 466 };
472 467
473 cpu6_opp4: opp-979200000 { 468 cpu6_opp4: opp-979200000 {
474 opp-hz = /bits/ 64 <97 469 opp-hz = /bits/ 64 <979200000>;
475 opp-peak-kBps = <21880 470 opp-peak-kBps = <2188000 8908800>;
476 }; 471 };
477 472
478 cpu6_opp5: opp-1113600000 { 473 cpu6_opp5: opp-1113600000 {
479 opp-hz = /bits/ 64 <11 474 opp-hz = /bits/ 64 <1113600000>;
480 opp-peak-kBps = <21880 475 opp-peak-kBps = <2188000 8908800>;
481 }; 476 };
482 477
483 cpu6_opp6: opp-1267200000 { 478 cpu6_opp6: opp-1267200000 {
484 opp-hz = /bits/ 64 <12 479 opp-hz = /bits/ 64 <1267200000>;
485 opp-peak-kBps = <40680 480 opp-peak-kBps = <4068000 12902400>;
486 }; 481 };
487 482
488 cpu6_opp7: opp-1555200000 { 483 cpu6_opp7: opp-1555200000 {
489 opp-hz = /bits/ 64 <15 484 opp-hz = /bits/ 64 <1555200000>;
490 opp-peak-kBps = <40680 485 opp-peak-kBps = <4068000 15052800>;
491 }; 486 };
492 487
493 cpu6_opp8: opp-1708800000 { 488 cpu6_opp8: opp-1708800000 {
494 opp-hz = /bits/ 64 <17 489 opp-hz = /bits/ 64 <1708800000>;
495 opp-peak-kBps = <62200 490 opp-peak-kBps = <6220000 19353600>;
496 }; 491 };
497 492
498 cpu6_opp9: opp-1843200000 { 493 cpu6_opp9: opp-1843200000 {
499 opp-hz = /bits/ 64 <18 494 opp-hz = /bits/ 64 <1843200000>;
500 opp-peak-kBps = <62200 495 opp-peak-kBps = <6220000 19353600>;
501 }; 496 };
502 497
503 cpu6_opp10: opp-1900800000 { 498 cpu6_opp10: opp-1900800000 {
504 opp-hz = /bits/ 64 <19 499 opp-hz = /bits/ 64 <1900800000>;
505 opp-peak-kBps = <62200 500 opp-peak-kBps = <6220000 22425600>;
506 }; 501 };
507 502
508 cpu6_opp11: opp-1996800000 { 503 cpu6_opp11: opp-1996800000 {
509 opp-hz = /bits/ 64 <19 504 opp-hz = /bits/ 64 <1996800000>;
510 opp-peak-kBps = <62200 505 opp-peak-kBps = <6220000 22425600>;
511 }; 506 };
512 507
513 cpu6_opp12: opp-2112000000 { 508 cpu6_opp12: opp-2112000000 {
514 opp-hz = /bits/ 64 <21 509 opp-hz = /bits/ 64 <2112000000>;
515 opp-peak-kBps = <62200 510 opp-peak-kBps = <6220000 22425600>;
516 }; 511 };
517 512
518 cpu6_opp13: opp-2208000000 { 513 cpu6_opp13: opp-2208000000 {
519 opp-hz = /bits/ 64 <22 514 opp-hz = /bits/ 64 <2208000000>;
520 opp-peak-kBps = <72160 515 opp-peak-kBps = <7216000 22425600>;
521 }; 516 };
522 517
523 cpu6_opp14: opp-2323200000 { 518 cpu6_opp14: opp-2323200000 {
524 opp-hz = /bits/ 64 <23 519 opp-hz = /bits/ 64 <2323200000>;
525 opp-peak-kBps = <72160 520 opp-peak-kBps = <7216000 22425600>;
526 }; 521 };
527 522
528 cpu6_opp15: opp-2400000000 { 523 cpu6_opp15: opp-2400000000 {
529 opp-hz = /bits/ 64 <24 524 opp-hz = /bits/ 64 <2400000000>;
530 opp-peak-kBps = <85320 525 opp-peak-kBps = <8532000 23347200>;
531 }; 526 };
532 <<
533 cpu6_opp16: opp-2553600000 { <<
534 opp-hz = /bits/ 64 <25 <<
535 opp-peak-kBps = <85320 <<
536 }; <<
537 }; <<
538 <<
539 qspi_opp_table: opp-table-qspi { <<
540 compatible = "operating-points <<
541 <<
542 opp-75000000 { <<
543 opp-hz = /bits/ 64 <75 <<
544 required-opps = <&rpmh <<
545 }; <<
546 <<
547 opp-150000000 { <<
548 opp-hz = /bits/ 64 <15 <<
549 required-opps = <&rpmh <<
550 }; <<
551 <<
552 opp-300000000 { <<
553 opp-hz = /bits/ 64 <30 <<
554 required-opps = <&rpmh <<
555 }; <<
556 }; 527 };
557 528
558 qup_opp_table: opp-table-qup { !! 529 memory@80000000 {
559 compatible = "operating-points !! 530 device_type = "memory";
560 !! 531 /* We expect the bootloader to fill in the size */
561 opp-75000000 { !! 532 reg = <0 0x80000000 0 0>;
562 opp-hz = /bits/ 64 <75 <<
563 required-opps = <&rpmh <<
564 }; <<
565 <<
566 opp-100000000 { <<
567 opp-hz = /bits/ 64 <10 <<
568 required-opps = <&rpmh <<
569 }; <<
570 <<
571 opp-128000000 { <<
572 opp-hz = /bits/ 64 <12 <<
573 required-opps = <&rpmh <<
574 }; <<
575 }; 533 };
576 534
577 pmu { 535 pmu {
578 compatible = "arm,armv8-pmuv3" 536 compatible = "arm,armv8-pmuv3";
579 interrupts = <GIC_PPI 5 IRQ_TY 537 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
580 }; 538 };
581 539
582 psci { !! 540 firmware {
583 compatible = "arm,psci-1.0"; !! 541 scm {
584 method = "smc"; !! 542 compatible = "qcom,scm-sc7180", "qcom,scm";
585 <<
586 CPU_PD0: cpu0 { <<
587 #power-domain-cells = <<
588 power-domains = <&CLUS <<
589 domain-idle-states = < <<
590 }; <<
591 <<
592 CPU_PD1: cpu1 { <<
593 #power-domain-cells = <<
594 power-domains = <&CLUS <<
595 domain-idle-states = < <<
596 }; <<
597 <<
598 CPU_PD2: cpu2 { <<
599 #power-domain-cells = <<
600 power-domains = <&CLUS <<
601 domain-idle-states = < <<
602 }; <<
603 <<
604 CPU_PD3: cpu3 { <<
605 #power-domain-cells = <<
606 power-domains = <&CLUS <<
607 domain-idle-states = < <<
608 }; <<
609 <<
610 CPU_PD4: cpu4 { <<
611 #power-domain-cells = <<
612 power-domains = <&CLUS <<
613 domain-idle-states = < <<
614 }; <<
615 <<
616 CPU_PD5: cpu5 { <<
617 #power-domain-cells = <<
618 power-domains = <&CLUS <<
619 domain-idle-states = < <<
620 }; <<
621 <<
622 CPU_PD6: cpu6 { <<
623 #power-domain-cells = <<
624 power-domains = <&CLUS <<
625 domain-idle-states = < <<
626 }; <<
627 <<
628 CPU_PD7: cpu7 { <<
629 #power-domain-cells = <<
630 power-domains = <&CLUS <<
631 domain-idle-states = < <<
632 }; <<
633 <<
634 CLUSTER_PD: cpu-cluster0 { <<
635 #power-domain-cells = <<
636 domain-idle-states = < <<
637 <<
638 <<
639 }; 543 };
640 }; 544 };
641 545
642 reserved_memory: reserved-memory { !! 546 tcsr_mutex: hwlock {
643 #address-cells = <2>; !! 547 compatible = "qcom,tcsr-mutex";
644 #size-cells = <2>; !! 548 syscon = <&tcsr_mutex_regs 0 0x1000>;
645 ranges; !! 549 #hwlock-cells = <1>;
646 <<
647 hyp_mem: memory@80000000 { <<
648 reg = <0x0 0x80000000 <<
649 no-map; <<
650 }; <<
651 <<
652 xbl_mem: memory@80600000 { <<
653 reg = <0x0 0x80600000 <<
654 no-map; <<
655 }; <<
656 <<
657 aop_mem: memory@80800000 { <<
658 reg = <0x0 0x80800000 <<
659 no-map; <<
660 }; <<
661 <<
662 aop_cmd_db_mem: memory@8082000 <<
663 reg = <0x0 0x80820000 <<
664 compatible = "qcom,cmd <<
665 no-map; <<
666 }; <<
667 <<
668 sec_apps_mem: memory@808ff000 <<
669 reg = <0x0 0x808ff000 <<
670 no-map; <<
671 }; <<
672 <<
673 smem_mem: memory@80900000 { <<
674 reg = <0x0 0x80900000 <<
675 no-map; <<
676 }; <<
677 <<
678 tz_mem: memory@80b00000 { <<
679 reg = <0x0 0x80b00000 <<
680 no-map; <<
681 }; <<
682 <<
683 ipa_fw_mem: memory@8b700000 { <<
684 reg = <0 0x8b700000 0 <<
685 no-map; <<
686 }; <<
687 <<
688 rmtfs_mem: memory@94600000 { <<
689 compatible = "qcom,rmt <<
690 reg = <0x0 0x94600000 <<
691 no-map; <<
692 <<
693 qcom,client-id = <1>; <<
694 qcom,vmid = <QCOM_SCM_ <<
695 }; <<
696 }; 550 };
697 551
698 smem { 552 smem {
699 compatible = "qcom,smem"; 553 compatible = "qcom,smem";
700 memory-region = <&smem_mem>; 554 memory-region = <&smem_mem>;
701 hwlocks = <&tcsr_mutex 3>; 555 hwlocks = <&tcsr_mutex 3>;
702 }; 556 };
703 557
704 smp2p-cdsp { 558 smp2p-cdsp {
705 compatible = "qcom,smp2p"; 559 compatible = "qcom,smp2p";
706 qcom,smem = <94>, <432>; 560 qcom,smem = <94>, <432>;
707 561
708 interrupts = <GIC_SPI 576 IRQ_ 562 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
709 563
710 mboxes = <&apss_shared 6>; 564 mboxes = <&apss_shared 6>;
711 565
712 qcom,local-pid = <0>; 566 qcom,local-pid = <0>;
713 qcom,remote-pid = <5>; 567 qcom,remote-pid = <5>;
714 568
715 cdsp_smp2p_out: master-kernel 569 cdsp_smp2p_out: master-kernel {
716 qcom,entry-name = "mas 570 qcom,entry-name = "master-kernel";
717 #qcom,smem-state-cells 571 #qcom,smem-state-cells = <1>;
718 }; 572 };
719 573
720 cdsp_smp2p_in: slave-kernel { 574 cdsp_smp2p_in: slave-kernel {
721 qcom,entry-name = "sla 575 qcom,entry-name = "slave-kernel";
722 576
723 interrupt-controller; 577 interrupt-controller;
724 #interrupt-cells = <2> 578 #interrupt-cells = <2>;
725 }; 579 };
726 }; 580 };
727 581
728 smp2p-lpass { 582 smp2p-lpass {
729 compatible = "qcom,smp2p"; 583 compatible = "qcom,smp2p";
730 qcom,smem = <443>, <429>; 584 qcom,smem = <443>, <429>;
731 585
732 interrupts = <GIC_SPI 158 IRQ_ 586 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
733 587
734 mboxes = <&apss_shared 10>; 588 mboxes = <&apss_shared 10>;
735 589
736 qcom,local-pid = <0>; 590 qcom,local-pid = <0>;
737 qcom,remote-pid = <2>; 591 qcom,remote-pid = <2>;
738 592
739 adsp_smp2p_out: master-kernel 593 adsp_smp2p_out: master-kernel {
740 qcom,entry-name = "mas 594 qcom,entry-name = "master-kernel";
741 #qcom,smem-state-cells 595 #qcom,smem-state-cells = <1>;
742 }; 596 };
743 597
744 adsp_smp2p_in: slave-kernel { 598 adsp_smp2p_in: slave-kernel {
745 qcom,entry-name = "sla 599 qcom,entry-name = "slave-kernel";
746 600
747 interrupt-controller; 601 interrupt-controller;
748 #interrupt-cells = <2> 602 #interrupt-cells = <2>;
749 }; 603 };
750 }; 604 };
751 605
752 smp2p-mpss { 606 smp2p-mpss {
753 compatible = "qcom,smp2p"; 607 compatible = "qcom,smp2p";
754 qcom,smem = <435>, <428>; 608 qcom,smem = <435>, <428>;
755 interrupts = <GIC_SPI 451 IRQ_ 609 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
756 mboxes = <&apss_shared 14>; 610 mboxes = <&apss_shared 14>;
757 qcom,local-pid = <0>; 611 qcom,local-pid = <0>;
758 qcom,remote-pid = <1>; 612 qcom,remote-pid = <1>;
759 613
760 modem_smp2p_out: master-kernel 614 modem_smp2p_out: master-kernel {
761 qcom,entry-name = "mas 615 qcom,entry-name = "master-kernel";
762 #qcom,smem-state-cells 616 #qcom,smem-state-cells = <1>;
763 }; 617 };
764 618
765 modem_smp2p_in: slave-kernel { 619 modem_smp2p_in: slave-kernel {
766 qcom,entry-name = "sla 620 qcom,entry-name = "slave-kernel";
767 interrupt-controller; 621 interrupt-controller;
768 #interrupt-cells = <2> 622 #interrupt-cells = <2>;
769 }; 623 };
770 624
771 ipa_smp2p_out: ipa-ap-to-modem 625 ipa_smp2p_out: ipa-ap-to-modem {
772 qcom,entry-name = "ipa 626 qcom,entry-name = "ipa";
773 #qcom,smem-state-cells 627 #qcom,smem-state-cells = <1>;
774 }; 628 };
775 629
776 ipa_smp2p_in: ipa-modem-to-ap 630 ipa_smp2p_in: ipa-modem-to-ap {
777 qcom,entry-name = "ipa 631 qcom,entry-name = "ipa";
778 interrupt-controller; 632 interrupt-controller;
779 #interrupt-cells = <2> 633 #interrupt-cells = <2>;
780 }; 634 };
781 }; 635 };
782 636
>> 637 psci {
>> 638 compatible = "arm,psci-1.0";
>> 639 method = "smc";
>> 640 };
>> 641
783 soc: soc@0 { 642 soc: soc@0 {
784 #address-cells = <2>; 643 #address-cells = <2>;
785 #size-cells = <2>; 644 #size-cells = <2>;
786 ranges = <0 0 0 0 0x10 0>; 645 ranges = <0 0 0 0 0x10 0>;
787 dma-ranges = <0 0 0 0 0x10 0>; 646 dma-ranges = <0 0 0 0 0x10 0>;
788 compatible = "simple-bus"; 647 compatible = "simple-bus";
789 648
790 gcc: clock-controller@100000 { 649 gcc: clock-controller@100000 {
791 compatible = "qcom,gcc 650 compatible = "qcom,gcc-sc7180";
792 reg = <0 0x00100000 0 651 reg = <0 0x00100000 0 0x1f0000>;
793 clocks = <&rpmhcc RPMH 652 clocks = <&rpmhcc RPMH_CXO_CLK>,
794 <&rpmhcc RPMH 653 <&rpmhcc RPMH_CXO_CLK_A>,
795 <&sleep_clk>; 654 <&sleep_clk>;
796 clock-names = "bi_tcxo 655 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
797 #clock-cells = <1>; 656 #clock-cells = <1>;
798 #reset-cells = <1>; 657 #reset-cells = <1>;
799 #power-domain-cells = 658 #power-domain-cells = <1>;
800 power-domains = <&rpmh <<
801 }; 659 };
802 660
803 qfprom: efuse@784000 { 661 qfprom: efuse@784000 {
804 compatible = "qcom,sc7 !! 662 compatible = "qcom,qfprom";
805 reg = <0 0x00784000 0 !! 663 reg = <0 0x00784000 0 0x8ff>,
806 <0 0x00780000 0 664 <0 0x00780000 0 0x7a0>,
807 <0 0x00782000 0 665 <0 0x00782000 0 0x100>,
808 <0 0x00786000 0 666 <0 0x00786000 0 0x1fff>;
809 667
810 clocks = <&gcc GCC_SEC 668 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>;
811 clock-names = "core"; 669 clock-names = "core";
812 #address-cells = <1>; 670 #address-cells = <1>;
813 #size-cells = <1>; 671 #size-cells = <1>;
814 672
815 qusb2p_hstx_trim: hstx 673 qusb2p_hstx_trim: hstx-trim-primary@25b {
816 reg = <0x25b 0 674 reg = <0x25b 0x1>;
817 bits = <1 3>; 675 bits = <1 3>;
818 }; 676 };
819 <<
820 gpu_speed_bin: gpu-spe <<
821 reg = <0x1d2 0 <<
822 bits = <5 8>; <<
823 }; <<
824 }; 677 };
825 678
826 sdhc_1: mmc@7c4000 { !! 679 sdhc_1: sdhci@7c4000 {
827 compatible = "qcom,sc7 680 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
828 reg = <0 0x007c4000 0 !! 681 reg = <0 0x7c4000 0 0x1000>,
829 <0 0x007c5000 !! 682 <0 0x07c5000 0 0x1000>;
830 reg-names = "hc", "cqh 683 reg-names = "hc", "cqhci";
831 684
832 iommus = <&apps_smmu 0 685 iommus = <&apps_smmu 0x60 0x0>;
833 interrupts = <GIC_SPI 686 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
834 <GIC_S 687 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
835 interrupt-names = "hc_ 688 interrupt-names = "hc_irq", "pwr_irq";
836 689
837 clocks = <&gcc GCC_SDC !! 690 clocks = <&gcc GCC_SDCC1_APPS_CLK>,
838 <&gcc GCC_SDC !! 691 <&gcc GCC_SDCC1_AHB_CLK>;
839 <&rpmhcc RPMH !! 692 clock-names = "core", "iface";
840 clock-names = "iface", <<
841 interconnects = <&aggr <<
842 <&gem_ <<
843 interconnect-names = " <<
844 power-domains = <&rpmh 693 power-domains = <&rpmhpd SC7180_CX>;
845 operating-points-v2 = 694 operating-points-v2 = <&sdhc1_opp_table>;
846 695
847 bus-width = <8>; 696 bus-width = <8>;
848 non-removable; 697 non-removable;
849 supports-cqe; 698 supports-cqe;
850 699
851 mmc-ddr-1_8v; 700 mmc-ddr-1_8v;
852 mmc-hs200-1_8v; 701 mmc-hs200-1_8v;
853 mmc-hs400-1_8v; 702 mmc-hs400-1_8v;
854 mmc-hs400-enhanced-str 703 mmc-hs400-enhanced-strobe;
855 704
856 status = "disabled"; 705 status = "disabled";
857 706
858 sdhc1_opp_table: opp-t !! 707 sdhc1_opp_table: sdhc1-opp-table {
859 compatible = " 708 compatible = "operating-points-v2";
860 709
861 opp-100000000 710 opp-100000000 {
862 opp-hz 711 opp-hz = /bits/ 64 <100000000>;
863 requir 712 required-opps = <&rpmhpd_opp_low_svs>;
864 opp-pe <<
865 opp-av <<
866 }; 713 };
867 714
868 opp-384000000 715 opp-384000000 {
869 opp-hz 716 opp-hz = /bits/ 64 <384000000>;
870 requir !! 717 required-opps = <&rpmhpd_opp_svs_l1>;
871 opp-pe <<
872 opp-av <<
873 }; 718 };
874 }; 719 };
875 }; 720 };
876 721
>> 722 qup_opp_table: qup-opp-table {
>> 723 compatible = "operating-points-v2";
>> 724
>> 725 opp-75000000 {
>> 726 opp-hz = /bits/ 64 <75000000>;
>> 727 required-opps = <&rpmhpd_opp_low_svs>;
>> 728 };
>> 729
>> 730 opp-100000000 {
>> 731 opp-hz = /bits/ 64 <100000000>;
>> 732 required-opps = <&rpmhpd_opp_svs>;
>> 733 };
>> 734
>> 735 opp-128000000 {
>> 736 opp-hz = /bits/ 64 <128000000>;
>> 737 required-opps = <&rpmhpd_opp_nom>;
>> 738 };
>> 739 };
>> 740
877 qupv3_id_0: geniqup@8c0000 { 741 qupv3_id_0: geniqup@8c0000 {
878 compatible = "qcom,gen 742 compatible = "qcom,geni-se-qup";
879 reg = <0 0x008c0000 0 743 reg = <0 0x008c0000 0 0x6000>;
880 clock-names = "m-ahb", 744 clock-names = "m-ahb", "s-ahb";
881 clocks = <&gcc GCC_QUP 745 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
882 <&gcc GCC_QUP 746 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
883 #address-cells = <2>; 747 #address-cells = <2>;
884 #size-cells = <2>; 748 #size-cells = <2>;
885 ranges; 749 ranges;
886 iommus = <&apps_smmu 0 750 iommus = <&apps_smmu 0x43 0x0>;
>> 751 interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>;
>> 752 interconnect-names = "qup-core";
887 status = "disabled"; 753 status = "disabled";
888 754
889 i2c0: i2c@880000 { 755 i2c0: i2c@880000 {
890 compatible = " 756 compatible = "qcom,geni-i2c";
891 reg = <0 0x008 757 reg = <0 0x00880000 0 0x4000>;
892 clock-names = 758 clock-names = "se";
893 clocks = <&gcc 759 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
894 pinctrl-names 760 pinctrl-names = "default";
895 pinctrl-0 = <& 761 pinctrl-0 = <&qup_i2c0_default>;
896 interrupts = < 762 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
897 #address-cells 763 #address-cells = <1>;
898 #size-cells = 764 #size-cells = <0>;
899 interconnects !! 765 interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
900 !! 766 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>,
901 !! 767 <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
902 interconnect-n 768 interconnect-names = "qup-core", "qup-config",
903 769 "qup-memory";
904 power-domains <<
905 required-opps <<
906 status = "disa 770 status = "disabled";
907 }; 771 };
908 772
909 spi0: spi@880000 { 773 spi0: spi@880000 {
910 compatible = " 774 compatible = "qcom,geni-spi";
911 reg = <0 0x008 775 reg = <0 0x00880000 0 0x4000>;
912 clock-names = 776 clock-names = "se";
913 clocks = <&gcc 777 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
914 pinctrl-names 778 pinctrl-names = "default";
915 pinctrl-0 = <& !! 779 pinctrl-0 = <&qup_spi0_default>;
916 interrupts = < 780 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
917 #address-cells 781 #address-cells = <1>;
918 #size-cells = 782 #size-cells = <0>;
919 power-domains 783 power-domains = <&rpmhpd SC7180_CX>;
920 operating-poin 784 operating-points-v2 = <&qup_opp_table>;
921 interconnects !! 785 interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
922 !! 786 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
923 interconnect-n 787 interconnect-names = "qup-core", "qup-config";
924 status = "disa 788 status = "disabled";
925 }; 789 };
926 790
927 uart0: serial@880000 { 791 uart0: serial@880000 {
928 compatible = " 792 compatible = "qcom,geni-uart";
929 reg = <0 0x008 793 reg = <0 0x00880000 0 0x4000>;
930 clock-names = 794 clock-names = "se";
931 clocks = <&gcc 795 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
932 pinctrl-names 796 pinctrl-names = "default";
933 pinctrl-0 = <& 797 pinctrl-0 = <&qup_uart0_default>;
934 interrupts = < 798 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
935 power-domains 799 power-domains = <&rpmhpd SC7180_CX>;
936 operating-poin 800 operating-points-v2 = <&qup_opp_table>;
937 interconnects !! 801 interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
938 !! 802 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
939 interconnect-n 803 interconnect-names = "qup-core", "qup-config";
940 status = "disa 804 status = "disabled";
941 }; 805 };
942 806
943 i2c1: i2c@884000 { 807 i2c1: i2c@884000 {
944 compatible = " 808 compatible = "qcom,geni-i2c";
945 reg = <0 0x008 809 reg = <0 0x00884000 0 0x4000>;
946 clock-names = 810 clock-names = "se";
947 clocks = <&gcc 811 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
948 pinctrl-names 812 pinctrl-names = "default";
949 pinctrl-0 = <& 813 pinctrl-0 = <&qup_i2c1_default>;
950 interrupts = < 814 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
951 #address-cells 815 #address-cells = <1>;
952 #size-cells = 816 #size-cells = <0>;
953 interconnects !! 817 interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
954 !! 818 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>,
955 !! 819 <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
956 interconnect-n 820 interconnect-names = "qup-core", "qup-config",
957 821 "qup-memory";
958 power-domains <<
959 required-opps <<
960 status = "disa 822 status = "disabled";
961 }; 823 };
962 824
963 spi1: spi@884000 { 825 spi1: spi@884000 {
964 compatible = " 826 compatible = "qcom,geni-spi";
965 reg = <0 0x008 827 reg = <0 0x00884000 0 0x4000>;
966 clock-names = 828 clock-names = "se";
967 clocks = <&gcc 829 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
968 pinctrl-names 830 pinctrl-names = "default";
969 pinctrl-0 = <& !! 831 pinctrl-0 = <&qup_spi1_default>;
970 interrupts = < 832 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
971 #address-cells 833 #address-cells = <1>;
972 #size-cells = 834 #size-cells = <0>;
973 power-domains 835 power-domains = <&rpmhpd SC7180_CX>;
974 operating-poin 836 operating-points-v2 = <&qup_opp_table>;
975 interconnects !! 837 interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
976 !! 838 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
977 interconnect-n 839 interconnect-names = "qup-core", "qup-config";
978 status = "disa 840 status = "disabled";
979 }; 841 };
980 842
981 uart1: serial@884000 { 843 uart1: serial@884000 {
982 compatible = " 844 compatible = "qcom,geni-uart";
983 reg = <0 0x008 845 reg = <0 0x00884000 0 0x4000>;
984 clock-names = 846 clock-names = "se";
985 clocks = <&gcc 847 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
986 pinctrl-names 848 pinctrl-names = "default";
987 pinctrl-0 = <& 849 pinctrl-0 = <&qup_uart1_default>;
988 interrupts = < 850 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
989 power-domains 851 power-domains = <&rpmhpd SC7180_CX>;
990 operating-poin 852 operating-points-v2 = <&qup_opp_table>;
991 interconnects !! 853 interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
992 !! 854 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
993 interconnect-n 855 interconnect-names = "qup-core", "qup-config";
994 status = "disa 856 status = "disabled";
995 }; 857 };
996 858
997 i2c2: i2c@888000 { 859 i2c2: i2c@888000 {
998 compatible = " 860 compatible = "qcom,geni-i2c";
999 reg = <0 0x008 861 reg = <0 0x00888000 0 0x4000>;
1000 clock-names = 862 clock-names = "se";
1001 clocks = <&gc 863 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1002 pinctrl-names 864 pinctrl-names = "default";
1003 pinctrl-0 = < 865 pinctrl-0 = <&qup_i2c2_default>;
1004 interrupts = 866 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1005 #address-cell 867 #address-cells = <1>;
1006 #size-cells = 868 #size-cells = <0>;
1007 interconnects !! 869 interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
1008 !! 870 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>,
1009 !! 871 <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
1010 interconnect- 872 interconnect-names = "qup-core", "qup-config",
1011 873 "qup-memory";
1012 power-domains <<
1013 required-opps <<
1014 status = "dis 874 status = "disabled";
1015 }; 875 };
1016 876
1017 uart2: serial@888000 877 uart2: serial@888000 {
1018 compatible = 878 compatible = "qcom,geni-uart";
1019 reg = <0 0x00 879 reg = <0 0x00888000 0 0x4000>;
1020 clock-names = 880 clock-names = "se";
1021 clocks = <&gc 881 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1022 pinctrl-names 882 pinctrl-names = "default";
1023 pinctrl-0 = < 883 pinctrl-0 = <&qup_uart2_default>;
1024 interrupts = 884 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1025 power-domains 885 power-domains = <&rpmhpd SC7180_CX>;
1026 operating-poi 886 operating-points-v2 = <&qup_opp_table>;
1027 interconnects !! 887 interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
1028 !! 888 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
1029 interconnect- 889 interconnect-names = "qup-core", "qup-config";
1030 status = "dis 890 status = "disabled";
1031 }; 891 };
1032 892
1033 i2c3: i2c@88c000 { 893 i2c3: i2c@88c000 {
1034 compatible = 894 compatible = "qcom,geni-i2c";
1035 reg = <0 0x00 895 reg = <0 0x0088c000 0 0x4000>;
1036 clock-names = 896 clock-names = "se";
1037 clocks = <&gc 897 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1038 pinctrl-names 898 pinctrl-names = "default";
1039 pinctrl-0 = < 899 pinctrl-0 = <&qup_i2c3_default>;
1040 interrupts = 900 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1041 #address-cell 901 #address-cells = <1>;
1042 #size-cells = 902 #size-cells = <0>;
1043 interconnects !! 903 interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
1044 !! 904 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>,
1045 !! 905 <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
1046 interconnect- 906 interconnect-names = "qup-core", "qup-config",
1047 907 "qup-memory";
1048 power-domains <<
1049 required-opps <<
1050 status = "dis 908 status = "disabled";
1051 }; 909 };
1052 910
1053 spi3: spi@88c000 { 911 spi3: spi@88c000 {
1054 compatible = 912 compatible = "qcom,geni-spi";
1055 reg = <0 0x00 913 reg = <0 0x0088c000 0 0x4000>;
1056 clock-names = 914 clock-names = "se";
1057 clocks = <&gc 915 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1058 pinctrl-names 916 pinctrl-names = "default";
1059 pinctrl-0 = < !! 917 pinctrl-0 = <&qup_spi3_default>;
1060 interrupts = 918 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1061 #address-cell 919 #address-cells = <1>;
1062 #size-cells = 920 #size-cells = <0>;
1063 power-domains 921 power-domains = <&rpmhpd SC7180_CX>;
1064 operating-poi 922 operating-points-v2 = <&qup_opp_table>;
1065 interconnects !! 923 interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
1066 !! 924 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
1067 interconnect- 925 interconnect-names = "qup-core", "qup-config";
1068 status = "dis 926 status = "disabled";
1069 }; 927 };
1070 928
1071 uart3: serial@88c000 929 uart3: serial@88c000 {
1072 compatible = 930 compatible = "qcom,geni-uart";
1073 reg = <0 0x00 931 reg = <0 0x0088c000 0 0x4000>;
1074 clock-names = 932 clock-names = "se";
1075 clocks = <&gc 933 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1076 pinctrl-names 934 pinctrl-names = "default";
1077 pinctrl-0 = < 935 pinctrl-0 = <&qup_uart3_default>;
1078 interrupts = 936 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1079 power-domains 937 power-domains = <&rpmhpd SC7180_CX>;
1080 operating-poi 938 operating-points-v2 = <&qup_opp_table>;
1081 interconnects !! 939 interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
1082 !! 940 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
1083 interconnect- 941 interconnect-names = "qup-core", "qup-config";
1084 status = "dis 942 status = "disabled";
1085 }; 943 };
1086 944
1087 i2c4: i2c@890000 { 945 i2c4: i2c@890000 {
1088 compatible = 946 compatible = "qcom,geni-i2c";
1089 reg = <0 0x00 947 reg = <0 0x00890000 0 0x4000>;
1090 clock-names = 948 clock-names = "se";
1091 clocks = <&gc 949 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1092 pinctrl-names 950 pinctrl-names = "default";
1093 pinctrl-0 = < 951 pinctrl-0 = <&qup_i2c4_default>;
1094 interrupts = 952 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1095 #address-cell 953 #address-cells = <1>;
1096 #size-cells = 954 #size-cells = <0>;
1097 interconnects !! 955 interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
1098 !! 956 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>,
1099 !! 957 <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
1100 interconnect- 958 interconnect-names = "qup-core", "qup-config",
1101 959 "qup-memory";
1102 power-domains <<
1103 required-opps <<
1104 status = "dis 960 status = "disabled";
1105 }; 961 };
1106 962
1107 uart4: serial@890000 963 uart4: serial@890000 {
1108 compatible = 964 compatible = "qcom,geni-uart";
1109 reg = <0 0x00 965 reg = <0 0x00890000 0 0x4000>;
1110 clock-names = 966 clock-names = "se";
1111 clocks = <&gc 967 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1112 pinctrl-names 968 pinctrl-names = "default";
1113 pinctrl-0 = < 969 pinctrl-0 = <&qup_uart4_default>;
1114 interrupts = 970 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1115 power-domains 971 power-domains = <&rpmhpd SC7180_CX>;
1116 operating-poi 972 operating-points-v2 = <&qup_opp_table>;
1117 interconnects !! 973 interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
1118 !! 974 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
1119 interconnect- 975 interconnect-names = "qup-core", "qup-config";
1120 status = "dis 976 status = "disabled";
1121 }; 977 };
1122 978
1123 i2c5: i2c@894000 { 979 i2c5: i2c@894000 {
1124 compatible = 980 compatible = "qcom,geni-i2c";
1125 reg = <0 0x00 981 reg = <0 0x00894000 0 0x4000>;
1126 clock-names = 982 clock-names = "se";
1127 clocks = <&gc 983 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1128 pinctrl-names 984 pinctrl-names = "default";
1129 pinctrl-0 = < 985 pinctrl-0 = <&qup_i2c5_default>;
1130 interrupts = 986 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1131 #address-cell 987 #address-cells = <1>;
1132 #size-cells = 988 #size-cells = <0>;
1133 interconnects !! 989 interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
1134 !! 990 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>,
1135 !! 991 <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
1136 interconnect- 992 interconnect-names = "qup-core", "qup-config",
1137 993 "qup-memory";
1138 power-domains <<
1139 required-opps <<
1140 status = "dis 994 status = "disabled";
1141 }; 995 };
1142 996
1143 spi5: spi@894000 { 997 spi5: spi@894000 {
1144 compatible = 998 compatible = "qcom,geni-spi";
1145 reg = <0 0x00 999 reg = <0 0x00894000 0 0x4000>;
1146 clock-names = 1000 clock-names = "se";
1147 clocks = <&gc 1001 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1148 pinctrl-names 1002 pinctrl-names = "default";
1149 pinctrl-0 = < !! 1003 pinctrl-0 = <&qup_spi5_default>;
1150 interrupts = 1004 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1151 #address-cell 1005 #address-cells = <1>;
1152 #size-cells = 1006 #size-cells = <0>;
1153 power-domains 1007 power-domains = <&rpmhpd SC7180_CX>;
1154 operating-poi 1008 operating-points-v2 = <&qup_opp_table>;
1155 interconnects !! 1009 interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
1156 !! 1010 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
1157 interconnect- 1011 interconnect-names = "qup-core", "qup-config";
1158 status = "dis 1012 status = "disabled";
1159 }; 1013 };
1160 1014
1161 uart5: serial@894000 1015 uart5: serial@894000 {
1162 compatible = 1016 compatible = "qcom,geni-uart";
1163 reg = <0 0x00 1017 reg = <0 0x00894000 0 0x4000>;
1164 clock-names = 1018 clock-names = "se";
1165 clocks = <&gc 1019 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1166 pinctrl-names 1020 pinctrl-names = "default";
1167 pinctrl-0 = < 1021 pinctrl-0 = <&qup_uart5_default>;
1168 interrupts = 1022 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1169 power-domains 1023 power-domains = <&rpmhpd SC7180_CX>;
1170 operating-poi 1024 operating-points-v2 = <&qup_opp_table>;
1171 interconnects !! 1025 interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
1172 !! 1026 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
1173 interconnect- 1027 interconnect-names = "qup-core", "qup-config";
1174 status = "dis 1028 status = "disabled";
1175 }; 1029 };
1176 }; 1030 };
1177 1031
1178 qupv3_id_1: geniqup@ac0000 { 1032 qupv3_id_1: geniqup@ac0000 {
1179 compatible = "qcom,ge 1033 compatible = "qcom,geni-se-qup";
1180 reg = <0 0x00ac0000 0 1034 reg = <0 0x00ac0000 0 0x6000>;
1181 clock-names = "m-ahb" 1035 clock-names = "m-ahb", "s-ahb";
1182 clocks = <&gcc GCC_QU 1036 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1183 <&gcc GCC_QU 1037 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1184 #address-cells = <2>; 1038 #address-cells = <2>;
1185 #size-cells = <2>; 1039 #size-cells = <2>;
1186 ranges; 1040 ranges;
1187 iommus = <&apps_smmu 1041 iommus = <&apps_smmu 0x4c3 0x0>;
>> 1042 interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>;
>> 1043 interconnect-names = "qup-core";
1188 status = "disabled"; 1044 status = "disabled";
1189 1045
1190 i2c6: i2c@a80000 { 1046 i2c6: i2c@a80000 {
1191 compatible = 1047 compatible = "qcom,geni-i2c";
1192 reg = <0 0x00 1048 reg = <0 0x00a80000 0 0x4000>;
1193 clock-names = 1049 clock-names = "se";
1194 clocks = <&gc 1050 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1195 pinctrl-names 1051 pinctrl-names = "default";
1196 pinctrl-0 = < 1052 pinctrl-0 = <&qup_i2c6_default>;
1197 interrupts = 1053 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1198 #address-cell 1054 #address-cells = <1>;
1199 #size-cells = 1055 #size-cells = <0>;
1200 interconnects !! 1056 interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
1201 !! 1057 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
1202 !! 1058 <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
1203 interconnect- 1059 interconnect-names = "qup-core", "qup-config",
1204 1060 "qup-memory";
1205 power-domains <<
1206 required-opps <<
1207 status = "dis 1061 status = "disabled";
1208 }; 1062 };
1209 1063
1210 spi6: spi@a80000 { 1064 spi6: spi@a80000 {
1211 compatible = 1065 compatible = "qcom,geni-spi";
1212 reg = <0 0x00 1066 reg = <0 0x00a80000 0 0x4000>;
1213 clock-names = 1067 clock-names = "se";
1214 clocks = <&gc 1068 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1215 pinctrl-names 1069 pinctrl-names = "default";
1216 pinctrl-0 = < !! 1070 pinctrl-0 = <&qup_spi6_default>;
1217 interrupts = 1071 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1218 #address-cell 1072 #address-cells = <1>;
1219 #size-cells = 1073 #size-cells = <0>;
1220 power-domains 1074 power-domains = <&rpmhpd SC7180_CX>;
1221 operating-poi 1075 operating-points-v2 = <&qup_opp_table>;
1222 interconnects !! 1076 interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
1223 !! 1077 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
1224 interconnect- 1078 interconnect-names = "qup-core", "qup-config";
1225 status = "dis 1079 status = "disabled";
1226 }; 1080 };
1227 1081
1228 uart6: serial@a80000 1082 uart6: serial@a80000 {
1229 compatible = 1083 compatible = "qcom,geni-uart";
1230 reg = <0 0x00 1084 reg = <0 0x00a80000 0 0x4000>;
1231 clock-names = 1085 clock-names = "se";
1232 clocks = <&gc 1086 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1233 pinctrl-names 1087 pinctrl-names = "default";
1234 pinctrl-0 = < 1088 pinctrl-0 = <&qup_uart6_default>;
1235 interrupts = 1089 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1236 power-domains 1090 power-domains = <&rpmhpd SC7180_CX>;
1237 operating-poi 1091 operating-points-v2 = <&qup_opp_table>;
1238 interconnects !! 1092 interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
1239 !! 1093 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
1240 interconnect- 1094 interconnect-names = "qup-core", "qup-config";
1241 status = "dis 1095 status = "disabled";
1242 }; 1096 };
1243 1097
1244 i2c7: i2c@a84000 { 1098 i2c7: i2c@a84000 {
1245 compatible = 1099 compatible = "qcom,geni-i2c";
1246 reg = <0 0x00 1100 reg = <0 0x00a84000 0 0x4000>;
1247 clock-names = 1101 clock-names = "se";
1248 clocks = <&gc 1102 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1249 pinctrl-names 1103 pinctrl-names = "default";
1250 pinctrl-0 = < 1104 pinctrl-0 = <&qup_i2c7_default>;
1251 interrupts = 1105 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1252 #address-cell 1106 #address-cells = <1>;
1253 #size-cells = 1107 #size-cells = <0>;
1254 interconnects !! 1108 interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
1255 !! 1109 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
1256 !! 1110 <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
1257 interconnect- 1111 interconnect-names = "qup-core", "qup-config",
1258 1112 "qup-memory";
1259 power-domains <<
1260 required-opps <<
1261 status = "dis 1113 status = "disabled";
1262 }; 1114 };
1263 1115
1264 uart7: serial@a84000 1116 uart7: serial@a84000 {
1265 compatible = 1117 compatible = "qcom,geni-uart";
1266 reg = <0 0x00 1118 reg = <0 0x00a84000 0 0x4000>;
1267 clock-names = 1119 clock-names = "se";
1268 clocks = <&gc 1120 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1269 pinctrl-names 1121 pinctrl-names = "default";
1270 pinctrl-0 = < 1122 pinctrl-0 = <&qup_uart7_default>;
1271 interrupts = 1123 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1272 power-domains 1124 power-domains = <&rpmhpd SC7180_CX>;
1273 operating-poi 1125 operating-points-v2 = <&qup_opp_table>;
1274 interconnects !! 1126 interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
1275 !! 1127 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
1276 interconnect- 1128 interconnect-names = "qup-core", "qup-config";
1277 status = "dis 1129 status = "disabled";
1278 }; 1130 };
1279 1131
1280 i2c8: i2c@a88000 { 1132 i2c8: i2c@a88000 {
1281 compatible = 1133 compatible = "qcom,geni-i2c";
1282 reg = <0 0x00 1134 reg = <0 0x00a88000 0 0x4000>;
1283 clock-names = 1135 clock-names = "se";
1284 clocks = <&gc 1136 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1285 pinctrl-names 1137 pinctrl-names = "default";
1286 pinctrl-0 = < 1138 pinctrl-0 = <&qup_i2c8_default>;
1287 interrupts = 1139 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1288 #address-cell 1140 #address-cells = <1>;
1289 #size-cells = 1141 #size-cells = <0>;
1290 interconnects !! 1142 interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
1291 !! 1143 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
1292 !! 1144 <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
1293 interconnect- 1145 interconnect-names = "qup-core", "qup-config",
1294 1146 "qup-memory";
1295 power-domains <<
1296 required-opps <<
1297 status = "dis 1147 status = "disabled";
1298 }; 1148 };
1299 1149
1300 spi8: spi@a88000 { 1150 spi8: spi@a88000 {
1301 compatible = 1151 compatible = "qcom,geni-spi";
1302 reg = <0 0x00 1152 reg = <0 0x00a88000 0 0x4000>;
1303 clock-names = 1153 clock-names = "se";
1304 clocks = <&gc 1154 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1305 pinctrl-names 1155 pinctrl-names = "default";
1306 pinctrl-0 = < !! 1156 pinctrl-0 = <&qup_spi8_default>;
1307 interrupts = 1157 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1308 #address-cell 1158 #address-cells = <1>;
1309 #size-cells = 1159 #size-cells = <0>;
1310 power-domains 1160 power-domains = <&rpmhpd SC7180_CX>;
1311 operating-poi 1161 operating-points-v2 = <&qup_opp_table>;
1312 interconnects !! 1162 interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
1313 !! 1163 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
1314 interconnect- 1164 interconnect-names = "qup-core", "qup-config";
1315 status = "dis 1165 status = "disabled";
1316 }; 1166 };
1317 1167
1318 uart8: serial@a88000 1168 uart8: serial@a88000 {
1319 compatible = 1169 compatible = "qcom,geni-debug-uart";
1320 reg = <0 0x00 1170 reg = <0 0x00a88000 0 0x4000>;
1321 clock-names = 1171 clock-names = "se";
1322 clocks = <&gc 1172 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1323 pinctrl-names 1173 pinctrl-names = "default";
1324 pinctrl-0 = < 1174 pinctrl-0 = <&qup_uart8_default>;
1325 interrupts = 1175 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1326 power-domains 1176 power-domains = <&rpmhpd SC7180_CX>;
1327 operating-poi 1177 operating-points-v2 = <&qup_opp_table>;
1328 interconnects !! 1178 interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
1329 !! 1179 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
1330 interconnect- 1180 interconnect-names = "qup-core", "qup-config";
1331 status = "dis 1181 status = "disabled";
1332 }; 1182 };
1333 1183
1334 i2c9: i2c@a8c000 { 1184 i2c9: i2c@a8c000 {
1335 compatible = 1185 compatible = "qcom,geni-i2c";
1336 reg = <0 0x00 1186 reg = <0 0x00a8c000 0 0x4000>;
1337 clock-names = 1187 clock-names = "se";
1338 clocks = <&gc 1188 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1339 pinctrl-names 1189 pinctrl-names = "default";
1340 pinctrl-0 = < 1190 pinctrl-0 = <&qup_i2c9_default>;
1341 interrupts = 1191 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1342 #address-cell 1192 #address-cells = <1>;
1343 #size-cells = 1193 #size-cells = <0>;
1344 interconnects !! 1194 interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
1345 !! 1195 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
1346 !! 1196 <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
1347 interconnect- 1197 interconnect-names = "qup-core", "qup-config",
1348 1198 "qup-memory";
1349 power-domains <<
1350 required-opps <<
1351 status = "dis 1199 status = "disabled";
1352 }; 1200 };
1353 1201
1354 uart9: serial@a8c000 1202 uart9: serial@a8c000 {
1355 compatible = 1203 compatible = "qcom,geni-uart";
1356 reg = <0 0x00 1204 reg = <0 0x00a8c000 0 0x4000>;
1357 clock-names = 1205 clock-names = "se";
1358 clocks = <&gc 1206 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1359 pinctrl-names 1207 pinctrl-names = "default";
1360 pinctrl-0 = < 1208 pinctrl-0 = <&qup_uart9_default>;
1361 interrupts = 1209 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1362 power-domains 1210 power-domains = <&rpmhpd SC7180_CX>;
1363 operating-poi 1211 operating-points-v2 = <&qup_opp_table>;
1364 interconnects !! 1212 interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
1365 !! 1213 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
1366 interconnect- 1214 interconnect-names = "qup-core", "qup-config";
1367 status = "dis 1215 status = "disabled";
1368 }; 1216 };
1369 1217
1370 i2c10: i2c@a90000 { 1218 i2c10: i2c@a90000 {
1371 compatible = 1219 compatible = "qcom,geni-i2c";
1372 reg = <0 0x00 1220 reg = <0 0x00a90000 0 0x4000>;
1373 clock-names = 1221 clock-names = "se";
1374 clocks = <&gc 1222 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1375 pinctrl-names 1223 pinctrl-names = "default";
1376 pinctrl-0 = < 1224 pinctrl-0 = <&qup_i2c10_default>;
1377 interrupts = 1225 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1378 #address-cell 1226 #address-cells = <1>;
1379 #size-cells = 1227 #size-cells = <0>;
1380 interconnects !! 1228 interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
1381 !! 1229 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
1382 !! 1230 <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
1383 interconnect- 1231 interconnect-names = "qup-core", "qup-config",
1384 1232 "qup-memory";
1385 power-domains <<
1386 required-opps <<
1387 status = "dis 1233 status = "disabled";
1388 }; 1234 };
1389 1235
1390 spi10: spi@a90000 { 1236 spi10: spi@a90000 {
1391 compatible = 1237 compatible = "qcom,geni-spi";
1392 reg = <0 0x00 1238 reg = <0 0x00a90000 0 0x4000>;
1393 clock-names = 1239 clock-names = "se";
1394 clocks = <&gc 1240 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1395 pinctrl-names 1241 pinctrl-names = "default";
1396 pinctrl-0 = < !! 1242 pinctrl-0 = <&qup_spi10_default>;
1397 interrupts = 1243 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1398 #address-cell 1244 #address-cells = <1>;
1399 #size-cells = 1245 #size-cells = <0>;
1400 power-domains 1246 power-domains = <&rpmhpd SC7180_CX>;
1401 operating-poi 1247 operating-points-v2 = <&qup_opp_table>;
1402 interconnects !! 1248 interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
1403 !! 1249 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
1404 interconnect- 1250 interconnect-names = "qup-core", "qup-config";
1405 status = "dis 1251 status = "disabled";
1406 }; 1252 };
1407 1253
1408 uart10: serial@a90000 1254 uart10: serial@a90000 {
1409 compatible = 1255 compatible = "qcom,geni-uart";
1410 reg = <0 0x00 1256 reg = <0 0x00a90000 0 0x4000>;
1411 clock-names = 1257 clock-names = "se";
1412 clocks = <&gc 1258 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1413 pinctrl-names 1259 pinctrl-names = "default";
1414 pinctrl-0 = < 1260 pinctrl-0 = <&qup_uart10_default>;
1415 interrupts = 1261 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1416 power-domains 1262 power-domains = <&rpmhpd SC7180_CX>;
1417 operating-poi 1263 operating-points-v2 = <&qup_opp_table>;
1418 interconnects !! 1264 interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
1419 !! 1265 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
1420 interconnect- 1266 interconnect-names = "qup-core", "qup-config";
1421 status = "dis 1267 status = "disabled";
1422 }; 1268 };
1423 1269
1424 i2c11: i2c@a94000 { 1270 i2c11: i2c@a94000 {
1425 compatible = 1271 compatible = "qcom,geni-i2c";
1426 reg = <0 0x00 1272 reg = <0 0x00a94000 0 0x4000>;
1427 clock-names = 1273 clock-names = "se";
1428 clocks = <&gc 1274 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1429 pinctrl-names 1275 pinctrl-names = "default";
1430 pinctrl-0 = < 1276 pinctrl-0 = <&qup_i2c11_default>;
1431 interrupts = 1277 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1432 #address-cell 1278 #address-cells = <1>;
1433 #size-cells = 1279 #size-cells = <0>;
1434 interconnects !! 1280 interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
1435 !! 1281 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
1436 !! 1282 <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
1437 interconnect- 1283 interconnect-names = "qup-core", "qup-config",
1438 1284 "qup-memory";
1439 power-domains <<
1440 required-opps <<
1441 status = "dis 1285 status = "disabled";
1442 }; 1286 };
1443 1287
1444 spi11: spi@a94000 { 1288 spi11: spi@a94000 {
1445 compatible = 1289 compatible = "qcom,geni-spi";
1446 reg = <0 0x00 1290 reg = <0 0x00a94000 0 0x4000>;
1447 clock-names = 1291 clock-names = "se";
1448 clocks = <&gc 1292 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1449 pinctrl-names 1293 pinctrl-names = "default";
1450 pinctrl-0 = < !! 1294 pinctrl-0 = <&qup_spi11_default>;
1451 interrupts = 1295 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1452 #address-cell 1296 #address-cells = <1>;
1453 #size-cells = 1297 #size-cells = <0>;
1454 power-domains 1298 power-domains = <&rpmhpd SC7180_CX>;
1455 operating-poi 1299 operating-points-v2 = <&qup_opp_table>;
1456 interconnects !! 1300 interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
1457 !! 1301 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
1458 interconnect- 1302 interconnect-names = "qup-core", "qup-config";
1459 status = "dis 1303 status = "disabled";
1460 }; 1304 };
1461 1305
1462 uart11: serial@a94000 1306 uart11: serial@a94000 {
1463 compatible = 1307 compatible = "qcom,geni-uart";
1464 reg = <0 0x00 1308 reg = <0 0x00a94000 0 0x4000>;
1465 clock-names = 1309 clock-names = "se";
1466 clocks = <&gc 1310 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1467 pinctrl-names 1311 pinctrl-names = "default";
1468 pinctrl-0 = < 1312 pinctrl-0 = <&qup_uart11_default>;
1469 interrupts = 1313 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1470 power-domains 1314 power-domains = <&rpmhpd SC7180_CX>;
1471 operating-poi 1315 operating-points-v2 = <&qup_opp_table>;
1472 interconnects !! 1316 interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
1473 !! 1317 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
1474 interconnect- 1318 interconnect-names = "qup-core", "qup-config";
1475 status = "dis 1319 status = "disabled";
1476 }; 1320 };
1477 }; 1321 };
1478 1322
1479 config_noc: interconnect@1500 1323 config_noc: interconnect@1500000 {
1480 compatible = "qcom,sc 1324 compatible = "qcom,sc7180-config-noc";
1481 reg = <0 0x01500000 0 1325 reg = <0 0x01500000 0 0x28000>;
1482 #interconnect-cells = !! 1326 #interconnect-cells = <1>;
1483 qcom,bcm-voters = <&a 1327 qcom,bcm-voters = <&apps_bcm_voter>;
1484 }; 1328 };
1485 1329
1486 system_noc: interconnect@1620 1330 system_noc: interconnect@1620000 {
1487 compatible = "qcom,sc 1331 compatible = "qcom,sc7180-system-noc";
1488 reg = <0 0x01620000 0 1332 reg = <0 0x01620000 0 0x17080>;
1489 #interconnect-cells = !! 1333 #interconnect-cells = <1>;
1490 qcom,bcm-voters = <&a 1334 qcom,bcm-voters = <&apps_bcm_voter>;
1491 }; 1335 };
1492 1336
1493 mc_virt: interconnect@1638000 1337 mc_virt: interconnect@1638000 {
1494 compatible = "qcom,sc 1338 compatible = "qcom,sc7180-mc-virt";
1495 reg = <0 0x01638000 0 1339 reg = <0 0x01638000 0 0x1000>;
1496 #interconnect-cells = !! 1340 #interconnect-cells = <1>;
1497 qcom,bcm-voters = <&a 1341 qcom,bcm-voters = <&apps_bcm_voter>;
1498 }; 1342 };
1499 1343
1500 qup_virt: interconnect@165000 1344 qup_virt: interconnect@1650000 {
1501 compatible = "qcom,sc 1345 compatible = "qcom,sc7180-qup-virt";
1502 reg = <0 0x01650000 0 1346 reg = <0 0x01650000 0 0x1000>;
1503 #interconnect-cells = !! 1347 #interconnect-cells = <1>;
1504 qcom,bcm-voters = <&a 1348 qcom,bcm-voters = <&apps_bcm_voter>;
1505 }; 1349 };
1506 1350
1507 aggre1_noc: interconnect@16e0 1351 aggre1_noc: interconnect@16e0000 {
1508 compatible = "qcom,sc 1352 compatible = "qcom,sc7180-aggre1-noc";
1509 reg = <0 0x016e0000 0 1353 reg = <0 0x016e0000 0 0x15080>;
1510 #interconnect-cells = !! 1354 #interconnect-cells = <1>;
1511 qcom,bcm-voters = <&a 1355 qcom,bcm-voters = <&apps_bcm_voter>;
1512 }; 1356 };
1513 1357
1514 aggre2_noc: interconnect@1705 1358 aggre2_noc: interconnect@1705000 {
1515 compatible = "qcom,sc 1359 compatible = "qcom,sc7180-aggre2-noc";
1516 reg = <0 0x01705000 0 1360 reg = <0 0x01705000 0 0x9000>;
1517 #interconnect-cells = !! 1361 #interconnect-cells = <1>;
1518 qcom,bcm-voters = <&a 1362 qcom,bcm-voters = <&apps_bcm_voter>;
1519 }; 1363 };
1520 1364
1521 compute_noc: interconnect@170 1365 compute_noc: interconnect@170e000 {
1522 compatible = "qcom,sc 1366 compatible = "qcom,sc7180-compute-noc";
1523 reg = <0 0x0170e000 0 1367 reg = <0 0x0170e000 0 0x6000>;
1524 #interconnect-cells = !! 1368 #interconnect-cells = <1>;
1525 qcom,bcm-voters = <&a 1369 qcom,bcm-voters = <&apps_bcm_voter>;
1526 }; 1370 };
1527 1371
1528 mmss_noc: interconnect@174000 1372 mmss_noc: interconnect@1740000 {
1529 compatible = "qcom,sc 1373 compatible = "qcom,sc7180-mmss-noc";
1530 reg = <0 0x01740000 0 1374 reg = <0 0x01740000 0 0x1c100>;
1531 #interconnect-cells = !! 1375 #interconnect-cells = <1>;
1532 qcom,bcm-voters = <&a 1376 qcom,bcm-voters = <&apps_bcm_voter>;
1533 }; 1377 };
1534 1378
1535 ufs_mem_hc: ufshc@1d84000 { !! 1379 ipa_virt: interconnect@1e00000 {
1536 compatible = "qcom,sc !! 1380 compatible = "qcom,sc7180-ipa-virt";
1537 "jedec,u !! 1381 reg = <0 0x01e00000 0 0x1000>;
1538 reg = <0 0x01d84000 0 !! 1382 #interconnect-cells = <1>;
1539 interrupts = <GIC_SPI !! 1383 qcom,bcm-voters = <&apps_bcm_voter>;
1540 phys = <&ufs_mem_phy> <<
1541 phy-names = "ufsphy"; <<
1542 lanes-per-direction = <<
1543 #reset-cells = <1>; <<
1544 resets = <&gcc GCC_UF <<
1545 reset-names = "rst"; <<
1546 <<
1547 power-domains = <&gcc <<
1548 <<
1549 iommus = <&apps_smmu <<
1550 <<
1551 clock-names = "core_c <<
1552 "bus_ag <<
1553 "iface_ <<
1554 "core_c <<
1555 "ref_cl <<
1556 "tx_lan <<
1557 "rx_lan <<
1558 clocks = <&gcc GCC_UF <<
1559 <&gcc GCC_AG <<
1560 <&gcc GCC_UF <<
1561 <&gcc GCC_UF <<
1562 <&rpmhcc RPM <<
1563 <&gcc GCC_UF <<
1564 <&gcc GCC_UF <<
1565 freq-table-hz = <5000 <<
1566 <0 0> <<
1567 <0 0> <<
1568 <3750 <<
1569 <0 0> <<
1570 <0 0> <<
1571 <0 0> <<
1572 <<
1573 interconnects = <&agg <<
1574 &mc_ <<
1575 <&gem <<
1576 &con <<
1577 interconnect-names = <<
1578 <<
1579 qcom,ice = <&ice>; <<
1580 <<
1581 status = "disabled"; <<
1582 }; <<
1583 <<
1584 ufs_mem_phy: phy@1d87000 { <<
1585 compatible = "qcom,sc <<
1586 reg = <0 0x01d87000 0 <<
1587 clocks = <&rpmhcc RPM <<
1588 <&gcc GCC_UF <<
1589 <&gcc GCC_UF <<
1590 clock-names = "ref", <<
1591 "ref_au <<
1592 "qref"; <<
1593 power-domains = <&gcc <<
1594 resets = <&ufs_mem_hc <<
1595 reset-names = "ufsphy <<
1596 #phy-cells = <0>; <<
1597 status = "disabled"; <<
1598 }; <<
1599 <<
1600 ice: crypto@1d90000 { <<
1601 compatible = "qcom,sc <<
1602 "qcom,in <<
1603 reg = <0 0x01d90000 0 <<
1604 clocks = <&gcc GCC_UF <<
1605 }; 1384 };
1606 1385
1607 ipa: ipa@1e40000 { 1386 ipa: ipa@1e40000 {
1608 compatible = "qcom,sc 1387 compatible = "qcom,sc7180-ipa";
1609 1388
1610 iommus = <&apps_smmu !! 1389 iommus = <&apps_smmu 0x440 0x3>;
1611 <&apps_smmu !! 1390 reg = <0 0x1e40000 0 0x7000>,
1612 reg = <0 0x01e40000 0 !! 1391 <0 0x1e47000 0 0x2000>,
1613 <0 0x01e47000 0 !! 1392 <0 0x1e04000 0 0x2c000>;
1614 <0 0x01e04000 0 <<
1615 reg-names = "ipa-reg" 1393 reg-names = "ipa-reg",
1616 "ipa-shar 1394 "ipa-shared",
1617 "gsi"; 1395 "gsi";
1618 1396
1619 interrupts-extended = !! 1397 interrupts-extended = <&intc 0 311 IRQ_TYPE_EDGE_RISING>,
1620 !! 1398 <&intc 0 432 IRQ_TYPE_LEVEL_HIGH>,
1621 1399 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1622 1400 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
1623 interrupt-names = "ip 1401 interrupt-names = "ipa",
1624 "gs 1402 "gsi",
1625 "ip 1403 "ipa-clock-query",
1626 "ip 1404 "ipa-setup-ready";
1627 1405
1628 clocks = <&rpmhcc RPM 1406 clocks = <&rpmhcc RPMH_IPA_CLK>;
1629 clock-names = "core"; 1407 clock-names = "core";
1630 1408
1631 interconnects = <&agg !! 1409 interconnects = <&aggre2_noc MASTER_IPA &mc_virt SLAVE_EBI1>,
1632 <&agg !! 1410 <&aggre2_noc MASTER_IPA &system_noc SLAVE_IMEM>,
1633 <&gem !! 1411 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_IPA_CFG>;
1634 interconnect-names = 1412 interconnect-names = "memory",
1635 1413 "imem",
1636 1414 "config";
1637 1415
1638 qcom,qmp = <&aoss_qmp <<
1639 <<
1640 qcom,smem-states = <& 1416 qcom,smem-states = <&ipa_smp2p_out 0>,
1641 <& 1417 <&ipa_smp2p_out 1>;
1642 qcom,smem-state-names 1418 qcom,smem-state-names = "ipa-clock-enabled-valid",
1643 1419 "ipa-clock-enabled";
1644 1420
1645 status = "disabled"; !! 1421 modem-remoteproc = <&remoteproc_mpss>;
1646 }; <<
1647 1422
1648 tcsr_mutex: hwlock@1f40000 { !! 1423 status = "disabled";
1649 compatible = "qcom,tc <<
1650 reg = <0 0x01f40000 0 <<
1651 #hwlock-cells = <1>; <<
1652 }; 1424 };
1653 1425
1654 tcsr_regs_1: syscon@1f60000 { !! 1426 tcsr_mutex_regs: syscon@1f40000 {
1655 compatible = "qcom,sc !! 1427 compatible = "syscon";
1656 reg = <0 0x01f60000 0 !! 1428 reg = <0 0x01f40000 0 0x40000>;
1657 }; 1429 };
1658 1430
1659 tcsr_regs_2: syscon@1fc0000 { !! 1431 tcsr_regs: syscon@1fc0000 {
1660 compatible = "qcom,sc !! 1432 compatible = "syscon";
1661 reg = <0 0x01fc0000 0 1433 reg = <0 0x01fc0000 0 0x40000>;
1662 }; 1434 };
1663 1435
1664 tlmm: pinctrl@3500000 { 1436 tlmm: pinctrl@3500000 {
1665 compatible = "qcom,sc 1437 compatible = "qcom,sc7180-pinctrl";
1666 reg = <0 0x03500000 0 1438 reg = <0 0x03500000 0 0x300000>,
1667 <0 0x03900000 0 1439 <0 0x03900000 0 0x300000>,
1668 <0 0x03d00000 0 1440 <0 0x03d00000 0 0x300000>;
1669 reg-names = "west", " 1441 reg-names = "west", "north", "south";
1670 interrupts = <GIC_SPI 1442 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1671 gpio-controller; 1443 gpio-controller;
1672 #gpio-cells = <2>; 1444 #gpio-cells = <2>;
1673 interrupt-controller; 1445 interrupt-controller;
1674 #interrupt-cells = <2 1446 #interrupt-cells = <2>;
1675 gpio-ranges = <&tlmm 1447 gpio-ranges = <&tlmm 0 0 120>;
1676 wakeup-parent = <&pdc 1448 wakeup-parent = <&pdc>;
1677 1449
1678 dp_hot_plug_det: dp-h !! 1450 qspi_clk: qspi-clk {
1679 pins = "gpio1 !! 1451 pinmux {
1680 function = "d !! 1452 pins = "gpio63";
1681 }; !! 1453 function = "qspi_clk";
1682 !! 1454 };
1683 qspi_clk: qspi-clk-st <<
1684 pins = "gpio6 <<
1685 function = "q <<
1686 }; <<
1687 <<
1688 qspi_cs0: qspi-cs0-st <<
1689 pins = "gpio6 <<
1690 function = "q <<
1691 }; <<
1692 <<
1693 qspi_cs1: qspi-cs1-st <<
1694 pins = "gpio7 <<
1695 function = "q <<
1696 }; <<
1697 <<
1698 qspi_data0: qspi-data <<
1699 pins = "gpio6 <<
1700 function = "q <<
1701 }; <<
1702 <<
1703 qspi_data1: qspi-data <<
1704 pins = "gpio6 <<
1705 function = "q <<
1706 }; <<
1707 <<
1708 qspi_data23: qspi-dat <<
1709 pins = "gpio6 <<
1710 function = "q <<
1711 }; <<
1712 <<
1713 qup_i2c0_default: qup <<
1714 pins = "gpio3 <<
1715 function = "q <<
1716 }; <<
1717 <<
1718 qup_i2c1_default: qup <<
1719 pins = "gpio0 <<
1720 function = "q <<
1721 }; <<
1722 <<
1723 qup_i2c2_default: qup <<
1724 pins = "gpio1 <<
1725 function = "q <<
1726 }; <<
1727 <<
1728 qup_i2c3_default: qup <<
1729 pins = "gpio3 <<
1730 function = "q <<
1731 }; <<
1732 <<
1733 qup_i2c4_default: qup <<
1734 pins = "gpio1 <<
1735 function = "q <<
1736 }; <<
1737 <<
1738 qup_i2c5_default: qup <<
1739 pins = "gpio2 <<
1740 function = "q <<
1741 }; <<
1742 <<
1743 qup_i2c6_default: qup <<
1744 pins = "gpio5 <<
1745 function = "q <<
1746 }; <<
1747 <<
1748 qup_i2c7_default: qup <<
1749 pins = "gpio6 <<
1750 function = "q <<
1751 }; <<
1752 <<
1753 qup_i2c8_default: qup <<
1754 pins = "gpio4 <<
1755 function = "q <<
1756 }; <<
1757 <<
1758 qup_i2c9_default: qup <<
1759 pins = "gpio4 <<
1760 function = "q <<
1761 }; <<
1762 <<
1763 qup_i2c10_default: qu <<
1764 pins = "gpio8 <<
1765 function = "q <<
1766 }; <<
1767 <<
1768 qup_i2c11_default: qu <<
1769 pins = "gpio5 <<
1770 function = "q <<
1771 }; <<
1772 <<
1773 qup_spi0_spi: qup-spi <<
1774 pins = "gpio3 <<
1775 function = "q <<
1776 }; <<
1777 <<
1778 qup_spi0_cs: qup-spi0 <<
1779 pins = "gpio3 <<
1780 function = "q <<
1781 }; <<
1782 <<
1783 qup_spi0_cs_gpio: qup <<
1784 pins = "gpio3 <<
1785 function = "g <<
1786 }; 1455 };
1787 1456
1788 qup_spi1_spi: qup-spi !! 1457 qspi_cs0: qspi-cs0 {
1789 pins = "gpio0 !! 1458 pinmux {
1790 function = "q !! 1459 pins = "gpio68";
>> 1460 function = "qspi_cs";
>> 1461 };
1791 }; 1462 };
1792 1463
1793 qup_spi1_cs: qup-spi1 !! 1464 qspi_cs1: qspi-cs1 {
1794 pins = "gpio3 !! 1465 pinmux {
1795 function = "q !! 1466 pins = "gpio72";
>> 1467 function = "qspi_cs";
>> 1468 };
1796 }; 1469 };
1797 1470
1798 qup_spi1_cs_gpio: qup !! 1471 qspi_data01: qspi-data01 {
1799 pins = "gpio3 !! 1472 pinmux-data {
1800 function = "g !! 1473 pins = "gpio64", "gpio65";
>> 1474 function = "qspi_data";
>> 1475 };
1801 }; 1476 };
1802 1477
1803 qup_spi3_spi: qup-spi !! 1478 qspi_data12: qspi-data12 {
1804 pins = "gpio3 !! 1479 pinmux-data {
1805 function = "q !! 1480 pins = "gpio66", "gpio67";
>> 1481 function = "qspi_data";
>> 1482 };
1806 }; 1483 };
1807 1484
1808 qup_spi3_cs: qup-spi3 !! 1485 qup_i2c0_default: qup-i2c0-default {
1809 pins = "gpio4 !! 1486 pinmux {
1810 function = "q !! 1487 pins = "gpio34", "gpio35";
>> 1488 function = "qup00";
>> 1489 };
1811 }; 1490 };
1812 1491
1813 qup_spi3_cs_gpio: qup !! 1492 qup_i2c1_default: qup-i2c1-default {
1814 pins = "gpio4 !! 1493 pinmux {
1815 function = "g !! 1494 pins = "gpio0", "gpio1";
>> 1495 function = "qup01";
>> 1496 };
1816 }; 1497 };
1817 1498
1818 qup_spi5_spi: qup-spi !! 1499 qup_i2c2_default: qup-i2c2-default {
1819 pins = "gpio2 !! 1500 pinmux {
1820 function = "q !! 1501 pins = "gpio15", "gpio16";
>> 1502 function = "qup02_i2c";
>> 1503 };
1821 }; 1504 };
1822 1505
1823 qup_spi5_cs: qup-spi5 !! 1506 qup_i2c3_default: qup-i2c3-default {
1824 pins = "gpio2 !! 1507 pinmux {
1825 function = "q !! 1508 pins = "gpio38", "gpio39";
>> 1509 function = "qup03";
>> 1510 };
1826 }; 1511 };
1827 1512
1828 qup_spi5_cs_gpio: qup !! 1513 qup_i2c4_default: qup-i2c4-default {
1829 pins = "gpio2 !! 1514 pinmux {
1830 function = "g !! 1515 pins = "gpio115", "gpio116";
>> 1516 function = "qup04_i2c";
>> 1517 };
1831 }; 1518 };
1832 1519
1833 qup_spi6_spi: qup-spi !! 1520 qup_i2c5_default: qup-i2c5-default {
1834 pins = "gpio5 !! 1521 pinmux {
1835 function = "q !! 1522 pins = "gpio25", "gpio26";
>> 1523 function = "qup05";
>> 1524 };
1836 }; 1525 };
1837 1526
1838 qup_spi6_cs: qup-spi6 !! 1527 qup_i2c6_default: qup-i2c6-default {
1839 pins = "gpio6 !! 1528 pinmux {
1840 function = "q !! 1529 pins = "gpio59", "gpio60";
>> 1530 function = "qup10";
>> 1531 };
1841 }; 1532 };
1842 1533
1843 qup_spi6_cs_gpio: qup !! 1534 qup_i2c7_default: qup-i2c7-default {
1844 pins = "gpio6 !! 1535 pinmux {
1845 function = "g !! 1536 pins = "gpio6", "gpio7";
>> 1537 function = "qup11_i2c";
>> 1538 };
1846 }; 1539 };
1847 1540
1848 qup_spi8_spi: qup-spi !! 1541 qup_i2c8_default: qup-i2c8-default {
1849 pins = "gpio4 !! 1542 pinmux {
1850 function = "q !! 1543 pins = "gpio42", "gpio43";
>> 1544 function = "qup12";
>> 1545 };
1851 }; 1546 };
1852 1547
1853 qup_spi8_cs: qup-spi8 !! 1548 qup_i2c9_default: qup-i2c9-default {
1854 pins = "gpio4 !! 1549 pinmux {
1855 function = "q !! 1550 pins = "gpio46", "gpio47";
>> 1551 function = "qup13_i2c";
>> 1552 };
1856 }; 1553 };
1857 1554
1858 qup_spi8_cs_gpio: qup !! 1555 qup_i2c10_default: qup-i2c10-default {
1859 pins = "gpio4 !! 1556 pinmux {
1860 function = "g !! 1557 pins = "gpio86", "gpio87";
>> 1558 function = "qup14";
>> 1559 };
1861 }; 1560 };
1862 1561
1863 qup_spi10_spi: qup-sp !! 1562 qup_i2c11_default: qup-i2c11-default {
1864 pins = "gpio8 !! 1563 pinmux {
1865 function = "q !! 1564 pins = "gpio53", "gpio54";
>> 1565 function = "qup15";
>> 1566 };
1866 }; 1567 };
1867 1568
1868 qup_spi10_cs: qup-spi !! 1569 qup_spi0_default: qup-spi0-default {
1869 pins = "gpio8 !! 1570 pinmux {
1870 function = "q !! 1571 pins = "gpio34", "gpio35",
>> 1572 "gpio36", "gpio37";
>> 1573 function = "qup00";
>> 1574 };
1871 }; 1575 };
1872 1576
1873 qup_spi10_cs_gpio: qu !! 1577 qup_spi1_default: qup-spi1-default {
1874 pins = "gpio8 !! 1578 pinmux {
1875 function = "g !! 1579 pins = "gpio0", "gpio1",
>> 1580 "gpio2", "gpio3";
>> 1581 function = "qup01";
>> 1582 };
1876 }; 1583 };
1877 1584
1878 qup_spi11_spi: qup-sp !! 1585 qup_spi3_default: qup-spi3-default {
1879 pins = "gpio5 !! 1586 pinmux {
1880 function = "q !! 1587 pins = "gpio38", "gpio39",
>> 1588 "gpio40", "gpio41";
>> 1589 function = "qup03";
>> 1590 };
1881 }; 1591 };
1882 1592
1883 qup_spi11_cs: qup-spi !! 1593 qup_spi5_default: qup-spi5-default {
1884 pins = "gpio5 !! 1594 pinmux {
1885 function = "q !! 1595 pins = "gpio25", "gpio26",
>> 1596 "gpio27", "gpio28";
>> 1597 function = "qup05";
>> 1598 };
1886 }; 1599 };
1887 1600
1888 qup_spi11_cs_gpio: qu !! 1601 qup_spi6_default: qup-spi6-default {
1889 pins = "gpio5 !! 1602 pinmux {
1890 function = "g !! 1603 pins = "gpio59", "gpio60",
>> 1604 "gpio61", "gpio62";
>> 1605 function = "qup10";
>> 1606 };
1891 }; 1607 };
1892 1608
1893 qup_uart0_default: qu !! 1609 qup_spi8_default: qup-spi8-default {
1894 qup_uart0_cts !! 1610 pinmux {
1895 pins !! 1611 pins = "gpio42", "gpio43",
1896 funct !! 1612 "gpio44", "gpio45";
>> 1613 function = "qup12";
1897 }; 1614 };
>> 1615 };
1898 1616
1899 qup_uart0_rts !! 1617 qup_spi10_default: qup-spi10-default {
1900 pins !! 1618 pinmux {
1901 funct !! 1619 pins = "gpio86", "gpio87",
>> 1620 "gpio88", "gpio89";
>> 1621 function = "qup14";
1902 }; 1622 };
>> 1623 };
1903 1624
1904 qup_uart0_tx: !! 1625 qup_spi11_default: qup-spi11-default {
1905 pins !! 1626 pinmux {
1906 funct !! 1627 pins = "gpio53", "gpio54",
>> 1628 "gpio55", "gpio56";
>> 1629 function = "qup15";
1907 }; 1630 };
>> 1631 };
1908 1632
1909 qup_uart0_rx: !! 1633 qup_uart0_default: qup-uart0-default {
1910 pins !! 1634 pinmux {
>> 1635 pins = "gpio34", "gpio35",
>> 1636 "gpio36", "gpio37";
1911 funct 1637 function = "qup00";
1912 }; 1638 };
1913 }; 1639 };
1914 1640
1915 qup_uart1_default: qu !! 1641 qup_uart1_default: qup-uart1-default {
1916 qup_uart1_cts !! 1642 pinmux {
1917 pins !! 1643 pins = "gpio0", "gpio1",
1918 funct !! 1644 "gpio2", "gpio3";
1919 }; <<
1920 <<
1921 qup_uart1_rts <<
1922 pins <<
1923 funct <<
1924 }; <<
1925 <<
1926 qup_uart1_tx: <<
1927 pins <<
1928 funct <<
1929 }; <<
1930 <<
1931 qup_uart1_rx: <<
1932 pins <<
1933 funct 1645 function = "qup01";
1934 }; 1646 };
1935 }; 1647 };
1936 1648
1937 qup_uart2_default: qu !! 1649 qup_uart2_default: qup-uart2-default {
1938 qup_uart2_tx: !! 1650 pinmux {
1939 pins !! 1651 pins = "gpio15", "gpio16";
1940 funct <<
1941 }; <<
1942 <<
1943 qup_uart2_rx: <<
1944 pins <<
1945 funct 1652 function = "qup02_uart";
1946 }; 1653 };
1947 }; 1654 };
1948 1655
1949 qup_uart3_default: qu !! 1656 qup_uart3_default: qup-uart3-default {
1950 qup_uart3_cts !! 1657 pinmux {
1951 pins !! 1658 pins = "gpio38", "gpio39",
1952 funct !! 1659 "gpio40", "gpio41";
1953 }; <<
1954 <<
1955 qup_uart3_rts <<
1956 pins <<
1957 funct <<
1958 }; <<
1959 <<
1960 qup_uart3_tx: <<
1961 pins <<
1962 funct <<
1963 }; <<
1964 <<
1965 qup_uart3_rx: <<
1966 pins <<
1967 funct 1660 function = "qup03";
1968 }; 1661 };
1969 }; 1662 };
1970 1663
1971 qup_uart4_default: qu !! 1664 qup_uart4_default: qup-uart4-default {
1972 qup_uart4_tx: !! 1665 pinmux {
1973 pins !! 1666 pins = "gpio115", "gpio116";
1974 funct <<
1975 }; <<
1976 <<
1977 qup_uart4_rx: <<
1978 pins <<
1979 funct 1667 function = "qup04_uart";
1980 }; 1668 };
1981 }; 1669 };
1982 1670
1983 qup_uart5_default: qu !! 1671 qup_uart5_default: qup-uart5-default {
1984 qup_uart5_cts !! 1672 pinmux {
1985 pins !! 1673 pins = "gpio25", "gpio26",
1986 funct !! 1674 "gpio27", "gpio28";
1987 }; <<
1988 <<
1989 qup_uart5_rts <<
1990 pins <<
1991 funct <<
1992 }; <<
1993 <<
1994 qup_uart5_tx: <<
1995 pins <<
1996 funct <<
1997 }; <<
1998 <<
1999 qup_uart5_rx: <<
2000 pins <<
2001 funct 1675 function = "qup05";
2002 }; 1676 };
2003 }; 1677 };
2004 1678
2005 qup_uart6_default: qu !! 1679 qup_uart6_default: qup-uart6-default {
2006 qup_uart6_cts !! 1680 pinmux {
2007 pins !! 1681 pins = "gpio59", "gpio60",
>> 1682 "gpio61", "gpio62";
2008 funct 1683 function = "qup10";
2009 }; 1684 };
>> 1685 };
2010 1686
2011 qup_uart6_rts !! 1687 qup_uart7_default: qup-uart7-default {
2012 pins !! 1688 pinmux {
2013 funct !! 1689 pins = "gpio6", "gpio7";
>> 1690 function = "qup11_uart";
2014 }; 1691 };
>> 1692 };
2015 1693
2016 qup_uart6_tx: !! 1694 qup_uart8_default: qup-uart8-default {
2017 pins !! 1695 pinmux {
2018 funct !! 1696 pins = "gpio44", "gpio45";
>> 1697 function = "qup12";
2019 }; 1698 };
>> 1699 };
2020 1700
2021 qup_uart6_rx: !! 1701 qup_uart9_default: qup-uart9-default {
2022 pins !! 1702 pinmux {
2023 funct !! 1703 pins = "gpio46", "gpio47";
>> 1704 function = "qup13_uart";
2024 }; 1705 };
2025 }; 1706 };
2026 1707
2027 qup_uart7_default: qu !! 1708 qup_uart10_default: qup-uart10-default {
2028 qup_uart7_tx: !! 1709 pinmux {
2029 pins !! 1710 pins = "gpio86", "gpio87",
2030 funct !! 1711 "gpio88", "gpio89";
>> 1712 function = "qup14";
2031 }; 1713 };
>> 1714 };
2032 1715
2033 qup_uart7_rx: !! 1716 qup_uart11_default: qup-uart11-default {
2034 pins !! 1717 pinmux {
2035 funct !! 1718 pins = "gpio53", "gpio54",
>> 1719 "gpio55", "gpio56";
>> 1720 function = "qup15";
2036 }; 1721 };
2037 }; 1722 };
2038 1723
2039 qup_uart8_default: qu !! 1724 sdc1_on: sdc1-on {
2040 qup_uart8_tx: !! 1725 pinconf-clk {
2041 pins !! 1726 pins = "sdc1_clk";
2042 funct !! 1727 bias-disable;
>> 1728 drive-strength = <16>;
2043 }; 1729 };
2044 1730
2045 qup_uart8_rx: !! 1731 pinconf-cmd {
2046 pins !! 1732 pins = "sdc1_cmd";
2047 funct !! 1733 bias-pull-up;
>> 1734 drive-strength = <10>;
2048 }; 1735 };
2049 }; <<
2050 1736
2051 qup_uart9_default: qu !! 1737 pinconf-data {
2052 qup_uart9_tx: !! 1738 pins = "sdc1_data";
2053 pins !! 1739 bias-pull-up;
2054 funct !! 1740 drive-strength = <10>;
2055 }; 1741 };
2056 1742
2057 qup_uart9_rx: !! 1743 pinconf-rclk {
2058 pins !! 1744 pins = "sdc1_rclk";
2059 funct !! 1745 bias-pull-down;
2060 }; 1746 };
2061 }; 1747 };
2062 1748
2063 qup_uart10_default: q !! 1749 sdc1_off: sdc1-off {
2064 qup_uart10_ct !! 1750 pinconf-clk {
2065 pins !! 1751 pins = "sdc1_clk";
2066 funct !! 1752 bias-disable;
>> 1753 drive-strength = <2>;
2067 }; 1754 };
2068 1755
2069 qup_uart10_rt !! 1756 pinconf-cmd {
2070 pins !! 1757 pins = "sdc1_cmd";
2071 funct !! 1758 bias-pull-up;
>> 1759 drive-strength = <2>;
2072 }; 1760 };
2073 1761
2074 qup_uart10_tx !! 1762 pinconf-data {
2075 pins !! 1763 pins = "sdc1_data";
2076 funct !! 1764 bias-pull-up;
>> 1765 drive-strength = <2>;
2077 }; 1766 };
2078 1767
2079 qup_uart10_rx !! 1768 pinconf-rclk {
2080 pins !! 1769 pins = "sdc1_rclk";
2081 funct !! 1770 bias-pull-down;
2082 }; 1771 };
2083 }; 1772 };
2084 1773
2085 qup_uart11_default: q !! 1774 sdc2_on: sdc2-on {
2086 qup_uart11_ct !! 1775 pinconf-clk {
2087 pins !! 1776 pins = "sdc2_clk";
2088 funct !! 1777 bias-disable;
>> 1778 drive-strength = <16>;
2089 }; 1779 };
2090 1780
2091 qup_uart11_rt !! 1781 pinconf-cmd {
2092 pins !! 1782 pins = "sdc2_cmd";
2093 funct !! 1783 bias-pull-up;
>> 1784 drive-strength = <10>;
2094 }; 1785 };
2095 1786
2096 qup_uart11_tx !! 1787 pinconf-data {
2097 pins !! 1788 pins = "sdc2_data";
2098 funct !! 1789 bias-pull-up;
>> 1790 drive-strength = <10>;
2099 }; 1791 };
2100 1792
2101 qup_uart11_rx !! 1793 pinconf-sd-cd {
2102 pins !! 1794 pins = "gpio69";
2103 funct !! 1795 bias-pull-up;
>> 1796 drive-strength = <2>;
2104 }; 1797 };
2105 }; 1798 };
2106 1799
2107 sec_mi2s_active: sec- !! 1800 sdc2_off: sdc2-off {
2108 pins = "gpio4 !! 1801 pinconf-clk {
2109 function = "m !! 1802 pins = "sdc2_clk";
2110 }; !! 1803 bias-disable;
>> 1804 drive-strength = <2>;
>> 1805 };
2111 1806
2112 pri_mi2s_active: pri- !! 1807 pinconf-cmd {
2113 pins = "gpio5 !! 1808 pins = "sdc2_cmd";
2114 function = "m !! 1809 bias-pull-up;
2115 }; !! 1810 drive-strength = <2>;
>> 1811 };
2116 1812
2117 pri_mi2s_mclk_active: !! 1813 pinconf-data {
2118 pins = "gpio5 !! 1814 pins = "sdc2_data";
2119 function = "l !! 1815 bias-pull-up;
2120 }; !! 1816 drive-strength = <2>;
>> 1817 };
2121 1818
2122 ter_mi2s_active: ter- !! 1819 pinconf-sd-cd {
2123 pins = "gpio6 !! 1820 pins = "gpio69";
2124 function = "m !! 1821 bias-disable;
>> 1822 drive-strength = <2>;
>> 1823 };
2125 }; 1824 };
2126 }; 1825 };
2127 1826
2128 remoteproc_mpss: remoteproc@4 1827 remoteproc_mpss: remoteproc@4080000 {
2129 compatible = "qcom,sc 1828 compatible = "qcom,sc7180-mpss-pas";
2130 reg = <0 0x04080000 0 !! 1829 reg = <0 0x04080000 0 0x4040>, <0 0x04180000 0 0x48>;
>> 1830 reg-names = "qdsp6", "rmb";
2131 1831
2132 interrupts-extended = 1832 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
2133 1833 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2134 1834 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2135 1835 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2136 1836 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
2137 1837 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
2138 interrupt-names = "wd 1838 interrupt-names = "wdog", "fatal", "ready", "handover",
2139 "st 1839 "stop-ack", "shutdown-ack";
2140 1840
2141 clocks = <&rpmhcc RPM !! 1841 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
2142 clock-names = "xo"; !! 1842 <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>,
>> 1843 <&gcc GCC_MSS_NAV_AXI_CLK>,
>> 1844 <&gcc GCC_MSS_SNOC_AXI_CLK>,
>> 1845 <&gcc GCC_MSS_MFAB_AXIS_CLK>,
>> 1846 <&rpmhcc RPMH_CXO_CLK>;
>> 1847 clock-names = "iface", "bus", "nav", "snoc_axi",
>> 1848 "mnoc_axi", "xo";
2143 1849
2144 power-domains = <&rpm !! 1850 power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>,
>> 1851 <&rpmhpd SC7180_CX>,
2145 <&rpm 1852 <&rpmhpd SC7180_MX>,
2146 <&rpm 1853 <&rpmhpd SC7180_MSS>;
2147 power-domain-names = !! 1854 power-domain-names = "load_state", "cx", "mx", "mss";
2148 1855
2149 memory-region = <&mps 1856 memory-region = <&mpss_mem>;
2150 1857
2151 qcom,qmp = <&aoss_qmp <<
2152 <<
2153 qcom,smem-states = <& 1858 qcom,smem-states = <&modem_smp2p_out 0>;
2154 qcom,smem-state-names 1859 qcom,smem-state-names = "stop";
2155 1860
>> 1861 resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
>> 1862 <&pdc_reset PDC_MODEM_SYNC_RESET>;
>> 1863 reset-names = "mss_restart", "pdc_reset";
>> 1864
>> 1865 qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
>> 1866 qcom,spare-regs = <&tcsr_regs 0xb3e4>;
>> 1867
2156 status = "disabled"; 1868 status = "disabled";
2157 1869
2158 glink-edge { 1870 glink-edge {
2159 interrupts = 1871 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
2160 label = "mode 1872 label = "modem";
2161 qcom,remote-p 1873 qcom,remote-pid = <1>;
2162 mboxes = <&ap 1874 mboxes = <&apss_shared 12>;
2163 }; 1875 };
2164 }; 1876 };
2165 1877
2166 gpu: gpu@5000000 { 1878 gpu: gpu@5000000 {
2167 compatible = "qcom,ad 1879 compatible = "qcom,adreno-618.0", "qcom,adreno";
>> 1880 #stream-id-cells = <16>;
2168 reg = <0 0x05000000 0 1881 reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x1000>,
2169 <0 0x05061000 1882 <0 0x05061000 0 0x800>;
2170 reg-names = "kgsl_3d0 1883 reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc";
2171 interrupts = <GIC_SPI 1884 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2172 iommus = <&adreno_smm 1885 iommus = <&adreno_smmu 0>;
2173 operating-points-v2 = 1886 operating-points-v2 = <&gpu_opp_table>;
2174 qcom,gmu = <&gmu>; 1887 qcom,gmu = <&gmu>;
2175 1888
2176 #cooling-cells = <2>; !! 1889 interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>;
2177 <<
2178 nvmem-cells = <&gpu_s <<
2179 nvmem-cell-names = "s <<
2180 <<
2181 interconnects = <&gem <<
2182 interconnect-names = 1890 interconnect-names = "gfx-mem";
2183 1891
2184 gpu_opp_table: opp-ta 1892 gpu_opp_table: opp-table {
2185 compatible = 1893 compatible = "operating-points-v2";
2186 1894
2187 opp-825000000 <<
2188 opp-h <<
2189 opp-l <<
2190 opp-p <<
2191 opp-s <<
2192 }; <<
2193 <<
2194 opp-800000000 1895 opp-800000000 {
2195 opp-h 1896 opp-hz = /bits/ 64 <800000000>;
2196 opp-l 1897 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2197 opp-p 1898 opp-peak-kBps = <8532000>;
2198 opp-s <<
2199 }; 1899 };
2200 1900
2201 opp-650000000 1901 opp-650000000 {
2202 opp-h 1902 opp-hz = /bits/ 64 <650000000>;
2203 opp-l 1903 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2204 opp-p 1904 opp-peak-kBps = <7216000>;
2205 opp-s <<
2206 }; 1905 };
2207 1906
2208 opp-565000000 1907 opp-565000000 {
2209 opp-h 1908 opp-hz = /bits/ 64 <565000000>;
2210 opp-l 1909 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2211 opp-p 1910 opp-peak-kBps = <5412000>;
2212 opp-s <<
2213 }; 1911 };
2214 1912
2215 opp-430000000 1913 opp-430000000 {
2216 opp-h 1914 opp-hz = /bits/ 64 <430000000>;
2217 opp-l 1915 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2218 opp-p 1916 opp-peak-kBps = <5412000>;
2219 opp-s <<
2220 }; 1917 };
2221 1918
2222 opp-355000000 1919 opp-355000000 {
2223 opp-h 1920 opp-hz = /bits/ 64 <355000000>;
2224 opp-l 1921 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2225 opp-p 1922 opp-peak-kBps = <3072000>;
2226 opp-s <<
2227 }; 1923 };
2228 1924
2229 opp-267000000 1925 opp-267000000 {
2230 opp-h 1926 opp-hz = /bits/ 64 <267000000>;
2231 opp-l 1927 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2232 opp-p 1928 opp-peak-kBps = <3072000>;
2233 opp-s <<
2234 }; 1929 };
2235 1930
2236 opp-180000000 1931 opp-180000000 {
2237 opp-h 1932 opp-hz = /bits/ 64 <180000000>;
2238 opp-l 1933 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2239 opp-p 1934 opp-peak-kBps = <1804000>;
2240 opp-s <<
2241 }; 1935 };
2242 }; 1936 };
2243 }; 1937 };
2244 1938
2245 adreno_smmu: iommu@5040000 { 1939 adreno_smmu: iommu@5040000 {
2246 compatible = "qcom,sc !! 1940 compatible = "qcom,sc7180-smmu-v2", "qcom,smmu-v2";
2247 reg = <0 0x05040000 0 1941 reg = <0 0x05040000 0 0x10000>;
2248 #iommu-cells = <1>; 1942 #iommu-cells = <1>;
2249 #global-interrupts = 1943 #global-interrupts = <2>;
2250 interrupts = <GIC_SPI 1944 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
2251 <GIC_ 1945 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
2252 <GIC_ 1946 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
2253 <GIC_ 1947 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
2254 <GIC_ 1948 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
2255 <GIC_ 1949 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
2256 <GIC_ 1950 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
2257 <GIC_ 1951 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
2258 <GIC_ 1952 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
2259 <GIC_ 1953 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
2260 1954
2261 clocks = <&gcc GCC_GP 1955 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2262 <&gcc GCC_GPU 1956 <&gcc GCC_GPU_CFG_AHB_CLK>;
2263 clock-names = "bus", 1957 clock-names = "bus", "iface";
2264 1958
2265 power-domains = <&gpu 1959 power-domains = <&gpucc CX_GDSC>;
2266 }; 1960 };
2267 1961
2268 gmu: gmu@506a000 { 1962 gmu: gmu@506a000 {
2269 compatible = "qcom,ad !! 1963 compatible="qcom,adreno-gmu-618.0", "qcom,adreno-gmu";
2270 reg = <0 0x0506a000 0 1964 reg = <0 0x0506a000 0 0x31000>, <0 0x0b290000 0 0x10000>,
2271 <0 0x0b490000 1965 <0 0x0b490000 0 0x10000>;
2272 reg-names = "gmu", "g 1966 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
2273 interrupts = <GIC_SPI 1967 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2274 <GIC_SPI 3 1968 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2275 interrupt-names = "hf 1969 interrupt-names = "hfi", "gmu";
2276 clocks = <&gpucc GPU_ 1970 clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
2277 <&gpucc GPU_CC 1971 <&gpucc GPU_CC_CXO_CLK>,
2278 <&gcc GCC_DDRS 1972 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2279 <&gcc GCC_GPU_ 1973 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
2280 clock-names = "gmu", 1974 clock-names = "gmu", "cxo", "axi", "memnoc";
2281 power-domains = <&gpu 1975 power-domains = <&gpucc CX_GDSC>, <&gpucc GX_GDSC>;
2282 power-domain-names = 1976 power-domain-names = "cx", "gx";
2283 iommus = <&adreno_smm 1977 iommus = <&adreno_smmu 5>;
2284 operating-points-v2 = 1978 operating-points-v2 = <&gmu_opp_table>;
2285 1979
2286 gmu_opp_table: opp-ta 1980 gmu_opp_table: opp-table {
2287 compatible = 1981 compatible = "operating-points-v2";
2288 1982
2289 opp-200000000 1983 opp-200000000 {
2290 opp-h 1984 opp-hz = /bits/ 64 <200000000>;
2291 opp-l 1985 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2292 }; 1986 };
2293 }; 1987 };
2294 }; 1988 };
2295 1989
2296 gpucc: clock-controller@50900 1990 gpucc: clock-controller@5090000 {
2297 compatible = "qcom,sc 1991 compatible = "qcom,sc7180-gpucc";
2298 reg = <0 0x05090000 0 1992 reg = <0 0x05090000 0 0x9000>;
2299 clocks = <&rpmhcc RPM 1993 clocks = <&rpmhcc RPMH_CXO_CLK>,
2300 <&gcc GCC_GP 1994 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2301 <&gcc GCC_GP 1995 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2302 clock-names = "bi_tcx 1996 clock-names = "bi_tcxo",
2303 "gcc_gp 1997 "gcc_gpu_gpll0_clk_src",
2304 "gcc_gp 1998 "gcc_gpu_gpll0_div_clk_src";
2305 #clock-cells = <1>; 1999 #clock-cells = <1>;
2306 #reset-cells = <1>; 2000 #reset-cells = <1>;
2307 #power-domain-cells = 2001 #power-domain-cells = <1>;
2308 }; 2002 };
2309 2003
2310 dma@10a2000 { <<
2311 compatible = "qcom,sc <<
2312 reg = <0x0 0x010a2000 <<
2313 <0x0 0x010ae000 <<
2314 status = "disabled"; <<
2315 }; <<
2316 <<
2317 stm@6002000 { 2004 stm@6002000 {
2318 compatible = "arm,cor 2005 compatible = "arm,coresight-stm", "arm,primecell";
2319 reg = <0 0x06002000 0 2006 reg = <0 0x06002000 0 0x1000>,
2320 <0 0x16280000 0 2007 <0 0x16280000 0 0x180000>;
2321 reg-names = "stm-base 2008 reg-names = "stm-base", "stm-stimulus-base";
2322 2009
2323 clocks = <&aoss_qmp>; 2010 clocks = <&aoss_qmp>;
2324 clock-names = "apb_pc 2011 clock-names = "apb_pclk";
2325 2012
2326 out-ports { 2013 out-ports {
2327 port { 2014 port {
2328 stm_o 2015 stm_out: endpoint {
2329 2016 remote-endpoint = <&funnel0_in7>;
2330 }; 2017 };
2331 }; 2018 };
2332 }; 2019 };
2333 }; 2020 };
2334 2021
2335 funnel@6041000 { 2022 funnel@6041000 {
2336 compatible = "arm,cor 2023 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2337 reg = <0 0x06041000 0 2024 reg = <0 0x06041000 0 0x1000>;
2338 2025
2339 clocks = <&aoss_qmp>; 2026 clocks = <&aoss_qmp>;
2340 clock-names = "apb_pc 2027 clock-names = "apb_pclk";
2341 2028
2342 out-ports { 2029 out-ports {
2343 port { 2030 port {
2344 funne 2031 funnel0_out: endpoint {
2345 2032 remote-endpoint = <&merge_funnel_in0>;
2346 }; 2033 };
2347 }; 2034 };
2348 }; 2035 };
2349 2036
2350 in-ports { 2037 in-ports {
2351 #address-cell 2038 #address-cells = <1>;
2352 #size-cells = 2039 #size-cells = <0>;
2353 2040
2354 port@7 { 2041 port@7 {
2355 reg = 2042 reg = <7>;
2356 funne 2043 funnel0_in7: endpoint {
2357 2044 remote-endpoint = <&stm_out>;
2358 }; 2045 };
2359 }; 2046 };
2360 }; 2047 };
2361 }; 2048 };
2362 2049
2363 funnel@6042000 { 2050 funnel@6042000 {
2364 compatible = "arm,cor 2051 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2365 reg = <0 0x06042000 0 2052 reg = <0 0x06042000 0 0x1000>;
2366 2053
2367 clocks = <&aoss_qmp>; 2054 clocks = <&aoss_qmp>;
2368 clock-names = "apb_pc 2055 clock-names = "apb_pclk";
2369 2056
2370 out-ports { 2057 out-ports {
2371 port { 2058 port {
2372 funne 2059 funnel1_out: endpoint {
2373 2060 remote-endpoint = <&merge_funnel_in1>;
2374 }; 2061 };
2375 }; 2062 };
2376 }; 2063 };
2377 2064
2378 in-ports { 2065 in-ports {
2379 #address-cell 2066 #address-cells = <1>;
2380 #size-cells = 2067 #size-cells = <0>;
2381 2068
2382 port@4 { 2069 port@4 {
2383 reg = 2070 reg = <4>;
2384 funne 2071 funnel1_in4: endpoint {
2385 2072 remote-endpoint = <&apss_merge_funnel_out>;
2386 }; 2073 };
2387 }; 2074 };
2388 }; 2075 };
2389 }; 2076 };
2390 2077
2391 funnel@6045000 { 2078 funnel@6045000 {
2392 compatible = "arm,cor 2079 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2393 reg = <0 0x06045000 0 2080 reg = <0 0x06045000 0 0x1000>;
2394 2081
2395 clocks = <&aoss_qmp>; 2082 clocks = <&aoss_qmp>;
2396 clock-names = "apb_pc 2083 clock-names = "apb_pclk";
2397 2084
2398 out-ports { 2085 out-ports {
2399 port { 2086 port {
2400 merge 2087 merge_funnel_out: endpoint {
2401 2088 remote-endpoint = <&swao_funnel_in>;
2402 }; 2089 };
2403 }; 2090 };
2404 }; 2091 };
2405 2092
2406 in-ports { 2093 in-ports {
2407 #address-cell 2094 #address-cells = <1>;
2408 #size-cells = 2095 #size-cells = <0>;
2409 2096
2410 port@0 { 2097 port@0 {
2411 reg = 2098 reg = <0>;
2412 merge 2099 merge_funnel_in0: endpoint {
2413 2100 remote-endpoint = <&funnel0_out>;
2414 }; 2101 };
2415 }; 2102 };
2416 2103
2417 port@1 { 2104 port@1 {
2418 reg = 2105 reg = <1>;
2419 merge 2106 merge_funnel_in1: endpoint {
2420 2107 remote-endpoint = <&funnel1_out>;
2421 }; 2108 };
2422 }; 2109 };
2423 }; 2110 };
2424 }; 2111 };
2425 2112
2426 replicator@6046000 { 2113 replicator@6046000 {
2427 compatible = "arm,cor 2114 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2428 reg = <0 0x06046000 0 2115 reg = <0 0x06046000 0 0x1000>;
2429 2116
2430 clocks = <&aoss_qmp>; 2117 clocks = <&aoss_qmp>;
2431 clock-names = "apb_pc 2118 clock-names = "apb_pclk";
2432 2119
2433 out-ports { 2120 out-ports {
2434 port { 2121 port {
2435 repli 2122 replicator_out: endpoint {
2436 2123 remote-endpoint = <&etr_in>;
2437 }; 2124 };
2438 }; 2125 };
2439 }; 2126 };
2440 2127
2441 in-ports { 2128 in-ports {
2442 port { 2129 port {
2443 repli 2130 replicator_in: endpoint {
2444 2131 remote-endpoint = <&swao_replicator_out>;
2445 }; 2132 };
2446 }; 2133 };
2447 }; 2134 };
2448 }; 2135 };
2449 2136
2450 etr@6048000 { 2137 etr@6048000 {
2451 compatible = "arm,cor 2138 compatible = "arm,coresight-tmc", "arm,primecell";
2452 reg = <0 0x06048000 0 2139 reg = <0 0x06048000 0 0x1000>;
2453 iommus = <&apps_smmu 2140 iommus = <&apps_smmu 0x04a0 0x20>;
2454 2141
2455 clocks = <&aoss_qmp>; 2142 clocks = <&aoss_qmp>;
2456 clock-names = "apb_pc 2143 clock-names = "apb_pclk";
2457 arm,scatter-gather; 2144 arm,scatter-gather;
2458 2145
2459 in-ports { 2146 in-ports {
2460 port { 2147 port {
2461 etr_i 2148 etr_in: endpoint {
2462 2149 remote-endpoint = <&replicator_out>;
2463 }; 2150 };
2464 }; 2151 };
2465 }; 2152 };
2466 }; 2153 };
2467 2154
2468 funnel@6b04000 { 2155 funnel@6b04000 {
2469 compatible = "arm,cor 2156 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2470 reg = <0 0x06b04000 0 2157 reg = <0 0x06b04000 0 0x1000>;
2471 2158
2472 clocks = <&aoss_qmp>; 2159 clocks = <&aoss_qmp>;
2473 clock-names = "apb_pc 2160 clock-names = "apb_pclk";
2474 2161
2475 out-ports { 2162 out-ports {
2476 port { 2163 port {
2477 swao_ 2164 swao_funnel_out: endpoint {
2478 2165 remote-endpoint = <&etf_in>;
2479 }; 2166 };
2480 }; 2167 };
2481 }; 2168 };
2482 2169
2483 in-ports { 2170 in-ports {
2484 #address-cell 2171 #address-cells = <1>;
2485 #size-cells = 2172 #size-cells = <0>;
2486 2173
2487 port@7 { 2174 port@7 {
2488 reg = 2175 reg = <7>;
2489 swao_ 2176 swao_funnel_in: endpoint {
2490 2177 remote-endpoint = <&merge_funnel_out>;
2491 }; 2178 };
2492 }; 2179 };
2493 }; 2180 };
2494 }; 2181 };
2495 2182
2496 etf@6b05000 { 2183 etf@6b05000 {
2497 compatible = "arm,cor 2184 compatible = "arm,coresight-tmc", "arm,primecell";
2498 reg = <0 0x06b05000 0 2185 reg = <0 0x06b05000 0 0x1000>;
2499 2186
2500 clocks = <&aoss_qmp>; 2187 clocks = <&aoss_qmp>;
2501 clock-names = "apb_pc 2188 clock-names = "apb_pclk";
2502 2189
2503 out-ports { 2190 out-ports {
2504 port { 2191 port {
2505 etf_o 2192 etf_out: endpoint {
2506 2193 remote-endpoint = <&swao_replicator_in>;
2507 }; 2194 };
2508 }; 2195 };
2509 }; 2196 };
2510 2197
2511 in-ports { 2198 in-ports {
2512 port { 2199 port {
2513 etf_i 2200 etf_in: endpoint {
2514 2201 remote-endpoint = <&swao_funnel_out>;
2515 }; 2202 };
2516 }; 2203 };
2517 }; 2204 };
2518 }; 2205 };
2519 2206
2520 replicator@6b06000 { 2207 replicator@6b06000 {
2521 compatible = "arm,cor 2208 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2522 reg = <0 0x06b06000 0 2209 reg = <0 0x06b06000 0 0x1000>;
2523 2210
2524 clocks = <&aoss_qmp>; 2211 clocks = <&aoss_qmp>;
2525 clock-names = "apb_pc 2212 clock-names = "apb_pclk";
2526 qcom,replicator-loses 2213 qcom,replicator-loses-context;
2527 2214
2528 out-ports { 2215 out-ports {
2529 port { 2216 port {
2530 swao_ 2217 swao_replicator_out: endpoint {
2531 2218 remote-endpoint = <&replicator_in>;
2532 }; 2219 };
2533 }; 2220 };
2534 }; 2221 };
2535 2222
2536 in-ports { 2223 in-ports {
2537 port { 2224 port {
2538 swao_ 2225 swao_replicator_in: endpoint {
2539 2226 remote-endpoint = <&etf_out>;
2540 }; 2227 };
2541 }; 2228 };
2542 }; 2229 };
2543 }; 2230 };
2544 2231
2545 etm@7040000 { 2232 etm@7040000 {
2546 compatible = "arm,cor 2233 compatible = "arm,coresight-etm4x", "arm,primecell";
2547 reg = <0 0x07040000 0 2234 reg = <0 0x07040000 0 0x1000>;
2548 2235
2549 cpu = <&CPU0>; 2236 cpu = <&CPU0>;
2550 2237
2551 clocks = <&aoss_qmp>; 2238 clocks = <&aoss_qmp>;
2552 clock-names = "apb_pc 2239 clock-names = "apb_pclk";
2553 arm,coresight-loses-c 2240 arm,coresight-loses-context-with-cpu;
2554 qcom,skip-power-up; 2241 qcom,skip-power-up;
2555 2242
2556 out-ports { 2243 out-ports {
2557 port { 2244 port {
2558 etm0_ 2245 etm0_out: endpoint {
2559 2246 remote-endpoint = <&apss_funnel_in0>;
2560 }; 2247 };
2561 }; 2248 };
2562 }; 2249 };
2563 }; 2250 };
2564 2251
2565 etm@7140000 { 2252 etm@7140000 {
2566 compatible = "arm,cor 2253 compatible = "arm,coresight-etm4x", "arm,primecell";
2567 reg = <0 0x07140000 0 2254 reg = <0 0x07140000 0 0x1000>;
2568 2255
2569 cpu = <&CPU1>; 2256 cpu = <&CPU1>;
2570 2257
2571 clocks = <&aoss_qmp>; 2258 clocks = <&aoss_qmp>;
2572 clock-names = "apb_pc 2259 clock-names = "apb_pclk";
2573 arm,coresight-loses-c 2260 arm,coresight-loses-context-with-cpu;
2574 qcom,skip-power-up; 2261 qcom,skip-power-up;
2575 2262
2576 out-ports { 2263 out-ports {
2577 port { 2264 port {
2578 etm1_ 2265 etm1_out: endpoint {
2579 2266 remote-endpoint = <&apss_funnel_in1>;
2580 }; 2267 };
2581 }; 2268 };
2582 }; 2269 };
2583 }; 2270 };
2584 2271
2585 etm@7240000 { 2272 etm@7240000 {
2586 compatible = "arm,cor 2273 compatible = "arm,coresight-etm4x", "arm,primecell";
2587 reg = <0 0x07240000 0 2274 reg = <0 0x07240000 0 0x1000>;
2588 2275
2589 cpu = <&CPU2>; 2276 cpu = <&CPU2>;
2590 2277
2591 clocks = <&aoss_qmp>; 2278 clocks = <&aoss_qmp>;
2592 clock-names = "apb_pc 2279 clock-names = "apb_pclk";
2593 arm,coresight-loses-c 2280 arm,coresight-loses-context-with-cpu;
2594 qcom,skip-power-up; 2281 qcom,skip-power-up;
2595 2282
2596 out-ports { 2283 out-ports {
2597 port { 2284 port {
2598 etm2_ 2285 etm2_out: endpoint {
2599 2286 remote-endpoint = <&apss_funnel_in2>;
2600 }; 2287 };
2601 }; 2288 };
2602 }; 2289 };
2603 }; 2290 };
2604 2291
2605 etm@7340000 { 2292 etm@7340000 {
2606 compatible = "arm,cor 2293 compatible = "arm,coresight-etm4x", "arm,primecell";
2607 reg = <0 0x07340000 0 2294 reg = <0 0x07340000 0 0x1000>;
2608 2295
2609 cpu = <&CPU3>; 2296 cpu = <&CPU3>;
2610 2297
2611 clocks = <&aoss_qmp>; 2298 clocks = <&aoss_qmp>;
2612 clock-names = "apb_pc 2299 clock-names = "apb_pclk";
2613 arm,coresight-loses-c 2300 arm,coresight-loses-context-with-cpu;
2614 qcom,skip-power-up; 2301 qcom,skip-power-up;
2615 2302
2616 out-ports { 2303 out-ports {
2617 port { 2304 port {
2618 etm3_ 2305 etm3_out: endpoint {
2619 2306 remote-endpoint = <&apss_funnel_in3>;
2620 }; 2307 };
2621 }; 2308 };
2622 }; 2309 };
2623 }; 2310 };
2624 2311
2625 etm@7440000 { 2312 etm@7440000 {
2626 compatible = "arm,cor 2313 compatible = "arm,coresight-etm4x", "arm,primecell";
2627 reg = <0 0x07440000 0 2314 reg = <0 0x07440000 0 0x1000>;
2628 2315
2629 cpu = <&CPU4>; 2316 cpu = <&CPU4>;
2630 2317
2631 clocks = <&aoss_qmp>; 2318 clocks = <&aoss_qmp>;
2632 clock-names = "apb_pc 2319 clock-names = "apb_pclk";
2633 arm,coresight-loses-c 2320 arm,coresight-loses-context-with-cpu;
2634 qcom,skip-power-up; 2321 qcom,skip-power-up;
2635 2322
2636 out-ports { 2323 out-ports {
2637 port { 2324 port {
2638 etm4_ 2325 etm4_out: endpoint {
2639 2326 remote-endpoint = <&apss_funnel_in4>;
2640 }; 2327 };
2641 }; 2328 };
2642 }; 2329 };
2643 }; 2330 };
2644 2331
2645 etm@7540000 { 2332 etm@7540000 {
2646 compatible = "arm,cor 2333 compatible = "arm,coresight-etm4x", "arm,primecell";
2647 reg = <0 0x07540000 0 2334 reg = <0 0x07540000 0 0x1000>;
2648 2335
2649 cpu = <&CPU5>; 2336 cpu = <&CPU5>;
2650 2337
2651 clocks = <&aoss_qmp>; 2338 clocks = <&aoss_qmp>;
2652 clock-names = "apb_pc 2339 clock-names = "apb_pclk";
2653 arm,coresight-loses-c 2340 arm,coresight-loses-context-with-cpu;
2654 qcom,skip-power-up; 2341 qcom,skip-power-up;
2655 2342
2656 out-ports { 2343 out-ports {
2657 port { 2344 port {
2658 etm5_ 2345 etm5_out: endpoint {
2659 2346 remote-endpoint = <&apss_funnel_in5>;
2660 }; 2347 };
2661 }; 2348 };
2662 }; 2349 };
2663 }; 2350 };
2664 2351
2665 etm@7640000 { 2352 etm@7640000 {
2666 compatible = "arm,cor 2353 compatible = "arm,coresight-etm4x", "arm,primecell";
2667 reg = <0 0x07640000 0 2354 reg = <0 0x07640000 0 0x1000>;
2668 2355
2669 cpu = <&CPU6>; 2356 cpu = <&CPU6>;
2670 2357
2671 clocks = <&aoss_qmp>; 2358 clocks = <&aoss_qmp>;
2672 clock-names = "apb_pc 2359 clock-names = "apb_pclk";
2673 arm,coresight-loses-c 2360 arm,coresight-loses-context-with-cpu;
2674 qcom,skip-power-up; 2361 qcom,skip-power-up;
2675 2362
2676 out-ports { 2363 out-ports {
2677 port { 2364 port {
2678 etm6_ 2365 etm6_out: endpoint {
2679 2366 remote-endpoint = <&apss_funnel_in6>;
2680 }; 2367 };
2681 }; 2368 };
2682 }; 2369 };
2683 }; 2370 };
2684 2371
2685 etm@7740000 { 2372 etm@7740000 {
2686 compatible = "arm,cor 2373 compatible = "arm,coresight-etm4x", "arm,primecell";
2687 reg = <0 0x07740000 0 2374 reg = <0 0x07740000 0 0x1000>;
2688 2375
2689 cpu = <&CPU7>; 2376 cpu = <&CPU7>;
2690 2377
2691 clocks = <&aoss_qmp>; 2378 clocks = <&aoss_qmp>;
2692 clock-names = "apb_pc 2379 clock-names = "apb_pclk";
2693 arm,coresight-loses-c 2380 arm,coresight-loses-context-with-cpu;
2694 qcom,skip-power-up; 2381 qcom,skip-power-up;
2695 2382
2696 out-ports { 2383 out-ports {
2697 port { 2384 port {
2698 etm7_ 2385 etm7_out: endpoint {
2699 2386 remote-endpoint = <&apss_funnel_in7>;
2700 }; 2387 };
2701 }; 2388 };
2702 }; 2389 };
2703 }; 2390 };
2704 2391
2705 funnel@7800000 { /* APSS Funn 2392 funnel@7800000 { /* APSS Funnel */
2706 compatible = "arm,cor 2393 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2707 reg = <0 0x07800000 0 2394 reg = <0 0x07800000 0 0x1000>;
2708 2395
2709 clocks = <&aoss_qmp>; 2396 clocks = <&aoss_qmp>;
2710 clock-names = "apb_pc 2397 clock-names = "apb_pclk";
2711 2398
2712 out-ports { 2399 out-ports {
2713 port { 2400 port {
2714 apss_ 2401 apss_funnel_out: endpoint {
2715 2402 remote-endpoint = <&apss_merge_funnel_in>;
2716 }; 2403 };
2717 }; 2404 };
2718 }; 2405 };
2719 2406
2720 in-ports { 2407 in-ports {
2721 #address-cell 2408 #address-cells = <1>;
2722 #size-cells = 2409 #size-cells = <0>;
2723 2410
2724 port@0 { 2411 port@0 {
2725 reg = 2412 reg = <0>;
2726 apss_ 2413 apss_funnel_in0: endpoint {
2727 2414 remote-endpoint = <&etm0_out>;
2728 }; 2415 };
2729 }; 2416 };
2730 2417
2731 port@1 { 2418 port@1 {
2732 reg = 2419 reg = <1>;
2733 apss_ 2420 apss_funnel_in1: endpoint {
2734 2421 remote-endpoint = <&etm1_out>;
2735 }; 2422 };
2736 }; 2423 };
2737 2424
2738 port@2 { 2425 port@2 {
2739 reg = 2426 reg = <2>;
2740 apss_ 2427 apss_funnel_in2: endpoint {
2741 2428 remote-endpoint = <&etm2_out>;
2742 }; 2429 };
2743 }; 2430 };
2744 2431
2745 port@3 { 2432 port@3 {
2746 reg = 2433 reg = <3>;
2747 apss_ 2434 apss_funnel_in3: endpoint {
2748 2435 remote-endpoint = <&etm3_out>;
2749 }; 2436 };
2750 }; 2437 };
2751 2438
2752 port@4 { 2439 port@4 {
2753 reg = 2440 reg = <4>;
2754 apss_ 2441 apss_funnel_in4: endpoint {
2755 2442 remote-endpoint = <&etm4_out>;
2756 }; 2443 };
2757 }; 2444 };
2758 2445
2759 port@5 { 2446 port@5 {
2760 reg = 2447 reg = <5>;
2761 apss_ 2448 apss_funnel_in5: endpoint {
2762 2449 remote-endpoint = <&etm5_out>;
2763 }; 2450 };
2764 }; 2451 };
2765 2452
2766 port@6 { 2453 port@6 {
2767 reg = 2454 reg = <6>;
2768 apss_ 2455 apss_funnel_in6: endpoint {
2769 2456 remote-endpoint = <&etm6_out>;
2770 }; 2457 };
2771 }; 2458 };
2772 2459
2773 port@7 { 2460 port@7 {
2774 reg = 2461 reg = <7>;
2775 apss_ 2462 apss_funnel_in7: endpoint {
2776 2463 remote-endpoint = <&etm7_out>;
2777 }; 2464 };
2778 }; 2465 };
2779 }; 2466 };
2780 }; 2467 };
2781 2468
2782 funnel@7810000 { 2469 funnel@7810000 {
2783 compatible = "arm,cor 2470 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2784 reg = <0 0x07810000 0 2471 reg = <0 0x07810000 0 0x1000>;
2785 2472
2786 clocks = <&aoss_qmp>; 2473 clocks = <&aoss_qmp>;
2787 clock-names = "apb_pc 2474 clock-names = "apb_pclk";
2788 2475
2789 out-ports { 2476 out-ports {
2790 port { 2477 port {
2791 apss_ 2478 apss_merge_funnel_out: endpoint {
2792 2479 remote-endpoint = <&funnel1_in4>;
2793 }; 2480 };
2794 }; 2481 };
2795 }; 2482 };
2796 2483
2797 in-ports { 2484 in-ports {
2798 port { 2485 port {
2799 apss_ 2486 apss_merge_funnel_in: endpoint {
2800 2487 remote-endpoint = <&apss_funnel_out>;
2801 }; 2488 };
2802 }; 2489 };
2803 }; 2490 };
2804 }; 2491 };
2805 2492
2806 sdhc_2: mmc@8804000 { !! 2493 sdhc_2: sdhci@8804000 {
2807 compatible = "qcom,sc 2494 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
2808 reg = <0 0x08804000 0 2495 reg = <0 0x08804000 0 0x1000>;
2809 2496
2810 iommus = <&apps_smmu 2497 iommus = <&apps_smmu 0x80 0>;
2811 interrupts = <GIC_SPI 2498 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
2812 <GIC_ 2499 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
2813 interrupt-names = "hc 2500 interrupt-names = "hc_irq", "pwr_irq";
2814 2501
2815 clocks = <&gcc GCC_SD !! 2502 clocks = <&gcc GCC_SDCC2_APPS_CLK>,
2816 <&gcc GCC_SD !! 2503 <&gcc GCC_SDCC2_AHB_CLK>;
2817 <&rpmhcc RPM !! 2504 clock-names = "core", "iface";
2818 clock-names = "iface" <<
2819 <<
2820 interconnects = <&agg <<
2821 <&gem <<
2822 interconnect-names = <<
2823 power-domains = <&rpm 2505 power-domains = <&rpmhpd SC7180_CX>;
2824 operating-points-v2 = 2506 operating-points-v2 = <&sdhc2_opp_table>;
2825 2507
2826 bus-width = <4>; 2508 bus-width = <4>;
2827 2509
2828 status = "disabled"; 2510 status = "disabled";
2829 2511
2830 sdhc2_opp_table: opp- !! 2512 sdhc2_opp_table: sdhc2-opp-table {
2831 compatible = 2513 compatible = "operating-points-v2";
2832 2514
2833 opp-100000000 2515 opp-100000000 {
2834 opp-h 2516 opp-hz = /bits/ 64 <100000000>;
2835 requi 2517 required-opps = <&rpmhpd_opp_low_svs>;
2836 opp-p <<
2837 opp-a <<
2838 }; 2518 };
2839 2519
2840 opp-202000000 2520 opp-202000000 {
2841 opp-h 2521 opp-hz = /bits/ 64 <202000000>;
2842 requi !! 2522 required-opps = <&rpmhpd_opp_svs_l1>;
2843 opp-p <<
2844 opp-a <<
2845 }; 2523 };
2846 }; 2524 };
2847 }; 2525 };
2848 2526
>> 2527 qspi_opp_table: qspi-opp-table {
>> 2528 compatible = "operating-points-v2";
>> 2529
>> 2530 opp-75000000 {
>> 2531 opp-hz = /bits/ 64 <75000000>;
>> 2532 required-opps = <&rpmhpd_opp_low_svs>;
>> 2533 };
>> 2534
>> 2535 opp-150000000 {
>> 2536 opp-hz = /bits/ 64 <150000000>;
>> 2537 required-opps = <&rpmhpd_opp_svs>;
>> 2538 };
>> 2539
>> 2540 opp-300000000 {
>> 2541 opp-hz = /bits/ 64 <300000000>;
>> 2542 required-opps = <&rpmhpd_opp_nom>;
>> 2543 };
>> 2544 };
>> 2545
2849 qspi: spi@88dc000 { 2546 qspi: spi@88dc000 {
2850 compatible = "qcom,sc !! 2547 compatible = "qcom,qspi-v1";
2851 reg = <0 0x088dc000 0 2548 reg = <0 0x088dc000 0 0x600>;
2852 iommus = <&apps_smmu <<
2853 #address-cells = <1>; 2549 #address-cells = <1>;
2854 #size-cells = <0>; 2550 #size-cells = <0>;
2855 interrupts = <GIC_SPI 2551 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
2856 clocks = <&gcc GCC_QS 2552 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
2857 <&gcc GCC_QS 2553 <&gcc GCC_QSPI_CORE_CLK>;
2858 clock-names = "iface" 2554 clock-names = "iface", "core";
2859 interconnects = <&gem !! 2555 interconnects = <&gem_noc MASTER_APPSS_PROC
2860 &conf !! 2556 &config_noc SLAVE_QSPI_0>;
2861 interconnect-names = 2557 interconnect-names = "qspi-config";
2862 power-domains = <&rpm 2558 power-domains = <&rpmhpd SC7180_CX>;
2863 operating-points-v2 = 2559 operating-points-v2 = <&qspi_opp_table>;
2864 status = "disabled"; 2560 status = "disabled";
2865 }; 2561 };
2866 2562
2867 usb_1_hsphy: phy@88e3000 { 2563 usb_1_hsphy: phy@88e3000 {
2868 compatible = "qcom,sc 2564 compatible = "qcom,sc7180-qusb2-phy", "qcom,qusb2-v2-phy";
2869 reg = <0 0x088e3000 0 2565 reg = <0 0x088e3000 0 0x400>;
2870 status = "disabled"; 2566 status = "disabled";
2871 #phy-cells = <0>; 2567 #phy-cells = <0>;
2872 clocks = <&gcc GCC_US 2568 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2873 <&rpmhcc RPM 2569 <&rpmhcc RPMH_CXO_CLK>;
2874 clock-names = "cfg_ah 2570 clock-names = "cfg_ahb", "ref";
2875 resets = <&gcc GCC_QU 2571 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2876 2572
2877 nvmem-cells = <&qusb2 2573 nvmem-cells = <&qusb2p_hstx_trim>;
2878 }; 2574 };
2879 2575
2880 usb_1_qmpphy: phy@88e8000 { !! 2576 usb_1_qmpphy: phy-wrapper@88e9000 {
2881 compatible = "qcom,sc !! 2577 compatible = "qcom,sc7180-qmp-usb3-phy";
2882 reg = <0 0x088e8000 0 !! 2578 reg = <0 0x088e9000 0 0x18c>,
>> 2579 <0 0x088e8000 0 0x38>;
>> 2580 reg-names = "reg-base", "dp_com";
2883 status = "disabled"; 2581 status = "disabled";
>> 2582 #clock-cells = <1>;
>> 2583 #address-cells = <2>;
>> 2584 #size-cells = <2>;
>> 2585 ranges;
2884 2586
2885 clocks = <&gcc GCC_US 2587 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
>> 2588 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2886 <&gcc GCC_US 2589 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
2887 <&gcc GCC_US !! 2590 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
2888 <&gcc GCC_US !! 2591 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
2889 <&gcc GCC_US <<
2890 clock-names = "aux", <<
2891 "ref", <<
2892 "com_au <<
2893 "usb3_p <<
2894 "cfg_ah <<
2895 2592
2896 resets = <&gcc GCC_US 2593 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
2897 <&gcc GCC_US 2594 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
2898 reset-names = "phy", 2595 reset-names = "phy", "common";
2899 2596
2900 #clock-cells = <1>; !! 2597 usb_1_ssphy: phy@88e9200 {
2901 #phy-cells = <1>; !! 2598 reg = <0 0x088e9200 0 0x128>,
2902 }; !! 2599 <0 0x088e9400 0 0x200>,
2903 !! 2600 <0 0x088e9c00 0 0x218>,
2904 pmu@90b6300 { !! 2601 <0 0x088e9600 0 0x128>,
2905 compatible = "qcom,sc !! 2602 <0 0x088e9800 0 0x200>,
2906 reg = <0 0x090b6300 0 !! 2603 <0 0x088e9a00 0 0x18>;
2907 interrupts = <GIC_SPI !! 2604 #clock-cells = <0>;
2908 !! 2605 #phy-cells = <0>;
2909 interconnects = <&gem !! 2606 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2910 &gem !! 2607 clock-names = "pipe0";
2911 operating-points-v2 = !! 2608 clock-output-names = "usb3_phy_pipe_clk_src";
2912 <<
2913 cpu_bwmon_opp_table: <<
2914 compatible = <<
2915 <<
2916 opp-0 { <<
2917 opp-p <<
2918 }; <<
2919 <<
2920 opp-1 { <<
2921 opp-p <<
2922 }; <<
2923 <<
2924 opp-2 { <<
2925 opp-p <<
2926 }; <<
2927 <<
2928 opp-3 { <<
2929 opp-p <<
2930 }; <<
2931 <<
2932 opp-4 { <<
2933 opp-p <<
2934 }; <<
2935 <<
2936 opp-5 { <<
2937 opp-p <<
2938 }; <<
2939 }; <<
2940 }; <<
2941 <<
2942 pmu@90cd000 { <<
2943 compatible = "qcom,sc <<
2944 reg = <0 0x090cd000 0 <<
2945 interrupts = <GIC_SPI <<
2946 <<
2947 interconnects = <&mc_ <<
2948 &mc_ <<
2949 operating-points-v2 = <<
2950 <<
2951 llcc_bwmon_opp_table: <<
2952 compatible = <<
2953 <<
2954 opp-0 { <<
2955 opp-p <<
2956 }; <<
2957 <<
2958 opp-1 { <<
2959 opp-p <<
2960 }; <<
2961 <<
2962 opp-2 { <<
2963 opp-p <<
2964 }; <<
2965 <<
2966 opp-3 { <<
2967 opp-p <<
2968 }; <<
2969 <<
2970 opp-4 { <<
2971 opp-p <<
2972 }; <<
2973 <<
2974 opp-5 { <<
2975 opp-p <<
2976 }; <<
2977 <<
2978 opp-6 { <<
2979 opp-p <<
2980 }; <<
2981 <<
2982 opp-7 { <<
2983 opp-p <<
2984 }; <<
2985 }; 2609 };
2986 }; 2610 };
2987 2611
2988 dc_noc: interconnect@9160000 2612 dc_noc: interconnect@9160000 {
2989 compatible = "qcom,sc 2613 compatible = "qcom,sc7180-dc-noc";
2990 reg = <0 0x09160000 0 2614 reg = <0 0x09160000 0 0x03200>;
2991 #interconnect-cells = !! 2615 #interconnect-cells = <1>;
2992 qcom,bcm-voters = <&a 2616 qcom,bcm-voters = <&apps_bcm_voter>;
2993 }; 2617 };
2994 2618
2995 system-cache-controller@92000 2619 system-cache-controller@9200000 {
2996 compatible = "qcom,sc 2620 compatible = "qcom,sc7180-llcc";
2997 reg = <0 0x09200000 0 2621 reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>;
2998 reg-names = "llcc0_ba !! 2622 reg-names = "llcc_base", "llcc_broadcast_base";
2999 interrupts = <GIC_SPI 2623 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
3000 }; 2624 };
3001 2625
3002 gem_noc: interconnect@9680000 2626 gem_noc: interconnect@9680000 {
3003 compatible = "qcom,sc 2627 compatible = "qcom,sc7180-gem-noc";
3004 reg = <0 0x09680000 0 2628 reg = <0 0x09680000 0 0x3e200>;
3005 #interconnect-cells = !! 2629 #interconnect-cells = <1>;
3006 qcom,bcm-voters = <&a 2630 qcom,bcm-voters = <&apps_bcm_voter>;
3007 }; 2631 };
3008 2632
3009 npu_noc: interconnect@9990000 2633 npu_noc: interconnect@9990000 {
3010 compatible = "qcom,sc 2634 compatible = "qcom,sc7180-npu-noc";
3011 reg = <0 0x09990000 0 2635 reg = <0 0x09990000 0 0x1600>;
3012 #interconnect-cells = !! 2636 #interconnect-cells = <1>;
3013 qcom,bcm-voters = <&a 2637 qcom,bcm-voters = <&apps_bcm_voter>;
3014 }; 2638 };
3015 2639
3016 usb_1: usb@a6f8800 { 2640 usb_1: usb@a6f8800 {
3017 compatible = "qcom,sc 2641 compatible = "qcom,sc7180-dwc3", "qcom,dwc3";
3018 reg = <0 0x0a6f8800 0 2642 reg = <0 0x0a6f8800 0 0x400>;
3019 status = "disabled"; 2643 status = "disabled";
3020 #address-cells = <2>; 2644 #address-cells = <2>;
3021 #size-cells = <2>; 2645 #size-cells = <2>;
3022 ranges; 2646 ranges;
3023 dma-ranges; 2647 dma-ranges;
3024 2648
3025 clocks = <&gcc GCC_CF 2649 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
3026 <&gcc GCC_US 2650 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
3027 <&gcc GCC_AG 2651 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
3028 <&gcc GCC_US !! 2652 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3029 <&gcc GCC_US !! 2653 <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
3030 clock-names = "cfg_no !! 2654 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
3031 "core", !! 2655 "sleep";
3032 "iface" <<
3033 "sleep" <<
3034 "mock_u <<
3035 2656
3036 assigned-clocks = <&g 2657 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3037 <&g 2658 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
3038 assigned-clock-rates 2659 assigned-clock-rates = <19200000>, <150000000>;
3039 2660
3040 interrupts-extended = !! 2661 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
3041 !! 2662 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
3042 !! 2663 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
3043 !! 2664 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
3044 !! 2665 interrupt-names = "hs_phy_irq", "ss_phy_irq",
3045 interrupt-names = "pw !! 2666 "dm_hs_phy_irq", "dp_hs_phy_irq";
3046 "hs <<
3047 "dp <<
3048 "dm <<
3049 "ss <<
3050 2667
3051 power-domains = <&gcc 2668 power-domains = <&gcc USB30_PRIM_GDSC>;
3052 required-opps = <&rpm <<
3053 2669
3054 resets = <&gcc GCC_US 2670 resets = <&gcc GCC_USB30_PRIM_BCR>;
3055 2671
3056 interconnects = <&agg !! 2672 interconnects = <&aggre2_noc MASTER_USB3 &mc_virt SLAVE_EBI1>,
3057 <&gem !! 2673 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3>;
3058 interconnect-names = 2674 interconnect-names = "usb-ddr", "apps-usb";
3059 2675
3060 wakeup-source; !! 2676 usb_1_dwc3: dwc3@a600000 {
3061 <<
3062 usb_1_dwc3: usb@a6000 <<
3063 compatible = 2677 compatible = "snps,dwc3";
3064 reg = <0 0x0a 2678 reg = <0 0x0a600000 0 0xe000>;
3065 interrupts = 2679 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
3066 iommus = <&ap 2680 iommus = <&apps_smmu 0x540 0>;
3067 snps,dis_u2_s 2681 snps,dis_u2_susphy_quirk;
3068 snps,dis_enbl 2682 snps,dis_enblslpm_quirk;
3069 snps,parkmode !! 2683 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
3070 phys = <&usb_ <<
3071 phy-names = " 2684 phy-names = "usb2-phy", "usb3-phy";
3072 maximum-speed 2685 maximum-speed = "super-speed";
3073 }; 2686 };
3074 }; 2687 };
3075 2688
3076 venus: video-codec@aa00000 { 2689 venus: video-codec@aa00000 {
3077 compatible = "qcom,sc 2690 compatible = "qcom,sc7180-venus";
3078 reg = <0 0x0aa00000 0 2691 reg = <0 0x0aa00000 0 0xff000>;
3079 interrupts = <GIC_SPI 2692 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
3080 power-domains = <&vid 2693 power-domains = <&videocc VENUS_GDSC>,
3081 <&vid !! 2694 <&videocc VCODEC0_GDSC>;
3082 <&rpm !! 2695 power-domain-names = "venus", "vcodec0";
3083 power-domain-names = <<
3084 operating-points-v2 = <<
3085 clocks = <&videocc VI 2696 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
3086 <&videocc VI 2697 <&videocc VIDEO_CC_VENUS_AHB_CLK>,
3087 <&videocc VI 2698 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>,
3088 <&videocc VI 2699 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
3089 <&videocc VI 2700 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>;
3090 clock-names = "core", 2701 clock-names = "core", "iface", "bus",
3091 "vcodec 2702 "vcodec0_core", "vcodec0_bus";
3092 iommus = <&apps_smmu 2703 iommus = <&apps_smmu 0x0c00 0x60>;
3093 memory-region = <&ven 2704 memory-region = <&venus_mem>;
3094 interconnects = <&mms !! 2705 interconnects = <&mmss_noc MASTER_VIDEO_P0 &mc_virt SLAVE_EBI1>,
3095 <&gem !! 2706 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_VENUS_CFG>;
3096 interconnect-names = 2707 interconnect-names = "video-mem", "cpu-cfg";
3097 2708
3098 video-decoder { 2709 video-decoder {
3099 compatible = 2710 compatible = "venus-decoder";
3100 }; 2711 };
3101 2712
3102 video-encoder { 2713 video-encoder {
3103 compatible = 2714 compatible = "venus-encoder";
3104 }; 2715 };
3105 <<
3106 venus_opp_table: opp- <<
3107 compatible = <<
3108 <<
3109 opp-150000000 <<
3110 opp-h <<
3111 requi <<
3112 }; <<
3113 <<
3114 opp-270000000 <<
3115 opp-h <<
3116 requi <<
3117 }; <<
3118 <<
3119 opp-340000000 <<
3120 opp-h <<
3121 requi <<
3122 }; <<
3123 <<
3124 opp-434000000 <<
3125 opp-h <<
3126 requi <<
3127 }; <<
3128 <<
3129 opp-500000097 <<
3130 opp-h <<
3131 requi <<
3132 }; <<
3133 }; <<
3134 }; 2716 };
3135 2717
3136 videocc: clock-controller@ab0 2718 videocc: clock-controller@ab00000 {
3137 compatible = "qcom,sc 2719 compatible = "qcom,sc7180-videocc";
3138 reg = <0 0x0ab00000 0 2720 reg = <0 0x0ab00000 0 0x10000>;
3139 clocks = <&rpmhcc RPM 2721 clocks = <&rpmhcc RPMH_CXO_CLK>;
3140 clock-names = "bi_tcx 2722 clock-names = "bi_tcxo";
3141 #clock-cells = <1>; 2723 #clock-cells = <1>;
3142 #reset-cells = <1>; 2724 #reset-cells = <1>;
3143 #power-domain-cells = 2725 #power-domain-cells = <1>;
3144 }; 2726 };
3145 2727
3146 camnoc_virt: interconnect@ac0 2728 camnoc_virt: interconnect@ac00000 {
3147 compatible = "qcom,sc 2729 compatible = "qcom,sc7180-camnoc-virt";
3148 reg = <0 0x0ac00000 0 2730 reg = <0 0x0ac00000 0 0x1000>;
3149 #interconnect-cells = !! 2731 #interconnect-cells = <1>;
3150 qcom,bcm-voters = <&a 2732 qcom,bcm-voters = <&apps_bcm_voter>;
3151 }; 2733 };
3152 2734
3153 camcc: clock-controller@ad000 !! 2735 mdss: mdss@ae00000 {
3154 compatible = "qcom,sc <<
3155 reg = <0 0x0ad00000 0 <<
3156 clocks = <&rpmhcc RPM <<
3157 <&gcc GCC_CAME <<
3158 <&gcc GCC_CAME <<
3159 clock-names = "bi_tcx <<
3160 #clock-cells = <1>; <<
3161 #reset-cells = <1>; <<
3162 #power-domain-cells = <<
3163 }; <<
3164 <<
3165 mdss: display-subsystem@ae000 <<
3166 compatible = "qcom,sc 2736 compatible = "qcom,sc7180-mdss";
3167 reg = <0 0x0ae00000 0 2737 reg = <0 0x0ae00000 0 0x1000>;
3168 reg-names = "mdss"; 2738 reg-names = "mdss";
3169 2739
3170 power-domains = <&dis 2740 power-domains = <&dispcc MDSS_GDSC>;
3171 2741
3172 clocks = <&gcc GCC_DI 2742 clocks = <&gcc GCC_DISP_AHB_CLK>,
>> 2743 <&gcc GCC_DISP_HF_AXI_CLK>,
3173 <&dispcc DIS 2744 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3174 <&dispcc DIS 2745 <&dispcc DISP_CC_MDSS_MDP_CLK>;
3175 clock-names = "iface" !! 2746 clock-names = "iface", "bus", "ahb", "core";
>> 2747
>> 2748 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
>> 2749 assigned-clock-rates = <300000000>;
3176 2750
3177 interrupts = <GIC_SPI 2751 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
3178 interrupt-controller; 2752 interrupt-controller;
3179 #interrupt-cells = <1 2753 #interrupt-cells = <1>;
3180 2754
3181 interconnects = <&mms <<
3182 &mc_ <<
3183 <&gem <<
3184 &con <<
3185 interconnect-names = <<
3186 <<
3187 <<
3188 iommus = <&apps_smmu 2755 iommus = <&apps_smmu 0x800 0x2>;
3189 2756
3190 #address-cells = <2>; 2757 #address-cells = <2>;
3191 #size-cells = <2>; 2758 #size-cells = <2>;
3192 ranges; 2759 ranges;
3193 2760
3194 status = "disabled"; 2761 status = "disabled";
3195 2762
3196 mdp: display-controll !! 2763 mdp: mdp@ae01000 {
3197 compatible = 2764 compatible = "qcom,sc7180-dpu";
3198 reg = <0 0x0a 2765 reg = <0 0x0ae01000 0 0x8f000>,
3199 <0 0x0a 2766 <0 0x0aeb0000 0 0x2008>;
3200 reg-names = " 2767 reg-names = "mdp", "vbif";
3201 2768
3202 clocks = <&gc !! 2769 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3203 <&di <<
3204 <&di 2770 <&dispcc DISP_CC_MDSS_ROT_CLK>,
3205 <&di 2771 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
3206 <&di 2772 <&dispcc DISP_CC_MDSS_MDP_CLK>,
3207 <&di 2773 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3208 clock-names = !! 2774 clock-names = "iface", "rot", "lut", "core",
3209 2775 "vsync";
3210 assigned-cloc !! 2776 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
>> 2777 <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
3211 2778 <&dispcc DISP_CC_MDSS_ROT_CLK>,
3212 2779 <&dispcc DISP_CC_MDSS_AHB_CLK>;
3213 assigned-cloc !! 2780 assigned-clock-rates = <300000000>,
>> 2781 <19200000>,
3214 2782 <19200000>,
3215 2783 <19200000>;
3216 operating-poi 2784 operating-points-v2 = <&mdp_opp_table>;
3217 power-domains 2785 power-domains = <&rpmhpd SC7180_CX>;
3218 2786
3219 interrupt-par 2787 interrupt-parent = <&mdss>;
3220 interrupts = 2788 interrupts = <0>;
3221 2789
>> 2790 status = "disabled";
>> 2791
3222 ports { 2792 ports {
3223 #addr 2793 #address-cells = <1>;
3224 #size 2794 #size-cells = <0>;
3225 2795
3226 port@ 2796 port@0 {
3227 2797 reg = <0>;
3228 2798 dpu_intf1_out: endpoint {
3229 !! 2799 remote-endpoint = <&dsi0_in>;
3230 <<
3231 }; <<
3232 <<
3233 port@ <<
3234 <<
3235 <<
3236 <<
3237 2800 };
3238 }; 2801 };
3239 }; 2802 };
3240 2803
3241 mdp_opp_table !! 2804 mdp_opp_table: mdp-opp-table {
3242 compa 2805 compatible = "operating-points-v2";
3243 2806
3244 opp-2 2807 opp-200000000 {
3245 2808 opp-hz = /bits/ 64 <200000000>;
3246 2809 required-opps = <&rpmhpd_opp_low_svs>;
3247 }; 2810 };
3248 2811
3249 opp-3 2812 opp-300000000 {
3250 2813 opp-hz = /bits/ 64 <300000000>;
3251 2814 required-opps = <&rpmhpd_opp_svs>;
3252 }; 2815 };
3253 2816
3254 opp-3 2817 opp-345000000 {
3255 2818 opp-hz = /bits/ 64 <345000000>;
3256 2819 required-opps = <&rpmhpd_opp_svs_l1>;
3257 }; 2820 };
3258 2821
3259 opp-4 2822 opp-460000000 {
3260 2823 opp-hz = /bits/ 64 <460000000>;
3261 2824 required-opps = <&rpmhpd_opp_nom>;
3262 }; 2825 };
3263 }; 2826 };
>> 2827
3264 }; 2828 };
3265 2829
3266 mdss_dsi0: dsi@ae9400 !! 2830 dsi0: dsi@ae94000 {
3267 compatible = !! 2831 compatible = "qcom,mdss-dsi-ctrl";
3268 <<
3269 reg = <0 0x0a 2832 reg = <0 0x0ae94000 0 0x400>;
3270 reg-names = " 2833 reg-names = "dsi_ctrl";
3271 2834
3272 interrupt-par 2835 interrupt-parent = <&mdss>;
3273 interrupts = 2836 interrupts = <4>;
3274 2837
3275 clocks = <&di 2838 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
3276 <&di 2839 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
3277 <&di 2840 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
3278 <&di 2841 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
3279 <&di 2842 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3280 <&gc 2843 <&gcc GCC_DISP_HF_AXI_CLK>;
3281 clock-names = 2844 clock-names = "byte",
3282 2845 "byte_intf",
3283 2846 "pixel",
3284 2847 "core",
3285 2848 "iface",
3286 2849 "bus";
3287 2850
3288 assigned-cloc <<
3289 assigned-cloc <<
3290 <<
3291 operating-poi 2851 operating-points-v2 = <&dsi_opp_table>;
3292 power-domains 2852 power-domains = <&rpmhpd SC7180_CX>;
3293 2853
3294 phys = <&mdss !! 2854 phys = <&dsi_phy>;
>> 2855 phy-names = "dsi";
3295 2856
3296 #address-cell 2857 #address-cells = <1>;
3297 #size-cells = 2858 #size-cells = <0>;
3298 2859
3299 status = "dis 2860 status = "disabled";
3300 2861
3301 ports { 2862 ports {
3302 #addr 2863 #address-cells = <1>;
3303 #size 2864 #size-cells = <0>;
3304 2865
3305 port@ 2866 port@0 {
3306 2867 reg = <0>;
3307 !! 2868 dsi0_in: endpoint {
3308 2869 remote-endpoint = <&dpu_intf1_out>;
3309 2870 };
3310 }; 2871 };
3311 2872
3312 port@ 2873 port@1 {
3313 2874 reg = <1>;
3314 !! 2875 dsi0_out: endpoint {
3315 2876 };
3316 }; 2877 };
3317 }; 2878 };
3318 2879
3319 dsi_opp_table !! 2880 dsi_opp_table: dsi-opp-table {
3320 compa 2881 compatible = "operating-points-v2";
3321 2882
3322 opp-1 2883 opp-187500000 {
3323 2884 opp-hz = /bits/ 64 <187500000>;
3324 2885 required-opps = <&rpmhpd_opp_low_svs>;
3325 }; 2886 };
3326 2887
3327 opp-3 2888 opp-300000000 {
3328 2889 opp-hz = /bits/ 64 <300000000>;
3329 2890 required-opps = <&rpmhpd_opp_svs>;
3330 }; 2891 };
3331 2892
3332 opp-3 2893 opp-358000000 {
3333 2894 opp-hz = /bits/ 64 <358000000>;
3334 2895 required-opps = <&rpmhpd_opp_svs_l1>;
3335 }; 2896 };
3336 }; 2897 };
3337 }; 2898 };
3338 2899
3339 mdss_dsi0_phy: phy@ae !! 2900 dsi_phy: dsi-phy@ae94400 {
3340 compatible = 2901 compatible = "qcom,dsi-phy-10nm";
3341 reg = <0 0x0a 2902 reg = <0 0x0ae94400 0 0x200>,
3342 <0 0x0a 2903 <0 0x0ae94600 0 0x280>,
3343 <0 0x0a 2904 <0 0x0ae94a00 0 0x1e0>;
3344 reg-names = " 2905 reg-names = "dsi_phy",
3345 " 2906 "dsi_phy_lane",
3346 " 2907 "dsi_pll";
3347 2908
3348 #clock-cells 2909 #clock-cells = <1>;
3349 #phy-cells = 2910 #phy-cells = <0>;
3350 2911
3351 clocks = <&di 2912 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3352 <&rp 2913 <&rpmhcc RPMH_CXO_CLK>;
3353 clock-names = 2914 clock-names = "iface", "ref";
3354 2915
3355 status = "dis 2916 status = "disabled";
3356 }; 2917 };
3357 <<
3358 mdss_dp: displayport- <<
3359 compatible = <<
3360 status = "dis <<
3361 <<
3362 reg = <0 0x0a <<
3363 <0 0x0a <<
3364 <0 0x0a <<
3365 <0 0x0a <<
3366 <0 0x0a <<
3367 <<
3368 interrupt-par <<
3369 interrupts = <<
3370 <<
3371 clocks = <&di <<
3372 <&di <<
3373 <&di <<
3374 <&di <<
3375 <&di <<
3376 clock-names = <<
3377 <<
3378 assigned-cloc <<
3379 <<
3380 assigned-cloc <<
3381 <<
3382 phys = <&usb_ <<
3383 phy-names = " <<
3384 <<
3385 operating-poi <<
3386 power-domains <<
3387 <<
3388 #sound-dai-ce <<
3389 <<
3390 ports { <<
3391 #addr <<
3392 #size <<
3393 port@ <<
3394 <<
3395 <<
3396 <<
3397 <<
3398 }; <<
3399 <<
3400 port@ <<
3401 <<
3402 <<
3403 }; <<
3404 }; <<
3405 <<
3406 dp_opp_table: <<
3407 compa <<
3408 <<
3409 opp-1 <<
3410 <<
3411 <<
3412 }; <<
3413 <<
3414 opp-2 <<
3415 <<
3416 <<
3417 }; <<
3418 <<
3419 opp-5 <<
3420 <<
3421 <<
3422 }; <<
3423 <<
3424 opp-8 <<
3425 <<
3426 <<
3427 }; <<
3428 }; <<
3429 }; <<
3430 }; 2918 };
3431 2919
3432 dispcc: clock-controller@af00 2920 dispcc: clock-controller@af00000 {
3433 compatible = "qcom,sc 2921 compatible = "qcom,sc7180-dispcc";
3434 reg = <0 0x0af00000 0 2922 reg = <0 0x0af00000 0 0x200000>;
3435 clocks = <&rpmhcc RPM 2923 clocks = <&rpmhcc RPMH_CXO_CLK>,
3436 <&gcc GCC_DI 2924 <&gcc GCC_DISP_GPLL0_CLK_SRC>,
3437 <&mdss_dsi0_ !! 2925 <&dsi_phy 0>,
3438 <&mdss_dsi0_ !! 2926 <&dsi_phy 1>,
3439 <&usb_1_qmpp !! 2927 <0>,
3440 <&usb_1_qmpp !! 2928 <0>;
3441 clock-names = "bi_tcx 2929 clock-names = "bi_tcxo",
3442 "gcc_di 2930 "gcc_disp_gpll0_clk_src",
3443 "dsi0_p 2931 "dsi0_phy_pll_out_byteclk",
3444 "dsi0_p 2932 "dsi0_phy_pll_out_dsiclk",
3445 "dp_phy 2933 "dp_phy_pll_link_clk",
3446 "dp_phy 2934 "dp_phy_pll_vco_div_clk";
3447 #clock-cells = <1>; 2935 #clock-cells = <1>;
3448 #reset-cells = <1>; 2936 #reset-cells = <1>;
3449 #power-domain-cells = 2937 #power-domain-cells = <1>;
3450 }; 2938 };
3451 2939
3452 pdc: interrupt-controller@b22 2940 pdc: interrupt-controller@b220000 {
3453 compatible = "qcom,sc 2941 compatible = "qcom,sc7180-pdc", "qcom,pdc";
3454 reg = <0 0x0b220000 0 2942 reg = <0 0x0b220000 0 0x30000>;
3455 qcom,pdc-ranges = <0 2943 qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>;
3456 #interrupt-cells = <2 2944 #interrupt-cells = <2>;
3457 interrupt-parent = <& 2945 interrupt-parent = <&intc>;
3458 interrupt-controller; 2946 interrupt-controller;
3459 }; 2947 };
3460 2948
3461 pdc_reset: reset-controller@b 2949 pdc_reset: reset-controller@b2e0000 {
3462 compatible = "qcom,sc 2950 compatible = "qcom,sc7180-pdc-global", "qcom,sdm845-pdc-global";
3463 reg = <0 0x0b2e0000 0 2951 reg = <0 0x0b2e0000 0 0x20000>;
3464 #reset-cells = <1>; 2952 #reset-cells = <1>;
3465 }; 2953 };
3466 2954
3467 tsens0: thermal-sensor@c26300 2955 tsens0: thermal-sensor@c263000 {
3468 compatible = "qcom,sc 2956 compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
3469 reg = <0 0x0c263000 0 2957 reg = <0 0x0c263000 0 0x1ff>, /* TM */
3470 <0 0x0c222000 2958 <0 0x0c222000 0 0x1ff>; /* SROT */
3471 #qcom,sensors = <15>; 2959 #qcom,sensors = <15>;
3472 interrupts = <GIC_SPI 2960 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
3473 <GIC_SPI 2961 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
3474 interrupt-names = "up 2962 interrupt-names = "uplow","critical";
3475 #thermal-sensor-cells 2963 #thermal-sensor-cells = <1>;
3476 }; 2964 };
3477 2965
3478 tsens1: thermal-sensor@c26500 2966 tsens1: thermal-sensor@c265000 {
3479 compatible = "qcom,sc 2967 compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
3480 reg = <0 0x0c265000 0 2968 reg = <0 0x0c265000 0 0x1ff>, /* TM */
3481 <0 0x0c223000 2969 <0 0x0c223000 0 0x1ff>; /* SROT */
3482 #qcom,sensors = <10>; 2970 #qcom,sensors = <10>;
3483 interrupts = <GIC_SPI 2971 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
3484 <GIC_SPI 2972 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
3485 interrupt-names = "up 2973 interrupt-names = "uplow","critical";
3486 #thermal-sensor-cells 2974 #thermal-sensor-cells = <1>;
3487 }; 2975 };
3488 2976
3489 aoss_reset: reset-controller@ 2977 aoss_reset: reset-controller@c2a0000 {
3490 compatible = "qcom,sc 2978 compatible = "qcom,sc7180-aoss-cc", "qcom,sdm845-aoss-cc";
3491 reg = <0 0x0c2a0000 0 2979 reg = <0 0x0c2a0000 0 0x31000>;
3492 #reset-cells = <1>; 2980 #reset-cells = <1>;
3493 }; 2981 };
3494 2982
3495 aoss_qmp: power-management@c3 !! 2983 aoss_qmp: qmp@c300000 {
3496 compatible = "qcom,sc !! 2984 compatible = "qcom,sc7180-aoss-qmp";
3497 reg = <0 0x0c300000 0 !! 2985 reg = <0 0x0c300000 0 0x100000>;
3498 interrupts = <GIC_SPI 2986 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
3499 mboxes = <&apss_share 2987 mboxes = <&apss_shared 0>;
3500 2988
3501 #clock-cells = <0>; 2989 #clock-cells = <0>;
3502 }; !! 2990 #power-domain-cells = <1>;
3503 <<
3504 sram@c3f0000 { <<
3505 compatible = "qcom,rp <<
3506 reg = <0 0x0c3f0000 0 <<
3507 }; 2991 };
3508 2992
3509 spmi_bus: spmi@c440000 { 2993 spmi_bus: spmi@c440000 {
3510 compatible = "qcom,sp 2994 compatible = "qcom,spmi-pmic-arb";
3511 reg = <0 0x0c440000 0 2995 reg = <0 0x0c440000 0 0x1100>,
3512 <0 0x0c600000 0 2996 <0 0x0c600000 0 0x2000000>,
3513 <0 0x0e600000 0 2997 <0 0x0e600000 0 0x100000>,
3514 <0 0x0e700000 0 2998 <0 0x0e700000 0 0xa0000>,
3515 <0 0x0c40a000 0 2999 <0 0x0c40a000 0 0x26000>;
3516 reg-names = "core", " 3000 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3517 interrupt-names = "pe 3001 interrupt-names = "periph_irq";
3518 interrupts-extended = 3002 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3519 qcom,ee = <0>; 3003 qcom,ee = <0>;
3520 qcom,channel = <0>; 3004 qcom,channel = <0>;
3521 #address-cells = <2>; <<
3522 #size-cells = <0>; <<
3523 interrupt-controller; <<
3524 #interrupt-cells = <4 <<
3525 }; <<
3526 <<
3527 sram@146aa000 { <<
3528 compatible = "qcom,sc <<
3529 reg = <0 0x146aa000 0 <<
3530 <<
3531 #address-cells = <1>; 3005 #address-cells = <1>;
3532 #size-cells = <1>; 3006 #size-cells = <1>;
3533 !! 3007 interrupt-controller;
3534 ranges = <0 0 0x146aa !! 3008 #interrupt-cells = <4>;
3535 !! 3009 cell-index = <0>;
3536 pil-reloc@94c { <<
3537 compatible = <<
3538 reg = <0x94c <<
3539 }; <<
3540 }; 3010 };
3541 3011
3542 apps_smmu: iommu@15000000 { 3012 apps_smmu: iommu@15000000 {
3543 compatible = "qcom,sc 3013 compatible = "qcom,sc7180-smmu-500", "arm,mmu-500";
3544 reg = <0 0x15000000 0 3014 reg = <0 0x15000000 0 0x100000>;
3545 #iommu-cells = <2>; 3015 #iommu-cells = <2>;
3546 #global-interrupts = 3016 #global-interrupts = <1>;
3547 interrupts = <GIC_SPI 3017 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
3548 <GIC_SPI 3018 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
3549 <GIC_SPI 3019 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
3550 <GIC_SPI 3020 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
3551 <GIC_SPI 3021 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
3552 <GIC_SPI 3022 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
3553 <GIC_SPI 3023 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
3554 <GIC_SPI 3024 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
3555 <GIC_SPI 3025 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
3556 <GIC_SPI 3026 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
3557 <GIC_SPI 3027 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
3558 <GIC_SPI 3028 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
3559 <GIC_SPI 3029 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
3560 <GIC_SPI 3030 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
3561 <GIC_SPI 3031 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
3562 <GIC_SPI 3032 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
3563 <GIC_SPI 3033 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
3564 <GIC_SPI 3034 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
3565 <GIC_SPI 3035 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
3566 <GIC_SPI 3036 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
3567 <GIC_SPI 3037 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
3568 <GIC_SPI 3038 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
3569 <GIC_SPI 3039 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
3570 <GIC_SPI 3040 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
3571 <GIC_SPI 3041 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
3572 <GIC_SPI 3042 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
3573 <GIC_SPI 3043 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
3574 <GIC_SPI 3044 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
3575 <GIC_SPI 3045 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
3576 <GIC_SPI 3046 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
3577 <GIC_SPI 3047 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
3578 <GIC_SPI 3048 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
3579 <GIC_SPI 3049 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
3580 <GIC_SPI 3050 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
3581 <GIC_SPI 3051 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
3582 <GIC_SPI 3052 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
3583 <GIC_SPI 3053 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
3584 <GIC_SPI 3054 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
3585 <GIC_SPI 3055 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
3586 <GIC_SPI 3056 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
3587 <GIC_SPI 3057 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
3588 <GIC_SPI 3058 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
3589 <GIC_SPI 3059 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
3590 <GIC_SPI 3060 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
3591 <GIC_SPI 3061 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
3592 <GIC_SPI 3062 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
3593 <GIC_SPI 3063 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
3594 <GIC_SPI 3064 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
3595 <GIC_SPI 3065 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
3596 <GIC_SPI 3066 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
3597 <GIC_SPI 3067 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
3598 <GIC_SPI 3068 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
3599 <GIC_SPI 3069 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
3600 <GIC_SPI 3070 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
3601 <GIC_SPI 3071 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
3602 <GIC_SPI 3072 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
3603 <GIC_SPI 3073 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
3604 <GIC_SPI 3074 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
3605 <GIC_SPI 3075 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
3606 <GIC_SPI 3076 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
3607 <GIC_SPI 3077 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
3608 <GIC_SPI 3078 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
3609 <GIC_SPI 3079 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
3610 <GIC_SPI 3080 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
3611 <GIC_SPI 3081 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
3612 <GIC_SPI 3082 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
3613 <GIC_SPI 3083 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
3614 <GIC_SPI 3084 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
3615 <GIC_SPI 3085 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
3616 <GIC_SPI 3086 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
3617 <GIC_SPI 3087 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
3618 <GIC_SPI 3088 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
3619 <GIC_SPI 3089 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
3620 <GIC_SPI 3090 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
3621 <GIC_SPI 3091 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
3622 <GIC_SPI 3092 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
3623 <GIC_SPI 3093 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
3624 <GIC_SPI 3094 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
3625 <GIC_SPI 3095 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
3626 <GIC_SPI 3096 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
3627 <GIC_SPI 3097 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
3628 }; 3098 };
3629 3099
3630 intc: interrupt-controller@17 3100 intc: interrupt-controller@17a00000 {
3631 compatible = "arm,gic 3101 compatible = "arm,gic-v3";
3632 #address-cells = <2>; 3102 #address-cells = <2>;
3633 #size-cells = <2>; 3103 #size-cells = <2>;
3634 ranges; 3104 ranges;
3635 #interrupt-cells = <3 3105 #interrupt-cells = <3>;
3636 interrupt-controller; 3106 interrupt-controller;
3637 reg = <0 0x17a00000 0 3107 reg = <0 0x17a00000 0 0x10000>, /* GICD */
3638 <0 0x17a60000 0 3108 <0 0x17a60000 0 0x100000>; /* GICR * 8 */
3639 interrupts = <GIC_PPI 3109 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3640 3110
3641 msi-controller@17a400 3111 msi-controller@17a40000 {
3642 compatible = 3112 compatible = "arm,gic-v3-its";
3643 msi-controlle 3113 msi-controller;
3644 #msi-cells = 3114 #msi-cells = <1>;
3645 reg = <0 0x17 3115 reg = <0 0x17a40000 0 0x20000>;
3646 status = "dis 3116 status = "disabled";
3647 }; 3117 };
3648 }; 3118 };
3649 3119
3650 apss_shared: mailbox@17c00000 3120 apss_shared: mailbox@17c00000 {
3651 compatible = "qcom,sc !! 3121 compatible = "qcom,sc7180-apss-shared";
3652 "qcom,sd <<
3653 reg = <0 0x17c00000 0 3122 reg = <0 0x17c00000 0 0x10000>;
3654 #mbox-cells = <1>; 3123 #mbox-cells = <1>;
3655 }; 3124 };
3656 3125
3657 watchdog@17c10000 { 3126 watchdog@17c10000 {
3658 compatible = "qcom,ap 3127 compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt";
3659 reg = <0 0x17c10000 0 3128 reg = <0 0x17c10000 0 0x1000>;
3660 clocks = <&sleep_clk> 3129 clocks = <&sleep_clk>;
3661 interrupts = <GIC_SPI <<
3662 }; 3130 };
3663 3131
3664 timer@17c20000 { !! 3132 timer@17c20000{
3665 #address-cells = <1>; !! 3133 #address-cells = <2>;
3666 #size-cells = <1>; !! 3134 #size-cells = <2>;
3667 ranges = <0 0 0 0x200 !! 3135 ranges;
3668 compatible = "arm,arm 3136 compatible = "arm,armv7-timer-mem";
3669 reg = <0 0x17c20000 0 3137 reg = <0 0x17c20000 0 0x1000>;
3670 3138
3671 frame@17c21000 { 3139 frame@17c21000 {
3672 frame-number 3140 frame-number = <0>;
3673 interrupts = 3141 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
3674 3142 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
3675 reg = <0x17c2 !! 3143 reg = <0 0x17c21000 0 0x1000>,
3676 <0x17c2 !! 3144 <0 0x17c22000 0 0x1000>;
3677 }; 3145 };
3678 3146
3679 frame@17c23000 { 3147 frame@17c23000 {
3680 frame-number 3148 frame-number = <1>;
3681 interrupts = 3149 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
3682 reg = <0x17c2 !! 3150 reg = <0 0x17c23000 0 0x1000>;
3683 status = "dis 3151 status = "disabled";
3684 }; 3152 };
3685 3153
3686 frame@17c25000 { 3154 frame@17c25000 {
3687 frame-number 3155 frame-number = <2>;
3688 interrupts = 3156 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
3689 reg = <0x17c2 !! 3157 reg = <0 0x17c25000 0 0x1000>;
3690 status = "dis 3158 status = "disabled";
3691 }; 3159 };
3692 3160
3693 frame@17c27000 { 3161 frame@17c27000 {
3694 frame-number 3162 frame-number = <3>;
3695 interrupts = 3163 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3696 reg = <0x17c2 !! 3164 reg = <0 0x17c27000 0 0x1000>;
3697 status = "dis 3165 status = "disabled";
3698 }; 3166 };
3699 3167
3700 frame@17c29000 { 3168 frame@17c29000 {
3701 frame-number 3169 frame-number = <4>;
3702 interrupts = 3170 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3703 reg = <0x17c2 !! 3171 reg = <0 0x17c29000 0 0x1000>;
3704 status = "dis 3172 status = "disabled";
3705 }; 3173 };
3706 3174
3707 frame@17c2b000 { 3175 frame@17c2b000 {
3708 frame-number 3176 frame-number = <5>;
3709 interrupts = 3177 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3710 reg = <0x17c2 !! 3178 reg = <0 0x17c2b000 0 0x1000>;
3711 status = "dis 3179 status = "disabled";
3712 }; 3180 };
3713 3181
3714 frame@17c2d000 { 3182 frame@17c2d000 {
3715 frame-number 3183 frame-number = <6>;
3716 interrupts = 3184 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
3717 reg = <0x17c2 !! 3185 reg = <0 0x17c2d000 0 0x1000>;
3718 status = "dis 3186 status = "disabled";
3719 }; 3187 };
3720 }; 3188 };
3721 3189
3722 apps_rsc: rsc@18200000 { 3190 apps_rsc: rsc@18200000 {
3723 compatible = "qcom,rp 3191 compatible = "qcom,rpmh-rsc";
3724 reg = <0 0x18200000 0 3192 reg = <0 0x18200000 0 0x10000>,
3725 <0 0x18210000 0 3193 <0 0x18210000 0 0x10000>,
3726 <0 0x18220000 0 3194 <0 0x18220000 0 0x10000>;
3727 reg-names = "drv-0", 3195 reg-names = "drv-0", "drv-1", "drv-2";
3728 interrupts = <GIC_SPI 3196 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
3729 <GIC_SPI 3197 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
3730 <GIC_SPI 3198 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
3731 qcom,tcs-offset = <0x 3199 qcom,tcs-offset = <0xd00>;
3732 qcom,drv-id = <2>; 3200 qcom,drv-id = <2>;
3733 qcom,tcs-config = <AC 3201 qcom,tcs-config = <ACTIVE_TCS 2>,
3734 <SL 3202 <SLEEP_TCS 3>,
3735 <WA 3203 <WAKE_TCS 3>,
3736 <CO 3204 <CONTROL_TCS 1>;
3737 power-domains = <&CLU <<
3738 3205
3739 rpmhcc: clock-control 3206 rpmhcc: clock-controller {
3740 compatible = 3207 compatible = "qcom,sc7180-rpmh-clk";
3741 clocks = <&xo 3208 clocks = <&xo_board>;
3742 clock-names = 3209 clock-names = "xo";
3743 #clock-cells 3210 #clock-cells = <1>;
3744 }; 3211 };
3745 3212
3746 rpmhpd: power-control 3213 rpmhpd: power-controller {
3747 compatible = 3214 compatible = "qcom,sc7180-rpmhpd";
3748 #power-domain 3215 #power-domain-cells = <1>;
3749 operating-poi 3216 operating-points-v2 = <&rpmhpd_opp_table>;
3750 3217
3751 rpmhpd_opp_ta 3218 rpmhpd_opp_table: opp-table {
3752 compa 3219 compatible = "operating-points-v2";
3753 3220
3754 rpmhp 3221 rpmhpd_opp_ret: opp1 {
3755 3222 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3756 }; 3223 };
3757 3224
3758 rpmhp 3225 rpmhpd_opp_min_svs: opp2 {
3759 3226 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3760 }; 3227 };
3761 3228
3762 rpmhp 3229 rpmhpd_opp_low_svs: opp3 {
3763 3230 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3764 }; 3231 };
3765 3232
3766 rpmhp 3233 rpmhpd_opp_svs: opp4 {
3767 3234 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3768 }; 3235 };
3769 3236
3770 rpmhp 3237 rpmhpd_opp_svs_l1: opp5 {
3771 3238 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3772 }; 3239 };
3773 3240
3774 rpmhp 3241 rpmhpd_opp_svs_l2: opp6 {
3775 3242 opp-level = <224>;
3776 }; 3243 };
3777 3244
3778 rpmhp 3245 rpmhpd_opp_nom: opp7 {
3779 3246 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3780 }; 3247 };
3781 3248
3782 rpmhp 3249 rpmhpd_opp_nom_l1: opp8 {
3783 3250 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3784 }; 3251 };
3785 3252
3786 rpmhp 3253 rpmhpd_opp_nom_l2: opp9 {
3787 3254 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3788 }; 3255 };
3789 3256
3790 rpmhp 3257 rpmhpd_opp_turbo: opp10 {
3791 3258 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3792 }; 3259 };
3793 3260
3794 rpmhp 3261 rpmhpd_opp_turbo_l1: opp11 {
3795 3262 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3796 }; 3263 };
3797 }; 3264 };
3798 }; 3265 };
3799 3266
3800 apps_bcm_voter: bcm-v !! 3267 apps_bcm_voter: bcm_voter {
3801 compatible = 3268 compatible = "qcom,bcm-voter";
3802 }; 3269 };
3803 }; 3270 };
3804 3271
3805 osm_l3: interconnect@18321000 3272 osm_l3: interconnect@18321000 {
3806 compatible = "qcom,sc !! 3273 compatible = "qcom,sc7180-osm-l3";
3807 reg = <0 0x18321000 0 3274 reg = <0 0x18321000 0 0x1400>;
3808 3275
3809 clocks = <&rpmhcc RPM 3276 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3810 clock-names = "xo", " 3277 clock-names = "xo", "alternate";
3811 3278
3812 #interconnect-cells = 3279 #interconnect-cells = <1>;
3813 }; 3280 };
3814 3281
3815 cpufreq_hw: cpufreq@18323000 3282 cpufreq_hw: cpufreq@18323000 {
3816 compatible = "qcom,sc !! 3283 compatible = "qcom,cpufreq-hw";
3817 reg = <0 0x18323000 0 3284 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>;
3818 reg-names = "freq-dom 3285 reg-names = "freq-domain0", "freq-domain1";
3819 3286
3820 clocks = <&rpmhcc RPM 3287 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3821 clock-names = "xo", " 3288 clock-names = "xo", "alternate";
3822 3289
3823 #freq-domain-cells = 3290 #freq-domain-cells = <1>;
3824 #clock-cells = <1>; <<
3825 }; 3291 };
3826 3292
3827 wifi: wifi@18800000 { 3293 wifi: wifi@18800000 {
3828 compatible = "qcom,wc 3294 compatible = "qcom,wcn3990-wifi";
3829 reg = <0 0x18800000 0 3295 reg = <0 0x18800000 0 0x800000>;
3830 reg-names = "membase" 3296 reg-names = "membase";
3831 iommus = <&apps_smmu 3297 iommus = <&apps_smmu 0xc0 0x1>;
3832 interrupts = 3298 interrupts =
3833 <GIC_SPI 414 3299 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH /* CE0 */ >,
3834 <GIC_SPI 415 3300 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH /* CE1 */ >,
3835 <GIC_SPI 416 3301 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH /* CE2 */ >,
3836 <GIC_SPI 417 3302 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH /* CE3 */ >,
3837 <GIC_SPI 418 3303 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH /* CE4 */ >,
3838 <GIC_SPI 419 3304 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH /* CE5 */ >,
3839 <GIC_SPI 420 3305 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH /* CE6 */ >,
3840 <GIC_SPI 421 3306 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH /* CE7 */ >,
3841 <GIC_SPI 422 3307 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH /* CE8 */ >,
3842 <GIC_SPI 423 3308 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH /* CE9 */ >,
3843 <GIC_SPI 424 3309 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH /* CE10 */>,
3844 <GIC_SPI 425 3310 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH /* CE11 */>;
3845 memory-region = <&wla 3311 memory-region = <&wlan_mem>;
3846 qcom,msa-fixed-perm; 3312 qcom,msa-fixed-perm;
3847 status = "disabled"; 3313 status = "disabled";
3848 }; 3314 };
3849 <<
3850 remoteproc_adsp: remoteproc@6 <<
3851 compatible = "qcom,sc <<
3852 reg = <0 0x62400000 0 <<
3853 <<
3854 interrupts-extended = <<
3855 <<
3856 <<
3857 <<
3858 <<
3859 interrupt-names = "wd <<
3860 "fa <<
3861 "re <<
3862 "ha <<
3863 "st <<
3864 <<
3865 clocks = <&rpmhcc RPM <<
3866 clock-names = "xo"; <<
3867 <<
3868 power-domains = <&rpm <<
3869 <&rpm <<
3870 power-domain-names = <<
3871 <<
3872 qcom,qmp = <&aoss_qmp <<
3873 qcom,smem-states = <& <<
3874 qcom,smem-state-names <<
3875 <<
3876 status = "disabled"; <<
3877 <<
3878 glink-edge { <<
3879 interrupts = <<
3880 label = "lpas <<
3881 qcom,remote-p <<
3882 mboxes = <&ap <<
3883 <<
3884 apr { <<
3885 compa <<
3886 qcom, <<
3887 qcom, <<
3888 #addr <<
3889 #size <<
3890 <<
3891 servi <<
3892 <<
3893 <<
3894 <<
3895 }; <<
3896 <<
3897 q6afe <<
3898 <<
3899 <<
3900 <<
3901 <<
3902 <<
3903 <<
3904 <<
3905 <<
3906 <<
3907 <<
3908 <<
3909 <<
3910 <<
3911 <<
3912 <<
3913 }; <<
3914 <<
3915 q6asm <<
3916 <<
3917 <<
3918 <<
3919 <<
3920 <<
3921 <<
3922 <<
3923 <<
3924 <<
3925 <<
3926 <<
3927 }; <<
3928 <<
3929 q6adm <<
3930 <<
3931 <<
3932 <<
3933 <<
3934 <<
3935 <<
3936 <<
3937 <<
3938 }; <<
3939 }; <<
3940 <<
3941 fastrpc { <<
3942 compa <<
3943 qcom, <<
3944 label <<
3945 #addr <<
3946 #size <<
3947 <<
3948 compu <<
3949 <<
3950 <<
3951 <<
3952 }; <<
3953 <<
3954 compu <<
3955 <<
3956 <<
3957 <<
3958 }; <<
3959 <<
3960 compu <<
3961 <<
3962 <<
3963 <<
3964 <<
3965 }; <<
3966 }; <<
3967 }; <<
3968 }; <<
3969 <<
3970 lpasscc: clock-controller@62d <<
3971 compatible = "qcom,sc <<
3972 reg = <0 0x62d00000 0 <<
3973 <0 0x62780000 0 <<
3974 reg-names = "lpass_co <<
3975 clocks = <&gcc GCC_LP <<
3976 <&rpmhcc RPM <<
3977 clock-names = "iface" <<
3978 power-domains = <&lpa <<
3979 #clock-cells = <1>; <<
3980 #power-domain-cells = <<
3981 <<
3982 status = "reserved"; <<
3983 }; <<
3984 <<
3985 lpass_cpu: lpass@62d87000 { <<
3986 compatible = "qcom,sc <<
3987 <<
3988 reg = <0 0x62d87000 0 <<
3989 reg-names = "lpass-hd <<
3990 <<
3991 iommus = <&apps_smmu <<
3992 <&apps_smmu 0 <<
3993 <&apps_smmu 0 <<
3994 <<
3995 power-domains = <&lpa <<
3996 required-opps = <&rpm <<
3997 <<
3998 status = "disabled"; <<
3999 <<
4000 clocks = <&gcc GCC_LP <<
4001 <&lpasscc LP <<
4002 <&lpasscc LP <<
4003 <&lpasscc LP <<
4004 <&lpasscc LP <<
4005 <&lpasscc LP <<
4006 <<
4007 clock-names = "pcnoc- <<
4008 "mclk <<
4009 "mi2s <<
4010 <<
4011 <<
4012 #sound-dai-cells = <1 <<
4013 #address-cells = <1>; <<
4014 #size-cells = <0>; <<
4015 <<
4016 interrupts = <GIC_SPI <<
4017 <GIC_ <<
4018 interrupt-names = "lp <<
4019 }; <<
4020 <<
4021 lpass_hm: clock-controller@63 <<
4022 compatible = "qcom,sc <<
4023 reg = <0 0x63000000 0 <<
4024 clocks = <&gcc GCC_LP <<
4025 <&rpmhcc RPM <<
4026 clock-names = "iface" <<
4027 power-domains = <&rpm <<
4028 <<
4029 #clock-cells = <1>; <<
4030 #power-domain-cells = <<
4031 <<
4032 status = "reserved"; <<
4033 }; <<
4034 }; 3315 };
4035 3316
4036 thermal-zones { 3317 thermal-zones {
4037 cpu0_thermal: cpu0-thermal { !! 3318 cpu0-thermal {
4038 polling-delay-passive !! 3319 polling-delay-passive = <0>;
>> 3320 polling-delay = <0>;
4039 3321
4040 thermal-sensors = <&t 3322 thermal-sensors = <&tsens0 1>;
4041 sustainable-power = < <<
4042 3323
4043 trips { 3324 trips {
4044 cpu0_alert0: 3325 cpu0_alert0: trip-point0 {
4045 tempe 3326 temperature = <90000>;
4046 hyste 3327 hysteresis = <2000>;
4047 type 3328 type = "passive";
4048 }; 3329 };
4049 3330
4050 cpu0_alert1: 3331 cpu0_alert1: trip-point1 {
4051 tempe 3332 temperature = <95000>;
4052 hyste 3333 hysteresis = <2000>;
4053 type 3334 type = "passive";
4054 }; 3335 };
4055 3336
4056 cpu0_crit: cp !! 3337 cpu0_crit: cpu_crit {
4057 tempe 3338 temperature = <110000>;
4058 hyste 3339 hysteresis = <1000>;
4059 type 3340 type = "critical";
4060 }; 3341 };
4061 }; 3342 };
4062 3343
4063 cooling-maps { 3344 cooling-maps {
4064 map0 { 3345 map0 {
4065 trip 3346 trip = <&cpu0_alert0>;
4066 cooli 3347 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4067 3348 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4068 3349 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4069 3350 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4070 3351 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4071 3352 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4072 }; 3353 };
4073 map1 { 3354 map1 {
4074 trip 3355 trip = <&cpu0_alert1>;
4075 cooli 3356 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4076 3357 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4077 3358 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4078 3359 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4079 3360 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4080 3361 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4081 }; 3362 };
4082 }; 3363 };
4083 }; 3364 };
4084 3365
4085 cpu1_thermal: cpu1-thermal { !! 3366 cpu1-thermal {
4086 polling-delay-passive !! 3367 polling-delay-passive = <0>;
>> 3368 polling-delay = <0>;
4087 3369
4088 thermal-sensors = <&t 3370 thermal-sensors = <&tsens0 2>;
4089 sustainable-power = < <<
4090 3371
4091 trips { 3372 trips {
4092 cpu1_alert0: 3373 cpu1_alert0: trip-point0 {
4093 tempe 3374 temperature = <90000>;
4094 hyste 3375 hysteresis = <2000>;
4095 type 3376 type = "passive";
4096 }; 3377 };
4097 3378
4098 cpu1_alert1: 3379 cpu1_alert1: trip-point1 {
4099 tempe 3380 temperature = <95000>;
4100 hyste 3381 hysteresis = <2000>;
4101 type 3382 type = "passive";
4102 }; 3383 };
4103 3384
4104 cpu1_crit: cp !! 3385 cpu1_crit: cpu_crit {
4105 tempe 3386 temperature = <110000>;
4106 hyste 3387 hysteresis = <1000>;
4107 type 3388 type = "critical";
4108 }; 3389 };
4109 }; 3390 };
4110 3391
4111 cooling-maps { 3392 cooling-maps {
4112 map0 { 3393 map0 {
4113 trip 3394 trip = <&cpu1_alert0>;
4114 cooli 3395 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4115 3396 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4116 3397 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4117 3398 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4118 3399 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4119 3400 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4120 }; 3401 };
4121 map1 { 3402 map1 {
4122 trip 3403 trip = <&cpu1_alert1>;
4123 cooli 3404 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4124 3405 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4125 3406 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4126 3407 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4127 3408 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4128 3409 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4129 }; 3410 };
4130 }; 3411 };
4131 }; 3412 };
4132 3413
4133 cpu2_thermal: cpu2-thermal { !! 3414 cpu2-thermal {
4134 polling-delay-passive !! 3415 polling-delay-passive = <0>;
>> 3416 polling-delay = <0>;
4135 3417
4136 thermal-sensors = <&t 3418 thermal-sensors = <&tsens0 3>;
4137 sustainable-power = < <<
4138 3419
4139 trips { 3420 trips {
4140 cpu2_alert0: 3421 cpu2_alert0: trip-point0 {
4141 tempe 3422 temperature = <90000>;
4142 hyste 3423 hysteresis = <2000>;
4143 type 3424 type = "passive";
4144 }; 3425 };
4145 3426
4146 cpu2_alert1: 3427 cpu2_alert1: trip-point1 {
4147 tempe 3428 temperature = <95000>;
4148 hyste 3429 hysteresis = <2000>;
4149 type 3430 type = "passive";
4150 }; 3431 };
4151 3432
4152 cpu2_crit: cp !! 3433 cpu2_crit: cpu_crit {
4153 tempe 3434 temperature = <110000>;
4154 hyste 3435 hysteresis = <1000>;
4155 type 3436 type = "critical";
4156 }; 3437 };
4157 }; 3438 };
4158 3439
4159 cooling-maps { 3440 cooling-maps {
4160 map0 { 3441 map0 {
4161 trip 3442 trip = <&cpu2_alert0>;
4162 cooli 3443 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4163 3444 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4164 3445 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4165 3446 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4166 3447 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4167 3448 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4168 }; 3449 };
4169 map1 { 3450 map1 {
4170 trip 3451 trip = <&cpu2_alert1>;
4171 cooli 3452 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4172 3453 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4173 3454 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4174 3455 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4175 3456 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4176 3457 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4177 }; 3458 };
4178 }; 3459 };
4179 }; 3460 };
4180 3461
4181 cpu3_thermal: cpu3-thermal { !! 3462 cpu3-thermal {
4182 polling-delay-passive !! 3463 polling-delay-passive = <0>;
>> 3464 polling-delay = <0>;
4183 3465
4184 thermal-sensors = <&t 3466 thermal-sensors = <&tsens0 4>;
4185 sustainable-power = < <<
4186 3467
4187 trips { 3468 trips {
4188 cpu3_alert0: 3469 cpu3_alert0: trip-point0 {
4189 tempe 3470 temperature = <90000>;
4190 hyste 3471 hysteresis = <2000>;
4191 type 3472 type = "passive";
4192 }; 3473 };
4193 3474
4194 cpu3_alert1: 3475 cpu3_alert1: trip-point1 {
4195 tempe 3476 temperature = <95000>;
4196 hyste 3477 hysteresis = <2000>;
4197 type 3478 type = "passive";
4198 }; 3479 };
4199 3480
4200 cpu3_crit: cp !! 3481 cpu3_crit: cpu_crit {
4201 tempe 3482 temperature = <110000>;
4202 hyste 3483 hysteresis = <1000>;
4203 type 3484 type = "critical";
4204 }; 3485 };
4205 }; 3486 };
4206 3487
4207 cooling-maps { 3488 cooling-maps {
4208 map0 { 3489 map0 {
4209 trip 3490 trip = <&cpu3_alert0>;
4210 cooli 3491 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4211 3492 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4212 3493 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4213 3494 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4214 3495 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4215 3496 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4216 }; 3497 };
4217 map1 { 3498 map1 {
4218 trip 3499 trip = <&cpu3_alert1>;
4219 cooli 3500 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4220 3501 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4221 3502 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4222 3503 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4223 3504 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4224 3505 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4225 }; 3506 };
4226 }; 3507 };
4227 }; 3508 };
4228 3509
4229 cpu4_thermal: cpu4-thermal { !! 3510 cpu4-thermal {
4230 polling-delay-passive !! 3511 polling-delay-passive = <0>;
>> 3512 polling-delay = <0>;
4231 3513
4232 thermal-sensors = <&t 3514 thermal-sensors = <&tsens0 5>;
4233 sustainable-power = < <<
4234 3515
4235 trips { 3516 trips {
4236 cpu4_alert0: 3517 cpu4_alert0: trip-point0 {
4237 tempe 3518 temperature = <90000>;
4238 hyste 3519 hysteresis = <2000>;
4239 type 3520 type = "passive";
4240 }; 3521 };
4241 3522
4242 cpu4_alert1: 3523 cpu4_alert1: trip-point1 {
4243 tempe 3524 temperature = <95000>;
4244 hyste 3525 hysteresis = <2000>;
4245 type 3526 type = "passive";
4246 }; 3527 };
4247 3528
4248 cpu4_crit: cp !! 3529 cpu4_crit: cpu_crit {
4249 tempe 3530 temperature = <110000>;
4250 hyste 3531 hysteresis = <1000>;
4251 type 3532 type = "critical";
4252 }; 3533 };
4253 }; 3534 };
4254 3535
4255 cooling-maps { 3536 cooling-maps {
4256 map0 { 3537 map0 {
4257 trip 3538 trip = <&cpu4_alert0>;
4258 cooli 3539 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4259 3540 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4260 3541 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4261 3542 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4262 3543 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4263 3544 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4264 }; 3545 };
4265 map1 { 3546 map1 {
4266 trip 3547 trip = <&cpu4_alert1>;
4267 cooli 3548 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4268 3549 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4269 3550 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4270 3551 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4271 3552 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4272 3553 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4273 }; 3554 };
4274 }; 3555 };
4275 }; 3556 };
4276 3557
4277 cpu5_thermal: cpu5-thermal { !! 3558 cpu5-thermal {
4278 polling-delay-passive !! 3559 polling-delay-passive = <0>;
>> 3560 polling-delay = <0>;
4279 3561
4280 thermal-sensors = <&t 3562 thermal-sensors = <&tsens0 6>;
4281 sustainable-power = < <<
4282 3563
4283 trips { 3564 trips {
4284 cpu5_alert0: 3565 cpu5_alert0: trip-point0 {
4285 tempe 3566 temperature = <90000>;
4286 hyste 3567 hysteresis = <2000>;
4287 type 3568 type = "passive";
4288 }; 3569 };
4289 3570
4290 cpu5_alert1: 3571 cpu5_alert1: trip-point1 {
4291 tempe 3572 temperature = <95000>;
4292 hyste 3573 hysteresis = <2000>;
4293 type 3574 type = "passive";
4294 }; 3575 };
4295 3576
4296 cpu5_crit: cp !! 3577 cpu5_crit: cpu_crit {
4297 tempe 3578 temperature = <110000>;
4298 hyste 3579 hysteresis = <1000>;
4299 type 3580 type = "critical";
4300 }; 3581 };
4301 }; 3582 };
4302 3583
4303 cooling-maps { 3584 cooling-maps {
4304 map0 { 3585 map0 {
4305 trip 3586 trip = <&cpu5_alert0>;
4306 cooli 3587 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4307 3588 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4308 3589 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4309 3590 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4310 3591 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4311 3592 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4312 }; 3593 };
4313 map1 { 3594 map1 {
4314 trip 3595 trip = <&cpu5_alert1>;
4315 cooli 3596 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4316 3597 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4317 3598 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4318 3599 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4319 3600 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4320 3601 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4321 }; 3602 };
4322 }; 3603 };
4323 }; 3604 };
4324 3605
4325 cpu6_thermal: cpu6-thermal { !! 3606 cpu6-thermal {
4326 polling-delay-passive !! 3607 polling-delay-passive = <0>;
>> 3608 polling-delay = <0>;
4327 3609
4328 thermal-sensors = <&t 3610 thermal-sensors = <&tsens0 9>;
4329 sustainable-power = < <<
4330 3611
4331 trips { 3612 trips {
4332 cpu6_alert0: 3613 cpu6_alert0: trip-point0 {
4333 tempe 3614 temperature = <90000>;
4334 hyste 3615 hysteresis = <2000>;
4335 type 3616 type = "passive";
4336 }; 3617 };
4337 3618
4338 cpu6_alert1: 3619 cpu6_alert1: trip-point1 {
4339 tempe 3620 temperature = <95000>;
4340 hyste 3621 hysteresis = <2000>;
4341 type 3622 type = "passive";
4342 }; 3623 };
4343 3624
4344 cpu6_crit: cp !! 3625 cpu6_crit: cpu_crit {
4345 tempe 3626 temperature = <110000>;
4346 hyste 3627 hysteresis = <1000>;
4347 type 3628 type = "critical";
4348 }; 3629 };
4349 }; 3630 };
4350 3631
4351 cooling-maps { 3632 cooling-maps {
4352 map0 { 3633 map0 {
4353 trip 3634 trip = <&cpu6_alert0>;
4354 cooli 3635 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4355 3636 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4356 }; 3637 };
4357 map1 { 3638 map1 {
4358 trip 3639 trip = <&cpu6_alert1>;
4359 cooli 3640 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4360 3641 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4361 }; 3642 };
4362 }; 3643 };
4363 }; 3644 };
4364 3645
4365 cpu7_thermal: cpu7-thermal { !! 3646 cpu7-thermal {
4366 polling-delay-passive !! 3647 polling-delay-passive = <0>;
>> 3648 polling-delay = <0>;
4367 3649
4368 thermal-sensors = <&t 3650 thermal-sensors = <&tsens0 10>;
4369 sustainable-power = < <<
4370 3651
4371 trips { 3652 trips {
4372 cpu7_alert0: 3653 cpu7_alert0: trip-point0 {
4373 tempe 3654 temperature = <90000>;
4374 hyste 3655 hysteresis = <2000>;
4375 type 3656 type = "passive";
4376 }; 3657 };
4377 3658
4378 cpu7_alert1: 3659 cpu7_alert1: trip-point1 {
4379 tempe 3660 temperature = <95000>;
4380 hyste 3661 hysteresis = <2000>;
4381 type 3662 type = "passive";
4382 }; 3663 };
4383 3664
4384 cpu7_crit: cp !! 3665 cpu7_crit: cpu_crit {
4385 tempe 3666 temperature = <110000>;
4386 hyste 3667 hysteresis = <1000>;
4387 type 3668 type = "critical";
4388 }; 3669 };
4389 }; 3670 };
4390 3671
4391 cooling-maps { 3672 cooling-maps {
4392 map0 { 3673 map0 {
4393 trip 3674 trip = <&cpu7_alert0>;
4394 cooli 3675 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4395 3676 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4396 }; 3677 };
4397 map1 { 3678 map1 {
4398 trip 3679 trip = <&cpu7_alert1>;
4399 cooli 3680 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4400 3681 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4401 }; 3682 };
4402 }; 3683 };
4403 }; 3684 };
4404 3685
4405 cpu8_thermal: cpu8-thermal { !! 3686 cpu8-thermal {
4406 polling-delay-passive !! 3687 polling-delay-passive = <0>;
>> 3688 polling-delay = <0>;
4407 3689
4408 thermal-sensors = <&t 3690 thermal-sensors = <&tsens0 11>;
4409 sustainable-power = < <<
4410 3691
4411 trips { 3692 trips {
4412 cpu8_alert0: 3693 cpu8_alert0: trip-point0 {
4413 tempe 3694 temperature = <90000>;
4414 hyste 3695 hysteresis = <2000>;
4415 type 3696 type = "passive";
4416 }; 3697 };
4417 3698
4418 cpu8_alert1: 3699 cpu8_alert1: trip-point1 {
4419 tempe 3700 temperature = <95000>;
4420 hyste 3701 hysteresis = <2000>;
4421 type 3702 type = "passive";
4422 }; 3703 };
4423 3704
4424 cpu8_crit: cp !! 3705 cpu8_crit: cpu_crit {
4425 tempe 3706 temperature = <110000>;
4426 hyste 3707 hysteresis = <1000>;
4427 type 3708 type = "critical";
4428 }; 3709 };
4429 }; 3710 };
4430 3711
4431 cooling-maps { 3712 cooling-maps {
4432 map0 { 3713 map0 {
4433 trip 3714 trip = <&cpu8_alert0>;
4434 cooli 3715 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4435 3716 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4436 }; 3717 };
4437 map1 { 3718 map1 {
4438 trip 3719 trip = <&cpu8_alert1>;
4439 cooli 3720 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4440 3721 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4441 }; 3722 };
4442 }; 3723 };
4443 }; 3724 };
4444 3725
4445 cpu9_thermal: cpu9-thermal { !! 3726 cpu9-thermal {
4446 polling-delay-passive !! 3727 polling-delay-passive = <0>;
>> 3728 polling-delay = <0>;
4447 3729
4448 thermal-sensors = <&t 3730 thermal-sensors = <&tsens0 12>;
4449 sustainable-power = < <<
4450 3731
4451 trips { 3732 trips {
4452 cpu9_alert0: 3733 cpu9_alert0: trip-point0 {
4453 tempe 3734 temperature = <90000>;
4454 hyste 3735 hysteresis = <2000>;
4455 type 3736 type = "passive";
4456 }; 3737 };
4457 3738
4458 cpu9_alert1: 3739 cpu9_alert1: trip-point1 {
4459 tempe 3740 temperature = <95000>;
4460 hyste 3741 hysteresis = <2000>;
4461 type 3742 type = "passive";
4462 }; 3743 };
4463 3744
4464 cpu9_crit: cp !! 3745 cpu9_crit: cpu_crit {
4465 tempe 3746 temperature = <110000>;
4466 hyste 3747 hysteresis = <1000>;
4467 type 3748 type = "critical";
4468 }; 3749 };
4469 }; 3750 };
4470 3751
4471 cooling-maps { 3752 cooling-maps {
4472 map0 { 3753 map0 {
4473 trip 3754 trip = <&cpu9_alert0>;
4474 cooli 3755 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4475 3756 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4476 }; 3757 };
4477 map1 { 3758 map1 {
4478 trip 3759 trip = <&cpu9_alert1>;
4479 cooli 3760 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4480 3761 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4481 }; 3762 };
4482 }; 3763 };
4483 }; 3764 };
4484 3765
4485 aoss0-thermal { 3766 aoss0-thermal {
4486 polling-delay-passive !! 3767 polling-delay-passive = <0>;
>> 3768 polling-delay = <0>;
4487 3769
4488 thermal-sensors = <&t 3770 thermal-sensors = <&tsens0 0>;
4489 3771
4490 trips { 3772 trips {
4491 aoss0_alert0: 3773 aoss0_alert0: trip-point0 {
4492 tempe 3774 temperature = <90000>;
4493 hyste 3775 hysteresis = <2000>;
4494 type 3776 type = "hot";
4495 }; 3777 };
4496 3778
4497 aoss0_crit: a !! 3779 aoss0_crit: aoss0_crit {
4498 tempe 3780 temperature = <110000>;
4499 hyste 3781 hysteresis = <2000>;
4500 type 3782 type = "critical";
4501 }; 3783 };
4502 }; 3784 };
4503 }; 3785 };
4504 3786
4505 cpuss0-thermal { 3787 cpuss0-thermal {
4506 polling-delay-passive !! 3788 polling-delay-passive = <0>;
>> 3789 polling-delay = <0>;
4507 3790
4508 thermal-sensors = <&t 3791 thermal-sensors = <&tsens0 7>;
4509 3792
4510 trips { 3793 trips {
4511 cpuss0_alert0 3794 cpuss0_alert0: trip-point0 {
4512 tempe 3795 temperature = <90000>;
4513 hyste 3796 hysteresis = <2000>;
4514 type 3797 type = "hot";
4515 }; 3798 };
4516 cpuss0_crit: !! 3799 cpuss0_crit: cluster0_crit {
4517 tempe 3800 temperature = <110000>;
4518 hyste 3801 hysteresis = <2000>;
4519 type 3802 type = "critical";
4520 }; 3803 };
4521 }; 3804 };
4522 }; 3805 };
4523 3806
4524 cpuss1-thermal { 3807 cpuss1-thermal {
4525 polling-delay-passive !! 3808 polling-delay-passive = <0>;
>> 3809 polling-delay = <0>;
4526 3810
4527 thermal-sensors = <&t 3811 thermal-sensors = <&tsens0 8>;
4528 3812
4529 trips { 3813 trips {
4530 cpuss1_alert0 3814 cpuss1_alert0: trip-point0 {
4531 tempe 3815 temperature = <90000>;
4532 hyste 3816 hysteresis = <2000>;
4533 type 3817 type = "hot";
4534 }; 3818 };
4535 cpuss1_crit: !! 3819 cpuss1_crit: cluster0_crit {
4536 tempe 3820 temperature = <110000>;
4537 hyste 3821 hysteresis = <2000>;
4538 type 3822 type = "critical";
4539 }; 3823 };
4540 }; 3824 };
4541 }; 3825 };
4542 3826
4543 gpuss0-thermal { 3827 gpuss0-thermal {
4544 polling-delay-passive !! 3828 polling-delay-passive = <0>;
>> 3829 polling-delay = <0>;
4545 3830
4546 thermal-sensors = <&t 3831 thermal-sensors = <&tsens0 13>;
4547 3832
4548 trips { 3833 trips {
4549 gpuss0_alert0 3834 gpuss0_alert0: trip-point0 {
4550 tempe !! 3835 temperature = <90000>;
4551 hyste 3836 hysteresis = <2000>;
4552 type !! 3837 type = "hot";
4553 }; 3838 };
4554 3839
4555 gpuss0_crit: !! 3840 gpuss0_crit: gpuss0_crit {
4556 tempe 3841 temperature = <110000>;
4557 hyste 3842 hysteresis = <2000>;
4558 type 3843 type = "critical";
4559 }; 3844 };
4560 }; 3845 };
4561 <<
4562 cooling-maps { <<
4563 map0 { <<
4564 trip <<
4565 cooli <<
4566 }; <<
4567 }; <<
4568 }; 3846 };
4569 3847
4570 gpuss1-thermal { 3848 gpuss1-thermal {
4571 polling-delay-passive !! 3849 polling-delay-passive = <0>;
>> 3850 polling-delay = <0>;
4572 3851
4573 thermal-sensors = <&t 3852 thermal-sensors = <&tsens0 14>;
4574 3853
4575 trips { 3854 trips {
4576 gpuss1_alert0 3855 gpuss1_alert0: trip-point0 {
4577 tempe !! 3856 temperature = <90000>;
4578 hyste 3857 hysteresis = <2000>;
4579 type !! 3858 type = "hot";
4580 }; 3859 };
4581 3860
4582 gpuss1_crit: !! 3861 gpuss1_crit: gpuss1_crit {
4583 tempe 3862 temperature = <110000>;
4584 hyste 3863 hysteresis = <2000>;
4585 type 3864 type = "critical";
4586 }; 3865 };
4587 }; 3866 };
4588 <<
4589 cooling-maps { <<
4590 map0 { <<
4591 trip <<
4592 cooli <<
4593 }; <<
4594 }; <<
4595 }; 3867 };
4596 3868
4597 aoss1-thermal { 3869 aoss1-thermal {
4598 polling-delay-passive !! 3870 polling-delay-passive = <0>;
>> 3871 polling-delay = <0>;
4599 3872
4600 thermal-sensors = <&t 3873 thermal-sensors = <&tsens1 0>;
4601 3874
4602 trips { 3875 trips {
4603 aoss1_alert0: 3876 aoss1_alert0: trip-point0 {
4604 tempe 3877 temperature = <90000>;
4605 hyste 3878 hysteresis = <2000>;
4606 type 3879 type = "hot";
4607 }; 3880 };
4608 3881
4609 aoss1_crit: a !! 3882 aoss1_crit: aoss1_crit {
4610 tempe 3883 temperature = <110000>;
4611 hyste 3884 hysteresis = <2000>;
4612 type 3885 type = "critical";
4613 }; 3886 };
4614 }; 3887 };
4615 }; 3888 };
4616 3889
4617 cwlan-thermal { 3890 cwlan-thermal {
4618 polling-delay-passive !! 3891 polling-delay-passive = <0>;
>> 3892 polling-delay = <0>;
4619 3893
4620 thermal-sensors = <&t 3894 thermal-sensors = <&tsens1 1>;
4621 3895
4622 trips { 3896 trips {
4623 cwlan_alert0: 3897 cwlan_alert0: trip-point0 {
4624 tempe 3898 temperature = <90000>;
4625 hyste 3899 hysteresis = <2000>;
4626 type 3900 type = "hot";
4627 }; 3901 };
4628 3902
4629 cwlan_crit: c !! 3903 cwlan_crit: cwlan_crit {
4630 tempe 3904 temperature = <110000>;
4631 hyste 3905 hysteresis = <2000>;
4632 type 3906 type = "critical";
4633 }; 3907 };
4634 }; 3908 };
4635 }; 3909 };
4636 3910
4637 audio-thermal { 3911 audio-thermal {
4638 polling-delay-passive !! 3912 polling-delay-passive = <0>;
>> 3913 polling-delay = <0>;
4639 3914
4640 thermal-sensors = <&t 3915 thermal-sensors = <&tsens1 2>;
4641 3916
4642 trips { 3917 trips {
4643 audio_alert0: 3918 audio_alert0: trip-point0 {
4644 tempe 3919 temperature = <90000>;
4645 hyste 3920 hysteresis = <2000>;
4646 type 3921 type = "hot";
4647 }; 3922 };
4648 3923
4649 audio_crit: a !! 3924 audio_crit: audio_crit {
4650 tempe 3925 temperature = <110000>;
4651 hyste 3926 hysteresis = <2000>;
4652 type 3927 type = "critical";
4653 }; 3928 };
4654 }; 3929 };
4655 }; 3930 };
4656 3931
4657 ddr-thermal { 3932 ddr-thermal {
4658 polling-delay-passive !! 3933 polling-delay-passive = <0>;
>> 3934 polling-delay = <0>;
4659 3935
4660 thermal-sensors = <&t 3936 thermal-sensors = <&tsens1 3>;
4661 3937
4662 trips { 3938 trips {
4663 ddr_alert0: t 3939 ddr_alert0: trip-point0 {
4664 tempe 3940 temperature = <90000>;
4665 hyste 3941 hysteresis = <2000>;
4666 type 3942 type = "hot";
4667 }; 3943 };
4668 3944
4669 ddr_crit: ddr !! 3945 ddr_crit: ddr_crit {
4670 tempe 3946 temperature = <110000>;
4671 hyste 3947 hysteresis = <2000>;
4672 type 3948 type = "critical";
4673 }; 3949 };
4674 }; 3950 };
4675 }; 3951 };
4676 3952
4677 q6-hvx-thermal { 3953 q6-hvx-thermal {
4678 polling-delay-passive !! 3954 polling-delay-passive = <0>;
>> 3955 polling-delay = <0>;
4679 3956
4680 thermal-sensors = <&t 3957 thermal-sensors = <&tsens1 4>;
4681 3958
4682 trips { 3959 trips {
4683 q6_hvx_alert0 3960 q6_hvx_alert0: trip-point0 {
4684 tempe 3961 temperature = <90000>;
4685 hyste 3962 hysteresis = <2000>;
4686 type 3963 type = "hot";
4687 }; 3964 };
4688 3965
4689 q6_hvx_crit: !! 3966 q6_hvx_crit: q6_hvx_crit {
4690 tempe 3967 temperature = <110000>;
4691 hyste 3968 hysteresis = <2000>;
4692 type 3969 type = "critical";
4693 }; 3970 };
4694 }; 3971 };
4695 }; 3972 };
4696 3973
4697 camera-thermal { 3974 camera-thermal {
4698 polling-delay-passive !! 3975 polling-delay-passive = <0>;
>> 3976 polling-delay = <0>;
4699 3977
4700 thermal-sensors = <&t 3978 thermal-sensors = <&tsens1 5>;
4701 3979
4702 trips { 3980 trips {
4703 camera_alert0 3981 camera_alert0: trip-point0 {
4704 tempe 3982 temperature = <90000>;
4705 hyste 3983 hysteresis = <2000>;
4706 type 3984 type = "hot";
4707 }; 3985 };
4708 3986
4709 camera_crit: !! 3987 camera_crit: camera_crit {
4710 tempe 3988 temperature = <110000>;
4711 hyste 3989 hysteresis = <2000>;
4712 type 3990 type = "critical";
4713 }; 3991 };
4714 }; 3992 };
4715 }; 3993 };
4716 3994
4717 mdm-core-thermal { 3995 mdm-core-thermal {
4718 polling-delay-passive !! 3996 polling-delay-passive = <0>;
>> 3997 polling-delay = <0>;
4719 3998
4720 thermal-sensors = <&t 3999 thermal-sensors = <&tsens1 6>;
4721 4000
4722 trips { 4001 trips {
4723 mdm_alert0: t 4002 mdm_alert0: trip-point0 {
4724 tempe 4003 temperature = <90000>;
4725 hyste 4004 hysteresis = <2000>;
4726 type 4005 type = "hot";
4727 }; 4006 };
4728 4007
4729 mdm_crit: mdm !! 4008 mdm_crit: mdm_crit {
4730 tempe 4009 temperature = <110000>;
4731 hyste 4010 hysteresis = <2000>;
4732 type 4011 type = "critical";
4733 }; 4012 };
4734 }; 4013 };
4735 }; 4014 };
4736 4015
4737 mdm-dsp-thermal { 4016 mdm-dsp-thermal {
4738 polling-delay-passive !! 4017 polling-delay-passive = <0>;
>> 4018 polling-delay = <0>;
4739 4019
4740 thermal-sensors = <&t 4020 thermal-sensors = <&tsens1 7>;
4741 4021
4742 trips { 4022 trips {
4743 mdm_dsp_alert 4023 mdm_dsp_alert0: trip-point0 {
4744 tempe 4024 temperature = <90000>;
4745 hyste 4025 hysteresis = <2000>;
4746 type 4026 type = "hot";
4747 }; 4027 };
4748 4028
4749 mdm_dsp_crit: !! 4029 mdm_dsp_crit: mdm_dsp_crit {
4750 tempe 4030 temperature = <110000>;
4751 hyste 4031 hysteresis = <2000>;
4752 type 4032 type = "critical";
4753 }; 4033 };
4754 }; 4034 };
4755 }; 4035 };
4756 4036
4757 npu-thermal { 4037 npu-thermal {
4758 polling-delay-passive !! 4038 polling-delay-passive = <0>;
>> 4039 polling-delay = <0>;
4759 4040
4760 thermal-sensors = <&t 4041 thermal-sensors = <&tsens1 8>;
4761 4042
4762 trips { 4043 trips {
4763 npu_alert0: t 4044 npu_alert0: trip-point0 {
4764 tempe 4045 temperature = <90000>;
4765 hyste 4046 hysteresis = <2000>;
4766 type 4047 type = "hot";
4767 }; 4048 };
4768 4049
4769 npu_crit: npu !! 4050 npu_crit: npu_crit {
4770 tempe 4051 temperature = <110000>;
4771 hyste 4052 hysteresis = <2000>;
4772 type 4053 type = "critical";
4773 }; 4054 };
4774 }; 4055 };
4775 }; 4056 };
4776 4057
4777 video-thermal { 4058 video-thermal {
4778 polling-delay-passive !! 4059 polling-delay-passive = <0>;
>> 4060 polling-delay = <0>;
4779 4061
4780 thermal-sensors = <&t 4062 thermal-sensors = <&tsens1 9>;
4781 4063
4782 trips { 4064 trips {
4783 video_alert0: 4065 video_alert0: trip-point0 {
4784 tempe 4066 temperature = <90000>;
4785 hyste 4067 hysteresis = <2000>;
4786 type 4068 type = "hot";
4787 }; 4069 };
4788 4070
4789 video_crit: v !! 4071 video_crit: video_crit {
4790 tempe 4072 temperature = <110000>;
4791 hyste 4073 hysteresis = <2000>;
4792 type 4074 type = "critical";
4793 }; 4075 };
4794 }; 4076 };
4795 }; 4077 };
4796 }; 4078 };
4797 4079
4798 timer { 4080 timer {
4799 compatible = "arm,armv8-timer 4081 compatible = "arm,armv8-timer";
4800 interrupts = <GIC_PPI 1 IRQ_T 4082 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
4801 <GIC_PPI 2 IRQ_T 4083 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
4802 <GIC_PPI 3 IRQ_T 4084 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
4803 <GIC_PPI 0 IRQ_T 4085 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
4804 }; 4086 };
4805 }; 4087 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.