1 // SPDX-License-Identifier: BSD-3-Clause 1 // SPDX-License-Identifier: BSD-3-Clause
2 /* 2 /*
3 * SC7180 SoC device tree source 3 * SC7180 SoC device tree source
4 * 4 *
5 * Copyright (c) 2019-2020, The Linux Foundati 5 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
6 */ 6 */
7 7
8 #include <dt-bindings/clock/qcom,dispcc-sc7180 8 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
9 #include <dt-bindings/clock/qcom,gcc-sc7180.h> 9 #include <dt-bindings/clock/qcom,gcc-sc7180.h>
10 #include <dt-bindings/clock/qcom,gpucc-sc7180. 10 #include <dt-bindings/clock/qcom,gpucc-sc7180.h>
11 #include <dt-bindings/clock/qcom,lpasscorecc-s 11 #include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h>
12 #include <dt-bindings/clock/qcom,rpmh.h> 12 #include <dt-bindings/clock/qcom,rpmh.h>
13 #include <dt-bindings/clock/qcom,videocc-sc718 13 #include <dt-bindings/clock/qcom,videocc-sc7180.h>
14 #include <dt-bindings/firmware/qcom,scm.h> <<
15 #include <dt-bindings/interconnect/qcom,icc.h> <<
16 #include <dt-bindings/interconnect/qcom,osm-l3 14 #include <dt-bindings/interconnect/qcom,osm-l3.h>
17 #include <dt-bindings/interconnect/qcom,sc7180 15 #include <dt-bindings/interconnect/qcom,sc7180.h>
18 #include <dt-bindings/interrupt-controller/arm 16 #include <dt-bindings/interrupt-controller/arm-gic.h>
19 #include <dt-bindings/phy/phy-qcom-qmp.h> <<
20 #include <dt-bindings/phy/phy-qcom-qusb2.h> 17 #include <dt-bindings/phy/phy-qcom-qusb2.h>
21 #include <dt-bindings/power/qcom-rpmpd.h> 18 #include <dt-bindings/power/qcom-rpmpd.h>
22 #include <dt-bindings/reset/qcom,sdm845-aoss.h 19 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
23 #include <dt-bindings/reset/qcom,sdm845-pdc.h> 20 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
24 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 21 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
25 #include <dt-bindings/soc/qcom,apr.h> <<
26 #include <dt-bindings/sound/qcom,q6afe.h> <<
27 #include <dt-bindings/thermal/thermal.h> 22 #include <dt-bindings/thermal/thermal.h>
28 23
29 / { 24 / {
30 interrupt-parent = <&intc>; 25 interrupt-parent = <&intc>;
31 26
32 #address-cells = <2>; 27 #address-cells = <2>;
33 #size-cells = <2>; 28 #size-cells = <2>;
34 29
>> 30 chosen { };
>> 31
35 aliases { 32 aliases {
36 mmc1 = &sdhc_1; 33 mmc1 = &sdhc_1;
37 mmc2 = &sdhc_2; 34 mmc2 = &sdhc_2;
38 i2c0 = &i2c0; 35 i2c0 = &i2c0;
39 i2c1 = &i2c1; 36 i2c1 = &i2c1;
40 i2c2 = &i2c2; 37 i2c2 = &i2c2;
41 i2c3 = &i2c3; 38 i2c3 = &i2c3;
42 i2c4 = &i2c4; 39 i2c4 = &i2c4;
43 i2c5 = &i2c5; 40 i2c5 = &i2c5;
44 i2c6 = &i2c6; 41 i2c6 = &i2c6;
45 i2c7 = &i2c7; 42 i2c7 = &i2c7;
46 i2c8 = &i2c8; 43 i2c8 = &i2c8;
47 i2c9 = &i2c9; 44 i2c9 = &i2c9;
48 i2c10 = &i2c10; 45 i2c10 = &i2c10;
49 i2c11 = &i2c11; 46 i2c11 = &i2c11;
50 spi0 = &spi0; 47 spi0 = &spi0;
51 spi1 = &spi1; 48 spi1 = &spi1;
52 spi3 = &spi3; 49 spi3 = &spi3;
53 spi5 = &spi5; 50 spi5 = &spi5;
54 spi6 = &spi6; 51 spi6 = &spi6;
55 spi8 = &spi8; 52 spi8 = &spi8;
56 spi10 = &spi10; 53 spi10 = &spi10;
57 spi11 = &spi11; 54 spi11 = &spi11;
58 }; 55 };
59 56
60 chosen { }; <<
61 <<
62 clocks { 57 clocks {
63 xo_board: xo-board { 58 xo_board: xo-board {
64 compatible = "fixed-cl 59 compatible = "fixed-clock";
65 clock-frequency = <384 60 clock-frequency = <38400000>;
66 #clock-cells = <0>; 61 #clock-cells = <0>;
67 }; 62 };
68 63
69 sleep_clk: sleep-clk { 64 sleep_clk: sleep-clk {
70 compatible = "fixed-cl 65 compatible = "fixed-clock";
71 clock-frequency = <327 66 clock-frequency = <32764>;
72 #clock-cells = <0>; 67 #clock-cells = <0>;
73 }; 68 };
74 }; 69 };
75 70
>> 71 reserved_memory: reserved-memory {
>> 72 #address-cells = <2>;
>> 73 #size-cells = <2>;
>> 74 ranges;
>> 75
>> 76 hyp_mem: memory@80000000 {
>> 77 reg = <0x0 0x80000000 0x0 0x600000>;
>> 78 no-map;
>> 79 };
>> 80
>> 81 xbl_mem: memory@80600000 {
>> 82 reg = <0x0 0x80600000 0x0 0x200000>;
>> 83 no-map;
>> 84 };
>> 85
>> 86 aop_mem: memory@80800000 {
>> 87 reg = <0x0 0x80800000 0x0 0x20000>;
>> 88 no-map;
>> 89 };
>> 90
>> 91 aop_cmd_db_mem: memory@80820000 {
>> 92 reg = <0x0 0x80820000 0x0 0x20000>;
>> 93 compatible = "qcom,cmd-db";
>> 94 no-map;
>> 95 };
>> 96
>> 97 sec_apps_mem: memory@808ff000 {
>> 98 reg = <0x0 0x808ff000 0x0 0x1000>;
>> 99 no-map;
>> 100 };
>> 101
>> 102 smem_mem: memory@80900000 {
>> 103 reg = <0x0 0x80900000 0x0 0x200000>;
>> 104 no-map;
>> 105 };
>> 106
>> 107 tz_mem: memory@80b00000 {
>> 108 reg = <0x0 0x80b00000 0x0 0x3900000>;
>> 109 no-map;
>> 110 };
>> 111
>> 112 ipa_fw_mem: memory@8b700000 {
>> 113 reg = <0 0x8b700000 0 0x10000>;
>> 114 no-map;
>> 115 };
>> 116
>> 117 rmtfs_mem: memory@94600000 {
>> 118 compatible = "qcom,rmtfs-mem";
>> 119 reg = <0x0 0x94600000 0x0 0x200000>;
>> 120 no-map;
>> 121
>> 122 qcom,client-id = <1>;
>> 123 qcom,vmid = <15>;
>> 124 };
>> 125 };
>> 126
76 cpus { 127 cpus {
77 #address-cells = <2>; 128 #address-cells = <2>;
78 #size-cells = <0>; 129 #size-cells = <0>;
79 130
80 CPU0: cpu@0 { 131 CPU0: cpu@0 {
81 device_type = "cpu"; 132 device_type = "cpu";
82 compatible = "qcom,kry 133 compatible = "qcom,kryo468";
83 reg = <0x0 0x0>; 134 reg = <0x0 0x0>;
84 clocks = <&cpufreq_hw <<
85 enable-method = "psci" 135 enable-method = "psci";
86 power-domains = <&CPU_ !! 136 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
87 power-domain-names = " !! 137 &LITTLE_CPU_SLEEP_1
>> 138 &CLUSTER_SLEEP_0>;
88 capacity-dmips-mhz = < 139 capacity-dmips-mhz = <415>;
89 dynamic-power-coeffici 140 dynamic-power-coefficient = <137>;
90 operating-points-v2 = 141 operating-points-v2 = <&cpu0_opp_table>;
91 interconnects = <&gem_ 142 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
92 <&osm_ 143 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
93 next-level-cache = <&L 144 next-level-cache = <&L2_0>;
94 #cooling-cells = <2>; 145 #cooling-cells = <2>;
95 qcom,freq-domain = <&c 146 qcom,freq-domain = <&cpufreq_hw 0>;
96 L2_0: l2-cache { 147 L2_0: l2-cache {
97 compatible = " 148 compatible = "cache";
98 cache-level = <<
99 cache-unified; <<
100 next-level-cac 149 next-level-cache = <&L3_0>;
101 L3_0: l3-cache 150 L3_0: l3-cache {
102 compat 151 compatible = "cache";
103 cache- <<
104 cache- <<
105 }; 152 };
106 }; 153 };
107 }; 154 };
108 155
109 CPU1: cpu@100 { 156 CPU1: cpu@100 {
110 device_type = "cpu"; 157 device_type = "cpu";
111 compatible = "qcom,kry 158 compatible = "qcom,kryo468";
112 reg = <0x0 0x100>; 159 reg = <0x0 0x100>;
113 clocks = <&cpufreq_hw <<
114 enable-method = "psci" 160 enable-method = "psci";
115 power-domains = <&CPU_ !! 161 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
116 power-domain-names = " !! 162 &LITTLE_CPU_SLEEP_1
>> 163 &CLUSTER_SLEEP_0>;
117 capacity-dmips-mhz = < 164 capacity-dmips-mhz = <415>;
118 dynamic-power-coeffici 165 dynamic-power-coefficient = <137>;
119 next-level-cache = <&L 166 next-level-cache = <&L2_100>;
120 operating-points-v2 = 167 operating-points-v2 = <&cpu0_opp_table>;
121 interconnects = <&gem_ 168 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
122 <&osm_ 169 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
123 #cooling-cells = <2>; 170 #cooling-cells = <2>;
124 qcom,freq-domain = <&c 171 qcom,freq-domain = <&cpufreq_hw 0>;
125 L2_100: l2-cache { 172 L2_100: l2-cache {
126 compatible = " 173 compatible = "cache";
127 cache-level = <<
128 cache-unified; <<
129 next-level-cac 174 next-level-cache = <&L3_0>;
130 }; 175 };
131 }; 176 };
132 177
133 CPU2: cpu@200 { 178 CPU2: cpu@200 {
134 device_type = "cpu"; 179 device_type = "cpu";
135 compatible = "qcom,kry 180 compatible = "qcom,kryo468";
136 reg = <0x0 0x200>; 181 reg = <0x0 0x200>;
137 clocks = <&cpufreq_hw <<
138 enable-method = "psci" 182 enable-method = "psci";
139 power-domains = <&CPU_ !! 183 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
140 power-domain-names = " !! 184 &LITTLE_CPU_SLEEP_1
>> 185 &CLUSTER_SLEEP_0>;
141 capacity-dmips-mhz = < 186 capacity-dmips-mhz = <415>;
142 dynamic-power-coeffici 187 dynamic-power-coefficient = <137>;
143 next-level-cache = <&L 188 next-level-cache = <&L2_200>;
144 operating-points-v2 = 189 operating-points-v2 = <&cpu0_opp_table>;
145 interconnects = <&gem_ 190 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
146 <&osm_ 191 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
147 #cooling-cells = <2>; 192 #cooling-cells = <2>;
148 qcom,freq-domain = <&c 193 qcom,freq-domain = <&cpufreq_hw 0>;
149 L2_200: l2-cache { 194 L2_200: l2-cache {
150 compatible = " 195 compatible = "cache";
151 cache-level = <<
152 cache-unified; <<
153 next-level-cac 196 next-level-cache = <&L3_0>;
154 }; 197 };
155 }; 198 };
156 199
157 CPU3: cpu@300 { 200 CPU3: cpu@300 {
158 device_type = "cpu"; 201 device_type = "cpu";
159 compatible = "qcom,kry 202 compatible = "qcom,kryo468";
160 reg = <0x0 0x300>; 203 reg = <0x0 0x300>;
161 clocks = <&cpufreq_hw <<
162 enable-method = "psci" 204 enable-method = "psci";
163 power-domains = <&CPU_ !! 205 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
164 power-domain-names = " !! 206 &LITTLE_CPU_SLEEP_1
>> 207 &CLUSTER_SLEEP_0>;
165 capacity-dmips-mhz = < 208 capacity-dmips-mhz = <415>;
166 dynamic-power-coeffici 209 dynamic-power-coefficient = <137>;
167 next-level-cache = <&L 210 next-level-cache = <&L2_300>;
168 operating-points-v2 = 211 operating-points-v2 = <&cpu0_opp_table>;
169 interconnects = <&gem_ 212 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
170 <&osm_ 213 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
171 #cooling-cells = <2>; 214 #cooling-cells = <2>;
172 qcom,freq-domain = <&c 215 qcom,freq-domain = <&cpufreq_hw 0>;
173 L2_300: l2-cache { 216 L2_300: l2-cache {
174 compatible = " 217 compatible = "cache";
175 cache-level = <<
176 cache-unified; <<
177 next-level-cac 218 next-level-cache = <&L3_0>;
178 }; 219 };
179 }; 220 };
180 221
181 CPU4: cpu@400 { 222 CPU4: cpu@400 {
182 device_type = "cpu"; 223 device_type = "cpu";
183 compatible = "qcom,kry 224 compatible = "qcom,kryo468";
184 reg = <0x0 0x400>; 225 reg = <0x0 0x400>;
185 clocks = <&cpufreq_hw <<
186 enable-method = "psci" 226 enable-method = "psci";
187 power-domains = <&CPU_ !! 227 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
188 power-domain-names = " !! 228 &LITTLE_CPU_SLEEP_1
>> 229 &CLUSTER_SLEEP_0>;
189 capacity-dmips-mhz = < 230 capacity-dmips-mhz = <415>;
190 dynamic-power-coeffici 231 dynamic-power-coefficient = <137>;
191 next-level-cache = <&L 232 next-level-cache = <&L2_400>;
192 operating-points-v2 = 233 operating-points-v2 = <&cpu0_opp_table>;
193 interconnects = <&gem_ 234 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
194 <&osm_ 235 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
195 #cooling-cells = <2>; 236 #cooling-cells = <2>;
196 qcom,freq-domain = <&c 237 qcom,freq-domain = <&cpufreq_hw 0>;
197 L2_400: l2-cache { 238 L2_400: l2-cache {
198 compatible = " 239 compatible = "cache";
199 cache-level = <<
200 cache-unified; <<
201 next-level-cac 240 next-level-cache = <&L3_0>;
202 }; 241 };
203 }; 242 };
204 243
205 CPU5: cpu@500 { 244 CPU5: cpu@500 {
206 device_type = "cpu"; 245 device_type = "cpu";
207 compatible = "qcom,kry 246 compatible = "qcom,kryo468";
208 reg = <0x0 0x500>; 247 reg = <0x0 0x500>;
209 clocks = <&cpufreq_hw <<
210 enable-method = "psci" 248 enable-method = "psci";
211 power-domains = <&CPU_ !! 249 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
212 power-domain-names = " !! 250 &LITTLE_CPU_SLEEP_1
>> 251 &CLUSTER_SLEEP_0>;
213 capacity-dmips-mhz = < 252 capacity-dmips-mhz = <415>;
214 dynamic-power-coeffici 253 dynamic-power-coefficient = <137>;
215 next-level-cache = <&L 254 next-level-cache = <&L2_500>;
216 operating-points-v2 = 255 operating-points-v2 = <&cpu0_opp_table>;
217 interconnects = <&gem_ 256 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
218 <&osm_ 257 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
219 #cooling-cells = <2>; 258 #cooling-cells = <2>;
220 qcom,freq-domain = <&c 259 qcom,freq-domain = <&cpufreq_hw 0>;
221 L2_500: l2-cache { 260 L2_500: l2-cache {
222 compatible = " 261 compatible = "cache";
223 cache-level = <<
224 cache-unified; <<
225 next-level-cac 262 next-level-cache = <&L3_0>;
226 }; 263 };
227 }; 264 };
228 265
229 CPU6: cpu@600 { 266 CPU6: cpu@600 {
230 device_type = "cpu"; 267 device_type = "cpu";
231 compatible = "qcom,kry 268 compatible = "qcom,kryo468";
232 reg = <0x0 0x600>; 269 reg = <0x0 0x600>;
233 clocks = <&cpufreq_hw <<
234 enable-method = "psci" 270 enable-method = "psci";
235 power-domains = <&CPU_ !! 271 cpu-idle-states = <&BIG_CPU_SLEEP_0
236 power-domain-names = " !! 272 &BIG_CPU_SLEEP_1
>> 273 &CLUSTER_SLEEP_0>;
237 capacity-dmips-mhz = < 274 capacity-dmips-mhz = <1024>;
238 dynamic-power-coeffici 275 dynamic-power-coefficient = <480>;
239 next-level-cache = <&L 276 next-level-cache = <&L2_600>;
240 operating-points-v2 = 277 operating-points-v2 = <&cpu6_opp_table>;
241 interconnects = <&gem_ 278 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
242 <&osm_ 279 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
243 #cooling-cells = <2>; 280 #cooling-cells = <2>;
244 qcom,freq-domain = <&c 281 qcom,freq-domain = <&cpufreq_hw 1>;
245 L2_600: l2-cache { 282 L2_600: l2-cache {
246 compatible = " 283 compatible = "cache";
247 cache-level = <<
248 cache-unified; <<
249 next-level-cac 284 next-level-cache = <&L3_0>;
250 }; 285 };
251 }; 286 };
252 287
253 CPU7: cpu@700 { 288 CPU7: cpu@700 {
254 device_type = "cpu"; 289 device_type = "cpu";
255 compatible = "qcom,kry 290 compatible = "qcom,kryo468";
256 reg = <0x0 0x700>; 291 reg = <0x0 0x700>;
257 clocks = <&cpufreq_hw <<
258 enable-method = "psci" 292 enable-method = "psci";
259 power-domains = <&CPU_ !! 293 cpu-idle-states = <&BIG_CPU_SLEEP_0
260 power-domain-names = " !! 294 &BIG_CPU_SLEEP_1
>> 295 &CLUSTER_SLEEP_0>;
261 capacity-dmips-mhz = < 296 capacity-dmips-mhz = <1024>;
262 dynamic-power-coeffici 297 dynamic-power-coefficient = <480>;
263 next-level-cache = <&L 298 next-level-cache = <&L2_700>;
264 operating-points-v2 = 299 operating-points-v2 = <&cpu6_opp_table>;
265 interconnects = <&gem_ 300 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
266 <&osm_ 301 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
267 #cooling-cells = <2>; 302 #cooling-cells = <2>;
268 qcom,freq-domain = <&c 303 qcom,freq-domain = <&cpufreq_hw 1>;
269 L2_700: l2-cache { 304 L2_700: l2-cache {
270 compatible = " 305 compatible = "cache";
271 cache-level = <<
272 cache-unified; <<
273 next-level-cac 306 next-level-cache = <&L3_0>;
274 }; 307 };
275 }; 308 };
276 309
277 cpu-map { 310 cpu-map {
278 cluster0 { 311 cluster0 {
279 core0 { 312 core0 {
280 cpu = 313 cpu = <&CPU0>;
281 }; 314 };
282 315
283 core1 { 316 core1 {
284 cpu = 317 cpu = <&CPU1>;
285 }; 318 };
286 319
287 core2 { 320 core2 {
288 cpu = 321 cpu = <&CPU2>;
289 }; 322 };
290 323
291 core3 { 324 core3 {
292 cpu = 325 cpu = <&CPU3>;
293 }; 326 };
294 327
295 core4 { 328 core4 {
296 cpu = 329 cpu = <&CPU4>;
297 }; 330 };
298 331
299 core5 { 332 core5 {
300 cpu = 333 cpu = <&CPU5>;
301 }; 334 };
302 335
303 core6 { 336 core6 {
304 cpu = 337 cpu = <&CPU6>;
305 }; 338 };
306 339
307 core7 { 340 core7 {
308 cpu = 341 cpu = <&CPU7>;
309 }; 342 };
310 }; 343 };
311 }; 344 };
312 345
313 idle_states: idle-states { !! 346 idle-states {
314 entry-method = "psci"; 347 entry-method = "psci";
315 348
316 LITTLE_CPU_SLEEP_0: cp 349 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
317 compatible = " 350 compatible = "arm,idle-state";
318 idle-state-nam 351 idle-state-name = "little-power-down";
319 arm,psci-suspe 352 arm,psci-suspend-param = <0x40000003>;
320 entry-latency- 353 entry-latency-us = <549>;
321 exit-latency-u 354 exit-latency-us = <901>;
322 min-residency- 355 min-residency-us = <1774>;
323 local-timer-st 356 local-timer-stop;
324 }; 357 };
325 358
326 LITTLE_CPU_SLEEP_1: cp 359 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
327 compatible = " 360 compatible = "arm,idle-state";
328 idle-state-nam 361 idle-state-name = "little-rail-power-down";
329 arm,psci-suspe 362 arm,psci-suspend-param = <0x40000004>;
330 entry-latency- 363 entry-latency-us = <702>;
331 exit-latency-u 364 exit-latency-us = <915>;
332 min-residency- 365 min-residency-us = <4001>;
333 local-timer-st 366 local-timer-stop;
334 }; 367 };
335 368
336 BIG_CPU_SLEEP_0: cpu-s 369 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
337 compatible = " 370 compatible = "arm,idle-state";
338 idle-state-nam 371 idle-state-name = "big-power-down";
339 arm,psci-suspe 372 arm,psci-suspend-param = <0x40000003>;
340 entry-latency- 373 entry-latency-us = <523>;
341 exit-latency-u 374 exit-latency-us = <1244>;
342 min-residency- 375 min-residency-us = <2207>;
343 local-timer-st 376 local-timer-stop;
344 }; 377 };
345 378
346 BIG_CPU_SLEEP_1: cpu-s 379 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
347 compatible = " 380 compatible = "arm,idle-state";
348 idle-state-nam 381 idle-state-name = "big-rail-power-down";
349 arm,psci-suspe 382 arm,psci-suspend-param = <0x40000004>;
350 entry-latency- 383 entry-latency-us = <526>;
351 exit-latency-u 384 exit-latency-us = <1854>;
352 min-residency- 385 min-residency-us = <5555>;
353 local-timer-st 386 local-timer-stop;
354 }; 387 };
355 }; <<
356 <<
357 domain_idle_states: domain-idl <<
358 CLUSTER_SLEEP_PC: clus <<
359 compatible = " <<
360 idle-state-nam <<
361 arm,psci-suspe <<
362 entry-latency- <<
363 exit-latency-u <<
364 min-residency- <<
365 }; <<
366 <<
367 CLUSTER_SLEEP_CX_RET: <<
368 compatible = " <<
369 idle-state-nam <<
370 arm,psci-suspe <<
371 entry-latency- <<
372 exit-latency-u <<
373 min-residency- <<
374 }; <<
375 388
376 CLUSTER_AOSS_SLEEP: cl !! 389 CLUSTER_SLEEP_0: cluster-sleep-0 {
377 compatible = " !! 390 compatible = "arm,idle-state";
378 idle-state-nam 391 idle-state-name = "cluster-power-down";
379 arm,psci-suspe !! 392 arm,psci-suspend-param = <0x40003444>;
380 entry-latency- 393 entry-latency-us = <3263>;
381 exit-latency-u 394 exit-latency-us = <6562>;
382 min-residency- !! 395 min-residency-us = <9926>;
>> 396 local-timer-stop;
383 }; 397 };
384 }; 398 };
385 }; 399 };
386 400
387 firmware { <<
388 scm: scm { <<
389 compatible = "qcom,scm <<
390 }; <<
391 }; <<
392 <<
393 memory@80000000 { <<
394 device_type = "memory"; <<
395 /* We expect the bootloader to <<
396 reg = <0 0x80000000 0 0>; <<
397 }; <<
398 <<
399 cpu0_opp_table: opp-table-cpu0 { 401 cpu0_opp_table: opp-table-cpu0 {
400 compatible = "operating-points 402 compatible = "operating-points-v2";
401 opp-shared; 403 opp-shared;
402 404
403 cpu0_opp1: opp-300000000 { 405 cpu0_opp1: opp-300000000 {
404 opp-hz = /bits/ 64 <30 406 opp-hz = /bits/ 64 <300000000>;
405 opp-peak-kBps = <12000 407 opp-peak-kBps = <1200000 4800000>;
406 }; 408 };
407 409
408 cpu0_opp2: opp-576000000 { 410 cpu0_opp2: opp-576000000 {
409 opp-hz = /bits/ 64 <57 411 opp-hz = /bits/ 64 <576000000>;
410 opp-peak-kBps = <12000 412 opp-peak-kBps = <1200000 4800000>;
411 }; 413 };
412 414
413 cpu0_opp3: opp-768000000 { 415 cpu0_opp3: opp-768000000 {
414 opp-hz = /bits/ 64 <76 416 opp-hz = /bits/ 64 <768000000>;
415 opp-peak-kBps = <12000 417 opp-peak-kBps = <1200000 4800000>;
416 }; 418 };
417 419
418 cpu0_opp4: opp-1017600000 { 420 cpu0_opp4: opp-1017600000 {
419 opp-hz = /bits/ 64 <10 421 opp-hz = /bits/ 64 <1017600000>;
420 opp-peak-kBps = <18040 422 opp-peak-kBps = <1804000 8908800>;
421 }; 423 };
422 424
423 cpu0_opp5: opp-1248000000 { 425 cpu0_opp5: opp-1248000000 {
424 opp-hz = /bits/ 64 <12 426 opp-hz = /bits/ 64 <1248000000>;
425 opp-peak-kBps = <21880 427 opp-peak-kBps = <2188000 12902400>;
426 }; 428 };
427 429
428 cpu0_opp6: opp-1324800000 { 430 cpu0_opp6: opp-1324800000 {
429 opp-hz = /bits/ 64 <13 431 opp-hz = /bits/ 64 <1324800000>;
430 opp-peak-kBps = <21880 432 opp-peak-kBps = <2188000 12902400>;
431 }; 433 };
432 434
433 cpu0_opp7: opp-1516800000 { 435 cpu0_opp7: opp-1516800000 {
434 opp-hz = /bits/ 64 <15 436 opp-hz = /bits/ 64 <1516800000>;
435 opp-peak-kBps = <30720 437 opp-peak-kBps = <3072000 15052800>;
436 }; 438 };
437 439
438 cpu0_opp8: opp-1612800000 { 440 cpu0_opp8: opp-1612800000 {
439 opp-hz = /bits/ 64 <16 441 opp-hz = /bits/ 64 <1612800000>;
440 opp-peak-kBps = <30720 442 opp-peak-kBps = <3072000 15052800>;
441 }; 443 };
442 444
443 cpu0_opp9: opp-1708800000 { 445 cpu0_opp9: opp-1708800000 {
444 opp-hz = /bits/ 64 <17 446 opp-hz = /bits/ 64 <1708800000>;
445 opp-peak-kBps = <30720 447 opp-peak-kBps = <3072000 15052800>;
446 }; 448 };
447 449
448 cpu0_opp10: opp-1804800000 { 450 cpu0_opp10: opp-1804800000 {
449 opp-hz = /bits/ 64 <18 451 opp-hz = /bits/ 64 <1804800000>;
450 opp-peak-kBps = <40680 452 opp-peak-kBps = <4068000 22425600>;
451 }; 453 };
452 }; 454 };
453 455
454 cpu6_opp_table: opp-table-cpu6 { 456 cpu6_opp_table: opp-table-cpu6 {
455 compatible = "operating-points 457 compatible = "operating-points-v2";
456 opp-shared; 458 opp-shared;
457 459
458 cpu6_opp1: opp-300000000 { 460 cpu6_opp1: opp-300000000 {
459 opp-hz = /bits/ 64 <30 461 opp-hz = /bits/ 64 <300000000>;
460 opp-peak-kBps = <21880 462 opp-peak-kBps = <2188000 8908800>;
461 }; 463 };
462 464
463 cpu6_opp2: opp-652800000 { 465 cpu6_opp2: opp-652800000 {
464 opp-hz = /bits/ 64 <65 466 opp-hz = /bits/ 64 <652800000>;
465 opp-peak-kBps = <21880 467 opp-peak-kBps = <2188000 8908800>;
466 }; 468 };
467 469
468 cpu6_opp3: opp-825600000 { 470 cpu6_opp3: opp-825600000 {
469 opp-hz = /bits/ 64 <82 471 opp-hz = /bits/ 64 <825600000>;
470 opp-peak-kBps = <21880 472 opp-peak-kBps = <2188000 8908800>;
471 }; 473 };
472 474
473 cpu6_opp4: opp-979200000 { 475 cpu6_opp4: opp-979200000 {
474 opp-hz = /bits/ 64 <97 476 opp-hz = /bits/ 64 <979200000>;
475 opp-peak-kBps = <21880 477 opp-peak-kBps = <2188000 8908800>;
476 }; 478 };
477 479
478 cpu6_opp5: opp-1113600000 { 480 cpu6_opp5: opp-1113600000 {
479 opp-hz = /bits/ 64 <11 481 opp-hz = /bits/ 64 <1113600000>;
480 opp-peak-kBps = <21880 482 opp-peak-kBps = <2188000 8908800>;
481 }; 483 };
482 484
483 cpu6_opp6: opp-1267200000 { 485 cpu6_opp6: opp-1267200000 {
484 opp-hz = /bits/ 64 <12 486 opp-hz = /bits/ 64 <1267200000>;
485 opp-peak-kBps = <40680 487 opp-peak-kBps = <4068000 12902400>;
486 }; 488 };
487 489
488 cpu6_opp7: opp-1555200000 { 490 cpu6_opp7: opp-1555200000 {
489 opp-hz = /bits/ 64 <15 491 opp-hz = /bits/ 64 <1555200000>;
490 opp-peak-kBps = <40680 492 opp-peak-kBps = <4068000 15052800>;
491 }; 493 };
492 494
493 cpu6_opp8: opp-1708800000 { 495 cpu6_opp8: opp-1708800000 {
494 opp-hz = /bits/ 64 <17 496 opp-hz = /bits/ 64 <1708800000>;
495 opp-peak-kBps = <62200 497 opp-peak-kBps = <6220000 19353600>;
496 }; 498 };
497 499
498 cpu6_opp9: opp-1843200000 { 500 cpu6_opp9: opp-1843200000 {
499 opp-hz = /bits/ 64 <18 501 opp-hz = /bits/ 64 <1843200000>;
500 opp-peak-kBps = <62200 502 opp-peak-kBps = <6220000 19353600>;
501 }; 503 };
502 504
503 cpu6_opp10: opp-1900800000 { 505 cpu6_opp10: opp-1900800000 {
504 opp-hz = /bits/ 64 <19 506 opp-hz = /bits/ 64 <1900800000>;
505 opp-peak-kBps = <62200 507 opp-peak-kBps = <6220000 22425600>;
506 }; 508 };
507 509
508 cpu6_opp11: opp-1996800000 { 510 cpu6_opp11: opp-1996800000 {
509 opp-hz = /bits/ 64 <19 511 opp-hz = /bits/ 64 <1996800000>;
510 opp-peak-kBps = <62200 512 opp-peak-kBps = <6220000 22425600>;
511 }; 513 };
512 514
513 cpu6_opp12: opp-2112000000 { 515 cpu6_opp12: opp-2112000000 {
514 opp-hz = /bits/ 64 <21 516 opp-hz = /bits/ 64 <2112000000>;
515 opp-peak-kBps = <62200 517 opp-peak-kBps = <6220000 22425600>;
516 }; 518 };
517 519
518 cpu6_opp13: opp-2208000000 { 520 cpu6_opp13: opp-2208000000 {
519 opp-hz = /bits/ 64 <22 521 opp-hz = /bits/ 64 <2208000000>;
520 opp-peak-kBps = <72160 522 opp-peak-kBps = <7216000 22425600>;
521 }; 523 };
522 524
523 cpu6_opp14: opp-2323200000 { 525 cpu6_opp14: opp-2323200000 {
524 opp-hz = /bits/ 64 <23 526 opp-hz = /bits/ 64 <2323200000>;
525 opp-peak-kBps = <72160 527 opp-peak-kBps = <7216000 22425600>;
526 }; 528 };
527 529
528 cpu6_opp15: opp-2400000000 { 530 cpu6_opp15: opp-2400000000 {
529 opp-hz = /bits/ 64 <24 531 opp-hz = /bits/ 64 <2400000000>;
530 opp-peak-kBps = <85320 532 opp-peak-kBps = <8532000 23347200>;
531 }; 533 };
532 534
533 cpu6_opp16: opp-2553600000 { 535 cpu6_opp16: opp-2553600000 {
534 opp-hz = /bits/ 64 <25 536 opp-hz = /bits/ 64 <2553600000>;
535 opp-peak-kBps = <85320 537 opp-peak-kBps = <8532000 23347200>;
536 }; 538 };
537 }; 539 };
538 540
539 qspi_opp_table: opp-table-qspi { !! 541 memory@80000000 {
540 compatible = "operating-points !! 542 device_type = "memory";
541 !! 543 /* We expect the bootloader to fill in the size */
542 opp-75000000 { !! 544 reg = <0 0x80000000 0 0>;
543 opp-hz = /bits/ 64 <75 <<
544 required-opps = <&rpmh <<
545 }; <<
546 <<
547 opp-150000000 { <<
548 opp-hz = /bits/ 64 <15 <<
549 required-opps = <&rpmh <<
550 }; <<
551 <<
552 opp-300000000 { <<
553 opp-hz = /bits/ 64 <30 <<
554 required-opps = <&rpmh <<
555 }; <<
556 }; <<
557 <<
558 qup_opp_table: opp-table-qup { <<
559 compatible = "operating-points <<
560 <<
561 opp-75000000 { <<
562 opp-hz = /bits/ 64 <75 <<
563 required-opps = <&rpmh <<
564 }; <<
565 <<
566 opp-100000000 { <<
567 opp-hz = /bits/ 64 <10 <<
568 required-opps = <&rpmh <<
569 }; <<
570 <<
571 opp-128000000 { <<
572 opp-hz = /bits/ 64 <12 <<
573 required-opps = <&rpmh <<
574 }; <<
575 }; 545 };
576 546
577 pmu { 547 pmu {
578 compatible = "arm,armv8-pmuv3" 548 compatible = "arm,armv8-pmuv3";
579 interrupts = <GIC_PPI 5 IRQ_TY 549 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
580 }; 550 };
581 551
582 psci { !! 552 firmware {
583 compatible = "arm,psci-1.0"; !! 553 scm {
584 method = "smc"; !! 554 compatible = "qcom,scm-sc7180", "qcom,scm";
585 <<
586 CPU_PD0: cpu0 { <<
587 #power-domain-cells = <<
588 power-domains = <&CLUS <<
589 domain-idle-states = < <<
590 }; <<
591 <<
592 CPU_PD1: cpu1 { <<
593 #power-domain-cells = <<
594 power-domains = <&CLUS <<
595 domain-idle-states = < <<
596 }; <<
597 <<
598 CPU_PD2: cpu2 { <<
599 #power-domain-cells = <<
600 power-domains = <&CLUS <<
601 domain-idle-states = < <<
602 }; <<
603 <<
604 CPU_PD3: cpu3 { <<
605 #power-domain-cells = <<
606 power-domains = <&CLUS <<
607 domain-idle-states = < <<
608 }; <<
609 <<
610 CPU_PD4: cpu4 { <<
611 #power-domain-cells = <<
612 power-domains = <&CLUS <<
613 domain-idle-states = < <<
614 }; <<
615 <<
616 CPU_PD5: cpu5 { <<
617 #power-domain-cells = <<
618 power-domains = <&CLUS <<
619 domain-idle-states = < <<
620 }; <<
621 <<
622 CPU_PD6: cpu6 { <<
623 #power-domain-cells = <<
624 power-domains = <&CLUS <<
625 domain-idle-states = < <<
626 }; <<
627 <<
628 CPU_PD7: cpu7 { <<
629 #power-domain-cells = <<
630 power-domains = <&CLUS <<
631 domain-idle-states = < <<
632 }; <<
633 <<
634 CLUSTER_PD: cpu-cluster0 { <<
635 #power-domain-cells = <<
636 domain-idle-states = < <<
637 <<
638 <<
639 }; <<
640 }; <<
641 <<
642 reserved_memory: reserved-memory { <<
643 #address-cells = <2>; <<
644 #size-cells = <2>; <<
645 ranges; <<
646 <<
647 hyp_mem: memory@80000000 { <<
648 reg = <0x0 0x80000000 <<
649 no-map; <<
650 }; <<
651 <<
652 xbl_mem: memory@80600000 { <<
653 reg = <0x0 0x80600000 <<
654 no-map; <<
655 }; <<
656 <<
657 aop_mem: memory@80800000 { <<
658 reg = <0x0 0x80800000 <<
659 no-map; <<
660 }; <<
661 <<
662 aop_cmd_db_mem: memory@8082000 <<
663 reg = <0x0 0x80820000 <<
664 compatible = "qcom,cmd <<
665 no-map; <<
666 }; <<
667 <<
668 sec_apps_mem: memory@808ff000 <<
669 reg = <0x0 0x808ff000 <<
670 no-map; <<
671 }; <<
672 <<
673 smem_mem: memory@80900000 { <<
674 reg = <0x0 0x80900000 <<
675 no-map; <<
676 }; <<
677 <<
678 tz_mem: memory@80b00000 { <<
679 reg = <0x0 0x80b00000 <<
680 no-map; <<
681 }; <<
682 <<
683 ipa_fw_mem: memory@8b700000 { <<
684 reg = <0 0x8b700000 0 <<
685 no-map; <<
686 }; <<
687 <<
688 rmtfs_mem: memory@94600000 { <<
689 compatible = "qcom,rmt <<
690 reg = <0x0 0x94600000 <<
691 no-map; <<
692 <<
693 qcom,client-id = <1>; <<
694 qcom,vmid = <QCOM_SCM_ <<
695 }; 555 };
696 }; 556 };
697 557
698 smem { 558 smem {
699 compatible = "qcom,smem"; 559 compatible = "qcom,smem";
700 memory-region = <&smem_mem>; 560 memory-region = <&smem_mem>;
701 hwlocks = <&tcsr_mutex 3>; 561 hwlocks = <&tcsr_mutex 3>;
702 }; 562 };
703 563
704 smp2p-cdsp { 564 smp2p-cdsp {
705 compatible = "qcom,smp2p"; 565 compatible = "qcom,smp2p";
706 qcom,smem = <94>, <432>; 566 qcom,smem = <94>, <432>;
707 567
708 interrupts = <GIC_SPI 576 IRQ_ 568 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
709 569
710 mboxes = <&apss_shared 6>; 570 mboxes = <&apss_shared 6>;
711 571
712 qcom,local-pid = <0>; 572 qcom,local-pid = <0>;
713 qcom,remote-pid = <5>; 573 qcom,remote-pid = <5>;
714 574
715 cdsp_smp2p_out: master-kernel 575 cdsp_smp2p_out: master-kernel {
716 qcom,entry-name = "mas 576 qcom,entry-name = "master-kernel";
717 #qcom,smem-state-cells 577 #qcom,smem-state-cells = <1>;
718 }; 578 };
719 579
720 cdsp_smp2p_in: slave-kernel { 580 cdsp_smp2p_in: slave-kernel {
721 qcom,entry-name = "sla 581 qcom,entry-name = "slave-kernel";
722 582
723 interrupt-controller; 583 interrupt-controller;
724 #interrupt-cells = <2> 584 #interrupt-cells = <2>;
725 }; 585 };
726 }; 586 };
727 587
728 smp2p-lpass { 588 smp2p-lpass {
729 compatible = "qcom,smp2p"; 589 compatible = "qcom,smp2p";
730 qcom,smem = <443>, <429>; 590 qcom,smem = <443>, <429>;
731 591
732 interrupts = <GIC_SPI 158 IRQ_ 592 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
733 593
734 mboxes = <&apss_shared 10>; 594 mboxes = <&apss_shared 10>;
735 595
736 qcom,local-pid = <0>; 596 qcom,local-pid = <0>;
737 qcom,remote-pid = <2>; 597 qcom,remote-pid = <2>;
738 598
739 adsp_smp2p_out: master-kernel 599 adsp_smp2p_out: master-kernel {
740 qcom,entry-name = "mas 600 qcom,entry-name = "master-kernel";
741 #qcom,smem-state-cells 601 #qcom,smem-state-cells = <1>;
742 }; 602 };
743 603
744 adsp_smp2p_in: slave-kernel { 604 adsp_smp2p_in: slave-kernel {
745 qcom,entry-name = "sla 605 qcom,entry-name = "slave-kernel";
746 606
747 interrupt-controller; 607 interrupt-controller;
748 #interrupt-cells = <2> 608 #interrupt-cells = <2>;
749 }; 609 };
750 }; 610 };
751 611
752 smp2p-mpss { 612 smp2p-mpss {
753 compatible = "qcom,smp2p"; 613 compatible = "qcom,smp2p";
754 qcom,smem = <435>, <428>; 614 qcom,smem = <435>, <428>;
755 interrupts = <GIC_SPI 451 IRQ_ 615 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
756 mboxes = <&apss_shared 14>; 616 mboxes = <&apss_shared 14>;
757 qcom,local-pid = <0>; 617 qcom,local-pid = <0>;
758 qcom,remote-pid = <1>; 618 qcom,remote-pid = <1>;
759 619
760 modem_smp2p_out: master-kernel 620 modem_smp2p_out: master-kernel {
761 qcom,entry-name = "mas 621 qcom,entry-name = "master-kernel";
762 #qcom,smem-state-cells 622 #qcom,smem-state-cells = <1>;
763 }; 623 };
764 624
765 modem_smp2p_in: slave-kernel { 625 modem_smp2p_in: slave-kernel {
766 qcom,entry-name = "sla 626 qcom,entry-name = "slave-kernel";
767 interrupt-controller; 627 interrupt-controller;
768 #interrupt-cells = <2> 628 #interrupt-cells = <2>;
769 }; 629 };
770 630
771 ipa_smp2p_out: ipa-ap-to-modem 631 ipa_smp2p_out: ipa-ap-to-modem {
772 qcom,entry-name = "ipa 632 qcom,entry-name = "ipa";
773 #qcom,smem-state-cells 633 #qcom,smem-state-cells = <1>;
774 }; 634 };
775 635
776 ipa_smp2p_in: ipa-modem-to-ap 636 ipa_smp2p_in: ipa-modem-to-ap {
777 qcom,entry-name = "ipa 637 qcom,entry-name = "ipa";
778 interrupt-controller; 638 interrupt-controller;
779 #interrupt-cells = <2> 639 #interrupt-cells = <2>;
780 }; 640 };
781 }; 641 };
782 642
>> 643 psci {
>> 644 compatible = "arm,psci-1.0";
>> 645 method = "smc";
>> 646 };
>> 647
783 soc: soc@0 { 648 soc: soc@0 {
784 #address-cells = <2>; 649 #address-cells = <2>;
785 #size-cells = <2>; 650 #size-cells = <2>;
786 ranges = <0 0 0 0 0x10 0>; 651 ranges = <0 0 0 0 0x10 0>;
787 dma-ranges = <0 0 0 0 0x10 0>; 652 dma-ranges = <0 0 0 0 0x10 0>;
788 compatible = "simple-bus"; 653 compatible = "simple-bus";
789 654
790 gcc: clock-controller@100000 { 655 gcc: clock-controller@100000 {
791 compatible = "qcom,gcc 656 compatible = "qcom,gcc-sc7180";
792 reg = <0 0x00100000 0 657 reg = <0 0x00100000 0 0x1f0000>;
793 clocks = <&rpmhcc RPMH 658 clocks = <&rpmhcc RPMH_CXO_CLK>,
794 <&rpmhcc RPMH 659 <&rpmhcc RPMH_CXO_CLK_A>,
795 <&sleep_clk>; 660 <&sleep_clk>;
796 clock-names = "bi_tcxo 661 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
797 #clock-cells = <1>; 662 #clock-cells = <1>;
798 #reset-cells = <1>; 663 #reset-cells = <1>;
799 #power-domain-cells = 664 #power-domain-cells = <1>;
800 power-domains = <&rpmh <<
801 }; 665 };
802 666
803 qfprom: efuse@784000 { 667 qfprom: efuse@784000 {
804 compatible = "qcom,sc7 668 compatible = "qcom,sc7180-qfprom", "qcom,qfprom";
805 reg = <0 0x00784000 0 669 reg = <0 0x00784000 0 0x7a0>,
806 <0 0x00780000 0 670 <0 0x00780000 0 0x7a0>,
807 <0 0x00782000 0 671 <0 0x00782000 0 0x100>,
808 <0 0x00786000 0 672 <0 0x00786000 0 0x1fff>;
809 673
810 clocks = <&gcc GCC_SEC 674 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>;
811 clock-names = "core"; 675 clock-names = "core";
812 #address-cells = <1>; 676 #address-cells = <1>;
813 #size-cells = <1>; 677 #size-cells = <1>;
814 678
815 qusb2p_hstx_trim: hstx 679 qusb2p_hstx_trim: hstx-trim-primary@25b {
816 reg = <0x25b 0 680 reg = <0x25b 0x1>;
817 bits = <1 3>; 681 bits = <1 3>;
818 }; 682 };
819 683
820 gpu_speed_bin: gpu-spe !! 684 gpu_speed_bin: gpu_speed_bin@1d2 {
821 reg = <0x1d2 0 685 reg = <0x1d2 0x2>;
822 bits = <5 8>; 686 bits = <5 8>;
823 }; 687 };
824 }; 688 };
825 689
826 sdhc_1: mmc@7c4000 { 690 sdhc_1: mmc@7c4000 {
827 compatible = "qcom,sc7 691 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
828 reg = <0 0x007c4000 0 !! 692 reg = <0 0x7c4000 0 0x1000>,
829 <0 0x007c5000 !! 693 <0 0x07c5000 0 0x1000>;
830 reg-names = "hc", "cqh 694 reg-names = "hc", "cqhci";
831 695
832 iommus = <&apps_smmu 0 696 iommus = <&apps_smmu 0x60 0x0>;
833 interrupts = <GIC_SPI 697 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
834 <GIC_S 698 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
835 interrupt-names = "hc_ 699 interrupt-names = "hc_irq", "pwr_irq";
836 700
837 clocks = <&gcc GCC_SDC 701 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
838 <&gcc GCC_SDC 702 <&gcc GCC_SDCC1_APPS_CLK>,
839 <&rpmhcc RPMH 703 <&rpmhcc RPMH_CXO_CLK>;
840 clock-names = "iface", 704 clock-names = "iface", "core", "xo";
841 interconnects = <&aggr 705 interconnects = <&aggre1_noc MASTER_EMMC 0 &mc_virt SLAVE_EBI1 0>,
842 <&gem_ 706 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_EMMC_CFG 0>;
843 interconnect-names = " 707 interconnect-names = "sdhc-ddr","cpu-sdhc";
844 power-domains = <&rpmh 708 power-domains = <&rpmhpd SC7180_CX>;
845 operating-points-v2 = 709 operating-points-v2 = <&sdhc1_opp_table>;
846 710
847 bus-width = <8>; 711 bus-width = <8>;
848 non-removable; 712 non-removable;
849 supports-cqe; 713 supports-cqe;
850 714
851 mmc-ddr-1_8v; 715 mmc-ddr-1_8v;
852 mmc-hs200-1_8v; 716 mmc-hs200-1_8v;
853 mmc-hs400-1_8v; 717 mmc-hs400-1_8v;
854 mmc-hs400-enhanced-str 718 mmc-hs400-enhanced-strobe;
855 719
856 status = "disabled"; 720 status = "disabled";
857 721
858 sdhc1_opp_table: opp-t 722 sdhc1_opp_table: opp-table {
859 compatible = " 723 compatible = "operating-points-v2";
860 724
861 opp-100000000 725 opp-100000000 {
862 opp-hz 726 opp-hz = /bits/ 64 <100000000>;
863 requir 727 required-opps = <&rpmhpd_opp_low_svs>;
864 opp-pe 728 opp-peak-kBps = <1800000 600000>;
865 opp-av 729 opp-avg-kBps = <100000 0>;
866 }; 730 };
867 731
868 opp-384000000 732 opp-384000000 {
869 opp-hz 733 opp-hz = /bits/ 64 <384000000>;
870 requir 734 required-opps = <&rpmhpd_opp_nom>;
871 opp-pe 735 opp-peak-kBps = <5400000 1600000>;
872 opp-av 736 opp-avg-kBps = <390000 0>;
873 }; 737 };
874 }; 738 };
875 }; 739 };
876 740
>> 741 qup_opp_table: opp-table-qup {
>> 742 compatible = "operating-points-v2";
>> 743
>> 744 opp-75000000 {
>> 745 opp-hz = /bits/ 64 <75000000>;
>> 746 required-opps = <&rpmhpd_opp_low_svs>;
>> 747 };
>> 748
>> 749 opp-100000000 {
>> 750 opp-hz = /bits/ 64 <100000000>;
>> 751 required-opps = <&rpmhpd_opp_svs>;
>> 752 };
>> 753
>> 754 opp-128000000 {
>> 755 opp-hz = /bits/ 64 <128000000>;
>> 756 required-opps = <&rpmhpd_opp_nom>;
>> 757 };
>> 758 };
>> 759
877 qupv3_id_0: geniqup@8c0000 { 760 qupv3_id_0: geniqup@8c0000 {
878 compatible = "qcom,gen 761 compatible = "qcom,geni-se-qup";
879 reg = <0 0x008c0000 0 762 reg = <0 0x008c0000 0 0x6000>;
880 clock-names = "m-ahb", 763 clock-names = "m-ahb", "s-ahb";
881 clocks = <&gcc GCC_QUP 764 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
882 <&gcc GCC_QUP 765 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
883 #address-cells = <2>; 766 #address-cells = <2>;
884 #size-cells = <2>; 767 #size-cells = <2>;
885 ranges; 768 ranges;
886 iommus = <&apps_smmu 0 769 iommus = <&apps_smmu 0x43 0x0>;
887 status = "disabled"; 770 status = "disabled";
888 771
889 i2c0: i2c@880000 { 772 i2c0: i2c@880000 {
890 compatible = " 773 compatible = "qcom,geni-i2c";
891 reg = <0 0x008 774 reg = <0 0x00880000 0 0x4000>;
892 clock-names = 775 clock-names = "se";
893 clocks = <&gcc 776 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
894 pinctrl-names 777 pinctrl-names = "default";
895 pinctrl-0 = <& 778 pinctrl-0 = <&qup_i2c0_default>;
896 interrupts = < 779 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
897 #address-cells 780 #address-cells = <1>;
898 #size-cells = 781 #size-cells = <0>;
899 interconnects 782 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
900 783 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
901 784 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
902 interconnect-n 785 interconnect-names = "qup-core", "qup-config",
903 786 "qup-memory";
904 power-domains 787 power-domains = <&rpmhpd SC7180_CX>;
905 required-opps 788 required-opps = <&rpmhpd_opp_low_svs>;
906 status = "disa 789 status = "disabled";
907 }; 790 };
908 791
909 spi0: spi@880000 { 792 spi0: spi@880000 {
910 compatible = " 793 compatible = "qcom,geni-spi";
911 reg = <0 0x008 794 reg = <0 0x00880000 0 0x4000>;
912 clock-names = 795 clock-names = "se";
913 clocks = <&gcc 796 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
914 pinctrl-names 797 pinctrl-names = "default";
915 pinctrl-0 = <& !! 798 pinctrl-0 = <&qup_spi0_default>;
916 interrupts = < 799 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
917 #address-cells 800 #address-cells = <1>;
918 #size-cells = 801 #size-cells = <0>;
919 power-domains 802 power-domains = <&rpmhpd SC7180_CX>;
920 operating-poin 803 operating-points-v2 = <&qup_opp_table>;
921 interconnects 804 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
922 805 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
923 interconnect-n 806 interconnect-names = "qup-core", "qup-config";
924 status = "disa 807 status = "disabled";
925 }; 808 };
926 809
927 uart0: serial@880000 { 810 uart0: serial@880000 {
928 compatible = " 811 compatible = "qcom,geni-uart";
929 reg = <0 0x008 812 reg = <0 0x00880000 0 0x4000>;
930 clock-names = 813 clock-names = "se";
931 clocks = <&gcc 814 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
932 pinctrl-names 815 pinctrl-names = "default";
933 pinctrl-0 = <& 816 pinctrl-0 = <&qup_uart0_default>;
934 interrupts = < 817 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
935 power-domains 818 power-domains = <&rpmhpd SC7180_CX>;
936 operating-poin 819 operating-points-v2 = <&qup_opp_table>;
937 interconnects 820 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
938 821 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
939 interconnect-n 822 interconnect-names = "qup-core", "qup-config";
940 status = "disa 823 status = "disabled";
941 }; 824 };
942 825
943 i2c1: i2c@884000 { 826 i2c1: i2c@884000 {
944 compatible = " 827 compatible = "qcom,geni-i2c";
945 reg = <0 0x008 828 reg = <0 0x00884000 0 0x4000>;
946 clock-names = 829 clock-names = "se";
947 clocks = <&gcc 830 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
948 pinctrl-names 831 pinctrl-names = "default";
949 pinctrl-0 = <& 832 pinctrl-0 = <&qup_i2c1_default>;
950 interrupts = < 833 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
951 #address-cells 834 #address-cells = <1>;
952 #size-cells = 835 #size-cells = <0>;
953 interconnects 836 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
954 837 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
955 838 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
956 interconnect-n 839 interconnect-names = "qup-core", "qup-config",
957 840 "qup-memory";
958 power-domains 841 power-domains = <&rpmhpd SC7180_CX>;
959 required-opps 842 required-opps = <&rpmhpd_opp_low_svs>;
960 status = "disa 843 status = "disabled";
961 }; 844 };
962 845
963 spi1: spi@884000 { 846 spi1: spi@884000 {
964 compatible = " 847 compatible = "qcom,geni-spi";
965 reg = <0 0x008 848 reg = <0 0x00884000 0 0x4000>;
966 clock-names = 849 clock-names = "se";
967 clocks = <&gcc 850 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
968 pinctrl-names 851 pinctrl-names = "default";
969 pinctrl-0 = <& !! 852 pinctrl-0 = <&qup_spi1_default>;
970 interrupts = < 853 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
971 #address-cells 854 #address-cells = <1>;
972 #size-cells = 855 #size-cells = <0>;
973 power-domains 856 power-domains = <&rpmhpd SC7180_CX>;
974 operating-poin 857 operating-points-v2 = <&qup_opp_table>;
975 interconnects 858 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
976 859 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
977 interconnect-n 860 interconnect-names = "qup-core", "qup-config";
978 status = "disa 861 status = "disabled";
979 }; 862 };
980 863
981 uart1: serial@884000 { 864 uart1: serial@884000 {
982 compatible = " 865 compatible = "qcom,geni-uart";
983 reg = <0 0x008 866 reg = <0 0x00884000 0 0x4000>;
984 clock-names = 867 clock-names = "se";
985 clocks = <&gcc 868 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
986 pinctrl-names 869 pinctrl-names = "default";
987 pinctrl-0 = <& 870 pinctrl-0 = <&qup_uart1_default>;
988 interrupts = < 871 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
989 power-domains 872 power-domains = <&rpmhpd SC7180_CX>;
990 operating-poin 873 operating-points-v2 = <&qup_opp_table>;
991 interconnects 874 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
992 875 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
993 interconnect-n 876 interconnect-names = "qup-core", "qup-config";
994 status = "disa 877 status = "disabled";
995 }; 878 };
996 879
997 i2c2: i2c@888000 { 880 i2c2: i2c@888000 {
998 compatible = " 881 compatible = "qcom,geni-i2c";
999 reg = <0 0x008 882 reg = <0 0x00888000 0 0x4000>;
1000 clock-names = 883 clock-names = "se";
1001 clocks = <&gc 884 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1002 pinctrl-names 885 pinctrl-names = "default";
1003 pinctrl-0 = < 886 pinctrl-0 = <&qup_i2c2_default>;
1004 interrupts = 887 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1005 #address-cell 888 #address-cells = <1>;
1006 #size-cells = 889 #size-cells = <0>;
1007 interconnects 890 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1008 891 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1009 892 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1010 interconnect- 893 interconnect-names = "qup-core", "qup-config",
1011 894 "qup-memory";
1012 power-domains 895 power-domains = <&rpmhpd SC7180_CX>;
1013 required-opps 896 required-opps = <&rpmhpd_opp_low_svs>;
1014 status = "dis 897 status = "disabled";
1015 }; 898 };
1016 899
1017 uart2: serial@888000 900 uart2: serial@888000 {
1018 compatible = 901 compatible = "qcom,geni-uart";
1019 reg = <0 0x00 902 reg = <0 0x00888000 0 0x4000>;
1020 clock-names = 903 clock-names = "se";
1021 clocks = <&gc 904 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1022 pinctrl-names 905 pinctrl-names = "default";
1023 pinctrl-0 = < 906 pinctrl-0 = <&qup_uart2_default>;
1024 interrupts = 907 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1025 power-domains 908 power-domains = <&rpmhpd SC7180_CX>;
1026 operating-poi 909 operating-points-v2 = <&qup_opp_table>;
1027 interconnects 910 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1028 911 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1029 interconnect- 912 interconnect-names = "qup-core", "qup-config";
1030 status = "dis 913 status = "disabled";
1031 }; 914 };
1032 915
1033 i2c3: i2c@88c000 { 916 i2c3: i2c@88c000 {
1034 compatible = 917 compatible = "qcom,geni-i2c";
1035 reg = <0 0x00 918 reg = <0 0x0088c000 0 0x4000>;
1036 clock-names = 919 clock-names = "se";
1037 clocks = <&gc 920 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1038 pinctrl-names 921 pinctrl-names = "default";
1039 pinctrl-0 = < 922 pinctrl-0 = <&qup_i2c3_default>;
1040 interrupts = 923 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1041 #address-cell 924 #address-cells = <1>;
1042 #size-cells = 925 #size-cells = <0>;
1043 interconnects 926 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1044 927 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1045 928 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1046 interconnect- 929 interconnect-names = "qup-core", "qup-config",
1047 930 "qup-memory";
1048 power-domains 931 power-domains = <&rpmhpd SC7180_CX>;
1049 required-opps 932 required-opps = <&rpmhpd_opp_low_svs>;
1050 status = "dis 933 status = "disabled";
1051 }; 934 };
1052 935
1053 spi3: spi@88c000 { 936 spi3: spi@88c000 {
1054 compatible = 937 compatible = "qcom,geni-spi";
1055 reg = <0 0x00 938 reg = <0 0x0088c000 0 0x4000>;
1056 clock-names = 939 clock-names = "se";
1057 clocks = <&gc 940 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1058 pinctrl-names 941 pinctrl-names = "default";
1059 pinctrl-0 = < !! 942 pinctrl-0 = <&qup_spi3_default>;
1060 interrupts = 943 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1061 #address-cell 944 #address-cells = <1>;
1062 #size-cells = 945 #size-cells = <0>;
1063 power-domains 946 power-domains = <&rpmhpd SC7180_CX>;
1064 operating-poi 947 operating-points-v2 = <&qup_opp_table>;
1065 interconnects 948 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1066 949 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1067 interconnect- 950 interconnect-names = "qup-core", "qup-config";
1068 status = "dis 951 status = "disabled";
1069 }; 952 };
1070 953
1071 uart3: serial@88c000 954 uart3: serial@88c000 {
1072 compatible = 955 compatible = "qcom,geni-uart";
1073 reg = <0 0x00 956 reg = <0 0x0088c000 0 0x4000>;
1074 clock-names = 957 clock-names = "se";
1075 clocks = <&gc 958 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1076 pinctrl-names 959 pinctrl-names = "default";
1077 pinctrl-0 = < 960 pinctrl-0 = <&qup_uart3_default>;
1078 interrupts = 961 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1079 power-domains 962 power-domains = <&rpmhpd SC7180_CX>;
1080 operating-poi 963 operating-points-v2 = <&qup_opp_table>;
1081 interconnects 964 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1082 965 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1083 interconnect- 966 interconnect-names = "qup-core", "qup-config";
1084 status = "dis 967 status = "disabled";
1085 }; 968 };
1086 969
1087 i2c4: i2c@890000 { 970 i2c4: i2c@890000 {
1088 compatible = 971 compatible = "qcom,geni-i2c";
1089 reg = <0 0x00 972 reg = <0 0x00890000 0 0x4000>;
1090 clock-names = 973 clock-names = "se";
1091 clocks = <&gc 974 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1092 pinctrl-names 975 pinctrl-names = "default";
1093 pinctrl-0 = < 976 pinctrl-0 = <&qup_i2c4_default>;
1094 interrupts = 977 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1095 #address-cell 978 #address-cells = <1>;
1096 #size-cells = 979 #size-cells = <0>;
1097 interconnects 980 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1098 981 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1099 982 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1100 interconnect- 983 interconnect-names = "qup-core", "qup-config",
1101 984 "qup-memory";
1102 power-domains 985 power-domains = <&rpmhpd SC7180_CX>;
1103 required-opps 986 required-opps = <&rpmhpd_opp_low_svs>;
1104 status = "dis 987 status = "disabled";
1105 }; 988 };
1106 989
1107 uart4: serial@890000 990 uart4: serial@890000 {
1108 compatible = 991 compatible = "qcom,geni-uart";
1109 reg = <0 0x00 992 reg = <0 0x00890000 0 0x4000>;
1110 clock-names = 993 clock-names = "se";
1111 clocks = <&gc 994 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1112 pinctrl-names 995 pinctrl-names = "default";
1113 pinctrl-0 = < 996 pinctrl-0 = <&qup_uart4_default>;
1114 interrupts = 997 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1115 power-domains 998 power-domains = <&rpmhpd SC7180_CX>;
1116 operating-poi 999 operating-points-v2 = <&qup_opp_table>;
1117 interconnects 1000 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1118 1001 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1119 interconnect- 1002 interconnect-names = "qup-core", "qup-config";
1120 status = "dis 1003 status = "disabled";
1121 }; 1004 };
1122 1005
1123 i2c5: i2c@894000 { 1006 i2c5: i2c@894000 {
1124 compatible = 1007 compatible = "qcom,geni-i2c";
1125 reg = <0 0x00 1008 reg = <0 0x00894000 0 0x4000>;
1126 clock-names = 1009 clock-names = "se";
1127 clocks = <&gc 1010 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1128 pinctrl-names 1011 pinctrl-names = "default";
1129 pinctrl-0 = < 1012 pinctrl-0 = <&qup_i2c5_default>;
1130 interrupts = 1013 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1131 #address-cell 1014 #address-cells = <1>;
1132 #size-cells = 1015 #size-cells = <0>;
1133 interconnects 1016 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1134 1017 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1135 1018 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1136 interconnect- 1019 interconnect-names = "qup-core", "qup-config",
1137 1020 "qup-memory";
1138 power-domains 1021 power-domains = <&rpmhpd SC7180_CX>;
1139 required-opps 1022 required-opps = <&rpmhpd_opp_low_svs>;
1140 status = "dis 1023 status = "disabled";
1141 }; 1024 };
1142 1025
1143 spi5: spi@894000 { 1026 spi5: spi@894000 {
1144 compatible = 1027 compatible = "qcom,geni-spi";
1145 reg = <0 0x00 1028 reg = <0 0x00894000 0 0x4000>;
1146 clock-names = 1029 clock-names = "se";
1147 clocks = <&gc 1030 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1148 pinctrl-names 1031 pinctrl-names = "default";
1149 pinctrl-0 = < !! 1032 pinctrl-0 = <&qup_spi5_default>;
1150 interrupts = 1033 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1151 #address-cell 1034 #address-cells = <1>;
1152 #size-cells = 1035 #size-cells = <0>;
1153 power-domains 1036 power-domains = <&rpmhpd SC7180_CX>;
1154 operating-poi 1037 operating-points-v2 = <&qup_opp_table>;
1155 interconnects 1038 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1156 1039 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1157 interconnect- 1040 interconnect-names = "qup-core", "qup-config";
1158 status = "dis 1041 status = "disabled";
1159 }; 1042 };
1160 1043
1161 uart5: serial@894000 1044 uart5: serial@894000 {
1162 compatible = 1045 compatible = "qcom,geni-uart";
1163 reg = <0 0x00 1046 reg = <0 0x00894000 0 0x4000>;
1164 clock-names = 1047 clock-names = "se";
1165 clocks = <&gc 1048 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1166 pinctrl-names 1049 pinctrl-names = "default";
1167 pinctrl-0 = < 1050 pinctrl-0 = <&qup_uart5_default>;
1168 interrupts = 1051 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1169 power-domains 1052 power-domains = <&rpmhpd SC7180_CX>;
1170 operating-poi 1053 operating-points-v2 = <&qup_opp_table>;
1171 interconnects 1054 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1172 1055 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1173 interconnect- 1056 interconnect-names = "qup-core", "qup-config";
1174 status = "dis 1057 status = "disabled";
1175 }; 1058 };
1176 }; 1059 };
1177 1060
1178 qupv3_id_1: geniqup@ac0000 { 1061 qupv3_id_1: geniqup@ac0000 {
1179 compatible = "qcom,ge 1062 compatible = "qcom,geni-se-qup";
1180 reg = <0 0x00ac0000 0 1063 reg = <0 0x00ac0000 0 0x6000>;
1181 clock-names = "m-ahb" 1064 clock-names = "m-ahb", "s-ahb";
1182 clocks = <&gcc GCC_QU 1065 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1183 <&gcc GCC_QU 1066 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1184 #address-cells = <2>; 1067 #address-cells = <2>;
1185 #size-cells = <2>; 1068 #size-cells = <2>;
1186 ranges; 1069 ranges;
1187 iommus = <&apps_smmu 1070 iommus = <&apps_smmu 0x4c3 0x0>;
1188 status = "disabled"; 1071 status = "disabled";
1189 1072
1190 i2c6: i2c@a80000 { 1073 i2c6: i2c@a80000 {
1191 compatible = 1074 compatible = "qcom,geni-i2c";
1192 reg = <0 0x00 1075 reg = <0 0x00a80000 0 0x4000>;
1193 clock-names = 1076 clock-names = "se";
1194 clocks = <&gc 1077 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1195 pinctrl-names 1078 pinctrl-names = "default";
1196 pinctrl-0 = < 1079 pinctrl-0 = <&qup_i2c6_default>;
1197 interrupts = 1080 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1198 #address-cell 1081 #address-cells = <1>;
1199 #size-cells = 1082 #size-cells = <0>;
1200 interconnects 1083 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1201 1084 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1202 1085 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1203 interconnect- 1086 interconnect-names = "qup-core", "qup-config",
1204 1087 "qup-memory";
1205 power-domains 1088 power-domains = <&rpmhpd SC7180_CX>;
1206 required-opps 1089 required-opps = <&rpmhpd_opp_low_svs>;
1207 status = "dis 1090 status = "disabled";
1208 }; 1091 };
1209 1092
1210 spi6: spi@a80000 { 1093 spi6: spi@a80000 {
1211 compatible = 1094 compatible = "qcom,geni-spi";
1212 reg = <0 0x00 1095 reg = <0 0x00a80000 0 0x4000>;
1213 clock-names = 1096 clock-names = "se";
1214 clocks = <&gc 1097 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1215 pinctrl-names 1098 pinctrl-names = "default";
1216 pinctrl-0 = < !! 1099 pinctrl-0 = <&qup_spi6_default>;
1217 interrupts = 1100 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1218 #address-cell 1101 #address-cells = <1>;
1219 #size-cells = 1102 #size-cells = <0>;
1220 power-domains 1103 power-domains = <&rpmhpd SC7180_CX>;
1221 operating-poi 1104 operating-points-v2 = <&qup_opp_table>;
1222 interconnects 1105 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1223 1106 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1224 interconnect- 1107 interconnect-names = "qup-core", "qup-config";
1225 status = "dis 1108 status = "disabled";
1226 }; 1109 };
1227 1110
1228 uart6: serial@a80000 1111 uart6: serial@a80000 {
1229 compatible = 1112 compatible = "qcom,geni-uart";
1230 reg = <0 0x00 1113 reg = <0 0x00a80000 0 0x4000>;
1231 clock-names = 1114 clock-names = "se";
1232 clocks = <&gc 1115 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1233 pinctrl-names 1116 pinctrl-names = "default";
1234 pinctrl-0 = < 1117 pinctrl-0 = <&qup_uart6_default>;
1235 interrupts = 1118 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1236 power-domains 1119 power-domains = <&rpmhpd SC7180_CX>;
1237 operating-poi 1120 operating-points-v2 = <&qup_opp_table>;
1238 interconnects 1121 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1239 1122 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1240 interconnect- 1123 interconnect-names = "qup-core", "qup-config";
1241 status = "dis 1124 status = "disabled";
1242 }; 1125 };
1243 1126
1244 i2c7: i2c@a84000 { 1127 i2c7: i2c@a84000 {
1245 compatible = 1128 compatible = "qcom,geni-i2c";
1246 reg = <0 0x00 1129 reg = <0 0x00a84000 0 0x4000>;
1247 clock-names = 1130 clock-names = "se";
1248 clocks = <&gc 1131 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1249 pinctrl-names 1132 pinctrl-names = "default";
1250 pinctrl-0 = < 1133 pinctrl-0 = <&qup_i2c7_default>;
1251 interrupts = 1134 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1252 #address-cell 1135 #address-cells = <1>;
1253 #size-cells = 1136 #size-cells = <0>;
1254 interconnects 1137 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1255 1138 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1256 1139 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1257 interconnect- 1140 interconnect-names = "qup-core", "qup-config",
1258 1141 "qup-memory";
1259 power-domains 1142 power-domains = <&rpmhpd SC7180_CX>;
1260 required-opps 1143 required-opps = <&rpmhpd_opp_low_svs>;
1261 status = "dis 1144 status = "disabled";
1262 }; 1145 };
1263 1146
1264 uart7: serial@a84000 1147 uart7: serial@a84000 {
1265 compatible = 1148 compatible = "qcom,geni-uart";
1266 reg = <0 0x00 1149 reg = <0 0x00a84000 0 0x4000>;
1267 clock-names = 1150 clock-names = "se";
1268 clocks = <&gc 1151 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1269 pinctrl-names 1152 pinctrl-names = "default";
1270 pinctrl-0 = < 1153 pinctrl-0 = <&qup_uart7_default>;
1271 interrupts = 1154 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1272 power-domains 1155 power-domains = <&rpmhpd SC7180_CX>;
1273 operating-poi 1156 operating-points-v2 = <&qup_opp_table>;
1274 interconnects 1157 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1275 1158 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1276 interconnect- 1159 interconnect-names = "qup-core", "qup-config";
1277 status = "dis 1160 status = "disabled";
1278 }; 1161 };
1279 1162
1280 i2c8: i2c@a88000 { 1163 i2c8: i2c@a88000 {
1281 compatible = 1164 compatible = "qcom,geni-i2c";
1282 reg = <0 0x00 1165 reg = <0 0x00a88000 0 0x4000>;
1283 clock-names = 1166 clock-names = "se";
1284 clocks = <&gc 1167 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1285 pinctrl-names 1168 pinctrl-names = "default";
1286 pinctrl-0 = < 1169 pinctrl-0 = <&qup_i2c8_default>;
1287 interrupts = 1170 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1288 #address-cell 1171 #address-cells = <1>;
1289 #size-cells = 1172 #size-cells = <0>;
1290 interconnects 1173 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1291 1174 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1292 1175 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1293 interconnect- 1176 interconnect-names = "qup-core", "qup-config",
1294 1177 "qup-memory";
1295 power-domains 1178 power-domains = <&rpmhpd SC7180_CX>;
1296 required-opps 1179 required-opps = <&rpmhpd_opp_low_svs>;
1297 status = "dis 1180 status = "disabled";
1298 }; 1181 };
1299 1182
1300 spi8: spi@a88000 { 1183 spi8: spi@a88000 {
1301 compatible = 1184 compatible = "qcom,geni-spi";
1302 reg = <0 0x00 1185 reg = <0 0x00a88000 0 0x4000>;
1303 clock-names = 1186 clock-names = "se";
1304 clocks = <&gc 1187 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1305 pinctrl-names 1188 pinctrl-names = "default";
1306 pinctrl-0 = < !! 1189 pinctrl-0 = <&qup_spi8_default>;
1307 interrupts = 1190 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1308 #address-cell 1191 #address-cells = <1>;
1309 #size-cells = 1192 #size-cells = <0>;
1310 power-domains 1193 power-domains = <&rpmhpd SC7180_CX>;
1311 operating-poi 1194 operating-points-v2 = <&qup_opp_table>;
1312 interconnects 1195 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1313 1196 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1314 interconnect- 1197 interconnect-names = "qup-core", "qup-config";
1315 status = "dis 1198 status = "disabled";
1316 }; 1199 };
1317 1200
1318 uart8: serial@a88000 1201 uart8: serial@a88000 {
1319 compatible = 1202 compatible = "qcom,geni-debug-uart";
1320 reg = <0 0x00 1203 reg = <0 0x00a88000 0 0x4000>;
1321 clock-names = 1204 clock-names = "se";
1322 clocks = <&gc 1205 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1323 pinctrl-names 1206 pinctrl-names = "default";
1324 pinctrl-0 = < 1207 pinctrl-0 = <&qup_uart8_default>;
1325 interrupts = 1208 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1326 power-domains 1209 power-domains = <&rpmhpd SC7180_CX>;
1327 operating-poi 1210 operating-points-v2 = <&qup_opp_table>;
1328 interconnects 1211 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1329 1212 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1330 interconnect- 1213 interconnect-names = "qup-core", "qup-config";
1331 status = "dis 1214 status = "disabled";
1332 }; 1215 };
1333 1216
1334 i2c9: i2c@a8c000 { 1217 i2c9: i2c@a8c000 {
1335 compatible = 1218 compatible = "qcom,geni-i2c";
1336 reg = <0 0x00 1219 reg = <0 0x00a8c000 0 0x4000>;
1337 clock-names = 1220 clock-names = "se";
1338 clocks = <&gc 1221 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1339 pinctrl-names 1222 pinctrl-names = "default";
1340 pinctrl-0 = < 1223 pinctrl-0 = <&qup_i2c9_default>;
1341 interrupts = 1224 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1342 #address-cell 1225 #address-cells = <1>;
1343 #size-cells = 1226 #size-cells = <0>;
1344 interconnects 1227 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1345 1228 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1346 1229 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1347 interconnect- 1230 interconnect-names = "qup-core", "qup-config",
1348 1231 "qup-memory";
1349 power-domains 1232 power-domains = <&rpmhpd SC7180_CX>;
1350 required-opps 1233 required-opps = <&rpmhpd_opp_low_svs>;
1351 status = "dis 1234 status = "disabled";
1352 }; 1235 };
1353 1236
1354 uart9: serial@a8c000 1237 uart9: serial@a8c000 {
1355 compatible = 1238 compatible = "qcom,geni-uart";
1356 reg = <0 0x00 1239 reg = <0 0x00a8c000 0 0x4000>;
1357 clock-names = 1240 clock-names = "se";
1358 clocks = <&gc 1241 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1359 pinctrl-names 1242 pinctrl-names = "default";
1360 pinctrl-0 = < 1243 pinctrl-0 = <&qup_uart9_default>;
1361 interrupts = 1244 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1362 power-domains 1245 power-domains = <&rpmhpd SC7180_CX>;
1363 operating-poi 1246 operating-points-v2 = <&qup_opp_table>;
1364 interconnects 1247 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1365 1248 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1366 interconnect- 1249 interconnect-names = "qup-core", "qup-config";
1367 status = "dis 1250 status = "disabled";
1368 }; 1251 };
1369 1252
1370 i2c10: i2c@a90000 { 1253 i2c10: i2c@a90000 {
1371 compatible = 1254 compatible = "qcom,geni-i2c";
1372 reg = <0 0x00 1255 reg = <0 0x00a90000 0 0x4000>;
1373 clock-names = 1256 clock-names = "se";
1374 clocks = <&gc 1257 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1375 pinctrl-names 1258 pinctrl-names = "default";
1376 pinctrl-0 = < 1259 pinctrl-0 = <&qup_i2c10_default>;
1377 interrupts = 1260 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1378 #address-cell 1261 #address-cells = <1>;
1379 #size-cells = 1262 #size-cells = <0>;
1380 interconnects 1263 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1381 1264 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1382 1265 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1383 interconnect- 1266 interconnect-names = "qup-core", "qup-config",
1384 1267 "qup-memory";
1385 power-domains 1268 power-domains = <&rpmhpd SC7180_CX>;
1386 required-opps 1269 required-opps = <&rpmhpd_opp_low_svs>;
1387 status = "dis 1270 status = "disabled";
1388 }; 1271 };
1389 1272
1390 spi10: spi@a90000 { 1273 spi10: spi@a90000 {
1391 compatible = 1274 compatible = "qcom,geni-spi";
1392 reg = <0 0x00 1275 reg = <0 0x00a90000 0 0x4000>;
1393 clock-names = 1276 clock-names = "se";
1394 clocks = <&gc 1277 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1395 pinctrl-names 1278 pinctrl-names = "default";
1396 pinctrl-0 = < !! 1279 pinctrl-0 = <&qup_spi10_default>;
1397 interrupts = 1280 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1398 #address-cell 1281 #address-cells = <1>;
1399 #size-cells = 1282 #size-cells = <0>;
1400 power-domains 1283 power-domains = <&rpmhpd SC7180_CX>;
1401 operating-poi 1284 operating-points-v2 = <&qup_opp_table>;
1402 interconnects 1285 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1403 1286 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1404 interconnect- 1287 interconnect-names = "qup-core", "qup-config";
1405 status = "dis 1288 status = "disabled";
1406 }; 1289 };
1407 1290
1408 uart10: serial@a90000 1291 uart10: serial@a90000 {
1409 compatible = 1292 compatible = "qcom,geni-uart";
1410 reg = <0 0x00 1293 reg = <0 0x00a90000 0 0x4000>;
1411 clock-names = 1294 clock-names = "se";
1412 clocks = <&gc 1295 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1413 pinctrl-names 1296 pinctrl-names = "default";
1414 pinctrl-0 = < 1297 pinctrl-0 = <&qup_uart10_default>;
1415 interrupts = 1298 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1416 power-domains 1299 power-domains = <&rpmhpd SC7180_CX>;
1417 operating-poi 1300 operating-points-v2 = <&qup_opp_table>;
1418 interconnects 1301 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1419 1302 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1420 interconnect- 1303 interconnect-names = "qup-core", "qup-config";
1421 status = "dis 1304 status = "disabled";
1422 }; 1305 };
1423 1306
1424 i2c11: i2c@a94000 { 1307 i2c11: i2c@a94000 {
1425 compatible = 1308 compatible = "qcom,geni-i2c";
1426 reg = <0 0x00 1309 reg = <0 0x00a94000 0 0x4000>;
1427 clock-names = 1310 clock-names = "se";
1428 clocks = <&gc 1311 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1429 pinctrl-names 1312 pinctrl-names = "default";
1430 pinctrl-0 = < 1313 pinctrl-0 = <&qup_i2c11_default>;
1431 interrupts = 1314 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1432 #address-cell 1315 #address-cells = <1>;
1433 #size-cells = 1316 #size-cells = <0>;
1434 interconnects 1317 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1435 1318 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1436 1319 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1437 interconnect- 1320 interconnect-names = "qup-core", "qup-config",
1438 1321 "qup-memory";
1439 power-domains 1322 power-domains = <&rpmhpd SC7180_CX>;
1440 required-opps 1323 required-opps = <&rpmhpd_opp_low_svs>;
1441 status = "dis 1324 status = "disabled";
1442 }; 1325 };
1443 1326
1444 spi11: spi@a94000 { 1327 spi11: spi@a94000 {
1445 compatible = 1328 compatible = "qcom,geni-spi";
1446 reg = <0 0x00 1329 reg = <0 0x00a94000 0 0x4000>;
1447 clock-names = 1330 clock-names = "se";
1448 clocks = <&gc 1331 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1449 pinctrl-names 1332 pinctrl-names = "default";
1450 pinctrl-0 = < !! 1333 pinctrl-0 = <&qup_spi11_default>;
1451 interrupts = 1334 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1452 #address-cell 1335 #address-cells = <1>;
1453 #size-cells = 1336 #size-cells = <0>;
1454 power-domains 1337 power-domains = <&rpmhpd SC7180_CX>;
1455 operating-poi 1338 operating-points-v2 = <&qup_opp_table>;
1456 interconnects 1339 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1457 1340 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1458 interconnect- 1341 interconnect-names = "qup-core", "qup-config";
1459 status = "dis 1342 status = "disabled";
1460 }; 1343 };
1461 1344
1462 uart11: serial@a94000 1345 uart11: serial@a94000 {
1463 compatible = 1346 compatible = "qcom,geni-uart";
1464 reg = <0 0x00 1347 reg = <0 0x00a94000 0 0x4000>;
1465 clock-names = 1348 clock-names = "se";
1466 clocks = <&gc 1349 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1467 pinctrl-names 1350 pinctrl-names = "default";
1468 pinctrl-0 = < 1351 pinctrl-0 = <&qup_uart11_default>;
1469 interrupts = 1352 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1470 power-domains 1353 power-domains = <&rpmhpd SC7180_CX>;
1471 operating-poi 1354 operating-points-v2 = <&qup_opp_table>;
1472 interconnects 1355 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1473 1356 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1474 interconnect- 1357 interconnect-names = "qup-core", "qup-config";
1475 status = "dis 1358 status = "disabled";
1476 }; 1359 };
1477 }; 1360 };
1478 1361
1479 config_noc: interconnect@1500 1362 config_noc: interconnect@1500000 {
1480 compatible = "qcom,sc 1363 compatible = "qcom,sc7180-config-noc";
1481 reg = <0 0x01500000 0 1364 reg = <0 0x01500000 0 0x28000>;
1482 #interconnect-cells = 1365 #interconnect-cells = <2>;
1483 qcom,bcm-voters = <&a 1366 qcom,bcm-voters = <&apps_bcm_voter>;
1484 }; 1367 };
1485 1368
1486 system_noc: interconnect@1620 1369 system_noc: interconnect@1620000 {
1487 compatible = "qcom,sc 1370 compatible = "qcom,sc7180-system-noc";
1488 reg = <0 0x01620000 0 1371 reg = <0 0x01620000 0 0x17080>;
1489 #interconnect-cells = 1372 #interconnect-cells = <2>;
1490 qcom,bcm-voters = <&a 1373 qcom,bcm-voters = <&apps_bcm_voter>;
1491 }; 1374 };
1492 1375
1493 mc_virt: interconnect@1638000 1376 mc_virt: interconnect@1638000 {
1494 compatible = "qcom,sc 1377 compatible = "qcom,sc7180-mc-virt";
1495 reg = <0 0x01638000 0 1378 reg = <0 0x01638000 0 0x1000>;
1496 #interconnect-cells = 1379 #interconnect-cells = <2>;
1497 qcom,bcm-voters = <&a 1380 qcom,bcm-voters = <&apps_bcm_voter>;
1498 }; 1381 };
1499 1382
1500 qup_virt: interconnect@165000 1383 qup_virt: interconnect@1650000 {
1501 compatible = "qcom,sc 1384 compatible = "qcom,sc7180-qup-virt";
1502 reg = <0 0x01650000 0 1385 reg = <0 0x01650000 0 0x1000>;
1503 #interconnect-cells = 1386 #interconnect-cells = <2>;
1504 qcom,bcm-voters = <&a 1387 qcom,bcm-voters = <&apps_bcm_voter>;
1505 }; 1388 };
1506 1389
1507 aggre1_noc: interconnect@16e0 1390 aggre1_noc: interconnect@16e0000 {
1508 compatible = "qcom,sc 1391 compatible = "qcom,sc7180-aggre1-noc";
1509 reg = <0 0x016e0000 0 1392 reg = <0 0x016e0000 0 0x15080>;
1510 #interconnect-cells = 1393 #interconnect-cells = <2>;
1511 qcom,bcm-voters = <&a 1394 qcom,bcm-voters = <&apps_bcm_voter>;
1512 }; 1395 };
1513 1396
1514 aggre2_noc: interconnect@1705 1397 aggre2_noc: interconnect@1705000 {
1515 compatible = "qcom,sc 1398 compatible = "qcom,sc7180-aggre2-noc";
1516 reg = <0 0x01705000 0 1399 reg = <0 0x01705000 0 0x9000>;
1517 #interconnect-cells = 1400 #interconnect-cells = <2>;
1518 qcom,bcm-voters = <&a 1401 qcom,bcm-voters = <&apps_bcm_voter>;
1519 }; 1402 };
1520 1403
1521 compute_noc: interconnect@170 1404 compute_noc: interconnect@170e000 {
1522 compatible = "qcom,sc 1405 compatible = "qcom,sc7180-compute-noc";
1523 reg = <0 0x0170e000 0 1406 reg = <0 0x0170e000 0 0x6000>;
1524 #interconnect-cells = 1407 #interconnect-cells = <2>;
1525 qcom,bcm-voters = <&a 1408 qcom,bcm-voters = <&apps_bcm_voter>;
1526 }; 1409 };
1527 1410
1528 mmss_noc: interconnect@174000 1411 mmss_noc: interconnect@1740000 {
1529 compatible = "qcom,sc 1412 compatible = "qcom,sc7180-mmss-noc";
1530 reg = <0 0x01740000 0 1413 reg = <0 0x01740000 0 0x1c100>;
1531 #interconnect-cells = 1414 #interconnect-cells = <2>;
1532 qcom,bcm-voters = <&a 1415 qcom,bcm-voters = <&apps_bcm_voter>;
1533 }; 1416 };
1534 1417
1535 ufs_mem_hc: ufshc@1d84000 { <<
1536 compatible = "qcom,sc <<
1537 "jedec,u <<
1538 reg = <0 0x01d84000 0 <<
1539 interrupts = <GIC_SPI <<
1540 phys = <&ufs_mem_phy> <<
1541 phy-names = "ufsphy"; <<
1542 lanes-per-direction = <<
1543 #reset-cells = <1>; <<
1544 resets = <&gcc GCC_UF <<
1545 reset-names = "rst"; <<
1546 <<
1547 power-domains = <&gcc <<
1548 <<
1549 iommus = <&apps_smmu <<
1550 <<
1551 clock-names = "core_c <<
1552 "bus_ag <<
1553 "iface_ <<
1554 "core_c <<
1555 "ref_cl <<
1556 "tx_lan <<
1557 "rx_lan <<
1558 clocks = <&gcc GCC_UF <<
1559 <&gcc GCC_AG <<
1560 <&gcc GCC_UF <<
1561 <&gcc GCC_UF <<
1562 <&rpmhcc RPM <<
1563 <&gcc GCC_UF <<
1564 <&gcc GCC_UF <<
1565 freq-table-hz = <5000 <<
1566 <0 0> <<
1567 <0 0> <<
1568 <3750 <<
1569 <0 0> <<
1570 <0 0> <<
1571 <0 0> <<
1572 <<
1573 interconnects = <&agg <<
1574 &mc_ <<
1575 <&gem <<
1576 &con <<
1577 interconnect-names = <<
1578 <<
1579 qcom,ice = <&ice>; <<
1580 <<
1581 status = "disabled"; <<
1582 }; <<
1583 <<
1584 ufs_mem_phy: phy@1d87000 { <<
1585 compatible = "qcom,sc <<
1586 reg = <0 0x01d87000 0 <<
1587 clocks = <&rpmhcc RPM <<
1588 <&gcc GCC_UF <<
1589 <&gcc GCC_UF <<
1590 clock-names = "ref", <<
1591 "ref_au <<
1592 "qref"; <<
1593 power-domains = <&gcc <<
1594 resets = <&ufs_mem_hc <<
1595 reset-names = "ufsphy <<
1596 #phy-cells = <0>; <<
1597 status = "disabled"; <<
1598 }; <<
1599 <<
1600 ice: crypto@1d90000 { <<
1601 compatible = "qcom,sc <<
1602 "qcom,in <<
1603 reg = <0 0x01d90000 0 <<
1604 clocks = <&gcc GCC_UF <<
1605 }; <<
1606 <<
1607 ipa: ipa@1e40000 { 1418 ipa: ipa@1e40000 {
1608 compatible = "qcom,sc 1419 compatible = "qcom,sc7180-ipa";
1609 1420
1610 iommus = <&apps_smmu 1421 iommus = <&apps_smmu 0x440 0x0>,
1611 <&apps_smmu 1422 <&apps_smmu 0x442 0x0>;
1612 reg = <0 0x01e40000 0 !! 1423 reg = <0 0x1e40000 0 0x7000>,
1613 <0 0x01e47000 0 !! 1424 <0 0x1e47000 0 0x2000>,
1614 <0 0x01e04000 0 !! 1425 <0 0x1e04000 0 0x2c000>;
1615 reg-names = "ipa-reg" 1426 reg-names = "ipa-reg",
1616 "ipa-shar 1427 "ipa-shared",
1617 "gsi"; 1428 "gsi";
1618 1429
1619 interrupts-extended = 1430 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
1620 1431 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
1621 1432 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1622 1433 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
1623 interrupt-names = "ip 1434 interrupt-names = "ipa",
1624 "gs 1435 "gsi",
1625 "ip 1436 "ipa-clock-query",
1626 "ip 1437 "ipa-setup-ready";
1627 1438
1628 clocks = <&rpmhcc RPM 1439 clocks = <&rpmhcc RPMH_IPA_CLK>;
1629 clock-names = "core"; 1440 clock-names = "core";
1630 1441
1631 interconnects = <&agg 1442 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
1632 <&agg 1443 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>,
1633 <&gem 1444 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
1634 interconnect-names = 1445 interconnect-names = "memory",
1635 1446 "imem",
1636 1447 "config";
1637 1448
1638 qcom,qmp = <&aoss_qmp 1449 qcom,qmp = <&aoss_qmp>;
1639 1450
1640 qcom,smem-states = <& 1451 qcom,smem-states = <&ipa_smp2p_out 0>,
1641 <& 1452 <&ipa_smp2p_out 1>;
1642 qcom,smem-state-names 1453 qcom,smem-state-names = "ipa-clock-enabled-valid",
1643 1454 "ipa-clock-enabled";
1644 1455
1645 status = "disabled"; 1456 status = "disabled";
1646 }; 1457 };
1647 1458
1648 tcsr_mutex: hwlock@1f40000 { 1459 tcsr_mutex: hwlock@1f40000 {
1649 compatible = "qcom,tc 1460 compatible = "qcom,tcsr-mutex";
1650 reg = <0 0x01f40000 0 1461 reg = <0 0x01f40000 0 0x20000>;
1651 #hwlock-cells = <1>; 1462 #hwlock-cells = <1>;
1652 }; 1463 };
1653 1464
1654 tcsr_regs_1: syscon@1f60000 { 1465 tcsr_regs_1: syscon@1f60000 {
1655 compatible = "qcom,sc 1466 compatible = "qcom,sc7180-tcsr", "syscon";
1656 reg = <0 0x01f60000 0 1467 reg = <0 0x01f60000 0 0x20000>;
1657 }; 1468 };
1658 1469
1659 tcsr_regs_2: syscon@1fc0000 { 1470 tcsr_regs_2: syscon@1fc0000 {
1660 compatible = "qcom,sc 1471 compatible = "qcom,sc7180-tcsr", "syscon";
1661 reg = <0 0x01fc0000 0 1472 reg = <0 0x01fc0000 0 0x40000>;
1662 }; 1473 };
1663 1474
1664 tlmm: pinctrl@3500000 { 1475 tlmm: pinctrl@3500000 {
1665 compatible = "qcom,sc 1476 compatible = "qcom,sc7180-pinctrl";
1666 reg = <0 0x03500000 0 1477 reg = <0 0x03500000 0 0x300000>,
1667 <0 0x03900000 0 1478 <0 0x03900000 0 0x300000>,
1668 <0 0x03d00000 0 1479 <0 0x03d00000 0 0x300000>;
1669 reg-names = "west", " 1480 reg-names = "west", "north", "south";
1670 interrupts = <GIC_SPI 1481 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1671 gpio-controller; 1482 gpio-controller;
1672 #gpio-cells = <2>; 1483 #gpio-cells = <2>;
1673 interrupt-controller; 1484 interrupt-controller;
1674 #interrupt-cells = <2 1485 #interrupt-cells = <2>;
1675 gpio-ranges = <&tlmm 1486 gpio-ranges = <&tlmm 0 0 120>;
1676 wakeup-parent = <&pdc 1487 wakeup-parent = <&pdc>;
1677 1488
1678 dp_hot_plug_det: dp-h !! 1489 dp_hot_plug_det: dp-hot-plug-det {
1679 pins = "gpio1 !! 1490 pinmux {
1680 function = "d !! 1491 pins = "gpio117";
1681 }; !! 1492 function = "dp_hot";
1682 !! 1493 };
1683 qspi_clk: qspi-clk-st <<
1684 pins = "gpio6 <<
1685 function = "q <<
1686 }; <<
1687 <<
1688 qspi_cs0: qspi-cs0-st <<
1689 pins = "gpio6 <<
1690 function = "q <<
1691 }; <<
1692 <<
1693 qspi_cs1: qspi-cs1-st <<
1694 pins = "gpio7 <<
1695 function = "q <<
1696 }; <<
1697 <<
1698 qspi_data0: qspi-data <<
1699 pins = "gpio6 <<
1700 function = "q <<
1701 }; <<
1702 <<
1703 qspi_data1: qspi-data <<
1704 pins = "gpio6 <<
1705 function = "q <<
1706 }; <<
1707 <<
1708 qspi_data23: qspi-dat <<
1709 pins = "gpio6 <<
1710 function = "q <<
1711 }; <<
1712 <<
1713 qup_i2c0_default: qup <<
1714 pins = "gpio3 <<
1715 function = "q <<
1716 }; <<
1717 <<
1718 qup_i2c1_default: qup <<
1719 pins = "gpio0 <<
1720 function = "q <<
1721 }; <<
1722 <<
1723 qup_i2c2_default: qup <<
1724 pins = "gpio1 <<
1725 function = "q <<
1726 }; <<
1727 <<
1728 qup_i2c3_default: qup <<
1729 pins = "gpio3 <<
1730 function = "q <<
1731 }; <<
1732 <<
1733 qup_i2c4_default: qup <<
1734 pins = "gpio1 <<
1735 function = "q <<
1736 }; <<
1737 <<
1738 qup_i2c5_default: qup <<
1739 pins = "gpio2 <<
1740 function = "q <<
1741 }; <<
1742 <<
1743 qup_i2c6_default: qup <<
1744 pins = "gpio5 <<
1745 function = "q <<
1746 }; <<
1747 <<
1748 qup_i2c7_default: qup <<
1749 pins = "gpio6 <<
1750 function = "q <<
1751 }; <<
1752 <<
1753 qup_i2c8_default: qup <<
1754 pins = "gpio4 <<
1755 function = "q <<
1756 }; <<
1757 <<
1758 qup_i2c9_default: qup <<
1759 pins = "gpio4 <<
1760 function = "q <<
1761 }; <<
1762 <<
1763 qup_i2c10_default: qu <<
1764 pins = "gpio8 <<
1765 function = "q <<
1766 }; <<
1767 <<
1768 qup_i2c11_default: qu <<
1769 pins = "gpio5 <<
1770 function = "q <<
1771 }; <<
1772 <<
1773 qup_spi0_spi: qup-spi <<
1774 pins = "gpio3 <<
1775 function = "q <<
1776 }; <<
1777 <<
1778 qup_spi0_cs: qup-spi0 <<
1779 pins = "gpio3 <<
1780 function = "q <<
1781 }; <<
1782 <<
1783 qup_spi0_cs_gpio: qup <<
1784 pins = "gpio3 <<
1785 function = "g <<
1786 }; <<
1787 <<
1788 qup_spi1_spi: qup-spi <<
1789 pins = "gpio0 <<
1790 function = "q <<
1791 }; <<
1792 <<
1793 qup_spi1_cs: qup-spi1 <<
1794 pins = "gpio3 <<
1795 function = "q <<
1796 }; <<
1797 <<
1798 qup_spi1_cs_gpio: qup <<
1799 pins = "gpio3 <<
1800 function = "g <<
1801 }; <<
1802 <<
1803 qup_spi3_spi: qup-spi <<
1804 pins = "gpio3 <<
1805 function = "q <<
1806 }; <<
1807 <<
1808 qup_spi3_cs: qup-spi3 <<
1809 pins = "gpio4 <<
1810 function = "q <<
1811 }; 1494 };
1812 1495
1813 qup_spi3_cs_gpio: qup !! 1496 qspi_clk: qspi-clk {
1814 pins = "gpio4 !! 1497 pinmux {
1815 function = "g !! 1498 pins = "gpio63";
>> 1499 function = "qspi_clk";
>> 1500 };
1816 }; 1501 };
1817 1502
1818 qup_spi5_spi: qup-spi !! 1503 qspi_cs0: qspi-cs0 {
1819 pins = "gpio2 !! 1504 pinmux {
1820 function = "q !! 1505 pins = "gpio68";
>> 1506 function = "qspi_cs";
>> 1507 };
1821 }; 1508 };
1822 1509
1823 qup_spi5_cs: qup-spi5 !! 1510 qspi_cs1: qspi-cs1 {
1824 pins = "gpio2 !! 1511 pinmux {
1825 function = "q !! 1512 pins = "gpio72";
>> 1513 function = "qspi_cs";
>> 1514 };
1826 }; 1515 };
1827 1516
1828 qup_spi5_cs_gpio: qup !! 1517 qspi_data01: qspi-data01 {
1829 pins = "gpio2 !! 1518 pinmux-data {
1830 function = "g !! 1519 pins = "gpio64", "gpio65";
>> 1520 function = "qspi_data";
>> 1521 };
1831 }; 1522 };
1832 1523
1833 qup_spi6_spi: qup-spi !! 1524 qspi_data23: qspi-data23 {
1834 pins = "gpio5 !! 1525 pinmux-data {
1835 function = "q !! 1526 pins = "gpio66", "gpio67";
>> 1527 function = "qspi_data";
>> 1528 };
1836 }; 1529 };
1837 1530
1838 qup_spi6_cs: qup-spi6 !! 1531 qup_i2c0_default: qup-i2c0-default {
1839 pins = "gpio6 !! 1532 pinmux {
1840 function = "q !! 1533 pins = "gpio34", "gpio35";
>> 1534 function = "qup00";
>> 1535 };
1841 }; 1536 };
1842 1537
1843 qup_spi6_cs_gpio: qup !! 1538 qup_i2c1_default: qup-i2c1-default {
1844 pins = "gpio6 !! 1539 pinmux {
1845 function = "g !! 1540 pins = "gpio0", "gpio1";
>> 1541 function = "qup01";
>> 1542 };
1846 }; 1543 };
1847 1544
1848 qup_spi8_spi: qup-spi !! 1545 qup_i2c2_default: qup-i2c2-default {
1849 pins = "gpio4 !! 1546 pinmux {
1850 function = "q !! 1547 pins = "gpio15", "gpio16";
>> 1548 function = "qup02_i2c";
>> 1549 };
1851 }; 1550 };
1852 1551
1853 qup_spi8_cs: qup-spi8 !! 1552 qup_i2c3_default: qup-i2c3-default {
1854 pins = "gpio4 !! 1553 pinmux {
1855 function = "q !! 1554 pins = "gpio38", "gpio39";
>> 1555 function = "qup03";
>> 1556 };
1856 }; 1557 };
1857 1558
1858 qup_spi8_cs_gpio: qup !! 1559 qup_i2c4_default: qup-i2c4-default {
1859 pins = "gpio4 !! 1560 pinmux {
1860 function = "g !! 1561 pins = "gpio115", "gpio116";
>> 1562 function = "qup04_i2c";
>> 1563 };
1861 }; 1564 };
1862 1565
1863 qup_spi10_spi: qup-sp !! 1566 qup_i2c5_default: qup-i2c5-default {
1864 pins = "gpio8 !! 1567 pinmux {
1865 function = "q !! 1568 pins = "gpio25", "gpio26";
>> 1569 function = "qup05";
>> 1570 };
1866 }; 1571 };
1867 1572
1868 qup_spi10_cs: qup-spi !! 1573 qup_i2c6_default: qup-i2c6-default {
1869 pins = "gpio8 !! 1574 pinmux {
1870 function = "q !! 1575 pins = "gpio59", "gpio60";
>> 1576 function = "qup10";
>> 1577 };
1871 }; 1578 };
1872 1579
1873 qup_spi10_cs_gpio: qu !! 1580 qup_i2c7_default: qup-i2c7-default {
1874 pins = "gpio8 !! 1581 pinmux {
1875 function = "g !! 1582 pins = "gpio6", "gpio7";
>> 1583 function = "qup11_i2c";
>> 1584 };
1876 }; 1585 };
1877 1586
1878 qup_spi11_spi: qup-sp !! 1587 qup_i2c8_default: qup-i2c8-default {
1879 pins = "gpio5 !! 1588 pinmux {
1880 function = "q !! 1589 pins = "gpio42", "gpio43";
>> 1590 function = "qup12";
>> 1591 };
1881 }; 1592 };
1882 1593
1883 qup_spi11_cs: qup-spi !! 1594 qup_i2c9_default: qup-i2c9-default {
1884 pins = "gpio5 !! 1595 pinmux {
1885 function = "q !! 1596 pins = "gpio46", "gpio47";
>> 1597 function = "qup13_i2c";
>> 1598 };
1886 }; 1599 };
1887 1600
1888 qup_spi11_cs_gpio: qu !! 1601 qup_i2c10_default: qup-i2c10-default {
1889 pins = "gpio5 !! 1602 pinmux {
1890 function = "g !! 1603 pins = "gpio86", "gpio87";
>> 1604 function = "qup14";
>> 1605 };
1891 }; 1606 };
1892 1607
1893 qup_uart0_default: qu !! 1608 qup_i2c11_default: qup-i2c11-default {
1894 qup_uart0_cts !! 1609 pinmux {
1895 pins !! 1610 pins = "gpio53", "gpio54";
1896 funct !! 1611 function = "qup15";
1897 }; 1612 };
>> 1613 };
1898 1614
1899 qup_uart0_rts !! 1615 qup_spi0_default: qup-spi0-default {
1900 pins !! 1616 pinmux {
>> 1617 pins = "gpio34", "gpio35",
>> 1618 "gpio36", "gpio37";
1901 funct 1619 function = "qup00";
1902 }; 1620 };
>> 1621 };
1903 1622
1904 qup_uart0_tx: !! 1623 qup_spi0_cs_gpio: qup-spi0-cs-gpio {
1905 pins !! 1624 pinmux {
>> 1625 pins = "gpio34", "gpio35",
>> 1626 "gpio36";
1906 funct 1627 function = "qup00";
1907 }; 1628 };
1908 1629
1909 qup_uart0_rx: !! 1630 pinmux-cs {
1910 pins 1631 pins = "gpio37";
1911 funct !! 1632 function = "gpio";
1912 }; 1633 };
1913 }; 1634 };
1914 1635
1915 qup_uart1_default: qu !! 1636 qup_spi1_default: qup-spi1-default {
1916 qup_uart1_cts !! 1637 pinmux {
1917 pins !! 1638 pins = "gpio0", "gpio1",
>> 1639 "gpio2", "gpio3";
1918 funct 1640 function = "qup01";
1919 }; 1641 };
>> 1642 };
1920 1643
1921 qup_uart1_rts !! 1644 qup_spi1_cs_gpio: qup-spi1-cs-gpio {
1922 pins !! 1645 pinmux {
>> 1646 pins = "gpio0", "gpio1",
>> 1647 "gpio2";
1923 funct 1648 function = "qup01";
1924 }; 1649 };
1925 1650
1926 qup_uart1_tx: !! 1651 pinmux-cs {
1927 pins !! 1652 pins = "gpio3";
1928 funct !! 1653 function = "gpio";
1929 }; 1654 };
>> 1655 };
1930 1656
1931 qup_uart1_rx: !! 1657 qup_spi3_default: qup-spi3-default {
1932 pins !! 1658 pinmux {
1933 funct !! 1659 pins = "gpio38", "gpio39",
>> 1660 "gpio40", "gpio41";
>> 1661 function = "qup03";
1934 }; 1662 };
1935 }; 1663 };
1936 1664
1937 qup_uart2_default: qu !! 1665 qup_spi3_cs_gpio: qup-spi3-cs-gpio {
1938 qup_uart2_tx: !! 1666 pinmux {
1939 pins !! 1667 pins = "gpio38", "gpio39",
1940 funct !! 1668 "gpio40";
>> 1669 function = "qup03";
1941 }; 1670 };
1942 1671
1943 qup_uart2_rx: !! 1672 pinmux-cs {
1944 pins !! 1673 pins = "gpio41";
1945 funct !! 1674 function = "gpio";
1946 }; 1675 };
1947 }; 1676 };
1948 1677
1949 qup_uart3_default: qu !! 1678 qup_spi5_default: qup-spi5-default {
1950 qup_uart3_cts !! 1679 pinmux {
1951 pins !! 1680 pins = "gpio25", "gpio26",
1952 funct !! 1681 "gpio27", "gpio28";
>> 1682 function = "qup05";
1953 }; 1683 };
>> 1684 };
1954 1685
1955 qup_uart3_rts !! 1686 qup_spi5_cs_gpio: qup-spi5-cs-gpio {
1956 pins !! 1687 pinmux {
1957 funct !! 1688 pins = "gpio25", "gpio26",
>> 1689 "gpio27";
>> 1690 function = "qup05";
1958 }; 1691 };
1959 1692
1960 qup_uart3_tx: !! 1693 pinmux-cs {
1961 pins !! 1694 pins = "gpio28";
1962 funct !! 1695 function = "gpio";
1963 }; 1696 };
>> 1697 };
1964 1698
1965 qup_uart3_rx: !! 1699 qup_spi6_default: qup-spi6-default {
1966 pins !! 1700 pinmux {
1967 funct !! 1701 pins = "gpio59", "gpio60",
>> 1702 "gpio61", "gpio62";
>> 1703 function = "qup10";
1968 }; 1704 };
1969 }; 1705 };
1970 1706
1971 qup_uart4_default: qu !! 1707 qup_spi6_cs_gpio: qup-spi6-cs-gpio {
1972 qup_uart4_tx: !! 1708 pinmux {
1973 pins !! 1709 pins = "gpio59", "gpio60",
1974 funct !! 1710 "gpio61";
>> 1711 function = "qup10";
1975 }; 1712 };
1976 1713
1977 qup_uart4_rx: !! 1714 pinmux-cs {
1978 pins !! 1715 pins = "gpio62";
1979 funct !! 1716 function = "gpio";
1980 }; 1717 };
1981 }; 1718 };
1982 1719
1983 qup_uart5_default: qu !! 1720 qup_spi8_default: qup-spi8-default {
1984 qup_uart5_cts !! 1721 pinmux {
1985 pins !! 1722 pins = "gpio42", "gpio43",
1986 funct !! 1723 "gpio44", "gpio45";
1987 }; !! 1724 function = "qup12";
1988 <<
1989 qup_uart5_rts <<
1990 pins <<
1991 funct <<
1992 }; 1725 };
>> 1726 };
1993 1727
1994 qup_uart5_tx: !! 1728 qup_spi8_cs_gpio: qup-spi8-cs-gpio {
1995 pins !! 1729 pinmux {
1996 funct !! 1730 pins = "gpio42", "gpio43",
>> 1731 "gpio44";
>> 1732 function = "qup12";
1997 }; 1733 };
1998 1734
1999 qup_uart5_rx: !! 1735 pinmux-cs {
2000 pins !! 1736 pins = "gpio45";
2001 funct !! 1737 function = "gpio";
2002 }; 1738 };
2003 }; 1739 };
2004 1740
2005 qup_uart6_default: qu !! 1741 qup_spi10_default: qup-spi10-default {
2006 qup_uart6_cts !! 1742 pinmux {
2007 pins !! 1743 pins = "gpio86", "gpio87",
2008 funct !! 1744 "gpio88", "gpio89";
>> 1745 function = "qup14";
2009 }; 1746 };
>> 1747 };
2010 1748
2011 qup_uart6_rts !! 1749 qup_spi10_cs_gpio: qup-spi10-cs-gpio {
2012 pins !! 1750 pinmux {
2013 funct !! 1751 pins = "gpio86", "gpio87",
>> 1752 "gpio88";
>> 1753 function = "qup14";
2014 }; 1754 };
2015 1755
2016 qup_uart6_tx: !! 1756 pinmux-cs {
2017 pins !! 1757 pins = "gpio89";
2018 funct !! 1758 function = "gpio";
2019 }; 1759 };
>> 1760 };
2020 1761
2021 qup_uart6_rx: !! 1762 qup_spi11_default: qup-spi11-default {
2022 pins !! 1763 pinmux {
2023 funct !! 1764 pins = "gpio53", "gpio54",
>> 1765 "gpio55", "gpio56";
>> 1766 function = "qup15";
2024 }; 1767 };
2025 }; 1768 };
2026 1769
2027 qup_uart7_default: qu !! 1770 qup_spi11_cs_gpio: qup-spi11-cs-gpio {
2028 qup_uart7_tx: !! 1771 pinmux {
2029 pins !! 1772 pins = "gpio53", "gpio54",
2030 funct !! 1773 "gpio55";
>> 1774 function = "qup15";
2031 }; 1775 };
2032 1776
2033 qup_uart7_rx: !! 1777 pinmux-cs {
2034 pins !! 1778 pins = "gpio56";
2035 funct !! 1779 function = "gpio";
2036 }; 1780 };
2037 }; 1781 };
2038 1782
2039 qup_uart8_default: qu !! 1783 qup_uart0_default: qup-uart0-default {
2040 qup_uart8_tx: !! 1784 pinmux {
2041 pins !! 1785 pins = "gpio34", "gpio35",
2042 funct !! 1786 "gpio36", "gpio37";
>> 1787 function = "qup00";
2043 }; 1788 };
>> 1789 };
2044 1790
2045 qup_uart8_rx: !! 1791 qup_uart1_default: qup-uart1-default {
2046 pins !! 1792 pinmux {
2047 funct !! 1793 pins = "gpio0", "gpio1",
>> 1794 "gpio2", "gpio3";
>> 1795 function = "qup01";
2048 }; 1796 };
2049 }; 1797 };
2050 1798
2051 qup_uart9_default: qu !! 1799 qup_uart2_default: qup-uart2-default {
2052 qup_uart9_tx: !! 1800 pinmux {
2053 pins !! 1801 pins = "gpio15", "gpio16";
2054 funct !! 1802 function = "qup02_uart";
2055 }; 1803 };
>> 1804 };
2056 1805
2057 qup_uart9_rx: !! 1806 qup_uart3_default: qup-uart3-default {
2058 pins !! 1807 pinmux {
2059 funct !! 1808 pins = "gpio38", "gpio39",
>> 1809 "gpio40", "gpio41";
>> 1810 function = "qup03";
2060 }; 1811 };
2061 }; 1812 };
2062 1813
2063 qup_uart10_default: q !! 1814 qup_uart4_default: qup-uart4-default {
2064 qup_uart10_ct !! 1815 pinmux {
2065 pins !! 1816 pins = "gpio115", "gpio116";
2066 funct !! 1817 function = "qup04_uart";
2067 }; 1818 };
>> 1819 };
2068 1820
2069 qup_uart10_rt !! 1821 qup_uart5_default: qup-uart5-default {
2070 pins !! 1822 pinmux {
2071 funct !! 1823 pins = "gpio25", "gpio26",
>> 1824 "gpio27", "gpio28";
>> 1825 function = "qup05";
2072 }; 1826 };
>> 1827 };
2073 1828
2074 qup_uart10_tx !! 1829 qup_uart6_default: qup-uart6-default {
2075 pins !! 1830 pinmux {
2076 funct !! 1831 pins = "gpio59", "gpio60",
>> 1832 "gpio61", "gpio62";
>> 1833 function = "qup10";
2077 }; 1834 };
>> 1835 };
2078 1836
2079 qup_uart10_rx !! 1837 qup_uart7_default: qup-uart7-default {
2080 pins !! 1838 pinmux {
2081 funct !! 1839 pins = "gpio6", "gpio7";
>> 1840 function = "qup11_uart";
2082 }; 1841 };
2083 }; 1842 };
2084 1843
2085 qup_uart11_default: q !! 1844 qup_uart8_default: qup-uart8-default {
2086 qup_uart11_ct !! 1845 pinmux {
2087 pins !! 1846 pins = "gpio44", "gpio45";
2088 funct !! 1847 function = "qup12";
2089 }; 1848 };
>> 1849 };
2090 1850
2091 qup_uart11_rt !! 1851 qup_uart9_default: qup-uart9-default {
2092 pins !! 1852 pinmux {
2093 funct !! 1853 pins = "gpio46", "gpio47";
>> 1854 function = "qup13_uart";
2094 }; 1855 };
>> 1856 };
2095 1857
2096 qup_uart11_tx !! 1858 qup_uart10_default: qup-uart10-default {
2097 pins !! 1859 pinmux {
2098 funct !! 1860 pins = "gpio86", "gpio87",
>> 1861 "gpio88", "gpio89";
>> 1862 function = "qup14";
2099 }; 1863 };
>> 1864 };
2100 1865
2101 qup_uart11_rx !! 1866 qup_uart11_default: qup-uart11-default {
2102 pins !! 1867 pinmux {
>> 1868 pins = "gpio53", "gpio54",
>> 1869 "gpio55", "gpio56";
2103 funct 1870 function = "qup15";
2104 }; 1871 };
2105 }; 1872 };
2106 1873
2107 sec_mi2s_active: sec- !! 1874 sec_mi2s_active: sec-mi2s-active {
2108 pins = "gpio4 !! 1875 pinmux {
2109 function = "m !! 1876 pins = "gpio49", "gpio50", "gpio51";
2110 }; !! 1877 function = "mi2s_1";
2111 !! 1878 };
2112 pri_mi2s_active: pri- <<
2113 pins = "gpio5 <<
2114 function = "m <<
2115 }; 1879 };
2116 1880
2117 pri_mi2s_mclk_active: !! 1881 pri_mi2s_active: pri-mi2s-active {
2118 pins = "gpio5 !! 1882 pinmux {
2119 function = "l !! 1883 pins = "gpio53", "gpio54", "gpio55", "gpio56";
>> 1884 function = "mi2s_0";
>> 1885 };
2120 }; 1886 };
2121 1887
2122 ter_mi2s_active: ter- !! 1888 pri_mi2s_mclk_active: pri-mi2s-mclk-active {
2123 pins = "gpio6 !! 1889 pinmux {
2124 function = "m !! 1890 pins = "gpio57";
>> 1891 function = "lpass_ext";
>> 1892 };
2125 }; 1893 };
2126 }; 1894 };
2127 1895
2128 remoteproc_mpss: remoteproc@4 1896 remoteproc_mpss: remoteproc@4080000 {
2129 compatible = "qcom,sc 1897 compatible = "qcom,sc7180-mpss-pas";
2130 reg = <0 0x04080000 0 !! 1898 reg = <0 0x04080000 0 0x4040>, <0 0x04180000 0 0x48>;
>> 1899 reg-names = "qdsp6", "rmb";
2131 1900
2132 interrupts-extended = 1901 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
2133 1902 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2134 1903 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2135 1904 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2136 1905 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
2137 1906 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
2138 interrupt-names = "wd 1907 interrupt-names = "wdog", "fatal", "ready", "handover",
2139 "st 1908 "stop-ack", "shutdown-ack";
2140 1909
2141 clocks = <&rpmhcc RPM !! 1910 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
2142 clock-names = "xo"; !! 1911 <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>,
>> 1912 <&gcc GCC_MSS_NAV_AXI_CLK>,
>> 1913 <&gcc GCC_MSS_SNOC_AXI_CLK>,
>> 1914 <&gcc GCC_MSS_MFAB_AXIS_CLK>,
>> 1915 <&rpmhcc RPMH_CXO_CLK>;
>> 1916 clock-names = "iface", "bus", "nav", "snoc_axi",
>> 1917 "mnoc_axi", "xo";
2143 1918
2144 power-domains = <&rpm 1919 power-domains = <&rpmhpd SC7180_CX>,
2145 <&rpm 1920 <&rpmhpd SC7180_MX>,
2146 <&rpm 1921 <&rpmhpd SC7180_MSS>;
2147 power-domain-names = 1922 power-domain-names = "cx", "mx", "mss";
2148 1923
2149 memory-region = <&mps 1924 memory-region = <&mpss_mem>;
2150 1925
2151 qcom,qmp = <&aoss_qmp 1926 qcom,qmp = <&aoss_qmp>;
2152 1927
2153 qcom,smem-states = <& 1928 qcom,smem-states = <&modem_smp2p_out 0>;
2154 qcom,smem-state-names 1929 qcom,smem-state-names = "stop";
2155 1930
>> 1931 resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
>> 1932 <&pdc_reset PDC_MODEM_SYNC_RESET>;
>> 1933 reset-names = "mss_restart", "pdc_reset";
>> 1934
>> 1935 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>;
>> 1936 qcom,spare-regs = <&tcsr_regs_2 0xb3e4>;
>> 1937
2156 status = "disabled"; 1938 status = "disabled";
2157 1939
2158 glink-edge { 1940 glink-edge {
2159 interrupts = 1941 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
2160 label = "mode 1942 label = "modem";
2161 qcom,remote-p 1943 qcom,remote-pid = <1>;
2162 mboxes = <&ap 1944 mboxes = <&apss_shared 12>;
2163 }; 1945 };
2164 }; 1946 };
2165 1947
2166 gpu: gpu@5000000 { 1948 gpu: gpu@5000000 {
2167 compatible = "qcom,ad 1949 compatible = "qcom,adreno-618.0", "qcom,adreno";
2168 reg = <0 0x05000000 0 1950 reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x1000>,
2169 <0 0x05061000 1951 <0 0x05061000 0 0x800>;
2170 reg-names = "kgsl_3d0 1952 reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc";
2171 interrupts = <GIC_SPI 1953 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2172 iommus = <&adreno_smm 1954 iommus = <&adreno_smmu 0>;
2173 operating-points-v2 = 1955 operating-points-v2 = <&gpu_opp_table>;
2174 qcom,gmu = <&gmu>; 1956 qcom,gmu = <&gmu>;
2175 1957
2176 #cooling-cells = <2>; 1958 #cooling-cells = <2>;
2177 1959
2178 nvmem-cells = <&gpu_s 1960 nvmem-cells = <&gpu_speed_bin>;
2179 nvmem-cell-names = "s 1961 nvmem-cell-names = "speed_bin";
2180 1962
2181 interconnects = <&gem 1963 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
2182 interconnect-names = 1964 interconnect-names = "gfx-mem";
2183 1965
2184 gpu_opp_table: opp-ta 1966 gpu_opp_table: opp-table {
2185 compatible = 1967 compatible = "operating-points-v2";
2186 1968
2187 opp-825000000 1969 opp-825000000 {
2188 opp-h 1970 opp-hz = /bits/ 64 <825000000>;
2189 opp-l 1971 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2190 opp-p 1972 opp-peak-kBps = <8532000>;
2191 opp-s 1973 opp-supported-hw = <0x04>;
2192 }; 1974 };
2193 1975
2194 opp-800000000 1976 opp-800000000 {
2195 opp-h 1977 opp-hz = /bits/ 64 <800000000>;
2196 opp-l 1978 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2197 opp-p 1979 opp-peak-kBps = <8532000>;
2198 opp-s 1980 opp-supported-hw = <0x07>;
2199 }; 1981 };
2200 1982
2201 opp-650000000 1983 opp-650000000 {
2202 opp-h 1984 opp-hz = /bits/ 64 <650000000>;
2203 opp-l 1985 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2204 opp-p 1986 opp-peak-kBps = <7216000>;
2205 opp-s 1987 opp-supported-hw = <0x07>;
2206 }; 1988 };
2207 1989
2208 opp-565000000 1990 opp-565000000 {
2209 opp-h 1991 opp-hz = /bits/ 64 <565000000>;
2210 opp-l 1992 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2211 opp-p 1993 opp-peak-kBps = <5412000>;
2212 opp-s 1994 opp-supported-hw = <0x07>;
2213 }; 1995 };
2214 1996
2215 opp-430000000 1997 opp-430000000 {
2216 opp-h 1998 opp-hz = /bits/ 64 <430000000>;
2217 opp-l 1999 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2218 opp-p 2000 opp-peak-kBps = <5412000>;
2219 opp-s 2001 opp-supported-hw = <0x07>;
2220 }; 2002 };
2221 2003
2222 opp-355000000 2004 opp-355000000 {
2223 opp-h 2005 opp-hz = /bits/ 64 <355000000>;
2224 opp-l 2006 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2225 opp-p 2007 opp-peak-kBps = <3072000>;
2226 opp-s 2008 opp-supported-hw = <0x07>;
2227 }; 2009 };
2228 2010
2229 opp-267000000 2011 opp-267000000 {
2230 opp-h 2012 opp-hz = /bits/ 64 <267000000>;
2231 opp-l 2013 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2232 opp-p 2014 opp-peak-kBps = <3072000>;
2233 opp-s 2015 opp-supported-hw = <0x07>;
2234 }; 2016 };
2235 2017
2236 opp-180000000 2018 opp-180000000 {
2237 opp-h 2019 opp-hz = /bits/ 64 <180000000>;
2238 opp-l 2020 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2239 opp-p 2021 opp-peak-kBps = <1804000>;
2240 opp-s 2022 opp-supported-hw = <0x07>;
2241 }; 2023 };
2242 }; 2024 };
2243 }; 2025 };
2244 2026
2245 adreno_smmu: iommu@5040000 { 2027 adreno_smmu: iommu@5040000 {
2246 compatible = "qcom,sc 2028 compatible = "qcom,sc7180-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
2247 reg = <0 0x05040000 0 2029 reg = <0 0x05040000 0 0x10000>;
2248 #iommu-cells = <1>; 2030 #iommu-cells = <1>;
2249 #global-interrupts = 2031 #global-interrupts = <2>;
2250 interrupts = <GIC_SPI 2032 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
2251 <GIC_ 2033 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
2252 <GIC_ 2034 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
2253 <GIC_ 2035 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
2254 <GIC_ 2036 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
2255 <GIC_ 2037 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
2256 <GIC_ 2038 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
2257 <GIC_ 2039 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
2258 <GIC_ 2040 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
2259 <GIC_ 2041 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
2260 2042
2261 clocks = <&gcc GCC_GP 2043 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2262 <&gcc GCC_GPU 2044 <&gcc GCC_GPU_CFG_AHB_CLK>;
2263 clock-names = "bus", 2045 clock-names = "bus", "iface";
2264 2046
2265 power-domains = <&gpu 2047 power-domains = <&gpucc CX_GDSC>;
2266 }; 2048 };
2267 2049
2268 gmu: gmu@506a000 { 2050 gmu: gmu@506a000 {
2269 compatible = "qcom,ad 2051 compatible = "qcom,adreno-gmu-618.0", "qcom,adreno-gmu";
2270 reg = <0 0x0506a000 0 2052 reg = <0 0x0506a000 0 0x31000>, <0 0x0b290000 0 0x10000>,
2271 <0 0x0b490000 2053 <0 0x0b490000 0 0x10000>;
2272 reg-names = "gmu", "g 2054 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
2273 interrupts = <GIC_SPI 2055 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2274 <GIC_SPI 3 2056 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2275 interrupt-names = "hf 2057 interrupt-names = "hfi", "gmu";
2276 clocks = <&gpucc GPU_ 2058 clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
2277 <&gpucc GPU_CC 2059 <&gpucc GPU_CC_CXO_CLK>,
2278 <&gcc GCC_DDRS 2060 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2279 <&gcc GCC_GPU_ 2061 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
2280 clock-names = "gmu", 2062 clock-names = "gmu", "cxo", "axi", "memnoc";
2281 power-domains = <&gpu 2063 power-domains = <&gpucc CX_GDSC>, <&gpucc GX_GDSC>;
2282 power-domain-names = 2064 power-domain-names = "cx", "gx";
2283 iommus = <&adreno_smm 2065 iommus = <&adreno_smmu 5>;
2284 operating-points-v2 = 2066 operating-points-v2 = <&gmu_opp_table>;
2285 2067
2286 gmu_opp_table: opp-ta 2068 gmu_opp_table: opp-table {
2287 compatible = 2069 compatible = "operating-points-v2";
2288 2070
2289 opp-200000000 2071 opp-200000000 {
2290 opp-h 2072 opp-hz = /bits/ 64 <200000000>;
2291 opp-l 2073 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2292 }; 2074 };
2293 }; 2075 };
2294 }; 2076 };
2295 2077
2296 gpucc: clock-controller@50900 2078 gpucc: clock-controller@5090000 {
2297 compatible = "qcom,sc 2079 compatible = "qcom,sc7180-gpucc";
2298 reg = <0 0x05090000 0 2080 reg = <0 0x05090000 0 0x9000>;
2299 clocks = <&rpmhcc RPM 2081 clocks = <&rpmhcc RPMH_CXO_CLK>,
2300 <&gcc GCC_GP 2082 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2301 <&gcc GCC_GP 2083 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2302 clock-names = "bi_tcx 2084 clock-names = "bi_tcxo",
2303 "gcc_gp 2085 "gcc_gpu_gpll0_clk_src",
2304 "gcc_gp 2086 "gcc_gpu_gpll0_div_clk_src";
2305 #clock-cells = <1>; 2087 #clock-cells = <1>;
2306 #reset-cells = <1>; 2088 #reset-cells = <1>;
2307 #power-domain-cells = 2089 #power-domain-cells = <1>;
2308 }; 2090 };
2309 2091
2310 dma@10a2000 { <<
2311 compatible = "qcom,sc <<
2312 reg = <0x0 0x010a2000 <<
2313 <0x0 0x010ae000 <<
2314 status = "disabled"; <<
2315 }; <<
2316 <<
2317 stm@6002000 { 2092 stm@6002000 {
2318 compatible = "arm,cor 2093 compatible = "arm,coresight-stm", "arm,primecell";
2319 reg = <0 0x06002000 0 2094 reg = <0 0x06002000 0 0x1000>,
2320 <0 0x16280000 0 2095 <0 0x16280000 0 0x180000>;
2321 reg-names = "stm-base 2096 reg-names = "stm-base", "stm-stimulus-base";
2322 2097
2323 clocks = <&aoss_qmp>; 2098 clocks = <&aoss_qmp>;
2324 clock-names = "apb_pc 2099 clock-names = "apb_pclk";
2325 2100
2326 out-ports { 2101 out-ports {
2327 port { 2102 port {
2328 stm_o 2103 stm_out: endpoint {
2329 2104 remote-endpoint = <&funnel0_in7>;
2330 }; 2105 };
2331 }; 2106 };
2332 }; 2107 };
2333 }; 2108 };
2334 2109
2335 funnel@6041000 { 2110 funnel@6041000 {
2336 compatible = "arm,cor 2111 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2337 reg = <0 0x06041000 0 2112 reg = <0 0x06041000 0 0x1000>;
2338 2113
2339 clocks = <&aoss_qmp>; 2114 clocks = <&aoss_qmp>;
2340 clock-names = "apb_pc 2115 clock-names = "apb_pclk";
2341 2116
2342 out-ports { 2117 out-ports {
2343 port { 2118 port {
2344 funne 2119 funnel0_out: endpoint {
2345 2120 remote-endpoint = <&merge_funnel_in0>;
2346 }; 2121 };
2347 }; 2122 };
2348 }; 2123 };
2349 2124
2350 in-ports { 2125 in-ports {
2351 #address-cell 2126 #address-cells = <1>;
2352 #size-cells = 2127 #size-cells = <0>;
2353 2128
2354 port@7 { 2129 port@7 {
2355 reg = 2130 reg = <7>;
2356 funne 2131 funnel0_in7: endpoint {
2357 2132 remote-endpoint = <&stm_out>;
2358 }; 2133 };
2359 }; 2134 };
2360 }; 2135 };
2361 }; 2136 };
2362 2137
2363 funnel@6042000 { 2138 funnel@6042000 {
2364 compatible = "arm,cor 2139 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2365 reg = <0 0x06042000 0 2140 reg = <0 0x06042000 0 0x1000>;
2366 2141
2367 clocks = <&aoss_qmp>; 2142 clocks = <&aoss_qmp>;
2368 clock-names = "apb_pc 2143 clock-names = "apb_pclk";
2369 2144
2370 out-ports { 2145 out-ports {
2371 port { 2146 port {
2372 funne 2147 funnel1_out: endpoint {
2373 2148 remote-endpoint = <&merge_funnel_in1>;
2374 }; 2149 };
2375 }; 2150 };
2376 }; 2151 };
2377 2152
2378 in-ports { 2153 in-ports {
2379 #address-cell 2154 #address-cells = <1>;
2380 #size-cells = 2155 #size-cells = <0>;
2381 2156
2382 port@4 { 2157 port@4 {
2383 reg = 2158 reg = <4>;
2384 funne 2159 funnel1_in4: endpoint {
2385 2160 remote-endpoint = <&apss_merge_funnel_out>;
2386 }; 2161 };
2387 }; 2162 };
2388 }; 2163 };
2389 }; 2164 };
2390 2165
2391 funnel@6045000 { 2166 funnel@6045000 {
2392 compatible = "arm,cor 2167 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2393 reg = <0 0x06045000 0 2168 reg = <0 0x06045000 0 0x1000>;
2394 2169
2395 clocks = <&aoss_qmp>; 2170 clocks = <&aoss_qmp>;
2396 clock-names = "apb_pc 2171 clock-names = "apb_pclk";
2397 2172
2398 out-ports { 2173 out-ports {
2399 port { 2174 port {
2400 merge 2175 merge_funnel_out: endpoint {
2401 2176 remote-endpoint = <&swao_funnel_in>;
2402 }; 2177 };
2403 }; 2178 };
2404 }; 2179 };
2405 2180
2406 in-ports { 2181 in-ports {
2407 #address-cell 2182 #address-cells = <1>;
2408 #size-cells = 2183 #size-cells = <0>;
2409 2184
2410 port@0 { 2185 port@0 {
2411 reg = 2186 reg = <0>;
2412 merge 2187 merge_funnel_in0: endpoint {
2413 2188 remote-endpoint = <&funnel0_out>;
2414 }; 2189 };
2415 }; 2190 };
2416 2191
2417 port@1 { 2192 port@1 {
2418 reg = 2193 reg = <1>;
2419 merge 2194 merge_funnel_in1: endpoint {
2420 2195 remote-endpoint = <&funnel1_out>;
2421 }; 2196 };
2422 }; 2197 };
2423 }; 2198 };
2424 }; 2199 };
2425 2200
2426 replicator@6046000 { 2201 replicator@6046000 {
2427 compatible = "arm,cor 2202 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2428 reg = <0 0x06046000 0 2203 reg = <0 0x06046000 0 0x1000>;
2429 2204
2430 clocks = <&aoss_qmp>; 2205 clocks = <&aoss_qmp>;
2431 clock-names = "apb_pc 2206 clock-names = "apb_pclk";
2432 2207
2433 out-ports { 2208 out-ports {
2434 port { 2209 port {
2435 repli 2210 replicator_out: endpoint {
2436 2211 remote-endpoint = <&etr_in>;
2437 }; 2212 };
2438 }; 2213 };
2439 }; 2214 };
2440 2215
2441 in-ports { 2216 in-ports {
2442 port { 2217 port {
2443 repli 2218 replicator_in: endpoint {
2444 2219 remote-endpoint = <&swao_replicator_out>;
2445 }; 2220 };
2446 }; 2221 };
2447 }; 2222 };
2448 }; 2223 };
2449 2224
2450 etr@6048000 { 2225 etr@6048000 {
2451 compatible = "arm,cor 2226 compatible = "arm,coresight-tmc", "arm,primecell";
2452 reg = <0 0x06048000 0 2227 reg = <0 0x06048000 0 0x1000>;
2453 iommus = <&apps_smmu 2228 iommus = <&apps_smmu 0x04a0 0x20>;
2454 2229
2455 clocks = <&aoss_qmp>; 2230 clocks = <&aoss_qmp>;
2456 clock-names = "apb_pc 2231 clock-names = "apb_pclk";
2457 arm,scatter-gather; 2232 arm,scatter-gather;
2458 2233
2459 in-ports { 2234 in-ports {
2460 port { 2235 port {
2461 etr_i 2236 etr_in: endpoint {
2462 2237 remote-endpoint = <&replicator_out>;
2463 }; 2238 };
2464 }; 2239 };
2465 }; 2240 };
2466 }; 2241 };
2467 2242
2468 funnel@6b04000 { 2243 funnel@6b04000 {
2469 compatible = "arm,cor 2244 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2470 reg = <0 0x06b04000 0 2245 reg = <0 0x06b04000 0 0x1000>;
2471 2246
2472 clocks = <&aoss_qmp>; 2247 clocks = <&aoss_qmp>;
2473 clock-names = "apb_pc 2248 clock-names = "apb_pclk";
2474 2249
2475 out-ports { 2250 out-ports {
2476 port { 2251 port {
2477 swao_ 2252 swao_funnel_out: endpoint {
2478 2253 remote-endpoint = <&etf_in>;
2479 }; 2254 };
2480 }; 2255 };
2481 }; 2256 };
2482 2257
2483 in-ports { 2258 in-ports {
2484 #address-cell 2259 #address-cells = <1>;
2485 #size-cells = 2260 #size-cells = <0>;
2486 2261
2487 port@7 { 2262 port@7 {
2488 reg = 2263 reg = <7>;
2489 swao_ 2264 swao_funnel_in: endpoint {
2490 2265 remote-endpoint = <&merge_funnel_out>;
2491 }; 2266 };
2492 }; 2267 };
2493 }; 2268 };
2494 }; 2269 };
2495 2270
2496 etf@6b05000 { 2271 etf@6b05000 {
2497 compatible = "arm,cor 2272 compatible = "arm,coresight-tmc", "arm,primecell";
2498 reg = <0 0x06b05000 0 2273 reg = <0 0x06b05000 0 0x1000>;
2499 2274
2500 clocks = <&aoss_qmp>; 2275 clocks = <&aoss_qmp>;
2501 clock-names = "apb_pc 2276 clock-names = "apb_pclk";
2502 2277
2503 out-ports { 2278 out-ports {
2504 port { 2279 port {
2505 etf_o 2280 etf_out: endpoint {
2506 2281 remote-endpoint = <&swao_replicator_in>;
2507 }; 2282 };
2508 }; 2283 };
2509 }; 2284 };
2510 2285
2511 in-ports { 2286 in-ports {
2512 port { 2287 port {
2513 etf_i 2288 etf_in: endpoint {
2514 2289 remote-endpoint = <&swao_funnel_out>;
2515 }; 2290 };
2516 }; 2291 };
2517 }; 2292 };
2518 }; 2293 };
2519 2294
2520 replicator@6b06000 { 2295 replicator@6b06000 {
2521 compatible = "arm,cor 2296 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2522 reg = <0 0x06b06000 0 2297 reg = <0 0x06b06000 0 0x1000>;
2523 2298
2524 clocks = <&aoss_qmp>; 2299 clocks = <&aoss_qmp>;
2525 clock-names = "apb_pc 2300 clock-names = "apb_pclk";
2526 qcom,replicator-loses 2301 qcom,replicator-loses-context;
2527 2302
2528 out-ports { 2303 out-ports {
2529 port { 2304 port {
2530 swao_ 2305 swao_replicator_out: endpoint {
2531 2306 remote-endpoint = <&replicator_in>;
2532 }; 2307 };
2533 }; 2308 };
2534 }; 2309 };
2535 2310
2536 in-ports { 2311 in-ports {
2537 port { 2312 port {
2538 swao_ 2313 swao_replicator_in: endpoint {
2539 2314 remote-endpoint = <&etf_out>;
2540 }; 2315 };
2541 }; 2316 };
2542 }; 2317 };
2543 }; 2318 };
2544 2319
2545 etm@7040000 { 2320 etm@7040000 {
2546 compatible = "arm,cor 2321 compatible = "arm,coresight-etm4x", "arm,primecell";
2547 reg = <0 0x07040000 0 2322 reg = <0 0x07040000 0 0x1000>;
2548 2323
2549 cpu = <&CPU0>; 2324 cpu = <&CPU0>;
2550 2325
2551 clocks = <&aoss_qmp>; 2326 clocks = <&aoss_qmp>;
2552 clock-names = "apb_pc 2327 clock-names = "apb_pclk";
2553 arm,coresight-loses-c 2328 arm,coresight-loses-context-with-cpu;
2554 qcom,skip-power-up; 2329 qcom,skip-power-up;
2555 2330
2556 out-ports { 2331 out-ports {
2557 port { 2332 port {
2558 etm0_ 2333 etm0_out: endpoint {
2559 2334 remote-endpoint = <&apss_funnel_in0>;
2560 }; 2335 };
2561 }; 2336 };
2562 }; 2337 };
2563 }; 2338 };
2564 2339
2565 etm@7140000 { 2340 etm@7140000 {
2566 compatible = "arm,cor 2341 compatible = "arm,coresight-etm4x", "arm,primecell";
2567 reg = <0 0x07140000 0 2342 reg = <0 0x07140000 0 0x1000>;
2568 2343
2569 cpu = <&CPU1>; 2344 cpu = <&CPU1>;
2570 2345
2571 clocks = <&aoss_qmp>; 2346 clocks = <&aoss_qmp>;
2572 clock-names = "apb_pc 2347 clock-names = "apb_pclk";
2573 arm,coresight-loses-c 2348 arm,coresight-loses-context-with-cpu;
2574 qcom,skip-power-up; 2349 qcom,skip-power-up;
2575 2350
2576 out-ports { 2351 out-ports {
2577 port { 2352 port {
2578 etm1_ 2353 etm1_out: endpoint {
2579 2354 remote-endpoint = <&apss_funnel_in1>;
2580 }; 2355 };
2581 }; 2356 };
2582 }; 2357 };
2583 }; 2358 };
2584 2359
2585 etm@7240000 { 2360 etm@7240000 {
2586 compatible = "arm,cor 2361 compatible = "arm,coresight-etm4x", "arm,primecell";
2587 reg = <0 0x07240000 0 2362 reg = <0 0x07240000 0 0x1000>;
2588 2363
2589 cpu = <&CPU2>; 2364 cpu = <&CPU2>;
2590 2365
2591 clocks = <&aoss_qmp>; 2366 clocks = <&aoss_qmp>;
2592 clock-names = "apb_pc 2367 clock-names = "apb_pclk";
2593 arm,coresight-loses-c 2368 arm,coresight-loses-context-with-cpu;
2594 qcom,skip-power-up; 2369 qcom,skip-power-up;
2595 2370
2596 out-ports { 2371 out-ports {
2597 port { 2372 port {
2598 etm2_ 2373 etm2_out: endpoint {
2599 2374 remote-endpoint = <&apss_funnel_in2>;
2600 }; 2375 };
2601 }; 2376 };
2602 }; 2377 };
2603 }; 2378 };
2604 2379
2605 etm@7340000 { 2380 etm@7340000 {
2606 compatible = "arm,cor 2381 compatible = "arm,coresight-etm4x", "arm,primecell";
2607 reg = <0 0x07340000 0 2382 reg = <0 0x07340000 0 0x1000>;
2608 2383
2609 cpu = <&CPU3>; 2384 cpu = <&CPU3>;
2610 2385
2611 clocks = <&aoss_qmp>; 2386 clocks = <&aoss_qmp>;
2612 clock-names = "apb_pc 2387 clock-names = "apb_pclk";
2613 arm,coresight-loses-c 2388 arm,coresight-loses-context-with-cpu;
2614 qcom,skip-power-up; 2389 qcom,skip-power-up;
2615 2390
2616 out-ports { 2391 out-ports {
2617 port { 2392 port {
2618 etm3_ 2393 etm3_out: endpoint {
2619 2394 remote-endpoint = <&apss_funnel_in3>;
2620 }; 2395 };
2621 }; 2396 };
2622 }; 2397 };
2623 }; 2398 };
2624 2399
2625 etm@7440000 { 2400 etm@7440000 {
2626 compatible = "arm,cor 2401 compatible = "arm,coresight-etm4x", "arm,primecell";
2627 reg = <0 0x07440000 0 2402 reg = <0 0x07440000 0 0x1000>;
2628 2403
2629 cpu = <&CPU4>; 2404 cpu = <&CPU4>;
2630 2405
2631 clocks = <&aoss_qmp>; 2406 clocks = <&aoss_qmp>;
2632 clock-names = "apb_pc 2407 clock-names = "apb_pclk";
2633 arm,coresight-loses-c 2408 arm,coresight-loses-context-with-cpu;
2634 qcom,skip-power-up; 2409 qcom,skip-power-up;
2635 2410
2636 out-ports { 2411 out-ports {
2637 port { 2412 port {
2638 etm4_ 2413 etm4_out: endpoint {
2639 2414 remote-endpoint = <&apss_funnel_in4>;
2640 }; 2415 };
2641 }; 2416 };
2642 }; 2417 };
2643 }; 2418 };
2644 2419
2645 etm@7540000 { 2420 etm@7540000 {
2646 compatible = "arm,cor 2421 compatible = "arm,coresight-etm4x", "arm,primecell";
2647 reg = <0 0x07540000 0 2422 reg = <0 0x07540000 0 0x1000>;
2648 2423
2649 cpu = <&CPU5>; 2424 cpu = <&CPU5>;
2650 2425
2651 clocks = <&aoss_qmp>; 2426 clocks = <&aoss_qmp>;
2652 clock-names = "apb_pc 2427 clock-names = "apb_pclk";
2653 arm,coresight-loses-c 2428 arm,coresight-loses-context-with-cpu;
2654 qcom,skip-power-up; 2429 qcom,skip-power-up;
2655 2430
2656 out-ports { 2431 out-ports {
2657 port { 2432 port {
2658 etm5_ 2433 etm5_out: endpoint {
2659 2434 remote-endpoint = <&apss_funnel_in5>;
2660 }; 2435 };
2661 }; 2436 };
2662 }; 2437 };
2663 }; 2438 };
2664 2439
2665 etm@7640000 { 2440 etm@7640000 {
2666 compatible = "arm,cor 2441 compatible = "arm,coresight-etm4x", "arm,primecell";
2667 reg = <0 0x07640000 0 2442 reg = <0 0x07640000 0 0x1000>;
2668 2443
2669 cpu = <&CPU6>; 2444 cpu = <&CPU6>;
2670 2445
2671 clocks = <&aoss_qmp>; 2446 clocks = <&aoss_qmp>;
2672 clock-names = "apb_pc 2447 clock-names = "apb_pclk";
2673 arm,coresight-loses-c 2448 arm,coresight-loses-context-with-cpu;
2674 qcom,skip-power-up; 2449 qcom,skip-power-up;
2675 2450
2676 out-ports { 2451 out-ports {
2677 port { 2452 port {
2678 etm6_ 2453 etm6_out: endpoint {
2679 2454 remote-endpoint = <&apss_funnel_in6>;
2680 }; 2455 };
2681 }; 2456 };
2682 }; 2457 };
2683 }; 2458 };
2684 2459
2685 etm@7740000 { 2460 etm@7740000 {
2686 compatible = "arm,cor 2461 compatible = "arm,coresight-etm4x", "arm,primecell";
2687 reg = <0 0x07740000 0 2462 reg = <0 0x07740000 0 0x1000>;
2688 2463
2689 cpu = <&CPU7>; 2464 cpu = <&CPU7>;
2690 2465
2691 clocks = <&aoss_qmp>; 2466 clocks = <&aoss_qmp>;
2692 clock-names = "apb_pc 2467 clock-names = "apb_pclk";
2693 arm,coresight-loses-c 2468 arm,coresight-loses-context-with-cpu;
2694 qcom,skip-power-up; 2469 qcom,skip-power-up;
2695 2470
2696 out-ports { 2471 out-ports {
2697 port { 2472 port {
2698 etm7_ 2473 etm7_out: endpoint {
2699 2474 remote-endpoint = <&apss_funnel_in7>;
2700 }; 2475 };
2701 }; 2476 };
2702 }; 2477 };
2703 }; 2478 };
2704 2479
2705 funnel@7800000 { /* APSS Funn 2480 funnel@7800000 { /* APSS Funnel */
2706 compatible = "arm,cor 2481 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2707 reg = <0 0x07800000 0 2482 reg = <0 0x07800000 0 0x1000>;
2708 2483
2709 clocks = <&aoss_qmp>; 2484 clocks = <&aoss_qmp>;
2710 clock-names = "apb_pc 2485 clock-names = "apb_pclk";
2711 2486
2712 out-ports { 2487 out-ports {
2713 port { 2488 port {
2714 apss_ 2489 apss_funnel_out: endpoint {
2715 2490 remote-endpoint = <&apss_merge_funnel_in>;
2716 }; 2491 };
2717 }; 2492 };
2718 }; 2493 };
2719 2494
2720 in-ports { 2495 in-ports {
2721 #address-cell 2496 #address-cells = <1>;
2722 #size-cells = 2497 #size-cells = <0>;
2723 2498
2724 port@0 { 2499 port@0 {
2725 reg = 2500 reg = <0>;
2726 apss_ 2501 apss_funnel_in0: endpoint {
2727 2502 remote-endpoint = <&etm0_out>;
2728 }; 2503 };
2729 }; 2504 };
2730 2505
2731 port@1 { 2506 port@1 {
2732 reg = 2507 reg = <1>;
2733 apss_ 2508 apss_funnel_in1: endpoint {
2734 2509 remote-endpoint = <&etm1_out>;
2735 }; 2510 };
2736 }; 2511 };
2737 2512
2738 port@2 { 2513 port@2 {
2739 reg = 2514 reg = <2>;
2740 apss_ 2515 apss_funnel_in2: endpoint {
2741 2516 remote-endpoint = <&etm2_out>;
2742 }; 2517 };
2743 }; 2518 };
2744 2519
2745 port@3 { 2520 port@3 {
2746 reg = 2521 reg = <3>;
2747 apss_ 2522 apss_funnel_in3: endpoint {
2748 2523 remote-endpoint = <&etm3_out>;
2749 }; 2524 };
2750 }; 2525 };
2751 2526
2752 port@4 { 2527 port@4 {
2753 reg = 2528 reg = <4>;
2754 apss_ 2529 apss_funnel_in4: endpoint {
2755 2530 remote-endpoint = <&etm4_out>;
2756 }; 2531 };
2757 }; 2532 };
2758 2533
2759 port@5 { 2534 port@5 {
2760 reg = 2535 reg = <5>;
2761 apss_ 2536 apss_funnel_in5: endpoint {
2762 2537 remote-endpoint = <&etm5_out>;
2763 }; 2538 };
2764 }; 2539 };
2765 2540
2766 port@6 { 2541 port@6 {
2767 reg = 2542 reg = <6>;
2768 apss_ 2543 apss_funnel_in6: endpoint {
2769 2544 remote-endpoint = <&etm6_out>;
2770 }; 2545 };
2771 }; 2546 };
2772 2547
2773 port@7 { 2548 port@7 {
2774 reg = 2549 reg = <7>;
2775 apss_ 2550 apss_funnel_in7: endpoint {
2776 2551 remote-endpoint = <&etm7_out>;
2777 }; 2552 };
2778 }; 2553 };
2779 }; 2554 };
2780 }; 2555 };
2781 2556
2782 funnel@7810000 { 2557 funnel@7810000 {
2783 compatible = "arm,cor 2558 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2784 reg = <0 0x07810000 0 2559 reg = <0 0x07810000 0 0x1000>;
2785 2560
2786 clocks = <&aoss_qmp>; 2561 clocks = <&aoss_qmp>;
2787 clock-names = "apb_pc 2562 clock-names = "apb_pclk";
2788 2563
2789 out-ports { 2564 out-ports {
2790 port { 2565 port {
2791 apss_ 2566 apss_merge_funnel_out: endpoint {
2792 2567 remote-endpoint = <&funnel1_in4>;
2793 }; 2568 };
2794 }; 2569 };
2795 }; 2570 };
2796 2571
2797 in-ports { 2572 in-ports {
2798 port { 2573 port {
2799 apss_ 2574 apss_merge_funnel_in: endpoint {
2800 2575 remote-endpoint = <&apss_funnel_out>;
2801 }; 2576 };
2802 }; 2577 };
2803 }; 2578 };
2804 }; 2579 };
2805 2580
2806 sdhc_2: mmc@8804000 { 2581 sdhc_2: mmc@8804000 {
2807 compatible = "qcom,sc 2582 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
2808 reg = <0 0x08804000 0 2583 reg = <0 0x08804000 0 0x1000>;
2809 2584
2810 iommus = <&apps_smmu 2585 iommus = <&apps_smmu 0x80 0>;
2811 interrupts = <GIC_SPI 2586 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
2812 <GIC_ 2587 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
2813 interrupt-names = "hc 2588 interrupt-names = "hc_irq", "pwr_irq";
2814 2589
2815 clocks = <&gcc GCC_SD 2590 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2816 <&gcc GCC_SD 2591 <&gcc GCC_SDCC2_APPS_CLK>,
2817 <&rpmhcc RPM 2592 <&rpmhcc RPMH_CXO_CLK>;
2818 clock-names = "iface" 2593 clock-names = "iface", "core", "xo";
2819 2594
2820 interconnects = <&agg 2595 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
2821 <&gem 2596 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
2822 interconnect-names = 2597 interconnect-names = "sdhc-ddr","cpu-sdhc";
2823 power-domains = <&rpm 2598 power-domains = <&rpmhpd SC7180_CX>;
2824 operating-points-v2 = 2599 operating-points-v2 = <&sdhc2_opp_table>;
2825 2600
2826 bus-width = <4>; 2601 bus-width = <4>;
2827 2602
2828 status = "disabled"; 2603 status = "disabled";
2829 2604
2830 sdhc2_opp_table: opp- 2605 sdhc2_opp_table: opp-table {
2831 compatible = 2606 compatible = "operating-points-v2";
2832 2607
2833 opp-100000000 2608 opp-100000000 {
2834 opp-h 2609 opp-hz = /bits/ 64 <100000000>;
2835 requi 2610 required-opps = <&rpmhpd_opp_low_svs>;
2836 opp-p 2611 opp-peak-kBps = <1800000 600000>;
2837 opp-a 2612 opp-avg-kBps = <100000 0>;
2838 }; 2613 };
2839 2614
2840 opp-202000000 2615 opp-202000000 {
2841 opp-h 2616 opp-hz = /bits/ 64 <202000000>;
2842 requi 2617 required-opps = <&rpmhpd_opp_nom>;
2843 opp-p 2618 opp-peak-kBps = <5400000 1600000>;
2844 opp-a 2619 opp-avg-kBps = <200000 0>;
2845 }; 2620 };
2846 }; 2621 };
2847 }; 2622 };
2848 2623
>> 2624 qspi_opp_table: opp-table-qspi {
>> 2625 compatible = "operating-points-v2";
>> 2626
>> 2627 opp-75000000 {
>> 2628 opp-hz = /bits/ 64 <75000000>;
>> 2629 required-opps = <&rpmhpd_opp_low_svs>;
>> 2630 };
>> 2631
>> 2632 opp-150000000 {
>> 2633 opp-hz = /bits/ 64 <150000000>;
>> 2634 required-opps = <&rpmhpd_opp_svs>;
>> 2635 };
>> 2636
>> 2637 opp-300000000 {
>> 2638 opp-hz = /bits/ 64 <300000000>;
>> 2639 required-opps = <&rpmhpd_opp_nom>;
>> 2640 };
>> 2641 };
>> 2642
2849 qspi: spi@88dc000 { 2643 qspi: spi@88dc000 {
2850 compatible = "qcom,sc 2644 compatible = "qcom,sc7180-qspi", "qcom,qspi-v1";
2851 reg = <0 0x088dc000 0 2645 reg = <0 0x088dc000 0 0x600>;
2852 iommus = <&apps_smmu <<
2853 #address-cells = <1>; 2646 #address-cells = <1>;
2854 #size-cells = <0>; 2647 #size-cells = <0>;
2855 interrupts = <GIC_SPI 2648 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
2856 clocks = <&gcc GCC_QS 2649 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
2857 <&gcc GCC_QS 2650 <&gcc GCC_QSPI_CORE_CLK>;
2858 clock-names = "iface" 2651 clock-names = "iface", "core";
2859 interconnects = <&gem 2652 interconnects = <&gem_noc MASTER_APPSS_PROC 0
2860 &conf 2653 &config_noc SLAVE_QSPI_0 0>;
2861 interconnect-names = 2654 interconnect-names = "qspi-config";
2862 power-domains = <&rpm 2655 power-domains = <&rpmhpd SC7180_CX>;
2863 operating-points-v2 = 2656 operating-points-v2 = <&qspi_opp_table>;
2864 status = "disabled"; 2657 status = "disabled";
2865 }; 2658 };
2866 2659
2867 usb_1_hsphy: phy@88e3000 { 2660 usb_1_hsphy: phy@88e3000 {
2868 compatible = "qcom,sc 2661 compatible = "qcom,sc7180-qusb2-phy", "qcom,qusb2-v2-phy";
2869 reg = <0 0x088e3000 0 2662 reg = <0 0x088e3000 0 0x400>;
2870 status = "disabled"; 2663 status = "disabled";
2871 #phy-cells = <0>; 2664 #phy-cells = <0>;
2872 clocks = <&gcc GCC_US 2665 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2873 <&rpmhcc RPM 2666 <&rpmhcc RPMH_CXO_CLK>;
2874 clock-names = "cfg_ah 2667 clock-names = "cfg_ahb", "ref";
2875 resets = <&gcc GCC_QU 2668 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2876 2669
2877 nvmem-cells = <&qusb2 2670 nvmem-cells = <&qusb2p_hstx_trim>;
2878 }; 2671 };
2879 2672
2880 usb_1_qmpphy: phy@88e8000 { !! 2673 usb_1_qmpphy: phy-wrapper@88e9000 {
2881 compatible = "qcom,sc 2674 compatible = "qcom,sc7180-qmp-usb3-dp-phy";
2882 reg = <0 0x088e8000 0 !! 2675 reg = <0 0x088e9000 0 0x18c>,
>> 2676 <0 0x088e8000 0 0x3c>,
>> 2677 <0 0x088ea000 0 0x18c>;
2883 status = "disabled"; 2678 status = "disabled";
>> 2679 #address-cells = <2>;
>> 2680 #size-cells = <2>;
>> 2681 ranges;
2884 2682
2885 clocks = <&gcc GCC_US 2683 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
>> 2684 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2886 <&gcc GCC_US 2685 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
2887 <&gcc GCC_US !! 2686 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
2888 <&gcc GCC_US !! 2687 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
2889 <&gcc GCC_US <<
2890 clock-names = "aux", <<
2891 "ref", <<
2892 "com_au <<
2893 "usb3_p <<
2894 "cfg_ah <<
2895 2688
2896 resets = <&gcc GCC_US 2689 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
2897 <&gcc GCC_US 2690 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
2898 reset-names = "phy", 2691 reset-names = "phy", "common";
2899 2692
2900 #clock-cells = <1>; !! 2693 usb_1_ssphy: usb3-phy@88e9200 {
2901 #phy-cells = <1>; !! 2694 reg = <0 0x088e9200 0 0x128>,
2902 }; !! 2695 <0 0x088e9400 0 0x200>,
2903 !! 2696 <0 0x088e9c00 0 0x218>,
2904 pmu@90b6300 { !! 2697 <0 0x088e9600 0 0x128>,
2905 compatible = "qcom,sc !! 2698 <0 0x088e9800 0 0x200>,
2906 reg = <0 0x090b6300 0 !! 2699 <0 0x088e9a00 0 0x18>;
2907 interrupts = <GIC_SPI !! 2700 #clock-cells = <0>;
2908 !! 2701 #phy-cells = <0>;
2909 interconnects = <&gem !! 2702 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2910 &gem !! 2703 clock-names = "pipe0";
2911 operating-points-v2 = !! 2704 clock-output-names = "usb3_phy_pipe_clk_src";
2912 <<
2913 cpu_bwmon_opp_table: <<
2914 compatible = <<
2915 <<
2916 opp-0 { <<
2917 opp-p <<
2918 }; <<
2919 <<
2920 opp-1 { <<
2921 opp-p <<
2922 }; <<
2923 <<
2924 opp-2 { <<
2925 opp-p <<
2926 }; <<
2927 <<
2928 opp-3 { <<
2929 opp-p <<
2930 }; <<
2931 <<
2932 opp-4 { <<
2933 opp-p <<
2934 }; <<
2935 <<
2936 opp-5 { <<
2937 opp-p <<
2938 }; <<
2939 }; 2705 };
2940 }; <<
2941 <<
2942 pmu@90cd000 { <<
2943 compatible = "qcom,sc <<
2944 reg = <0 0x090cd000 0 <<
2945 interrupts = <GIC_SPI <<
2946 <<
2947 interconnects = <&mc_ <<
2948 &mc_ <<
2949 operating-points-v2 = <<
2950 <<
2951 llcc_bwmon_opp_table: <<
2952 compatible = <<
2953 2706
2954 opp-0 { !! 2707 dp_phy: dp-phy@88ea200 {
2955 opp-p !! 2708 reg = <0 0x088ea200 0 0x200>,
2956 }; !! 2709 <0 0x088ea400 0 0x200>,
2957 !! 2710 <0 0x088eaa00 0 0x200>,
2958 opp-1 { !! 2711 <0 0x088ea600 0 0x200>,
2959 opp-p !! 2712 <0 0x088ea800 0 0x200>;
2960 }; !! 2713 #clock-cells = <1>;
2961 !! 2714 #phy-cells = <0>;
2962 opp-2 { <<
2963 opp-p <<
2964 }; <<
2965 <<
2966 opp-3 { <<
2967 opp-p <<
2968 }; <<
2969 <<
2970 opp-4 { <<
2971 opp-p <<
2972 }; <<
2973 <<
2974 opp-5 { <<
2975 opp-p <<
2976 }; <<
2977 <<
2978 opp-6 { <<
2979 opp-p <<
2980 }; <<
2981 <<
2982 opp-7 { <<
2983 opp-p <<
2984 }; <<
2985 }; 2715 };
2986 }; 2716 };
2987 2717
2988 dc_noc: interconnect@9160000 2718 dc_noc: interconnect@9160000 {
2989 compatible = "qcom,sc 2719 compatible = "qcom,sc7180-dc-noc";
2990 reg = <0 0x09160000 0 2720 reg = <0 0x09160000 0 0x03200>;
2991 #interconnect-cells = 2721 #interconnect-cells = <2>;
2992 qcom,bcm-voters = <&a 2722 qcom,bcm-voters = <&apps_bcm_voter>;
2993 }; 2723 };
2994 2724
2995 system-cache-controller@92000 2725 system-cache-controller@9200000 {
2996 compatible = "qcom,sc 2726 compatible = "qcom,sc7180-llcc";
2997 reg = <0 0x09200000 0 2727 reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>;
2998 reg-names = "llcc0_ba !! 2728 reg-names = "llcc_base", "llcc_broadcast_base";
2999 interrupts = <GIC_SPI 2729 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
3000 }; 2730 };
3001 2731
3002 gem_noc: interconnect@9680000 2732 gem_noc: interconnect@9680000 {
3003 compatible = "qcom,sc 2733 compatible = "qcom,sc7180-gem-noc";
3004 reg = <0 0x09680000 0 2734 reg = <0 0x09680000 0 0x3e200>;
3005 #interconnect-cells = 2735 #interconnect-cells = <2>;
3006 qcom,bcm-voters = <&a 2736 qcom,bcm-voters = <&apps_bcm_voter>;
3007 }; 2737 };
3008 2738
3009 npu_noc: interconnect@9990000 2739 npu_noc: interconnect@9990000 {
3010 compatible = "qcom,sc 2740 compatible = "qcom,sc7180-npu-noc";
3011 reg = <0 0x09990000 0 2741 reg = <0 0x09990000 0 0x1600>;
3012 #interconnect-cells = 2742 #interconnect-cells = <2>;
3013 qcom,bcm-voters = <&a 2743 qcom,bcm-voters = <&apps_bcm_voter>;
3014 }; 2744 };
3015 2745
3016 usb_1: usb@a6f8800 { 2746 usb_1: usb@a6f8800 {
3017 compatible = "qcom,sc 2747 compatible = "qcom,sc7180-dwc3", "qcom,dwc3";
3018 reg = <0 0x0a6f8800 0 2748 reg = <0 0x0a6f8800 0 0x400>;
3019 status = "disabled"; 2749 status = "disabled";
3020 #address-cells = <2>; 2750 #address-cells = <2>;
3021 #size-cells = <2>; 2751 #size-cells = <2>;
3022 ranges; 2752 ranges;
3023 dma-ranges; 2753 dma-ranges;
3024 2754
3025 clocks = <&gcc GCC_CF 2755 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
3026 <&gcc GCC_US 2756 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
3027 <&gcc GCC_AG 2757 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
3028 <&gcc GCC_US 2758 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
3029 <&gcc GCC_US 2759 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
3030 clock-names = "cfg_no 2760 clock-names = "cfg_noc",
3031 "core", 2761 "core",
3032 "iface" 2762 "iface",
3033 "sleep" 2763 "sleep",
3034 "mock_u 2764 "mock_utmi";
3035 2765
3036 assigned-clocks = <&g 2766 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3037 <&g 2767 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
3038 assigned-clock-rates 2768 assigned-clock-rates = <19200000>, <150000000>;
3039 2769
3040 interrupts-extended = !! 2770 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
3041 !! 2771 <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
3042 <<
3043 2772 <&pdc 8 IRQ_TYPE_EDGE_BOTH>,
3044 !! 2773 <&pdc 9 IRQ_TYPE_EDGE_BOTH>;
3045 interrupt-names = "pw !! 2774 interrupt-names = "hs_phy_irq", "ss_phy_irq",
3046 "hs !! 2775 "dm_hs_phy_irq", "dp_hs_phy_irq";
3047 "dp <<
3048 "dm <<
3049 "ss <<
3050 2776
3051 power-domains = <&gcc 2777 power-domains = <&gcc USB30_PRIM_GDSC>;
3052 required-opps = <&rpm <<
3053 2778
3054 resets = <&gcc GCC_US 2779 resets = <&gcc GCC_USB30_PRIM_BCR>;
3055 2780
3056 interconnects = <&agg 2781 interconnects = <&aggre2_noc MASTER_USB3 0 &mc_virt SLAVE_EBI1 0>,
3057 <&gem 2782 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3 0>;
3058 interconnect-names = 2783 interconnect-names = "usb-ddr", "apps-usb";
3059 2784
3060 wakeup-source; <<
3061 <<
3062 usb_1_dwc3: usb@a6000 2785 usb_1_dwc3: usb@a600000 {
3063 compatible = 2786 compatible = "snps,dwc3";
3064 reg = <0 0x0a 2787 reg = <0 0x0a600000 0 0xe000>;
3065 interrupts = 2788 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
3066 iommus = <&ap 2789 iommus = <&apps_smmu 0x540 0>;
3067 snps,dis_u2_s 2790 snps,dis_u2_susphy_quirk;
3068 snps,dis_enbl 2791 snps,dis_enblslpm_quirk;
3069 snps,parkmode !! 2792 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
3070 phys = <&usb_ <<
3071 phy-names = " 2793 phy-names = "usb2-phy", "usb3-phy";
3072 maximum-speed 2794 maximum-speed = "super-speed";
3073 }; 2795 };
3074 }; 2796 };
3075 2797
3076 venus: video-codec@aa00000 { 2798 venus: video-codec@aa00000 {
3077 compatible = "qcom,sc 2799 compatible = "qcom,sc7180-venus";
3078 reg = <0 0x0aa00000 0 2800 reg = <0 0x0aa00000 0 0xff000>;
3079 interrupts = <GIC_SPI 2801 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
3080 power-domains = <&vid 2802 power-domains = <&videocc VENUS_GDSC>,
3081 <&vid 2803 <&videocc VCODEC0_GDSC>,
3082 <&rpm 2804 <&rpmhpd SC7180_CX>;
3083 power-domain-names = 2805 power-domain-names = "venus", "vcodec0", "cx";
3084 operating-points-v2 = 2806 operating-points-v2 = <&venus_opp_table>;
3085 clocks = <&videocc VI 2807 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
3086 <&videocc VI 2808 <&videocc VIDEO_CC_VENUS_AHB_CLK>,
3087 <&videocc VI 2809 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>,
3088 <&videocc VI 2810 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
3089 <&videocc VI 2811 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>;
3090 clock-names = "core", 2812 clock-names = "core", "iface", "bus",
3091 "vcodec 2813 "vcodec0_core", "vcodec0_bus";
3092 iommus = <&apps_smmu 2814 iommus = <&apps_smmu 0x0c00 0x60>;
3093 memory-region = <&ven 2815 memory-region = <&venus_mem>;
3094 interconnects = <&mms 2816 interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>,
3095 <&gem 2817 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>;
3096 interconnect-names = 2818 interconnect-names = "video-mem", "cpu-cfg";
3097 2819
3098 video-decoder { 2820 video-decoder {
3099 compatible = 2821 compatible = "venus-decoder";
3100 }; 2822 };
3101 2823
3102 video-encoder { 2824 video-encoder {
3103 compatible = 2825 compatible = "venus-encoder";
3104 }; 2826 };
3105 2827
3106 venus_opp_table: opp- 2828 venus_opp_table: opp-table {
3107 compatible = 2829 compatible = "operating-points-v2";
3108 2830
3109 opp-150000000 2831 opp-150000000 {
3110 opp-h 2832 opp-hz = /bits/ 64 <150000000>;
3111 requi 2833 required-opps = <&rpmhpd_opp_low_svs>;
3112 }; 2834 };
3113 2835
3114 opp-270000000 2836 opp-270000000 {
3115 opp-h 2837 opp-hz = /bits/ 64 <270000000>;
3116 requi 2838 required-opps = <&rpmhpd_opp_svs>;
3117 }; 2839 };
3118 2840
3119 opp-340000000 2841 opp-340000000 {
3120 opp-h 2842 opp-hz = /bits/ 64 <340000000>;
3121 requi 2843 required-opps = <&rpmhpd_opp_svs_l1>;
3122 }; 2844 };
3123 2845
3124 opp-434000000 2846 opp-434000000 {
3125 opp-h 2847 opp-hz = /bits/ 64 <434000000>;
3126 requi 2848 required-opps = <&rpmhpd_opp_nom>;
3127 }; 2849 };
3128 2850
3129 opp-500000097 2851 opp-500000097 {
3130 opp-h 2852 opp-hz = /bits/ 64 <500000097>;
3131 requi 2853 required-opps = <&rpmhpd_opp_turbo>;
3132 }; 2854 };
3133 }; 2855 };
3134 }; 2856 };
3135 2857
3136 videocc: clock-controller@ab0 2858 videocc: clock-controller@ab00000 {
3137 compatible = "qcom,sc 2859 compatible = "qcom,sc7180-videocc";
3138 reg = <0 0x0ab00000 0 2860 reg = <0 0x0ab00000 0 0x10000>;
3139 clocks = <&rpmhcc RPM 2861 clocks = <&rpmhcc RPMH_CXO_CLK>;
3140 clock-names = "bi_tcx 2862 clock-names = "bi_tcxo";
3141 #clock-cells = <1>; 2863 #clock-cells = <1>;
3142 #reset-cells = <1>; 2864 #reset-cells = <1>;
3143 #power-domain-cells = 2865 #power-domain-cells = <1>;
3144 }; 2866 };
3145 2867
3146 camnoc_virt: interconnect@ac0 2868 camnoc_virt: interconnect@ac00000 {
3147 compatible = "qcom,sc 2869 compatible = "qcom,sc7180-camnoc-virt";
3148 reg = <0 0x0ac00000 0 2870 reg = <0 0x0ac00000 0 0x1000>;
3149 #interconnect-cells = 2871 #interconnect-cells = <2>;
3150 qcom,bcm-voters = <&a 2872 qcom,bcm-voters = <&apps_bcm_voter>;
3151 }; 2873 };
3152 2874
3153 camcc: clock-controller@ad000 2875 camcc: clock-controller@ad00000 {
3154 compatible = "qcom,sc 2876 compatible = "qcom,sc7180-camcc";
3155 reg = <0 0x0ad00000 0 2877 reg = <0 0x0ad00000 0 0x10000>;
3156 clocks = <&rpmhcc RPM 2878 clocks = <&rpmhcc RPMH_CXO_CLK>,
3157 <&gcc GCC_CAME 2879 <&gcc GCC_CAMERA_AHB_CLK>,
3158 <&gcc GCC_CAME 2880 <&gcc GCC_CAMERA_XO_CLK>;
3159 clock-names = "bi_tcx 2881 clock-names = "bi_tcxo", "iface", "xo";
3160 #clock-cells = <1>; 2882 #clock-cells = <1>;
3161 #reset-cells = <1>; 2883 #reset-cells = <1>;
3162 #power-domain-cells = 2884 #power-domain-cells = <1>;
3163 }; 2885 };
3164 2886
3165 mdss: display-subsystem@ae000 !! 2887 mdss: mdss@ae00000 {
3166 compatible = "qcom,sc 2888 compatible = "qcom,sc7180-mdss";
3167 reg = <0 0x0ae00000 0 2889 reg = <0 0x0ae00000 0 0x1000>;
3168 reg-names = "mdss"; 2890 reg-names = "mdss";
3169 2891
3170 power-domains = <&dis 2892 power-domains = <&dispcc MDSS_GDSC>;
3171 2893
3172 clocks = <&gcc GCC_DI 2894 clocks = <&gcc GCC_DISP_AHB_CLK>,
3173 <&dispcc DIS 2895 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3174 <&dispcc DIS 2896 <&dispcc DISP_CC_MDSS_MDP_CLK>;
3175 clock-names = "iface" 2897 clock-names = "iface", "ahb", "core";
3176 2898
3177 interrupts = <GIC_SPI 2899 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
3178 interrupt-controller; 2900 interrupt-controller;
3179 #interrupt-cells = <1 2901 #interrupt-cells = <1>;
3180 2902
3181 interconnects = <&mms !! 2903 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>;
3182 &mc_ !! 2904 interconnect-names = "mdp0-mem";
3183 <&gem <<
3184 &con <<
3185 interconnect-names = <<
3186 <<
3187 2905
3188 iommus = <&apps_smmu 2906 iommus = <&apps_smmu 0x800 0x2>;
3189 2907
3190 #address-cells = <2>; 2908 #address-cells = <2>;
3191 #size-cells = <2>; 2909 #size-cells = <2>;
3192 ranges; 2910 ranges;
3193 2911
3194 status = "disabled"; 2912 status = "disabled";
3195 2913
3196 mdp: display-controll 2914 mdp: display-controller@ae01000 {
3197 compatible = 2915 compatible = "qcom,sc7180-dpu";
3198 reg = <0 0x0a 2916 reg = <0 0x0ae01000 0 0x8f000>,
3199 <0 0x0a 2917 <0 0x0aeb0000 0 0x2008>;
3200 reg-names = " 2918 reg-names = "mdp", "vbif";
3201 2919
3202 clocks = <&gc 2920 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
3203 <&di 2921 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3204 <&di 2922 <&dispcc DISP_CC_MDSS_ROT_CLK>,
3205 <&di 2923 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
3206 <&di 2924 <&dispcc DISP_CC_MDSS_MDP_CLK>,
3207 <&di 2925 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3208 clock-names = 2926 clock-names = "bus", "iface", "rot", "lut", "core",
3209 2927 "vsync";
3210 assigned-cloc 2928 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
3211 2929 <&dispcc DISP_CC_MDSS_ROT_CLK>,
3212 2930 <&dispcc DISP_CC_MDSS_AHB_CLK>;
3213 assigned-cloc 2931 assigned-clock-rates = <19200000>,
3214 2932 <19200000>,
3215 2933 <19200000>;
3216 operating-poi 2934 operating-points-v2 = <&mdp_opp_table>;
3217 power-domains 2935 power-domains = <&rpmhpd SC7180_CX>;
3218 2936
3219 interrupt-par 2937 interrupt-parent = <&mdss>;
3220 interrupts = 2938 interrupts = <0>;
3221 2939
>> 2940 status = "disabled";
>> 2941
3222 ports { 2942 ports {
3223 #addr 2943 #address-cells = <1>;
3224 #size 2944 #size-cells = <0>;
3225 2945
3226 port@ 2946 port@0 {
3227 2947 reg = <0>;
3228 2948 dpu_intf1_out: endpoint {
3229 !! 2949 remote-endpoint = <&dsi0_in>;
3230 2950 };
3231 }; 2951 };
3232 2952
3233 port@ 2953 port@2 {
3234 2954 reg = <2>;
3235 2955 dpu_intf0_out: endpoint {
3236 2956 remote-endpoint = <&dp_in>;
3237 2957 };
3238 }; 2958 };
3239 }; 2959 };
3240 2960
3241 mdp_opp_table 2961 mdp_opp_table: opp-table {
3242 compa 2962 compatible = "operating-points-v2";
3243 2963
3244 opp-2 2964 opp-200000000 {
3245 2965 opp-hz = /bits/ 64 <200000000>;
3246 2966 required-opps = <&rpmhpd_opp_low_svs>;
3247 }; 2967 };
3248 2968
3249 opp-3 2969 opp-300000000 {
3250 2970 opp-hz = /bits/ 64 <300000000>;
3251 2971 required-opps = <&rpmhpd_opp_svs>;
3252 }; 2972 };
3253 2973
3254 opp-3 2974 opp-345000000 {
3255 2975 opp-hz = /bits/ 64 <345000000>;
3256 2976 required-opps = <&rpmhpd_opp_svs_l1>;
3257 }; 2977 };
3258 2978
3259 opp-4 2979 opp-460000000 {
3260 2980 opp-hz = /bits/ 64 <460000000>;
3261 2981 required-opps = <&rpmhpd_opp_nom>;
3262 }; 2982 };
3263 }; 2983 };
>> 2984
3264 }; 2985 };
3265 2986
3266 mdss_dsi0: dsi@ae9400 !! 2987 dsi0: dsi@ae94000 {
3267 compatible = !! 2988 compatible = "qcom,mdss-dsi-ctrl";
3268 <<
3269 reg = <0 0x0a 2989 reg = <0 0x0ae94000 0 0x400>;
3270 reg-names = " 2990 reg-names = "dsi_ctrl";
3271 2991
3272 interrupt-par 2992 interrupt-parent = <&mdss>;
3273 interrupts = 2993 interrupts = <4>;
3274 2994
3275 clocks = <&di 2995 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
3276 <&di 2996 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
3277 <&di 2997 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
3278 <&di 2998 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
3279 <&di 2999 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3280 <&gc 3000 <&gcc GCC_DISP_HF_AXI_CLK>;
3281 clock-names = 3001 clock-names = "byte",
3282 3002 "byte_intf",
3283 3003 "pixel",
3284 3004 "core",
3285 3005 "iface",
3286 3006 "bus";
3287 3007
3288 assigned-cloc 3008 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
3289 assigned-cloc !! 3009 assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>;
3290 3010
3291 operating-poi 3011 operating-points-v2 = <&dsi_opp_table>;
3292 power-domains 3012 power-domains = <&rpmhpd SC7180_CX>;
3293 3013
3294 phys = <&mdss !! 3014 phys = <&dsi_phy>;
>> 3015 phy-names = "dsi";
3295 3016
3296 #address-cell 3017 #address-cells = <1>;
3297 #size-cells = 3018 #size-cells = <0>;
3298 3019
3299 status = "dis 3020 status = "disabled";
3300 3021
3301 ports { 3022 ports {
3302 #addr 3023 #address-cells = <1>;
3303 #size 3024 #size-cells = <0>;
3304 3025
3305 port@ 3026 port@0 {
3306 3027 reg = <0>;
3307 !! 3028 dsi0_in: endpoint {
3308 3029 remote-endpoint = <&dpu_intf1_out>;
3309 3030 };
3310 }; 3031 };
3311 3032
3312 port@ 3033 port@1 {
3313 3034 reg = <1>;
3314 !! 3035 dsi0_out: endpoint {
3315 3036 };
3316 }; 3037 };
3317 }; 3038 };
3318 3039
3319 dsi_opp_table 3040 dsi_opp_table: opp-table {
3320 compa 3041 compatible = "operating-points-v2";
3321 3042
3322 opp-1 3043 opp-187500000 {
3323 3044 opp-hz = /bits/ 64 <187500000>;
3324 3045 required-opps = <&rpmhpd_opp_low_svs>;
3325 }; 3046 };
3326 3047
3327 opp-3 3048 opp-300000000 {
3328 3049 opp-hz = /bits/ 64 <300000000>;
3329 3050 required-opps = <&rpmhpd_opp_svs>;
3330 }; 3051 };
3331 3052
3332 opp-3 3053 opp-358000000 {
3333 3054 opp-hz = /bits/ 64 <358000000>;
3334 3055 required-opps = <&rpmhpd_opp_svs_l1>;
3335 }; 3056 };
3336 }; 3057 };
3337 }; 3058 };
3338 3059
3339 mdss_dsi0_phy: phy@ae !! 3060 dsi_phy: dsi-phy@ae94400 {
3340 compatible = 3061 compatible = "qcom,dsi-phy-10nm";
3341 reg = <0 0x0a 3062 reg = <0 0x0ae94400 0 0x200>,
3342 <0 0x0a 3063 <0 0x0ae94600 0 0x280>,
3343 <0 0x0a 3064 <0 0x0ae94a00 0 0x1e0>;
3344 reg-names = " 3065 reg-names = "dsi_phy",
3345 " 3066 "dsi_phy_lane",
3346 " 3067 "dsi_pll";
3347 3068
3348 #clock-cells 3069 #clock-cells = <1>;
3349 #phy-cells = 3070 #phy-cells = <0>;
3350 3071
3351 clocks = <&di 3072 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3352 <&rp 3073 <&rpmhcc RPMH_CXO_CLK>;
3353 clock-names = 3074 clock-names = "iface", "ref";
3354 3075
3355 status = "dis 3076 status = "disabled";
3356 }; 3077 };
3357 3078
3358 mdss_dp: displayport- 3079 mdss_dp: displayport-controller@ae90000 {
3359 compatible = 3080 compatible = "qcom,sc7180-dp";
3360 status = "dis 3081 status = "disabled";
3361 3082
3362 reg = <0 0x0a !! 3083 reg = <0 0xae90000 0 0x200>,
3363 <0 0x0a !! 3084 <0 0xae90200 0 0x200>,
3364 <0 0x0a !! 3085 <0 0xae90400 0 0xc00>,
3365 <0 0x0a !! 3086 <0 0xae91000 0 0x400>,
3366 <0 0x0a !! 3087 <0 0xae91400 0 0x400>;
3367 3088
3368 interrupt-par 3089 interrupt-parent = <&mdss>;
3369 interrupts = 3090 interrupts = <12>;
3370 3091
3371 clocks = <&di 3092 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3372 <&di 3093 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
3373 <&di 3094 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
3374 <&di 3095 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
3375 <&di 3096 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
3376 clock-names = 3097 clock-names = "core_iface", "core_aux", "ctrl_link",
3377 3098 "ctrl_link_iface", "stream_pixel";
3378 assigned-cloc 3099 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
3379 3100 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
3380 assigned-cloc !! 3101 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
3381 !! 3102 phys = <&dp_phy>;
3382 phys = <&usb_ <<
3383 phy-names = " 3103 phy-names = "dp";
3384 3104
3385 operating-poi 3105 operating-points-v2 = <&dp_opp_table>;
3386 power-domains 3106 power-domains = <&rpmhpd SC7180_CX>;
3387 3107
3388 #sound-dai-ce 3108 #sound-dai-cells = <0>;
3389 3109
3390 ports { 3110 ports {
3391 #addr 3111 #address-cells = <1>;
3392 #size 3112 #size-cells = <0>;
3393 port@ 3113 port@0 {
3394 3114 reg = <0>;
3395 3115 dp_in: endpoint {
3396 3116 remote-endpoint = <&dpu_intf0_out>;
3397 3117 };
3398 }; 3118 };
3399 3119
3400 port@ 3120 port@1 {
3401 3121 reg = <1>;
3402 !! 3122 dp_out: endpoint { };
3403 }; 3123 };
3404 }; 3124 };
3405 3125
3406 dp_opp_table: 3126 dp_opp_table: opp-table {
3407 compa 3127 compatible = "operating-points-v2";
3408 3128
3409 opp-1 3129 opp-160000000 {
3410 3130 opp-hz = /bits/ 64 <160000000>;
3411 3131 required-opps = <&rpmhpd_opp_low_svs>;
3412 }; 3132 };
3413 3133
3414 opp-2 3134 opp-270000000 {
3415 3135 opp-hz = /bits/ 64 <270000000>;
3416 3136 required-opps = <&rpmhpd_opp_svs>;
3417 }; 3137 };
3418 3138
3419 opp-5 3139 opp-540000000 {
3420 3140 opp-hz = /bits/ 64 <540000000>;
3421 3141 required-opps = <&rpmhpd_opp_svs_l1>;
3422 }; 3142 };
3423 3143
3424 opp-8 3144 opp-810000000 {
3425 3145 opp-hz = /bits/ 64 <810000000>;
3426 3146 required-opps = <&rpmhpd_opp_nom>;
3427 }; 3147 };
3428 }; 3148 };
3429 }; 3149 };
3430 }; 3150 };
3431 3151
3432 dispcc: clock-controller@af00 3152 dispcc: clock-controller@af00000 {
3433 compatible = "qcom,sc 3153 compatible = "qcom,sc7180-dispcc";
3434 reg = <0 0x0af00000 0 3154 reg = <0 0x0af00000 0 0x200000>;
3435 clocks = <&rpmhcc RPM 3155 clocks = <&rpmhcc RPMH_CXO_CLK>,
3436 <&gcc GCC_DI 3156 <&gcc GCC_DISP_GPLL0_CLK_SRC>,
3437 <&mdss_dsi0_ !! 3157 <&dsi_phy 0>,
3438 <&mdss_dsi0_ !! 3158 <&dsi_phy 1>,
3439 <&usb_1_qmpp !! 3159 <&dp_phy 0>,
3440 <&usb_1_qmpp !! 3160 <&dp_phy 1>;
3441 clock-names = "bi_tcx 3161 clock-names = "bi_tcxo",
3442 "gcc_di 3162 "gcc_disp_gpll0_clk_src",
3443 "dsi0_p 3163 "dsi0_phy_pll_out_byteclk",
3444 "dsi0_p 3164 "dsi0_phy_pll_out_dsiclk",
3445 "dp_phy 3165 "dp_phy_pll_link_clk",
3446 "dp_phy 3166 "dp_phy_pll_vco_div_clk";
3447 #clock-cells = <1>; 3167 #clock-cells = <1>;
3448 #reset-cells = <1>; 3168 #reset-cells = <1>;
3449 #power-domain-cells = 3169 #power-domain-cells = <1>;
3450 }; 3170 };
3451 3171
3452 pdc: interrupt-controller@b22 3172 pdc: interrupt-controller@b220000 {
3453 compatible = "qcom,sc 3173 compatible = "qcom,sc7180-pdc", "qcom,pdc";
3454 reg = <0 0x0b220000 0 3174 reg = <0 0x0b220000 0 0x30000>;
3455 qcom,pdc-ranges = <0 3175 qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>;
3456 #interrupt-cells = <2 3176 #interrupt-cells = <2>;
3457 interrupt-parent = <& 3177 interrupt-parent = <&intc>;
3458 interrupt-controller; 3178 interrupt-controller;
3459 }; 3179 };
3460 3180
3461 pdc_reset: reset-controller@b 3181 pdc_reset: reset-controller@b2e0000 {
3462 compatible = "qcom,sc 3182 compatible = "qcom,sc7180-pdc-global", "qcom,sdm845-pdc-global";
3463 reg = <0 0x0b2e0000 0 3183 reg = <0 0x0b2e0000 0 0x20000>;
3464 #reset-cells = <1>; 3184 #reset-cells = <1>;
3465 }; 3185 };
3466 3186
3467 tsens0: thermal-sensor@c26300 3187 tsens0: thermal-sensor@c263000 {
3468 compatible = "qcom,sc 3188 compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
3469 reg = <0 0x0c263000 0 3189 reg = <0 0x0c263000 0 0x1ff>, /* TM */
3470 <0 0x0c222000 3190 <0 0x0c222000 0 0x1ff>; /* SROT */
3471 #qcom,sensors = <15>; 3191 #qcom,sensors = <15>;
3472 interrupts = <GIC_SPI 3192 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
3473 <GIC_SPI 3193 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
3474 interrupt-names = "up 3194 interrupt-names = "uplow","critical";
3475 #thermal-sensor-cells 3195 #thermal-sensor-cells = <1>;
3476 }; 3196 };
3477 3197
3478 tsens1: thermal-sensor@c26500 3198 tsens1: thermal-sensor@c265000 {
3479 compatible = "qcom,sc 3199 compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
3480 reg = <0 0x0c265000 0 3200 reg = <0 0x0c265000 0 0x1ff>, /* TM */
3481 <0 0x0c223000 3201 <0 0x0c223000 0 0x1ff>; /* SROT */
3482 #qcom,sensors = <10>; 3202 #qcom,sensors = <10>;
3483 interrupts = <GIC_SPI 3203 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
3484 <GIC_SPI 3204 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
3485 interrupt-names = "up 3205 interrupt-names = "uplow","critical";
3486 #thermal-sensor-cells 3206 #thermal-sensor-cells = <1>;
3487 }; 3207 };
3488 3208
3489 aoss_reset: reset-controller@ 3209 aoss_reset: reset-controller@c2a0000 {
3490 compatible = "qcom,sc 3210 compatible = "qcom,sc7180-aoss-cc", "qcom,sdm845-aoss-cc";
3491 reg = <0 0x0c2a0000 0 3211 reg = <0 0x0c2a0000 0 0x31000>;
3492 #reset-cells = <1>; 3212 #reset-cells = <1>;
3493 }; 3213 };
3494 3214
3495 aoss_qmp: power-management@c3 !! 3215 aoss_qmp: power-controller@c300000 {
3496 compatible = "qcom,sc 3216 compatible = "qcom,sc7180-aoss-qmp", "qcom,aoss-qmp";
3497 reg = <0 0x0c300000 0 3217 reg = <0 0x0c300000 0 0x400>;
3498 interrupts = <GIC_SPI 3218 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
3499 mboxes = <&apss_share 3219 mboxes = <&apss_shared 0>;
3500 3220
3501 #clock-cells = <0>; 3221 #clock-cells = <0>;
3502 }; 3222 };
3503 3223
3504 sram@c3f0000 { 3224 sram@c3f0000 {
3505 compatible = "qcom,rp 3225 compatible = "qcom,rpmh-stats";
3506 reg = <0 0x0c3f0000 0 3226 reg = <0 0x0c3f0000 0 0x400>;
3507 }; 3227 };
3508 3228
3509 spmi_bus: spmi@c440000 { 3229 spmi_bus: spmi@c440000 {
3510 compatible = "qcom,sp 3230 compatible = "qcom,spmi-pmic-arb";
3511 reg = <0 0x0c440000 0 3231 reg = <0 0x0c440000 0 0x1100>,
3512 <0 0x0c600000 0 3232 <0 0x0c600000 0 0x2000000>,
3513 <0 0x0e600000 0 3233 <0 0x0e600000 0 0x100000>,
3514 <0 0x0e700000 0 3234 <0 0x0e700000 0 0xa0000>,
3515 <0 0x0c40a000 0 3235 <0 0x0c40a000 0 0x26000>;
3516 reg-names = "core", " 3236 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3517 interrupt-names = "pe 3237 interrupt-names = "periph_irq";
3518 interrupts-extended = 3238 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3519 qcom,ee = <0>; 3239 qcom,ee = <0>;
3520 qcom,channel = <0>; 3240 qcom,channel = <0>;
3521 #address-cells = <2>; 3241 #address-cells = <2>;
3522 #size-cells = <0>; 3242 #size-cells = <0>;
3523 interrupt-controller; 3243 interrupt-controller;
3524 #interrupt-cells = <4 3244 #interrupt-cells = <4>;
>> 3245 cell-index = <0>;
3525 }; 3246 };
3526 3247
3527 sram@146aa000 { 3248 sram@146aa000 {
3528 compatible = "qcom,sc 3249 compatible = "qcom,sc7180-imem", "syscon", "simple-mfd";
3529 reg = <0 0x146aa000 0 3250 reg = <0 0x146aa000 0 0x2000>;
3530 3251
3531 #address-cells = <1>; 3252 #address-cells = <1>;
3532 #size-cells = <1>; 3253 #size-cells = <1>;
3533 3254
3534 ranges = <0 0 0x146aa 3255 ranges = <0 0 0x146aa000 0x2000>;
3535 3256
3536 pil-reloc@94c { 3257 pil-reloc@94c {
3537 compatible = 3258 compatible = "qcom,pil-reloc-info";
3538 reg = <0x94c 3259 reg = <0x94c 0xc8>;
3539 }; 3260 };
3540 }; 3261 };
3541 3262
3542 apps_smmu: iommu@15000000 { 3263 apps_smmu: iommu@15000000 {
3543 compatible = "qcom,sc 3264 compatible = "qcom,sc7180-smmu-500", "arm,mmu-500";
3544 reg = <0 0x15000000 0 3265 reg = <0 0x15000000 0 0x100000>;
3545 #iommu-cells = <2>; 3266 #iommu-cells = <2>;
3546 #global-interrupts = 3267 #global-interrupts = <1>;
3547 interrupts = <GIC_SPI 3268 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
3548 <GIC_SPI 3269 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
3549 <GIC_SPI 3270 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
3550 <GIC_SPI 3271 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
3551 <GIC_SPI 3272 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
3552 <GIC_SPI 3273 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
3553 <GIC_SPI 3274 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
3554 <GIC_SPI 3275 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
3555 <GIC_SPI 3276 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
3556 <GIC_SPI 3277 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
3557 <GIC_SPI 3278 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
3558 <GIC_SPI 3279 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
3559 <GIC_SPI 3280 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
3560 <GIC_SPI 3281 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
3561 <GIC_SPI 3282 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
3562 <GIC_SPI 3283 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
3563 <GIC_SPI 3284 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
3564 <GIC_SPI 3285 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
3565 <GIC_SPI 3286 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
3566 <GIC_SPI 3287 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
3567 <GIC_SPI 3288 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
3568 <GIC_SPI 3289 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
3569 <GIC_SPI 3290 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
3570 <GIC_SPI 3291 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
3571 <GIC_SPI 3292 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
3572 <GIC_SPI 3293 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
3573 <GIC_SPI 3294 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
3574 <GIC_SPI 3295 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
3575 <GIC_SPI 3296 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
3576 <GIC_SPI 3297 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
3577 <GIC_SPI 3298 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
3578 <GIC_SPI 3299 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
3579 <GIC_SPI 3300 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
3580 <GIC_SPI 3301 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
3581 <GIC_SPI 3302 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
3582 <GIC_SPI 3303 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
3583 <GIC_SPI 3304 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
3584 <GIC_SPI 3305 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
3585 <GIC_SPI 3306 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
3586 <GIC_SPI 3307 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
3587 <GIC_SPI 3308 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
3588 <GIC_SPI 3309 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
3589 <GIC_SPI 3310 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
3590 <GIC_SPI 3311 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
3591 <GIC_SPI 3312 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
3592 <GIC_SPI 3313 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
3593 <GIC_SPI 3314 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
3594 <GIC_SPI 3315 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
3595 <GIC_SPI 3316 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
3596 <GIC_SPI 3317 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
3597 <GIC_SPI 3318 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
3598 <GIC_SPI 3319 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
3599 <GIC_SPI 3320 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
3600 <GIC_SPI 3321 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
3601 <GIC_SPI 3322 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
3602 <GIC_SPI 3323 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
3603 <GIC_SPI 3324 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
3604 <GIC_SPI 3325 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
3605 <GIC_SPI 3326 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
3606 <GIC_SPI 3327 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
3607 <GIC_SPI 3328 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
3608 <GIC_SPI 3329 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
3609 <GIC_SPI 3330 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
3610 <GIC_SPI 3331 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
3611 <GIC_SPI 3332 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
3612 <GIC_SPI 3333 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
3613 <GIC_SPI 3334 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
3614 <GIC_SPI 3335 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
3615 <GIC_SPI 3336 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
3616 <GIC_SPI 3337 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
3617 <GIC_SPI 3338 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
3618 <GIC_SPI 3339 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
3619 <GIC_SPI 3340 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
3620 <GIC_SPI 3341 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
3621 <GIC_SPI 3342 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
3622 <GIC_SPI 3343 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
3623 <GIC_SPI 3344 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
3624 <GIC_SPI 3345 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
3625 <GIC_SPI 3346 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
3626 <GIC_SPI 3347 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
3627 <GIC_SPI 3348 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
3628 }; 3349 };
3629 3350
3630 intc: interrupt-controller@17 3351 intc: interrupt-controller@17a00000 {
3631 compatible = "arm,gic 3352 compatible = "arm,gic-v3";
3632 #address-cells = <2>; 3353 #address-cells = <2>;
3633 #size-cells = <2>; 3354 #size-cells = <2>;
3634 ranges; 3355 ranges;
3635 #interrupt-cells = <3 3356 #interrupt-cells = <3>;
3636 interrupt-controller; 3357 interrupt-controller;
3637 reg = <0 0x17a00000 0 3358 reg = <0 0x17a00000 0 0x10000>, /* GICD */
3638 <0 0x17a60000 0 3359 <0 0x17a60000 0 0x100000>; /* GICR * 8 */
3639 interrupts = <GIC_PPI 3360 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3640 3361
3641 msi-controller@17a400 3362 msi-controller@17a40000 {
3642 compatible = 3363 compatible = "arm,gic-v3-its";
3643 msi-controlle 3364 msi-controller;
3644 #msi-cells = 3365 #msi-cells = <1>;
3645 reg = <0 0x17 3366 reg = <0 0x17a40000 0 0x20000>;
3646 status = "dis 3367 status = "disabled";
3647 }; 3368 };
3648 }; 3369 };
3649 3370
3650 apss_shared: mailbox@17c00000 3371 apss_shared: mailbox@17c00000 {
3651 compatible = "qcom,sc !! 3372 compatible = "qcom,sc7180-apss-shared";
3652 "qcom,sd <<
3653 reg = <0 0x17c00000 0 3373 reg = <0 0x17c00000 0 0x10000>;
3654 #mbox-cells = <1>; 3374 #mbox-cells = <1>;
3655 }; 3375 };
3656 3376
3657 watchdog@17c10000 { 3377 watchdog@17c10000 {
3658 compatible = "qcom,ap 3378 compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt";
3659 reg = <0 0x17c10000 0 3379 reg = <0 0x17c10000 0 0x1000>;
3660 clocks = <&sleep_clk> 3380 clocks = <&sleep_clk>;
3661 interrupts = <GIC_SPI 3381 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
3662 }; 3382 };
3663 3383
3664 timer@17c20000 { !! 3384 timer@17c20000{
3665 #address-cells = <1>; 3385 #address-cells = <1>;
3666 #size-cells = <1>; 3386 #size-cells = <1>;
3667 ranges = <0 0 0 0x200 3387 ranges = <0 0 0 0x20000000>;
3668 compatible = "arm,arm 3388 compatible = "arm,armv7-timer-mem";
3669 reg = <0 0x17c20000 0 3389 reg = <0 0x17c20000 0 0x1000>;
3670 3390
3671 frame@17c21000 { 3391 frame@17c21000 {
3672 frame-number 3392 frame-number = <0>;
3673 interrupts = 3393 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
3674 3394 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
3675 reg = <0x17c2 3395 reg = <0x17c21000 0x1000>,
3676 <0x17c2 3396 <0x17c22000 0x1000>;
3677 }; 3397 };
3678 3398
3679 frame@17c23000 { 3399 frame@17c23000 {
3680 frame-number 3400 frame-number = <1>;
3681 interrupts = 3401 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
3682 reg = <0x17c2 3402 reg = <0x17c23000 0x1000>;
3683 status = "dis 3403 status = "disabled";
3684 }; 3404 };
3685 3405
3686 frame@17c25000 { 3406 frame@17c25000 {
3687 frame-number 3407 frame-number = <2>;
3688 interrupts = 3408 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
3689 reg = <0x17c2 3409 reg = <0x17c25000 0x1000>;
3690 status = "dis 3410 status = "disabled";
3691 }; 3411 };
3692 3412
3693 frame@17c27000 { 3413 frame@17c27000 {
3694 frame-number 3414 frame-number = <3>;
3695 interrupts = 3415 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3696 reg = <0x17c2 3416 reg = <0x17c27000 0x1000>;
3697 status = "dis 3417 status = "disabled";
3698 }; 3418 };
3699 3419
3700 frame@17c29000 { 3420 frame@17c29000 {
3701 frame-number 3421 frame-number = <4>;
3702 interrupts = 3422 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3703 reg = <0x17c2 3423 reg = <0x17c29000 0x1000>;
3704 status = "dis 3424 status = "disabled";
3705 }; 3425 };
3706 3426
3707 frame@17c2b000 { 3427 frame@17c2b000 {
3708 frame-number 3428 frame-number = <5>;
3709 interrupts = 3429 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3710 reg = <0x17c2 3430 reg = <0x17c2b000 0x1000>;
3711 status = "dis 3431 status = "disabled";
3712 }; 3432 };
3713 3433
3714 frame@17c2d000 { 3434 frame@17c2d000 {
3715 frame-number 3435 frame-number = <6>;
3716 interrupts = 3436 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
3717 reg = <0x17c2 3437 reg = <0x17c2d000 0x1000>;
3718 status = "dis 3438 status = "disabled";
3719 }; 3439 };
3720 }; 3440 };
3721 3441
3722 apps_rsc: rsc@18200000 { 3442 apps_rsc: rsc@18200000 {
3723 compatible = "qcom,rp 3443 compatible = "qcom,rpmh-rsc";
3724 reg = <0 0x18200000 0 3444 reg = <0 0x18200000 0 0x10000>,
3725 <0 0x18210000 0 3445 <0 0x18210000 0 0x10000>,
3726 <0 0x18220000 0 3446 <0 0x18220000 0 0x10000>;
3727 reg-names = "drv-0", 3447 reg-names = "drv-0", "drv-1", "drv-2";
3728 interrupts = <GIC_SPI 3448 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
3729 <GIC_SPI 3449 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
3730 <GIC_SPI 3450 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
3731 qcom,tcs-offset = <0x 3451 qcom,tcs-offset = <0xd00>;
3732 qcom,drv-id = <2>; 3452 qcom,drv-id = <2>;
3733 qcom,tcs-config = <AC 3453 qcom,tcs-config = <ACTIVE_TCS 2>,
3734 <SL 3454 <SLEEP_TCS 3>,
3735 <WA 3455 <WAKE_TCS 3>,
3736 <CO 3456 <CONTROL_TCS 1>;
3737 power-domains = <&CLU <<
3738 3457
3739 rpmhcc: clock-control 3458 rpmhcc: clock-controller {
3740 compatible = 3459 compatible = "qcom,sc7180-rpmh-clk";
3741 clocks = <&xo 3460 clocks = <&xo_board>;
3742 clock-names = 3461 clock-names = "xo";
3743 #clock-cells 3462 #clock-cells = <1>;
3744 }; 3463 };
3745 3464
3746 rpmhpd: power-control 3465 rpmhpd: power-controller {
3747 compatible = 3466 compatible = "qcom,sc7180-rpmhpd";
3748 #power-domain 3467 #power-domain-cells = <1>;
3749 operating-poi 3468 operating-points-v2 = <&rpmhpd_opp_table>;
3750 3469
3751 rpmhpd_opp_ta 3470 rpmhpd_opp_table: opp-table {
3752 compa 3471 compatible = "operating-points-v2";
3753 3472
3754 rpmhp 3473 rpmhpd_opp_ret: opp1 {
3755 3474 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3756 }; 3475 };
3757 3476
3758 rpmhp 3477 rpmhpd_opp_min_svs: opp2 {
3759 3478 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3760 }; 3479 };
3761 3480
3762 rpmhp 3481 rpmhpd_opp_low_svs: opp3 {
3763 3482 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3764 }; 3483 };
3765 3484
3766 rpmhp 3485 rpmhpd_opp_svs: opp4 {
3767 3486 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3768 }; 3487 };
3769 3488
3770 rpmhp 3489 rpmhpd_opp_svs_l1: opp5 {
3771 3490 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3772 }; 3491 };
3773 3492
3774 rpmhp 3493 rpmhpd_opp_svs_l2: opp6 {
3775 3494 opp-level = <224>;
3776 }; 3495 };
3777 3496
3778 rpmhp 3497 rpmhpd_opp_nom: opp7 {
3779 3498 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3780 }; 3499 };
3781 3500
3782 rpmhp 3501 rpmhpd_opp_nom_l1: opp8 {
3783 3502 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3784 }; 3503 };
3785 3504
3786 rpmhp 3505 rpmhpd_opp_nom_l2: opp9 {
3787 3506 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3788 }; 3507 };
3789 3508
3790 rpmhp 3509 rpmhpd_opp_turbo: opp10 {
3791 3510 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3792 }; 3511 };
3793 3512
3794 rpmhp 3513 rpmhpd_opp_turbo_l1: opp11 {
3795 3514 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3796 }; 3515 };
3797 }; 3516 };
3798 }; 3517 };
3799 3518
3800 apps_bcm_voter: bcm-v 3519 apps_bcm_voter: bcm-voter {
3801 compatible = 3520 compatible = "qcom,bcm-voter";
3802 }; 3521 };
3803 }; 3522 };
3804 3523
3805 osm_l3: interconnect@18321000 3524 osm_l3: interconnect@18321000 {
3806 compatible = "qcom,sc !! 3525 compatible = "qcom,sc7180-osm-l3";
3807 reg = <0 0x18321000 0 3526 reg = <0 0x18321000 0 0x1400>;
3808 3527
3809 clocks = <&rpmhcc RPM 3528 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3810 clock-names = "xo", " 3529 clock-names = "xo", "alternate";
3811 3530
3812 #interconnect-cells = 3531 #interconnect-cells = <1>;
3813 }; 3532 };
3814 3533
3815 cpufreq_hw: cpufreq@18323000 3534 cpufreq_hw: cpufreq@18323000 {
3816 compatible = "qcom,sc !! 3535 compatible = "qcom,cpufreq-hw";
3817 reg = <0 0x18323000 0 3536 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>;
3818 reg-names = "freq-dom 3537 reg-names = "freq-domain0", "freq-domain1";
3819 3538
3820 clocks = <&rpmhcc RPM 3539 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3821 clock-names = "xo", " 3540 clock-names = "xo", "alternate";
3822 3541
3823 #freq-domain-cells = 3542 #freq-domain-cells = <1>;
3824 #clock-cells = <1>; <<
3825 }; 3543 };
3826 3544
3827 wifi: wifi@18800000 { 3545 wifi: wifi@18800000 {
3828 compatible = "qcom,wc 3546 compatible = "qcom,wcn3990-wifi";
3829 reg = <0 0x18800000 0 3547 reg = <0 0x18800000 0 0x800000>;
3830 reg-names = "membase" 3548 reg-names = "membase";
3831 iommus = <&apps_smmu 3549 iommus = <&apps_smmu 0xc0 0x1>;
3832 interrupts = 3550 interrupts =
3833 <GIC_SPI 414 3551 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH /* CE0 */ >,
3834 <GIC_SPI 415 3552 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH /* CE1 */ >,
3835 <GIC_SPI 416 3553 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH /* CE2 */ >,
3836 <GIC_SPI 417 3554 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH /* CE3 */ >,
3837 <GIC_SPI 418 3555 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH /* CE4 */ >,
3838 <GIC_SPI 419 3556 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH /* CE5 */ >,
3839 <GIC_SPI 420 3557 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH /* CE6 */ >,
3840 <GIC_SPI 421 3558 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH /* CE7 */ >,
3841 <GIC_SPI 422 3559 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH /* CE8 */ >,
3842 <GIC_SPI 423 3560 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH /* CE9 */ >,
3843 <GIC_SPI 424 3561 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH /* CE10 */>,
3844 <GIC_SPI 425 3562 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH /* CE11 */>;
3845 memory-region = <&wla 3563 memory-region = <&wlan_mem>;
3846 qcom,msa-fixed-perm; 3564 qcom,msa-fixed-perm;
3847 status = "disabled"; 3565 status = "disabled";
3848 }; 3566 };
3849 3567
3850 remoteproc_adsp: remoteproc@6 <<
3851 compatible = "qcom,sc <<
3852 reg = <0 0x62400000 0 <<
3853 <<
3854 interrupts-extended = <<
3855 <<
3856 <<
3857 <<
3858 <<
3859 interrupt-names = "wd <<
3860 "fa <<
3861 "re <<
3862 "ha <<
3863 "st <<
3864 <<
3865 clocks = <&rpmhcc RPM <<
3866 clock-names = "xo"; <<
3867 <<
3868 power-domains = <&rpm <<
3869 <&rpm <<
3870 power-domain-names = <<
3871 <<
3872 qcom,qmp = <&aoss_qmp <<
3873 qcom,smem-states = <& <<
3874 qcom,smem-state-names <<
3875 <<
3876 status = "disabled"; <<
3877 <<
3878 glink-edge { <<
3879 interrupts = <<
3880 label = "lpas <<
3881 qcom,remote-p <<
3882 mboxes = <&ap <<
3883 <<
3884 apr { <<
3885 compa <<
3886 qcom, <<
3887 qcom, <<
3888 #addr <<
3889 #size <<
3890 <<
3891 servi <<
3892 <<
3893 <<
3894 <<
3895 }; <<
3896 <<
3897 q6afe <<
3898 <<
3899 <<
3900 <<
3901 <<
3902 <<
3903 <<
3904 <<
3905 <<
3906 <<
3907 <<
3908 <<
3909 <<
3910 <<
3911 <<
3912 <<
3913 }; <<
3914 <<
3915 q6asm <<
3916 <<
3917 <<
3918 <<
3919 <<
3920 <<
3921 <<
3922 <<
3923 <<
3924 <<
3925 <<
3926 <<
3927 }; <<
3928 <<
3929 q6adm <<
3930 <<
3931 <<
3932 <<
3933 <<
3934 <<
3935 <<
3936 <<
3937 <<
3938 }; <<
3939 }; <<
3940 <<
3941 fastrpc { <<
3942 compa <<
3943 qcom, <<
3944 label <<
3945 #addr <<
3946 #size <<
3947 <<
3948 compu <<
3949 <<
3950 <<
3951 <<
3952 }; <<
3953 <<
3954 compu <<
3955 <<
3956 <<
3957 <<
3958 }; <<
3959 <<
3960 compu <<
3961 <<
3962 <<
3963 <<
3964 <<
3965 }; <<
3966 }; <<
3967 }; <<
3968 }; <<
3969 <<
3970 lpasscc: clock-controller@62d 3568 lpasscc: clock-controller@62d00000 {
3971 compatible = "qcom,sc 3569 compatible = "qcom,sc7180-lpasscorecc";
3972 reg = <0 0x62d00000 0 3570 reg = <0 0x62d00000 0 0x50000>,
3973 <0 0x62780000 0 3571 <0 0x62780000 0 0x30000>;
3974 reg-names = "lpass_co 3572 reg-names = "lpass_core_cc", "lpass_audio_cc";
3975 clocks = <&gcc GCC_LP 3573 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>,
3976 <&rpmhcc RPM 3574 <&rpmhcc RPMH_CXO_CLK>;
3977 clock-names = "iface" 3575 clock-names = "iface", "bi_tcxo";
3978 power-domains = <&lpa 3576 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>;
3979 #clock-cells = <1>; 3577 #clock-cells = <1>;
3980 #power-domain-cells = 3578 #power-domain-cells = <1>;
3981 <<
3982 status = "reserved"; <<
3983 }; 3579 };
3984 3580
3985 lpass_cpu: lpass@62d87000 { 3581 lpass_cpu: lpass@62d87000 {
3986 compatible = "qcom,sc 3582 compatible = "qcom,sc7180-lpass-cpu";
3987 3583
3988 reg = <0 0x62d87000 0 3584 reg = <0 0x62d87000 0 0x68000>, <0 0x62f00000 0 0x29000>;
3989 reg-names = "lpass-hd 3585 reg-names = "lpass-hdmiif", "lpass-lpaif";
3990 3586
3991 iommus = <&apps_smmu 3587 iommus = <&apps_smmu 0x1020 0>,
3992 <&apps_smmu 0 3588 <&apps_smmu 0x1021 0>,
3993 <&apps_smmu 0 3589 <&apps_smmu 0x1032 0>;
3994 3590
3995 power-domains = <&lpa 3591 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>;
3996 required-opps = <&rpm <<
3997 3592
3998 status = "disabled"; 3593 status = "disabled";
3999 3594
4000 clocks = <&gcc GCC_LP 3595 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>,
4001 <&lpasscc LP 3596 <&lpasscc LPASS_AUDIO_CORE_CORE_CLK>,
4002 <&lpasscc LP 3597 <&lpasscc LPASS_AUDIO_CORE_EXT_MCLK0_CLK>,
4003 <&lpasscc LP 3598 <&lpasscc LPASS_AUDIO_CORE_SYSNOC_MPORT_CORE_CLK>,
4004 <&lpasscc LP 3599 <&lpasscc LPASS_AUDIO_CORE_LPAIF_PRI_IBIT_CLK>,
4005 <&lpasscc LP 3600 <&lpasscc LPASS_AUDIO_CORE_LPAIF_SEC_IBIT_CLK>;
4006 3601
4007 clock-names = "pcnoc- 3602 clock-names = "pcnoc-sway-clk", "audio-core",
4008 "mclk 3603 "mclk0", "pcnoc-mport-clk",
4009 "mi2s 3604 "mi2s-bit-clk0", "mi2s-bit-clk1";
4010 3605
4011 3606
4012 #sound-dai-cells = <1 3607 #sound-dai-cells = <1>;
4013 #address-cells = <1>; 3608 #address-cells = <1>;
4014 #size-cells = <0>; 3609 #size-cells = <0>;
4015 3610
4016 interrupts = <GIC_SPI 3611 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
4017 <GIC_ 3612 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
4018 interrupt-names = "lp 3613 interrupt-names = "lpass-irq-lpaif", "lpass-irq-hdmi";
4019 }; 3614 };
4020 3615
4021 lpass_hm: clock-controller@63 3616 lpass_hm: clock-controller@63000000 {
4022 compatible = "qcom,sc 3617 compatible = "qcom,sc7180-lpasshm";
4023 reg = <0 0x63000000 0 3618 reg = <0 0x63000000 0 0x28>;
4024 clocks = <&gcc GCC_LP 3619 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>,
4025 <&rpmhcc RPM 3620 <&rpmhcc RPMH_CXO_CLK>;
4026 clock-names = "iface" 3621 clock-names = "iface", "bi_tcxo";
4027 power-domains = <&rpm <<
4028 <<
4029 #clock-cells = <1>; 3622 #clock-cells = <1>;
4030 #power-domain-cells = 3623 #power-domain-cells = <1>;
4031 <<
4032 status = "reserved"; <<
4033 }; 3624 };
4034 }; 3625 };
4035 3626
4036 thermal-zones { 3627 thermal-zones {
4037 cpu0_thermal: cpu0-thermal { 3628 cpu0_thermal: cpu0-thermal {
4038 polling-delay-passive 3629 polling-delay-passive = <250>;
>> 3630 polling-delay = <0>;
4039 3631
4040 thermal-sensors = <&t 3632 thermal-sensors = <&tsens0 1>;
4041 sustainable-power = < 3633 sustainable-power = <1052>;
4042 3634
4043 trips { 3635 trips {
4044 cpu0_alert0: 3636 cpu0_alert0: trip-point0 {
4045 tempe 3637 temperature = <90000>;
4046 hyste 3638 hysteresis = <2000>;
4047 type 3639 type = "passive";
4048 }; 3640 };
4049 3641
4050 cpu0_alert1: 3642 cpu0_alert1: trip-point1 {
4051 tempe 3643 temperature = <95000>;
4052 hyste 3644 hysteresis = <2000>;
4053 type 3645 type = "passive";
4054 }; 3646 };
4055 3647
4056 cpu0_crit: cp !! 3648 cpu0_crit: cpu_crit {
4057 tempe 3649 temperature = <110000>;
4058 hyste 3650 hysteresis = <1000>;
4059 type 3651 type = "critical";
4060 }; 3652 };
4061 }; 3653 };
4062 3654
4063 cooling-maps { 3655 cooling-maps {
4064 map0 { 3656 map0 {
4065 trip 3657 trip = <&cpu0_alert0>;
4066 cooli 3658 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4067 3659 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4068 3660 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4069 3661 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4070 3662 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4071 3663 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4072 }; 3664 };
4073 map1 { 3665 map1 {
4074 trip 3666 trip = <&cpu0_alert1>;
4075 cooli 3667 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4076 3668 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4077 3669 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4078 3670 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4079 3671 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4080 3672 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4081 }; 3673 };
4082 }; 3674 };
4083 }; 3675 };
4084 3676
4085 cpu1_thermal: cpu1-thermal { 3677 cpu1_thermal: cpu1-thermal {
4086 polling-delay-passive 3678 polling-delay-passive = <250>;
>> 3679 polling-delay = <0>;
4087 3680
4088 thermal-sensors = <&t 3681 thermal-sensors = <&tsens0 2>;
4089 sustainable-power = < 3682 sustainable-power = <1052>;
4090 3683
4091 trips { 3684 trips {
4092 cpu1_alert0: 3685 cpu1_alert0: trip-point0 {
4093 tempe 3686 temperature = <90000>;
4094 hyste 3687 hysteresis = <2000>;
4095 type 3688 type = "passive";
4096 }; 3689 };
4097 3690
4098 cpu1_alert1: 3691 cpu1_alert1: trip-point1 {
4099 tempe 3692 temperature = <95000>;
4100 hyste 3693 hysteresis = <2000>;
4101 type 3694 type = "passive";
4102 }; 3695 };
4103 3696
4104 cpu1_crit: cp !! 3697 cpu1_crit: cpu_crit {
4105 tempe 3698 temperature = <110000>;
4106 hyste 3699 hysteresis = <1000>;
4107 type 3700 type = "critical";
4108 }; 3701 };
4109 }; 3702 };
4110 3703
4111 cooling-maps { 3704 cooling-maps {
4112 map0 { 3705 map0 {
4113 trip 3706 trip = <&cpu1_alert0>;
4114 cooli 3707 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4115 3708 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4116 3709 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4117 3710 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4118 3711 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4119 3712 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4120 }; 3713 };
4121 map1 { 3714 map1 {
4122 trip 3715 trip = <&cpu1_alert1>;
4123 cooli 3716 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4124 3717 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4125 3718 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4126 3719 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4127 3720 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4128 3721 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4129 }; 3722 };
4130 }; 3723 };
4131 }; 3724 };
4132 3725
4133 cpu2_thermal: cpu2-thermal { 3726 cpu2_thermal: cpu2-thermal {
4134 polling-delay-passive 3727 polling-delay-passive = <250>;
>> 3728 polling-delay = <0>;
4135 3729
4136 thermal-sensors = <&t 3730 thermal-sensors = <&tsens0 3>;
4137 sustainable-power = < 3731 sustainable-power = <1052>;
4138 3732
4139 trips { 3733 trips {
4140 cpu2_alert0: 3734 cpu2_alert0: trip-point0 {
4141 tempe 3735 temperature = <90000>;
4142 hyste 3736 hysteresis = <2000>;
4143 type 3737 type = "passive";
4144 }; 3738 };
4145 3739
4146 cpu2_alert1: 3740 cpu2_alert1: trip-point1 {
4147 tempe 3741 temperature = <95000>;
4148 hyste 3742 hysteresis = <2000>;
4149 type 3743 type = "passive";
4150 }; 3744 };
4151 3745
4152 cpu2_crit: cp !! 3746 cpu2_crit: cpu_crit {
4153 tempe 3747 temperature = <110000>;
4154 hyste 3748 hysteresis = <1000>;
4155 type 3749 type = "critical";
4156 }; 3750 };
4157 }; 3751 };
4158 3752
4159 cooling-maps { 3753 cooling-maps {
4160 map0 { 3754 map0 {
4161 trip 3755 trip = <&cpu2_alert0>;
4162 cooli 3756 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4163 3757 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4164 3758 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4165 3759 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4166 3760 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4167 3761 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4168 }; 3762 };
4169 map1 { 3763 map1 {
4170 trip 3764 trip = <&cpu2_alert1>;
4171 cooli 3765 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4172 3766 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4173 3767 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4174 3768 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4175 3769 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4176 3770 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4177 }; 3771 };
4178 }; 3772 };
4179 }; 3773 };
4180 3774
4181 cpu3_thermal: cpu3-thermal { 3775 cpu3_thermal: cpu3-thermal {
4182 polling-delay-passive 3776 polling-delay-passive = <250>;
>> 3777 polling-delay = <0>;
4183 3778
4184 thermal-sensors = <&t 3779 thermal-sensors = <&tsens0 4>;
4185 sustainable-power = < 3780 sustainable-power = <1052>;
4186 3781
4187 trips { 3782 trips {
4188 cpu3_alert0: 3783 cpu3_alert0: trip-point0 {
4189 tempe 3784 temperature = <90000>;
4190 hyste 3785 hysteresis = <2000>;
4191 type 3786 type = "passive";
4192 }; 3787 };
4193 3788
4194 cpu3_alert1: 3789 cpu3_alert1: trip-point1 {
4195 tempe 3790 temperature = <95000>;
4196 hyste 3791 hysteresis = <2000>;
4197 type 3792 type = "passive";
4198 }; 3793 };
4199 3794
4200 cpu3_crit: cp !! 3795 cpu3_crit: cpu_crit {
4201 tempe 3796 temperature = <110000>;
4202 hyste 3797 hysteresis = <1000>;
4203 type 3798 type = "critical";
4204 }; 3799 };
4205 }; 3800 };
4206 3801
4207 cooling-maps { 3802 cooling-maps {
4208 map0 { 3803 map0 {
4209 trip 3804 trip = <&cpu3_alert0>;
4210 cooli 3805 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4211 3806 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4212 3807 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4213 3808 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4214 3809 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4215 3810 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4216 }; 3811 };
4217 map1 { 3812 map1 {
4218 trip 3813 trip = <&cpu3_alert1>;
4219 cooli 3814 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4220 3815 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4221 3816 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4222 3817 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4223 3818 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4224 3819 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4225 }; 3820 };
4226 }; 3821 };
4227 }; 3822 };
4228 3823
4229 cpu4_thermal: cpu4-thermal { 3824 cpu4_thermal: cpu4-thermal {
4230 polling-delay-passive 3825 polling-delay-passive = <250>;
>> 3826 polling-delay = <0>;
4231 3827
4232 thermal-sensors = <&t 3828 thermal-sensors = <&tsens0 5>;
4233 sustainable-power = < 3829 sustainable-power = <1052>;
4234 3830
4235 trips { 3831 trips {
4236 cpu4_alert0: 3832 cpu4_alert0: trip-point0 {
4237 tempe 3833 temperature = <90000>;
4238 hyste 3834 hysteresis = <2000>;
4239 type 3835 type = "passive";
4240 }; 3836 };
4241 3837
4242 cpu4_alert1: 3838 cpu4_alert1: trip-point1 {
4243 tempe 3839 temperature = <95000>;
4244 hyste 3840 hysteresis = <2000>;
4245 type 3841 type = "passive";
4246 }; 3842 };
4247 3843
4248 cpu4_crit: cp !! 3844 cpu4_crit: cpu_crit {
4249 tempe 3845 temperature = <110000>;
4250 hyste 3846 hysteresis = <1000>;
4251 type 3847 type = "critical";
4252 }; 3848 };
4253 }; 3849 };
4254 3850
4255 cooling-maps { 3851 cooling-maps {
4256 map0 { 3852 map0 {
4257 trip 3853 trip = <&cpu4_alert0>;
4258 cooli 3854 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4259 3855 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4260 3856 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4261 3857 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4262 3858 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4263 3859 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4264 }; 3860 };
4265 map1 { 3861 map1 {
4266 trip 3862 trip = <&cpu4_alert1>;
4267 cooli 3863 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4268 3864 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4269 3865 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4270 3866 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4271 3867 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4272 3868 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4273 }; 3869 };
4274 }; 3870 };
4275 }; 3871 };
4276 3872
4277 cpu5_thermal: cpu5-thermal { 3873 cpu5_thermal: cpu5-thermal {
4278 polling-delay-passive 3874 polling-delay-passive = <250>;
>> 3875 polling-delay = <0>;
4279 3876
4280 thermal-sensors = <&t 3877 thermal-sensors = <&tsens0 6>;
4281 sustainable-power = < 3878 sustainable-power = <1052>;
4282 3879
4283 trips { 3880 trips {
4284 cpu5_alert0: 3881 cpu5_alert0: trip-point0 {
4285 tempe 3882 temperature = <90000>;
4286 hyste 3883 hysteresis = <2000>;
4287 type 3884 type = "passive";
4288 }; 3885 };
4289 3886
4290 cpu5_alert1: 3887 cpu5_alert1: trip-point1 {
4291 tempe 3888 temperature = <95000>;
4292 hyste 3889 hysteresis = <2000>;
4293 type 3890 type = "passive";
4294 }; 3891 };
4295 3892
4296 cpu5_crit: cp !! 3893 cpu5_crit: cpu_crit {
4297 tempe 3894 temperature = <110000>;
4298 hyste 3895 hysteresis = <1000>;
4299 type 3896 type = "critical";
4300 }; 3897 };
4301 }; 3898 };
4302 3899
4303 cooling-maps { 3900 cooling-maps {
4304 map0 { 3901 map0 {
4305 trip 3902 trip = <&cpu5_alert0>;
4306 cooli 3903 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4307 3904 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4308 3905 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4309 3906 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4310 3907 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4311 3908 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4312 }; 3909 };
4313 map1 { 3910 map1 {
4314 trip 3911 trip = <&cpu5_alert1>;
4315 cooli 3912 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4316 3913 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4317 3914 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4318 3915 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4319 3916 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4320 3917 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4321 }; 3918 };
4322 }; 3919 };
4323 }; 3920 };
4324 3921
4325 cpu6_thermal: cpu6-thermal { 3922 cpu6_thermal: cpu6-thermal {
4326 polling-delay-passive 3923 polling-delay-passive = <250>;
>> 3924 polling-delay = <0>;
4327 3925
4328 thermal-sensors = <&t 3926 thermal-sensors = <&tsens0 9>;
4329 sustainable-power = < 3927 sustainable-power = <1425>;
4330 3928
4331 trips { 3929 trips {
4332 cpu6_alert0: 3930 cpu6_alert0: trip-point0 {
4333 tempe 3931 temperature = <90000>;
4334 hyste 3932 hysteresis = <2000>;
4335 type 3933 type = "passive";
4336 }; 3934 };
4337 3935
4338 cpu6_alert1: 3936 cpu6_alert1: trip-point1 {
4339 tempe 3937 temperature = <95000>;
4340 hyste 3938 hysteresis = <2000>;
4341 type 3939 type = "passive";
4342 }; 3940 };
4343 3941
4344 cpu6_crit: cp !! 3942 cpu6_crit: cpu_crit {
4345 tempe 3943 temperature = <110000>;
4346 hyste 3944 hysteresis = <1000>;
4347 type 3945 type = "critical";
4348 }; 3946 };
4349 }; 3947 };
4350 3948
4351 cooling-maps { 3949 cooling-maps {
4352 map0 { 3950 map0 {
4353 trip 3951 trip = <&cpu6_alert0>;
4354 cooli 3952 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4355 3953 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4356 }; 3954 };
4357 map1 { 3955 map1 {
4358 trip 3956 trip = <&cpu6_alert1>;
4359 cooli 3957 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4360 3958 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4361 }; 3959 };
4362 }; 3960 };
4363 }; 3961 };
4364 3962
4365 cpu7_thermal: cpu7-thermal { 3963 cpu7_thermal: cpu7-thermal {
4366 polling-delay-passive 3964 polling-delay-passive = <250>;
>> 3965 polling-delay = <0>;
4367 3966
4368 thermal-sensors = <&t 3967 thermal-sensors = <&tsens0 10>;
4369 sustainable-power = < 3968 sustainable-power = <1425>;
4370 3969
4371 trips { 3970 trips {
4372 cpu7_alert0: 3971 cpu7_alert0: trip-point0 {
4373 tempe 3972 temperature = <90000>;
4374 hyste 3973 hysteresis = <2000>;
4375 type 3974 type = "passive";
4376 }; 3975 };
4377 3976
4378 cpu7_alert1: 3977 cpu7_alert1: trip-point1 {
4379 tempe 3978 temperature = <95000>;
4380 hyste 3979 hysteresis = <2000>;
4381 type 3980 type = "passive";
4382 }; 3981 };
4383 3982
4384 cpu7_crit: cp !! 3983 cpu7_crit: cpu_crit {
4385 tempe 3984 temperature = <110000>;
4386 hyste 3985 hysteresis = <1000>;
4387 type 3986 type = "critical";
4388 }; 3987 };
4389 }; 3988 };
4390 3989
4391 cooling-maps { 3990 cooling-maps {
4392 map0 { 3991 map0 {
4393 trip 3992 trip = <&cpu7_alert0>;
4394 cooli 3993 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4395 3994 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4396 }; 3995 };
4397 map1 { 3996 map1 {
4398 trip 3997 trip = <&cpu7_alert1>;
4399 cooli 3998 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4400 3999 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4401 }; 4000 };
4402 }; 4001 };
4403 }; 4002 };
4404 4003
4405 cpu8_thermal: cpu8-thermal { 4004 cpu8_thermal: cpu8-thermal {
4406 polling-delay-passive 4005 polling-delay-passive = <250>;
>> 4006 polling-delay = <0>;
4407 4007
4408 thermal-sensors = <&t 4008 thermal-sensors = <&tsens0 11>;
4409 sustainable-power = < 4009 sustainable-power = <1425>;
4410 4010
4411 trips { 4011 trips {
4412 cpu8_alert0: 4012 cpu8_alert0: trip-point0 {
4413 tempe 4013 temperature = <90000>;
4414 hyste 4014 hysteresis = <2000>;
4415 type 4015 type = "passive";
4416 }; 4016 };
4417 4017
4418 cpu8_alert1: 4018 cpu8_alert1: trip-point1 {
4419 tempe 4019 temperature = <95000>;
4420 hyste 4020 hysteresis = <2000>;
4421 type 4021 type = "passive";
4422 }; 4022 };
4423 4023
4424 cpu8_crit: cp !! 4024 cpu8_crit: cpu_crit {
4425 tempe 4025 temperature = <110000>;
4426 hyste 4026 hysteresis = <1000>;
4427 type 4027 type = "critical";
4428 }; 4028 };
4429 }; 4029 };
4430 4030
4431 cooling-maps { 4031 cooling-maps {
4432 map0 { 4032 map0 {
4433 trip 4033 trip = <&cpu8_alert0>;
4434 cooli 4034 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4435 4035 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4436 }; 4036 };
4437 map1 { 4037 map1 {
4438 trip 4038 trip = <&cpu8_alert1>;
4439 cooli 4039 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4440 4040 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4441 }; 4041 };
4442 }; 4042 };
4443 }; 4043 };
4444 4044
4445 cpu9_thermal: cpu9-thermal { 4045 cpu9_thermal: cpu9-thermal {
4446 polling-delay-passive 4046 polling-delay-passive = <250>;
>> 4047 polling-delay = <0>;
4447 4048
4448 thermal-sensors = <&t 4049 thermal-sensors = <&tsens0 12>;
4449 sustainable-power = < 4050 sustainable-power = <1425>;
4450 4051
4451 trips { 4052 trips {
4452 cpu9_alert0: 4053 cpu9_alert0: trip-point0 {
4453 tempe 4054 temperature = <90000>;
4454 hyste 4055 hysteresis = <2000>;
4455 type 4056 type = "passive";
4456 }; 4057 };
4457 4058
4458 cpu9_alert1: 4059 cpu9_alert1: trip-point1 {
4459 tempe 4060 temperature = <95000>;
4460 hyste 4061 hysteresis = <2000>;
4461 type 4062 type = "passive";
4462 }; 4063 };
4463 4064
4464 cpu9_crit: cp !! 4065 cpu9_crit: cpu_crit {
4465 tempe 4066 temperature = <110000>;
4466 hyste 4067 hysteresis = <1000>;
4467 type 4068 type = "critical";
4468 }; 4069 };
4469 }; 4070 };
4470 4071
4471 cooling-maps { 4072 cooling-maps {
4472 map0 { 4073 map0 {
4473 trip 4074 trip = <&cpu9_alert0>;
4474 cooli 4075 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4475 4076 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4476 }; 4077 };
4477 map1 { 4078 map1 {
4478 trip 4079 trip = <&cpu9_alert1>;
4479 cooli 4080 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4480 4081 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4481 }; 4082 };
4482 }; 4083 };
4483 }; 4084 };
4484 4085
4485 aoss0-thermal { 4086 aoss0-thermal {
4486 polling-delay-passive 4087 polling-delay-passive = <250>;
>> 4088 polling-delay = <0>;
4487 4089
4488 thermal-sensors = <&t 4090 thermal-sensors = <&tsens0 0>;
4489 4091
4490 trips { 4092 trips {
4491 aoss0_alert0: 4093 aoss0_alert0: trip-point0 {
4492 tempe 4094 temperature = <90000>;
4493 hyste 4095 hysteresis = <2000>;
4494 type 4096 type = "hot";
4495 }; 4097 };
4496 4098
4497 aoss0_crit: a !! 4099 aoss0_crit: aoss0_crit {
4498 tempe 4100 temperature = <110000>;
4499 hyste 4101 hysteresis = <2000>;
4500 type 4102 type = "critical";
4501 }; 4103 };
4502 }; 4104 };
4503 }; 4105 };
4504 4106
4505 cpuss0-thermal { 4107 cpuss0-thermal {
4506 polling-delay-passive 4108 polling-delay-passive = <250>;
>> 4109 polling-delay = <0>;
4507 4110
4508 thermal-sensors = <&t 4111 thermal-sensors = <&tsens0 7>;
4509 4112
4510 trips { 4113 trips {
4511 cpuss0_alert0 4114 cpuss0_alert0: trip-point0 {
4512 tempe 4115 temperature = <90000>;
4513 hyste 4116 hysteresis = <2000>;
4514 type 4117 type = "hot";
4515 }; 4118 };
4516 cpuss0_crit: !! 4119 cpuss0_crit: cluster0_crit {
4517 tempe 4120 temperature = <110000>;
4518 hyste 4121 hysteresis = <2000>;
4519 type 4122 type = "critical";
4520 }; 4123 };
4521 }; 4124 };
4522 }; 4125 };
4523 4126
4524 cpuss1-thermal { 4127 cpuss1-thermal {
4525 polling-delay-passive 4128 polling-delay-passive = <250>;
>> 4129 polling-delay = <0>;
4526 4130
4527 thermal-sensors = <&t 4131 thermal-sensors = <&tsens0 8>;
4528 4132
4529 trips { 4133 trips {
4530 cpuss1_alert0 4134 cpuss1_alert0: trip-point0 {
4531 tempe 4135 temperature = <90000>;
4532 hyste 4136 hysteresis = <2000>;
4533 type 4137 type = "hot";
4534 }; 4138 };
4535 cpuss1_crit: !! 4139 cpuss1_crit: cluster0_crit {
4536 tempe 4140 temperature = <110000>;
4537 hyste 4141 hysteresis = <2000>;
4538 type 4142 type = "critical";
4539 }; 4143 };
4540 }; 4144 };
4541 }; 4145 };
4542 4146
4543 gpuss0-thermal { 4147 gpuss0-thermal {
4544 polling-delay-passive 4148 polling-delay-passive = <250>;
>> 4149 polling-delay = <0>;
4545 4150
4546 thermal-sensors = <&t 4151 thermal-sensors = <&tsens0 13>;
4547 4152
4548 trips { 4153 trips {
4549 gpuss0_alert0 4154 gpuss0_alert0: trip-point0 {
4550 tempe 4155 temperature = <95000>;
4551 hyste 4156 hysteresis = <2000>;
4552 type 4157 type = "passive";
4553 }; 4158 };
4554 4159
4555 gpuss0_crit: !! 4160 gpuss0_crit: gpuss0_crit {
4556 tempe 4161 temperature = <110000>;
4557 hyste 4162 hysteresis = <2000>;
4558 type 4163 type = "critical";
4559 }; 4164 };
4560 }; 4165 };
4561 4166
4562 cooling-maps { 4167 cooling-maps {
4563 map0 { 4168 map0 {
4564 trip 4169 trip = <&gpuss0_alert0>;
4565 cooli 4170 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4566 }; 4171 };
4567 }; 4172 };
4568 }; 4173 };
4569 4174
4570 gpuss1-thermal { 4175 gpuss1-thermal {
4571 polling-delay-passive 4176 polling-delay-passive = <250>;
>> 4177 polling-delay = <0>;
4572 4178
4573 thermal-sensors = <&t 4179 thermal-sensors = <&tsens0 14>;
4574 4180
4575 trips { 4181 trips {
4576 gpuss1_alert0 4182 gpuss1_alert0: trip-point0 {
4577 tempe 4183 temperature = <95000>;
4578 hyste 4184 hysteresis = <2000>;
4579 type 4185 type = "passive";
4580 }; 4186 };
4581 4187
4582 gpuss1_crit: !! 4188 gpuss1_crit: gpuss1_crit {
4583 tempe 4189 temperature = <110000>;
4584 hyste 4190 hysteresis = <2000>;
4585 type 4191 type = "critical";
4586 }; 4192 };
4587 }; 4193 };
4588 4194
4589 cooling-maps { 4195 cooling-maps {
4590 map0 { 4196 map0 {
4591 trip 4197 trip = <&gpuss1_alert0>;
4592 cooli 4198 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4593 }; 4199 };
4594 }; 4200 };
4595 }; 4201 };
4596 4202
4597 aoss1-thermal { 4203 aoss1-thermal {
4598 polling-delay-passive 4204 polling-delay-passive = <250>;
>> 4205 polling-delay = <0>;
4599 4206
4600 thermal-sensors = <&t 4207 thermal-sensors = <&tsens1 0>;
4601 4208
4602 trips { 4209 trips {
4603 aoss1_alert0: 4210 aoss1_alert0: trip-point0 {
4604 tempe 4211 temperature = <90000>;
4605 hyste 4212 hysteresis = <2000>;
4606 type 4213 type = "hot";
4607 }; 4214 };
4608 4215
4609 aoss1_crit: a !! 4216 aoss1_crit: aoss1_crit {
4610 tempe 4217 temperature = <110000>;
4611 hyste 4218 hysteresis = <2000>;
4612 type 4219 type = "critical";
4613 }; 4220 };
4614 }; 4221 };
4615 }; 4222 };
4616 4223
4617 cwlan-thermal { 4224 cwlan-thermal {
4618 polling-delay-passive 4225 polling-delay-passive = <250>;
>> 4226 polling-delay = <0>;
4619 4227
4620 thermal-sensors = <&t 4228 thermal-sensors = <&tsens1 1>;
4621 4229
4622 trips { 4230 trips {
4623 cwlan_alert0: 4231 cwlan_alert0: trip-point0 {
4624 tempe 4232 temperature = <90000>;
4625 hyste 4233 hysteresis = <2000>;
4626 type 4234 type = "hot";
4627 }; 4235 };
4628 4236
4629 cwlan_crit: c !! 4237 cwlan_crit: cwlan_crit {
4630 tempe 4238 temperature = <110000>;
4631 hyste 4239 hysteresis = <2000>;
4632 type 4240 type = "critical";
4633 }; 4241 };
4634 }; 4242 };
4635 }; 4243 };
4636 4244
4637 audio-thermal { 4245 audio-thermal {
4638 polling-delay-passive 4246 polling-delay-passive = <250>;
>> 4247 polling-delay = <0>;
4639 4248
4640 thermal-sensors = <&t 4249 thermal-sensors = <&tsens1 2>;
4641 4250
4642 trips { 4251 trips {
4643 audio_alert0: 4252 audio_alert0: trip-point0 {
4644 tempe 4253 temperature = <90000>;
4645 hyste 4254 hysteresis = <2000>;
4646 type 4255 type = "hot";
4647 }; 4256 };
4648 4257
4649 audio_crit: a !! 4258 audio_crit: audio_crit {
4650 tempe 4259 temperature = <110000>;
4651 hyste 4260 hysteresis = <2000>;
4652 type 4261 type = "critical";
4653 }; 4262 };
4654 }; 4263 };
4655 }; 4264 };
4656 4265
4657 ddr-thermal { 4266 ddr-thermal {
4658 polling-delay-passive 4267 polling-delay-passive = <250>;
>> 4268 polling-delay = <0>;
4659 4269
4660 thermal-sensors = <&t 4270 thermal-sensors = <&tsens1 3>;
4661 4271
4662 trips { 4272 trips {
4663 ddr_alert0: t 4273 ddr_alert0: trip-point0 {
4664 tempe 4274 temperature = <90000>;
4665 hyste 4275 hysteresis = <2000>;
4666 type 4276 type = "hot";
4667 }; 4277 };
4668 4278
4669 ddr_crit: ddr !! 4279 ddr_crit: ddr_crit {
4670 tempe 4280 temperature = <110000>;
4671 hyste 4281 hysteresis = <2000>;
4672 type 4282 type = "critical";
4673 }; 4283 };
4674 }; 4284 };
4675 }; 4285 };
4676 4286
4677 q6-hvx-thermal { 4287 q6-hvx-thermal {
4678 polling-delay-passive 4288 polling-delay-passive = <250>;
>> 4289 polling-delay = <0>;
4679 4290
4680 thermal-sensors = <&t 4291 thermal-sensors = <&tsens1 4>;
4681 4292
4682 trips { 4293 trips {
4683 q6_hvx_alert0 4294 q6_hvx_alert0: trip-point0 {
4684 tempe 4295 temperature = <90000>;
4685 hyste 4296 hysteresis = <2000>;
4686 type 4297 type = "hot";
4687 }; 4298 };
4688 4299
4689 q6_hvx_crit: !! 4300 q6_hvx_crit: q6_hvx_crit {
4690 tempe 4301 temperature = <110000>;
4691 hyste 4302 hysteresis = <2000>;
4692 type 4303 type = "critical";
4693 }; 4304 };
4694 }; 4305 };
4695 }; 4306 };
4696 4307
4697 camera-thermal { 4308 camera-thermal {
4698 polling-delay-passive 4309 polling-delay-passive = <250>;
>> 4310 polling-delay = <0>;
4699 4311
4700 thermal-sensors = <&t 4312 thermal-sensors = <&tsens1 5>;
4701 4313
4702 trips { 4314 trips {
4703 camera_alert0 4315 camera_alert0: trip-point0 {
4704 tempe 4316 temperature = <90000>;
4705 hyste 4317 hysteresis = <2000>;
4706 type 4318 type = "hot";
4707 }; 4319 };
4708 4320
4709 camera_crit: !! 4321 camera_crit: camera_crit {
4710 tempe 4322 temperature = <110000>;
4711 hyste 4323 hysteresis = <2000>;
4712 type 4324 type = "critical";
4713 }; 4325 };
4714 }; 4326 };
4715 }; 4327 };
4716 4328
4717 mdm-core-thermal { 4329 mdm-core-thermal {
4718 polling-delay-passive 4330 polling-delay-passive = <250>;
>> 4331 polling-delay = <0>;
4719 4332
4720 thermal-sensors = <&t 4333 thermal-sensors = <&tsens1 6>;
4721 4334
4722 trips { 4335 trips {
4723 mdm_alert0: t 4336 mdm_alert0: trip-point0 {
4724 tempe 4337 temperature = <90000>;
4725 hyste 4338 hysteresis = <2000>;
4726 type 4339 type = "hot";
4727 }; 4340 };
4728 4341
4729 mdm_crit: mdm !! 4342 mdm_crit: mdm_crit {
4730 tempe 4343 temperature = <110000>;
4731 hyste 4344 hysteresis = <2000>;
4732 type 4345 type = "critical";
4733 }; 4346 };
4734 }; 4347 };
4735 }; 4348 };
4736 4349
4737 mdm-dsp-thermal { 4350 mdm-dsp-thermal {
4738 polling-delay-passive 4351 polling-delay-passive = <250>;
>> 4352 polling-delay = <0>;
4739 4353
4740 thermal-sensors = <&t 4354 thermal-sensors = <&tsens1 7>;
4741 4355
4742 trips { 4356 trips {
4743 mdm_dsp_alert 4357 mdm_dsp_alert0: trip-point0 {
4744 tempe 4358 temperature = <90000>;
4745 hyste 4359 hysteresis = <2000>;
4746 type 4360 type = "hot";
4747 }; 4361 };
4748 4362
4749 mdm_dsp_crit: !! 4363 mdm_dsp_crit: mdm_dsp_crit {
4750 tempe 4364 temperature = <110000>;
4751 hyste 4365 hysteresis = <2000>;
4752 type 4366 type = "critical";
4753 }; 4367 };
4754 }; 4368 };
4755 }; 4369 };
4756 4370
4757 npu-thermal { 4371 npu-thermal {
4758 polling-delay-passive 4372 polling-delay-passive = <250>;
>> 4373 polling-delay = <0>;
4759 4374
4760 thermal-sensors = <&t 4375 thermal-sensors = <&tsens1 8>;
4761 4376
4762 trips { 4377 trips {
4763 npu_alert0: t 4378 npu_alert0: trip-point0 {
4764 tempe 4379 temperature = <90000>;
4765 hyste 4380 hysteresis = <2000>;
4766 type 4381 type = "hot";
4767 }; 4382 };
4768 4383
4769 npu_crit: npu !! 4384 npu_crit: npu_crit {
4770 tempe 4385 temperature = <110000>;
4771 hyste 4386 hysteresis = <2000>;
4772 type 4387 type = "critical";
4773 }; 4388 };
4774 }; 4389 };
4775 }; 4390 };
4776 4391
4777 video-thermal { 4392 video-thermal {
4778 polling-delay-passive 4393 polling-delay-passive = <250>;
>> 4394 polling-delay = <0>;
4779 4395
4780 thermal-sensors = <&t 4396 thermal-sensors = <&tsens1 9>;
4781 4397
4782 trips { 4398 trips {
4783 video_alert0: 4399 video_alert0: trip-point0 {
4784 tempe 4400 temperature = <90000>;
4785 hyste 4401 hysteresis = <2000>;
4786 type 4402 type = "hot";
4787 }; 4403 };
4788 4404
4789 video_crit: v !! 4405 video_crit: video_crit {
4790 tempe 4406 temperature = <110000>;
4791 hyste 4407 hysteresis = <2000>;
4792 type 4408 type = "critical";
4793 }; 4409 };
4794 }; 4410 };
4795 }; 4411 };
4796 }; 4412 };
4797 4413
4798 timer { 4414 timer {
4799 compatible = "arm,armv8-timer 4415 compatible = "arm,armv8-timer";
4800 interrupts = <GIC_PPI 1 IRQ_T 4416 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
4801 <GIC_PPI 2 IRQ_T 4417 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
4802 <GIC_PPI 3 IRQ_T 4418 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
4803 <GIC_PPI 0 IRQ_T 4419 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
4804 }; 4420 };
4805 }; 4421 };
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