1 // SPDX-License-Identifier: BSD-3-Clause 1 // SPDX-License-Identifier: BSD-3-Clause
2 /* 2 /*
3 * SC7180 SoC device tree source 3 * SC7180 SoC device tree source
4 * 4 *
5 * Copyright (c) 2019-2020, The Linux Foundati 5 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
6 */ 6 */
7 7
8 #include <dt-bindings/clock/qcom,dispcc-sc7180 8 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
9 #include <dt-bindings/clock/qcom,gcc-sc7180.h> 9 #include <dt-bindings/clock/qcom,gcc-sc7180.h>
10 #include <dt-bindings/clock/qcom,gpucc-sc7180. 10 #include <dt-bindings/clock/qcom,gpucc-sc7180.h>
11 #include <dt-bindings/clock/qcom,lpasscorecc-s 11 #include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h>
12 #include <dt-bindings/clock/qcom,rpmh.h> 12 #include <dt-bindings/clock/qcom,rpmh.h>
13 #include <dt-bindings/clock/qcom,videocc-sc718 13 #include <dt-bindings/clock/qcom,videocc-sc7180.h>
14 #include <dt-bindings/firmware/qcom,scm.h> <<
15 #include <dt-bindings/interconnect/qcom,icc.h> <<
16 #include <dt-bindings/interconnect/qcom,osm-l3 14 #include <dt-bindings/interconnect/qcom,osm-l3.h>
17 #include <dt-bindings/interconnect/qcom,sc7180 15 #include <dt-bindings/interconnect/qcom,sc7180.h>
18 #include <dt-bindings/interrupt-controller/arm 16 #include <dt-bindings/interrupt-controller/arm-gic.h>
19 #include <dt-bindings/phy/phy-qcom-qmp.h> <<
20 #include <dt-bindings/phy/phy-qcom-qusb2.h> 17 #include <dt-bindings/phy/phy-qcom-qusb2.h>
21 #include <dt-bindings/power/qcom-rpmpd.h> 18 #include <dt-bindings/power/qcom-rpmpd.h>
22 #include <dt-bindings/reset/qcom,sdm845-aoss.h 19 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
23 #include <dt-bindings/reset/qcom,sdm845-pdc.h> 20 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
24 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 21 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
25 #include <dt-bindings/soc/qcom,apr.h> <<
26 #include <dt-bindings/sound/qcom,q6afe.h> <<
27 #include <dt-bindings/thermal/thermal.h> 22 #include <dt-bindings/thermal/thermal.h>
28 23
29 / { 24 / {
30 interrupt-parent = <&intc>; 25 interrupt-parent = <&intc>;
31 26
32 #address-cells = <2>; 27 #address-cells = <2>;
33 #size-cells = <2>; 28 #size-cells = <2>;
34 29
35 aliases { 30 aliases {
36 mmc1 = &sdhc_1; 31 mmc1 = &sdhc_1;
37 mmc2 = &sdhc_2; 32 mmc2 = &sdhc_2;
38 i2c0 = &i2c0; 33 i2c0 = &i2c0;
39 i2c1 = &i2c1; 34 i2c1 = &i2c1;
40 i2c2 = &i2c2; 35 i2c2 = &i2c2;
41 i2c3 = &i2c3; 36 i2c3 = &i2c3;
42 i2c4 = &i2c4; 37 i2c4 = &i2c4;
43 i2c5 = &i2c5; 38 i2c5 = &i2c5;
44 i2c6 = &i2c6; 39 i2c6 = &i2c6;
45 i2c7 = &i2c7; 40 i2c7 = &i2c7;
46 i2c8 = &i2c8; 41 i2c8 = &i2c8;
47 i2c9 = &i2c9; 42 i2c9 = &i2c9;
48 i2c10 = &i2c10; 43 i2c10 = &i2c10;
49 i2c11 = &i2c11; 44 i2c11 = &i2c11;
50 spi0 = &spi0; 45 spi0 = &spi0;
51 spi1 = &spi1; 46 spi1 = &spi1;
52 spi3 = &spi3; 47 spi3 = &spi3;
53 spi5 = &spi5; 48 spi5 = &spi5;
54 spi6 = &spi6; 49 spi6 = &spi6;
55 spi8 = &spi8; 50 spi8 = &spi8;
56 spi10 = &spi10; 51 spi10 = &spi10;
57 spi11 = &spi11; 52 spi11 = &spi11;
58 }; 53 };
59 54
60 chosen { }; 55 chosen { };
61 56
62 clocks { 57 clocks {
63 xo_board: xo-board { 58 xo_board: xo-board {
64 compatible = "fixed-cl 59 compatible = "fixed-clock";
65 clock-frequency = <384 60 clock-frequency = <38400000>;
66 #clock-cells = <0>; 61 #clock-cells = <0>;
67 }; 62 };
68 63
69 sleep_clk: sleep-clk { 64 sleep_clk: sleep-clk {
70 compatible = "fixed-cl 65 compatible = "fixed-clock";
71 clock-frequency = <327 66 clock-frequency = <32764>;
72 #clock-cells = <0>; 67 #clock-cells = <0>;
73 }; 68 };
74 }; 69 };
75 70
76 cpus { 71 cpus {
77 #address-cells = <2>; 72 #address-cells = <2>;
78 #size-cells = <0>; 73 #size-cells = <0>;
79 74
80 CPU0: cpu@0 { 75 CPU0: cpu@0 {
81 device_type = "cpu"; 76 device_type = "cpu";
82 compatible = "qcom,kry 77 compatible = "qcom,kryo468";
83 reg = <0x0 0x0>; 78 reg = <0x0 0x0>;
84 clocks = <&cpufreq_hw <<
85 enable-method = "psci" 79 enable-method = "psci";
86 power-domains = <&CPU_ !! 80 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
87 power-domain-names = " !! 81 &LITTLE_CPU_SLEEP_1
>> 82 &CLUSTER_SLEEP_0>;
88 capacity-dmips-mhz = < 83 capacity-dmips-mhz = <415>;
89 dynamic-power-coeffici 84 dynamic-power-coefficient = <137>;
90 operating-points-v2 = 85 operating-points-v2 = <&cpu0_opp_table>;
91 interconnects = <&gem_ 86 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
92 <&osm_ 87 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
93 next-level-cache = <&L 88 next-level-cache = <&L2_0>;
94 #cooling-cells = <2>; 89 #cooling-cells = <2>;
95 qcom,freq-domain = <&c 90 qcom,freq-domain = <&cpufreq_hw 0>;
96 L2_0: l2-cache { 91 L2_0: l2-cache {
97 compatible = " 92 compatible = "cache";
98 cache-level = 93 cache-level = <2>;
99 cache-unified; <<
100 next-level-cac 94 next-level-cache = <&L3_0>;
101 L3_0: l3-cache 95 L3_0: l3-cache {
102 compat 96 compatible = "cache";
103 cache- 97 cache-level = <3>;
104 cache- <<
105 }; 98 };
106 }; 99 };
107 }; 100 };
108 101
109 CPU1: cpu@100 { 102 CPU1: cpu@100 {
110 device_type = "cpu"; 103 device_type = "cpu";
111 compatible = "qcom,kry 104 compatible = "qcom,kryo468";
112 reg = <0x0 0x100>; 105 reg = <0x0 0x100>;
113 clocks = <&cpufreq_hw <<
114 enable-method = "psci" 106 enable-method = "psci";
115 power-domains = <&CPU_ !! 107 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
116 power-domain-names = " !! 108 &LITTLE_CPU_SLEEP_1
>> 109 &CLUSTER_SLEEP_0>;
117 capacity-dmips-mhz = < 110 capacity-dmips-mhz = <415>;
118 dynamic-power-coeffici 111 dynamic-power-coefficient = <137>;
119 next-level-cache = <&L 112 next-level-cache = <&L2_100>;
120 operating-points-v2 = 113 operating-points-v2 = <&cpu0_opp_table>;
121 interconnects = <&gem_ 114 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
122 <&osm_ 115 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
123 #cooling-cells = <2>; 116 #cooling-cells = <2>;
124 qcom,freq-domain = <&c 117 qcom,freq-domain = <&cpufreq_hw 0>;
125 L2_100: l2-cache { 118 L2_100: l2-cache {
126 compatible = " 119 compatible = "cache";
127 cache-level = 120 cache-level = <2>;
128 cache-unified; <<
129 next-level-cac 121 next-level-cache = <&L3_0>;
130 }; 122 };
131 }; 123 };
132 124
133 CPU2: cpu@200 { 125 CPU2: cpu@200 {
134 device_type = "cpu"; 126 device_type = "cpu";
135 compatible = "qcom,kry 127 compatible = "qcom,kryo468";
136 reg = <0x0 0x200>; 128 reg = <0x0 0x200>;
137 clocks = <&cpufreq_hw <<
138 enable-method = "psci" 129 enable-method = "psci";
139 power-domains = <&CPU_ !! 130 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
140 power-domain-names = " !! 131 &LITTLE_CPU_SLEEP_1
>> 132 &CLUSTER_SLEEP_0>;
141 capacity-dmips-mhz = < 133 capacity-dmips-mhz = <415>;
142 dynamic-power-coeffici 134 dynamic-power-coefficient = <137>;
143 next-level-cache = <&L 135 next-level-cache = <&L2_200>;
144 operating-points-v2 = 136 operating-points-v2 = <&cpu0_opp_table>;
145 interconnects = <&gem_ 137 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
146 <&osm_ 138 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
147 #cooling-cells = <2>; 139 #cooling-cells = <2>;
148 qcom,freq-domain = <&c 140 qcom,freq-domain = <&cpufreq_hw 0>;
149 L2_200: l2-cache { 141 L2_200: l2-cache {
150 compatible = " 142 compatible = "cache";
151 cache-level = 143 cache-level = <2>;
152 cache-unified; <<
153 next-level-cac 144 next-level-cache = <&L3_0>;
154 }; 145 };
155 }; 146 };
156 147
157 CPU3: cpu@300 { 148 CPU3: cpu@300 {
158 device_type = "cpu"; 149 device_type = "cpu";
159 compatible = "qcom,kry 150 compatible = "qcom,kryo468";
160 reg = <0x0 0x300>; 151 reg = <0x0 0x300>;
161 clocks = <&cpufreq_hw <<
162 enable-method = "psci" 152 enable-method = "psci";
163 power-domains = <&CPU_ !! 153 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
164 power-domain-names = " !! 154 &LITTLE_CPU_SLEEP_1
>> 155 &CLUSTER_SLEEP_0>;
165 capacity-dmips-mhz = < 156 capacity-dmips-mhz = <415>;
166 dynamic-power-coeffici 157 dynamic-power-coefficient = <137>;
167 next-level-cache = <&L 158 next-level-cache = <&L2_300>;
168 operating-points-v2 = 159 operating-points-v2 = <&cpu0_opp_table>;
169 interconnects = <&gem_ 160 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
170 <&osm_ 161 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
171 #cooling-cells = <2>; 162 #cooling-cells = <2>;
172 qcom,freq-domain = <&c 163 qcom,freq-domain = <&cpufreq_hw 0>;
173 L2_300: l2-cache { 164 L2_300: l2-cache {
174 compatible = " 165 compatible = "cache";
175 cache-level = 166 cache-level = <2>;
176 cache-unified; <<
177 next-level-cac 167 next-level-cache = <&L3_0>;
178 }; 168 };
179 }; 169 };
180 170
181 CPU4: cpu@400 { 171 CPU4: cpu@400 {
182 device_type = "cpu"; 172 device_type = "cpu";
183 compatible = "qcom,kry 173 compatible = "qcom,kryo468";
184 reg = <0x0 0x400>; 174 reg = <0x0 0x400>;
185 clocks = <&cpufreq_hw <<
186 enable-method = "psci" 175 enable-method = "psci";
187 power-domains = <&CPU_ !! 176 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
188 power-domain-names = " !! 177 &LITTLE_CPU_SLEEP_1
>> 178 &CLUSTER_SLEEP_0>;
189 capacity-dmips-mhz = < 179 capacity-dmips-mhz = <415>;
190 dynamic-power-coeffici 180 dynamic-power-coefficient = <137>;
191 next-level-cache = <&L 181 next-level-cache = <&L2_400>;
192 operating-points-v2 = 182 operating-points-v2 = <&cpu0_opp_table>;
193 interconnects = <&gem_ 183 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
194 <&osm_ 184 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
195 #cooling-cells = <2>; 185 #cooling-cells = <2>;
196 qcom,freq-domain = <&c 186 qcom,freq-domain = <&cpufreq_hw 0>;
197 L2_400: l2-cache { 187 L2_400: l2-cache {
198 compatible = " 188 compatible = "cache";
199 cache-level = 189 cache-level = <2>;
200 cache-unified; <<
201 next-level-cac 190 next-level-cache = <&L3_0>;
202 }; 191 };
203 }; 192 };
204 193
205 CPU5: cpu@500 { 194 CPU5: cpu@500 {
206 device_type = "cpu"; 195 device_type = "cpu";
207 compatible = "qcom,kry 196 compatible = "qcom,kryo468";
208 reg = <0x0 0x500>; 197 reg = <0x0 0x500>;
209 clocks = <&cpufreq_hw <<
210 enable-method = "psci" 198 enable-method = "psci";
211 power-domains = <&CPU_ !! 199 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
212 power-domain-names = " !! 200 &LITTLE_CPU_SLEEP_1
>> 201 &CLUSTER_SLEEP_0>;
213 capacity-dmips-mhz = < 202 capacity-dmips-mhz = <415>;
214 dynamic-power-coeffici 203 dynamic-power-coefficient = <137>;
215 next-level-cache = <&L 204 next-level-cache = <&L2_500>;
216 operating-points-v2 = 205 operating-points-v2 = <&cpu0_opp_table>;
217 interconnects = <&gem_ 206 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
218 <&osm_ 207 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
219 #cooling-cells = <2>; 208 #cooling-cells = <2>;
220 qcom,freq-domain = <&c 209 qcom,freq-domain = <&cpufreq_hw 0>;
221 L2_500: l2-cache { 210 L2_500: l2-cache {
222 compatible = " 211 compatible = "cache";
223 cache-level = 212 cache-level = <2>;
224 cache-unified; <<
225 next-level-cac 213 next-level-cache = <&L3_0>;
226 }; 214 };
227 }; 215 };
228 216
229 CPU6: cpu@600 { 217 CPU6: cpu@600 {
230 device_type = "cpu"; 218 device_type = "cpu";
231 compatible = "qcom,kry 219 compatible = "qcom,kryo468";
232 reg = <0x0 0x600>; 220 reg = <0x0 0x600>;
233 clocks = <&cpufreq_hw <<
234 enable-method = "psci" 221 enable-method = "psci";
235 power-domains = <&CPU_ !! 222 cpu-idle-states = <&BIG_CPU_SLEEP_0
236 power-domain-names = " !! 223 &BIG_CPU_SLEEP_1
>> 224 &CLUSTER_SLEEP_0>;
237 capacity-dmips-mhz = < 225 capacity-dmips-mhz = <1024>;
238 dynamic-power-coeffici 226 dynamic-power-coefficient = <480>;
239 next-level-cache = <&L 227 next-level-cache = <&L2_600>;
240 operating-points-v2 = 228 operating-points-v2 = <&cpu6_opp_table>;
241 interconnects = <&gem_ 229 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
242 <&osm_ 230 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
243 #cooling-cells = <2>; 231 #cooling-cells = <2>;
244 qcom,freq-domain = <&c 232 qcom,freq-domain = <&cpufreq_hw 1>;
245 L2_600: l2-cache { 233 L2_600: l2-cache {
246 compatible = " 234 compatible = "cache";
247 cache-level = 235 cache-level = <2>;
248 cache-unified; <<
249 next-level-cac 236 next-level-cache = <&L3_0>;
250 }; 237 };
251 }; 238 };
252 239
253 CPU7: cpu@700 { 240 CPU7: cpu@700 {
254 device_type = "cpu"; 241 device_type = "cpu";
255 compatible = "qcom,kry 242 compatible = "qcom,kryo468";
256 reg = <0x0 0x700>; 243 reg = <0x0 0x700>;
257 clocks = <&cpufreq_hw <<
258 enable-method = "psci" 244 enable-method = "psci";
259 power-domains = <&CPU_ !! 245 cpu-idle-states = <&BIG_CPU_SLEEP_0
260 power-domain-names = " !! 246 &BIG_CPU_SLEEP_1
>> 247 &CLUSTER_SLEEP_0>;
261 capacity-dmips-mhz = < 248 capacity-dmips-mhz = <1024>;
262 dynamic-power-coeffici 249 dynamic-power-coefficient = <480>;
263 next-level-cache = <&L 250 next-level-cache = <&L2_700>;
264 operating-points-v2 = 251 operating-points-v2 = <&cpu6_opp_table>;
265 interconnects = <&gem_ 252 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
266 <&osm_ 253 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
267 #cooling-cells = <2>; 254 #cooling-cells = <2>;
268 qcom,freq-domain = <&c 255 qcom,freq-domain = <&cpufreq_hw 1>;
269 L2_700: l2-cache { 256 L2_700: l2-cache {
270 compatible = " 257 compatible = "cache";
271 cache-level = 258 cache-level = <2>;
272 cache-unified; <<
273 next-level-cac 259 next-level-cache = <&L3_0>;
274 }; 260 };
275 }; 261 };
276 262
277 cpu-map { 263 cpu-map {
278 cluster0 { 264 cluster0 {
279 core0 { 265 core0 {
280 cpu = 266 cpu = <&CPU0>;
281 }; 267 };
282 268
283 core1 { 269 core1 {
284 cpu = 270 cpu = <&CPU1>;
285 }; 271 };
286 272
287 core2 { 273 core2 {
288 cpu = 274 cpu = <&CPU2>;
289 }; 275 };
290 276
291 core3 { 277 core3 {
292 cpu = 278 cpu = <&CPU3>;
293 }; 279 };
294 280
295 core4 { 281 core4 {
296 cpu = 282 cpu = <&CPU4>;
297 }; 283 };
298 284
299 core5 { 285 core5 {
300 cpu = 286 cpu = <&CPU5>;
301 }; 287 };
302 288
303 core6 { 289 core6 {
304 cpu = 290 cpu = <&CPU6>;
305 }; 291 };
306 292
307 core7 { 293 core7 {
308 cpu = 294 cpu = <&CPU7>;
309 }; 295 };
310 }; 296 };
311 }; 297 };
312 298
313 idle_states: idle-states { !! 299 idle-states {
314 entry-method = "psci"; 300 entry-method = "psci";
315 301
316 LITTLE_CPU_SLEEP_0: cp 302 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
317 compatible = " 303 compatible = "arm,idle-state";
318 idle-state-nam 304 idle-state-name = "little-power-down";
319 arm,psci-suspe 305 arm,psci-suspend-param = <0x40000003>;
320 entry-latency- 306 entry-latency-us = <549>;
321 exit-latency-u 307 exit-latency-us = <901>;
322 min-residency- 308 min-residency-us = <1774>;
323 local-timer-st 309 local-timer-stop;
324 }; 310 };
325 311
326 LITTLE_CPU_SLEEP_1: cp 312 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
327 compatible = " 313 compatible = "arm,idle-state";
328 idle-state-nam 314 idle-state-name = "little-rail-power-down";
329 arm,psci-suspe 315 arm,psci-suspend-param = <0x40000004>;
330 entry-latency- 316 entry-latency-us = <702>;
331 exit-latency-u 317 exit-latency-us = <915>;
332 min-residency- 318 min-residency-us = <4001>;
333 local-timer-st 319 local-timer-stop;
334 }; 320 };
335 321
336 BIG_CPU_SLEEP_0: cpu-s 322 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
337 compatible = " 323 compatible = "arm,idle-state";
338 idle-state-nam 324 idle-state-name = "big-power-down";
339 arm,psci-suspe 325 arm,psci-suspend-param = <0x40000003>;
340 entry-latency- 326 entry-latency-us = <523>;
341 exit-latency-u 327 exit-latency-us = <1244>;
342 min-residency- 328 min-residency-us = <2207>;
343 local-timer-st 329 local-timer-stop;
344 }; 330 };
345 331
346 BIG_CPU_SLEEP_1: cpu-s 332 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
347 compatible = " 333 compatible = "arm,idle-state";
348 idle-state-nam 334 idle-state-name = "big-rail-power-down";
349 arm,psci-suspe 335 arm,psci-suspend-param = <0x40000004>;
350 entry-latency- 336 entry-latency-us = <526>;
351 exit-latency-u 337 exit-latency-us = <1854>;
352 min-residency- 338 min-residency-us = <5555>;
353 local-timer-st 339 local-timer-stop;
354 }; 340 };
355 }; <<
356 <<
357 domain_idle_states: domain-idl <<
358 CLUSTER_SLEEP_PC: clus <<
359 compatible = " <<
360 idle-state-nam <<
361 arm,psci-suspe <<
362 entry-latency- <<
363 exit-latency-u <<
364 min-residency- <<
365 }; <<
366 <<
367 CLUSTER_SLEEP_CX_RET: <<
368 compatible = " <<
369 idle-state-nam <<
370 arm,psci-suspe <<
371 entry-latency- <<
372 exit-latency-u <<
373 min-residency- <<
374 }; <<
375 341
376 CLUSTER_AOSS_SLEEP: cl !! 342 CLUSTER_SLEEP_0: cluster-sleep-0 {
377 compatible = " !! 343 compatible = "arm,idle-state";
378 idle-state-nam 344 idle-state-name = "cluster-power-down";
379 arm,psci-suspe !! 345 arm,psci-suspend-param = <0x40003444>;
380 entry-latency- 346 entry-latency-us = <3263>;
381 exit-latency-u 347 exit-latency-us = <6562>;
382 min-residency- !! 348 min-residency-us = <9926>;
>> 349 local-timer-stop;
383 }; 350 };
384 }; 351 };
385 }; 352 };
386 353
387 firmware { 354 firmware {
388 scm: scm { !! 355 scm {
389 compatible = "qcom,scm 356 compatible = "qcom,scm-sc7180", "qcom,scm";
390 }; 357 };
391 }; 358 };
392 359
393 memory@80000000 { 360 memory@80000000 {
394 device_type = "memory"; 361 device_type = "memory";
395 /* We expect the bootloader to 362 /* We expect the bootloader to fill in the size */
396 reg = <0 0x80000000 0 0>; 363 reg = <0 0x80000000 0 0>;
397 }; 364 };
398 365
399 cpu0_opp_table: opp-table-cpu0 { 366 cpu0_opp_table: opp-table-cpu0 {
400 compatible = "operating-points 367 compatible = "operating-points-v2";
401 opp-shared; 368 opp-shared;
402 369
403 cpu0_opp1: opp-300000000 { 370 cpu0_opp1: opp-300000000 {
404 opp-hz = /bits/ 64 <30 371 opp-hz = /bits/ 64 <300000000>;
405 opp-peak-kBps = <12000 372 opp-peak-kBps = <1200000 4800000>;
406 }; 373 };
407 374
408 cpu0_opp2: opp-576000000 { 375 cpu0_opp2: opp-576000000 {
409 opp-hz = /bits/ 64 <57 376 opp-hz = /bits/ 64 <576000000>;
410 opp-peak-kBps = <12000 377 opp-peak-kBps = <1200000 4800000>;
411 }; 378 };
412 379
413 cpu0_opp3: opp-768000000 { 380 cpu0_opp3: opp-768000000 {
414 opp-hz = /bits/ 64 <76 381 opp-hz = /bits/ 64 <768000000>;
415 opp-peak-kBps = <12000 382 opp-peak-kBps = <1200000 4800000>;
416 }; 383 };
417 384
418 cpu0_opp4: opp-1017600000 { 385 cpu0_opp4: opp-1017600000 {
419 opp-hz = /bits/ 64 <10 386 opp-hz = /bits/ 64 <1017600000>;
420 opp-peak-kBps = <18040 387 opp-peak-kBps = <1804000 8908800>;
421 }; 388 };
422 389
423 cpu0_opp5: opp-1248000000 { 390 cpu0_opp5: opp-1248000000 {
424 opp-hz = /bits/ 64 <12 391 opp-hz = /bits/ 64 <1248000000>;
425 opp-peak-kBps = <21880 392 opp-peak-kBps = <2188000 12902400>;
426 }; 393 };
427 394
428 cpu0_opp6: opp-1324800000 { 395 cpu0_opp6: opp-1324800000 {
429 opp-hz = /bits/ 64 <13 396 opp-hz = /bits/ 64 <1324800000>;
430 opp-peak-kBps = <21880 397 opp-peak-kBps = <2188000 12902400>;
431 }; 398 };
432 399
433 cpu0_opp7: opp-1516800000 { 400 cpu0_opp7: opp-1516800000 {
434 opp-hz = /bits/ 64 <15 401 opp-hz = /bits/ 64 <1516800000>;
435 opp-peak-kBps = <30720 402 opp-peak-kBps = <3072000 15052800>;
436 }; 403 };
437 404
438 cpu0_opp8: opp-1612800000 { 405 cpu0_opp8: opp-1612800000 {
439 opp-hz = /bits/ 64 <16 406 opp-hz = /bits/ 64 <1612800000>;
440 opp-peak-kBps = <30720 407 opp-peak-kBps = <3072000 15052800>;
441 }; 408 };
442 409
443 cpu0_opp9: opp-1708800000 { 410 cpu0_opp9: opp-1708800000 {
444 opp-hz = /bits/ 64 <17 411 opp-hz = /bits/ 64 <1708800000>;
445 opp-peak-kBps = <30720 412 opp-peak-kBps = <3072000 15052800>;
446 }; 413 };
447 414
448 cpu0_opp10: opp-1804800000 { 415 cpu0_opp10: opp-1804800000 {
449 opp-hz = /bits/ 64 <18 416 opp-hz = /bits/ 64 <1804800000>;
450 opp-peak-kBps = <40680 417 opp-peak-kBps = <4068000 22425600>;
451 }; 418 };
452 }; 419 };
453 420
454 cpu6_opp_table: opp-table-cpu6 { 421 cpu6_opp_table: opp-table-cpu6 {
455 compatible = "operating-points 422 compatible = "operating-points-v2";
456 opp-shared; 423 opp-shared;
457 424
458 cpu6_opp1: opp-300000000 { 425 cpu6_opp1: opp-300000000 {
459 opp-hz = /bits/ 64 <30 426 opp-hz = /bits/ 64 <300000000>;
460 opp-peak-kBps = <21880 427 opp-peak-kBps = <2188000 8908800>;
461 }; 428 };
462 429
463 cpu6_opp2: opp-652800000 { 430 cpu6_opp2: opp-652800000 {
464 opp-hz = /bits/ 64 <65 431 opp-hz = /bits/ 64 <652800000>;
465 opp-peak-kBps = <21880 432 opp-peak-kBps = <2188000 8908800>;
466 }; 433 };
467 434
468 cpu6_opp3: opp-825600000 { 435 cpu6_opp3: opp-825600000 {
469 opp-hz = /bits/ 64 <82 436 opp-hz = /bits/ 64 <825600000>;
470 opp-peak-kBps = <21880 437 opp-peak-kBps = <2188000 8908800>;
471 }; 438 };
472 439
473 cpu6_opp4: opp-979200000 { 440 cpu6_opp4: opp-979200000 {
474 opp-hz = /bits/ 64 <97 441 opp-hz = /bits/ 64 <979200000>;
475 opp-peak-kBps = <21880 442 opp-peak-kBps = <2188000 8908800>;
476 }; 443 };
477 444
478 cpu6_opp5: opp-1113600000 { 445 cpu6_opp5: opp-1113600000 {
479 opp-hz = /bits/ 64 <11 446 opp-hz = /bits/ 64 <1113600000>;
480 opp-peak-kBps = <21880 447 opp-peak-kBps = <2188000 8908800>;
481 }; 448 };
482 449
483 cpu6_opp6: opp-1267200000 { 450 cpu6_opp6: opp-1267200000 {
484 opp-hz = /bits/ 64 <12 451 opp-hz = /bits/ 64 <1267200000>;
485 opp-peak-kBps = <40680 452 opp-peak-kBps = <4068000 12902400>;
486 }; 453 };
487 454
488 cpu6_opp7: opp-1555200000 { 455 cpu6_opp7: opp-1555200000 {
489 opp-hz = /bits/ 64 <15 456 opp-hz = /bits/ 64 <1555200000>;
490 opp-peak-kBps = <40680 457 opp-peak-kBps = <4068000 15052800>;
491 }; 458 };
492 459
493 cpu6_opp8: opp-1708800000 { 460 cpu6_opp8: opp-1708800000 {
494 opp-hz = /bits/ 64 <17 461 opp-hz = /bits/ 64 <1708800000>;
495 opp-peak-kBps = <62200 462 opp-peak-kBps = <6220000 19353600>;
496 }; 463 };
497 464
498 cpu6_opp9: opp-1843200000 { 465 cpu6_opp9: opp-1843200000 {
499 opp-hz = /bits/ 64 <18 466 opp-hz = /bits/ 64 <1843200000>;
500 opp-peak-kBps = <62200 467 opp-peak-kBps = <6220000 19353600>;
501 }; 468 };
502 469
503 cpu6_opp10: opp-1900800000 { 470 cpu6_opp10: opp-1900800000 {
504 opp-hz = /bits/ 64 <19 471 opp-hz = /bits/ 64 <1900800000>;
505 opp-peak-kBps = <62200 472 opp-peak-kBps = <6220000 22425600>;
506 }; 473 };
507 474
508 cpu6_opp11: opp-1996800000 { 475 cpu6_opp11: opp-1996800000 {
509 opp-hz = /bits/ 64 <19 476 opp-hz = /bits/ 64 <1996800000>;
510 opp-peak-kBps = <62200 477 opp-peak-kBps = <6220000 22425600>;
511 }; 478 };
512 479
513 cpu6_opp12: opp-2112000000 { 480 cpu6_opp12: opp-2112000000 {
514 opp-hz = /bits/ 64 <21 481 opp-hz = /bits/ 64 <2112000000>;
515 opp-peak-kBps = <62200 482 opp-peak-kBps = <6220000 22425600>;
516 }; 483 };
517 484
518 cpu6_opp13: opp-2208000000 { 485 cpu6_opp13: opp-2208000000 {
519 opp-hz = /bits/ 64 <22 486 opp-hz = /bits/ 64 <2208000000>;
520 opp-peak-kBps = <72160 487 opp-peak-kBps = <7216000 22425600>;
521 }; 488 };
522 489
523 cpu6_opp14: opp-2323200000 { 490 cpu6_opp14: opp-2323200000 {
524 opp-hz = /bits/ 64 <23 491 opp-hz = /bits/ 64 <2323200000>;
525 opp-peak-kBps = <72160 492 opp-peak-kBps = <7216000 22425600>;
526 }; 493 };
527 494
528 cpu6_opp15: opp-2400000000 { 495 cpu6_opp15: opp-2400000000 {
529 opp-hz = /bits/ 64 <24 496 opp-hz = /bits/ 64 <2400000000>;
530 opp-peak-kBps = <85320 497 opp-peak-kBps = <8532000 23347200>;
531 }; 498 };
532 499
533 cpu6_opp16: opp-2553600000 { 500 cpu6_opp16: opp-2553600000 {
534 opp-hz = /bits/ 64 <25 501 opp-hz = /bits/ 64 <2553600000>;
535 opp-peak-kBps = <85320 502 opp-peak-kBps = <8532000 23347200>;
536 }; 503 };
537 }; 504 };
538 505
539 qspi_opp_table: opp-table-qspi { 506 qspi_opp_table: opp-table-qspi {
540 compatible = "operating-points 507 compatible = "operating-points-v2";
541 508
542 opp-75000000 { 509 opp-75000000 {
543 opp-hz = /bits/ 64 <75 510 opp-hz = /bits/ 64 <75000000>;
544 required-opps = <&rpmh 511 required-opps = <&rpmhpd_opp_low_svs>;
545 }; 512 };
546 513
547 opp-150000000 { 514 opp-150000000 {
548 opp-hz = /bits/ 64 <15 515 opp-hz = /bits/ 64 <150000000>;
549 required-opps = <&rpmh 516 required-opps = <&rpmhpd_opp_svs>;
550 }; 517 };
551 518
552 opp-300000000 { 519 opp-300000000 {
553 opp-hz = /bits/ 64 <30 520 opp-hz = /bits/ 64 <300000000>;
554 required-opps = <&rpmh 521 required-opps = <&rpmhpd_opp_nom>;
555 }; 522 };
556 }; 523 };
557 524
558 qup_opp_table: opp-table-qup { 525 qup_opp_table: opp-table-qup {
559 compatible = "operating-points 526 compatible = "operating-points-v2";
560 527
561 opp-75000000 { 528 opp-75000000 {
562 opp-hz = /bits/ 64 <75 529 opp-hz = /bits/ 64 <75000000>;
563 required-opps = <&rpmh 530 required-opps = <&rpmhpd_opp_low_svs>;
564 }; 531 };
565 532
566 opp-100000000 { 533 opp-100000000 {
567 opp-hz = /bits/ 64 <10 534 opp-hz = /bits/ 64 <100000000>;
568 required-opps = <&rpmh 535 required-opps = <&rpmhpd_opp_svs>;
569 }; 536 };
570 537
571 opp-128000000 { 538 opp-128000000 {
572 opp-hz = /bits/ 64 <12 539 opp-hz = /bits/ 64 <128000000>;
573 required-opps = <&rpmh 540 required-opps = <&rpmhpd_opp_nom>;
574 }; 541 };
575 }; 542 };
576 543
577 pmu { 544 pmu {
578 compatible = "arm,armv8-pmuv3" 545 compatible = "arm,armv8-pmuv3";
579 interrupts = <GIC_PPI 5 IRQ_TY 546 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
580 }; 547 };
581 548
582 psci { 549 psci {
583 compatible = "arm,psci-1.0"; 550 compatible = "arm,psci-1.0";
584 method = "smc"; 551 method = "smc";
585 <<
586 CPU_PD0: cpu0 { <<
587 #power-domain-cells = <<
588 power-domains = <&CLUS <<
589 domain-idle-states = < <<
590 }; <<
591 <<
592 CPU_PD1: cpu1 { <<
593 #power-domain-cells = <<
594 power-domains = <&CLUS <<
595 domain-idle-states = < <<
596 }; <<
597 <<
598 CPU_PD2: cpu2 { <<
599 #power-domain-cells = <<
600 power-domains = <&CLUS <<
601 domain-idle-states = < <<
602 }; <<
603 <<
604 CPU_PD3: cpu3 { <<
605 #power-domain-cells = <<
606 power-domains = <&CLUS <<
607 domain-idle-states = < <<
608 }; <<
609 <<
610 CPU_PD4: cpu4 { <<
611 #power-domain-cells = <<
612 power-domains = <&CLUS <<
613 domain-idle-states = < <<
614 }; <<
615 <<
616 CPU_PD5: cpu5 { <<
617 #power-domain-cells = <<
618 power-domains = <&CLUS <<
619 domain-idle-states = < <<
620 }; <<
621 <<
622 CPU_PD6: cpu6 { <<
623 #power-domain-cells = <<
624 power-domains = <&CLUS <<
625 domain-idle-states = < <<
626 }; <<
627 <<
628 CPU_PD7: cpu7 { <<
629 #power-domain-cells = <<
630 power-domains = <&CLUS <<
631 domain-idle-states = < <<
632 }; <<
633 <<
634 CLUSTER_PD: cpu-cluster0 { <<
635 #power-domain-cells = <<
636 domain-idle-states = < <<
637 <<
638 <<
639 }; <<
640 }; 552 };
641 553
642 reserved_memory: reserved-memory { 554 reserved_memory: reserved-memory {
643 #address-cells = <2>; 555 #address-cells = <2>;
644 #size-cells = <2>; 556 #size-cells = <2>;
645 ranges; 557 ranges;
646 558
647 hyp_mem: memory@80000000 { 559 hyp_mem: memory@80000000 {
648 reg = <0x0 0x80000000 560 reg = <0x0 0x80000000 0x0 0x600000>;
649 no-map; 561 no-map;
650 }; 562 };
651 563
652 xbl_mem: memory@80600000 { 564 xbl_mem: memory@80600000 {
653 reg = <0x0 0x80600000 565 reg = <0x0 0x80600000 0x0 0x200000>;
654 no-map; 566 no-map;
655 }; 567 };
656 568
657 aop_mem: memory@80800000 { 569 aop_mem: memory@80800000 {
658 reg = <0x0 0x80800000 570 reg = <0x0 0x80800000 0x0 0x20000>;
659 no-map; 571 no-map;
660 }; 572 };
661 573
662 aop_cmd_db_mem: memory@8082000 574 aop_cmd_db_mem: memory@80820000 {
663 reg = <0x0 0x80820000 575 reg = <0x0 0x80820000 0x0 0x20000>;
664 compatible = "qcom,cmd 576 compatible = "qcom,cmd-db";
665 no-map; 577 no-map;
666 }; 578 };
667 579
668 sec_apps_mem: memory@808ff000 580 sec_apps_mem: memory@808ff000 {
669 reg = <0x0 0x808ff000 581 reg = <0x0 0x808ff000 0x0 0x1000>;
670 no-map; 582 no-map;
671 }; 583 };
672 584
673 smem_mem: memory@80900000 { 585 smem_mem: memory@80900000 {
674 reg = <0x0 0x80900000 586 reg = <0x0 0x80900000 0x0 0x200000>;
675 no-map; 587 no-map;
676 }; 588 };
677 589
678 tz_mem: memory@80b00000 { 590 tz_mem: memory@80b00000 {
679 reg = <0x0 0x80b00000 591 reg = <0x0 0x80b00000 0x0 0x3900000>;
680 no-map; 592 no-map;
681 }; 593 };
682 594
683 ipa_fw_mem: memory@8b700000 { 595 ipa_fw_mem: memory@8b700000 {
684 reg = <0 0x8b700000 0 596 reg = <0 0x8b700000 0 0x10000>;
685 no-map; 597 no-map;
686 }; 598 };
687 599
688 rmtfs_mem: memory@94600000 { 600 rmtfs_mem: memory@94600000 {
689 compatible = "qcom,rmt 601 compatible = "qcom,rmtfs-mem";
690 reg = <0x0 0x94600000 602 reg = <0x0 0x94600000 0x0 0x200000>;
691 no-map; 603 no-map;
692 604
693 qcom,client-id = <1>; 605 qcom,client-id = <1>;
694 qcom,vmid = <QCOM_SCM_ !! 606 qcom,vmid = <15>;
695 }; 607 };
696 }; 608 };
697 609
698 smem { 610 smem {
699 compatible = "qcom,smem"; 611 compatible = "qcom,smem";
700 memory-region = <&smem_mem>; 612 memory-region = <&smem_mem>;
701 hwlocks = <&tcsr_mutex 3>; 613 hwlocks = <&tcsr_mutex 3>;
702 }; 614 };
703 615
704 smp2p-cdsp { 616 smp2p-cdsp {
705 compatible = "qcom,smp2p"; 617 compatible = "qcom,smp2p";
706 qcom,smem = <94>, <432>; 618 qcom,smem = <94>, <432>;
707 619
708 interrupts = <GIC_SPI 576 IRQ_ 620 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
709 621
710 mboxes = <&apss_shared 6>; 622 mboxes = <&apss_shared 6>;
711 623
712 qcom,local-pid = <0>; 624 qcom,local-pid = <0>;
713 qcom,remote-pid = <5>; 625 qcom,remote-pid = <5>;
714 626
715 cdsp_smp2p_out: master-kernel 627 cdsp_smp2p_out: master-kernel {
716 qcom,entry-name = "mas 628 qcom,entry-name = "master-kernel";
717 #qcom,smem-state-cells 629 #qcom,smem-state-cells = <1>;
718 }; 630 };
719 631
720 cdsp_smp2p_in: slave-kernel { 632 cdsp_smp2p_in: slave-kernel {
721 qcom,entry-name = "sla 633 qcom,entry-name = "slave-kernel";
722 634
723 interrupt-controller; 635 interrupt-controller;
724 #interrupt-cells = <2> 636 #interrupt-cells = <2>;
725 }; 637 };
726 }; 638 };
727 639
728 smp2p-lpass { 640 smp2p-lpass {
729 compatible = "qcom,smp2p"; 641 compatible = "qcom,smp2p";
730 qcom,smem = <443>, <429>; 642 qcom,smem = <443>, <429>;
731 643
732 interrupts = <GIC_SPI 158 IRQ_ 644 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
733 645
734 mboxes = <&apss_shared 10>; 646 mboxes = <&apss_shared 10>;
735 647
736 qcom,local-pid = <0>; 648 qcom,local-pid = <0>;
737 qcom,remote-pid = <2>; 649 qcom,remote-pid = <2>;
738 650
739 adsp_smp2p_out: master-kernel 651 adsp_smp2p_out: master-kernel {
740 qcom,entry-name = "mas 652 qcom,entry-name = "master-kernel";
741 #qcom,smem-state-cells 653 #qcom,smem-state-cells = <1>;
742 }; 654 };
743 655
744 adsp_smp2p_in: slave-kernel { 656 adsp_smp2p_in: slave-kernel {
745 qcom,entry-name = "sla 657 qcom,entry-name = "slave-kernel";
746 658
747 interrupt-controller; 659 interrupt-controller;
748 #interrupt-cells = <2> 660 #interrupt-cells = <2>;
749 }; 661 };
750 }; 662 };
751 663
752 smp2p-mpss { 664 smp2p-mpss {
753 compatible = "qcom,smp2p"; 665 compatible = "qcom,smp2p";
754 qcom,smem = <435>, <428>; 666 qcom,smem = <435>, <428>;
755 interrupts = <GIC_SPI 451 IRQ_ 667 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
756 mboxes = <&apss_shared 14>; 668 mboxes = <&apss_shared 14>;
757 qcom,local-pid = <0>; 669 qcom,local-pid = <0>;
758 qcom,remote-pid = <1>; 670 qcom,remote-pid = <1>;
759 671
760 modem_smp2p_out: master-kernel 672 modem_smp2p_out: master-kernel {
761 qcom,entry-name = "mas 673 qcom,entry-name = "master-kernel";
762 #qcom,smem-state-cells 674 #qcom,smem-state-cells = <1>;
763 }; 675 };
764 676
765 modem_smp2p_in: slave-kernel { 677 modem_smp2p_in: slave-kernel {
766 qcom,entry-name = "sla 678 qcom,entry-name = "slave-kernel";
767 interrupt-controller; 679 interrupt-controller;
768 #interrupt-cells = <2> 680 #interrupt-cells = <2>;
769 }; 681 };
770 682
771 ipa_smp2p_out: ipa-ap-to-modem 683 ipa_smp2p_out: ipa-ap-to-modem {
772 qcom,entry-name = "ipa 684 qcom,entry-name = "ipa";
773 #qcom,smem-state-cells 685 #qcom,smem-state-cells = <1>;
774 }; 686 };
775 687
776 ipa_smp2p_in: ipa-modem-to-ap 688 ipa_smp2p_in: ipa-modem-to-ap {
777 qcom,entry-name = "ipa 689 qcom,entry-name = "ipa";
778 interrupt-controller; 690 interrupt-controller;
779 #interrupt-cells = <2> 691 #interrupt-cells = <2>;
780 }; 692 };
781 }; 693 };
782 694
783 soc: soc@0 { 695 soc: soc@0 {
784 #address-cells = <2>; 696 #address-cells = <2>;
785 #size-cells = <2>; 697 #size-cells = <2>;
786 ranges = <0 0 0 0 0x10 0>; 698 ranges = <0 0 0 0 0x10 0>;
787 dma-ranges = <0 0 0 0 0x10 0>; 699 dma-ranges = <0 0 0 0 0x10 0>;
788 compatible = "simple-bus"; 700 compatible = "simple-bus";
789 701
790 gcc: clock-controller@100000 { 702 gcc: clock-controller@100000 {
791 compatible = "qcom,gcc 703 compatible = "qcom,gcc-sc7180";
792 reg = <0 0x00100000 0 704 reg = <0 0x00100000 0 0x1f0000>;
793 clocks = <&rpmhcc RPMH 705 clocks = <&rpmhcc RPMH_CXO_CLK>,
794 <&rpmhcc RPMH 706 <&rpmhcc RPMH_CXO_CLK_A>,
795 <&sleep_clk>; 707 <&sleep_clk>;
796 clock-names = "bi_tcxo 708 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
797 #clock-cells = <1>; 709 #clock-cells = <1>;
798 #reset-cells = <1>; 710 #reset-cells = <1>;
799 #power-domain-cells = 711 #power-domain-cells = <1>;
800 power-domains = <&rpmh 712 power-domains = <&rpmhpd SC7180_CX>;
801 }; 713 };
802 714
803 qfprom: efuse@784000 { 715 qfprom: efuse@784000 {
804 compatible = "qcom,sc7 716 compatible = "qcom,sc7180-qfprom", "qcom,qfprom";
805 reg = <0 0x00784000 0 717 reg = <0 0x00784000 0 0x7a0>,
806 <0 0x00780000 0 718 <0 0x00780000 0 0x7a0>,
807 <0 0x00782000 0 719 <0 0x00782000 0 0x100>,
808 <0 0x00786000 0 720 <0 0x00786000 0 0x1fff>;
809 721
810 clocks = <&gcc GCC_SEC 722 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>;
811 clock-names = "core"; 723 clock-names = "core";
812 #address-cells = <1>; 724 #address-cells = <1>;
813 #size-cells = <1>; 725 #size-cells = <1>;
814 726
815 qusb2p_hstx_trim: hstx 727 qusb2p_hstx_trim: hstx-trim-primary@25b {
816 reg = <0x25b 0 728 reg = <0x25b 0x1>;
817 bits = <1 3>; 729 bits = <1 3>;
818 }; 730 };
819 731
820 gpu_speed_bin: gpu-spe !! 732 gpu_speed_bin: gpu_speed_bin@1d2 {
821 reg = <0x1d2 0 733 reg = <0x1d2 0x2>;
822 bits = <5 8>; 734 bits = <5 8>;
823 }; 735 };
824 }; 736 };
825 737
826 sdhc_1: mmc@7c4000 { 738 sdhc_1: mmc@7c4000 {
827 compatible = "qcom,sc7 739 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
828 reg = <0 0x007c4000 0 740 reg = <0 0x007c4000 0 0x1000>,
829 <0 0x007c5000 741 <0 0x007c5000 0 0x1000>;
830 reg-names = "hc", "cqh 742 reg-names = "hc", "cqhci";
831 743
832 iommus = <&apps_smmu 0 744 iommus = <&apps_smmu 0x60 0x0>;
833 interrupts = <GIC_SPI 745 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
834 <GIC_S 746 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
835 interrupt-names = "hc_ 747 interrupt-names = "hc_irq", "pwr_irq";
836 748
837 clocks = <&gcc GCC_SDC 749 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
838 <&gcc GCC_SDC 750 <&gcc GCC_SDCC1_APPS_CLK>,
839 <&rpmhcc RPMH 751 <&rpmhcc RPMH_CXO_CLK>;
840 clock-names = "iface", 752 clock-names = "iface", "core", "xo";
841 interconnects = <&aggr 753 interconnects = <&aggre1_noc MASTER_EMMC 0 &mc_virt SLAVE_EBI1 0>,
842 <&gem_ 754 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_EMMC_CFG 0>;
843 interconnect-names = " 755 interconnect-names = "sdhc-ddr","cpu-sdhc";
844 power-domains = <&rpmh 756 power-domains = <&rpmhpd SC7180_CX>;
845 operating-points-v2 = 757 operating-points-v2 = <&sdhc1_opp_table>;
846 758
847 bus-width = <8>; 759 bus-width = <8>;
848 non-removable; 760 non-removable;
849 supports-cqe; 761 supports-cqe;
850 762
851 mmc-ddr-1_8v; 763 mmc-ddr-1_8v;
852 mmc-hs200-1_8v; 764 mmc-hs200-1_8v;
853 mmc-hs400-1_8v; 765 mmc-hs400-1_8v;
854 mmc-hs400-enhanced-str 766 mmc-hs400-enhanced-strobe;
855 767
856 status = "disabled"; 768 status = "disabled";
857 769
858 sdhc1_opp_table: opp-t 770 sdhc1_opp_table: opp-table {
859 compatible = " 771 compatible = "operating-points-v2";
860 772
861 opp-100000000 773 opp-100000000 {
862 opp-hz 774 opp-hz = /bits/ 64 <100000000>;
863 requir 775 required-opps = <&rpmhpd_opp_low_svs>;
864 opp-pe 776 opp-peak-kBps = <1800000 600000>;
865 opp-av 777 opp-avg-kBps = <100000 0>;
866 }; 778 };
867 779
868 opp-384000000 780 opp-384000000 {
869 opp-hz 781 opp-hz = /bits/ 64 <384000000>;
870 requir 782 required-opps = <&rpmhpd_opp_nom>;
871 opp-pe 783 opp-peak-kBps = <5400000 1600000>;
872 opp-av 784 opp-avg-kBps = <390000 0>;
873 }; 785 };
874 }; 786 };
875 }; 787 };
876 788
877 qupv3_id_0: geniqup@8c0000 { 789 qupv3_id_0: geniqup@8c0000 {
878 compatible = "qcom,gen 790 compatible = "qcom,geni-se-qup";
879 reg = <0 0x008c0000 0 791 reg = <0 0x008c0000 0 0x6000>;
880 clock-names = "m-ahb", 792 clock-names = "m-ahb", "s-ahb";
881 clocks = <&gcc GCC_QUP 793 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
882 <&gcc GCC_QUP 794 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
883 #address-cells = <2>; 795 #address-cells = <2>;
884 #size-cells = <2>; 796 #size-cells = <2>;
885 ranges; 797 ranges;
886 iommus = <&apps_smmu 0 798 iommus = <&apps_smmu 0x43 0x0>;
887 status = "disabled"; 799 status = "disabled";
888 800
889 i2c0: i2c@880000 { 801 i2c0: i2c@880000 {
890 compatible = " 802 compatible = "qcom,geni-i2c";
891 reg = <0 0x008 803 reg = <0 0x00880000 0 0x4000>;
892 clock-names = 804 clock-names = "se";
893 clocks = <&gcc 805 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
894 pinctrl-names 806 pinctrl-names = "default";
895 pinctrl-0 = <& 807 pinctrl-0 = <&qup_i2c0_default>;
896 interrupts = < 808 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
897 #address-cells 809 #address-cells = <1>;
898 #size-cells = 810 #size-cells = <0>;
899 interconnects 811 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
900 812 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
901 813 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
902 interconnect-n 814 interconnect-names = "qup-core", "qup-config",
903 815 "qup-memory";
904 power-domains 816 power-domains = <&rpmhpd SC7180_CX>;
905 required-opps 817 required-opps = <&rpmhpd_opp_low_svs>;
906 status = "disa 818 status = "disabled";
907 }; 819 };
908 820
909 spi0: spi@880000 { 821 spi0: spi@880000 {
910 compatible = " 822 compatible = "qcom,geni-spi";
911 reg = <0 0x008 823 reg = <0 0x00880000 0 0x4000>;
912 clock-names = 824 clock-names = "se";
913 clocks = <&gcc 825 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
914 pinctrl-names 826 pinctrl-names = "default";
915 pinctrl-0 = <& 827 pinctrl-0 = <&qup_spi0_spi>, <&qup_spi0_cs>;
916 interrupts = < 828 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
917 #address-cells 829 #address-cells = <1>;
918 #size-cells = 830 #size-cells = <0>;
919 power-domains 831 power-domains = <&rpmhpd SC7180_CX>;
920 operating-poin 832 operating-points-v2 = <&qup_opp_table>;
921 interconnects 833 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
922 834 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
923 interconnect-n 835 interconnect-names = "qup-core", "qup-config";
924 status = "disa 836 status = "disabled";
925 }; 837 };
926 838
927 uart0: serial@880000 { 839 uart0: serial@880000 {
928 compatible = " 840 compatible = "qcom,geni-uart";
929 reg = <0 0x008 841 reg = <0 0x00880000 0 0x4000>;
930 clock-names = 842 clock-names = "se";
931 clocks = <&gcc 843 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
932 pinctrl-names 844 pinctrl-names = "default";
933 pinctrl-0 = <& 845 pinctrl-0 = <&qup_uart0_default>;
934 interrupts = < 846 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
935 power-domains 847 power-domains = <&rpmhpd SC7180_CX>;
936 operating-poin 848 operating-points-v2 = <&qup_opp_table>;
937 interconnects 849 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
938 850 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
939 interconnect-n 851 interconnect-names = "qup-core", "qup-config";
940 status = "disa 852 status = "disabled";
941 }; 853 };
942 854
943 i2c1: i2c@884000 { 855 i2c1: i2c@884000 {
944 compatible = " 856 compatible = "qcom,geni-i2c";
945 reg = <0 0x008 857 reg = <0 0x00884000 0 0x4000>;
946 clock-names = 858 clock-names = "se";
947 clocks = <&gcc 859 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
948 pinctrl-names 860 pinctrl-names = "default";
949 pinctrl-0 = <& 861 pinctrl-0 = <&qup_i2c1_default>;
950 interrupts = < 862 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
951 #address-cells 863 #address-cells = <1>;
952 #size-cells = 864 #size-cells = <0>;
953 interconnects 865 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
954 866 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
955 867 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
956 interconnect-n 868 interconnect-names = "qup-core", "qup-config",
957 869 "qup-memory";
958 power-domains 870 power-domains = <&rpmhpd SC7180_CX>;
959 required-opps 871 required-opps = <&rpmhpd_opp_low_svs>;
960 status = "disa 872 status = "disabled";
961 }; 873 };
962 874
963 spi1: spi@884000 { 875 spi1: spi@884000 {
964 compatible = " 876 compatible = "qcom,geni-spi";
965 reg = <0 0x008 877 reg = <0 0x00884000 0 0x4000>;
966 clock-names = 878 clock-names = "se";
967 clocks = <&gcc 879 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
968 pinctrl-names 880 pinctrl-names = "default";
969 pinctrl-0 = <& 881 pinctrl-0 = <&qup_spi1_spi>, <&qup_spi1_cs>;
970 interrupts = < 882 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
971 #address-cells 883 #address-cells = <1>;
972 #size-cells = 884 #size-cells = <0>;
973 power-domains 885 power-domains = <&rpmhpd SC7180_CX>;
974 operating-poin 886 operating-points-v2 = <&qup_opp_table>;
975 interconnects 887 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
976 888 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
977 interconnect-n 889 interconnect-names = "qup-core", "qup-config";
978 status = "disa 890 status = "disabled";
979 }; 891 };
980 892
981 uart1: serial@884000 { 893 uart1: serial@884000 {
982 compatible = " 894 compatible = "qcom,geni-uart";
983 reg = <0 0x008 895 reg = <0 0x00884000 0 0x4000>;
984 clock-names = 896 clock-names = "se";
985 clocks = <&gcc 897 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
986 pinctrl-names 898 pinctrl-names = "default";
987 pinctrl-0 = <& 899 pinctrl-0 = <&qup_uart1_default>;
988 interrupts = < 900 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
989 power-domains 901 power-domains = <&rpmhpd SC7180_CX>;
990 operating-poin 902 operating-points-v2 = <&qup_opp_table>;
991 interconnects 903 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
992 904 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
993 interconnect-n 905 interconnect-names = "qup-core", "qup-config";
994 status = "disa 906 status = "disabled";
995 }; 907 };
996 908
997 i2c2: i2c@888000 { 909 i2c2: i2c@888000 {
998 compatible = " 910 compatible = "qcom,geni-i2c";
999 reg = <0 0x008 911 reg = <0 0x00888000 0 0x4000>;
1000 clock-names = 912 clock-names = "se";
1001 clocks = <&gc 913 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1002 pinctrl-names 914 pinctrl-names = "default";
1003 pinctrl-0 = < 915 pinctrl-0 = <&qup_i2c2_default>;
1004 interrupts = 916 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1005 #address-cell 917 #address-cells = <1>;
1006 #size-cells = 918 #size-cells = <0>;
1007 interconnects 919 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1008 920 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1009 921 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1010 interconnect- 922 interconnect-names = "qup-core", "qup-config",
1011 923 "qup-memory";
1012 power-domains 924 power-domains = <&rpmhpd SC7180_CX>;
1013 required-opps 925 required-opps = <&rpmhpd_opp_low_svs>;
1014 status = "dis 926 status = "disabled";
1015 }; 927 };
1016 928
1017 uart2: serial@888000 929 uart2: serial@888000 {
1018 compatible = 930 compatible = "qcom,geni-uart";
1019 reg = <0 0x00 931 reg = <0 0x00888000 0 0x4000>;
1020 clock-names = 932 clock-names = "se";
1021 clocks = <&gc 933 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1022 pinctrl-names 934 pinctrl-names = "default";
1023 pinctrl-0 = < 935 pinctrl-0 = <&qup_uart2_default>;
1024 interrupts = 936 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1025 power-domains 937 power-domains = <&rpmhpd SC7180_CX>;
1026 operating-poi 938 operating-points-v2 = <&qup_opp_table>;
1027 interconnects 939 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1028 940 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1029 interconnect- 941 interconnect-names = "qup-core", "qup-config";
1030 status = "dis 942 status = "disabled";
1031 }; 943 };
1032 944
1033 i2c3: i2c@88c000 { 945 i2c3: i2c@88c000 {
1034 compatible = 946 compatible = "qcom,geni-i2c";
1035 reg = <0 0x00 947 reg = <0 0x0088c000 0 0x4000>;
1036 clock-names = 948 clock-names = "se";
1037 clocks = <&gc 949 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1038 pinctrl-names 950 pinctrl-names = "default";
1039 pinctrl-0 = < 951 pinctrl-0 = <&qup_i2c3_default>;
1040 interrupts = 952 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1041 #address-cell 953 #address-cells = <1>;
1042 #size-cells = 954 #size-cells = <0>;
1043 interconnects 955 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1044 956 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1045 957 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1046 interconnect- 958 interconnect-names = "qup-core", "qup-config",
1047 959 "qup-memory";
1048 power-domains 960 power-domains = <&rpmhpd SC7180_CX>;
1049 required-opps 961 required-opps = <&rpmhpd_opp_low_svs>;
1050 status = "dis 962 status = "disabled";
1051 }; 963 };
1052 964
1053 spi3: spi@88c000 { 965 spi3: spi@88c000 {
1054 compatible = 966 compatible = "qcom,geni-spi";
1055 reg = <0 0x00 967 reg = <0 0x0088c000 0 0x4000>;
1056 clock-names = 968 clock-names = "se";
1057 clocks = <&gc 969 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1058 pinctrl-names 970 pinctrl-names = "default";
1059 pinctrl-0 = < 971 pinctrl-0 = <&qup_spi3_spi>, <&qup_spi3_cs>;
1060 interrupts = 972 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1061 #address-cell 973 #address-cells = <1>;
1062 #size-cells = 974 #size-cells = <0>;
1063 power-domains 975 power-domains = <&rpmhpd SC7180_CX>;
1064 operating-poi 976 operating-points-v2 = <&qup_opp_table>;
1065 interconnects 977 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1066 978 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1067 interconnect- 979 interconnect-names = "qup-core", "qup-config";
1068 status = "dis 980 status = "disabled";
1069 }; 981 };
1070 982
1071 uart3: serial@88c000 983 uart3: serial@88c000 {
1072 compatible = 984 compatible = "qcom,geni-uart";
1073 reg = <0 0x00 985 reg = <0 0x0088c000 0 0x4000>;
1074 clock-names = 986 clock-names = "se";
1075 clocks = <&gc 987 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1076 pinctrl-names 988 pinctrl-names = "default";
1077 pinctrl-0 = < 989 pinctrl-0 = <&qup_uart3_default>;
1078 interrupts = 990 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1079 power-domains 991 power-domains = <&rpmhpd SC7180_CX>;
1080 operating-poi 992 operating-points-v2 = <&qup_opp_table>;
1081 interconnects 993 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1082 994 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1083 interconnect- 995 interconnect-names = "qup-core", "qup-config";
1084 status = "dis 996 status = "disabled";
1085 }; 997 };
1086 998
1087 i2c4: i2c@890000 { 999 i2c4: i2c@890000 {
1088 compatible = 1000 compatible = "qcom,geni-i2c";
1089 reg = <0 0x00 1001 reg = <0 0x00890000 0 0x4000>;
1090 clock-names = 1002 clock-names = "se";
1091 clocks = <&gc 1003 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1092 pinctrl-names 1004 pinctrl-names = "default";
1093 pinctrl-0 = < 1005 pinctrl-0 = <&qup_i2c4_default>;
1094 interrupts = 1006 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1095 #address-cell 1007 #address-cells = <1>;
1096 #size-cells = 1008 #size-cells = <0>;
1097 interconnects 1009 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1098 1010 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1099 1011 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1100 interconnect- 1012 interconnect-names = "qup-core", "qup-config",
1101 1013 "qup-memory";
1102 power-domains 1014 power-domains = <&rpmhpd SC7180_CX>;
1103 required-opps 1015 required-opps = <&rpmhpd_opp_low_svs>;
1104 status = "dis 1016 status = "disabled";
1105 }; 1017 };
1106 1018
1107 uart4: serial@890000 1019 uart4: serial@890000 {
1108 compatible = 1020 compatible = "qcom,geni-uart";
1109 reg = <0 0x00 1021 reg = <0 0x00890000 0 0x4000>;
1110 clock-names = 1022 clock-names = "se";
1111 clocks = <&gc 1023 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1112 pinctrl-names 1024 pinctrl-names = "default";
1113 pinctrl-0 = < 1025 pinctrl-0 = <&qup_uart4_default>;
1114 interrupts = 1026 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1115 power-domains 1027 power-domains = <&rpmhpd SC7180_CX>;
1116 operating-poi 1028 operating-points-v2 = <&qup_opp_table>;
1117 interconnects 1029 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1118 1030 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1119 interconnect- 1031 interconnect-names = "qup-core", "qup-config";
1120 status = "dis 1032 status = "disabled";
1121 }; 1033 };
1122 1034
1123 i2c5: i2c@894000 { 1035 i2c5: i2c@894000 {
1124 compatible = 1036 compatible = "qcom,geni-i2c";
1125 reg = <0 0x00 1037 reg = <0 0x00894000 0 0x4000>;
1126 clock-names = 1038 clock-names = "se";
1127 clocks = <&gc 1039 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1128 pinctrl-names 1040 pinctrl-names = "default";
1129 pinctrl-0 = < 1041 pinctrl-0 = <&qup_i2c5_default>;
1130 interrupts = 1042 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1131 #address-cell 1043 #address-cells = <1>;
1132 #size-cells = 1044 #size-cells = <0>;
1133 interconnects 1045 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1134 1046 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1135 1047 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1136 interconnect- 1048 interconnect-names = "qup-core", "qup-config",
1137 1049 "qup-memory";
1138 power-domains 1050 power-domains = <&rpmhpd SC7180_CX>;
1139 required-opps 1051 required-opps = <&rpmhpd_opp_low_svs>;
1140 status = "dis 1052 status = "disabled";
1141 }; 1053 };
1142 1054
1143 spi5: spi@894000 { 1055 spi5: spi@894000 {
1144 compatible = 1056 compatible = "qcom,geni-spi";
1145 reg = <0 0x00 1057 reg = <0 0x00894000 0 0x4000>;
1146 clock-names = 1058 clock-names = "se";
1147 clocks = <&gc 1059 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1148 pinctrl-names 1060 pinctrl-names = "default";
1149 pinctrl-0 = < 1061 pinctrl-0 = <&qup_spi5_spi>, <&qup_spi5_cs>;
1150 interrupts = 1062 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1151 #address-cell 1063 #address-cells = <1>;
1152 #size-cells = 1064 #size-cells = <0>;
1153 power-domains 1065 power-domains = <&rpmhpd SC7180_CX>;
1154 operating-poi 1066 operating-points-v2 = <&qup_opp_table>;
1155 interconnects 1067 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1156 1068 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1157 interconnect- 1069 interconnect-names = "qup-core", "qup-config";
1158 status = "dis 1070 status = "disabled";
1159 }; 1071 };
1160 1072
1161 uart5: serial@894000 1073 uart5: serial@894000 {
1162 compatible = 1074 compatible = "qcom,geni-uart";
1163 reg = <0 0x00 1075 reg = <0 0x00894000 0 0x4000>;
1164 clock-names = 1076 clock-names = "se";
1165 clocks = <&gc 1077 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1166 pinctrl-names 1078 pinctrl-names = "default";
1167 pinctrl-0 = < 1079 pinctrl-0 = <&qup_uart5_default>;
1168 interrupts = 1080 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1169 power-domains 1081 power-domains = <&rpmhpd SC7180_CX>;
1170 operating-poi 1082 operating-points-v2 = <&qup_opp_table>;
1171 interconnects 1083 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1172 1084 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1173 interconnect- 1085 interconnect-names = "qup-core", "qup-config";
1174 status = "dis 1086 status = "disabled";
1175 }; 1087 };
1176 }; 1088 };
1177 1089
1178 qupv3_id_1: geniqup@ac0000 { 1090 qupv3_id_1: geniqup@ac0000 {
1179 compatible = "qcom,ge 1091 compatible = "qcom,geni-se-qup";
1180 reg = <0 0x00ac0000 0 1092 reg = <0 0x00ac0000 0 0x6000>;
1181 clock-names = "m-ahb" 1093 clock-names = "m-ahb", "s-ahb";
1182 clocks = <&gcc GCC_QU 1094 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1183 <&gcc GCC_QU 1095 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1184 #address-cells = <2>; 1096 #address-cells = <2>;
1185 #size-cells = <2>; 1097 #size-cells = <2>;
1186 ranges; 1098 ranges;
1187 iommus = <&apps_smmu 1099 iommus = <&apps_smmu 0x4c3 0x0>;
1188 status = "disabled"; 1100 status = "disabled";
1189 1101
1190 i2c6: i2c@a80000 { 1102 i2c6: i2c@a80000 {
1191 compatible = 1103 compatible = "qcom,geni-i2c";
1192 reg = <0 0x00 1104 reg = <0 0x00a80000 0 0x4000>;
1193 clock-names = 1105 clock-names = "se";
1194 clocks = <&gc 1106 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1195 pinctrl-names 1107 pinctrl-names = "default";
1196 pinctrl-0 = < 1108 pinctrl-0 = <&qup_i2c6_default>;
1197 interrupts = 1109 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1198 #address-cell 1110 #address-cells = <1>;
1199 #size-cells = 1111 #size-cells = <0>;
1200 interconnects 1112 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1201 1113 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1202 1114 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1203 interconnect- 1115 interconnect-names = "qup-core", "qup-config",
1204 1116 "qup-memory";
1205 power-domains 1117 power-domains = <&rpmhpd SC7180_CX>;
1206 required-opps 1118 required-opps = <&rpmhpd_opp_low_svs>;
1207 status = "dis 1119 status = "disabled";
1208 }; 1120 };
1209 1121
1210 spi6: spi@a80000 { 1122 spi6: spi@a80000 {
1211 compatible = 1123 compatible = "qcom,geni-spi";
1212 reg = <0 0x00 1124 reg = <0 0x00a80000 0 0x4000>;
1213 clock-names = 1125 clock-names = "se";
1214 clocks = <&gc 1126 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1215 pinctrl-names 1127 pinctrl-names = "default";
1216 pinctrl-0 = < 1128 pinctrl-0 = <&qup_spi6_spi>, <&qup_spi6_cs>;
1217 interrupts = 1129 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1218 #address-cell 1130 #address-cells = <1>;
1219 #size-cells = 1131 #size-cells = <0>;
1220 power-domains 1132 power-domains = <&rpmhpd SC7180_CX>;
1221 operating-poi 1133 operating-points-v2 = <&qup_opp_table>;
1222 interconnects 1134 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1223 1135 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1224 interconnect- 1136 interconnect-names = "qup-core", "qup-config";
1225 status = "dis 1137 status = "disabled";
1226 }; 1138 };
1227 1139
1228 uart6: serial@a80000 1140 uart6: serial@a80000 {
1229 compatible = 1141 compatible = "qcom,geni-uart";
1230 reg = <0 0x00 1142 reg = <0 0x00a80000 0 0x4000>;
1231 clock-names = 1143 clock-names = "se";
1232 clocks = <&gc 1144 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1233 pinctrl-names 1145 pinctrl-names = "default";
1234 pinctrl-0 = < 1146 pinctrl-0 = <&qup_uart6_default>;
1235 interrupts = 1147 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1236 power-domains 1148 power-domains = <&rpmhpd SC7180_CX>;
1237 operating-poi 1149 operating-points-v2 = <&qup_opp_table>;
1238 interconnects 1150 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1239 1151 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1240 interconnect- 1152 interconnect-names = "qup-core", "qup-config";
1241 status = "dis 1153 status = "disabled";
1242 }; 1154 };
1243 1155
1244 i2c7: i2c@a84000 { 1156 i2c7: i2c@a84000 {
1245 compatible = 1157 compatible = "qcom,geni-i2c";
1246 reg = <0 0x00 1158 reg = <0 0x00a84000 0 0x4000>;
1247 clock-names = 1159 clock-names = "se";
1248 clocks = <&gc 1160 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1249 pinctrl-names 1161 pinctrl-names = "default";
1250 pinctrl-0 = < 1162 pinctrl-0 = <&qup_i2c7_default>;
1251 interrupts = 1163 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1252 #address-cell 1164 #address-cells = <1>;
1253 #size-cells = 1165 #size-cells = <0>;
1254 interconnects 1166 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1255 1167 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1256 1168 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1257 interconnect- 1169 interconnect-names = "qup-core", "qup-config",
1258 1170 "qup-memory";
1259 power-domains 1171 power-domains = <&rpmhpd SC7180_CX>;
1260 required-opps 1172 required-opps = <&rpmhpd_opp_low_svs>;
1261 status = "dis 1173 status = "disabled";
1262 }; 1174 };
1263 1175
1264 uart7: serial@a84000 1176 uart7: serial@a84000 {
1265 compatible = 1177 compatible = "qcom,geni-uart";
1266 reg = <0 0x00 1178 reg = <0 0x00a84000 0 0x4000>;
1267 clock-names = 1179 clock-names = "se";
1268 clocks = <&gc 1180 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1269 pinctrl-names 1181 pinctrl-names = "default";
1270 pinctrl-0 = < 1182 pinctrl-0 = <&qup_uart7_default>;
1271 interrupts = 1183 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1272 power-domains 1184 power-domains = <&rpmhpd SC7180_CX>;
1273 operating-poi 1185 operating-points-v2 = <&qup_opp_table>;
1274 interconnects 1186 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1275 1187 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1276 interconnect- 1188 interconnect-names = "qup-core", "qup-config";
1277 status = "dis 1189 status = "disabled";
1278 }; 1190 };
1279 1191
1280 i2c8: i2c@a88000 { 1192 i2c8: i2c@a88000 {
1281 compatible = 1193 compatible = "qcom,geni-i2c";
1282 reg = <0 0x00 1194 reg = <0 0x00a88000 0 0x4000>;
1283 clock-names = 1195 clock-names = "se";
1284 clocks = <&gc 1196 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1285 pinctrl-names 1197 pinctrl-names = "default";
1286 pinctrl-0 = < 1198 pinctrl-0 = <&qup_i2c8_default>;
1287 interrupts = 1199 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1288 #address-cell 1200 #address-cells = <1>;
1289 #size-cells = 1201 #size-cells = <0>;
1290 interconnects 1202 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1291 1203 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1292 1204 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1293 interconnect- 1205 interconnect-names = "qup-core", "qup-config",
1294 1206 "qup-memory";
1295 power-domains 1207 power-domains = <&rpmhpd SC7180_CX>;
1296 required-opps 1208 required-opps = <&rpmhpd_opp_low_svs>;
1297 status = "dis 1209 status = "disabled";
1298 }; 1210 };
1299 1211
1300 spi8: spi@a88000 { 1212 spi8: spi@a88000 {
1301 compatible = 1213 compatible = "qcom,geni-spi";
1302 reg = <0 0x00 1214 reg = <0 0x00a88000 0 0x4000>;
1303 clock-names = 1215 clock-names = "se";
1304 clocks = <&gc 1216 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1305 pinctrl-names 1217 pinctrl-names = "default";
1306 pinctrl-0 = < 1218 pinctrl-0 = <&qup_spi8_spi>, <&qup_spi8_cs>;
1307 interrupts = 1219 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1308 #address-cell 1220 #address-cells = <1>;
1309 #size-cells = 1221 #size-cells = <0>;
1310 power-domains 1222 power-domains = <&rpmhpd SC7180_CX>;
1311 operating-poi 1223 operating-points-v2 = <&qup_opp_table>;
1312 interconnects 1224 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1313 1225 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1314 interconnect- 1226 interconnect-names = "qup-core", "qup-config";
1315 status = "dis 1227 status = "disabled";
1316 }; 1228 };
1317 1229
1318 uart8: serial@a88000 1230 uart8: serial@a88000 {
1319 compatible = 1231 compatible = "qcom,geni-debug-uart";
1320 reg = <0 0x00 1232 reg = <0 0x00a88000 0 0x4000>;
1321 clock-names = 1233 clock-names = "se";
1322 clocks = <&gc 1234 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1323 pinctrl-names 1235 pinctrl-names = "default";
1324 pinctrl-0 = < 1236 pinctrl-0 = <&qup_uart8_default>;
1325 interrupts = 1237 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1326 power-domains 1238 power-domains = <&rpmhpd SC7180_CX>;
1327 operating-poi 1239 operating-points-v2 = <&qup_opp_table>;
1328 interconnects 1240 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1329 1241 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1330 interconnect- 1242 interconnect-names = "qup-core", "qup-config";
1331 status = "dis 1243 status = "disabled";
1332 }; 1244 };
1333 1245
1334 i2c9: i2c@a8c000 { 1246 i2c9: i2c@a8c000 {
1335 compatible = 1247 compatible = "qcom,geni-i2c";
1336 reg = <0 0x00 1248 reg = <0 0x00a8c000 0 0x4000>;
1337 clock-names = 1249 clock-names = "se";
1338 clocks = <&gc 1250 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1339 pinctrl-names 1251 pinctrl-names = "default";
1340 pinctrl-0 = < 1252 pinctrl-0 = <&qup_i2c9_default>;
1341 interrupts = 1253 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1342 #address-cell 1254 #address-cells = <1>;
1343 #size-cells = 1255 #size-cells = <0>;
1344 interconnects 1256 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1345 1257 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1346 1258 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1347 interconnect- 1259 interconnect-names = "qup-core", "qup-config",
1348 1260 "qup-memory";
1349 power-domains 1261 power-domains = <&rpmhpd SC7180_CX>;
1350 required-opps 1262 required-opps = <&rpmhpd_opp_low_svs>;
1351 status = "dis 1263 status = "disabled";
1352 }; 1264 };
1353 1265
1354 uart9: serial@a8c000 1266 uart9: serial@a8c000 {
1355 compatible = 1267 compatible = "qcom,geni-uart";
1356 reg = <0 0x00 1268 reg = <0 0x00a8c000 0 0x4000>;
1357 clock-names = 1269 clock-names = "se";
1358 clocks = <&gc 1270 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1359 pinctrl-names 1271 pinctrl-names = "default";
1360 pinctrl-0 = < 1272 pinctrl-0 = <&qup_uart9_default>;
1361 interrupts = 1273 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1362 power-domains 1274 power-domains = <&rpmhpd SC7180_CX>;
1363 operating-poi 1275 operating-points-v2 = <&qup_opp_table>;
1364 interconnects 1276 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1365 1277 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1366 interconnect- 1278 interconnect-names = "qup-core", "qup-config";
1367 status = "dis 1279 status = "disabled";
1368 }; 1280 };
1369 1281
1370 i2c10: i2c@a90000 { 1282 i2c10: i2c@a90000 {
1371 compatible = 1283 compatible = "qcom,geni-i2c";
1372 reg = <0 0x00 1284 reg = <0 0x00a90000 0 0x4000>;
1373 clock-names = 1285 clock-names = "se";
1374 clocks = <&gc 1286 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1375 pinctrl-names 1287 pinctrl-names = "default";
1376 pinctrl-0 = < 1288 pinctrl-0 = <&qup_i2c10_default>;
1377 interrupts = 1289 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1378 #address-cell 1290 #address-cells = <1>;
1379 #size-cells = 1291 #size-cells = <0>;
1380 interconnects 1292 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1381 1293 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1382 1294 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1383 interconnect- 1295 interconnect-names = "qup-core", "qup-config",
1384 1296 "qup-memory";
1385 power-domains 1297 power-domains = <&rpmhpd SC7180_CX>;
1386 required-opps 1298 required-opps = <&rpmhpd_opp_low_svs>;
1387 status = "dis 1299 status = "disabled";
1388 }; 1300 };
1389 1301
1390 spi10: spi@a90000 { 1302 spi10: spi@a90000 {
1391 compatible = 1303 compatible = "qcom,geni-spi";
1392 reg = <0 0x00 1304 reg = <0 0x00a90000 0 0x4000>;
1393 clock-names = 1305 clock-names = "se";
1394 clocks = <&gc 1306 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1395 pinctrl-names 1307 pinctrl-names = "default";
1396 pinctrl-0 = < 1308 pinctrl-0 = <&qup_spi10_spi>, <&qup_spi10_cs>;
1397 interrupts = 1309 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1398 #address-cell 1310 #address-cells = <1>;
1399 #size-cells = 1311 #size-cells = <0>;
1400 power-domains 1312 power-domains = <&rpmhpd SC7180_CX>;
1401 operating-poi 1313 operating-points-v2 = <&qup_opp_table>;
1402 interconnects 1314 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1403 1315 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1404 interconnect- 1316 interconnect-names = "qup-core", "qup-config";
1405 status = "dis 1317 status = "disabled";
1406 }; 1318 };
1407 1319
1408 uart10: serial@a90000 1320 uart10: serial@a90000 {
1409 compatible = 1321 compatible = "qcom,geni-uart";
1410 reg = <0 0x00 1322 reg = <0 0x00a90000 0 0x4000>;
1411 clock-names = 1323 clock-names = "se";
1412 clocks = <&gc 1324 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1413 pinctrl-names 1325 pinctrl-names = "default";
1414 pinctrl-0 = < 1326 pinctrl-0 = <&qup_uart10_default>;
1415 interrupts = 1327 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1416 power-domains 1328 power-domains = <&rpmhpd SC7180_CX>;
1417 operating-poi 1329 operating-points-v2 = <&qup_opp_table>;
1418 interconnects 1330 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1419 1331 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1420 interconnect- 1332 interconnect-names = "qup-core", "qup-config";
1421 status = "dis 1333 status = "disabled";
1422 }; 1334 };
1423 1335
1424 i2c11: i2c@a94000 { 1336 i2c11: i2c@a94000 {
1425 compatible = 1337 compatible = "qcom,geni-i2c";
1426 reg = <0 0x00 1338 reg = <0 0x00a94000 0 0x4000>;
1427 clock-names = 1339 clock-names = "se";
1428 clocks = <&gc 1340 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1429 pinctrl-names 1341 pinctrl-names = "default";
1430 pinctrl-0 = < 1342 pinctrl-0 = <&qup_i2c11_default>;
1431 interrupts = 1343 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1432 #address-cell 1344 #address-cells = <1>;
1433 #size-cells = 1345 #size-cells = <0>;
1434 interconnects 1346 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1435 1347 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1436 1348 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1437 interconnect- 1349 interconnect-names = "qup-core", "qup-config",
1438 1350 "qup-memory";
1439 power-domains 1351 power-domains = <&rpmhpd SC7180_CX>;
1440 required-opps 1352 required-opps = <&rpmhpd_opp_low_svs>;
1441 status = "dis 1353 status = "disabled";
1442 }; 1354 };
1443 1355
1444 spi11: spi@a94000 { 1356 spi11: spi@a94000 {
1445 compatible = 1357 compatible = "qcom,geni-spi";
1446 reg = <0 0x00 1358 reg = <0 0x00a94000 0 0x4000>;
1447 clock-names = 1359 clock-names = "se";
1448 clocks = <&gc 1360 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1449 pinctrl-names 1361 pinctrl-names = "default";
1450 pinctrl-0 = < 1362 pinctrl-0 = <&qup_spi11_spi>, <&qup_spi11_cs>;
1451 interrupts = 1363 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1452 #address-cell 1364 #address-cells = <1>;
1453 #size-cells = 1365 #size-cells = <0>;
1454 power-domains 1366 power-domains = <&rpmhpd SC7180_CX>;
1455 operating-poi 1367 operating-points-v2 = <&qup_opp_table>;
1456 interconnects 1368 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1457 1369 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1458 interconnect- 1370 interconnect-names = "qup-core", "qup-config";
1459 status = "dis 1371 status = "disabled";
1460 }; 1372 };
1461 1373
1462 uart11: serial@a94000 1374 uart11: serial@a94000 {
1463 compatible = 1375 compatible = "qcom,geni-uart";
1464 reg = <0 0x00 1376 reg = <0 0x00a94000 0 0x4000>;
1465 clock-names = 1377 clock-names = "se";
1466 clocks = <&gc 1378 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1467 pinctrl-names 1379 pinctrl-names = "default";
1468 pinctrl-0 = < 1380 pinctrl-0 = <&qup_uart11_default>;
1469 interrupts = 1381 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1470 power-domains 1382 power-domains = <&rpmhpd SC7180_CX>;
1471 operating-poi 1383 operating-points-v2 = <&qup_opp_table>;
1472 interconnects 1384 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1473 1385 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1474 interconnect- 1386 interconnect-names = "qup-core", "qup-config";
1475 status = "dis 1387 status = "disabled";
1476 }; 1388 };
1477 }; 1389 };
1478 1390
1479 config_noc: interconnect@1500 1391 config_noc: interconnect@1500000 {
1480 compatible = "qcom,sc 1392 compatible = "qcom,sc7180-config-noc";
1481 reg = <0 0x01500000 0 1393 reg = <0 0x01500000 0 0x28000>;
1482 #interconnect-cells = 1394 #interconnect-cells = <2>;
1483 qcom,bcm-voters = <&a 1395 qcom,bcm-voters = <&apps_bcm_voter>;
1484 }; 1396 };
1485 1397
1486 system_noc: interconnect@1620 1398 system_noc: interconnect@1620000 {
1487 compatible = "qcom,sc 1399 compatible = "qcom,sc7180-system-noc";
1488 reg = <0 0x01620000 0 1400 reg = <0 0x01620000 0 0x17080>;
1489 #interconnect-cells = 1401 #interconnect-cells = <2>;
1490 qcom,bcm-voters = <&a 1402 qcom,bcm-voters = <&apps_bcm_voter>;
1491 }; 1403 };
1492 1404
1493 mc_virt: interconnect@1638000 1405 mc_virt: interconnect@1638000 {
1494 compatible = "qcom,sc 1406 compatible = "qcom,sc7180-mc-virt";
1495 reg = <0 0x01638000 0 1407 reg = <0 0x01638000 0 0x1000>;
1496 #interconnect-cells = 1408 #interconnect-cells = <2>;
1497 qcom,bcm-voters = <&a 1409 qcom,bcm-voters = <&apps_bcm_voter>;
1498 }; 1410 };
1499 1411
1500 qup_virt: interconnect@165000 1412 qup_virt: interconnect@1650000 {
1501 compatible = "qcom,sc 1413 compatible = "qcom,sc7180-qup-virt";
1502 reg = <0 0x01650000 0 1414 reg = <0 0x01650000 0 0x1000>;
1503 #interconnect-cells = 1415 #interconnect-cells = <2>;
1504 qcom,bcm-voters = <&a 1416 qcom,bcm-voters = <&apps_bcm_voter>;
1505 }; 1417 };
1506 1418
1507 aggre1_noc: interconnect@16e0 1419 aggre1_noc: interconnect@16e0000 {
1508 compatible = "qcom,sc 1420 compatible = "qcom,sc7180-aggre1-noc";
1509 reg = <0 0x016e0000 0 1421 reg = <0 0x016e0000 0 0x15080>;
1510 #interconnect-cells = 1422 #interconnect-cells = <2>;
1511 qcom,bcm-voters = <&a 1423 qcom,bcm-voters = <&apps_bcm_voter>;
1512 }; 1424 };
1513 1425
1514 aggre2_noc: interconnect@1705 1426 aggre2_noc: interconnect@1705000 {
1515 compatible = "qcom,sc 1427 compatible = "qcom,sc7180-aggre2-noc";
1516 reg = <0 0x01705000 0 1428 reg = <0 0x01705000 0 0x9000>;
1517 #interconnect-cells = 1429 #interconnect-cells = <2>;
1518 qcom,bcm-voters = <&a 1430 qcom,bcm-voters = <&apps_bcm_voter>;
1519 }; 1431 };
1520 1432
1521 compute_noc: interconnect@170 1433 compute_noc: interconnect@170e000 {
1522 compatible = "qcom,sc 1434 compatible = "qcom,sc7180-compute-noc";
1523 reg = <0 0x0170e000 0 1435 reg = <0 0x0170e000 0 0x6000>;
1524 #interconnect-cells = 1436 #interconnect-cells = <2>;
1525 qcom,bcm-voters = <&a 1437 qcom,bcm-voters = <&apps_bcm_voter>;
1526 }; 1438 };
1527 1439
1528 mmss_noc: interconnect@174000 1440 mmss_noc: interconnect@1740000 {
1529 compatible = "qcom,sc 1441 compatible = "qcom,sc7180-mmss-noc";
1530 reg = <0 0x01740000 0 1442 reg = <0 0x01740000 0 0x1c100>;
1531 #interconnect-cells = 1443 #interconnect-cells = <2>;
1532 qcom,bcm-voters = <&a 1444 qcom,bcm-voters = <&apps_bcm_voter>;
1533 }; 1445 };
1534 1446
1535 ufs_mem_hc: ufshc@1d84000 { <<
1536 compatible = "qcom,sc <<
1537 "jedec,u <<
1538 reg = <0 0x01d84000 0 <<
1539 interrupts = <GIC_SPI <<
1540 phys = <&ufs_mem_phy> <<
1541 phy-names = "ufsphy"; <<
1542 lanes-per-direction = <<
1543 #reset-cells = <1>; <<
1544 resets = <&gcc GCC_UF <<
1545 reset-names = "rst"; <<
1546 <<
1547 power-domains = <&gcc <<
1548 <<
1549 iommus = <&apps_smmu <<
1550 <<
1551 clock-names = "core_c <<
1552 "bus_ag <<
1553 "iface_ <<
1554 "core_c <<
1555 "ref_cl <<
1556 "tx_lan <<
1557 "rx_lan <<
1558 clocks = <&gcc GCC_UF <<
1559 <&gcc GCC_AG <<
1560 <&gcc GCC_UF <<
1561 <&gcc GCC_UF <<
1562 <&rpmhcc RPM <<
1563 <&gcc GCC_UF <<
1564 <&gcc GCC_UF <<
1565 freq-table-hz = <5000 <<
1566 <0 0> <<
1567 <0 0> <<
1568 <3750 <<
1569 <0 0> <<
1570 <0 0> <<
1571 <0 0> <<
1572 <<
1573 interconnects = <&agg <<
1574 &mc_ <<
1575 <&gem <<
1576 &con <<
1577 interconnect-names = <<
1578 <<
1579 qcom,ice = <&ice>; <<
1580 <<
1581 status = "disabled"; <<
1582 }; <<
1583 <<
1584 ufs_mem_phy: phy@1d87000 { <<
1585 compatible = "qcom,sc <<
1586 reg = <0 0x01d87000 0 <<
1587 clocks = <&rpmhcc RPM <<
1588 <&gcc GCC_UF <<
1589 <&gcc GCC_UF <<
1590 clock-names = "ref", <<
1591 "ref_au <<
1592 "qref"; <<
1593 power-domains = <&gcc <<
1594 resets = <&ufs_mem_hc <<
1595 reset-names = "ufsphy <<
1596 #phy-cells = <0>; <<
1597 status = "disabled"; <<
1598 }; <<
1599 <<
1600 ice: crypto@1d90000 { <<
1601 compatible = "qcom,sc <<
1602 "qcom,in <<
1603 reg = <0 0x01d90000 0 <<
1604 clocks = <&gcc GCC_UF <<
1605 }; <<
1606 <<
1607 ipa: ipa@1e40000 { 1447 ipa: ipa@1e40000 {
1608 compatible = "qcom,sc 1448 compatible = "qcom,sc7180-ipa";
1609 1449
1610 iommus = <&apps_smmu 1450 iommus = <&apps_smmu 0x440 0x0>,
1611 <&apps_smmu 1451 <&apps_smmu 0x442 0x0>;
1612 reg = <0 0x01e40000 0 1452 reg = <0 0x01e40000 0 0x7000>,
1613 <0 0x01e47000 0 1453 <0 0x01e47000 0 0x2000>,
1614 <0 0x01e04000 0 1454 <0 0x01e04000 0 0x2c000>;
1615 reg-names = "ipa-reg" 1455 reg-names = "ipa-reg",
1616 "ipa-shar 1456 "ipa-shared",
1617 "gsi"; 1457 "gsi";
1618 1458
1619 interrupts-extended = 1459 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
1620 1460 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
1621 1461 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1622 1462 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
1623 interrupt-names = "ip 1463 interrupt-names = "ipa",
1624 "gs 1464 "gsi",
1625 "ip 1465 "ipa-clock-query",
1626 "ip 1466 "ipa-setup-ready";
1627 1467
1628 clocks = <&rpmhcc RPM 1468 clocks = <&rpmhcc RPMH_IPA_CLK>;
1629 clock-names = "core"; 1469 clock-names = "core";
1630 1470
1631 interconnects = <&agg 1471 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
1632 <&agg 1472 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>,
1633 <&gem 1473 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
1634 interconnect-names = 1474 interconnect-names = "memory",
1635 1475 "imem",
1636 1476 "config";
1637 1477
1638 qcom,qmp = <&aoss_qmp 1478 qcom,qmp = <&aoss_qmp>;
1639 1479
1640 qcom,smem-states = <& 1480 qcom,smem-states = <&ipa_smp2p_out 0>,
1641 <& 1481 <&ipa_smp2p_out 1>;
1642 qcom,smem-state-names 1482 qcom,smem-state-names = "ipa-clock-enabled-valid",
1643 1483 "ipa-clock-enabled";
1644 1484
1645 status = "disabled"; 1485 status = "disabled";
1646 }; 1486 };
1647 1487
1648 tcsr_mutex: hwlock@1f40000 { 1488 tcsr_mutex: hwlock@1f40000 {
1649 compatible = "qcom,tc 1489 compatible = "qcom,tcsr-mutex";
1650 reg = <0 0x01f40000 0 1490 reg = <0 0x01f40000 0 0x20000>;
1651 #hwlock-cells = <1>; 1491 #hwlock-cells = <1>;
1652 }; 1492 };
1653 1493
1654 tcsr_regs_1: syscon@1f60000 { 1494 tcsr_regs_1: syscon@1f60000 {
1655 compatible = "qcom,sc 1495 compatible = "qcom,sc7180-tcsr", "syscon";
1656 reg = <0 0x01f60000 0 1496 reg = <0 0x01f60000 0 0x20000>;
1657 }; 1497 };
1658 1498
1659 tcsr_regs_2: syscon@1fc0000 { 1499 tcsr_regs_2: syscon@1fc0000 {
1660 compatible = "qcom,sc 1500 compatible = "qcom,sc7180-tcsr", "syscon";
1661 reg = <0 0x01fc0000 0 1501 reg = <0 0x01fc0000 0 0x40000>;
1662 }; 1502 };
1663 1503
1664 tlmm: pinctrl@3500000 { 1504 tlmm: pinctrl@3500000 {
1665 compatible = "qcom,sc 1505 compatible = "qcom,sc7180-pinctrl";
1666 reg = <0 0x03500000 0 1506 reg = <0 0x03500000 0 0x300000>,
1667 <0 0x03900000 0 1507 <0 0x03900000 0 0x300000>,
1668 <0 0x03d00000 0 1508 <0 0x03d00000 0 0x300000>;
1669 reg-names = "west", " 1509 reg-names = "west", "north", "south";
1670 interrupts = <GIC_SPI 1510 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1671 gpio-controller; 1511 gpio-controller;
1672 #gpio-cells = <2>; 1512 #gpio-cells = <2>;
1673 interrupt-controller; 1513 interrupt-controller;
1674 #interrupt-cells = <2 1514 #interrupt-cells = <2>;
1675 gpio-ranges = <&tlmm 1515 gpio-ranges = <&tlmm 0 0 120>;
1676 wakeup-parent = <&pdc 1516 wakeup-parent = <&pdc>;
1677 1517
1678 dp_hot_plug_det: dp-h 1518 dp_hot_plug_det: dp-hot-plug-det-state {
1679 pins = "gpio1 1519 pins = "gpio117";
1680 function = "d 1520 function = "dp_hot";
1681 }; 1521 };
1682 1522
1683 qspi_clk: qspi-clk-st 1523 qspi_clk: qspi-clk-state {
1684 pins = "gpio6 1524 pins = "gpio63";
1685 function = "q 1525 function = "qspi_clk";
1686 }; 1526 };
1687 1527
1688 qspi_cs0: qspi-cs0-st 1528 qspi_cs0: qspi-cs0-state {
1689 pins = "gpio6 1529 pins = "gpio68";
1690 function = "q 1530 function = "qspi_cs";
1691 }; 1531 };
1692 1532
1693 qspi_cs1: qspi-cs1-st 1533 qspi_cs1: qspi-cs1-state {
1694 pins = "gpio7 1534 pins = "gpio72";
1695 function = "q 1535 function = "qspi_cs";
1696 }; 1536 };
1697 1537
1698 qspi_data0: qspi-data !! 1538 qspi_data01: qspi-data01-state {
1699 pins = "gpio6 !! 1539 pins = "gpio64", "gpio65";
1700 function = "q <<
1701 }; <<
1702 <<
1703 qspi_data1: qspi-data <<
1704 pins = "gpio6 <<
1705 function = "q 1540 function = "qspi_data";
1706 }; 1541 };
1707 1542
1708 qspi_data23: qspi-dat 1543 qspi_data23: qspi-data23-state {
1709 pins = "gpio6 1544 pins = "gpio66", "gpio67";
1710 function = "q 1545 function = "qspi_data";
1711 }; 1546 };
1712 1547
1713 qup_i2c0_default: qup 1548 qup_i2c0_default: qup-i2c0-default-state {
1714 pins = "gpio3 1549 pins = "gpio34", "gpio35";
1715 function = "q 1550 function = "qup00";
1716 }; 1551 };
1717 1552
1718 qup_i2c1_default: qup 1553 qup_i2c1_default: qup-i2c1-default-state {
1719 pins = "gpio0 1554 pins = "gpio0", "gpio1";
1720 function = "q 1555 function = "qup01";
1721 }; 1556 };
1722 1557
1723 qup_i2c2_default: qup 1558 qup_i2c2_default: qup-i2c2-default-state {
1724 pins = "gpio1 1559 pins = "gpio15", "gpio16";
1725 function = "q 1560 function = "qup02_i2c";
1726 }; 1561 };
1727 1562
1728 qup_i2c3_default: qup 1563 qup_i2c3_default: qup-i2c3-default-state {
1729 pins = "gpio3 1564 pins = "gpio38", "gpio39";
1730 function = "q 1565 function = "qup03";
1731 }; 1566 };
1732 1567
1733 qup_i2c4_default: qup 1568 qup_i2c4_default: qup-i2c4-default-state {
1734 pins = "gpio1 1569 pins = "gpio115", "gpio116";
1735 function = "q 1570 function = "qup04_i2c";
1736 }; 1571 };
1737 1572
1738 qup_i2c5_default: qup 1573 qup_i2c5_default: qup-i2c5-default-state {
1739 pins = "gpio2 1574 pins = "gpio25", "gpio26";
1740 function = "q 1575 function = "qup05";
1741 }; 1576 };
1742 1577
1743 qup_i2c6_default: qup 1578 qup_i2c6_default: qup-i2c6-default-state {
1744 pins = "gpio5 1579 pins = "gpio59", "gpio60";
1745 function = "q 1580 function = "qup10";
1746 }; 1581 };
1747 1582
1748 qup_i2c7_default: qup 1583 qup_i2c7_default: qup-i2c7-default-state {
1749 pins = "gpio6 1584 pins = "gpio6", "gpio7";
1750 function = "q 1585 function = "qup11_i2c";
1751 }; 1586 };
1752 1587
1753 qup_i2c8_default: qup 1588 qup_i2c8_default: qup-i2c8-default-state {
1754 pins = "gpio4 1589 pins = "gpio42", "gpio43";
1755 function = "q 1590 function = "qup12";
1756 }; 1591 };
1757 1592
1758 qup_i2c9_default: qup 1593 qup_i2c9_default: qup-i2c9-default-state {
1759 pins = "gpio4 1594 pins = "gpio46", "gpio47";
1760 function = "q 1595 function = "qup13_i2c";
1761 }; 1596 };
1762 1597
1763 qup_i2c10_default: qu 1598 qup_i2c10_default: qup-i2c10-default-state {
1764 pins = "gpio8 1599 pins = "gpio86", "gpio87";
1765 function = "q 1600 function = "qup14";
1766 }; 1601 };
1767 1602
1768 qup_i2c11_default: qu 1603 qup_i2c11_default: qup-i2c11-default-state {
1769 pins = "gpio5 1604 pins = "gpio53", "gpio54";
1770 function = "q 1605 function = "qup15";
1771 }; 1606 };
1772 1607
1773 qup_spi0_spi: qup-spi 1608 qup_spi0_spi: qup-spi0-spi-state {
1774 pins = "gpio3 1609 pins = "gpio34", "gpio35", "gpio36";
1775 function = "q 1610 function = "qup00";
1776 }; 1611 };
1777 1612
1778 qup_spi0_cs: qup-spi0 1613 qup_spi0_cs: qup-spi0-cs-state {
1779 pins = "gpio3 1614 pins = "gpio37";
1780 function = "q 1615 function = "qup00";
1781 }; 1616 };
1782 1617
1783 qup_spi0_cs_gpio: qup 1618 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state {
1784 pins = "gpio3 1619 pins = "gpio37";
1785 function = "g 1620 function = "gpio";
1786 }; 1621 };
1787 1622
1788 qup_spi1_spi: qup-spi 1623 qup_spi1_spi: qup-spi1-spi-state {
1789 pins = "gpio0 1624 pins = "gpio0", "gpio1", "gpio2";
1790 function = "q 1625 function = "qup01";
1791 }; 1626 };
1792 1627
1793 qup_spi1_cs: qup-spi1 1628 qup_spi1_cs: qup-spi1-cs-state {
1794 pins = "gpio3 1629 pins = "gpio3";
1795 function = "q 1630 function = "qup01";
1796 }; 1631 };
1797 1632
1798 qup_spi1_cs_gpio: qup 1633 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state {
1799 pins = "gpio3 1634 pins = "gpio3";
1800 function = "g 1635 function = "gpio";
1801 }; 1636 };
1802 1637
1803 qup_spi3_spi: qup-spi 1638 qup_spi3_spi: qup-spi3-spi-state {
1804 pins = "gpio3 1639 pins = "gpio38", "gpio39", "gpio40";
1805 function = "q 1640 function = "qup03";
1806 }; 1641 };
1807 1642
1808 qup_spi3_cs: qup-spi3 1643 qup_spi3_cs: qup-spi3-cs-state {
1809 pins = "gpio4 1644 pins = "gpio41";
1810 function = "q 1645 function = "qup03";
1811 }; 1646 };
1812 1647
1813 qup_spi3_cs_gpio: qup 1648 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state {
1814 pins = "gpio4 1649 pins = "gpio41";
1815 function = "g 1650 function = "gpio";
1816 }; 1651 };
1817 1652
1818 qup_spi5_spi: qup-spi 1653 qup_spi5_spi: qup-spi5-spi-state {
1819 pins = "gpio2 1654 pins = "gpio25", "gpio26", "gpio27";
1820 function = "q 1655 function = "qup05";
1821 }; 1656 };
1822 1657
1823 qup_spi5_cs: qup-spi5 1658 qup_spi5_cs: qup-spi5-cs-state {
1824 pins = "gpio2 1659 pins = "gpio28";
1825 function = "q 1660 function = "qup05";
1826 }; 1661 };
1827 1662
1828 qup_spi5_cs_gpio: qup 1663 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state {
1829 pins = "gpio2 1664 pins = "gpio28";
1830 function = "g 1665 function = "gpio";
1831 }; 1666 };
1832 1667
1833 qup_spi6_spi: qup-spi 1668 qup_spi6_spi: qup-spi6-spi-state {
1834 pins = "gpio5 1669 pins = "gpio59", "gpio60", "gpio61";
1835 function = "q 1670 function = "qup10";
1836 }; 1671 };
1837 1672
1838 qup_spi6_cs: qup-spi6 1673 qup_spi6_cs: qup-spi6-cs-state {
1839 pins = "gpio6 1674 pins = "gpio62";
1840 function = "q 1675 function = "qup10";
1841 }; 1676 };
1842 1677
1843 qup_spi6_cs_gpio: qup 1678 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state {
1844 pins = "gpio6 1679 pins = "gpio62";
1845 function = "g 1680 function = "gpio";
1846 }; 1681 };
1847 1682
1848 qup_spi8_spi: qup-spi 1683 qup_spi8_spi: qup-spi8-spi-state {
1849 pins = "gpio4 1684 pins = "gpio42", "gpio43", "gpio44";
1850 function = "q 1685 function = "qup12";
1851 }; 1686 };
1852 1687
1853 qup_spi8_cs: qup-spi8 1688 qup_spi8_cs: qup-spi8-cs-state {
1854 pins = "gpio4 1689 pins = "gpio45";
1855 function = "q 1690 function = "qup12";
1856 }; 1691 };
1857 1692
1858 qup_spi8_cs_gpio: qup 1693 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state {
1859 pins = "gpio4 1694 pins = "gpio45";
1860 function = "g 1695 function = "gpio";
1861 }; 1696 };
1862 1697
1863 qup_spi10_spi: qup-sp 1698 qup_spi10_spi: qup-spi10-spi-state {
1864 pins = "gpio8 1699 pins = "gpio86", "gpio87", "gpio88";
1865 function = "q 1700 function = "qup14";
1866 }; 1701 };
1867 1702
1868 qup_spi10_cs: qup-spi 1703 qup_spi10_cs: qup-spi10-cs-state {
1869 pins = "gpio8 1704 pins = "gpio89";
1870 function = "q 1705 function = "qup14";
1871 }; 1706 };
1872 1707
1873 qup_spi10_cs_gpio: qu 1708 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state {
1874 pins = "gpio8 1709 pins = "gpio89";
1875 function = "g 1710 function = "gpio";
1876 }; 1711 };
1877 1712
1878 qup_spi11_spi: qup-sp 1713 qup_spi11_spi: qup-spi11-spi-state {
1879 pins = "gpio5 1714 pins = "gpio53", "gpio54", "gpio55";
1880 function = "q 1715 function = "qup15";
1881 }; 1716 };
1882 1717
1883 qup_spi11_cs: qup-spi 1718 qup_spi11_cs: qup-spi11-cs-state {
1884 pins = "gpio5 1719 pins = "gpio56";
1885 function = "q 1720 function = "qup15";
1886 }; 1721 };
1887 1722
1888 qup_spi11_cs_gpio: qu 1723 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state {
1889 pins = "gpio5 1724 pins = "gpio56";
1890 function = "g 1725 function = "gpio";
1891 }; 1726 };
1892 1727
1893 qup_uart0_default: qu 1728 qup_uart0_default: qup-uart0-default-state {
1894 qup_uart0_cts 1729 qup_uart0_cts: cts-pins {
1895 pins 1730 pins = "gpio34";
1896 funct 1731 function = "qup00";
1897 }; 1732 };
1898 1733
1899 qup_uart0_rts 1734 qup_uart0_rts: rts-pins {
1900 pins 1735 pins = "gpio35";
1901 funct 1736 function = "qup00";
1902 }; 1737 };
1903 1738
1904 qup_uart0_tx: 1739 qup_uart0_tx: tx-pins {
1905 pins 1740 pins = "gpio36";
1906 funct 1741 function = "qup00";
1907 }; 1742 };
1908 1743
1909 qup_uart0_rx: 1744 qup_uart0_rx: rx-pins {
1910 pins 1745 pins = "gpio37";
1911 funct 1746 function = "qup00";
1912 }; 1747 };
1913 }; 1748 };
1914 1749
1915 qup_uart1_default: qu 1750 qup_uart1_default: qup-uart1-default-state {
1916 qup_uart1_cts 1751 qup_uart1_cts: cts-pins {
1917 pins 1752 pins = "gpio0";
1918 funct 1753 function = "qup01";
1919 }; 1754 };
1920 1755
1921 qup_uart1_rts 1756 qup_uart1_rts: rts-pins {
1922 pins 1757 pins = "gpio1";
1923 funct 1758 function = "qup01";
1924 }; 1759 };
1925 1760
1926 qup_uart1_tx: 1761 qup_uart1_tx: tx-pins {
1927 pins 1762 pins = "gpio2";
1928 funct 1763 function = "qup01";
1929 }; 1764 };
1930 1765
1931 qup_uart1_rx: 1766 qup_uart1_rx: rx-pins {
1932 pins 1767 pins = "gpio3";
1933 funct 1768 function = "qup01";
1934 }; 1769 };
1935 }; 1770 };
1936 1771
1937 qup_uart2_default: qu 1772 qup_uart2_default: qup-uart2-default-state {
1938 qup_uart2_tx: 1773 qup_uart2_tx: tx-pins {
1939 pins 1774 pins = "gpio15";
1940 funct 1775 function = "qup02_uart";
1941 }; 1776 };
1942 1777
1943 qup_uart2_rx: 1778 qup_uart2_rx: rx-pins {
1944 pins 1779 pins = "gpio16";
1945 funct 1780 function = "qup02_uart";
1946 }; 1781 };
1947 }; 1782 };
1948 1783
1949 qup_uart3_default: qu 1784 qup_uart3_default: qup-uart3-default-state {
1950 qup_uart3_cts 1785 qup_uart3_cts: cts-pins {
1951 pins 1786 pins = "gpio38";
1952 funct 1787 function = "qup03";
1953 }; 1788 };
1954 1789
1955 qup_uart3_rts 1790 qup_uart3_rts: rts-pins {
1956 pins 1791 pins = "gpio39";
1957 funct 1792 function = "qup03";
1958 }; 1793 };
1959 1794
1960 qup_uart3_tx: 1795 qup_uart3_tx: tx-pins {
1961 pins 1796 pins = "gpio40";
1962 funct 1797 function = "qup03";
1963 }; 1798 };
1964 1799
1965 qup_uart3_rx: 1800 qup_uart3_rx: rx-pins {
1966 pins 1801 pins = "gpio41";
1967 funct 1802 function = "qup03";
1968 }; 1803 };
1969 }; 1804 };
1970 1805
1971 qup_uart4_default: qu 1806 qup_uart4_default: qup-uart4-default-state {
1972 qup_uart4_tx: 1807 qup_uart4_tx: tx-pins {
1973 pins 1808 pins = "gpio115";
1974 funct 1809 function = "qup04_uart";
1975 }; 1810 };
1976 1811
1977 qup_uart4_rx: 1812 qup_uart4_rx: rx-pins {
1978 pins 1813 pins = "gpio116";
1979 funct 1814 function = "qup04_uart";
1980 }; 1815 };
1981 }; 1816 };
1982 1817
1983 qup_uart5_default: qu 1818 qup_uart5_default: qup-uart5-default-state {
1984 qup_uart5_cts 1819 qup_uart5_cts: cts-pins {
1985 pins 1820 pins = "gpio25";
1986 funct 1821 function = "qup05";
1987 }; 1822 };
1988 1823
1989 qup_uart5_rts 1824 qup_uart5_rts: rts-pins {
1990 pins 1825 pins = "gpio26";
1991 funct 1826 function = "qup05";
1992 }; 1827 };
1993 1828
1994 qup_uart5_tx: 1829 qup_uart5_tx: tx-pins {
1995 pins 1830 pins = "gpio27";
1996 funct 1831 function = "qup05";
1997 }; 1832 };
1998 1833
1999 qup_uart5_rx: 1834 qup_uart5_rx: rx-pins {
2000 pins 1835 pins = "gpio28";
2001 funct 1836 function = "qup05";
2002 }; 1837 };
2003 }; 1838 };
2004 1839
2005 qup_uart6_default: qu 1840 qup_uart6_default: qup-uart6-default-state {
2006 qup_uart6_cts 1841 qup_uart6_cts: cts-pins {
2007 pins 1842 pins = "gpio59";
2008 funct 1843 function = "qup10";
2009 }; 1844 };
2010 1845
2011 qup_uart6_rts 1846 qup_uart6_rts: rts-pins {
2012 pins 1847 pins = "gpio60";
2013 funct 1848 function = "qup10";
2014 }; 1849 };
2015 1850
2016 qup_uart6_tx: 1851 qup_uart6_tx: tx-pins {
2017 pins 1852 pins = "gpio61";
2018 funct 1853 function = "qup10";
2019 }; 1854 };
2020 1855
2021 qup_uart6_rx: 1856 qup_uart6_rx: rx-pins {
2022 pins 1857 pins = "gpio62";
2023 funct 1858 function = "qup10";
2024 }; 1859 };
2025 }; 1860 };
2026 1861
2027 qup_uart7_default: qu 1862 qup_uart7_default: qup-uart7-default-state {
2028 qup_uart7_tx: 1863 qup_uart7_tx: tx-pins {
2029 pins 1864 pins = "gpio6";
2030 funct 1865 function = "qup11_uart";
2031 }; 1866 };
2032 1867
2033 qup_uart7_rx: 1868 qup_uart7_rx: rx-pins {
2034 pins 1869 pins = "gpio7";
2035 funct 1870 function = "qup11_uart";
2036 }; 1871 };
2037 }; 1872 };
2038 1873
2039 qup_uart8_default: qu 1874 qup_uart8_default: qup-uart8-default-state {
2040 qup_uart8_tx: 1875 qup_uart8_tx: tx-pins {
2041 pins 1876 pins = "gpio44";
2042 funct 1877 function = "qup12";
2043 }; 1878 };
2044 1879
2045 qup_uart8_rx: 1880 qup_uart8_rx: rx-pins {
2046 pins 1881 pins = "gpio45";
2047 funct 1882 function = "qup12";
2048 }; 1883 };
2049 }; 1884 };
2050 1885
2051 qup_uart9_default: qu 1886 qup_uart9_default: qup-uart9-default-state {
2052 qup_uart9_tx: 1887 qup_uart9_tx: tx-pins {
2053 pins 1888 pins = "gpio46";
2054 funct 1889 function = "qup13_uart";
2055 }; 1890 };
2056 1891
2057 qup_uart9_rx: 1892 qup_uart9_rx: rx-pins {
2058 pins 1893 pins = "gpio47";
2059 funct 1894 function = "qup13_uart";
2060 }; 1895 };
2061 }; 1896 };
2062 1897
2063 qup_uart10_default: q 1898 qup_uart10_default: qup-uart10-default-state {
2064 qup_uart10_ct 1899 qup_uart10_cts: cts-pins {
2065 pins 1900 pins = "gpio86";
2066 funct 1901 function = "qup14";
2067 }; 1902 };
2068 1903
2069 qup_uart10_rt 1904 qup_uart10_rts: rts-pins {
2070 pins 1905 pins = "gpio87";
2071 funct 1906 function = "qup14";
2072 }; 1907 };
2073 1908
2074 qup_uart10_tx 1909 qup_uart10_tx: tx-pins {
2075 pins 1910 pins = "gpio88";
2076 funct 1911 function = "qup14";
2077 }; 1912 };
2078 1913
2079 qup_uart10_rx 1914 qup_uart10_rx: rx-pins {
2080 pins 1915 pins = "gpio89";
2081 funct 1916 function = "qup14";
2082 }; 1917 };
2083 }; 1918 };
2084 1919
2085 qup_uart11_default: q 1920 qup_uart11_default: qup-uart11-default-state {
2086 qup_uart11_ct 1921 qup_uart11_cts: cts-pins {
2087 pins 1922 pins = "gpio53";
2088 funct 1923 function = "qup15";
2089 }; 1924 };
2090 1925
2091 qup_uart11_rt 1926 qup_uart11_rts: rts-pins {
2092 pins 1927 pins = "gpio54";
2093 funct 1928 function = "qup15";
2094 }; 1929 };
2095 1930
2096 qup_uart11_tx 1931 qup_uart11_tx: tx-pins {
2097 pins 1932 pins = "gpio55";
2098 funct 1933 function = "qup15";
2099 }; 1934 };
2100 1935
2101 qup_uart11_rx 1936 qup_uart11_rx: rx-pins {
2102 pins 1937 pins = "gpio56";
2103 funct 1938 function = "qup15";
2104 }; 1939 };
2105 }; 1940 };
2106 1941
2107 sec_mi2s_active: sec- 1942 sec_mi2s_active: sec-mi2s-active-state {
2108 pins = "gpio4 1943 pins = "gpio49", "gpio50", "gpio51";
2109 function = "m 1944 function = "mi2s_1";
2110 }; 1945 };
2111 1946
2112 pri_mi2s_active: pri- 1947 pri_mi2s_active: pri-mi2s-active-state {
2113 pins = "gpio5 1948 pins = "gpio53", "gpio54", "gpio55", "gpio56";
2114 function = "m 1949 function = "mi2s_0";
2115 }; 1950 };
2116 1951
2117 pri_mi2s_mclk_active: 1952 pri_mi2s_mclk_active: pri-mi2s-mclk-active-state {
2118 pins = "gpio5 1953 pins = "gpio57";
2119 function = "l 1954 function = "lpass_ext";
2120 }; 1955 };
2121 <<
2122 ter_mi2s_active: ter- <<
2123 pins = "gpio6 <<
2124 function = "m <<
2125 }; <<
2126 }; 1956 };
2127 1957
2128 remoteproc_mpss: remoteproc@4 1958 remoteproc_mpss: remoteproc@4080000 {
2129 compatible = "qcom,sc 1959 compatible = "qcom,sc7180-mpss-pas";
2130 reg = <0 0x04080000 0 1960 reg = <0 0x04080000 0 0x4040>;
2131 1961
2132 interrupts-extended = 1962 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
2133 1963 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2134 1964 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2135 1965 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2136 1966 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
2137 1967 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
2138 interrupt-names = "wd 1968 interrupt-names = "wdog", "fatal", "ready", "handover",
2139 "st 1969 "stop-ack", "shutdown-ack";
2140 1970
2141 clocks = <&rpmhcc RPM 1971 clocks = <&rpmhcc RPMH_CXO_CLK>;
2142 clock-names = "xo"; 1972 clock-names = "xo";
2143 1973
2144 power-domains = <&rpm 1974 power-domains = <&rpmhpd SC7180_CX>,
2145 <&rpm 1975 <&rpmhpd SC7180_MX>,
2146 <&rpm 1976 <&rpmhpd SC7180_MSS>;
2147 power-domain-names = 1977 power-domain-names = "cx", "mx", "mss";
2148 1978
2149 memory-region = <&mps 1979 memory-region = <&mpss_mem>;
2150 1980
2151 qcom,qmp = <&aoss_qmp 1981 qcom,qmp = <&aoss_qmp>;
2152 1982
2153 qcom,smem-states = <& 1983 qcom,smem-states = <&modem_smp2p_out 0>;
2154 qcom,smem-state-names 1984 qcom,smem-state-names = "stop";
2155 1985
2156 status = "disabled"; 1986 status = "disabled";
2157 1987
2158 glink-edge { 1988 glink-edge {
2159 interrupts = 1989 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
2160 label = "mode 1990 label = "modem";
2161 qcom,remote-p 1991 qcom,remote-pid = <1>;
2162 mboxes = <&ap 1992 mboxes = <&apss_shared 12>;
2163 }; 1993 };
2164 }; 1994 };
2165 1995
2166 gpu: gpu@5000000 { 1996 gpu: gpu@5000000 {
2167 compatible = "qcom,ad 1997 compatible = "qcom,adreno-618.0", "qcom,adreno";
2168 reg = <0 0x05000000 0 1998 reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x1000>,
2169 <0 0x05061000 1999 <0 0x05061000 0 0x800>;
2170 reg-names = "kgsl_3d0 2000 reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc";
2171 interrupts = <GIC_SPI 2001 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2172 iommus = <&adreno_smm 2002 iommus = <&adreno_smmu 0>;
2173 operating-points-v2 = 2003 operating-points-v2 = <&gpu_opp_table>;
2174 qcom,gmu = <&gmu>; 2004 qcom,gmu = <&gmu>;
2175 2005
2176 #cooling-cells = <2>; 2006 #cooling-cells = <2>;
2177 2007
2178 nvmem-cells = <&gpu_s 2008 nvmem-cells = <&gpu_speed_bin>;
2179 nvmem-cell-names = "s 2009 nvmem-cell-names = "speed_bin";
2180 2010
2181 interconnects = <&gem 2011 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
2182 interconnect-names = 2012 interconnect-names = "gfx-mem";
2183 2013
2184 gpu_opp_table: opp-ta 2014 gpu_opp_table: opp-table {
2185 compatible = 2015 compatible = "operating-points-v2";
2186 2016
2187 opp-825000000 2017 opp-825000000 {
2188 opp-h 2018 opp-hz = /bits/ 64 <825000000>;
2189 opp-l 2019 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2190 opp-p 2020 opp-peak-kBps = <8532000>;
2191 opp-s 2021 opp-supported-hw = <0x04>;
2192 }; 2022 };
2193 2023
2194 opp-800000000 2024 opp-800000000 {
2195 opp-h 2025 opp-hz = /bits/ 64 <800000000>;
2196 opp-l 2026 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2197 opp-p 2027 opp-peak-kBps = <8532000>;
2198 opp-s 2028 opp-supported-hw = <0x07>;
2199 }; 2029 };
2200 2030
2201 opp-650000000 2031 opp-650000000 {
2202 opp-h 2032 opp-hz = /bits/ 64 <650000000>;
2203 opp-l 2033 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2204 opp-p 2034 opp-peak-kBps = <7216000>;
2205 opp-s 2035 opp-supported-hw = <0x07>;
2206 }; 2036 };
2207 2037
2208 opp-565000000 2038 opp-565000000 {
2209 opp-h 2039 opp-hz = /bits/ 64 <565000000>;
2210 opp-l 2040 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2211 opp-p 2041 opp-peak-kBps = <5412000>;
2212 opp-s 2042 opp-supported-hw = <0x07>;
2213 }; 2043 };
2214 2044
2215 opp-430000000 2045 opp-430000000 {
2216 opp-h 2046 opp-hz = /bits/ 64 <430000000>;
2217 opp-l 2047 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2218 opp-p 2048 opp-peak-kBps = <5412000>;
2219 opp-s 2049 opp-supported-hw = <0x07>;
2220 }; 2050 };
2221 2051
2222 opp-355000000 2052 opp-355000000 {
2223 opp-h 2053 opp-hz = /bits/ 64 <355000000>;
2224 opp-l 2054 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2225 opp-p 2055 opp-peak-kBps = <3072000>;
2226 opp-s 2056 opp-supported-hw = <0x07>;
2227 }; 2057 };
2228 2058
2229 opp-267000000 2059 opp-267000000 {
2230 opp-h 2060 opp-hz = /bits/ 64 <267000000>;
2231 opp-l 2061 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2232 opp-p 2062 opp-peak-kBps = <3072000>;
2233 opp-s 2063 opp-supported-hw = <0x07>;
2234 }; 2064 };
2235 2065
2236 opp-180000000 2066 opp-180000000 {
2237 opp-h 2067 opp-hz = /bits/ 64 <180000000>;
2238 opp-l 2068 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2239 opp-p 2069 opp-peak-kBps = <1804000>;
2240 opp-s 2070 opp-supported-hw = <0x07>;
2241 }; 2071 };
2242 }; 2072 };
2243 }; 2073 };
2244 2074
2245 adreno_smmu: iommu@5040000 { 2075 adreno_smmu: iommu@5040000 {
2246 compatible = "qcom,sc 2076 compatible = "qcom,sc7180-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
2247 reg = <0 0x05040000 0 2077 reg = <0 0x05040000 0 0x10000>;
2248 #iommu-cells = <1>; 2078 #iommu-cells = <1>;
2249 #global-interrupts = 2079 #global-interrupts = <2>;
2250 interrupts = <GIC_SPI 2080 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
2251 <GIC_ 2081 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
2252 <GIC_ 2082 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
2253 <GIC_ 2083 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
2254 <GIC_ 2084 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
2255 <GIC_ 2085 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
2256 <GIC_ 2086 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
2257 <GIC_ 2087 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
2258 <GIC_ 2088 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
2259 <GIC_ 2089 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
2260 2090
2261 clocks = <&gcc GCC_GP 2091 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2262 <&gcc GCC_GPU 2092 <&gcc GCC_GPU_CFG_AHB_CLK>;
2263 clock-names = "bus", 2093 clock-names = "bus", "iface";
2264 2094
2265 power-domains = <&gpu 2095 power-domains = <&gpucc CX_GDSC>;
2266 }; 2096 };
2267 2097
2268 gmu: gmu@506a000 { 2098 gmu: gmu@506a000 {
2269 compatible = "qcom,ad 2099 compatible = "qcom,adreno-gmu-618.0", "qcom,adreno-gmu";
2270 reg = <0 0x0506a000 0 2100 reg = <0 0x0506a000 0 0x31000>, <0 0x0b290000 0 0x10000>,
2271 <0 0x0b490000 2101 <0 0x0b490000 0 0x10000>;
2272 reg-names = "gmu", "g 2102 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
2273 interrupts = <GIC_SPI 2103 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2274 <GIC_SPI 3 2104 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2275 interrupt-names = "hf 2105 interrupt-names = "hfi", "gmu";
2276 clocks = <&gpucc GPU_ 2106 clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
2277 <&gpucc GPU_CC 2107 <&gpucc GPU_CC_CXO_CLK>,
2278 <&gcc GCC_DDRS 2108 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2279 <&gcc GCC_GPU_ 2109 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
2280 clock-names = "gmu", 2110 clock-names = "gmu", "cxo", "axi", "memnoc";
2281 power-domains = <&gpu 2111 power-domains = <&gpucc CX_GDSC>, <&gpucc GX_GDSC>;
2282 power-domain-names = 2112 power-domain-names = "cx", "gx";
2283 iommus = <&adreno_smm 2113 iommus = <&adreno_smmu 5>;
2284 operating-points-v2 = 2114 operating-points-v2 = <&gmu_opp_table>;
2285 2115
2286 gmu_opp_table: opp-ta 2116 gmu_opp_table: opp-table {
2287 compatible = 2117 compatible = "operating-points-v2";
2288 2118
2289 opp-200000000 2119 opp-200000000 {
2290 opp-h 2120 opp-hz = /bits/ 64 <200000000>;
2291 opp-l 2121 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2292 }; 2122 };
2293 }; 2123 };
2294 }; 2124 };
2295 2125
2296 gpucc: clock-controller@50900 2126 gpucc: clock-controller@5090000 {
2297 compatible = "qcom,sc 2127 compatible = "qcom,sc7180-gpucc";
2298 reg = <0 0x05090000 0 2128 reg = <0 0x05090000 0 0x9000>;
2299 clocks = <&rpmhcc RPM 2129 clocks = <&rpmhcc RPMH_CXO_CLK>,
2300 <&gcc GCC_GP 2130 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2301 <&gcc GCC_GP 2131 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2302 clock-names = "bi_tcx 2132 clock-names = "bi_tcxo",
2303 "gcc_gp 2133 "gcc_gpu_gpll0_clk_src",
2304 "gcc_gp 2134 "gcc_gpu_gpll0_div_clk_src";
2305 #clock-cells = <1>; 2135 #clock-cells = <1>;
2306 #reset-cells = <1>; 2136 #reset-cells = <1>;
2307 #power-domain-cells = 2137 #power-domain-cells = <1>;
2308 }; 2138 };
2309 2139
2310 dma@10a2000 { 2140 dma@10a2000 {
2311 compatible = "qcom,sc 2141 compatible = "qcom,sc7180-dcc", "qcom,dcc";
2312 reg = <0x0 0x010a2000 2142 reg = <0x0 0x010a2000 0x0 0x1000>,
2313 <0x0 0x010ae000 2143 <0x0 0x010ae000 0x0 0x2000>;
2314 status = "disabled"; <<
2315 }; 2144 };
2316 2145
2317 stm@6002000 { 2146 stm@6002000 {
2318 compatible = "arm,cor 2147 compatible = "arm,coresight-stm", "arm,primecell";
2319 reg = <0 0x06002000 0 2148 reg = <0 0x06002000 0 0x1000>,
2320 <0 0x16280000 0 2149 <0 0x16280000 0 0x180000>;
2321 reg-names = "stm-base 2150 reg-names = "stm-base", "stm-stimulus-base";
2322 2151
2323 clocks = <&aoss_qmp>; 2152 clocks = <&aoss_qmp>;
2324 clock-names = "apb_pc 2153 clock-names = "apb_pclk";
2325 2154
2326 out-ports { 2155 out-ports {
2327 port { 2156 port {
2328 stm_o 2157 stm_out: endpoint {
2329 2158 remote-endpoint = <&funnel0_in7>;
2330 }; 2159 };
2331 }; 2160 };
2332 }; 2161 };
2333 }; 2162 };
2334 2163
2335 funnel@6041000 { 2164 funnel@6041000 {
2336 compatible = "arm,cor 2165 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2337 reg = <0 0x06041000 0 2166 reg = <0 0x06041000 0 0x1000>;
2338 2167
2339 clocks = <&aoss_qmp>; 2168 clocks = <&aoss_qmp>;
2340 clock-names = "apb_pc 2169 clock-names = "apb_pclk";
2341 2170
2342 out-ports { 2171 out-ports {
2343 port { 2172 port {
2344 funne 2173 funnel0_out: endpoint {
2345 2174 remote-endpoint = <&merge_funnel_in0>;
2346 }; 2175 };
2347 }; 2176 };
2348 }; 2177 };
2349 2178
2350 in-ports { 2179 in-ports {
2351 #address-cell 2180 #address-cells = <1>;
2352 #size-cells = 2181 #size-cells = <0>;
2353 2182
2354 port@7 { 2183 port@7 {
2355 reg = 2184 reg = <7>;
2356 funne 2185 funnel0_in7: endpoint {
2357 2186 remote-endpoint = <&stm_out>;
2358 }; 2187 };
2359 }; 2188 };
2360 }; 2189 };
2361 }; 2190 };
2362 2191
2363 funnel@6042000 { 2192 funnel@6042000 {
2364 compatible = "arm,cor 2193 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2365 reg = <0 0x06042000 0 2194 reg = <0 0x06042000 0 0x1000>;
2366 2195
2367 clocks = <&aoss_qmp>; 2196 clocks = <&aoss_qmp>;
2368 clock-names = "apb_pc 2197 clock-names = "apb_pclk";
2369 2198
2370 out-ports { 2199 out-ports {
2371 port { 2200 port {
2372 funne 2201 funnel1_out: endpoint {
2373 2202 remote-endpoint = <&merge_funnel_in1>;
2374 }; 2203 };
2375 }; 2204 };
2376 }; 2205 };
2377 2206
2378 in-ports { 2207 in-ports {
2379 #address-cell 2208 #address-cells = <1>;
2380 #size-cells = 2209 #size-cells = <0>;
2381 2210
2382 port@4 { 2211 port@4 {
2383 reg = 2212 reg = <4>;
2384 funne 2213 funnel1_in4: endpoint {
2385 2214 remote-endpoint = <&apss_merge_funnel_out>;
2386 }; 2215 };
2387 }; 2216 };
2388 }; 2217 };
2389 }; 2218 };
2390 2219
2391 funnel@6045000 { 2220 funnel@6045000 {
2392 compatible = "arm,cor 2221 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2393 reg = <0 0x06045000 0 2222 reg = <0 0x06045000 0 0x1000>;
2394 2223
2395 clocks = <&aoss_qmp>; 2224 clocks = <&aoss_qmp>;
2396 clock-names = "apb_pc 2225 clock-names = "apb_pclk";
2397 2226
2398 out-ports { 2227 out-ports {
2399 port { 2228 port {
2400 merge 2229 merge_funnel_out: endpoint {
2401 2230 remote-endpoint = <&swao_funnel_in>;
2402 }; 2231 };
2403 }; 2232 };
2404 }; 2233 };
2405 2234
2406 in-ports { 2235 in-ports {
2407 #address-cell 2236 #address-cells = <1>;
2408 #size-cells = 2237 #size-cells = <0>;
2409 2238
2410 port@0 { 2239 port@0 {
2411 reg = 2240 reg = <0>;
2412 merge 2241 merge_funnel_in0: endpoint {
2413 2242 remote-endpoint = <&funnel0_out>;
2414 }; 2243 };
2415 }; 2244 };
2416 2245
2417 port@1 { 2246 port@1 {
2418 reg = 2247 reg = <1>;
2419 merge 2248 merge_funnel_in1: endpoint {
2420 2249 remote-endpoint = <&funnel1_out>;
2421 }; 2250 };
2422 }; 2251 };
2423 }; 2252 };
2424 }; 2253 };
2425 2254
2426 replicator@6046000 { 2255 replicator@6046000 {
2427 compatible = "arm,cor 2256 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2428 reg = <0 0x06046000 0 2257 reg = <0 0x06046000 0 0x1000>;
2429 2258
2430 clocks = <&aoss_qmp>; 2259 clocks = <&aoss_qmp>;
2431 clock-names = "apb_pc 2260 clock-names = "apb_pclk";
2432 2261
2433 out-ports { 2262 out-ports {
2434 port { 2263 port {
2435 repli 2264 replicator_out: endpoint {
2436 2265 remote-endpoint = <&etr_in>;
2437 }; 2266 };
2438 }; 2267 };
2439 }; 2268 };
2440 2269
2441 in-ports { 2270 in-ports {
2442 port { 2271 port {
2443 repli 2272 replicator_in: endpoint {
2444 2273 remote-endpoint = <&swao_replicator_out>;
2445 }; 2274 };
2446 }; 2275 };
2447 }; 2276 };
2448 }; 2277 };
2449 2278
2450 etr@6048000 { 2279 etr@6048000 {
2451 compatible = "arm,cor 2280 compatible = "arm,coresight-tmc", "arm,primecell";
2452 reg = <0 0x06048000 0 2281 reg = <0 0x06048000 0 0x1000>;
2453 iommus = <&apps_smmu 2282 iommus = <&apps_smmu 0x04a0 0x20>;
2454 2283
2455 clocks = <&aoss_qmp>; 2284 clocks = <&aoss_qmp>;
2456 clock-names = "apb_pc 2285 clock-names = "apb_pclk";
2457 arm,scatter-gather; 2286 arm,scatter-gather;
2458 2287
2459 in-ports { 2288 in-ports {
2460 port { 2289 port {
2461 etr_i 2290 etr_in: endpoint {
2462 2291 remote-endpoint = <&replicator_out>;
2463 }; 2292 };
2464 }; 2293 };
2465 }; 2294 };
2466 }; 2295 };
2467 2296
2468 funnel@6b04000 { 2297 funnel@6b04000 {
2469 compatible = "arm,cor 2298 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2470 reg = <0 0x06b04000 0 2299 reg = <0 0x06b04000 0 0x1000>;
2471 2300
2472 clocks = <&aoss_qmp>; 2301 clocks = <&aoss_qmp>;
2473 clock-names = "apb_pc 2302 clock-names = "apb_pclk";
2474 2303
2475 out-ports { 2304 out-ports {
2476 port { 2305 port {
2477 swao_ 2306 swao_funnel_out: endpoint {
2478 2307 remote-endpoint = <&etf_in>;
2479 }; 2308 };
2480 }; 2309 };
2481 }; 2310 };
2482 2311
2483 in-ports { 2312 in-ports {
2484 #address-cell 2313 #address-cells = <1>;
2485 #size-cells = 2314 #size-cells = <0>;
2486 2315
2487 port@7 { 2316 port@7 {
2488 reg = 2317 reg = <7>;
2489 swao_ 2318 swao_funnel_in: endpoint {
2490 2319 remote-endpoint = <&merge_funnel_out>;
2491 }; 2320 };
2492 }; 2321 };
2493 }; 2322 };
2494 }; 2323 };
2495 2324
2496 etf@6b05000 { 2325 etf@6b05000 {
2497 compatible = "arm,cor 2326 compatible = "arm,coresight-tmc", "arm,primecell";
2498 reg = <0 0x06b05000 0 2327 reg = <0 0x06b05000 0 0x1000>;
2499 2328
2500 clocks = <&aoss_qmp>; 2329 clocks = <&aoss_qmp>;
2501 clock-names = "apb_pc 2330 clock-names = "apb_pclk";
2502 2331
2503 out-ports { 2332 out-ports {
2504 port { 2333 port {
2505 etf_o 2334 etf_out: endpoint {
2506 2335 remote-endpoint = <&swao_replicator_in>;
2507 }; 2336 };
2508 }; 2337 };
2509 }; 2338 };
2510 2339
2511 in-ports { 2340 in-ports {
2512 port { 2341 port {
2513 etf_i 2342 etf_in: endpoint {
2514 2343 remote-endpoint = <&swao_funnel_out>;
2515 }; 2344 };
2516 }; 2345 };
2517 }; 2346 };
2518 }; 2347 };
2519 2348
2520 replicator@6b06000 { 2349 replicator@6b06000 {
2521 compatible = "arm,cor 2350 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2522 reg = <0 0x06b06000 0 2351 reg = <0 0x06b06000 0 0x1000>;
2523 2352
2524 clocks = <&aoss_qmp>; 2353 clocks = <&aoss_qmp>;
2525 clock-names = "apb_pc 2354 clock-names = "apb_pclk";
2526 qcom,replicator-loses 2355 qcom,replicator-loses-context;
2527 2356
2528 out-ports { 2357 out-ports {
2529 port { 2358 port {
2530 swao_ 2359 swao_replicator_out: endpoint {
2531 2360 remote-endpoint = <&replicator_in>;
2532 }; 2361 };
2533 }; 2362 };
2534 }; 2363 };
2535 2364
2536 in-ports { 2365 in-ports {
2537 port { 2366 port {
2538 swao_ 2367 swao_replicator_in: endpoint {
2539 2368 remote-endpoint = <&etf_out>;
2540 }; 2369 };
2541 }; 2370 };
2542 }; 2371 };
2543 }; 2372 };
2544 2373
2545 etm@7040000 { 2374 etm@7040000 {
2546 compatible = "arm,cor 2375 compatible = "arm,coresight-etm4x", "arm,primecell";
2547 reg = <0 0x07040000 0 2376 reg = <0 0x07040000 0 0x1000>;
2548 2377
2549 cpu = <&CPU0>; 2378 cpu = <&CPU0>;
2550 2379
2551 clocks = <&aoss_qmp>; 2380 clocks = <&aoss_qmp>;
2552 clock-names = "apb_pc 2381 clock-names = "apb_pclk";
2553 arm,coresight-loses-c 2382 arm,coresight-loses-context-with-cpu;
2554 qcom,skip-power-up; 2383 qcom,skip-power-up;
2555 2384
2556 out-ports { 2385 out-ports {
2557 port { 2386 port {
2558 etm0_ 2387 etm0_out: endpoint {
2559 2388 remote-endpoint = <&apss_funnel_in0>;
2560 }; 2389 };
2561 }; 2390 };
2562 }; 2391 };
2563 }; 2392 };
2564 2393
2565 etm@7140000 { 2394 etm@7140000 {
2566 compatible = "arm,cor 2395 compatible = "arm,coresight-etm4x", "arm,primecell";
2567 reg = <0 0x07140000 0 2396 reg = <0 0x07140000 0 0x1000>;
2568 2397
2569 cpu = <&CPU1>; 2398 cpu = <&CPU1>;
2570 2399
2571 clocks = <&aoss_qmp>; 2400 clocks = <&aoss_qmp>;
2572 clock-names = "apb_pc 2401 clock-names = "apb_pclk";
2573 arm,coresight-loses-c 2402 arm,coresight-loses-context-with-cpu;
2574 qcom,skip-power-up; 2403 qcom,skip-power-up;
2575 2404
2576 out-ports { 2405 out-ports {
2577 port { 2406 port {
2578 etm1_ 2407 etm1_out: endpoint {
2579 2408 remote-endpoint = <&apss_funnel_in1>;
2580 }; 2409 };
2581 }; 2410 };
2582 }; 2411 };
2583 }; 2412 };
2584 2413
2585 etm@7240000 { 2414 etm@7240000 {
2586 compatible = "arm,cor 2415 compatible = "arm,coresight-etm4x", "arm,primecell";
2587 reg = <0 0x07240000 0 2416 reg = <0 0x07240000 0 0x1000>;
2588 2417
2589 cpu = <&CPU2>; 2418 cpu = <&CPU2>;
2590 2419
2591 clocks = <&aoss_qmp>; 2420 clocks = <&aoss_qmp>;
2592 clock-names = "apb_pc 2421 clock-names = "apb_pclk";
2593 arm,coresight-loses-c 2422 arm,coresight-loses-context-with-cpu;
2594 qcom,skip-power-up; 2423 qcom,skip-power-up;
2595 2424
2596 out-ports { 2425 out-ports {
2597 port { 2426 port {
2598 etm2_ 2427 etm2_out: endpoint {
2599 2428 remote-endpoint = <&apss_funnel_in2>;
2600 }; 2429 };
2601 }; 2430 };
2602 }; 2431 };
2603 }; 2432 };
2604 2433
2605 etm@7340000 { 2434 etm@7340000 {
2606 compatible = "arm,cor 2435 compatible = "arm,coresight-etm4x", "arm,primecell";
2607 reg = <0 0x07340000 0 2436 reg = <0 0x07340000 0 0x1000>;
2608 2437
2609 cpu = <&CPU3>; 2438 cpu = <&CPU3>;
2610 2439
2611 clocks = <&aoss_qmp>; 2440 clocks = <&aoss_qmp>;
2612 clock-names = "apb_pc 2441 clock-names = "apb_pclk";
2613 arm,coresight-loses-c 2442 arm,coresight-loses-context-with-cpu;
2614 qcom,skip-power-up; 2443 qcom,skip-power-up;
2615 2444
2616 out-ports { 2445 out-ports {
2617 port { 2446 port {
2618 etm3_ 2447 etm3_out: endpoint {
2619 2448 remote-endpoint = <&apss_funnel_in3>;
2620 }; 2449 };
2621 }; 2450 };
2622 }; 2451 };
2623 }; 2452 };
2624 2453
2625 etm@7440000 { 2454 etm@7440000 {
2626 compatible = "arm,cor 2455 compatible = "arm,coresight-etm4x", "arm,primecell";
2627 reg = <0 0x07440000 0 2456 reg = <0 0x07440000 0 0x1000>;
2628 2457
2629 cpu = <&CPU4>; 2458 cpu = <&CPU4>;
2630 2459
2631 clocks = <&aoss_qmp>; 2460 clocks = <&aoss_qmp>;
2632 clock-names = "apb_pc 2461 clock-names = "apb_pclk";
2633 arm,coresight-loses-c 2462 arm,coresight-loses-context-with-cpu;
2634 qcom,skip-power-up; 2463 qcom,skip-power-up;
2635 2464
2636 out-ports { 2465 out-ports {
2637 port { 2466 port {
2638 etm4_ 2467 etm4_out: endpoint {
2639 2468 remote-endpoint = <&apss_funnel_in4>;
2640 }; 2469 };
2641 }; 2470 };
2642 }; 2471 };
2643 }; 2472 };
2644 2473
2645 etm@7540000 { 2474 etm@7540000 {
2646 compatible = "arm,cor 2475 compatible = "arm,coresight-etm4x", "arm,primecell";
2647 reg = <0 0x07540000 0 2476 reg = <0 0x07540000 0 0x1000>;
2648 2477
2649 cpu = <&CPU5>; 2478 cpu = <&CPU5>;
2650 2479
2651 clocks = <&aoss_qmp>; 2480 clocks = <&aoss_qmp>;
2652 clock-names = "apb_pc 2481 clock-names = "apb_pclk";
2653 arm,coresight-loses-c 2482 arm,coresight-loses-context-with-cpu;
2654 qcom,skip-power-up; 2483 qcom,skip-power-up;
2655 2484
2656 out-ports { 2485 out-ports {
2657 port { 2486 port {
2658 etm5_ 2487 etm5_out: endpoint {
2659 2488 remote-endpoint = <&apss_funnel_in5>;
2660 }; 2489 };
2661 }; 2490 };
2662 }; 2491 };
2663 }; 2492 };
2664 2493
2665 etm@7640000 { 2494 etm@7640000 {
2666 compatible = "arm,cor 2495 compatible = "arm,coresight-etm4x", "arm,primecell";
2667 reg = <0 0x07640000 0 2496 reg = <0 0x07640000 0 0x1000>;
2668 2497
2669 cpu = <&CPU6>; 2498 cpu = <&CPU6>;
2670 2499
2671 clocks = <&aoss_qmp>; 2500 clocks = <&aoss_qmp>;
2672 clock-names = "apb_pc 2501 clock-names = "apb_pclk";
2673 arm,coresight-loses-c 2502 arm,coresight-loses-context-with-cpu;
2674 qcom,skip-power-up; 2503 qcom,skip-power-up;
2675 2504
2676 out-ports { 2505 out-ports {
2677 port { 2506 port {
2678 etm6_ 2507 etm6_out: endpoint {
2679 2508 remote-endpoint = <&apss_funnel_in6>;
2680 }; 2509 };
2681 }; 2510 };
2682 }; 2511 };
2683 }; 2512 };
2684 2513
2685 etm@7740000 { 2514 etm@7740000 {
2686 compatible = "arm,cor 2515 compatible = "arm,coresight-etm4x", "arm,primecell";
2687 reg = <0 0x07740000 0 2516 reg = <0 0x07740000 0 0x1000>;
2688 2517
2689 cpu = <&CPU7>; 2518 cpu = <&CPU7>;
2690 2519
2691 clocks = <&aoss_qmp>; 2520 clocks = <&aoss_qmp>;
2692 clock-names = "apb_pc 2521 clock-names = "apb_pclk";
2693 arm,coresight-loses-c 2522 arm,coresight-loses-context-with-cpu;
2694 qcom,skip-power-up; 2523 qcom,skip-power-up;
2695 2524
2696 out-ports { 2525 out-ports {
2697 port { 2526 port {
2698 etm7_ 2527 etm7_out: endpoint {
2699 2528 remote-endpoint = <&apss_funnel_in7>;
2700 }; 2529 };
2701 }; 2530 };
2702 }; 2531 };
2703 }; 2532 };
2704 2533
2705 funnel@7800000 { /* APSS Funn 2534 funnel@7800000 { /* APSS Funnel */
2706 compatible = "arm,cor 2535 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2707 reg = <0 0x07800000 0 2536 reg = <0 0x07800000 0 0x1000>;
2708 2537
2709 clocks = <&aoss_qmp>; 2538 clocks = <&aoss_qmp>;
2710 clock-names = "apb_pc 2539 clock-names = "apb_pclk";
2711 2540
2712 out-ports { 2541 out-ports {
2713 port { 2542 port {
2714 apss_ 2543 apss_funnel_out: endpoint {
2715 2544 remote-endpoint = <&apss_merge_funnel_in>;
2716 }; 2545 };
2717 }; 2546 };
2718 }; 2547 };
2719 2548
2720 in-ports { 2549 in-ports {
2721 #address-cell 2550 #address-cells = <1>;
2722 #size-cells = 2551 #size-cells = <0>;
2723 2552
2724 port@0 { 2553 port@0 {
2725 reg = 2554 reg = <0>;
2726 apss_ 2555 apss_funnel_in0: endpoint {
2727 2556 remote-endpoint = <&etm0_out>;
2728 }; 2557 };
2729 }; 2558 };
2730 2559
2731 port@1 { 2560 port@1 {
2732 reg = 2561 reg = <1>;
2733 apss_ 2562 apss_funnel_in1: endpoint {
2734 2563 remote-endpoint = <&etm1_out>;
2735 }; 2564 };
2736 }; 2565 };
2737 2566
2738 port@2 { 2567 port@2 {
2739 reg = 2568 reg = <2>;
2740 apss_ 2569 apss_funnel_in2: endpoint {
2741 2570 remote-endpoint = <&etm2_out>;
2742 }; 2571 };
2743 }; 2572 };
2744 2573
2745 port@3 { 2574 port@3 {
2746 reg = 2575 reg = <3>;
2747 apss_ 2576 apss_funnel_in3: endpoint {
2748 2577 remote-endpoint = <&etm3_out>;
2749 }; 2578 };
2750 }; 2579 };
2751 2580
2752 port@4 { 2581 port@4 {
2753 reg = 2582 reg = <4>;
2754 apss_ 2583 apss_funnel_in4: endpoint {
2755 2584 remote-endpoint = <&etm4_out>;
2756 }; 2585 };
2757 }; 2586 };
2758 2587
2759 port@5 { 2588 port@5 {
2760 reg = 2589 reg = <5>;
2761 apss_ 2590 apss_funnel_in5: endpoint {
2762 2591 remote-endpoint = <&etm5_out>;
2763 }; 2592 };
2764 }; 2593 };
2765 2594
2766 port@6 { 2595 port@6 {
2767 reg = 2596 reg = <6>;
2768 apss_ 2597 apss_funnel_in6: endpoint {
2769 2598 remote-endpoint = <&etm6_out>;
2770 }; 2599 };
2771 }; 2600 };
2772 2601
2773 port@7 { 2602 port@7 {
2774 reg = 2603 reg = <7>;
2775 apss_ 2604 apss_funnel_in7: endpoint {
2776 2605 remote-endpoint = <&etm7_out>;
2777 }; 2606 };
2778 }; 2607 };
2779 }; 2608 };
2780 }; 2609 };
2781 2610
2782 funnel@7810000 { 2611 funnel@7810000 {
2783 compatible = "arm,cor 2612 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2784 reg = <0 0x07810000 0 2613 reg = <0 0x07810000 0 0x1000>;
2785 2614
2786 clocks = <&aoss_qmp>; 2615 clocks = <&aoss_qmp>;
2787 clock-names = "apb_pc 2616 clock-names = "apb_pclk";
2788 2617
2789 out-ports { 2618 out-ports {
2790 port { 2619 port {
2791 apss_ 2620 apss_merge_funnel_out: endpoint {
2792 2621 remote-endpoint = <&funnel1_in4>;
2793 }; 2622 };
2794 }; 2623 };
2795 }; 2624 };
2796 2625
2797 in-ports { 2626 in-ports {
2798 port { 2627 port {
2799 apss_ 2628 apss_merge_funnel_in: endpoint {
2800 2629 remote-endpoint = <&apss_funnel_out>;
2801 }; 2630 };
2802 }; 2631 };
2803 }; 2632 };
2804 }; 2633 };
2805 2634
2806 sdhc_2: mmc@8804000 { 2635 sdhc_2: mmc@8804000 {
2807 compatible = "qcom,sc 2636 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
2808 reg = <0 0x08804000 0 2637 reg = <0 0x08804000 0 0x1000>;
2809 2638
2810 iommus = <&apps_smmu 2639 iommus = <&apps_smmu 0x80 0>;
2811 interrupts = <GIC_SPI 2640 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
2812 <GIC_ 2641 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
2813 interrupt-names = "hc 2642 interrupt-names = "hc_irq", "pwr_irq";
2814 2643
2815 clocks = <&gcc GCC_SD 2644 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2816 <&gcc GCC_SD 2645 <&gcc GCC_SDCC2_APPS_CLK>,
2817 <&rpmhcc RPM 2646 <&rpmhcc RPMH_CXO_CLK>;
2818 clock-names = "iface" 2647 clock-names = "iface", "core", "xo";
2819 2648
2820 interconnects = <&agg 2649 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
2821 <&gem 2650 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
2822 interconnect-names = 2651 interconnect-names = "sdhc-ddr","cpu-sdhc";
2823 power-domains = <&rpm 2652 power-domains = <&rpmhpd SC7180_CX>;
2824 operating-points-v2 = 2653 operating-points-v2 = <&sdhc2_opp_table>;
2825 2654
2826 bus-width = <4>; 2655 bus-width = <4>;
2827 2656
2828 status = "disabled"; 2657 status = "disabled";
2829 2658
2830 sdhc2_opp_table: opp- 2659 sdhc2_opp_table: opp-table {
2831 compatible = 2660 compatible = "operating-points-v2";
2832 2661
2833 opp-100000000 2662 opp-100000000 {
2834 opp-h 2663 opp-hz = /bits/ 64 <100000000>;
2835 requi 2664 required-opps = <&rpmhpd_opp_low_svs>;
2836 opp-p 2665 opp-peak-kBps = <1800000 600000>;
2837 opp-a 2666 opp-avg-kBps = <100000 0>;
2838 }; 2667 };
2839 2668
2840 opp-202000000 2669 opp-202000000 {
2841 opp-h 2670 opp-hz = /bits/ 64 <202000000>;
2842 requi 2671 required-opps = <&rpmhpd_opp_nom>;
2843 opp-p 2672 opp-peak-kBps = <5400000 1600000>;
2844 opp-a 2673 opp-avg-kBps = <200000 0>;
2845 }; 2674 };
2846 }; 2675 };
2847 }; 2676 };
2848 2677
2849 qspi: spi@88dc000 { 2678 qspi: spi@88dc000 {
2850 compatible = "qcom,sc 2679 compatible = "qcom,sc7180-qspi", "qcom,qspi-v1";
2851 reg = <0 0x088dc000 0 2680 reg = <0 0x088dc000 0 0x600>;
2852 iommus = <&apps_smmu <<
2853 #address-cells = <1>; 2681 #address-cells = <1>;
2854 #size-cells = <0>; 2682 #size-cells = <0>;
2855 interrupts = <GIC_SPI 2683 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
2856 clocks = <&gcc GCC_QS 2684 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
2857 <&gcc GCC_QS 2685 <&gcc GCC_QSPI_CORE_CLK>;
2858 clock-names = "iface" 2686 clock-names = "iface", "core";
2859 interconnects = <&gem 2687 interconnects = <&gem_noc MASTER_APPSS_PROC 0
2860 &conf 2688 &config_noc SLAVE_QSPI_0 0>;
2861 interconnect-names = 2689 interconnect-names = "qspi-config";
2862 power-domains = <&rpm 2690 power-domains = <&rpmhpd SC7180_CX>;
2863 operating-points-v2 = 2691 operating-points-v2 = <&qspi_opp_table>;
2864 status = "disabled"; 2692 status = "disabled";
2865 }; 2693 };
2866 2694
2867 usb_1_hsphy: phy@88e3000 { 2695 usb_1_hsphy: phy@88e3000 {
2868 compatible = "qcom,sc 2696 compatible = "qcom,sc7180-qusb2-phy", "qcom,qusb2-v2-phy";
2869 reg = <0 0x088e3000 0 2697 reg = <0 0x088e3000 0 0x400>;
2870 status = "disabled"; 2698 status = "disabled";
2871 #phy-cells = <0>; 2699 #phy-cells = <0>;
2872 clocks = <&gcc GCC_US 2700 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2873 <&rpmhcc RPM 2701 <&rpmhcc RPMH_CXO_CLK>;
2874 clock-names = "cfg_ah 2702 clock-names = "cfg_ahb", "ref";
2875 resets = <&gcc GCC_QU 2703 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2876 2704
2877 nvmem-cells = <&qusb2 2705 nvmem-cells = <&qusb2p_hstx_trim>;
2878 }; 2706 };
2879 2707
2880 usb_1_qmpphy: phy@88e8000 { !! 2708 usb_1_qmpphy: phy-wrapper@88e9000 {
2881 compatible = "qcom,sc 2709 compatible = "qcom,sc7180-qmp-usb3-dp-phy";
2882 reg = <0 0x088e8000 0 !! 2710 reg = <0 0x088e9000 0 0x18c>,
>> 2711 <0 0x088e8000 0 0x3c>,
>> 2712 <0 0x088ea000 0 0x18c>;
2883 status = "disabled"; 2713 status = "disabled";
>> 2714 #address-cells = <2>;
>> 2715 #size-cells = <2>;
>> 2716 ranges;
2884 2717
2885 clocks = <&gcc GCC_US 2718 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
>> 2719 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2886 <&gcc GCC_US 2720 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
2887 <&gcc GCC_US !! 2721 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
2888 <&gcc GCC_US !! 2722 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
2889 <&gcc GCC_US <<
2890 clock-names = "aux", <<
2891 "ref", <<
2892 "com_au <<
2893 "usb3_p <<
2894 "cfg_ah <<
2895 2723
2896 resets = <&gcc GCC_US 2724 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
2897 <&gcc GCC_US 2725 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
2898 reset-names = "phy", 2726 reset-names = "phy", "common";
2899 2727
2900 #clock-cells = <1>; !! 2728 usb_1_ssphy: usb3-phy@88e9200 {
2901 #phy-cells = <1>; !! 2729 reg = <0 0x088e9200 0 0x128>,
2902 }; !! 2730 <0 0x088e9400 0 0x200>,
2903 !! 2731 <0 0x088e9c00 0 0x218>,
2904 pmu@90b6300 { !! 2732 <0 0x088e9600 0 0x128>,
2905 compatible = "qcom,sc !! 2733 <0 0x088e9800 0 0x200>,
2906 reg = <0 0x090b6300 0 !! 2734 <0 0x088e9a00 0 0x18>;
2907 interrupts = <GIC_SPI !! 2735 #clock-cells = <0>;
2908 !! 2736 #phy-cells = <0>;
2909 interconnects = <&gem !! 2737 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2910 &gem !! 2738 clock-names = "pipe0";
2911 operating-points-v2 = !! 2739 clock-output-names = "usb3_phy_pipe_clk_src";
2912 <<
2913 cpu_bwmon_opp_table: <<
2914 compatible = <<
2915 <<
2916 opp-0 { <<
2917 opp-p <<
2918 }; <<
2919 <<
2920 opp-1 { <<
2921 opp-p <<
2922 }; <<
2923 <<
2924 opp-2 { <<
2925 opp-p <<
2926 }; <<
2927 <<
2928 opp-3 { <<
2929 opp-p <<
2930 }; <<
2931 <<
2932 opp-4 { <<
2933 opp-p <<
2934 }; <<
2935 <<
2936 opp-5 { <<
2937 opp-p <<
2938 }; <<
2939 }; 2740 };
2940 }; <<
2941 <<
2942 pmu@90cd000 { <<
2943 compatible = "qcom,sc <<
2944 reg = <0 0x090cd000 0 <<
2945 interrupts = <GIC_SPI <<
2946 <<
2947 interconnects = <&mc_ <<
2948 &mc_ <<
2949 operating-points-v2 = <<
2950 <<
2951 llcc_bwmon_opp_table: <<
2952 compatible = <<
2953 <<
2954 opp-0 { <<
2955 opp-p <<
2956 }; <<
2957 <<
2958 opp-1 { <<
2959 opp-p <<
2960 }; <<
2961 <<
2962 opp-2 { <<
2963 opp-p <<
2964 }; <<
2965 <<
2966 opp-3 { <<
2967 opp-p <<
2968 }; <<
2969 <<
2970 opp-4 { <<
2971 opp-p <<
2972 }; <<
2973 <<
2974 opp-5 { <<
2975 opp-p <<
2976 }; <<
2977 <<
2978 opp-6 { <<
2979 opp-p <<
2980 }; <<
2981 2741
2982 opp-7 { !! 2742 dp_phy: dp-phy@88ea200 {
2983 opp-p !! 2743 reg = <0 0x088ea200 0 0x200>,
2984 }; !! 2744 <0 0x088ea400 0 0x200>,
>> 2745 <0 0x088eaa00 0 0x200>,
>> 2746 <0 0x088ea600 0 0x200>,
>> 2747 <0 0x088ea800 0 0x200>;
>> 2748 #clock-cells = <1>;
>> 2749 #phy-cells = <0>;
2985 }; 2750 };
2986 }; 2751 };
2987 2752
2988 dc_noc: interconnect@9160000 2753 dc_noc: interconnect@9160000 {
2989 compatible = "qcom,sc 2754 compatible = "qcom,sc7180-dc-noc";
2990 reg = <0 0x09160000 0 2755 reg = <0 0x09160000 0 0x03200>;
2991 #interconnect-cells = 2756 #interconnect-cells = <2>;
2992 qcom,bcm-voters = <&a 2757 qcom,bcm-voters = <&apps_bcm_voter>;
2993 }; 2758 };
2994 2759
2995 system-cache-controller@92000 2760 system-cache-controller@9200000 {
2996 compatible = "qcom,sc 2761 compatible = "qcom,sc7180-llcc";
2997 reg = <0 0x09200000 0 2762 reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>;
2998 reg-names = "llcc0_ba !! 2763 reg-names = "llcc_base", "llcc_broadcast_base";
2999 interrupts = <GIC_SPI 2764 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
3000 }; 2765 };
3001 2766
3002 gem_noc: interconnect@9680000 2767 gem_noc: interconnect@9680000 {
3003 compatible = "qcom,sc 2768 compatible = "qcom,sc7180-gem-noc";
3004 reg = <0 0x09680000 0 2769 reg = <0 0x09680000 0 0x3e200>;
3005 #interconnect-cells = 2770 #interconnect-cells = <2>;
3006 qcom,bcm-voters = <&a 2771 qcom,bcm-voters = <&apps_bcm_voter>;
3007 }; 2772 };
3008 2773
3009 npu_noc: interconnect@9990000 2774 npu_noc: interconnect@9990000 {
3010 compatible = "qcom,sc 2775 compatible = "qcom,sc7180-npu-noc";
3011 reg = <0 0x09990000 0 2776 reg = <0 0x09990000 0 0x1600>;
3012 #interconnect-cells = 2777 #interconnect-cells = <2>;
3013 qcom,bcm-voters = <&a 2778 qcom,bcm-voters = <&apps_bcm_voter>;
3014 }; 2779 };
3015 2780
3016 usb_1: usb@a6f8800 { 2781 usb_1: usb@a6f8800 {
3017 compatible = "qcom,sc 2782 compatible = "qcom,sc7180-dwc3", "qcom,dwc3";
3018 reg = <0 0x0a6f8800 0 2783 reg = <0 0x0a6f8800 0 0x400>;
3019 status = "disabled"; 2784 status = "disabled";
3020 #address-cells = <2>; 2785 #address-cells = <2>;
3021 #size-cells = <2>; 2786 #size-cells = <2>;
3022 ranges; 2787 ranges;
3023 dma-ranges; 2788 dma-ranges;
3024 2789
3025 clocks = <&gcc GCC_CF 2790 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
3026 <&gcc GCC_US 2791 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
3027 <&gcc GCC_AG 2792 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
3028 <&gcc GCC_US 2793 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
3029 <&gcc GCC_US 2794 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
3030 clock-names = "cfg_no 2795 clock-names = "cfg_noc",
3031 "core", 2796 "core",
3032 "iface" 2797 "iface",
3033 "sleep" 2798 "sleep",
3034 "mock_u 2799 "mock_utmi";
3035 2800
3036 assigned-clocks = <&g 2801 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3037 <&g 2802 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
3038 assigned-clock-rates 2803 assigned-clock-rates = <19200000>, <150000000>;
3039 2804
3040 interrupts-extended = !! 2805 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
3041 !! 2806 <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
3042 !! 2807 <&pdc 8 IRQ_TYPE_LEVEL_HIGH>,
3043 !! 2808 <&pdc 9 IRQ_TYPE_LEVEL_HIGH>;
3044 !! 2809 interrupt-names = "hs_phy_irq", "ss_phy_irq",
3045 interrupt-names = "pw !! 2810 "dm_hs_phy_irq", "dp_hs_phy_irq";
3046 "hs <<
3047 "dp <<
3048 "dm <<
3049 "ss <<
3050 2811
3051 power-domains = <&gcc 2812 power-domains = <&gcc USB30_PRIM_GDSC>;
3052 required-opps = <&rpm 2813 required-opps = <&rpmhpd_opp_nom>;
3053 2814
3054 resets = <&gcc GCC_US 2815 resets = <&gcc GCC_USB30_PRIM_BCR>;
3055 2816
3056 interconnects = <&agg 2817 interconnects = <&aggre2_noc MASTER_USB3 0 &mc_virt SLAVE_EBI1 0>,
3057 <&gem 2818 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3 0>;
3058 interconnect-names = 2819 interconnect-names = "usb-ddr", "apps-usb";
3059 2820
3060 wakeup-source; 2821 wakeup-source;
3061 2822
3062 usb_1_dwc3: usb@a6000 2823 usb_1_dwc3: usb@a600000 {
3063 compatible = 2824 compatible = "snps,dwc3";
3064 reg = <0 0x0a 2825 reg = <0 0x0a600000 0 0xe000>;
3065 interrupts = 2826 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
3066 iommus = <&ap 2827 iommus = <&apps_smmu 0x540 0>;
3067 snps,dis_u2_s 2828 snps,dis_u2_susphy_quirk;
3068 snps,dis_enbl 2829 snps,dis_enblslpm_quirk;
3069 snps,parkmode !! 2830 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
3070 phys = <&usb_ <<
3071 phy-names = " 2831 phy-names = "usb2-phy", "usb3-phy";
3072 maximum-speed 2832 maximum-speed = "super-speed";
3073 }; 2833 };
3074 }; 2834 };
3075 2835
3076 venus: video-codec@aa00000 { 2836 venus: video-codec@aa00000 {
3077 compatible = "qcom,sc 2837 compatible = "qcom,sc7180-venus";
3078 reg = <0 0x0aa00000 0 2838 reg = <0 0x0aa00000 0 0xff000>;
3079 interrupts = <GIC_SPI 2839 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
3080 power-domains = <&vid 2840 power-domains = <&videocc VENUS_GDSC>,
3081 <&vid 2841 <&videocc VCODEC0_GDSC>,
3082 <&rpm 2842 <&rpmhpd SC7180_CX>;
3083 power-domain-names = 2843 power-domain-names = "venus", "vcodec0", "cx";
3084 operating-points-v2 = 2844 operating-points-v2 = <&venus_opp_table>;
3085 clocks = <&videocc VI 2845 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
3086 <&videocc VI 2846 <&videocc VIDEO_CC_VENUS_AHB_CLK>,
3087 <&videocc VI 2847 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>,
3088 <&videocc VI 2848 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
3089 <&videocc VI 2849 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>;
3090 clock-names = "core", 2850 clock-names = "core", "iface", "bus",
3091 "vcodec 2851 "vcodec0_core", "vcodec0_bus";
3092 iommus = <&apps_smmu 2852 iommus = <&apps_smmu 0x0c00 0x60>;
3093 memory-region = <&ven 2853 memory-region = <&venus_mem>;
3094 interconnects = <&mms 2854 interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>,
3095 <&gem 2855 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>;
3096 interconnect-names = 2856 interconnect-names = "video-mem", "cpu-cfg";
3097 2857
3098 video-decoder { 2858 video-decoder {
3099 compatible = 2859 compatible = "venus-decoder";
3100 }; 2860 };
3101 2861
3102 video-encoder { 2862 video-encoder {
3103 compatible = 2863 compatible = "venus-encoder";
3104 }; 2864 };
3105 2865
3106 venus_opp_table: opp- 2866 venus_opp_table: opp-table {
3107 compatible = 2867 compatible = "operating-points-v2";
3108 2868
3109 opp-150000000 2869 opp-150000000 {
3110 opp-h 2870 opp-hz = /bits/ 64 <150000000>;
3111 requi 2871 required-opps = <&rpmhpd_opp_low_svs>;
3112 }; 2872 };
3113 2873
3114 opp-270000000 2874 opp-270000000 {
3115 opp-h 2875 opp-hz = /bits/ 64 <270000000>;
3116 requi 2876 required-opps = <&rpmhpd_opp_svs>;
3117 }; 2877 };
3118 2878
3119 opp-340000000 2879 opp-340000000 {
3120 opp-h 2880 opp-hz = /bits/ 64 <340000000>;
3121 requi 2881 required-opps = <&rpmhpd_opp_svs_l1>;
3122 }; 2882 };
3123 2883
3124 opp-434000000 2884 opp-434000000 {
3125 opp-h 2885 opp-hz = /bits/ 64 <434000000>;
3126 requi 2886 required-opps = <&rpmhpd_opp_nom>;
3127 }; 2887 };
3128 2888
3129 opp-500000097 2889 opp-500000097 {
3130 opp-h 2890 opp-hz = /bits/ 64 <500000097>;
3131 requi 2891 required-opps = <&rpmhpd_opp_turbo>;
3132 }; 2892 };
3133 }; 2893 };
3134 }; 2894 };
3135 2895
3136 videocc: clock-controller@ab0 2896 videocc: clock-controller@ab00000 {
3137 compatible = "qcom,sc 2897 compatible = "qcom,sc7180-videocc";
3138 reg = <0 0x0ab00000 0 2898 reg = <0 0x0ab00000 0 0x10000>;
3139 clocks = <&rpmhcc RPM 2899 clocks = <&rpmhcc RPMH_CXO_CLK>;
3140 clock-names = "bi_tcx 2900 clock-names = "bi_tcxo";
3141 #clock-cells = <1>; 2901 #clock-cells = <1>;
3142 #reset-cells = <1>; 2902 #reset-cells = <1>;
3143 #power-domain-cells = 2903 #power-domain-cells = <1>;
3144 }; 2904 };
3145 2905
3146 camnoc_virt: interconnect@ac0 2906 camnoc_virt: interconnect@ac00000 {
3147 compatible = "qcom,sc 2907 compatible = "qcom,sc7180-camnoc-virt";
3148 reg = <0 0x0ac00000 0 2908 reg = <0 0x0ac00000 0 0x1000>;
3149 #interconnect-cells = 2909 #interconnect-cells = <2>;
3150 qcom,bcm-voters = <&a 2910 qcom,bcm-voters = <&apps_bcm_voter>;
3151 }; 2911 };
3152 2912
3153 camcc: clock-controller@ad000 2913 camcc: clock-controller@ad00000 {
3154 compatible = "qcom,sc 2914 compatible = "qcom,sc7180-camcc";
3155 reg = <0 0x0ad00000 0 2915 reg = <0 0x0ad00000 0 0x10000>;
3156 clocks = <&rpmhcc RPM 2916 clocks = <&rpmhcc RPMH_CXO_CLK>,
3157 <&gcc GCC_CAME 2917 <&gcc GCC_CAMERA_AHB_CLK>,
3158 <&gcc GCC_CAME 2918 <&gcc GCC_CAMERA_XO_CLK>;
3159 clock-names = "bi_tcx 2919 clock-names = "bi_tcxo", "iface", "xo";
3160 #clock-cells = <1>; 2920 #clock-cells = <1>;
3161 #reset-cells = <1>; 2921 #reset-cells = <1>;
3162 #power-domain-cells = 2922 #power-domain-cells = <1>;
3163 }; 2923 };
3164 2924
3165 mdss: display-subsystem@ae000 2925 mdss: display-subsystem@ae00000 {
3166 compatible = "qcom,sc 2926 compatible = "qcom,sc7180-mdss";
3167 reg = <0 0x0ae00000 0 2927 reg = <0 0x0ae00000 0 0x1000>;
3168 reg-names = "mdss"; 2928 reg-names = "mdss";
3169 2929
3170 power-domains = <&dis 2930 power-domains = <&dispcc MDSS_GDSC>;
3171 2931
3172 clocks = <&gcc GCC_DI 2932 clocks = <&gcc GCC_DISP_AHB_CLK>,
3173 <&dispcc DIS 2933 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3174 <&dispcc DIS 2934 <&dispcc DISP_CC_MDSS_MDP_CLK>;
3175 clock-names = "iface" 2935 clock-names = "iface", "ahb", "core";
3176 2936
3177 interrupts = <GIC_SPI 2937 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
3178 interrupt-controller; 2938 interrupt-controller;
3179 #interrupt-cells = <1 2939 #interrupt-cells = <1>;
3180 2940
3181 interconnects = <&mms !! 2941 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>;
3182 &mc_ !! 2942 interconnect-names = "mdp0-mem";
3183 <&gem <<
3184 &con <<
3185 interconnect-names = <<
3186 <<
3187 2943
3188 iommus = <&apps_smmu 2944 iommus = <&apps_smmu 0x800 0x2>;
3189 2945
3190 #address-cells = <2>; 2946 #address-cells = <2>;
3191 #size-cells = <2>; 2947 #size-cells = <2>;
3192 ranges; 2948 ranges;
3193 2949
3194 status = "disabled"; 2950 status = "disabled";
3195 2951
3196 mdp: display-controll 2952 mdp: display-controller@ae01000 {
3197 compatible = 2953 compatible = "qcom,sc7180-dpu";
3198 reg = <0 0x0a 2954 reg = <0 0x0ae01000 0 0x8f000>,
3199 <0 0x0a 2955 <0 0x0aeb0000 0 0x2008>;
3200 reg-names = " 2956 reg-names = "mdp", "vbif";
3201 2957
3202 clocks = <&gc 2958 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
3203 <&di 2959 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3204 <&di 2960 <&dispcc DISP_CC_MDSS_ROT_CLK>,
3205 <&di 2961 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
3206 <&di 2962 <&dispcc DISP_CC_MDSS_MDP_CLK>,
3207 <&di 2963 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3208 clock-names = 2964 clock-names = "bus", "iface", "rot", "lut", "core",
3209 2965 "vsync";
3210 assigned-cloc 2966 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
3211 2967 <&dispcc DISP_CC_MDSS_ROT_CLK>,
3212 2968 <&dispcc DISP_CC_MDSS_AHB_CLK>;
3213 assigned-cloc 2969 assigned-clock-rates = <19200000>,
3214 2970 <19200000>,
3215 2971 <19200000>;
3216 operating-poi 2972 operating-points-v2 = <&mdp_opp_table>;
3217 power-domains 2973 power-domains = <&rpmhpd SC7180_CX>;
3218 2974
3219 interrupt-par 2975 interrupt-parent = <&mdss>;
3220 interrupts = 2976 interrupts = <0>;
3221 2977
>> 2978 status = "disabled";
>> 2979
3222 ports { 2980 ports {
3223 #addr 2981 #address-cells = <1>;
3224 #size 2982 #size-cells = <0>;
3225 2983
3226 port@ 2984 port@0 {
3227 2985 reg = <0>;
3228 2986 dpu_intf1_out: endpoint {
3229 !! 2987 remote-endpoint = <&dsi0_in>;
3230 2988 };
3231 }; 2989 };
3232 2990
3233 port@ 2991 port@2 {
3234 2992 reg = <2>;
3235 2993 dpu_intf0_out: endpoint {
3236 2994 remote-endpoint = <&dp_in>;
3237 2995 };
3238 }; 2996 };
3239 }; 2997 };
3240 2998
3241 mdp_opp_table 2999 mdp_opp_table: opp-table {
3242 compa 3000 compatible = "operating-points-v2";
3243 3001
3244 opp-2 3002 opp-200000000 {
3245 3003 opp-hz = /bits/ 64 <200000000>;
3246 3004 required-opps = <&rpmhpd_opp_low_svs>;
3247 }; 3005 };
3248 3006
3249 opp-3 3007 opp-300000000 {
3250 3008 opp-hz = /bits/ 64 <300000000>;
3251 3009 required-opps = <&rpmhpd_opp_svs>;
3252 }; 3010 };
3253 3011
3254 opp-3 3012 opp-345000000 {
3255 3013 opp-hz = /bits/ 64 <345000000>;
3256 3014 required-opps = <&rpmhpd_opp_svs_l1>;
3257 }; 3015 };
3258 3016
3259 opp-4 3017 opp-460000000 {
3260 3018 opp-hz = /bits/ 64 <460000000>;
3261 3019 required-opps = <&rpmhpd_opp_nom>;
3262 }; 3020 };
3263 }; 3021 };
>> 3022
3264 }; 3023 };
3265 3024
3266 mdss_dsi0: dsi@ae9400 !! 3025 dsi0: dsi@ae94000 {
3267 compatible = 3026 compatible = "qcom,sc7180-dsi-ctrl",
3268 3027 "qcom,mdss-dsi-ctrl";
3269 reg = <0 0x0a 3028 reg = <0 0x0ae94000 0 0x400>;
3270 reg-names = " 3029 reg-names = "dsi_ctrl";
3271 3030
3272 interrupt-par 3031 interrupt-parent = <&mdss>;
3273 interrupts = 3032 interrupts = <4>;
3274 3033
3275 clocks = <&di 3034 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
3276 <&di 3035 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
3277 <&di 3036 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
3278 <&di 3037 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
3279 <&di 3038 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3280 <&gc 3039 <&gcc GCC_DISP_HF_AXI_CLK>;
3281 clock-names = 3040 clock-names = "byte",
3282 3041 "byte_intf",
3283 3042 "pixel",
3284 3043 "core",
3285 3044 "iface",
3286 3045 "bus";
3287 3046
3288 assigned-cloc 3047 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
3289 assigned-cloc !! 3048 assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>;
3290 3049
3291 operating-poi 3050 operating-points-v2 = <&dsi_opp_table>;
3292 power-domains 3051 power-domains = <&rpmhpd SC7180_CX>;
3293 3052
3294 phys = <&mdss !! 3053 phys = <&dsi_phy>;
3295 3054
3296 #address-cell 3055 #address-cells = <1>;
3297 #size-cells = 3056 #size-cells = <0>;
3298 3057
3299 status = "dis 3058 status = "disabled";
3300 3059
3301 ports { 3060 ports {
3302 #addr 3061 #address-cells = <1>;
3303 #size 3062 #size-cells = <0>;
3304 3063
3305 port@ 3064 port@0 {
3306 3065 reg = <0>;
3307 !! 3066 dsi0_in: endpoint {
3308 3067 remote-endpoint = <&dpu_intf1_out>;
3309 3068 };
3310 }; 3069 };
3311 3070
3312 port@ 3071 port@1 {
3313 3072 reg = <1>;
3314 !! 3073 dsi0_out: endpoint {
3315 3074 };
3316 }; 3075 };
3317 }; 3076 };
3318 3077
3319 dsi_opp_table 3078 dsi_opp_table: opp-table {
3320 compa 3079 compatible = "operating-points-v2";
3321 3080
3322 opp-1 3081 opp-187500000 {
3323 3082 opp-hz = /bits/ 64 <187500000>;
3324 3083 required-opps = <&rpmhpd_opp_low_svs>;
3325 }; 3084 };
3326 3085
3327 opp-3 3086 opp-300000000 {
3328 3087 opp-hz = /bits/ 64 <300000000>;
3329 3088 required-opps = <&rpmhpd_opp_svs>;
3330 }; 3089 };
3331 3090
3332 opp-3 3091 opp-358000000 {
3333 3092 opp-hz = /bits/ 64 <358000000>;
3334 3093 required-opps = <&rpmhpd_opp_svs_l1>;
3335 }; 3094 };
3336 }; 3095 };
3337 }; 3096 };
3338 3097
3339 mdss_dsi0_phy: phy@ae !! 3098 dsi_phy: phy@ae94400 {
3340 compatible = 3099 compatible = "qcom,dsi-phy-10nm";
3341 reg = <0 0x0a 3100 reg = <0 0x0ae94400 0 0x200>,
3342 <0 0x0a 3101 <0 0x0ae94600 0 0x280>,
3343 <0 0x0a 3102 <0 0x0ae94a00 0 0x1e0>;
3344 reg-names = " 3103 reg-names = "dsi_phy",
3345 " 3104 "dsi_phy_lane",
3346 " 3105 "dsi_pll";
3347 3106
3348 #clock-cells 3107 #clock-cells = <1>;
3349 #phy-cells = 3108 #phy-cells = <0>;
3350 3109
3351 clocks = <&di 3110 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3352 <&rp 3111 <&rpmhcc RPMH_CXO_CLK>;
3353 clock-names = 3112 clock-names = "iface", "ref";
3354 3113
3355 status = "dis 3114 status = "disabled";
3356 }; 3115 };
3357 3116
3358 mdss_dp: displayport- 3117 mdss_dp: displayport-controller@ae90000 {
3359 compatible = 3118 compatible = "qcom,sc7180-dp";
3360 status = "dis 3119 status = "disabled";
3361 3120
3362 reg = <0 0x0a 3121 reg = <0 0x0ae90000 0 0x200>,
3363 <0 0x0a 3122 <0 0x0ae90200 0 0x200>,
3364 <0 0x0a 3123 <0 0x0ae90400 0 0xc00>,
3365 <0 0x0a 3124 <0 0x0ae91000 0 0x400>,
3366 <0 0x0a 3125 <0 0x0ae91400 0 0x400>;
3367 3126
3368 interrupt-par 3127 interrupt-parent = <&mdss>;
3369 interrupts = 3128 interrupts = <12>;
3370 3129
3371 clocks = <&di 3130 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3372 <&di 3131 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
3373 <&di 3132 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
3374 <&di 3133 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
3375 <&di 3134 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
3376 clock-names = 3135 clock-names = "core_iface", "core_aux", "ctrl_link",
3377 3136 "ctrl_link_iface", "stream_pixel";
3378 assigned-cloc 3137 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
3379 3138 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
3380 assigned-cloc !! 3139 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
3381 !! 3140 phys = <&dp_phy>;
3382 phys = <&usb_ <<
3383 phy-names = " 3141 phy-names = "dp";
3384 3142
3385 operating-poi 3143 operating-points-v2 = <&dp_opp_table>;
3386 power-domains 3144 power-domains = <&rpmhpd SC7180_CX>;
3387 3145
3388 #sound-dai-ce 3146 #sound-dai-cells = <0>;
3389 3147
3390 ports { 3148 ports {
3391 #addr 3149 #address-cells = <1>;
3392 #size 3150 #size-cells = <0>;
3393 port@ 3151 port@0 {
3394 3152 reg = <0>;
3395 3153 dp_in: endpoint {
3396 3154 remote-endpoint = <&dpu_intf0_out>;
3397 3155 };
3398 }; 3156 };
3399 3157
3400 port@ 3158 port@1 {
3401 3159 reg = <1>;
3402 3160 mdss_dp_out: endpoint { };
3403 }; 3161 };
3404 }; 3162 };
3405 3163
3406 dp_opp_table: 3164 dp_opp_table: opp-table {
3407 compa 3165 compatible = "operating-points-v2";
3408 3166
3409 opp-1 3167 opp-160000000 {
3410 3168 opp-hz = /bits/ 64 <160000000>;
3411 3169 required-opps = <&rpmhpd_opp_low_svs>;
3412 }; 3170 };
3413 3171
3414 opp-2 3172 opp-270000000 {
3415 3173 opp-hz = /bits/ 64 <270000000>;
3416 3174 required-opps = <&rpmhpd_opp_svs>;
3417 }; 3175 };
3418 3176
3419 opp-5 3177 opp-540000000 {
3420 3178 opp-hz = /bits/ 64 <540000000>;
3421 3179 required-opps = <&rpmhpd_opp_svs_l1>;
3422 }; 3180 };
3423 3181
3424 opp-8 3182 opp-810000000 {
3425 3183 opp-hz = /bits/ 64 <810000000>;
3426 3184 required-opps = <&rpmhpd_opp_nom>;
3427 }; 3185 };
3428 }; 3186 };
3429 }; 3187 };
3430 }; 3188 };
3431 3189
3432 dispcc: clock-controller@af00 3190 dispcc: clock-controller@af00000 {
3433 compatible = "qcom,sc 3191 compatible = "qcom,sc7180-dispcc";
3434 reg = <0 0x0af00000 0 3192 reg = <0 0x0af00000 0 0x200000>;
3435 clocks = <&rpmhcc RPM 3193 clocks = <&rpmhcc RPMH_CXO_CLK>,
3436 <&gcc GCC_DI 3194 <&gcc GCC_DISP_GPLL0_CLK_SRC>,
3437 <&mdss_dsi0_ !! 3195 <&dsi_phy 0>,
3438 <&mdss_dsi0_ !! 3196 <&dsi_phy 1>,
3439 <&usb_1_qmpp !! 3197 <&dp_phy 0>,
3440 <&usb_1_qmpp !! 3198 <&dp_phy 1>;
3441 clock-names = "bi_tcx 3199 clock-names = "bi_tcxo",
3442 "gcc_di 3200 "gcc_disp_gpll0_clk_src",
3443 "dsi0_p 3201 "dsi0_phy_pll_out_byteclk",
3444 "dsi0_p 3202 "dsi0_phy_pll_out_dsiclk",
3445 "dp_phy 3203 "dp_phy_pll_link_clk",
3446 "dp_phy 3204 "dp_phy_pll_vco_div_clk";
3447 #clock-cells = <1>; 3205 #clock-cells = <1>;
3448 #reset-cells = <1>; 3206 #reset-cells = <1>;
3449 #power-domain-cells = 3207 #power-domain-cells = <1>;
3450 }; 3208 };
3451 3209
3452 pdc: interrupt-controller@b22 3210 pdc: interrupt-controller@b220000 {
3453 compatible = "qcom,sc 3211 compatible = "qcom,sc7180-pdc", "qcom,pdc";
3454 reg = <0 0x0b220000 0 3212 reg = <0 0x0b220000 0 0x30000>;
3455 qcom,pdc-ranges = <0 3213 qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>;
3456 #interrupt-cells = <2 3214 #interrupt-cells = <2>;
3457 interrupt-parent = <& 3215 interrupt-parent = <&intc>;
3458 interrupt-controller; 3216 interrupt-controller;
3459 }; 3217 };
3460 3218
3461 pdc_reset: reset-controller@b 3219 pdc_reset: reset-controller@b2e0000 {
3462 compatible = "qcom,sc 3220 compatible = "qcom,sc7180-pdc-global", "qcom,sdm845-pdc-global";
3463 reg = <0 0x0b2e0000 0 3221 reg = <0 0x0b2e0000 0 0x20000>;
3464 #reset-cells = <1>; 3222 #reset-cells = <1>;
3465 }; 3223 };
3466 3224
3467 tsens0: thermal-sensor@c26300 3225 tsens0: thermal-sensor@c263000 {
3468 compatible = "qcom,sc 3226 compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
3469 reg = <0 0x0c263000 0 3227 reg = <0 0x0c263000 0 0x1ff>, /* TM */
3470 <0 0x0c222000 3228 <0 0x0c222000 0 0x1ff>; /* SROT */
3471 #qcom,sensors = <15>; 3229 #qcom,sensors = <15>;
3472 interrupts = <GIC_SPI 3230 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
3473 <GIC_SPI 3231 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
3474 interrupt-names = "up 3232 interrupt-names = "uplow","critical";
3475 #thermal-sensor-cells 3233 #thermal-sensor-cells = <1>;
3476 }; 3234 };
3477 3235
3478 tsens1: thermal-sensor@c26500 3236 tsens1: thermal-sensor@c265000 {
3479 compatible = "qcom,sc 3237 compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
3480 reg = <0 0x0c265000 0 3238 reg = <0 0x0c265000 0 0x1ff>, /* TM */
3481 <0 0x0c223000 3239 <0 0x0c223000 0 0x1ff>; /* SROT */
3482 #qcom,sensors = <10>; 3240 #qcom,sensors = <10>;
3483 interrupts = <GIC_SPI 3241 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
3484 <GIC_SPI 3242 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
3485 interrupt-names = "up 3243 interrupt-names = "uplow","critical";
3486 #thermal-sensor-cells 3244 #thermal-sensor-cells = <1>;
3487 }; 3245 };
3488 3246
3489 aoss_reset: reset-controller@ 3247 aoss_reset: reset-controller@c2a0000 {
3490 compatible = "qcom,sc 3248 compatible = "qcom,sc7180-aoss-cc", "qcom,sdm845-aoss-cc";
3491 reg = <0 0x0c2a0000 0 3249 reg = <0 0x0c2a0000 0 0x31000>;
3492 #reset-cells = <1>; 3250 #reset-cells = <1>;
3493 }; 3251 };
3494 3252
3495 aoss_qmp: power-management@c3 3253 aoss_qmp: power-management@c300000 {
3496 compatible = "qcom,sc 3254 compatible = "qcom,sc7180-aoss-qmp", "qcom,aoss-qmp";
3497 reg = <0 0x0c300000 0 3255 reg = <0 0x0c300000 0 0x400>;
3498 interrupts = <GIC_SPI 3256 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
3499 mboxes = <&apss_share 3257 mboxes = <&apss_shared 0>;
3500 3258
3501 #clock-cells = <0>; 3259 #clock-cells = <0>;
3502 }; 3260 };
3503 3261
3504 sram@c3f0000 { 3262 sram@c3f0000 {
3505 compatible = "qcom,rp 3263 compatible = "qcom,rpmh-stats";
3506 reg = <0 0x0c3f0000 0 3264 reg = <0 0x0c3f0000 0 0x400>;
3507 }; 3265 };
3508 3266
3509 spmi_bus: spmi@c440000 { 3267 spmi_bus: spmi@c440000 {
3510 compatible = "qcom,sp 3268 compatible = "qcom,spmi-pmic-arb";
3511 reg = <0 0x0c440000 0 3269 reg = <0 0x0c440000 0 0x1100>,
3512 <0 0x0c600000 0 3270 <0 0x0c600000 0 0x2000000>,
3513 <0 0x0e600000 0 3271 <0 0x0e600000 0 0x100000>,
3514 <0 0x0e700000 0 3272 <0 0x0e700000 0 0xa0000>,
3515 <0 0x0c40a000 0 3273 <0 0x0c40a000 0 0x26000>;
3516 reg-names = "core", " 3274 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3517 interrupt-names = "pe 3275 interrupt-names = "periph_irq";
3518 interrupts-extended = 3276 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3519 qcom,ee = <0>; 3277 qcom,ee = <0>;
3520 qcom,channel = <0>; 3278 qcom,channel = <0>;
3521 #address-cells = <2>; 3279 #address-cells = <2>;
3522 #size-cells = <0>; 3280 #size-cells = <0>;
3523 interrupt-controller; 3281 interrupt-controller;
3524 #interrupt-cells = <4 3282 #interrupt-cells = <4>;
>> 3283 cell-index = <0>;
3525 }; 3284 };
3526 3285
3527 sram@146aa000 { 3286 sram@146aa000 {
3528 compatible = "qcom,sc 3287 compatible = "qcom,sc7180-imem", "syscon", "simple-mfd";
3529 reg = <0 0x146aa000 0 3288 reg = <0 0x146aa000 0 0x2000>;
3530 3289
3531 #address-cells = <1>; 3290 #address-cells = <1>;
3532 #size-cells = <1>; 3291 #size-cells = <1>;
3533 3292
3534 ranges = <0 0 0x146aa 3293 ranges = <0 0 0x146aa000 0x2000>;
3535 3294
3536 pil-reloc@94c { 3295 pil-reloc@94c {
3537 compatible = 3296 compatible = "qcom,pil-reloc-info";
3538 reg = <0x94c 3297 reg = <0x94c 0xc8>;
3539 }; 3298 };
3540 }; 3299 };
3541 3300
3542 apps_smmu: iommu@15000000 { 3301 apps_smmu: iommu@15000000 {
3543 compatible = "qcom,sc 3302 compatible = "qcom,sc7180-smmu-500", "arm,mmu-500";
3544 reg = <0 0x15000000 0 3303 reg = <0 0x15000000 0 0x100000>;
3545 #iommu-cells = <2>; 3304 #iommu-cells = <2>;
3546 #global-interrupts = 3305 #global-interrupts = <1>;
3547 interrupts = <GIC_SPI 3306 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
3548 <GIC_SPI 3307 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
3549 <GIC_SPI 3308 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
3550 <GIC_SPI 3309 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
3551 <GIC_SPI 3310 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
3552 <GIC_SPI 3311 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
3553 <GIC_SPI 3312 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
3554 <GIC_SPI 3313 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
3555 <GIC_SPI 3314 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
3556 <GIC_SPI 3315 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
3557 <GIC_SPI 3316 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
3558 <GIC_SPI 3317 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
3559 <GIC_SPI 3318 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
3560 <GIC_SPI 3319 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
3561 <GIC_SPI 3320 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
3562 <GIC_SPI 3321 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
3563 <GIC_SPI 3322 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
3564 <GIC_SPI 3323 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
3565 <GIC_SPI 3324 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
3566 <GIC_SPI 3325 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
3567 <GIC_SPI 3326 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
3568 <GIC_SPI 3327 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
3569 <GIC_SPI 3328 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
3570 <GIC_SPI 3329 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
3571 <GIC_SPI 3330 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
3572 <GIC_SPI 3331 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
3573 <GIC_SPI 3332 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
3574 <GIC_SPI 3333 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
3575 <GIC_SPI 3334 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
3576 <GIC_SPI 3335 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
3577 <GIC_SPI 3336 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
3578 <GIC_SPI 3337 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
3579 <GIC_SPI 3338 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
3580 <GIC_SPI 3339 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
3581 <GIC_SPI 3340 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
3582 <GIC_SPI 3341 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
3583 <GIC_SPI 3342 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
3584 <GIC_SPI 3343 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
3585 <GIC_SPI 3344 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
3586 <GIC_SPI 3345 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
3587 <GIC_SPI 3346 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
3588 <GIC_SPI 3347 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
3589 <GIC_SPI 3348 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
3590 <GIC_SPI 3349 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
3591 <GIC_SPI 3350 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
3592 <GIC_SPI 3351 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
3593 <GIC_SPI 3352 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
3594 <GIC_SPI 3353 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
3595 <GIC_SPI 3354 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
3596 <GIC_SPI 3355 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
3597 <GIC_SPI 3356 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
3598 <GIC_SPI 3357 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
3599 <GIC_SPI 3358 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
3600 <GIC_SPI 3359 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
3601 <GIC_SPI 3360 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
3602 <GIC_SPI 3361 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
3603 <GIC_SPI 3362 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
3604 <GIC_SPI 3363 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
3605 <GIC_SPI 3364 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
3606 <GIC_SPI 3365 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
3607 <GIC_SPI 3366 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
3608 <GIC_SPI 3367 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
3609 <GIC_SPI 3368 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
3610 <GIC_SPI 3369 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
3611 <GIC_SPI 3370 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
3612 <GIC_SPI 3371 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
3613 <GIC_SPI 3372 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
3614 <GIC_SPI 3373 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
3615 <GIC_SPI 3374 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
3616 <GIC_SPI 3375 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
3617 <GIC_SPI 3376 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
3618 <GIC_SPI 3377 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
3619 <GIC_SPI 3378 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
3620 <GIC_SPI 3379 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
3621 <GIC_SPI 3380 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
3622 <GIC_SPI 3381 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
3623 <GIC_SPI 3382 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
3624 <GIC_SPI 3383 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
3625 <GIC_SPI 3384 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
3626 <GIC_SPI 3385 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
3627 <GIC_SPI 3386 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
3628 }; 3387 };
3629 3388
3630 intc: interrupt-controller@17 3389 intc: interrupt-controller@17a00000 {
3631 compatible = "arm,gic 3390 compatible = "arm,gic-v3";
3632 #address-cells = <2>; 3391 #address-cells = <2>;
3633 #size-cells = <2>; 3392 #size-cells = <2>;
3634 ranges; 3393 ranges;
3635 #interrupt-cells = <3 3394 #interrupt-cells = <3>;
3636 interrupt-controller; 3395 interrupt-controller;
3637 reg = <0 0x17a00000 0 3396 reg = <0 0x17a00000 0 0x10000>, /* GICD */
3638 <0 0x17a60000 0 3397 <0 0x17a60000 0 0x100000>; /* GICR * 8 */
3639 interrupts = <GIC_PPI 3398 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3640 3399
3641 msi-controller@17a400 3400 msi-controller@17a40000 {
3642 compatible = 3401 compatible = "arm,gic-v3-its";
3643 msi-controlle 3402 msi-controller;
3644 #msi-cells = 3403 #msi-cells = <1>;
3645 reg = <0 0x17 3404 reg = <0 0x17a40000 0 0x20000>;
3646 status = "dis 3405 status = "disabled";
3647 }; 3406 };
3648 }; 3407 };
3649 3408
3650 apss_shared: mailbox@17c00000 3409 apss_shared: mailbox@17c00000 {
3651 compatible = "qcom,sc !! 3410 compatible = "qcom,sc7180-apss-shared";
3652 "qcom,sd <<
3653 reg = <0 0x17c00000 0 3411 reg = <0 0x17c00000 0 0x10000>;
3654 #mbox-cells = <1>; 3412 #mbox-cells = <1>;
3655 }; 3413 };
3656 3414
3657 watchdog@17c10000 { 3415 watchdog@17c10000 {
3658 compatible = "qcom,ap 3416 compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt";
3659 reg = <0 0x17c10000 0 3417 reg = <0 0x17c10000 0 0x1000>;
3660 clocks = <&sleep_clk> 3418 clocks = <&sleep_clk>;
3661 interrupts = <GIC_SPI !! 3419 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
3662 }; 3420 };
3663 3421
3664 timer@17c20000 { 3422 timer@17c20000 {
3665 #address-cells = <1>; 3423 #address-cells = <1>;
3666 #size-cells = <1>; 3424 #size-cells = <1>;
3667 ranges = <0 0 0 0x200 3425 ranges = <0 0 0 0x20000000>;
3668 compatible = "arm,arm 3426 compatible = "arm,armv7-timer-mem";
3669 reg = <0 0x17c20000 0 3427 reg = <0 0x17c20000 0 0x1000>;
3670 3428
3671 frame@17c21000 { 3429 frame@17c21000 {
3672 frame-number 3430 frame-number = <0>;
3673 interrupts = 3431 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
3674 3432 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
3675 reg = <0x17c2 3433 reg = <0x17c21000 0x1000>,
3676 <0x17c2 3434 <0x17c22000 0x1000>;
3677 }; 3435 };
3678 3436
3679 frame@17c23000 { 3437 frame@17c23000 {
3680 frame-number 3438 frame-number = <1>;
3681 interrupts = 3439 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
3682 reg = <0x17c2 3440 reg = <0x17c23000 0x1000>;
3683 status = "dis 3441 status = "disabled";
3684 }; 3442 };
3685 3443
3686 frame@17c25000 { 3444 frame@17c25000 {
3687 frame-number 3445 frame-number = <2>;
3688 interrupts = 3446 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
3689 reg = <0x17c2 3447 reg = <0x17c25000 0x1000>;
3690 status = "dis 3448 status = "disabled";
3691 }; 3449 };
3692 3450
3693 frame@17c27000 { 3451 frame@17c27000 {
3694 frame-number 3452 frame-number = <3>;
3695 interrupts = 3453 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3696 reg = <0x17c2 3454 reg = <0x17c27000 0x1000>;
3697 status = "dis 3455 status = "disabled";
3698 }; 3456 };
3699 3457
3700 frame@17c29000 { 3458 frame@17c29000 {
3701 frame-number 3459 frame-number = <4>;
3702 interrupts = 3460 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3703 reg = <0x17c2 3461 reg = <0x17c29000 0x1000>;
3704 status = "dis 3462 status = "disabled";
3705 }; 3463 };
3706 3464
3707 frame@17c2b000 { 3465 frame@17c2b000 {
3708 frame-number 3466 frame-number = <5>;
3709 interrupts = 3467 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3710 reg = <0x17c2 3468 reg = <0x17c2b000 0x1000>;
3711 status = "dis 3469 status = "disabled";
3712 }; 3470 };
3713 3471
3714 frame@17c2d000 { 3472 frame@17c2d000 {
3715 frame-number 3473 frame-number = <6>;
3716 interrupts = 3474 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
3717 reg = <0x17c2 3475 reg = <0x17c2d000 0x1000>;
3718 status = "dis 3476 status = "disabled";
3719 }; 3477 };
3720 }; 3478 };
3721 3479
3722 apps_rsc: rsc@18200000 { 3480 apps_rsc: rsc@18200000 {
3723 compatible = "qcom,rp 3481 compatible = "qcom,rpmh-rsc";
3724 reg = <0 0x18200000 0 3482 reg = <0 0x18200000 0 0x10000>,
3725 <0 0x18210000 0 3483 <0 0x18210000 0 0x10000>,
3726 <0 0x18220000 0 3484 <0 0x18220000 0 0x10000>;
3727 reg-names = "drv-0", 3485 reg-names = "drv-0", "drv-1", "drv-2";
3728 interrupts = <GIC_SPI 3486 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
3729 <GIC_SPI 3487 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
3730 <GIC_SPI 3488 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
3731 qcom,tcs-offset = <0x 3489 qcom,tcs-offset = <0xd00>;
3732 qcom,drv-id = <2>; 3490 qcom,drv-id = <2>;
3733 qcom,tcs-config = <AC 3491 qcom,tcs-config = <ACTIVE_TCS 2>,
3734 <SL 3492 <SLEEP_TCS 3>,
3735 <WA 3493 <WAKE_TCS 3>,
3736 <CO 3494 <CONTROL_TCS 1>;
3737 power-domains = <&CLU <<
3738 3495
3739 rpmhcc: clock-control 3496 rpmhcc: clock-controller {
3740 compatible = 3497 compatible = "qcom,sc7180-rpmh-clk";
3741 clocks = <&xo 3498 clocks = <&xo_board>;
3742 clock-names = 3499 clock-names = "xo";
3743 #clock-cells 3500 #clock-cells = <1>;
3744 }; 3501 };
3745 3502
3746 rpmhpd: power-control 3503 rpmhpd: power-controller {
3747 compatible = 3504 compatible = "qcom,sc7180-rpmhpd";
3748 #power-domain 3505 #power-domain-cells = <1>;
3749 operating-poi 3506 operating-points-v2 = <&rpmhpd_opp_table>;
3750 3507
3751 rpmhpd_opp_ta 3508 rpmhpd_opp_table: opp-table {
3752 compa 3509 compatible = "operating-points-v2";
3753 3510
3754 rpmhp 3511 rpmhpd_opp_ret: opp1 {
3755 3512 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3756 }; 3513 };
3757 3514
3758 rpmhp 3515 rpmhpd_opp_min_svs: opp2 {
3759 3516 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3760 }; 3517 };
3761 3518
3762 rpmhp 3519 rpmhpd_opp_low_svs: opp3 {
3763 3520 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3764 }; 3521 };
3765 3522
3766 rpmhp 3523 rpmhpd_opp_svs: opp4 {
3767 3524 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3768 }; 3525 };
3769 3526
3770 rpmhp 3527 rpmhpd_opp_svs_l1: opp5 {
3771 3528 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3772 }; 3529 };
3773 3530
3774 rpmhp 3531 rpmhpd_opp_svs_l2: opp6 {
3775 3532 opp-level = <224>;
3776 }; 3533 };
3777 3534
3778 rpmhp 3535 rpmhpd_opp_nom: opp7 {
3779 3536 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3780 }; 3537 };
3781 3538
3782 rpmhp 3539 rpmhpd_opp_nom_l1: opp8 {
3783 3540 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3784 }; 3541 };
3785 3542
3786 rpmhp 3543 rpmhpd_opp_nom_l2: opp9 {
3787 3544 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3788 }; 3545 };
3789 3546
3790 rpmhp 3547 rpmhpd_opp_turbo: opp10 {
3791 3548 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3792 }; 3549 };
3793 3550
3794 rpmhp 3551 rpmhpd_opp_turbo_l1: opp11 {
3795 3552 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3796 }; 3553 };
3797 }; 3554 };
3798 }; 3555 };
3799 3556
3800 apps_bcm_voter: bcm-v 3557 apps_bcm_voter: bcm-voter {
3801 compatible = 3558 compatible = "qcom,bcm-voter";
3802 }; 3559 };
3803 }; 3560 };
3804 3561
3805 osm_l3: interconnect@18321000 3562 osm_l3: interconnect@18321000 {
3806 compatible = "qcom,sc 3563 compatible = "qcom,sc7180-osm-l3", "qcom,osm-l3";
3807 reg = <0 0x18321000 0 3564 reg = <0 0x18321000 0 0x1400>;
3808 3565
3809 clocks = <&rpmhcc RPM 3566 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3810 clock-names = "xo", " 3567 clock-names = "xo", "alternate";
3811 3568
3812 #interconnect-cells = 3569 #interconnect-cells = <1>;
3813 }; 3570 };
3814 3571
3815 cpufreq_hw: cpufreq@18323000 3572 cpufreq_hw: cpufreq@18323000 {
3816 compatible = "qcom,sc !! 3573 compatible = "qcom,cpufreq-hw";
3817 reg = <0 0x18323000 0 3574 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>;
3818 reg-names = "freq-dom 3575 reg-names = "freq-domain0", "freq-domain1";
3819 3576
3820 clocks = <&rpmhcc RPM 3577 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3821 clock-names = "xo", " 3578 clock-names = "xo", "alternate";
3822 3579
3823 #freq-domain-cells = 3580 #freq-domain-cells = <1>;
3824 #clock-cells = <1>; <<
3825 }; 3581 };
3826 3582
3827 wifi: wifi@18800000 { 3583 wifi: wifi@18800000 {
3828 compatible = "qcom,wc 3584 compatible = "qcom,wcn3990-wifi";
3829 reg = <0 0x18800000 0 3585 reg = <0 0x18800000 0 0x800000>;
3830 reg-names = "membase" 3586 reg-names = "membase";
3831 iommus = <&apps_smmu 3587 iommus = <&apps_smmu 0xc0 0x1>;
3832 interrupts = 3588 interrupts =
3833 <GIC_SPI 414 3589 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH /* CE0 */ >,
3834 <GIC_SPI 415 3590 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH /* CE1 */ >,
3835 <GIC_SPI 416 3591 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH /* CE2 */ >,
3836 <GIC_SPI 417 3592 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH /* CE3 */ >,
3837 <GIC_SPI 418 3593 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH /* CE4 */ >,
3838 <GIC_SPI 419 3594 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH /* CE5 */ >,
3839 <GIC_SPI 420 3595 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH /* CE6 */ >,
3840 <GIC_SPI 421 3596 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH /* CE7 */ >,
3841 <GIC_SPI 422 3597 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH /* CE8 */ >,
3842 <GIC_SPI 423 3598 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH /* CE9 */ >,
3843 <GIC_SPI 424 3599 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH /* CE10 */>,
3844 <GIC_SPI 425 3600 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH /* CE11 */>;
3845 memory-region = <&wla 3601 memory-region = <&wlan_mem>;
3846 qcom,msa-fixed-perm; 3602 qcom,msa-fixed-perm;
3847 status = "disabled"; 3603 status = "disabled";
3848 }; 3604 };
3849 3605
3850 remoteproc_adsp: remoteproc@6 <<
3851 compatible = "qcom,sc <<
3852 reg = <0 0x62400000 0 <<
3853 <<
3854 interrupts-extended = <<
3855 <<
3856 <<
3857 <<
3858 <<
3859 interrupt-names = "wd <<
3860 "fa <<
3861 "re <<
3862 "ha <<
3863 "st <<
3864 <<
3865 clocks = <&rpmhcc RPM <<
3866 clock-names = "xo"; <<
3867 <<
3868 power-domains = <&rpm <<
3869 <&rpm <<
3870 power-domain-names = <<
3871 <<
3872 qcom,qmp = <&aoss_qmp <<
3873 qcom,smem-states = <& <<
3874 qcom,smem-state-names <<
3875 <<
3876 status = "disabled"; <<
3877 <<
3878 glink-edge { <<
3879 interrupts = <<
3880 label = "lpas <<
3881 qcom,remote-p <<
3882 mboxes = <&ap <<
3883 <<
3884 apr { <<
3885 compa <<
3886 qcom, <<
3887 qcom, <<
3888 #addr <<
3889 #size <<
3890 <<
3891 servi <<
3892 <<
3893 <<
3894 <<
3895 }; <<
3896 <<
3897 q6afe <<
3898 <<
3899 <<
3900 <<
3901 <<
3902 <<
3903 <<
3904 <<
3905 <<
3906 <<
3907 <<
3908 <<
3909 <<
3910 <<
3911 <<
3912 <<
3913 }; <<
3914 <<
3915 q6asm <<
3916 <<
3917 <<
3918 <<
3919 <<
3920 <<
3921 <<
3922 <<
3923 <<
3924 <<
3925 <<
3926 <<
3927 }; <<
3928 <<
3929 q6adm <<
3930 <<
3931 <<
3932 <<
3933 <<
3934 <<
3935 <<
3936 <<
3937 <<
3938 }; <<
3939 }; <<
3940 <<
3941 fastrpc { <<
3942 compa <<
3943 qcom, <<
3944 label <<
3945 #addr <<
3946 #size <<
3947 <<
3948 compu <<
3949 <<
3950 <<
3951 <<
3952 }; <<
3953 <<
3954 compu <<
3955 <<
3956 <<
3957 <<
3958 }; <<
3959 <<
3960 compu <<
3961 <<
3962 <<
3963 <<
3964 <<
3965 }; <<
3966 }; <<
3967 }; <<
3968 }; <<
3969 <<
3970 lpasscc: clock-controller@62d 3606 lpasscc: clock-controller@62d00000 {
3971 compatible = "qcom,sc 3607 compatible = "qcom,sc7180-lpasscorecc";
3972 reg = <0 0x62d00000 0 3608 reg = <0 0x62d00000 0 0x50000>,
3973 <0 0x62780000 0 3609 <0 0x62780000 0 0x30000>;
3974 reg-names = "lpass_co 3610 reg-names = "lpass_core_cc", "lpass_audio_cc";
3975 clocks = <&gcc GCC_LP 3611 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>,
3976 <&rpmhcc RPM 3612 <&rpmhcc RPMH_CXO_CLK>;
3977 clock-names = "iface" 3613 clock-names = "iface", "bi_tcxo";
3978 power-domains = <&lpa 3614 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>;
3979 #clock-cells = <1>; 3615 #clock-cells = <1>;
3980 #power-domain-cells = 3616 #power-domain-cells = <1>;
3981 <<
3982 status = "reserved"; <<
3983 }; 3617 };
3984 3618
3985 lpass_cpu: lpass@62d87000 { 3619 lpass_cpu: lpass@62d87000 {
3986 compatible = "qcom,sc 3620 compatible = "qcom,sc7180-lpass-cpu";
3987 3621
3988 reg = <0 0x62d87000 0 3622 reg = <0 0x62d87000 0 0x68000>, <0 0x62f00000 0 0x29000>;
3989 reg-names = "lpass-hd 3623 reg-names = "lpass-hdmiif", "lpass-lpaif";
3990 3624
3991 iommus = <&apps_smmu 3625 iommus = <&apps_smmu 0x1020 0>,
3992 <&apps_smmu 0 3626 <&apps_smmu 0x1021 0>,
3993 <&apps_smmu 0 3627 <&apps_smmu 0x1032 0>;
3994 3628
3995 power-domains = <&lpa 3629 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>;
3996 required-opps = <&rpm 3630 required-opps = <&rpmhpd_opp_nom>;
3997 3631
3998 status = "disabled"; 3632 status = "disabled";
3999 3633
4000 clocks = <&gcc GCC_LP 3634 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>,
4001 <&lpasscc LP 3635 <&lpasscc LPASS_AUDIO_CORE_CORE_CLK>,
4002 <&lpasscc LP 3636 <&lpasscc LPASS_AUDIO_CORE_EXT_MCLK0_CLK>,
4003 <&lpasscc LP 3637 <&lpasscc LPASS_AUDIO_CORE_SYSNOC_MPORT_CORE_CLK>,
4004 <&lpasscc LP 3638 <&lpasscc LPASS_AUDIO_CORE_LPAIF_PRI_IBIT_CLK>,
4005 <&lpasscc LP 3639 <&lpasscc LPASS_AUDIO_CORE_LPAIF_SEC_IBIT_CLK>;
4006 3640
4007 clock-names = "pcnoc- 3641 clock-names = "pcnoc-sway-clk", "audio-core",
4008 "mclk 3642 "mclk0", "pcnoc-mport-clk",
4009 "mi2s 3643 "mi2s-bit-clk0", "mi2s-bit-clk1";
4010 3644
4011 3645
4012 #sound-dai-cells = <1 3646 #sound-dai-cells = <1>;
4013 #address-cells = <1>; 3647 #address-cells = <1>;
4014 #size-cells = <0>; 3648 #size-cells = <0>;
4015 3649
4016 interrupts = <GIC_SPI 3650 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
4017 <GIC_ 3651 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
4018 interrupt-names = "lp 3652 interrupt-names = "lpass-irq-lpaif", "lpass-irq-hdmi";
4019 }; 3653 };
4020 3654
4021 lpass_hm: clock-controller@63 3655 lpass_hm: clock-controller@63000000 {
4022 compatible = "qcom,sc 3656 compatible = "qcom,sc7180-lpasshm";
4023 reg = <0 0x63000000 0 3657 reg = <0 0x63000000 0 0x28>;
4024 clocks = <&gcc GCC_LP 3658 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>,
4025 <&rpmhcc RPM 3659 <&rpmhcc RPMH_CXO_CLK>;
4026 clock-names = "iface" 3660 clock-names = "iface", "bi_tcxo";
4027 power-domains = <&rpm 3661 power-domains = <&rpmhpd SC7180_CX>;
4028 3662
4029 #clock-cells = <1>; 3663 #clock-cells = <1>;
4030 #power-domain-cells = 3664 #power-domain-cells = <1>;
4031 <<
4032 status = "reserved"; <<
4033 }; 3665 };
4034 }; 3666 };
4035 3667
4036 thermal-zones { 3668 thermal-zones {
4037 cpu0_thermal: cpu0-thermal { 3669 cpu0_thermal: cpu0-thermal {
4038 polling-delay-passive 3670 polling-delay-passive = <250>;
>> 3671 polling-delay = <0>;
4039 3672
4040 thermal-sensors = <&t 3673 thermal-sensors = <&tsens0 1>;
4041 sustainable-power = < 3674 sustainable-power = <1052>;
4042 3675
4043 trips { 3676 trips {
4044 cpu0_alert0: 3677 cpu0_alert0: trip-point0 {
4045 tempe 3678 temperature = <90000>;
4046 hyste 3679 hysteresis = <2000>;
4047 type 3680 type = "passive";
4048 }; 3681 };
4049 3682
4050 cpu0_alert1: 3683 cpu0_alert1: trip-point1 {
4051 tempe 3684 temperature = <95000>;
4052 hyste 3685 hysteresis = <2000>;
4053 type 3686 type = "passive";
4054 }; 3687 };
4055 3688
4056 cpu0_crit: cp 3689 cpu0_crit: cpu-crit {
4057 tempe 3690 temperature = <110000>;
4058 hyste 3691 hysteresis = <1000>;
4059 type 3692 type = "critical";
4060 }; 3693 };
4061 }; 3694 };
4062 3695
4063 cooling-maps { 3696 cooling-maps {
4064 map0 { 3697 map0 {
4065 trip 3698 trip = <&cpu0_alert0>;
4066 cooli 3699 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4067 3700 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4068 3701 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4069 3702 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4070 3703 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4071 3704 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4072 }; 3705 };
4073 map1 { 3706 map1 {
4074 trip 3707 trip = <&cpu0_alert1>;
4075 cooli 3708 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4076 3709 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4077 3710 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4078 3711 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4079 3712 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4080 3713 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4081 }; 3714 };
4082 }; 3715 };
4083 }; 3716 };
4084 3717
4085 cpu1_thermal: cpu1-thermal { 3718 cpu1_thermal: cpu1-thermal {
4086 polling-delay-passive 3719 polling-delay-passive = <250>;
>> 3720 polling-delay = <0>;
4087 3721
4088 thermal-sensors = <&t 3722 thermal-sensors = <&tsens0 2>;
4089 sustainable-power = < 3723 sustainable-power = <1052>;
4090 3724
4091 trips { 3725 trips {
4092 cpu1_alert0: 3726 cpu1_alert0: trip-point0 {
4093 tempe 3727 temperature = <90000>;
4094 hyste 3728 hysteresis = <2000>;
4095 type 3729 type = "passive";
4096 }; 3730 };
4097 3731
4098 cpu1_alert1: 3732 cpu1_alert1: trip-point1 {
4099 tempe 3733 temperature = <95000>;
4100 hyste 3734 hysteresis = <2000>;
4101 type 3735 type = "passive";
4102 }; 3736 };
4103 3737
4104 cpu1_crit: cp 3738 cpu1_crit: cpu-crit {
4105 tempe 3739 temperature = <110000>;
4106 hyste 3740 hysteresis = <1000>;
4107 type 3741 type = "critical";
4108 }; 3742 };
4109 }; 3743 };
4110 3744
4111 cooling-maps { 3745 cooling-maps {
4112 map0 { 3746 map0 {
4113 trip 3747 trip = <&cpu1_alert0>;
4114 cooli 3748 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4115 3749 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4116 3750 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4117 3751 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4118 3752 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4119 3753 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4120 }; 3754 };
4121 map1 { 3755 map1 {
4122 trip 3756 trip = <&cpu1_alert1>;
4123 cooli 3757 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4124 3758 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4125 3759 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4126 3760 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4127 3761 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4128 3762 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4129 }; 3763 };
4130 }; 3764 };
4131 }; 3765 };
4132 3766
4133 cpu2_thermal: cpu2-thermal { 3767 cpu2_thermal: cpu2-thermal {
4134 polling-delay-passive 3768 polling-delay-passive = <250>;
>> 3769 polling-delay = <0>;
4135 3770
4136 thermal-sensors = <&t 3771 thermal-sensors = <&tsens0 3>;
4137 sustainable-power = < 3772 sustainable-power = <1052>;
4138 3773
4139 trips { 3774 trips {
4140 cpu2_alert0: 3775 cpu2_alert0: trip-point0 {
4141 tempe 3776 temperature = <90000>;
4142 hyste 3777 hysteresis = <2000>;
4143 type 3778 type = "passive";
4144 }; 3779 };
4145 3780
4146 cpu2_alert1: 3781 cpu2_alert1: trip-point1 {
4147 tempe 3782 temperature = <95000>;
4148 hyste 3783 hysteresis = <2000>;
4149 type 3784 type = "passive";
4150 }; 3785 };
4151 3786
4152 cpu2_crit: cp 3787 cpu2_crit: cpu-crit {
4153 tempe 3788 temperature = <110000>;
4154 hyste 3789 hysteresis = <1000>;
4155 type 3790 type = "critical";
4156 }; 3791 };
4157 }; 3792 };
4158 3793
4159 cooling-maps { 3794 cooling-maps {
4160 map0 { 3795 map0 {
4161 trip 3796 trip = <&cpu2_alert0>;
4162 cooli 3797 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4163 3798 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4164 3799 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4165 3800 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4166 3801 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4167 3802 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4168 }; 3803 };
4169 map1 { 3804 map1 {
4170 trip 3805 trip = <&cpu2_alert1>;
4171 cooli 3806 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4172 3807 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4173 3808 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4174 3809 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4175 3810 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4176 3811 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4177 }; 3812 };
4178 }; 3813 };
4179 }; 3814 };
4180 3815
4181 cpu3_thermal: cpu3-thermal { 3816 cpu3_thermal: cpu3-thermal {
4182 polling-delay-passive 3817 polling-delay-passive = <250>;
>> 3818 polling-delay = <0>;
4183 3819
4184 thermal-sensors = <&t 3820 thermal-sensors = <&tsens0 4>;
4185 sustainable-power = < 3821 sustainable-power = <1052>;
4186 3822
4187 trips { 3823 trips {
4188 cpu3_alert0: 3824 cpu3_alert0: trip-point0 {
4189 tempe 3825 temperature = <90000>;
4190 hyste 3826 hysteresis = <2000>;
4191 type 3827 type = "passive";
4192 }; 3828 };
4193 3829
4194 cpu3_alert1: 3830 cpu3_alert1: trip-point1 {
4195 tempe 3831 temperature = <95000>;
4196 hyste 3832 hysteresis = <2000>;
4197 type 3833 type = "passive";
4198 }; 3834 };
4199 3835
4200 cpu3_crit: cp 3836 cpu3_crit: cpu-crit {
4201 tempe 3837 temperature = <110000>;
4202 hyste 3838 hysteresis = <1000>;
4203 type 3839 type = "critical";
4204 }; 3840 };
4205 }; 3841 };
4206 3842
4207 cooling-maps { 3843 cooling-maps {
4208 map0 { 3844 map0 {
4209 trip 3845 trip = <&cpu3_alert0>;
4210 cooli 3846 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4211 3847 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4212 3848 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4213 3849 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4214 3850 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4215 3851 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4216 }; 3852 };
4217 map1 { 3853 map1 {
4218 trip 3854 trip = <&cpu3_alert1>;
4219 cooli 3855 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4220 3856 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4221 3857 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4222 3858 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4223 3859 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4224 3860 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4225 }; 3861 };
4226 }; 3862 };
4227 }; 3863 };
4228 3864
4229 cpu4_thermal: cpu4-thermal { 3865 cpu4_thermal: cpu4-thermal {
4230 polling-delay-passive 3866 polling-delay-passive = <250>;
>> 3867 polling-delay = <0>;
4231 3868
4232 thermal-sensors = <&t 3869 thermal-sensors = <&tsens0 5>;
4233 sustainable-power = < 3870 sustainable-power = <1052>;
4234 3871
4235 trips { 3872 trips {
4236 cpu4_alert0: 3873 cpu4_alert0: trip-point0 {
4237 tempe 3874 temperature = <90000>;
4238 hyste 3875 hysteresis = <2000>;
4239 type 3876 type = "passive";
4240 }; 3877 };
4241 3878
4242 cpu4_alert1: 3879 cpu4_alert1: trip-point1 {
4243 tempe 3880 temperature = <95000>;
4244 hyste 3881 hysteresis = <2000>;
4245 type 3882 type = "passive";
4246 }; 3883 };
4247 3884
4248 cpu4_crit: cp 3885 cpu4_crit: cpu-crit {
4249 tempe 3886 temperature = <110000>;
4250 hyste 3887 hysteresis = <1000>;
4251 type 3888 type = "critical";
4252 }; 3889 };
4253 }; 3890 };
4254 3891
4255 cooling-maps { 3892 cooling-maps {
4256 map0 { 3893 map0 {
4257 trip 3894 trip = <&cpu4_alert0>;
4258 cooli 3895 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4259 3896 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4260 3897 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4261 3898 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4262 3899 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4263 3900 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4264 }; 3901 };
4265 map1 { 3902 map1 {
4266 trip 3903 trip = <&cpu4_alert1>;
4267 cooli 3904 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4268 3905 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4269 3906 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4270 3907 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4271 3908 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4272 3909 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4273 }; 3910 };
4274 }; 3911 };
4275 }; 3912 };
4276 3913
4277 cpu5_thermal: cpu5-thermal { 3914 cpu5_thermal: cpu5-thermal {
4278 polling-delay-passive 3915 polling-delay-passive = <250>;
>> 3916 polling-delay = <0>;
4279 3917
4280 thermal-sensors = <&t 3918 thermal-sensors = <&tsens0 6>;
4281 sustainable-power = < 3919 sustainable-power = <1052>;
4282 3920
4283 trips { 3921 trips {
4284 cpu5_alert0: 3922 cpu5_alert0: trip-point0 {
4285 tempe 3923 temperature = <90000>;
4286 hyste 3924 hysteresis = <2000>;
4287 type 3925 type = "passive";
4288 }; 3926 };
4289 3927
4290 cpu5_alert1: 3928 cpu5_alert1: trip-point1 {
4291 tempe 3929 temperature = <95000>;
4292 hyste 3930 hysteresis = <2000>;
4293 type 3931 type = "passive";
4294 }; 3932 };
4295 3933
4296 cpu5_crit: cp 3934 cpu5_crit: cpu-crit {
4297 tempe 3935 temperature = <110000>;
4298 hyste 3936 hysteresis = <1000>;
4299 type 3937 type = "critical";
4300 }; 3938 };
4301 }; 3939 };
4302 3940
4303 cooling-maps { 3941 cooling-maps {
4304 map0 { 3942 map0 {
4305 trip 3943 trip = <&cpu5_alert0>;
4306 cooli 3944 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4307 3945 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4308 3946 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4309 3947 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4310 3948 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4311 3949 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4312 }; 3950 };
4313 map1 { 3951 map1 {
4314 trip 3952 trip = <&cpu5_alert1>;
4315 cooli 3953 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4316 3954 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4317 3955 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4318 3956 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4319 3957 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4320 3958 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4321 }; 3959 };
4322 }; 3960 };
4323 }; 3961 };
4324 3962
4325 cpu6_thermal: cpu6-thermal { 3963 cpu6_thermal: cpu6-thermal {
4326 polling-delay-passive 3964 polling-delay-passive = <250>;
>> 3965 polling-delay = <0>;
4327 3966
4328 thermal-sensors = <&t 3967 thermal-sensors = <&tsens0 9>;
4329 sustainable-power = < 3968 sustainable-power = <1425>;
4330 3969
4331 trips { 3970 trips {
4332 cpu6_alert0: 3971 cpu6_alert0: trip-point0 {
4333 tempe 3972 temperature = <90000>;
4334 hyste 3973 hysteresis = <2000>;
4335 type 3974 type = "passive";
4336 }; 3975 };
4337 3976
4338 cpu6_alert1: 3977 cpu6_alert1: trip-point1 {
4339 tempe 3978 temperature = <95000>;
4340 hyste 3979 hysteresis = <2000>;
4341 type 3980 type = "passive";
4342 }; 3981 };
4343 3982
4344 cpu6_crit: cp 3983 cpu6_crit: cpu-crit {
4345 tempe 3984 temperature = <110000>;
4346 hyste 3985 hysteresis = <1000>;
4347 type 3986 type = "critical";
4348 }; 3987 };
4349 }; 3988 };
4350 3989
4351 cooling-maps { 3990 cooling-maps {
4352 map0 { 3991 map0 {
4353 trip 3992 trip = <&cpu6_alert0>;
4354 cooli 3993 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4355 3994 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4356 }; 3995 };
4357 map1 { 3996 map1 {
4358 trip 3997 trip = <&cpu6_alert1>;
4359 cooli 3998 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4360 3999 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4361 }; 4000 };
4362 }; 4001 };
4363 }; 4002 };
4364 4003
4365 cpu7_thermal: cpu7-thermal { 4004 cpu7_thermal: cpu7-thermal {
4366 polling-delay-passive 4005 polling-delay-passive = <250>;
>> 4006 polling-delay = <0>;
4367 4007
4368 thermal-sensors = <&t 4008 thermal-sensors = <&tsens0 10>;
4369 sustainable-power = < 4009 sustainable-power = <1425>;
4370 4010
4371 trips { 4011 trips {
4372 cpu7_alert0: 4012 cpu7_alert0: trip-point0 {
4373 tempe 4013 temperature = <90000>;
4374 hyste 4014 hysteresis = <2000>;
4375 type 4015 type = "passive";
4376 }; 4016 };
4377 4017
4378 cpu7_alert1: 4018 cpu7_alert1: trip-point1 {
4379 tempe 4019 temperature = <95000>;
4380 hyste 4020 hysteresis = <2000>;
4381 type 4021 type = "passive";
4382 }; 4022 };
4383 4023
4384 cpu7_crit: cp 4024 cpu7_crit: cpu-crit {
4385 tempe 4025 temperature = <110000>;
4386 hyste 4026 hysteresis = <1000>;
4387 type 4027 type = "critical";
4388 }; 4028 };
4389 }; 4029 };
4390 4030
4391 cooling-maps { 4031 cooling-maps {
4392 map0 { 4032 map0 {
4393 trip 4033 trip = <&cpu7_alert0>;
4394 cooli 4034 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4395 4035 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4396 }; 4036 };
4397 map1 { 4037 map1 {
4398 trip 4038 trip = <&cpu7_alert1>;
4399 cooli 4039 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4400 4040 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4401 }; 4041 };
4402 }; 4042 };
4403 }; 4043 };
4404 4044
4405 cpu8_thermal: cpu8-thermal { 4045 cpu8_thermal: cpu8-thermal {
4406 polling-delay-passive 4046 polling-delay-passive = <250>;
>> 4047 polling-delay = <0>;
4407 4048
4408 thermal-sensors = <&t 4049 thermal-sensors = <&tsens0 11>;
4409 sustainable-power = < 4050 sustainable-power = <1425>;
4410 4051
4411 trips { 4052 trips {
4412 cpu8_alert0: 4053 cpu8_alert0: trip-point0 {
4413 tempe 4054 temperature = <90000>;
4414 hyste 4055 hysteresis = <2000>;
4415 type 4056 type = "passive";
4416 }; 4057 };
4417 4058
4418 cpu8_alert1: 4059 cpu8_alert1: trip-point1 {
4419 tempe 4060 temperature = <95000>;
4420 hyste 4061 hysteresis = <2000>;
4421 type 4062 type = "passive";
4422 }; 4063 };
4423 4064
4424 cpu8_crit: cp 4065 cpu8_crit: cpu-crit {
4425 tempe 4066 temperature = <110000>;
4426 hyste 4067 hysteresis = <1000>;
4427 type 4068 type = "critical";
4428 }; 4069 };
4429 }; 4070 };
4430 4071
4431 cooling-maps { 4072 cooling-maps {
4432 map0 { 4073 map0 {
4433 trip 4074 trip = <&cpu8_alert0>;
4434 cooli 4075 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4435 4076 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4436 }; 4077 };
4437 map1 { 4078 map1 {
4438 trip 4079 trip = <&cpu8_alert1>;
4439 cooli 4080 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4440 4081 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4441 }; 4082 };
4442 }; 4083 };
4443 }; 4084 };
4444 4085
4445 cpu9_thermal: cpu9-thermal { 4086 cpu9_thermal: cpu9-thermal {
4446 polling-delay-passive 4087 polling-delay-passive = <250>;
>> 4088 polling-delay = <0>;
4447 4089
4448 thermal-sensors = <&t 4090 thermal-sensors = <&tsens0 12>;
4449 sustainable-power = < 4091 sustainable-power = <1425>;
4450 4092
4451 trips { 4093 trips {
4452 cpu9_alert0: 4094 cpu9_alert0: trip-point0 {
4453 tempe 4095 temperature = <90000>;
4454 hyste 4096 hysteresis = <2000>;
4455 type 4097 type = "passive";
4456 }; 4098 };
4457 4099
4458 cpu9_alert1: 4100 cpu9_alert1: trip-point1 {
4459 tempe 4101 temperature = <95000>;
4460 hyste 4102 hysteresis = <2000>;
4461 type 4103 type = "passive";
4462 }; 4104 };
4463 4105
4464 cpu9_crit: cp 4106 cpu9_crit: cpu-crit {
4465 tempe 4107 temperature = <110000>;
4466 hyste 4108 hysteresis = <1000>;
4467 type 4109 type = "critical";
4468 }; 4110 };
4469 }; 4111 };
4470 4112
4471 cooling-maps { 4113 cooling-maps {
4472 map0 { 4114 map0 {
4473 trip 4115 trip = <&cpu9_alert0>;
4474 cooli 4116 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4475 4117 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4476 }; 4118 };
4477 map1 { 4119 map1 {
4478 trip 4120 trip = <&cpu9_alert1>;
4479 cooli 4121 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4480 4122 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4481 }; 4123 };
4482 }; 4124 };
4483 }; 4125 };
4484 4126
4485 aoss0-thermal { 4127 aoss0-thermal {
4486 polling-delay-passive 4128 polling-delay-passive = <250>;
>> 4129 polling-delay = <0>;
4487 4130
4488 thermal-sensors = <&t 4131 thermal-sensors = <&tsens0 0>;
4489 4132
4490 trips { 4133 trips {
4491 aoss0_alert0: 4134 aoss0_alert0: trip-point0 {
4492 tempe 4135 temperature = <90000>;
4493 hyste 4136 hysteresis = <2000>;
4494 type 4137 type = "hot";
4495 }; 4138 };
4496 4139
4497 aoss0_crit: a 4140 aoss0_crit: aoss0-crit {
4498 tempe 4141 temperature = <110000>;
4499 hyste 4142 hysteresis = <2000>;
4500 type 4143 type = "critical";
4501 }; 4144 };
4502 }; 4145 };
4503 }; 4146 };
4504 4147
4505 cpuss0-thermal { 4148 cpuss0-thermal {
4506 polling-delay-passive 4149 polling-delay-passive = <250>;
>> 4150 polling-delay = <0>;
4507 4151
4508 thermal-sensors = <&t 4152 thermal-sensors = <&tsens0 7>;
4509 4153
4510 trips { 4154 trips {
4511 cpuss0_alert0 4155 cpuss0_alert0: trip-point0 {
4512 tempe 4156 temperature = <90000>;
4513 hyste 4157 hysteresis = <2000>;
4514 type 4158 type = "hot";
4515 }; 4159 };
4516 cpuss0_crit: 4160 cpuss0_crit: cluster0-crit {
4517 tempe 4161 temperature = <110000>;
4518 hyste 4162 hysteresis = <2000>;
4519 type 4163 type = "critical";
4520 }; 4164 };
4521 }; 4165 };
4522 }; 4166 };
4523 4167
4524 cpuss1-thermal { 4168 cpuss1-thermal {
4525 polling-delay-passive 4169 polling-delay-passive = <250>;
>> 4170 polling-delay = <0>;
4526 4171
4527 thermal-sensors = <&t 4172 thermal-sensors = <&tsens0 8>;
4528 4173
4529 trips { 4174 trips {
4530 cpuss1_alert0 4175 cpuss1_alert0: trip-point0 {
4531 tempe 4176 temperature = <90000>;
4532 hyste 4177 hysteresis = <2000>;
4533 type 4178 type = "hot";
4534 }; 4179 };
4535 cpuss1_crit: 4180 cpuss1_crit: cluster0-crit {
4536 tempe 4181 temperature = <110000>;
4537 hyste 4182 hysteresis = <2000>;
4538 type 4183 type = "critical";
4539 }; 4184 };
4540 }; 4185 };
4541 }; 4186 };
4542 4187
4543 gpuss0-thermal { 4188 gpuss0-thermal {
4544 polling-delay-passive 4189 polling-delay-passive = <250>;
>> 4190 polling-delay = <0>;
4545 4191
4546 thermal-sensors = <&t 4192 thermal-sensors = <&tsens0 13>;
4547 4193
4548 trips { 4194 trips {
4549 gpuss0_alert0 4195 gpuss0_alert0: trip-point0 {
4550 tempe 4196 temperature = <95000>;
4551 hyste 4197 hysteresis = <2000>;
4552 type 4198 type = "passive";
4553 }; 4199 };
4554 4200
4555 gpuss0_crit: 4201 gpuss0_crit: gpuss0-crit {
4556 tempe 4202 temperature = <110000>;
4557 hyste 4203 hysteresis = <2000>;
4558 type 4204 type = "critical";
4559 }; 4205 };
4560 }; 4206 };
4561 4207
4562 cooling-maps { 4208 cooling-maps {
4563 map0 { 4209 map0 {
4564 trip 4210 trip = <&gpuss0_alert0>;
4565 cooli 4211 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4566 }; 4212 };
4567 }; 4213 };
4568 }; 4214 };
4569 4215
4570 gpuss1-thermal { 4216 gpuss1-thermal {
4571 polling-delay-passive 4217 polling-delay-passive = <250>;
>> 4218 polling-delay = <0>;
4572 4219
4573 thermal-sensors = <&t 4220 thermal-sensors = <&tsens0 14>;
4574 4221
4575 trips { 4222 trips {
4576 gpuss1_alert0 4223 gpuss1_alert0: trip-point0 {
4577 tempe 4224 temperature = <95000>;
4578 hyste 4225 hysteresis = <2000>;
4579 type 4226 type = "passive";
4580 }; 4227 };
4581 4228
4582 gpuss1_crit: 4229 gpuss1_crit: gpuss1-crit {
4583 tempe 4230 temperature = <110000>;
4584 hyste 4231 hysteresis = <2000>;
4585 type 4232 type = "critical";
4586 }; 4233 };
4587 }; 4234 };
4588 4235
4589 cooling-maps { 4236 cooling-maps {
4590 map0 { 4237 map0 {
4591 trip 4238 trip = <&gpuss1_alert0>;
4592 cooli 4239 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4593 }; 4240 };
4594 }; 4241 };
4595 }; 4242 };
4596 4243
4597 aoss1-thermal { 4244 aoss1-thermal {
4598 polling-delay-passive 4245 polling-delay-passive = <250>;
>> 4246 polling-delay = <0>;
4599 4247
4600 thermal-sensors = <&t 4248 thermal-sensors = <&tsens1 0>;
4601 4249
4602 trips { 4250 trips {
4603 aoss1_alert0: 4251 aoss1_alert0: trip-point0 {
4604 tempe 4252 temperature = <90000>;
4605 hyste 4253 hysteresis = <2000>;
4606 type 4254 type = "hot";
4607 }; 4255 };
4608 4256
4609 aoss1_crit: a 4257 aoss1_crit: aoss1-crit {
4610 tempe 4258 temperature = <110000>;
4611 hyste 4259 hysteresis = <2000>;
4612 type 4260 type = "critical";
4613 }; 4261 };
4614 }; 4262 };
4615 }; 4263 };
4616 4264
4617 cwlan-thermal { 4265 cwlan-thermal {
4618 polling-delay-passive 4266 polling-delay-passive = <250>;
>> 4267 polling-delay = <0>;
4619 4268
4620 thermal-sensors = <&t 4269 thermal-sensors = <&tsens1 1>;
4621 4270
4622 trips { 4271 trips {
4623 cwlan_alert0: 4272 cwlan_alert0: trip-point0 {
4624 tempe 4273 temperature = <90000>;
4625 hyste 4274 hysteresis = <2000>;
4626 type 4275 type = "hot";
4627 }; 4276 };
4628 4277
4629 cwlan_crit: c 4278 cwlan_crit: cwlan-crit {
4630 tempe 4279 temperature = <110000>;
4631 hyste 4280 hysteresis = <2000>;
4632 type 4281 type = "critical";
4633 }; 4282 };
4634 }; 4283 };
4635 }; 4284 };
4636 4285
4637 audio-thermal { 4286 audio-thermal {
4638 polling-delay-passive 4287 polling-delay-passive = <250>;
>> 4288 polling-delay = <0>;
4639 4289
4640 thermal-sensors = <&t 4290 thermal-sensors = <&tsens1 2>;
4641 4291
4642 trips { 4292 trips {
4643 audio_alert0: 4293 audio_alert0: trip-point0 {
4644 tempe 4294 temperature = <90000>;
4645 hyste 4295 hysteresis = <2000>;
4646 type 4296 type = "hot";
4647 }; 4297 };
4648 4298
4649 audio_crit: a 4299 audio_crit: audio-crit {
4650 tempe 4300 temperature = <110000>;
4651 hyste 4301 hysteresis = <2000>;
4652 type 4302 type = "critical";
4653 }; 4303 };
4654 }; 4304 };
4655 }; 4305 };
4656 4306
4657 ddr-thermal { 4307 ddr-thermal {
4658 polling-delay-passive 4308 polling-delay-passive = <250>;
>> 4309 polling-delay = <0>;
4659 4310
4660 thermal-sensors = <&t 4311 thermal-sensors = <&tsens1 3>;
4661 4312
4662 trips { 4313 trips {
4663 ddr_alert0: t 4314 ddr_alert0: trip-point0 {
4664 tempe 4315 temperature = <90000>;
4665 hyste 4316 hysteresis = <2000>;
4666 type 4317 type = "hot";
4667 }; 4318 };
4668 4319
4669 ddr_crit: ddr 4320 ddr_crit: ddr-crit {
4670 tempe 4321 temperature = <110000>;
4671 hyste 4322 hysteresis = <2000>;
4672 type 4323 type = "critical";
4673 }; 4324 };
4674 }; 4325 };
4675 }; 4326 };
4676 4327
4677 q6-hvx-thermal { 4328 q6-hvx-thermal {
4678 polling-delay-passive 4329 polling-delay-passive = <250>;
>> 4330 polling-delay = <0>;
4679 4331
4680 thermal-sensors = <&t 4332 thermal-sensors = <&tsens1 4>;
4681 4333
4682 trips { 4334 trips {
4683 q6_hvx_alert0 4335 q6_hvx_alert0: trip-point0 {
4684 tempe 4336 temperature = <90000>;
4685 hyste 4337 hysteresis = <2000>;
4686 type 4338 type = "hot";
4687 }; 4339 };
4688 4340
4689 q6_hvx_crit: 4341 q6_hvx_crit: q6-hvx-crit {
4690 tempe 4342 temperature = <110000>;
4691 hyste 4343 hysteresis = <2000>;
4692 type 4344 type = "critical";
4693 }; 4345 };
4694 }; 4346 };
4695 }; 4347 };
4696 4348
4697 camera-thermal { 4349 camera-thermal {
4698 polling-delay-passive 4350 polling-delay-passive = <250>;
>> 4351 polling-delay = <0>;
4699 4352
4700 thermal-sensors = <&t 4353 thermal-sensors = <&tsens1 5>;
4701 4354
4702 trips { 4355 trips {
4703 camera_alert0 4356 camera_alert0: trip-point0 {
4704 tempe 4357 temperature = <90000>;
4705 hyste 4358 hysteresis = <2000>;
4706 type 4359 type = "hot";
4707 }; 4360 };
4708 4361
4709 camera_crit: 4362 camera_crit: camera-crit {
4710 tempe 4363 temperature = <110000>;
4711 hyste 4364 hysteresis = <2000>;
4712 type 4365 type = "critical";
4713 }; 4366 };
4714 }; 4367 };
4715 }; 4368 };
4716 4369
4717 mdm-core-thermal { 4370 mdm-core-thermal {
4718 polling-delay-passive 4371 polling-delay-passive = <250>;
>> 4372 polling-delay = <0>;
4719 4373
4720 thermal-sensors = <&t 4374 thermal-sensors = <&tsens1 6>;
4721 4375
4722 trips { 4376 trips {
4723 mdm_alert0: t 4377 mdm_alert0: trip-point0 {
4724 tempe 4378 temperature = <90000>;
4725 hyste 4379 hysteresis = <2000>;
4726 type 4380 type = "hot";
4727 }; 4381 };
4728 4382
4729 mdm_crit: mdm 4383 mdm_crit: mdm-crit {
4730 tempe 4384 temperature = <110000>;
4731 hyste 4385 hysteresis = <2000>;
4732 type 4386 type = "critical";
4733 }; 4387 };
4734 }; 4388 };
4735 }; 4389 };
4736 4390
4737 mdm-dsp-thermal { 4391 mdm-dsp-thermal {
4738 polling-delay-passive 4392 polling-delay-passive = <250>;
>> 4393 polling-delay = <0>;
4739 4394
4740 thermal-sensors = <&t 4395 thermal-sensors = <&tsens1 7>;
4741 4396
4742 trips { 4397 trips {
4743 mdm_dsp_alert 4398 mdm_dsp_alert0: trip-point0 {
4744 tempe 4399 temperature = <90000>;
4745 hyste 4400 hysteresis = <2000>;
4746 type 4401 type = "hot";
4747 }; 4402 };
4748 4403
4749 mdm_dsp_crit: 4404 mdm_dsp_crit: mdm-dsp-crit {
4750 tempe 4405 temperature = <110000>;
4751 hyste 4406 hysteresis = <2000>;
4752 type 4407 type = "critical";
4753 }; 4408 };
4754 }; 4409 };
4755 }; 4410 };
4756 4411
4757 npu-thermal { 4412 npu-thermal {
4758 polling-delay-passive 4413 polling-delay-passive = <250>;
>> 4414 polling-delay = <0>;
4759 4415
4760 thermal-sensors = <&t 4416 thermal-sensors = <&tsens1 8>;
4761 4417
4762 trips { 4418 trips {
4763 npu_alert0: t 4419 npu_alert0: trip-point0 {
4764 tempe 4420 temperature = <90000>;
4765 hyste 4421 hysteresis = <2000>;
4766 type 4422 type = "hot";
4767 }; 4423 };
4768 4424
4769 npu_crit: npu 4425 npu_crit: npu-crit {
4770 tempe 4426 temperature = <110000>;
4771 hyste 4427 hysteresis = <2000>;
4772 type 4428 type = "critical";
4773 }; 4429 };
4774 }; 4430 };
4775 }; 4431 };
4776 4432
4777 video-thermal { 4433 video-thermal {
4778 polling-delay-passive 4434 polling-delay-passive = <250>;
>> 4435 polling-delay = <0>;
4779 4436
4780 thermal-sensors = <&t 4437 thermal-sensors = <&tsens1 9>;
4781 4438
4782 trips { 4439 trips {
4783 video_alert0: 4440 video_alert0: trip-point0 {
4784 tempe 4441 temperature = <90000>;
4785 hyste 4442 hysteresis = <2000>;
4786 type 4443 type = "hot";
4787 }; 4444 };
4788 4445
4789 video_crit: v 4446 video_crit: video-crit {
4790 tempe 4447 temperature = <110000>;
4791 hyste 4448 hysteresis = <2000>;
4792 type 4449 type = "critical";
4793 }; 4450 };
4794 }; 4451 };
4795 }; 4452 };
4796 }; 4453 };
4797 4454
4798 timer { 4455 timer {
4799 compatible = "arm,armv8-timer 4456 compatible = "arm,armv8-timer";
4800 interrupts = <GIC_PPI 1 IRQ_T 4457 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
4801 <GIC_PPI 2 IRQ_T 4458 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
4802 <GIC_PPI 3 IRQ_T 4459 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
4803 <GIC_PPI 0 IRQ_T 4460 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
4804 }; 4461 };
4805 }; 4462 };
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