1 // SPDX-License-Identifier: BSD-3-Clause 1 // SPDX-License-Identifier: BSD-3-Clause
2 /* 2 /*
3 * SC7180 SoC device tree source 3 * SC7180 SoC device tree source
4 * 4 *
5 * Copyright (c) 2019-2020, The Linux Foundati 5 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
6 */ 6 */
7 7
8 #include <dt-bindings/clock/qcom,dispcc-sc7180 8 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
9 #include <dt-bindings/clock/qcom,gcc-sc7180.h> 9 #include <dt-bindings/clock/qcom,gcc-sc7180.h>
10 #include <dt-bindings/clock/qcom,gpucc-sc7180. 10 #include <dt-bindings/clock/qcom,gpucc-sc7180.h>
11 #include <dt-bindings/clock/qcom,lpasscorecc-s 11 #include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h>
12 #include <dt-bindings/clock/qcom,rpmh.h> 12 #include <dt-bindings/clock/qcom,rpmh.h>
13 #include <dt-bindings/clock/qcom,videocc-sc718 13 #include <dt-bindings/clock/qcom,videocc-sc7180.h>
14 #include <dt-bindings/firmware/qcom,scm.h> <<
15 #include <dt-bindings/interconnect/qcom,icc.h> <<
16 #include <dt-bindings/interconnect/qcom,osm-l3 14 #include <dt-bindings/interconnect/qcom,osm-l3.h>
17 #include <dt-bindings/interconnect/qcom,sc7180 15 #include <dt-bindings/interconnect/qcom,sc7180.h>
18 #include <dt-bindings/interrupt-controller/arm 16 #include <dt-bindings/interrupt-controller/arm-gic.h>
19 #include <dt-bindings/phy/phy-qcom-qmp.h> <<
20 #include <dt-bindings/phy/phy-qcom-qusb2.h> 17 #include <dt-bindings/phy/phy-qcom-qusb2.h>
21 #include <dt-bindings/power/qcom-rpmpd.h> 18 #include <dt-bindings/power/qcom-rpmpd.h>
22 #include <dt-bindings/reset/qcom,sdm845-aoss.h 19 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
23 #include <dt-bindings/reset/qcom,sdm845-pdc.h> 20 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
24 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 21 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
25 #include <dt-bindings/soc/qcom,apr.h> <<
26 #include <dt-bindings/sound/qcom,q6afe.h> <<
27 #include <dt-bindings/thermal/thermal.h> 22 #include <dt-bindings/thermal/thermal.h>
28 23
29 / { 24 / {
30 interrupt-parent = <&intc>; 25 interrupt-parent = <&intc>;
31 26
32 #address-cells = <2>; 27 #address-cells = <2>;
33 #size-cells = <2>; 28 #size-cells = <2>;
34 29
35 aliases { 30 aliases {
36 mmc1 = &sdhc_1; 31 mmc1 = &sdhc_1;
37 mmc2 = &sdhc_2; 32 mmc2 = &sdhc_2;
38 i2c0 = &i2c0; 33 i2c0 = &i2c0;
39 i2c1 = &i2c1; 34 i2c1 = &i2c1;
40 i2c2 = &i2c2; 35 i2c2 = &i2c2;
41 i2c3 = &i2c3; 36 i2c3 = &i2c3;
42 i2c4 = &i2c4; 37 i2c4 = &i2c4;
43 i2c5 = &i2c5; 38 i2c5 = &i2c5;
44 i2c6 = &i2c6; 39 i2c6 = &i2c6;
45 i2c7 = &i2c7; 40 i2c7 = &i2c7;
46 i2c8 = &i2c8; 41 i2c8 = &i2c8;
47 i2c9 = &i2c9; 42 i2c9 = &i2c9;
48 i2c10 = &i2c10; 43 i2c10 = &i2c10;
49 i2c11 = &i2c11; 44 i2c11 = &i2c11;
50 spi0 = &spi0; 45 spi0 = &spi0;
51 spi1 = &spi1; 46 spi1 = &spi1;
52 spi3 = &spi3; 47 spi3 = &spi3;
53 spi5 = &spi5; 48 spi5 = &spi5;
54 spi6 = &spi6; 49 spi6 = &spi6;
55 spi8 = &spi8; 50 spi8 = &spi8;
56 spi10 = &spi10; 51 spi10 = &spi10;
57 spi11 = &spi11; 52 spi11 = &spi11;
58 }; 53 };
59 54
60 chosen { }; 55 chosen { };
61 56
62 clocks { 57 clocks {
63 xo_board: xo-board { 58 xo_board: xo-board {
64 compatible = "fixed-cl 59 compatible = "fixed-clock";
65 clock-frequency = <384 60 clock-frequency = <38400000>;
66 #clock-cells = <0>; 61 #clock-cells = <0>;
67 }; 62 };
68 63
69 sleep_clk: sleep-clk { 64 sleep_clk: sleep-clk {
70 compatible = "fixed-cl 65 compatible = "fixed-clock";
71 clock-frequency = <327 66 clock-frequency = <32764>;
72 #clock-cells = <0>; 67 #clock-cells = <0>;
73 }; 68 };
74 }; 69 };
75 70
76 cpus { 71 cpus {
77 #address-cells = <2>; 72 #address-cells = <2>;
78 #size-cells = <0>; 73 #size-cells = <0>;
79 74
80 CPU0: cpu@0 { 75 CPU0: cpu@0 {
81 device_type = "cpu"; 76 device_type = "cpu";
82 compatible = "qcom,kry 77 compatible = "qcom,kryo468";
83 reg = <0x0 0x0>; 78 reg = <0x0 0x0>;
84 clocks = <&cpufreq_hw 79 clocks = <&cpufreq_hw 0>;
85 enable-method = "psci" 80 enable-method = "psci";
86 power-domains = <&CPU_ !! 81 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
87 power-domain-names = " !! 82 &LITTLE_CPU_SLEEP_1
>> 83 &CLUSTER_SLEEP_0>;
88 capacity-dmips-mhz = < 84 capacity-dmips-mhz = <415>;
89 dynamic-power-coeffici 85 dynamic-power-coefficient = <137>;
90 operating-points-v2 = 86 operating-points-v2 = <&cpu0_opp_table>;
91 interconnects = <&gem_ 87 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
92 <&osm_ 88 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
93 next-level-cache = <&L 89 next-level-cache = <&L2_0>;
94 #cooling-cells = <2>; 90 #cooling-cells = <2>;
95 qcom,freq-domain = <&c 91 qcom,freq-domain = <&cpufreq_hw 0>;
96 L2_0: l2-cache { 92 L2_0: l2-cache {
97 compatible = " 93 compatible = "cache";
98 cache-level = 94 cache-level = <2>;
99 cache-unified; 95 cache-unified;
100 next-level-cac 96 next-level-cache = <&L3_0>;
101 L3_0: l3-cache 97 L3_0: l3-cache {
102 compat 98 compatible = "cache";
103 cache- 99 cache-level = <3>;
104 cache- 100 cache-unified;
105 }; 101 };
106 }; 102 };
107 }; 103 };
108 104
109 CPU1: cpu@100 { 105 CPU1: cpu@100 {
110 device_type = "cpu"; 106 device_type = "cpu";
111 compatible = "qcom,kry 107 compatible = "qcom,kryo468";
112 reg = <0x0 0x100>; 108 reg = <0x0 0x100>;
113 clocks = <&cpufreq_hw 109 clocks = <&cpufreq_hw 0>;
114 enable-method = "psci" 110 enable-method = "psci";
115 power-domains = <&CPU_ !! 111 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
116 power-domain-names = " !! 112 &LITTLE_CPU_SLEEP_1
>> 113 &CLUSTER_SLEEP_0>;
117 capacity-dmips-mhz = < 114 capacity-dmips-mhz = <415>;
118 dynamic-power-coeffici 115 dynamic-power-coefficient = <137>;
119 next-level-cache = <&L 116 next-level-cache = <&L2_100>;
120 operating-points-v2 = 117 operating-points-v2 = <&cpu0_opp_table>;
121 interconnects = <&gem_ 118 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
122 <&osm_ 119 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
123 #cooling-cells = <2>; 120 #cooling-cells = <2>;
124 qcom,freq-domain = <&c 121 qcom,freq-domain = <&cpufreq_hw 0>;
125 L2_100: l2-cache { 122 L2_100: l2-cache {
126 compatible = " 123 compatible = "cache";
127 cache-level = 124 cache-level = <2>;
128 cache-unified; 125 cache-unified;
129 next-level-cac 126 next-level-cache = <&L3_0>;
130 }; 127 };
131 }; 128 };
132 129
133 CPU2: cpu@200 { 130 CPU2: cpu@200 {
134 device_type = "cpu"; 131 device_type = "cpu";
135 compatible = "qcom,kry 132 compatible = "qcom,kryo468";
136 reg = <0x0 0x200>; 133 reg = <0x0 0x200>;
137 clocks = <&cpufreq_hw 134 clocks = <&cpufreq_hw 0>;
138 enable-method = "psci" 135 enable-method = "psci";
139 power-domains = <&CPU_ !! 136 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
140 power-domain-names = " !! 137 &LITTLE_CPU_SLEEP_1
>> 138 &CLUSTER_SLEEP_0>;
141 capacity-dmips-mhz = < 139 capacity-dmips-mhz = <415>;
142 dynamic-power-coeffici 140 dynamic-power-coefficient = <137>;
143 next-level-cache = <&L 141 next-level-cache = <&L2_200>;
144 operating-points-v2 = 142 operating-points-v2 = <&cpu0_opp_table>;
145 interconnects = <&gem_ 143 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
146 <&osm_ 144 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
147 #cooling-cells = <2>; 145 #cooling-cells = <2>;
148 qcom,freq-domain = <&c 146 qcom,freq-domain = <&cpufreq_hw 0>;
149 L2_200: l2-cache { 147 L2_200: l2-cache {
150 compatible = " 148 compatible = "cache";
151 cache-level = 149 cache-level = <2>;
152 cache-unified; 150 cache-unified;
153 next-level-cac 151 next-level-cache = <&L3_0>;
154 }; 152 };
155 }; 153 };
156 154
157 CPU3: cpu@300 { 155 CPU3: cpu@300 {
158 device_type = "cpu"; 156 device_type = "cpu";
159 compatible = "qcom,kry 157 compatible = "qcom,kryo468";
160 reg = <0x0 0x300>; 158 reg = <0x0 0x300>;
161 clocks = <&cpufreq_hw 159 clocks = <&cpufreq_hw 0>;
162 enable-method = "psci" 160 enable-method = "psci";
163 power-domains = <&CPU_ !! 161 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
164 power-domain-names = " !! 162 &LITTLE_CPU_SLEEP_1
>> 163 &CLUSTER_SLEEP_0>;
165 capacity-dmips-mhz = < 164 capacity-dmips-mhz = <415>;
166 dynamic-power-coeffici 165 dynamic-power-coefficient = <137>;
167 next-level-cache = <&L 166 next-level-cache = <&L2_300>;
168 operating-points-v2 = 167 operating-points-v2 = <&cpu0_opp_table>;
169 interconnects = <&gem_ 168 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
170 <&osm_ 169 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
171 #cooling-cells = <2>; 170 #cooling-cells = <2>;
172 qcom,freq-domain = <&c 171 qcom,freq-domain = <&cpufreq_hw 0>;
173 L2_300: l2-cache { 172 L2_300: l2-cache {
174 compatible = " 173 compatible = "cache";
175 cache-level = 174 cache-level = <2>;
176 cache-unified; 175 cache-unified;
177 next-level-cac 176 next-level-cache = <&L3_0>;
178 }; 177 };
179 }; 178 };
180 179
181 CPU4: cpu@400 { 180 CPU4: cpu@400 {
182 device_type = "cpu"; 181 device_type = "cpu";
183 compatible = "qcom,kry 182 compatible = "qcom,kryo468";
184 reg = <0x0 0x400>; 183 reg = <0x0 0x400>;
185 clocks = <&cpufreq_hw 184 clocks = <&cpufreq_hw 0>;
186 enable-method = "psci" 185 enable-method = "psci";
187 power-domains = <&CPU_ !! 186 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
188 power-domain-names = " !! 187 &LITTLE_CPU_SLEEP_1
>> 188 &CLUSTER_SLEEP_0>;
189 capacity-dmips-mhz = < 189 capacity-dmips-mhz = <415>;
190 dynamic-power-coeffici 190 dynamic-power-coefficient = <137>;
191 next-level-cache = <&L 191 next-level-cache = <&L2_400>;
192 operating-points-v2 = 192 operating-points-v2 = <&cpu0_opp_table>;
193 interconnects = <&gem_ 193 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
194 <&osm_ 194 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
195 #cooling-cells = <2>; 195 #cooling-cells = <2>;
196 qcom,freq-domain = <&c 196 qcom,freq-domain = <&cpufreq_hw 0>;
197 L2_400: l2-cache { 197 L2_400: l2-cache {
198 compatible = " 198 compatible = "cache";
199 cache-level = 199 cache-level = <2>;
200 cache-unified; 200 cache-unified;
201 next-level-cac 201 next-level-cache = <&L3_0>;
202 }; 202 };
203 }; 203 };
204 204
205 CPU5: cpu@500 { 205 CPU5: cpu@500 {
206 device_type = "cpu"; 206 device_type = "cpu";
207 compatible = "qcom,kry 207 compatible = "qcom,kryo468";
208 reg = <0x0 0x500>; 208 reg = <0x0 0x500>;
209 clocks = <&cpufreq_hw 209 clocks = <&cpufreq_hw 0>;
210 enable-method = "psci" 210 enable-method = "psci";
211 power-domains = <&CPU_ !! 211 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
212 power-domain-names = " !! 212 &LITTLE_CPU_SLEEP_1
>> 213 &CLUSTER_SLEEP_0>;
213 capacity-dmips-mhz = < 214 capacity-dmips-mhz = <415>;
214 dynamic-power-coeffici 215 dynamic-power-coefficient = <137>;
215 next-level-cache = <&L 216 next-level-cache = <&L2_500>;
216 operating-points-v2 = 217 operating-points-v2 = <&cpu0_opp_table>;
217 interconnects = <&gem_ 218 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
218 <&osm_ 219 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
219 #cooling-cells = <2>; 220 #cooling-cells = <2>;
220 qcom,freq-domain = <&c 221 qcom,freq-domain = <&cpufreq_hw 0>;
221 L2_500: l2-cache { 222 L2_500: l2-cache {
222 compatible = " 223 compatible = "cache";
223 cache-level = 224 cache-level = <2>;
224 cache-unified; 225 cache-unified;
225 next-level-cac 226 next-level-cache = <&L3_0>;
226 }; 227 };
227 }; 228 };
228 229
229 CPU6: cpu@600 { 230 CPU6: cpu@600 {
230 device_type = "cpu"; 231 device_type = "cpu";
231 compatible = "qcom,kry 232 compatible = "qcom,kryo468";
232 reg = <0x0 0x600>; 233 reg = <0x0 0x600>;
233 clocks = <&cpufreq_hw 234 clocks = <&cpufreq_hw 1>;
234 enable-method = "psci" 235 enable-method = "psci";
235 power-domains = <&CPU_ !! 236 cpu-idle-states = <&BIG_CPU_SLEEP_0
236 power-domain-names = " !! 237 &BIG_CPU_SLEEP_1
>> 238 &CLUSTER_SLEEP_0>;
237 capacity-dmips-mhz = < 239 capacity-dmips-mhz = <1024>;
238 dynamic-power-coeffici 240 dynamic-power-coefficient = <480>;
239 next-level-cache = <&L 241 next-level-cache = <&L2_600>;
240 operating-points-v2 = 242 operating-points-v2 = <&cpu6_opp_table>;
241 interconnects = <&gem_ 243 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
242 <&osm_ 244 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
243 #cooling-cells = <2>; 245 #cooling-cells = <2>;
244 qcom,freq-domain = <&c 246 qcom,freq-domain = <&cpufreq_hw 1>;
245 L2_600: l2-cache { 247 L2_600: l2-cache {
246 compatible = " 248 compatible = "cache";
247 cache-level = 249 cache-level = <2>;
248 cache-unified; 250 cache-unified;
249 next-level-cac 251 next-level-cache = <&L3_0>;
250 }; 252 };
251 }; 253 };
252 254
253 CPU7: cpu@700 { 255 CPU7: cpu@700 {
254 device_type = "cpu"; 256 device_type = "cpu";
255 compatible = "qcom,kry 257 compatible = "qcom,kryo468";
256 reg = <0x0 0x700>; 258 reg = <0x0 0x700>;
257 clocks = <&cpufreq_hw 259 clocks = <&cpufreq_hw 1>;
258 enable-method = "psci" 260 enable-method = "psci";
259 power-domains = <&CPU_ !! 261 cpu-idle-states = <&BIG_CPU_SLEEP_0
260 power-domain-names = " !! 262 &BIG_CPU_SLEEP_1
>> 263 &CLUSTER_SLEEP_0>;
261 capacity-dmips-mhz = < 264 capacity-dmips-mhz = <1024>;
262 dynamic-power-coeffici 265 dynamic-power-coefficient = <480>;
263 next-level-cache = <&L 266 next-level-cache = <&L2_700>;
264 operating-points-v2 = 267 operating-points-v2 = <&cpu6_opp_table>;
265 interconnects = <&gem_ 268 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
266 <&osm_ 269 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
267 #cooling-cells = <2>; 270 #cooling-cells = <2>;
268 qcom,freq-domain = <&c 271 qcom,freq-domain = <&cpufreq_hw 1>;
269 L2_700: l2-cache { 272 L2_700: l2-cache {
270 compatible = " 273 compatible = "cache";
271 cache-level = 274 cache-level = <2>;
272 cache-unified; 275 cache-unified;
273 next-level-cac 276 next-level-cache = <&L3_0>;
274 }; 277 };
275 }; 278 };
276 279
277 cpu-map { 280 cpu-map {
278 cluster0 { 281 cluster0 {
279 core0 { 282 core0 {
280 cpu = 283 cpu = <&CPU0>;
281 }; 284 };
282 285
283 core1 { 286 core1 {
284 cpu = 287 cpu = <&CPU1>;
285 }; 288 };
286 289
287 core2 { 290 core2 {
288 cpu = 291 cpu = <&CPU2>;
289 }; 292 };
290 293
291 core3 { 294 core3 {
292 cpu = 295 cpu = <&CPU3>;
293 }; 296 };
294 297
295 core4 { 298 core4 {
296 cpu = 299 cpu = <&CPU4>;
297 }; 300 };
298 301
299 core5 { 302 core5 {
300 cpu = 303 cpu = <&CPU5>;
301 }; 304 };
302 305
303 core6 { 306 core6 {
304 cpu = 307 cpu = <&CPU6>;
305 }; 308 };
306 309
307 core7 { 310 core7 {
308 cpu = 311 cpu = <&CPU7>;
309 }; 312 };
310 }; 313 };
311 }; 314 };
312 315
313 idle_states: idle-states { !! 316 idle-states {
314 entry-method = "psci"; 317 entry-method = "psci";
315 318
316 LITTLE_CPU_SLEEP_0: cp 319 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
317 compatible = " 320 compatible = "arm,idle-state";
318 idle-state-nam 321 idle-state-name = "little-power-down";
319 arm,psci-suspe 322 arm,psci-suspend-param = <0x40000003>;
320 entry-latency- 323 entry-latency-us = <549>;
321 exit-latency-u 324 exit-latency-us = <901>;
322 min-residency- 325 min-residency-us = <1774>;
323 local-timer-st 326 local-timer-stop;
324 }; 327 };
325 328
326 LITTLE_CPU_SLEEP_1: cp 329 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
327 compatible = " 330 compatible = "arm,idle-state";
328 idle-state-nam 331 idle-state-name = "little-rail-power-down";
329 arm,psci-suspe 332 arm,psci-suspend-param = <0x40000004>;
330 entry-latency- 333 entry-latency-us = <702>;
331 exit-latency-u 334 exit-latency-us = <915>;
332 min-residency- 335 min-residency-us = <4001>;
333 local-timer-st 336 local-timer-stop;
334 }; 337 };
335 338
336 BIG_CPU_SLEEP_0: cpu-s 339 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
337 compatible = " 340 compatible = "arm,idle-state";
338 idle-state-nam 341 idle-state-name = "big-power-down";
339 arm,psci-suspe 342 arm,psci-suspend-param = <0x40000003>;
340 entry-latency- 343 entry-latency-us = <523>;
341 exit-latency-u 344 exit-latency-us = <1244>;
342 min-residency- 345 min-residency-us = <2207>;
343 local-timer-st 346 local-timer-stop;
344 }; 347 };
345 348
346 BIG_CPU_SLEEP_1: cpu-s 349 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
347 compatible = " 350 compatible = "arm,idle-state";
348 idle-state-nam 351 idle-state-name = "big-rail-power-down";
349 arm,psci-suspe 352 arm,psci-suspend-param = <0x40000004>;
350 entry-latency- 353 entry-latency-us = <526>;
351 exit-latency-u 354 exit-latency-us = <1854>;
352 min-residency- 355 min-residency-us = <5555>;
353 local-timer-st 356 local-timer-stop;
354 }; 357 };
355 }; <<
356 <<
357 domain_idle_states: domain-idl <<
358 CLUSTER_SLEEP_PC: clus <<
359 compatible = " <<
360 idle-state-nam <<
361 arm,psci-suspe <<
362 entry-latency- <<
363 exit-latency-u <<
364 min-residency- <<
365 }; <<
366 <<
367 CLUSTER_SLEEP_CX_RET: <<
368 compatible = " <<
369 idle-state-nam <<
370 arm,psci-suspe <<
371 entry-latency- <<
372 exit-latency-u <<
373 min-residency- <<
374 }; <<
375 358
376 CLUSTER_AOSS_SLEEP: cl !! 359 CLUSTER_SLEEP_0: cluster-sleep-0 {
377 compatible = " !! 360 compatible = "arm,idle-state";
378 idle-state-nam 361 idle-state-name = "cluster-power-down";
379 arm,psci-suspe !! 362 arm,psci-suspend-param = <0x40003444>;
380 entry-latency- 363 entry-latency-us = <3263>;
381 exit-latency-u 364 exit-latency-us = <6562>;
382 min-residency- !! 365 min-residency-us = <9926>;
>> 366 local-timer-stop;
383 }; 367 };
384 }; 368 };
385 }; 369 };
386 370
387 firmware { 371 firmware {
388 scm: scm { 372 scm: scm {
389 compatible = "qcom,scm 373 compatible = "qcom,scm-sc7180", "qcom,scm";
390 }; 374 };
391 }; 375 };
392 376
393 memory@80000000 { 377 memory@80000000 {
394 device_type = "memory"; 378 device_type = "memory";
395 /* We expect the bootloader to 379 /* We expect the bootloader to fill in the size */
396 reg = <0 0x80000000 0 0>; 380 reg = <0 0x80000000 0 0>;
397 }; 381 };
398 382
399 cpu0_opp_table: opp-table-cpu0 { 383 cpu0_opp_table: opp-table-cpu0 {
400 compatible = "operating-points 384 compatible = "operating-points-v2";
401 opp-shared; 385 opp-shared;
402 386
403 cpu0_opp1: opp-300000000 { 387 cpu0_opp1: opp-300000000 {
404 opp-hz = /bits/ 64 <30 388 opp-hz = /bits/ 64 <300000000>;
405 opp-peak-kBps = <12000 389 opp-peak-kBps = <1200000 4800000>;
406 }; 390 };
407 391
408 cpu0_opp2: opp-576000000 { 392 cpu0_opp2: opp-576000000 {
409 opp-hz = /bits/ 64 <57 393 opp-hz = /bits/ 64 <576000000>;
410 opp-peak-kBps = <12000 394 opp-peak-kBps = <1200000 4800000>;
411 }; 395 };
412 396
413 cpu0_opp3: opp-768000000 { 397 cpu0_opp3: opp-768000000 {
414 opp-hz = /bits/ 64 <76 398 opp-hz = /bits/ 64 <768000000>;
415 opp-peak-kBps = <12000 399 opp-peak-kBps = <1200000 4800000>;
416 }; 400 };
417 401
418 cpu0_opp4: opp-1017600000 { 402 cpu0_opp4: opp-1017600000 {
419 opp-hz = /bits/ 64 <10 403 opp-hz = /bits/ 64 <1017600000>;
420 opp-peak-kBps = <18040 404 opp-peak-kBps = <1804000 8908800>;
421 }; 405 };
422 406
423 cpu0_opp5: opp-1248000000 { 407 cpu0_opp5: opp-1248000000 {
424 opp-hz = /bits/ 64 <12 408 opp-hz = /bits/ 64 <1248000000>;
425 opp-peak-kBps = <21880 409 opp-peak-kBps = <2188000 12902400>;
426 }; 410 };
427 411
428 cpu0_opp6: opp-1324800000 { 412 cpu0_opp6: opp-1324800000 {
429 opp-hz = /bits/ 64 <13 413 opp-hz = /bits/ 64 <1324800000>;
430 opp-peak-kBps = <21880 414 opp-peak-kBps = <2188000 12902400>;
431 }; 415 };
432 416
433 cpu0_opp7: opp-1516800000 { 417 cpu0_opp7: opp-1516800000 {
434 opp-hz = /bits/ 64 <15 418 opp-hz = /bits/ 64 <1516800000>;
435 opp-peak-kBps = <30720 419 opp-peak-kBps = <3072000 15052800>;
436 }; 420 };
437 421
438 cpu0_opp8: opp-1612800000 { 422 cpu0_opp8: opp-1612800000 {
439 opp-hz = /bits/ 64 <16 423 opp-hz = /bits/ 64 <1612800000>;
440 opp-peak-kBps = <30720 424 opp-peak-kBps = <3072000 15052800>;
441 }; 425 };
442 426
443 cpu0_opp9: opp-1708800000 { 427 cpu0_opp9: opp-1708800000 {
444 opp-hz = /bits/ 64 <17 428 opp-hz = /bits/ 64 <1708800000>;
445 opp-peak-kBps = <30720 429 opp-peak-kBps = <3072000 15052800>;
446 }; 430 };
447 431
448 cpu0_opp10: opp-1804800000 { 432 cpu0_opp10: opp-1804800000 {
449 opp-hz = /bits/ 64 <18 433 opp-hz = /bits/ 64 <1804800000>;
450 opp-peak-kBps = <40680 434 opp-peak-kBps = <4068000 22425600>;
451 }; 435 };
452 }; 436 };
453 437
454 cpu6_opp_table: opp-table-cpu6 { 438 cpu6_opp_table: opp-table-cpu6 {
455 compatible = "operating-points 439 compatible = "operating-points-v2";
456 opp-shared; 440 opp-shared;
457 441
458 cpu6_opp1: opp-300000000 { 442 cpu6_opp1: opp-300000000 {
459 opp-hz = /bits/ 64 <30 443 opp-hz = /bits/ 64 <300000000>;
460 opp-peak-kBps = <21880 444 opp-peak-kBps = <2188000 8908800>;
461 }; 445 };
462 446
463 cpu6_opp2: opp-652800000 { 447 cpu6_opp2: opp-652800000 {
464 opp-hz = /bits/ 64 <65 448 opp-hz = /bits/ 64 <652800000>;
465 opp-peak-kBps = <21880 449 opp-peak-kBps = <2188000 8908800>;
466 }; 450 };
467 451
468 cpu6_opp3: opp-825600000 { 452 cpu6_opp3: opp-825600000 {
469 opp-hz = /bits/ 64 <82 453 opp-hz = /bits/ 64 <825600000>;
470 opp-peak-kBps = <21880 454 opp-peak-kBps = <2188000 8908800>;
471 }; 455 };
472 456
473 cpu6_opp4: opp-979200000 { 457 cpu6_opp4: opp-979200000 {
474 opp-hz = /bits/ 64 <97 458 opp-hz = /bits/ 64 <979200000>;
475 opp-peak-kBps = <21880 459 opp-peak-kBps = <2188000 8908800>;
476 }; 460 };
477 461
478 cpu6_opp5: opp-1113600000 { 462 cpu6_opp5: opp-1113600000 {
479 opp-hz = /bits/ 64 <11 463 opp-hz = /bits/ 64 <1113600000>;
480 opp-peak-kBps = <21880 464 opp-peak-kBps = <2188000 8908800>;
481 }; 465 };
482 466
483 cpu6_opp6: opp-1267200000 { 467 cpu6_opp6: opp-1267200000 {
484 opp-hz = /bits/ 64 <12 468 opp-hz = /bits/ 64 <1267200000>;
485 opp-peak-kBps = <40680 469 opp-peak-kBps = <4068000 12902400>;
486 }; 470 };
487 471
488 cpu6_opp7: opp-1555200000 { 472 cpu6_opp7: opp-1555200000 {
489 opp-hz = /bits/ 64 <15 473 opp-hz = /bits/ 64 <1555200000>;
490 opp-peak-kBps = <40680 474 opp-peak-kBps = <4068000 15052800>;
491 }; 475 };
492 476
493 cpu6_opp8: opp-1708800000 { 477 cpu6_opp8: opp-1708800000 {
494 opp-hz = /bits/ 64 <17 478 opp-hz = /bits/ 64 <1708800000>;
495 opp-peak-kBps = <62200 479 opp-peak-kBps = <6220000 19353600>;
496 }; 480 };
497 481
498 cpu6_opp9: opp-1843200000 { 482 cpu6_opp9: opp-1843200000 {
499 opp-hz = /bits/ 64 <18 483 opp-hz = /bits/ 64 <1843200000>;
500 opp-peak-kBps = <62200 484 opp-peak-kBps = <6220000 19353600>;
501 }; 485 };
502 486
503 cpu6_opp10: opp-1900800000 { 487 cpu6_opp10: opp-1900800000 {
504 opp-hz = /bits/ 64 <19 488 opp-hz = /bits/ 64 <1900800000>;
505 opp-peak-kBps = <62200 489 opp-peak-kBps = <6220000 22425600>;
506 }; 490 };
507 491
508 cpu6_opp11: opp-1996800000 { 492 cpu6_opp11: opp-1996800000 {
509 opp-hz = /bits/ 64 <19 493 opp-hz = /bits/ 64 <1996800000>;
510 opp-peak-kBps = <62200 494 opp-peak-kBps = <6220000 22425600>;
511 }; 495 };
512 496
513 cpu6_opp12: opp-2112000000 { 497 cpu6_opp12: opp-2112000000 {
514 opp-hz = /bits/ 64 <21 498 opp-hz = /bits/ 64 <2112000000>;
515 opp-peak-kBps = <62200 499 opp-peak-kBps = <6220000 22425600>;
516 }; 500 };
517 501
518 cpu6_opp13: opp-2208000000 { 502 cpu6_opp13: opp-2208000000 {
519 opp-hz = /bits/ 64 <22 503 opp-hz = /bits/ 64 <2208000000>;
520 opp-peak-kBps = <72160 504 opp-peak-kBps = <7216000 22425600>;
521 }; 505 };
522 506
523 cpu6_opp14: opp-2323200000 { 507 cpu6_opp14: opp-2323200000 {
524 opp-hz = /bits/ 64 <23 508 opp-hz = /bits/ 64 <2323200000>;
525 opp-peak-kBps = <72160 509 opp-peak-kBps = <7216000 22425600>;
526 }; 510 };
527 511
528 cpu6_opp15: opp-2400000000 { 512 cpu6_opp15: opp-2400000000 {
529 opp-hz = /bits/ 64 <24 513 opp-hz = /bits/ 64 <2400000000>;
530 opp-peak-kBps = <85320 514 opp-peak-kBps = <8532000 23347200>;
531 }; 515 };
532 516
533 cpu6_opp16: opp-2553600000 { 517 cpu6_opp16: opp-2553600000 {
534 opp-hz = /bits/ 64 <25 518 opp-hz = /bits/ 64 <2553600000>;
535 opp-peak-kBps = <85320 519 opp-peak-kBps = <8532000 23347200>;
536 }; 520 };
537 }; 521 };
538 522
539 qspi_opp_table: opp-table-qspi { 523 qspi_opp_table: opp-table-qspi {
540 compatible = "operating-points 524 compatible = "operating-points-v2";
541 525
542 opp-75000000 { 526 opp-75000000 {
543 opp-hz = /bits/ 64 <75 527 opp-hz = /bits/ 64 <75000000>;
544 required-opps = <&rpmh 528 required-opps = <&rpmhpd_opp_low_svs>;
545 }; 529 };
546 530
547 opp-150000000 { 531 opp-150000000 {
548 opp-hz = /bits/ 64 <15 532 opp-hz = /bits/ 64 <150000000>;
549 required-opps = <&rpmh 533 required-opps = <&rpmhpd_opp_svs>;
550 }; 534 };
551 535
552 opp-300000000 { 536 opp-300000000 {
553 opp-hz = /bits/ 64 <30 537 opp-hz = /bits/ 64 <300000000>;
554 required-opps = <&rpmh 538 required-opps = <&rpmhpd_opp_nom>;
555 }; 539 };
556 }; 540 };
557 541
558 qup_opp_table: opp-table-qup { 542 qup_opp_table: opp-table-qup {
559 compatible = "operating-points 543 compatible = "operating-points-v2";
560 544
561 opp-75000000 { 545 opp-75000000 {
562 opp-hz = /bits/ 64 <75 546 opp-hz = /bits/ 64 <75000000>;
563 required-opps = <&rpmh 547 required-opps = <&rpmhpd_opp_low_svs>;
564 }; 548 };
565 549
566 opp-100000000 { 550 opp-100000000 {
567 opp-hz = /bits/ 64 <10 551 opp-hz = /bits/ 64 <100000000>;
568 required-opps = <&rpmh 552 required-opps = <&rpmhpd_opp_svs>;
569 }; 553 };
570 554
571 opp-128000000 { 555 opp-128000000 {
572 opp-hz = /bits/ 64 <12 556 opp-hz = /bits/ 64 <128000000>;
573 required-opps = <&rpmh 557 required-opps = <&rpmhpd_opp_nom>;
574 }; 558 };
575 }; 559 };
576 560
577 pmu { 561 pmu {
578 compatible = "arm,armv8-pmuv3" 562 compatible = "arm,armv8-pmuv3";
579 interrupts = <GIC_PPI 5 IRQ_TY 563 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
580 }; 564 };
581 565
582 psci { 566 psci {
583 compatible = "arm,psci-1.0"; 567 compatible = "arm,psci-1.0";
584 method = "smc"; 568 method = "smc";
585 <<
586 CPU_PD0: cpu0 { <<
587 #power-domain-cells = <<
588 power-domains = <&CLUS <<
589 domain-idle-states = < <<
590 }; <<
591 <<
592 CPU_PD1: cpu1 { <<
593 #power-domain-cells = <<
594 power-domains = <&CLUS <<
595 domain-idle-states = < <<
596 }; <<
597 <<
598 CPU_PD2: cpu2 { <<
599 #power-domain-cells = <<
600 power-domains = <&CLUS <<
601 domain-idle-states = < <<
602 }; <<
603 <<
604 CPU_PD3: cpu3 { <<
605 #power-domain-cells = <<
606 power-domains = <&CLUS <<
607 domain-idle-states = < <<
608 }; <<
609 <<
610 CPU_PD4: cpu4 { <<
611 #power-domain-cells = <<
612 power-domains = <&CLUS <<
613 domain-idle-states = < <<
614 }; <<
615 <<
616 CPU_PD5: cpu5 { <<
617 #power-domain-cells = <<
618 power-domains = <&CLUS <<
619 domain-idle-states = < <<
620 }; <<
621 <<
622 CPU_PD6: cpu6 { <<
623 #power-domain-cells = <<
624 power-domains = <&CLUS <<
625 domain-idle-states = < <<
626 }; <<
627 <<
628 CPU_PD7: cpu7 { <<
629 #power-domain-cells = <<
630 power-domains = <&CLUS <<
631 domain-idle-states = < <<
632 }; <<
633 <<
634 CLUSTER_PD: cpu-cluster0 { <<
635 #power-domain-cells = <<
636 domain-idle-states = < <<
637 <<
638 <<
639 }; <<
640 }; 569 };
641 570
642 reserved_memory: reserved-memory { 571 reserved_memory: reserved-memory {
643 #address-cells = <2>; 572 #address-cells = <2>;
644 #size-cells = <2>; 573 #size-cells = <2>;
645 ranges; 574 ranges;
646 575
647 hyp_mem: memory@80000000 { 576 hyp_mem: memory@80000000 {
648 reg = <0x0 0x80000000 577 reg = <0x0 0x80000000 0x0 0x600000>;
649 no-map; 578 no-map;
650 }; 579 };
651 580
652 xbl_mem: memory@80600000 { 581 xbl_mem: memory@80600000 {
653 reg = <0x0 0x80600000 582 reg = <0x0 0x80600000 0x0 0x200000>;
654 no-map; 583 no-map;
655 }; 584 };
656 585
657 aop_mem: memory@80800000 { 586 aop_mem: memory@80800000 {
658 reg = <0x0 0x80800000 587 reg = <0x0 0x80800000 0x0 0x20000>;
659 no-map; 588 no-map;
660 }; 589 };
661 590
662 aop_cmd_db_mem: memory@8082000 591 aop_cmd_db_mem: memory@80820000 {
663 reg = <0x0 0x80820000 592 reg = <0x0 0x80820000 0x0 0x20000>;
664 compatible = "qcom,cmd 593 compatible = "qcom,cmd-db";
665 no-map; 594 no-map;
666 }; 595 };
667 596
668 sec_apps_mem: memory@808ff000 597 sec_apps_mem: memory@808ff000 {
669 reg = <0x0 0x808ff000 598 reg = <0x0 0x808ff000 0x0 0x1000>;
670 no-map; 599 no-map;
671 }; 600 };
672 601
673 smem_mem: memory@80900000 { 602 smem_mem: memory@80900000 {
674 reg = <0x0 0x80900000 603 reg = <0x0 0x80900000 0x0 0x200000>;
675 no-map; 604 no-map;
676 }; 605 };
677 606
678 tz_mem: memory@80b00000 { 607 tz_mem: memory@80b00000 {
679 reg = <0x0 0x80b00000 608 reg = <0x0 0x80b00000 0x0 0x3900000>;
680 no-map; 609 no-map;
681 }; 610 };
682 611
683 ipa_fw_mem: memory@8b700000 { 612 ipa_fw_mem: memory@8b700000 {
684 reg = <0 0x8b700000 0 613 reg = <0 0x8b700000 0 0x10000>;
685 no-map; 614 no-map;
686 }; 615 };
687 616
688 rmtfs_mem: memory@94600000 { 617 rmtfs_mem: memory@94600000 {
689 compatible = "qcom,rmt 618 compatible = "qcom,rmtfs-mem";
690 reg = <0x0 0x94600000 619 reg = <0x0 0x94600000 0x0 0x200000>;
691 no-map; 620 no-map;
692 621
693 qcom,client-id = <1>; 622 qcom,client-id = <1>;
694 qcom,vmid = <QCOM_SCM_ !! 623 qcom,vmid = <15>;
695 }; 624 };
696 }; 625 };
697 626
698 smem { 627 smem {
699 compatible = "qcom,smem"; 628 compatible = "qcom,smem";
700 memory-region = <&smem_mem>; 629 memory-region = <&smem_mem>;
701 hwlocks = <&tcsr_mutex 3>; 630 hwlocks = <&tcsr_mutex 3>;
702 }; 631 };
703 632
704 smp2p-cdsp { 633 smp2p-cdsp {
705 compatible = "qcom,smp2p"; 634 compatible = "qcom,smp2p";
706 qcom,smem = <94>, <432>; 635 qcom,smem = <94>, <432>;
707 636
708 interrupts = <GIC_SPI 576 IRQ_ 637 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
709 638
710 mboxes = <&apss_shared 6>; 639 mboxes = <&apss_shared 6>;
711 640
712 qcom,local-pid = <0>; 641 qcom,local-pid = <0>;
713 qcom,remote-pid = <5>; 642 qcom,remote-pid = <5>;
714 643
715 cdsp_smp2p_out: master-kernel 644 cdsp_smp2p_out: master-kernel {
716 qcom,entry-name = "mas 645 qcom,entry-name = "master-kernel";
717 #qcom,smem-state-cells 646 #qcom,smem-state-cells = <1>;
718 }; 647 };
719 648
720 cdsp_smp2p_in: slave-kernel { 649 cdsp_smp2p_in: slave-kernel {
721 qcom,entry-name = "sla 650 qcom,entry-name = "slave-kernel";
722 651
723 interrupt-controller; 652 interrupt-controller;
724 #interrupt-cells = <2> 653 #interrupt-cells = <2>;
725 }; 654 };
726 }; 655 };
727 656
728 smp2p-lpass { 657 smp2p-lpass {
729 compatible = "qcom,smp2p"; 658 compatible = "qcom,smp2p";
730 qcom,smem = <443>, <429>; 659 qcom,smem = <443>, <429>;
731 660
732 interrupts = <GIC_SPI 158 IRQ_ 661 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
733 662
734 mboxes = <&apss_shared 10>; 663 mboxes = <&apss_shared 10>;
735 664
736 qcom,local-pid = <0>; 665 qcom,local-pid = <0>;
737 qcom,remote-pid = <2>; 666 qcom,remote-pid = <2>;
738 667
739 adsp_smp2p_out: master-kernel 668 adsp_smp2p_out: master-kernel {
740 qcom,entry-name = "mas 669 qcom,entry-name = "master-kernel";
741 #qcom,smem-state-cells 670 #qcom,smem-state-cells = <1>;
742 }; 671 };
743 672
744 adsp_smp2p_in: slave-kernel { 673 adsp_smp2p_in: slave-kernel {
745 qcom,entry-name = "sla 674 qcom,entry-name = "slave-kernel";
746 675
747 interrupt-controller; 676 interrupt-controller;
748 #interrupt-cells = <2> 677 #interrupt-cells = <2>;
749 }; 678 };
750 }; 679 };
751 680
752 smp2p-mpss { 681 smp2p-mpss {
753 compatible = "qcom,smp2p"; 682 compatible = "qcom,smp2p";
754 qcom,smem = <435>, <428>; 683 qcom,smem = <435>, <428>;
755 interrupts = <GIC_SPI 451 IRQ_ 684 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
756 mboxes = <&apss_shared 14>; 685 mboxes = <&apss_shared 14>;
757 qcom,local-pid = <0>; 686 qcom,local-pid = <0>;
758 qcom,remote-pid = <1>; 687 qcom,remote-pid = <1>;
759 688
760 modem_smp2p_out: master-kernel 689 modem_smp2p_out: master-kernel {
761 qcom,entry-name = "mas 690 qcom,entry-name = "master-kernel";
762 #qcom,smem-state-cells 691 #qcom,smem-state-cells = <1>;
763 }; 692 };
764 693
765 modem_smp2p_in: slave-kernel { 694 modem_smp2p_in: slave-kernel {
766 qcom,entry-name = "sla 695 qcom,entry-name = "slave-kernel";
767 interrupt-controller; 696 interrupt-controller;
768 #interrupt-cells = <2> 697 #interrupt-cells = <2>;
769 }; 698 };
770 699
771 ipa_smp2p_out: ipa-ap-to-modem 700 ipa_smp2p_out: ipa-ap-to-modem {
772 qcom,entry-name = "ipa 701 qcom,entry-name = "ipa";
773 #qcom,smem-state-cells 702 #qcom,smem-state-cells = <1>;
774 }; 703 };
775 704
776 ipa_smp2p_in: ipa-modem-to-ap 705 ipa_smp2p_in: ipa-modem-to-ap {
777 qcom,entry-name = "ipa 706 qcom,entry-name = "ipa";
778 interrupt-controller; 707 interrupt-controller;
779 #interrupt-cells = <2> 708 #interrupt-cells = <2>;
780 }; 709 };
781 }; 710 };
782 711
783 soc: soc@0 { 712 soc: soc@0 {
784 #address-cells = <2>; 713 #address-cells = <2>;
785 #size-cells = <2>; 714 #size-cells = <2>;
786 ranges = <0 0 0 0 0x10 0>; 715 ranges = <0 0 0 0 0x10 0>;
787 dma-ranges = <0 0 0 0 0x10 0>; 716 dma-ranges = <0 0 0 0 0x10 0>;
788 compatible = "simple-bus"; 717 compatible = "simple-bus";
789 718
790 gcc: clock-controller@100000 { 719 gcc: clock-controller@100000 {
791 compatible = "qcom,gcc 720 compatible = "qcom,gcc-sc7180";
792 reg = <0 0x00100000 0 721 reg = <0 0x00100000 0 0x1f0000>;
793 clocks = <&rpmhcc RPMH 722 clocks = <&rpmhcc RPMH_CXO_CLK>,
794 <&rpmhcc RPMH 723 <&rpmhcc RPMH_CXO_CLK_A>,
795 <&sleep_clk>; 724 <&sleep_clk>;
796 clock-names = "bi_tcxo 725 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
797 #clock-cells = <1>; 726 #clock-cells = <1>;
798 #reset-cells = <1>; 727 #reset-cells = <1>;
799 #power-domain-cells = 728 #power-domain-cells = <1>;
800 power-domains = <&rpmh 729 power-domains = <&rpmhpd SC7180_CX>;
801 }; 730 };
802 731
803 qfprom: efuse@784000 { 732 qfprom: efuse@784000 {
804 compatible = "qcom,sc7 733 compatible = "qcom,sc7180-qfprom", "qcom,qfprom";
805 reg = <0 0x00784000 0 734 reg = <0 0x00784000 0 0x7a0>,
806 <0 0x00780000 0 735 <0 0x00780000 0 0x7a0>,
807 <0 0x00782000 0 736 <0 0x00782000 0 0x100>,
808 <0 0x00786000 0 737 <0 0x00786000 0 0x1fff>;
809 738
810 clocks = <&gcc GCC_SEC 739 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>;
811 clock-names = "core"; 740 clock-names = "core";
812 #address-cells = <1>; 741 #address-cells = <1>;
813 #size-cells = <1>; 742 #size-cells = <1>;
814 743
815 qusb2p_hstx_trim: hstx 744 qusb2p_hstx_trim: hstx-trim-primary@25b {
816 reg = <0x25b 0 745 reg = <0x25b 0x1>;
817 bits = <1 3>; 746 bits = <1 3>;
818 }; 747 };
819 748
820 gpu_speed_bin: gpu-spe !! 749 gpu_speed_bin: gpu_speed_bin@1d2 {
821 reg = <0x1d2 0 750 reg = <0x1d2 0x2>;
822 bits = <5 8>; 751 bits = <5 8>;
823 }; 752 };
824 }; 753 };
825 754
826 sdhc_1: mmc@7c4000 { 755 sdhc_1: mmc@7c4000 {
827 compatible = "qcom,sc7 756 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
828 reg = <0 0x007c4000 0 757 reg = <0 0x007c4000 0 0x1000>,
829 <0 0x007c5000 758 <0 0x007c5000 0 0x1000>;
830 reg-names = "hc", "cqh 759 reg-names = "hc", "cqhci";
831 760
832 iommus = <&apps_smmu 0 761 iommus = <&apps_smmu 0x60 0x0>;
833 interrupts = <GIC_SPI 762 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
834 <GIC_S 763 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
835 interrupt-names = "hc_ 764 interrupt-names = "hc_irq", "pwr_irq";
836 765
837 clocks = <&gcc GCC_SDC 766 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
838 <&gcc GCC_SDC 767 <&gcc GCC_SDCC1_APPS_CLK>,
839 <&rpmhcc RPMH 768 <&rpmhcc RPMH_CXO_CLK>;
840 clock-names = "iface", 769 clock-names = "iface", "core", "xo";
841 interconnects = <&aggr 770 interconnects = <&aggre1_noc MASTER_EMMC 0 &mc_virt SLAVE_EBI1 0>,
842 <&gem_ 771 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_EMMC_CFG 0>;
843 interconnect-names = " 772 interconnect-names = "sdhc-ddr","cpu-sdhc";
844 power-domains = <&rpmh 773 power-domains = <&rpmhpd SC7180_CX>;
845 operating-points-v2 = 774 operating-points-v2 = <&sdhc1_opp_table>;
846 775
847 bus-width = <8>; 776 bus-width = <8>;
848 non-removable; 777 non-removable;
849 supports-cqe; 778 supports-cqe;
850 779
851 mmc-ddr-1_8v; 780 mmc-ddr-1_8v;
852 mmc-hs200-1_8v; 781 mmc-hs200-1_8v;
853 mmc-hs400-1_8v; 782 mmc-hs400-1_8v;
854 mmc-hs400-enhanced-str 783 mmc-hs400-enhanced-strobe;
855 784
856 status = "disabled"; 785 status = "disabled";
857 786
858 sdhc1_opp_table: opp-t 787 sdhc1_opp_table: opp-table {
859 compatible = " 788 compatible = "operating-points-v2";
860 789
861 opp-100000000 790 opp-100000000 {
862 opp-hz 791 opp-hz = /bits/ 64 <100000000>;
863 requir 792 required-opps = <&rpmhpd_opp_low_svs>;
864 opp-pe 793 opp-peak-kBps = <1800000 600000>;
865 opp-av 794 opp-avg-kBps = <100000 0>;
866 }; 795 };
867 796
868 opp-384000000 797 opp-384000000 {
869 opp-hz 798 opp-hz = /bits/ 64 <384000000>;
870 requir 799 required-opps = <&rpmhpd_opp_nom>;
871 opp-pe 800 opp-peak-kBps = <5400000 1600000>;
872 opp-av 801 opp-avg-kBps = <390000 0>;
873 }; 802 };
874 }; 803 };
875 }; 804 };
876 805
877 qupv3_id_0: geniqup@8c0000 { 806 qupv3_id_0: geniqup@8c0000 {
878 compatible = "qcom,gen 807 compatible = "qcom,geni-se-qup";
879 reg = <0 0x008c0000 0 808 reg = <0 0x008c0000 0 0x6000>;
880 clock-names = "m-ahb", 809 clock-names = "m-ahb", "s-ahb";
881 clocks = <&gcc GCC_QUP 810 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
882 <&gcc GCC_QUP 811 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
883 #address-cells = <2>; 812 #address-cells = <2>;
884 #size-cells = <2>; 813 #size-cells = <2>;
885 ranges; 814 ranges;
886 iommus = <&apps_smmu 0 815 iommus = <&apps_smmu 0x43 0x0>;
887 status = "disabled"; 816 status = "disabled";
888 817
889 i2c0: i2c@880000 { 818 i2c0: i2c@880000 {
890 compatible = " 819 compatible = "qcom,geni-i2c";
891 reg = <0 0x008 820 reg = <0 0x00880000 0 0x4000>;
892 clock-names = 821 clock-names = "se";
893 clocks = <&gcc 822 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
894 pinctrl-names 823 pinctrl-names = "default";
895 pinctrl-0 = <& 824 pinctrl-0 = <&qup_i2c0_default>;
896 interrupts = < 825 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
897 #address-cells 826 #address-cells = <1>;
898 #size-cells = 827 #size-cells = <0>;
899 interconnects 828 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
900 829 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
901 830 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
902 interconnect-n 831 interconnect-names = "qup-core", "qup-config",
903 832 "qup-memory";
904 power-domains 833 power-domains = <&rpmhpd SC7180_CX>;
905 required-opps 834 required-opps = <&rpmhpd_opp_low_svs>;
906 status = "disa 835 status = "disabled";
907 }; 836 };
908 837
909 spi0: spi@880000 { 838 spi0: spi@880000 {
910 compatible = " 839 compatible = "qcom,geni-spi";
911 reg = <0 0x008 840 reg = <0 0x00880000 0 0x4000>;
912 clock-names = 841 clock-names = "se";
913 clocks = <&gcc 842 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
914 pinctrl-names 843 pinctrl-names = "default";
915 pinctrl-0 = <& 844 pinctrl-0 = <&qup_spi0_spi>, <&qup_spi0_cs>;
916 interrupts = < 845 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
917 #address-cells 846 #address-cells = <1>;
918 #size-cells = 847 #size-cells = <0>;
919 power-domains 848 power-domains = <&rpmhpd SC7180_CX>;
920 operating-poin 849 operating-points-v2 = <&qup_opp_table>;
921 interconnects 850 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
922 851 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
923 interconnect-n 852 interconnect-names = "qup-core", "qup-config";
924 status = "disa 853 status = "disabled";
925 }; 854 };
926 855
927 uart0: serial@880000 { 856 uart0: serial@880000 {
928 compatible = " 857 compatible = "qcom,geni-uart";
929 reg = <0 0x008 858 reg = <0 0x00880000 0 0x4000>;
930 clock-names = 859 clock-names = "se";
931 clocks = <&gcc 860 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
932 pinctrl-names 861 pinctrl-names = "default";
933 pinctrl-0 = <& 862 pinctrl-0 = <&qup_uart0_default>;
934 interrupts = < 863 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
935 power-domains 864 power-domains = <&rpmhpd SC7180_CX>;
936 operating-poin 865 operating-points-v2 = <&qup_opp_table>;
937 interconnects 866 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
938 867 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
939 interconnect-n 868 interconnect-names = "qup-core", "qup-config";
940 status = "disa 869 status = "disabled";
941 }; 870 };
942 871
943 i2c1: i2c@884000 { 872 i2c1: i2c@884000 {
944 compatible = " 873 compatible = "qcom,geni-i2c";
945 reg = <0 0x008 874 reg = <0 0x00884000 0 0x4000>;
946 clock-names = 875 clock-names = "se";
947 clocks = <&gcc 876 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
948 pinctrl-names 877 pinctrl-names = "default";
949 pinctrl-0 = <& 878 pinctrl-0 = <&qup_i2c1_default>;
950 interrupts = < 879 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
951 #address-cells 880 #address-cells = <1>;
952 #size-cells = 881 #size-cells = <0>;
953 interconnects 882 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
954 883 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
955 884 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
956 interconnect-n 885 interconnect-names = "qup-core", "qup-config",
957 886 "qup-memory";
958 power-domains 887 power-domains = <&rpmhpd SC7180_CX>;
959 required-opps 888 required-opps = <&rpmhpd_opp_low_svs>;
960 status = "disa 889 status = "disabled";
961 }; 890 };
962 891
963 spi1: spi@884000 { 892 spi1: spi@884000 {
964 compatible = " 893 compatible = "qcom,geni-spi";
965 reg = <0 0x008 894 reg = <0 0x00884000 0 0x4000>;
966 clock-names = 895 clock-names = "se";
967 clocks = <&gcc 896 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
968 pinctrl-names 897 pinctrl-names = "default";
969 pinctrl-0 = <& 898 pinctrl-0 = <&qup_spi1_spi>, <&qup_spi1_cs>;
970 interrupts = < 899 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
971 #address-cells 900 #address-cells = <1>;
972 #size-cells = 901 #size-cells = <0>;
973 power-domains 902 power-domains = <&rpmhpd SC7180_CX>;
974 operating-poin 903 operating-points-v2 = <&qup_opp_table>;
975 interconnects 904 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
976 905 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
977 interconnect-n 906 interconnect-names = "qup-core", "qup-config";
978 status = "disa 907 status = "disabled";
979 }; 908 };
980 909
981 uart1: serial@884000 { 910 uart1: serial@884000 {
982 compatible = " 911 compatible = "qcom,geni-uart";
983 reg = <0 0x008 912 reg = <0 0x00884000 0 0x4000>;
984 clock-names = 913 clock-names = "se";
985 clocks = <&gcc 914 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
986 pinctrl-names 915 pinctrl-names = "default";
987 pinctrl-0 = <& 916 pinctrl-0 = <&qup_uart1_default>;
988 interrupts = < 917 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
989 power-domains 918 power-domains = <&rpmhpd SC7180_CX>;
990 operating-poin 919 operating-points-v2 = <&qup_opp_table>;
991 interconnects 920 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
992 921 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
993 interconnect-n 922 interconnect-names = "qup-core", "qup-config";
994 status = "disa 923 status = "disabled";
995 }; 924 };
996 925
997 i2c2: i2c@888000 { 926 i2c2: i2c@888000 {
998 compatible = " 927 compatible = "qcom,geni-i2c";
999 reg = <0 0x008 928 reg = <0 0x00888000 0 0x4000>;
1000 clock-names = 929 clock-names = "se";
1001 clocks = <&gc 930 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1002 pinctrl-names 931 pinctrl-names = "default";
1003 pinctrl-0 = < 932 pinctrl-0 = <&qup_i2c2_default>;
1004 interrupts = 933 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1005 #address-cell 934 #address-cells = <1>;
1006 #size-cells = 935 #size-cells = <0>;
1007 interconnects 936 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1008 937 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1009 938 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1010 interconnect- 939 interconnect-names = "qup-core", "qup-config",
1011 940 "qup-memory";
1012 power-domains 941 power-domains = <&rpmhpd SC7180_CX>;
1013 required-opps 942 required-opps = <&rpmhpd_opp_low_svs>;
1014 status = "dis 943 status = "disabled";
1015 }; 944 };
1016 945
1017 uart2: serial@888000 946 uart2: serial@888000 {
1018 compatible = 947 compatible = "qcom,geni-uart";
1019 reg = <0 0x00 948 reg = <0 0x00888000 0 0x4000>;
1020 clock-names = 949 clock-names = "se";
1021 clocks = <&gc 950 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1022 pinctrl-names 951 pinctrl-names = "default";
1023 pinctrl-0 = < 952 pinctrl-0 = <&qup_uart2_default>;
1024 interrupts = 953 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1025 power-domains 954 power-domains = <&rpmhpd SC7180_CX>;
1026 operating-poi 955 operating-points-v2 = <&qup_opp_table>;
1027 interconnects 956 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1028 957 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1029 interconnect- 958 interconnect-names = "qup-core", "qup-config";
1030 status = "dis 959 status = "disabled";
1031 }; 960 };
1032 961
1033 i2c3: i2c@88c000 { 962 i2c3: i2c@88c000 {
1034 compatible = 963 compatible = "qcom,geni-i2c";
1035 reg = <0 0x00 964 reg = <0 0x0088c000 0 0x4000>;
1036 clock-names = 965 clock-names = "se";
1037 clocks = <&gc 966 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1038 pinctrl-names 967 pinctrl-names = "default";
1039 pinctrl-0 = < 968 pinctrl-0 = <&qup_i2c3_default>;
1040 interrupts = 969 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1041 #address-cell 970 #address-cells = <1>;
1042 #size-cells = 971 #size-cells = <0>;
1043 interconnects 972 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1044 973 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1045 974 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1046 interconnect- 975 interconnect-names = "qup-core", "qup-config",
1047 976 "qup-memory";
1048 power-domains 977 power-domains = <&rpmhpd SC7180_CX>;
1049 required-opps 978 required-opps = <&rpmhpd_opp_low_svs>;
1050 status = "dis 979 status = "disabled";
1051 }; 980 };
1052 981
1053 spi3: spi@88c000 { 982 spi3: spi@88c000 {
1054 compatible = 983 compatible = "qcom,geni-spi";
1055 reg = <0 0x00 984 reg = <0 0x0088c000 0 0x4000>;
1056 clock-names = 985 clock-names = "se";
1057 clocks = <&gc 986 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1058 pinctrl-names 987 pinctrl-names = "default";
1059 pinctrl-0 = < 988 pinctrl-0 = <&qup_spi3_spi>, <&qup_spi3_cs>;
1060 interrupts = 989 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1061 #address-cell 990 #address-cells = <1>;
1062 #size-cells = 991 #size-cells = <0>;
1063 power-domains 992 power-domains = <&rpmhpd SC7180_CX>;
1064 operating-poi 993 operating-points-v2 = <&qup_opp_table>;
1065 interconnects 994 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1066 995 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1067 interconnect- 996 interconnect-names = "qup-core", "qup-config";
1068 status = "dis 997 status = "disabled";
1069 }; 998 };
1070 999
1071 uart3: serial@88c000 1000 uart3: serial@88c000 {
1072 compatible = 1001 compatible = "qcom,geni-uart";
1073 reg = <0 0x00 1002 reg = <0 0x0088c000 0 0x4000>;
1074 clock-names = 1003 clock-names = "se";
1075 clocks = <&gc 1004 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1076 pinctrl-names 1005 pinctrl-names = "default";
1077 pinctrl-0 = < 1006 pinctrl-0 = <&qup_uart3_default>;
1078 interrupts = 1007 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1079 power-domains 1008 power-domains = <&rpmhpd SC7180_CX>;
1080 operating-poi 1009 operating-points-v2 = <&qup_opp_table>;
1081 interconnects 1010 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1082 1011 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1083 interconnect- 1012 interconnect-names = "qup-core", "qup-config";
1084 status = "dis 1013 status = "disabled";
1085 }; 1014 };
1086 1015
1087 i2c4: i2c@890000 { 1016 i2c4: i2c@890000 {
1088 compatible = 1017 compatible = "qcom,geni-i2c";
1089 reg = <0 0x00 1018 reg = <0 0x00890000 0 0x4000>;
1090 clock-names = 1019 clock-names = "se";
1091 clocks = <&gc 1020 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1092 pinctrl-names 1021 pinctrl-names = "default";
1093 pinctrl-0 = < 1022 pinctrl-0 = <&qup_i2c4_default>;
1094 interrupts = 1023 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1095 #address-cell 1024 #address-cells = <1>;
1096 #size-cells = 1025 #size-cells = <0>;
1097 interconnects 1026 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1098 1027 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1099 1028 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1100 interconnect- 1029 interconnect-names = "qup-core", "qup-config",
1101 1030 "qup-memory";
1102 power-domains 1031 power-domains = <&rpmhpd SC7180_CX>;
1103 required-opps 1032 required-opps = <&rpmhpd_opp_low_svs>;
1104 status = "dis 1033 status = "disabled";
1105 }; 1034 };
1106 1035
1107 uart4: serial@890000 1036 uart4: serial@890000 {
1108 compatible = 1037 compatible = "qcom,geni-uart";
1109 reg = <0 0x00 1038 reg = <0 0x00890000 0 0x4000>;
1110 clock-names = 1039 clock-names = "se";
1111 clocks = <&gc 1040 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1112 pinctrl-names 1041 pinctrl-names = "default";
1113 pinctrl-0 = < 1042 pinctrl-0 = <&qup_uart4_default>;
1114 interrupts = 1043 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1115 power-domains 1044 power-domains = <&rpmhpd SC7180_CX>;
1116 operating-poi 1045 operating-points-v2 = <&qup_opp_table>;
1117 interconnects 1046 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1118 1047 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1119 interconnect- 1048 interconnect-names = "qup-core", "qup-config";
1120 status = "dis 1049 status = "disabled";
1121 }; 1050 };
1122 1051
1123 i2c5: i2c@894000 { 1052 i2c5: i2c@894000 {
1124 compatible = 1053 compatible = "qcom,geni-i2c";
1125 reg = <0 0x00 1054 reg = <0 0x00894000 0 0x4000>;
1126 clock-names = 1055 clock-names = "se";
1127 clocks = <&gc 1056 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1128 pinctrl-names 1057 pinctrl-names = "default";
1129 pinctrl-0 = < 1058 pinctrl-0 = <&qup_i2c5_default>;
1130 interrupts = 1059 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1131 #address-cell 1060 #address-cells = <1>;
1132 #size-cells = 1061 #size-cells = <0>;
1133 interconnects 1062 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1134 1063 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1135 1064 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1136 interconnect- 1065 interconnect-names = "qup-core", "qup-config",
1137 1066 "qup-memory";
1138 power-domains 1067 power-domains = <&rpmhpd SC7180_CX>;
1139 required-opps 1068 required-opps = <&rpmhpd_opp_low_svs>;
1140 status = "dis 1069 status = "disabled";
1141 }; 1070 };
1142 1071
1143 spi5: spi@894000 { 1072 spi5: spi@894000 {
1144 compatible = 1073 compatible = "qcom,geni-spi";
1145 reg = <0 0x00 1074 reg = <0 0x00894000 0 0x4000>;
1146 clock-names = 1075 clock-names = "se";
1147 clocks = <&gc 1076 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1148 pinctrl-names 1077 pinctrl-names = "default";
1149 pinctrl-0 = < 1078 pinctrl-0 = <&qup_spi5_spi>, <&qup_spi5_cs>;
1150 interrupts = 1079 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1151 #address-cell 1080 #address-cells = <1>;
1152 #size-cells = 1081 #size-cells = <0>;
1153 power-domains 1082 power-domains = <&rpmhpd SC7180_CX>;
1154 operating-poi 1083 operating-points-v2 = <&qup_opp_table>;
1155 interconnects 1084 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1156 1085 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1157 interconnect- 1086 interconnect-names = "qup-core", "qup-config";
1158 status = "dis 1087 status = "disabled";
1159 }; 1088 };
1160 1089
1161 uart5: serial@894000 1090 uart5: serial@894000 {
1162 compatible = 1091 compatible = "qcom,geni-uart";
1163 reg = <0 0x00 1092 reg = <0 0x00894000 0 0x4000>;
1164 clock-names = 1093 clock-names = "se";
1165 clocks = <&gc 1094 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1166 pinctrl-names 1095 pinctrl-names = "default";
1167 pinctrl-0 = < 1096 pinctrl-0 = <&qup_uart5_default>;
1168 interrupts = 1097 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1169 power-domains 1098 power-domains = <&rpmhpd SC7180_CX>;
1170 operating-poi 1099 operating-points-v2 = <&qup_opp_table>;
1171 interconnects 1100 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1172 1101 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1173 interconnect- 1102 interconnect-names = "qup-core", "qup-config";
1174 status = "dis 1103 status = "disabled";
1175 }; 1104 };
1176 }; 1105 };
1177 1106
1178 qupv3_id_1: geniqup@ac0000 { 1107 qupv3_id_1: geniqup@ac0000 {
1179 compatible = "qcom,ge 1108 compatible = "qcom,geni-se-qup";
1180 reg = <0 0x00ac0000 0 1109 reg = <0 0x00ac0000 0 0x6000>;
1181 clock-names = "m-ahb" 1110 clock-names = "m-ahb", "s-ahb";
1182 clocks = <&gcc GCC_QU 1111 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1183 <&gcc GCC_QU 1112 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1184 #address-cells = <2>; 1113 #address-cells = <2>;
1185 #size-cells = <2>; 1114 #size-cells = <2>;
1186 ranges; 1115 ranges;
1187 iommus = <&apps_smmu 1116 iommus = <&apps_smmu 0x4c3 0x0>;
1188 status = "disabled"; 1117 status = "disabled";
1189 1118
1190 i2c6: i2c@a80000 { 1119 i2c6: i2c@a80000 {
1191 compatible = 1120 compatible = "qcom,geni-i2c";
1192 reg = <0 0x00 1121 reg = <0 0x00a80000 0 0x4000>;
1193 clock-names = 1122 clock-names = "se";
1194 clocks = <&gc 1123 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1195 pinctrl-names 1124 pinctrl-names = "default";
1196 pinctrl-0 = < 1125 pinctrl-0 = <&qup_i2c6_default>;
1197 interrupts = 1126 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1198 #address-cell 1127 #address-cells = <1>;
1199 #size-cells = 1128 #size-cells = <0>;
1200 interconnects 1129 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1201 1130 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1202 1131 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1203 interconnect- 1132 interconnect-names = "qup-core", "qup-config",
1204 1133 "qup-memory";
1205 power-domains 1134 power-domains = <&rpmhpd SC7180_CX>;
1206 required-opps 1135 required-opps = <&rpmhpd_opp_low_svs>;
1207 status = "dis 1136 status = "disabled";
1208 }; 1137 };
1209 1138
1210 spi6: spi@a80000 { 1139 spi6: spi@a80000 {
1211 compatible = 1140 compatible = "qcom,geni-spi";
1212 reg = <0 0x00 1141 reg = <0 0x00a80000 0 0x4000>;
1213 clock-names = 1142 clock-names = "se";
1214 clocks = <&gc 1143 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1215 pinctrl-names 1144 pinctrl-names = "default";
1216 pinctrl-0 = < 1145 pinctrl-0 = <&qup_spi6_spi>, <&qup_spi6_cs>;
1217 interrupts = 1146 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1218 #address-cell 1147 #address-cells = <1>;
1219 #size-cells = 1148 #size-cells = <0>;
1220 power-domains 1149 power-domains = <&rpmhpd SC7180_CX>;
1221 operating-poi 1150 operating-points-v2 = <&qup_opp_table>;
1222 interconnects 1151 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1223 1152 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1224 interconnect- 1153 interconnect-names = "qup-core", "qup-config";
1225 status = "dis 1154 status = "disabled";
1226 }; 1155 };
1227 1156
1228 uart6: serial@a80000 1157 uart6: serial@a80000 {
1229 compatible = 1158 compatible = "qcom,geni-uart";
1230 reg = <0 0x00 1159 reg = <0 0x00a80000 0 0x4000>;
1231 clock-names = 1160 clock-names = "se";
1232 clocks = <&gc 1161 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1233 pinctrl-names 1162 pinctrl-names = "default";
1234 pinctrl-0 = < 1163 pinctrl-0 = <&qup_uart6_default>;
1235 interrupts = 1164 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1236 power-domains 1165 power-domains = <&rpmhpd SC7180_CX>;
1237 operating-poi 1166 operating-points-v2 = <&qup_opp_table>;
1238 interconnects 1167 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1239 1168 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1240 interconnect- 1169 interconnect-names = "qup-core", "qup-config";
1241 status = "dis 1170 status = "disabled";
1242 }; 1171 };
1243 1172
1244 i2c7: i2c@a84000 { 1173 i2c7: i2c@a84000 {
1245 compatible = 1174 compatible = "qcom,geni-i2c";
1246 reg = <0 0x00 1175 reg = <0 0x00a84000 0 0x4000>;
1247 clock-names = 1176 clock-names = "se";
1248 clocks = <&gc 1177 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1249 pinctrl-names 1178 pinctrl-names = "default";
1250 pinctrl-0 = < 1179 pinctrl-0 = <&qup_i2c7_default>;
1251 interrupts = 1180 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1252 #address-cell 1181 #address-cells = <1>;
1253 #size-cells = 1182 #size-cells = <0>;
1254 interconnects 1183 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1255 1184 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1256 1185 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1257 interconnect- 1186 interconnect-names = "qup-core", "qup-config",
1258 1187 "qup-memory";
1259 power-domains 1188 power-domains = <&rpmhpd SC7180_CX>;
1260 required-opps 1189 required-opps = <&rpmhpd_opp_low_svs>;
1261 status = "dis 1190 status = "disabled";
1262 }; 1191 };
1263 1192
1264 uart7: serial@a84000 1193 uart7: serial@a84000 {
1265 compatible = 1194 compatible = "qcom,geni-uart";
1266 reg = <0 0x00 1195 reg = <0 0x00a84000 0 0x4000>;
1267 clock-names = 1196 clock-names = "se";
1268 clocks = <&gc 1197 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1269 pinctrl-names 1198 pinctrl-names = "default";
1270 pinctrl-0 = < 1199 pinctrl-0 = <&qup_uart7_default>;
1271 interrupts = 1200 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1272 power-domains 1201 power-domains = <&rpmhpd SC7180_CX>;
1273 operating-poi 1202 operating-points-v2 = <&qup_opp_table>;
1274 interconnects 1203 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1275 1204 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1276 interconnect- 1205 interconnect-names = "qup-core", "qup-config";
1277 status = "dis 1206 status = "disabled";
1278 }; 1207 };
1279 1208
1280 i2c8: i2c@a88000 { 1209 i2c8: i2c@a88000 {
1281 compatible = 1210 compatible = "qcom,geni-i2c";
1282 reg = <0 0x00 1211 reg = <0 0x00a88000 0 0x4000>;
1283 clock-names = 1212 clock-names = "se";
1284 clocks = <&gc 1213 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1285 pinctrl-names 1214 pinctrl-names = "default";
1286 pinctrl-0 = < 1215 pinctrl-0 = <&qup_i2c8_default>;
1287 interrupts = 1216 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1288 #address-cell 1217 #address-cells = <1>;
1289 #size-cells = 1218 #size-cells = <0>;
1290 interconnects 1219 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1291 1220 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1292 1221 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1293 interconnect- 1222 interconnect-names = "qup-core", "qup-config",
1294 1223 "qup-memory";
1295 power-domains 1224 power-domains = <&rpmhpd SC7180_CX>;
1296 required-opps 1225 required-opps = <&rpmhpd_opp_low_svs>;
1297 status = "dis 1226 status = "disabled";
1298 }; 1227 };
1299 1228
1300 spi8: spi@a88000 { 1229 spi8: spi@a88000 {
1301 compatible = 1230 compatible = "qcom,geni-spi";
1302 reg = <0 0x00 1231 reg = <0 0x00a88000 0 0x4000>;
1303 clock-names = 1232 clock-names = "se";
1304 clocks = <&gc 1233 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1305 pinctrl-names 1234 pinctrl-names = "default";
1306 pinctrl-0 = < 1235 pinctrl-0 = <&qup_spi8_spi>, <&qup_spi8_cs>;
1307 interrupts = 1236 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1308 #address-cell 1237 #address-cells = <1>;
1309 #size-cells = 1238 #size-cells = <0>;
1310 power-domains 1239 power-domains = <&rpmhpd SC7180_CX>;
1311 operating-poi 1240 operating-points-v2 = <&qup_opp_table>;
1312 interconnects 1241 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1313 1242 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1314 interconnect- 1243 interconnect-names = "qup-core", "qup-config";
1315 status = "dis 1244 status = "disabled";
1316 }; 1245 };
1317 1246
1318 uart8: serial@a88000 1247 uart8: serial@a88000 {
1319 compatible = 1248 compatible = "qcom,geni-debug-uart";
1320 reg = <0 0x00 1249 reg = <0 0x00a88000 0 0x4000>;
1321 clock-names = 1250 clock-names = "se";
1322 clocks = <&gc 1251 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1323 pinctrl-names 1252 pinctrl-names = "default";
1324 pinctrl-0 = < 1253 pinctrl-0 = <&qup_uart8_default>;
1325 interrupts = 1254 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1326 power-domains 1255 power-domains = <&rpmhpd SC7180_CX>;
1327 operating-poi 1256 operating-points-v2 = <&qup_opp_table>;
1328 interconnects 1257 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1329 1258 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1330 interconnect- 1259 interconnect-names = "qup-core", "qup-config";
1331 status = "dis 1260 status = "disabled";
1332 }; 1261 };
1333 1262
1334 i2c9: i2c@a8c000 { 1263 i2c9: i2c@a8c000 {
1335 compatible = 1264 compatible = "qcom,geni-i2c";
1336 reg = <0 0x00 1265 reg = <0 0x00a8c000 0 0x4000>;
1337 clock-names = 1266 clock-names = "se";
1338 clocks = <&gc 1267 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1339 pinctrl-names 1268 pinctrl-names = "default";
1340 pinctrl-0 = < 1269 pinctrl-0 = <&qup_i2c9_default>;
1341 interrupts = 1270 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1342 #address-cell 1271 #address-cells = <1>;
1343 #size-cells = 1272 #size-cells = <0>;
1344 interconnects 1273 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1345 1274 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1346 1275 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1347 interconnect- 1276 interconnect-names = "qup-core", "qup-config",
1348 1277 "qup-memory";
1349 power-domains 1278 power-domains = <&rpmhpd SC7180_CX>;
1350 required-opps 1279 required-opps = <&rpmhpd_opp_low_svs>;
1351 status = "dis 1280 status = "disabled";
1352 }; 1281 };
1353 1282
1354 uart9: serial@a8c000 1283 uart9: serial@a8c000 {
1355 compatible = 1284 compatible = "qcom,geni-uart";
1356 reg = <0 0x00 1285 reg = <0 0x00a8c000 0 0x4000>;
1357 clock-names = 1286 clock-names = "se";
1358 clocks = <&gc 1287 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1359 pinctrl-names 1288 pinctrl-names = "default";
1360 pinctrl-0 = < 1289 pinctrl-0 = <&qup_uart9_default>;
1361 interrupts = 1290 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1362 power-domains 1291 power-domains = <&rpmhpd SC7180_CX>;
1363 operating-poi 1292 operating-points-v2 = <&qup_opp_table>;
1364 interconnects 1293 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1365 1294 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1366 interconnect- 1295 interconnect-names = "qup-core", "qup-config";
1367 status = "dis 1296 status = "disabled";
1368 }; 1297 };
1369 1298
1370 i2c10: i2c@a90000 { 1299 i2c10: i2c@a90000 {
1371 compatible = 1300 compatible = "qcom,geni-i2c";
1372 reg = <0 0x00 1301 reg = <0 0x00a90000 0 0x4000>;
1373 clock-names = 1302 clock-names = "se";
1374 clocks = <&gc 1303 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1375 pinctrl-names 1304 pinctrl-names = "default";
1376 pinctrl-0 = < 1305 pinctrl-0 = <&qup_i2c10_default>;
1377 interrupts = 1306 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1378 #address-cell 1307 #address-cells = <1>;
1379 #size-cells = 1308 #size-cells = <0>;
1380 interconnects 1309 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1381 1310 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1382 1311 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1383 interconnect- 1312 interconnect-names = "qup-core", "qup-config",
1384 1313 "qup-memory";
1385 power-domains 1314 power-domains = <&rpmhpd SC7180_CX>;
1386 required-opps 1315 required-opps = <&rpmhpd_opp_low_svs>;
1387 status = "dis 1316 status = "disabled";
1388 }; 1317 };
1389 1318
1390 spi10: spi@a90000 { 1319 spi10: spi@a90000 {
1391 compatible = 1320 compatible = "qcom,geni-spi";
1392 reg = <0 0x00 1321 reg = <0 0x00a90000 0 0x4000>;
1393 clock-names = 1322 clock-names = "se";
1394 clocks = <&gc 1323 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1395 pinctrl-names 1324 pinctrl-names = "default";
1396 pinctrl-0 = < 1325 pinctrl-0 = <&qup_spi10_spi>, <&qup_spi10_cs>;
1397 interrupts = 1326 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1398 #address-cell 1327 #address-cells = <1>;
1399 #size-cells = 1328 #size-cells = <0>;
1400 power-domains 1329 power-domains = <&rpmhpd SC7180_CX>;
1401 operating-poi 1330 operating-points-v2 = <&qup_opp_table>;
1402 interconnects 1331 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1403 1332 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1404 interconnect- 1333 interconnect-names = "qup-core", "qup-config";
1405 status = "dis 1334 status = "disabled";
1406 }; 1335 };
1407 1336
1408 uart10: serial@a90000 1337 uart10: serial@a90000 {
1409 compatible = 1338 compatible = "qcom,geni-uart";
1410 reg = <0 0x00 1339 reg = <0 0x00a90000 0 0x4000>;
1411 clock-names = 1340 clock-names = "se";
1412 clocks = <&gc 1341 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1413 pinctrl-names 1342 pinctrl-names = "default";
1414 pinctrl-0 = < 1343 pinctrl-0 = <&qup_uart10_default>;
1415 interrupts = 1344 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1416 power-domains 1345 power-domains = <&rpmhpd SC7180_CX>;
1417 operating-poi 1346 operating-points-v2 = <&qup_opp_table>;
1418 interconnects 1347 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1419 1348 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1420 interconnect- 1349 interconnect-names = "qup-core", "qup-config";
1421 status = "dis 1350 status = "disabled";
1422 }; 1351 };
1423 1352
1424 i2c11: i2c@a94000 { 1353 i2c11: i2c@a94000 {
1425 compatible = 1354 compatible = "qcom,geni-i2c";
1426 reg = <0 0x00 1355 reg = <0 0x00a94000 0 0x4000>;
1427 clock-names = 1356 clock-names = "se";
1428 clocks = <&gc 1357 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1429 pinctrl-names 1358 pinctrl-names = "default";
1430 pinctrl-0 = < 1359 pinctrl-0 = <&qup_i2c11_default>;
1431 interrupts = 1360 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1432 #address-cell 1361 #address-cells = <1>;
1433 #size-cells = 1362 #size-cells = <0>;
1434 interconnects 1363 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1435 1364 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1436 1365 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1437 interconnect- 1366 interconnect-names = "qup-core", "qup-config",
1438 1367 "qup-memory";
1439 power-domains 1368 power-domains = <&rpmhpd SC7180_CX>;
1440 required-opps 1369 required-opps = <&rpmhpd_opp_low_svs>;
1441 status = "dis 1370 status = "disabled";
1442 }; 1371 };
1443 1372
1444 spi11: spi@a94000 { 1373 spi11: spi@a94000 {
1445 compatible = 1374 compatible = "qcom,geni-spi";
1446 reg = <0 0x00 1375 reg = <0 0x00a94000 0 0x4000>;
1447 clock-names = 1376 clock-names = "se";
1448 clocks = <&gc 1377 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1449 pinctrl-names 1378 pinctrl-names = "default";
1450 pinctrl-0 = < 1379 pinctrl-0 = <&qup_spi11_spi>, <&qup_spi11_cs>;
1451 interrupts = 1380 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1452 #address-cell 1381 #address-cells = <1>;
1453 #size-cells = 1382 #size-cells = <0>;
1454 power-domains 1383 power-domains = <&rpmhpd SC7180_CX>;
1455 operating-poi 1384 operating-points-v2 = <&qup_opp_table>;
1456 interconnects 1385 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1457 1386 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1458 interconnect- 1387 interconnect-names = "qup-core", "qup-config";
1459 status = "dis 1388 status = "disabled";
1460 }; 1389 };
1461 1390
1462 uart11: serial@a94000 1391 uart11: serial@a94000 {
1463 compatible = 1392 compatible = "qcom,geni-uart";
1464 reg = <0 0x00 1393 reg = <0 0x00a94000 0 0x4000>;
1465 clock-names = 1394 clock-names = "se";
1466 clocks = <&gc 1395 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1467 pinctrl-names 1396 pinctrl-names = "default";
1468 pinctrl-0 = < 1397 pinctrl-0 = <&qup_uart11_default>;
1469 interrupts = 1398 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1470 power-domains 1399 power-domains = <&rpmhpd SC7180_CX>;
1471 operating-poi 1400 operating-points-v2 = <&qup_opp_table>;
1472 interconnects 1401 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1473 1402 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1474 interconnect- 1403 interconnect-names = "qup-core", "qup-config";
1475 status = "dis 1404 status = "disabled";
1476 }; 1405 };
1477 }; 1406 };
1478 1407
1479 config_noc: interconnect@1500 1408 config_noc: interconnect@1500000 {
1480 compatible = "qcom,sc 1409 compatible = "qcom,sc7180-config-noc";
1481 reg = <0 0x01500000 0 1410 reg = <0 0x01500000 0 0x28000>;
1482 #interconnect-cells = 1411 #interconnect-cells = <2>;
1483 qcom,bcm-voters = <&a 1412 qcom,bcm-voters = <&apps_bcm_voter>;
1484 }; 1413 };
1485 1414
1486 system_noc: interconnect@1620 1415 system_noc: interconnect@1620000 {
1487 compatible = "qcom,sc 1416 compatible = "qcom,sc7180-system-noc";
1488 reg = <0 0x01620000 0 1417 reg = <0 0x01620000 0 0x17080>;
1489 #interconnect-cells = 1418 #interconnect-cells = <2>;
1490 qcom,bcm-voters = <&a 1419 qcom,bcm-voters = <&apps_bcm_voter>;
1491 }; 1420 };
1492 1421
1493 mc_virt: interconnect@1638000 1422 mc_virt: interconnect@1638000 {
1494 compatible = "qcom,sc 1423 compatible = "qcom,sc7180-mc-virt";
1495 reg = <0 0x01638000 0 1424 reg = <0 0x01638000 0 0x1000>;
1496 #interconnect-cells = 1425 #interconnect-cells = <2>;
1497 qcom,bcm-voters = <&a 1426 qcom,bcm-voters = <&apps_bcm_voter>;
1498 }; 1427 };
1499 1428
1500 qup_virt: interconnect@165000 1429 qup_virt: interconnect@1650000 {
1501 compatible = "qcom,sc 1430 compatible = "qcom,sc7180-qup-virt";
1502 reg = <0 0x01650000 0 1431 reg = <0 0x01650000 0 0x1000>;
1503 #interconnect-cells = 1432 #interconnect-cells = <2>;
1504 qcom,bcm-voters = <&a 1433 qcom,bcm-voters = <&apps_bcm_voter>;
1505 }; 1434 };
1506 1435
1507 aggre1_noc: interconnect@16e0 1436 aggre1_noc: interconnect@16e0000 {
1508 compatible = "qcom,sc 1437 compatible = "qcom,sc7180-aggre1-noc";
1509 reg = <0 0x016e0000 0 1438 reg = <0 0x016e0000 0 0x15080>;
1510 #interconnect-cells = 1439 #interconnect-cells = <2>;
1511 qcom,bcm-voters = <&a 1440 qcom,bcm-voters = <&apps_bcm_voter>;
1512 }; 1441 };
1513 1442
1514 aggre2_noc: interconnect@1705 1443 aggre2_noc: interconnect@1705000 {
1515 compatible = "qcom,sc 1444 compatible = "qcom,sc7180-aggre2-noc";
1516 reg = <0 0x01705000 0 1445 reg = <0 0x01705000 0 0x9000>;
1517 #interconnect-cells = 1446 #interconnect-cells = <2>;
1518 qcom,bcm-voters = <&a 1447 qcom,bcm-voters = <&apps_bcm_voter>;
1519 }; 1448 };
1520 1449
1521 compute_noc: interconnect@170 1450 compute_noc: interconnect@170e000 {
1522 compatible = "qcom,sc 1451 compatible = "qcom,sc7180-compute-noc";
1523 reg = <0 0x0170e000 0 1452 reg = <0 0x0170e000 0 0x6000>;
1524 #interconnect-cells = 1453 #interconnect-cells = <2>;
1525 qcom,bcm-voters = <&a 1454 qcom,bcm-voters = <&apps_bcm_voter>;
1526 }; 1455 };
1527 1456
1528 mmss_noc: interconnect@174000 1457 mmss_noc: interconnect@1740000 {
1529 compatible = "qcom,sc 1458 compatible = "qcom,sc7180-mmss-noc";
1530 reg = <0 0x01740000 0 1459 reg = <0 0x01740000 0 0x1c100>;
1531 #interconnect-cells = 1460 #interconnect-cells = <2>;
1532 qcom,bcm-voters = <&a 1461 qcom,bcm-voters = <&apps_bcm_voter>;
1533 }; 1462 };
1534 1463
1535 ufs_mem_hc: ufshc@1d84000 { <<
1536 compatible = "qcom,sc <<
1537 "jedec,u <<
1538 reg = <0 0x01d84000 0 <<
1539 interrupts = <GIC_SPI <<
1540 phys = <&ufs_mem_phy> <<
1541 phy-names = "ufsphy"; <<
1542 lanes-per-direction = <<
1543 #reset-cells = <1>; <<
1544 resets = <&gcc GCC_UF <<
1545 reset-names = "rst"; <<
1546 <<
1547 power-domains = <&gcc <<
1548 <<
1549 iommus = <&apps_smmu <<
1550 <<
1551 clock-names = "core_c <<
1552 "bus_ag <<
1553 "iface_ <<
1554 "core_c <<
1555 "ref_cl <<
1556 "tx_lan <<
1557 "rx_lan <<
1558 clocks = <&gcc GCC_UF <<
1559 <&gcc GCC_AG <<
1560 <&gcc GCC_UF <<
1561 <&gcc GCC_UF <<
1562 <&rpmhcc RPM <<
1563 <&gcc GCC_UF <<
1564 <&gcc GCC_UF <<
1565 freq-table-hz = <5000 <<
1566 <0 0> <<
1567 <0 0> <<
1568 <3750 <<
1569 <0 0> <<
1570 <0 0> <<
1571 <0 0> <<
1572 <<
1573 interconnects = <&agg <<
1574 &mc_ <<
1575 <&gem <<
1576 &con <<
1577 interconnect-names = <<
1578 <<
1579 qcom,ice = <&ice>; <<
1580 <<
1581 status = "disabled"; <<
1582 }; <<
1583 <<
1584 ufs_mem_phy: phy@1d87000 { <<
1585 compatible = "qcom,sc <<
1586 reg = <0 0x01d87000 0 <<
1587 clocks = <&rpmhcc RPM <<
1588 <&gcc GCC_UF <<
1589 <&gcc GCC_UF <<
1590 clock-names = "ref", <<
1591 "ref_au <<
1592 "qref"; <<
1593 power-domains = <&gcc <<
1594 resets = <&ufs_mem_hc <<
1595 reset-names = "ufsphy <<
1596 #phy-cells = <0>; <<
1597 status = "disabled"; <<
1598 }; <<
1599 <<
1600 ice: crypto@1d90000 { <<
1601 compatible = "qcom,sc <<
1602 "qcom,in <<
1603 reg = <0 0x01d90000 0 <<
1604 clocks = <&gcc GCC_UF <<
1605 }; <<
1606 <<
1607 ipa: ipa@1e40000 { 1464 ipa: ipa@1e40000 {
1608 compatible = "qcom,sc 1465 compatible = "qcom,sc7180-ipa";
1609 1466
1610 iommus = <&apps_smmu 1467 iommus = <&apps_smmu 0x440 0x0>,
1611 <&apps_smmu 1468 <&apps_smmu 0x442 0x0>;
1612 reg = <0 0x01e40000 0 1469 reg = <0 0x01e40000 0 0x7000>,
1613 <0 0x01e47000 0 1470 <0 0x01e47000 0 0x2000>,
1614 <0 0x01e04000 0 1471 <0 0x01e04000 0 0x2c000>;
1615 reg-names = "ipa-reg" 1472 reg-names = "ipa-reg",
1616 "ipa-shar 1473 "ipa-shared",
1617 "gsi"; 1474 "gsi";
1618 1475
1619 interrupts-extended = 1476 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
1620 1477 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
1621 1478 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1622 1479 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
1623 interrupt-names = "ip 1480 interrupt-names = "ipa",
1624 "gs 1481 "gsi",
1625 "ip 1482 "ipa-clock-query",
1626 "ip 1483 "ipa-setup-ready";
1627 1484
1628 clocks = <&rpmhcc RPM 1485 clocks = <&rpmhcc RPMH_IPA_CLK>;
1629 clock-names = "core"; 1486 clock-names = "core";
1630 1487
1631 interconnects = <&agg 1488 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
1632 <&agg 1489 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>,
1633 <&gem 1490 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
1634 interconnect-names = 1491 interconnect-names = "memory",
1635 1492 "imem",
1636 1493 "config";
1637 1494
1638 qcom,qmp = <&aoss_qmp 1495 qcom,qmp = <&aoss_qmp>;
1639 1496
1640 qcom,smem-states = <& 1497 qcom,smem-states = <&ipa_smp2p_out 0>,
1641 <& 1498 <&ipa_smp2p_out 1>;
1642 qcom,smem-state-names 1499 qcom,smem-state-names = "ipa-clock-enabled-valid",
1643 1500 "ipa-clock-enabled";
1644 1501
1645 status = "disabled"; 1502 status = "disabled";
1646 }; 1503 };
1647 1504
1648 tcsr_mutex: hwlock@1f40000 { 1505 tcsr_mutex: hwlock@1f40000 {
1649 compatible = "qcom,tc 1506 compatible = "qcom,tcsr-mutex";
1650 reg = <0 0x01f40000 0 1507 reg = <0 0x01f40000 0 0x20000>;
1651 #hwlock-cells = <1>; 1508 #hwlock-cells = <1>;
1652 }; 1509 };
1653 1510
1654 tcsr_regs_1: syscon@1f60000 { 1511 tcsr_regs_1: syscon@1f60000 {
1655 compatible = "qcom,sc 1512 compatible = "qcom,sc7180-tcsr", "syscon";
1656 reg = <0 0x01f60000 0 1513 reg = <0 0x01f60000 0 0x20000>;
1657 }; 1514 };
1658 1515
1659 tcsr_regs_2: syscon@1fc0000 { 1516 tcsr_regs_2: syscon@1fc0000 {
1660 compatible = "qcom,sc 1517 compatible = "qcom,sc7180-tcsr", "syscon";
1661 reg = <0 0x01fc0000 0 1518 reg = <0 0x01fc0000 0 0x40000>;
1662 }; 1519 };
1663 1520
1664 tlmm: pinctrl@3500000 { 1521 tlmm: pinctrl@3500000 {
1665 compatible = "qcom,sc 1522 compatible = "qcom,sc7180-pinctrl";
1666 reg = <0 0x03500000 0 1523 reg = <0 0x03500000 0 0x300000>,
1667 <0 0x03900000 0 1524 <0 0x03900000 0 0x300000>,
1668 <0 0x03d00000 0 1525 <0 0x03d00000 0 0x300000>;
1669 reg-names = "west", " 1526 reg-names = "west", "north", "south";
1670 interrupts = <GIC_SPI 1527 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1671 gpio-controller; 1528 gpio-controller;
1672 #gpio-cells = <2>; 1529 #gpio-cells = <2>;
1673 interrupt-controller; 1530 interrupt-controller;
1674 #interrupt-cells = <2 1531 #interrupt-cells = <2>;
1675 gpio-ranges = <&tlmm 1532 gpio-ranges = <&tlmm 0 0 120>;
1676 wakeup-parent = <&pdc 1533 wakeup-parent = <&pdc>;
1677 1534
1678 dp_hot_plug_det: dp-h 1535 dp_hot_plug_det: dp-hot-plug-det-state {
1679 pins = "gpio1 1536 pins = "gpio117";
1680 function = "d 1537 function = "dp_hot";
1681 }; 1538 };
1682 1539
1683 qspi_clk: qspi-clk-st 1540 qspi_clk: qspi-clk-state {
1684 pins = "gpio6 1541 pins = "gpio63";
1685 function = "q 1542 function = "qspi_clk";
1686 }; 1543 };
1687 1544
1688 qspi_cs0: qspi-cs0-st 1545 qspi_cs0: qspi-cs0-state {
1689 pins = "gpio6 1546 pins = "gpio68";
1690 function = "q 1547 function = "qspi_cs";
1691 }; 1548 };
1692 1549
1693 qspi_cs1: qspi-cs1-st 1550 qspi_cs1: qspi-cs1-state {
1694 pins = "gpio7 1551 pins = "gpio72";
1695 function = "q 1552 function = "qspi_cs";
1696 }; 1553 };
1697 1554
1698 qspi_data0: qspi-data 1555 qspi_data0: qspi-data0-state {
1699 pins = "gpio6 1556 pins = "gpio64";
1700 function = "q 1557 function = "qspi_data";
1701 }; 1558 };
1702 1559
1703 qspi_data1: qspi-data 1560 qspi_data1: qspi-data1-state {
1704 pins = "gpio6 1561 pins = "gpio65";
1705 function = "q 1562 function = "qspi_data";
1706 }; 1563 };
1707 1564
1708 qspi_data23: qspi-dat 1565 qspi_data23: qspi-data23-state {
1709 pins = "gpio6 1566 pins = "gpio66", "gpio67";
1710 function = "q 1567 function = "qspi_data";
1711 }; 1568 };
1712 1569
1713 qup_i2c0_default: qup 1570 qup_i2c0_default: qup-i2c0-default-state {
1714 pins = "gpio3 1571 pins = "gpio34", "gpio35";
1715 function = "q 1572 function = "qup00";
1716 }; 1573 };
1717 1574
1718 qup_i2c1_default: qup 1575 qup_i2c1_default: qup-i2c1-default-state {
1719 pins = "gpio0 1576 pins = "gpio0", "gpio1";
1720 function = "q 1577 function = "qup01";
1721 }; 1578 };
1722 1579
1723 qup_i2c2_default: qup 1580 qup_i2c2_default: qup-i2c2-default-state {
1724 pins = "gpio1 1581 pins = "gpio15", "gpio16";
1725 function = "q 1582 function = "qup02_i2c";
1726 }; 1583 };
1727 1584
1728 qup_i2c3_default: qup 1585 qup_i2c3_default: qup-i2c3-default-state {
1729 pins = "gpio3 1586 pins = "gpio38", "gpio39";
1730 function = "q 1587 function = "qup03";
1731 }; 1588 };
1732 1589
1733 qup_i2c4_default: qup 1590 qup_i2c4_default: qup-i2c4-default-state {
1734 pins = "gpio1 1591 pins = "gpio115", "gpio116";
1735 function = "q 1592 function = "qup04_i2c";
1736 }; 1593 };
1737 1594
1738 qup_i2c5_default: qup 1595 qup_i2c5_default: qup-i2c5-default-state {
1739 pins = "gpio2 1596 pins = "gpio25", "gpio26";
1740 function = "q 1597 function = "qup05";
1741 }; 1598 };
1742 1599
1743 qup_i2c6_default: qup 1600 qup_i2c6_default: qup-i2c6-default-state {
1744 pins = "gpio5 1601 pins = "gpio59", "gpio60";
1745 function = "q 1602 function = "qup10";
1746 }; 1603 };
1747 1604
1748 qup_i2c7_default: qup 1605 qup_i2c7_default: qup-i2c7-default-state {
1749 pins = "gpio6 1606 pins = "gpio6", "gpio7";
1750 function = "q 1607 function = "qup11_i2c";
1751 }; 1608 };
1752 1609
1753 qup_i2c8_default: qup 1610 qup_i2c8_default: qup-i2c8-default-state {
1754 pins = "gpio4 1611 pins = "gpio42", "gpio43";
1755 function = "q 1612 function = "qup12";
1756 }; 1613 };
1757 1614
1758 qup_i2c9_default: qup 1615 qup_i2c9_default: qup-i2c9-default-state {
1759 pins = "gpio4 1616 pins = "gpio46", "gpio47";
1760 function = "q 1617 function = "qup13_i2c";
1761 }; 1618 };
1762 1619
1763 qup_i2c10_default: qu 1620 qup_i2c10_default: qup-i2c10-default-state {
1764 pins = "gpio8 1621 pins = "gpio86", "gpio87";
1765 function = "q 1622 function = "qup14";
1766 }; 1623 };
1767 1624
1768 qup_i2c11_default: qu 1625 qup_i2c11_default: qup-i2c11-default-state {
1769 pins = "gpio5 1626 pins = "gpio53", "gpio54";
1770 function = "q 1627 function = "qup15";
1771 }; 1628 };
1772 1629
1773 qup_spi0_spi: qup-spi 1630 qup_spi0_spi: qup-spi0-spi-state {
1774 pins = "gpio3 1631 pins = "gpio34", "gpio35", "gpio36";
1775 function = "q 1632 function = "qup00";
1776 }; 1633 };
1777 1634
1778 qup_spi0_cs: qup-spi0 1635 qup_spi0_cs: qup-spi0-cs-state {
1779 pins = "gpio3 1636 pins = "gpio37";
1780 function = "q 1637 function = "qup00";
1781 }; 1638 };
1782 1639
1783 qup_spi0_cs_gpio: qup 1640 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state {
1784 pins = "gpio3 1641 pins = "gpio37";
1785 function = "g 1642 function = "gpio";
1786 }; 1643 };
1787 1644
1788 qup_spi1_spi: qup-spi 1645 qup_spi1_spi: qup-spi1-spi-state {
1789 pins = "gpio0 1646 pins = "gpio0", "gpio1", "gpio2";
1790 function = "q 1647 function = "qup01";
1791 }; 1648 };
1792 1649
1793 qup_spi1_cs: qup-spi1 1650 qup_spi1_cs: qup-spi1-cs-state {
1794 pins = "gpio3 1651 pins = "gpio3";
1795 function = "q 1652 function = "qup01";
1796 }; 1653 };
1797 1654
1798 qup_spi1_cs_gpio: qup 1655 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state {
1799 pins = "gpio3 1656 pins = "gpio3";
1800 function = "g 1657 function = "gpio";
1801 }; 1658 };
1802 1659
1803 qup_spi3_spi: qup-spi 1660 qup_spi3_spi: qup-spi3-spi-state {
1804 pins = "gpio3 1661 pins = "gpio38", "gpio39", "gpio40";
1805 function = "q 1662 function = "qup03";
1806 }; 1663 };
1807 1664
1808 qup_spi3_cs: qup-spi3 1665 qup_spi3_cs: qup-spi3-cs-state {
1809 pins = "gpio4 1666 pins = "gpio41";
1810 function = "q 1667 function = "qup03";
1811 }; 1668 };
1812 1669
1813 qup_spi3_cs_gpio: qup 1670 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state {
1814 pins = "gpio4 1671 pins = "gpio41";
1815 function = "g 1672 function = "gpio";
1816 }; 1673 };
1817 1674
1818 qup_spi5_spi: qup-spi 1675 qup_spi5_spi: qup-spi5-spi-state {
1819 pins = "gpio2 1676 pins = "gpio25", "gpio26", "gpio27";
1820 function = "q 1677 function = "qup05";
1821 }; 1678 };
1822 1679
1823 qup_spi5_cs: qup-spi5 1680 qup_spi5_cs: qup-spi5-cs-state {
1824 pins = "gpio2 1681 pins = "gpio28";
1825 function = "q 1682 function = "qup05";
1826 }; 1683 };
1827 1684
1828 qup_spi5_cs_gpio: qup 1685 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state {
1829 pins = "gpio2 1686 pins = "gpio28";
1830 function = "g 1687 function = "gpio";
1831 }; 1688 };
1832 1689
1833 qup_spi6_spi: qup-spi 1690 qup_spi6_spi: qup-spi6-spi-state {
1834 pins = "gpio5 1691 pins = "gpio59", "gpio60", "gpio61";
1835 function = "q 1692 function = "qup10";
1836 }; 1693 };
1837 1694
1838 qup_spi6_cs: qup-spi6 1695 qup_spi6_cs: qup-spi6-cs-state {
1839 pins = "gpio6 1696 pins = "gpio62";
1840 function = "q 1697 function = "qup10";
1841 }; 1698 };
1842 1699
1843 qup_spi6_cs_gpio: qup 1700 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state {
1844 pins = "gpio6 1701 pins = "gpio62";
1845 function = "g 1702 function = "gpio";
1846 }; 1703 };
1847 1704
1848 qup_spi8_spi: qup-spi 1705 qup_spi8_spi: qup-spi8-spi-state {
1849 pins = "gpio4 1706 pins = "gpio42", "gpio43", "gpio44";
1850 function = "q 1707 function = "qup12";
1851 }; 1708 };
1852 1709
1853 qup_spi8_cs: qup-spi8 1710 qup_spi8_cs: qup-spi8-cs-state {
1854 pins = "gpio4 1711 pins = "gpio45";
1855 function = "q 1712 function = "qup12";
1856 }; 1713 };
1857 1714
1858 qup_spi8_cs_gpio: qup 1715 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state {
1859 pins = "gpio4 1716 pins = "gpio45";
1860 function = "g 1717 function = "gpio";
1861 }; 1718 };
1862 1719
1863 qup_spi10_spi: qup-sp 1720 qup_spi10_spi: qup-spi10-spi-state {
1864 pins = "gpio8 1721 pins = "gpio86", "gpio87", "gpio88";
1865 function = "q 1722 function = "qup14";
1866 }; 1723 };
1867 1724
1868 qup_spi10_cs: qup-spi 1725 qup_spi10_cs: qup-spi10-cs-state {
1869 pins = "gpio8 1726 pins = "gpio89";
1870 function = "q 1727 function = "qup14";
1871 }; 1728 };
1872 1729
1873 qup_spi10_cs_gpio: qu 1730 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state {
1874 pins = "gpio8 1731 pins = "gpio89";
1875 function = "g 1732 function = "gpio";
1876 }; 1733 };
1877 1734
1878 qup_spi11_spi: qup-sp 1735 qup_spi11_spi: qup-spi11-spi-state {
1879 pins = "gpio5 1736 pins = "gpio53", "gpio54", "gpio55";
1880 function = "q 1737 function = "qup15";
1881 }; 1738 };
1882 1739
1883 qup_spi11_cs: qup-spi 1740 qup_spi11_cs: qup-spi11-cs-state {
1884 pins = "gpio5 1741 pins = "gpio56";
1885 function = "q 1742 function = "qup15";
1886 }; 1743 };
1887 1744
1888 qup_spi11_cs_gpio: qu 1745 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state {
1889 pins = "gpio5 1746 pins = "gpio56";
1890 function = "g 1747 function = "gpio";
1891 }; 1748 };
1892 1749
1893 qup_uart0_default: qu 1750 qup_uart0_default: qup-uart0-default-state {
1894 qup_uart0_cts 1751 qup_uart0_cts: cts-pins {
1895 pins 1752 pins = "gpio34";
1896 funct 1753 function = "qup00";
1897 }; 1754 };
1898 1755
1899 qup_uart0_rts 1756 qup_uart0_rts: rts-pins {
1900 pins 1757 pins = "gpio35";
1901 funct 1758 function = "qup00";
1902 }; 1759 };
1903 1760
1904 qup_uart0_tx: 1761 qup_uart0_tx: tx-pins {
1905 pins 1762 pins = "gpio36";
1906 funct 1763 function = "qup00";
1907 }; 1764 };
1908 1765
1909 qup_uart0_rx: 1766 qup_uart0_rx: rx-pins {
1910 pins 1767 pins = "gpio37";
1911 funct 1768 function = "qup00";
1912 }; 1769 };
1913 }; 1770 };
1914 1771
1915 qup_uart1_default: qu 1772 qup_uart1_default: qup-uart1-default-state {
1916 qup_uart1_cts 1773 qup_uart1_cts: cts-pins {
1917 pins 1774 pins = "gpio0";
1918 funct 1775 function = "qup01";
1919 }; 1776 };
1920 1777
1921 qup_uart1_rts 1778 qup_uart1_rts: rts-pins {
1922 pins 1779 pins = "gpio1";
1923 funct 1780 function = "qup01";
1924 }; 1781 };
1925 1782
1926 qup_uart1_tx: 1783 qup_uart1_tx: tx-pins {
1927 pins 1784 pins = "gpio2";
1928 funct 1785 function = "qup01";
1929 }; 1786 };
1930 1787
1931 qup_uart1_rx: 1788 qup_uart1_rx: rx-pins {
1932 pins 1789 pins = "gpio3";
1933 funct 1790 function = "qup01";
1934 }; 1791 };
1935 }; 1792 };
1936 1793
1937 qup_uart2_default: qu 1794 qup_uart2_default: qup-uart2-default-state {
1938 qup_uart2_tx: 1795 qup_uart2_tx: tx-pins {
1939 pins 1796 pins = "gpio15";
1940 funct 1797 function = "qup02_uart";
1941 }; 1798 };
1942 1799
1943 qup_uart2_rx: 1800 qup_uart2_rx: rx-pins {
1944 pins 1801 pins = "gpio16";
1945 funct 1802 function = "qup02_uart";
1946 }; 1803 };
1947 }; 1804 };
1948 1805
1949 qup_uart3_default: qu 1806 qup_uart3_default: qup-uart3-default-state {
1950 qup_uart3_cts 1807 qup_uart3_cts: cts-pins {
1951 pins 1808 pins = "gpio38";
1952 funct 1809 function = "qup03";
1953 }; 1810 };
1954 1811
1955 qup_uart3_rts 1812 qup_uart3_rts: rts-pins {
1956 pins 1813 pins = "gpio39";
1957 funct 1814 function = "qup03";
1958 }; 1815 };
1959 1816
1960 qup_uart3_tx: 1817 qup_uart3_tx: tx-pins {
1961 pins 1818 pins = "gpio40";
1962 funct 1819 function = "qup03";
1963 }; 1820 };
1964 1821
1965 qup_uart3_rx: 1822 qup_uart3_rx: rx-pins {
1966 pins 1823 pins = "gpio41";
1967 funct 1824 function = "qup03";
1968 }; 1825 };
1969 }; 1826 };
1970 1827
1971 qup_uart4_default: qu 1828 qup_uart4_default: qup-uart4-default-state {
1972 qup_uart4_tx: 1829 qup_uart4_tx: tx-pins {
1973 pins 1830 pins = "gpio115";
1974 funct 1831 function = "qup04_uart";
1975 }; 1832 };
1976 1833
1977 qup_uart4_rx: 1834 qup_uart4_rx: rx-pins {
1978 pins 1835 pins = "gpio116";
1979 funct 1836 function = "qup04_uart";
1980 }; 1837 };
1981 }; 1838 };
1982 1839
1983 qup_uart5_default: qu 1840 qup_uart5_default: qup-uart5-default-state {
1984 qup_uart5_cts 1841 qup_uart5_cts: cts-pins {
1985 pins 1842 pins = "gpio25";
1986 funct 1843 function = "qup05";
1987 }; 1844 };
1988 1845
1989 qup_uart5_rts 1846 qup_uart5_rts: rts-pins {
1990 pins 1847 pins = "gpio26";
1991 funct 1848 function = "qup05";
1992 }; 1849 };
1993 1850
1994 qup_uart5_tx: 1851 qup_uart5_tx: tx-pins {
1995 pins 1852 pins = "gpio27";
1996 funct 1853 function = "qup05";
1997 }; 1854 };
1998 1855
1999 qup_uart5_rx: 1856 qup_uart5_rx: rx-pins {
2000 pins 1857 pins = "gpio28";
2001 funct 1858 function = "qup05";
2002 }; 1859 };
2003 }; 1860 };
2004 1861
2005 qup_uart6_default: qu 1862 qup_uart6_default: qup-uart6-default-state {
2006 qup_uart6_cts 1863 qup_uart6_cts: cts-pins {
2007 pins 1864 pins = "gpio59";
2008 funct 1865 function = "qup10";
2009 }; 1866 };
2010 1867
2011 qup_uart6_rts 1868 qup_uart6_rts: rts-pins {
2012 pins 1869 pins = "gpio60";
2013 funct 1870 function = "qup10";
2014 }; 1871 };
2015 1872
2016 qup_uart6_tx: 1873 qup_uart6_tx: tx-pins {
2017 pins 1874 pins = "gpio61";
2018 funct 1875 function = "qup10";
2019 }; 1876 };
2020 1877
2021 qup_uart6_rx: 1878 qup_uart6_rx: rx-pins {
2022 pins 1879 pins = "gpio62";
2023 funct 1880 function = "qup10";
2024 }; 1881 };
2025 }; 1882 };
2026 1883
2027 qup_uart7_default: qu 1884 qup_uart7_default: qup-uart7-default-state {
2028 qup_uart7_tx: 1885 qup_uart7_tx: tx-pins {
2029 pins 1886 pins = "gpio6";
2030 funct 1887 function = "qup11_uart";
2031 }; 1888 };
2032 1889
2033 qup_uart7_rx: 1890 qup_uart7_rx: rx-pins {
2034 pins 1891 pins = "gpio7";
2035 funct 1892 function = "qup11_uart";
2036 }; 1893 };
2037 }; 1894 };
2038 1895
2039 qup_uart8_default: qu 1896 qup_uart8_default: qup-uart8-default-state {
2040 qup_uart8_tx: 1897 qup_uart8_tx: tx-pins {
2041 pins 1898 pins = "gpio44";
2042 funct 1899 function = "qup12";
2043 }; 1900 };
2044 1901
2045 qup_uart8_rx: 1902 qup_uart8_rx: rx-pins {
2046 pins 1903 pins = "gpio45";
2047 funct 1904 function = "qup12";
2048 }; 1905 };
2049 }; 1906 };
2050 1907
2051 qup_uart9_default: qu 1908 qup_uart9_default: qup-uart9-default-state {
2052 qup_uart9_tx: 1909 qup_uart9_tx: tx-pins {
2053 pins 1910 pins = "gpio46";
2054 funct 1911 function = "qup13_uart";
2055 }; 1912 };
2056 1913
2057 qup_uart9_rx: 1914 qup_uart9_rx: rx-pins {
2058 pins 1915 pins = "gpio47";
2059 funct 1916 function = "qup13_uart";
2060 }; 1917 };
2061 }; 1918 };
2062 1919
2063 qup_uart10_default: q 1920 qup_uart10_default: qup-uart10-default-state {
2064 qup_uart10_ct 1921 qup_uart10_cts: cts-pins {
2065 pins 1922 pins = "gpio86";
2066 funct 1923 function = "qup14";
2067 }; 1924 };
2068 1925
2069 qup_uart10_rt 1926 qup_uart10_rts: rts-pins {
2070 pins 1927 pins = "gpio87";
2071 funct 1928 function = "qup14";
2072 }; 1929 };
2073 1930
2074 qup_uart10_tx 1931 qup_uart10_tx: tx-pins {
2075 pins 1932 pins = "gpio88";
2076 funct 1933 function = "qup14";
2077 }; 1934 };
2078 1935
2079 qup_uart10_rx 1936 qup_uart10_rx: rx-pins {
2080 pins 1937 pins = "gpio89";
2081 funct 1938 function = "qup14";
2082 }; 1939 };
2083 }; 1940 };
2084 1941
2085 qup_uart11_default: q 1942 qup_uart11_default: qup-uart11-default-state {
2086 qup_uart11_ct 1943 qup_uart11_cts: cts-pins {
2087 pins 1944 pins = "gpio53";
2088 funct 1945 function = "qup15";
2089 }; 1946 };
2090 1947
2091 qup_uart11_rt 1948 qup_uart11_rts: rts-pins {
2092 pins 1949 pins = "gpio54";
2093 funct 1950 function = "qup15";
2094 }; 1951 };
2095 1952
2096 qup_uart11_tx 1953 qup_uart11_tx: tx-pins {
2097 pins 1954 pins = "gpio55";
2098 funct 1955 function = "qup15";
2099 }; 1956 };
2100 1957
2101 qup_uart11_rx 1958 qup_uart11_rx: rx-pins {
2102 pins 1959 pins = "gpio56";
2103 funct 1960 function = "qup15";
2104 }; 1961 };
2105 }; 1962 };
2106 1963
2107 sec_mi2s_active: sec- 1964 sec_mi2s_active: sec-mi2s-active-state {
2108 pins = "gpio4 1965 pins = "gpio49", "gpio50", "gpio51";
2109 function = "m 1966 function = "mi2s_1";
2110 }; 1967 };
2111 1968
2112 pri_mi2s_active: pri- 1969 pri_mi2s_active: pri-mi2s-active-state {
2113 pins = "gpio5 1970 pins = "gpio53", "gpio54", "gpio55", "gpio56";
2114 function = "m 1971 function = "mi2s_0";
2115 }; 1972 };
2116 1973
2117 pri_mi2s_mclk_active: 1974 pri_mi2s_mclk_active: pri-mi2s-mclk-active-state {
2118 pins = "gpio5 1975 pins = "gpio57";
2119 function = "l 1976 function = "lpass_ext";
2120 }; 1977 };
2121 <<
2122 ter_mi2s_active: ter- <<
2123 pins = "gpio6 <<
2124 function = "m <<
2125 }; <<
2126 }; 1978 };
2127 1979
2128 remoteproc_mpss: remoteproc@4 1980 remoteproc_mpss: remoteproc@4080000 {
2129 compatible = "qcom,sc 1981 compatible = "qcom,sc7180-mpss-pas";
2130 reg = <0 0x04080000 0 1982 reg = <0 0x04080000 0 0x4040>;
2131 1983
2132 interrupts-extended = 1984 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
2133 1985 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2134 1986 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2135 1987 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2136 1988 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
2137 1989 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
2138 interrupt-names = "wd 1990 interrupt-names = "wdog", "fatal", "ready", "handover",
2139 "st 1991 "stop-ack", "shutdown-ack";
2140 1992
2141 clocks = <&rpmhcc RPM 1993 clocks = <&rpmhcc RPMH_CXO_CLK>;
2142 clock-names = "xo"; 1994 clock-names = "xo";
2143 1995
2144 power-domains = <&rpm 1996 power-domains = <&rpmhpd SC7180_CX>,
2145 <&rpm 1997 <&rpmhpd SC7180_MX>,
2146 <&rpm 1998 <&rpmhpd SC7180_MSS>;
2147 power-domain-names = 1999 power-domain-names = "cx", "mx", "mss";
2148 2000
2149 memory-region = <&mps 2001 memory-region = <&mpss_mem>;
2150 2002
2151 qcom,qmp = <&aoss_qmp 2003 qcom,qmp = <&aoss_qmp>;
2152 2004
2153 qcom,smem-states = <& 2005 qcom,smem-states = <&modem_smp2p_out 0>;
2154 qcom,smem-state-names 2006 qcom,smem-state-names = "stop";
2155 2007
2156 status = "disabled"; 2008 status = "disabled";
2157 2009
2158 glink-edge { 2010 glink-edge {
2159 interrupts = 2011 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
2160 label = "mode 2012 label = "modem";
2161 qcom,remote-p 2013 qcom,remote-pid = <1>;
2162 mboxes = <&ap 2014 mboxes = <&apss_shared 12>;
2163 }; 2015 };
2164 }; 2016 };
2165 2017
2166 gpu: gpu@5000000 { 2018 gpu: gpu@5000000 {
2167 compatible = "qcom,ad 2019 compatible = "qcom,adreno-618.0", "qcom,adreno";
2168 reg = <0 0x05000000 0 2020 reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x1000>,
2169 <0 0x05061000 2021 <0 0x05061000 0 0x800>;
2170 reg-names = "kgsl_3d0 2022 reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc";
2171 interrupts = <GIC_SPI 2023 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2172 iommus = <&adreno_smm 2024 iommus = <&adreno_smmu 0>;
2173 operating-points-v2 = 2025 operating-points-v2 = <&gpu_opp_table>;
2174 qcom,gmu = <&gmu>; 2026 qcom,gmu = <&gmu>;
2175 2027
2176 #cooling-cells = <2>; 2028 #cooling-cells = <2>;
2177 2029
2178 nvmem-cells = <&gpu_s 2030 nvmem-cells = <&gpu_speed_bin>;
2179 nvmem-cell-names = "s 2031 nvmem-cell-names = "speed_bin";
2180 2032
2181 interconnects = <&gem 2033 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
2182 interconnect-names = 2034 interconnect-names = "gfx-mem";
2183 2035
2184 gpu_opp_table: opp-ta 2036 gpu_opp_table: opp-table {
2185 compatible = 2037 compatible = "operating-points-v2";
2186 2038
2187 opp-825000000 2039 opp-825000000 {
2188 opp-h 2040 opp-hz = /bits/ 64 <825000000>;
2189 opp-l 2041 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2190 opp-p 2042 opp-peak-kBps = <8532000>;
2191 opp-s 2043 opp-supported-hw = <0x04>;
2192 }; 2044 };
2193 2045
2194 opp-800000000 2046 opp-800000000 {
2195 opp-h 2047 opp-hz = /bits/ 64 <800000000>;
2196 opp-l 2048 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2197 opp-p 2049 opp-peak-kBps = <8532000>;
2198 opp-s 2050 opp-supported-hw = <0x07>;
2199 }; 2051 };
2200 2052
2201 opp-650000000 2053 opp-650000000 {
2202 opp-h 2054 opp-hz = /bits/ 64 <650000000>;
2203 opp-l 2055 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2204 opp-p 2056 opp-peak-kBps = <7216000>;
2205 opp-s 2057 opp-supported-hw = <0x07>;
2206 }; 2058 };
2207 2059
2208 opp-565000000 2060 opp-565000000 {
2209 opp-h 2061 opp-hz = /bits/ 64 <565000000>;
2210 opp-l 2062 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2211 opp-p 2063 opp-peak-kBps = <5412000>;
2212 opp-s 2064 opp-supported-hw = <0x07>;
2213 }; 2065 };
2214 2066
2215 opp-430000000 2067 opp-430000000 {
2216 opp-h 2068 opp-hz = /bits/ 64 <430000000>;
2217 opp-l 2069 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2218 opp-p 2070 opp-peak-kBps = <5412000>;
2219 opp-s 2071 opp-supported-hw = <0x07>;
2220 }; 2072 };
2221 2073
2222 opp-355000000 2074 opp-355000000 {
2223 opp-h 2075 opp-hz = /bits/ 64 <355000000>;
2224 opp-l 2076 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2225 opp-p 2077 opp-peak-kBps = <3072000>;
2226 opp-s 2078 opp-supported-hw = <0x07>;
2227 }; 2079 };
2228 2080
2229 opp-267000000 2081 opp-267000000 {
2230 opp-h 2082 opp-hz = /bits/ 64 <267000000>;
2231 opp-l 2083 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2232 opp-p 2084 opp-peak-kBps = <3072000>;
2233 opp-s 2085 opp-supported-hw = <0x07>;
2234 }; 2086 };
2235 2087
2236 opp-180000000 2088 opp-180000000 {
2237 opp-h 2089 opp-hz = /bits/ 64 <180000000>;
2238 opp-l 2090 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2239 opp-p 2091 opp-peak-kBps = <1804000>;
2240 opp-s 2092 opp-supported-hw = <0x07>;
2241 }; 2093 };
2242 }; 2094 };
2243 }; 2095 };
2244 2096
2245 adreno_smmu: iommu@5040000 { 2097 adreno_smmu: iommu@5040000 {
2246 compatible = "qcom,sc 2098 compatible = "qcom,sc7180-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
2247 reg = <0 0x05040000 0 2099 reg = <0 0x05040000 0 0x10000>;
2248 #iommu-cells = <1>; 2100 #iommu-cells = <1>;
2249 #global-interrupts = 2101 #global-interrupts = <2>;
2250 interrupts = <GIC_SPI 2102 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
2251 <GIC_ 2103 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
2252 <GIC_ 2104 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
2253 <GIC_ 2105 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
2254 <GIC_ 2106 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
2255 <GIC_ 2107 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
2256 <GIC_ 2108 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
2257 <GIC_ 2109 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
2258 <GIC_ 2110 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
2259 <GIC_ 2111 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
2260 2112
2261 clocks = <&gcc GCC_GP 2113 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2262 <&gcc GCC_GPU 2114 <&gcc GCC_GPU_CFG_AHB_CLK>;
2263 clock-names = "bus", 2115 clock-names = "bus", "iface";
2264 2116
2265 power-domains = <&gpu 2117 power-domains = <&gpucc CX_GDSC>;
2266 }; 2118 };
2267 2119
2268 gmu: gmu@506a000 { 2120 gmu: gmu@506a000 {
2269 compatible = "qcom,ad 2121 compatible = "qcom,adreno-gmu-618.0", "qcom,adreno-gmu";
2270 reg = <0 0x0506a000 0 2122 reg = <0 0x0506a000 0 0x31000>, <0 0x0b290000 0 0x10000>,
2271 <0 0x0b490000 2123 <0 0x0b490000 0 0x10000>;
2272 reg-names = "gmu", "g 2124 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
2273 interrupts = <GIC_SPI 2125 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2274 <GIC_SPI 3 2126 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2275 interrupt-names = "hf 2127 interrupt-names = "hfi", "gmu";
2276 clocks = <&gpucc GPU_ 2128 clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
2277 <&gpucc GPU_CC 2129 <&gpucc GPU_CC_CXO_CLK>,
2278 <&gcc GCC_DDRS 2130 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2279 <&gcc GCC_GPU_ 2131 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
2280 clock-names = "gmu", 2132 clock-names = "gmu", "cxo", "axi", "memnoc";
2281 power-domains = <&gpu 2133 power-domains = <&gpucc CX_GDSC>, <&gpucc GX_GDSC>;
2282 power-domain-names = 2134 power-domain-names = "cx", "gx";
2283 iommus = <&adreno_smm 2135 iommus = <&adreno_smmu 5>;
2284 operating-points-v2 = 2136 operating-points-v2 = <&gmu_opp_table>;
2285 2137
2286 gmu_opp_table: opp-ta 2138 gmu_opp_table: opp-table {
2287 compatible = 2139 compatible = "operating-points-v2";
2288 2140
2289 opp-200000000 2141 opp-200000000 {
2290 opp-h 2142 opp-hz = /bits/ 64 <200000000>;
2291 opp-l 2143 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2292 }; 2144 };
2293 }; 2145 };
2294 }; 2146 };
2295 2147
2296 gpucc: clock-controller@50900 2148 gpucc: clock-controller@5090000 {
2297 compatible = "qcom,sc 2149 compatible = "qcom,sc7180-gpucc";
2298 reg = <0 0x05090000 0 2150 reg = <0 0x05090000 0 0x9000>;
2299 clocks = <&rpmhcc RPM 2151 clocks = <&rpmhcc RPMH_CXO_CLK>,
2300 <&gcc GCC_GP 2152 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2301 <&gcc GCC_GP 2153 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2302 clock-names = "bi_tcx 2154 clock-names = "bi_tcxo",
2303 "gcc_gp 2155 "gcc_gpu_gpll0_clk_src",
2304 "gcc_gp 2156 "gcc_gpu_gpll0_div_clk_src";
2305 #clock-cells = <1>; 2157 #clock-cells = <1>;
2306 #reset-cells = <1>; 2158 #reset-cells = <1>;
2307 #power-domain-cells = 2159 #power-domain-cells = <1>;
2308 }; 2160 };
2309 2161
2310 dma@10a2000 { 2162 dma@10a2000 {
2311 compatible = "qcom,sc 2163 compatible = "qcom,sc7180-dcc", "qcom,dcc";
2312 reg = <0x0 0x010a2000 2164 reg = <0x0 0x010a2000 0x0 0x1000>,
2313 <0x0 0x010ae000 2165 <0x0 0x010ae000 0x0 0x2000>;
2314 status = "disabled"; <<
2315 }; 2166 };
2316 2167
2317 stm@6002000 { 2168 stm@6002000 {
2318 compatible = "arm,cor 2169 compatible = "arm,coresight-stm", "arm,primecell";
2319 reg = <0 0x06002000 0 2170 reg = <0 0x06002000 0 0x1000>,
2320 <0 0x16280000 0 2171 <0 0x16280000 0 0x180000>;
2321 reg-names = "stm-base 2172 reg-names = "stm-base", "stm-stimulus-base";
2322 2173
2323 clocks = <&aoss_qmp>; 2174 clocks = <&aoss_qmp>;
2324 clock-names = "apb_pc 2175 clock-names = "apb_pclk";
2325 2176
2326 out-ports { 2177 out-ports {
2327 port { 2178 port {
2328 stm_o 2179 stm_out: endpoint {
2329 2180 remote-endpoint = <&funnel0_in7>;
2330 }; 2181 };
2331 }; 2182 };
2332 }; 2183 };
2333 }; 2184 };
2334 2185
2335 funnel@6041000 { 2186 funnel@6041000 {
2336 compatible = "arm,cor 2187 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2337 reg = <0 0x06041000 0 2188 reg = <0 0x06041000 0 0x1000>;
2338 2189
2339 clocks = <&aoss_qmp>; 2190 clocks = <&aoss_qmp>;
2340 clock-names = "apb_pc 2191 clock-names = "apb_pclk";
2341 2192
2342 out-ports { 2193 out-ports {
2343 port { 2194 port {
2344 funne 2195 funnel0_out: endpoint {
2345 2196 remote-endpoint = <&merge_funnel_in0>;
2346 }; 2197 };
2347 }; 2198 };
2348 }; 2199 };
2349 2200
2350 in-ports { 2201 in-ports {
2351 #address-cell 2202 #address-cells = <1>;
2352 #size-cells = 2203 #size-cells = <0>;
2353 2204
2354 port@7 { 2205 port@7 {
2355 reg = 2206 reg = <7>;
2356 funne 2207 funnel0_in7: endpoint {
2357 2208 remote-endpoint = <&stm_out>;
2358 }; 2209 };
2359 }; 2210 };
2360 }; 2211 };
2361 }; 2212 };
2362 2213
2363 funnel@6042000 { 2214 funnel@6042000 {
2364 compatible = "arm,cor 2215 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2365 reg = <0 0x06042000 0 2216 reg = <0 0x06042000 0 0x1000>;
2366 2217
2367 clocks = <&aoss_qmp>; 2218 clocks = <&aoss_qmp>;
2368 clock-names = "apb_pc 2219 clock-names = "apb_pclk";
2369 2220
2370 out-ports { 2221 out-ports {
2371 port { 2222 port {
2372 funne 2223 funnel1_out: endpoint {
2373 2224 remote-endpoint = <&merge_funnel_in1>;
2374 }; 2225 };
2375 }; 2226 };
2376 }; 2227 };
2377 2228
2378 in-ports { 2229 in-ports {
2379 #address-cell 2230 #address-cells = <1>;
2380 #size-cells = 2231 #size-cells = <0>;
2381 2232
2382 port@4 { 2233 port@4 {
2383 reg = 2234 reg = <4>;
2384 funne 2235 funnel1_in4: endpoint {
2385 2236 remote-endpoint = <&apss_merge_funnel_out>;
2386 }; 2237 };
2387 }; 2238 };
2388 }; 2239 };
2389 }; 2240 };
2390 2241
2391 funnel@6045000 { 2242 funnel@6045000 {
2392 compatible = "arm,cor 2243 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2393 reg = <0 0x06045000 0 2244 reg = <0 0x06045000 0 0x1000>;
2394 2245
2395 clocks = <&aoss_qmp>; 2246 clocks = <&aoss_qmp>;
2396 clock-names = "apb_pc 2247 clock-names = "apb_pclk";
2397 2248
2398 out-ports { 2249 out-ports {
2399 port { 2250 port {
2400 merge 2251 merge_funnel_out: endpoint {
2401 2252 remote-endpoint = <&swao_funnel_in>;
2402 }; 2253 };
2403 }; 2254 };
2404 }; 2255 };
2405 2256
2406 in-ports { 2257 in-ports {
2407 #address-cell 2258 #address-cells = <1>;
2408 #size-cells = 2259 #size-cells = <0>;
2409 2260
2410 port@0 { 2261 port@0 {
2411 reg = 2262 reg = <0>;
2412 merge 2263 merge_funnel_in0: endpoint {
2413 2264 remote-endpoint = <&funnel0_out>;
2414 }; 2265 };
2415 }; 2266 };
2416 2267
2417 port@1 { 2268 port@1 {
2418 reg = 2269 reg = <1>;
2419 merge 2270 merge_funnel_in1: endpoint {
2420 2271 remote-endpoint = <&funnel1_out>;
2421 }; 2272 };
2422 }; 2273 };
2423 }; 2274 };
2424 }; 2275 };
2425 2276
2426 replicator@6046000 { 2277 replicator@6046000 {
2427 compatible = "arm,cor 2278 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2428 reg = <0 0x06046000 0 2279 reg = <0 0x06046000 0 0x1000>;
2429 2280
2430 clocks = <&aoss_qmp>; 2281 clocks = <&aoss_qmp>;
2431 clock-names = "apb_pc 2282 clock-names = "apb_pclk";
2432 2283
2433 out-ports { 2284 out-ports {
2434 port { 2285 port {
2435 repli 2286 replicator_out: endpoint {
2436 2287 remote-endpoint = <&etr_in>;
2437 }; 2288 };
2438 }; 2289 };
2439 }; 2290 };
2440 2291
2441 in-ports { 2292 in-ports {
2442 port { 2293 port {
2443 repli 2294 replicator_in: endpoint {
2444 2295 remote-endpoint = <&swao_replicator_out>;
2445 }; 2296 };
2446 }; 2297 };
2447 }; 2298 };
2448 }; 2299 };
2449 2300
2450 etr@6048000 { 2301 etr@6048000 {
2451 compatible = "arm,cor 2302 compatible = "arm,coresight-tmc", "arm,primecell";
2452 reg = <0 0x06048000 0 2303 reg = <0 0x06048000 0 0x1000>;
2453 iommus = <&apps_smmu 2304 iommus = <&apps_smmu 0x04a0 0x20>;
2454 2305
2455 clocks = <&aoss_qmp>; 2306 clocks = <&aoss_qmp>;
2456 clock-names = "apb_pc 2307 clock-names = "apb_pclk";
2457 arm,scatter-gather; 2308 arm,scatter-gather;
2458 2309
2459 in-ports { 2310 in-ports {
2460 port { 2311 port {
2461 etr_i 2312 etr_in: endpoint {
2462 2313 remote-endpoint = <&replicator_out>;
2463 }; 2314 };
2464 }; 2315 };
2465 }; 2316 };
2466 }; 2317 };
2467 2318
2468 funnel@6b04000 { 2319 funnel@6b04000 {
2469 compatible = "arm,cor 2320 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2470 reg = <0 0x06b04000 0 2321 reg = <0 0x06b04000 0 0x1000>;
2471 2322
2472 clocks = <&aoss_qmp>; 2323 clocks = <&aoss_qmp>;
2473 clock-names = "apb_pc 2324 clock-names = "apb_pclk";
2474 2325
2475 out-ports { 2326 out-ports {
2476 port { 2327 port {
2477 swao_ 2328 swao_funnel_out: endpoint {
2478 2329 remote-endpoint = <&etf_in>;
2479 }; 2330 };
2480 }; 2331 };
2481 }; 2332 };
2482 2333
2483 in-ports { 2334 in-ports {
2484 #address-cell 2335 #address-cells = <1>;
2485 #size-cells = 2336 #size-cells = <0>;
2486 2337
2487 port@7 { 2338 port@7 {
2488 reg = 2339 reg = <7>;
2489 swao_ 2340 swao_funnel_in: endpoint {
2490 2341 remote-endpoint = <&merge_funnel_out>;
2491 }; 2342 };
2492 }; 2343 };
2493 }; 2344 };
2494 }; 2345 };
2495 2346
2496 etf@6b05000 { 2347 etf@6b05000 {
2497 compatible = "arm,cor 2348 compatible = "arm,coresight-tmc", "arm,primecell";
2498 reg = <0 0x06b05000 0 2349 reg = <0 0x06b05000 0 0x1000>;
2499 2350
2500 clocks = <&aoss_qmp>; 2351 clocks = <&aoss_qmp>;
2501 clock-names = "apb_pc 2352 clock-names = "apb_pclk";
2502 2353
2503 out-ports { 2354 out-ports {
2504 port { 2355 port {
2505 etf_o 2356 etf_out: endpoint {
2506 2357 remote-endpoint = <&swao_replicator_in>;
2507 }; 2358 };
2508 }; 2359 };
2509 }; 2360 };
2510 2361
2511 in-ports { 2362 in-ports {
2512 port { 2363 port {
2513 etf_i 2364 etf_in: endpoint {
2514 2365 remote-endpoint = <&swao_funnel_out>;
2515 }; 2366 };
2516 }; 2367 };
2517 }; 2368 };
2518 }; 2369 };
2519 2370
2520 replicator@6b06000 { 2371 replicator@6b06000 {
2521 compatible = "arm,cor 2372 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2522 reg = <0 0x06b06000 0 2373 reg = <0 0x06b06000 0 0x1000>;
2523 2374
2524 clocks = <&aoss_qmp>; 2375 clocks = <&aoss_qmp>;
2525 clock-names = "apb_pc 2376 clock-names = "apb_pclk";
2526 qcom,replicator-loses 2377 qcom,replicator-loses-context;
2527 2378
2528 out-ports { 2379 out-ports {
2529 port { 2380 port {
2530 swao_ 2381 swao_replicator_out: endpoint {
2531 2382 remote-endpoint = <&replicator_in>;
2532 }; 2383 };
2533 }; 2384 };
2534 }; 2385 };
2535 2386
2536 in-ports { 2387 in-ports {
2537 port { 2388 port {
2538 swao_ 2389 swao_replicator_in: endpoint {
2539 2390 remote-endpoint = <&etf_out>;
2540 }; 2391 };
2541 }; 2392 };
2542 }; 2393 };
2543 }; 2394 };
2544 2395
2545 etm@7040000 { 2396 etm@7040000 {
2546 compatible = "arm,cor 2397 compatible = "arm,coresight-etm4x", "arm,primecell";
2547 reg = <0 0x07040000 0 2398 reg = <0 0x07040000 0 0x1000>;
2548 2399
2549 cpu = <&CPU0>; 2400 cpu = <&CPU0>;
2550 2401
2551 clocks = <&aoss_qmp>; 2402 clocks = <&aoss_qmp>;
2552 clock-names = "apb_pc 2403 clock-names = "apb_pclk";
2553 arm,coresight-loses-c 2404 arm,coresight-loses-context-with-cpu;
2554 qcom,skip-power-up; 2405 qcom,skip-power-up;
2555 2406
2556 out-ports { 2407 out-ports {
2557 port { 2408 port {
2558 etm0_ 2409 etm0_out: endpoint {
2559 2410 remote-endpoint = <&apss_funnel_in0>;
2560 }; 2411 };
2561 }; 2412 };
2562 }; 2413 };
2563 }; 2414 };
2564 2415
2565 etm@7140000 { 2416 etm@7140000 {
2566 compatible = "arm,cor 2417 compatible = "arm,coresight-etm4x", "arm,primecell";
2567 reg = <0 0x07140000 0 2418 reg = <0 0x07140000 0 0x1000>;
2568 2419
2569 cpu = <&CPU1>; 2420 cpu = <&CPU1>;
2570 2421
2571 clocks = <&aoss_qmp>; 2422 clocks = <&aoss_qmp>;
2572 clock-names = "apb_pc 2423 clock-names = "apb_pclk";
2573 arm,coresight-loses-c 2424 arm,coresight-loses-context-with-cpu;
2574 qcom,skip-power-up; 2425 qcom,skip-power-up;
2575 2426
2576 out-ports { 2427 out-ports {
2577 port { 2428 port {
2578 etm1_ 2429 etm1_out: endpoint {
2579 2430 remote-endpoint = <&apss_funnel_in1>;
2580 }; 2431 };
2581 }; 2432 };
2582 }; 2433 };
2583 }; 2434 };
2584 2435
2585 etm@7240000 { 2436 etm@7240000 {
2586 compatible = "arm,cor 2437 compatible = "arm,coresight-etm4x", "arm,primecell";
2587 reg = <0 0x07240000 0 2438 reg = <0 0x07240000 0 0x1000>;
2588 2439
2589 cpu = <&CPU2>; 2440 cpu = <&CPU2>;
2590 2441
2591 clocks = <&aoss_qmp>; 2442 clocks = <&aoss_qmp>;
2592 clock-names = "apb_pc 2443 clock-names = "apb_pclk";
2593 arm,coresight-loses-c 2444 arm,coresight-loses-context-with-cpu;
2594 qcom,skip-power-up; 2445 qcom,skip-power-up;
2595 2446
2596 out-ports { 2447 out-ports {
2597 port { 2448 port {
2598 etm2_ 2449 etm2_out: endpoint {
2599 2450 remote-endpoint = <&apss_funnel_in2>;
2600 }; 2451 };
2601 }; 2452 };
2602 }; 2453 };
2603 }; 2454 };
2604 2455
2605 etm@7340000 { 2456 etm@7340000 {
2606 compatible = "arm,cor 2457 compatible = "arm,coresight-etm4x", "arm,primecell";
2607 reg = <0 0x07340000 0 2458 reg = <0 0x07340000 0 0x1000>;
2608 2459
2609 cpu = <&CPU3>; 2460 cpu = <&CPU3>;
2610 2461
2611 clocks = <&aoss_qmp>; 2462 clocks = <&aoss_qmp>;
2612 clock-names = "apb_pc 2463 clock-names = "apb_pclk";
2613 arm,coresight-loses-c 2464 arm,coresight-loses-context-with-cpu;
2614 qcom,skip-power-up; 2465 qcom,skip-power-up;
2615 2466
2616 out-ports { 2467 out-ports {
2617 port { 2468 port {
2618 etm3_ 2469 etm3_out: endpoint {
2619 2470 remote-endpoint = <&apss_funnel_in3>;
2620 }; 2471 };
2621 }; 2472 };
2622 }; 2473 };
2623 }; 2474 };
2624 2475
2625 etm@7440000 { 2476 etm@7440000 {
2626 compatible = "arm,cor 2477 compatible = "arm,coresight-etm4x", "arm,primecell";
2627 reg = <0 0x07440000 0 2478 reg = <0 0x07440000 0 0x1000>;
2628 2479
2629 cpu = <&CPU4>; 2480 cpu = <&CPU4>;
2630 2481
2631 clocks = <&aoss_qmp>; 2482 clocks = <&aoss_qmp>;
2632 clock-names = "apb_pc 2483 clock-names = "apb_pclk";
2633 arm,coresight-loses-c 2484 arm,coresight-loses-context-with-cpu;
2634 qcom,skip-power-up; 2485 qcom,skip-power-up;
2635 2486
2636 out-ports { 2487 out-ports {
2637 port { 2488 port {
2638 etm4_ 2489 etm4_out: endpoint {
2639 2490 remote-endpoint = <&apss_funnel_in4>;
2640 }; 2491 };
2641 }; 2492 };
2642 }; 2493 };
2643 }; 2494 };
2644 2495
2645 etm@7540000 { 2496 etm@7540000 {
2646 compatible = "arm,cor 2497 compatible = "arm,coresight-etm4x", "arm,primecell";
2647 reg = <0 0x07540000 0 2498 reg = <0 0x07540000 0 0x1000>;
2648 2499
2649 cpu = <&CPU5>; 2500 cpu = <&CPU5>;
2650 2501
2651 clocks = <&aoss_qmp>; 2502 clocks = <&aoss_qmp>;
2652 clock-names = "apb_pc 2503 clock-names = "apb_pclk";
2653 arm,coresight-loses-c 2504 arm,coresight-loses-context-with-cpu;
2654 qcom,skip-power-up; 2505 qcom,skip-power-up;
2655 2506
2656 out-ports { 2507 out-ports {
2657 port { 2508 port {
2658 etm5_ 2509 etm5_out: endpoint {
2659 2510 remote-endpoint = <&apss_funnel_in5>;
2660 }; 2511 };
2661 }; 2512 };
2662 }; 2513 };
2663 }; 2514 };
2664 2515
2665 etm@7640000 { 2516 etm@7640000 {
2666 compatible = "arm,cor 2517 compatible = "arm,coresight-etm4x", "arm,primecell";
2667 reg = <0 0x07640000 0 2518 reg = <0 0x07640000 0 0x1000>;
2668 2519
2669 cpu = <&CPU6>; 2520 cpu = <&CPU6>;
2670 2521
2671 clocks = <&aoss_qmp>; 2522 clocks = <&aoss_qmp>;
2672 clock-names = "apb_pc 2523 clock-names = "apb_pclk";
2673 arm,coresight-loses-c 2524 arm,coresight-loses-context-with-cpu;
2674 qcom,skip-power-up; 2525 qcom,skip-power-up;
2675 2526
2676 out-ports { 2527 out-ports {
2677 port { 2528 port {
2678 etm6_ 2529 etm6_out: endpoint {
2679 2530 remote-endpoint = <&apss_funnel_in6>;
2680 }; 2531 };
2681 }; 2532 };
2682 }; 2533 };
2683 }; 2534 };
2684 2535
2685 etm@7740000 { 2536 etm@7740000 {
2686 compatible = "arm,cor 2537 compatible = "arm,coresight-etm4x", "arm,primecell";
2687 reg = <0 0x07740000 0 2538 reg = <0 0x07740000 0 0x1000>;
2688 2539
2689 cpu = <&CPU7>; 2540 cpu = <&CPU7>;
2690 2541
2691 clocks = <&aoss_qmp>; 2542 clocks = <&aoss_qmp>;
2692 clock-names = "apb_pc 2543 clock-names = "apb_pclk";
2693 arm,coresight-loses-c 2544 arm,coresight-loses-context-with-cpu;
2694 qcom,skip-power-up; 2545 qcom,skip-power-up;
2695 2546
2696 out-ports { 2547 out-ports {
2697 port { 2548 port {
2698 etm7_ 2549 etm7_out: endpoint {
2699 2550 remote-endpoint = <&apss_funnel_in7>;
2700 }; 2551 };
2701 }; 2552 };
2702 }; 2553 };
2703 }; 2554 };
2704 2555
2705 funnel@7800000 { /* APSS Funn 2556 funnel@7800000 { /* APSS Funnel */
2706 compatible = "arm,cor 2557 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2707 reg = <0 0x07800000 0 2558 reg = <0 0x07800000 0 0x1000>;
2708 2559
2709 clocks = <&aoss_qmp>; 2560 clocks = <&aoss_qmp>;
2710 clock-names = "apb_pc 2561 clock-names = "apb_pclk";
2711 2562
2712 out-ports { 2563 out-ports {
2713 port { 2564 port {
2714 apss_ 2565 apss_funnel_out: endpoint {
2715 2566 remote-endpoint = <&apss_merge_funnel_in>;
2716 }; 2567 };
2717 }; 2568 };
2718 }; 2569 };
2719 2570
2720 in-ports { 2571 in-ports {
2721 #address-cell 2572 #address-cells = <1>;
2722 #size-cells = 2573 #size-cells = <0>;
2723 2574
2724 port@0 { 2575 port@0 {
2725 reg = 2576 reg = <0>;
2726 apss_ 2577 apss_funnel_in0: endpoint {
2727 2578 remote-endpoint = <&etm0_out>;
2728 }; 2579 };
2729 }; 2580 };
2730 2581
2731 port@1 { 2582 port@1 {
2732 reg = 2583 reg = <1>;
2733 apss_ 2584 apss_funnel_in1: endpoint {
2734 2585 remote-endpoint = <&etm1_out>;
2735 }; 2586 };
2736 }; 2587 };
2737 2588
2738 port@2 { 2589 port@2 {
2739 reg = 2590 reg = <2>;
2740 apss_ 2591 apss_funnel_in2: endpoint {
2741 2592 remote-endpoint = <&etm2_out>;
2742 }; 2593 };
2743 }; 2594 };
2744 2595
2745 port@3 { 2596 port@3 {
2746 reg = 2597 reg = <3>;
2747 apss_ 2598 apss_funnel_in3: endpoint {
2748 2599 remote-endpoint = <&etm3_out>;
2749 }; 2600 };
2750 }; 2601 };
2751 2602
2752 port@4 { 2603 port@4 {
2753 reg = 2604 reg = <4>;
2754 apss_ 2605 apss_funnel_in4: endpoint {
2755 2606 remote-endpoint = <&etm4_out>;
2756 }; 2607 };
2757 }; 2608 };
2758 2609
2759 port@5 { 2610 port@5 {
2760 reg = 2611 reg = <5>;
2761 apss_ 2612 apss_funnel_in5: endpoint {
2762 2613 remote-endpoint = <&etm5_out>;
2763 }; 2614 };
2764 }; 2615 };
2765 2616
2766 port@6 { 2617 port@6 {
2767 reg = 2618 reg = <6>;
2768 apss_ 2619 apss_funnel_in6: endpoint {
2769 2620 remote-endpoint = <&etm6_out>;
2770 }; 2621 };
2771 }; 2622 };
2772 2623
2773 port@7 { 2624 port@7 {
2774 reg = 2625 reg = <7>;
2775 apss_ 2626 apss_funnel_in7: endpoint {
2776 2627 remote-endpoint = <&etm7_out>;
2777 }; 2628 };
2778 }; 2629 };
2779 }; 2630 };
2780 }; 2631 };
2781 2632
2782 funnel@7810000 { 2633 funnel@7810000 {
2783 compatible = "arm,cor 2634 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2784 reg = <0 0x07810000 0 2635 reg = <0 0x07810000 0 0x1000>;
2785 2636
2786 clocks = <&aoss_qmp>; 2637 clocks = <&aoss_qmp>;
2787 clock-names = "apb_pc 2638 clock-names = "apb_pclk";
2788 2639
2789 out-ports { 2640 out-ports {
2790 port { 2641 port {
2791 apss_ 2642 apss_merge_funnel_out: endpoint {
2792 2643 remote-endpoint = <&funnel1_in4>;
2793 }; 2644 };
2794 }; 2645 };
2795 }; 2646 };
2796 2647
2797 in-ports { 2648 in-ports {
2798 port { 2649 port {
2799 apss_ 2650 apss_merge_funnel_in: endpoint {
2800 2651 remote-endpoint = <&apss_funnel_out>;
2801 }; 2652 };
2802 }; 2653 };
2803 }; 2654 };
2804 }; 2655 };
2805 2656
2806 sdhc_2: mmc@8804000 { 2657 sdhc_2: mmc@8804000 {
2807 compatible = "qcom,sc 2658 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
2808 reg = <0 0x08804000 0 2659 reg = <0 0x08804000 0 0x1000>;
2809 2660
2810 iommus = <&apps_smmu 2661 iommus = <&apps_smmu 0x80 0>;
2811 interrupts = <GIC_SPI 2662 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
2812 <GIC_ 2663 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
2813 interrupt-names = "hc 2664 interrupt-names = "hc_irq", "pwr_irq";
2814 2665
2815 clocks = <&gcc GCC_SD 2666 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2816 <&gcc GCC_SD 2667 <&gcc GCC_SDCC2_APPS_CLK>,
2817 <&rpmhcc RPM 2668 <&rpmhcc RPMH_CXO_CLK>;
2818 clock-names = "iface" 2669 clock-names = "iface", "core", "xo";
2819 2670
2820 interconnects = <&agg 2671 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
2821 <&gem 2672 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
2822 interconnect-names = 2673 interconnect-names = "sdhc-ddr","cpu-sdhc";
2823 power-domains = <&rpm 2674 power-domains = <&rpmhpd SC7180_CX>;
2824 operating-points-v2 = 2675 operating-points-v2 = <&sdhc2_opp_table>;
2825 2676
2826 bus-width = <4>; 2677 bus-width = <4>;
2827 2678
2828 status = "disabled"; 2679 status = "disabled";
2829 2680
2830 sdhc2_opp_table: opp- 2681 sdhc2_opp_table: opp-table {
2831 compatible = 2682 compatible = "operating-points-v2";
2832 2683
2833 opp-100000000 2684 opp-100000000 {
2834 opp-h 2685 opp-hz = /bits/ 64 <100000000>;
2835 requi 2686 required-opps = <&rpmhpd_opp_low_svs>;
2836 opp-p 2687 opp-peak-kBps = <1800000 600000>;
2837 opp-a 2688 opp-avg-kBps = <100000 0>;
2838 }; 2689 };
2839 2690
2840 opp-202000000 2691 opp-202000000 {
2841 opp-h 2692 opp-hz = /bits/ 64 <202000000>;
2842 requi 2693 required-opps = <&rpmhpd_opp_nom>;
2843 opp-p 2694 opp-peak-kBps = <5400000 1600000>;
2844 opp-a 2695 opp-avg-kBps = <200000 0>;
2845 }; 2696 };
2846 }; 2697 };
2847 }; 2698 };
2848 2699
2849 qspi: spi@88dc000 { 2700 qspi: spi@88dc000 {
2850 compatible = "qcom,sc 2701 compatible = "qcom,sc7180-qspi", "qcom,qspi-v1";
2851 reg = <0 0x088dc000 0 2702 reg = <0 0x088dc000 0 0x600>;
2852 iommus = <&apps_smmu 2703 iommus = <&apps_smmu 0x20 0x0>;
2853 #address-cells = <1>; 2704 #address-cells = <1>;
2854 #size-cells = <0>; 2705 #size-cells = <0>;
2855 interrupts = <GIC_SPI 2706 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
2856 clocks = <&gcc GCC_QS 2707 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
2857 <&gcc GCC_QS 2708 <&gcc GCC_QSPI_CORE_CLK>;
2858 clock-names = "iface" 2709 clock-names = "iface", "core";
2859 interconnects = <&gem 2710 interconnects = <&gem_noc MASTER_APPSS_PROC 0
2860 &conf 2711 &config_noc SLAVE_QSPI_0 0>;
2861 interconnect-names = 2712 interconnect-names = "qspi-config";
2862 power-domains = <&rpm 2713 power-domains = <&rpmhpd SC7180_CX>;
2863 operating-points-v2 = 2714 operating-points-v2 = <&qspi_opp_table>;
2864 status = "disabled"; 2715 status = "disabled";
2865 }; 2716 };
2866 2717
2867 usb_1_hsphy: phy@88e3000 { 2718 usb_1_hsphy: phy@88e3000 {
2868 compatible = "qcom,sc 2719 compatible = "qcom,sc7180-qusb2-phy", "qcom,qusb2-v2-phy";
2869 reg = <0 0x088e3000 0 2720 reg = <0 0x088e3000 0 0x400>;
2870 status = "disabled"; 2721 status = "disabled";
2871 #phy-cells = <0>; 2722 #phy-cells = <0>;
2872 clocks = <&gcc GCC_US 2723 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2873 <&rpmhcc RPM 2724 <&rpmhcc RPMH_CXO_CLK>;
2874 clock-names = "cfg_ah 2725 clock-names = "cfg_ahb", "ref";
2875 resets = <&gcc GCC_QU 2726 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2876 2727
2877 nvmem-cells = <&qusb2 2728 nvmem-cells = <&qusb2p_hstx_trim>;
2878 }; 2729 };
2879 2730
2880 usb_1_qmpphy: phy@88e8000 { !! 2731 usb_1_qmpphy: phy-wrapper@88e9000 {
2881 compatible = "qcom,sc 2732 compatible = "qcom,sc7180-qmp-usb3-dp-phy";
2882 reg = <0 0x088e8000 0 !! 2733 reg = <0 0x088e9000 0 0x18c>,
>> 2734 <0 0x088e8000 0 0x3c>,
>> 2735 <0 0x088ea000 0 0x18c>;
2883 status = "disabled"; 2736 status = "disabled";
>> 2737 #address-cells = <2>;
>> 2738 #size-cells = <2>;
>> 2739 ranges;
2884 2740
2885 clocks = <&gcc GCC_US 2741 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
>> 2742 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2886 <&gcc GCC_US 2743 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
2887 <&gcc GCC_US !! 2744 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
2888 <&gcc GCC_US !! 2745 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
2889 <&gcc GCC_US <<
2890 clock-names = "aux", <<
2891 "ref", <<
2892 "com_au <<
2893 "usb3_p <<
2894 "cfg_ah <<
2895 2746
2896 resets = <&gcc GCC_US 2747 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
2897 <&gcc GCC_US 2748 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
2898 reset-names = "phy", 2749 reset-names = "phy", "common";
2899 2750
2900 #clock-cells = <1>; !! 2751 usb_1_ssphy: usb3-phy@88e9200 {
2901 #phy-cells = <1>; !! 2752 reg = <0 0x088e9200 0 0x128>,
2902 }; !! 2753 <0 0x088e9400 0 0x200>,
2903 !! 2754 <0 0x088e9c00 0 0x218>,
2904 pmu@90b6300 { !! 2755 <0 0x088e9600 0 0x128>,
2905 compatible = "qcom,sc !! 2756 <0 0x088e9800 0 0x200>,
2906 reg = <0 0x090b6300 0 !! 2757 <0 0x088e9a00 0 0x18>;
2907 interrupts = <GIC_SPI !! 2758 #clock-cells = <0>;
2908 !! 2759 #phy-cells = <0>;
2909 interconnects = <&gem !! 2760 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2910 &gem !! 2761 clock-names = "pipe0";
2911 operating-points-v2 = !! 2762 clock-output-names = "usb3_phy_pipe_clk_src";
2912 <<
2913 cpu_bwmon_opp_table: <<
2914 compatible = <<
2915 <<
2916 opp-0 { <<
2917 opp-p <<
2918 }; <<
2919 <<
2920 opp-1 { <<
2921 opp-p <<
2922 }; <<
2923 <<
2924 opp-2 { <<
2925 opp-p <<
2926 }; <<
2927 <<
2928 opp-3 { <<
2929 opp-p <<
2930 }; <<
2931 <<
2932 opp-4 { <<
2933 opp-p <<
2934 }; <<
2935 <<
2936 opp-5 { <<
2937 opp-p <<
2938 }; <<
2939 }; 2763 };
2940 }; <<
2941 <<
2942 pmu@90cd000 { <<
2943 compatible = "qcom,sc <<
2944 reg = <0 0x090cd000 0 <<
2945 interrupts = <GIC_SPI <<
2946 <<
2947 interconnects = <&mc_ <<
2948 &mc_ <<
2949 operating-points-v2 = <<
2950 <<
2951 llcc_bwmon_opp_table: <<
2952 compatible = <<
2953 <<
2954 opp-0 { <<
2955 opp-p <<
2956 }; <<
2957 <<
2958 opp-1 { <<
2959 opp-p <<
2960 }; <<
2961 <<
2962 opp-2 { <<
2963 opp-p <<
2964 }; <<
2965 2764
2966 opp-3 { !! 2765 dp_phy: dp-phy@88ea200 {
2967 opp-p !! 2766 reg = <0 0x088ea200 0 0x200>,
2968 }; !! 2767 <0 0x088ea400 0 0x200>,
2969 !! 2768 <0 0x088eaa00 0 0x200>,
2970 opp-4 { !! 2769 <0 0x088ea600 0 0x200>,
2971 opp-p !! 2770 <0 0x088ea800 0 0x200>;
2972 }; !! 2771 #clock-cells = <1>;
2973 !! 2772 #phy-cells = <0>;
2974 opp-5 { <<
2975 opp-p <<
2976 }; <<
2977 <<
2978 opp-6 { <<
2979 opp-p <<
2980 }; <<
2981 <<
2982 opp-7 { <<
2983 opp-p <<
2984 }; <<
2985 }; 2773 };
2986 }; 2774 };
2987 2775
2988 dc_noc: interconnect@9160000 2776 dc_noc: interconnect@9160000 {
2989 compatible = "qcom,sc 2777 compatible = "qcom,sc7180-dc-noc";
2990 reg = <0 0x09160000 0 2778 reg = <0 0x09160000 0 0x03200>;
2991 #interconnect-cells = 2779 #interconnect-cells = <2>;
2992 qcom,bcm-voters = <&a 2780 qcom,bcm-voters = <&apps_bcm_voter>;
2993 }; 2781 };
2994 2782
2995 system-cache-controller@92000 2783 system-cache-controller@9200000 {
2996 compatible = "qcom,sc 2784 compatible = "qcom,sc7180-llcc";
2997 reg = <0 0x09200000 0 2785 reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>;
2998 reg-names = "llcc0_ba 2786 reg-names = "llcc0_base", "llcc_broadcast_base";
2999 interrupts = <GIC_SPI 2787 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
3000 }; 2788 };
3001 2789
3002 gem_noc: interconnect@9680000 2790 gem_noc: interconnect@9680000 {
3003 compatible = "qcom,sc 2791 compatible = "qcom,sc7180-gem-noc";
3004 reg = <0 0x09680000 0 2792 reg = <0 0x09680000 0 0x3e200>;
3005 #interconnect-cells = 2793 #interconnect-cells = <2>;
3006 qcom,bcm-voters = <&a 2794 qcom,bcm-voters = <&apps_bcm_voter>;
3007 }; 2795 };
3008 2796
3009 npu_noc: interconnect@9990000 2797 npu_noc: interconnect@9990000 {
3010 compatible = "qcom,sc 2798 compatible = "qcom,sc7180-npu-noc";
3011 reg = <0 0x09990000 0 2799 reg = <0 0x09990000 0 0x1600>;
3012 #interconnect-cells = 2800 #interconnect-cells = <2>;
3013 qcom,bcm-voters = <&a 2801 qcom,bcm-voters = <&apps_bcm_voter>;
3014 }; 2802 };
3015 2803
3016 usb_1: usb@a6f8800 { 2804 usb_1: usb@a6f8800 {
3017 compatible = "qcom,sc 2805 compatible = "qcom,sc7180-dwc3", "qcom,dwc3";
3018 reg = <0 0x0a6f8800 0 2806 reg = <0 0x0a6f8800 0 0x400>;
3019 status = "disabled"; 2807 status = "disabled";
3020 #address-cells = <2>; 2808 #address-cells = <2>;
3021 #size-cells = <2>; 2809 #size-cells = <2>;
3022 ranges; 2810 ranges;
3023 dma-ranges; 2811 dma-ranges;
3024 2812
3025 clocks = <&gcc GCC_CF 2813 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
3026 <&gcc GCC_US 2814 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
3027 <&gcc GCC_AG 2815 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
3028 <&gcc GCC_US 2816 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
3029 <&gcc GCC_US 2817 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
3030 clock-names = "cfg_no 2818 clock-names = "cfg_noc",
3031 "core", 2819 "core",
3032 "iface" 2820 "iface",
3033 "sleep" 2821 "sleep",
3034 "mock_u 2822 "mock_utmi";
3035 2823
3036 assigned-clocks = <&g 2824 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3037 <&g 2825 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
3038 assigned-clock-rates 2826 assigned-clock-rates = <19200000>, <150000000>;
3039 2827
3040 interrupts-extended = !! 2828 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
3041 !! 2829 <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
3042 !! 2830 <&pdc 8 IRQ_TYPE_LEVEL_HIGH>,
3043 !! 2831 <&pdc 9 IRQ_TYPE_LEVEL_HIGH>;
3044 !! 2832 interrupt-names = "hs_phy_irq", "ss_phy_irq",
3045 interrupt-names = "pw !! 2833 "dm_hs_phy_irq", "dp_hs_phy_irq";
3046 "hs <<
3047 "dp <<
3048 "dm <<
3049 "ss <<
3050 2834
3051 power-domains = <&gcc 2835 power-domains = <&gcc USB30_PRIM_GDSC>;
3052 required-opps = <&rpm 2836 required-opps = <&rpmhpd_opp_nom>;
3053 2837
3054 resets = <&gcc GCC_US 2838 resets = <&gcc GCC_USB30_PRIM_BCR>;
3055 2839
3056 interconnects = <&agg 2840 interconnects = <&aggre2_noc MASTER_USB3 0 &mc_virt SLAVE_EBI1 0>,
3057 <&gem 2841 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3 0>;
3058 interconnect-names = 2842 interconnect-names = "usb-ddr", "apps-usb";
3059 2843
3060 wakeup-source; 2844 wakeup-source;
3061 2845
3062 usb_1_dwc3: usb@a6000 2846 usb_1_dwc3: usb@a600000 {
3063 compatible = 2847 compatible = "snps,dwc3";
3064 reg = <0 0x0a 2848 reg = <0 0x0a600000 0 0xe000>;
3065 interrupts = 2849 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
3066 iommus = <&ap 2850 iommus = <&apps_smmu 0x540 0>;
3067 snps,dis_u2_s 2851 snps,dis_u2_susphy_quirk;
3068 snps,dis_enbl 2852 snps,dis_enblslpm_quirk;
3069 snps,parkmode !! 2853 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
3070 phys = <&usb_ <<
3071 phy-names = " 2854 phy-names = "usb2-phy", "usb3-phy";
3072 maximum-speed 2855 maximum-speed = "super-speed";
3073 }; 2856 };
3074 }; 2857 };
3075 2858
3076 venus: video-codec@aa00000 { 2859 venus: video-codec@aa00000 {
3077 compatible = "qcom,sc 2860 compatible = "qcom,sc7180-venus";
3078 reg = <0 0x0aa00000 0 2861 reg = <0 0x0aa00000 0 0xff000>;
3079 interrupts = <GIC_SPI 2862 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
3080 power-domains = <&vid 2863 power-domains = <&videocc VENUS_GDSC>,
3081 <&vid 2864 <&videocc VCODEC0_GDSC>,
3082 <&rpm 2865 <&rpmhpd SC7180_CX>;
3083 power-domain-names = 2866 power-domain-names = "venus", "vcodec0", "cx";
3084 operating-points-v2 = 2867 operating-points-v2 = <&venus_opp_table>;
3085 clocks = <&videocc VI 2868 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
3086 <&videocc VI 2869 <&videocc VIDEO_CC_VENUS_AHB_CLK>,
3087 <&videocc VI 2870 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>,
3088 <&videocc VI 2871 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
3089 <&videocc VI 2872 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>;
3090 clock-names = "core", 2873 clock-names = "core", "iface", "bus",
3091 "vcodec 2874 "vcodec0_core", "vcodec0_bus";
3092 iommus = <&apps_smmu 2875 iommus = <&apps_smmu 0x0c00 0x60>;
3093 memory-region = <&ven 2876 memory-region = <&venus_mem>;
3094 interconnects = <&mms 2877 interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>,
3095 <&gem 2878 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>;
3096 interconnect-names = 2879 interconnect-names = "video-mem", "cpu-cfg";
3097 2880
3098 video-decoder { 2881 video-decoder {
3099 compatible = 2882 compatible = "venus-decoder";
3100 }; 2883 };
3101 2884
3102 video-encoder { 2885 video-encoder {
3103 compatible = 2886 compatible = "venus-encoder";
3104 }; 2887 };
3105 2888
3106 venus_opp_table: opp- 2889 venus_opp_table: opp-table {
3107 compatible = 2890 compatible = "operating-points-v2";
3108 2891
3109 opp-150000000 2892 opp-150000000 {
3110 opp-h 2893 opp-hz = /bits/ 64 <150000000>;
3111 requi 2894 required-opps = <&rpmhpd_opp_low_svs>;
3112 }; 2895 };
3113 2896
3114 opp-270000000 2897 opp-270000000 {
3115 opp-h 2898 opp-hz = /bits/ 64 <270000000>;
3116 requi 2899 required-opps = <&rpmhpd_opp_svs>;
3117 }; 2900 };
3118 2901
3119 opp-340000000 2902 opp-340000000 {
3120 opp-h 2903 opp-hz = /bits/ 64 <340000000>;
3121 requi 2904 required-opps = <&rpmhpd_opp_svs_l1>;
3122 }; 2905 };
3123 2906
3124 opp-434000000 2907 opp-434000000 {
3125 opp-h 2908 opp-hz = /bits/ 64 <434000000>;
3126 requi 2909 required-opps = <&rpmhpd_opp_nom>;
3127 }; 2910 };
3128 2911
3129 opp-500000097 2912 opp-500000097 {
3130 opp-h 2913 opp-hz = /bits/ 64 <500000097>;
3131 requi 2914 required-opps = <&rpmhpd_opp_turbo>;
3132 }; 2915 };
3133 }; 2916 };
3134 }; 2917 };
3135 2918
3136 videocc: clock-controller@ab0 2919 videocc: clock-controller@ab00000 {
3137 compatible = "qcom,sc 2920 compatible = "qcom,sc7180-videocc";
3138 reg = <0 0x0ab00000 0 2921 reg = <0 0x0ab00000 0 0x10000>;
3139 clocks = <&rpmhcc RPM 2922 clocks = <&rpmhcc RPMH_CXO_CLK>;
3140 clock-names = "bi_tcx 2923 clock-names = "bi_tcxo";
3141 #clock-cells = <1>; 2924 #clock-cells = <1>;
3142 #reset-cells = <1>; 2925 #reset-cells = <1>;
3143 #power-domain-cells = 2926 #power-domain-cells = <1>;
3144 }; 2927 };
3145 2928
3146 camnoc_virt: interconnect@ac0 2929 camnoc_virt: interconnect@ac00000 {
3147 compatible = "qcom,sc 2930 compatible = "qcom,sc7180-camnoc-virt";
3148 reg = <0 0x0ac00000 0 2931 reg = <0 0x0ac00000 0 0x1000>;
3149 #interconnect-cells = 2932 #interconnect-cells = <2>;
3150 qcom,bcm-voters = <&a 2933 qcom,bcm-voters = <&apps_bcm_voter>;
3151 }; 2934 };
3152 2935
3153 camcc: clock-controller@ad000 2936 camcc: clock-controller@ad00000 {
3154 compatible = "qcom,sc 2937 compatible = "qcom,sc7180-camcc";
3155 reg = <0 0x0ad00000 0 2938 reg = <0 0x0ad00000 0 0x10000>;
3156 clocks = <&rpmhcc RPM 2939 clocks = <&rpmhcc RPMH_CXO_CLK>,
3157 <&gcc GCC_CAME 2940 <&gcc GCC_CAMERA_AHB_CLK>,
3158 <&gcc GCC_CAME 2941 <&gcc GCC_CAMERA_XO_CLK>;
3159 clock-names = "bi_tcx 2942 clock-names = "bi_tcxo", "iface", "xo";
3160 #clock-cells = <1>; 2943 #clock-cells = <1>;
3161 #reset-cells = <1>; 2944 #reset-cells = <1>;
3162 #power-domain-cells = 2945 #power-domain-cells = <1>;
3163 }; 2946 };
3164 2947
3165 mdss: display-subsystem@ae000 2948 mdss: display-subsystem@ae00000 {
3166 compatible = "qcom,sc 2949 compatible = "qcom,sc7180-mdss";
3167 reg = <0 0x0ae00000 0 2950 reg = <0 0x0ae00000 0 0x1000>;
3168 reg-names = "mdss"; 2951 reg-names = "mdss";
3169 2952
3170 power-domains = <&dis 2953 power-domains = <&dispcc MDSS_GDSC>;
3171 2954
3172 clocks = <&gcc GCC_DI 2955 clocks = <&gcc GCC_DISP_AHB_CLK>,
3173 <&dispcc DIS 2956 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3174 <&dispcc DIS 2957 <&dispcc DISP_CC_MDSS_MDP_CLK>;
3175 clock-names = "iface" 2958 clock-names = "iface", "ahb", "core";
3176 2959
3177 interrupts = <GIC_SPI 2960 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
3178 interrupt-controller; 2961 interrupt-controller;
3179 #interrupt-cells = <1 2962 #interrupt-cells = <1>;
3180 2963
3181 interconnects = <&mms !! 2964 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>;
3182 &mc_ !! 2965 interconnect-names = "mdp0-mem";
3183 <&gem <<
3184 &con <<
3185 interconnect-names = <<
3186 <<
3187 2966
3188 iommus = <&apps_smmu 2967 iommus = <&apps_smmu 0x800 0x2>;
3189 2968
3190 #address-cells = <2>; 2969 #address-cells = <2>;
3191 #size-cells = <2>; 2970 #size-cells = <2>;
3192 ranges; 2971 ranges;
3193 2972
3194 status = "disabled"; 2973 status = "disabled";
3195 2974
3196 mdp: display-controll 2975 mdp: display-controller@ae01000 {
3197 compatible = 2976 compatible = "qcom,sc7180-dpu";
3198 reg = <0 0x0a 2977 reg = <0 0x0ae01000 0 0x8f000>,
3199 <0 0x0a 2978 <0 0x0aeb0000 0 0x2008>;
3200 reg-names = " 2979 reg-names = "mdp", "vbif";
3201 2980
3202 clocks = <&gc 2981 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
3203 <&di 2982 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3204 <&di 2983 <&dispcc DISP_CC_MDSS_ROT_CLK>,
3205 <&di 2984 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
3206 <&di 2985 <&dispcc DISP_CC_MDSS_MDP_CLK>,
3207 <&di 2986 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3208 clock-names = 2987 clock-names = "bus", "iface", "rot", "lut", "core",
3209 2988 "vsync";
3210 assigned-cloc 2989 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
3211 2990 <&dispcc DISP_CC_MDSS_ROT_CLK>,
3212 2991 <&dispcc DISP_CC_MDSS_AHB_CLK>;
3213 assigned-cloc 2992 assigned-clock-rates = <19200000>,
3214 2993 <19200000>,
3215 2994 <19200000>;
3216 operating-poi 2995 operating-points-v2 = <&mdp_opp_table>;
3217 power-domains 2996 power-domains = <&rpmhpd SC7180_CX>;
3218 2997
3219 interrupt-par 2998 interrupt-parent = <&mdss>;
3220 interrupts = 2999 interrupts = <0>;
3221 3000
3222 ports { 3001 ports {
3223 #addr 3002 #address-cells = <1>;
3224 #size 3003 #size-cells = <0>;
3225 3004
3226 port@ 3005 port@0 {
3227 3006 reg = <0>;
3228 3007 dpu_intf1_out: endpoint {
3229 3008 remote-endpoint = <&mdss_dsi0_in>;
3230 3009 };
3231 }; 3010 };
3232 3011
3233 port@ 3012 port@2 {
3234 3013 reg = <2>;
3235 3014 dpu_intf0_out: endpoint {
3236 3015 remote-endpoint = <&dp_in>;
3237 3016 };
3238 }; 3017 };
3239 }; 3018 };
3240 3019
3241 mdp_opp_table 3020 mdp_opp_table: opp-table {
3242 compa 3021 compatible = "operating-points-v2";
3243 3022
3244 opp-2 3023 opp-200000000 {
3245 3024 opp-hz = /bits/ 64 <200000000>;
3246 3025 required-opps = <&rpmhpd_opp_low_svs>;
3247 }; 3026 };
3248 3027
3249 opp-3 3028 opp-300000000 {
3250 3029 opp-hz = /bits/ 64 <300000000>;
3251 3030 required-opps = <&rpmhpd_opp_svs>;
3252 }; 3031 };
3253 3032
3254 opp-3 3033 opp-345000000 {
3255 3034 opp-hz = /bits/ 64 <345000000>;
3256 3035 required-opps = <&rpmhpd_opp_svs_l1>;
3257 }; 3036 };
3258 3037
3259 opp-4 3038 opp-460000000 {
3260 3039 opp-hz = /bits/ 64 <460000000>;
3261 3040 required-opps = <&rpmhpd_opp_nom>;
3262 }; 3041 };
3263 }; 3042 };
3264 }; 3043 };
3265 3044
3266 mdss_dsi0: dsi@ae9400 3045 mdss_dsi0: dsi@ae94000 {
3267 compatible = 3046 compatible = "qcom,sc7180-dsi-ctrl",
3268 3047 "qcom,mdss-dsi-ctrl";
3269 reg = <0 0x0a 3048 reg = <0 0x0ae94000 0 0x400>;
3270 reg-names = " 3049 reg-names = "dsi_ctrl";
3271 3050
3272 interrupt-par 3051 interrupt-parent = <&mdss>;
3273 interrupts = 3052 interrupts = <4>;
3274 3053
3275 clocks = <&di 3054 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
3276 <&di 3055 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
3277 <&di 3056 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
3278 <&di 3057 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
3279 <&di 3058 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3280 <&gc 3059 <&gcc GCC_DISP_HF_AXI_CLK>;
3281 clock-names = 3060 clock-names = "byte",
3282 3061 "byte_intf",
3283 3062 "pixel",
3284 3063 "core",
3285 3064 "iface",
3286 3065 "bus";
3287 3066
3288 assigned-cloc 3067 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
3289 assigned-cloc 3068 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
3290 3069
3291 operating-poi 3070 operating-points-v2 = <&dsi_opp_table>;
3292 power-domains 3071 power-domains = <&rpmhpd SC7180_CX>;
3293 3072
3294 phys = <&mdss 3073 phys = <&mdss_dsi0_phy>;
3295 3074
3296 #address-cell 3075 #address-cells = <1>;
3297 #size-cells = 3076 #size-cells = <0>;
3298 3077
3299 status = "dis 3078 status = "disabled";
3300 3079
3301 ports { 3080 ports {
3302 #addr 3081 #address-cells = <1>;
3303 #size 3082 #size-cells = <0>;
3304 3083
3305 port@ 3084 port@0 {
3306 3085 reg = <0>;
3307 3086 mdss_dsi0_in: endpoint {
3308 3087 remote-endpoint = <&dpu_intf1_out>;
3309 3088 };
3310 }; 3089 };
3311 3090
3312 port@ 3091 port@1 {
3313 3092 reg = <1>;
3314 3093 mdss_dsi0_out: endpoint {
3315 3094 };
3316 }; 3095 };
3317 }; 3096 };
3318 3097
3319 dsi_opp_table 3098 dsi_opp_table: opp-table {
3320 compa 3099 compatible = "operating-points-v2";
3321 3100
3322 opp-1 3101 opp-187500000 {
3323 3102 opp-hz = /bits/ 64 <187500000>;
3324 3103 required-opps = <&rpmhpd_opp_low_svs>;
3325 }; 3104 };
3326 3105
3327 opp-3 3106 opp-300000000 {
3328 3107 opp-hz = /bits/ 64 <300000000>;
3329 3108 required-opps = <&rpmhpd_opp_svs>;
3330 }; 3109 };
3331 3110
3332 opp-3 3111 opp-358000000 {
3333 3112 opp-hz = /bits/ 64 <358000000>;
3334 3113 required-opps = <&rpmhpd_opp_svs_l1>;
3335 }; 3114 };
3336 }; 3115 };
3337 }; 3116 };
3338 3117
3339 mdss_dsi0_phy: phy@ae 3118 mdss_dsi0_phy: phy@ae94400 {
3340 compatible = 3119 compatible = "qcom,dsi-phy-10nm";
3341 reg = <0 0x0a 3120 reg = <0 0x0ae94400 0 0x200>,
3342 <0 0x0a 3121 <0 0x0ae94600 0 0x280>,
3343 <0 0x0a 3122 <0 0x0ae94a00 0 0x1e0>;
3344 reg-names = " 3123 reg-names = "dsi_phy",
3345 " 3124 "dsi_phy_lane",
3346 " 3125 "dsi_pll";
3347 3126
3348 #clock-cells 3127 #clock-cells = <1>;
3349 #phy-cells = 3128 #phy-cells = <0>;
3350 3129
3351 clocks = <&di 3130 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3352 <&rp 3131 <&rpmhcc RPMH_CXO_CLK>;
3353 clock-names = 3132 clock-names = "iface", "ref";
3354 3133
3355 status = "dis 3134 status = "disabled";
3356 }; 3135 };
3357 3136
3358 mdss_dp: displayport- 3137 mdss_dp: displayport-controller@ae90000 {
3359 compatible = 3138 compatible = "qcom,sc7180-dp";
3360 status = "dis 3139 status = "disabled";
3361 3140
3362 reg = <0 0x0a 3141 reg = <0 0x0ae90000 0 0x200>,
3363 <0 0x0a 3142 <0 0x0ae90200 0 0x200>,
3364 <0 0x0a 3143 <0 0x0ae90400 0 0xc00>,
3365 <0 0x0a 3144 <0 0x0ae91000 0 0x400>,
3366 <0 0x0a 3145 <0 0x0ae91400 0 0x400>;
3367 3146
3368 interrupt-par 3147 interrupt-parent = <&mdss>;
3369 interrupts = 3148 interrupts = <12>;
3370 3149
3371 clocks = <&di 3150 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3372 <&di 3151 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
3373 <&di 3152 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
3374 <&di 3153 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
3375 <&di 3154 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
3376 clock-names = 3155 clock-names = "core_iface", "core_aux", "ctrl_link",
3377 3156 "ctrl_link_iface", "stream_pixel";
3378 assigned-cloc 3157 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
3379 3158 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
3380 assigned-cloc !! 3159 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
3381 !! 3160 phys = <&dp_phy>;
3382 phys = <&usb_ <<
3383 phy-names = " 3161 phy-names = "dp";
3384 3162
3385 operating-poi 3163 operating-points-v2 = <&dp_opp_table>;
3386 power-domains 3164 power-domains = <&rpmhpd SC7180_CX>;
3387 3165
3388 #sound-dai-ce 3166 #sound-dai-cells = <0>;
3389 3167
3390 ports { 3168 ports {
3391 #addr 3169 #address-cells = <1>;
3392 #size 3170 #size-cells = <0>;
3393 port@ 3171 port@0 {
3394 3172 reg = <0>;
3395 3173 dp_in: endpoint {
3396 3174 remote-endpoint = <&dpu_intf0_out>;
3397 3175 };
3398 }; 3176 };
3399 3177
3400 port@ 3178 port@1 {
3401 3179 reg = <1>;
3402 3180 mdss_dp_out: endpoint { };
3403 }; 3181 };
3404 }; 3182 };
3405 3183
3406 dp_opp_table: 3184 dp_opp_table: opp-table {
3407 compa 3185 compatible = "operating-points-v2";
3408 3186
3409 opp-1 3187 opp-160000000 {
3410 3188 opp-hz = /bits/ 64 <160000000>;
3411 3189 required-opps = <&rpmhpd_opp_low_svs>;
3412 }; 3190 };
3413 3191
3414 opp-2 3192 opp-270000000 {
3415 3193 opp-hz = /bits/ 64 <270000000>;
3416 3194 required-opps = <&rpmhpd_opp_svs>;
3417 }; 3195 };
3418 3196
3419 opp-5 3197 opp-540000000 {
3420 3198 opp-hz = /bits/ 64 <540000000>;
3421 3199 required-opps = <&rpmhpd_opp_svs_l1>;
3422 }; 3200 };
3423 3201
3424 opp-8 3202 opp-810000000 {
3425 3203 opp-hz = /bits/ 64 <810000000>;
3426 3204 required-opps = <&rpmhpd_opp_nom>;
3427 }; 3205 };
3428 }; 3206 };
3429 }; 3207 };
3430 }; 3208 };
3431 3209
3432 dispcc: clock-controller@af00 3210 dispcc: clock-controller@af00000 {
3433 compatible = "qcom,sc 3211 compatible = "qcom,sc7180-dispcc";
3434 reg = <0 0x0af00000 0 3212 reg = <0 0x0af00000 0 0x200000>;
3435 clocks = <&rpmhcc RPM 3213 clocks = <&rpmhcc RPMH_CXO_CLK>,
3436 <&gcc GCC_DI 3214 <&gcc GCC_DISP_GPLL0_CLK_SRC>,
3437 <&mdss_dsi0_ 3215 <&mdss_dsi0_phy 0>,
3438 <&mdss_dsi0_ 3216 <&mdss_dsi0_phy 1>,
3439 <&usb_1_qmpp !! 3217 <&dp_phy 0>,
3440 <&usb_1_qmpp !! 3218 <&dp_phy 1>;
3441 clock-names = "bi_tcx 3219 clock-names = "bi_tcxo",
3442 "gcc_di 3220 "gcc_disp_gpll0_clk_src",
3443 "dsi0_p 3221 "dsi0_phy_pll_out_byteclk",
3444 "dsi0_p 3222 "dsi0_phy_pll_out_dsiclk",
3445 "dp_phy 3223 "dp_phy_pll_link_clk",
3446 "dp_phy 3224 "dp_phy_pll_vco_div_clk";
3447 #clock-cells = <1>; 3225 #clock-cells = <1>;
3448 #reset-cells = <1>; 3226 #reset-cells = <1>;
3449 #power-domain-cells = 3227 #power-domain-cells = <1>;
3450 }; 3228 };
3451 3229
3452 pdc: interrupt-controller@b22 3230 pdc: interrupt-controller@b220000 {
3453 compatible = "qcom,sc 3231 compatible = "qcom,sc7180-pdc", "qcom,pdc";
3454 reg = <0 0x0b220000 0 3232 reg = <0 0x0b220000 0 0x30000>;
3455 qcom,pdc-ranges = <0 3233 qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>;
3456 #interrupt-cells = <2 3234 #interrupt-cells = <2>;
3457 interrupt-parent = <& 3235 interrupt-parent = <&intc>;
3458 interrupt-controller; 3236 interrupt-controller;
3459 }; 3237 };
3460 3238
3461 pdc_reset: reset-controller@b 3239 pdc_reset: reset-controller@b2e0000 {
3462 compatible = "qcom,sc 3240 compatible = "qcom,sc7180-pdc-global", "qcom,sdm845-pdc-global";
3463 reg = <0 0x0b2e0000 0 3241 reg = <0 0x0b2e0000 0 0x20000>;
3464 #reset-cells = <1>; 3242 #reset-cells = <1>;
3465 }; 3243 };
3466 3244
3467 tsens0: thermal-sensor@c26300 3245 tsens0: thermal-sensor@c263000 {
3468 compatible = "qcom,sc 3246 compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
3469 reg = <0 0x0c263000 0 3247 reg = <0 0x0c263000 0 0x1ff>, /* TM */
3470 <0 0x0c222000 3248 <0 0x0c222000 0 0x1ff>; /* SROT */
3471 #qcom,sensors = <15>; 3249 #qcom,sensors = <15>;
3472 interrupts = <GIC_SPI 3250 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
3473 <GIC_SPI 3251 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
3474 interrupt-names = "up 3252 interrupt-names = "uplow","critical";
3475 #thermal-sensor-cells 3253 #thermal-sensor-cells = <1>;
3476 }; 3254 };
3477 3255
3478 tsens1: thermal-sensor@c26500 3256 tsens1: thermal-sensor@c265000 {
3479 compatible = "qcom,sc 3257 compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
3480 reg = <0 0x0c265000 0 3258 reg = <0 0x0c265000 0 0x1ff>, /* TM */
3481 <0 0x0c223000 3259 <0 0x0c223000 0 0x1ff>; /* SROT */
3482 #qcom,sensors = <10>; 3260 #qcom,sensors = <10>;
3483 interrupts = <GIC_SPI 3261 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
3484 <GIC_SPI 3262 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
3485 interrupt-names = "up 3263 interrupt-names = "uplow","critical";
3486 #thermal-sensor-cells 3264 #thermal-sensor-cells = <1>;
3487 }; 3265 };
3488 3266
3489 aoss_reset: reset-controller@ 3267 aoss_reset: reset-controller@c2a0000 {
3490 compatible = "qcom,sc 3268 compatible = "qcom,sc7180-aoss-cc", "qcom,sdm845-aoss-cc";
3491 reg = <0 0x0c2a0000 0 3269 reg = <0 0x0c2a0000 0 0x31000>;
3492 #reset-cells = <1>; 3270 #reset-cells = <1>;
3493 }; 3271 };
3494 3272
3495 aoss_qmp: power-management@c3 3273 aoss_qmp: power-management@c300000 {
3496 compatible = "qcom,sc 3274 compatible = "qcom,sc7180-aoss-qmp", "qcom,aoss-qmp";
3497 reg = <0 0x0c300000 0 3275 reg = <0 0x0c300000 0 0x400>;
3498 interrupts = <GIC_SPI 3276 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
3499 mboxes = <&apss_share 3277 mboxes = <&apss_shared 0>;
3500 3278
3501 #clock-cells = <0>; 3279 #clock-cells = <0>;
3502 }; 3280 };
3503 3281
3504 sram@c3f0000 { 3282 sram@c3f0000 {
3505 compatible = "qcom,rp 3283 compatible = "qcom,rpmh-stats";
3506 reg = <0 0x0c3f0000 0 3284 reg = <0 0x0c3f0000 0 0x400>;
3507 }; 3285 };
3508 3286
3509 spmi_bus: spmi@c440000 { 3287 spmi_bus: spmi@c440000 {
3510 compatible = "qcom,sp 3288 compatible = "qcom,spmi-pmic-arb";
3511 reg = <0 0x0c440000 0 3289 reg = <0 0x0c440000 0 0x1100>,
3512 <0 0x0c600000 0 3290 <0 0x0c600000 0 0x2000000>,
3513 <0 0x0e600000 0 3291 <0 0x0e600000 0 0x100000>,
3514 <0 0x0e700000 0 3292 <0 0x0e700000 0 0xa0000>,
3515 <0 0x0c40a000 0 3293 <0 0x0c40a000 0 0x26000>;
3516 reg-names = "core", " 3294 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3517 interrupt-names = "pe 3295 interrupt-names = "periph_irq";
3518 interrupts-extended = 3296 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3519 qcom,ee = <0>; 3297 qcom,ee = <0>;
3520 qcom,channel = <0>; 3298 qcom,channel = <0>;
3521 #address-cells = <2>; 3299 #address-cells = <2>;
3522 #size-cells = <0>; 3300 #size-cells = <0>;
3523 interrupt-controller; 3301 interrupt-controller;
3524 #interrupt-cells = <4 3302 #interrupt-cells = <4>;
3525 }; 3303 };
3526 3304
3527 sram@146aa000 { 3305 sram@146aa000 {
3528 compatible = "qcom,sc 3306 compatible = "qcom,sc7180-imem", "syscon", "simple-mfd";
3529 reg = <0 0x146aa000 0 3307 reg = <0 0x146aa000 0 0x2000>;
3530 3308
3531 #address-cells = <1>; 3309 #address-cells = <1>;
3532 #size-cells = <1>; 3310 #size-cells = <1>;
3533 3311
3534 ranges = <0 0 0x146aa 3312 ranges = <0 0 0x146aa000 0x2000>;
3535 3313
3536 pil-reloc@94c { 3314 pil-reloc@94c {
3537 compatible = 3315 compatible = "qcom,pil-reloc-info";
3538 reg = <0x94c 3316 reg = <0x94c 0xc8>;
3539 }; 3317 };
3540 }; 3318 };
3541 3319
3542 apps_smmu: iommu@15000000 { 3320 apps_smmu: iommu@15000000 {
3543 compatible = "qcom,sc 3321 compatible = "qcom,sc7180-smmu-500", "arm,mmu-500";
3544 reg = <0 0x15000000 0 3322 reg = <0 0x15000000 0 0x100000>;
3545 #iommu-cells = <2>; 3323 #iommu-cells = <2>;
3546 #global-interrupts = 3324 #global-interrupts = <1>;
3547 interrupts = <GIC_SPI 3325 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
3548 <GIC_SPI 3326 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
3549 <GIC_SPI 3327 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
3550 <GIC_SPI 3328 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
3551 <GIC_SPI 3329 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
3552 <GIC_SPI 3330 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
3553 <GIC_SPI 3331 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
3554 <GIC_SPI 3332 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
3555 <GIC_SPI 3333 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
3556 <GIC_SPI 3334 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
3557 <GIC_SPI 3335 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
3558 <GIC_SPI 3336 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
3559 <GIC_SPI 3337 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
3560 <GIC_SPI 3338 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
3561 <GIC_SPI 3339 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
3562 <GIC_SPI 3340 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
3563 <GIC_SPI 3341 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
3564 <GIC_SPI 3342 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
3565 <GIC_SPI 3343 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
3566 <GIC_SPI 3344 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
3567 <GIC_SPI 3345 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
3568 <GIC_SPI 3346 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
3569 <GIC_SPI 3347 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
3570 <GIC_SPI 3348 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
3571 <GIC_SPI 3349 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
3572 <GIC_SPI 3350 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
3573 <GIC_SPI 3351 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
3574 <GIC_SPI 3352 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
3575 <GIC_SPI 3353 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
3576 <GIC_SPI 3354 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
3577 <GIC_SPI 3355 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
3578 <GIC_SPI 3356 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
3579 <GIC_SPI 3357 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
3580 <GIC_SPI 3358 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
3581 <GIC_SPI 3359 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
3582 <GIC_SPI 3360 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
3583 <GIC_SPI 3361 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
3584 <GIC_SPI 3362 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
3585 <GIC_SPI 3363 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
3586 <GIC_SPI 3364 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
3587 <GIC_SPI 3365 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
3588 <GIC_SPI 3366 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
3589 <GIC_SPI 3367 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
3590 <GIC_SPI 3368 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
3591 <GIC_SPI 3369 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
3592 <GIC_SPI 3370 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
3593 <GIC_SPI 3371 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
3594 <GIC_SPI 3372 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
3595 <GIC_SPI 3373 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
3596 <GIC_SPI 3374 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
3597 <GIC_SPI 3375 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
3598 <GIC_SPI 3376 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
3599 <GIC_SPI 3377 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
3600 <GIC_SPI 3378 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
3601 <GIC_SPI 3379 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
3602 <GIC_SPI 3380 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
3603 <GIC_SPI 3381 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
3604 <GIC_SPI 3382 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
3605 <GIC_SPI 3383 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
3606 <GIC_SPI 3384 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
3607 <GIC_SPI 3385 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
3608 <GIC_SPI 3386 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
3609 <GIC_SPI 3387 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
3610 <GIC_SPI 3388 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
3611 <GIC_SPI 3389 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
3612 <GIC_SPI 3390 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
3613 <GIC_SPI 3391 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
3614 <GIC_SPI 3392 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
3615 <GIC_SPI 3393 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
3616 <GIC_SPI 3394 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
3617 <GIC_SPI 3395 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
3618 <GIC_SPI 3396 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
3619 <GIC_SPI 3397 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
3620 <GIC_SPI 3398 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
3621 <GIC_SPI 3399 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
3622 <GIC_SPI 3400 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
3623 <GIC_SPI 3401 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
3624 <GIC_SPI 3402 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
3625 <GIC_SPI 3403 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
3626 <GIC_SPI 3404 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
3627 <GIC_SPI 3405 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
3628 }; 3406 };
3629 3407
3630 intc: interrupt-controller@17 3408 intc: interrupt-controller@17a00000 {
3631 compatible = "arm,gic 3409 compatible = "arm,gic-v3";
3632 #address-cells = <2>; 3410 #address-cells = <2>;
3633 #size-cells = <2>; 3411 #size-cells = <2>;
3634 ranges; 3412 ranges;
3635 #interrupt-cells = <3 3413 #interrupt-cells = <3>;
3636 interrupt-controller; 3414 interrupt-controller;
3637 reg = <0 0x17a00000 0 3415 reg = <0 0x17a00000 0 0x10000>, /* GICD */
3638 <0 0x17a60000 0 3416 <0 0x17a60000 0 0x100000>; /* GICR * 8 */
3639 interrupts = <GIC_PPI 3417 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3640 3418
3641 msi-controller@17a400 3419 msi-controller@17a40000 {
3642 compatible = 3420 compatible = "arm,gic-v3-its";
3643 msi-controlle 3421 msi-controller;
3644 #msi-cells = 3422 #msi-cells = <1>;
3645 reg = <0 0x17 3423 reg = <0 0x17a40000 0 0x20000>;
3646 status = "dis 3424 status = "disabled";
3647 }; 3425 };
3648 }; 3426 };
3649 3427
3650 apss_shared: mailbox@17c00000 3428 apss_shared: mailbox@17c00000 {
3651 compatible = "qcom,sc 3429 compatible = "qcom,sc7180-apss-shared",
3652 "qcom,sd 3430 "qcom,sdm845-apss-shared";
3653 reg = <0 0x17c00000 0 3431 reg = <0 0x17c00000 0 0x10000>;
3654 #mbox-cells = <1>; 3432 #mbox-cells = <1>;
3655 }; 3433 };
3656 3434
3657 watchdog@17c10000 { 3435 watchdog@17c10000 {
3658 compatible = "qcom,ap 3436 compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt";
3659 reg = <0 0x17c10000 0 3437 reg = <0 0x17c10000 0 0x1000>;
3660 clocks = <&sleep_clk> 3438 clocks = <&sleep_clk>;
3661 interrupts = <GIC_SPI !! 3439 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
3662 }; 3440 };
3663 3441
3664 timer@17c20000 { 3442 timer@17c20000 {
3665 #address-cells = <1>; 3443 #address-cells = <1>;
3666 #size-cells = <1>; 3444 #size-cells = <1>;
3667 ranges = <0 0 0 0x200 3445 ranges = <0 0 0 0x20000000>;
3668 compatible = "arm,arm 3446 compatible = "arm,armv7-timer-mem";
3669 reg = <0 0x17c20000 0 3447 reg = <0 0x17c20000 0 0x1000>;
3670 3448
3671 frame@17c21000 { 3449 frame@17c21000 {
3672 frame-number 3450 frame-number = <0>;
3673 interrupts = 3451 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
3674 3452 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
3675 reg = <0x17c2 3453 reg = <0x17c21000 0x1000>,
3676 <0x17c2 3454 <0x17c22000 0x1000>;
3677 }; 3455 };
3678 3456
3679 frame@17c23000 { 3457 frame@17c23000 {
3680 frame-number 3458 frame-number = <1>;
3681 interrupts = 3459 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
3682 reg = <0x17c2 3460 reg = <0x17c23000 0x1000>;
3683 status = "dis 3461 status = "disabled";
3684 }; 3462 };
3685 3463
3686 frame@17c25000 { 3464 frame@17c25000 {
3687 frame-number 3465 frame-number = <2>;
3688 interrupts = 3466 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
3689 reg = <0x17c2 3467 reg = <0x17c25000 0x1000>;
3690 status = "dis 3468 status = "disabled";
3691 }; 3469 };
3692 3470
3693 frame@17c27000 { 3471 frame@17c27000 {
3694 frame-number 3472 frame-number = <3>;
3695 interrupts = 3473 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3696 reg = <0x17c2 3474 reg = <0x17c27000 0x1000>;
3697 status = "dis 3475 status = "disabled";
3698 }; 3476 };
3699 3477
3700 frame@17c29000 { 3478 frame@17c29000 {
3701 frame-number 3479 frame-number = <4>;
3702 interrupts = 3480 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3703 reg = <0x17c2 3481 reg = <0x17c29000 0x1000>;
3704 status = "dis 3482 status = "disabled";
3705 }; 3483 };
3706 3484
3707 frame@17c2b000 { 3485 frame@17c2b000 {
3708 frame-number 3486 frame-number = <5>;
3709 interrupts = 3487 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3710 reg = <0x17c2 3488 reg = <0x17c2b000 0x1000>;
3711 status = "dis 3489 status = "disabled";
3712 }; 3490 };
3713 3491
3714 frame@17c2d000 { 3492 frame@17c2d000 {
3715 frame-number 3493 frame-number = <6>;
3716 interrupts = 3494 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
3717 reg = <0x17c2 3495 reg = <0x17c2d000 0x1000>;
3718 status = "dis 3496 status = "disabled";
3719 }; 3497 };
3720 }; 3498 };
3721 3499
3722 apps_rsc: rsc@18200000 { 3500 apps_rsc: rsc@18200000 {
3723 compatible = "qcom,rp 3501 compatible = "qcom,rpmh-rsc";
3724 reg = <0 0x18200000 0 3502 reg = <0 0x18200000 0 0x10000>,
3725 <0 0x18210000 0 3503 <0 0x18210000 0 0x10000>,
3726 <0 0x18220000 0 3504 <0 0x18220000 0 0x10000>;
3727 reg-names = "drv-0", 3505 reg-names = "drv-0", "drv-1", "drv-2";
3728 interrupts = <GIC_SPI 3506 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
3729 <GIC_SPI 3507 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
3730 <GIC_SPI 3508 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
3731 qcom,tcs-offset = <0x 3509 qcom,tcs-offset = <0xd00>;
3732 qcom,drv-id = <2>; 3510 qcom,drv-id = <2>;
3733 qcom,tcs-config = <AC 3511 qcom,tcs-config = <ACTIVE_TCS 2>,
3734 <SL 3512 <SLEEP_TCS 3>,
3735 <WA 3513 <WAKE_TCS 3>,
3736 <CO 3514 <CONTROL_TCS 1>;
3737 power-domains = <&CLU <<
3738 3515
3739 rpmhcc: clock-control 3516 rpmhcc: clock-controller {
3740 compatible = 3517 compatible = "qcom,sc7180-rpmh-clk";
3741 clocks = <&xo 3518 clocks = <&xo_board>;
3742 clock-names = 3519 clock-names = "xo";
3743 #clock-cells 3520 #clock-cells = <1>;
3744 }; 3521 };
3745 3522
3746 rpmhpd: power-control 3523 rpmhpd: power-controller {
3747 compatible = 3524 compatible = "qcom,sc7180-rpmhpd";
3748 #power-domain 3525 #power-domain-cells = <1>;
3749 operating-poi 3526 operating-points-v2 = <&rpmhpd_opp_table>;
3750 3527
3751 rpmhpd_opp_ta 3528 rpmhpd_opp_table: opp-table {
3752 compa 3529 compatible = "operating-points-v2";
3753 3530
3754 rpmhp 3531 rpmhpd_opp_ret: opp1 {
3755 3532 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3756 }; 3533 };
3757 3534
3758 rpmhp 3535 rpmhpd_opp_min_svs: opp2 {
3759 3536 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3760 }; 3537 };
3761 3538
3762 rpmhp 3539 rpmhpd_opp_low_svs: opp3 {
3763 3540 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3764 }; 3541 };
3765 3542
3766 rpmhp 3543 rpmhpd_opp_svs: opp4 {
3767 3544 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3768 }; 3545 };
3769 3546
3770 rpmhp 3547 rpmhpd_opp_svs_l1: opp5 {
3771 3548 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3772 }; 3549 };
3773 3550
3774 rpmhp 3551 rpmhpd_opp_svs_l2: opp6 {
3775 3552 opp-level = <224>;
3776 }; 3553 };
3777 3554
3778 rpmhp 3555 rpmhpd_opp_nom: opp7 {
3779 3556 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3780 }; 3557 };
3781 3558
3782 rpmhp 3559 rpmhpd_opp_nom_l1: opp8 {
3783 3560 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3784 }; 3561 };
3785 3562
3786 rpmhp 3563 rpmhpd_opp_nom_l2: opp9 {
3787 3564 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3788 }; 3565 };
3789 3566
3790 rpmhp 3567 rpmhpd_opp_turbo: opp10 {
3791 3568 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3792 }; 3569 };
3793 3570
3794 rpmhp 3571 rpmhpd_opp_turbo_l1: opp11 {
3795 3572 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3796 }; 3573 };
3797 }; 3574 };
3798 }; 3575 };
3799 3576
3800 apps_bcm_voter: bcm-v 3577 apps_bcm_voter: bcm-voter {
3801 compatible = 3578 compatible = "qcom,bcm-voter";
3802 }; 3579 };
3803 }; 3580 };
3804 3581
3805 osm_l3: interconnect@18321000 3582 osm_l3: interconnect@18321000 {
3806 compatible = "qcom,sc 3583 compatible = "qcom,sc7180-osm-l3", "qcom,osm-l3";
3807 reg = <0 0x18321000 0 3584 reg = <0 0x18321000 0 0x1400>;
3808 3585
3809 clocks = <&rpmhcc RPM 3586 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3810 clock-names = "xo", " 3587 clock-names = "xo", "alternate";
3811 3588
3812 #interconnect-cells = 3589 #interconnect-cells = <1>;
3813 }; 3590 };
3814 3591
3815 cpufreq_hw: cpufreq@18323000 3592 cpufreq_hw: cpufreq@18323000 {
3816 compatible = "qcom,sc 3593 compatible = "qcom,sc7180-cpufreq-hw", "qcom,cpufreq-hw";
3817 reg = <0 0x18323000 0 3594 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>;
3818 reg-names = "freq-dom 3595 reg-names = "freq-domain0", "freq-domain1";
3819 3596
3820 clocks = <&rpmhcc RPM 3597 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3821 clock-names = "xo", " 3598 clock-names = "xo", "alternate";
3822 3599
3823 #freq-domain-cells = 3600 #freq-domain-cells = <1>;
3824 #clock-cells = <1>; 3601 #clock-cells = <1>;
3825 }; 3602 };
3826 3603
3827 wifi: wifi@18800000 { 3604 wifi: wifi@18800000 {
3828 compatible = "qcom,wc 3605 compatible = "qcom,wcn3990-wifi";
3829 reg = <0 0x18800000 0 3606 reg = <0 0x18800000 0 0x800000>;
3830 reg-names = "membase" 3607 reg-names = "membase";
3831 iommus = <&apps_smmu 3608 iommus = <&apps_smmu 0xc0 0x1>;
3832 interrupts = 3609 interrupts =
3833 <GIC_SPI 414 3610 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH /* CE0 */ >,
3834 <GIC_SPI 415 3611 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH /* CE1 */ >,
3835 <GIC_SPI 416 3612 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH /* CE2 */ >,
3836 <GIC_SPI 417 3613 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH /* CE3 */ >,
3837 <GIC_SPI 418 3614 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH /* CE4 */ >,
3838 <GIC_SPI 419 3615 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH /* CE5 */ >,
3839 <GIC_SPI 420 3616 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH /* CE6 */ >,
3840 <GIC_SPI 421 3617 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH /* CE7 */ >,
3841 <GIC_SPI 422 3618 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH /* CE8 */ >,
3842 <GIC_SPI 423 3619 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH /* CE9 */ >,
3843 <GIC_SPI 424 3620 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH /* CE10 */>,
3844 <GIC_SPI 425 3621 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH /* CE11 */>;
3845 memory-region = <&wla 3622 memory-region = <&wlan_mem>;
3846 qcom,msa-fixed-perm; 3623 qcom,msa-fixed-perm;
3847 status = "disabled"; 3624 status = "disabled";
3848 }; 3625 };
3849 3626
3850 remoteproc_adsp: remoteproc@6 <<
3851 compatible = "qcom,sc <<
3852 reg = <0 0x62400000 0 <<
3853 <<
3854 interrupts-extended = <<
3855 <<
3856 <<
3857 <<
3858 <<
3859 interrupt-names = "wd <<
3860 "fa <<
3861 "re <<
3862 "ha <<
3863 "st <<
3864 <<
3865 clocks = <&rpmhcc RPM <<
3866 clock-names = "xo"; <<
3867 <<
3868 power-domains = <&rpm <<
3869 <&rpm <<
3870 power-domain-names = <<
3871 <<
3872 qcom,qmp = <&aoss_qmp <<
3873 qcom,smem-states = <& <<
3874 qcom,smem-state-names <<
3875 <<
3876 status = "disabled"; <<
3877 <<
3878 glink-edge { <<
3879 interrupts = <<
3880 label = "lpas <<
3881 qcom,remote-p <<
3882 mboxes = <&ap <<
3883 <<
3884 apr { <<
3885 compa <<
3886 qcom, <<
3887 qcom, <<
3888 #addr <<
3889 #size <<
3890 <<
3891 servi <<
3892 <<
3893 <<
3894 <<
3895 }; <<
3896 <<
3897 q6afe <<
3898 <<
3899 <<
3900 <<
3901 <<
3902 <<
3903 <<
3904 <<
3905 <<
3906 <<
3907 <<
3908 <<
3909 <<
3910 <<
3911 <<
3912 <<
3913 }; <<
3914 <<
3915 q6asm <<
3916 <<
3917 <<
3918 <<
3919 <<
3920 <<
3921 <<
3922 <<
3923 <<
3924 <<
3925 <<
3926 <<
3927 }; <<
3928 <<
3929 q6adm <<
3930 <<
3931 <<
3932 <<
3933 <<
3934 <<
3935 <<
3936 <<
3937 <<
3938 }; <<
3939 }; <<
3940 <<
3941 fastrpc { <<
3942 compa <<
3943 qcom, <<
3944 label <<
3945 #addr <<
3946 #size <<
3947 <<
3948 compu <<
3949 <<
3950 <<
3951 <<
3952 }; <<
3953 <<
3954 compu <<
3955 <<
3956 <<
3957 <<
3958 }; <<
3959 <<
3960 compu <<
3961 <<
3962 <<
3963 <<
3964 <<
3965 }; <<
3966 }; <<
3967 }; <<
3968 }; <<
3969 <<
3970 lpasscc: clock-controller@62d 3627 lpasscc: clock-controller@62d00000 {
3971 compatible = "qcom,sc 3628 compatible = "qcom,sc7180-lpasscorecc";
3972 reg = <0 0x62d00000 0 3629 reg = <0 0x62d00000 0 0x50000>,
3973 <0 0x62780000 0 3630 <0 0x62780000 0 0x30000>;
3974 reg-names = "lpass_co 3631 reg-names = "lpass_core_cc", "lpass_audio_cc";
3975 clocks = <&gcc GCC_LP 3632 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>,
3976 <&rpmhcc RPM 3633 <&rpmhcc RPMH_CXO_CLK>;
3977 clock-names = "iface" 3634 clock-names = "iface", "bi_tcxo";
3978 power-domains = <&lpa 3635 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>;
3979 #clock-cells = <1>; 3636 #clock-cells = <1>;
3980 #power-domain-cells = 3637 #power-domain-cells = <1>;
3981 3638
3982 status = "reserved"; 3639 status = "reserved"; /* Controlled by ADSP */
3983 }; 3640 };
3984 3641
3985 lpass_cpu: lpass@62d87000 { 3642 lpass_cpu: lpass@62d87000 {
3986 compatible = "qcom,sc 3643 compatible = "qcom,sc7180-lpass-cpu";
3987 3644
3988 reg = <0 0x62d87000 0 3645 reg = <0 0x62d87000 0 0x68000>, <0 0x62f00000 0 0x29000>;
3989 reg-names = "lpass-hd 3646 reg-names = "lpass-hdmiif", "lpass-lpaif";
3990 3647
3991 iommus = <&apps_smmu 3648 iommus = <&apps_smmu 0x1020 0>,
3992 <&apps_smmu 0 3649 <&apps_smmu 0x1021 0>,
3993 <&apps_smmu 0 3650 <&apps_smmu 0x1032 0>;
3994 3651
3995 power-domains = <&lpa 3652 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>;
3996 required-opps = <&rpm 3653 required-opps = <&rpmhpd_opp_nom>;
3997 3654
3998 status = "disabled"; 3655 status = "disabled";
3999 3656
4000 clocks = <&gcc GCC_LP 3657 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>,
4001 <&lpasscc LP 3658 <&lpasscc LPASS_AUDIO_CORE_CORE_CLK>,
4002 <&lpasscc LP 3659 <&lpasscc LPASS_AUDIO_CORE_EXT_MCLK0_CLK>,
4003 <&lpasscc LP 3660 <&lpasscc LPASS_AUDIO_CORE_SYSNOC_MPORT_CORE_CLK>,
4004 <&lpasscc LP 3661 <&lpasscc LPASS_AUDIO_CORE_LPAIF_PRI_IBIT_CLK>,
4005 <&lpasscc LP 3662 <&lpasscc LPASS_AUDIO_CORE_LPAIF_SEC_IBIT_CLK>;
4006 3663
4007 clock-names = "pcnoc- 3664 clock-names = "pcnoc-sway-clk", "audio-core",
4008 "mclk 3665 "mclk0", "pcnoc-mport-clk",
4009 "mi2s 3666 "mi2s-bit-clk0", "mi2s-bit-clk1";
4010 3667
4011 3668
4012 #sound-dai-cells = <1 3669 #sound-dai-cells = <1>;
4013 #address-cells = <1>; 3670 #address-cells = <1>;
4014 #size-cells = <0>; 3671 #size-cells = <0>;
4015 3672
4016 interrupts = <GIC_SPI 3673 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
4017 <GIC_ 3674 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
4018 interrupt-names = "lp 3675 interrupt-names = "lpass-irq-lpaif", "lpass-irq-hdmi";
4019 }; 3676 };
4020 3677
4021 lpass_hm: clock-controller@63 3678 lpass_hm: clock-controller@63000000 {
4022 compatible = "qcom,sc 3679 compatible = "qcom,sc7180-lpasshm";
4023 reg = <0 0x63000000 0 3680 reg = <0 0x63000000 0 0x28>;
4024 clocks = <&gcc GCC_LP 3681 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>,
4025 <&rpmhcc RPM 3682 <&rpmhcc RPMH_CXO_CLK>;
4026 clock-names = "iface" 3683 clock-names = "iface", "bi_tcxo";
4027 power-domains = <&rpm 3684 power-domains = <&rpmhpd SC7180_CX>;
4028 3685
4029 #clock-cells = <1>; 3686 #clock-cells = <1>;
4030 #power-domain-cells = 3687 #power-domain-cells = <1>;
4031 3688
4032 status = "reserved"; 3689 status = "reserved"; /* Controlled by ADSP */
4033 }; 3690 };
4034 }; 3691 };
4035 3692
4036 thermal-zones { 3693 thermal-zones {
4037 cpu0_thermal: cpu0-thermal { 3694 cpu0_thermal: cpu0-thermal {
4038 polling-delay-passive 3695 polling-delay-passive = <250>;
>> 3696 polling-delay = <0>;
4039 3697
4040 thermal-sensors = <&t 3698 thermal-sensors = <&tsens0 1>;
4041 sustainable-power = < 3699 sustainable-power = <1052>;
4042 3700
4043 trips { 3701 trips {
4044 cpu0_alert0: 3702 cpu0_alert0: trip-point0 {
4045 tempe 3703 temperature = <90000>;
4046 hyste 3704 hysteresis = <2000>;
4047 type 3705 type = "passive";
4048 }; 3706 };
4049 3707
4050 cpu0_alert1: 3708 cpu0_alert1: trip-point1 {
4051 tempe 3709 temperature = <95000>;
4052 hyste 3710 hysteresis = <2000>;
4053 type 3711 type = "passive";
4054 }; 3712 };
4055 3713
4056 cpu0_crit: cp 3714 cpu0_crit: cpu-crit {
4057 tempe 3715 temperature = <110000>;
4058 hyste 3716 hysteresis = <1000>;
4059 type 3717 type = "critical";
4060 }; 3718 };
4061 }; 3719 };
4062 3720
4063 cooling-maps { 3721 cooling-maps {
4064 map0 { 3722 map0 {
4065 trip 3723 trip = <&cpu0_alert0>;
4066 cooli 3724 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4067 3725 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4068 3726 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4069 3727 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4070 3728 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4071 3729 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4072 }; 3730 };
4073 map1 { 3731 map1 {
4074 trip 3732 trip = <&cpu0_alert1>;
4075 cooli 3733 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4076 3734 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4077 3735 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4078 3736 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4079 3737 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4080 3738 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4081 }; 3739 };
4082 }; 3740 };
4083 }; 3741 };
4084 3742
4085 cpu1_thermal: cpu1-thermal { 3743 cpu1_thermal: cpu1-thermal {
4086 polling-delay-passive 3744 polling-delay-passive = <250>;
>> 3745 polling-delay = <0>;
4087 3746
4088 thermal-sensors = <&t 3747 thermal-sensors = <&tsens0 2>;
4089 sustainable-power = < 3748 sustainable-power = <1052>;
4090 3749
4091 trips { 3750 trips {
4092 cpu1_alert0: 3751 cpu1_alert0: trip-point0 {
4093 tempe 3752 temperature = <90000>;
4094 hyste 3753 hysteresis = <2000>;
4095 type 3754 type = "passive";
4096 }; 3755 };
4097 3756
4098 cpu1_alert1: 3757 cpu1_alert1: trip-point1 {
4099 tempe 3758 temperature = <95000>;
4100 hyste 3759 hysteresis = <2000>;
4101 type 3760 type = "passive";
4102 }; 3761 };
4103 3762
4104 cpu1_crit: cp 3763 cpu1_crit: cpu-crit {
4105 tempe 3764 temperature = <110000>;
4106 hyste 3765 hysteresis = <1000>;
4107 type 3766 type = "critical";
4108 }; 3767 };
4109 }; 3768 };
4110 3769
4111 cooling-maps { 3770 cooling-maps {
4112 map0 { 3771 map0 {
4113 trip 3772 trip = <&cpu1_alert0>;
4114 cooli 3773 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4115 3774 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4116 3775 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4117 3776 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4118 3777 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4119 3778 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4120 }; 3779 };
4121 map1 { 3780 map1 {
4122 trip 3781 trip = <&cpu1_alert1>;
4123 cooli 3782 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4124 3783 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4125 3784 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4126 3785 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4127 3786 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4128 3787 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4129 }; 3788 };
4130 }; 3789 };
4131 }; 3790 };
4132 3791
4133 cpu2_thermal: cpu2-thermal { 3792 cpu2_thermal: cpu2-thermal {
4134 polling-delay-passive 3793 polling-delay-passive = <250>;
>> 3794 polling-delay = <0>;
4135 3795
4136 thermal-sensors = <&t 3796 thermal-sensors = <&tsens0 3>;
4137 sustainable-power = < 3797 sustainable-power = <1052>;
4138 3798
4139 trips { 3799 trips {
4140 cpu2_alert0: 3800 cpu2_alert0: trip-point0 {
4141 tempe 3801 temperature = <90000>;
4142 hyste 3802 hysteresis = <2000>;
4143 type 3803 type = "passive";
4144 }; 3804 };
4145 3805
4146 cpu2_alert1: 3806 cpu2_alert1: trip-point1 {
4147 tempe 3807 temperature = <95000>;
4148 hyste 3808 hysteresis = <2000>;
4149 type 3809 type = "passive";
4150 }; 3810 };
4151 3811
4152 cpu2_crit: cp 3812 cpu2_crit: cpu-crit {
4153 tempe 3813 temperature = <110000>;
4154 hyste 3814 hysteresis = <1000>;
4155 type 3815 type = "critical";
4156 }; 3816 };
4157 }; 3817 };
4158 3818
4159 cooling-maps { 3819 cooling-maps {
4160 map0 { 3820 map0 {
4161 trip 3821 trip = <&cpu2_alert0>;
4162 cooli 3822 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4163 3823 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4164 3824 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4165 3825 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4166 3826 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4167 3827 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4168 }; 3828 };
4169 map1 { 3829 map1 {
4170 trip 3830 trip = <&cpu2_alert1>;
4171 cooli 3831 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4172 3832 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4173 3833 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4174 3834 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4175 3835 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4176 3836 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4177 }; 3837 };
4178 }; 3838 };
4179 }; 3839 };
4180 3840
4181 cpu3_thermal: cpu3-thermal { 3841 cpu3_thermal: cpu3-thermal {
4182 polling-delay-passive 3842 polling-delay-passive = <250>;
>> 3843 polling-delay = <0>;
4183 3844
4184 thermal-sensors = <&t 3845 thermal-sensors = <&tsens0 4>;
4185 sustainable-power = < 3846 sustainable-power = <1052>;
4186 3847
4187 trips { 3848 trips {
4188 cpu3_alert0: 3849 cpu3_alert0: trip-point0 {
4189 tempe 3850 temperature = <90000>;
4190 hyste 3851 hysteresis = <2000>;
4191 type 3852 type = "passive";
4192 }; 3853 };
4193 3854
4194 cpu3_alert1: 3855 cpu3_alert1: trip-point1 {
4195 tempe 3856 temperature = <95000>;
4196 hyste 3857 hysteresis = <2000>;
4197 type 3858 type = "passive";
4198 }; 3859 };
4199 3860
4200 cpu3_crit: cp 3861 cpu3_crit: cpu-crit {
4201 tempe 3862 temperature = <110000>;
4202 hyste 3863 hysteresis = <1000>;
4203 type 3864 type = "critical";
4204 }; 3865 };
4205 }; 3866 };
4206 3867
4207 cooling-maps { 3868 cooling-maps {
4208 map0 { 3869 map0 {
4209 trip 3870 trip = <&cpu3_alert0>;
4210 cooli 3871 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4211 3872 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4212 3873 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4213 3874 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4214 3875 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4215 3876 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4216 }; 3877 };
4217 map1 { 3878 map1 {
4218 trip 3879 trip = <&cpu3_alert1>;
4219 cooli 3880 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4220 3881 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4221 3882 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4222 3883 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4223 3884 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4224 3885 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4225 }; 3886 };
4226 }; 3887 };
4227 }; 3888 };
4228 3889
4229 cpu4_thermal: cpu4-thermal { 3890 cpu4_thermal: cpu4-thermal {
4230 polling-delay-passive 3891 polling-delay-passive = <250>;
>> 3892 polling-delay = <0>;
4231 3893
4232 thermal-sensors = <&t 3894 thermal-sensors = <&tsens0 5>;
4233 sustainable-power = < 3895 sustainable-power = <1052>;
4234 3896
4235 trips { 3897 trips {
4236 cpu4_alert0: 3898 cpu4_alert0: trip-point0 {
4237 tempe 3899 temperature = <90000>;
4238 hyste 3900 hysteresis = <2000>;
4239 type 3901 type = "passive";
4240 }; 3902 };
4241 3903
4242 cpu4_alert1: 3904 cpu4_alert1: trip-point1 {
4243 tempe 3905 temperature = <95000>;
4244 hyste 3906 hysteresis = <2000>;
4245 type 3907 type = "passive";
4246 }; 3908 };
4247 3909
4248 cpu4_crit: cp 3910 cpu4_crit: cpu-crit {
4249 tempe 3911 temperature = <110000>;
4250 hyste 3912 hysteresis = <1000>;
4251 type 3913 type = "critical";
4252 }; 3914 };
4253 }; 3915 };
4254 3916
4255 cooling-maps { 3917 cooling-maps {
4256 map0 { 3918 map0 {
4257 trip 3919 trip = <&cpu4_alert0>;
4258 cooli 3920 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4259 3921 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4260 3922 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4261 3923 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4262 3924 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4263 3925 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4264 }; 3926 };
4265 map1 { 3927 map1 {
4266 trip 3928 trip = <&cpu4_alert1>;
4267 cooli 3929 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4268 3930 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4269 3931 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4270 3932 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4271 3933 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4272 3934 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4273 }; 3935 };
4274 }; 3936 };
4275 }; 3937 };
4276 3938
4277 cpu5_thermal: cpu5-thermal { 3939 cpu5_thermal: cpu5-thermal {
4278 polling-delay-passive 3940 polling-delay-passive = <250>;
>> 3941 polling-delay = <0>;
4279 3942
4280 thermal-sensors = <&t 3943 thermal-sensors = <&tsens0 6>;
4281 sustainable-power = < 3944 sustainable-power = <1052>;
4282 3945
4283 trips { 3946 trips {
4284 cpu5_alert0: 3947 cpu5_alert0: trip-point0 {
4285 tempe 3948 temperature = <90000>;
4286 hyste 3949 hysteresis = <2000>;
4287 type 3950 type = "passive";
4288 }; 3951 };
4289 3952
4290 cpu5_alert1: 3953 cpu5_alert1: trip-point1 {
4291 tempe 3954 temperature = <95000>;
4292 hyste 3955 hysteresis = <2000>;
4293 type 3956 type = "passive";
4294 }; 3957 };
4295 3958
4296 cpu5_crit: cp 3959 cpu5_crit: cpu-crit {
4297 tempe 3960 temperature = <110000>;
4298 hyste 3961 hysteresis = <1000>;
4299 type 3962 type = "critical";
4300 }; 3963 };
4301 }; 3964 };
4302 3965
4303 cooling-maps { 3966 cooling-maps {
4304 map0 { 3967 map0 {
4305 trip 3968 trip = <&cpu5_alert0>;
4306 cooli 3969 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4307 3970 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4308 3971 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4309 3972 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4310 3973 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4311 3974 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4312 }; 3975 };
4313 map1 { 3976 map1 {
4314 trip 3977 trip = <&cpu5_alert1>;
4315 cooli 3978 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4316 3979 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4317 3980 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4318 3981 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4319 3982 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4320 3983 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4321 }; 3984 };
4322 }; 3985 };
4323 }; 3986 };
4324 3987
4325 cpu6_thermal: cpu6-thermal { 3988 cpu6_thermal: cpu6-thermal {
4326 polling-delay-passive 3989 polling-delay-passive = <250>;
>> 3990 polling-delay = <0>;
4327 3991
4328 thermal-sensors = <&t 3992 thermal-sensors = <&tsens0 9>;
4329 sustainable-power = < 3993 sustainable-power = <1425>;
4330 3994
4331 trips { 3995 trips {
4332 cpu6_alert0: 3996 cpu6_alert0: trip-point0 {
4333 tempe 3997 temperature = <90000>;
4334 hyste 3998 hysteresis = <2000>;
4335 type 3999 type = "passive";
4336 }; 4000 };
4337 4001
4338 cpu6_alert1: 4002 cpu6_alert1: trip-point1 {
4339 tempe 4003 temperature = <95000>;
4340 hyste 4004 hysteresis = <2000>;
4341 type 4005 type = "passive";
4342 }; 4006 };
4343 4007
4344 cpu6_crit: cp 4008 cpu6_crit: cpu-crit {
4345 tempe 4009 temperature = <110000>;
4346 hyste 4010 hysteresis = <1000>;
4347 type 4011 type = "critical";
4348 }; 4012 };
4349 }; 4013 };
4350 4014
4351 cooling-maps { 4015 cooling-maps {
4352 map0 { 4016 map0 {
4353 trip 4017 trip = <&cpu6_alert0>;
4354 cooli 4018 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4355 4019 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4356 }; 4020 };
4357 map1 { 4021 map1 {
4358 trip 4022 trip = <&cpu6_alert1>;
4359 cooli 4023 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4360 4024 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4361 }; 4025 };
4362 }; 4026 };
4363 }; 4027 };
4364 4028
4365 cpu7_thermal: cpu7-thermal { 4029 cpu7_thermal: cpu7-thermal {
4366 polling-delay-passive 4030 polling-delay-passive = <250>;
>> 4031 polling-delay = <0>;
4367 4032
4368 thermal-sensors = <&t 4033 thermal-sensors = <&tsens0 10>;
4369 sustainable-power = < 4034 sustainable-power = <1425>;
4370 4035
4371 trips { 4036 trips {
4372 cpu7_alert0: 4037 cpu7_alert0: trip-point0 {
4373 tempe 4038 temperature = <90000>;
4374 hyste 4039 hysteresis = <2000>;
4375 type 4040 type = "passive";
4376 }; 4041 };
4377 4042
4378 cpu7_alert1: 4043 cpu7_alert1: trip-point1 {
4379 tempe 4044 temperature = <95000>;
4380 hyste 4045 hysteresis = <2000>;
4381 type 4046 type = "passive";
4382 }; 4047 };
4383 4048
4384 cpu7_crit: cp 4049 cpu7_crit: cpu-crit {
4385 tempe 4050 temperature = <110000>;
4386 hyste 4051 hysteresis = <1000>;
4387 type 4052 type = "critical";
4388 }; 4053 };
4389 }; 4054 };
4390 4055
4391 cooling-maps { 4056 cooling-maps {
4392 map0 { 4057 map0 {
4393 trip 4058 trip = <&cpu7_alert0>;
4394 cooli 4059 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4395 4060 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4396 }; 4061 };
4397 map1 { 4062 map1 {
4398 trip 4063 trip = <&cpu7_alert1>;
4399 cooli 4064 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4400 4065 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4401 }; 4066 };
4402 }; 4067 };
4403 }; 4068 };
4404 4069
4405 cpu8_thermal: cpu8-thermal { 4070 cpu8_thermal: cpu8-thermal {
4406 polling-delay-passive 4071 polling-delay-passive = <250>;
>> 4072 polling-delay = <0>;
4407 4073
4408 thermal-sensors = <&t 4074 thermal-sensors = <&tsens0 11>;
4409 sustainable-power = < 4075 sustainable-power = <1425>;
4410 4076
4411 trips { 4077 trips {
4412 cpu8_alert0: 4078 cpu8_alert0: trip-point0 {
4413 tempe 4079 temperature = <90000>;
4414 hyste 4080 hysteresis = <2000>;
4415 type 4081 type = "passive";
4416 }; 4082 };
4417 4083
4418 cpu8_alert1: 4084 cpu8_alert1: trip-point1 {
4419 tempe 4085 temperature = <95000>;
4420 hyste 4086 hysteresis = <2000>;
4421 type 4087 type = "passive";
4422 }; 4088 };
4423 4089
4424 cpu8_crit: cp 4090 cpu8_crit: cpu-crit {
4425 tempe 4091 temperature = <110000>;
4426 hyste 4092 hysteresis = <1000>;
4427 type 4093 type = "critical";
4428 }; 4094 };
4429 }; 4095 };
4430 4096
4431 cooling-maps { 4097 cooling-maps {
4432 map0 { 4098 map0 {
4433 trip 4099 trip = <&cpu8_alert0>;
4434 cooli 4100 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4435 4101 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4436 }; 4102 };
4437 map1 { 4103 map1 {
4438 trip 4104 trip = <&cpu8_alert1>;
4439 cooli 4105 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4440 4106 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4441 }; 4107 };
4442 }; 4108 };
4443 }; 4109 };
4444 4110
4445 cpu9_thermal: cpu9-thermal { 4111 cpu9_thermal: cpu9-thermal {
4446 polling-delay-passive 4112 polling-delay-passive = <250>;
>> 4113 polling-delay = <0>;
4447 4114
4448 thermal-sensors = <&t 4115 thermal-sensors = <&tsens0 12>;
4449 sustainable-power = < 4116 sustainable-power = <1425>;
4450 4117
4451 trips { 4118 trips {
4452 cpu9_alert0: 4119 cpu9_alert0: trip-point0 {
4453 tempe 4120 temperature = <90000>;
4454 hyste 4121 hysteresis = <2000>;
4455 type 4122 type = "passive";
4456 }; 4123 };
4457 4124
4458 cpu9_alert1: 4125 cpu9_alert1: trip-point1 {
4459 tempe 4126 temperature = <95000>;
4460 hyste 4127 hysteresis = <2000>;
4461 type 4128 type = "passive";
4462 }; 4129 };
4463 4130
4464 cpu9_crit: cp 4131 cpu9_crit: cpu-crit {
4465 tempe 4132 temperature = <110000>;
4466 hyste 4133 hysteresis = <1000>;
4467 type 4134 type = "critical";
4468 }; 4135 };
4469 }; 4136 };
4470 4137
4471 cooling-maps { 4138 cooling-maps {
4472 map0 { 4139 map0 {
4473 trip 4140 trip = <&cpu9_alert0>;
4474 cooli 4141 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4475 4142 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4476 }; 4143 };
4477 map1 { 4144 map1 {
4478 trip 4145 trip = <&cpu9_alert1>;
4479 cooli 4146 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4480 4147 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4481 }; 4148 };
4482 }; 4149 };
4483 }; 4150 };
4484 4151
4485 aoss0-thermal { 4152 aoss0-thermal {
4486 polling-delay-passive 4153 polling-delay-passive = <250>;
>> 4154 polling-delay = <0>;
4487 4155
4488 thermal-sensors = <&t 4156 thermal-sensors = <&tsens0 0>;
4489 4157
4490 trips { 4158 trips {
4491 aoss0_alert0: 4159 aoss0_alert0: trip-point0 {
4492 tempe 4160 temperature = <90000>;
4493 hyste 4161 hysteresis = <2000>;
4494 type 4162 type = "hot";
4495 }; 4163 };
4496 4164
4497 aoss0_crit: a 4165 aoss0_crit: aoss0-crit {
4498 tempe 4166 temperature = <110000>;
4499 hyste 4167 hysteresis = <2000>;
4500 type 4168 type = "critical";
4501 }; 4169 };
4502 }; 4170 };
4503 }; 4171 };
4504 4172
4505 cpuss0-thermal { 4173 cpuss0-thermal {
4506 polling-delay-passive 4174 polling-delay-passive = <250>;
>> 4175 polling-delay = <0>;
4507 4176
4508 thermal-sensors = <&t 4177 thermal-sensors = <&tsens0 7>;
4509 4178
4510 trips { 4179 trips {
4511 cpuss0_alert0 4180 cpuss0_alert0: trip-point0 {
4512 tempe 4181 temperature = <90000>;
4513 hyste 4182 hysteresis = <2000>;
4514 type 4183 type = "hot";
4515 }; 4184 };
4516 cpuss0_crit: 4185 cpuss0_crit: cluster0-crit {
4517 tempe 4186 temperature = <110000>;
4518 hyste 4187 hysteresis = <2000>;
4519 type 4188 type = "critical";
4520 }; 4189 };
4521 }; 4190 };
4522 }; 4191 };
4523 4192
4524 cpuss1-thermal { 4193 cpuss1-thermal {
4525 polling-delay-passive 4194 polling-delay-passive = <250>;
>> 4195 polling-delay = <0>;
4526 4196
4527 thermal-sensors = <&t 4197 thermal-sensors = <&tsens0 8>;
4528 4198
4529 trips { 4199 trips {
4530 cpuss1_alert0 4200 cpuss1_alert0: trip-point0 {
4531 tempe 4201 temperature = <90000>;
4532 hyste 4202 hysteresis = <2000>;
4533 type 4203 type = "hot";
4534 }; 4204 };
4535 cpuss1_crit: 4205 cpuss1_crit: cluster0-crit {
4536 tempe 4206 temperature = <110000>;
4537 hyste 4207 hysteresis = <2000>;
4538 type 4208 type = "critical";
4539 }; 4209 };
4540 }; 4210 };
4541 }; 4211 };
4542 4212
4543 gpuss0-thermal { 4213 gpuss0-thermal {
4544 polling-delay-passive 4214 polling-delay-passive = <250>;
>> 4215 polling-delay = <0>;
4545 4216
4546 thermal-sensors = <&t 4217 thermal-sensors = <&tsens0 13>;
4547 4218
4548 trips { 4219 trips {
4549 gpuss0_alert0 4220 gpuss0_alert0: trip-point0 {
4550 tempe 4221 temperature = <95000>;
4551 hyste 4222 hysteresis = <2000>;
4552 type 4223 type = "passive";
4553 }; 4224 };
4554 4225
4555 gpuss0_crit: 4226 gpuss0_crit: gpuss0-crit {
4556 tempe 4227 temperature = <110000>;
4557 hyste 4228 hysteresis = <2000>;
4558 type 4229 type = "critical";
4559 }; 4230 };
4560 }; 4231 };
4561 4232
4562 cooling-maps { 4233 cooling-maps {
4563 map0 { 4234 map0 {
4564 trip 4235 trip = <&gpuss0_alert0>;
4565 cooli 4236 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4566 }; 4237 };
4567 }; 4238 };
4568 }; 4239 };
4569 4240
4570 gpuss1-thermal { 4241 gpuss1-thermal {
4571 polling-delay-passive 4242 polling-delay-passive = <250>;
>> 4243 polling-delay = <0>;
4572 4244
4573 thermal-sensors = <&t 4245 thermal-sensors = <&tsens0 14>;
4574 4246
4575 trips { 4247 trips {
4576 gpuss1_alert0 4248 gpuss1_alert0: trip-point0 {
4577 tempe 4249 temperature = <95000>;
4578 hyste 4250 hysteresis = <2000>;
4579 type 4251 type = "passive";
4580 }; 4252 };
4581 4253
4582 gpuss1_crit: 4254 gpuss1_crit: gpuss1-crit {
4583 tempe 4255 temperature = <110000>;
4584 hyste 4256 hysteresis = <2000>;
4585 type 4257 type = "critical";
4586 }; 4258 };
4587 }; 4259 };
4588 4260
4589 cooling-maps { 4261 cooling-maps {
4590 map0 { 4262 map0 {
4591 trip 4263 trip = <&gpuss1_alert0>;
4592 cooli 4264 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4593 }; 4265 };
4594 }; 4266 };
4595 }; 4267 };
4596 4268
4597 aoss1-thermal { 4269 aoss1-thermal {
4598 polling-delay-passive 4270 polling-delay-passive = <250>;
>> 4271 polling-delay = <0>;
4599 4272
4600 thermal-sensors = <&t 4273 thermal-sensors = <&tsens1 0>;
4601 4274
4602 trips { 4275 trips {
4603 aoss1_alert0: 4276 aoss1_alert0: trip-point0 {
4604 tempe 4277 temperature = <90000>;
4605 hyste 4278 hysteresis = <2000>;
4606 type 4279 type = "hot";
4607 }; 4280 };
4608 4281
4609 aoss1_crit: a 4282 aoss1_crit: aoss1-crit {
4610 tempe 4283 temperature = <110000>;
4611 hyste 4284 hysteresis = <2000>;
4612 type 4285 type = "critical";
4613 }; 4286 };
4614 }; 4287 };
4615 }; 4288 };
4616 4289
4617 cwlan-thermal { 4290 cwlan-thermal {
4618 polling-delay-passive 4291 polling-delay-passive = <250>;
>> 4292 polling-delay = <0>;
4619 4293
4620 thermal-sensors = <&t 4294 thermal-sensors = <&tsens1 1>;
4621 4295
4622 trips { 4296 trips {
4623 cwlan_alert0: 4297 cwlan_alert0: trip-point0 {
4624 tempe 4298 temperature = <90000>;
4625 hyste 4299 hysteresis = <2000>;
4626 type 4300 type = "hot";
4627 }; 4301 };
4628 4302
4629 cwlan_crit: c 4303 cwlan_crit: cwlan-crit {
4630 tempe 4304 temperature = <110000>;
4631 hyste 4305 hysteresis = <2000>;
4632 type 4306 type = "critical";
4633 }; 4307 };
4634 }; 4308 };
4635 }; 4309 };
4636 4310
4637 audio-thermal { 4311 audio-thermal {
4638 polling-delay-passive 4312 polling-delay-passive = <250>;
>> 4313 polling-delay = <0>;
4639 4314
4640 thermal-sensors = <&t 4315 thermal-sensors = <&tsens1 2>;
4641 4316
4642 trips { 4317 trips {
4643 audio_alert0: 4318 audio_alert0: trip-point0 {
4644 tempe 4319 temperature = <90000>;
4645 hyste 4320 hysteresis = <2000>;
4646 type 4321 type = "hot";
4647 }; 4322 };
4648 4323
4649 audio_crit: a 4324 audio_crit: audio-crit {
4650 tempe 4325 temperature = <110000>;
4651 hyste 4326 hysteresis = <2000>;
4652 type 4327 type = "critical";
4653 }; 4328 };
4654 }; 4329 };
4655 }; 4330 };
4656 4331
4657 ddr-thermal { 4332 ddr-thermal {
4658 polling-delay-passive 4333 polling-delay-passive = <250>;
>> 4334 polling-delay = <0>;
4659 4335
4660 thermal-sensors = <&t 4336 thermal-sensors = <&tsens1 3>;
4661 4337
4662 trips { 4338 trips {
4663 ddr_alert0: t 4339 ddr_alert0: trip-point0 {
4664 tempe 4340 temperature = <90000>;
4665 hyste 4341 hysteresis = <2000>;
4666 type 4342 type = "hot";
4667 }; 4343 };
4668 4344
4669 ddr_crit: ddr 4345 ddr_crit: ddr-crit {
4670 tempe 4346 temperature = <110000>;
4671 hyste 4347 hysteresis = <2000>;
4672 type 4348 type = "critical";
4673 }; 4349 };
4674 }; 4350 };
4675 }; 4351 };
4676 4352
4677 q6-hvx-thermal { 4353 q6-hvx-thermal {
4678 polling-delay-passive 4354 polling-delay-passive = <250>;
>> 4355 polling-delay = <0>;
4679 4356
4680 thermal-sensors = <&t 4357 thermal-sensors = <&tsens1 4>;
4681 4358
4682 trips { 4359 trips {
4683 q6_hvx_alert0 4360 q6_hvx_alert0: trip-point0 {
4684 tempe 4361 temperature = <90000>;
4685 hyste 4362 hysteresis = <2000>;
4686 type 4363 type = "hot";
4687 }; 4364 };
4688 4365
4689 q6_hvx_crit: 4366 q6_hvx_crit: q6-hvx-crit {
4690 tempe 4367 temperature = <110000>;
4691 hyste 4368 hysteresis = <2000>;
4692 type 4369 type = "critical";
4693 }; 4370 };
4694 }; 4371 };
4695 }; 4372 };
4696 4373
4697 camera-thermal { 4374 camera-thermal {
4698 polling-delay-passive 4375 polling-delay-passive = <250>;
>> 4376 polling-delay = <0>;
4699 4377
4700 thermal-sensors = <&t 4378 thermal-sensors = <&tsens1 5>;
4701 4379
4702 trips { 4380 trips {
4703 camera_alert0 4381 camera_alert0: trip-point0 {
4704 tempe 4382 temperature = <90000>;
4705 hyste 4383 hysteresis = <2000>;
4706 type 4384 type = "hot";
4707 }; 4385 };
4708 4386
4709 camera_crit: 4387 camera_crit: camera-crit {
4710 tempe 4388 temperature = <110000>;
4711 hyste 4389 hysteresis = <2000>;
4712 type 4390 type = "critical";
4713 }; 4391 };
4714 }; 4392 };
4715 }; 4393 };
4716 4394
4717 mdm-core-thermal { 4395 mdm-core-thermal {
4718 polling-delay-passive 4396 polling-delay-passive = <250>;
>> 4397 polling-delay = <0>;
4719 4398
4720 thermal-sensors = <&t 4399 thermal-sensors = <&tsens1 6>;
4721 4400
4722 trips { 4401 trips {
4723 mdm_alert0: t 4402 mdm_alert0: trip-point0 {
4724 tempe 4403 temperature = <90000>;
4725 hyste 4404 hysteresis = <2000>;
4726 type 4405 type = "hot";
4727 }; 4406 };
4728 4407
4729 mdm_crit: mdm 4408 mdm_crit: mdm-crit {
4730 tempe 4409 temperature = <110000>;
4731 hyste 4410 hysteresis = <2000>;
4732 type 4411 type = "critical";
4733 }; 4412 };
4734 }; 4413 };
4735 }; 4414 };
4736 4415
4737 mdm-dsp-thermal { 4416 mdm-dsp-thermal {
4738 polling-delay-passive 4417 polling-delay-passive = <250>;
>> 4418 polling-delay = <0>;
4739 4419
4740 thermal-sensors = <&t 4420 thermal-sensors = <&tsens1 7>;
4741 4421
4742 trips { 4422 trips {
4743 mdm_dsp_alert 4423 mdm_dsp_alert0: trip-point0 {
4744 tempe 4424 temperature = <90000>;
4745 hyste 4425 hysteresis = <2000>;
4746 type 4426 type = "hot";
4747 }; 4427 };
4748 4428
4749 mdm_dsp_crit: 4429 mdm_dsp_crit: mdm-dsp-crit {
4750 tempe 4430 temperature = <110000>;
4751 hyste 4431 hysteresis = <2000>;
4752 type 4432 type = "critical";
4753 }; 4433 };
4754 }; 4434 };
4755 }; 4435 };
4756 4436
4757 npu-thermal { 4437 npu-thermal {
4758 polling-delay-passive 4438 polling-delay-passive = <250>;
>> 4439 polling-delay = <0>;
4759 4440
4760 thermal-sensors = <&t 4441 thermal-sensors = <&tsens1 8>;
4761 4442
4762 trips { 4443 trips {
4763 npu_alert0: t 4444 npu_alert0: trip-point0 {
4764 tempe 4445 temperature = <90000>;
4765 hyste 4446 hysteresis = <2000>;
4766 type 4447 type = "hot";
4767 }; 4448 };
4768 4449
4769 npu_crit: npu 4450 npu_crit: npu-crit {
4770 tempe 4451 temperature = <110000>;
4771 hyste 4452 hysteresis = <2000>;
4772 type 4453 type = "critical";
4773 }; 4454 };
4774 }; 4455 };
4775 }; 4456 };
4776 4457
4777 video-thermal { 4458 video-thermal {
4778 polling-delay-passive 4459 polling-delay-passive = <250>;
>> 4460 polling-delay = <0>;
4779 4461
4780 thermal-sensors = <&t 4462 thermal-sensors = <&tsens1 9>;
4781 4463
4782 trips { 4464 trips {
4783 video_alert0: 4465 video_alert0: trip-point0 {
4784 tempe 4466 temperature = <90000>;
4785 hyste 4467 hysteresis = <2000>;
4786 type 4468 type = "hot";
4787 }; 4469 };
4788 4470
4789 video_crit: v 4471 video_crit: video-crit {
4790 tempe 4472 temperature = <110000>;
4791 hyste 4473 hysteresis = <2000>;
4792 type 4474 type = "critical";
4793 }; 4475 };
4794 }; 4476 };
4795 }; 4477 };
4796 }; 4478 };
4797 4479
4798 timer { 4480 timer {
4799 compatible = "arm,armv8-timer 4481 compatible = "arm,armv8-timer";
4800 interrupts = <GIC_PPI 1 IRQ_T 4482 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
4801 <GIC_PPI 2 IRQ_T 4483 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
4802 <GIC_PPI 3 IRQ_T 4484 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
4803 <GIC_PPI 0 IRQ_T 4485 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
4804 }; 4486 };
4805 }; 4487 };
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