1 // SPDX-License-Identifier: BSD-3-Clause 1 // SPDX-License-Identifier: BSD-3-Clause
2 /* 2 /*
3 * SC7180 SoC device tree source 3 * SC7180 SoC device tree source
4 * 4 *
5 * Copyright (c) 2019-2020, The Linux Foundati 5 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
6 */ 6 */
7 7
8 #include <dt-bindings/clock/qcom,dispcc-sc7180 8 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
9 #include <dt-bindings/clock/qcom,gcc-sc7180.h> 9 #include <dt-bindings/clock/qcom,gcc-sc7180.h>
10 #include <dt-bindings/clock/qcom,gpucc-sc7180. 10 #include <dt-bindings/clock/qcom,gpucc-sc7180.h>
11 #include <dt-bindings/clock/qcom,lpasscorecc-s 11 #include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h>
12 #include <dt-bindings/clock/qcom,rpmh.h> 12 #include <dt-bindings/clock/qcom,rpmh.h>
13 #include <dt-bindings/clock/qcom,videocc-sc718 13 #include <dt-bindings/clock/qcom,videocc-sc7180.h>
14 #include <dt-bindings/firmware/qcom,scm.h> <<
15 #include <dt-bindings/interconnect/qcom,icc.h> 14 #include <dt-bindings/interconnect/qcom,icc.h>
16 #include <dt-bindings/interconnect/qcom,osm-l3 15 #include <dt-bindings/interconnect/qcom,osm-l3.h>
17 #include <dt-bindings/interconnect/qcom,sc7180 16 #include <dt-bindings/interconnect/qcom,sc7180.h>
18 #include <dt-bindings/interrupt-controller/arm 17 #include <dt-bindings/interrupt-controller/arm-gic.h>
19 #include <dt-bindings/phy/phy-qcom-qmp.h> 18 #include <dt-bindings/phy/phy-qcom-qmp.h>
20 #include <dt-bindings/phy/phy-qcom-qusb2.h> 19 #include <dt-bindings/phy/phy-qcom-qusb2.h>
21 #include <dt-bindings/power/qcom-rpmpd.h> 20 #include <dt-bindings/power/qcom-rpmpd.h>
22 #include <dt-bindings/reset/qcom,sdm845-aoss.h 21 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
23 #include <dt-bindings/reset/qcom,sdm845-pdc.h> 22 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
24 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 23 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
25 #include <dt-bindings/soc/qcom,apr.h> <<
26 #include <dt-bindings/sound/qcom,q6afe.h> <<
27 #include <dt-bindings/thermal/thermal.h> 24 #include <dt-bindings/thermal/thermal.h>
28 25
29 / { 26 / {
30 interrupt-parent = <&intc>; 27 interrupt-parent = <&intc>;
31 28
32 #address-cells = <2>; 29 #address-cells = <2>;
33 #size-cells = <2>; 30 #size-cells = <2>;
34 31
35 aliases { 32 aliases {
36 mmc1 = &sdhc_1; 33 mmc1 = &sdhc_1;
37 mmc2 = &sdhc_2; 34 mmc2 = &sdhc_2;
38 i2c0 = &i2c0; 35 i2c0 = &i2c0;
39 i2c1 = &i2c1; 36 i2c1 = &i2c1;
40 i2c2 = &i2c2; 37 i2c2 = &i2c2;
41 i2c3 = &i2c3; 38 i2c3 = &i2c3;
42 i2c4 = &i2c4; 39 i2c4 = &i2c4;
43 i2c5 = &i2c5; 40 i2c5 = &i2c5;
44 i2c6 = &i2c6; 41 i2c6 = &i2c6;
45 i2c7 = &i2c7; 42 i2c7 = &i2c7;
46 i2c8 = &i2c8; 43 i2c8 = &i2c8;
47 i2c9 = &i2c9; 44 i2c9 = &i2c9;
48 i2c10 = &i2c10; 45 i2c10 = &i2c10;
49 i2c11 = &i2c11; 46 i2c11 = &i2c11;
50 spi0 = &spi0; 47 spi0 = &spi0;
51 spi1 = &spi1; 48 spi1 = &spi1;
52 spi3 = &spi3; 49 spi3 = &spi3;
53 spi5 = &spi5; 50 spi5 = &spi5;
54 spi6 = &spi6; 51 spi6 = &spi6;
55 spi8 = &spi8; 52 spi8 = &spi8;
56 spi10 = &spi10; 53 spi10 = &spi10;
57 spi11 = &spi11; 54 spi11 = &spi11;
58 }; 55 };
59 56
60 chosen { }; 57 chosen { };
61 58
62 clocks { 59 clocks {
63 xo_board: xo-board { 60 xo_board: xo-board {
64 compatible = "fixed-cl 61 compatible = "fixed-clock";
65 clock-frequency = <384 62 clock-frequency = <38400000>;
66 #clock-cells = <0>; 63 #clock-cells = <0>;
67 }; 64 };
68 65
69 sleep_clk: sleep-clk { 66 sleep_clk: sleep-clk {
70 compatible = "fixed-cl 67 compatible = "fixed-clock";
71 clock-frequency = <327 68 clock-frequency = <32764>;
72 #clock-cells = <0>; 69 #clock-cells = <0>;
73 }; 70 };
74 }; 71 };
75 72
76 cpus { 73 cpus {
77 #address-cells = <2>; 74 #address-cells = <2>;
78 #size-cells = <0>; 75 #size-cells = <0>;
79 76
80 CPU0: cpu@0 { 77 CPU0: cpu@0 {
81 device_type = "cpu"; 78 device_type = "cpu";
82 compatible = "qcom,kry 79 compatible = "qcom,kryo468";
83 reg = <0x0 0x0>; 80 reg = <0x0 0x0>;
84 clocks = <&cpufreq_hw 81 clocks = <&cpufreq_hw 0>;
85 enable-method = "psci" 82 enable-method = "psci";
86 power-domains = <&CPU_ 83 power-domains = <&CPU_PD0>;
87 power-domain-names = " 84 power-domain-names = "psci";
88 capacity-dmips-mhz = < 85 capacity-dmips-mhz = <415>;
89 dynamic-power-coeffici 86 dynamic-power-coefficient = <137>;
90 operating-points-v2 = 87 operating-points-v2 = <&cpu0_opp_table>;
91 interconnects = <&gem_ 88 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
92 <&osm_ 89 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
93 next-level-cache = <&L 90 next-level-cache = <&L2_0>;
94 #cooling-cells = <2>; 91 #cooling-cells = <2>;
95 qcom,freq-domain = <&c 92 qcom,freq-domain = <&cpufreq_hw 0>;
96 L2_0: l2-cache { 93 L2_0: l2-cache {
97 compatible = " 94 compatible = "cache";
98 cache-level = 95 cache-level = <2>;
99 cache-unified; 96 cache-unified;
100 next-level-cac 97 next-level-cache = <&L3_0>;
101 L3_0: l3-cache 98 L3_0: l3-cache {
102 compat 99 compatible = "cache";
103 cache- 100 cache-level = <3>;
104 cache- 101 cache-unified;
105 }; 102 };
106 }; 103 };
107 }; 104 };
108 105
109 CPU1: cpu@100 { 106 CPU1: cpu@100 {
110 device_type = "cpu"; 107 device_type = "cpu";
111 compatible = "qcom,kry 108 compatible = "qcom,kryo468";
112 reg = <0x0 0x100>; 109 reg = <0x0 0x100>;
113 clocks = <&cpufreq_hw 110 clocks = <&cpufreq_hw 0>;
114 enable-method = "psci" 111 enable-method = "psci";
115 power-domains = <&CPU_ 112 power-domains = <&CPU_PD1>;
116 power-domain-names = " 113 power-domain-names = "psci";
117 capacity-dmips-mhz = < 114 capacity-dmips-mhz = <415>;
118 dynamic-power-coeffici 115 dynamic-power-coefficient = <137>;
119 next-level-cache = <&L 116 next-level-cache = <&L2_100>;
120 operating-points-v2 = 117 operating-points-v2 = <&cpu0_opp_table>;
121 interconnects = <&gem_ 118 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
122 <&osm_ 119 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
123 #cooling-cells = <2>; 120 #cooling-cells = <2>;
124 qcom,freq-domain = <&c 121 qcom,freq-domain = <&cpufreq_hw 0>;
125 L2_100: l2-cache { 122 L2_100: l2-cache {
126 compatible = " 123 compatible = "cache";
127 cache-level = 124 cache-level = <2>;
128 cache-unified; 125 cache-unified;
129 next-level-cac 126 next-level-cache = <&L3_0>;
130 }; 127 };
131 }; 128 };
132 129
133 CPU2: cpu@200 { 130 CPU2: cpu@200 {
134 device_type = "cpu"; 131 device_type = "cpu";
135 compatible = "qcom,kry 132 compatible = "qcom,kryo468";
136 reg = <0x0 0x200>; 133 reg = <0x0 0x200>;
137 clocks = <&cpufreq_hw 134 clocks = <&cpufreq_hw 0>;
138 enable-method = "psci" 135 enable-method = "psci";
139 power-domains = <&CPU_ 136 power-domains = <&CPU_PD2>;
140 power-domain-names = " 137 power-domain-names = "psci";
141 capacity-dmips-mhz = < 138 capacity-dmips-mhz = <415>;
142 dynamic-power-coeffici 139 dynamic-power-coefficient = <137>;
143 next-level-cache = <&L 140 next-level-cache = <&L2_200>;
144 operating-points-v2 = 141 operating-points-v2 = <&cpu0_opp_table>;
145 interconnects = <&gem_ 142 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
146 <&osm_ 143 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
147 #cooling-cells = <2>; 144 #cooling-cells = <2>;
148 qcom,freq-domain = <&c 145 qcom,freq-domain = <&cpufreq_hw 0>;
149 L2_200: l2-cache { 146 L2_200: l2-cache {
150 compatible = " 147 compatible = "cache";
151 cache-level = 148 cache-level = <2>;
152 cache-unified; 149 cache-unified;
153 next-level-cac 150 next-level-cache = <&L3_0>;
154 }; 151 };
155 }; 152 };
156 153
157 CPU3: cpu@300 { 154 CPU3: cpu@300 {
158 device_type = "cpu"; 155 device_type = "cpu";
159 compatible = "qcom,kry 156 compatible = "qcom,kryo468";
160 reg = <0x0 0x300>; 157 reg = <0x0 0x300>;
161 clocks = <&cpufreq_hw 158 clocks = <&cpufreq_hw 0>;
162 enable-method = "psci" 159 enable-method = "psci";
163 power-domains = <&CPU_ 160 power-domains = <&CPU_PD3>;
164 power-domain-names = " 161 power-domain-names = "psci";
165 capacity-dmips-mhz = < 162 capacity-dmips-mhz = <415>;
166 dynamic-power-coeffici 163 dynamic-power-coefficient = <137>;
167 next-level-cache = <&L 164 next-level-cache = <&L2_300>;
168 operating-points-v2 = 165 operating-points-v2 = <&cpu0_opp_table>;
169 interconnects = <&gem_ 166 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
170 <&osm_ 167 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
171 #cooling-cells = <2>; 168 #cooling-cells = <2>;
172 qcom,freq-domain = <&c 169 qcom,freq-domain = <&cpufreq_hw 0>;
173 L2_300: l2-cache { 170 L2_300: l2-cache {
174 compatible = " 171 compatible = "cache";
175 cache-level = 172 cache-level = <2>;
176 cache-unified; 173 cache-unified;
177 next-level-cac 174 next-level-cache = <&L3_0>;
178 }; 175 };
179 }; 176 };
180 177
181 CPU4: cpu@400 { 178 CPU4: cpu@400 {
182 device_type = "cpu"; 179 device_type = "cpu";
183 compatible = "qcom,kry 180 compatible = "qcom,kryo468";
184 reg = <0x0 0x400>; 181 reg = <0x0 0x400>;
185 clocks = <&cpufreq_hw 182 clocks = <&cpufreq_hw 0>;
186 enable-method = "psci" 183 enable-method = "psci";
187 power-domains = <&CPU_ 184 power-domains = <&CPU_PD4>;
188 power-domain-names = " 185 power-domain-names = "psci";
189 capacity-dmips-mhz = < 186 capacity-dmips-mhz = <415>;
190 dynamic-power-coeffici 187 dynamic-power-coefficient = <137>;
191 next-level-cache = <&L 188 next-level-cache = <&L2_400>;
192 operating-points-v2 = 189 operating-points-v2 = <&cpu0_opp_table>;
193 interconnects = <&gem_ 190 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
194 <&osm_ 191 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
195 #cooling-cells = <2>; 192 #cooling-cells = <2>;
196 qcom,freq-domain = <&c 193 qcom,freq-domain = <&cpufreq_hw 0>;
197 L2_400: l2-cache { 194 L2_400: l2-cache {
198 compatible = " 195 compatible = "cache";
199 cache-level = 196 cache-level = <2>;
200 cache-unified; 197 cache-unified;
201 next-level-cac 198 next-level-cache = <&L3_0>;
202 }; 199 };
203 }; 200 };
204 201
205 CPU5: cpu@500 { 202 CPU5: cpu@500 {
206 device_type = "cpu"; 203 device_type = "cpu";
207 compatible = "qcom,kry 204 compatible = "qcom,kryo468";
208 reg = <0x0 0x500>; 205 reg = <0x0 0x500>;
209 clocks = <&cpufreq_hw 206 clocks = <&cpufreq_hw 0>;
210 enable-method = "psci" 207 enable-method = "psci";
211 power-domains = <&CPU_ 208 power-domains = <&CPU_PD5>;
212 power-domain-names = " 209 power-domain-names = "psci";
213 capacity-dmips-mhz = < 210 capacity-dmips-mhz = <415>;
214 dynamic-power-coeffici 211 dynamic-power-coefficient = <137>;
215 next-level-cache = <&L 212 next-level-cache = <&L2_500>;
216 operating-points-v2 = 213 operating-points-v2 = <&cpu0_opp_table>;
217 interconnects = <&gem_ 214 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
218 <&osm_ 215 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
219 #cooling-cells = <2>; 216 #cooling-cells = <2>;
220 qcom,freq-domain = <&c 217 qcom,freq-domain = <&cpufreq_hw 0>;
221 L2_500: l2-cache { 218 L2_500: l2-cache {
222 compatible = " 219 compatible = "cache";
223 cache-level = 220 cache-level = <2>;
224 cache-unified; 221 cache-unified;
225 next-level-cac 222 next-level-cache = <&L3_0>;
226 }; 223 };
227 }; 224 };
228 225
229 CPU6: cpu@600 { 226 CPU6: cpu@600 {
230 device_type = "cpu"; 227 device_type = "cpu";
231 compatible = "qcom,kry 228 compatible = "qcom,kryo468";
232 reg = <0x0 0x600>; 229 reg = <0x0 0x600>;
233 clocks = <&cpufreq_hw 230 clocks = <&cpufreq_hw 1>;
234 enable-method = "psci" 231 enable-method = "psci";
235 power-domains = <&CPU_ 232 power-domains = <&CPU_PD6>;
236 power-domain-names = " 233 power-domain-names = "psci";
237 capacity-dmips-mhz = < 234 capacity-dmips-mhz = <1024>;
238 dynamic-power-coeffici 235 dynamic-power-coefficient = <480>;
239 next-level-cache = <&L 236 next-level-cache = <&L2_600>;
240 operating-points-v2 = 237 operating-points-v2 = <&cpu6_opp_table>;
241 interconnects = <&gem_ 238 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
242 <&osm_ 239 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
243 #cooling-cells = <2>; 240 #cooling-cells = <2>;
244 qcom,freq-domain = <&c 241 qcom,freq-domain = <&cpufreq_hw 1>;
245 L2_600: l2-cache { 242 L2_600: l2-cache {
246 compatible = " 243 compatible = "cache";
247 cache-level = 244 cache-level = <2>;
248 cache-unified; 245 cache-unified;
249 next-level-cac 246 next-level-cache = <&L3_0>;
250 }; 247 };
251 }; 248 };
252 249
253 CPU7: cpu@700 { 250 CPU7: cpu@700 {
254 device_type = "cpu"; 251 device_type = "cpu";
255 compatible = "qcom,kry 252 compatible = "qcom,kryo468";
256 reg = <0x0 0x700>; 253 reg = <0x0 0x700>;
257 clocks = <&cpufreq_hw 254 clocks = <&cpufreq_hw 1>;
258 enable-method = "psci" 255 enable-method = "psci";
259 power-domains = <&CPU_ 256 power-domains = <&CPU_PD7>;
260 power-domain-names = " 257 power-domain-names = "psci";
261 capacity-dmips-mhz = < 258 capacity-dmips-mhz = <1024>;
262 dynamic-power-coeffici 259 dynamic-power-coefficient = <480>;
263 next-level-cache = <&L 260 next-level-cache = <&L2_700>;
264 operating-points-v2 = 261 operating-points-v2 = <&cpu6_opp_table>;
265 interconnects = <&gem_ 262 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
266 <&osm_ 263 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
267 #cooling-cells = <2>; 264 #cooling-cells = <2>;
268 qcom,freq-domain = <&c 265 qcom,freq-domain = <&cpufreq_hw 1>;
269 L2_700: l2-cache { 266 L2_700: l2-cache {
270 compatible = " 267 compatible = "cache";
271 cache-level = 268 cache-level = <2>;
272 cache-unified; 269 cache-unified;
273 next-level-cac 270 next-level-cache = <&L3_0>;
274 }; 271 };
275 }; 272 };
276 273
277 cpu-map { 274 cpu-map {
278 cluster0 { 275 cluster0 {
279 core0 { 276 core0 {
280 cpu = 277 cpu = <&CPU0>;
281 }; 278 };
282 279
283 core1 { 280 core1 {
284 cpu = 281 cpu = <&CPU1>;
285 }; 282 };
286 283
287 core2 { 284 core2 {
288 cpu = 285 cpu = <&CPU2>;
289 }; 286 };
290 287
291 core3 { 288 core3 {
292 cpu = 289 cpu = <&CPU3>;
293 }; 290 };
294 291
295 core4 { 292 core4 {
296 cpu = 293 cpu = <&CPU4>;
297 }; 294 };
298 295
299 core5 { 296 core5 {
300 cpu = 297 cpu = <&CPU5>;
301 }; 298 };
302 299
303 core6 { 300 core6 {
304 cpu = 301 cpu = <&CPU6>;
305 }; 302 };
306 303
307 core7 { 304 core7 {
308 cpu = 305 cpu = <&CPU7>;
309 }; 306 };
310 }; 307 };
311 }; 308 };
312 309
313 idle_states: idle-states { 310 idle_states: idle-states {
314 entry-method = "psci"; 311 entry-method = "psci";
315 312
316 LITTLE_CPU_SLEEP_0: cp 313 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
317 compatible = " 314 compatible = "arm,idle-state";
318 idle-state-nam 315 idle-state-name = "little-power-down";
319 arm,psci-suspe 316 arm,psci-suspend-param = <0x40000003>;
320 entry-latency- 317 entry-latency-us = <549>;
321 exit-latency-u 318 exit-latency-us = <901>;
322 min-residency- 319 min-residency-us = <1774>;
323 local-timer-st 320 local-timer-stop;
324 }; 321 };
325 322
326 LITTLE_CPU_SLEEP_1: cp 323 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
327 compatible = " 324 compatible = "arm,idle-state";
328 idle-state-nam 325 idle-state-name = "little-rail-power-down";
329 arm,psci-suspe 326 arm,psci-suspend-param = <0x40000004>;
330 entry-latency- 327 entry-latency-us = <702>;
331 exit-latency-u 328 exit-latency-us = <915>;
332 min-residency- 329 min-residency-us = <4001>;
333 local-timer-st 330 local-timer-stop;
334 }; 331 };
335 332
336 BIG_CPU_SLEEP_0: cpu-s 333 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
337 compatible = " 334 compatible = "arm,idle-state";
338 idle-state-nam 335 idle-state-name = "big-power-down";
339 arm,psci-suspe 336 arm,psci-suspend-param = <0x40000003>;
340 entry-latency- 337 entry-latency-us = <523>;
341 exit-latency-u 338 exit-latency-us = <1244>;
342 min-residency- 339 min-residency-us = <2207>;
343 local-timer-st 340 local-timer-stop;
344 }; 341 };
345 342
346 BIG_CPU_SLEEP_1: cpu-s 343 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
347 compatible = " 344 compatible = "arm,idle-state";
348 idle-state-nam 345 idle-state-name = "big-rail-power-down";
349 arm,psci-suspe 346 arm,psci-suspend-param = <0x40000004>;
350 entry-latency- 347 entry-latency-us = <526>;
351 exit-latency-u 348 exit-latency-us = <1854>;
352 min-residency- 349 min-residency-us = <5555>;
353 local-timer-st 350 local-timer-stop;
354 }; 351 };
355 }; 352 };
356 353
357 domain_idle_states: domain-idl 354 domain_idle_states: domain-idle-states {
358 CLUSTER_SLEEP_PC: clus 355 CLUSTER_SLEEP_PC: cluster-sleep-0 {
359 compatible = " 356 compatible = "domain-idle-state";
360 idle-state-nam 357 idle-state-name = "cluster-l3-power-collapse";
361 arm,psci-suspe 358 arm,psci-suspend-param = <0x41000044>;
362 entry-latency- 359 entry-latency-us = <2752>;
363 exit-latency-u 360 exit-latency-us = <3048>;
364 min-residency- 361 min-residency-us = <6118>;
365 }; 362 };
366 363
367 CLUSTER_SLEEP_CX_RET: 364 CLUSTER_SLEEP_CX_RET: cluster-sleep-1 {
368 compatible = " 365 compatible = "domain-idle-state";
369 idle-state-nam 366 idle-state-name = "cluster-cx-retention";
370 arm,psci-suspe 367 arm,psci-suspend-param = <0x41001244>;
371 entry-latency- 368 entry-latency-us = <3638>;
372 exit-latency-u 369 exit-latency-us = <4562>;
373 min-residency- 370 min-residency-us = <8467>;
374 }; 371 };
375 372
376 CLUSTER_AOSS_SLEEP: cl 373 CLUSTER_AOSS_SLEEP: cluster-sleep-2 {
377 compatible = " 374 compatible = "domain-idle-state";
378 idle-state-nam 375 idle-state-name = "cluster-power-down";
379 arm,psci-suspe 376 arm,psci-suspend-param = <0x4100b244>;
380 entry-latency- 377 entry-latency-us = <3263>;
381 exit-latency-u 378 exit-latency-us = <6562>;
382 min-residency- 379 min-residency-us = <9826>;
383 }; 380 };
384 }; 381 };
385 }; 382 };
386 383
387 firmware { 384 firmware {
388 scm: scm { 385 scm: scm {
389 compatible = "qcom,scm 386 compatible = "qcom,scm-sc7180", "qcom,scm";
390 }; 387 };
391 }; 388 };
392 389
393 memory@80000000 { 390 memory@80000000 {
394 device_type = "memory"; 391 device_type = "memory";
395 /* We expect the bootloader to 392 /* We expect the bootloader to fill in the size */
396 reg = <0 0x80000000 0 0>; 393 reg = <0 0x80000000 0 0>;
397 }; 394 };
398 395
399 cpu0_opp_table: opp-table-cpu0 { 396 cpu0_opp_table: opp-table-cpu0 {
400 compatible = "operating-points 397 compatible = "operating-points-v2";
401 opp-shared; 398 opp-shared;
402 399
403 cpu0_opp1: opp-300000000 { 400 cpu0_opp1: opp-300000000 {
404 opp-hz = /bits/ 64 <30 401 opp-hz = /bits/ 64 <300000000>;
405 opp-peak-kBps = <12000 402 opp-peak-kBps = <1200000 4800000>;
406 }; 403 };
407 404
408 cpu0_opp2: opp-576000000 { 405 cpu0_opp2: opp-576000000 {
409 opp-hz = /bits/ 64 <57 406 opp-hz = /bits/ 64 <576000000>;
410 opp-peak-kBps = <12000 407 opp-peak-kBps = <1200000 4800000>;
411 }; 408 };
412 409
413 cpu0_opp3: opp-768000000 { 410 cpu0_opp3: opp-768000000 {
414 opp-hz = /bits/ 64 <76 411 opp-hz = /bits/ 64 <768000000>;
415 opp-peak-kBps = <12000 412 opp-peak-kBps = <1200000 4800000>;
416 }; 413 };
417 414
418 cpu0_opp4: opp-1017600000 { 415 cpu0_opp4: opp-1017600000 {
419 opp-hz = /bits/ 64 <10 416 opp-hz = /bits/ 64 <1017600000>;
420 opp-peak-kBps = <18040 417 opp-peak-kBps = <1804000 8908800>;
421 }; 418 };
422 419
423 cpu0_opp5: opp-1248000000 { 420 cpu0_opp5: opp-1248000000 {
424 opp-hz = /bits/ 64 <12 421 opp-hz = /bits/ 64 <1248000000>;
425 opp-peak-kBps = <21880 422 opp-peak-kBps = <2188000 12902400>;
426 }; 423 };
427 424
428 cpu0_opp6: opp-1324800000 { 425 cpu0_opp6: opp-1324800000 {
429 opp-hz = /bits/ 64 <13 426 opp-hz = /bits/ 64 <1324800000>;
430 opp-peak-kBps = <21880 427 opp-peak-kBps = <2188000 12902400>;
431 }; 428 };
432 429
433 cpu0_opp7: opp-1516800000 { 430 cpu0_opp7: opp-1516800000 {
434 opp-hz = /bits/ 64 <15 431 opp-hz = /bits/ 64 <1516800000>;
435 opp-peak-kBps = <30720 432 opp-peak-kBps = <3072000 15052800>;
436 }; 433 };
437 434
438 cpu0_opp8: opp-1612800000 { 435 cpu0_opp8: opp-1612800000 {
439 opp-hz = /bits/ 64 <16 436 opp-hz = /bits/ 64 <1612800000>;
440 opp-peak-kBps = <30720 437 opp-peak-kBps = <3072000 15052800>;
441 }; 438 };
442 439
443 cpu0_opp9: opp-1708800000 { 440 cpu0_opp9: opp-1708800000 {
444 opp-hz = /bits/ 64 <17 441 opp-hz = /bits/ 64 <1708800000>;
445 opp-peak-kBps = <30720 442 opp-peak-kBps = <3072000 15052800>;
446 }; 443 };
447 444
448 cpu0_opp10: opp-1804800000 { 445 cpu0_opp10: opp-1804800000 {
449 opp-hz = /bits/ 64 <18 446 opp-hz = /bits/ 64 <1804800000>;
450 opp-peak-kBps = <40680 447 opp-peak-kBps = <4068000 22425600>;
451 }; 448 };
452 }; 449 };
453 450
454 cpu6_opp_table: opp-table-cpu6 { 451 cpu6_opp_table: opp-table-cpu6 {
455 compatible = "operating-points 452 compatible = "operating-points-v2";
456 opp-shared; 453 opp-shared;
457 454
458 cpu6_opp1: opp-300000000 { 455 cpu6_opp1: opp-300000000 {
459 opp-hz = /bits/ 64 <30 456 opp-hz = /bits/ 64 <300000000>;
460 opp-peak-kBps = <21880 457 opp-peak-kBps = <2188000 8908800>;
461 }; 458 };
462 459
463 cpu6_opp2: opp-652800000 { 460 cpu6_opp2: opp-652800000 {
464 opp-hz = /bits/ 64 <65 461 opp-hz = /bits/ 64 <652800000>;
465 opp-peak-kBps = <21880 462 opp-peak-kBps = <2188000 8908800>;
466 }; 463 };
467 464
468 cpu6_opp3: opp-825600000 { 465 cpu6_opp3: opp-825600000 {
469 opp-hz = /bits/ 64 <82 466 opp-hz = /bits/ 64 <825600000>;
470 opp-peak-kBps = <21880 467 opp-peak-kBps = <2188000 8908800>;
471 }; 468 };
472 469
473 cpu6_opp4: opp-979200000 { 470 cpu6_opp4: opp-979200000 {
474 opp-hz = /bits/ 64 <97 471 opp-hz = /bits/ 64 <979200000>;
475 opp-peak-kBps = <21880 472 opp-peak-kBps = <2188000 8908800>;
476 }; 473 };
477 474
478 cpu6_opp5: opp-1113600000 { 475 cpu6_opp5: opp-1113600000 {
479 opp-hz = /bits/ 64 <11 476 opp-hz = /bits/ 64 <1113600000>;
480 opp-peak-kBps = <21880 477 opp-peak-kBps = <2188000 8908800>;
481 }; 478 };
482 479
483 cpu6_opp6: opp-1267200000 { 480 cpu6_opp6: opp-1267200000 {
484 opp-hz = /bits/ 64 <12 481 opp-hz = /bits/ 64 <1267200000>;
485 opp-peak-kBps = <40680 482 opp-peak-kBps = <4068000 12902400>;
486 }; 483 };
487 484
488 cpu6_opp7: opp-1555200000 { 485 cpu6_opp7: opp-1555200000 {
489 opp-hz = /bits/ 64 <15 486 opp-hz = /bits/ 64 <1555200000>;
490 opp-peak-kBps = <40680 487 opp-peak-kBps = <4068000 15052800>;
491 }; 488 };
492 489
493 cpu6_opp8: opp-1708800000 { 490 cpu6_opp8: opp-1708800000 {
494 opp-hz = /bits/ 64 <17 491 opp-hz = /bits/ 64 <1708800000>;
495 opp-peak-kBps = <62200 492 opp-peak-kBps = <6220000 19353600>;
496 }; 493 };
497 494
498 cpu6_opp9: opp-1843200000 { 495 cpu6_opp9: opp-1843200000 {
499 opp-hz = /bits/ 64 <18 496 opp-hz = /bits/ 64 <1843200000>;
500 opp-peak-kBps = <62200 497 opp-peak-kBps = <6220000 19353600>;
501 }; 498 };
502 499
503 cpu6_opp10: opp-1900800000 { 500 cpu6_opp10: opp-1900800000 {
504 opp-hz = /bits/ 64 <19 501 opp-hz = /bits/ 64 <1900800000>;
505 opp-peak-kBps = <62200 502 opp-peak-kBps = <6220000 22425600>;
506 }; 503 };
507 504
508 cpu6_opp11: opp-1996800000 { 505 cpu6_opp11: opp-1996800000 {
509 opp-hz = /bits/ 64 <19 506 opp-hz = /bits/ 64 <1996800000>;
510 opp-peak-kBps = <62200 507 opp-peak-kBps = <6220000 22425600>;
511 }; 508 };
512 509
513 cpu6_opp12: opp-2112000000 { 510 cpu6_opp12: opp-2112000000 {
514 opp-hz = /bits/ 64 <21 511 opp-hz = /bits/ 64 <2112000000>;
515 opp-peak-kBps = <62200 512 opp-peak-kBps = <6220000 22425600>;
516 }; 513 };
517 514
518 cpu6_opp13: opp-2208000000 { 515 cpu6_opp13: opp-2208000000 {
519 opp-hz = /bits/ 64 <22 516 opp-hz = /bits/ 64 <2208000000>;
520 opp-peak-kBps = <72160 517 opp-peak-kBps = <7216000 22425600>;
521 }; 518 };
522 519
523 cpu6_opp14: opp-2323200000 { 520 cpu6_opp14: opp-2323200000 {
524 opp-hz = /bits/ 64 <23 521 opp-hz = /bits/ 64 <2323200000>;
525 opp-peak-kBps = <72160 522 opp-peak-kBps = <7216000 22425600>;
526 }; 523 };
527 524
528 cpu6_opp15: opp-2400000000 { 525 cpu6_opp15: opp-2400000000 {
529 opp-hz = /bits/ 64 <24 526 opp-hz = /bits/ 64 <2400000000>;
530 opp-peak-kBps = <85320 527 opp-peak-kBps = <8532000 23347200>;
531 }; 528 };
532 529
533 cpu6_opp16: opp-2553600000 { 530 cpu6_opp16: opp-2553600000 {
534 opp-hz = /bits/ 64 <25 531 opp-hz = /bits/ 64 <2553600000>;
535 opp-peak-kBps = <85320 532 opp-peak-kBps = <8532000 23347200>;
536 }; 533 };
537 }; 534 };
538 535
539 qspi_opp_table: opp-table-qspi { 536 qspi_opp_table: opp-table-qspi {
540 compatible = "operating-points 537 compatible = "operating-points-v2";
541 538
542 opp-75000000 { 539 opp-75000000 {
543 opp-hz = /bits/ 64 <75 540 opp-hz = /bits/ 64 <75000000>;
544 required-opps = <&rpmh 541 required-opps = <&rpmhpd_opp_low_svs>;
545 }; 542 };
546 543
547 opp-150000000 { 544 opp-150000000 {
548 opp-hz = /bits/ 64 <15 545 opp-hz = /bits/ 64 <150000000>;
549 required-opps = <&rpmh 546 required-opps = <&rpmhpd_opp_svs>;
550 }; 547 };
551 548
552 opp-300000000 { 549 opp-300000000 {
553 opp-hz = /bits/ 64 <30 550 opp-hz = /bits/ 64 <300000000>;
554 required-opps = <&rpmh 551 required-opps = <&rpmhpd_opp_nom>;
555 }; 552 };
556 }; 553 };
557 554
558 qup_opp_table: opp-table-qup { 555 qup_opp_table: opp-table-qup {
559 compatible = "operating-points 556 compatible = "operating-points-v2";
560 557
561 opp-75000000 { 558 opp-75000000 {
562 opp-hz = /bits/ 64 <75 559 opp-hz = /bits/ 64 <75000000>;
563 required-opps = <&rpmh 560 required-opps = <&rpmhpd_opp_low_svs>;
564 }; 561 };
565 562
566 opp-100000000 { 563 opp-100000000 {
567 opp-hz = /bits/ 64 <10 564 opp-hz = /bits/ 64 <100000000>;
568 required-opps = <&rpmh 565 required-opps = <&rpmhpd_opp_svs>;
569 }; 566 };
570 567
571 opp-128000000 { 568 opp-128000000 {
572 opp-hz = /bits/ 64 <12 569 opp-hz = /bits/ 64 <128000000>;
573 required-opps = <&rpmh 570 required-opps = <&rpmhpd_opp_nom>;
574 }; 571 };
575 }; 572 };
576 573
577 pmu { 574 pmu {
578 compatible = "arm,armv8-pmuv3" 575 compatible = "arm,armv8-pmuv3";
579 interrupts = <GIC_PPI 5 IRQ_TY 576 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
580 }; 577 };
581 578
582 psci { 579 psci {
583 compatible = "arm,psci-1.0"; 580 compatible = "arm,psci-1.0";
584 method = "smc"; 581 method = "smc";
585 582
586 CPU_PD0: cpu0 { 583 CPU_PD0: cpu0 {
587 #power-domain-cells = 584 #power-domain-cells = <0>;
588 power-domains = <&CLUS 585 power-domains = <&CLUSTER_PD>;
589 domain-idle-states = < 586 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
590 }; 587 };
591 588
592 CPU_PD1: cpu1 { 589 CPU_PD1: cpu1 {
593 #power-domain-cells = 590 #power-domain-cells = <0>;
594 power-domains = <&CLUS 591 power-domains = <&CLUSTER_PD>;
595 domain-idle-states = < 592 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
596 }; 593 };
597 594
598 CPU_PD2: cpu2 { 595 CPU_PD2: cpu2 {
599 #power-domain-cells = 596 #power-domain-cells = <0>;
600 power-domains = <&CLUS 597 power-domains = <&CLUSTER_PD>;
601 domain-idle-states = < 598 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
602 }; 599 };
603 600
604 CPU_PD3: cpu3 { 601 CPU_PD3: cpu3 {
605 #power-domain-cells = 602 #power-domain-cells = <0>;
606 power-domains = <&CLUS 603 power-domains = <&CLUSTER_PD>;
607 domain-idle-states = < 604 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
608 }; 605 };
609 606
610 CPU_PD4: cpu4 { 607 CPU_PD4: cpu4 {
611 #power-domain-cells = 608 #power-domain-cells = <0>;
612 power-domains = <&CLUS 609 power-domains = <&CLUSTER_PD>;
613 domain-idle-states = < 610 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
614 }; 611 };
615 612
616 CPU_PD5: cpu5 { 613 CPU_PD5: cpu5 {
617 #power-domain-cells = 614 #power-domain-cells = <0>;
618 power-domains = <&CLUS 615 power-domains = <&CLUSTER_PD>;
619 domain-idle-states = < 616 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
620 }; 617 };
621 618
622 CPU_PD6: cpu6 { 619 CPU_PD6: cpu6 {
623 #power-domain-cells = 620 #power-domain-cells = <0>;
624 power-domains = <&CLUS 621 power-domains = <&CLUSTER_PD>;
625 domain-idle-states = < 622 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
626 }; 623 };
627 624
628 CPU_PD7: cpu7 { 625 CPU_PD7: cpu7 {
629 #power-domain-cells = 626 #power-domain-cells = <0>;
630 power-domains = <&CLUS 627 power-domains = <&CLUSTER_PD>;
631 domain-idle-states = < 628 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
632 }; 629 };
633 630
634 CLUSTER_PD: cpu-cluster0 { 631 CLUSTER_PD: cpu-cluster0 {
635 #power-domain-cells = 632 #power-domain-cells = <0>;
636 domain-idle-states = < 633 domain-idle-states = <&CLUSTER_SLEEP_PC
637 634 &CLUSTER_SLEEP_CX_RET
638 635 &CLUSTER_AOSS_SLEEP>;
639 }; 636 };
640 }; 637 };
641 638
642 reserved_memory: reserved-memory { 639 reserved_memory: reserved-memory {
643 #address-cells = <2>; 640 #address-cells = <2>;
644 #size-cells = <2>; 641 #size-cells = <2>;
645 ranges; 642 ranges;
646 643
647 hyp_mem: memory@80000000 { 644 hyp_mem: memory@80000000 {
648 reg = <0x0 0x80000000 645 reg = <0x0 0x80000000 0x0 0x600000>;
649 no-map; 646 no-map;
650 }; 647 };
651 648
652 xbl_mem: memory@80600000 { 649 xbl_mem: memory@80600000 {
653 reg = <0x0 0x80600000 650 reg = <0x0 0x80600000 0x0 0x200000>;
654 no-map; 651 no-map;
655 }; 652 };
656 653
657 aop_mem: memory@80800000 { 654 aop_mem: memory@80800000 {
658 reg = <0x0 0x80800000 655 reg = <0x0 0x80800000 0x0 0x20000>;
659 no-map; 656 no-map;
660 }; 657 };
661 658
662 aop_cmd_db_mem: memory@8082000 659 aop_cmd_db_mem: memory@80820000 {
663 reg = <0x0 0x80820000 660 reg = <0x0 0x80820000 0x0 0x20000>;
664 compatible = "qcom,cmd 661 compatible = "qcom,cmd-db";
665 no-map; 662 no-map;
666 }; 663 };
667 664
668 sec_apps_mem: memory@808ff000 665 sec_apps_mem: memory@808ff000 {
669 reg = <0x0 0x808ff000 666 reg = <0x0 0x808ff000 0x0 0x1000>;
670 no-map; 667 no-map;
671 }; 668 };
672 669
673 smem_mem: memory@80900000 { 670 smem_mem: memory@80900000 {
674 reg = <0x0 0x80900000 671 reg = <0x0 0x80900000 0x0 0x200000>;
675 no-map; 672 no-map;
676 }; 673 };
677 674
678 tz_mem: memory@80b00000 { 675 tz_mem: memory@80b00000 {
679 reg = <0x0 0x80b00000 676 reg = <0x0 0x80b00000 0x0 0x3900000>;
680 no-map; 677 no-map;
681 }; 678 };
682 679
683 ipa_fw_mem: memory@8b700000 { 680 ipa_fw_mem: memory@8b700000 {
684 reg = <0 0x8b700000 0 681 reg = <0 0x8b700000 0 0x10000>;
685 no-map; 682 no-map;
686 }; 683 };
687 684
688 rmtfs_mem: memory@94600000 { 685 rmtfs_mem: memory@94600000 {
689 compatible = "qcom,rmt 686 compatible = "qcom,rmtfs-mem";
690 reg = <0x0 0x94600000 687 reg = <0x0 0x94600000 0x0 0x200000>;
691 no-map; 688 no-map;
692 689
693 qcom,client-id = <1>; 690 qcom,client-id = <1>;
694 qcom,vmid = <QCOM_SCM_ !! 691 qcom,vmid = <15>;
695 }; 692 };
696 }; 693 };
697 694
698 smem { 695 smem {
699 compatible = "qcom,smem"; 696 compatible = "qcom,smem";
700 memory-region = <&smem_mem>; 697 memory-region = <&smem_mem>;
701 hwlocks = <&tcsr_mutex 3>; 698 hwlocks = <&tcsr_mutex 3>;
702 }; 699 };
703 700
704 smp2p-cdsp { 701 smp2p-cdsp {
705 compatible = "qcom,smp2p"; 702 compatible = "qcom,smp2p";
706 qcom,smem = <94>, <432>; 703 qcom,smem = <94>, <432>;
707 704
708 interrupts = <GIC_SPI 576 IRQ_ 705 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
709 706
710 mboxes = <&apss_shared 6>; 707 mboxes = <&apss_shared 6>;
711 708
712 qcom,local-pid = <0>; 709 qcom,local-pid = <0>;
713 qcom,remote-pid = <5>; 710 qcom,remote-pid = <5>;
714 711
715 cdsp_smp2p_out: master-kernel 712 cdsp_smp2p_out: master-kernel {
716 qcom,entry-name = "mas 713 qcom,entry-name = "master-kernel";
717 #qcom,smem-state-cells 714 #qcom,smem-state-cells = <1>;
718 }; 715 };
719 716
720 cdsp_smp2p_in: slave-kernel { 717 cdsp_smp2p_in: slave-kernel {
721 qcom,entry-name = "sla 718 qcom,entry-name = "slave-kernel";
722 719
723 interrupt-controller; 720 interrupt-controller;
724 #interrupt-cells = <2> 721 #interrupt-cells = <2>;
725 }; 722 };
726 }; 723 };
727 724
728 smp2p-lpass { 725 smp2p-lpass {
729 compatible = "qcom,smp2p"; 726 compatible = "qcom,smp2p";
730 qcom,smem = <443>, <429>; 727 qcom,smem = <443>, <429>;
731 728
732 interrupts = <GIC_SPI 158 IRQ_ 729 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
733 730
734 mboxes = <&apss_shared 10>; 731 mboxes = <&apss_shared 10>;
735 732
736 qcom,local-pid = <0>; 733 qcom,local-pid = <0>;
737 qcom,remote-pid = <2>; 734 qcom,remote-pid = <2>;
738 735
739 adsp_smp2p_out: master-kernel 736 adsp_smp2p_out: master-kernel {
740 qcom,entry-name = "mas 737 qcom,entry-name = "master-kernel";
741 #qcom,smem-state-cells 738 #qcom,smem-state-cells = <1>;
742 }; 739 };
743 740
744 adsp_smp2p_in: slave-kernel { 741 adsp_smp2p_in: slave-kernel {
745 qcom,entry-name = "sla 742 qcom,entry-name = "slave-kernel";
746 743
747 interrupt-controller; 744 interrupt-controller;
748 #interrupt-cells = <2> 745 #interrupt-cells = <2>;
749 }; 746 };
750 }; 747 };
751 748
752 smp2p-mpss { 749 smp2p-mpss {
753 compatible = "qcom,smp2p"; 750 compatible = "qcom,smp2p";
754 qcom,smem = <435>, <428>; 751 qcom,smem = <435>, <428>;
755 interrupts = <GIC_SPI 451 IRQ_ 752 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
756 mboxes = <&apss_shared 14>; 753 mboxes = <&apss_shared 14>;
757 qcom,local-pid = <0>; 754 qcom,local-pid = <0>;
758 qcom,remote-pid = <1>; 755 qcom,remote-pid = <1>;
759 756
760 modem_smp2p_out: master-kernel 757 modem_smp2p_out: master-kernel {
761 qcom,entry-name = "mas 758 qcom,entry-name = "master-kernel";
762 #qcom,smem-state-cells 759 #qcom,smem-state-cells = <1>;
763 }; 760 };
764 761
765 modem_smp2p_in: slave-kernel { 762 modem_smp2p_in: slave-kernel {
766 qcom,entry-name = "sla 763 qcom,entry-name = "slave-kernel";
767 interrupt-controller; 764 interrupt-controller;
768 #interrupt-cells = <2> 765 #interrupt-cells = <2>;
769 }; 766 };
770 767
771 ipa_smp2p_out: ipa-ap-to-modem 768 ipa_smp2p_out: ipa-ap-to-modem {
772 qcom,entry-name = "ipa 769 qcom,entry-name = "ipa";
773 #qcom,smem-state-cells 770 #qcom,smem-state-cells = <1>;
774 }; 771 };
775 772
776 ipa_smp2p_in: ipa-modem-to-ap 773 ipa_smp2p_in: ipa-modem-to-ap {
777 qcom,entry-name = "ipa 774 qcom,entry-name = "ipa";
778 interrupt-controller; 775 interrupt-controller;
779 #interrupt-cells = <2> 776 #interrupt-cells = <2>;
780 }; 777 };
781 }; 778 };
782 779
783 soc: soc@0 { 780 soc: soc@0 {
784 #address-cells = <2>; 781 #address-cells = <2>;
785 #size-cells = <2>; 782 #size-cells = <2>;
786 ranges = <0 0 0 0 0x10 0>; 783 ranges = <0 0 0 0 0x10 0>;
787 dma-ranges = <0 0 0 0 0x10 0>; 784 dma-ranges = <0 0 0 0 0x10 0>;
788 compatible = "simple-bus"; 785 compatible = "simple-bus";
789 786
790 gcc: clock-controller@100000 { 787 gcc: clock-controller@100000 {
791 compatible = "qcom,gcc 788 compatible = "qcom,gcc-sc7180";
792 reg = <0 0x00100000 0 789 reg = <0 0x00100000 0 0x1f0000>;
793 clocks = <&rpmhcc RPMH 790 clocks = <&rpmhcc RPMH_CXO_CLK>,
794 <&rpmhcc RPMH 791 <&rpmhcc RPMH_CXO_CLK_A>,
795 <&sleep_clk>; 792 <&sleep_clk>;
796 clock-names = "bi_tcxo 793 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
797 #clock-cells = <1>; 794 #clock-cells = <1>;
798 #reset-cells = <1>; 795 #reset-cells = <1>;
799 #power-domain-cells = 796 #power-domain-cells = <1>;
800 power-domains = <&rpmh 797 power-domains = <&rpmhpd SC7180_CX>;
801 }; 798 };
802 799
803 qfprom: efuse@784000 { 800 qfprom: efuse@784000 {
804 compatible = "qcom,sc7 801 compatible = "qcom,sc7180-qfprom", "qcom,qfprom";
805 reg = <0 0x00784000 0 802 reg = <0 0x00784000 0 0x7a0>,
806 <0 0x00780000 0 803 <0 0x00780000 0 0x7a0>,
807 <0 0x00782000 0 804 <0 0x00782000 0 0x100>,
808 <0 0x00786000 0 805 <0 0x00786000 0 0x1fff>;
809 806
810 clocks = <&gcc GCC_SEC 807 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>;
811 clock-names = "core"; 808 clock-names = "core";
812 #address-cells = <1>; 809 #address-cells = <1>;
813 #size-cells = <1>; 810 #size-cells = <1>;
814 811
815 qusb2p_hstx_trim: hstx 812 qusb2p_hstx_trim: hstx-trim-primary@25b {
816 reg = <0x25b 0 813 reg = <0x25b 0x1>;
817 bits = <1 3>; 814 bits = <1 3>;
818 }; 815 };
819 816
820 gpu_speed_bin: gpu-spe !! 817 gpu_speed_bin: gpu_speed_bin@1d2 {
821 reg = <0x1d2 0 818 reg = <0x1d2 0x2>;
822 bits = <5 8>; 819 bits = <5 8>;
823 }; 820 };
824 }; 821 };
825 822
826 sdhc_1: mmc@7c4000 { 823 sdhc_1: mmc@7c4000 {
827 compatible = "qcom,sc7 824 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
828 reg = <0 0x007c4000 0 825 reg = <0 0x007c4000 0 0x1000>,
829 <0 0x007c5000 826 <0 0x007c5000 0 0x1000>;
830 reg-names = "hc", "cqh 827 reg-names = "hc", "cqhci";
831 828
832 iommus = <&apps_smmu 0 829 iommus = <&apps_smmu 0x60 0x0>;
833 interrupts = <GIC_SPI 830 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
834 <GIC_S 831 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
835 interrupt-names = "hc_ 832 interrupt-names = "hc_irq", "pwr_irq";
836 833
837 clocks = <&gcc GCC_SDC 834 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
838 <&gcc GCC_SDC 835 <&gcc GCC_SDCC1_APPS_CLK>,
839 <&rpmhcc RPMH 836 <&rpmhcc RPMH_CXO_CLK>;
840 clock-names = "iface", 837 clock-names = "iface", "core", "xo";
841 interconnects = <&aggr 838 interconnects = <&aggre1_noc MASTER_EMMC 0 &mc_virt SLAVE_EBI1 0>,
842 <&gem_ 839 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_EMMC_CFG 0>;
843 interconnect-names = " 840 interconnect-names = "sdhc-ddr","cpu-sdhc";
844 power-domains = <&rpmh 841 power-domains = <&rpmhpd SC7180_CX>;
845 operating-points-v2 = 842 operating-points-v2 = <&sdhc1_opp_table>;
846 843
847 bus-width = <8>; 844 bus-width = <8>;
848 non-removable; 845 non-removable;
849 supports-cqe; 846 supports-cqe;
850 847
851 mmc-ddr-1_8v; 848 mmc-ddr-1_8v;
852 mmc-hs200-1_8v; 849 mmc-hs200-1_8v;
853 mmc-hs400-1_8v; 850 mmc-hs400-1_8v;
854 mmc-hs400-enhanced-str 851 mmc-hs400-enhanced-strobe;
855 852
856 status = "disabled"; 853 status = "disabled";
857 854
858 sdhc1_opp_table: opp-t 855 sdhc1_opp_table: opp-table {
859 compatible = " 856 compatible = "operating-points-v2";
860 857
861 opp-100000000 858 opp-100000000 {
862 opp-hz 859 opp-hz = /bits/ 64 <100000000>;
863 requir 860 required-opps = <&rpmhpd_opp_low_svs>;
864 opp-pe 861 opp-peak-kBps = <1800000 600000>;
865 opp-av 862 opp-avg-kBps = <100000 0>;
866 }; 863 };
867 864
868 opp-384000000 865 opp-384000000 {
869 opp-hz 866 opp-hz = /bits/ 64 <384000000>;
870 requir 867 required-opps = <&rpmhpd_opp_nom>;
871 opp-pe 868 opp-peak-kBps = <5400000 1600000>;
872 opp-av 869 opp-avg-kBps = <390000 0>;
873 }; 870 };
874 }; 871 };
875 }; 872 };
876 873
877 qupv3_id_0: geniqup@8c0000 { 874 qupv3_id_0: geniqup@8c0000 {
878 compatible = "qcom,gen 875 compatible = "qcom,geni-se-qup";
879 reg = <0 0x008c0000 0 876 reg = <0 0x008c0000 0 0x6000>;
880 clock-names = "m-ahb", 877 clock-names = "m-ahb", "s-ahb";
881 clocks = <&gcc GCC_QUP 878 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
882 <&gcc GCC_QUP 879 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
883 #address-cells = <2>; 880 #address-cells = <2>;
884 #size-cells = <2>; 881 #size-cells = <2>;
885 ranges; 882 ranges;
886 iommus = <&apps_smmu 0 883 iommus = <&apps_smmu 0x43 0x0>;
887 status = "disabled"; 884 status = "disabled";
888 885
889 i2c0: i2c@880000 { 886 i2c0: i2c@880000 {
890 compatible = " 887 compatible = "qcom,geni-i2c";
891 reg = <0 0x008 888 reg = <0 0x00880000 0 0x4000>;
892 clock-names = 889 clock-names = "se";
893 clocks = <&gcc 890 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
894 pinctrl-names 891 pinctrl-names = "default";
895 pinctrl-0 = <& 892 pinctrl-0 = <&qup_i2c0_default>;
896 interrupts = < 893 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
897 #address-cells 894 #address-cells = <1>;
898 #size-cells = 895 #size-cells = <0>;
899 interconnects 896 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
900 897 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
901 898 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
902 interconnect-n 899 interconnect-names = "qup-core", "qup-config",
903 900 "qup-memory";
904 power-domains 901 power-domains = <&rpmhpd SC7180_CX>;
905 required-opps 902 required-opps = <&rpmhpd_opp_low_svs>;
906 status = "disa 903 status = "disabled";
907 }; 904 };
908 905
909 spi0: spi@880000 { 906 spi0: spi@880000 {
910 compatible = " 907 compatible = "qcom,geni-spi";
911 reg = <0 0x008 908 reg = <0 0x00880000 0 0x4000>;
912 clock-names = 909 clock-names = "se";
913 clocks = <&gcc 910 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
914 pinctrl-names 911 pinctrl-names = "default";
915 pinctrl-0 = <& 912 pinctrl-0 = <&qup_spi0_spi>, <&qup_spi0_cs>;
916 interrupts = < 913 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
917 #address-cells 914 #address-cells = <1>;
918 #size-cells = 915 #size-cells = <0>;
919 power-domains 916 power-domains = <&rpmhpd SC7180_CX>;
920 operating-poin 917 operating-points-v2 = <&qup_opp_table>;
921 interconnects 918 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
922 919 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
923 interconnect-n 920 interconnect-names = "qup-core", "qup-config";
924 status = "disa 921 status = "disabled";
925 }; 922 };
926 923
927 uart0: serial@880000 { 924 uart0: serial@880000 {
928 compatible = " 925 compatible = "qcom,geni-uart";
929 reg = <0 0x008 926 reg = <0 0x00880000 0 0x4000>;
930 clock-names = 927 clock-names = "se";
931 clocks = <&gcc 928 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
932 pinctrl-names 929 pinctrl-names = "default";
933 pinctrl-0 = <& 930 pinctrl-0 = <&qup_uart0_default>;
934 interrupts = < 931 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
935 power-domains 932 power-domains = <&rpmhpd SC7180_CX>;
936 operating-poin 933 operating-points-v2 = <&qup_opp_table>;
937 interconnects 934 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
938 935 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
939 interconnect-n 936 interconnect-names = "qup-core", "qup-config";
940 status = "disa 937 status = "disabled";
941 }; 938 };
942 939
943 i2c1: i2c@884000 { 940 i2c1: i2c@884000 {
944 compatible = " 941 compatible = "qcom,geni-i2c";
945 reg = <0 0x008 942 reg = <0 0x00884000 0 0x4000>;
946 clock-names = 943 clock-names = "se";
947 clocks = <&gcc 944 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
948 pinctrl-names 945 pinctrl-names = "default";
949 pinctrl-0 = <& 946 pinctrl-0 = <&qup_i2c1_default>;
950 interrupts = < 947 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
951 #address-cells 948 #address-cells = <1>;
952 #size-cells = 949 #size-cells = <0>;
953 interconnects 950 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
954 951 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
955 952 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
956 interconnect-n 953 interconnect-names = "qup-core", "qup-config",
957 954 "qup-memory";
958 power-domains 955 power-domains = <&rpmhpd SC7180_CX>;
959 required-opps 956 required-opps = <&rpmhpd_opp_low_svs>;
960 status = "disa 957 status = "disabled";
961 }; 958 };
962 959
963 spi1: spi@884000 { 960 spi1: spi@884000 {
964 compatible = " 961 compatible = "qcom,geni-spi";
965 reg = <0 0x008 962 reg = <0 0x00884000 0 0x4000>;
966 clock-names = 963 clock-names = "se";
967 clocks = <&gcc 964 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
968 pinctrl-names 965 pinctrl-names = "default";
969 pinctrl-0 = <& 966 pinctrl-0 = <&qup_spi1_spi>, <&qup_spi1_cs>;
970 interrupts = < 967 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
971 #address-cells 968 #address-cells = <1>;
972 #size-cells = 969 #size-cells = <0>;
973 power-domains 970 power-domains = <&rpmhpd SC7180_CX>;
974 operating-poin 971 operating-points-v2 = <&qup_opp_table>;
975 interconnects 972 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
976 973 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
977 interconnect-n 974 interconnect-names = "qup-core", "qup-config";
978 status = "disa 975 status = "disabled";
979 }; 976 };
980 977
981 uart1: serial@884000 { 978 uart1: serial@884000 {
982 compatible = " 979 compatible = "qcom,geni-uart";
983 reg = <0 0x008 980 reg = <0 0x00884000 0 0x4000>;
984 clock-names = 981 clock-names = "se";
985 clocks = <&gcc 982 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
986 pinctrl-names 983 pinctrl-names = "default";
987 pinctrl-0 = <& 984 pinctrl-0 = <&qup_uart1_default>;
988 interrupts = < 985 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
989 power-domains 986 power-domains = <&rpmhpd SC7180_CX>;
990 operating-poin 987 operating-points-v2 = <&qup_opp_table>;
991 interconnects 988 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
992 989 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
993 interconnect-n 990 interconnect-names = "qup-core", "qup-config";
994 status = "disa 991 status = "disabled";
995 }; 992 };
996 993
997 i2c2: i2c@888000 { 994 i2c2: i2c@888000 {
998 compatible = " 995 compatible = "qcom,geni-i2c";
999 reg = <0 0x008 996 reg = <0 0x00888000 0 0x4000>;
1000 clock-names = 997 clock-names = "se";
1001 clocks = <&gc 998 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1002 pinctrl-names 999 pinctrl-names = "default";
1003 pinctrl-0 = < 1000 pinctrl-0 = <&qup_i2c2_default>;
1004 interrupts = 1001 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1005 #address-cell 1002 #address-cells = <1>;
1006 #size-cells = 1003 #size-cells = <0>;
1007 interconnects 1004 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1008 1005 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1009 1006 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1010 interconnect- 1007 interconnect-names = "qup-core", "qup-config",
1011 1008 "qup-memory";
1012 power-domains 1009 power-domains = <&rpmhpd SC7180_CX>;
1013 required-opps 1010 required-opps = <&rpmhpd_opp_low_svs>;
1014 status = "dis 1011 status = "disabled";
1015 }; 1012 };
1016 1013
1017 uart2: serial@888000 1014 uart2: serial@888000 {
1018 compatible = 1015 compatible = "qcom,geni-uart";
1019 reg = <0 0x00 1016 reg = <0 0x00888000 0 0x4000>;
1020 clock-names = 1017 clock-names = "se";
1021 clocks = <&gc 1018 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1022 pinctrl-names 1019 pinctrl-names = "default";
1023 pinctrl-0 = < 1020 pinctrl-0 = <&qup_uart2_default>;
1024 interrupts = 1021 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1025 power-domains 1022 power-domains = <&rpmhpd SC7180_CX>;
1026 operating-poi 1023 operating-points-v2 = <&qup_opp_table>;
1027 interconnects 1024 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1028 1025 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1029 interconnect- 1026 interconnect-names = "qup-core", "qup-config";
1030 status = "dis 1027 status = "disabled";
1031 }; 1028 };
1032 1029
1033 i2c3: i2c@88c000 { 1030 i2c3: i2c@88c000 {
1034 compatible = 1031 compatible = "qcom,geni-i2c";
1035 reg = <0 0x00 1032 reg = <0 0x0088c000 0 0x4000>;
1036 clock-names = 1033 clock-names = "se";
1037 clocks = <&gc 1034 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1038 pinctrl-names 1035 pinctrl-names = "default";
1039 pinctrl-0 = < 1036 pinctrl-0 = <&qup_i2c3_default>;
1040 interrupts = 1037 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1041 #address-cell 1038 #address-cells = <1>;
1042 #size-cells = 1039 #size-cells = <0>;
1043 interconnects 1040 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1044 1041 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1045 1042 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1046 interconnect- 1043 interconnect-names = "qup-core", "qup-config",
1047 1044 "qup-memory";
1048 power-domains 1045 power-domains = <&rpmhpd SC7180_CX>;
1049 required-opps 1046 required-opps = <&rpmhpd_opp_low_svs>;
1050 status = "dis 1047 status = "disabled";
1051 }; 1048 };
1052 1049
1053 spi3: spi@88c000 { 1050 spi3: spi@88c000 {
1054 compatible = 1051 compatible = "qcom,geni-spi";
1055 reg = <0 0x00 1052 reg = <0 0x0088c000 0 0x4000>;
1056 clock-names = 1053 clock-names = "se";
1057 clocks = <&gc 1054 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1058 pinctrl-names 1055 pinctrl-names = "default";
1059 pinctrl-0 = < 1056 pinctrl-0 = <&qup_spi3_spi>, <&qup_spi3_cs>;
1060 interrupts = 1057 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1061 #address-cell 1058 #address-cells = <1>;
1062 #size-cells = 1059 #size-cells = <0>;
1063 power-domains 1060 power-domains = <&rpmhpd SC7180_CX>;
1064 operating-poi 1061 operating-points-v2 = <&qup_opp_table>;
1065 interconnects 1062 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1066 1063 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1067 interconnect- 1064 interconnect-names = "qup-core", "qup-config";
1068 status = "dis 1065 status = "disabled";
1069 }; 1066 };
1070 1067
1071 uart3: serial@88c000 1068 uart3: serial@88c000 {
1072 compatible = 1069 compatible = "qcom,geni-uart";
1073 reg = <0 0x00 1070 reg = <0 0x0088c000 0 0x4000>;
1074 clock-names = 1071 clock-names = "se";
1075 clocks = <&gc 1072 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1076 pinctrl-names 1073 pinctrl-names = "default";
1077 pinctrl-0 = < 1074 pinctrl-0 = <&qup_uart3_default>;
1078 interrupts = 1075 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1079 power-domains 1076 power-domains = <&rpmhpd SC7180_CX>;
1080 operating-poi 1077 operating-points-v2 = <&qup_opp_table>;
1081 interconnects 1078 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1082 1079 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1083 interconnect- 1080 interconnect-names = "qup-core", "qup-config";
1084 status = "dis 1081 status = "disabled";
1085 }; 1082 };
1086 1083
1087 i2c4: i2c@890000 { 1084 i2c4: i2c@890000 {
1088 compatible = 1085 compatible = "qcom,geni-i2c";
1089 reg = <0 0x00 1086 reg = <0 0x00890000 0 0x4000>;
1090 clock-names = 1087 clock-names = "se";
1091 clocks = <&gc 1088 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1092 pinctrl-names 1089 pinctrl-names = "default";
1093 pinctrl-0 = < 1090 pinctrl-0 = <&qup_i2c4_default>;
1094 interrupts = 1091 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1095 #address-cell 1092 #address-cells = <1>;
1096 #size-cells = 1093 #size-cells = <0>;
1097 interconnects 1094 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1098 1095 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1099 1096 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1100 interconnect- 1097 interconnect-names = "qup-core", "qup-config",
1101 1098 "qup-memory";
1102 power-domains 1099 power-domains = <&rpmhpd SC7180_CX>;
1103 required-opps 1100 required-opps = <&rpmhpd_opp_low_svs>;
1104 status = "dis 1101 status = "disabled";
1105 }; 1102 };
1106 1103
1107 uart4: serial@890000 1104 uart4: serial@890000 {
1108 compatible = 1105 compatible = "qcom,geni-uart";
1109 reg = <0 0x00 1106 reg = <0 0x00890000 0 0x4000>;
1110 clock-names = 1107 clock-names = "se";
1111 clocks = <&gc 1108 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1112 pinctrl-names 1109 pinctrl-names = "default";
1113 pinctrl-0 = < 1110 pinctrl-0 = <&qup_uart4_default>;
1114 interrupts = 1111 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1115 power-domains 1112 power-domains = <&rpmhpd SC7180_CX>;
1116 operating-poi 1113 operating-points-v2 = <&qup_opp_table>;
1117 interconnects 1114 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1118 1115 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1119 interconnect- 1116 interconnect-names = "qup-core", "qup-config";
1120 status = "dis 1117 status = "disabled";
1121 }; 1118 };
1122 1119
1123 i2c5: i2c@894000 { 1120 i2c5: i2c@894000 {
1124 compatible = 1121 compatible = "qcom,geni-i2c";
1125 reg = <0 0x00 1122 reg = <0 0x00894000 0 0x4000>;
1126 clock-names = 1123 clock-names = "se";
1127 clocks = <&gc 1124 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1128 pinctrl-names 1125 pinctrl-names = "default";
1129 pinctrl-0 = < 1126 pinctrl-0 = <&qup_i2c5_default>;
1130 interrupts = 1127 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1131 #address-cell 1128 #address-cells = <1>;
1132 #size-cells = 1129 #size-cells = <0>;
1133 interconnects 1130 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1134 1131 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1135 1132 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1136 interconnect- 1133 interconnect-names = "qup-core", "qup-config",
1137 1134 "qup-memory";
1138 power-domains 1135 power-domains = <&rpmhpd SC7180_CX>;
1139 required-opps 1136 required-opps = <&rpmhpd_opp_low_svs>;
1140 status = "dis 1137 status = "disabled";
1141 }; 1138 };
1142 1139
1143 spi5: spi@894000 { 1140 spi5: spi@894000 {
1144 compatible = 1141 compatible = "qcom,geni-spi";
1145 reg = <0 0x00 1142 reg = <0 0x00894000 0 0x4000>;
1146 clock-names = 1143 clock-names = "se";
1147 clocks = <&gc 1144 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1148 pinctrl-names 1145 pinctrl-names = "default";
1149 pinctrl-0 = < 1146 pinctrl-0 = <&qup_spi5_spi>, <&qup_spi5_cs>;
1150 interrupts = 1147 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1151 #address-cell 1148 #address-cells = <1>;
1152 #size-cells = 1149 #size-cells = <0>;
1153 power-domains 1150 power-domains = <&rpmhpd SC7180_CX>;
1154 operating-poi 1151 operating-points-v2 = <&qup_opp_table>;
1155 interconnects 1152 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1156 1153 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1157 interconnect- 1154 interconnect-names = "qup-core", "qup-config";
1158 status = "dis 1155 status = "disabled";
1159 }; 1156 };
1160 1157
1161 uart5: serial@894000 1158 uart5: serial@894000 {
1162 compatible = 1159 compatible = "qcom,geni-uart";
1163 reg = <0 0x00 1160 reg = <0 0x00894000 0 0x4000>;
1164 clock-names = 1161 clock-names = "se";
1165 clocks = <&gc 1162 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1166 pinctrl-names 1163 pinctrl-names = "default";
1167 pinctrl-0 = < 1164 pinctrl-0 = <&qup_uart5_default>;
1168 interrupts = 1165 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1169 power-domains 1166 power-domains = <&rpmhpd SC7180_CX>;
1170 operating-poi 1167 operating-points-v2 = <&qup_opp_table>;
1171 interconnects 1168 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1172 1169 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1173 interconnect- 1170 interconnect-names = "qup-core", "qup-config";
1174 status = "dis 1171 status = "disabled";
1175 }; 1172 };
1176 }; 1173 };
1177 1174
1178 qupv3_id_1: geniqup@ac0000 { 1175 qupv3_id_1: geniqup@ac0000 {
1179 compatible = "qcom,ge 1176 compatible = "qcom,geni-se-qup";
1180 reg = <0 0x00ac0000 0 1177 reg = <0 0x00ac0000 0 0x6000>;
1181 clock-names = "m-ahb" 1178 clock-names = "m-ahb", "s-ahb";
1182 clocks = <&gcc GCC_QU 1179 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1183 <&gcc GCC_QU 1180 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1184 #address-cells = <2>; 1181 #address-cells = <2>;
1185 #size-cells = <2>; 1182 #size-cells = <2>;
1186 ranges; 1183 ranges;
1187 iommus = <&apps_smmu 1184 iommus = <&apps_smmu 0x4c3 0x0>;
1188 status = "disabled"; 1185 status = "disabled";
1189 1186
1190 i2c6: i2c@a80000 { 1187 i2c6: i2c@a80000 {
1191 compatible = 1188 compatible = "qcom,geni-i2c";
1192 reg = <0 0x00 1189 reg = <0 0x00a80000 0 0x4000>;
1193 clock-names = 1190 clock-names = "se";
1194 clocks = <&gc 1191 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1195 pinctrl-names 1192 pinctrl-names = "default";
1196 pinctrl-0 = < 1193 pinctrl-0 = <&qup_i2c6_default>;
1197 interrupts = 1194 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1198 #address-cell 1195 #address-cells = <1>;
1199 #size-cells = 1196 #size-cells = <0>;
1200 interconnects 1197 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1201 1198 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1202 1199 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1203 interconnect- 1200 interconnect-names = "qup-core", "qup-config",
1204 1201 "qup-memory";
1205 power-domains 1202 power-domains = <&rpmhpd SC7180_CX>;
1206 required-opps 1203 required-opps = <&rpmhpd_opp_low_svs>;
1207 status = "dis 1204 status = "disabled";
1208 }; 1205 };
1209 1206
1210 spi6: spi@a80000 { 1207 spi6: spi@a80000 {
1211 compatible = 1208 compatible = "qcom,geni-spi";
1212 reg = <0 0x00 1209 reg = <0 0x00a80000 0 0x4000>;
1213 clock-names = 1210 clock-names = "se";
1214 clocks = <&gc 1211 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1215 pinctrl-names 1212 pinctrl-names = "default";
1216 pinctrl-0 = < 1213 pinctrl-0 = <&qup_spi6_spi>, <&qup_spi6_cs>;
1217 interrupts = 1214 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1218 #address-cell 1215 #address-cells = <1>;
1219 #size-cells = 1216 #size-cells = <0>;
1220 power-domains 1217 power-domains = <&rpmhpd SC7180_CX>;
1221 operating-poi 1218 operating-points-v2 = <&qup_opp_table>;
1222 interconnects 1219 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1223 1220 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1224 interconnect- 1221 interconnect-names = "qup-core", "qup-config";
1225 status = "dis 1222 status = "disabled";
1226 }; 1223 };
1227 1224
1228 uart6: serial@a80000 1225 uart6: serial@a80000 {
1229 compatible = 1226 compatible = "qcom,geni-uart";
1230 reg = <0 0x00 1227 reg = <0 0x00a80000 0 0x4000>;
1231 clock-names = 1228 clock-names = "se";
1232 clocks = <&gc 1229 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1233 pinctrl-names 1230 pinctrl-names = "default";
1234 pinctrl-0 = < 1231 pinctrl-0 = <&qup_uart6_default>;
1235 interrupts = 1232 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1236 power-domains 1233 power-domains = <&rpmhpd SC7180_CX>;
1237 operating-poi 1234 operating-points-v2 = <&qup_opp_table>;
1238 interconnects 1235 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1239 1236 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1240 interconnect- 1237 interconnect-names = "qup-core", "qup-config";
1241 status = "dis 1238 status = "disabled";
1242 }; 1239 };
1243 1240
1244 i2c7: i2c@a84000 { 1241 i2c7: i2c@a84000 {
1245 compatible = 1242 compatible = "qcom,geni-i2c";
1246 reg = <0 0x00 1243 reg = <0 0x00a84000 0 0x4000>;
1247 clock-names = 1244 clock-names = "se";
1248 clocks = <&gc 1245 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1249 pinctrl-names 1246 pinctrl-names = "default";
1250 pinctrl-0 = < 1247 pinctrl-0 = <&qup_i2c7_default>;
1251 interrupts = 1248 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1252 #address-cell 1249 #address-cells = <1>;
1253 #size-cells = 1250 #size-cells = <0>;
1254 interconnects 1251 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1255 1252 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1256 1253 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1257 interconnect- 1254 interconnect-names = "qup-core", "qup-config",
1258 1255 "qup-memory";
1259 power-domains 1256 power-domains = <&rpmhpd SC7180_CX>;
1260 required-opps 1257 required-opps = <&rpmhpd_opp_low_svs>;
1261 status = "dis 1258 status = "disabled";
1262 }; 1259 };
1263 1260
1264 uart7: serial@a84000 1261 uart7: serial@a84000 {
1265 compatible = 1262 compatible = "qcom,geni-uart";
1266 reg = <0 0x00 1263 reg = <0 0x00a84000 0 0x4000>;
1267 clock-names = 1264 clock-names = "se";
1268 clocks = <&gc 1265 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1269 pinctrl-names 1266 pinctrl-names = "default";
1270 pinctrl-0 = < 1267 pinctrl-0 = <&qup_uart7_default>;
1271 interrupts = 1268 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1272 power-domains 1269 power-domains = <&rpmhpd SC7180_CX>;
1273 operating-poi 1270 operating-points-v2 = <&qup_opp_table>;
1274 interconnects 1271 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1275 1272 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1276 interconnect- 1273 interconnect-names = "qup-core", "qup-config";
1277 status = "dis 1274 status = "disabled";
1278 }; 1275 };
1279 1276
1280 i2c8: i2c@a88000 { 1277 i2c8: i2c@a88000 {
1281 compatible = 1278 compatible = "qcom,geni-i2c";
1282 reg = <0 0x00 1279 reg = <0 0x00a88000 0 0x4000>;
1283 clock-names = 1280 clock-names = "se";
1284 clocks = <&gc 1281 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1285 pinctrl-names 1282 pinctrl-names = "default";
1286 pinctrl-0 = < 1283 pinctrl-0 = <&qup_i2c8_default>;
1287 interrupts = 1284 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1288 #address-cell 1285 #address-cells = <1>;
1289 #size-cells = 1286 #size-cells = <0>;
1290 interconnects 1287 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1291 1288 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1292 1289 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1293 interconnect- 1290 interconnect-names = "qup-core", "qup-config",
1294 1291 "qup-memory";
1295 power-domains 1292 power-domains = <&rpmhpd SC7180_CX>;
1296 required-opps 1293 required-opps = <&rpmhpd_opp_low_svs>;
1297 status = "dis 1294 status = "disabled";
1298 }; 1295 };
1299 1296
1300 spi8: spi@a88000 { 1297 spi8: spi@a88000 {
1301 compatible = 1298 compatible = "qcom,geni-spi";
1302 reg = <0 0x00 1299 reg = <0 0x00a88000 0 0x4000>;
1303 clock-names = 1300 clock-names = "se";
1304 clocks = <&gc 1301 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1305 pinctrl-names 1302 pinctrl-names = "default";
1306 pinctrl-0 = < 1303 pinctrl-0 = <&qup_spi8_spi>, <&qup_spi8_cs>;
1307 interrupts = 1304 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1308 #address-cell 1305 #address-cells = <1>;
1309 #size-cells = 1306 #size-cells = <0>;
1310 power-domains 1307 power-domains = <&rpmhpd SC7180_CX>;
1311 operating-poi 1308 operating-points-v2 = <&qup_opp_table>;
1312 interconnects 1309 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1313 1310 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1314 interconnect- 1311 interconnect-names = "qup-core", "qup-config";
1315 status = "dis 1312 status = "disabled";
1316 }; 1313 };
1317 1314
1318 uart8: serial@a88000 1315 uart8: serial@a88000 {
1319 compatible = 1316 compatible = "qcom,geni-debug-uart";
1320 reg = <0 0x00 1317 reg = <0 0x00a88000 0 0x4000>;
1321 clock-names = 1318 clock-names = "se";
1322 clocks = <&gc 1319 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1323 pinctrl-names 1320 pinctrl-names = "default";
1324 pinctrl-0 = < 1321 pinctrl-0 = <&qup_uart8_default>;
1325 interrupts = 1322 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1326 power-domains 1323 power-domains = <&rpmhpd SC7180_CX>;
1327 operating-poi 1324 operating-points-v2 = <&qup_opp_table>;
1328 interconnects 1325 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1329 1326 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1330 interconnect- 1327 interconnect-names = "qup-core", "qup-config";
1331 status = "dis 1328 status = "disabled";
1332 }; 1329 };
1333 1330
1334 i2c9: i2c@a8c000 { 1331 i2c9: i2c@a8c000 {
1335 compatible = 1332 compatible = "qcom,geni-i2c";
1336 reg = <0 0x00 1333 reg = <0 0x00a8c000 0 0x4000>;
1337 clock-names = 1334 clock-names = "se";
1338 clocks = <&gc 1335 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1339 pinctrl-names 1336 pinctrl-names = "default";
1340 pinctrl-0 = < 1337 pinctrl-0 = <&qup_i2c9_default>;
1341 interrupts = 1338 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1342 #address-cell 1339 #address-cells = <1>;
1343 #size-cells = 1340 #size-cells = <0>;
1344 interconnects 1341 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1345 1342 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1346 1343 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1347 interconnect- 1344 interconnect-names = "qup-core", "qup-config",
1348 1345 "qup-memory";
1349 power-domains 1346 power-domains = <&rpmhpd SC7180_CX>;
1350 required-opps 1347 required-opps = <&rpmhpd_opp_low_svs>;
1351 status = "dis 1348 status = "disabled";
1352 }; 1349 };
1353 1350
1354 uart9: serial@a8c000 1351 uart9: serial@a8c000 {
1355 compatible = 1352 compatible = "qcom,geni-uart";
1356 reg = <0 0x00 1353 reg = <0 0x00a8c000 0 0x4000>;
1357 clock-names = 1354 clock-names = "se";
1358 clocks = <&gc 1355 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1359 pinctrl-names 1356 pinctrl-names = "default";
1360 pinctrl-0 = < 1357 pinctrl-0 = <&qup_uart9_default>;
1361 interrupts = 1358 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1362 power-domains 1359 power-domains = <&rpmhpd SC7180_CX>;
1363 operating-poi 1360 operating-points-v2 = <&qup_opp_table>;
1364 interconnects 1361 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1365 1362 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1366 interconnect- 1363 interconnect-names = "qup-core", "qup-config";
1367 status = "dis 1364 status = "disabled";
1368 }; 1365 };
1369 1366
1370 i2c10: i2c@a90000 { 1367 i2c10: i2c@a90000 {
1371 compatible = 1368 compatible = "qcom,geni-i2c";
1372 reg = <0 0x00 1369 reg = <0 0x00a90000 0 0x4000>;
1373 clock-names = 1370 clock-names = "se";
1374 clocks = <&gc 1371 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1375 pinctrl-names 1372 pinctrl-names = "default";
1376 pinctrl-0 = < 1373 pinctrl-0 = <&qup_i2c10_default>;
1377 interrupts = 1374 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1378 #address-cell 1375 #address-cells = <1>;
1379 #size-cells = 1376 #size-cells = <0>;
1380 interconnects 1377 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1381 1378 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1382 1379 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1383 interconnect- 1380 interconnect-names = "qup-core", "qup-config",
1384 1381 "qup-memory";
1385 power-domains 1382 power-domains = <&rpmhpd SC7180_CX>;
1386 required-opps 1383 required-opps = <&rpmhpd_opp_low_svs>;
1387 status = "dis 1384 status = "disabled";
1388 }; 1385 };
1389 1386
1390 spi10: spi@a90000 { 1387 spi10: spi@a90000 {
1391 compatible = 1388 compatible = "qcom,geni-spi";
1392 reg = <0 0x00 1389 reg = <0 0x00a90000 0 0x4000>;
1393 clock-names = 1390 clock-names = "se";
1394 clocks = <&gc 1391 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1395 pinctrl-names 1392 pinctrl-names = "default";
1396 pinctrl-0 = < 1393 pinctrl-0 = <&qup_spi10_spi>, <&qup_spi10_cs>;
1397 interrupts = 1394 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1398 #address-cell 1395 #address-cells = <1>;
1399 #size-cells = 1396 #size-cells = <0>;
1400 power-domains 1397 power-domains = <&rpmhpd SC7180_CX>;
1401 operating-poi 1398 operating-points-v2 = <&qup_opp_table>;
1402 interconnects 1399 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1403 1400 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1404 interconnect- 1401 interconnect-names = "qup-core", "qup-config";
1405 status = "dis 1402 status = "disabled";
1406 }; 1403 };
1407 1404
1408 uart10: serial@a90000 1405 uart10: serial@a90000 {
1409 compatible = 1406 compatible = "qcom,geni-uart";
1410 reg = <0 0x00 1407 reg = <0 0x00a90000 0 0x4000>;
1411 clock-names = 1408 clock-names = "se";
1412 clocks = <&gc 1409 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1413 pinctrl-names 1410 pinctrl-names = "default";
1414 pinctrl-0 = < 1411 pinctrl-0 = <&qup_uart10_default>;
1415 interrupts = 1412 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1416 power-domains 1413 power-domains = <&rpmhpd SC7180_CX>;
1417 operating-poi 1414 operating-points-v2 = <&qup_opp_table>;
1418 interconnects 1415 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1419 1416 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1420 interconnect- 1417 interconnect-names = "qup-core", "qup-config";
1421 status = "dis 1418 status = "disabled";
1422 }; 1419 };
1423 1420
1424 i2c11: i2c@a94000 { 1421 i2c11: i2c@a94000 {
1425 compatible = 1422 compatible = "qcom,geni-i2c";
1426 reg = <0 0x00 1423 reg = <0 0x00a94000 0 0x4000>;
1427 clock-names = 1424 clock-names = "se";
1428 clocks = <&gc 1425 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1429 pinctrl-names 1426 pinctrl-names = "default";
1430 pinctrl-0 = < 1427 pinctrl-0 = <&qup_i2c11_default>;
1431 interrupts = 1428 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1432 #address-cell 1429 #address-cells = <1>;
1433 #size-cells = 1430 #size-cells = <0>;
1434 interconnects 1431 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1435 1432 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1436 1433 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1437 interconnect- 1434 interconnect-names = "qup-core", "qup-config",
1438 1435 "qup-memory";
1439 power-domains 1436 power-domains = <&rpmhpd SC7180_CX>;
1440 required-opps 1437 required-opps = <&rpmhpd_opp_low_svs>;
1441 status = "dis 1438 status = "disabled";
1442 }; 1439 };
1443 1440
1444 spi11: spi@a94000 { 1441 spi11: spi@a94000 {
1445 compatible = 1442 compatible = "qcom,geni-spi";
1446 reg = <0 0x00 1443 reg = <0 0x00a94000 0 0x4000>;
1447 clock-names = 1444 clock-names = "se";
1448 clocks = <&gc 1445 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1449 pinctrl-names 1446 pinctrl-names = "default";
1450 pinctrl-0 = < 1447 pinctrl-0 = <&qup_spi11_spi>, <&qup_spi11_cs>;
1451 interrupts = 1448 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1452 #address-cell 1449 #address-cells = <1>;
1453 #size-cells = 1450 #size-cells = <0>;
1454 power-domains 1451 power-domains = <&rpmhpd SC7180_CX>;
1455 operating-poi 1452 operating-points-v2 = <&qup_opp_table>;
1456 interconnects 1453 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1457 1454 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1458 interconnect- 1455 interconnect-names = "qup-core", "qup-config";
1459 status = "dis 1456 status = "disabled";
1460 }; 1457 };
1461 1458
1462 uart11: serial@a94000 1459 uart11: serial@a94000 {
1463 compatible = 1460 compatible = "qcom,geni-uart";
1464 reg = <0 0x00 1461 reg = <0 0x00a94000 0 0x4000>;
1465 clock-names = 1462 clock-names = "se";
1466 clocks = <&gc 1463 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1467 pinctrl-names 1464 pinctrl-names = "default";
1468 pinctrl-0 = < 1465 pinctrl-0 = <&qup_uart11_default>;
1469 interrupts = 1466 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1470 power-domains 1467 power-domains = <&rpmhpd SC7180_CX>;
1471 operating-poi 1468 operating-points-v2 = <&qup_opp_table>;
1472 interconnects 1469 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1473 1470 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1474 interconnect- 1471 interconnect-names = "qup-core", "qup-config";
1475 status = "dis 1472 status = "disabled";
1476 }; 1473 };
1477 }; 1474 };
1478 1475
1479 config_noc: interconnect@1500 1476 config_noc: interconnect@1500000 {
1480 compatible = "qcom,sc 1477 compatible = "qcom,sc7180-config-noc";
1481 reg = <0 0x01500000 0 1478 reg = <0 0x01500000 0 0x28000>;
1482 #interconnect-cells = 1479 #interconnect-cells = <2>;
1483 qcom,bcm-voters = <&a 1480 qcom,bcm-voters = <&apps_bcm_voter>;
1484 }; 1481 };
1485 1482
1486 system_noc: interconnect@1620 1483 system_noc: interconnect@1620000 {
1487 compatible = "qcom,sc 1484 compatible = "qcom,sc7180-system-noc";
1488 reg = <0 0x01620000 0 1485 reg = <0 0x01620000 0 0x17080>;
1489 #interconnect-cells = 1486 #interconnect-cells = <2>;
1490 qcom,bcm-voters = <&a 1487 qcom,bcm-voters = <&apps_bcm_voter>;
1491 }; 1488 };
1492 1489
1493 mc_virt: interconnect@1638000 1490 mc_virt: interconnect@1638000 {
1494 compatible = "qcom,sc 1491 compatible = "qcom,sc7180-mc-virt";
1495 reg = <0 0x01638000 0 1492 reg = <0 0x01638000 0 0x1000>;
1496 #interconnect-cells = 1493 #interconnect-cells = <2>;
1497 qcom,bcm-voters = <&a 1494 qcom,bcm-voters = <&apps_bcm_voter>;
1498 }; 1495 };
1499 1496
1500 qup_virt: interconnect@165000 1497 qup_virt: interconnect@1650000 {
1501 compatible = "qcom,sc 1498 compatible = "qcom,sc7180-qup-virt";
1502 reg = <0 0x01650000 0 1499 reg = <0 0x01650000 0 0x1000>;
1503 #interconnect-cells = 1500 #interconnect-cells = <2>;
1504 qcom,bcm-voters = <&a 1501 qcom,bcm-voters = <&apps_bcm_voter>;
1505 }; 1502 };
1506 1503
1507 aggre1_noc: interconnect@16e0 1504 aggre1_noc: interconnect@16e0000 {
1508 compatible = "qcom,sc 1505 compatible = "qcom,sc7180-aggre1-noc";
1509 reg = <0 0x016e0000 0 1506 reg = <0 0x016e0000 0 0x15080>;
1510 #interconnect-cells = 1507 #interconnect-cells = <2>;
1511 qcom,bcm-voters = <&a 1508 qcom,bcm-voters = <&apps_bcm_voter>;
1512 }; 1509 };
1513 1510
1514 aggre2_noc: interconnect@1705 1511 aggre2_noc: interconnect@1705000 {
1515 compatible = "qcom,sc 1512 compatible = "qcom,sc7180-aggre2-noc";
1516 reg = <0 0x01705000 0 1513 reg = <0 0x01705000 0 0x9000>;
1517 #interconnect-cells = 1514 #interconnect-cells = <2>;
1518 qcom,bcm-voters = <&a 1515 qcom,bcm-voters = <&apps_bcm_voter>;
1519 }; 1516 };
1520 1517
1521 compute_noc: interconnect@170 1518 compute_noc: interconnect@170e000 {
1522 compatible = "qcom,sc 1519 compatible = "qcom,sc7180-compute-noc";
1523 reg = <0 0x0170e000 0 1520 reg = <0 0x0170e000 0 0x6000>;
1524 #interconnect-cells = 1521 #interconnect-cells = <2>;
1525 qcom,bcm-voters = <&a 1522 qcom,bcm-voters = <&apps_bcm_voter>;
1526 }; 1523 };
1527 1524
1528 mmss_noc: interconnect@174000 1525 mmss_noc: interconnect@1740000 {
1529 compatible = "qcom,sc 1526 compatible = "qcom,sc7180-mmss-noc";
1530 reg = <0 0x01740000 0 1527 reg = <0 0x01740000 0 0x1c100>;
1531 #interconnect-cells = 1528 #interconnect-cells = <2>;
1532 qcom,bcm-voters = <&a 1529 qcom,bcm-voters = <&apps_bcm_voter>;
1533 }; 1530 };
1534 1531
1535 ufs_mem_hc: ufshc@1d84000 { <<
1536 compatible = "qcom,sc <<
1537 "jedec,u <<
1538 reg = <0 0x01d84000 0 <<
1539 interrupts = <GIC_SPI <<
1540 phys = <&ufs_mem_phy> <<
1541 phy-names = "ufsphy"; <<
1542 lanes-per-direction = <<
1543 #reset-cells = <1>; <<
1544 resets = <&gcc GCC_UF <<
1545 reset-names = "rst"; <<
1546 <<
1547 power-domains = <&gcc <<
1548 <<
1549 iommus = <&apps_smmu <<
1550 <<
1551 clock-names = "core_c <<
1552 "bus_ag <<
1553 "iface_ <<
1554 "core_c <<
1555 "ref_cl <<
1556 "tx_lan <<
1557 "rx_lan <<
1558 clocks = <&gcc GCC_UF <<
1559 <&gcc GCC_AG <<
1560 <&gcc GCC_UF <<
1561 <&gcc GCC_UF <<
1562 <&rpmhcc RPM <<
1563 <&gcc GCC_UF <<
1564 <&gcc GCC_UF <<
1565 freq-table-hz = <5000 <<
1566 <0 0> <<
1567 <0 0> <<
1568 <3750 <<
1569 <0 0> <<
1570 <0 0> <<
1571 <0 0> <<
1572 <<
1573 interconnects = <&agg <<
1574 &mc_ <<
1575 <&gem <<
1576 &con <<
1577 interconnect-names = <<
1578 <<
1579 qcom,ice = <&ice>; <<
1580 <<
1581 status = "disabled"; <<
1582 }; <<
1583 <<
1584 ufs_mem_phy: phy@1d87000 { <<
1585 compatible = "qcom,sc <<
1586 reg = <0 0x01d87000 0 <<
1587 clocks = <&rpmhcc RPM <<
1588 <&gcc GCC_UF <<
1589 <&gcc GCC_UF <<
1590 clock-names = "ref", <<
1591 "ref_au <<
1592 "qref"; <<
1593 power-domains = <&gcc <<
1594 resets = <&ufs_mem_hc <<
1595 reset-names = "ufsphy <<
1596 #phy-cells = <0>; <<
1597 status = "disabled"; <<
1598 }; <<
1599 <<
1600 ice: crypto@1d90000 { <<
1601 compatible = "qcom,sc <<
1602 "qcom,in <<
1603 reg = <0 0x01d90000 0 <<
1604 clocks = <&gcc GCC_UF <<
1605 }; <<
1606 <<
1607 ipa: ipa@1e40000 { 1532 ipa: ipa@1e40000 {
1608 compatible = "qcom,sc 1533 compatible = "qcom,sc7180-ipa";
1609 1534
1610 iommus = <&apps_smmu 1535 iommus = <&apps_smmu 0x440 0x0>,
1611 <&apps_smmu 1536 <&apps_smmu 0x442 0x0>;
1612 reg = <0 0x01e40000 0 1537 reg = <0 0x01e40000 0 0x7000>,
1613 <0 0x01e47000 0 1538 <0 0x01e47000 0 0x2000>,
1614 <0 0x01e04000 0 1539 <0 0x01e04000 0 0x2c000>;
1615 reg-names = "ipa-reg" 1540 reg-names = "ipa-reg",
1616 "ipa-shar 1541 "ipa-shared",
1617 "gsi"; 1542 "gsi";
1618 1543
1619 interrupts-extended = 1544 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
1620 1545 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
1621 1546 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1622 1547 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
1623 interrupt-names = "ip 1548 interrupt-names = "ipa",
1624 "gs 1549 "gsi",
1625 "ip 1550 "ipa-clock-query",
1626 "ip 1551 "ipa-setup-ready";
1627 1552
1628 clocks = <&rpmhcc RPM 1553 clocks = <&rpmhcc RPMH_IPA_CLK>;
1629 clock-names = "core"; 1554 clock-names = "core";
1630 1555
1631 interconnects = <&agg 1556 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
1632 <&agg 1557 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>,
1633 <&gem 1558 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
1634 interconnect-names = 1559 interconnect-names = "memory",
1635 1560 "imem",
1636 1561 "config";
1637 1562
1638 qcom,qmp = <&aoss_qmp 1563 qcom,qmp = <&aoss_qmp>;
1639 1564
1640 qcom,smem-states = <& 1565 qcom,smem-states = <&ipa_smp2p_out 0>,
1641 <& 1566 <&ipa_smp2p_out 1>;
1642 qcom,smem-state-names 1567 qcom,smem-state-names = "ipa-clock-enabled-valid",
1643 1568 "ipa-clock-enabled";
1644 1569
1645 status = "disabled"; 1570 status = "disabled";
1646 }; 1571 };
1647 1572
1648 tcsr_mutex: hwlock@1f40000 { 1573 tcsr_mutex: hwlock@1f40000 {
1649 compatible = "qcom,tc 1574 compatible = "qcom,tcsr-mutex";
1650 reg = <0 0x01f40000 0 1575 reg = <0 0x01f40000 0 0x20000>;
1651 #hwlock-cells = <1>; 1576 #hwlock-cells = <1>;
1652 }; 1577 };
1653 1578
1654 tcsr_regs_1: syscon@1f60000 { 1579 tcsr_regs_1: syscon@1f60000 {
1655 compatible = "qcom,sc 1580 compatible = "qcom,sc7180-tcsr", "syscon";
1656 reg = <0 0x01f60000 0 1581 reg = <0 0x01f60000 0 0x20000>;
1657 }; 1582 };
1658 1583
1659 tcsr_regs_2: syscon@1fc0000 { 1584 tcsr_regs_2: syscon@1fc0000 {
1660 compatible = "qcom,sc 1585 compatible = "qcom,sc7180-tcsr", "syscon";
1661 reg = <0 0x01fc0000 0 1586 reg = <0 0x01fc0000 0 0x40000>;
1662 }; 1587 };
1663 1588
1664 tlmm: pinctrl@3500000 { 1589 tlmm: pinctrl@3500000 {
1665 compatible = "qcom,sc 1590 compatible = "qcom,sc7180-pinctrl";
1666 reg = <0 0x03500000 0 1591 reg = <0 0x03500000 0 0x300000>,
1667 <0 0x03900000 0 1592 <0 0x03900000 0 0x300000>,
1668 <0 0x03d00000 0 1593 <0 0x03d00000 0 0x300000>;
1669 reg-names = "west", " 1594 reg-names = "west", "north", "south";
1670 interrupts = <GIC_SPI 1595 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1671 gpio-controller; 1596 gpio-controller;
1672 #gpio-cells = <2>; 1597 #gpio-cells = <2>;
1673 interrupt-controller; 1598 interrupt-controller;
1674 #interrupt-cells = <2 1599 #interrupt-cells = <2>;
1675 gpio-ranges = <&tlmm 1600 gpio-ranges = <&tlmm 0 0 120>;
1676 wakeup-parent = <&pdc 1601 wakeup-parent = <&pdc>;
1677 1602
1678 dp_hot_plug_det: dp-h 1603 dp_hot_plug_det: dp-hot-plug-det-state {
1679 pins = "gpio1 1604 pins = "gpio117";
1680 function = "d 1605 function = "dp_hot";
1681 }; 1606 };
1682 1607
1683 qspi_clk: qspi-clk-st 1608 qspi_clk: qspi-clk-state {
1684 pins = "gpio6 1609 pins = "gpio63";
1685 function = "q 1610 function = "qspi_clk";
1686 }; 1611 };
1687 1612
1688 qspi_cs0: qspi-cs0-st 1613 qspi_cs0: qspi-cs0-state {
1689 pins = "gpio6 1614 pins = "gpio68";
1690 function = "q 1615 function = "qspi_cs";
1691 }; 1616 };
1692 1617
1693 qspi_cs1: qspi-cs1-st 1618 qspi_cs1: qspi-cs1-state {
1694 pins = "gpio7 1619 pins = "gpio72";
1695 function = "q 1620 function = "qspi_cs";
1696 }; 1621 };
1697 1622
1698 qspi_data0: qspi-data 1623 qspi_data0: qspi-data0-state {
1699 pins = "gpio6 1624 pins = "gpio64";
1700 function = "q 1625 function = "qspi_data";
1701 }; 1626 };
1702 1627
1703 qspi_data1: qspi-data 1628 qspi_data1: qspi-data1-state {
1704 pins = "gpio6 1629 pins = "gpio65";
1705 function = "q 1630 function = "qspi_data";
1706 }; 1631 };
1707 1632
1708 qspi_data23: qspi-dat 1633 qspi_data23: qspi-data23-state {
1709 pins = "gpio6 1634 pins = "gpio66", "gpio67";
1710 function = "q 1635 function = "qspi_data";
1711 }; 1636 };
1712 1637
1713 qup_i2c0_default: qup 1638 qup_i2c0_default: qup-i2c0-default-state {
1714 pins = "gpio3 1639 pins = "gpio34", "gpio35";
1715 function = "q 1640 function = "qup00";
1716 }; 1641 };
1717 1642
1718 qup_i2c1_default: qup 1643 qup_i2c1_default: qup-i2c1-default-state {
1719 pins = "gpio0 1644 pins = "gpio0", "gpio1";
1720 function = "q 1645 function = "qup01";
1721 }; 1646 };
1722 1647
1723 qup_i2c2_default: qup 1648 qup_i2c2_default: qup-i2c2-default-state {
1724 pins = "gpio1 1649 pins = "gpio15", "gpio16";
1725 function = "q 1650 function = "qup02_i2c";
1726 }; 1651 };
1727 1652
1728 qup_i2c3_default: qup 1653 qup_i2c3_default: qup-i2c3-default-state {
1729 pins = "gpio3 1654 pins = "gpio38", "gpio39";
1730 function = "q 1655 function = "qup03";
1731 }; 1656 };
1732 1657
1733 qup_i2c4_default: qup 1658 qup_i2c4_default: qup-i2c4-default-state {
1734 pins = "gpio1 1659 pins = "gpio115", "gpio116";
1735 function = "q 1660 function = "qup04_i2c";
1736 }; 1661 };
1737 1662
1738 qup_i2c5_default: qup 1663 qup_i2c5_default: qup-i2c5-default-state {
1739 pins = "gpio2 1664 pins = "gpio25", "gpio26";
1740 function = "q 1665 function = "qup05";
1741 }; 1666 };
1742 1667
1743 qup_i2c6_default: qup 1668 qup_i2c6_default: qup-i2c6-default-state {
1744 pins = "gpio5 1669 pins = "gpio59", "gpio60";
1745 function = "q 1670 function = "qup10";
1746 }; 1671 };
1747 1672
1748 qup_i2c7_default: qup 1673 qup_i2c7_default: qup-i2c7-default-state {
1749 pins = "gpio6 1674 pins = "gpio6", "gpio7";
1750 function = "q 1675 function = "qup11_i2c";
1751 }; 1676 };
1752 1677
1753 qup_i2c8_default: qup 1678 qup_i2c8_default: qup-i2c8-default-state {
1754 pins = "gpio4 1679 pins = "gpio42", "gpio43";
1755 function = "q 1680 function = "qup12";
1756 }; 1681 };
1757 1682
1758 qup_i2c9_default: qup 1683 qup_i2c9_default: qup-i2c9-default-state {
1759 pins = "gpio4 1684 pins = "gpio46", "gpio47";
1760 function = "q 1685 function = "qup13_i2c";
1761 }; 1686 };
1762 1687
1763 qup_i2c10_default: qu 1688 qup_i2c10_default: qup-i2c10-default-state {
1764 pins = "gpio8 1689 pins = "gpio86", "gpio87";
1765 function = "q 1690 function = "qup14";
1766 }; 1691 };
1767 1692
1768 qup_i2c11_default: qu 1693 qup_i2c11_default: qup-i2c11-default-state {
1769 pins = "gpio5 1694 pins = "gpio53", "gpio54";
1770 function = "q 1695 function = "qup15";
1771 }; 1696 };
1772 1697
1773 qup_spi0_spi: qup-spi 1698 qup_spi0_spi: qup-spi0-spi-state {
1774 pins = "gpio3 1699 pins = "gpio34", "gpio35", "gpio36";
1775 function = "q 1700 function = "qup00";
1776 }; 1701 };
1777 1702
1778 qup_spi0_cs: qup-spi0 1703 qup_spi0_cs: qup-spi0-cs-state {
1779 pins = "gpio3 1704 pins = "gpio37";
1780 function = "q 1705 function = "qup00";
1781 }; 1706 };
1782 1707
1783 qup_spi0_cs_gpio: qup 1708 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state {
1784 pins = "gpio3 1709 pins = "gpio37";
1785 function = "g 1710 function = "gpio";
1786 }; 1711 };
1787 1712
1788 qup_spi1_spi: qup-spi 1713 qup_spi1_spi: qup-spi1-spi-state {
1789 pins = "gpio0 1714 pins = "gpio0", "gpio1", "gpio2";
1790 function = "q 1715 function = "qup01";
1791 }; 1716 };
1792 1717
1793 qup_spi1_cs: qup-spi1 1718 qup_spi1_cs: qup-spi1-cs-state {
1794 pins = "gpio3 1719 pins = "gpio3";
1795 function = "q 1720 function = "qup01";
1796 }; 1721 };
1797 1722
1798 qup_spi1_cs_gpio: qup 1723 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state {
1799 pins = "gpio3 1724 pins = "gpio3";
1800 function = "g 1725 function = "gpio";
1801 }; 1726 };
1802 1727
1803 qup_spi3_spi: qup-spi 1728 qup_spi3_spi: qup-spi3-spi-state {
1804 pins = "gpio3 1729 pins = "gpio38", "gpio39", "gpio40";
1805 function = "q 1730 function = "qup03";
1806 }; 1731 };
1807 1732
1808 qup_spi3_cs: qup-spi3 1733 qup_spi3_cs: qup-spi3-cs-state {
1809 pins = "gpio4 1734 pins = "gpio41";
1810 function = "q 1735 function = "qup03";
1811 }; 1736 };
1812 1737
1813 qup_spi3_cs_gpio: qup 1738 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state {
1814 pins = "gpio4 1739 pins = "gpio41";
1815 function = "g 1740 function = "gpio";
1816 }; 1741 };
1817 1742
1818 qup_spi5_spi: qup-spi 1743 qup_spi5_spi: qup-spi5-spi-state {
1819 pins = "gpio2 1744 pins = "gpio25", "gpio26", "gpio27";
1820 function = "q 1745 function = "qup05";
1821 }; 1746 };
1822 1747
1823 qup_spi5_cs: qup-spi5 1748 qup_spi5_cs: qup-spi5-cs-state {
1824 pins = "gpio2 1749 pins = "gpio28";
1825 function = "q 1750 function = "qup05";
1826 }; 1751 };
1827 1752
1828 qup_spi5_cs_gpio: qup 1753 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state {
1829 pins = "gpio2 1754 pins = "gpio28";
1830 function = "g 1755 function = "gpio";
1831 }; 1756 };
1832 1757
1833 qup_spi6_spi: qup-spi 1758 qup_spi6_spi: qup-spi6-spi-state {
1834 pins = "gpio5 1759 pins = "gpio59", "gpio60", "gpio61";
1835 function = "q 1760 function = "qup10";
1836 }; 1761 };
1837 1762
1838 qup_spi6_cs: qup-spi6 1763 qup_spi6_cs: qup-spi6-cs-state {
1839 pins = "gpio6 1764 pins = "gpio62";
1840 function = "q 1765 function = "qup10";
1841 }; 1766 };
1842 1767
1843 qup_spi6_cs_gpio: qup 1768 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state {
1844 pins = "gpio6 1769 pins = "gpio62";
1845 function = "g 1770 function = "gpio";
1846 }; 1771 };
1847 1772
1848 qup_spi8_spi: qup-spi 1773 qup_spi8_spi: qup-spi8-spi-state {
1849 pins = "gpio4 1774 pins = "gpio42", "gpio43", "gpio44";
1850 function = "q 1775 function = "qup12";
1851 }; 1776 };
1852 1777
1853 qup_spi8_cs: qup-spi8 1778 qup_spi8_cs: qup-spi8-cs-state {
1854 pins = "gpio4 1779 pins = "gpio45";
1855 function = "q 1780 function = "qup12";
1856 }; 1781 };
1857 1782
1858 qup_spi8_cs_gpio: qup 1783 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state {
1859 pins = "gpio4 1784 pins = "gpio45";
1860 function = "g 1785 function = "gpio";
1861 }; 1786 };
1862 1787
1863 qup_spi10_spi: qup-sp 1788 qup_spi10_spi: qup-spi10-spi-state {
1864 pins = "gpio8 1789 pins = "gpio86", "gpio87", "gpio88";
1865 function = "q 1790 function = "qup14";
1866 }; 1791 };
1867 1792
1868 qup_spi10_cs: qup-spi 1793 qup_spi10_cs: qup-spi10-cs-state {
1869 pins = "gpio8 1794 pins = "gpio89";
1870 function = "q 1795 function = "qup14";
1871 }; 1796 };
1872 1797
1873 qup_spi10_cs_gpio: qu 1798 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state {
1874 pins = "gpio8 1799 pins = "gpio89";
1875 function = "g 1800 function = "gpio";
1876 }; 1801 };
1877 1802
1878 qup_spi11_spi: qup-sp 1803 qup_spi11_spi: qup-spi11-spi-state {
1879 pins = "gpio5 1804 pins = "gpio53", "gpio54", "gpio55";
1880 function = "q 1805 function = "qup15";
1881 }; 1806 };
1882 1807
1883 qup_spi11_cs: qup-spi 1808 qup_spi11_cs: qup-spi11-cs-state {
1884 pins = "gpio5 1809 pins = "gpio56";
1885 function = "q 1810 function = "qup15";
1886 }; 1811 };
1887 1812
1888 qup_spi11_cs_gpio: qu 1813 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state {
1889 pins = "gpio5 1814 pins = "gpio56";
1890 function = "g 1815 function = "gpio";
1891 }; 1816 };
1892 1817
1893 qup_uart0_default: qu 1818 qup_uart0_default: qup-uart0-default-state {
1894 qup_uart0_cts 1819 qup_uart0_cts: cts-pins {
1895 pins 1820 pins = "gpio34";
1896 funct 1821 function = "qup00";
1897 }; 1822 };
1898 1823
1899 qup_uart0_rts 1824 qup_uart0_rts: rts-pins {
1900 pins 1825 pins = "gpio35";
1901 funct 1826 function = "qup00";
1902 }; 1827 };
1903 1828
1904 qup_uart0_tx: 1829 qup_uart0_tx: tx-pins {
1905 pins 1830 pins = "gpio36";
1906 funct 1831 function = "qup00";
1907 }; 1832 };
1908 1833
1909 qup_uart0_rx: 1834 qup_uart0_rx: rx-pins {
1910 pins 1835 pins = "gpio37";
1911 funct 1836 function = "qup00";
1912 }; 1837 };
1913 }; 1838 };
1914 1839
1915 qup_uart1_default: qu 1840 qup_uart1_default: qup-uart1-default-state {
1916 qup_uart1_cts 1841 qup_uart1_cts: cts-pins {
1917 pins 1842 pins = "gpio0";
1918 funct 1843 function = "qup01";
1919 }; 1844 };
1920 1845
1921 qup_uart1_rts 1846 qup_uart1_rts: rts-pins {
1922 pins 1847 pins = "gpio1";
1923 funct 1848 function = "qup01";
1924 }; 1849 };
1925 1850
1926 qup_uart1_tx: 1851 qup_uart1_tx: tx-pins {
1927 pins 1852 pins = "gpio2";
1928 funct 1853 function = "qup01";
1929 }; 1854 };
1930 1855
1931 qup_uart1_rx: 1856 qup_uart1_rx: rx-pins {
1932 pins 1857 pins = "gpio3";
1933 funct 1858 function = "qup01";
1934 }; 1859 };
1935 }; 1860 };
1936 1861
1937 qup_uart2_default: qu 1862 qup_uart2_default: qup-uart2-default-state {
1938 qup_uart2_tx: 1863 qup_uart2_tx: tx-pins {
1939 pins 1864 pins = "gpio15";
1940 funct 1865 function = "qup02_uart";
1941 }; 1866 };
1942 1867
1943 qup_uart2_rx: 1868 qup_uart2_rx: rx-pins {
1944 pins 1869 pins = "gpio16";
1945 funct 1870 function = "qup02_uart";
1946 }; 1871 };
1947 }; 1872 };
1948 1873
1949 qup_uart3_default: qu 1874 qup_uart3_default: qup-uart3-default-state {
1950 qup_uart3_cts 1875 qup_uart3_cts: cts-pins {
1951 pins 1876 pins = "gpio38";
1952 funct 1877 function = "qup03";
1953 }; 1878 };
1954 1879
1955 qup_uart3_rts 1880 qup_uart3_rts: rts-pins {
1956 pins 1881 pins = "gpio39";
1957 funct 1882 function = "qup03";
1958 }; 1883 };
1959 1884
1960 qup_uart3_tx: 1885 qup_uart3_tx: tx-pins {
1961 pins 1886 pins = "gpio40";
1962 funct 1887 function = "qup03";
1963 }; 1888 };
1964 1889
1965 qup_uart3_rx: 1890 qup_uart3_rx: rx-pins {
1966 pins 1891 pins = "gpio41";
1967 funct 1892 function = "qup03";
1968 }; 1893 };
1969 }; 1894 };
1970 1895
1971 qup_uart4_default: qu 1896 qup_uart4_default: qup-uart4-default-state {
1972 qup_uart4_tx: 1897 qup_uart4_tx: tx-pins {
1973 pins 1898 pins = "gpio115";
1974 funct 1899 function = "qup04_uart";
1975 }; 1900 };
1976 1901
1977 qup_uart4_rx: 1902 qup_uart4_rx: rx-pins {
1978 pins 1903 pins = "gpio116";
1979 funct 1904 function = "qup04_uart";
1980 }; 1905 };
1981 }; 1906 };
1982 1907
1983 qup_uart5_default: qu 1908 qup_uart5_default: qup-uart5-default-state {
1984 qup_uart5_cts 1909 qup_uart5_cts: cts-pins {
1985 pins 1910 pins = "gpio25";
1986 funct 1911 function = "qup05";
1987 }; 1912 };
1988 1913
1989 qup_uart5_rts 1914 qup_uart5_rts: rts-pins {
1990 pins 1915 pins = "gpio26";
1991 funct 1916 function = "qup05";
1992 }; 1917 };
1993 1918
1994 qup_uart5_tx: 1919 qup_uart5_tx: tx-pins {
1995 pins 1920 pins = "gpio27";
1996 funct 1921 function = "qup05";
1997 }; 1922 };
1998 1923
1999 qup_uart5_rx: 1924 qup_uart5_rx: rx-pins {
2000 pins 1925 pins = "gpio28";
2001 funct 1926 function = "qup05";
2002 }; 1927 };
2003 }; 1928 };
2004 1929
2005 qup_uart6_default: qu 1930 qup_uart6_default: qup-uart6-default-state {
2006 qup_uart6_cts 1931 qup_uart6_cts: cts-pins {
2007 pins 1932 pins = "gpio59";
2008 funct 1933 function = "qup10";
2009 }; 1934 };
2010 1935
2011 qup_uart6_rts 1936 qup_uart6_rts: rts-pins {
2012 pins 1937 pins = "gpio60";
2013 funct 1938 function = "qup10";
2014 }; 1939 };
2015 1940
2016 qup_uart6_tx: 1941 qup_uart6_tx: tx-pins {
2017 pins 1942 pins = "gpio61";
2018 funct 1943 function = "qup10";
2019 }; 1944 };
2020 1945
2021 qup_uart6_rx: 1946 qup_uart6_rx: rx-pins {
2022 pins 1947 pins = "gpio62";
2023 funct 1948 function = "qup10";
2024 }; 1949 };
2025 }; 1950 };
2026 1951
2027 qup_uart7_default: qu 1952 qup_uart7_default: qup-uart7-default-state {
2028 qup_uart7_tx: 1953 qup_uart7_tx: tx-pins {
2029 pins 1954 pins = "gpio6";
2030 funct 1955 function = "qup11_uart";
2031 }; 1956 };
2032 1957
2033 qup_uart7_rx: 1958 qup_uart7_rx: rx-pins {
2034 pins 1959 pins = "gpio7";
2035 funct 1960 function = "qup11_uart";
2036 }; 1961 };
2037 }; 1962 };
2038 1963
2039 qup_uart8_default: qu 1964 qup_uart8_default: qup-uart8-default-state {
2040 qup_uart8_tx: 1965 qup_uart8_tx: tx-pins {
2041 pins 1966 pins = "gpio44";
2042 funct 1967 function = "qup12";
2043 }; 1968 };
2044 1969
2045 qup_uart8_rx: 1970 qup_uart8_rx: rx-pins {
2046 pins 1971 pins = "gpio45";
2047 funct 1972 function = "qup12";
2048 }; 1973 };
2049 }; 1974 };
2050 1975
2051 qup_uart9_default: qu 1976 qup_uart9_default: qup-uart9-default-state {
2052 qup_uart9_tx: 1977 qup_uart9_tx: tx-pins {
2053 pins 1978 pins = "gpio46";
2054 funct 1979 function = "qup13_uart";
2055 }; 1980 };
2056 1981
2057 qup_uart9_rx: 1982 qup_uart9_rx: rx-pins {
2058 pins 1983 pins = "gpio47";
2059 funct 1984 function = "qup13_uart";
2060 }; 1985 };
2061 }; 1986 };
2062 1987
2063 qup_uart10_default: q 1988 qup_uart10_default: qup-uart10-default-state {
2064 qup_uart10_ct 1989 qup_uart10_cts: cts-pins {
2065 pins 1990 pins = "gpio86";
2066 funct 1991 function = "qup14";
2067 }; 1992 };
2068 1993
2069 qup_uart10_rt 1994 qup_uart10_rts: rts-pins {
2070 pins 1995 pins = "gpio87";
2071 funct 1996 function = "qup14";
2072 }; 1997 };
2073 1998
2074 qup_uart10_tx 1999 qup_uart10_tx: tx-pins {
2075 pins 2000 pins = "gpio88";
2076 funct 2001 function = "qup14";
2077 }; 2002 };
2078 2003
2079 qup_uart10_rx 2004 qup_uart10_rx: rx-pins {
2080 pins 2005 pins = "gpio89";
2081 funct 2006 function = "qup14";
2082 }; 2007 };
2083 }; 2008 };
2084 2009
2085 qup_uart11_default: q 2010 qup_uart11_default: qup-uart11-default-state {
2086 qup_uart11_ct 2011 qup_uart11_cts: cts-pins {
2087 pins 2012 pins = "gpio53";
2088 funct 2013 function = "qup15";
2089 }; 2014 };
2090 2015
2091 qup_uart11_rt 2016 qup_uart11_rts: rts-pins {
2092 pins 2017 pins = "gpio54";
2093 funct 2018 function = "qup15";
2094 }; 2019 };
2095 2020
2096 qup_uart11_tx 2021 qup_uart11_tx: tx-pins {
2097 pins 2022 pins = "gpio55";
2098 funct 2023 function = "qup15";
2099 }; 2024 };
2100 2025
2101 qup_uart11_rx 2026 qup_uart11_rx: rx-pins {
2102 pins 2027 pins = "gpio56";
2103 funct 2028 function = "qup15";
2104 }; 2029 };
2105 }; 2030 };
2106 2031
2107 sec_mi2s_active: sec- 2032 sec_mi2s_active: sec-mi2s-active-state {
2108 pins = "gpio4 2033 pins = "gpio49", "gpio50", "gpio51";
2109 function = "m 2034 function = "mi2s_1";
2110 }; 2035 };
2111 2036
2112 pri_mi2s_active: pri- 2037 pri_mi2s_active: pri-mi2s-active-state {
2113 pins = "gpio5 2038 pins = "gpio53", "gpio54", "gpio55", "gpio56";
2114 function = "m 2039 function = "mi2s_0";
2115 }; 2040 };
2116 2041
2117 pri_mi2s_mclk_active: 2042 pri_mi2s_mclk_active: pri-mi2s-mclk-active-state {
2118 pins = "gpio5 2043 pins = "gpio57";
2119 function = "l 2044 function = "lpass_ext";
2120 }; 2045 };
2121 <<
2122 ter_mi2s_active: ter- <<
2123 pins = "gpio6 <<
2124 function = "m <<
2125 }; <<
2126 }; 2046 };
2127 2047
2128 remoteproc_mpss: remoteproc@4 2048 remoteproc_mpss: remoteproc@4080000 {
2129 compatible = "qcom,sc 2049 compatible = "qcom,sc7180-mpss-pas";
2130 reg = <0 0x04080000 0 2050 reg = <0 0x04080000 0 0x4040>;
2131 2051
2132 interrupts-extended = 2052 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
2133 2053 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2134 2054 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2135 2055 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2136 2056 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
2137 2057 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
2138 interrupt-names = "wd 2058 interrupt-names = "wdog", "fatal", "ready", "handover",
2139 "st 2059 "stop-ack", "shutdown-ack";
2140 2060
2141 clocks = <&rpmhcc RPM 2061 clocks = <&rpmhcc RPMH_CXO_CLK>;
2142 clock-names = "xo"; 2062 clock-names = "xo";
2143 2063
2144 power-domains = <&rpm 2064 power-domains = <&rpmhpd SC7180_CX>,
2145 <&rpm 2065 <&rpmhpd SC7180_MX>,
2146 <&rpm 2066 <&rpmhpd SC7180_MSS>;
2147 power-domain-names = 2067 power-domain-names = "cx", "mx", "mss";
2148 2068
2149 memory-region = <&mps 2069 memory-region = <&mpss_mem>;
2150 2070
2151 qcom,qmp = <&aoss_qmp 2071 qcom,qmp = <&aoss_qmp>;
2152 2072
2153 qcom,smem-states = <& 2073 qcom,smem-states = <&modem_smp2p_out 0>;
2154 qcom,smem-state-names 2074 qcom,smem-state-names = "stop";
2155 2075
2156 status = "disabled"; 2076 status = "disabled";
2157 2077
2158 glink-edge { 2078 glink-edge {
2159 interrupts = 2079 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
2160 label = "mode 2080 label = "modem";
2161 qcom,remote-p 2081 qcom,remote-pid = <1>;
2162 mboxes = <&ap 2082 mboxes = <&apss_shared 12>;
2163 }; 2083 };
2164 }; 2084 };
2165 2085
2166 gpu: gpu@5000000 { 2086 gpu: gpu@5000000 {
2167 compatible = "qcom,ad 2087 compatible = "qcom,adreno-618.0", "qcom,adreno";
2168 reg = <0 0x05000000 0 2088 reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x1000>,
2169 <0 0x05061000 2089 <0 0x05061000 0 0x800>;
2170 reg-names = "kgsl_3d0 2090 reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc";
2171 interrupts = <GIC_SPI 2091 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2172 iommus = <&adreno_smm 2092 iommus = <&adreno_smmu 0>;
2173 operating-points-v2 = 2093 operating-points-v2 = <&gpu_opp_table>;
2174 qcom,gmu = <&gmu>; 2094 qcom,gmu = <&gmu>;
2175 2095
2176 #cooling-cells = <2>; 2096 #cooling-cells = <2>;
2177 2097
2178 nvmem-cells = <&gpu_s 2098 nvmem-cells = <&gpu_speed_bin>;
2179 nvmem-cell-names = "s 2099 nvmem-cell-names = "speed_bin";
2180 2100
2181 interconnects = <&gem 2101 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
2182 interconnect-names = 2102 interconnect-names = "gfx-mem";
2183 2103
2184 gpu_opp_table: opp-ta 2104 gpu_opp_table: opp-table {
2185 compatible = 2105 compatible = "operating-points-v2";
2186 2106
2187 opp-825000000 2107 opp-825000000 {
2188 opp-h 2108 opp-hz = /bits/ 64 <825000000>;
2189 opp-l 2109 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2190 opp-p 2110 opp-peak-kBps = <8532000>;
2191 opp-s 2111 opp-supported-hw = <0x04>;
2192 }; 2112 };
2193 2113
2194 opp-800000000 2114 opp-800000000 {
2195 opp-h 2115 opp-hz = /bits/ 64 <800000000>;
2196 opp-l 2116 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2197 opp-p 2117 opp-peak-kBps = <8532000>;
2198 opp-s 2118 opp-supported-hw = <0x07>;
2199 }; 2119 };
2200 2120
2201 opp-650000000 2121 opp-650000000 {
2202 opp-h 2122 opp-hz = /bits/ 64 <650000000>;
2203 opp-l 2123 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2204 opp-p 2124 opp-peak-kBps = <7216000>;
2205 opp-s 2125 opp-supported-hw = <0x07>;
2206 }; 2126 };
2207 2127
2208 opp-565000000 2128 opp-565000000 {
2209 opp-h 2129 opp-hz = /bits/ 64 <565000000>;
2210 opp-l 2130 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2211 opp-p 2131 opp-peak-kBps = <5412000>;
2212 opp-s 2132 opp-supported-hw = <0x07>;
2213 }; 2133 };
2214 2134
2215 opp-430000000 2135 opp-430000000 {
2216 opp-h 2136 opp-hz = /bits/ 64 <430000000>;
2217 opp-l 2137 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2218 opp-p 2138 opp-peak-kBps = <5412000>;
2219 opp-s 2139 opp-supported-hw = <0x07>;
2220 }; 2140 };
2221 2141
2222 opp-355000000 2142 opp-355000000 {
2223 opp-h 2143 opp-hz = /bits/ 64 <355000000>;
2224 opp-l 2144 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2225 opp-p 2145 opp-peak-kBps = <3072000>;
2226 opp-s 2146 opp-supported-hw = <0x07>;
2227 }; 2147 };
2228 2148
2229 opp-267000000 2149 opp-267000000 {
2230 opp-h 2150 opp-hz = /bits/ 64 <267000000>;
2231 opp-l 2151 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2232 opp-p 2152 opp-peak-kBps = <3072000>;
2233 opp-s 2153 opp-supported-hw = <0x07>;
2234 }; 2154 };
2235 2155
2236 opp-180000000 2156 opp-180000000 {
2237 opp-h 2157 opp-hz = /bits/ 64 <180000000>;
2238 opp-l 2158 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2239 opp-p 2159 opp-peak-kBps = <1804000>;
2240 opp-s 2160 opp-supported-hw = <0x07>;
2241 }; 2161 };
2242 }; 2162 };
2243 }; 2163 };
2244 2164
2245 adreno_smmu: iommu@5040000 { 2165 adreno_smmu: iommu@5040000 {
2246 compatible = "qcom,sc 2166 compatible = "qcom,sc7180-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
2247 reg = <0 0x05040000 0 2167 reg = <0 0x05040000 0 0x10000>;
2248 #iommu-cells = <1>; 2168 #iommu-cells = <1>;
2249 #global-interrupts = 2169 #global-interrupts = <2>;
2250 interrupts = <GIC_SPI 2170 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
2251 <GIC_ 2171 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
2252 <GIC_ 2172 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
2253 <GIC_ 2173 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
2254 <GIC_ 2174 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
2255 <GIC_ 2175 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
2256 <GIC_ 2176 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
2257 <GIC_ 2177 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
2258 <GIC_ 2178 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
2259 <GIC_ 2179 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
2260 2180
2261 clocks = <&gcc GCC_GP 2181 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2262 <&gcc GCC_GPU 2182 <&gcc GCC_GPU_CFG_AHB_CLK>;
2263 clock-names = "bus", 2183 clock-names = "bus", "iface";
2264 2184
2265 power-domains = <&gpu 2185 power-domains = <&gpucc CX_GDSC>;
2266 }; 2186 };
2267 2187
2268 gmu: gmu@506a000 { 2188 gmu: gmu@506a000 {
2269 compatible = "qcom,ad 2189 compatible = "qcom,adreno-gmu-618.0", "qcom,adreno-gmu";
2270 reg = <0 0x0506a000 0 2190 reg = <0 0x0506a000 0 0x31000>, <0 0x0b290000 0 0x10000>,
2271 <0 0x0b490000 2191 <0 0x0b490000 0 0x10000>;
2272 reg-names = "gmu", "g 2192 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
2273 interrupts = <GIC_SPI 2193 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2274 <GIC_SPI 3 2194 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2275 interrupt-names = "hf 2195 interrupt-names = "hfi", "gmu";
2276 clocks = <&gpucc GPU_ 2196 clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
2277 <&gpucc GPU_CC 2197 <&gpucc GPU_CC_CXO_CLK>,
2278 <&gcc GCC_DDRS 2198 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2279 <&gcc GCC_GPU_ 2199 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
2280 clock-names = "gmu", 2200 clock-names = "gmu", "cxo", "axi", "memnoc";
2281 power-domains = <&gpu 2201 power-domains = <&gpucc CX_GDSC>, <&gpucc GX_GDSC>;
2282 power-domain-names = 2202 power-domain-names = "cx", "gx";
2283 iommus = <&adreno_smm 2203 iommus = <&adreno_smmu 5>;
2284 operating-points-v2 = 2204 operating-points-v2 = <&gmu_opp_table>;
2285 2205
2286 gmu_opp_table: opp-ta 2206 gmu_opp_table: opp-table {
2287 compatible = 2207 compatible = "operating-points-v2";
2288 2208
2289 opp-200000000 2209 opp-200000000 {
2290 opp-h 2210 opp-hz = /bits/ 64 <200000000>;
2291 opp-l 2211 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2292 }; 2212 };
2293 }; 2213 };
2294 }; 2214 };
2295 2215
2296 gpucc: clock-controller@50900 2216 gpucc: clock-controller@5090000 {
2297 compatible = "qcom,sc 2217 compatible = "qcom,sc7180-gpucc";
2298 reg = <0 0x05090000 0 2218 reg = <0 0x05090000 0 0x9000>;
2299 clocks = <&rpmhcc RPM 2219 clocks = <&rpmhcc RPMH_CXO_CLK>,
2300 <&gcc GCC_GP 2220 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2301 <&gcc GCC_GP 2221 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2302 clock-names = "bi_tcx 2222 clock-names = "bi_tcxo",
2303 "gcc_gp 2223 "gcc_gpu_gpll0_clk_src",
2304 "gcc_gp 2224 "gcc_gpu_gpll0_div_clk_src";
2305 #clock-cells = <1>; 2225 #clock-cells = <1>;
2306 #reset-cells = <1>; 2226 #reset-cells = <1>;
2307 #power-domain-cells = 2227 #power-domain-cells = <1>;
2308 }; 2228 };
2309 2229
2310 dma@10a2000 { 2230 dma@10a2000 {
2311 compatible = "qcom,sc 2231 compatible = "qcom,sc7180-dcc", "qcom,dcc";
2312 reg = <0x0 0x010a2000 2232 reg = <0x0 0x010a2000 0x0 0x1000>,
2313 <0x0 0x010ae000 2233 <0x0 0x010ae000 0x0 0x2000>;
2314 status = "disabled"; <<
2315 }; 2234 };
2316 2235
2317 stm@6002000 { 2236 stm@6002000 {
2318 compatible = "arm,cor 2237 compatible = "arm,coresight-stm", "arm,primecell";
2319 reg = <0 0x06002000 0 2238 reg = <0 0x06002000 0 0x1000>,
2320 <0 0x16280000 0 2239 <0 0x16280000 0 0x180000>;
2321 reg-names = "stm-base 2240 reg-names = "stm-base", "stm-stimulus-base";
2322 2241
2323 clocks = <&aoss_qmp>; 2242 clocks = <&aoss_qmp>;
2324 clock-names = "apb_pc 2243 clock-names = "apb_pclk";
2325 2244
2326 out-ports { 2245 out-ports {
2327 port { 2246 port {
2328 stm_o 2247 stm_out: endpoint {
2329 2248 remote-endpoint = <&funnel0_in7>;
2330 }; 2249 };
2331 }; 2250 };
2332 }; 2251 };
2333 }; 2252 };
2334 2253
2335 funnel@6041000 { 2254 funnel@6041000 {
2336 compatible = "arm,cor 2255 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2337 reg = <0 0x06041000 0 2256 reg = <0 0x06041000 0 0x1000>;
2338 2257
2339 clocks = <&aoss_qmp>; 2258 clocks = <&aoss_qmp>;
2340 clock-names = "apb_pc 2259 clock-names = "apb_pclk";
2341 2260
2342 out-ports { 2261 out-ports {
2343 port { 2262 port {
2344 funne 2263 funnel0_out: endpoint {
2345 2264 remote-endpoint = <&merge_funnel_in0>;
2346 }; 2265 };
2347 }; 2266 };
2348 }; 2267 };
2349 2268
2350 in-ports { 2269 in-ports {
2351 #address-cell 2270 #address-cells = <1>;
2352 #size-cells = 2271 #size-cells = <0>;
2353 2272
2354 port@7 { 2273 port@7 {
2355 reg = 2274 reg = <7>;
2356 funne 2275 funnel0_in7: endpoint {
2357 2276 remote-endpoint = <&stm_out>;
2358 }; 2277 };
2359 }; 2278 };
2360 }; 2279 };
2361 }; 2280 };
2362 2281
2363 funnel@6042000 { 2282 funnel@6042000 {
2364 compatible = "arm,cor 2283 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2365 reg = <0 0x06042000 0 2284 reg = <0 0x06042000 0 0x1000>;
2366 2285
2367 clocks = <&aoss_qmp>; 2286 clocks = <&aoss_qmp>;
2368 clock-names = "apb_pc 2287 clock-names = "apb_pclk";
2369 2288
2370 out-ports { 2289 out-ports {
2371 port { 2290 port {
2372 funne 2291 funnel1_out: endpoint {
2373 2292 remote-endpoint = <&merge_funnel_in1>;
2374 }; 2293 };
2375 }; 2294 };
2376 }; 2295 };
2377 2296
2378 in-ports { 2297 in-ports {
2379 #address-cell 2298 #address-cells = <1>;
2380 #size-cells = 2299 #size-cells = <0>;
2381 2300
2382 port@4 { 2301 port@4 {
2383 reg = 2302 reg = <4>;
2384 funne 2303 funnel1_in4: endpoint {
2385 2304 remote-endpoint = <&apss_merge_funnel_out>;
2386 }; 2305 };
2387 }; 2306 };
2388 }; 2307 };
2389 }; 2308 };
2390 2309
2391 funnel@6045000 { 2310 funnel@6045000 {
2392 compatible = "arm,cor 2311 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2393 reg = <0 0x06045000 0 2312 reg = <0 0x06045000 0 0x1000>;
2394 2313
2395 clocks = <&aoss_qmp>; 2314 clocks = <&aoss_qmp>;
2396 clock-names = "apb_pc 2315 clock-names = "apb_pclk";
2397 2316
2398 out-ports { 2317 out-ports {
2399 port { 2318 port {
2400 merge 2319 merge_funnel_out: endpoint {
2401 2320 remote-endpoint = <&swao_funnel_in>;
2402 }; 2321 };
2403 }; 2322 };
2404 }; 2323 };
2405 2324
2406 in-ports { 2325 in-ports {
2407 #address-cell 2326 #address-cells = <1>;
2408 #size-cells = 2327 #size-cells = <0>;
2409 2328
2410 port@0 { 2329 port@0 {
2411 reg = 2330 reg = <0>;
2412 merge 2331 merge_funnel_in0: endpoint {
2413 2332 remote-endpoint = <&funnel0_out>;
2414 }; 2333 };
2415 }; 2334 };
2416 2335
2417 port@1 { 2336 port@1 {
2418 reg = 2337 reg = <1>;
2419 merge 2338 merge_funnel_in1: endpoint {
2420 2339 remote-endpoint = <&funnel1_out>;
2421 }; 2340 };
2422 }; 2341 };
2423 }; 2342 };
2424 }; 2343 };
2425 2344
2426 replicator@6046000 { 2345 replicator@6046000 {
2427 compatible = "arm,cor 2346 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2428 reg = <0 0x06046000 0 2347 reg = <0 0x06046000 0 0x1000>;
2429 2348
2430 clocks = <&aoss_qmp>; 2349 clocks = <&aoss_qmp>;
2431 clock-names = "apb_pc 2350 clock-names = "apb_pclk";
2432 2351
2433 out-ports { 2352 out-ports {
2434 port { 2353 port {
2435 repli 2354 replicator_out: endpoint {
2436 2355 remote-endpoint = <&etr_in>;
2437 }; 2356 };
2438 }; 2357 };
2439 }; 2358 };
2440 2359
2441 in-ports { 2360 in-ports {
2442 port { 2361 port {
2443 repli 2362 replicator_in: endpoint {
2444 2363 remote-endpoint = <&swao_replicator_out>;
2445 }; 2364 };
2446 }; 2365 };
2447 }; 2366 };
2448 }; 2367 };
2449 2368
2450 etr@6048000 { 2369 etr@6048000 {
2451 compatible = "arm,cor 2370 compatible = "arm,coresight-tmc", "arm,primecell";
2452 reg = <0 0x06048000 0 2371 reg = <0 0x06048000 0 0x1000>;
2453 iommus = <&apps_smmu 2372 iommus = <&apps_smmu 0x04a0 0x20>;
2454 2373
2455 clocks = <&aoss_qmp>; 2374 clocks = <&aoss_qmp>;
2456 clock-names = "apb_pc 2375 clock-names = "apb_pclk";
2457 arm,scatter-gather; 2376 arm,scatter-gather;
2458 2377
2459 in-ports { 2378 in-ports {
2460 port { 2379 port {
2461 etr_i 2380 etr_in: endpoint {
2462 2381 remote-endpoint = <&replicator_out>;
2463 }; 2382 };
2464 }; 2383 };
2465 }; 2384 };
2466 }; 2385 };
2467 2386
2468 funnel@6b04000 { 2387 funnel@6b04000 {
2469 compatible = "arm,cor 2388 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2470 reg = <0 0x06b04000 0 2389 reg = <0 0x06b04000 0 0x1000>;
2471 2390
2472 clocks = <&aoss_qmp>; 2391 clocks = <&aoss_qmp>;
2473 clock-names = "apb_pc 2392 clock-names = "apb_pclk";
2474 2393
2475 out-ports { 2394 out-ports {
2476 port { 2395 port {
2477 swao_ 2396 swao_funnel_out: endpoint {
2478 2397 remote-endpoint = <&etf_in>;
2479 }; 2398 };
2480 }; 2399 };
2481 }; 2400 };
2482 2401
2483 in-ports { 2402 in-ports {
2484 #address-cell 2403 #address-cells = <1>;
2485 #size-cells = 2404 #size-cells = <0>;
2486 2405
2487 port@7 { 2406 port@7 {
2488 reg = 2407 reg = <7>;
2489 swao_ 2408 swao_funnel_in: endpoint {
2490 2409 remote-endpoint = <&merge_funnel_out>;
2491 }; 2410 };
2492 }; 2411 };
2493 }; 2412 };
2494 }; 2413 };
2495 2414
2496 etf@6b05000 { 2415 etf@6b05000 {
2497 compatible = "arm,cor 2416 compatible = "arm,coresight-tmc", "arm,primecell";
2498 reg = <0 0x06b05000 0 2417 reg = <0 0x06b05000 0 0x1000>;
2499 2418
2500 clocks = <&aoss_qmp>; 2419 clocks = <&aoss_qmp>;
2501 clock-names = "apb_pc 2420 clock-names = "apb_pclk";
2502 2421
2503 out-ports { 2422 out-ports {
2504 port { 2423 port {
2505 etf_o 2424 etf_out: endpoint {
2506 2425 remote-endpoint = <&swao_replicator_in>;
2507 }; 2426 };
2508 }; 2427 };
2509 }; 2428 };
2510 2429
2511 in-ports { 2430 in-ports {
2512 port { 2431 port {
2513 etf_i 2432 etf_in: endpoint {
2514 2433 remote-endpoint = <&swao_funnel_out>;
2515 }; 2434 };
2516 }; 2435 };
2517 }; 2436 };
2518 }; 2437 };
2519 2438
2520 replicator@6b06000 { 2439 replicator@6b06000 {
2521 compatible = "arm,cor 2440 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2522 reg = <0 0x06b06000 0 2441 reg = <0 0x06b06000 0 0x1000>;
2523 2442
2524 clocks = <&aoss_qmp>; 2443 clocks = <&aoss_qmp>;
2525 clock-names = "apb_pc 2444 clock-names = "apb_pclk";
2526 qcom,replicator-loses 2445 qcom,replicator-loses-context;
2527 2446
2528 out-ports { 2447 out-ports {
2529 port { 2448 port {
2530 swao_ 2449 swao_replicator_out: endpoint {
2531 2450 remote-endpoint = <&replicator_in>;
2532 }; 2451 };
2533 }; 2452 };
2534 }; 2453 };
2535 2454
2536 in-ports { 2455 in-ports {
2537 port { 2456 port {
2538 swao_ 2457 swao_replicator_in: endpoint {
2539 2458 remote-endpoint = <&etf_out>;
2540 }; 2459 };
2541 }; 2460 };
2542 }; 2461 };
2543 }; 2462 };
2544 2463
2545 etm@7040000 { 2464 etm@7040000 {
2546 compatible = "arm,cor 2465 compatible = "arm,coresight-etm4x", "arm,primecell";
2547 reg = <0 0x07040000 0 2466 reg = <0 0x07040000 0 0x1000>;
2548 2467
2549 cpu = <&CPU0>; 2468 cpu = <&CPU0>;
2550 2469
2551 clocks = <&aoss_qmp>; 2470 clocks = <&aoss_qmp>;
2552 clock-names = "apb_pc 2471 clock-names = "apb_pclk";
2553 arm,coresight-loses-c 2472 arm,coresight-loses-context-with-cpu;
2554 qcom,skip-power-up; 2473 qcom,skip-power-up;
2555 2474
2556 out-ports { 2475 out-ports {
2557 port { 2476 port {
2558 etm0_ 2477 etm0_out: endpoint {
2559 2478 remote-endpoint = <&apss_funnel_in0>;
2560 }; 2479 };
2561 }; 2480 };
2562 }; 2481 };
2563 }; 2482 };
2564 2483
2565 etm@7140000 { 2484 etm@7140000 {
2566 compatible = "arm,cor 2485 compatible = "arm,coresight-etm4x", "arm,primecell";
2567 reg = <0 0x07140000 0 2486 reg = <0 0x07140000 0 0x1000>;
2568 2487
2569 cpu = <&CPU1>; 2488 cpu = <&CPU1>;
2570 2489
2571 clocks = <&aoss_qmp>; 2490 clocks = <&aoss_qmp>;
2572 clock-names = "apb_pc 2491 clock-names = "apb_pclk";
2573 arm,coresight-loses-c 2492 arm,coresight-loses-context-with-cpu;
2574 qcom,skip-power-up; 2493 qcom,skip-power-up;
2575 2494
2576 out-ports { 2495 out-ports {
2577 port { 2496 port {
2578 etm1_ 2497 etm1_out: endpoint {
2579 2498 remote-endpoint = <&apss_funnel_in1>;
2580 }; 2499 };
2581 }; 2500 };
2582 }; 2501 };
2583 }; 2502 };
2584 2503
2585 etm@7240000 { 2504 etm@7240000 {
2586 compatible = "arm,cor 2505 compatible = "arm,coresight-etm4x", "arm,primecell";
2587 reg = <0 0x07240000 0 2506 reg = <0 0x07240000 0 0x1000>;
2588 2507
2589 cpu = <&CPU2>; 2508 cpu = <&CPU2>;
2590 2509
2591 clocks = <&aoss_qmp>; 2510 clocks = <&aoss_qmp>;
2592 clock-names = "apb_pc 2511 clock-names = "apb_pclk";
2593 arm,coresight-loses-c 2512 arm,coresight-loses-context-with-cpu;
2594 qcom,skip-power-up; 2513 qcom,skip-power-up;
2595 2514
2596 out-ports { 2515 out-ports {
2597 port { 2516 port {
2598 etm2_ 2517 etm2_out: endpoint {
2599 2518 remote-endpoint = <&apss_funnel_in2>;
2600 }; 2519 };
2601 }; 2520 };
2602 }; 2521 };
2603 }; 2522 };
2604 2523
2605 etm@7340000 { 2524 etm@7340000 {
2606 compatible = "arm,cor 2525 compatible = "arm,coresight-etm4x", "arm,primecell";
2607 reg = <0 0x07340000 0 2526 reg = <0 0x07340000 0 0x1000>;
2608 2527
2609 cpu = <&CPU3>; 2528 cpu = <&CPU3>;
2610 2529
2611 clocks = <&aoss_qmp>; 2530 clocks = <&aoss_qmp>;
2612 clock-names = "apb_pc 2531 clock-names = "apb_pclk";
2613 arm,coresight-loses-c 2532 arm,coresight-loses-context-with-cpu;
2614 qcom,skip-power-up; 2533 qcom,skip-power-up;
2615 2534
2616 out-ports { 2535 out-ports {
2617 port { 2536 port {
2618 etm3_ 2537 etm3_out: endpoint {
2619 2538 remote-endpoint = <&apss_funnel_in3>;
2620 }; 2539 };
2621 }; 2540 };
2622 }; 2541 };
2623 }; 2542 };
2624 2543
2625 etm@7440000 { 2544 etm@7440000 {
2626 compatible = "arm,cor 2545 compatible = "arm,coresight-etm4x", "arm,primecell";
2627 reg = <0 0x07440000 0 2546 reg = <0 0x07440000 0 0x1000>;
2628 2547
2629 cpu = <&CPU4>; 2548 cpu = <&CPU4>;
2630 2549
2631 clocks = <&aoss_qmp>; 2550 clocks = <&aoss_qmp>;
2632 clock-names = "apb_pc 2551 clock-names = "apb_pclk";
2633 arm,coresight-loses-c 2552 arm,coresight-loses-context-with-cpu;
2634 qcom,skip-power-up; 2553 qcom,skip-power-up;
2635 2554
2636 out-ports { 2555 out-ports {
2637 port { 2556 port {
2638 etm4_ 2557 etm4_out: endpoint {
2639 2558 remote-endpoint = <&apss_funnel_in4>;
2640 }; 2559 };
2641 }; 2560 };
2642 }; 2561 };
2643 }; 2562 };
2644 2563
2645 etm@7540000 { 2564 etm@7540000 {
2646 compatible = "arm,cor 2565 compatible = "arm,coresight-etm4x", "arm,primecell";
2647 reg = <0 0x07540000 0 2566 reg = <0 0x07540000 0 0x1000>;
2648 2567
2649 cpu = <&CPU5>; 2568 cpu = <&CPU5>;
2650 2569
2651 clocks = <&aoss_qmp>; 2570 clocks = <&aoss_qmp>;
2652 clock-names = "apb_pc 2571 clock-names = "apb_pclk";
2653 arm,coresight-loses-c 2572 arm,coresight-loses-context-with-cpu;
2654 qcom,skip-power-up; 2573 qcom,skip-power-up;
2655 2574
2656 out-ports { 2575 out-ports {
2657 port { 2576 port {
2658 etm5_ 2577 etm5_out: endpoint {
2659 2578 remote-endpoint = <&apss_funnel_in5>;
2660 }; 2579 };
2661 }; 2580 };
2662 }; 2581 };
2663 }; 2582 };
2664 2583
2665 etm@7640000 { 2584 etm@7640000 {
2666 compatible = "arm,cor 2585 compatible = "arm,coresight-etm4x", "arm,primecell";
2667 reg = <0 0x07640000 0 2586 reg = <0 0x07640000 0 0x1000>;
2668 2587
2669 cpu = <&CPU6>; 2588 cpu = <&CPU6>;
2670 2589
2671 clocks = <&aoss_qmp>; 2590 clocks = <&aoss_qmp>;
2672 clock-names = "apb_pc 2591 clock-names = "apb_pclk";
2673 arm,coresight-loses-c 2592 arm,coresight-loses-context-with-cpu;
2674 qcom,skip-power-up; 2593 qcom,skip-power-up;
2675 2594
2676 out-ports { 2595 out-ports {
2677 port { 2596 port {
2678 etm6_ 2597 etm6_out: endpoint {
2679 2598 remote-endpoint = <&apss_funnel_in6>;
2680 }; 2599 };
2681 }; 2600 };
2682 }; 2601 };
2683 }; 2602 };
2684 2603
2685 etm@7740000 { 2604 etm@7740000 {
2686 compatible = "arm,cor 2605 compatible = "arm,coresight-etm4x", "arm,primecell";
2687 reg = <0 0x07740000 0 2606 reg = <0 0x07740000 0 0x1000>;
2688 2607
2689 cpu = <&CPU7>; 2608 cpu = <&CPU7>;
2690 2609
2691 clocks = <&aoss_qmp>; 2610 clocks = <&aoss_qmp>;
2692 clock-names = "apb_pc 2611 clock-names = "apb_pclk";
2693 arm,coresight-loses-c 2612 arm,coresight-loses-context-with-cpu;
2694 qcom,skip-power-up; 2613 qcom,skip-power-up;
2695 2614
2696 out-ports { 2615 out-ports {
2697 port { 2616 port {
2698 etm7_ 2617 etm7_out: endpoint {
2699 2618 remote-endpoint = <&apss_funnel_in7>;
2700 }; 2619 };
2701 }; 2620 };
2702 }; 2621 };
2703 }; 2622 };
2704 2623
2705 funnel@7800000 { /* APSS Funn 2624 funnel@7800000 { /* APSS Funnel */
2706 compatible = "arm,cor 2625 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2707 reg = <0 0x07800000 0 2626 reg = <0 0x07800000 0 0x1000>;
2708 2627
2709 clocks = <&aoss_qmp>; 2628 clocks = <&aoss_qmp>;
2710 clock-names = "apb_pc 2629 clock-names = "apb_pclk";
2711 2630
2712 out-ports { 2631 out-ports {
2713 port { 2632 port {
2714 apss_ 2633 apss_funnel_out: endpoint {
2715 2634 remote-endpoint = <&apss_merge_funnel_in>;
2716 }; 2635 };
2717 }; 2636 };
2718 }; 2637 };
2719 2638
2720 in-ports { 2639 in-ports {
2721 #address-cell 2640 #address-cells = <1>;
2722 #size-cells = 2641 #size-cells = <0>;
2723 2642
2724 port@0 { 2643 port@0 {
2725 reg = 2644 reg = <0>;
2726 apss_ 2645 apss_funnel_in0: endpoint {
2727 2646 remote-endpoint = <&etm0_out>;
2728 }; 2647 };
2729 }; 2648 };
2730 2649
2731 port@1 { 2650 port@1 {
2732 reg = 2651 reg = <1>;
2733 apss_ 2652 apss_funnel_in1: endpoint {
2734 2653 remote-endpoint = <&etm1_out>;
2735 }; 2654 };
2736 }; 2655 };
2737 2656
2738 port@2 { 2657 port@2 {
2739 reg = 2658 reg = <2>;
2740 apss_ 2659 apss_funnel_in2: endpoint {
2741 2660 remote-endpoint = <&etm2_out>;
2742 }; 2661 };
2743 }; 2662 };
2744 2663
2745 port@3 { 2664 port@3 {
2746 reg = 2665 reg = <3>;
2747 apss_ 2666 apss_funnel_in3: endpoint {
2748 2667 remote-endpoint = <&etm3_out>;
2749 }; 2668 };
2750 }; 2669 };
2751 2670
2752 port@4 { 2671 port@4 {
2753 reg = 2672 reg = <4>;
2754 apss_ 2673 apss_funnel_in4: endpoint {
2755 2674 remote-endpoint = <&etm4_out>;
2756 }; 2675 };
2757 }; 2676 };
2758 2677
2759 port@5 { 2678 port@5 {
2760 reg = 2679 reg = <5>;
2761 apss_ 2680 apss_funnel_in5: endpoint {
2762 2681 remote-endpoint = <&etm5_out>;
2763 }; 2682 };
2764 }; 2683 };
2765 2684
2766 port@6 { 2685 port@6 {
2767 reg = 2686 reg = <6>;
2768 apss_ 2687 apss_funnel_in6: endpoint {
2769 2688 remote-endpoint = <&etm6_out>;
2770 }; 2689 };
2771 }; 2690 };
2772 2691
2773 port@7 { 2692 port@7 {
2774 reg = 2693 reg = <7>;
2775 apss_ 2694 apss_funnel_in7: endpoint {
2776 2695 remote-endpoint = <&etm7_out>;
2777 }; 2696 };
2778 }; 2697 };
2779 }; 2698 };
2780 }; 2699 };
2781 2700
2782 funnel@7810000 { 2701 funnel@7810000 {
2783 compatible = "arm,cor 2702 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2784 reg = <0 0x07810000 0 2703 reg = <0 0x07810000 0 0x1000>;
2785 2704
2786 clocks = <&aoss_qmp>; 2705 clocks = <&aoss_qmp>;
2787 clock-names = "apb_pc 2706 clock-names = "apb_pclk";
2788 2707
2789 out-ports { 2708 out-ports {
2790 port { 2709 port {
2791 apss_ 2710 apss_merge_funnel_out: endpoint {
2792 2711 remote-endpoint = <&funnel1_in4>;
2793 }; 2712 };
2794 }; 2713 };
2795 }; 2714 };
2796 2715
2797 in-ports { 2716 in-ports {
2798 port { 2717 port {
2799 apss_ 2718 apss_merge_funnel_in: endpoint {
2800 2719 remote-endpoint = <&apss_funnel_out>;
2801 }; 2720 };
2802 }; 2721 };
2803 }; 2722 };
2804 }; 2723 };
2805 2724
2806 sdhc_2: mmc@8804000 { 2725 sdhc_2: mmc@8804000 {
2807 compatible = "qcom,sc 2726 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
2808 reg = <0 0x08804000 0 2727 reg = <0 0x08804000 0 0x1000>;
2809 2728
2810 iommus = <&apps_smmu 2729 iommus = <&apps_smmu 0x80 0>;
2811 interrupts = <GIC_SPI 2730 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
2812 <GIC_ 2731 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
2813 interrupt-names = "hc 2732 interrupt-names = "hc_irq", "pwr_irq";
2814 2733
2815 clocks = <&gcc GCC_SD 2734 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2816 <&gcc GCC_SD 2735 <&gcc GCC_SDCC2_APPS_CLK>,
2817 <&rpmhcc RPM 2736 <&rpmhcc RPMH_CXO_CLK>;
2818 clock-names = "iface" 2737 clock-names = "iface", "core", "xo";
2819 2738
2820 interconnects = <&agg 2739 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
2821 <&gem 2740 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
2822 interconnect-names = 2741 interconnect-names = "sdhc-ddr","cpu-sdhc";
2823 power-domains = <&rpm 2742 power-domains = <&rpmhpd SC7180_CX>;
2824 operating-points-v2 = 2743 operating-points-v2 = <&sdhc2_opp_table>;
2825 2744
2826 bus-width = <4>; 2745 bus-width = <4>;
2827 2746
2828 status = "disabled"; 2747 status = "disabled";
2829 2748
2830 sdhc2_opp_table: opp- 2749 sdhc2_opp_table: opp-table {
2831 compatible = 2750 compatible = "operating-points-v2";
2832 2751
2833 opp-100000000 2752 opp-100000000 {
2834 opp-h 2753 opp-hz = /bits/ 64 <100000000>;
2835 requi 2754 required-opps = <&rpmhpd_opp_low_svs>;
2836 opp-p 2755 opp-peak-kBps = <1800000 600000>;
2837 opp-a 2756 opp-avg-kBps = <100000 0>;
2838 }; 2757 };
2839 2758
2840 opp-202000000 2759 opp-202000000 {
2841 opp-h 2760 opp-hz = /bits/ 64 <202000000>;
2842 requi 2761 required-opps = <&rpmhpd_opp_nom>;
2843 opp-p 2762 opp-peak-kBps = <5400000 1600000>;
2844 opp-a 2763 opp-avg-kBps = <200000 0>;
2845 }; 2764 };
2846 }; 2765 };
2847 }; 2766 };
2848 2767
2849 qspi: spi@88dc000 { 2768 qspi: spi@88dc000 {
2850 compatible = "qcom,sc 2769 compatible = "qcom,sc7180-qspi", "qcom,qspi-v1";
2851 reg = <0 0x088dc000 0 2770 reg = <0 0x088dc000 0 0x600>;
2852 iommus = <&apps_smmu 2771 iommus = <&apps_smmu 0x20 0x0>;
2853 #address-cells = <1>; 2772 #address-cells = <1>;
2854 #size-cells = <0>; 2773 #size-cells = <0>;
2855 interrupts = <GIC_SPI 2774 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
2856 clocks = <&gcc GCC_QS 2775 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
2857 <&gcc GCC_QS 2776 <&gcc GCC_QSPI_CORE_CLK>;
2858 clock-names = "iface" 2777 clock-names = "iface", "core";
2859 interconnects = <&gem 2778 interconnects = <&gem_noc MASTER_APPSS_PROC 0
2860 &conf 2779 &config_noc SLAVE_QSPI_0 0>;
2861 interconnect-names = 2780 interconnect-names = "qspi-config";
2862 power-domains = <&rpm 2781 power-domains = <&rpmhpd SC7180_CX>;
2863 operating-points-v2 = 2782 operating-points-v2 = <&qspi_opp_table>;
2864 status = "disabled"; 2783 status = "disabled";
2865 }; 2784 };
2866 2785
2867 usb_1_hsphy: phy@88e3000 { 2786 usb_1_hsphy: phy@88e3000 {
2868 compatible = "qcom,sc 2787 compatible = "qcom,sc7180-qusb2-phy", "qcom,qusb2-v2-phy";
2869 reg = <0 0x088e3000 0 2788 reg = <0 0x088e3000 0 0x400>;
2870 status = "disabled"; 2789 status = "disabled";
2871 #phy-cells = <0>; 2790 #phy-cells = <0>;
2872 clocks = <&gcc GCC_US 2791 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2873 <&rpmhcc RPM 2792 <&rpmhcc RPMH_CXO_CLK>;
2874 clock-names = "cfg_ah 2793 clock-names = "cfg_ahb", "ref";
2875 resets = <&gcc GCC_QU 2794 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2876 2795
2877 nvmem-cells = <&qusb2 2796 nvmem-cells = <&qusb2p_hstx_trim>;
2878 }; 2797 };
2879 2798
2880 usb_1_qmpphy: phy@88e8000 { 2799 usb_1_qmpphy: phy@88e8000 {
2881 compatible = "qcom,sc 2800 compatible = "qcom,sc7180-qmp-usb3-dp-phy";
2882 reg = <0 0x088e8000 0 2801 reg = <0 0x088e8000 0 0x3000>;
2883 status = "disabled"; 2802 status = "disabled";
2884 2803
2885 clocks = <&gcc GCC_US 2804 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2886 <&gcc GCC_US 2805 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
2887 <&gcc GCC_US 2806 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
2888 <&gcc GCC_US 2807 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
2889 <&gcc GCC_US 2808 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
2890 clock-names = "aux", 2809 clock-names = "aux",
2891 "ref", 2810 "ref",
2892 "com_au 2811 "com_aux",
2893 "usb3_p 2812 "usb3_pipe",
2894 "cfg_ah 2813 "cfg_ahb";
2895 2814
2896 resets = <&gcc GCC_US 2815 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
2897 <&gcc GCC_US 2816 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
2898 reset-names = "phy", 2817 reset-names = "phy", "common";
2899 2818
2900 #clock-cells = <1>; 2819 #clock-cells = <1>;
2901 #phy-cells = <1>; 2820 #phy-cells = <1>;
2902 }; 2821 };
2903 2822
2904 pmu@90b6300 { 2823 pmu@90b6300 {
2905 compatible = "qcom,sc 2824 compatible = "qcom,sc7180-cpu-bwmon", "qcom,sdm845-bwmon";
2906 reg = <0 0x090b6300 0 2825 reg = <0 0x090b6300 0 0x600>;
2907 interrupts = <GIC_SPI 2826 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
2908 2827
2909 interconnects = <&gem 2828 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
2910 &gem 2829 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>;
2911 operating-points-v2 = 2830 operating-points-v2 = <&cpu_bwmon_opp_table>;
2912 2831
2913 cpu_bwmon_opp_table: 2832 cpu_bwmon_opp_table: opp-table {
2914 compatible = 2833 compatible = "operating-points-v2";
2915 2834
2916 opp-0 { 2835 opp-0 {
2917 opp-p 2836 opp-peak-kBps = <2288000>;
2918 }; 2837 };
2919 2838
2920 opp-1 { 2839 opp-1 {
2921 opp-p 2840 opp-peak-kBps = <4577000>;
2922 }; 2841 };
2923 2842
2924 opp-2 { 2843 opp-2 {
2925 opp-p 2844 opp-peak-kBps = <7110000>;
2926 }; 2845 };
2927 2846
2928 opp-3 { 2847 opp-3 {
2929 opp-p 2848 opp-peak-kBps = <9155000>;
2930 }; 2849 };
2931 2850
2932 opp-4 { 2851 opp-4 {
2933 opp-p 2852 opp-peak-kBps = <12298000>;
2934 }; 2853 };
2935 2854
2936 opp-5 { 2855 opp-5 {
2937 opp-p 2856 opp-peak-kBps = <14236000>;
2938 }; 2857 };
2939 }; 2858 };
2940 }; 2859 };
2941 2860
2942 pmu@90cd000 { 2861 pmu@90cd000 {
2943 compatible = "qcom,sc 2862 compatible = "qcom,sc7180-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
2944 reg = <0 0x090cd000 0 2863 reg = <0 0x090cd000 0 0x1000>;
2945 interrupts = <GIC_SPI 2864 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
2946 2865
2947 interconnects = <&mc_ 2866 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
2948 &mc_ 2867 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>;
2949 operating-points-v2 = 2868 operating-points-v2 = <&llcc_bwmon_opp_table>;
2950 2869
2951 llcc_bwmon_opp_table: 2870 llcc_bwmon_opp_table: opp-table {
2952 compatible = 2871 compatible = "operating-points-v2";
2953 2872
2954 opp-0 { 2873 opp-0 {
2955 opp-p 2874 opp-peak-kBps = <1144000>;
2956 }; 2875 };
2957 2876
2958 opp-1 { 2877 opp-1 {
2959 opp-p 2878 opp-peak-kBps = <1720000>;
2960 }; 2879 };
2961 2880
2962 opp-2 { 2881 opp-2 {
2963 opp-p 2882 opp-peak-kBps = <2086000>;
2964 }; 2883 };
2965 2884
2966 opp-3 { 2885 opp-3 {
2967 opp-p 2886 opp-peak-kBps = <2929000>;
2968 }; 2887 };
2969 2888
2970 opp-4 { 2889 opp-4 {
2971 opp-p 2890 opp-peak-kBps = <3879000>;
2972 }; 2891 };
2973 2892
2974 opp-5 { 2893 opp-5 {
2975 opp-p 2894 opp-peak-kBps = <5931000>;
2976 }; 2895 };
2977 2896
2978 opp-6 { 2897 opp-6 {
2979 opp-p 2898 opp-peak-kBps = <6881000>;
2980 }; 2899 };
2981 2900
2982 opp-7 { 2901 opp-7 {
2983 opp-p 2902 opp-peak-kBps = <8137000>;
2984 }; 2903 };
2985 }; 2904 };
2986 }; 2905 };
2987 2906
2988 dc_noc: interconnect@9160000 2907 dc_noc: interconnect@9160000 {
2989 compatible = "qcom,sc 2908 compatible = "qcom,sc7180-dc-noc";
2990 reg = <0 0x09160000 0 2909 reg = <0 0x09160000 0 0x03200>;
2991 #interconnect-cells = 2910 #interconnect-cells = <2>;
2992 qcom,bcm-voters = <&a 2911 qcom,bcm-voters = <&apps_bcm_voter>;
2993 }; 2912 };
2994 2913
2995 system-cache-controller@92000 2914 system-cache-controller@9200000 {
2996 compatible = "qcom,sc 2915 compatible = "qcom,sc7180-llcc";
2997 reg = <0 0x09200000 0 2916 reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>;
2998 reg-names = "llcc0_ba 2917 reg-names = "llcc0_base", "llcc_broadcast_base";
2999 interrupts = <GIC_SPI 2918 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
3000 }; 2919 };
3001 2920
3002 gem_noc: interconnect@9680000 2921 gem_noc: interconnect@9680000 {
3003 compatible = "qcom,sc 2922 compatible = "qcom,sc7180-gem-noc";
3004 reg = <0 0x09680000 0 2923 reg = <0 0x09680000 0 0x3e200>;
3005 #interconnect-cells = 2924 #interconnect-cells = <2>;
3006 qcom,bcm-voters = <&a 2925 qcom,bcm-voters = <&apps_bcm_voter>;
3007 }; 2926 };
3008 2927
3009 npu_noc: interconnect@9990000 2928 npu_noc: interconnect@9990000 {
3010 compatible = "qcom,sc 2929 compatible = "qcom,sc7180-npu-noc";
3011 reg = <0 0x09990000 0 2930 reg = <0 0x09990000 0 0x1600>;
3012 #interconnect-cells = 2931 #interconnect-cells = <2>;
3013 qcom,bcm-voters = <&a 2932 qcom,bcm-voters = <&apps_bcm_voter>;
3014 }; 2933 };
3015 2934
3016 usb_1: usb@a6f8800 { 2935 usb_1: usb@a6f8800 {
3017 compatible = "qcom,sc 2936 compatible = "qcom,sc7180-dwc3", "qcom,dwc3";
3018 reg = <0 0x0a6f8800 0 2937 reg = <0 0x0a6f8800 0 0x400>;
3019 status = "disabled"; 2938 status = "disabled";
3020 #address-cells = <2>; 2939 #address-cells = <2>;
3021 #size-cells = <2>; 2940 #size-cells = <2>;
3022 ranges; 2941 ranges;
3023 dma-ranges; 2942 dma-ranges;
3024 2943
3025 clocks = <&gcc GCC_CF 2944 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
3026 <&gcc GCC_US 2945 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
3027 <&gcc GCC_AG 2946 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
3028 <&gcc GCC_US 2947 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
3029 <&gcc GCC_US 2948 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
3030 clock-names = "cfg_no 2949 clock-names = "cfg_noc",
3031 "core", 2950 "core",
3032 "iface" 2951 "iface",
3033 "sleep" 2952 "sleep",
3034 "mock_u 2953 "mock_utmi";
3035 2954
3036 assigned-clocks = <&g 2955 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3037 <&g 2956 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
3038 assigned-clock-rates 2957 assigned-clock-rates = <19200000>, <150000000>;
3039 2958
3040 interrupts-extended = !! 2959 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
3041 !! 2960 <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
3042 <<
3043 2961 <&pdc 8 IRQ_TYPE_EDGE_BOTH>,
3044 !! 2962 <&pdc 9 IRQ_TYPE_EDGE_BOTH>;
3045 interrupt-names = "pw !! 2963 interrupt-names = "hs_phy_irq", "ss_phy_irq",
3046 "hs !! 2964 "dm_hs_phy_irq", "dp_hs_phy_irq";
3047 "dp <<
3048 "dm <<
3049 "ss <<
3050 2965
3051 power-domains = <&gcc 2966 power-domains = <&gcc USB30_PRIM_GDSC>;
3052 required-opps = <&rpm 2967 required-opps = <&rpmhpd_opp_nom>;
3053 2968
3054 resets = <&gcc GCC_US 2969 resets = <&gcc GCC_USB30_PRIM_BCR>;
3055 2970
3056 interconnects = <&agg 2971 interconnects = <&aggre2_noc MASTER_USB3 0 &mc_virt SLAVE_EBI1 0>,
3057 <&gem 2972 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3 0>;
3058 interconnect-names = 2973 interconnect-names = "usb-ddr", "apps-usb";
3059 2974
3060 wakeup-source; 2975 wakeup-source;
3061 2976
3062 usb_1_dwc3: usb@a6000 2977 usb_1_dwc3: usb@a600000 {
3063 compatible = 2978 compatible = "snps,dwc3";
3064 reg = <0 0x0a 2979 reg = <0 0x0a600000 0 0xe000>;
3065 interrupts = 2980 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
3066 iommus = <&ap 2981 iommus = <&apps_smmu 0x540 0>;
3067 snps,dis_u2_s 2982 snps,dis_u2_susphy_quirk;
3068 snps,dis_enbl 2983 snps,dis_enblslpm_quirk;
3069 snps,parkmode 2984 snps,parkmode-disable-ss-quirk;
3070 phys = <&usb_ 2985 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
3071 phy-names = " 2986 phy-names = "usb2-phy", "usb3-phy";
3072 maximum-speed 2987 maximum-speed = "super-speed";
3073 }; 2988 };
3074 }; 2989 };
3075 2990
3076 venus: video-codec@aa00000 { 2991 venus: video-codec@aa00000 {
3077 compatible = "qcom,sc 2992 compatible = "qcom,sc7180-venus";
3078 reg = <0 0x0aa00000 0 2993 reg = <0 0x0aa00000 0 0xff000>;
3079 interrupts = <GIC_SPI 2994 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
3080 power-domains = <&vid 2995 power-domains = <&videocc VENUS_GDSC>,
3081 <&vid 2996 <&videocc VCODEC0_GDSC>,
3082 <&rpm 2997 <&rpmhpd SC7180_CX>;
3083 power-domain-names = 2998 power-domain-names = "venus", "vcodec0", "cx";
3084 operating-points-v2 = 2999 operating-points-v2 = <&venus_opp_table>;
3085 clocks = <&videocc VI 3000 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
3086 <&videocc VI 3001 <&videocc VIDEO_CC_VENUS_AHB_CLK>,
3087 <&videocc VI 3002 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>,
3088 <&videocc VI 3003 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
3089 <&videocc VI 3004 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>;
3090 clock-names = "core", 3005 clock-names = "core", "iface", "bus",
3091 "vcodec 3006 "vcodec0_core", "vcodec0_bus";
3092 iommus = <&apps_smmu 3007 iommus = <&apps_smmu 0x0c00 0x60>;
3093 memory-region = <&ven 3008 memory-region = <&venus_mem>;
3094 interconnects = <&mms 3009 interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>,
3095 <&gem 3010 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>;
3096 interconnect-names = 3011 interconnect-names = "video-mem", "cpu-cfg";
3097 3012
3098 video-decoder { 3013 video-decoder {
3099 compatible = 3014 compatible = "venus-decoder";
3100 }; 3015 };
3101 3016
3102 video-encoder { 3017 video-encoder {
3103 compatible = 3018 compatible = "venus-encoder";
3104 }; 3019 };
3105 3020
3106 venus_opp_table: opp- 3021 venus_opp_table: opp-table {
3107 compatible = 3022 compatible = "operating-points-v2";
3108 3023
3109 opp-150000000 3024 opp-150000000 {
3110 opp-h 3025 opp-hz = /bits/ 64 <150000000>;
3111 requi 3026 required-opps = <&rpmhpd_opp_low_svs>;
3112 }; 3027 };
3113 3028
3114 opp-270000000 3029 opp-270000000 {
3115 opp-h 3030 opp-hz = /bits/ 64 <270000000>;
3116 requi 3031 required-opps = <&rpmhpd_opp_svs>;
3117 }; 3032 };
3118 3033
3119 opp-340000000 3034 opp-340000000 {
3120 opp-h 3035 opp-hz = /bits/ 64 <340000000>;
3121 requi 3036 required-opps = <&rpmhpd_opp_svs_l1>;
3122 }; 3037 };
3123 3038
3124 opp-434000000 3039 opp-434000000 {
3125 opp-h 3040 opp-hz = /bits/ 64 <434000000>;
3126 requi 3041 required-opps = <&rpmhpd_opp_nom>;
3127 }; 3042 };
3128 3043
3129 opp-500000097 3044 opp-500000097 {
3130 opp-h 3045 opp-hz = /bits/ 64 <500000097>;
3131 requi 3046 required-opps = <&rpmhpd_opp_turbo>;
3132 }; 3047 };
3133 }; 3048 };
3134 }; 3049 };
3135 3050
3136 videocc: clock-controller@ab0 3051 videocc: clock-controller@ab00000 {
3137 compatible = "qcom,sc 3052 compatible = "qcom,sc7180-videocc";
3138 reg = <0 0x0ab00000 0 3053 reg = <0 0x0ab00000 0 0x10000>;
3139 clocks = <&rpmhcc RPM 3054 clocks = <&rpmhcc RPMH_CXO_CLK>;
3140 clock-names = "bi_tcx 3055 clock-names = "bi_tcxo";
3141 #clock-cells = <1>; 3056 #clock-cells = <1>;
3142 #reset-cells = <1>; 3057 #reset-cells = <1>;
3143 #power-domain-cells = 3058 #power-domain-cells = <1>;
3144 }; 3059 };
3145 3060
3146 camnoc_virt: interconnect@ac0 3061 camnoc_virt: interconnect@ac00000 {
3147 compatible = "qcom,sc 3062 compatible = "qcom,sc7180-camnoc-virt";
3148 reg = <0 0x0ac00000 0 3063 reg = <0 0x0ac00000 0 0x1000>;
3149 #interconnect-cells = 3064 #interconnect-cells = <2>;
3150 qcom,bcm-voters = <&a 3065 qcom,bcm-voters = <&apps_bcm_voter>;
3151 }; 3066 };
3152 3067
3153 camcc: clock-controller@ad000 3068 camcc: clock-controller@ad00000 {
3154 compatible = "qcom,sc 3069 compatible = "qcom,sc7180-camcc";
3155 reg = <0 0x0ad00000 0 3070 reg = <0 0x0ad00000 0 0x10000>;
3156 clocks = <&rpmhcc RPM 3071 clocks = <&rpmhcc RPMH_CXO_CLK>,
3157 <&gcc GCC_CAME 3072 <&gcc GCC_CAMERA_AHB_CLK>,
3158 <&gcc GCC_CAME 3073 <&gcc GCC_CAMERA_XO_CLK>;
3159 clock-names = "bi_tcx 3074 clock-names = "bi_tcxo", "iface", "xo";
3160 #clock-cells = <1>; 3075 #clock-cells = <1>;
3161 #reset-cells = <1>; 3076 #reset-cells = <1>;
3162 #power-domain-cells = 3077 #power-domain-cells = <1>;
3163 }; 3078 };
3164 3079
3165 mdss: display-subsystem@ae000 3080 mdss: display-subsystem@ae00000 {
3166 compatible = "qcom,sc 3081 compatible = "qcom,sc7180-mdss";
3167 reg = <0 0x0ae00000 0 3082 reg = <0 0x0ae00000 0 0x1000>;
3168 reg-names = "mdss"; 3083 reg-names = "mdss";
3169 3084
3170 power-domains = <&dis 3085 power-domains = <&dispcc MDSS_GDSC>;
3171 3086
3172 clocks = <&gcc GCC_DI 3087 clocks = <&gcc GCC_DISP_AHB_CLK>,
3173 <&dispcc DIS 3088 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3174 <&dispcc DIS 3089 <&dispcc DISP_CC_MDSS_MDP_CLK>;
3175 clock-names = "iface" 3090 clock-names = "iface", "ahb", "core";
3176 3091
3177 interrupts = <GIC_SPI 3092 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
3178 interrupt-controller; 3093 interrupt-controller;
3179 #interrupt-cells = <1 3094 #interrupt-cells = <1>;
3180 3095
3181 interconnects = <&mms !! 3096 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>;
3182 &mc_ !! 3097 interconnect-names = "mdp0-mem";
3183 <&gem <<
3184 &con <<
3185 interconnect-names = <<
3186 <<
3187 3098
3188 iommus = <&apps_smmu 3099 iommus = <&apps_smmu 0x800 0x2>;
3189 3100
3190 #address-cells = <2>; 3101 #address-cells = <2>;
3191 #size-cells = <2>; 3102 #size-cells = <2>;
3192 ranges; 3103 ranges;
3193 3104
3194 status = "disabled"; 3105 status = "disabled";
3195 3106
3196 mdp: display-controll 3107 mdp: display-controller@ae01000 {
3197 compatible = 3108 compatible = "qcom,sc7180-dpu";
3198 reg = <0 0x0a 3109 reg = <0 0x0ae01000 0 0x8f000>,
3199 <0 0x0a 3110 <0 0x0aeb0000 0 0x2008>;
3200 reg-names = " 3111 reg-names = "mdp", "vbif";
3201 3112
3202 clocks = <&gc 3113 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
3203 <&di 3114 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3204 <&di 3115 <&dispcc DISP_CC_MDSS_ROT_CLK>,
3205 <&di 3116 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
3206 <&di 3117 <&dispcc DISP_CC_MDSS_MDP_CLK>,
3207 <&di 3118 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3208 clock-names = 3119 clock-names = "bus", "iface", "rot", "lut", "core",
3209 3120 "vsync";
3210 assigned-cloc 3121 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
3211 3122 <&dispcc DISP_CC_MDSS_ROT_CLK>,
3212 3123 <&dispcc DISP_CC_MDSS_AHB_CLK>;
3213 assigned-cloc 3124 assigned-clock-rates = <19200000>,
3214 3125 <19200000>,
3215 3126 <19200000>;
3216 operating-poi 3127 operating-points-v2 = <&mdp_opp_table>;
3217 power-domains 3128 power-domains = <&rpmhpd SC7180_CX>;
3218 3129
3219 interrupt-par 3130 interrupt-parent = <&mdss>;
3220 interrupts = 3131 interrupts = <0>;
3221 3132
3222 ports { 3133 ports {
3223 #addr 3134 #address-cells = <1>;
3224 #size 3135 #size-cells = <0>;
3225 3136
3226 port@ 3137 port@0 {
3227 3138 reg = <0>;
3228 3139 dpu_intf1_out: endpoint {
3229 3140 remote-endpoint = <&mdss_dsi0_in>;
3230 3141 };
3231 }; 3142 };
3232 3143
3233 port@ 3144 port@2 {
3234 3145 reg = <2>;
3235 3146 dpu_intf0_out: endpoint {
3236 3147 remote-endpoint = <&dp_in>;
3237 3148 };
3238 }; 3149 };
3239 }; 3150 };
3240 3151
3241 mdp_opp_table 3152 mdp_opp_table: opp-table {
3242 compa 3153 compatible = "operating-points-v2";
3243 3154
3244 opp-2 3155 opp-200000000 {
3245 3156 opp-hz = /bits/ 64 <200000000>;
3246 3157 required-opps = <&rpmhpd_opp_low_svs>;
3247 }; 3158 };
3248 3159
3249 opp-3 3160 opp-300000000 {
3250 3161 opp-hz = /bits/ 64 <300000000>;
3251 3162 required-opps = <&rpmhpd_opp_svs>;
3252 }; 3163 };
3253 3164
3254 opp-3 3165 opp-345000000 {
3255 3166 opp-hz = /bits/ 64 <345000000>;
3256 3167 required-opps = <&rpmhpd_opp_svs_l1>;
3257 }; 3168 };
3258 3169
3259 opp-4 3170 opp-460000000 {
3260 3171 opp-hz = /bits/ 64 <460000000>;
3261 3172 required-opps = <&rpmhpd_opp_nom>;
3262 }; 3173 };
3263 }; 3174 };
3264 }; 3175 };
3265 3176
3266 mdss_dsi0: dsi@ae9400 3177 mdss_dsi0: dsi@ae94000 {
3267 compatible = 3178 compatible = "qcom,sc7180-dsi-ctrl",
3268 3179 "qcom,mdss-dsi-ctrl";
3269 reg = <0 0x0a 3180 reg = <0 0x0ae94000 0 0x400>;
3270 reg-names = " 3181 reg-names = "dsi_ctrl";
3271 3182
3272 interrupt-par 3183 interrupt-parent = <&mdss>;
3273 interrupts = 3184 interrupts = <4>;
3274 3185
3275 clocks = <&di 3186 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
3276 <&di 3187 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
3277 <&di 3188 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
3278 <&di 3189 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
3279 <&di 3190 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3280 <&gc 3191 <&gcc GCC_DISP_HF_AXI_CLK>;
3281 clock-names = 3192 clock-names = "byte",
3282 3193 "byte_intf",
3283 3194 "pixel",
3284 3195 "core",
3285 3196 "iface",
3286 3197 "bus";
3287 3198
3288 assigned-cloc 3199 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
3289 assigned-cloc 3200 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
3290 3201
3291 operating-poi 3202 operating-points-v2 = <&dsi_opp_table>;
3292 power-domains 3203 power-domains = <&rpmhpd SC7180_CX>;
3293 3204
3294 phys = <&mdss 3205 phys = <&mdss_dsi0_phy>;
3295 3206
3296 #address-cell 3207 #address-cells = <1>;
3297 #size-cells = 3208 #size-cells = <0>;
3298 3209
3299 status = "dis 3210 status = "disabled";
3300 3211
3301 ports { 3212 ports {
3302 #addr 3213 #address-cells = <1>;
3303 #size 3214 #size-cells = <0>;
3304 3215
3305 port@ 3216 port@0 {
3306 3217 reg = <0>;
3307 3218 mdss_dsi0_in: endpoint {
3308 3219 remote-endpoint = <&dpu_intf1_out>;
3309 3220 };
3310 }; 3221 };
3311 3222
3312 port@ 3223 port@1 {
3313 3224 reg = <1>;
3314 3225 mdss_dsi0_out: endpoint {
3315 3226 };
3316 }; 3227 };
3317 }; 3228 };
3318 3229
3319 dsi_opp_table 3230 dsi_opp_table: opp-table {
3320 compa 3231 compatible = "operating-points-v2";
3321 3232
3322 opp-1 3233 opp-187500000 {
3323 3234 opp-hz = /bits/ 64 <187500000>;
3324 3235 required-opps = <&rpmhpd_opp_low_svs>;
3325 }; 3236 };
3326 3237
3327 opp-3 3238 opp-300000000 {
3328 3239 opp-hz = /bits/ 64 <300000000>;
3329 3240 required-opps = <&rpmhpd_opp_svs>;
3330 }; 3241 };
3331 3242
3332 opp-3 3243 opp-358000000 {
3333 3244 opp-hz = /bits/ 64 <358000000>;
3334 3245 required-opps = <&rpmhpd_opp_svs_l1>;
3335 }; 3246 };
3336 }; 3247 };
3337 }; 3248 };
3338 3249
3339 mdss_dsi0_phy: phy@ae 3250 mdss_dsi0_phy: phy@ae94400 {
3340 compatible = 3251 compatible = "qcom,dsi-phy-10nm";
3341 reg = <0 0x0a 3252 reg = <0 0x0ae94400 0 0x200>,
3342 <0 0x0a 3253 <0 0x0ae94600 0 0x280>,
3343 <0 0x0a 3254 <0 0x0ae94a00 0 0x1e0>;
3344 reg-names = " 3255 reg-names = "dsi_phy",
3345 " 3256 "dsi_phy_lane",
3346 " 3257 "dsi_pll";
3347 3258
3348 #clock-cells 3259 #clock-cells = <1>;
3349 #phy-cells = 3260 #phy-cells = <0>;
3350 3261
3351 clocks = <&di 3262 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3352 <&rp 3263 <&rpmhcc RPMH_CXO_CLK>;
3353 clock-names = 3264 clock-names = "iface", "ref";
3354 3265
3355 status = "dis 3266 status = "disabled";
3356 }; 3267 };
3357 3268
3358 mdss_dp: displayport- 3269 mdss_dp: displayport-controller@ae90000 {
3359 compatible = 3270 compatible = "qcom,sc7180-dp";
3360 status = "dis 3271 status = "disabled";
3361 3272
3362 reg = <0 0x0a 3273 reg = <0 0x0ae90000 0 0x200>,
3363 <0 0x0a 3274 <0 0x0ae90200 0 0x200>,
3364 <0 0x0a 3275 <0 0x0ae90400 0 0xc00>,
3365 <0 0x0a 3276 <0 0x0ae91000 0 0x400>,
3366 <0 0x0a 3277 <0 0x0ae91400 0 0x400>;
3367 3278
3368 interrupt-par 3279 interrupt-parent = <&mdss>;
3369 interrupts = 3280 interrupts = <12>;
3370 3281
3371 clocks = <&di 3282 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3372 <&di 3283 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
3373 <&di 3284 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
3374 <&di 3285 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
3375 <&di 3286 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
3376 clock-names = 3287 clock-names = "core_iface", "core_aux", "ctrl_link",
3377 3288 "ctrl_link_iface", "stream_pixel";
3378 assigned-cloc 3289 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
3379 3290 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
3380 assigned-cloc 3291 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3381 3292 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
3382 phys = <&usb_ 3293 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
3383 phy-names = " 3294 phy-names = "dp";
3384 3295
3385 operating-poi 3296 operating-points-v2 = <&dp_opp_table>;
3386 power-domains 3297 power-domains = <&rpmhpd SC7180_CX>;
3387 3298
3388 #sound-dai-ce 3299 #sound-dai-cells = <0>;
3389 3300
3390 ports { 3301 ports {
3391 #addr 3302 #address-cells = <1>;
3392 #size 3303 #size-cells = <0>;
3393 port@ 3304 port@0 {
3394 3305 reg = <0>;
3395 3306 dp_in: endpoint {
3396 3307 remote-endpoint = <&dpu_intf0_out>;
3397 3308 };
3398 }; 3309 };
3399 3310
3400 port@ 3311 port@1 {
3401 3312 reg = <1>;
3402 3313 mdss_dp_out: endpoint { };
3403 }; 3314 };
3404 }; 3315 };
3405 3316
3406 dp_opp_table: 3317 dp_opp_table: opp-table {
3407 compa 3318 compatible = "operating-points-v2";
3408 3319
3409 opp-1 3320 opp-160000000 {
3410 3321 opp-hz = /bits/ 64 <160000000>;
3411 3322 required-opps = <&rpmhpd_opp_low_svs>;
3412 }; 3323 };
3413 3324
3414 opp-2 3325 opp-270000000 {
3415 3326 opp-hz = /bits/ 64 <270000000>;
3416 3327 required-opps = <&rpmhpd_opp_svs>;
3417 }; 3328 };
3418 3329
3419 opp-5 3330 opp-540000000 {
3420 3331 opp-hz = /bits/ 64 <540000000>;
3421 3332 required-opps = <&rpmhpd_opp_svs_l1>;
3422 }; 3333 };
3423 3334
3424 opp-8 3335 opp-810000000 {
3425 3336 opp-hz = /bits/ 64 <810000000>;
3426 3337 required-opps = <&rpmhpd_opp_nom>;
3427 }; 3338 };
3428 }; 3339 };
3429 }; 3340 };
3430 }; 3341 };
3431 3342
3432 dispcc: clock-controller@af00 3343 dispcc: clock-controller@af00000 {
3433 compatible = "qcom,sc 3344 compatible = "qcom,sc7180-dispcc";
3434 reg = <0 0x0af00000 0 3345 reg = <0 0x0af00000 0 0x200000>;
3435 clocks = <&rpmhcc RPM 3346 clocks = <&rpmhcc RPMH_CXO_CLK>,
3436 <&gcc GCC_DI 3347 <&gcc GCC_DISP_GPLL0_CLK_SRC>,
3437 <&mdss_dsi0_ 3348 <&mdss_dsi0_phy 0>,
3438 <&mdss_dsi0_ 3349 <&mdss_dsi0_phy 1>,
3439 <&usb_1_qmpp 3350 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3440 <&usb_1_qmpp 3351 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
3441 clock-names = "bi_tcx 3352 clock-names = "bi_tcxo",
3442 "gcc_di 3353 "gcc_disp_gpll0_clk_src",
3443 "dsi0_p 3354 "dsi0_phy_pll_out_byteclk",
3444 "dsi0_p 3355 "dsi0_phy_pll_out_dsiclk",
3445 "dp_phy 3356 "dp_phy_pll_link_clk",
3446 "dp_phy 3357 "dp_phy_pll_vco_div_clk";
3447 #clock-cells = <1>; 3358 #clock-cells = <1>;
3448 #reset-cells = <1>; 3359 #reset-cells = <1>;
3449 #power-domain-cells = 3360 #power-domain-cells = <1>;
3450 }; 3361 };
3451 3362
3452 pdc: interrupt-controller@b22 3363 pdc: interrupt-controller@b220000 {
3453 compatible = "qcom,sc 3364 compatible = "qcom,sc7180-pdc", "qcom,pdc";
3454 reg = <0 0x0b220000 0 3365 reg = <0 0x0b220000 0 0x30000>;
3455 qcom,pdc-ranges = <0 3366 qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>;
3456 #interrupt-cells = <2 3367 #interrupt-cells = <2>;
3457 interrupt-parent = <& 3368 interrupt-parent = <&intc>;
3458 interrupt-controller; 3369 interrupt-controller;
3459 }; 3370 };
3460 3371
3461 pdc_reset: reset-controller@b 3372 pdc_reset: reset-controller@b2e0000 {
3462 compatible = "qcom,sc 3373 compatible = "qcom,sc7180-pdc-global", "qcom,sdm845-pdc-global";
3463 reg = <0 0x0b2e0000 0 3374 reg = <0 0x0b2e0000 0 0x20000>;
3464 #reset-cells = <1>; 3375 #reset-cells = <1>;
3465 }; 3376 };
3466 3377
3467 tsens0: thermal-sensor@c26300 3378 tsens0: thermal-sensor@c263000 {
3468 compatible = "qcom,sc 3379 compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
3469 reg = <0 0x0c263000 0 3380 reg = <0 0x0c263000 0 0x1ff>, /* TM */
3470 <0 0x0c222000 3381 <0 0x0c222000 0 0x1ff>; /* SROT */
3471 #qcom,sensors = <15>; 3382 #qcom,sensors = <15>;
3472 interrupts = <GIC_SPI 3383 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
3473 <GIC_SPI 3384 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
3474 interrupt-names = "up 3385 interrupt-names = "uplow","critical";
3475 #thermal-sensor-cells 3386 #thermal-sensor-cells = <1>;
3476 }; 3387 };
3477 3388
3478 tsens1: thermal-sensor@c26500 3389 tsens1: thermal-sensor@c265000 {
3479 compatible = "qcom,sc 3390 compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
3480 reg = <0 0x0c265000 0 3391 reg = <0 0x0c265000 0 0x1ff>, /* TM */
3481 <0 0x0c223000 3392 <0 0x0c223000 0 0x1ff>; /* SROT */
3482 #qcom,sensors = <10>; 3393 #qcom,sensors = <10>;
3483 interrupts = <GIC_SPI 3394 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
3484 <GIC_SPI 3395 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
3485 interrupt-names = "up 3396 interrupt-names = "uplow","critical";
3486 #thermal-sensor-cells 3397 #thermal-sensor-cells = <1>;
3487 }; 3398 };
3488 3399
3489 aoss_reset: reset-controller@ 3400 aoss_reset: reset-controller@c2a0000 {
3490 compatible = "qcom,sc 3401 compatible = "qcom,sc7180-aoss-cc", "qcom,sdm845-aoss-cc";
3491 reg = <0 0x0c2a0000 0 3402 reg = <0 0x0c2a0000 0 0x31000>;
3492 #reset-cells = <1>; 3403 #reset-cells = <1>;
3493 }; 3404 };
3494 3405
3495 aoss_qmp: power-management@c3 3406 aoss_qmp: power-management@c300000 {
3496 compatible = "qcom,sc 3407 compatible = "qcom,sc7180-aoss-qmp", "qcom,aoss-qmp";
3497 reg = <0 0x0c300000 0 3408 reg = <0 0x0c300000 0 0x400>;
3498 interrupts = <GIC_SPI 3409 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
3499 mboxes = <&apss_share 3410 mboxes = <&apss_shared 0>;
3500 3411
3501 #clock-cells = <0>; 3412 #clock-cells = <0>;
3502 }; 3413 };
3503 3414
3504 sram@c3f0000 { 3415 sram@c3f0000 {
3505 compatible = "qcom,rp 3416 compatible = "qcom,rpmh-stats";
3506 reg = <0 0x0c3f0000 0 3417 reg = <0 0x0c3f0000 0 0x400>;
3507 }; 3418 };
3508 3419
3509 spmi_bus: spmi@c440000 { 3420 spmi_bus: spmi@c440000 {
3510 compatible = "qcom,sp 3421 compatible = "qcom,spmi-pmic-arb";
3511 reg = <0 0x0c440000 0 3422 reg = <0 0x0c440000 0 0x1100>,
3512 <0 0x0c600000 0 3423 <0 0x0c600000 0 0x2000000>,
3513 <0 0x0e600000 0 3424 <0 0x0e600000 0 0x100000>,
3514 <0 0x0e700000 0 3425 <0 0x0e700000 0 0xa0000>,
3515 <0 0x0c40a000 0 3426 <0 0x0c40a000 0 0x26000>;
3516 reg-names = "core", " 3427 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3517 interrupt-names = "pe 3428 interrupt-names = "periph_irq";
3518 interrupts-extended = 3429 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3519 qcom,ee = <0>; 3430 qcom,ee = <0>;
3520 qcom,channel = <0>; 3431 qcom,channel = <0>;
3521 #address-cells = <2>; 3432 #address-cells = <2>;
3522 #size-cells = <0>; 3433 #size-cells = <0>;
3523 interrupt-controller; 3434 interrupt-controller;
3524 #interrupt-cells = <4 3435 #interrupt-cells = <4>;
3525 }; 3436 };
3526 3437
3527 sram@146aa000 { 3438 sram@146aa000 {
3528 compatible = "qcom,sc 3439 compatible = "qcom,sc7180-imem", "syscon", "simple-mfd";
3529 reg = <0 0x146aa000 0 3440 reg = <0 0x146aa000 0 0x2000>;
3530 3441
3531 #address-cells = <1>; 3442 #address-cells = <1>;
3532 #size-cells = <1>; 3443 #size-cells = <1>;
3533 3444
3534 ranges = <0 0 0x146aa 3445 ranges = <0 0 0x146aa000 0x2000>;
3535 3446
3536 pil-reloc@94c { 3447 pil-reloc@94c {
3537 compatible = 3448 compatible = "qcom,pil-reloc-info";
3538 reg = <0x94c 3449 reg = <0x94c 0xc8>;
3539 }; 3450 };
3540 }; 3451 };
3541 3452
3542 apps_smmu: iommu@15000000 { 3453 apps_smmu: iommu@15000000 {
3543 compatible = "qcom,sc 3454 compatible = "qcom,sc7180-smmu-500", "arm,mmu-500";
3544 reg = <0 0x15000000 0 3455 reg = <0 0x15000000 0 0x100000>;
3545 #iommu-cells = <2>; 3456 #iommu-cells = <2>;
3546 #global-interrupts = 3457 #global-interrupts = <1>;
3547 interrupts = <GIC_SPI 3458 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
3548 <GIC_SPI 3459 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
3549 <GIC_SPI 3460 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
3550 <GIC_SPI 3461 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
3551 <GIC_SPI 3462 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
3552 <GIC_SPI 3463 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
3553 <GIC_SPI 3464 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
3554 <GIC_SPI 3465 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
3555 <GIC_SPI 3466 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
3556 <GIC_SPI 3467 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
3557 <GIC_SPI 3468 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
3558 <GIC_SPI 3469 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
3559 <GIC_SPI 3470 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
3560 <GIC_SPI 3471 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
3561 <GIC_SPI 3472 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
3562 <GIC_SPI 3473 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
3563 <GIC_SPI 3474 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
3564 <GIC_SPI 3475 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
3565 <GIC_SPI 3476 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
3566 <GIC_SPI 3477 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
3567 <GIC_SPI 3478 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
3568 <GIC_SPI 3479 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
3569 <GIC_SPI 3480 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
3570 <GIC_SPI 3481 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
3571 <GIC_SPI 3482 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
3572 <GIC_SPI 3483 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
3573 <GIC_SPI 3484 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
3574 <GIC_SPI 3485 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
3575 <GIC_SPI 3486 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
3576 <GIC_SPI 3487 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
3577 <GIC_SPI 3488 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
3578 <GIC_SPI 3489 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
3579 <GIC_SPI 3490 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
3580 <GIC_SPI 3491 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
3581 <GIC_SPI 3492 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
3582 <GIC_SPI 3493 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
3583 <GIC_SPI 3494 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
3584 <GIC_SPI 3495 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
3585 <GIC_SPI 3496 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
3586 <GIC_SPI 3497 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
3587 <GIC_SPI 3498 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
3588 <GIC_SPI 3499 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
3589 <GIC_SPI 3500 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
3590 <GIC_SPI 3501 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
3591 <GIC_SPI 3502 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
3592 <GIC_SPI 3503 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
3593 <GIC_SPI 3504 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
3594 <GIC_SPI 3505 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
3595 <GIC_SPI 3506 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
3596 <GIC_SPI 3507 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
3597 <GIC_SPI 3508 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
3598 <GIC_SPI 3509 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
3599 <GIC_SPI 3510 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
3600 <GIC_SPI 3511 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
3601 <GIC_SPI 3512 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
3602 <GIC_SPI 3513 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
3603 <GIC_SPI 3514 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
3604 <GIC_SPI 3515 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
3605 <GIC_SPI 3516 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
3606 <GIC_SPI 3517 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
3607 <GIC_SPI 3518 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
3608 <GIC_SPI 3519 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
3609 <GIC_SPI 3520 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
3610 <GIC_SPI 3521 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
3611 <GIC_SPI 3522 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
3612 <GIC_SPI 3523 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
3613 <GIC_SPI 3524 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
3614 <GIC_SPI 3525 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
3615 <GIC_SPI 3526 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
3616 <GIC_SPI 3527 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
3617 <GIC_SPI 3528 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
3618 <GIC_SPI 3529 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
3619 <GIC_SPI 3530 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
3620 <GIC_SPI 3531 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
3621 <GIC_SPI 3532 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
3622 <GIC_SPI 3533 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
3623 <GIC_SPI 3534 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
3624 <GIC_SPI 3535 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
3625 <GIC_SPI 3536 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
3626 <GIC_SPI 3537 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
3627 <GIC_SPI 3538 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
3628 }; 3539 };
3629 3540
3630 intc: interrupt-controller@17 3541 intc: interrupt-controller@17a00000 {
3631 compatible = "arm,gic 3542 compatible = "arm,gic-v3";
3632 #address-cells = <2>; 3543 #address-cells = <2>;
3633 #size-cells = <2>; 3544 #size-cells = <2>;
3634 ranges; 3545 ranges;
3635 #interrupt-cells = <3 3546 #interrupt-cells = <3>;
3636 interrupt-controller; 3547 interrupt-controller;
3637 reg = <0 0x17a00000 0 3548 reg = <0 0x17a00000 0 0x10000>, /* GICD */
3638 <0 0x17a60000 0 3549 <0 0x17a60000 0 0x100000>; /* GICR * 8 */
3639 interrupts = <GIC_PPI 3550 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3640 3551
3641 msi-controller@17a400 3552 msi-controller@17a40000 {
3642 compatible = 3553 compatible = "arm,gic-v3-its";
3643 msi-controlle 3554 msi-controller;
3644 #msi-cells = 3555 #msi-cells = <1>;
3645 reg = <0 0x17 3556 reg = <0 0x17a40000 0 0x20000>;
3646 status = "dis 3557 status = "disabled";
3647 }; 3558 };
3648 }; 3559 };
3649 3560
3650 apss_shared: mailbox@17c00000 3561 apss_shared: mailbox@17c00000 {
3651 compatible = "qcom,sc 3562 compatible = "qcom,sc7180-apss-shared",
3652 "qcom,sd 3563 "qcom,sdm845-apss-shared";
3653 reg = <0 0x17c00000 0 3564 reg = <0 0x17c00000 0 0x10000>;
3654 #mbox-cells = <1>; 3565 #mbox-cells = <1>;
3655 }; 3566 };
3656 3567
3657 watchdog@17c10000 { 3568 watchdog@17c10000 {
3658 compatible = "qcom,ap 3569 compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt";
3659 reg = <0 0x17c10000 0 3570 reg = <0 0x17c10000 0 0x1000>;
3660 clocks = <&sleep_clk> 3571 clocks = <&sleep_clk>;
3661 interrupts = <GIC_SPI 3572 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
3662 }; 3573 };
3663 3574
3664 timer@17c20000 { 3575 timer@17c20000 {
3665 #address-cells = <1>; 3576 #address-cells = <1>;
3666 #size-cells = <1>; 3577 #size-cells = <1>;
3667 ranges = <0 0 0 0x200 3578 ranges = <0 0 0 0x20000000>;
3668 compatible = "arm,arm 3579 compatible = "arm,armv7-timer-mem";
3669 reg = <0 0x17c20000 0 3580 reg = <0 0x17c20000 0 0x1000>;
3670 3581
3671 frame@17c21000 { 3582 frame@17c21000 {
3672 frame-number 3583 frame-number = <0>;
3673 interrupts = 3584 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
3674 3585 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
3675 reg = <0x17c2 3586 reg = <0x17c21000 0x1000>,
3676 <0x17c2 3587 <0x17c22000 0x1000>;
3677 }; 3588 };
3678 3589
3679 frame@17c23000 { 3590 frame@17c23000 {
3680 frame-number 3591 frame-number = <1>;
3681 interrupts = 3592 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
3682 reg = <0x17c2 3593 reg = <0x17c23000 0x1000>;
3683 status = "dis 3594 status = "disabled";
3684 }; 3595 };
3685 3596
3686 frame@17c25000 { 3597 frame@17c25000 {
3687 frame-number 3598 frame-number = <2>;
3688 interrupts = 3599 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
3689 reg = <0x17c2 3600 reg = <0x17c25000 0x1000>;
3690 status = "dis 3601 status = "disabled";
3691 }; 3602 };
3692 3603
3693 frame@17c27000 { 3604 frame@17c27000 {
3694 frame-number 3605 frame-number = <3>;
3695 interrupts = 3606 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3696 reg = <0x17c2 3607 reg = <0x17c27000 0x1000>;
3697 status = "dis 3608 status = "disabled";
3698 }; 3609 };
3699 3610
3700 frame@17c29000 { 3611 frame@17c29000 {
3701 frame-number 3612 frame-number = <4>;
3702 interrupts = 3613 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3703 reg = <0x17c2 3614 reg = <0x17c29000 0x1000>;
3704 status = "dis 3615 status = "disabled";
3705 }; 3616 };
3706 3617
3707 frame@17c2b000 { 3618 frame@17c2b000 {
3708 frame-number 3619 frame-number = <5>;
3709 interrupts = 3620 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3710 reg = <0x17c2 3621 reg = <0x17c2b000 0x1000>;
3711 status = "dis 3622 status = "disabled";
3712 }; 3623 };
3713 3624
3714 frame@17c2d000 { 3625 frame@17c2d000 {
3715 frame-number 3626 frame-number = <6>;
3716 interrupts = 3627 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
3717 reg = <0x17c2 3628 reg = <0x17c2d000 0x1000>;
3718 status = "dis 3629 status = "disabled";
3719 }; 3630 };
3720 }; 3631 };
3721 3632
3722 apps_rsc: rsc@18200000 { 3633 apps_rsc: rsc@18200000 {
3723 compatible = "qcom,rp 3634 compatible = "qcom,rpmh-rsc";
3724 reg = <0 0x18200000 0 3635 reg = <0 0x18200000 0 0x10000>,
3725 <0 0x18210000 0 3636 <0 0x18210000 0 0x10000>,
3726 <0 0x18220000 0 3637 <0 0x18220000 0 0x10000>;
3727 reg-names = "drv-0", 3638 reg-names = "drv-0", "drv-1", "drv-2";
3728 interrupts = <GIC_SPI 3639 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
3729 <GIC_SPI 3640 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
3730 <GIC_SPI 3641 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
3731 qcom,tcs-offset = <0x 3642 qcom,tcs-offset = <0xd00>;
3732 qcom,drv-id = <2>; 3643 qcom,drv-id = <2>;
3733 qcom,tcs-config = <AC 3644 qcom,tcs-config = <ACTIVE_TCS 2>,
3734 <SL 3645 <SLEEP_TCS 3>,
3735 <WA 3646 <WAKE_TCS 3>,
3736 <CO 3647 <CONTROL_TCS 1>;
3737 power-domains = <&CLU 3648 power-domains = <&CLUSTER_PD>;
3738 3649
3739 rpmhcc: clock-control 3650 rpmhcc: clock-controller {
3740 compatible = 3651 compatible = "qcom,sc7180-rpmh-clk";
3741 clocks = <&xo 3652 clocks = <&xo_board>;
3742 clock-names = 3653 clock-names = "xo";
3743 #clock-cells 3654 #clock-cells = <1>;
3744 }; 3655 };
3745 3656
3746 rpmhpd: power-control 3657 rpmhpd: power-controller {
3747 compatible = 3658 compatible = "qcom,sc7180-rpmhpd";
3748 #power-domain 3659 #power-domain-cells = <1>;
3749 operating-poi 3660 operating-points-v2 = <&rpmhpd_opp_table>;
3750 3661
3751 rpmhpd_opp_ta 3662 rpmhpd_opp_table: opp-table {
3752 compa 3663 compatible = "operating-points-v2";
3753 3664
3754 rpmhp 3665 rpmhpd_opp_ret: opp1 {
3755 3666 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3756 }; 3667 };
3757 3668
3758 rpmhp 3669 rpmhpd_opp_min_svs: opp2 {
3759 3670 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3760 }; 3671 };
3761 3672
3762 rpmhp 3673 rpmhpd_opp_low_svs: opp3 {
3763 3674 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3764 }; 3675 };
3765 3676
3766 rpmhp 3677 rpmhpd_opp_svs: opp4 {
3767 3678 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3768 }; 3679 };
3769 3680
3770 rpmhp 3681 rpmhpd_opp_svs_l1: opp5 {
3771 3682 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3772 }; 3683 };
3773 3684
3774 rpmhp 3685 rpmhpd_opp_svs_l2: opp6 {
3775 3686 opp-level = <224>;
3776 }; 3687 };
3777 3688
3778 rpmhp 3689 rpmhpd_opp_nom: opp7 {
3779 3690 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3780 }; 3691 };
3781 3692
3782 rpmhp 3693 rpmhpd_opp_nom_l1: opp8 {
3783 3694 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3784 }; 3695 };
3785 3696
3786 rpmhp 3697 rpmhpd_opp_nom_l2: opp9 {
3787 3698 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3788 }; 3699 };
3789 3700
3790 rpmhp 3701 rpmhpd_opp_turbo: opp10 {
3791 3702 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3792 }; 3703 };
3793 3704
3794 rpmhp 3705 rpmhpd_opp_turbo_l1: opp11 {
3795 3706 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3796 }; 3707 };
3797 }; 3708 };
3798 }; 3709 };
3799 3710
3800 apps_bcm_voter: bcm-v 3711 apps_bcm_voter: bcm-voter {
3801 compatible = 3712 compatible = "qcom,bcm-voter";
3802 }; 3713 };
3803 }; 3714 };
3804 3715
3805 osm_l3: interconnect@18321000 3716 osm_l3: interconnect@18321000 {
3806 compatible = "qcom,sc 3717 compatible = "qcom,sc7180-osm-l3", "qcom,osm-l3";
3807 reg = <0 0x18321000 0 3718 reg = <0 0x18321000 0 0x1400>;
3808 3719
3809 clocks = <&rpmhcc RPM 3720 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3810 clock-names = "xo", " 3721 clock-names = "xo", "alternate";
3811 3722
3812 #interconnect-cells = 3723 #interconnect-cells = <1>;
3813 }; 3724 };
3814 3725
3815 cpufreq_hw: cpufreq@18323000 3726 cpufreq_hw: cpufreq@18323000 {
3816 compatible = "qcom,sc 3727 compatible = "qcom,sc7180-cpufreq-hw", "qcom,cpufreq-hw";
3817 reg = <0 0x18323000 0 3728 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>;
3818 reg-names = "freq-dom 3729 reg-names = "freq-domain0", "freq-domain1";
3819 3730
3820 clocks = <&rpmhcc RPM 3731 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3821 clock-names = "xo", " 3732 clock-names = "xo", "alternate";
3822 3733
3823 #freq-domain-cells = 3734 #freq-domain-cells = <1>;
3824 #clock-cells = <1>; 3735 #clock-cells = <1>;
3825 }; 3736 };
3826 3737
3827 wifi: wifi@18800000 { 3738 wifi: wifi@18800000 {
3828 compatible = "qcom,wc 3739 compatible = "qcom,wcn3990-wifi";
3829 reg = <0 0x18800000 0 3740 reg = <0 0x18800000 0 0x800000>;
3830 reg-names = "membase" 3741 reg-names = "membase";
3831 iommus = <&apps_smmu 3742 iommus = <&apps_smmu 0xc0 0x1>;
3832 interrupts = 3743 interrupts =
3833 <GIC_SPI 414 3744 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH /* CE0 */ >,
3834 <GIC_SPI 415 3745 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH /* CE1 */ >,
3835 <GIC_SPI 416 3746 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH /* CE2 */ >,
3836 <GIC_SPI 417 3747 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH /* CE3 */ >,
3837 <GIC_SPI 418 3748 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH /* CE4 */ >,
3838 <GIC_SPI 419 3749 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH /* CE5 */ >,
3839 <GIC_SPI 420 3750 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH /* CE6 */ >,
3840 <GIC_SPI 421 3751 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH /* CE7 */ >,
3841 <GIC_SPI 422 3752 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH /* CE8 */ >,
3842 <GIC_SPI 423 3753 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH /* CE9 */ >,
3843 <GIC_SPI 424 3754 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH /* CE10 */>,
3844 <GIC_SPI 425 3755 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH /* CE11 */>;
3845 memory-region = <&wla 3756 memory-region = <&wlan_mem>;
3846 qcom,msa-fixed-perm; 3757 qcom,msa-fixed-perm;
3847 status = "disabled"; 3758 status = "disabled";
3848 }; 3759 };
3849 3760
3850 remoteproc_adsp: remoteproc@6 <<
3851 compatible = "qcom,sc <<
3852 reg = <0 0x62400000 0 <<
3853 <<
3854 interrupts-extended = <<
3855 <<
3856 <<
3857 <<
3858 <<
3859 interrupt-names = "wd <<
3860 "fa <<
3861 "re <<
3862 "ha <<
3863 "st <<
3864 <<
3865 clocks = <&rpmhcc RPM <<
3866 clock-names = "xo"; <<
3867 <<
3868 power-domains = <&rpm <<
3869 <&rpm <<
3870 power-domain-names = <<
3871 <<
3872 qcom,qmp = <&aoss_qmp <<
3873 qcom,smem-states = <& <<
3874 qcom,smem-state-names <<
3875 <<
3876 status = "disabled"; <<
3877 <<
3878 glink-edge { <<
3879 interrupts = <<
3880 label = "lpas <<
3881 qcom,remote-p <<
3882 mboxes = <&ap <<
3883 <<
3884 apr { <<
3885 compa <<
3886 qcom, <<
3887 qcom, <<
3888 #addr <<
3889 #size <<
3890 <<
3891 servi <<
3892 <<
3893 <<
3894 <<
3895 }; <<
3896 <<
3897 q6afe <<
3898 <<
3899 <<
3900 <<
3901 <<
3902 <<
3903 <<
3904 <<
3905 <<
3906 <<
3907 <<
3908 <<
3909 <<
3910 <<
3911 <<
3912 <<
3913 }; <<
3914 <<
3915 q6asm <<
3916 <<
3917 <<
3918 <<
3919 <<
3920 <<
3921 <<
3922 <<
3923 <<
3924 <<
3925 <<
3926 <<
3927 }; <<
3928 <<
3929 q6adm <<
3930 <<
3931 <<
3932 <<
3933 <<
3934 <<
3935 <<
3936 <<
3937 <<
3938 }; <<
3939 }; <<
3940 <<
3941 fastrpc { <<
3942 compa <<
3943 qcom, <<
3944 label <<
3945 #addr <<
3946 #size <<
3947 <<
3948 compu <<
3949 <<
3950 <<
3951 <<
3952 }; <<
3953 <<
3954 compu <<
3955 <<
3956 <<
3957 <<
3958 }; <<
3959 <<
3960 compu <<
3961 <<
3962 <<
3963 <<
3964 <<
3965 }; <<
3966 }; <<
3967 }; <<
3968 }; <<
3969 <<
3970 lpasscc: clock-controller@62d 3761 lpasscc: clock-controller@62d00000 {
3971 compatible = "qcom,sc 3762 compatible = "qcom,sc7180-lpasscorecc";
3972 reg = <0 0x62d00000 0 3763 reg = <0 0x62d00000 0 0x50000>,
3973 <0 0x62780000 0 3764 <0 0x62780000 0 0x30000>;
3974 reg-names = "lpass_co 3765 reg-names = "lpass_core_cc", "lpass_audio_cc";
3975 clocks = <&gcc GCC_LP 3766 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>,
3976 <&rpmhcc RPM 3767 <&rpmhcc RPMH_CXO_CLK>;
3977 clock-names = "iface" 3768 clock-names = "iface", "bi_tcxo";
3978 power-domains = <&lpa 3769 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>;
3979 #clock-cells = <1>; 3770 #clock-cells = <1>;
3980 #power-domain-cells = 3771 #power-domain-cells = <1>;
3981 3772
3982 status = "reserved"; 3773 status = "reserved"; /* Controlled by ADSP */
3983 }; 3774 };
3984 3775
3985 lpass_cpu: lpass@62d87000 { 3776 lpass_cpu: lpass@62d87000 {
3986 compatible = "qcom,sc 3777 compatible = "qcom,sc7180-lpass-cpu";
3987 3778
3988 reg = <0 0x62d87000 0 3779 reg = <0 0x62d87000 0 0x68000>, <0 0x62f00000 0 0x29000>;
3989 reg-names = "lpass-hd 3780 reg-names = "lpass-hdmiif", "lpass-lpaif";
3990 3781
3991 iommus = <&apps_smmu 3782 iommus = <&apps_smmu 0x1020 0>,
3992 <&apps_smmu 0 3783 <&apps_smmu 0x1021 0>,
3993 <&apps_smmu 0 3784 <&apps_smmu 0x1032 0>;
3994 3785
3995 power-domains = <&lpa 3786 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>;
3996 required-opps = <&rpm 3787 required-opps = <&rpmhpd_opp_nom>;
3997 3788
3998 status = "disabled"; 3789 status = "disabled";
3999 3790
4000 clocks = <&gcc GCC_LP 3791 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>,
4001 <&lpasscc LP 3792 <&lpasscc LPASS_AUDIO_CORE_CORE_CLK>,
4002 <&lpasscc LP 3793 <&lpasscc LPASS_AUDIO_CORE_EXT_MCLK0_CLK>,
4003 <&lpasscc LP 3794 <&lpasscc LPASS_AUDIO_CORE_SYSNOC_MPORT_CORE_CLK>,
4004 <&lpasscc LP 3795 <&lpasscc LPASS_AUDIO_CORE_LPAIF_PRI_IBIT_CLK>,
4005 <&lpasscc LP 3796 <&lpasscc LPASS_AUDIO_CORE_LPAIF_SEC_IBIT_CLK>;
4006 3797
4007 clock-names = "pcnoc- 3798 clock-names = "pcnoc-sway-clk", "audio-core",
4008 "mclk 3799 "mclk0", "pcnoc-mport-clk",
4009 "mi2s 3800 "mi2s-bit-clk0", "mi2s-bit-clk1";
4010 3801
4011 3802
4012 #sound-dai-cells = <1 3803 #sound-dai-cells = <1>;
4013 #address-cells = <1>; 3804 #address-cells = <1>;
4014 #size-cells = <0>; 3805 #size-cells = <0>;
4015 3806
4016 interrupts = <GIC_SPI 3807 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
4017 <GIC_ 3808 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
4018 interrupt-names = "lp 3809 interrupt-names = "lpass-irq-lpaif", "lpass-irq-hdmi";
4019 }; 3810 };
4020 3811
4021 lpass_hm: clock-controller@63 3812 lpass_hm: clock-controller@63000000 {
4022 compatible = "qcom,sc 3813 compatible = "qcom,sc7180-lpasshm";
4023 reg = <0 0x63000000 0 3814 reg = <0 0x63000000 0 0x28>;
4024 clocks = <&gcc GCC_LP 3815 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>,
4025 <&rpmhcc RPM 3816 <&rpmhcc RPMH_CXO_CLK>;
4026 clock-names = "iface" 3817 clock-names = "iface", "bi_tcxo";
4027 power-domains = <&rpm 3818 power-domains = <&rpmhpd SC7180_CX>;
4028 3819
4029 #clock-cells = <1>; 3820 #clock-cells = <1>;
4030 #power-domain-cells = 3821 #power-domain-cells = <1>;
4031 3822
4032 status = "reserved"; 3823 status = "reserved"; /* Controlled by ADSP */
4033 }; 3824 };
4034 }; 3825 };
4035 3826
4036 thermal-zones { 3827 thermal-zones {
4037 cpu0_thermal: cpu0-thermal { 3828 cpu0_thermal: cpu0-thermal {
4038 polling-delay-passive 3829 polling-delay-passive = <250>;
>> 3830 polling-delay = <0>;
4039 3831
4040 thermal-sensors = <&t 3832 thermal-sensors = <&tsens0 1>;
4041 sustainable-power = < 3833 sustainable-power = <1052>;
4042 3834
4043 trips { 3835 trips {
4044 cpu0_alert0: 3836 cpu0_alert0: trip-point0 {
4045 tempe 3837 temperature = <90000>;
4046 hyste 3838 hysteresis = <2000>;
4047 type 3839 type = "passive";
4048 }; 3840 };
4049 3841
4050 cpu0_alert1: 3842 cpu0_alert1: trip-point1 {
4051 tempe 3843 temperature = <95000>;
4052 hyste 3844 hysteresis = <2000>;
4053 type 3845 type = "passive";
4054 }; 3846 };
4055 3847
4056 cpu0_crit: cp 3848 cpu0_crit: cpu-crit {
4057 tempe 3849 temperature = <110000>;
4058 hyste 3850 hysteresis = <1000>;
4059 type 3851 type = "critical";
4060 }; 3852 };
4061 }; 3853 };
4062 3854
4063 cooling-maps { 3855 cooling-maps {
4064 map0 { 3856 map0 {
4065 trip 3857 trip = <&cpu0_alert0>;
4066 cooli 3858 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4067 3859 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4068 3860 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4069 3861 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4070 3862 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4071 3863 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4072 }; 3864 };
4073 map1 { 3865 map1 {
4074 trip 3866 trip = <&cpu0_alert1>;
4075 cooli 3867 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4076 3868 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4077 3869 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4078 3870 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4079 3871 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4080 3872 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4081 }; 3873 };
4082 }; 3874 };
4083 }; 3875 };
4084 3876
4085 cpu1_thermal: cpu1-thermal { 3877 cpu1_thermal: cpu1-thermal {
4086 polling-delay-passive 3878 polling-delay-passive = <250>;
>> 3879 polling-delay = <0>;
4087 3880
4088 thermal-sensors = <&t 3881 thermal-sensors = <&tsens0 2>;
4089 sustainable-power = < 3882 sustainable-power = <1052>;
4090 3883
4091 trips { 3884 trips {
4092 cpu1_alert0: 3885 cpu1_alert0: trip-point0 {
4093 tempe 3886 temperature = <90000>;
4094 hyste 3887 hysteresis = <2000>;
4095 type 3888 type = "passive";
4096 }; 3889 };
4097 3890
4098 cpu1_alert1: 3891 cpu1_alert1: trip-point1 {
4099 tempe 3892 temperature = <95000>;
4100 hyste 3893 hysteresis = <2000>;
4101 type 3894 type = "passive";
4102 }; 3895 };
4103 3896
4104 cpu1_crit: cp 3897 cpu1_crit: cpu-crit {
4105 tempe 3898 temperature = <110000>;
4106 hyste 3899 hysteresis = <1000>;
4107 type 3900 type = "critical";
4108 }; 3901 };
4109 }; 3902 };
4110 3903
4111 cooling-maps { 3904 cooling-maps {
4112 map0 { 3905 map0 {
4113 trip 3906 trip = <&cpu1_alert0>;
4114 cooli 3907 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4115 3908 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4116 3909 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4117 3910 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4118 3911 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4119 3912 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4120 }; 3913 };
4121 map1 { 3914 map1 {
4122 trip 3915 trip = <&cpu1_alert1>;
4123 cooli 3916 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4124 3917 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4125 3918 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4126 3919 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4127 3920 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4128 3921 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4129 }; 3922 };
4130 }; 3923 };
4131 }; 3924 };
4132 3925
4133 cpu2_thermal: cpu2-thermal { 3926 cpu2_thermal: cpu2-thermal {
4134 polling-delay-passive 3927 polling-delay-passive = <250>;
>> 3928 polling-delay = <0>;
4135 3929
4136 thermal-sensors = <&t 3930 thermal-sensors = <&tsens0 3>;
4137 sustainable-power = < 3931 sustainable-power = <1052>;
4138 3932
4139 trips { 3933 trips {
4140 cpu2_alert0: 3934 cpu2_alert0: trip-point0 {
4141 tempe 3935 temperature = <90000>;
4142 hyste 3936 hysteresis = <2000>;
4143 type 3937 type = "passive";
4144 }; 3938 };
4145 3939
4146 cpu2_alert1: 3940 cpu2_alert1: trip-point1 {
4147 tempe 3941 temperature = <95000>;
4148 hyste 3942 hysteresis = <2000>;
4149 type 3943 type = "passive";
4150 }; 3944 };
4151 3945
4152 cpu2_crit: cp 3946 cpu2_crit: cpu-crit {
4153 tempe 3947 temperature = <110000>;
4154 hyste 3948 hysteresis = <1000>;
4155 type 3949 type = "critical";
4156 }; 3950 };
4157 }; 3951 };
4158 3952
4159 cooling-maps { 3953 cooling-maps {
4160 map0 { 3954 map0 {
4161 trip 3955 trip = <&cpu2_alert0>;
4162 cooli 3956 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4163 3957 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4164 3958 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4165 3959 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4166 3960 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4167 3961 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4168 }; 3962 };
4169 map1 { 3963 map1 {
4170 trip 3964 trip = <&cpu2_alert1>;
4171 cooli 3965 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4172 3966 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4173 3967 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4174 3968 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4175 3969 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4176 3970 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4177 }; 3971 };
4178 }; 3972 };
4179 }; 3973 };
4180 3974
4181 cpu3_thermal: cpu3-thermal { 3975 cpu3_thermal: cpu3-thermal {
4182 polling-delay-passive 3976 polling-delay-passive = <250>;
>> 3977 polling-delay = <0>;
4183 3978
4184 thermal-sensors = <&t 3979 thermal-sensors = <&tsens0 4>;
4185 sustainable-power = < 3980 sustainable-power = <1052>;
4186 3981
4187 trips { 3982 trips {
4188 cpu3_alert0: 3983 cpu3_alert0: trip-point0 {
4189 tempe 3984 temperature = <90000>;
4190 hyste 3985 hysteresis = <2000>;
4191 type 3986 type = "passive";
4192 }; 3987 };
4193 3988
4194 cpu3_alert1: 3989 cpu3_alert1: trip-point1 {
4195 tempe 3990 temperature = <95000>;
4196 hyste 3991 hysteresis = <2000>;
4197 type 3992 type = "passive";
4198 }; 3993 };
4199 3994
4200 cpu3_crit: cp 3995 cpu3_crit: cpu-crit {
4201 tempe 3996 temperature = <110000>;
4202 hyste 3997 hysteresis = <1000>;
4203 type 3998 type = "critical";
4204 }; 3999 };
4205 }; 4000 };
4206 4001
4207 cooling-maps { 4002 cooling-maps {
4208 map0 { 4003 map0 {
4209 trip 4004 trip = <&cpu3_alert0>;
4210 cooli 4005 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4211 4006 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4212 4007 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4213 4008 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4214 4009 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4215 4010 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4216 }; 4011 };
4217 map1 { 4012 map1 {
4218 trip 4013 trip = <&cpu3_alert1>;
4219 cooli 4014 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4220 4015 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4221 4016 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4222 4017 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4223 4018 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4224 4019 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4225 }; 4020 };
4226 }; 4021 };
4227 }; 4022 };
4228 4023
4229 cpu4_thermal: cpu4-thermal { 4024 cpu4_thermal: cpu4-thermal {
4230 polling-delay-passive 4025 polling-delay-passive = <250>;
>> 4026 polling-delay = <0>;
4231 4027
4232 thermal-sensors = <&t 4028 thermal-sensors = <&tsens0 5>;
4233 sustainable-power = < 4029 sustainable-power = <1052>;
4234 4030
4235 trips { 4031 trips {
4236 cpu4_alert0: 4032 cpu4_alert0: trip-point0 {
4237 tempe 4033 temperature = <90000>;
4238 hyste 4034 hysteresis = <2000>;
4239 type 4035 type = "passive";
4240 }; 4036 };
4241 4037
4242 cpu4_alert1: 4038 cpu4_alert1: trip-point1 {
4243 tempe 4039 temperature = <95000>;
4244 hyste 4040 hysteresis = <2000>;
4245 type 4041 type = "passive";
4246 }; 4042 };
4247 4043
4248 cpu4_crit: cp 4044 cpu4_crit: cpu-crit {
4249 tempe 4045 temperature = <110000>;
4250 hyste 4046 hysteresis = <1000>;
4251 type 4047 type = "critical";
4252 }; 4048 };
4253 }; 4049 };
4254 4050
4255 cooling-maps { 4051 cooling-maps {
4256 map0 { 4052 map0 {
4257 trip 4053 trip = <&cpu4_alert0>;
4258 cooli 4054 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4259 4055 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4260 4056 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4261 4057 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4262 4058 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4263 4059 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4264 }; 4060 };
4265 map1 { 4061 map1 {
4266 trip 4062 trip = <&cpu4_alert1>;
4267 cooli 4063 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4268 4064 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4269 4065 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4270 4066 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4271 4067 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4272 4068 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4273 }; 4069 };
4274 }; 4070 };
4275 }; 4071 };
4276 4072
4277 cpu5_thermal: cpu5-thermal { 4073 cpu5_thermal: cpu5-thermal {
4278 polling-delay-passive 4074 polling-delay-passive = <250>;
>> 4075 polling-delay = <0>;
4279 4076
4280 thermal-sensors = <&t 4077 thermal-sensors = <&tsens0 6>;
4281 sustainable-power = < 4078 sustainable-power = <1052>;
4282 4079
4283 trips { 4080 trips {
4284 cpu5_alert0: 4081 cpu5_alert0: trip-point0 {
4285 tempe 4082 temperature = <90000>;
4286 hyste 4083 hysteresis = <2000>;
4287 type 4084 type = "passive";
4288 }; 4085 };
4289 4086
4290 cpu5_alert1: 4087 cpu5_alert1: trip-point1 {
4291 tempe 4088 temperature = <95000>;
4292 hyste 4089 hysteresis = <2000>;
4293 type 4090 type = "passive";
4294 }; 4091 };
4295 4092
4296 cpu5_crit: cp 4093 cpu5_crit: cpu-crit {
4297 tempe 4094 temperature = <110000>;
4298 hyste 4095 hysteresis = <1000>;
4299 type 4096 type = "critical";
4300 }; 4097 };
4301 }; 4098 };
4302 4099
4303 cooling-maps { 4100 cooling-maps {
4304 map0 { 4101 map0 {
4305 trip 4102 trip = <&cpu5_alert0>;
4306 cooli 4103 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4307 4104 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4308 4105 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4309 4106 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4310 4107 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4311 4108 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4312 }; 4109 };
4313 map1 { 4110 map1 {
4314 trip 4111 trip = <&cpu5_alert1>;
4315 cooli 4112 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4316 4113 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4317 4114 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4318 4115 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4319 4116 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4320 4117 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4321 }; 4118 };
4322 }; 4119 };
4323 }; 4120 };
4324 4121
4325 cpu6_thermal: cpu6-thermal { 4122 cpu6_thermal: cpu6-thermal {
4326 polling-delay-passive 4123 polling-delay-passive = <250>;
>> 4124 polling-delay = <0>;
4327 4125
4328 thermal-sensors = <&t 4126 thermal-sensors = <&tsens0 9>;
4329 sustainable-power = < 4127 sustainable-power = <1425>;
4330 4128
4331 trips { 4129 trips {
4332 cpu6_alert0: 4130 cpu6_alert0: trip-point0 {
4333 tempe 4131 temperature = <90000>;
4334 hyste 4132 hysteresis = <2000>;
4335 type 4133 type = "passive";
4336 }; 4134 };
4337 4135
4338 cpu6_alert1: 4136 cpu6_alert1: trip-point1 {
4339 tempe 4137 temperature = <95000>;
4340 hyste 4138 hysteresis = <2000>;
4341 type 4139 type = "passive";
4342 }; 4140 };
4343 4141
4344 cpu6_crit: cp 4142 cpu6_crit: cpu-crit {
4345 tempe 4143 temperature = <110000>;
4346 hyste 4144 hysteresis = <1000>;
4347 type 4145 type = "critical";
4348 }; 4146 };
4349 }; 4147 };
4350 4148
4351 cooling-maps { 4149 cooling-maps {
4352 map0 { 4150 map0 {
4353 trip 4151 trip = <&cpu6_alert0>;
4354 cooli 4152 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4355 4153 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4356 }; 4154 };
4357 map1 { 4155 map1 {
4358 trip 4156 trip = <&cpu6_alert1>;
4359 cooli 4157 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4360 4158 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4361 }; 4159 };
4362 }; 4160 };
4363 }; 4161 };
4364 4162
4365 cpu7_thermal: cpu7-thermal { 4163 cpu7_thermal: cpu7-thermal {
4366 polling-delay-passive 4164 polling-delay-passive = <250>;
>> 4165 polling-delay = <0>;
4367 4166
4368 thermal-sensors = <&t 4167 thermal-sensors = <&tsens0 10>;
4369 sustainable-power = < 4168 sustainable-power = <1425>;
4370 4169
4371 trips { 4170 trips {
4372 cpu7_alert0: 4171 cpu7_alert0: trip-point0 {
4373 tempe 4172 temperature = <90000>;
4374 hyste 4173 hysteresis = <2000>;
4375 type 4174 type = "passive";
4376 }; 4175 };
4377 4176
4378 cpu7_alert1: 4177 cpu7_alert1: trip-point1 {
4379 tempe 4178 temperature = <95000>;
4380 hyste 4179 hysteresis = <2000>;
4381 type 4180 type = "passive";
4382 }; 4181 };
4383 4182
4384 cpu7_crit: cp 4183 cpu7_crit: cpu-crit {
4385 tempe 4184 temperature = <110000>;
4386 hyste 4185 hysteresis = <1000>;
4387 type 4186 type = "critical";
4388 }; 4187 };
4389 }; 4188 };
4390 4189
4391 cooling-maps { 4190 cooling-maps {
4392 map0 { 4191 map0 {
4393 trip 4192 trip = <&cpu7_alert0>;
4394 cooli 4193 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4395 4194 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4396 }; 4195 };
4397 map1 { 4196 map1 {
4398 trip 4197 trip = <&cpu7_alert1>;
4399 cooli 4198 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4400 4199 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4401 }; 4200 };
4402 }; 4201 };
4403 }; 4202 };
4404 4203
4405 cpu8_thermal: cpu8-thermal { 4204 cpu8_thermal: cpu8-thermal {
4406 polling-delay-passive 4205 polling-delay-passive = <250>;
>> 4206 polling-delay = <0>;
4407 4207
4408 thermal-sensors = <&t 4208 thermal-sensors = <&tsens0 11>;
4409 sustainable-power = < 4209 sustainable-power = <1425>;
4410 4210
4411 trips { 4211 trips {
4412 cpu8_alert0: 4212 cpu8_alert0: trip-point0 {
4413 tempe 4213 temperature = <90000>;
4414 hyste 4214 hysteresis = <2000>;
4415 type 4215 type = "passive";
4416 }; 4216 };
4417 4217
4418 cpu8_alert1: 4218 cpu8_alert1: trip-point1 {
4419 tempe 4219 temperature = <95000>;
4420 hyste 4220 hysteresis = <2000>;
4421 type 4221 type = "passive";
4422 }; 4222 };
4423 4223
4424 cpu8_crit: cp 4224 cpu8_crit: cpu-crit {
4425 tempe 4225 temperature = <110000>;
4426 hyste 4226 hysteresis = <1000>;
4427 type 4227 type = "critical";
4428 }; 4228 };
4429 }; 4229 };
4430 4230
4431 cooling-maps { 4231 cooling-maps {
4432 map0 { 4232 map0 {
4433 trip 4233 trip = <&cpu8_alert0>;
4434 cooli 4234 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4435 4235 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4436 }; 4236 };
4437 map1 { 4237 map1 {
4438 trip 4238 trip = <&cpu8_alert1>;
4439 cooli 4239 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4440 4240 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4441 }; 4241 };
4442 }; 4242 };
4443 }; 4243 };
4444 4244
4445 cpu9_thermal: cpu9-thermal { 4245 cpu9_thermal: cpu9-thermal {
4446 polling-delay-passive 4246 polling-delay-passive = <250>;
>> 4247 polling-delay = <0>;
4447 4248
4448 thermal-sensors = <&t 4249 thermal-sensors = <&tsens0 12>;
4449 sustainable-power = < 4250 sustainable-power = <1425>;
4450 4251
4451 trips { 4252 trips {
4452 cpu9_alert0: 4253 cpu9_alert0: trip-point0 {
4453 tempe 4254 temperature = <90000>;
4454 hyste 4255 hysteresis = <2000>;
4455 type 4256 type = "passive";
4456 }; 4257 };
4457 4258
4458 cpu9_alert1: 4259 cpu9_alert1: trip-point1 {
4459 tempe 4260 temperature = <95000>;
4460 hyste 4261 hysteresis = <2000>;
4461 type 4262 type = "passive";
4462 }; 4263 };
4463 4264
4464 cpu9_crit: cp 4265 cpu9_crit: cpu-crit {
4465 tempe 4266 temperature = <110000>;
4466 hyste 4267 hysteresis = <1000>;
4467 type 4268 type = "critical";
4468 }; 4269 };
4469 }; 4270 };
4470 4271
4471 cooling-maps { 4272 cooling-maps {
4472 map0 { 4273 map0 {
4473 trip 4274 trip = <&cpu9_alert0>;
4474 cooli 4275 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4475 4276 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4476 }; 4277 };
4477 map1 { 4278 map1 {
4478 trip 4279 trip = <&cpu9_alert1>;
4479 cooli 4280 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4480 4281 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4481 }; 4282 };
4482 }; 4283 };
4483 }; 4284 };
4484 4285
4485 aoss0-thermal { 4286 aoss0-thermal {
4486 polling-delay-passive 4287 polling-delay-passive = <250>;
>> 4288 polling-delay = <0>;
4487 4289
4488 thermal-sensors = <&t 4290 thermal-sensors = <&tsens0 0>;
4489 4291
4490 trips { 4292 trips {
4491 aoss0_alert0: 4293 aoss0_alert0: trip-point0 {
4492 tempe 4294 temperature = <90000>;
4493 hyste 4295 hysteresis = <2000>;
4494 type 4296 type = "hot";
4495 }; 4297 };
4496 4298
4497 aoss0_crit: a 4299 aoss0_crit: aoss0-crit {
4498 tempe 4300 temperature = <110000>;
4499 hyste 4301 hysteresis = <2000>;
4500 type 4302 type = "critical";
4501 }; 4303 };
4502 }; 4304 };
4503 }; 4305 };
4504 4306
4505 cpuss0-thermal { 4307 cpuss0-thermal {
4506 polling-delay-passive 4308 polling-delay-passive = <250>;
>> 4309 polling-delay = <0>;
4507 4310
4508 thermal-sensors = <&t 4311 thermal-sensors = <&tsens0 7>;
4509 4312
4510 trips { 4313 trips {
4511 cpuss0_alert0 4314 cpuss0_alert0: trip-point0 {
4512 tempe 4315 temperature = <90000>;
4513 hyste 4316 hysteresis = <2000>;
4514 type 4317 type = "hot";
4515 }; 4318 };
4516 cpuss0_crit: 4319 cpuss0_crit: cluster0-crit {
4517 tempe 4320 temperature = <110000>;
4518 hyste 4321 hysteresis = <2000>;
4519 type 4322 type = "critical";
4520 }; 4323 };
4521 }; 4324 };
4522 }; 4325 };
4523 4326
4524 cpuss1-thermal { 4327 cpuss1-thermal {
4525 polling-delay-passive 4328 polling-delay-passive = <250>;
>> 4329 polling-delay = <0>;
4526 4330
4527 thermal-sensors = <&t 4331 thermal-sensors = <&tsens0 8>;
4528 4332
4529 trips { 4333 trips {
4530 cpuss1_alert0 4334 cpuss1_alert0: trip-point0 {
4531 tempe 4335 temperature = <90000>;
4532 hyste 4336 hysteresis = <2000>;
4533 type 4337 type = "hot";
4534 }; 4338 };
4535 cpuss1_crit: 4339 cpuss1_crit: cluster0-crit {
4536 tempe 4340 temperature = <110000>;
4537 hyste 4341 hysteresis = <2000>;
4538 type 4342 type = "critical";
4539 }; 4343 };
4540 }; 4344 };
4541 }; 4345 };
4542 4346
4543 gpuss0-thermal { 4347 gpuss0-thermal {
4544 polling-delay-passive 4348 polling-delay-passive = <250>;
>> 4349 polling-delay = <0>;
4545 4350
4546 thermal-sensors = <&t 4351 thermal-sensors = <&tsens0 13>;
4547 4352
4548 trips { 4353 trips {
4549 gpuss0_alert0 4354 gpuss0_alert0: trip-point0 {
4550 tempe 4355 temperature = <95000>;
4551 hyste 4356 hysteresis = <2000>;
4552 type 4357 type = "passive";
4553 }; 4358 };
4554 4359
4555 gpuss0_crit: 4360 gpuss0_crit: gpuss0-crit {
4556 tempe 4361 temperature = <110000>;
4557 hyste 4362 hysteresis = <2000>;
4558 type 4363 type = "critical";
4559 }; 4364 };
4560 }; 4365 };
4561 4366
4562 cooling-maps { 4367 cooling-maps {
4563 map0 { 4368 map0 {
4564 trip 4369 trip = <&gpuss0_alert0>;
4565 cooli 4370 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4566 }; 4371 };
4567 }; 4372 };
4568 }; 4373 };
4569 4374
4570 gpuss1-thermal { 4375 gpuss1-thermal {
4571 polling-delay-passive 4376 polling-delay-passive = <250>;
>> 4377 polling-delay = <0>;
4572 4378
4573 thermal-sensors = <&t 4379 thermal-sensors = <&tsens0 14>;
4574 4380
4575 trips { 4381 trips {
4576 gpuss1_alert0 4382 gpuss1_alert0: trip-point0 {
4577 tempe 4383 temperature = <95000>;
4578 hyste 4384 hysteresis = <2000>;
4579 type 4385 type = "passive";
4580 }; 4386 };
4581 4387
4582 gpuss1_crit: 4388 gpuss1_crit: gpuss1-crit {
4583 tempe 4389 temperature = <110000>;
4584 hyste 4390 hysteresis = <2000>;
4585 type 4391 type = "critical";
4586 }; 4392 };
4587 }; 4393 };
4588 4394
4589 cooling-maps { 4395 cooling-maps {
4590 map0 { 4396 map0 {
4591 trip 4397 trip = <&gpuss1_alert0>;
4592 cooli 4398 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4593 }; 4399 };
4594 }; 4400 };
4595 }; 4401 };
4596 4402
4597 aoss1-thermal { 4403 aoss1-thermal {
4598 polling-delay-passive 4404 polling-delay-passive = <250>;
>> 4405 polling-delay = <0>;
4599 4406
4600 thermal-sensors = <&t 4407 thermal-sensors = <&tsens1 0>;
4601 4408
4602 trips { 4409 trips {
4603 aoss1_alert0: 4410 aoss1_alert0: trip-point0 {
4604 tempe 4411 temperature = <90000>;
4605 hyste 4412 hysteresis = <2000>;
4606 type 4413 type = "hot";
4607 }; 4414 };
4608 4415
4609 aoss1_crit: a 4416 aoss1_crit: aoss1-crit {
4610 tempe 4417 temperature = <110000>;
4611 hyste 4418 hysteresis = <2000>;
4612 type 4419 type = "critical";
4613 }; 4420 };
4614 }; 4421 };
4615 }; 4422 };
4616 4423
4617 cwlan-thermal { 4424 cwlan-thermal {
4618 polling-delay-passive 4425 polling-delay-passive = <250>;
>> 4426 polling-delay = <0>;
4619 4427
4620 thermal-sensors = <&t 4428 thermal-sensors = <&tsens1 1>;
4621 4429
4622 trips { 4430 trips {
4623 cwlan_alert0: 4431 cwlan_alert0: trip-point0 {
4624 tempe 4432 temperature = <90000>;
4625 hyste 4433 hysteresis = <2000>;
4626 type 4434 type = "hot";
4627 }; 4435 };
4628 4436
4629 cwlan_crit: c 4437 cwlan_crit: cwlan-crit {
4630 tempe 4438 temperature = <110000>;
4631 hyste 4439 hysteresis = <2000>;
4632 type 4440 type = "critical";
4633 }; 4441 };
4634 }; 4442 };
4635 }; 4443 };
4636 4444
4637 audio-thermal { 4445 audio-thermal {
4638 polling-delay-passive 4446 polling-delay-passive = <250>;
>> 4447 polling-delay = <0>;
4639 4448
4640 thermal-sensors = <&t 4449 thermal-sensors = <&tsens1 2>;
4641 4450
4642 trips { 4451 trips {
4643 audio_alert0: 4452 audio_alert0: trip-point0 {
4644 tempe 4453 temperature = <90000>;
4645 hyste 4454 hysteresis = <2000>;
4646 type 4455 type = "hot";
4647 }; 4456 };
4648 4457
4649 audio_crit: a 4458 audio_crit: audio-crit {
4650 tempe 4459 temperature = <110000>;
4651 hyste 4460 hysteresis = <2000>;
4652 type 4461 type = "critical";
4653 }; 4462 };
4654 }; 4463 };
4655 }; 4464 };
4656 4465
4657 ddr-thermal { 4466 ddr-thermal {
4658 polling-delay-passive 4467 polling-delay-passive = <250>;
>> 4468 polling-delay = <0>;
4659 4469
4660 thermal-sensors = <&t 4470 thermal-sensors = <&tsens1 3>;
4661 4471
4662 trips { 4472 trips {
4663 ddr_alert0: t 4473 ddr_alert0: trip-point0 {
4664 tempe 4474 temperature = <90000>;
4665 hyste 4475 hysteresis = <2000>;
4666 type 4476 type = "hot";
4667 }; 4477 };
4668 4478
4669 ddr_crit: ddr 4479 ddr_crit: ddr-crit {
4670 tempe 4480 temperature = <110000>;
4671 hyste 4481 hysteresis = <2000>;
4672 type 4482 type = "critical";
4673 }; 4483 };
4674 }; 4484 };
4675 }; 4485 };
4676 4486
4677 q6-hvx-thermal { 4487 q6-hvx-thermal {
4678 polling-delay-passive 4488 polling-delay-passive = <250>;
>> 4489 polling-delay = <0>;
4679 4490
4680 thermal-sensors = <&t 4491 thermal-sensors = <&tsens1 4>;
4681 4492
4682 trips { 4493 trips {
4683 q6_hvx_alert0 4494 q6_hvx_alert0: trip-point0 {
4684 tempe 4495 temperature = <90000>;
4685 hyste 4496 hysteresis = <2000>;
4686 type 4497 type = "hot";
4687 }; 4498 };
4688 4499
4689 q6_hvx_crit: 4500 q6_hvx_crit: q6-hvx-crit {
4690 tempe 4501 temperature = <110000>;
4691 hyste 4502 hysteresis = <2000>;
4692 type 4503 type = "critical";
4693 }; 4504 };
4694 }; 4505 };
4695 }; 4506 };
4696 4507
4697 camera-thermal { 4508 camera-thermal {
4698 polling-delay-passive 4509 polling-delay-passive = <250>;
>> 4510 polling-delay = <0>;
4699 4511
4700 thermal-sensors = <&t 4512 thermal-sensors = <&tsens1 5>;
4701 4513
4702 trips { 4514 trips {
4703 camera_alert0 4515 camera_alert0: trip-point0 {
4704 tempe 4516 temperature = <90000>;
4705 hyste 4517 hysteresis = <2000>;
4706 type 4518 type = "hot";
4707 }; 4519 };
4708 4520
4709 camera_crit: 4521 camera_crit: camera-crit {
4710 tempe 4522 temperature = <110000>;
4711 hyste 4523 hysteresis = <2000>;
4712 type 4524 type = "critical";
4713 }; 4525 };
4714 }; 4526 };
4715 }; 4527 };
4716 4528
4717 mdm-core-thermal { 4529 mdm-core-thermal {
4718 polling-delay-passive 4530 polling-delay-passive = <250>;
>> 4531 polling-delay = <0>;
4719 4532
4720 thermal-sensors = <&t 4533 thermal-sensors = <&tsens1 6>;
4721 4534
4722 trips { 4535 trips {
4723 mdm_alert0: t 4536 mdm_alert0: trip-point0 {
4724 tempe 4537 temperature = <90000>;
4725 hyste 4538 hysteresis = <2000>;
4726 type 4539 type = "hot";
4727 }; 4540 };
4728 4541
4729 mdm_crit: mdm 4542 mdm_crit: mdm-crit {
4730 tempe 4543 temperature = <110000>;
4731 hyste 4544 hysteresis = <2000>;
4732 type 4545 type = "critical";
4733 }; 4546 };
4734 }; 4547 };
4735 }; 4548 };
4736 4549
4737 mdm-dsp-thermal { 4550 mdm-dsp-thermal {
4738 polling-delay-passive 4551 polling-delay-passive = <250>;
>> 4552 polling-delay = <0>;
4739 4553
4740 thermal-sensors = <&t 4554 thermal-sensors = <&tsens1 7>;
4741 4555
4742 trips { 4556 trips {
4743 mdm_dsp_alert 4557 mdm_dsp_alert0: trip-point0 {
4744 tempe 4558 temperature = <90000>;
4745 hyste 4559 hysteresis = <2000>;
4746 type 4560 type = "hot";
4747 }; 4561 };
4748 4562
4749 mdm_dsp_crit: 4563 mdm_dsp_crit: mdm-dsp-crit {
4750 tempe 4564 temperature = <110000>;
4751 hyste 4565 hysteresis = <2000>;
4752 type 4566 type = "critical";
4753 }; 4567 };
4754 }; 4568 };
4755 }; 4569 };
4756 4570
4757 npu-thermal { 4571 npu-thermal {
4758 polling-delay-passive 4572 polling-delay-passive = <250>;
>> 4573 polling-delay = <0>;
4759 4574
4760 thermal-sensors = <&t 4575 thermal-sensors = <&tsens1 8>;
4761 4576
4762 trips { 4577 trips {
4763 npu_alert0: t 4578 npu_alert0: trip-point0 {
4764 tempe 4579 temperature = <90000>;
4765 hyste 4580 hysteresis = <2000>;
4766 type 4581 type = "hot";
4767 }; 4582 };
4768 4583
4769 npu_crit: npu 4584 npu_crit: npu-crit {
4770 tempe 4585 temperature = <110000>;
4771 hyste 4586 hysteresis = <2000>;
4772 type 4587 type = "critical";
4773 }; 4588 };
4774 }; 4589 };
4775 }; 4590 };
4776 4591
4777 video-thermal { 4592 video-thermal {
4778 polling-delay-passive 4593 polling-delay-passive = <250>;
>> 4594 polling-delay = <0>;
4779 4595
4780 thermal-sensors = <&t 4596 thermal-sensors = <&tsens1 9>;
4781 4597
4782 trips { 4598 trips {
4783 video_alert0: 4599 video_alert0: trip-point0 {
4784 tempe 4600 temperature = <90000>;
4785 hyste 4601 hysteresis = <2000>;
4786 type 4602 type = "hot";
4787 }; 4603 };
4788 4604
4789 video_crit: v 4605 video_crit: video-crit {
4790 tempe 4606 temperature = <110000>;
4791 hyste 4607 hysteresis = <2000>;
4792 type 4608 type = "critical";
4793 }; 4609 };
4794 }; 4610 };
4795 }; 4611 };
4796 }; 4612 };
4797 4613
4798 timer { 4614 timer {
4799 compatible = "arm,armv8-timer 4615 compatible = "arm,armv8-timer";
4800 interrupts = <GIC_PPI 1 IRQ_T 4616 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
4801 <GIC_PPI 2 IRQ_T 4617 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
4802 <GIC_PPI 3 IRQ_T 4618 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
4803 <GIC_PPI 0 IRQ_T 4619 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
4804 }; 4620 };
4805 }; 4621 };
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