1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * 3 *
4 * This file defines the common audio settings 4 * This file defines the common audio settings for the child boards
5 * using rt5682 codec. 5 * using rt5682 codec.
6 * 6 *
7 * Copyright 2022 Google LLC. 7 * Copyright 2022 Google LLC.
8 */ 8 */
9 9
10 / { 10 / {
11 /* BOARD-SPECIFIC TOP LEVEL NODES */ 11 /* BOARD-SPECIFIC TOP LEVEL NODES */
12 sound: sound { 12 sound: sound {
13 compatible = "google,sc7280-he 13 compatible = "google,sc7280-herobrine";
14 model = "sc7280-rt5682-max9836 14 model = "sc7280-rt5682-max98360a-1mic";
15 15
16 audio-routing = "Headphone Jac 16 audio-routing = "Headphone Jack", "HPOL",
17 "Headphone Jac 17 "Headphone Jack", "HPOR";
18 18
19 #address-cells = <1>; 19 #address-cells = <1>;
20 #size-cells = <0>; 20 #size-cells = <0>;
21 21
22 dai-link@0 { 22 dai-link@0 {
23 link-name = "MAX98360" 23 link-name = "MAX98360";
24 reg = <0>; 24 reg = <0>;
25 25
26 cpu { 26 cpu {
27 sound-dai = <& 27 sound-dai = <&lpass_cpu MI2S_SECONDARY>;
28 }; 28 };
29 29
30 codec { 30 codec {
31 sound-dai = <& 31 sound-dai = <&max98360a>;
32 }; 32 };
33 }; 33 };
34 34
35 dai-link@1 { 35 dai-link@1 {
36 link-name = "DisplayPo 36 link-name = "DisplayPort";
37 reg = <1>; 37 reg = <1>;
38 38
39 cpu { 39 cpu {
40 sound-dai = <& 40 sound-dai = <&lpass_cpu LPASS_DP_RX>;
41 }; 41 };
42 42
43 codec { 43 codec {
44 sound-dai = <& 44 sound-dai = <&mdss_dp>;
45 }; 45 };
46 }; 46 };
47 47
48 dai-link@2 { 48 dai-link@2 {
49 link-name = "ALC5682"; 49 link-name = "ALC5682";
50 reg = <2>; 50 reg = <2>;
51 51
52 cpu { 52 cpu {
53 sound-dai = <& 53 sound-dai = <&lpass_cpu MI2S_PRIMARY>;
54 }; 54 };
55 55
56 codec { 56 codec {
57 sound-dai = <& 57 sound-dai = <&alc5682 0 /* aif1 */>;
58 }; 58 };
59 }; 59 };
60 }; 60 };
61 }; 61 };
62 62
63 hp_i2c: &i2c2 { 63 hp_i2c: &i2c2 {
64 clock-frequency = <400000>; 64 clock-frequency = <400000>;
65 status = "okay"; 65 status = "okay";
66 66
67 alc5682: codec@1a { 67 alc5682: codec@1a {
68 compatible = "realtek,rt5682s" 68 compatible = "realtek,rt5682s";
69 reg = <0x1a>; 69 reg = <0x1a>;
70 pinctrl-names = "default"; 70 pinctrl-names = "default";
71 pinctrl-0 = <&hp_irq>; 71 pinctrl-0 = <&hp_irq>;
72 72
73 #sound-dai-cells = <1>; 73 #sound-dai-cells = <1>;
74 74
75 interrupt-parent = <&tlmm>; 75 interrupt-parent = <&tlmm>;
76 interrupts = <101 IRQ_TYPE_EDG 76 interrupts = <101 IRQ_TYPE_EDGE_BOTH>;
77 77
78 AVDD-supply = <&pp1800_alc5682 78 AVDD-supply = <&pp1800_alc5682>;
79 DBVDD-supply = <&pp1800_alc568 <<
80 LDO1-IN-supply = <&pp1800_alc5 <<
81 MICVDD-supply = <&pp3300_codec 79 MICVDD-supply = <&pp3300_codec>;
82 80
83 realtek,dmic1-data-pin = <1>; 81 realtek,dmic1-data-pin = <1>;
84 realtek,dmic1-clk-pin = <2>; 82 realtek,dmic1-clk-pin = <2>;
85 realtek,jd-src = <1>; 83 realtek,jd-src = <1>;
86 realtek,dmic-clk-rate-hz = <20 84 realtek,dmic-clk-rate-hz = <2048000>;
87 }; 85 };
88 }; 86 };
89 87
90 &lpass_cpu { 88 &lpass_cpu {
91 pinctrl-names = "default"; 89 pinctrl-names = "default";
92 pinctrl-0 = <&mi2s0_data0>, <&mi2s0_da 90 pinctrl-0 = <&mi2s0_data0>, <&mi2s0_data1>, <&mi2s0_mclk>, <&mi2s0_sclk>, <&mi2s0_ws>,
93 <&mi2s1_data0>, <&mi2s 91 <&mi2s1_data0>, <&mi2s1_sclk>, <&mi2s1_ws>;
94 92
95 #address-cells = <1>; 93 #address-cells = <1>;
96 #size-cells = <0>; 94 #size-cells = <0>;
97 95
98 status = "okay"; 96 status = "okay";
99 97
100 dai-link@0 { 98 dai-link@0 {
101 reg = <MI2S_PRIMARY>; 99 reg = <MI2S_PRIMARY>;
102 qcom,playback-sd-lines = <1>; 100 qcom,playback-sd-lines = <1>;
103 qcom,capture-sd-lines = <0>; 101 qcom,capture-sd-lines = <0>;
104 }; 102 };
105 103
106 dai-link@1 { 104 dai-link@1 {
107 reg = <MI2S_SECONDARY>; 105 reg = <MI2S_SECONDARY>;
108 qcom,playback-sd-lines = <0>; 106 qcom,playback-sd-lines = <0>;
109 }; 107 };
110 108
111 dai-link@5 { 109 dai-link@5 {
112 reg = <LPASS_DP_RX>; 110 reg = <LPASS_DP_RX>;
113 }; 111 };
114 }; 112 };
115 113
116 /* PINCTRL - ADDITIONS TO NODES IN PARENT DEVI 114 /* PINCTRL - ADDITIONS TO NODES IN PARENT DEVICE TREE FILES */
117 115
118 &mi2s0_data0 { 116 &mi2s0_data0 {
119 drive-strength = <6>; 117 drive-strength = <6>;
120 bias-disable; 118 bias-disable;
121 }; 119 };
122 120
123 &mi2s0_data1 { 121 &mi2s0_data1 {
124 drive-strength = <6>; 122 drive-strength = <6>;
125 bias-disable; 123 bias-disable;
126 }; 124 };
127 125
128 &mi2s0_mclk { 126 &mi2s0_mclk {
129 drive-strength = <6>; 127 drive-strength = <6>;
130 bias-disable; 128 bias-disable;
131 }; 129 };
132 130
133 &mi2s0_sclk { 131 &mi2s0_sclk {
134 drive-strength = <6>; 132 drive-strength = <6>;
135 bias-disable; 133 bias-disable;
136 }; 134 };
137 135
138 &mi2s0_ws { 136 &mi2s0_ws {
139 drive-strength = <6>; 137 drive-strength = <6>;
140 bias-disable; 138 bias-disable;
141 }; 139 };
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