1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Google Herobrine dts fragment for LTE SKUs 3 * Google Herobrine dts fragment for LTE SKUs
4 * 4 *
5 * Copyright 2022 Google LLC. 5 * Copyright 2022 Google LLC.
6 */ 6 */
7 /* Modem setup is different on Chrome setups t 7 /* Modem setup is different on Chrome setups than typical Qualcomm setup */
8 8
9 / { <<
10 reserved-memory { <<
11 mba_mem: memory@9c700000 { <<
12 reg = <0x0 0x9c700000 <<
13 no-map; <<
14 }; <<
15 <<
16 mdata_mem: mpss-metadata { <<
17 alloc-ranges = <0x0 0x <<
18 size = <0x0 0x4000>; <<
19 no-map; <<
20 }; <<
21 }; <<
22 }; <<
23 <<
24 &ipa { <<
25 qcom,gsi-loader = "modem"; <<
26 status = "okay"; <<
27 }; <<
28 <<
29 &remoteproc_mpss { 9 &remoteproc_mpss {
30 compatible = "qcom,sc7280-mss-pil"; 10 compatible = "qcom,sc7280-mss-pil";
31 reg = <0 0x04080000 0 0x10000>, <0 0x0 <<
32 reg-names = "qdsp6", "rmb"; <<
33 <<
34 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, <<
35 <&gcc GCC_MSS_OFFLINE_AXI_CLK <<
36 <&gcc GCC_MSS_SNOC_AXI_CLK>, <<
37 <&rpmhcc RPMH_PKA_CLK>, <<
38 <&rpmhcc RPMH_CXO_CLK>; <<
39 clock-names = "iface", "offline", "sno <<
40 <<
41 iommus = <&apps_smmu 0x124 0x0>, <&app 11 iommus = <&apps_smmu 0x124 0x0>, <&apps_smmu 0x488 0x7>;
42 interconnects = <&mc_virt MASTER_LLCC 12 interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>;
43 memory-region = <&mba_mem>, <&mpss_mem !! 13 memory-region = <&mba_mem>, <&mpss_mem>;
44 firmware-name = "qcom/sc7280-herobrine 14 firmware-name = "qcom/sc7280-herobrine/modem/mba.mbn",
45 "qcom/sc7280-herobrine 15 "qcom/sc7280-herobrine/modem/qdsp6sw.mbn";
46 <<
47 resets = <&aoss_reset AOSS_CC_MSS_REST <<
48 <&pdc_reset PDC_MODEM_SYNC_RE <<
49 reset-names = "mss_restart", "pdc_rese <<
50 <<
51 qcom,halt-regs = <&tcsr_1 0x3000 0x500 <<
52 qcom,ext-regs = <&tcsr_2 0x10000 0x100 <<
53 qcom,qaccept-regs = <&tcsr_1 0x3030 0x <<
54 <<
55 status = "okay"; 16 status = "okay";
56 }; <<
57 <<
58 /* Increase the size from 2.5MB to 8MB */ <<
59 &rmtfs_mem { <<
60 reg = <0x0 0x9c900000 0x0 0x800000>; <<
61 }; 17 };
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