1 // SPDX-License-Identifier: BSD-3-Clause
2 /*
3 * Copyright (c) 2021, The Linux Foundation. A
4 * Copyright (c) 2022, Linaro Limited
5 */
6
7 #include <dt-bindings/clock/qcom,dispcc-sc8280
8 #include <dt-bindings/clock/qcom,gcc-sc8280xp.
9 #include <dt-bindings/clock/qcom,gpucc-sc8280x
10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/clock/qcom,sc8280xp-camc
12 #include <dt-bindings/clock/qcom,sc8280xp-lpas
13 #include <dt-bindings/interconnect/qcom,osm-l3
14 #include <dt-bindings/interconnect/qcom,sc8280
15 #include <dt-bindings/interrupt-controller/arm
16 #include <dt-bindings/mailbox/qcom-ipcc.h>
17 #include <dt-bindings/phy/phy-qcom-qmp.h>
18 #include <dt-bindings/power/qcom-rpmpd.h>
19 #include <dt-bindings/soc/qcom,gpr.h>
20 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
21 #include <dt-bindings/sound/qcom,q6afe.h>
22 #include <dt-bindings/thermal/thermal.h>
23
24 / {
25 interrupt-parent = <&intc>;
26
27 #address-cells = <2>;
28 #size-cells = <2>;
29
30 clocks {
31 xo_board_clk: xo-board-clk {
32 compatible = "fixed-cl
33 #clock-cells = <0>;
34 };
35
36 sleep_clk: sleep-clk {
37 compatible = "fixed-cl
38 #clock-cells = <0>;
39 clock-frequency = <327
40 };
41 };
42
43 cpus {
44 #address-cells = <2>;
45 #size-cells = <0>;
46
47 CPU0: cpu@0 {
48 device_type = "cpu";
49 compatible = "arm,cort
50 reg = <0x0 0x0>;
51 clocks = <&cpufreq_hw
52 enable-method = "psci"
53 capacity-dmips-mhz = <
54 dynamic-power-coeffici
55 next-level-cache = <&L
56 power-domains = <&CPU_
57 power-domain-names = "
58 qcom,freq-domain = <&c
59 operating-points-v2 =
60 interconnects = <&epss
61 #cooling-cells = <2>;
62 L2_0: l2-cache {
63 compatible = "
64 cache-level =
65 cache-unified;
66 next-level-cac
67 L3_0: l3-cache
68 compat
69 cache-
70 cache-
71 };
72 };
73 };
74
75 CPU1: cpu@100 {
76 device_type = "cpu";
77 compatible = "arm,cort
78 reg = <0x0 0x100>;
79 clocks = <&cpufreq_hw
80 enable-method = "psci"
81 capacity-dmips-mhz = <
82 dynamic-power-coeffici
83 next-level-cache = <&L
84 power-domains = <&CPU_
85 power-domain-names = "
86 qcom,freq-domain = <&c
87 operating-points-v2 =
88 interconnects = <&epss
89 #cooling-cells = <2>;
90 L2_100: l2-cache {
91 compatible = "
92 cache-level =
93 cache-unified;
94 next-level-cac
95 };
96 };
97
98 CPU2: cpu@200 {
99 device_type = "cpu";
100 compatible = "arm,cort
101 reg = <0x0 0x200>;
102 clocks = <&cpufreq_hw
103 enable-method = "psci"
104 capacity-dmips-mhz = <
105 dynamic-power-coeffici
106 next-level-cache = <&L
107 power-domains = <&CPU_
108 power-domain-names = "
109 qcom,freq-domain = <&c
110 operating-points-v2 =
111 interconnects = <&epss
112 #cooling-cells = <2>;
113 L2_200: l2-cache {
114 compatible = "
115 cache-level =
116 cache-unified;
117 next-level-cac
118 };
119 };
120
121 CPU3: cpu@300 {
122 device_type = "cpu";
123 compatible = "arm,cort
124 reg = <0x0 0x300>;
125 clocks = <&cpufreq_hw
126 enable-method = "psci"
127 capacity-dmips-mhz = <
128 dynamic-power-coeffici
129 next-level-cache = <&L
130 power-domains = <&CPU_
131 power-domain-names = "
132 qcom,freq-domain = <&c
133 operating-points-v2 =
134 interconnects = <&epss
135 #cooling-cells = <2>;
136 L2_300: l2-cache {
137 compatible = "
138 cache-level =
139 cache-unified;
140 next-level-cac
141 };
142 };
143
144 CPU4: cpu@400 {
145 device_type = "cpu";
146 compatible = "arm,cort
147 reg = <0x0 0x400>;
148 clocks = <&cpufreq_hw
149 enable-method = "psci"
150 capacity-dmips-mhz = <
151 dynamic-power-coeffici
152 next-level-cache = <&L
153 power-domains = <&CPU_
154 power-domain-names = "
155 qcom,freq-domain = <&c
156 operating-points-v2 =
157 interconnects = <&epss
158 #cooling-cells = <2>;
159 L2_400: l2-cache {
160 compatible = "
161 cache-level =
162 cache-unified;
163 next-level-cac
164 };
165 };
166
167 CPU5: cpu@500 {
168 device_type = "cpu";
169 compatible = "arm,cort
170 reg = <0x0 0x500>;
171 clocks = <&cpufreq_hw
172 enable-method = "psci"
173 capacity-dmips-mhz = <
174 dynamic-power-coeffici
175 next-level-cache = <&L
176 power-domains = <&CPU_
177 power-domain-names = "
178 qcom,freq-domain = <&c
179 operating-points-v2 =
180 interconnects = <&epss
181 #cooling-cells = <2>;
182 L2_500: l2-cache {
183 compatible = "
184 cache-level =
185 cache-unified;
186 next-level-cac
187 };
188 };
189
190 CPU6: cpu@600 {
191 device_type = "cpu";
192 compatible = "arm,cort
193 reg = <0x0 0x600>;
194 clocks = <&cpufreq_hw
195 enable-method = "psci"
196 capacity-dmips-mhz = <
197 dynamic-power-coeffici
198 next-level-cache = <&L
199 power-domains = <&CPU_
200 power-domain-names = "
201 qcom,freq-domain = <&c
202 operating-points-v2 =
203 interconnects = <&epss
204 #cooling-cells = <2>;
205 L2_600: l2-cache {
206 compatible = "
207 cache-level =
208 cache-unified;
209 next-level-cac
210 };
211 };
212
213 CPU7: cpu@700 {
214 device_type = "cpu";
215 compatible = "arm,cort
216 reg = <0x0 0x700>;
217 clocks = <&cpufreq_hw
218 enable-method = "psci"
219 capacity-dmips-mhz = <
220 dynamic-power-coeffici
221 next-level-cache = <&L
222 power-domains = <&CPU_
223 power-domain-names = "
224 qcom,freq-domain = <&c
225 operating-points-v2 =
226 interconnects = <&epss
227 #cooling-cells = <2>;
228 L2_700: l2-cache {
229 compatible = "
230 cache-level =
231 cache-unified;
232 next-level-cac
233 };
234 };
235
236 cpu-map {
237 cluster0 {
238 core0 {
239 cpu =
240 };
241
242 core1 {
243 cpu =
244 };
245
246 core2 {
247 cpu =
248 };
249
250 core3 {
251 cpu =
252 };
253
254 core4 {
255 cpu =
256 };
257
258 core5 {
259 cpu =
260 };
261
262 core6 {
263 cpu =
264 };
265
266 core7 {
267 cpu =
268 };
269 };
270 };
271
272 idle-states {
273 entry-method = "psci";
274
275 LITTLE_CPU_SLEEP_0: cp
276 compatible = "
277 idle-state-nam
278 arm,psci-suspe
279 entry-latency-
280 exit-latency-u
281 min-residency-
282 local-timer-st
283 };
284
285 BIG_CPU_SLEEP_0: cpu-s
286 compatible = "
287 idle-state-nam
288 arm,psci-suspe
289 entry-latency-
290 exit-latency-u
291 min-residency-
292 local-timer-st
293 };
294 };
295
296 domain-idle-states {
297 CLUSTER_SLEEP_0: clust
298 compatible = "
299 arm,psci-suspe
300 entry-latency-
301 exit-latency-u
302 min-residency-
303 };
304 };
305 };
306
307 firmware {
308 scm: scm {
309 compatible = "qcom,scm
310 interconnects = <&aggr
311 qcom,dload-mode = <&tc
312 };
313 };
314
315 aggre1_noc: interconnect-aggre1-noc {
316 compatible = "qcom,sc8280xp-ag
317 #interconnect-cells = <2>;
318 qcom,bcm-voters = <&apps_bcm_v
319 };
320
321 aggre2_noc: interconnect-aggre2-noc {
322 compatible = "qcom,sc8280xp-ag
323 #interconnect-cells = <2>;
324 qcom,bcm-voters = <&apps_bcm_v
325 };
326
327 clk_virt: interconnect-clk-virt {
328 compatible = "qcom,sc8280xp-cl
329 #interconnect-cells = <2>;
330 qcom,bcm-voters = <&apps_bcm_v
331 };
332
333 config_noc: interconnect-config-noc {
334 compatible = "qcom,sc8280xp-co
335 #interconnect-cells = <2>;
336 qcom,bcm-voters = <&apps_bcm_v
337 };
338
339 dc_noc: interconnect-dc-noc {
340 compatible = "qcom,sc8280xp-dc
341 #interconnect-cells = <2>;
342 qcom,bcm-voters = <&apps_bcm_v
343 };
344
345 gem_noc: interconnect-gem-noc {
346 compatible = "qcom,sc8280xp-ge
347 #interconnect-cells = <2>;
348 qcom,bcm-voters = <&apps_bcm_v
349 };
350
351 lpass_noc: interconnect-lpass-ag-noc {
352 compatible = "qcom,sc8280xp-lp
353 #interconnect-cells = <2>;
354 qcom,bcm-voters = <&apps_bcm_v
355 };
356
357 mc_virt: interconnect-mc-virt {
358 compatible = "qcom,sc8280xp-mc
359 #interconnect-cells = <2>;
360 qcom,bcm-voters = <&apps_bcm_v
361 };
362
363 mmss_noc: interconnect-mmss-noc {
364 compatible = "qcom,sc8280xp-mm
365 #interconnect-cells = <2>;
366 qcom,bcm-voters = <&apps_bcm_v
367 };
368
369 nspa_noc: interconnect-nspa-noc {
370 compatible = "qcom,sc8280xp-ns
371 #interconnect-cells = <2>;
372 qcom,bcm-voters = <&apps_bcm_v
373 };
374
375 nspb_noc: interconnect-nspb-noc {
376 compatible = "qcom,sc8280xp-ns
377 #interconnect-cells = <2>;
378 qcom,bcm-voters = <&apps_bcm_v
379 };
380
381 system_noc: interconnect-system-noc {
382 compatible = "qcom,sc8280xp-sy
383 #interconnect-cells = <2>;
384 qcom,bcm-voters = <&apps_bcm_v
385 };
386
387 memory@80000000 {
388 device_type = "memory";
389 /* We expect the bootloader to
390 reg = <0x0 0x80000000 0x0 0x0>
391 };
392
393 cpu0_opp_table: opp-table-cpu0 {
394 compatible = "operating-points
395 opp-shared;
396
397 opp-300000000 {
398 opp-hz = /bits/ 64 <30
399 opp-peak-kBps = <(3000
400 };
401 opp-403200000 {
402 opp-hz = /bits/ 64 <40
403 opp-peak-kBps = <(3840
404 };
405 opp-499200000 {
406 opp-hz = /bits/ 64 <49
407 opp-peak-kBps = <(4800
408 };
409 opp-595200000 {
410 opp-hz = /bits/ 64 <59
411 opp-peak-kBps = <(5760
412 };
413 opp-691200000 {
414 opp-hz = /bits/ 64 <69
415 opp-peak-kBps = <(6720
416 };
417 opp-806400000 {
418 opp-hz = /bits/ 64 <80
419 opp-peak-kBps = <(7680
420 };
421 opp-902400000 {
422 opp-hz = /bits/ 64 <90
423 opp-peak-kBps = <(8640
424 };
425 opp-1017600000 {
426 opp-hz = /bits/ 64 <10
427 opp-peak-kBps = <(9600
428 };
429 opp-1113600000 {
430 opp-hz = /bits/ 64 <11
431 opp-peak-kBps = <(1075
432 };
433 opp-1209600000 {
434 opp-hz = /bits/ 64 <12
435 opp-peak-kBps = <(1171
436 };
437 opp-1324800000 {
438 opp-hz = /bits/ 64 <13
439 opp-peak-kBps = <(1267
440 };
441 opp-1440000000 {
442 opp-hz = /bits/ 64 <14
443 opp-peak-kBps = <(1363
444 };
445 opp-1555200000 {
446 opp-hz = /bits/ 64 <15
447 opp-peak-kBps = <(1536
448 };
449 opp-1670400000 {
450 opp-hz = /bits/ 64 <16
451 opp-peak-kBps = <(1612
452 };
453 opp-1785600000 {
454 opp-hz = /bits/ 64 <17
455 opp-peak-kBps = <(1689
456 };
457 opp-1881600000 {
458 opp-hz = /bits/ 64 <18
459 opp-peak-kBps = <(1689
460 };
461 opp-1996800000 {
462 opp-hz = /bits/ 64 <19
463 opp-peak-kBps = <(1689
464 };
465 opp-2112000000 {
466 opp-hz = /bits/ 64 <21
467 opp-peak-kBps = <(1689
468 };
469 opp-2227200000 {
470 opp-hz = /bits/ 64 <22
471 opp-peak-kBps = <(1689
472 };
473 opp-2342400000 {
474 opp-hz = /bits/ 64 <23
475 opp-peak-kBps = <(1689
476 };
477 opp-2438400000 {
478 opp-hz = /bits/ 64 <24
479 opp-peak-kBps = <(1689
480 };
481 };
482
483 cpu4_opp_table: opp-table-cpu4 {
484 compatible = "operating-points
485 opp-shared;
486
487 opp-825600000 {
488 opp-hz = /bits/ 64 <82
489 opp-peak-kBps = <(7680
490 };
491 opp-940800000 {
492 opp-hz = /bits/ 64 <94
493 opp-peak-kBps = <(8640
494 };
495 opp-1056000000 {
496 opp-hz = /bits/ 64 <10
497 opp-peak-kBps = <(9600
498 };
499 opp-1171200000 {
500 opp-hz = /bits/ 64 <11
501 opp-peak-kBps = <(1171
502 };
503 opp-1286400000 {
504 opp-hz = /bits/ 64 <12
505 opp-peak-kBps = <(1267
506 };
507 opp-1401600000 {
508 opp-hz = /bits/ 64 <14
509 opp-peak-kBps = <(1363
510 };
511 opp-1516800000 {
512 opp-hz = /bits/ 64 <15
513 opp-peak-kBps = <(1459
514 };
515 opp-1632000000 {
516 opp-hz = /bits/ 64 <16
517 opp-peak-kBps = <(1612
518 };
519 opp-1747200000 {
520 opp-hz = /bits/ 64 <17
521 opp-peak-kBps = <(1689
522 };
523 opp-1862400000 {
524 opp-hz = /bits/ 64 <18
525 opp-peak-kBps = <(1689
526 };
527 opp-1977600000 {
528 opp-hz = /bits/ 64 <19
529 opp-peak-kBps = <(1689
530 };
531 opp-2073600000 {
532 opp-hz = /bits/ 64 <20
533 opp-peak-kBps = <(1689
534 };
535 opp-2169600000 {
536 opp-hz = /bits/ 64 <21
537 opp-peak-kBps = <(1689
538 };
539 opp-2284800000 {
540 opp-hz = /bits/ 64 <22
541 opp-peak-kBps = <(1689
542 };
543 opp-2400000000 {
544 opp-hz = /bits/ 64 <24
545 opp-peak-kBps = <(1689
546 };
547 opp-2496000000 {
548 opp-hz = /bits/ 64 <24
549 opp-peak-kBps = <(1689
550 };
551 opp-2592000000 {
552 opp-hz = /bits/ 64 <25
553 opp-peak-kBps = <(1689
554 };
555 opp-2688000000 {
556 opp-hz = /bits/ 64 <26
557 opp-peak-kBps = <(1689
558 };
559 opp-2803200000 {
560 opp-hz = /bits/ 64 <28
561 opp-peak-kBps = <(1689
562 };
563 opp-2899200000 {
564 opp-hz = /bits/ 64 <28
565 opp-peak-kBps = <(1689
566 };
567 opp-2995200000 {
568 opp-hz = /bits/ 64 <29
569 opp-peak-kBps = <(1689
570 };
571 };
572
573 qup_opp_table_100mhz: opp-table-qup100
574 compatible = "operating-points
575
576 opp-75000000 {
577 opp-hz = /bits/ 64 <75
578 required-opps = <&rpmh
579 };
580
581 opp-100000000 {
582 opp-hz = /bits/ 64 <10
583 required-opps = <&rpmh
584 };
585 };
586
587 pmu {
588 compatible = "arm,armv8-pmuv3"
589 interrupts = <GIC_PPI 7 IRQ_TY
590 };
591
592 psci {
593 compatible = "arm,psci-1.0";
594 method = "smc";
595
596 CPU_PD0: power-domain-cpu0 {
597 #power-domain-cells =
598 power-domains = <&CLUS
599 domain-idle-states = <
600 };
601
602 CPU_PD1: power-domain-cpu1 {
603 #power-domain-cells =
604 power-domains = <&CLUS
605 domain-idle-states = <
606 };
607
608 CPU_PD2: power-domain-cpu2 {
609 #power-domain-cells =
610 power-domains = <&CLUS
611 domain-idle-states = <
612 };
613
614 CPU_PD3: power-domain-cpu3 {
615 #power-domain-cells =
616 power-domains = <&CLUS
617 domain-idle-states = <
618 };
619
620 CPU_PD4: power-domain-cpu4 {
621 #power-domain-cells =
622 power-domains = <&CLUS
623 domain-idle-states = <
624 };
625
626 CPU_PD5: power-domain-cpu5 {
627 #power-domain-cells =
628 power-domains = <&CLUS
629 domain-idle-states = <
630 };
631
632 CPU_PD6: power-domain-cpu6 {
633 #power-domain-cells =
634 power-domains = <&CLUS
635 domain-idle-states = <
636 };
637
638 CPU_PD7: power-domain-cpu7 {
639 #power-domain-cells =
640 power-domains = <&CLUS
641 domain-idle-states = <
642 };
643
644 CLUSTER_PD: power-domain-cpu-c
645 #power-domain-cells =
646 domain-idle-states = <
647 };
648 };
649
650 reserved-memory {
651 #address-cells = <2>;
652 #size-cells = <2>;
653 ranges;
654
655 reserved-region@80000000 {
656 reg = <0 0x80000000 0
657 no-map;
658 };
659
660 cmd_db: cmd-db-region@80860000
661 compatible = "qcom,cmd
662 reg = <0 0x80860000 0
663 no-map;
664 };
665
666 reserved-region@80880000 {
667 reg = <0 0x80880000 0
668 no-map;
669 };
670
671 smem_mem: smem-region@80900000
672 compatible = "qcom,sme
673 reg = <0 0x80900000 0
674 no-map;
675 hwlocks = <&tcsr_mutex
676 };
677
678 reserved-region@80b00000 {
679 reg = <0 0x80b00000 0
680 no-map;
681 };
682
683 reserved-region@83b00000 {
684 reg = <0 0x83b00000 0
685 no-map;
686 };
687
688 reserved-region@85b00000 {
689 reg = <0 0x85b00000 0
690 no-map;
691 };
692
693 pil_adsp_mem: adsp-region@86c0
694 reg = <0 0x86c00000 0
695 no-map;
696 };
697
698 pil_nsp0_mem: cdsp0-region@8a1
699 reg = <0 0x8a100000 0
700 no-map;
701 };
702
703 pil_nsp1_mem: cdsp1-region@8c6
704 reg = <0 0x8c600000 0
705 no-map;
706 };
707
708 reserved-region@aeb00000 {
709 reg = <0 0xaeb00000 0
710 no-map;
711 };
712 };
713
714 smp2p-adsp {
715 compatible = "qcom,smp2p";
716 qcom,smem = <443>, <429>;
717 interrupts-extended = <&ipcc I
718 I
719 I
720 mboxes = <&ipcc IPCC_CLIENT_LP
721 IPCC_MPROC_SIG
722
723 qcom,local-pid = <0>;
724 qcom,remote-pid = <2>;
725
726 smp2p_adsp_out: master-kernel
727 qcom,entry-name = "mas
728 #qcom,smem-state-cells
729 };
730
731 smp2p_adsp_in: slave-kernel {
732 qcom,entry-name = "sla
733 interrupt-controller;
734 #interrupt-cells = <2>
735 };
736 };
737
738 smp2p-nsp0 {
739 compatible = "qcom,smp2p";
740 qcom,smem = <94>, <432>;
741 interrupts-extended = <&ipcc I
742 I
743 I
744 mboxes = <&ipcc IPCC_CLIENT_CD
745 IPCC_MPROC_SIG
746
747 qcom,local-pid = <0>;
748 qcom,remote-pid = <5>;
749
750 smp2p_nsp0_out: master-kernel
751 qcom,entry-name = "mas
752 #qcom,smem-state-cells
753 };
754
755 smp2p_nsp0_in: slave-kernel {
756 qcom,entry-name = "sla
757 interrupt-controller;
758 #interrupt-cells = <2>
759 };
760 };
761
762 smp2p-nsp1 {
763 compatible = "qcom,smp2p";
764 qcom,smem = <617>, <616>;
765 interrupts-extended = <&ipcc I
766 I
767 I
768 mboxes = <&ipcc IPCC_CLIENT_NS
769 IPCC_MPROC_SIG
770
771 qcom,local-pid = <0>;
772 qcom,remote-pid = <12>;
773
774 smp2p_nsp1_out: master-kernel
775 qcom,entry-name = "mas
776 #qcom,smem-state-cells
777 };
778
779 smp2p_nsp1_in: slave-kernel {
780 qcom,entry-name = "sla
781 interrupt-controller;
782 #interrupt-cells = <2>
783 };
784 };
785
786 soc: soc@0 {
787 compatible = "simple-bus";
788 #address-cells = <2>;
789 #size-cells = <2>;
790 ranges = <0 0 0 0 0x10 0>;
791 dma-ranges = <0 0 0 0 0x10 0>;
792
793 ethernet0: ethernet@20000 {
794 compatible = "qcom,sc8
795 reg = <0x0 0x00020000
796 <0x0 0x00036000
797 reg-names = "stmmaceth
798
799 clocks = <&gcc GCC_EMA
800 <&gcc GCC_EMA
801 <&gcc GCC_EMA
802 <&gcc GCC_EMA
803 clock-names = "stmmace
804 "pclk",
805 "ptp_ref
806 "rgmii";
807
808 interrupts = <GIC_SPI
809 <GIC_SPI
810 interrupt-names = "mac
811
812 iommus = <&apps_smmu 0
813 power-domains = <&gcc
814
815 snps,tso;
816 snps,pbl = <32>;
817 rx-fifo-depth = <4096>
818 tx-fifo-depth = <4096>
819
820 status = "disabled";
821 };
822
823 gcc: clock-controller@100000 {
824 compatible = "qcom,gcc
825 reg = <0x0 0x00100000
826 #clock-cells = <1>;
827 #reset-cells = <1>;
828 #power-domain-cells =
829 clocks = <&rpmhcc RPMH
830 <&sleep_clk>,
831 <0>,
832 <0>,
833 <0>,
834 <0>,
835 <0>,
836 <0>,
837 <&usb_0_qmpph
838 <0>,
839 <0>,
840 <0>,
841 <0>,
842 <0>,
843 <0>,
844 <0>,
845 <&usb_1_qmpph
846 <0>,
847 <0>,
848 <0>,
849 <0>,
850 <0>,
851 <0>,
852 <0>,
853 <0>,
854 <0>,
855 <&pcie2a_phy>
856 <&pcie2b_phy>
857 <&pcie3a_phy>
858 <&pcie3b_phy>
859 <&pcie4_phy>,
860 <0>,
861 <0>;
862 power-domains = <&rpmh
863 };
864
865 ipcc: mailbox@408000 {
866 compatible = "qcom,sc8
867 reg = <0 0x00408000 0
868 interrupts = <GIC_SPI
869 interrupt-controller;
870 #interrupt-cells = <3>
871 #mbox-cells = <2>;
872 };
873
874 qfprom: efuse@784000 {
875 compatible = "qcom,sc8
876 reg = <0 0x00784000 0
877 #address-cells = <1>;
878 #size-cells = <1>;
879
880 gpu_speed_bin: gpu-spe
881 reg = <0x18b 0
882 bits = <5 3>;
883 };
884 };
885
886 qup2: geniqup@8c0000 {
887 compatible = "qcom,gen
888 reg = <0 0x008c0000 0
889 clocks = <&gcc GCC_QUP
890 <&gcc GCC_QUP
891 clock-names = "m-ahb",
892 iommus = <&apps_smmu 0
893
894 #address-cells = <2>;
895 #size-cells = <2>;
896 ranges;
897
898 status = "disabled";
899
900 i2c16: i2c@880000 {
901 compatible = "
902 reg = <0 0x008
903 #address-cells
904 #size-cells =
905 clocks = <&gcc
906 clock-names =
907 interrupts = <
908 power-domains
909 interconnects
910
911
912 interconnect-n
913 status = "disa
914 };
915
916 spi16: spi@880000 {
917 compatible = "
918 reg = <0 0x008
919 #address-cells
920 #size-cells =
921 clocks = <&gcc
922 clock-names =
923 interrupts = <
924 power-domains
925 interconnects
926
927
928 interconnect-n
929 status = "disa
930 };
931
932 i2c17: i2c@884000 {
933 compatible = "
934 reg = <0 0x008
935 #address-cells
936 #size-cells =
937 clocks = <&gcc
938 clock-names =
939 interrupts = <
940 power-domains
941 interconnects
942
943
944 interconnect-n
945 status = "disa
946 };
947
948 spi17: spi@884000 {
949 compatible = "
950 reg = <0 0x008
951 #address-cells
952 #size-cells =
953 clocks = <&gcc
954 clock-names =
955 interrupts = <
956 power-domains
957 interconnects
958
959
960 interconnect-n
961 status = "disa
962 };
963
964 uart17: serial@884000
965 compatible = "
966 reg = <0 0x008
967 clocks = <&gcc
968 clock-names =
969 interrupts = <
970 operating-poin
971 power-domains
972 interconnects
973
974 interconnect-n
975 status = "disa
976 };
977
978 i2c18: i2c@888000 {
979 compatible = "
980 reg = <0 0x008
981 #address-cells
982 #size-cells =
983 clocks = <&gcc
984 clock-names =
985 interrupts = <
986 power-domains
987 interconnects
988
989
990 interconnect-n
991 status = "disa
992 };
993
994 spi18: spi@888000 {
995 compatible = "
996 reg = <0 0x008
997 #address-cells
998 #size-cells =
999 clocks = <&gcc
1000 clock-names =
1001 interrupts =
1002 power-domains
1003 interconnects
1004
1005
1006 interconnect-
1007 status = "dis
1008 };
1009
1010 i2c19: i2c@88c000 {
1011 compatible =
1012 reg = <0 0x00
1013 #address-cell
1014 #size-cells =
1015 clocks = <&gc
1016 clock-names =
1017 interrupts =
1018 power-domains
1019 interconnects
1020
1021
1022 interconnect-
1023 status = "dis
1024 };
1025
1026 spi19: spi@88c000 {
1027 compatible =
1028 reg = <0 0x00
1029 #address-cell
1030 #size-cells =
1031 clocks = <&gc
1032 clock-names =
1033 interrupts =
1034 power-domains
1035 interconnects
1036
1037
1038 interconnect-
1039 status = "dis
1040 };
1041
1042 i2c20: i2c@890000 {
1043 compatible =
1044 reg = <0 0x00
1045 #address-cell
1046 #size-cells =
1047 clocks = <&gc
1048 clock-names =
1049 interrupts =
1050 power-domains
1051 interconnects
1052
1053
1054 interconnect-
1055 status = "dis
1056 };
1057
1058 spi20: spi@890000 {
1059 compatible =
1060 reg = <0 0x00
1061 #address-cell
1062 #size-cells =
1063 clocks = <&gc
1064 clock-names =
1065 interrupts =
1066 power-domains
1067 interconnects
1068
1069
1070 interconnect-
1071 status = "dis
1072 };
1073
1074 i2c21: i2c@894000 {
1075 compatible =
1076 reg = <0 0x00
1077 clock-names =
1078 clocks = <&gc
1079 interrupts =
1080 #address-cell
1081 #size-cells =
1082 power-domains
1083 interconnects
1084
1085
1086 interconnect-
1087 status = "dis
1088 };
1089
1090 spi21: spi@894000 {
1091 compatible =
1092 reg = <0 0x00
1093 #address-cell
1094 #size-cells =
1095 clocks = <&gc
1096 clock-names =
1097 interrupts =
1098 power-domains
1099 interconnects
1100
1101
1102 interconnect-
1103 status = "dis
1104 };
1105
1106 i2c22: i2c@898000 {
1107 compatible =
1108 reg = <0 0x00
1109 #address-cell
1110 #size-cells =
1111 clock-names =
1112 clocks = <&gc
1113 interrupts =
1114 power-domains
1115 interconnects
1116
1117
1118 interconnect-
1119 status = "dis
1120 };
1121
1122 spi22: spi@898000 {
1123 compatible =
1124 reg = <0 0x00
1125 #address-cell
1126 #size-cells =
1127 clocks = <&gc
1128 clock-names =
1129 interrupts =
1130 power-domains
1131 interconnects
1132
1133
1134 interconnect-
1135 status = "dis
1136 };
1137
1138 i2c23: i2c@89c000 {
1139 compatible =
1140 reg = <0 0x00
1141 #address-cell
1142 #size-cells =
1143 clock-names =
1144 clocks = <&gc
1145 interrupts =
1146 power-domains
1147 interconnects
1148
1149
1150 interconnect-
1151 status = "dis
1152 };
1153
1154 spi23: spi@89c000 {
1155 compatible =
1156 reg = <0 0x00
1157 #address-cell
1158 #size-cells =
1159 clocks = <&gc
1160 clock-names =
1161 interrupts =
1162 power-domains
1163 interconnects
1164
1165
1166 interconnect-
1167 status = "dis
1168 };
1169 };
1170
1171 qup0: geniqup@9c0000 {
1172 compatible = "qcom,ge
1173 reg = <0 0x009c0000 0
1174 clocks = <&gcc GCC_QU
1175 <&gcc GCC_QU
1176 clock-names = "m-ahb"
1177 iommus = <&apps_smmu
1178
1179 #address-cells = <2>;
1180 #size-cells = <2>;
1181 ranges;
1182
1183 status = "disabled";
1184
1185 i2c0: i2c@980000 {
1186 compatible =
1187 reg = <0 0x00
1188 #address-cell
1189 #size-cells =
1190 clock-names =
1191 clocks = <&gc
1192 interrupts =
1193 power-domains
1194 interconnects
1195
1196
1197 interconnect-
1198 status = "dis
1199 };
1200
1201 spi0: spi@980000 {
1202 compatible =
1203 reg = <0 0x00
1204 #address-cell
1205 #size-cells =
1206 clocks = <&gc
1207 clock-names =
1208 interrupts =
1209 power-domains
1210 interconnects
1211
1212
1213 interconnect-
1214 status = "dis
1215 };
1216
1217 i2c1: i2c@984000 {
1218 compatible =
1219 reg = <0 0x00
1220 #address-cell
1221 #size-cells =
1222 clock-names =
1223 clocks = <&gc
1224 interrupts =
1225 power-domains
1226 interconnects
1227
1228
1229 interconnect-
1230 status = "dis
1231 };
1232
1233 spi1: spi@984000 {
1234 compatible =
1235 reg = <0 0x00
1236 #address-cell
1237 #size-cells =
1238 clocks = <&gc
1239 clock-names =
1240 interrupts =
1241 power-domains
1242 interconnects
1243
1244
1245 interconnect-
1246 status = "dis
1247 };
1248
1249 i2c2: i2c@988000 {
1250 compatible =
1251 reg = <0 0x00
1252 #address-cell
1253 #size-cells =
1254 clock-names =
1255 clocks = <&gc
1256 interrupts =
1257 power-domains
1258 interconnects
1259
1260
1261 interconnect-
1262 status = "dis
1263 };
1264
1265 spi2: spi@988000 {
1266 compatible =
1267 reg = <0 0x00
1268 #address-cell
1269 #size-cells =
1270 clocks = <&gc
1271 clock-names =
1272 interrupts =
1273 power-domains
1274 interconnects
1275
1276
1277 interconnect-
1278 status = "dis
1279 };
1280
1281 uart2: serial@988000
1282 compatible =
1283 reg = <0 0x00
1284 clocks = <&gc
1285 clock-names =
1286 interrupts =
1287 operating-poi
1288 power-domains
1289 interconnects
1290
1291 interconnect-
1292 status = "dis
1293 };
1294
1295 i2c3: i2c@98c000 {
1296 compatible =
1297 reg = <0 0x00
1298 #address-cell
1299 #size-cells =
1300 clock-names =
1301 clocks = <&gc
1302 interrupts =
1303 power-domains
1304 interconnects
1305
1306
1307 interconnect-
1308 status = "dis
1309 };
1310
1311 spi3: spi@98c000 {
1312 compatible =
1313 reg = <0 0x00
1314 #address-cell
1315 #size-cells =
1316 clocks = <&gc
1317 clock-names =
1318 interrupts =
1319 power-domains
1320 interconnects
1321
1322
1323 interconnect-
1324 status = "dis
1325 };
1326
1327 i2c4: i2c@990000 {
1328 compatible =
1329 reg = <0 0x00
1330 clock-names =
1331 clocks = <&gc
1332 interrupts =
1333 #address-cell
1334 #size-cells =
1335 power-domains
1336 interconnects
1337
1338
1339 interconnect-
1340 status = "dis
1341 };
1342
1343 spi4: spi@990000 {
1344 compatible =
1345 reg = <0 0x00
1346 #address-cell
1347 #size-cells =
1348 clocks = <&gc
1349 clock-names =
1350 interrupts =
1351 power-domains
1352 interconnects
1353
1354
1355 interconnect-
1356 status = "dis
1357 };
1358
1359 i2c5: i2c@994000 {
1360 compatible =
1361 reg = <0 0x00
1362 #address-cell
1363 #size-cells =
1364 clock-names =
1365 clocks = <&gc
1366 interrupts =
1367 power-domains
1368 interconnects
1369
1370
1371 interconnect-
1372 status = "dis
1373 };
1374
1375 spi5: spi@994000 {
1376 compatible =
1377 reg = <0 0x00
1378 #address-cell
1379 #size-cells =
1380 clocks = <&gc
1381 clock-names =
1382 interrupts =
1383 power-domains
1384 interconnects
1385
1386
1387 interconnect-
1388 status = "dis
1389 };
1390
1391 i2c6: i2c@998000 {
1392 compatible =
1393 reg = <0 0x00
1394 #address-cell
1395 #size-cells =
1396 clock-names =
1397 clocks = <&gc
1398 interrupts =
1399 power-domains
1400 interconnects
1401
1402
1403 interconnect-
1404 status = "dis
1405 };
1406
1407 spi6: spi@998000 {
1408 compatible =
1409 reg = <0 0x00
1410 #address-cell
1411 #size-cells =
1412 clocks = <&gc
1413 clock-names =
1414 interrupts =
1415 power-domains
1416 interconnects
1417
1418
1419 interconnect-
1420 status = "dis
1421 };
1422
1423 i2c7: i2c@99c000 {
1424 compatible =
1425 reg = <0 0x00
1426 #address-cell
1427 #size-cells =
1428 clock-names =
1429 clocks = <&gc
1430 interrupts =
1431 power-domains
1432 interconnects
1433
1434
1435 interconnect-
1436 status = "dis
1437 };
1438
1439 spi7: spi@99c000 {
1440 compatible =
1441 reg = <0 0x00
1442 #address-cell
1443 #size-cells =
1444 clocks = <&gc
1445 clock-names =
1446 interrupts =
1447 power-domains
1448 interconnects
1449
1450
1451 interconnect-
1452 status = "dis
1453 };
1454 };
1455
1456 qup1: geniqup@ac0000 {
1457 compatible = "qcom,ge
1458 reg = <0 0x00ac0000 0
1459 clocks = <&gcc GCC_QU
1460 <&gcc GCC_QU
1461 clock-names = "m-ahb"
1462 iommus = <&apps_smmu
1463
1464 #address-cells = <2>;
1465 #size-cells = <2>;
1466 ranges;
1467
1468 status = "disabled";
1469
1470 i2c8: i2c@a80000 {
1471 compatible =
1472 reg = <0 0x00
1473 #address-cell
1474 #size-cells =
1475 clocks = <&gc
1476 clock-names =
1477 interrupts =
1478 power-domains
1479 interconnects
1480
1481
1482 interconnect-
1483 status = "dis
1484 };
1485
1486 spi8: spi@a80000 {
1487 compatible =
1488 reg = <0 0x00
1489 #address-cell
1490 #size-cells =
1491 clocks = <&gc
1492 clock-names =
1493 interrupts =
1494 power-domains
1495 interconnects
1496
1497
1498 interconnect-
1499 status = "dis
1500 };
1501
1502 i2c9: i2c@a84000 {
1503 compatible =
1504 reg = <0 0x00
1505 #address-cell
1506 #size-cells =
1507 clocks = <&gc
1508 clock-names =
1509 interrupts =
1510 power-domains
1511 interconnects
1512
1513
1514 interconnect-
1515 status = "dis
1516 };
1517
1518 spi9: spi@a84000 {
1519 compatible =
1520 reg = <0 0x00
1521 #address-cell
1522 #size-cells =
1523 clocks = <&gc
1524 clock-names =
1525 interrupts =
1526 power-domains
1527 interconnects
1528
1529
1530 interconnect-
1531 status = "dis
1532 };
1533
1534 i2c10: i2c@a88000 {
1535 compatible =
1536 reg = <0 0x00
1537 #address-cell
1538 #size-cells =
1539 clocks = <&gc
1540 clock-names =
1541 interrupts =
1542 power-domains
1543 interconnects
1544
1545
1546 interconnect-
1547 status = "dis
1548 };
1549
1550 spi10: spi@a88000 {
1551 compatible =
1552 reg = <0 0x00
1553 #address-cell
1554 #size-cells =
1555 clocks = <&gc
1556 clock-names =
1557 interrupts =
1558 power-domains
1559 interconnects
1560
1561
1562 interconnect-
1563 status = "dis
1564 };
1565
1566 i2c11: i2c@a8c000 {
1567 compatible =
1568 reg = <0 0x00
1569 #address-cell
1570 #size-cells =
1571 clocks = <&gc
1572 clock-names =
1573 interrupts =
1574 power-domains
1575 interconnects
1576
1577
1578 interconnect-
1579 status = "dis
1580 };
1581
1582 spi11: spi@a8c000 {
1583 compatible =
1584 reg = <0 0x00
1585 #address-cell
1586 #size-cells =
1587 clocks = <&gc
1588 clock-names =
1589 interrupts =
1590 power-domains
1591 interconnects
1592
1593
1594 interconnect-
1595 status = "dis
1596 };
1597
1598 i2c12: i2c@a90000 {
1599 compatible =
1600 reg = <0 0x00
1601 #address-cell
1602 #size-cells =
1603 clocks = <&gc
1604 clock-names =
1605 interrupts =
1606 power-domains
1607 interconnects
1608
1609
1610 interconnect-
1611 status = "dis
1612 };
1613
1614 spi12: spi@a90000 {
1615 compatible =
1616 reg = <0 0x00
1617 #address-cell
1618 #size-cells =
1619 clocks = <&gc
1620 clock-names =
1621 interrupts =
1622 power-domains
1623 interconnects
1624
1625
1626 interconnect-
1627 status = "dis
1628 };
1629
1630 i2c13: i2c@a94000 {
1631 compatible =
1632 reg = <0 0x00
1633 #address-cell
1634 #size-cells =
1635 clocks = <&gc
1636 clock-names =
1637 interrupts =
1638 power-domains
1639 interconnects
1640
1641
1642 interconnect-
1643 status = "dis
1644 };
1645
1646 spi13: spi@a94000 {
1647 compatible =
1648 reg = <0 0x00
1649 #address-cell
1650 #size-cells =
1651 clocks = <&gc
1652 clock-names =
1653 interrupts =
1654 power-domains
1655 interconnects
1656
1657
1658 interconnect-
1659 status = "dis
1660 };
1661
1662 i2c14: i2c@a98000 {
1663 compatible =
1664 reg = <0 0x00
1665 #address-cell
1666 #size-cells =
1667 clocks = <&gc
1668 clock-names =
1669 interrupts =
1670 power-domains
1671 interconnects
1672
1673
1674 interconnect-
1675 status = "dis
1676 };
1677
1678 spi14: spi@a98000 {
1679 compatible =
1680 reg = <0 0x00
1681 #address-cell
1682 #size-cells =
1683 clocks = <&gc
1684 clock-names =
1685 interrupts =
1686 power-domains
1687 interconnects
1688
1689
1690 interconnect-
1691 status = "dis
1692 };
1693
1694 i2c15: i2c@a9c000 {
1695 compatible =
1696 reg = <0 0x00
1697 #address-cell
1698 #size-cells =
1699 clocks = <&gc
1700 clock-names =
1701 interrupts =
1702 power-domains
1703 interconnects
1704
1705
1706 interconnect-
1707 status = "dis
1708 };
1709
1710 spi15: spi@a9c000 {
1711 compatible =
1712 reg = <0 0x00
1713 #address-cell
1714 #size-cells =
1715 clocks = <&gc
1716 clock-names =
1717 interrupts =
1718 power-domains
1719 interconnects
1720
1721
1722 interconnect-
1723 status = "dis
1724 };
1725 };
1726
1727 rng: rng@10d3000 {
1728 compatible = "qcom,pr
1729 reg = <0 0x010d3000 0
1730 clocks = <&rpmhcc RPM
1731 clock-names = "core";
1732 };
1733
1734 pcie4: pcie@1c00000 {
1735 device_type = "pci";
1736 compatible = "qcom,pc
1737 reg = <0x0 0x01c00000
1738 <0x0 0x30000000
1739 <0x0 0x30000f20
1740 <0x0 0x30001000
1741 <0x0 0x30100000
1742 <0x0 0x01c03000
1743 reg-names = "parf", "
1744 #address-cells = <3>;
1745 #size-cells = <2>;
1746 ranges = <0x01000000
1747 <0x02000000
1748 bus-range = <0x00 0xf
1749
1750 dma-coherent;
1751
1752 linux,pci-domain = <6
1753 num-lanes = <1>;
1754
1755 msi-map = <0x0 &its 0
1756
1757 interrupts = <GIC_SPI
1758 <GIC_SPI
1759 <GIC_SPI
1760 <GIC_SPI
1761 interrupt-names = "ms
1762
1763 #interrupt-cells = <1
1764 interrupt-map-mask =
1765 interrupt-map = <0 0
1766 <0 0
1767 <0 0
1768 <0 0
1769
1770 clocks = <&gcc GCC_PC
1771 <&gcc GCC_PC
1772 <&gcc GCC_PC
1773 <&gcc GCC_PC
1774 <&gcc GCC_PC
1775 <&gcc GCC_DD
1776 <&gcc GCC_AG
1777 <&gcc GCC_AG
1778 <&gcc GCC_CN
1779 clock-names = "aux",
1780 "cfg",
1781 "bus_ma
1782 "bus_sl
1783 "slave_
1784 "ddrss_
1785 "noc_ag
1786 "noc_ag
1787 "cnoc_q
1788
1789 assigned-clocks = <&g
1790 assigned-clock-rates
1791
1792 interconnects = <&agg
1793 <&gem
1794 interconnect-names =
1795
1796 resets = <&gcc GCC_PC
1797 reset-names = "pci";
1798
1799 power-domains = <&gcc
1800 required-opps = <&rpm
1801
1802 phys = <&pcie4_phy>;
1803 phy-names = "pciephy"
1804
1805 status = "disabled";
1806
1807 pcie4_port0: pcie@0 {
1808 device_type =
1809 reg = <0x0 0x
1810 bus-range = <
1811
1812 #address-cell
1813 #size-cells =
1814 ranges;
1815 };
1816 };
1817
1818 pcie4_phy: phy@1c06000 {
1819 compatible = "qcom,sc
1820 reg = <0x0 0x01c06000
1821
1822 clocks = <&gcc GCC_PC
1823 <&gcc GCC_PC
1824 <&gcc GCC_PC
1825 <&gcc GCC_PC
1826 <&gcc GCC_PC
1827 <&gcc GCC_PC
1828 clock-names = "aux",
1829 "pipe",
1830
1831 assigned-clocks = <&g
1832 assigned-clock-rates
1833
1834 power-domains = <&gcc
1835
1836 resets = <&gcc GCC_PC
1837 reset-names = "phy";
1838
1839 #clock-cells = <0>;
1840 clock-output-names =
1841
1842 #phy-cells = <0>;
1843
1844 status = "disabled";
1845 };
1846
1847 pcie3b: pcie@1c08000 {
1848 device_type = "pci";
1849 compatible = "qcom,pc
1850 reg = <0x0 0x01c08000
1851 <0x0 0x32000000
1852 <0x0 0x32000f20
1853 <0x0 0x32001000
1854 <0x0 0x32100000
1855 <0x0 0x01c0b000
1856 reg-names = "parf", "
1857 #address-cells = <3>;
1858 #size-cells = <2>;
1859 ranges = <0x01000000
1860 <0x02000000
1861 bus-range = <0x00 0xf
1862
1863 dma-coherent;
1864
1865 linux,pci-domain = <5
1866 num-lanes = <2>;
1867
1868 msi-map = <0x0 &its 0
1869
1870 interrupts = <GIC_SPI
1871 <GIC_SPI
1872 <GIC_SPI
1873 <GIC_SPI
1874 interrupt-names = "ms
1875
1876 #interrupt-cells = <1
1877 interrupt-map-mask =
1878 interrupt-map = <0 0
1879 <0 0
1880 <0 0
1881 <0 0
1882
1883 clocks = <&gcc GCC_PC
1884 <&gcc GCC_PC
1885 <&gcc GCC_PC
1886 <&gcc GCC_PC
1887 <&gcc GCC_PC
1888 <&gcc GCC_DD
1889 <&gcc GCC_AG
1890 <&gcc GCC_AG
1891 clock-names = "aux",
1892 "cfg",
1893 "bus_ma
1894 "bus_sl
1895 "slave_
1896 "ddrss_
1897 "noc_ag
1898 "noc_ag
1899
1900 assigned-clocks = <&g
1901 assigned-clock-rates
1902
1903 interconnects = <&agg
1904 <&gem
1905 interconnect-names =
1906
1907 resets = <&gcc GCC_PC
1908 reset-names = "pci";
1909
1910 power-domains = <&gcc
1911 required-opps = <&rpm
1912
1913 phys = <&pcie3b_phy>;
1914 phy-names = "pciephy"
1915
1916 status = "disabled";
1917
1918 pcie3b_port0: pcie@0
1919 device_type =
1920 reg = <0x0 0x
1921 bus-range = <
1922
1923 #address-cell
1924 #size-cells =
1925 ranges;
1926 };
1927 };
1928
1929 pcie3b_phy: phy@1c0e000 {
1930 compatible = "qcom,sc
1931 reg = <0x0 0x01c0e000
1932
1933 clocks = <&gcc GCC_PC
1934 <&gcc GCC_PC
1935 <&gcc GCC_PC
1936 <&gcc GCC_PC
1937 <&gcc GCC_PC
1938 <&gcc GCC_PC
1939 clock-names = "aux",
1940 "pipe",
1941
1942 assigned-clocks = <&g
1943 assigned-clock-rates
1944
1945 power-domains = <&gcc
1946
1947 resets = <&gcc GCC_PC
1948 reset-names = "phy";
1949
1950 #clock-cells = <0>;
1951 clock-output-names =
1952
1953 #phy-cells = <0>;
1954
1955 status = "disabled";
1956 };
1957
1958 pcie3a: pcie@1c10000 {
1959 device_type = "pci";
1960 compatible = "qcom,pc
1961 reg = <0x0 0x01c10000
1962 <0x0 0x34000000
1963 <0x0 0x34000f20
1964 <0x0 0x34001000
1965 <0x0 0x34100000
1966 <0x0 0x01c13000
1967 reg-names = "parf", "
1968 #address-cells = <3>;
1969 #size-cells = <2>;
1970 ranges = <0x01000000
1971 <0x02000000
1972 bus-range = <0x00 0xf
1973
1974 dma-coherent;
1975
1976 linux,pci-domain = <4
1977 num-lanes = <4>;
1978
1979 msi-map = <0x0 &its 0
1980
1981 interrupts = <GIC_SPI
1982 <GIC_SPI
1983 <GIC_SPI
1984 <GIC_SPI
1985 interrupt-names = "ms
1986
1987 #interrupt-cells = <1
1988 interrupt-map-mask =
1989 interrupt-map = <0 0
1990 <0 0
1991 <0 0
1992 <0 0
1993
1994 clocks = <&gcc GCC_PC
1995 <&gcc GCC_PC
1996 <&gcc GCC_PC
1997 <&gcc GCC_PC
1998 <&gcc GCC_PC
1999 <&gcc GCC_DD
2000 <&gcc GCC_AG
2001 <&gcc GCC_AG
2002 clock-names = "aux",
2003 "cfg",
2004 "bus_ma
2005 "bus_sl
2006 "slave_
2007 "ddrss_
2008 "noc_ag
2009 "noc_ag
2010
2011 assigned-clocks = <&g
2012 assigned-clock-rates
2013
2014 interconnects = <&agg
2015 <&gem
2016 interconnect-names =
2017
2018 resets = <&gcc GCC_PC
2019 reset-names = "pci";
2020
2021 power-domains = <&gcc
2022 required-opps = <&rpm
2023
2024 phys = <&pcie3a_phy>;
2025 phy-names = "pciephy"
2026
2027 status = "disabled";
2028
2029 pcie3a_port0: pcie@0
2030 device_type =
2031 reg = <0x0 0x
2032 bus-range = <
2033
2034 #address-cell
2035 #size-cells =
2036 ranges;
2037 };
2038 };
2039
2040 pcie3a_phy: phy@1c14000 {
2041 compatible = "qcom,sc
2042 reg = <0x0 0x01c14000
2043 <0x0 0x01c16000
2044
2045 clocks = <&gcc GCC_PC
2046 <&gcc GCC_PC
2047 <&gcc GCC_PC
2048 <&gcc GCC_PC
2049 <&gcc GCC_PC
2050 <&gcc GCC_PC
2051 clock-names = "aux",
2052 "pipe",
2053
2054 assigned-clocks = <&g
2055 assigned-clock-rates
2056
2057 power-domains = <&gcc
2058
2059 resets = <&gcc GCC_PC
2060 reset-names = "phy";
2061
2062 qcom,4ln-config-sel =
2063
2064 #clock-cells = <0>;
2065 clock-output-names =
2066
2067 #phy-cells = <0>;
2068
2069 status = "disabled";
2070 };
2071
2072 pcie2b: pcie@1c18000 {
2073 device_type = "pci";
2074 compatible = "qcom,pc
2075 reg = <0x0 0x01c18000
2076 <0x0 0x38000000
2077 <0x0 0x38000f20
2078 <0x0 0x38001000
2079 <0x0 0x38100000
2080 <0x0 0x01c1b000
2081 reg-names = "parf", "
2082 #address-cells = <3>;
2083 #size-cells = <2>;
2084 ranges = <0x01000000
2085 <0x02000000
2086 bus-range = <0x00 0xf
2087
2088 dma-coherent;
2089
2090 linux,pci-domain = <3
2091 num-lanes = <2>;
2092
2093 msi-map = <0x0 &its 0
2094
2095 interrupts = <GIC_SPI
2096 <GIC_SPI
2097 <GIC_SPI
2098 <GIC_SPI
2099 interrupt-names = "ms
2100
2101 #interrupt-cells = <1
2102 interrupt-map-mask =
2103 interrupt-map = <0 0
2104 <0 0
2105 <0 0
2106 <0 0
2107
2108 clocks = <&gcc GCC_PC
2109 <&gcc GCC_PC
2110 <&gcc GCC_PC
2111 <&gcc GCC_PC
2112 <&gcc GCC_PC
2113 <&gcc GCC_DD
2114 <&gcc GCC_AG
2115 <&gcc GCC_AG
2116 clock-names = "aux",
2117 "cfg",
2118 "bus_ma
2119 "bus_sl
2120 "slave_
2121 "ddrss_
2122 "noc_ag
2123 "noc_ag
2124
2125 assigned-clocks = <&g
2126 assigned-clock-rates
2127
2128 interconnects = <&agg
2129 <&gem
2130 interconnect-names =
2131
2132 resets = <&gcc GCC_PC
2133 reset-names = "pci";
2134
2135 power-domains = <&gcc
2136 required-opps = <&rpm
2137
2138 phys = <&pcie2b_phy>;
2139 phy-names = "pciephy"
2140
2141 status = "disabled";
2142
2143 pcie2b_port0: pcie@0
2144 device_type =
2145 reg = <0x0 0x
2146 bus-range = <
2147
2148 #address-cell
2149 #size-cells =
2150 ranges;
2151 };
2152 };
2153
2154 pcie2b_phy: phy@1c1e000 {
2155 compatible = "qcom,sc
2156 reg = <0x0 0x01c1e000
2157
2158 clocks = <&gcc GCC_PC
2159 <&gcc GCC_PC
2160 <&gcc GCC_PC
2161 <&gcc GCC_PC
2162 <&gcc GCC_PC
2163 <&gcc GCC_PC
2164 clock-names = "aux",
2165 "pipe",
2166
2167 assigned-clocks = <&g
2168 assigned-clock-rates
2169
2170 power-domains = <&gcc
2171
2172 resets = <&gcc GCC_PC
2173 reset-names = "phy";
2174
2175 #clock-cells = <0>;
2176 clock-output-names =
2177
2178 #phy-cells = <0>;
2179
2180 status = "disabled";
2181 };
2182
2183 pcie2a: pcie@1c20000 {
2184 device_type = "pci";
2185 compatible = "qcom,pc
2186 reg = <0x0 0x01c20000
2187 <0x0 0x3c000000
2188 <0x0 0x3c000f20
2189 <0x0 0x3c001000
2190 <0x0 0x3c100000
2191 <0x0 0x01c23000
2192 reg-names = "parf", "
2193 #address-cells = <3>;
2194 #size-cells = <2>;
2195 ranges = <0x01000000
2196 <0x02000000
2197 bus-range = <0x00 0xf
2198
2199 dma-coherent;
2200
2201 linux,pci-domain = <2
2202 num-lanes = <4>;
2203
2204 msi-map = <0x0 &its 0
2205
2206 interrupts = <GIC_SPI
2207 <GIC_SPI
2208 <GIC_SPI
2209 <GIC_SPI
2210 interrupt-names = "ms
2211
2212 #interrupt-cells = <1
2213 interrupt-map-mask =
2214 interrupt-map = <0 0
2215 <0 0
2216 <0 0
2217 <0 0
2218
2219 clocks = <&gcc GCC_PC
2220 <&gcc GCC_PC
2221 <&gcc GCC_PC
2222 <&gcc GCC_PC
2223 <&gcc GCC_PC
2224 <&gcc GCC_DD
2225 <&gcc GCC_AG
2226 <&gcc GCC_AG
2227 clock-names = "aux",
2228 "cfg",
2229 "bus_ma
2230 "bus_sl
2231 "slave_
2232 "ddrss_
2233 "noc_ag
2234 "noc_ag
2235
2236 assigned-clocks = <&g
2237 assigned-clock-rates
2238
2239 interconnects = <&agg
2240 <&gem
2241 interconnect-names =
2242
2243 resets = <&gcc GCC_PC
2244 reset-names = "pci";
2245
2246 power-domains = <&gcc
2247 required-opps = <&rpm
2248
2249 phys = <&pcie2a_phy>;
2250 phy-names = "pciephy"
2251
2252 status = "disabled";
2253
2254 pcie2a_port0: pcie@0
2255 device_type =
2256 reg = <0x0 0x
2257 bus-range = <
2258
2259 #address-cell
2260 #size-cells =
2261 ranges;
2262 };
2263 };
2264
2265 pcie2a_phy: phy@1c24000 {
2266 compatible = "qcom,sc
2267 reg = <0x0 0x01c24000
2268 <0x0 0x01c26000
2269
2270 clocks = <&gcc GCC_PC
2271 <&gcc GCC_PC
2272 <&gcc GCC_PC
2273 <&gcc GCC_PC
2274 <&gcc GCC_PC
2275 <&gcc GCC_PC
2276 clock-names = "aux",
2277 "pipe",
2278
2279 assigned-clocks = <&g
2280 assigned-clock-rates
2281
2282 power-domains = <&gcc
2283
2284 resets = <&gcc GCC_PC
2285 reset-names = "phy";
2286
2287 qcom,4ln-config-sel =
2288
2289 #clock-cells = <0>;
2290 clock-output-names =
2291
2292 #phy-cells = <0>;
2293
2294 status = "disabled";
2295 };
2296
2297 ufs_mem_hc: ufs@1d84000 {
2298 compatible = "qcom,sc
2299 "jedec,u
2300 reg = <0 0x01d84000 0
2301 interrupts = <GIC_SPI
2302 phys = <&ufs_mem_phy>
2303 phy-names = "ufsphy";
2304 lanes-per-direction =
2305 #reset-cells = <1>;
2306 resets = <&gcc GCC_UF
2307 reset-names = "rst";
2308
2309 power-domains = <&gcc
2310 required-opps = <&rpm
2311
2312 iommus = <&apps_smmu
2313 dma-coherent;
2314
2315 clocks = <&gcc GCC_UF
2316 <&gcc GCC_AG
2317 <&gcc GCC_UF
2318 <&gcc GCC_UF
2319 <&gcc GCC_UF
2320 <&gcc GCC_UF
2321 <&gcc GCC_UF
2322 <&gcc GCC_UF
2323 clock-names = "core_c
2324 "bus_ag
2325 "iface_
2326 "core_c
2327 "ref_cl
2328 "tx_lan
2329 "rx_lan
2330 "rx_lan
2331 freq-table-hz = <7500
2332 <0 0>
2333 <0 0>
2334 <7500
2335 <0 0>
2336 <0 0>
2337 <0 0>
2338 <0 0>
2339 status = "disabled";
2340 };
2341
2342 ufs_mem_phy: phy@1d87000 {
2343 compatible = "qcom,sc
2344 reg = <0 0x01d87000 0
2345
2346 clocks = <&rpmhcc RPM
2347 <&gcc GCC_UF
2348 <&gcc GCC_UF
2349 clock-names = "ref",
2350 "ref_au
2351 "qref";
2352
2353 power-domains = <&gcc
2354
2355 resets = <&ufs_mem_hc
2356 reset-names = "ufsphy
2357
2358 #phy-cells = <0>;
2359
2360 status = "disabled";
2361 };
2362
2363 ufs_card_hc: ufs@1da4000 {
2364 compatible = "qcom,sc
2365 "jedec,u
2366 reg = <0 0x01da4000 0
2367 interrupts = <GIC_SPI
2368 phys = <&ufs_card_phy
2369 phy-names = "ufsphy";
2370 lanes-per-direction =
2371 #reset-cells = <1>;
2372 resets = <&gcc GCC_UF
2373 reset-names = "rst";
2374
2375 power-domains = <&gcc
2376
2377 iommus = <&apps_smmu
2378 dma-coherent;
2379
2380 clocks = <&gcc GCC_UF
2381 <&gcc GCC_AG
2382 <&gcc GCC_UF
2383 <&gcc GCC_UF
2384 <&gcc GCC_UF
2385 <&gcc GCC_UF
2386 <&gcc GCC_UF
2387 <&gcc GCC_UF
2388 clock-names = "core_c
2389 "bus_ag
2390 "iface_
2391 "core_c
2392 "ref_cl
2393 "tx_lan
2394 "rx_lan
2395 "rx_lan
2396 freq-table-hz = <7500
2397 <0 0>
2398 <0 0>
2399 <7500
2400 <0 0>
2401 <0 0>
2402 <0 0>
2403 <0 0>
2404 status = "disabled";
2405 };
2406
2407 ufs_card_phy: phy@1da7000 {
2408 compatible = "qcom,sc
2409 reg = <0 0x01da7000 0
2410
2411 clocks = <&rpmhcc RPM
2412 <&gcc GCC_UF
2413 <&gcc GCC_UF
2414 clock-names = "ref",
2415 "ref_au
2416 "qref";
2417
2418 power-domains = <&gcc
2419
2420 resets = <&ufs_card_h
2421 reset-names = "ufsphy
2422
2423 #phy-cells = <0>;
2424
2425 status = "disabled";
2426 };
2427
2428 tcsr_mutex: hwlock@1f40000 {
2429 compatible = "qcom,tc
2430 reg = <0x0 0x01f40000
2431 #hwlock-cells = <1>;
2432 };
2433
2434 tcsr: syscon@1fc0000 {
2435 compatible = "qcom,sc
2436 reg = <0x0 0x01fc0000
2437 };
2438
2439 gpu: gpu@3d00000 {
2440 compatible = "qcom,ad
2441
2442 reg = <0 0x03d00000 0
2443 <0 0x03d9e000 0
2444 <0 0x03d61000 0
2445 reg-names = "kgsl_3d0
2446 "cx_mem",
2447 "cx_dbgc"
2448 interrupts = <GIC_SPI
2449 iommus = <&gpu_smmu 0
2450 operating-points-v2 =
2451
2452 qcom,gmu = <&gmu>;
2453 interconnects = <&gem
2454 interconnect-names =
2455 #cooling-cells = <2>;
2456
2457 status = "disabled";
2458
2459 gpu_opp_table: opp-ta
2460 compatible =
2461
2462 opp-270000000
2463 opp-h
2464 opp-l
2465 opp-p
2466 };
2467
2468 opp-410000000
2469 opp-h
2470 opp-l
2471 opp-p
2472 };
2473
2474 opp-500000000
2475 opp-h
2476 opp-l
2477 opp-p
2478 };
2479
2480 opp-547000000
2481 opp-h
2482 opp-l
2483 opp-p
2484 };
2485
2486 opp-606000000
2487 opp-h
2488 opp-l
2489 opp-p
2490 };
2491
2492 opp-640000000
2493 opp-h
2494 opp-l
2495 opp-p
2496 };
2497
2498 opp-655000000
2499 opp-h
2500 opp-l
2501 opp-p
2502 };
2503
2504 opp-690000000
2505 opp-h
2506 opp-l
2507 opp-p
2508 };
2509 };
2510 };
2511
2512 gmu: gmu@3d6a000 {
2513 compatible = "qcom,ad
2514 reg = <0 0x03d6a000 0
2515 <0 0x03de0000 0
2516 <0 0x0b290000 0
2517 reg-names = "gmu", "r
2518 interrupts = <GIC_SPI
2519 <GIC_SPI
2520 interrupt-names = "hf
2521 clocks = <&gpucc GPU_
2522 <&gpucc GPU_
2523 <&gcc GCC_DD
2524 <&gcc GCC_GP
2525 <&gpucc GPU_
2526 <&gpucc GPU_
2527 <&gpucc GPU_
2528 clock-names = "gmu",
2529 "cxo",
2530 "axi",
2531 "memnoc
2532 "ahb",
2533 "hub",
2534 "smmu_v
2535 power-domains = <&gpu
2536 <&gpu
2537 power-domain-names =
2538
2539 iommus = <&gpu_smmu 5
2540 operating-points-v2 =
2541
2542 gmu_opp_table: opp-ta
2543 compatible =
2544
2545 opp-200000000
2546 opp-h
2547 opp-l
2548 };
2549
2550 opp-500000000
2551 opp-h
2552 opp-l
2553 };
2554 };
2555 };
2556
2557 gpucc: clock-controller@3d900
2558 compatible = "qcom,sc
2559 reg = <0 0x03d90000 0
2560 clocks = <&rpmhcc RPM
2561 <&gcc GCC_GP
2562 <&gcc GCC_GP
2563 clock-names = "bi_tcx
2564 "gcc_gp
2565 "gcc_gp
2566
2567 power-domains = <&rpm
2568 #clock-cells = <1>;
2569 #reset-cells = <1>;
2570 #power-domain-cells =
2571 };
2572
2573 gpu_smmu: iommu@3da0000 {
2574 compatible = "qcom,sc
2575 "qcom,sm
2576 reg = <0 0x03da0000 0
2577 #iommu-cells = <2>;
2578 #global-interrupts =
2579 interrupts = <GIC_SPI
2580 <GIC_SPI
2581 <GIC_SPI
2582 <GIC_SPI
2583 <GIC_SPI
2584 <GIC_SPI
2585 <GIC_SPI
2586 <GIC_SPI
2587 <GIC_SPI
2588 <GIC_SPI
2589 <GIC_SPI
2590 <GIC_SPI
2591 <GIC_SPI
2592 <GIC_SPI
2593
2594 clocks = <&gcc GCC_GP
2595 <&gcc GCC_GP
2596 <&gpucc GPU_
2597 <&gpucc GPU_
2598 <&gpucc GPU_
2599 <&gpucc GPU_
2600 <&gpucc GPU_
2601 clock-names = "gcc_gp
2602 "gcc_gp
2603 "gpu_cc
2604 "gpu_cc
2605 "gpu_cc
2606 "gpu_cc
2607 "gpu_cc
2608
2609 power-domains = <&gpu
2610 dma-coherent;
2611 };
2612
2613 usb_0_hsphy: phy@88e5000 {
2614 compatible = "qcom,sc
2615 "qcom,us
2616 reg = <0 0x088e5000 0
2617 clocks = <&rpmhcc RPM
2618 clock-names = "ref";
2619 resets = <&gcc GCC_QU
2620
2621 #phy-cells = <0>;
2622
2623 status = "disabled";
2624 };
2625
2626 usb_2_hsphy0: phy@88e7000 {
2627 compatible = "qcom,sc
2628 "qcom,us
2629 reg = <0 0x088e7000 0
2630 clocks = <&gcc GCC_US
2631 clock-names = "ref";
2632 resets = <&gcc GCC_QU
2633
2634 #phy-cells = <0>;
2635
2636 status = "disabled";
2637 };
2638
2639 usb_2_hsphy1: phy@88e8000 {
2640 compatible = "qcom,sc
2641 "qcom,us
2642 reg = <0 0x088e8000 0
2643 clocks = <&gcc GCC_US
2644 clock-names = "ref";
2645 resets = <&gcc GCC_QU
2646
2647 #phy-cells = <0>;
2648
2649 status = "disabled";
2650 };
2651
2652 usb_2_hsphy2: phy@88e9000 {
2653 compatible = "qcom,sc
2654 "qcom,us
2655 reg = <0 0x088e9000 0
2656 clocks = <&gcc GCC_US
2657 clock-names = "ref";
2658 resets = <&gcc GCC_QU
2659
2660 #phy-cells = <0>;
2661
2662 status = "disabled";
2663 };
2664
2665 usb_2_hsphy3: phy@88ea000 {
2666 compatible = "qcom,sc
2667 "qcom,us
2668 reg = <0 0x088ea000 0
2669 clocks = <&gcc GCC_US
2670 clock-names = "ref";
2671 resets = <&gcc GCC_QU
2672
2673 #phy-cells = <0>;
2674
2675 status = "disabled";
2676 };
2677
2678 usb_2_qmpphy0: phy@88ef000 {
2679 compatible = "qcom,sc
2680 reg = <0 0x088ef000 0
2681
2682 clocks = <&gcc GCC_US
2683 <&gcc GCC_US
2684 <&gcc GCC_US
2685 <&gcc GCC_US
2686 clock-names = "aux",
2687
2688 resets = <&gcc GCC_US
2689 <&gcc GCC_US
2690 reset-names = "phy",
2691
2692 power-domains = <&gcc
2693
2694 #clock-cells = <0>;
2695 clock-output-names =
2696
2697 #phy-cells = <0>;
2698
2699 status = "disabled";
2700 };
2701
2702 usb_2_qmpphy1: phy@88f1000 {
2703 compatible = "qcom,sc
2704 reg = <0 0x088f1000 0
2705
2706 clocks = <&gcc GCC_US
2707 <&gcc GCC_US
2708 <&gcc GCC_US
2709 <&gcc GCC_US
2710 clock-names = "aux",
2711
2712 resets = <&gcc GCC_US
2713 <&gcc GCC_US
2714 reset-names = "phy",
2715
2716 power-domains = <&gcc
2717
2718 #clock-cells = <0>;
2719 clock-output-names =
2720
2721 #phy-cells = <0>;
2722
2723 status = "disabled";
2724 };
2725
2726 remoteproc_adsp: remoteproc@3
2727 compatible = "qcom,sc
2728 reg = <0 0x03000000 0
2729
2730 interrupts-extended =
2731
2732
2733
2734
2735
2736 interrupt-names = "wd
2737 "ha
2738
2739 clocks = <&rpmhcc RPM
2740 clock-names = "xo";
2741
2742 power-domains = <&rpm
2743 <&rpm
2744 power-domain-names =
2745
2746 memory-region = <&pil
2747
2748 qcom,qmp = <&aoss_qmp
2749
2750 qcom,smem-states = <&
2751 qcom,smem-state-names
2752
2753 status = "disabled";
2754
2755 remoteproc_adsp_glink
2756 interrupts-ex
2757
2758
2759 mboxes = <&ip
2760
2761
2762 label = "lpas
2763 qcom,remote-p
2764
2765 gpr {
2766 compa
2767 qcom,
2768 qcom,
2769 qcom,
2770 #addr
2771 #size
2772
2773 q6apm
2774
2775
2776
2777
2778
2779
2780
2781
2782
2783
2784
2785
2786
2787
2788 };
2789
2790 q6prm
2791
2792
2793
2794
2795
2796
2797
2798
2799 };
2800 };
2801 };
2802 };
2803
2804 rxmacro: rxmacro@3200000 {
2805 compatible = "qcom,sc
2806 reg = <0 0x03200000 0
2807 clocks = <&q6prmcc LP
2808 <&q6prmcc LP
2809 <&q6prmcc LP
2810 <&q6prmcc LP
2811 <&vamacro>;
2812 clock-names = "mclk",
2813 assigned-clocks = <&q
2814 <&q
2815 assigned-clock-rates
2816
2817 clock-output-names =
2818 #clock-cells = <0>;
2819 #sound-dai-cells = <1
2820
2821 pinctrl-names = "defa
2822 pinctrl-0 = <&rx_swr_
2823
2824 status = "disabled";
2825 };
2826
2827 swr1: soundwire@3210000 {
2828 compatible = "qcom,so
2829 reg = <0 0x03210000 0
2830 interrupts = <GIC_SPI
2831 clocks = <&rxmacro>;
2832 clock-names = "iface"
2833 resets = <&lpass_audi
2834 reset-names = "swr_au
2835 label = "RX";
2836
2837 qcom,din-ports = <0>;
2838 qcom,dout-ports = <5>
2839
2840 qcom,ports-sinterval-
2841 qcom,ports-offset1 =
2842 qcom,ports-offset2 =
2843 qcom,ports-hstart =
2844 qcom,ports-hstop =
2845 qcom,ports-word-lengt
2846 qcom,ports-block-pack
2847 qcom,ports-lane-contr
2848 qcom,ports-block-grou
2849
2850 #sound-dai-cells = <1
2851 #address-cells = <2>;
2852 #size-cells = <0>;
2853
2854 status = "disabled";
2855 };
2856
2857 txmacro: txmacro@3220000 {
2858 compatible = "qcom,sc
2859 reg = <0 0x03220000 0
2860 pinctrl-names = "defa
2861 pinctrl-0 = <&tx_swr_
2862 clocks = <&q6prmcc LP
2863 <&q6prmcc LP
2864 <&q6prmcc LP
2865 <&q6prmcc LP
2866 <&vamacro>;
2867
2868 clock-names = "mclk",
2869 assigned-clocks = <&q
2870 <&q
2871 assigned-clock-rates
2872 clock-output-names =
2873
2874 #clock-cells = <0>;
2875 #sound-dai-cells = <1
2876
2877 status = "disabled";
2878 };
2879
2880 wsamacro: codec@3240000 {
2881 compatible = "qcom,sc
2882 reg = <0 0x03240000 0
2883 clocks = <&q6prmcc LP
2884 <&q6prmcc LP
2885 <&q6prmcc LP
2886 <&q6prmcc LP
2887 <&vamacro>;
2888 clock-names = "mclk",
2889 assigned-clocks = <&q
2890 <&q
2891 assigned-clock-rates
2892
2893 #clock-cells = <0>;
2894 clock-output-names =
2895 #sound-dai-cells = <1
2896
2897 pinctrl-names = "defa
2898 pinctrl-0 = <&wsa_swr
2899
2900 status = "disabled";
2901 };
2902
2903 swr0: soundwire@3250000 {
2904 reg = <0 0x03250000 0
2905 compatible = "qcom,so
2906 interrupts = <GIC_SPI
2907 clocks = <&wsamacro>;
2908 clock-names = "iface"
2909 resets = <&lpass_audi
2910 reset-names = "swr_au
2911 label = "WSA";
2912
2913 qcom,din-ports = <2>;
2914 qcom,dout-ports = <6>
2915
2916 qcom,ports-sinterval-
2917 qcom,ports-offset1 =
2918 qcom,ports-offset2 =
2919 qcom,ports-hstart =
2920 qcom,ports-hstop =
2921 qcom,ports-word-lengt
2922 qcom,ports-block-pack
2923 qcom,ports-block-grou
2924 qcom,ports-lane-contr
2925
2926 #sound-dai-cells = <1
2927 #address-cells = <2>;
2928 #size-cells = <0>;
2929
2930 status = "disabled";
2931 };
2932
2933 lpass_audiocc: clock-controll
2934 compatible = "qcom,sc
2935 reg = <0 0x032a9000 0
2936 #clock-cells = <1>;
2937 #reset-cells = <1>;
2938 };
2939
2940 swr2: soundwire@3330000 {
2941 compatible = "qcom,so
2942 reg = <0 0x03330000 0
2943 interrupts = <GIC_SPI
2944 <GIC_SPI
2945 interrupt-names = "co
2946
2947 clocks = <&txmacro>;
2948 clock-names = "iface"
2949 resets = <&lpasscc LP
2950 reset-names = "swr_au
2951 label = "TX";
2952 #sound-dai-cells = <1
2953 #address-cells = <2>;
2954 #size-cells = <0>;
2955
2956 qcom,din-ports = <4>;
2957 qcom,dout-ports = <0>
2958 qcom,ports-sinterval-
2959 qcom,ports-offset1 =
2960 qcom,ports-offset2 =
2961 qcom,ports-block-pack
2962 qcom,ports-hstart =
2963 qcom,ports-hstop =
2964 qcom,ports-word-lengt
2965 qcom,ports-block-grou
2966 qcom,ports-lane-contr
2967
2968 status = "disabled";
2969 };
2970
2971 vamacro: codec@3370000 {
2972 compatible = "qcom,sc
2973 reg = <0 0x03370000 0
2974 clocks = <&q6prmcc LP
2975 <&q6prmcc LP
2976 <&q6prmcc LP
2977 <&q6prmcc LP
2978 clock-names = "mclk",
2979 assigned-clocks = <&q
2980 assigned-clock-rates
2981
2982 #clock-cells = <0>;
2983 clock-output-names =
2984 #sound-dai-cells = <1
2985
2986 status = "disabled";
2987 };
2988
2989 lpass_tlmm: pinctrl@33c0000 {
2990 compatible = "qcom,sc
2991 reg = <0 0x33c0000 0x
2992 <0 0x3550000 0x
2993 gpio-controller;
2994 #gpio-cells = <2>;
2995 gpio-ranges = <&lpass
2996
2997 clocks = <&q6prmcc LP
2998 <&q6prmcc LP
2999 clock-names = "core",
3000
3001 status = "disabled";
3002
3003 tx_swr_default: tx-sw
3004 clk-pins {
3005 pins
3006 funct
3007 drive
3008 slew-
3009 bias-
3010 };
3011
3012 data-pins {
3013 pins
3014 funct
3015 drive
3016 slew-
3017 bias-
3018 };
3019 };
3020
3021 rx_swr_default: rx-sw
3022 clk-pins {
3023 pins
3024 funct
3025 drive
3026 slew-
3027 bias-
3028 };
3029
3030 data-pins {
3031 pins
3032 funct
3033 drive
3034 slew-
3035 bias-
3036 };
3037 };
3038
3039 dmic01_default: dmic0
3040 clk-pins {
3041 pins
3042 funct
3043 drive
3044 outpu
3045 };
3046
3047 data-pins {
3048 pins
3049 funct
3050 drive
3051 input
3052 };
3053 };
3054
3055 dmic01_sleep: dmic01-
3056 clk-pins {
3057 pins
3058 funct
3059 drive
3060 bias-
3061 outpu
3062 };
3063
3064 data-pins {
3065 pins
3066 funct
3067 drive
3068 bias-
3069 input
3070 };
3071 };
3072
3073 dmic23_default: dmic2
3074 clk-pins {
3075 pins
3076 funct
3077 drive
3078 outpu
3079 };
3080
3081 data-pins {
3082 pins
3083 funct
3084 drive
3085 input
3086 };
3087 };
3088
3089 dmic23_sleep: dmic23-
3090 clk-pins {
3091 pins
3092 funct
3093 drive
3094 bias-
3095 outpu
3096 };
3097
3098 data-pins {
3099 pins
3100 funct
3101 drive
3102 bias-
3103 input
3104 };
3105 };
3106
3107 wsa_swr_default: wsa-
3108 clk-pins {
3109 pins
3110 funct
3111 drive
3112 slew-
3113 bias-
3114 };
3115
3116 data-pins {
3117 pins
3118 funct
3119 drive
3120 slew-
3121 bias-
3122 };
3123 };
3124
3125 wsa2_swr_default: wsa
3126 clk-pins {
3127 pins
3128 funct
3129 drive
3130 slew-
3131 bias-
3132 };
3133
3134 data-pins {
3135 pins
3136 funct
3137 drive
3138 slew-
3139 bias-
3140 };
3141 };
3142 };
3143
3144 lpasscc: clock-controller@33e
3145 compatible = "qcom,sc
3146 reg = <0 0x033e0000 0
3147 #clock-cells = <1>;
3148 #reset-cells = <1>;
3149 };
3150
3151 sdc2: mmc@8804000 {
3152 compatible = "qcom,sc
3153 reg = <0 0x08804000 0
3154
3155 interrupts = <GIC_SPI
3156 <GIC_SPI
3157 interrupt-names = "hc
3158
3159 clocks = <&gcc GCC_SD
3160 <&gcc GCC_SD
3161 <&rpmhcc RPM
3162 clock-names = "iface"
3163 resets = <&gcc GCC_SD
3164 interconnects = <&agg
3165 <&gem
3166 interconnect-names =
3167 iommus = <&apps_smmu
3168 power-domains = <&rpm
3169 operating-points-v2 =
3170 bus-width = <4>;
3171 dma-coherent;
3172
3173 status = "disabled";
3174
3175 sdc2_opp_table: opp-t
3176 compatible =
3177
3178 opp-100000000
3179 opp-h
3180 requi
3181 opp-p
3182 opp-a
3183 };
3184
3185 opp-202000000
3186 opp-h
3187 requi
3188 opp-p
3189 opp-a
3190 };
3191 };
3192 };
3193
3194 usb_0_qmpphy: phy@88eb000 {
3195 compatible = "qcom,sc
3196 reg = <0 0x088eb000 0
3197
3198 clocks = <&gcc GCC_US
3199 <&gcc GCC_US
3200 <&gcc GCC_US
3201 <&gcc GCC_US
3202 clock-names = "aux",
3203
3204 power-domains = <&gcc
3205
3206 resets = <&gcc GCC_US
3207 <&gcc GCC_US
3208 reset-names = "phy",
3209
3210 #clock-cells = <1>;
3211 #phy-cells = <1>;
3212
3213 status = "disabled";
3214
3215 ports {
3216 #address-cell
3217 #size-cells =
3218
3219 port@0 {
3220 reg =
3221
3222 usb_0
3223 };
3224
3225 port@1 {
3226 reg =
3227
3228 usb_0
3229
3230 };
3231 };
3232
3233 port@2 {
3234 reg =
3235
3236 usb_0
3237 };
3238 };
3239 };
3240
3241 usb_1_hsphy: phy@8902000 {
3242 compatible = "qcom,sc
3243 "qcom,us
3244 reg = <0 0x08902000 0
3245 #phy-cells = <0>;
3246
3247 clocks = <&rpmhcc RPM
3248 clock-names = "ref";
3249
3250 resets = <&gcc GCC_QU
3251
3252 status = "disabled";
3253 };
3254
3255 usb_1_qmpphy: phy@8903000 {
3256 compatible = "qcom,sc
3257 reg = <0 0x08903000 0
3258
3259 clocks = <&gcc GCC_US
3260 <&gcc GCC_US
3261 <&gcc GCC_US
3262 <&gcc GCC_US
3263 clock-names = "aux",
3264
3265 power-domains = <&gcc
3266
3267 resets = <&gcc GCC_US
3268 <&gcc GCC_US
3269 reset-names = "phy",
3270
3271 #clock-cells = <1>;
3272 #phy-cells = <1>;
3273
3274 status = "disabled";
3275
3276 ports {
3277 #address-cell
3278 #size-cells =
3279
3280 port@0 {
3281 reg =
3282
3283 usb_1
3284 };
3285
3286 port@1 {
3287 reg =
3288
3289 usb_1
3290
3291 };
3292 };
3293
3294 port@2 {
3295 reg =
3296
3297 usb_1
3298 };
3299 };
3300 };
3301
3302 mdss1_dp0_phy: phy@8909a00 {
3303 compatible = "qcom,sc
3304 reg = <0 0x08909a00 0
3305 <0 0x08909200 0
3306 <0 0x08909600 0
3307 <0 0x08909000 0
3308
3309 clocks = <&dispcc1 DI
3310 <&dispcc1 DI
3311 clock-names = "aux",
3312 power-domains = <&rpm
3313
3314 #clock-cells = <1>;
3315 #phy-cells = <0>;
3316
3317 status = "disabled";
3318 };
3319
3320 mdss1_dp1_phy: phy@890ca00 {
3321 compatible = "qcom,sc
3322 reg = <0 0x0890ca00 0
3323 <0 0x0890c200 0
3324 <0 0x0890c600 0
3325 <0 0x0890c000 0
3326
3327 clocks = <&dispcc1 DI
3328 <&dispcc1 DI
3329 clock-names = "aux",
3330 power-domains = <&rpm
3331
3332 #clock-cells = <1>;
3333 #phy-cells = <0>;
3334
3335 status = "disabled";
3336 };
3337
3338 pmu@9091000 {
3339 compatible = "qcom,sc
3340 reg = <0 0x09091000 0
3341
3342 interrupts = <GIC_SPI
3343
3344 interconnects = <&mc_
3345
3346 operating-points-v2 =
3347
3348 llcc_bwmon_opp_table:
3349 compatible =
3350
3351 opp-0 {
3352 opp-p
3353 };
3354 opp-1 {
3355 opp-p
3356 };
3357 opp-2 {
3358 opp-p
3359 };
3360 opp-3 {
3361 opp-p
3362 };
3363 opp-4 {
3364 opp-p
3365 };
3366 opp-5 {
3367 opp-p
3368 };
3369 opp-6 {
3370 opp-p
3371 };
3372 opp-7 {
3373 opp-p
3374 };
3375 opp-8 {
3376 opp-p
3377 };
3378 opp-9 {
3379 opp-p
3380 };
3381 opp-10 {
3382 opp-p
3383 };
3384 opp-11 {
3385 opp-p
3386 };
3387 opp-12 {
3388 opp-p
3389 };
3390 };
3391 };
3392
3393 pmu@90b6400 {
3394 compatible = "qcom,sc
3395 reg = <0 0x090b6400 0
3396
3397 interrupts = <GIC_SPI
3398
3399 interconnects = <&gem
3400 operating-points-v2 =
3401
3402 cpu_bwmon_opp_table:
3403 compatible =
3404
3405 opp-0 {
3406 opp-p
3407 };
3408 opp-1 {
3409 opp-p
3410 };
3411 opp-2 {
3412 opp-p
3413 };
3414 opp-3 {
3415 opp-p
3416 };
3417 opp-4 {
3418 opp-p
3419 };
3420 opp-5 {
3421 opp-p
3422 };
3423 opp-6 {
3424 opp-p
3425 };
3426 };
3427 };
3428
3429 system-cache-controller@92000
3430 compatible = "qcom,sc
3431 reg = <0 0x09200000 0
3432 <0 0x09300000 0
3433 <0 0x09400000 0
3434 <0 0x09500000 0
3435 <0 0x09600000 0
3436 reg-names = "llcc0_ba
3437 "llcc3_ba
3438 "llcc6_ba
3439 interrupts = <GIC_SPI
3440 };
3441
3442 usb_2: usb@a4f8800 {
3443 compatible = "qcom,sc
3444 reg = <0 0x0a4f8800 0
3445 #address-cells = <2>;
3446 #size-cells = <2>;
3447 ranges;
3448
3449 clocks = <&gcc GCC_CF
3450 <&gcc GCC_US
3451 <&gcc GCC_AG
3452 <&gcc GCC_US
3453 <&gcc GCC_US
3454 <&gcc GCC_AG
3455 <&gcc GCC_AG
3456 <&gcc GCC_AG
3457 <&gcc GCC_SY
3458 clock-names = "cfg_no
3459 "noc_ag
3460
3461 assigned-clocks = <&g
3462 <&g
3463 assigned-clock-rates
3464
3465 interrupts-extended =
3466
3467
3468
3469
3470
3471
3472
3473
3474
3475
3476
3477
3478
3479
3480
3481
3482
3483
3484 interrupt-names = "pw
3485 "pw
3486 "hs
3487 "hs
3488 "dp
3489 "dp
3490 "dp
3491 "dp
3492 "ss
3493
3494 power-domains = <&gcc
3495 required-opps = <&rpm
3496
3497 resets = <&gcc GCC_US
3498
3499 interconnects = <&agg
3500 <&gem
3501 interconnect-names =
3502
3503 wakeup-source;
3504
3505 status = "disabled";
3506
3507 usb_2_dwc3: usb@a4000
3508 compatible =
3509 reg = <0 0x0a
3510 interrupts =
3511 iommus = <&ap
3512 phys = <&usb_
3513 <&usb_
3514 <&usb_
3515 <&usb_
3516 phy-names = "
3517 "
3518 "
3519 "
3520 dr_mode = "ho
3521 };
3522 };
3523
3524 usb_0: usb@a6f8800 {
3525 compatible = "qcom,sc
3526 reg = <0 0x0a6f8800 0
3527 #address-cells = <2>;
3528 #size-cells = <2>;
3529 ranges;
3530
3531 clocks = <&gcc GCC_CF
3532 <&gcc GCC_US
3533 <&gcc GCC_AG
3534 <&gcc GCC_US
3535 <&gcc GCC_US
3536 <&gcc GCC_AG
3537 <&gcc GCC_AG
3538 <&gcc GCC_AG
3539 <&gcc GCC_SY
3540 clock-names = "cfg_no
3541 "noc_ag
3542
3543 assigned-clocks = <&g
3544 <&g
3545 assigned-clock-rates
3546
3547 interrupts-extended =
3548
3549
3550
3551
3552 interrupt-names = "pw
3553 "hs
3554 "dp
3555 "dm
3556 "ss
3557
3558 power-domains = <&gcc
3559 required-opps = <&rpm
3560
3561 resets = <&gcc GCC_US
3562
3563 interconnects = <&agg
3564 <&gem
3565 interconnect-names =
3566
3567 wakeup-source;
3568
3569 status = "disabled";
3570
3571 usb_0_dwc3: usb@a6000
3572 compatible =
3573 reg = <0 0x0a
3574 interrupts =
3575 iommus = <&ap
3576 phys = <&usb_
3577 phy-names = "
3578
3579 ports {
3580 #addr
3581 #size
3582
3583 port@
3584
3585
3586
3587
3588 };
3589
3590 port@
3591
3592
3593
3594
3595
3596 };
3597 };
3598 };
3599 };
3600
3601 usb_1: usb@a8f8800 {
3602 compatible = "qcom,sc
3603 reg = <0 0x0a8f8800 0
3604 #address-cells = <2>;
3605 #size-cells = <2>;
3606 ranges;
3607
3608 clocks = <&gcc GCC_CF
3609 <&gcc GCC_US
3610 <&gcc GCC_AG
3611 <&gcc GCC_US
3612 <&gcc GCC_US
3613 <&gcc GCC_AG
3614 <&gcc GCC_AG
3615 <&gcc GCC_AG
3616 <&gcc GCC_SY
3617 clock-names = "cfg_no
3618 "noc_ag
3619
3620 assigned-clocks = <&g
3621 <&g
3622 assigned-clock-rates
3623
3624 interrupts-extended =
3625
3626
3627
3628
3629 interrupt-names = "pw
3630 "hs
3631 "dp
3632 "dm
3633 "ss
3634
3635 power-domains = <&gcc
3636 required-opps = <&rpm
3637
3638 resets = <&gcc GCC_US
3639
3640 interconnects = <&agg
3641 <&gem
3642 interconnect-names =
3643
3644 wakeup-source;
3645
3646 status = "disabled";
3647
3648 usb_1_dwc3: usb@a8000
3649 compatible =
3650 reg = <0 0x0a
3651 interrupts =
3652 iommus = <&ap
3653 phys = <&usb_
3654 phy-names = "
3655
3656 ports {
3657 #addr
3658 #size
3659
3660 port@
3661
3662
3663
3664
3665 };
3666
3667 port@
3668
3669
3670
3671
3672
3673 };
3674 };
3675 };
3676 };
3677
3678 cci0: cci@ac4a000 {
3679 compatible = "qcom,sc
3680 reg = <0 0x0ac4a000 0
3681
3682 interrupts = <GIC_SPI
3683
3684 clocks = <&camcc CAMC
3685 <&camcc CAMC
3686 <&camcc CAMC
3687 <&camcc CAMC
3688 clock-names = "camnoc
3689 "slow_a
3690 "cpas_a
3691 "cci";
3692
3693 power-domains = <&cam
3694
3695 pinctrl-0 = <&cci0_de
3696 pinctrl-1 = <&cci0_sl
3697 pinctrl-names = "defa
3698
3699 #address-cells = <1>;
3700 #size-cells = <0>;
3701
3702 status = "disabled";
3703
3704 cci0_i2c0: i2c-bus@0
3705 reg = <0>;
3706 clock-frequen
3707 #address-cell
3708 #size-cells =
3709 };
3710
3711 cci0_i2c1: i2c-bus@1
3712 reg = <1>;
3713 clock-frequen
3714 #address-cell
3715 #size-cells =
3716 };
3717 };
3718
3719 cci1: cci@ac4b000 {
3720 compatible = "qcom,sc
3721 reg = <0 0x0ac4b000 0
3722
3723 interrupts = <GIC_SPI
3724
3725 clocks = <&camcc CAMC
3726 <&camcc CAMC
3727 <&camcc CAMC
3728 <&camcc CAMC
3729 clock-names = "camnoc
3730 "slow_a
3731 "cpas_a
3732 "cci";
3733
3734 power-domains = <&cam
3735
3736 pinctrl-0 = <&cci1_de
3737 pinctrl-1 = <&cci1_sl
3738 pinctrl-names = "defa
3739
3740 #address-cells = <1>;
3741 #size-cells = <0>;
3742
3743 status = "disabled";
3744
3745 cci1_i2c0: i2c-bus@0
3746 reg = <0>;
3747 clock-frequen
3748 #address-cell
3749 #size-cells =
3750 };
3751
3752 cci1_i2c1: i2c-bus@1
3753 reg = <1>;
3754 clock-frequen
3755 #address-cell
3756 #size-cells =
3757 };
3758 };
3759
3760 cci2: cci@ac4c000 {
3761 compatible = "qcom,sc
3762 reg = <0 0x0ac4c000 0
3763
3764 interrupts = <GIC_SPI
3765
3766 clocks = <&camcc CAMC
3767 <&camcc CAMC
3768 <&camcc CAMC
3769 <&camcc CAMC
3770 clock-names = "camnoc
3771 "slow_a
3772 "cpas_a
3773 "cci";
3774 power-domains = <&cam
3775
3776 pinctrl-0 = <&cci2_de
3777 pinctrl-1 = <&cci2_sl
3778 pinctrl-names = "defa
3779
3780 #address-cells = <1>;
3781 #size-cells = <0>;
3782
3783 status = "disabled";
3784
3785 cci2_i2c0: i2c-bus@0
3786 reg = <0>;
3787 clock-frequen
3788 #address-cell
3789 #size-cells =
3790 };
3791
3792 cci2_i2c1: i2c-bus@1
3793 reg = <1>;
3794 clock-frequen
3795 #address-cell
3796 #size-cells =
3797 };
3798 };
3799
3800 cci3: cci@ac4d000 {
3801 compatible = "qcom,sc
3802 reg = <0 0x0ac4d000 0
3803
3804 interrupts = <GIC_SPI
3805
3806 clocks = <&camcc CAMC
3807 <&camcc CAMC
3808 <&camcc CAMC
3809 <&camcc CAMC
3810 clock-names = "camnoc
3811 "slow_a
3812 "cpas_a
3813 "cci";
3814
3815 power-domains = <&cam
3816
3817 pinctrl-0 = <&cci3_de
3818 pinctrl-1 = <&cci3_sl
3819 pinctrl-names = "defa
3820
3821 #address-cells = <1>;
3822 #size-cells = <0>;
3823
3824 status = "disabled";
3825
3826 cci3_i2c0: i2c-bus@0
3827 reg = <0>;
3828 clock-frequen
3829 #address-cell
3830 #size-cells =
3831 };
3832
3833 cci3_i2c1: i2c-bus@1
3834 reg = <1>;
3835 clock-frequen
3836 #address-cell
3837 #size-cells =
3838 };
3839 };
3840
3841 camss: camss@ac5a000 {
3842 compatible = "qcom,sc
3843
3844 reg = <0 0x0ac5a000 0
3845 <0 0x0ac5c000 0
3846 <0 0x0ac65000 0
3847 <0 0x0ac67000 0
3848 <0 0x0acaf000 0
3849 <0 0x0acb3000 0
3850 <0 0x0acb6000 0
3851 <0 0x0acba000 0
3852 <0 0x0acbd000 0
3853 <0 0x0acc1000 0
3854 <0 0x0acc4000 0
3855 <0 0x0acc8000 0
3856 <0 0x0accb000 0
3857 <0 0x0accf000 0
3858 <0 0x0acd2000 0
3859 <0 0x0acd6000 0
3860 <0 0x0acd9000 0
3861 <0 0x0acdd000 0
3862 <0 0x0ace0000 0
3863 <0 0x0ace4000 0
3864 reg-names = "csiphy2"
3865 "csiphy3"
3866 "csiphy0"
3867 "csiphy1"
3868 "vfe0",
3869 "csid0",
3870 "vfe1",
3871 "csid1",
3872 "vfe2",
3873 "csid2",
3874 "vfe_lite
3875 "csid0_li
3876 "vfe_lite
3877 "csid1_li
3878 "vfe_lite
3879 "csid2_li
3880 "vfe_lite
3881 "csid3_li
3882 "vfe3",
3883 "csid3";
3884
3885 interrupts = <GIC_SPI
3886 <GIC_SPI
3887 <GIC_SPI
3888 <GIC_SPI
3889 <GIC_SPI
3890 <GIC_SPI
3891 <GIC_SPI
3892 <GIC_SPI
3893 <GIC_SPI
3894 <GIC_SPI
3895 <GIC_SPI
3896 <GIC_SPI
3897 <GIC_SPI
3898 <GIC_SPI
3899 <GIC_SPI
3900 <GIC_SPI
3901 <GIC_SPI
3902 <GIC_SPI
3903 <GIC_SPI
3904 <GIC_SPI
3905 interrupt-names = "cs
3906 "vf
3907 "cs
3908 "cs
3909 "vf
3910 "cs
3911 "vf
3912 "cs
3913 "vf
3914 "cs
3915 "cs
3916 "cs
3917 "cs
3918 "vf
3919 "cs
3920 "cs
3921 "vf
3922 "vf
3923 "cs
3924 "vf
3925
3926 power-domains = <&cam
3927 <&cam
3928 <&cam
3929 <&cam
3930 <&cam
3931 power-domain-names =
3932
3933
3934
3935
3936
3937 clocks = <&camcc CAMC
3938 <&camcc CAMC
3939 <&camcc CAMC
3940 <&camcc CAMC
3941 <&camcc CAMC
3942 <&camcc CAMC
3943 <&camcc CAMC
3944 <&camcc CAMC
3945 <&camcc CAMC
3946 <&camcc CAMC
3947 <&camcc CAMC
3948 <&camcc CAMC
3949 <&camcc CAMC
3950 <&camcc CAMC
3951 <&camcc CAMC
3952 <&camcc CAMC
3953 <&camcc CAMC
3954 <&camcc CAMC
3955 <&camcc CAMC
3956 <&camcc CAMC
3957 <&camcc CAMC
3958 <&camcc CAMC
3959 <&camcc CAMC
3960 <&camcc CAMC
3961 <&camcc CAMC
3962 <&camcc CAMC
3963 <&camcc CAMC
3964 <&camcc CAMC
3965 <&camcc CAMC
3966 <&camcc CAMC
3967 <&camcc CAMC
3968 <&camcc CAMC
3969 <&camcc CAMC
3970 <&camcc CAMC
3971 <&camcc CAMC
3972 <&camcc CAMC
3973 <&camcc CAMC
3974 <&camcc CAMC
3975 <&gcc GCC_CA
3976 <&gcc GCC_CA
3977 clock-names = "camnoc
3978 "cpas_a
3979 "csiphy
3980 "csiphy
3981 "csiphy
3982 "csiphy
3983 "csiphy
3984 "csiphy
3985 "csiphy
3986 "csiphy
3987 "vfe0_a
3988 "vfe0",
3989 "vfe0_c
3990 "vfe0_c
3991 "vfe1_a
3992 "vfe1",
3993 "vfe1_c
3994 "vfe1_c
3995 "vfe2_a
3996 "vfe2",
3997 "vfe2_c
3998 "vfe2_c
3999 "vfe3_a
4000 "vfe3",
4001 "vfe3_c
4002 "vfe3_c
4003 "vfe_li
4004 "vfe_li
4005 "vfe_li
4006 "vfe_li
4007 "vfe_li
4008 "vfe_li
4009 "vfe_li
4010 "vfe_li
4011 "vfe_li
4012 "vfe_li
4013 "vfe_li
4014 "vfe_li
4015 "gcc_ax
4016 "gcc_ax
4017
4018 iommus = <&apps_smmu
4019 <&apps_smmu
4020 <&apps_smmu
4021 <&apps_smmu
4022 <&apps_smmu
4023 <&apps_smmu
4024 <&apps_smmu
4025 <&apps_smmu
4026 <&apps_smmu
4027 <&apps_smmu
4028 <&apps_smmu
4029 <&apps_smmu
4030 <&apps_smmu
4031 <&apps_smmu
4032 <&apps_smmu
4033 <&apps_smmu
4034
4035 interconnects = <&gem
4036 <&mms
4037 <&mms
4038 <&mms
4039 interconnect-names =
4040
4041
4042
4043
4044 status = "disabled";
4045
4046 ports {
4047 #address-cell
4048 #size-cells =
4049
4050 port@0 {
4051 reg =
4052 #addr
4053 #size
4054 };
4055
4056 port@1 {
4057 reg =
4058 #addr
4059 #size
4060 };
4061
4062 port@2 {
4063 reg =
4064 #addr
4065 #size
4066 };
4067
4068 port@3 {
4069 reg =
4070 #addr
4071 #size
4072 };
4073 };
4074 };
4075
4076 camcc: clock-controller@ad000
4077 compatible = "qcom,sc
4078 reg = <0 0x0ad00000 0
4079 clocks = <&gcc GCC_CA
4080 <&rpmhcc RPM
4081 <&rpmhcc RPM
4082 <&sleep_clk>
4083 power-domains = <&rpm
4084 required-opps = <&rpm
4085 #clock-cells = <1>;
4086 #reset-cells = <1>;
4087 #power-domain-cells =
4088 };
4089
4090 mdss0: display-subsystem@ae00
4091 compatible = "qcom,sc
4092 reg = <0 0x0ae00000 0
4093 reg-names = "mdss";
4094
4095 clocks = <&gcc GCC_DI
4096 <&dispcc0 DI
4097 <&dispcc0 DI
4098 clock-names = "iface"
4099 "ahb",
4100 "core";
4101 interrupts = <GIC_SPI
4102 interconnects = <&mms
4103 <&mms
4104 interconnect-names =
4105 iommus = <&apps_smmu
4106 power-domains = <&dis
4107 resets = <&dispcc0 DI
4108
4109 interrupt-controller;
4110 #interrupt-cells = <1
4111 #address-cells = <2>;
4112 #size-cells = <2>;
4113 ranges;
4114
4115 status = "disabled";
4116
4117 mdss0_mdp: display-co
4118 compatible =
4119 reg = <0 0x0a
4120 <0 0x0a
4121 reg-names = "
4122
4123 clocks = <&gc
4124 <&gc
4125 <&di
4126 <&di
4127 <&di
4128 <&di
4129 clock-names =
4130
4131
4132
4133
4134
4135 interrupt-par
4136 interrupts =
4137 power-domains
4138
4139 assigned-cloc
4140 assigned-cloc
4141 operating-poi
4142
4143 ports {
4144 #addr
4145 #size
4146
4147 port@
4148
4149
4150
4151
4152 };
4153
4154 port@
4155
4156
4157
4158
4159 };
4160
4161 port@
4162
4163
4164
4165
4166 };
4167
4168 port@
4169
4170
4171
4172
4173 };
4174 };
4175
4176 mdss0_mdp_opp
4177 compa
4178
4179 opp-2
4180
4181
4182 };
4183
4184 opp-3
4185
4186
4187 };
4188
4189 opp-3
4190
4191
4192 };
4193
4194 opp-5
4195
4196
4197 };
4198 opp-6
4199
4200
4201 };
4202 };
4203 };
4204
4205 mdss0_dp0: displaypor
4206 compatible =
4207 reg = <0 0xae
4208 <0 0xae
4209 <0 0xae
4210 <0 0xae
4211 <0 0xae
4212 interrupt-par
4213 interrupts =
4214 clocks = <&di
4215 <&di
4216 <&di
4217 <&di
4218 <&di
4219 clock-names =
4220
4221
4222
4223
4224 assigned-cloc
4225
4226 assigned-cloc
4227
4228
4229 phys = <&usb_
4230 phy-names = "
4231
4232 #sound-dai-ce
4233
4234 operating-poi
4235 power-domains
4236
4237 status = "dis
4238
4239 ports {
4240 #addr
4241 #size
4242
4243 port@
4244
4245
4246
4247
4248
4249 };
4250
4251 port@
4252
4253
4254
4255
4256 };
4257 };
4258
4259 mdss0_dp0_opp
4260 compa
4261
4262 opp-1
4263
4264
4265 };
4266
4267 opp-2
4268
4269
4270 };
4271
4272 opp-5
4273
4274
4275 };
4276
4277 opp-8
4278
4279
4280 };
4281 };
4282 };
4283
4284 mdss0_dp1: displaypor
4285 compatible =
4286 reg = <0 0xae
4287 <0 0xae
4288 <0 0xae
4289 <0 0xae
4290 <0 0xae
4291 interrupt-par
4292 interrupts =
4293 clocks = <&di
4294 <&di
4295 <&di
4296 <&di
4297 <&di
4298 clock-names =
4299
4300
4301
4302 assigned-cloc
4303
4304 assigned-cloc
4305
4306
4307 phys = <&usb_
4308 phy-names = "
4309
4310 #sound-dai-ce
4311
4312 operating-poi
4313 power-domains
4314
4315 status = "dis
4316
4317 ports {
4318 #addr
4319 #size
4320
4321 port@
4322
4323
4324
4325
4326
4327 };
4328
4329 port@
4330
4331
4332
4333
4334 };
4335 };
4336
4337 mdss0_dp1_opp
4338 compa
4339
4340 opp-1
4341
4342
4343 };
4344
4345 opp-2
4346
4347
4348 };
4349
4350 opp-5
4351
4352
4353 };
4354
4355 opp-8
4356
4357
4358 };
4359 };
4360 };
4361
4362 mdss0_dp2: displaypor
4363 compatible =
4364 reg = <0 0xae
4365 <0 0xae
4366 <0 0xae
4367 <0 0xae
4368 <0 0xae
4369
4370 clocks = <&di
4371 <&di
4372 <&di
4373 <&di
4374 <&di
4375 clock-names =
4376
4377
4378 interrupt-par
4379 interrupts =
4380 phys = <&mdss
4381 phy-names = "
4382 power-domains
4383
4384 assigned-cloc
4385
4386 assigned-cloc
4387 operating-poi
4388
4389 #sound-dai-ce
4390
4391 status = "dis
4392
4393 ports {
4394 #addr
4395 #size
4396
4397 port@
4398
4399
4400
4401
4402 };
4403
4404 port@
4405
4406 };
4407 };
4408
4409 mdss0_dp2_opp
4410 compa
4411
4412 opp-1
4413
4414
4415 };
4416
4417 opp-2
4418
4419
4420 };
4421
4422 opp-5
4423
4424
4425 };
4426
4427 opp-8
4428
4429
4430 };
4431 };
4432 };
4433
4434 mdss0_dp3: displaypor
4435 compatible =
4436 reg = <0 0xae
4437 <0 0xae
4438 <0 0xae
4439 <0 0xae
4440 <0 0xae
4441
4442 clocks = <&di
4443 <&di
4444 <&di
4445 <&di
4446 <&di
4447 clock-names =
4448
4449
4450 interrupt-par
4451 interrupts =
4452 phys = <&mdss
4453 phy-names = "
4454 power-domains
4455
4456 assigned-cloc
4457
4458 assigned-cloc
4459 operating-poi
4460
4461 #sound-dai-ce
4462
4463 status = "dis
4464
4465 ports {
4466 #addr
4467 #size
4468
4469 port@
4470
4471
4472
4473
4474 };
4475
4476 port@
4477
4478 };
4479 };
4480
4481 mdss0_dp3_opp
4482 compa
4483
4484 opp-1
4485
4486
4487 };
4488
4489 opp-2
4490
4491
4492 };
4493
4494 opp-5
4495
4496
4497 };
4498
4499 opp-8
4500
4501
4502 };
4503 };
4504 };
4505 };
4506
4507 mdss0_dp2_phy: phy@aec2a00 {
4508 compatible = "qcom,sc
4509 reg = <0 0x0aec2a00 0
4510 <0 0x0aec2200 0
4511 <0 0x0aec2600 0
4512 <0 0x0aec2000 0
4513
4514 clocks = <&dispcc0 DI
4515 <&dispcc0 DI
4516 clock-names = "aux",
4517 power-domains = <&rpm
4518
4519 #clock-cells = <1>;
4520 #phy-cells = <0>;
4521
4522 status = "disabled";
4523 };
4524
4525 mdss0_dp3_phy: phy@aec5a00 {
4526 compatible = "qcom,sc
4527 reg = <0 0x0aec5a00 0
4528 <0 0x0aec5200 0
4529 <0 0x0aec5600 0
4530 <0 0x0aec5000 0
4531
4532 clocks = <&dispcc0 DI
4533 <&dispcc0 DI
4534 clock-names = "aux",
4535 power-domains = <&rpm
4536
4537 #clock-cells = <1>;
4538 #phy-cells = <0>;
4539
4540 status = "disabled";
4541 };
4542
4543 dispcc0: clock-controller@af0
4544 compatible = "qcom,sc
4545 reg = <0 0x0af00000 0
4546
4547 clocks = <&gcc GCC_DI
4548 <&rpmhcc RPM
4549 <&sleep_clk>
4550 <&usb_0_qmpp
4551 <&usb_0_qmpp
4552 <&usb_1_qmpp
4553 <&usb_1_qmpp
4554 <&mdss0_dp2_
4555 <&mdss0_dp2_
4556 <&mdss0_dp3_
4557 <&mdss0_dp3_
4558 <0>,
4559 <0>,
4560 <0>,
4561 <0>;
4562 power-domains = <&rpm
4563
4564 #clock-cells = <1>;
4565 #power-domain-cells =
4566 #reset-cells = <1>;
4567
4568 status = "disabled";
4569 };
4570
4571 pdc: interrupt-controller@b22
4572 compatible = "qcom,sc
4573 reg = <0 0x0b220000 0
4574 qcom,pdc-ranges = <0
4575 <40
4576 <54
4577 <55
4578 <59
4579 <62
4580 <64
4581 <66
4582 <69
4583 <70
4584 <12
4585 <15
4586 <16
4587 <16
4588 <16
4589 <19
4590 <20
4591 <20
4592 <20
4593 <20
4594 <20
4595 <20
4596 <20
4597 <20
4598 <20
4599 <21
4600 <21
4601 <21
4602 <21
4603 <21
4604 <21
4605 <22
4606 <22
4607 <22
4608 <23
4609 <23
4610 <23
4611 <23
4612 <23
4613 <23
4614 <23
4615 <23
4616 <24
4617 <24
4618 <24
4619 <24
4620 <24
4621 <24
4622 <25
4623 <25
4624 <25
4625 <25
4626 <25
4627 <25
4628 <25
4629 <26
4630 <26
4631 #interrupt-cells = <2
4632 interrupt-parent = <&
4633 interrupt-controller;
4634 };
4635
4636 tsens2: thermal-sensor@c25100
4637 compatible = "qcom,sc
4638 reg = <0 0x0c251000 0
4639 <0 0x0c224000 0
4640 #qcom,sensors = <11>;
4641 interrupts-extended =
4642
4643 interrupt-names = "up
4644 #thermal-sensor-cells
4645 };
4646
4647 tsens3: thermal-sensor@c25200
4648 compatible = "qcom,sc
4649 reg = <0 0x0c252000 0
4650 <0 0x0c225000 0
4651 #qcom,sensors = <5>;
4652 interrupts-extended =
4653
4654 interrupt-names = "up
4655 #thermal-sensor-cells
4656 };
4657
4658 tsens0: thermal-sensor@c26300
4659 compatible = "qcom,sc
4660 reg = <0 0x0c263000 0
4661 <0 0x0c222000 0
4662 #qcom,sensors = <14>;
4663 interrupts-extended =
4664
4665 interrupt-names = "up
4666 #thermal-sensor-cells
4667 };
4668
4669 restart@c264000 {
4670 compatible = "qcom,ps
4671 reg = <0 0x0c264000 0
4672 /* TZ seems to block
4673 status = "reserved";
4674 };
4675
4676 tsens1: thermal-sensor@c26500
4677 compatible = "qcom,sc
4678 reg = <0 0x0c265000 0
4679 <0 0x0c223000 0
4680 #qcom,sensors = <16>;
4681 interrupts-extended =
4682
4683 interrupt-names = "up
4684 #thermal-sensor-cells
4685 };
4686
4687 aoss_qmp: power-management@c3
4688 compatible = "qcom,sc
4689 reg = <0 0x0c300000 0
4690 interrupts-extended =
4691 mboxes = <&ipcc IPCC_
4692
4693 #clock-cells = <0>;
4694 };
4695
4696 sram@c3f0000 {
4697 compatible = "qcom,rp
4698 reg = <0 0x0c3f0000 0
4699 qcom,qmp = <&aoss_qmp
4700 };
4701
4702 spmi_bus: spmi@c440000 {
4703 compatible = "qcom,sp
4704 reg = <0 0x0c440000 0
4705 <0 0x0c600000 0
4706 <0 0x0e600000 0
4707 <0 0x0e700000 0
4708 <0 0x0c40a000 0
4709 reg-names = "core", "
4710 interrupt-names = "pe
4711 interrupts-extended =
4712 qcom,ee = <0>;
4713 qcom,channel = <0>;
4714 #address-cells = <2>;
4715 #size-cells = <0>;
4716 interrupt-controller;
4717 #interrupt-cells = <4
4718 };
4719
4720 tlmm: pinctrl@f100000 {
4721 compatible = "qcom,sc
4722 reg = <0 0x0f100000 0
4723 interrupts = <GIC_SPI
4724 gpio-controller;
4725 #gpio-cells = <2>;
4726 interrupt-controller;
4727 #interrupt-cells = <2
4728 gpio-ranges = <&tlmm
4729 wakeup-parent = <&pdc
4730
4731 cci0_default: cci0-de
4732 cci0_i2c0_def
4733 /* cc
4734 pins
4735 funct
4736 drive
4737 bias-
4738 };
4739
4740 cci0_i2c1_def
4741 /* cc
4742 pins
4743 funct
4744 drive
4745 bias-
4746 };
4747 };
4748
4749 cci0_sleep: cci0-slee
4750 cci0_i2c0_sle
4751 /* cc
4752 pins
4753 funct
4754 drive
4755 bias-
4756 };
4757
4758 cci0_i2c1_sle
4759 /* cc
4760 pins
4761 funct
4762 drive
4763 bias-
4764 };
4765 };
4766
4767 cci1_default: cci1-de
4768 cci1_i2c0_def
4769 /* cc
4770 pins
4771 funct
4772 drive
4773 bias-
4774 };
4775
4776 cci1_i2c1_def
4777 /* cc
4778 pins
4779 funct
4780 drive
4781 bias-
4782 };
4783 };
4784
4785 cci1_sleep: cci1-slee
4786 cci1_i2c0_sle
4787 /* cc
4788 pins
4789 funct
4790 drive
4791 bias-
4792 };
4793
4794 cci1_i2c1_sle
4795 /* cc
4796 pins
4797 funct
4798 drive
4799 bias-
4800 };
4801 };
4802
4803 cci2_default: cci2-de
4804 cci2_i2c0_def
4805 /* cc
4806 pins
4807 funct
4808 drive
4809 bias-
4810 };
4811
4812 cci2_i2c1_def
4813 /* cc
4814 pins
4815 funct
4816 drive
4817 bias-
4818 };
4819 };
4820
4821 cci2_sleep: cci2-slee
4822 cci2_i2c0_sle
4823 /* cc
4824 pins
4825 funct
4826 drive
4827 bias-
4828 };
4829
4830 cci2_i2c1_sle
4831 /* cc
4832 pins
4833 funct
4834 drive
4835 bias-
4836 };
4837 };
4838
4839 cci3_default: cci3-de
4840 cci3_i2c0_def
4841 /* cc
4842 pins
4843 funct
4844 drive
4845 bias-
4846 };
4847
4848 cci3_i2c1_def
4849 /* cc
4850 pins
4851 funct
4852 drive
4853 bias-
4854 };
4855 };
4856
4857 cci3_sleep: cci3-slee
4858 cci3_i2c0_sle
4859 /* cc
4860 pins
4861 funct
4862 drive
4863 bias-
4864 };
4865
4866 cci3_i2c1_sle
4867 /* cc
4868 pins
4869 funct
4870 drive
4871 bias-
4872 };
4873 };
4874 };
4875
4876 apps_smmu: iommu@15000000 {
4877 compatible = "qcom,sc
4878 reg = <0 0x15000000 0
4879 #iommu-cells = <2>;
4880 #global-interrupts =
4881 interrupts = <GIC_SPI
4882 <GIC_SPI
4883 <GIC_SPI
4884 <GIC_SPI
4885 <GIC_SPI
4886 <GIC_SPI
4887 <GIC_SPI
4888 <GIC_SPI
4889 <GIC_SPI
4890 <GIC_SPI
4891 <GIC_SPI
4892 <GIC_SPI
4893 <GIC_SPI
4894 <GIC_SPI
4895 <GIC_SPI
4896 <GIC_SPI
4897 <GIC_SPI
4898 <GIC_SPI
4899 <GIC_SPI
4900 <GIC_SPI
4901 <GIC_SPI
4902 <GIC_SPI
4903 <GIC_SPI
4904 <GIC_SPI
4905 <GIC_SPI
4906 <GIC_SPI
4907 <GIC_SPI
4908 <GIC_SPI
4909 <GIC_SPI
4910 <GIC_SPI
4911 <GIC_SPI
4912 <GIC_SPI
4913 <GIC_SPI
4914 <GIC_SPI
4915 <GIC_SPI
4916 <GIC_SPI
4917 <GIC_SPI
4918 <GIC_SPI
4919 <GIC_SPI
4920 <GIC_SPI
4921 <GIC_SPI
4922 <GIC_SPI
4923 <GIC_SPI
4924 <GIC_SPI
4925 <GIC_SPI
4926 <GIC_SPI
4927 <GIC_SPI
4928 <GIC_SPI
4929 <GIC_SPI
4930 <GIC_SPI
4931 <GIC_SPI
4932 <GIC_SPI
4933 <GIC_SPI
4934 <GIC_SPI
4935 <GIC_SPI
4936 <GIC_SPI
4937 <GIC_SPI
4938 <GIC_SPI
4939 <GIC_SPI
4940 <GIC_SPI
4941 <GIC_SPI
4942 <GIC_SPI
4943 <GIC_SPI
4944 <GIC_SPI
4945 <GIC_SPI
4946 <GIC_SPI
4947 <GIC_SPI
4948 <GIC_SPI
4949 <GIC_SPI
4950 <GIC_SPI
4951 <GIC_SPI
4952 <GIC_SPI
4953 <GIC_SPI
4954 <GIC_SPI
4955 <GIC_SPI
4956 <GIC_SPI
4957 <GIC_SPI
4958 <GIC_SPI
4959 <GIC_SPI
4960 <GIC_SPI
4961 <GIC_SPI
4962 <GIC_SPI
4963 <GIC_SPI
4964 <GIC_SPI
4965 <GIC_SPI
4966 <GIC_SPI
4967 <GIC_SPI
4968 <GIC_SPI
4969 <GIC_SPI
4970 <GIC_SPI
4971 <GIC_SPI
4972 <GIC_SPI
4973 <GIC_SPI
4974 <GIC_SPI
4975 <GIC_SPI
4976 <GIC_SPI
4977 <GIC_SPI
4978 <GIC_SPI
4979 <GIC_SPI
4980 <GIC_SPI
4981 <GIC_SPI
4982 <GIC_SPI
4983 <GIC_SPI
4984 <GIC_SPI
4985 <GIC_SPI
4986 <GIC_SPI
4987 <GIC_SPI
4988 <GIC_SPI
4989 <GIC_SPI
4990 <GIC_SPI
4991 <GIC_SPI
4992 <GIC_SPI
4993 <GIC_SPI
4994 <GIC_SPI
4995 <GIC_SPI
4996 <GIC_SPI
4997 <GIC_SPI
4998 <GIC_SPI
4999 <GIC_SPI
5000 <GIC_SPI
5001 <GIC_SPI
5002 <GIC_SPI
5003 <GIC_SPI
5004 <GIC_SPI
5005 <GIC_SPI
5006 <GIC_SPI
5007 <GIC_SPI
5008 <GIC_SPI
5009 <GIC_SPI
5010 <GIC_SPI
5011 };
5012
5013 intc: interrupt-controller@17
5014 compatible = "arm,gic
5015 interrupt-controller;
5016 #interrupt-cells = <3
5017 reg = <0x0 0x17a00000
5018 <0x0 0x17a60000
5019 interrupts = <GIC_PPI
5020 #redistributor-region
5021 redistributor-stride
5022
5023 #address-cells = <2>;
5024 #size-cells = <2>;
5025 ranges;
5026
5027 its: msi-controller@1
5028 compatible =
5029 reg = <0 0x17
5030 msi-controlle
5031 #msi-cells =
5032 };
5033 };
5034
5035 watchdog@17c10000 {
5036 compatible = "qcom,ap
5037 reg = <0 0x17c10000 0
5038 clocks = <&sleep_clk>
5039 interrupts = <GIC_SPI
5040 };
5041
5042 timer@17c20000 {
5043 compatible = "arm,arm
5044 reg = <0x0 0x17c20000
5045 #address-cells = <1>;
5046 #size-cells = <1>;
5047 ranges = <0x0 0x0 0x0
5048
5049 frame@17c21000 {
5050 frame-number
5051 interrupts =
5052
5053 reg = <0x17c2
5054 <0x17c2
5055 };
5056
5057 frame@17c23000 {
5058 frame-number
5059 interrupts =
5060 reg = <0x17c2
5061 status = "dis
5062 };
5063
5064 frame@17c25000 {
5065 frame-number
5066 interrupts =
5067 reg = <0x17c2
5068 status = "dis
5069 };
5070
5071 frame@17c27000 {
5072 frame-number
5073 interrupts =
5074 reg = <0x17c2
5075 status = "dis
5076 };
5077
5078 frame@17c29000 {
5079 frame-number
5080 interrupts =
5081 reg = <0x17c2
5082 status = "dis
5083 };
5084
5085 frame@17c2b000 {
5086 frame-number
5087 interrupts =
5088 reg = <0x17c2
5089 status = "dis
5090 };
5091
5092 frame@17c2d000 {
5093 frame-number
5094 interrupts =
5095 reg = <0x17c2
5096 status = "dis
5097 };
5098 };
5099
5100 apps_rsc: rsc@18200000 {
5101 compatible = "qcom,rp
5102 reg = <0x0 0x18200000
5103 <0x0 0x182100
5104 <0x0 0x182200
5105 reg-names = "drv-0",
5106 interrupts = <GIC_SPI
5107 <GIC_SPI
5108 <GIC_SPI
5109 qcom,tcs-offset = <0x
5110 qcom,drv-id = <2>;
5111 qcom,tcs-config = <AC
5112 <WA
5113 label = "apps_rsc";
5114 power-domains = <&CLU
5115
5116 apps_bcm_voter: bcm-v
5117 compatible =
5118 };
5119
5120 rpmhcc: clock-control
5121 compatible =
5122 #clock-cells
5123 clock-names =
5124 clocks = <&xo
5125 };
5126
5127 rpmhpd: power-control
5128 compatible =
5129 #power-domain
5130 operating-poi
5131
5132 rpmhpd_opp_ta
5133 compa
5134
5135 rpmhp
5136
5137 };
5138
5139 rpmhp
5140
5141 };
5142
5143 rpmhp
5144
5145 };
5146
5147 rpmhp
5148
5149 };
5150
5151 rpmhp
5152
5153 };
5154
5155 rpmhp
5156
5157 };
5158
5159 rpmhp
5160
5161 };
5162
5163 rpmhp
5164
5165 };
5166
5167 rpmhp
5168
5169 };
5170
5171 rpmhp
5172
5173 };
5174 };
5175 };
5176 };
5177
5178 epss_l3: interconnect@1859000
5179 compatible = "qcom,sc
5180 reg = <0 0x18590000 0
5181
5182 clocks = <&rpmhcc RPM
5183 clock-names = "xo", "
5184
5185 #interconnect-cells =
5186 };
5187
5188 cpufreq_hw: cpufreq@18591000
5189 compatible = "qcom,sc
5190 reg = <0 0x18591000 0
5191 <0 0x18592000 0
5192 reg-names = "freq-dom
5193
5194 interrupts = <GIC_SPI
5195 <GIC_SPI
5196 interrupt-names = "dc
5197 "dc
5198
5199 clocks = <&rpmhcc RPM
5200 clock-names = "xo", "
5201
5202 #freq-domain-cells =
5203 #clock-cells = <1>;
5204 };
5205
5206 remoteproc_nsp0: remoteproc@1
5207 compatible = "qcom,sc
5208 reg = <0 0x1b300000 0
5209
5210 interrupts-extended =
5211
5212
5213
5214
5215 interrupt-names = "wd
5216 "ha
5217
5218 clocks = <&rpmhcc RPM
5219 clock-names = "xo";
5220
5221 power-domains = <&rpm
5222 power-domain-names =
5223
5224 memory-region = <&pil
5225
5226 qcom,smem-states = <&
5227 qcom,smem-state-names
5228
5229 interconnects = <&nsp
5230
5231 status = "disabled";
5232
5233 glink-edge {
5234 interrupts-ex
5235
5236
5237 mboxes = <&ip
5238
5239
5240 label = "nsp0
5241 qcom,remote-p
5242
5243 fastrpc {
5244 compa
5245 qcom,
5246 label
5247 #addr
5248 #size
5249
5250 compu
5251
5252
5253
5254 };
5255
5256 compu
5257
5258
5259
5260 };
5261
5262 compu
5263
5264
5265
5266 };
5267
5268 compu
5269
5270
5271
5272 };
5273
5274 compu
5275
5276
5277
5278 };
5279
5280 compu
5281
5282
5283
5284 };
5285
5286 compu
5287
5288
5289
5290 };
5291
5292 compu
5293
5294
5295
5296 };
5297
5298 compu
5299
5300
5301
5302 };
5303
5304 compu
5305
5306
5307
5308 };
5309
5310 compu
5311
5312
5313
5314 };
5315
5316 compu
5317
5318
5319
5320 };
5321
5322 compu
5323
5324
5325
5326 };
5327
5328 compu
5329
5330
5331
5332 };
5333 };
5334 };
5335 };
5336
5337 remoteproc_nsp1: remoteproc@2
5338 compatible = "qcom,sc
5339 reg = <0 0x21300000 0
5340
5341 interrupts-extended =
5342
5343
5344
5345
5346 interrupt-names = "wd
5347 "ha
5348
5349 clocks = <&rpmhcc RPM
5350 clock-names = "xo";
5351
5352 power-domains = <&rpm
5353 power-domain-names =
5354
5355 memory-region = <&pil
5356
5357 qcom,smem-states = <&
5358 qcom,smem-state-names
5359
5360 interconnects = <&nsp
5361
5362 status = "disabled";
5363
5364 glink-edge {
5365 interrupts-ex
5366
5367
5368 mboxes = <&ip
5369
5370
5371 label = "nsp1
5372 qcom,remote-p
5373 };
5374 };
5375
5376 mdss1: display-subsystem@2200
5377 compatible = "qcom,sc
5378 reg = <0 0x22000000 0
5379 reg-names = "mdss";
5380
5381 clocks = <&gcc GCC_DI
5382 <&dispcc1 DI
5383 <&dispcc1 DI
5384 clock-names = "iface"
5385 "ahb",
5386 "core";
5387 interconnects = <&mms
5388 <&mms
5389 interconnect-names =
5390 interrupts = <GIC_SPI
5391
5392 iommus = <&apps_smmu
5393 power-domains = <&dis
5394 resets = <&dispcc1 DI
5395
5396 interrupt-controller;
5397 #interrupt-cells = <1
5398 #address-cells = <2>;
5399 #size-cells = <2>;
5400 ranges;
5401
5402 status = "disabled";
5403
5404 mdss1_mdp: display-co
5405 compatible =
5406 reg = <0 0x22
5407 <0 0x22
5408 reg-names = "
5409
5410 clocks = <&gc
5411 <&gc
5412 <&di
5413 <&di
5414 <&di
5415 <&di
5416 clock-names =
5417
5418
5419
5420
5421
5422 interrupt-par
5423 interrupts =
5424 power-domains
5425
5426 assigned-cloc
5427 assigned-cloc
5428 operating-poi
5429
5430 ports {
5431 #addr
5432 #size
5433
5434 port@
5435
5436
5437
5438
5439 };
5440
5441 port@
5442
5443
5444
5445
5446 };
5447
5448 port@
5449
5450
5451
5452
5453 };
5454
5455 port@
5456
5457
5458
5459
5460 };
5461 };
5462
5463 mdss1_mdp_opp
5464 compa
5465
5466 opp-2
5467
5468
5469 };
5470
5471 opp-3
5472
5473
5474 };
5475
5476 opp-3
5477
5478
5479 };
5480
5481 opp-5
5482
5483
5484 };
5485 opp-6
5486
5487
5488 };
5489 };
5490 };
5491
5492 mdss1_dp0: displaypor
5493 compatible =
5494 reg = <0 0x22
5495 <0 0x22
5496 <0 0x22
5497 <0 0x22
5498 <0 0x22
5499
5500 clocks = <&di
5501 <&di
5502 <&di
5503 <&di
5504 <&di
5505 clock-names =
5506
5507
5508 interrupt-par
5509 interrupts =
5510 phys = <&mdss
5511 phy-names = "
5512 power-domains
5513
5514 assigned-cloc
5515
5516 assigned-cloc
5517 operating-poi
5518
5519 #sound-dai-ce
5520
5521 status = "dis
5522
5523 ports {
5524 #addr
5525 #size
5526
5527 port@
5528
5529
5530
5531
5532 };
5533
5534 port@
5535
5536 };
5537 };
5538
5539 mdss1_dp0_opp
5540 compa
5541
5542 opp-1
5543
5544
5545 };
5546
5547 opp-2
5548
5549
5550 };
5551
5552 opp-5
5553
5554
5555 };
5556
5557 opp-8
5558
5559
5560 };
5561 };
5562 };
5563
5564 mdss1_dp1: displaypor
5565 compatible =
5566 reg = <0 0x22
5567 <0 0x22
5568 <0 0x22
5569 <0 0x22
5570 <0 0x22
5571
5572 clocks = <&di
5573 <&di
5574 <&di
5575 <&di
5576 <&di
5577 clock-names =
5578
5579
5580 interrupt-par
5581 interrupts =
5582 phys = <&mdss
5583 phy-names = "
5584 power-domains
5585
5586 assigned-cloc
5587
5588 assigned-cloc
5589 operating-poi
5590
5591 #sound-dai-ce
5592
5593 status = "dis
5594
5595 ports {
5596 #addr
5597 #size
5598
5599 port@
5600
5601
5602
5603
5604 };
5605
5606 port@
5607
5608 };
5609 };
5610
5611 mdss1_dp1_opp
5612 compa
5613
5614 opp-1
5615
5616
5617 };
5618
5619 opp-2
5620
5621
5622 };
5623
5624 opp-5
5625
5626
5627 };
5628
5629 opp-8
5630
5631
5632 };
5633 };
5634 };
5635
5636 mdss1_dp2: displaypor
5637 compatible =
5638 reg = <0 0x22
5639 <0 0x22
5640 <0 0x22
5641 <0 0x22
5642 <0 0x22
5643
5644 clocks = <&di
5645 <&di
5646 <&di
5647 <&di
5648 <&di
5649 clock-names =
5650
5651
5652 interrupt-par
5653 interrupts =
5654 phys = <&mdss
5655 phy-names = "
5656 power-domains
5657
5658 assigned-cloc
5659
5660 assigned-cloc
5661 operating-poi
5662
5663 #sound-dai-ce
5664
5665 status = "dis
5666
5667 ports {
5668 #addr
5669 #size
5670
5671 port@
5672
5673
5674
5675
5676 };
5677
5678 port@
5679
5680 };
5681 };
5682
5683 mdss1_dp2_opp
5684 compa
5685
5686 opp-1
5687
5688
5689 };
5690
5691 opp-2
5692
5693
5694 };
5695
5696 opp-5
5697
5698
5699 };
5700
5701 opp-8
5702
5703
5704 };
5705 };
5706 };
5707
5708 mdss1_dp3: displaypor
5709 compatible =
5710 reg = <0 0x22
5711 <0 0x22
5712 <0 0x22
5713 <0 0x22
5714 <0 0x22
5715
5716 clocks = <&di
5717 <&di
5718 <&di
5719 <&di
5720 <&di
5721 clock-names =
5722
5723
5724 interrupt-par
5725 interrupts =
5726 phys = <&mdss
5727 phy-names = "
5728 power-domains
5729
5730 assigned-cloc
5731
5732 assigned-cloc
5733 operating-poi
5734
5735 #sound-dai-ce
5736
5737 status = "dis
5738
5739 ports {
5740 #addr
5741 #size
5742
5743 port@
5744
5745
5746
5747
5748 };
5749
5750 port@
5751
5752 };
5753 };
5754
5755 mdss1_dp3_opp
5756 compa
5757
5758 opp-1
5759
5760
5761 };
5762
5763 opp-2
5764
5765
5766 };
5767
5768 opp-5
5769
5770
5771 };
5772
5773 opp-8
5774
5775
5776 };
5777 };
5778 };
5779 };
5780
5781 mdss1_dp2_phy: phy@220c2a00 {
5782 compatible = "qcom,sc
5783 reg = <0 0x220c2a00 0
5784 <0 0x220c2200 0
5785 <0 0x220c2600 0
5786 <0 0x220c2000 0
5787
5788 clocks = <&dispcc1 DI
5789 <&dispcc1 DI
5790 clock-names = "aux",
5791 power-domains = <&rpm
5792
5793 #clock-cells = <1>;
5794 #phy-cells = <0>;
5795
5796 status = "disabled";
5797 };
5798
5799 mdss1_dp3_phy: phy@220c5a00 {
5800 compatible = "qcom,sc
5801 reg = <0 0x220c5a00 0
5802 <0 0x220c5200 0
5803 <0 0x220c5600 0
5804 <0 0x220c5000 0
5805
5806 clocks = <&dispcc1 DI
5807 <&dispcc1 DI
5808 clock-names = "aux",
5809 power-domains = <&rpm
5810
5811 #clock-cells = <1>;
5812 #phy-cells = <0>;
5813
5814 status = "disabled";
5815 };
5816
5817 dispcc1: clock-controller@221
5818 compatible = "qcom,sc
5819 reg = <0 0x22100000 0
5820
5821 clocks = <&gcc GCC_DI
5822 <&rpmhcc RPM
5823 <0>,
5824 <&mdss1_dp0_
5825 <&mdss1_dp0_
5826 <&mdss1_dp1_
5827 <&mdss1_dp1_
5828 <&mdss1_dp2_
5829 <&mdss1_dp2_
5830 <&mdss1_dp3_
5831 <&mdss1_dp3_
5832 <0>,
5833 <0>,
5834 <0>,
5835 <0>;
5836 power-domains = <&rpm
5837
5838 #clock-cells = <1>;
5839 #power-domain-cells =
5840 #reset-cells = <1>;
5841
5842 status = "disabled";
5843 };
5844
5845 ethernet1: ethernet@23000000
5846 compatible = "qcom,sc
5847 reg = <0x0 0x23000000
5848 <0x0 0x23016000
5849 reg-names = "stmmacet
5850
5851 clocks = <&gcc GCC_EM
5852 <&gcc GCC_EM
5853 <&gcc GCC_EM
5854 <&gcc GCC_EM
5855 clock-names = "stmmac
5856 "pclk",
5857 "ptp_re
5858 "rgmii"
5859
5860 interrupts = <GIC_SPI
5861 <GIC_SPI
5862 interrupt-names = "ma
5863
5864 iommus = <&apps_smmu
5865 power-domains = <&gcc
5866
5867 snps,tso;
5868 snps,pbl = <32>;
5869 rx-fifo-depth = <4096
5870 tx-fifo-depth = <4096
5871
5872 status = "disabled";
5873 };
5874 };
5875
5876 sound: sound {
5877 };
5878
5879 thermal-zones {
5880 cpu0-thermal {
5881 polling-delay-passive
5882
5883 thermal-sensors = <&t
5884
5885 trips {
5886 cpu-crit {
5887 tempe
5888 hyste
5889 type
5890 };
5891 };
5892 };
5893
5894 cpu1-thermal {
5895 polling-delay-passive
5896
5897 thermal-sensors = <&t
5898
5899 trips {
5900 cpu-crit {
5901 tempe
5902 hyste
5903 type
5904 };
5905 };
5906 };
5907
5908 cpu2-thermal {
5909 polling-delay-passive
5910
5911 thermal-sensors = <&t
5912
5913 trips {
5914 cpu-crit {
5915 tempe
5916 hyste
5917 type
5918 };
5919 };
5920 };
5921
5922 cpu3-thermal {
5923 polling-delay-passive
5924
5925 thermal-sensors = <&t
5926
5927 trips {
5928 cpu-crit {
5929 tempe
5930 hyste
5931 type
5932 };
5933 };
5934 };
5935
5936 cpu4-thermal {
5937 polling-delay-passive
5938
5939 thermal-sensors = <&t
5940
5941 trips {
5942 cpu-crit {
5943 tempe
5944 hyste
5945 type
5946 };
5947 };
5948 };
5949
5950 cpu5-thermal {
5951 polling-delay-passive
5952
5953 thermal-sensors = <&t
5954
5955 trips {
5956 cpu-crit {
5957 tempe
5958 hyste
5959 type
5960 };
5961 };
5962 };
5963
5964 cpu6-thermal {
5965 polling-delay-passive
5966
5967 thermal-sensors = <&t
5968
5969 trips {
5970 cpu-crit {
5971 tempe
5972 hyste
5973 type
5974 };
5975 };
5976 };
5977
5978 cpu7-thermal {
5979 polling-delay-passive
5980
5981 thermal-sensors = <&t
5982
5983 trips {
5984 cpu-crit {
5985 tempe
5986 hyste
5987 type
5988 };
5989 };
5990 };
5991
5992 cluster0-thermal {
5993 polling-delay-passive
5994
5995 thermal-sensors = <&t
5996
5997 trips {
5998 cpu-crit {
5999 tempe
6000 hyste
6001 type
6002 };
6003 };
6004 };
6005
6006 gpu-thermal {
6007 polling-delay-passive
6008
6009 thermal-sensors = <&t
6010
6011 cooling-maps {
6012 map0 {
6013 trip
6014 cooli
6015 };
6016 };
6017
6018 trips {
6019 gpu_alert0: t
6020 tempe
6021 hyste
6022 type
6023 };
6024
6025 trip-point1 {
6026 tempe
6027 hyste
6028 type
6029 };
6030 };
6031 };
6032
6033 mem-thermal {
6034 polling-delay-passive
6035
6036 thermal-sensors = <&t
6037
6038 trips {
6039 trip-point0 {
6040 tempe
6041 hyste
6042 type
6043 };
6044 };
6045 };
6046 };
6047
6048 timer {
6049 compatible = "arm,armv8-timer
6050 interrupts = <GIC_PPI 13 (GIC
6051 <GIC_PPI 14 (GIC
6052 <GIC_PPI 11 (GIC
6053 <GIC_PPI 10 (GIC
6054 };
6055 };
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