1 // SPDX-License-Identifier: BSD-3-Clause 1 // SPDX-License-Identifier: BSD-3-Clause
2 /* 2 /*
3 * Copyright (c) 2021, The Linux Foundation. A 3 * Copyright (c) 2021, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2022, Linaro Limited 4 * Copyright (c) 2022, Linaro Limited
5 */ 5 */
6 6
7 #include <dt-bindings/clock/qcom,dispcc-sc8280 <<
8 #include <dt-bindings/clock/qcom,gcc-sc8280xp. 7 #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
9 #include <dt-bindings/clock/qcom,gpucc-sc8280x <<
10 #include <dt-bindings/clock/qcom,rpmh.h> 8 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/clock/qcom,sc8280xp-camc <<
12 #include <dt-bindings/clock/qcom,sc8280xp-lpas <<
13 #include <dt-bindings/interconnect/qcom,osm-l3 9 #include <dt-bindings/interconnect/qcom,osm-l3.h>
14 #include <dt-bindings/interconnect/qcom,sc8280 10 #include <dt-bindings/interconnect/qcom,sc8280xp.h>
15 #include <dt-bindings/interrupt-controller/arm 11 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/mailbox/qcom-ipcc.h> 12 #include <dt-bindings/mailbox/qcom-ipcc.h>
17 #include <dt-bindings/phy/phy-qcom-qmp.h> 13 #include <dt-bindings/phy/phy-qcom-qmp.h>
18 #include <dt-bindings/power/qcom-rpmpd.h> 14 #include <dt-bindings/power/qcom-rpmpd.h>
19 #include <dt-bindings/soc/qcom,gpr.h> <<
20 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 15 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
21 #include <dt-bindings/sound/qcom,q6afe.h> <<
22 #include <dt-bindings/thermal/thermal.h> 16 #include <dt-bindings/thermal/thermal.h>
23 17
24 / { 18 / {
25 interrupt-parent = <&intc>; 19 interrupt-parent = <&intc>;
26 20
27 #address-cells = <2>; 21 #address-cells = <2>;
28 #size-cells = <2>; 22 #size-cells = <2>;
29 23
30 clocks { 24 clocks {
31 xo_board_clk: xo-board-clk { 25 xo_board_clk: xo-board-clk {
32 compatible = "fixed-cl 26 compatible = "fixed-clock";
33 #clock-cells = <0>; 27 #clock-cells = <0>;
34 }; 28 };
35 29
36 sleep_clk: sleep-clk { 30 sleep_clk: sleep-clk {
37 compatible = "fixed-cl 31 compatible = "fixed-clock";
38 #clock-cells = <0>; 32 #clock-cells = <0>;
39 clock-frequency = <327 33 clock-frequency = <32764>;
40 }; 34 };
41 }; 35 };
42 36
>> 37 cpu0_opp_table: cpu0-opp-table {
>> 38 compatible = "operating-points-v2";
>> 39 opp-shared;
>> 40
>> 41 opp-300000000 {
>> 42 opp-hz = /bits/ 64 <300000000>;
>> 43 opp-peak-kBps = <(300000 * 32)>;
>> 44 };
>> 45 opp-403200000 {
>> 46 opp-hz = /bits/ 64 <403200000>;
>> 47 opp-peak-kBps = <(384000 * 32)>;
>> 48 };
>> 49 opp-499200000 {
>> 50 opp-hz = /bits/ 64 <499200000>;
>> 51 opp-peak-kBps = <(480000 * 32)>;
>> 52 };
>> 53 opp-595200000 {
>> 54 opp-hz = /bits/ 64 <595200000>;
>> 55 opp-peak-kBps = <(576000 * 32)>;
>> 56 };
>> 57 opp-691200000 {
>> 58 opp-hz = /bits/ 64 <691200000>;
>> 59 opp-peak-kBps = <(672000 * 32)>;
>> 60 };
>> 61 opp-806400000 {
>> 62 opp-hz = /bits/ 64 <806400000>;
>> 63 opp-peak-kBps = <(768000 * 32)>;
>> 64 };
>> 65 opp-902400000 {
>> 66 opp-hz = /bits/ 64 <902400000>;
>> 67 opp-peak-kBps = <(864000 * 32)>;
>> 68 };
>> 69 opp-1017600000 {
>> 70 opp-hz = /bits/ 64 <1017600000>;
>> 71 opp-peak-kBps = <(960000 * 32)>;
>> 72 };
>> 73 opp-1113600000 {
>> 74 opp-hz = /bits/ 64 <1113600000>;
>> 75 opp-peak-kBps = <(1075200 * 32)>;
>> 76 };
>> 77 opp-1209600000 {
>> 78 opp-hz = /bits/ 64 <1209600000>;
>> 79 opp-peak-kBps = <(1171200 * 32)>;
>> 80 };
>> 81 opp-1324800000 {
>> 82 opp-hz = /bits/ 64 <1324800000>;
>> 83 opp-peak-kBps = <(1267200 * 32)>;
>> 84 };
>> 85 opp-1440000000 {
>> 86 opp-hz = /bits/ 64 <1440000000>;
>> 87 opp-peak-kBps = <(1363200 * 32)>;
>> 88 };
>> 89 opp-1555200000 {
>> 90 opp-hz = /bits/ 64 <1555200000>;
>> 91 opp-peak-kBps = <(1536000 * 32)>;
>> 92 };
>> 93 opp-1670400000 {
>> 94 opp-hz = /bits/ 64 <1670400000>;
>> 95 opp-peak-kBps = <(1612800 * 32)>;
>> 96 };
>> 97 opp-1785600000 {
>> 98 opp-hz = /bits/ 64 <1785600000>;
>> 99 opp-peak-kBps = <(1689600 * 32)>;
>> 100 };
>> 101 opp-1881600000 {
>> 102 opp-hz = /bits/ 64 <1881600000>;
>> 103 opp-peak-kBps = <(1689600 * 32)>;
>> 104 };
>> 105 opp-1996800000 {
>> 106 opp-hz = /bits/ 64 <1996800000>;
>> 107 opp-peak-kBps = <(1689600 * 32)>;
>> 108 };
>> 109 opp-2112000000 {
>> 110 opp-hz = /bits/ 64 <2112000000>;
>> 111 opp-peak-kBps = <(1689600 * 32)>;
>> 112 };
>> 113 opp-2227200000 {
>> 114 opp-hz = /bits/ 64 <2227200000>;
>> 115 opp-peak-kBps = <(1689600 * 32)>;
>> 116 };
>> 117 opp-2342400000 {
>> 118 opp-hz = /bits/ 64 <2342400000>;
>> 119 opp-peak-kBps = <(1689600 * 32)>;
>> 120 };
>> 121 opp-2438400000 {
>> 122 opp-hz = /bits/ 64 <2438400000>;
>> 123 opp-peak-kBps = <(1689600 * 32)>;
>> 124 };
>> 125 };
>> 126
>> 127 cpu4_opp_table: cpu4-opp-table {
>> 128 compatible = "operating-points-v2";
>> 129 opp-shared;
>> 130
>> 131 opp-825600000 {
>> 132 opp-hz = /bits/ 64 <825600000>;
>> 133 opp-peak-kBps = <(768000 * 32)>;
>> 134 };
>> 135 opp-940800000 {
>> 136 opp-hz = /bits/ 64 <940800000>;
>> 137 opp-peak-kBps = <(864000 * 32)>;
>> 138 };
>> 139 opp-1056000000 {
>> 140 opp-hz = /bits/ 64 <1056000000>;
>> 141 opp-peak-kBps = <(960000 * 32)>;
>> 142 };
>> 143 opp-1171200000 {
>> 144 opp-hz = /bits/ 64 <1171200000>;
>> 145 opp-peak-kBps = <(1171200 * 32)>;
>> 146 };
>> 147 opp-1286400000 {
>> 148 opp-hz = /bits/ 64 <1286400000>;
>> 149 opp-peak-kBps = <(1267200 * 32)>;
>> 150 };
>> 151 opp-1401600000 {
>> 152 opp-hz = /bits/ 64 <1401600000>;
>> 153 opp-peak-kBps = <(1363200 * 32)>;
>> 154 };
>> 155 opp-1516800000 {
>> 156 opp-hz = /bits/ 64 <1516800000>;
>> 157 opp-peak-kBps = <(1459200 * 32)>;
>> 158 };
>> 159 opp-1632000000 {
>> 160 opp-hz = /bits/ 64 <1632000000>;
>> 161 opp-peak-kBps = <(1612800 * 32)>;
>> 162 };
>> 163 opp-1747200000 {
>> 164 opp-hz = /bits/ 64 <1747200000>;
>> 165 opp-peak-kBps = <(1689600 * 32)>;
>> 166 };
>> 167 opp-1862400000 {
>> 168 opp-hz = /bits/ 64 <1862400000>;
>> 169 opp-peak-kBps = <(1689600 * 32)>;
>> 170 };
>> 171 opp-1977600000 {
>> 172 opp-hz = /bits/ 64 <1977600000>;
>> 173 opp-peak-kBps = <(1689600 * 32)>;
>> 174 };
>> 175 opp-2073600000 {
>> 176 opp-hz = /bits/ 64 <2073600000>;
>> 177 opp-peak-kBps = <(1689600 * 32)>;
>> 178 };
>> 179 opp-2169600000 {
>> 180 opp-hz = /bits/ 64 <2169600000>;
>> 181 opp-peak-kBps = <(1689600 * 32)>;
>> 182 };
>> 183 opp-2284800000 {
>> 184 opp-hz = /bits/ 64 <2284800000>;
>> 185 opp-peak-kBps = <(1689600 * 32)>;
>> 186 };
>> 187 opp-2400000000 {
>> 188 opp-hz = /bits/ 64 <2400000000>;
>> 189 opp-peak-kBps = <(1689600 * 32)>;
>> 190 };
>> 191 opp-2496000000 {
>> 192 opp-hz = /bits/ 64 <2496000000>;
>> 193 opp-peak-kBps = <(1689600 * 32)>;
>> 194 };
>> 195 opp-2592000000 {
>> 196 opp-hz = /bits/ 64 <2592000000>;
>> 197 opp-peak-kBps = <(1689600 * 32)>;
>> 198 };
>> 199 opp-2688000000 {
>> 200 opp-hz = /bits/ 64 <2688000000>;
>> 201 opp-peak-kBps = <(1689600 * 32)>;
>> 202 };
>> 203 opp-2803200000 {
>> 204 opp-hz = /bits/ 64 <2803200000>;
>> 205 opp-peak-kBps = <(1689600 * 32)>;
>> 206 };
>> 207 opp-2899200000 {
>> 208 opp-hz = /bits/ 64 <2899200000>;
>> 209 opp-peak-kBps = <(1689600 * 32)>;
>> 210 };
>> 211 opp-2995200000 {
>> 212 opp-hz = /bits/ 64 <2995200000>;
>> 213 opp-peak-kBps = <(1689600 * 32)>;
>> 214 };
>> 215 };
>> 216
43 cpus { 217 cpus {
44 #address-cells = <2>; 218 #address-cells = <2>;
45 #size-cells = <0>; 219 #size-cells = <0>;
46 220
47 CPU0: cpu@0 { 221 CPU0: cpu@0 {
48 device_type = "cpu"; 222 device_type = "cpu";
49 compatible = "arm,cort !! 223 compatible = "qcom,kryo";
50 reg = <0x0 0x0>; 224 reg = <0x0 0x0>;
51 clocks = <&cpufreq_hw <<
52 enable-method = "psci" 225 enable-method = "psci";
53 capacity-dmips-mhz = < !! 226 capacity-dmips-mhz = <602>;
54 dynamic-power-coeffici <<
55 next-level-cache = <&L 227 next-level-cache = <&L2_0>;
56 power-domains = <&CPU_ 228 power-domains = <&CPU_PD0>;
57 power-domain-names = " 229 power-domain-names = "psci";
58 qcom,freq-domain = <&c 230 qcom,freq-domain = <&cpufreq_hw 0>;
59 operating-points-v2 = 231 operating-points-v2 = <&cpu0_opp_table>;
60 interconnects = <&epss 232 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
61 #cooling-cells = <2>; 233 #cooling-cells = <2>;
62 L2_0: l2-cache { 234 L2_0: l2-cache {
63 compatible = " 235 compatible = "cache";
64 cache-level = <<
65 cache-unified; <<
66 next-level-cac 236 next-level-cache = <&L3_0>;
67 L3_0: l3-cache 237 L3_0: l3-cache {
68 compat !! 238 compatible = "cache";
69 cache- <<
70 cache- <<
71 }; 239 };
72 }; 240 };
73 }; 241 };
74 242
75 CPU1: cpu@100 { 243 CPU1: cpu@100 {
76 device_type = "cpu"; 244 device_type = "cpu";
77 compatible = "arm,cort !! 245 compatible = "qcom,kryo";
78 reg = <0x0 0x100>; 246 reg = <0x0 0x100>;
79 clocks = <&cpufreq_hw <<
80 enable-method = "psci" 247 enable-method = "psci";
81 capacity-dmips-mhz = < !! 248 capacity-dmips-mhz = <602>;
82 dynamic-power-coeffici <<
83 next-level-cache = <&L 249 next-level-cache = <&L2_100>;
84 power-domains = <&CPU_ 250 power-domains = <&CPU_PD1>;
85 power-domain-names = " 251 power-domain-names = "psci";
86 qcom,freq-domain = <&c 252 qcom,freq-domain = <&cpufreq_hw 0>;
87 operating-points-v2 = 253 operating-points-v2 = <&cpu0_opp_table>;
88 interconnects = <&epss 254 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
89 #cooling-cells = <2>; 255 #cooling-cells = <2>;
90 L2_100: l2-cache { 256 L2_100: l2-cache {
91 compatible = " 257 compatible = "cache";
92 cache-level = <<
93 cache-unified; <<
94 next-level-cac 258 next-level-cache = <&L3_0>;
95 }; 259 };
96 }; 260 };
97 261
98 CPU2: cpu@200 { 262 CPU2: cpu@200 {
99 device_type = "cpu"; 263 device_type = "cpu";
100 compatible = "arm,cort !! 264 compatible = "qcom,kryo";
101 reg = <0x0 0x200>; 265 reg = <0x0 0x200>;
102 clocks = <&cpufreq_hw <<
103 enable-method = "psci" 266 enable-method = "psci";
104 capacity-dmips-mhz = < !! 267 capacity-dmips-mhz = <602>;
105 dynamic-power-coeffici <<
106 next-level-cache = <&L 268 next-level-cache = <&L2_200>;
107 power-domains = <&CPU_ 269 power-domains = <&CPU_PD2>;
108 power-domain-names = " 270 power-domain-names = "psci";
109 qcom,freq-domain = <&c 271 qcom,freq-domain = <&cpufreq_hw 0>;
110 operating-points-v2 = 272 operating-points-v2 = <&cpu0_opp_table>;
111 interconnects = <&epss 273 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
112 #cooling-cells = <2>; 274 #cooling-cells = <2>;
113 L2_200: l2-cache { 275 L2_200: l2-cache {
114 compatible = " 276 compatible = "cache";
115 cache-level = <<
116 cache-unified; <<
117 next-level-cac 277 next-level-cache = <&L3_0>;
118 }; 278 };
119 }; 279 };
120 280
121 CPU3: cpu@300 { 281 CPU3: cpu@300 {
122 device_type = "cpu"; 282 device_type = "cpu";
123 compatible = "arm,cort !! 283 compatible = "qcom,kryo";
124 reg = <0x0 0x300>; 284 reg = <0x0 0x300>;
125 clocks = <&cpufreq_hw <<
126 enable-method = "psci" 285 enable-method = "psci";
127 capacity-dmips-mhz = < !! 286 capacity-dmips-mhz = <602>;
128 dynamic-power-coeffici <<
129 next-level-cache = <&L 287 next-level-cache = <&L2_300>;
130 power-domains = <&CPU_ 288 power-domains = <&CPU_PD3>;
131 power-domain-names = " 289 power-domain-names = "psci";
132 qcom,freq-domain = <&c 290 qcom,freq-domain = <&cpufreq_hw 0>;
133 operating-points-v2 = 291 operating-points-v2 = <&cpu0_opp_table>;
134 interconnects = <&epss 292 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
135 #cooling-cells = <2>; 293 #cooling-cells = <2>;
136 L2_300: l2-cache { 294 L2_300: l2-cache {
137 compatible = " 295 compatible = "cache";
138 cache-level = <<
139 cache-unified; <<
140 next-level-cac 296 next-level-cache = <&L3_0>;
141 }; 297 };
142 }; 298 };
143 299
144 CPU4: cpu@400 { 300 CPU4: cpu@400 {
145 device_type = "cpu"; 301 device_type = "cpu";
146 compatible = "arm,cort !! 302 compatible = "qcom,kryo";
147 reg = <0x0 0x400>; 303 reg = <0x0 0x400>;
148 clocks = <&cpufreq_hw <<
149 enable-method = "psci" 304 enable-method = "psci";
150 capacity-dmips-mhz = < 305 capacity-dmips-mhz = <1024>;
151 dynamic-power-coeffici <<
152 next-level-cache = <&L 306 next-level-cache = <&L2_400>;
153 power-domains = <&CPU_ 307 power-domains = <&CPU_PD4>;
154 power-domain-names = " 308 power-domain-names = "psci";
155 qcom,freq-domain = <&c 309 qcom,freq-domain = <&cpufreq_hw 1>;
156 operating-points-v2 = 310 operating-points-v2 = <&cpu4_opp_table>;
157 interconnects = <&epss 311 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
158 #cooling-cells = <2>; 312 #cooling-cells = <2>;
159 L2_400: l2-cache { 313 L2_400: l2-cache {
160 compatible = " 314 compatible = "cache";
161 cache-level = <<
162 cache-unified; <<
163 next-level-cac 315 next-level-cache = <&L3_0>;
164 }; 316 };
165 }; 317 };
166 318
167 CPU5: cpu@500 { 319 CPU5: cpu@500 {
168 device_type = "cpu"; 320 device_type = "cpu";
169 compatible = "arm,cort !! 321 compatible = "qcom,kryo";
170 reg = <0x0 0x500>; 322 reg = <0x0 0x500>;
171 clocks = <&cpufreq_hw <<
172 enable-method = "psci" 323 enable-method = "psci";
173 capacity-dmips-mhz = < 324 capacity-dmips-mhz = <1024>;
174 dynamic-power-coeffici <<
175 next-level-cache = <&L 325 next-level-cache = <&L2_500>;
176 power-domains = <&CPU_ 326 power-domains = <&CPU_PD5>;
177 power-domain-names = " 327 power-domain-names = "psci";
178 qcom,freq-domain = <&c 328 qcom,freq-domain = <&cpufreq_hw 1>;
179 operating-points-v2 = 329 operating-points-v2 = <&cpu4_opp_table>;
180 interconnects = <&epss 330 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
181 #cooling-cells = <2>; 331 #cooling-cells = <2>;
182 L2_500: l2-cache { 332 L2_500: l2-cache {
183 compatible = " 333 compatible = "cache";
184 cache-level = <<
185 cache-unified; <<
186 next-level-cac 334 next-level-cache = <&L3_0>;
187 }; 335 };
188 }; 336 };
189 337
190 CPU6: cpu@600 { 338 CPU6: cpu@600 {
191 device_type = "cpu"; 339 device_type = "cpu";
192 compatible = "arm,cort !! 340 compatible = "qcom,kryo";
193 reg = <0x0 0x600>; 341 reg = <0x0 0x600>;
194 clocks = <&cpufreq_hw <<
195 enable-method = "psci" 342 enable-method = "psci";
196 capacity-dmips-mhz = < 343 capacity-dmips-mhz = <1024>;
197 dynamic-power-coeffici <<
198 next-level-cache = <&L 344 next-level-cache = <&L2_600>;
199 power-domains = <&CPU_ 345 power-domains = <&CPU_PD6>;
200 power-domain-names = " 346 power-domain-names = "psci";
201 qcom,freq-domain = <&c 347 qcom,freq-domain = <&cpufreq_hw 1>;
202 operating-points-v2 = 348 operating-points-v2 = <&cpu4_opp_table>;
203 interconnects = <&epss 349 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
204 #cooling-cells = <2>; 350 #cooling-cells = <2>;
205 L2_600: l2-cache { 351 L2_600: l2-cache {
206 compatible = " 352 compatible = "cache";
207 cache-level = <<
208 cache-unified; <<
209 next-level-cac 353 next-level-cache = <&L3_0>;
210 }; 354 };
211 }; 355 };
212 356
213 CPU7: cpu@700 { 357 CPU7: cpu@700 {
214 device_type = "cpu"; 358 device_type = "cpu";
215 compatible = "arm,cort !! 359 compatible = "qcom,kryo";
216 reg = <0x0 0x700>; 360 reg = <0x0 0x700>;
217 clocks = <&cpufreq_hw <<
218 enable-method = "psci" 361 enable-method = "psci";
219 capacity-dmips-mhz = < 362 capacity-dmips-mhz = <1024>;
220 dynamic-power-coeffici <<
221 next-level-cache = <&L 363 next-level-cache = <&L2_700>;
222 power-domains = <&CPU_ 364 power-domains = <&CPU_PD7>;
223 power-domain-names = " 365 power-domain-names = "psci";
224 qcom,freq-domain = <&c 366 qcom,freq-domain = <&cpufreq_hw 1>;
225 operating-points-v2 = 367 operating-points-v2 = <&cpu4_opp_table>;
226 interconnects = <&epss 368 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
227 #cooling-cells = <2>; 369 #cooling-cells = <2>;
228 L2_700: l2-cache { 370 L2_700: l2-cache {
229 compatible = " 371 compatible = "cache";
230 cache-level = <<
231 cache-unified; <<
232 next-level-cac 372 next-level-cache = <&L3_0>;
233 }; 373 };
234 }; 374 };
235 375
236 cpu-map { 376 cpu-map {
237 cluster0 { 377 cluster0 {
238 core0 { 378 core0 {
239 cpu = 379 cpu = <&CPU0>;
240 }; 380 };
241 381
242 core1 { 382 core1 {
243 cpu = 383 cpu = <&CPU1>;
244 }; 384 };
245 385
246 core2 { 386 core2 {
247 cpu = 387 cpu = <&CPU2>;
248 }; 388 };
249 389
250 core3 { 390 core3 {
251 cpu = 391 cpu = <&CPU3>;
252 }; 392 };
253 393
254 core4 { 394 core4 {
255 cpu = 395 cpu = <&CPU4>;
256 }; 396 };
257 397
258 core5 { 398 core5 {
259 cpu = 399 cpu = <&CPU5>;
260 }; 400 };
261 401
262 core6 { 402 core6 {
263 cpu = 403 cpu = <&CPU6>;
264 }; 404 };
265 405
266 core7 { 406 core7 {
267 cpu = 407 cpu = <&CPU7>;
268 }; 408 };
269 }; 409 };
270 }; 410 };
271 411
272 idle-states { 412 idle-states {
273 entry-method = "psci"; 413 entry-method = "psci";
274 414
275 LITTLE_CPU_SLEEP_0: cp 415 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
276 compatible = " 416 compatible = "arm,idle-state";
277 idle-state-nam 417 idle-state-name = "little-rail-power-collapse";
278 arm,psci-suspe 418 arm,psci-suspend-param = <0x40000004>;
279 entry-latency- 419 entry-latency-us = <355>;
280 exit-latency-u 420 exit-latency-us = <909>;
281 min-residency- 421 min-residency-us = <3934>;
282 local-timer-st 422 local-timer-stop;
283 }; 423 };
284 424
285 BIG_CPU_SLEEP_0: cpu-s 425 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
286 compatible = " 426 compatible = "arm,idle-state";
287 idle-state-nam 427 idle-state-name = "big-rail-power-collapse";
288 arm,psci-suspe 428 arm,psci-suspend-param = <0x40000004>;
289 entry-latency- 429 entry-latency-us = <241>;
290 exit-latency-u 430 exit-latency-us = <1461>;
291 min-residency- 431 min-residency-us = <4488>;
292 local-timer-st 432 local-timer-stop;
293 }; 433 };
294 }; 434 };
295 435
296 domain-idle-states { 436 domain-idle-states {
297 CLUSTER_SLEEP_0: clust 437 CLUSTER_SLEEP_0: cluster-sleep-0 {
298 compatible = " 438 compatible = "domain-idle-state";
>> 439 idle-state-name = "cluster-power-collapse";
299 arm,psci-suspe 440 arm,psci-suspend-param = <0x4100c344>;
300 entry-latency- 441 entry-latency-us = <3263>;
301 exit-latency-u 442 exit-latency-us = <6562>;
302 min-residency- 443 min-residency-us = <9987>;
303 }; 444 };
304 }; 445 };
305 }; 446 };
306 447
307 firmware { 448 firmware {
308 scm: scm { 449 scm: scm {
309 compatible = "qcom,scm 450 compatible = "qcom,scm-sc8280xp", "qcom,scm";
310 interconnects = <&aggr <<
311 qcom,dload-mode = <&tc <<
312 }; 451 };
313 }; 452 };
314 453
315 aggre1_noc: interconnect-aggre1-noc { 454 aggre1_noc: interconnect-aggre1-noc {
316 compatible = "qcom,sc8280xp-ag 455 compatible = "qcom,sc8280xp-aggre1-noc";
317 #interconnect-cells = <2>; 456 #interconnect-cells = <2>;
318 qcom,bcm-voters = <&apps_bcm_v 457 qcom,bcm-voters = <&apps_bcm_voter>;
319 }; 458 };
320 459
321 aggre2_noc: interconnect-aggre2-noc { 460 aggre2_noc: interconnect-aggre2-noc {
322 compatible = "qcom,sc8280xp-ag 461 compatible = "qcom,sc8280xp-aggre2-noc";
323 #interconnect-cells = <2>; 462 #interconnect-cells = <2>;
324 qcom,bcm-voters = <&apps_bcm_v 463 qcom,bcm-voters = <&apps_bcm_voter>;
325 }; 464 };
326 465
327 clk_virt: interconnect-clk-virt { 466 clk_virt: interconnect-clk-virt {
328 compatible = "qcom,sc8280xp-cl 467 compatible = "qcom,sc8280xp-clk-virt";
329 #interconnect-cells = <2>; 468 #interconnect-cells = <2>;
330 qcom,bcm-voters = <&apps_bcm_v 469 qcom,bcm-voters = <&apps_bcm_voter>;
331 }; 470 };
332 471
333 config_noc: interconnect-config-noc { 472 config_noc: interconnect-config-noc {
334 compatible = "qcom,sc8280xp-co 473 compatible = "qcom,sc8280xp-config-noc";
335 #interconnect-cells = <2>; 474 #interconnect-cells = <2>;
336 qcom,bcm-voters = <&apps_bcm_v 475 qcom,bcm-voters = <&apps_bcm_voter>;
337 }; 476 };
338 477
339 dc_noc: interconnect-dc-noc { 478 dc_noc: interconnect-dc-noc {
340 compatible = "qcom,sc8280xp-dc 479 compatible = "qcom,sc8280xp-dc-noc";
341 #interconnect-cells = <2>; 480 #interconnect-cells = <2>;
342 qcom,bcm-voters = <&apps_bcm_v 481 qcom,bcm-voters = <&apps_bcm_voter>;
343 }; 482 };
344 483
345 gem_noc: interconnect-gem-noc { 484 gem_noc: interconnect-gem-noc {
346 compatible = "qcom,sc8280xp-ge 485 compatible = "qcom,sc8280xp-gem-noc";
347 #interconnect-cells = <2>; 486 #interconnect-cells = <2>;
348 qcom,bcm-voters = <&apps_bcm_v 487 qcom,bcm-voters = <&apps_bcm_voter>;
349 }; 488 };
350 489
351 lpass_noc: interconnect-lpass-ag-noc { 490 lpass_noc: interconnect-lpass-ag-noc {
352 compatible = "qcom,sc8280xp-lp 491 compatible = "qcom,sc8280xp-lpass-ag-noc";
353 #interconnect-cells = <2>; 492 #interconnect-cells = <2>;
354 qcom,bcm-voters = <&apps_bcm_v 493 qcom,bcm-voters = <&apps_bcm_voter>;
355 }; 494 };
356 495
357 mc_virt: interconnect-mc-virt { 496 mc_virt: interconnect-mc-virt {
358 compatible = "qcom,sc8280xp-mc 497 compatible = "qcom,sc8280xp-mc-virt";
359 #interconnect-cells = <2>; 498 #interconnect-cells = <2>;
360 qcom,bcm-voters = <&apps_bcm_v 499 qcom,bcm-voters = <&apps_bcm_voter>;
361 }; 500 };
362 501
363 mmss_noc: interconnect-mmss-noc { 502 mmss_noc: interconnect-mmss-noc {
364 compatible = "qcom,sc8280xp-mm 503 compatible = "qcom,sc8280xp-mmss-noc";
365 #interconnect-cells = <2>; 504 #interconnect-cells = <2>;
366 qcom,bcm-voters = <&apps_bcm_v 505 qcom,bcm-voters = <&apps_bcm_voter>;
367 }; 506 };
368 507
369 nspa_noc: interconnect-nspa-noc { 508 nspa_noc: interconnect-nspa-noc {
370 compatible = "qcom,sc8280xp-ns 509 compatible = "qcom,sc8280xp-nspa-noc";
371 #interconnect-cells = <2>; 510 #interconnect-cells = <2>;
372 qcom,bcm-voters = <&apps_bcm_v 511 qcom,bcm-voters = <&apps_bcm_voter>;
373 }; 512 };
374 513
375 nspb_noc: interconnect-nspb-noc { 514 nspb_noc: interconnect-nspb-noc {
376 compatible = "qcom,sc8280xp-ns 515 compatible = "qcom,sc8280xp-nspb-noc";
377 #interconnect-cells = <2>; 516 #interconnect-cells = <2>;
378 qcom,bcm-voters = <&apps_bcm_v 517 qcom,bcm-voters = <&apps_bcm_voter>;
379 }; 518 };
380 519
381 system_noc: interconnect-system-noc { 520 system_noc: interconnect-system-noc {
382 compatible = "qcom,sc8280xp-sy 521 compatible = "qcom,sc8280xp-system-noc";
383 #interconnect-cells = <2>; 522 #interconnect-cells = <2>;
384 qcom,bcm-voters = <&apps_bcm_v 523 qcom,bcm-voters = <&apps_bcm_voter>;
385 }; 524 };
386 525
387 memory@80000000 { 526 memory@80000000 {
388 device_type = "memory"; 527 device_type = "memory";
389 /* We expect the bootloader to 528 /* We expect the bootloader to fill in the size */
390 reg = <0x0 0x80000000 0x0 0x0> 529 reg = <0x0 0x80000000 0x0 0x0>;
391 }; 530 };
392 531
393 cpu0_opp_table: opp-table-cpu0 { <<
394 compatible = "operating-points <<
395 opp-shared; <<
396 <<
397 opp-300000000 { <<
398 opp-hz = /bits/ 64 <30 <<
399 opp-peak-kBps = <(3000 <<
400 }; <<
401 opp-403200000 { <<
402 opp-hz = /bits/ 64 <40 <<
403 opp-peak-kBps = <(3840 <<
404 }; <<
405 opp-499200000 { <<
406 opp-hz = /bits/ 64 <49 <<
407 opp-peak-kBps = <(4800 <<
408 }; <<
409 opp-595200000 { <<
410 opp-hz = /bits/ 64 <59 <<
411 opp-peak-kBps = <(5760 <<
412 }; <<
413 opp-691200000 { <<
414 opp-hz = /bits/ 64 <69 <<
415 opp-peak-kBps = <(6720 <<
416 }; <<
417 opp-806400000 { <<
418 opp-hz = /bits/ 64 <80 <<
419 opp-peak-kBps = <(7680 <<
420 }; <<
421 opp-902400000 { <<
422 opp-hz = /bits/ 64 <90 <<
423 opp-peak-kBps = <(8640 <<
424 }; <<
425 opp-1017600000 { <<
426 opp-hz = /bits/ 64 <10 <<
427 opp-peak-kBps = <(9600 <<
428 }; <<
429 opp-1113600000 { <<
430 opp-hz = /bits/ 64 <11 <<
431 opp-peak-kBps = <(1075 <<
432 }; <<
433 opp-1209600000 { <<
434 opp-hz = /bits/ 64 <12 <<
435 opp-peak-kBps = <(1171 <<
436 }; <<
437 opp-1324800000 { <<
438 opp-hz = /bits/ 64 <13 <<
439 opp-peak-kBps = <(1267 <<
440 }; <<
441 opp-1440000000 { <<
442 opp-hz = /bits/ 64 <14 <<
443 opp-peak-kBps = <(1363 <<
444 }; <<
445 opp-1555200000 { <<
446 opp-hz = /bits/ 64 <15 <<
447 opp-peak-kBps = <(1536 <<
448 }; <<
449 opp-1670400000 { <<
450 opp-hz = /bits/ 64 <16 <<
451 opp-peak-kBps = <(1612 <<
452 }; <<
453 opp-1785600000 { <<
454 opp-hz = /bits/ 64 <17 <<
455 opp-peak-kBps = <(1689 <<
456 }; <<
457 opp-1881600000 { <<
458 opp-hz = /bits/ 64 <18 <<
459 opp-peak-kBps = <(1689 <<
460 }; <<
461 opp-1996800000 { <<
462 opp-hz = /bits/ 64 <19 <<
463 opp-peak-kBps = <(1689 <<
464 }; <<
465 opp-2112000000 { <<
466 opp-hz = /bits/ 64 <21 <<
467 opp-peak-kBps = <(1689 <<
468 }; <<
469 opp-2227200000 { <<
470 opp-hz = /bits/ 64 <22 <<
471 opp-peak-kBps = <(1689 <<
472 }; <<
473 opp-2342400000 { <<
474 opp-hz = /bits/ 64 <23 <<
475 opp-peak-kBps = <(1689 <<
476 }; <<
477 opp-2438400000 { <<
478 opp-hz = /bits/ 64 <24 <<
479 opp-peak-kBps = <(1689 <<
480 }; <<
481 }; <<
482 <<
483 cpu4_opp_table: opp-table-cpu4 { <<
484 compatible = "operating-points <<
485 opp-shared; <<
486 <<
487 opp-825600000 { <<
488 opp-hz = /bits/ 64 <82 <<
489 opp-peak-kBps = <(7680 <<
490 }; <<
491 opp-940800000 { <<
492 opp-hz = /bits/ 64 <94 <<
493 opp-peak-kBps = <(8640 <<
494 }; <<
495 opp-1056000000 { <<
496 opp-hz = /bits/ 64 <10 <<
497 opp-peak-kBps = <(9600 <<
498 }; <<
499 opp-1171200000 { <<
500 opp-hz = /bits/ 64 <11 <<
501 opp-peak-kBps = <(1171 <<
502 }; <<
503 opp-1286400000 { <<
504 opp-hz = /bits/ 64 <12 <<
505 opp-peak-kBps = <(1267 <<
506 }; <<
507 opp-1401600000 { <<
508 opp-hz = /bits/ 64 <14 <<
509 opp-peak-kBps = <(1363 <<
510 }; <<
511 opp-1516800000 { <<
512 opp-hz = /bits/ 64 <15 <<
513 opp-peak-kBps = <(1459 <<
514 }; <<
515 opp-1632000000 { <<
516 opp-hz = /bits/ 64 <16 <<
517 opp-peak-kBps = <(1612 <<
518 }; <<
519 opp-1747200000 { <<
520 opp-hz = /bits/ 64 <17 <<
521 opp-peak-kBps = <(1689 <<
522 }; <<
523 opp-1862400000 { <<
524 opp-hz = /bits/ 64 <18 <<
525 opp-peak-kBps = <(1689 <<
526 }; <<
527 opp-1977600000 { <<
528 opp-hz = /bits/ 64 <19 <<
529 opp-peak-kBps = <(1689 <<
530 }; <<
531 opp-2073600000 { <<
532 opp-hz = /bits/ 64 <20 <<
533 opp-peak-kBps = <(1689 <<
534 }; <<
535 opp-2169600000 { <<
536 opp-hz = /bits/ 64 <21 <<
537 opp-peak-kBps = <(1689 <<
538 }; <<
539 opp-2284800000 { <<
540 opp-hz = /bits/ 64 <22 <<
541 opp-peak-kBps = <(1689 <<
542 }; <<
543 opp-2400000000 { <<
544 opp-hz = /bits/ 64 <24 <<
545 opp-peak-kBps = <(1689 <<
546 }; <<
547 opp-2496000000 { <<
548 opp-hz = /bits/ 64 <24 <<
549 opp-peak-kBps = <(1689 <<
550 }; <<
551 opp-2592000000 { <<
552 opp-hz = /bits/ 64 <25 <<
553 opp-peak-kBps = <(1689 <<
554 }; <<
555 opp-2688000000 { <<
556 opp-hz = /bits/ 64 <26 <<
557 opp-peak-kBps = <(1689 <<
558 }; <<
559 opp-2803200000 { <<
560 opp-hz = /bits/ 64 <28 <<
561 opp-peak-kBps = <(1689 <<
562 }; <<
563 opp-2899200000 { <<
564 opp-hz = /bits/ 64 <28 <<
565 opp-peak-kBps = <(1689 <<
566 }; <<
567 opp-2995200000 { <<
568 opp-hz = /bits/ 64 <29 <<
569 opp-peak-kBps = <(1689 <<
570 }; <<
571 }; <<
572 <<
573 qup_opp_table_100mhz: opp-table-qup100 <<
574 compatible = "operating-points <<
575 <<
576 opp-75000000 { <<
577 opp-hz = /bits/ 64 <75 <<
578 required-opps = <&rpmh <<
579 }; <<
580 <<
581 opp-100000000 { <<
582 opp-hz = /bits/ 64 <10 <<
583 required-opps = <&rpmh <<
584 }; <<
585 }; <<
586 <<
587 pmu { 532 pmu {
588 compatible = "arm,armv8-pmuv3" 533 compatible = "arm,armv8-pmuv3";
589 interrupts = <GIC_PPI 7 IRQ_TY 534 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
590 }; 535 };
591 536
592 psci { 537 psci {
593 compatible = "arm,psci-1.0"; 538 compatible = "arm,psci-1.0";
594 method = "smc"; 539 method = "smc";
595 540
596 CPU_PD0: power-domain-cpu0 { !! 541 CPU_PD0: cpu0 {
597 #power-domain-cells = 542 #power-domain-cells = <0>;
598 power-domains = <&CLUS 543 power-domains = <&CLUSTER_PD>;
599 domain-idle-states = < 544 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
600 }; 545 };
601 546
602 CPU_PD1: power-domain-cpu1 { !! 547 CPU_PD1: cpu1 {
603 #power-domain-cells = 548 #power-domain-cells = <0>;
604 power-domains = <&CLUS 549 power-domains = <&CLUSTER_PD>;
605 domain-idle-states = < 550 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
606 }; 551 };
607 552
608 CPU_PD2: power-domain-cpu2 { !! 553 CPU_PD2: cpu2 {
609 #power-domain-cells = 554 #power-domain-cells = <0>;
610 power-domains = <&CLUS 555 power-domains = <&CLUSTER_PD>;
611 domain-idle-states = < 556 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
612 }; 557 };
613 558
614 CPU_PD3: power-domain-cpu3 { !! 559 CPU_PD3: cpu3 {
615 #power-domain-cells = 560 #power-domain-cells = <0>;
616 power-domains = <&CLUS 561 power-domains = <&CLUSTER_PD>;
617 domain-idle-states = < 562 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
618 }; 563 };
619 564
620 CPU_PD4: power-domain-cpu4 { !! 565 CPU_PD4: cpu4 {
621 #power-domain-cells = 566 #power-domain-cells = <0>;
622 power-domains = <&CLUS 567 power-domains = <&CLUSTER_PD>;
623 domain-idle-states = < 568 domain-idle-states = <&BIG_CPU_SLEEP_0>;
624 }; 569 };
625 570
626 CPU_PD5: power-domain-cpu5 { !! 571 CPU_PD5: cpu5 {
627 #power-domain-cells = 572 #power-domain-cells = <0>;
628 power-domains = <&CLUS 573 power-domains = <&CLUSTER_PD>;
629 domain-idle-states = < 574 domain-idle-states = <&BIG_CPU_SLEEP_0>;
630 }; 575 };
631 576
632 CPU_PD6: power-domain-cpu6 { !! 577 CPU_PD6: cpu6 {
633 #power-domain-cells = 578 #power-domain-cells = <0>;
634 power-domains = <&CLUS 579 power-domains = <&CLUSTER_PD>;
635 domain-idle-states = < 580 domain-idle-states = <&BIG_CPU_SLEEP_0>;
636 }; 581 };
637 582
638 CPU_PD7: power-domain-cpu7 { !! 583 CPU_PD7: cpu7 {
639 #power-domain-cells = 584 #power-domain-cells = <0>;
640 power-domains = <&CLUS 585 power-domains = <&CLUSTER_PD>;
641 domain-idle-states = < 586 domain-idle-states = <&BIG_CPU_SLEEP_0>;
642 }; 587 };
643 588
644 CLUSTER_PD: power-domain-cpu-c !! 589 CLUSTER_PD: cpu-cluster0 {
645 #power-domain-cells = 590 #power-domain-cells = <0>;
646 domain-idle-states = < 591 domain-idle-states = <&CLUSTER_SLEEP_0>;
647 }; 592 };
648 }; 593 };
649 594
>> 595 qup_opp_table_100mhz: qup-100mhz-opp-table {
>> 596 compatible = "operating-points-v2";
>> 597
>> 598 opp-75000000 {
>> 599 opp-hz = /bits/ 64 <75000000>;
>> 600 required-opps = <&rpmhpd_opp_low_svs>;
>> 601 };
>> 602
>> 603 opp-100000000 {
>> 604 opp-hz = /bits/ 64 <100000000>;
>> 605 required-opps = <&rpmhpd_opp_svs>;
>> 606 };
>> 607 };
>> 608
650 reserved-memory { 609 reserved-memory {
651 #address-cells = <2>; 610 #address-cells = <2>;
652 #size-cells = <2>; 611 #size-cells = <2>;
653 ranges; 612 ranges;
654 613
655 reserved-region@80000000 { 614 reserved-region@80000000 {
656 reg = <0 0x80000000 0 615 reg = <0 0x80000000 0 0x860000>;
657 no-map; 616 no-map;
658 }; 617 };
659 618
660 cmd_db: cmd-db-region@80860000 619 cmd_db: cmd-db-region@80860000 {
661 compatible = "qcom,cmd 620 compatible = "qcom,cmd-db";
662 reg = <0 0x80860000 0 621 reg = <0 0x80860000 0 0x20000>;
663 no-map; 622 no-map;
664 }; 623 };
665 624
666 reserved-region@80880000 { 625 reserved-region@80880000 {
667 reg = <0 0x80880000 0 626 reg = <0 0x80880000 0 0x80000>;
668 no-map; 627 no-map;
669 }; 628 };
670 629
671 smem_mem: smem-region@80900000 630 smem_mem: smem-region@80900000 {
672 compatible = "qcom,sme 631 compatible = "qcom,smem";
673 reg = <0 0x80900000 0 632 reg = <0 0x80900000 0 0x200000>;
674 no-map; 633 no-map;
675 hwlocks = <&tcsr_mutex 634 hwlocks = <&tcsr_mutex 3>;
676 }; 635 };
677 636
678 reserved-region@80b00000 { 637 reserved-region@80b00000 {
679 reg = <0 0x80b00000 0 638 reg = <0 0x80b00000 0 0x100000>;
680 no-map; 639 no-map;
681 }; 640 };
682 641
683 reserved-region@83b00000 { 642 reserved-region@83b00000 {
684 reg = <0 0x83b00000 0 643 reg = <0 0x83b00000 0 0x1700000>;
685 no-map; 644 no-map;
686 }; 645 };
687 646
688 reserved-region@85b00000 { 647 reserved-region@85b00000 {
689 reg = <0 0x85b00000 0 648 reg = <0 0x85b00000 0 0xc00000>;
690 no-map; 649 no-map;
691 }; 650 };
692 651
693 pil_adsp_mem: adsp-region@86c0 652 pil_adsp_mem: adsp-region@86c00000 {
694 reg = <0 0x86c00000 0 653 reg = <0 0x86c00000 0 0x2000000>;
695 no-map; 654 no-map;
696 }; 655 };
697 656
698 pil_nsp0_mem: cdsp0-region@8a1 657 pil_nsp0_mem: cdsp0-region@8a100000 {
699 reg = <0 0x8a100000 0 658 reg = <0 0x8a100000 0 0x1e00000>;
700 no-map; 659 no-map;
701 }; 660 };
702 661
703 pil_nsp1_mem: cdsp1-region@8c6 662 pil_nsp1_mem: cdsp1-region@8c600000 {
704 reg = <0 0x8c600000 0 663 reg = <0 0x8c600000 0 0x1e00000>;
705 no-map; 664 no-map;
706 }; 665 };
707 666
708 reserved-region@aeb00000 { 667 reserved-region@aeb00000 {
709 reg = <0 0xaeb00000 0 668 reg = <0 0xaeb00000 0 0x16600000>;
710 no-map; 669 no-map;
711 }; 670 };
712 }; 671 };
713 672
714 smp2p-adsp { 673 smp2p-adsp {
715 compatible = "qcom,smp2p"; 674 compatible = "qcom,smp2p";
716 qcom,smem = <443>, <429>; 675 qcom,smem = <443>, <429>;
717 interrupts-extended = <&ipcc I 676 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
718 I 677 IPCC_MPROC_SIGNAL_SMP2P
719 I 678 IRQ_TYPE_EDGE_RISING>;
720 mboxes = <&ipcc IPCC_CLIENT_LP 679 mboxes = <&ipcc IPCC_CLIENT_LPASS
721 IPCC_MPROC_SIG 680 IPCC_MPROC_SIGNAL_SMP2P>;
722 681
723 qcom,local-pid = <0>; 682 qcom,local-pid = <0>;
724 qcom,remote-pid = <2>; 683 qcom,remote-pid = <2>;
725 684
726 smp2p_adsp_out: master-kernel 685 smp2p_adsp_out: master-kernel {
727 qcom,entry-name = "mas 686 qcom,entry-name = "master-kernel";
728 #qcom,smem-state-cells 687 #qcom,smem-state-cells = <1>;
729 }; 688 };
730 689
731 smp2p_adsp_in: slave-kernel { 690 smp2p_adsp_in: slave-kernel {
732 qcom,entry-name = "sla 691 qcom,entry-name = "slave-kernel";
733 interrupt-controller; 692 interrupt-controller;
734 #interrupt-cells = <2> 693 #interrupt-cells = <2>;
735 }; 694 };
736 }; 695 };
737 696
738 smp2p-nsp0 { 697 smp2p-nsp0 {
739 compatible = "qcom,smp2p"; 698 compatible = "qcom,smp2p";
740 qcom,smem = <94>, <432>; 699 qcom,smem = <94>, <432>;
741 interrupts-extended = <&ipcc I 700 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
742 I 701 IPCC_MPROC_SIGNAL_SMP2P
743 I 702 IRQ_TYPE_EDGE_RISING>;
744 mboxes = <&ipcc IPCC_CLIENT_CD 703 mboxes = <&ipcc IPCC_CLIENT_CDSP
745 IPCC_MPROC_SIG 704 IPCC_MPROC_SIGNAL_SMP2P>;
746 705
747 qcom,local-pid = <0>; 706 qcom,local-pid = <0>;
748 qcom,remote-pid = <5>; 707 qcom,remote-pid = <5>;
749 708
750 smp2p_nsp0_out: master-kernel 709 smp2p_nsp0_out: master-kernel {
751 qcom,entry-name = "mas 710 qcom,entry-name = "master-kernel";
752 #qcom,smem-state-cells 711 #qcom,smem-state-cells = <1>;
753 }; 712 };
754 713
755 smp2p_nsp0_in: slave-kernel { 714 smp2p_nsp0_in: slave-kernel {
756 qcom,entry-name = "sla 715 qcom,entry-name = "slave-kernel";
757 interrupt-controller; 716 interrupt-controller;
758 #interrupt-cells = <2> 717 #interrupt-cells = <2>;
759 }; 718 };
760 }; 719 };
761 720
762 smp2p-nsp1 { 721 smp2p-nsp1 {
763 compatible = "qcom,smp2p"; 722 compatible = "qcom,smp2p";
764 qcom,smem = <617>, <616>; 723 qcom,smem = <617>, <616>;
765 interrupts-extended = <&ipcc I 724 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1
766 I 725 IPCC_MPROC_SIGNAL_SMP2P
767 I 726 IRQ_TYPE_EDGE_RISING>;
768 mboxes = <&ipcc IPCC_CLIENT_NS 727 mboxes = <&ipcc IPCC_CLIENT_NSP1
769 IPCC_MPROC_SIG 728 IPCC_MPROC_SIGNAL_SMP2P>;
770 729
771 qcom,local-pid = <0>; 730 qcom,local-pid = <0>;
772 qcom,remote-pid = <12>; 731 qcom,remote-pid = <12>;
773 732
774 smp2p_nsp1_out: master-kernel 733 smp2p_nsp1_out: master-kernel {
775 qcom,entry-name = "mas 734 qcom,entry-name = "master-kernel";
776 #qcom,smem-state-cells 735 #qcom,smem-state-cells = <1>;
777 }; 736 };
778 737
779 smp2p_nsp1_in: slave-kernel { 738 smp2p_nsp1_in: slave-kernel {
780 qcom,entry-name = "sla 739 qcom,entry-name = "slave-kernel";
781 interrupt-controller; 740 interrupt-controller;
782 #interrupt-cells = <2> 741 #interrupt-cells = <2>;
783 }; 742 };
784 }; 743 };
785 744
786 soc: soc@0 { 745 soc: soc@0 {
787 compatible = "simple-bus"; 746 compatible = "simple-bus";
788 #address-cells = <2>; 747 #address-cells = <2>;
789 #size-cells = <2>; 748 #size-cells = <2>;
790 ranges = <0 0 0 0 0x10 0>; 749 ranges = <0 0 0 0 0x10 0>;
791 dma-ranges = <0 0 0 0 0x10 0>; 750 dma-ranges = <0 0 0 0 0x10 0>;
792 751
793 ethernet0: ethernet@20000 { <<
794 compatible = "qcom,sc8 <<
795 reg = <0x0 0x00020000 <<
796 <0x0 0x00036000 <<
797 reg-names = "stmmaceth <<
798 <<
799 clocks = <&gcc GCC_EMA <<
800 <&gcc GCC_EMA <<
801 <&gcc GCC_EMA <<
802 <&gcc GCC_EMA <<
803 clock-names = "stmmace <<
804 "pclk", <<
805 "ptp_ref <<
806 "rgmii"; <<
807 <<
808 interrupts = <GIC_SPI <<
809 <GIC_SPI <<
810 interrupt-names = "mac <<
811 <<
812 iommus = <&apps_smmu 0 <<
813 power-domains = <&gcc <<
814 <<
815 snps,tso; <<
816 snps,pbl = <32>; <<
817 rx-fifo-depth = <4096> <<
818 tx-fifo-depth = <4096> <<
819 <<
820 status = "disabled"; <<
821 }; <<
822 <<
823 gcc: clock-controller@100000 { 752 gcc: clock-controller@100000 {
824 compatible = "qcom,gcc 753 compatible = "qcom,gcc-sc8280xp";
825 reg = <0x0 0x00100000 754 reg = <0x0 0x00100000 0x0 0x1f0000>;
826 #clock-cells = <1>; 755 #clock-cells = <1>;
827 #reset-cells = <1>; 756 #reset-cells = <1>;
828 #power-domain-cells = 757 #power-domain-cells = <1>;
829 clocks = <&rpmhcc RPMH 758 clocks = <&rpmhcc RPMH_CXO_CLK>,
830 <&sleep_clk>, 759 <&sleep_clk>,
831 <0>, 760 <0>,
832 <0>, 761 <0>,
833 <0>, 762 <0>,
834 <0>, 763 <0>,
835 <0>, 764 <0>,
836 <0>, 765 <0>,
837 <&usb_0_qmpph 766 <&usb_0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
838 <0>, 767 <0>,
839 <0>, 768 <0>,
840 <0>, 769 <0>,
841 <0>, 770 <0>,
842 <0>, 771 <0>,
843 <0>, 772 <0>,
844 <0>, 773 <0>,
845 <&usb_1_qmpph 774 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
846 <0>, 775 <0>,
847 <0>, 776 <0>,
848 <0>, 777 <0>,
849 <0>, 778 <0>,
850 <0>, 779 <0>,
851 <0>, 780 <0>,
852 <0>, 781 <0>,
853 <0>, 782 <0>,
854 <0>, 783 <0>,
855 <&pcie2a_phy> 784 <&pcie2a_phy>,
856 <&pcie2b_phy> 785 <&pcie2b_phy>,
857 <&pcie3a_phy> 786 <&pcie3a_phy>,
858 <&pcie3b_phy> 787 <&pcie3b_phy>,
859 <&pcie4_phy>, 788 <&pcie4_phy>,
860 <0>, 789 <0>,
861 <0>; 790 <0>;
862 power-domains = <&rpmh 791 power-domains = <&rpmhpd SC8280XP_CX>;
863 }; 792 };
864 793
865 ipcc: mailbox@408000 { 794 ipcc: mailbox@408000 {
866 compatible = "qcom,sc8 795 compatible = "qcom,sc8280xp-ipcc", "qcom,ipcc";
867 reg = <0 0x00408000 0 796 reg = <0 0x00408000 0 0x1000>;
868 interrupts = <GIC_SPI 797 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
869 interrupt-controller; 798 interrupt-controller;
870 #interrupt-cells = <3> 799 #interrupt-cells = <3>;
871 #mbox-cells = <2>; 800 #mbox-cells = <2>;
872 }; 801 };
873 802
874 qfprom: efuse@784000 { <<
875 compatible = "qcom,sc8 <<
876 reg = <0 0x00784000 0 <<
877 #address-cells = <1>; <<
878 #size-cells = <1>; <<
879 <<
880 gpu_speed_bin: gpu-spe <<
881 reg = <0x18b 0 <<
882 bits = <5 3>; <<
883 }; <<
884 }; <<
885 <<
886 qup2: geniqup@8c0000 { 803 qup2: geniqup@8c0000 {
887 compatible = "qcom,gen 804 compatible = "qcom,geni-se-qup";
888 reg = <0 0x008c0000 0 805 reg = <0 0x008c0000 0 0x2000>;
889 clocks = <&gcc GCC_QUP 806 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
890 <&gcc GCC_QUP 807 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
891 clock-names = "m-ahb", 808 clock-names = "m-ahb", "s-ahb";
892 iommus = <&apps_smmu 0 809 iommus = <&apps_smmu 0xa3 0>;
893 810
894 #address-cells = <2>; 811 #address-cells = <2>;
895 #size-cells = <2>; 812 #size-cells = <2>;
896 ranges; 813 ranges;
897 814
898 status = "disabled"; 815 status = "disabled";
899 816
900 i2c16: i2c@880000 { !! 817 qup2_uart17: serial@884000 {
901 compatible = " <<
902 reg = <0 0x008 <<
903 #address-cells <<
904 #size-cells = <<
905 clocks = <&gcc <<
906 clock-names = <<
907 interrupts = < <<
908 power-domains <<
909 interconnects <<
910 <<
911 <<
912 interconnect-n <<
913 status = "disa <<
914 }; <<
915 <<
916 spi16: spi@880000 { <<
917 compatible = " <<
918 reg = <0 0x008 <<
919 #address-cells <<
920 #size-cells = <<
921 clocks = <&gcc <<
922 clock-names = <<
923 interrupts = < <<
924 power-domains <<
925 interconnects <<
926 <<
927 <<
928 interconnect-n <<
929 status = "disa <<
930 }; <<
931 <<
932 i2c17: i2c@884000 { <<
933 compatible = " <<
934 reg = <0 0x008 <<
935 #address-cells <<
936 #size-cells = <<
937 clocks = <&gcc <<
938 clock-names = <<
939 interrupts = < <<
940 power-domains <<
941 interconnects <<
942 <<
943 <<
944 interconnect-n <<
945 status = "disa <<
946 }; <<
947 <<
948 spi17: spi@884000 { <<
949 compatible = " <<
950 reg = <0 0x008 <<
951 #address-cells <<
952 #size-cells = <<
953 clocks = <&gcc <<
954 clock-names = <<
955 interrupts = < <<
956 power-domains <<
957 interconnects <<
958 <<
959 <<
960 interconnect-n <<
961 status = "disa <<
962 }; <<
963 <<
964 uart17: serial@884000 <<
965 compatible = " 818 compatible = "qcom,geni-uart";
966 reg = <0 0x008 819 reg = <0 0x00884000 0 0x4000>;
967 clocks = <&gcc 820 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
968 clock-names = 821 clock-names = "se";
969 interrupts = < 822 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
970 operating-poin 823 operating-points-v2 = <&qup_opp_table_100mhz>;
971 power-domains 824 power-domains = <&rpmhpd SC8280XP_CX>;
972 interconnects 825 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
973 826 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>;
974 interconnect-n 827 interconnect-names = "qup-core", "qup-config";
975 status = "disa 828 status = "disabled";
976 }; 829 };
977 830
978 i2c18: i2c@888000 { !! 831 qup2_i2c5: i2c@894000 {
979 compatible = " <<
980 reg = <0 0x008 <<
981 #address-cells <<
982 #size-cells = <<
983 clocks = <&gcc <<
984 clock-names = <<
985 interrupts = < <<
986 power-domains <<
987 interconnects <<
988 <<
989 <<
990 interconnect-n <<
991 status = "disa <<
992 }; <<
993 <<
994 spi18: spi@888000 { <<
995 compatible = " <<
996 reg = <0 0x008 <<
997 #address-cells <<
998 #size-cells = <<
999 clocks = <&gcc <<
1000 clock-names = <<
1001 interrupts = <<
1002 power-domains <<
1003 interconnects <<
1004 <<
1005 <<
1006 interconnect- <<
1007 status = "dis <<
1008 }; <<
1009 <<
1010 i2c19: i2c@88c000 { <<
1011 compatible = <<
1012 reg = <0 0x00 <<
1013 #address-cell <<
1014 #size-cells = <<
1015 clocks = <&gc <<
1016 clock-names = <<
1017 interrupts = <<
1018 power-domains <<
1019 interconnects <<
1020 <<
1021 <<
1022 interconnect- <<
1023 status = "dis <<
1024 }; <<
1025 <<
1026 spi19: spi@88c000 { <<
1027 compatible = <<
1028 reg = <0 0x00 <<
1029 #address-cell <<
1030 #size-cells = <<
1031 clocks = <&gc <<
1032 clock-names = <<
1033 interrupts = <<
1034 power-domains <<
1035 interconnects <<
1036 <<
1037 <<
1038 interconnect- <<
1039 status = "dis <<
1040 }; <<
1041 <<
1042 i2c20: i2c@890000 { <<
1043 compatible = <<
1044 reg = <0 0x00 <<
1045 #address-cell <<
1046 #size-cells = <<
1047 clocks = <&gc <<
1048 clock-names = <<
1049 interrupts = <<
1050 power-domains <<
1051 interconnects <<
1052 <<
1053 <<
1054 interconnect- <<
1055 status = "dis <<
1056 }; <<
1057 <<
1058 spi20: spi@890000 { <<
1059 compatible = <<
1060 reg = <0 0x00 <<
1061 #address-cell <<
1062 #size-cells = <<
1063 clocks = <&gc <<
1064 clock-names = <<
1065 interrupts = <<
1066 power-domains <<
1067 interconnects <<
1068 <<
1069 <<
1070 interconnect- <<
1071 status = "dis <<
1072 }; <<
1073 <<
1074 i2c21: i2c@894000 { <<
1075 compatible = 832 compatible = "qcom,geni-i2c";
1076 reg = <0 0x00 833 reg = <0 0x00894000 0 0x4000>;
1077 clock-names = 834 clock-names = "se";
1078 clocks = <&gc 835 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1079 interrupts = 836 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1080 #address-cell 837 #address-cells = <1>;
1081 #size-cells = 838 #size-cells = <0>;
1082 power-domains 839 power-domains = <&rpmhpd SC8280XP_CX>;
1083 interconnects 840 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1084 841 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1085 842 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1086 interconnect- 843 interconnect-names = "qup-core", "qup-config", "qup-memory";
1087 status = "dis 844 status = "disabled";
1088 }; 845 };
1089 <<
1090 spi21: spi@894000 { <<
1091 compatible = <<
1092 reg = <0 0x00 <<
1093 #address-cell <<
1094 #size-cells = <<
1095 clocks = <&gc <<
1096 clock-names = <<
1097 interrupts = <<
1098 power-domains <<
1099 interconnects <<
1100 <<
1101 <<
1102 interconnect- <<
1103 status = "dis <<
1104 }; <<
1105 <<
1106 i2c22: i2c@898000 { <<
1107 compatible = <<
1108 reg = <0 0x00 <<
1109 #address-cell <<
1110 #size-cells = <<
1111 clock-names = <<
1112 clocks = <&gc <<
1113 interrupts = <<
1114 power-domains <<
1115 interconnects <<
1116 <<
1117 <<
1118 interconnect- <<
1119 status = "dis <<
1120 }; <<
1121 <<
1122 spi22: spi@898000 { <<
1123 compatible = <<
1124 reg = <0 0x00 <<
1125 #address-cell <<
1126 #size-cells = <<
1127 clocks = <&gc <<
1128 clock-names = <<
1129 interrupts = <<
1130 power-domains <<
1131 interconnects <<
1132 <<
1133 <<
1134 interconnect- <<
1135 status = "dis <<
1136 }; <<
1137 <<
1138 i2c23: i2c@89c000 { <<
1139 compatible = <<
1140 reg = <0 0x00 <<
1141 #address-cell <<
1142 #size-cells = <<
1143 clock-names = <<
1144 clocks = <&gc <<
1145 interrupts = <<
1146 power-domains <<
1147 interconnects <<
1148 <<
1149 <<
1150 interconnect- <<
1151 status = "dis <<
1152 }; <<
1153 <<
1154 spi23: spi@89c000 { <<
1155 compatible = <<
1156 reg = <0 0x00 <<
1157 #address-cell <<
1158 #size-cells = <<
1159 clocks = <&gc <<
1160 clock-names = <<
1161 interrupts = <<
1162 power-domains <<
1163 interconnects <<
1164 <<
1165 <<
1166 interconnect- <<
1167 status = "dis <<
1168 }; <<
1169 }; 846 };
1170 847
1171 qup0: geniqup@9c0000 { 848 qup0: geniqup@9c0000 {
1172 compatible = "qcom,ge 849 compatible = "qcom,geni-se-qup";
1173 reg = <0 0x009c0000 0 850 reg = <0 0x009c0000 0 0x6000>;
1174 clocks = <&gcc GCC_QU 851 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1175 <&gcc GCC_QU 852 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1176 clock-names = "m-ahb" 853 clock-names = "m-ahb", "s-ahb";
1177 iommus = <&apps_smmu 854 iommus = <&apps_smmu 0x563 0>;
1178 855
1179 #address-cells = <2>; 856 #address-cells = <2>;
1180 #size-cells = <2>; 857 #size-cells = <2>;
1181 ranges; 858 ranges;
1182 859
1183 status = "disabled"; 860 status = "disabled";
1184 861
1185 i2c0: i2c@980000 { !! 862 qup0_i2c4: i2c@990000 {
1186 compatible = <<
1187 reg = <0 0x00 <<
1188 #address-cell <<
1189 #size-cells = <<
1190 clock-names = <<
1191 clocks = <&gc <<
1192 interrupts = <<
1193 power-domains <<
1194 interconnects <<
1195 <<
1196 <<
1197 interconnect- <<
1198 status = "dis <<
1199 }; <<
1200 <<
1201 spi0: spi@980000 { <<
1202 compatible = <<
1203 reg = <0 0x00 <<
1204 #address-cell <<
1205 #size-cells = <<
1206 clocks = <&gc <<
1207 clock-names = <<
1208 interrupts = <<
1209 power-domains <<
1210 interconnects <<
1211 <<
1212 <<
1213 interconnect- <<
1214 status = "dis <<
1215 }; <<
1216 <<
1217 i2c1: i2c@984000 { <<
1218 compatible = <<
1219 reg = <0 0x00 <<
1220 #address-cell <<
1221 #size-cells = <<
1222 clock-names = <<
1223 clocks = <&gc <<
1224 interrupts = <<
1225 power-domains <<
1226 interconnects <<
1227 <<
1228 <<
1229 interconnect- <<
1230 status = "dis <<
1231 }; <<
1232 <<
1233 spi1: spi@984000 { <<
1234 compatible = <<
1235 reg = <0 0x00 <<
1236 #address-cell <<
1237 #size-cells = <<
1238 clocks = <&gc <<
1239 clock-names = <<
1240 interrupts = <<
1241 power-domains <<
1242 interconnects <<
1243 <<
1244 <<
1245 interconnect- <<
1246 status = "dis <<
1247 }; <<
1248 <<
1249 i2c2: i2c@988000 { <<
1250 compatible = <<
1251 reg = <0 0x00 <<
1252 #address-cell <<
1253 #size-cells = <<
1254 clock-names = <<
1255 clocks = <&gc <<
1256 interrupts = <<
1257 power-domains <<
1258 interconnects <<
1259 <<
1260 <<
1261 interconnect- <<
1262 status = "dis <<
1263 }; <<
1264 <<
1265 spi2: spi@988000 { <<
1266 compatible = <<
1267 reg = <0 0x00 <<
1268 #address-cell <<
1269 #size-cells = <<
1270 clocks = <&gc <<
1271 clock-names = <<
1272 interrupts = <<
1273 power-domains <<
1274 interconnects <<
1275 <<
1276 <<
1277 interconnect- <<
1278 status = "dis <<
1279 }; <<
1280 <<
1281 uart2: serial@988000 <<
1282 compatible = <<
1283 reg = <0 0x00 <<
1284 clocks = <&gc <<
1285 clock-names = <<
1286 interrupts = <<
1287 operating-poi <<
1288 power-domains <<
1289 interconnects <<
1290 <<
1291 interconnect- <<
1292 status = "dis <<
1293 }; <<
1294 <<
1295 i2c3: i2c@98c000 { <<
1296 compatible = <<
1297 reg = <0 0x00 <<
1298 #address-cell <<
1299 #size-cells = <<
1300 clock-names = <<
1301 clocks = <&gc <<
1302 interrupts = <<
1303 power-domains <<
1304 interconnects <<
1305 <<
1306 <<
1307 interconnect- <<
1308 status = "dis <<
1309 }; <<
1310 <<
1311 spi3: spi@98c000 { <<
1312 compatible = <<
1313 reg = <0 0x00 <<
1314 #address-cell <<
1315 #size-cells = <<
1316 clocks = <&gc <<
1317 clock-names = <<
1318 interrupts = <<
1319 power-domains <<
1320 interconnects <<
1321 <<
1322 <<
1323 interconnect- <<
1324 status = "dis <<
1325 }; <<
1326 <<
1327 i2c4: i2c@990000 { <<
1328 compatible = 863 compatible = "qcom,geni-i2c";
1329 reg = <0 0x00 864 reg = <0 0x00990000 0 0x4000>;
1330 clock-names = 865 clock-names = "se";
1331 clocks = <&gc 866 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1332 interrupts = 867 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1333 #address-cell 868 #address-cells = <1>;
1334 #size-cells = 869 #size-cells = <0>;
1335 power-domains 870 power-domains = <&rpmhpd SC8280XP_CX>;
1336 interconnects 871 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1337 872 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1338 873 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1339 interconnect- 874 interconnect-names = "qup-core", "qup-config", "qup-memory";
1340 status = "dis 875 status = "disabled";
1341 }; 876 };
1342 <<
1343 spi4: spi@990000 { <<
1344 compatible = <<
1345 reg = <0 0x00 <<
1346 #address-cell <<
1347 #size-cells = <<
1348 clocks = <&gc <<
1349 clock-names = <<
1350 interrupts = <<
1351 power-domains <<
1352 interconnects <<
1353 <<
1354 <<
1355 interconnect- <<
1356 status = "dis <<
1357 }; <<
1358 <<
1359 i2c5: i2c@994000 { <<
1360 compatible = <<
1361 reg = <0 0x00 <<
1362 #address-cell <<
1363 #size-cells = <<
1364 clock-names = <<
1365 clocks = <&gc <<
1366 interrupts = <<
1367 power-domains <<
1368 interconnects <<
1369 <<
1370 <<
1371 interconnect- <<
1372 status = "dis <<
1373 }; <<
1374 <<
1375 spi5: spi@994000 { <<
1376 compatible = <<
1377 reg = <0 0x00 <<
1378 #address-cell <<
1379 #size-cells = <<
1380 clocks = <&gc <<
1381 clock-names = <<
1382 interrupts = <<
1383 power-domains <<
1384 interconnects <<
1385 <<
1386 <<
1387 interconnect- <<
1388 status = "dis <<
1389 }; <<
1390 <<
1391 i2c6: i2c@998000 { <<
1392 compatible = <<
1393 reg = <0 0x00 <<
1394 #address-cell <<
1395 #size-cells = <<
1396 clock-names = <<
1397 clocks = <&gc <<
1398 interrupts = <<
1399 power-domains <<
1400 interconnects <<
1401 <<
1402 <<
1403 interconnect- <<
1404 status = "dis <<
1405 }; <<
1406 <<
1407 spi6: spi@998000 { <<
1408 compatible = <<
1409 reg = <0 0x00 <<
1410 #address-cell <<
1411 #size-cells = <<
1412 clocks = <&gc <<
1413 clock-names = <<
1414 interrupts = <<
1415 power-domains <<
1416 interconnects <<
1417 <<
1418 <<
1419 interconnect- <<
1420 status = "dis <<
1421 }; <<
1422 <<
1423 i2c7: i2c@99c000 { <<
1424 compatible = <<
1425 reg = <0 0x00 <<
1426 #address-cell <<
1427 #size-cells = <<
1428 clock-names = <<
1429 clocks = <&gc <<
1430 interrupts = <<
1431 power-domains <<
1432 interconnects <<
1433 <<
1434 <<
1435 interconnect- <<
1436 status = "dis <<
1437 }; <<
1438 <<
1439 spi7: spi@99c000 { <<
1440 compatible = <<
1441 reg = <0 0x00 <<
1442 #address-cell <<
1443 #size-cells = <<
1444 clocks = <&gc <<
1445 clock-names = <<
1446 interrupts = <<
1447 power-domains <<
1448 interconnects <<
1449 <<
1450 <<
1451 interconnect- <<
1452 status = "dis <<
1453 }; <<
1454 }; 877 };
1455 878
1456 qup1: geniqup@ac0000 { 879 qup1: geniqup@ac0000 {
1457 compatible = "qcom,ge 880 compatible = "qcom,geni-se-qup";
1458 reg = <0 0x00ac0000 0 881 reg = <0 0x00ac0000 0 0x6000>;
1459 clocks = <&gcc GCC_QU 882 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1460 <&gcc GCC_QU 883 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1461 clock-names = "m-ahb" 884 clock-names = "m-ahb", "s-ahb";
1462 iommus = <&apps_smmu 885 iommus = <&apps_smmu 0x83 0>;
1463 886
1464 #address-cells = <2>; 887 #address-cells = <2>;
1465 #size-cells = <2>; 888 #size-cells = <2>;
1466 ranges; 889 ranges;
1467 890
1468 status = "disabled"; 891 status = "disabled";
1469 <<
1470 i2c8: i2c@a80000 { <<
1471 compatible = <<
1472 reg = <0 0x00 <<
1473 #address-cell <<
1474 #size-cells = <<
1475 clocks = <&gc <<
1476 clock-names = <<
1477 interrupts = <<
1478 power-domains <<
1479 interconnects <<
1480 <<
1481 <<
1482 interconnect- <<
1483 status = "dis <<
1484 }; <<
1485 <<
1486 spi8: spi@a80000 { <<
1487 compatible = <<
1488 reg = <0 0x00 <<
1489 #address-cell <<
1490 #size-cells = <<
1491 clocks = <&gc <<
1492 clock-names = <<
1493 interrupts = <<
1494 power-domains <<
1495 interconnects <<
1496 <<
1497 <<
1498 interconnect- <<
1499 status = "dis <<
1500 }; <<
1501 <<
1502 i2c9: i2c@a84000 { <<
1503 compatible = <<
1504 reg = <0 0x00 <<
1505 #address-cell <<
1506 #size-cells = <<
1507 clocks = <&gc <<
1508 clock-names = <<
1509 interrupts = <<
1510 power-domains <<
1511 interconnects <<
1512 <<
1513 <<
1514 interconnect- <<
1515 status = "dis <<
1516 }; <<
1517 <<
1518 spi9: spi@a84000 { <<
1519 compatible = <<
1520 reg = <0 0x00 <<
1521 #address-cell <<
1522 #size-cells = <<
1523 clocks = <&gc <<
1524 clock-names = <<
1525 interrupts = <<
1526 power-domains <<
1527 interconnects <<
1528 <<
1529 <<
1530 interconnect- <<
1531 status = "dis <<
1532 }; <<
1533 <<
1534 i2c10: i2c@a88000 { <<
1535 compatible = <<
1536 reg = <0 0x00 <<
1537 #address-cell <<
1538 #size-cells = <<
1539 clocks = <&gc <<
1540 clock-names = <<
1541 interrupts = <<
1542 power-domains <<
1543 interconnects <<
1544 <<
1545 <<
1546 interconnect- <<
1547 status = "dis <<
1548 }; <<
1549 <<
1550 spi10: spi@a88000 { <<
1551 compatible = <<
1552 reg = <0 0x00 <<
1553 #address-cell <<
1554 #size-cells = <<
1555 clocks = <&gc <<
1556 clock-names = <<
1557 interrupts = <<
1558 power-domains <<
1559 interconnects <<
1560 <<
1561 <<
1562 interconnect- <<
1563 status = "dis <<
1564 }; <<
1565 <<
1566 i2c11: i2c@a8c000 { <<
1567 compatible = <<
1568 reg = <0 0x00 <<
1569 #address-cell <<
1570 #size-cells = <<
1571 clocks = <&gc <<
1572 clock-names = <<
1573 interrupts = <<
1574 power-domains <<
1575 interconnects <<
1576 <<
1577 <<
1578 interconnect- <<
1579 status = "dis <<
1580 }; <<
1581 <<
1582 spi11: spi@a8c000 { <<
1583 compatible = <<
1584 reg = <0 0x00 <<
1585 #address-cell <<
1586 #size-cells = <<
1587 clocks = <&gc <<
1588 clock-names = <<
1589 interrupts = <<
1590 power-domains <<
1591 interconnects <<
1592 <<
1593 <<
1594 interconnect- <<
1595 status = "dis <<
1596 }; <<
1597 <<
1598 i2c12: i2c@a90000 { <<
1599 compatible = <<
1600 reg = <0 0x00 <<
1601 #address-cell <<
1602 #size-cells = <<
1603 clocks = <&gc <<
1604 clock-names = <<
1605 interrupts = <<
1606 power-domains <<
1607 interconnects <<
1608 <<
1609 <<
1610 interconnect- <<
1611 status = "dis <<
1612 }; <<
1613 <<
1614 spi12: spi@a90000 { <<
1615 compatible = <<
1616 reg = <0 0x00 <<
1617 #address-cell <<
1618 #size-cells = <<
1619 clocks = <&gc <<
1620 clock-names = <<
1621 interrupts = <<
1622 power-domains <<
1623 interconnects <<
1624 <<
1625 <<
1626 interconnect- <<
1627 status = "dis <<
1628 }; <<
1629 <<
1630 i2c13: i2c@a94000 { <<
1631 compatible = <<
1632 reg = <0 0x00 <<
1633 #address-cell <<
1634 #size-cells = <<
1635 clocks = <&gc <<
1636 clock-names = <<
1637 interrupts = <<
1638 power-domains <<
1639 interconnects <<
1640 <<
1641 <<
1642 interconnect- <<
1643 status = "dis <<
1644 }; <<
1645 <<
1646 spi13: spi@a94000 { <<
1647 compatible = <<
1648 reg = <0 0x00 <<
1649 #address-cell <<
1650 #size-cells = <<
1651 clocks = <&gc <<
1652 clock-names = <<
1653 interrupts = <<
1654 power-domains <<
1655 interconnects <<
1656 <<
1657 <<
1658 interconnect- <<
1659 status = "dis <<
1660 }; <<
1661 <<
1662 i2c14: i2c@a98000 { <<
1663 compatible = <<
1664 reg = <0 0x00 <<
1665 #address-cell <<
1666 #size-cells = <<
1667 clocks = <&gc <<
1668 clock-names = <<
1669 interrupts = <<
1670 power-domains <<
1671 interconnects <<
1672 <<
1673 <<
1674 interconnect- <<
1675 status = "dis <<
1676 }; <<
1677 <<
1678 spi14: spi@a98000 { <<
1679 compatible = <<
1680 reg = <0 0x00 <<
1681 #address-cell <<
1682 #size-cells = <<
1683 clocks = <&gc <<
1684 clock-names = <<
1685 interrupts = <<
1686 power-domains <<
1687 interconnects <<
1688 <<
1689 <<
1690 interconnect- <<
1691 status = "dis <<
1692 }; <<
1693 <<
1694 i2c15: i2c@a9c000 { <<
1695 compatible = <<
1696 reg = <0 0x00 <<
1697 #address-cell <<
1698 #size-cells = <<
1699 clocks = <&gc <<
1700 clock-names = <<
1701 interrupts = <<
1702 power-domains <<
1703 interconnects <<
1704 <<
1705 <<
1706 interconnect- <<
1707 status = "dis <<
1708 }; <<
1709 <<
1710 spi15: spi@a9c000 { <<
1711 compatible = <<
1712 reg = <0 0x00 <<
1713 #address-cell <<
1714 #size-cells = <<
1715 clocks = <&gc <<
1716 clock-names = <<
1717 interrupts = <<
1718 power-domains <<
1719 interconnects <<
1720 <<
1721 <<
1722 interconnect- <<
1723 status = "dis <<
1724 }; <<
1725 }; <<
1726 <<
1727 rng: rng@10d3000 { <<
1728 compatible = "qcom,pr <<
1729 reg = <0 0x010d3000 0 <<
1730 clocks = <&rpmhcc RPM <<
1731 clock-names = "core"; <<
1732 }; 892 };
1733 893
1734 pcie4: pcie@1c00000 { 894 pcie4: pcie@1c00000 {
1735 device_type = "pci"; 895 device_type = "pci";
1736 compatible = "qcom,pc 896 compatible = "qcom,pcie-sc8280xp";
1737 reg = <0x0 0x01c00000 897 reg = <0x0 0x01c00000 0x0 0x3000>,
1738 <0x0 0x30000000 898 <0x0 0x30000000 0x0 0xf1d>,
1739 <0x0 0x30000f20 899 <0x0 0x30000f20 0x0 0xa8>,
1740 <0x0 0x30001000 900 <0x0 0x30001000 0x0 0x1000>,
1741 <0x0 0x30100000 !! 901 <0x0 0x30100000 0x0 0x100000>;
1742 <0x0 0x01c03000 !! 902 reg-names = "parf", "dbi", "elbi", "atu", "config";
1743 reg-names = "parf", " <<
1744 #address-cells = <3>; 903 #address-cells = <3>;
1745 #size-cells = <2>; 904 #size-cells = <2>;
1746 ranges = <0x01000000 905 ranges = <0x01000000 0x0 0x00000000 0x0 0x30200000 0x0 0x100000>,
1747 <0x02000000 906 <0x02000000 0x0 0x30300000 0x0 0x30300000 0x0 0x1d00000>;
1748 bus-range = <0x00 0xf 907 bus-range = <0x00 0xff>;
1749 908
1750 dma-coherent; 909 dma-coherent;
1751 910
1752 linux,pci-domain = <6 911 linux,pci-domain = <6>;
1753 num-lanes = <1>; 912 num-lanes = <1>;
1754 913
1755 msi-map = <0x0 &its 0 <<
1756 <<
1757 interrupts = <GIC_SPI 914 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
1758 <GIC_SPI 915 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
1759 <GIC_SPI 916 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
1760 <GIC_SPI 917 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
1761 interrupt-names = "ms 918 interrupt-names = "msi0", "msi1", "msi2", "msi3";
1762 919
1763 #interrupt-cells = <1 920 #interrupt-cells = <1>;
1764 interrupt-map-mask = 921 interrupt-map-mask = <0 0 0 0x7>;
1765 interrupt-map = <0 0 922 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
1766 <0 0 923 <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
1767 <0 0 924 <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
1768 <0 0 925 <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
1769 926
1770 clocks = <&gcc GCC_PC 927 clocks = <&gcc GCC_PCIE_4_AUX_CLK>,
1771 <&gcc GCC_PC 928 <&gcc GCC_PCIE_4_CFG_AHB_CLK>,
1772 <&gcc GCC_PC 929 <&gcc GCC_PCIE_4_MSTR_AXI_CLK>,
1773 <&gcc GCC_PC 930 <&gcc GCC_PCIE_4_SLV_AXI_CLK>,
1774 <&gcc GCC_PC 931 <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>,
1775 <&gcc GCC_DD 932 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1776 <&gcc GCC_AG 933 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
1777 <&gcc GCC_AG 934 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>,
1778 <&gcc GCC_CN 935 <&gcc GCC_CNOC_PCIE4_QX_CLK>;
1779 clock-names = "aux", 936 clock-names = "aux",
1780 "cfg", 937 "cfg",
1781 "bus_ma 938 "bus_master",
1782 "bus_sl 939 "bus_slave",
1783 "slave_ 940 "slave_q2a",
1784 "ddrss_ 941 "ddrss_sf_tbu",
1785 "noc_ag 942 "noc_aggr_4",
1786 "noc_ag 943 "noc_aggr_south_sf",
1787 "cnoc_q 944 "cnoc_qx";
1788 945
1789 assigned-clocks = <&g 946 assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>;
1790 assigned-clock-rates 947 assigned-clock-rates = <19200000>;
1791 948
1792 interconnects = <&agg 949 interconnects = <&aggre2_noc MASTER_PCIE_4 0 &mc_virt SLAVE_EBI1 0>,
1793 <&gem 950 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_4 0>;
1794 interconnect-names = 951 interconnect-names = "pcie-mem", "cpu-pcie";
1795 952
1796 resets = <&gcc GCC_PC 953 resets = <&gcc GCC_PCIE_4_BCR>;
1797 reset-names = "pci"; 954 reset-names = "pci";
1798 955
1799 power-domains = <&gcc 956 power-domains = <&gcc PCIE_4_GDSC>;
1800 required-opps = <&rpm <<
1801 957
1802 phys = <&pcie4_phy>; 958 phys = <&pcie4_phy>;
1803 phy-names = "pciephy" 959 phy-names = "pciephy";
1804 960
1805 status = "disabled"; 961 status = "disabled";
1806 <<
1807 pcie4_port0: pcie@0 { <<
1808 device_type = <<
1809 reg = <0x0 0x <<
1810 bus-range = < <<
1811 <<
1812 #address-cell <<
1813 #size-cells = <<
1814 ranges; <<
1815 }; <<
1816 }; 962 };
1817 963
1818 pcie4_phy: phy@1c06000 { 964 pcie4_phy: phy@1c06000 {
1819 compatible = "qcom,sc 965 compatible = "qcom,sc8280xp-qmp-gen3x1-pcie-phy";
1820 reg = <0x0 0x01c06000 966 reg = <0x0 0x01c06000 0x0 0x2000>;
1821 967
1822 clocks = <&gcc GCC_PC 968 clocks = <&gcc GCC_PCIE_4_AUX_CLK>,
1823 <&gcc GCC_PC 969 <&gcc GCC_PCIE_4_CFG_AHB_CLK>,
1824 <&gcc GCC_PC 970 <&gcc GCC_PCIE_4_CLKREF_CLK>,
1825 <&gcc GCC_PC 971 <&gcc GCC_PCIE4_PHY_RCHNG_CLK>,
1826 <&gcc GCC_PC 972 <&gcc GCC_PCIE_4_PIPE_CLK>,
1827 <&gcc GCC_PC 973 <&gcc GCC_PCIE_4_PIPEDIV2_CLK>;
1828 clock-names = "aux", 974 clock-names = "aux", "cfg_ahb", "ref", "rchng",
1829 "pipe", 975 "pipe", "pipediv2";
1830 976
1831 assigned-clocks = <&g 977 assigned-clocks = <&gcc GCC_PCIE4_PHY_RCHNG_CLK>;
1832 assigned-clock-rates 978 assigned-clock-rates = <100000000>;
1833 979
1834 power-domains = <&gcc 980 power-domains = <&gcc PCIE_4_GDSC>;
1835 981
1836 resets = <&gcc GCC_PC 982 resets = <&gcc GCC_PCIE_4_PHY_BCR>;
1837 reset-names = "phy"; 983 reset-names = "phy";
1838 984
1839 #clock-cells = <0>; 985 #clock-cells = <0>;
1840 clock-output-names = 986 clock-output-names = "pcie_4_pipe_clk";
1841 987
1842 #phy-cells = <0>; 988 #phy-cells = <0>;
1843 989
1844 status = "disabled"; 990 status = "disabled";
1845 }; 991 };
1846 992
1847 pcie3b: pcie@1c08000 { 993 pcie3b: pcie@1c08000 {
1848 device_type = "pci"; 994 device_type = "pci";
1849 compatible = "qcom,pc 995 compatible = "qcom,pcie-sc8280xp";
1850 reg = <0x0 0x01c08000 996 reg = <0x0 0x01c08000 0x0 0x3000>,
1851 <0x0 0x32000000 997 <0x0 0x32000000 0x0 0xf1d>,
1852 <0x0 0x32000f20 998 <0x0 0x32000f20 0x0 0xa8>,
1853 <0x0 0x32001000 999 <0x0 0x32001000 0x0 0x1000>,
1854 <0x0 0x32100000 !! 1000 <0x0 0x32100000 0x0 0x100000>;
1855 <0x0 0x01c0b000 !! 1001 reg-names = "parf", "dbi", "elbi", "atu", "config";
1856 reg-names = "parf", " <<
1857 #address-cells = <3>; 1002 #address-cells = <3>;
1858 #size-cells = <2>; 1003 #size-cells = <2>;
1859 ranges = <0x01000000 1004 ranges = <0x01000000 0x0 0x00000000 0x0 0x32200000 0x0 0x100000>,
1860 <0x02000000 1005 <0x02000000 0x0 0x32300000 0x0 0x32300000 0x0 0x1d00000>;
1861 bus-range = <0x00 0xf 1006 bus-range = <0x00 0xff>;
1862 1007
1863 dma-coherent; 1008 dma-coherent;
1864 1009
1865 linux,pci-domain = <5 1010 linux,pci-domain = <5>;
1866 num-lanes = <2>; 1011 num-lanes = <2>;
1867 1012
1868 msi-map = <0x0 &its 0 <<
1869 <<
1870 interrupts = <GIC_SPI 1013 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1871 <GIC_SPI 1014 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1872 <GIC_SPI 1015 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
1873 <GIC_SPI 1016 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
1874 interrupt-names = "ms 1017 interrupt-names = "msi0", "msi1", "msi2", "msi3";
1875 1018
1876 #interrupt-cells = <1 1019 #interrupt-cells = <1>;
1877 interrupt-map-mask = 1020 interrupt-map-mask = <0 0 0 0x7>;
1878 interrupt-map = <0 0 1021 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>,
1879 <0 0 1022 <0 0 0 2 &intc 0 0 GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>,
1880 <0 0 1023 <0 0 0 3 &intc 0 0 GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>,
1881 <0 0 1024 <0 0 0 4 &intc 0 0 GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>;
1882 1025
1883 clocks = <&gcc GCC_PC 1026 clocks = <&gcc GCC_PCIE_3B_AUX_CLK>,
1884 <&gcc GCC_PC 1027 <&gcc GCC_PCIE_3B_CFG_AHB_CLK>,
1885 <&gcc GCC_PC 1028 <&gcc GCC_PCIE_3B_MSTR_AXI_CLK>,
1886 <&gcc GCC_PC 1029 <&gcc GCC_PCIE_3B_SLV_AXI_CLK>,
1887 <&gcc GCC_PC 1030 <&gcc GCC_PCIE_3B_SLV_Q2A_AXI_CLK>,
1888 <&gcc GCC_DD 1031 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1889 <&gcc GCC_AG 1032 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
1890 <&gcc GCC_AG 1033 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
1891 clock-names = "aux", 1034 clock-names = "aux",
1892 "cfg", 1035 "cfg",
1893 "bus_ma 1036 "bus_master",
1894 "bus_sl 1037 "bus_slave",
1895 "slave_ 1038 "slave_q2a",
1896 "ddrss_ 1039 "ddrss_sf_tbu",
1897 "noc_ag 1040 "noc_aggr_4",
1898 "noc_ag 1041 "noc_aggr_south_sf";
1899 1042
1900 assigned-clocks = <&g 1043 assigned-clocks = <&gcc GCC_PCIE_3B_AUX_CLK>;
1901 assigned-clock-rates 1044 assigned-clock-rates = <19200000>;
1902 1045
1903 interconnects = <&agg 1046 interconnects = <&aggre2_noc MASTER_PCIE_3B 0 &mc_virt SLAVE_EBI1 0>,
1904 <&gem 1047 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3B 0>;
1905 interconnect-names = 1048 interconnect-names = "pcie-mem", "cpu-pcie";
1906 1049
1907 resets = <&gcc GCC_PC 1050 resets = <&gcc GCC_PCIE_3B_BCR>;
1908 reset-names = "pci"; 1051 reset-names = "pci";
1909 1052
1910 power-domains = <&gcc 1053 power-domains = <&gcc PCIE_3B_GDSC>;
1911 required-opps = <&rpm <<
1912 1054
1913 phys = <&pcie3b_phy>; 1055 phys = <&pcie3b_phy>;
1914 phy-names = "pciephy" 1056 phy-names = "pciephy";
1915 1057
1916 status = "disabled"; 1058 status = "disabled";
1917 <<
1918 pcie3b_port0: pcie@0 <<
1919 device_type = <<
1920 reg = <0x0 0x <<
1921 bus-range = < <<
1922 <<
1923 #address-cell <<
1924 #size-cells = <<
1925 ranges; <<
1926 }; <<
1927 }; 1059 };
1928 1060
1929 pcie3b_phy: phy@1c0e000 { 1061 pcie3b_phy: phy@1c0e000 {
1930 compatible = "qcom,sc 1062 compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy";
1931 reg = <0x0 0x01c0e000 1063 reg = <0x0 0x01c0e000 0x0 0x2000>;
1932 1064
1933 clocks = <&gcc GCC_PC 1065 clocks = <&gcc GCC_PCIE_3B_AUX_CLK>,
1934 <&gcc GCC_PC 1066 <&gcc GCC_PCIE_3B_CFG_AHB_CLK>,
1935 <&gcc GCC_PC 1067 <&gcc GCC_PCIE_3A3B_CLKREF_CLK>,
1936 <&gcc GCC_PC 1068 <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>,
1937 <&gcc GCC_PC 1069 <&gcc GCC_PCIE_3B_PIPE_CLK>,
1938 <&gcc GCC_PC 1070 <&gcc GCC_PCIE_3B_PIPEDIV2_CLK>;
1939 clock-names = "aux", 1071 clock-names = "aux", "cfg_ahb", "ref", "rchng",
1940 "pipe", 1072 "pipe", "pipediv2";
1941 1073
1942 assigned-clocks = <&g 1074 assigned-clocks = <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>;
1943 assigned-clock-rates 1075 assigned-clock-rates = <100000000>;
1944 1076
1945 power-domains = <&gcc 1077 power-domains = <&gcc PCIE_3B_GDSC>;
1946 1078
1947 resets = <&gcc GCC_PC 1079 resets = <&gcc GCC_PCIE_3B_PHY_BCR>;
1948 reset-names = "phy"; 1080 reset-names = "phy";
1949 1081
1950 #clock-cells = <0>; 1082 #clock-cells = <0>;
1951 clock-output-names = 1083 clock-output-names = "pcie_3b_pipe_clk";
1952 1084
1953 #phy-cells = <0>; 1085 #phy-cells = <0>;
1954 1086
1955 status = "disabled"; 1087 status = "disabled";
1956 }; 1088 };
1957 1089
1958 pcie3a: pcie@1c10000 { 1090 pcie3a: pcie@1c10000 {
1959 device_type = "pci"; 1091 device_type = "pci";
1960 compatible = "qcom,pc 1092 compatible = "qcom,pcie-sc8280xp";
1961 reg = <0x0 0x01c10000 1093 reg = <0x0 0x01c10000 0x0 0x3000>,
1962 <0x0 0x34000000 1094 <0x0 0x34000000 0x0 0xf1d>,
1963 <0x0 0x34000f20 1095 <0x0 0x34000f20 0x0 0xa8>,
1964 <0x0 0x34001000 1096 <0x0 0x34001000 0x0 0x1000>,
1965 <0x0 0x34100000 !! 1097 <0x0 0x34100000 0x0 0x100000>;
1966 <0x0 0x01c13000 !! 1098 reg-names = "parf", "dbi", "elbi", "atu", "config";
1967 reg-names = "parf", " <<
1968 #address-cells = <3>; 1099 #address-cells = <3>;
1969 #size-cells = <2>; 1100 #size-cells = <2>;
1970 ranges = <0x01000000 1101 ranges = <0x01000000 0x0 0x00000000 0x0 0x34200000 0x0 0x100000>,
1971 <0x02000000 1102 <0x02000000 0x0 0x34300000 0x0 0x34300000 0x0 0x1d00000>;
1972 bus-range = <0x00 0xf 1103 bus-range = <0x00 0xff>;
1973 1104
1974 dma-coherent; 1105 dma-coherent;
1975 1106
1976 linux,pci-domain = <4 1107 linux,pci-domain = <4>;
1977 num-lanes = <4>; 1108 num-lanes = <4>;
1978 1109
1979 msi-map = <0x0 &its 0 <<
1980 <<
1981 interrupts = <GIC_SPI 1110 interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
1982 <GIC_SPI 1111 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
1983 <GIC_SPI 1112 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
1984 <GIC_SPI 1113 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1985 interrupt-names = "ms 1114 interrupt-names = "msi0", "msi1", "msi2", "msi3";
1986 1115
1987 #interrupt-cells = <1 1116 #interrupt-cells = <1>;
1988 interrupt-map-mask = 1117 interrupt-map-mask = <0 0 0 0x7>;
1989 interrupt-map = <0 0 1118 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>,
1990 <0 0 1119 <0 0 0 2 &intc 0 0 GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>,
1991 <0 0 1120 <0 0 0 3 &intc 0 0 GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>,
1992 <0 0 1121 <0 0 0 4 &intc 0 0 GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>;
1993 1122
1994 clocks = <&gcc GCC_PC 1123 clocks = <&gcc GCC_PCIE_3A_AUX_CLK>,
1995 <&gcc GCC_PC 1124 <&gcc GCC_PCIE_3A_CFG_AHB_CLK>,
1996 <&gcc GCC_PC 1125 <&gcc GCC_PCIE_3A_MSTR_AXI_CLK>,
1997 <&gcc GCC_PC 1126 <&gcc GCC_PCIE_3A_SLV_AXI_CLK>,
1998 <&gcc GCC_PC 1127 <&gcc GCC_PCIE_3A_SLV_Q2A_AXI_CLK>,
1999 <&gcc GCC_DD 1128 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
2000 <&gcc GCC_AG 1129 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
2001 <&gcc GCC_AG 1130 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
2002 clock-names = "aux", 1131 clock-names = "aux",
2003 "cfg", 1132 "cfg",
2004 "bus_ma 1133 "bus_master",
2005 "bus_sl 1134 "bus_slave",
2006 "slave_ 1135 "slave_q2a",
2007 "ddrss_ 1136 "ddrss_sf_tbu",
2008 "noc_ag 1137 "noc_aggr_4",
2009 "noc_ag 1138 "noc_aggr_south_sf";
2010 1139
2011 assigned-clocks = <&g 1140 assigned-clocks = <&gcc GCC_PCIE_3A_AUX_CLK>;
2012 assigned-clock-rates 1141 assigned-clock-rates = <19200000>;
2013 1142
2014 interconnects = <&agg 1143 interconnects = <&aggre2_noc MASTER_PCIE_3A 0 &mc_virt SLAVE_EBI1 0>,
2015 <&gem 1144 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3A 0>;
2016 interconnect-names = 1145 interconnect-names = "pcie-mem", "cpu-pcie";
2017 1146
2018 resets = <&gcc GCC_PC 1147 resets = <&gcc GCC_PCIE_3A_BCR>;
2019 reset-names = "pci"; 1148 reset-names = "pci";
2020 1149
2021 power-domains = <&gcc 1150 power-domains = <&gcc PCIE_3A_GDSC>;
2022 required-opps = <&rpm <<
2023 1151
2024 phys = <&pcie3a_phy>; 1152 phys = <&pcie3a_phy>;
2025 phy-names = "pciephy" 1153 phy-names = "pciephy";
2026 1154
2027 status = "disabled"; 1155 status = "disabled";
2028 <<
2029 pcie3a_port0: pcie@0 <<
2030 device_type = <<
2031 reg = <0x0 0x <<
2032 bus-range = < <<
2033 <<
2034 #address-cell <<
2035 #size-cells = <<
2036 ranges; <<
2037 }; <<
2038 }; 1156 };
2039 1157
2040 pcie3a_phy: phy@1c14000 { 1158 pcie3a_phy: phy@1c14000 {
2041 compatible = "qcom,sc 1159 compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy";
2042 reg = <0x0 0x01c14000 1160 reg = <0x0 0x01c14000 0x0 0x2000>,
2043 <0x0 0x01c16000 1161 <0x0 0x01c16000 0x0 0x2000>;
2044 1162
2045 clocks = <&gcc GCC_PC 1163 clocks = <&gcc GCC_PCIE_3A_AUX_CLK>,
2046 <&gcc GCC_PC 1164 <&gcc GCC_PCIE_3A_CFG_AHB_CLK>,
2047 <&gcc GCC_PC 1165 <&gcc GCC_PCIE_3A3B_CLKREF_CLK>,
2048 <&gcc GCC_PC 1166 <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>,
2049 <&gcc GCC_PC 1167 <&gcc GCC_PCIE_3A_PIPE_CLK>,
2050 <&gcc GCC_PC 1168 <&gcc GCC_PCIE_3A_PIPEDIV2_CLK>;
2051 clock-names = "aux", 1169 clock-names = "aux", "cfg_ahb", "ref", "rchng",
2052 "pipe", 1170 "pipe", "pipediv2";
2053 1171
2054 assigned-clocks = <&g 1172 assigned-clocks = <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>;
2055 assigned-clock-rates 1173 assigned-clock-rates = <100000000>;
2056 1174
2057 power-domains = <&gcc 1175 power-domains = <&gcc PCIE_3A_GDSC>;
2058 1176
2059 resets = <&gcc GCC_PC 1177 resets = <&gcc GCC_PCIE_3A_PHY_BCR>;
2060 reset-names = "phy"; 1178 reset-names = "phy";
2061 1179
2062 qcom,4ln-config-sel = 1180 qcom,4ln-config-sel = <&tcsr 0xa044 1>;
2063 1181
2064 #clock-cells = <0>; 1182 #clock-cells = <0>;
2065 clock-output-names = 1183 clock-output-names = "pcie_3a_pipe_clk";
2066 1184
2067 #phy-cells = <0>; 1185 #phy-cells = <0>;
2068 1186
2069 status = "disabled"; 1187 status = "disabled";
2070 }; 1188 };
2071 1189
2072 pcie2b: pcie@1c18000 { 1190 pcie2b: pcie@1c18000 {
2073 device_type = "pci"; 1191 device_type = "pci";
2074 compatible = "qcom,pc 1192 compatible = "qcom,pcie-sc8280xp";
2075 reg = <0x0 0x01c18000 1193 reg = <0x0 0x01c18000 0x0 0x3000>,
2076 <0x0 0x38000000 1194 <0x0 0x38000000 0x0 0xf1d>,
2077 <0x0 0x38000f20 1195 <0x0 0x38000f20 0x0 0xa8>,
2078 <0x0 0x38001000 1196 <0x0 0x38001000 0x0 0x1000>,
2079 <0x0 0x38100000 !! 1197 <0x0 0x38100000 0x0 0x100000>;
2080 <0x0 0x01c1b000 !! 1198 reg-names = "parf", "dbi", "elbi", "atu", "config";
2081 reg-names = "parf", " <<
2082 #address-cells = <3>; 1199 #address-cells = <3>;
2083 #size-cells = <2>; 1200 #size-cells = <2>;
2084 ranges = <0x01000000 1201 ranges = <0x01000000 0x0 0x00000000 0x0 0x38200000 0x0 0x100000>,
2085 <0x02000000 1202 <0x02000000 0x0 0x38300000 0x0 0x38300000 0x0 0x1d00000>;
2086 bus-range = <0x00 0xf 1203 bus-range = <0x00 0xff>;
2087 1204
2088 dma-coherent; 1205 dma-coherent;
2089 1206
2090 linux,pci-domain = <3 1207 linux,pci-domain = <3>;
2091 num-lanes = <2>; 1208 num-lanes = <2>;
2092 1209
2093 msi-map = <0x0 &its 0 <<
2094 <<
2095 interrupts = <GIC_SPI 1210 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
2096 <GIC_SPI 1211 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
2097 <GIC_SPI 1212 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
2098 <GIC_SPI 1213 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
2099 interrupt-names = "ms 1214 interrupt-names = "msi0", "msi1", "msi2", "msi3";
2100 1215
2101 #interrupt-cells = <1 1216 #interrupt-cells = <1>;
2102 interrupt-map-mask = 1217 interrupt-map-mask = <0 0 0 0x7>;
2103 interrupt-map = <0 0 1218 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
2104 <0 0 1219 <0 0 0 2 &intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
2105 <0 0 1220 <0 0 0 3 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
2106 <0 0 1221 <0 0 0 4 &intc 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>;
2107 1222
2108 clocks = <&gcc GCC_PC 1223 clocks = <&gcc GCC_PCIE_2B_AUX_CLK>,
2109 <&gcc GCC_PC 1224 <&gcc GCC_PCIE_2B_CFG_AHB_CLK>,
2110 <&gcc GCC_PC 1225 <&gcc GCC_PCIE_2B_MSTR_AXI_CLK>,
2111 <&gcc GCC_PC 1226 <&gcc GCC_PCIE_2B_SLV_AXI_CLK>,
2112 <&gcc GCC_PC 1227 <&gcc GCC_PCIE_2B_SLV_Q2A_AXI_CLK>,
2113 <&gcc GCC_DD 1228 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
2114 <&gcc GCC_AG 1229 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
2115 <&gcc GCC_AG 1230 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
2116 clock-names = "aux", 1231 clock-names = "aux",
2117 "cfg", 1232 "cfg",
2118 "bus_ma 1233 "bus_master",
2119 "bus_sl 1234 "bus_slave",
2120 "slave_ 1235 "slave_q2a",
2121 "ddrss_ 1236 "ddrss_sf_tbu",
2122 "noc_ag 1237 "noc_aggr_4",
2123 "noc_ag 1238 "noc_aggr_south_sf";
2124 1239
2125 assigned-clocks = <&g 1240 assigned-clocks = <&gcc GCC_PCIE_2B_AUX_CLK>;
2126 assigned-clock-rates 1241 assigned-clock-rates = <19200000>;
2127 1242
2128 interconnects = <&agg 1243 interconnects = <&aggre2_noc MASTER_PCIE_2B 0 &mc_virt SLAVE_EBI1 0>,
2129 <&gem 1244 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2B 0>;
2130 interconnect-names = 1245 interconnect-names = "pcie-mem", "cpu-pcie";
2131 1246
2132 resets = <&gcc GCC_PC 1247 resets = <&gcc GCC_PCIE_2B_BCR>;
2133 reset-names = "pci"; 1248 reset-names = "pci";
2134 1249
2135 power-domains = <&gcc 1250 power-domains = <&gcc PCIE_2B_GDSC>;
2136 required-opps = <&rpm <<
2137 1251
2138 phys = <&pcie2b_phy>; 1252 phys = <&pcie2b_phy>;
2139 phy-names = "pciephy" 1253 phy-names = "pciephy";
2140 1254
2141 status = "disabled"; 1255 status = "disabled";
2142 <<
2143 pcie2b_port0: pcie@0 <<
2144 device_type = <<
2145 reg = <0x0 0x <<
2146 bus-range = < <<
2147 <<
2148 #address-cell <<
2149 #size-cells = <<
2150 ranges; <<
2151 }; <<
2152 }; 1256 };
2153 1257
2154 pcie2b_phy: phy@1c1e000 { 1258 pcie2b_phy: phy@1c1e000 {
2155 compatible = "qcom,sc 1259 compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy";
2156 reg = <0x0 0x01c1e000 1260 reg = <0x0 0x01c1e000 0x0 0x2000>;
2157 1261
2158 clocks = <&gcc GCC_PC 1262 clocks = <&gcc GCC_PCIE_2B_AUX_CLK>,
2159 <&gcc GCC_PC 1263 <&gcc GCC_PCIE_2B_CFG_AHB_CLK>,
2160 <&gcc GCC_PC 1264 <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
2161 <&gcc GCC_PC 1265 <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>,
2162 <&gcc GCC_PC 1266 <&gcc GCC_PCIE_2B_PIPE_CLK>,
2163 <&gcc GCC_PC 1267 <&gcc GCC_PCIE_2B_PIPEDIV2_CLK>;
2164 clock-names = "aux", 1268 clock-names = "aux", "cfg_ahb", "ref", "rchng",
2165 "pipe", 1269 "pipe", "pipediv2";
2166 1270
2167 assigned-clocks = <&g 1271 assigned-clocks = <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>;
2168 assigned-clock-rates 1272 assigned-clock-rates = <100000000>;
2169 1273
2170 power-domains = <&gcc 1274 power-domains = <&gcc PCIE_2B_GDSC>;
2171 1275
2172 resets = <&gcc GCC_PC 1276 resets = <&gcc GCC_PCIE_2B_PHY_BCR>;
2173 reset-names = "phy"; 1277 reset-names = "phy";
2174 1278
2175 #clock-cells = <0>; 1279 #clock-cells = <0>;
2176 clock-output-names = 1280 clock-output-names = "pcie_2b_pipe_clk";
2177 1281
2178 #phy-cells = <0>; 1282 #phy-cells = <0>;
2179 1283
2180 status = "disabled"; 1284 status = "disabled";
2181 }; 1285 };
2182 1286
2183 pcie2a: pcie@1c20000 { 1287 pcie2a: pcie@1c20000 {
2184 device_type = "pci"; 1288 device_type = "pci";
2185 compatible = "qcom,pc 1289 compatible = "qcom,pcie-sc8280xp";
2186 reg = <0x0 0x01c20000 1290 reg = <0x0 0x01c20000 0x0 0x3000>,
2187 <0x0 0x3c000000 1291 <0x0 0x3c000000 0x0 0xf1d>,
2188 <0x0 0x3c000f20 1292 <0x0 0x3c000f20 0x0 0xa8>,
2189 <0x0 0x3c001000 1293 <0x0 0x3c001000 0x0 0x1000>,
2190 <0x0 0x3c100000 !! 1294 <0x0 0x3c100000 0x0 0x100000>;
2191 <0x0 0x01c23000 !! 1295 reg-names = "parf", "dbi", "elbi", "atu", "config";
2192 reg-names = "parf", " <<
2193 #address-cells = <3>; 1296 #address-cells = <3>;
2194 #size-cells = <2>; 1297 #size-cells = <2>;
2195 ranges = <0x01000000 1298 ranges = <0x01000000 0x0 0x00000000 0x0 0x3c200000 0x0 0x100000>,
2196 <0x02000000 1299 <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>;
2197 bus-range = <0x00 0xf 1300 bus-range = <0x00 0xff>;
2198 1301
2199 dma-coherent; 1302 dma-coherent;
2200 1303
2201 linux,pci-domain = <2 1304 linux,pci-domain = <2>;
2202 num-lanes = <4>; 1305 num-lanes = <4>;
2203 1306
2204 msi-map = <0x0 &its 0 <<
2205 <<
2206 interrupts = <GIC_SPI 1307 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
2207 <GIC_SPI 1308 <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>,
2208 <GIC_SPI 1309 <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>,
2209 <GIC_SPI 1310 <GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH>;
2210 interrupt-names = "ms 1311 interrupt-names = "msi0", "msi1", "msi2", "msi3";
2211 1312
2212 #interrupt-cells = <1 1313 #interrupt-cells = <1>;
2213 interrupt-map-mask = 1314 interrupt-map-mask = <0 0 0 0x7>;
2214 interrupt-map = <0 0 1315 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>,
2215 <0 0 1316 <0 0 0 2 &intc 0 0 GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>,
2216 <0 0 1317 <0 0 0 3 &intc 0 0 GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>,
2217 <0 0 1318 <0 0 0 4 &intc 0 0 GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>;
2218 1319
2219 clocks = <&gcc GCC_PC 1320 clocks = <&gcc GCC_PCIE_2A_AUX_CLK>,
2220 <&gcc GCC_PC 1321 <&gcc GCC_PCIE_2A_CFG_AHB_CLK>,
2221 <&gcc GCC_PC 1322 <&gcc GCC_PCIE_2A_MSTR_AXI_CLK>,
2222 <&gcc GCC_PC 1323 <&gcc GCC_PCIE_2A_SLV_AXI_CLK>,
2223 <&gcc GCC_PC 1324 <&gcc GCC_PCIE_2A_SLV_Q2A_AXI_CLK>,
2224 <&gcc GCC_DD 1325 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
2225 <&gcc GCC_AG 1326 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
2226 <&gcc GCC_AG 1327 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
2227 clock-names = "aux", 1328 clock-names = "aux",
2228 "cfg", 1329 "cfg",
2229 "bus_ma 1330 "bus_master",
2230 "bus_sl 1331 "bus_slave",
2231 "slave_ 1332 "slave_q2a",
2232 "ddrss_ 1333 "ddrss_sf_tbu",
2233 "noc_ag 1334 "noc_aggr_4",
2234 "noc_ag 1335 "noc_aggr_south_sf";
2235 1336
2236 assigned-clocks = <&g 1337 assigned-clocks = <&gcc GCC_PCIE_2A_AUX_CLK>;
2237 assigned-clock-rates 1338 assigned-clock-rates = <19200000>;
2238 1339
2239 interconnects = <&agg 1340 interconnects = <&aggre2_noc MASTER_PCIE_2A 0 &mc_virt SLAVE_EBI1 0>,
2240 <&gem 1341 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2A 0>;
2241 interconnect-names = 1342 interconnect-names = "pcie-mem", "cpu-pcie";
2242 1343
2243 resets = <&gcc GCC_PC 1344 resets = <&gcc GCC_PCIE_2A_BCR>;
2244 reset-names = "pci"; 1345 reset-names = "pci";
2245 1346
2246 power-domains = <&gcc 1347 power-domains = <&gcc PCIE_2A_GDSC>;
2247 required-opps = <&rpm <<
2248 1348
2249 phys = <&pcie2a_phy>; 1349 phys = <&pcie2a_phy>;
2250 phy-names = "pciephy" 1350 phy-names = "pciephy";
2251 1351
2252 status = "disabled"; 1352 status = "disabled";
2253 <<
2254 pcie2a_port0: pcie@0 <<
2255 device_type = <<
2256 reg = <0x0 0x <<
2257 bus-range = < <<
2258 <<
2259 #address-cell <<
2260 #size-cells = <<
2261 ranges; <<
2262 }; <<
2263 }; 1353 };
2264 1354
2265 pcie2a_phy: phy@1c24000 { 1355 pcie2a_phy: phy@1c24000 {
2266 compatible = "qcom,sc 1356 compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy";
2267 reg = <0x0 0x01c24000 1357 reg = <0x0 0x01c24000 0x0 0x2000>,
2268 <0x0 0x01c26000 1358 <0x0 0x01c26000 0x0 0x2000>;
2269 1359
2270 clocks = <&gcc GCC_PC 1360 clocks = <&gcc GCC_PCIE_2A_AUX_CLK>,
2271 <&gcc GCC_PC 1361 <&gcc GCC_PCIE_2A_CFG_AHB_CLK>,
2272 <&gcc GCC_PC 1362 <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
2273 <&gcc GCC_PC 1363 <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>,
2274 <&gcc GCC_PC 1364 <&gcc GCC_PCIE_2A_PIPE_CLK>,
2275 <&gcc GCC_PC 1365 <&gcc GCC_PCIE_2A_PIPEDIV2_CLK>;
2276 clock-names = "aux", 1366 clock-names = "aux", "cfg_ahb", "ref", "rchng",
2277 "pipe", 1367 "pipe", "pipediv2";
2278 1368
2279 assigned-clocks = <&g 1369 assigned-clocks = <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>;
2280 assigned-clock-rates 1370 assigned-clock-rates = <100000000>;
2281 1371
2282 power-domains = <&gcc 1372 power-domains = <&gcc PCIE_2A_GDSC>;
2283 1373
2284 resets = <&gcc GCC_PC 1374 resets = <&gcc GCC_PCIE_2A_PHY_BCR>;
2285 reset-names = "phy"; 1375 reset-names = "phy";
2286 1376
2287 qcom,4ln-config-sel = 1377 qcom,4ln-config-sel = <&tcsr 0xa044 0>;
2288 1378
2289 #clock-cells = <0>; 1379 #clock-cells = <0>;
2290 clock-output-names = 1380 clock-output-names = "pcie_2a_pipe_clk";
2291 1381
2292 #phy-cells = <0>; 1382 #phy-cells = <0>;
2293 1383
2294 status = "disabled"; 1384 status = "disabled";
2295 }; 1385 };
2296 1386
2297 ufs_mem_hc: ufs@1d84000 { 1387 ufs_mem_hc: ufs@1d84000 {
2298 compatible = "qcom,sc 1388 compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc",
2299 "jedec,u 1389 "jedec,ufs-2.0";
2300 reg = <0 0x01d84000 0 1390 reg = <0 0x01d84000 0 0x3000>;
2301 interrupts = <GIC_SPI 1391 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2302 phys = <&ufs_mem_phy> 1392 phys = <&ufs_mem_phy>;
2303 phy-names = "ufsphy"; 1393 phy-names = "ufsphy";
2304 lanes-per-direction = 1394 lanes-per-direction = <2>;
2305 #reset-cells = <1>; 1395 #reset-cells = <1>;
2306 resets = <&gcc GCC_UF 1396 resets = <&gcc GCC_UFS_PHY_BCR>;
2307 reset-names = "rst"; 1397 reset-names = "rst";
2308 1398
2309 power-domains = <&gcc 1399 power-domains = <&gcc UFS_PHY_GDSC>;
2310 required-opps = <&rpm 1400 required-opps = <&rpmhpd_opp_nom>;
2311 1401
2312 iommus = <&apps_smmu 1402 iommus = <&apps_smmu 0xe0 0x0>;
2313 dma-coherent; 1403 dma-coherent;
2314 1404
2315 clocks = <&gcc GCC_UF 1405 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
2316 <&gcc GCC_AG 1406 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2317 <&gcc GCC_UF 1407 <&gcc GCC_UFS_PHY_AHB_CLK>,
2318 <&gcc GCC_UF 1408 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2319 <&gcc GCC_UF 1409 <&gcc GCC_UFS_REF_CLKREF_CLK>,
2320 <&gcc GCC_UF 1410 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2321 <&gcc GCC_UF 1411 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2322 <&gcc GCC_UF 1412 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
2323 clock-names = "core_c 1413 clock-names = "core_clk",
2324 "bus_ag 1414 "bus_aggr_clk",
2325 "iface_ 1415 "iface_clk",
2326 "core_c 1416 "core_clk_unipro",
2327 "ref_cl 1417 "ref_clk",
2328 "tx_lan 1418 "tx_lane0_sync_clk",
2329 "rx_lan 1419 "rx_lane0_sync_clk",
2330 "rx_lan 1420 "rx_lane1_sync_clk";
2331 freq-table-hz = <7500 1421 freq-table-hz = <75000000 300000000>,
2332 <0 0> 1422 <0 0>,
2333 <0 0> 1423 <0 0>,
2334 <7500 1424 <75000000 300000000>,
2335 <0 0> 1425 <0 0>,
2336 <0 0> 1426 <0 0>,
2337 <0 0> 1427 <0 0>,
2338 <0 0> 1428 <0 0>;
2339 status = "disabled"; 1429 status = "disabled";
2340 }; 1430 };
2341 1431
2342 ufs_mem_phy: phy@1d87000 { 1432 ufs_mem_phy: phy@1d87000 {
2343 compatible = "qcom,sc 1433 compatible = "qcom,sc8280xp-qmp-ufs-phy";
2344 reg = <0 0x01d87000 0 1434 reg = <0 0x01d87000 0 0x1000>;
2345 1435
2346 clocks = <&rpmhcc RPM !! 1436 clocks = <&gcc GCC_UFS_CARD_CLKREF_CLK>,
2347 <&gcc GCC_UF !! 1437 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
2348 <&gcc GCC_UF !! 1438 clock-names = "ref", "ref_aux";
2349 clock-names = "ref", <<
2350 "ref_au <<
2351 "qref"; <<
2352 1439
2353 power-domains = <&gcc 1440 power-domains = <&gcc UFS_PHY_GDSC>;
2354 1441
2355 resets = <&ufs_mem_hc 1442 resets = <&ufs_mem_hc 0>;
2356 reset-names = "ufsphy 1443 reset-names = "ufsphy";
2357 1444
2358 #phy-cells = <0>; 1445 #phy-cells = <0>;
2359 1446
2360 status = "disabled"; 1447 status = "disabled";
2361 }; 1448 };
2362 1449
2363 ufs_card_hc: ufs@1da4000 { 1450 ufs_card_hc: ufs@1da4000 {
2364 compatible = "qcom,sc 1451 compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc",
2365 "jedec,u 1452 "jedec,ufs-2.0";
2366 reg = <0 0x01da4000 0 1453 reg = <0 0x01da4000 0 0x3000>;
2367 interrupts = <GIC_SPI 1454 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
2368 phys = <&ufs_card_phy 1455 phys = <&ufs_card_phy>;
2369 phy-names = "ufsphy"; 1456 phy-names = "ufsphy";
2370 lanes-per-direction = 1457 lanes-per-direction = <2>;
2371 #reset-cells = <1>; 1458 #reset-cells = <1>;
2372 resets = <&gcc GCC_UF 1459 resets = <&gcc GCC_UFS_CARD_BCR>;
2373 reset-names = "rst"; 1460 reset-names = "rst";
2374 1461
2375 power-domains = <&gcc 1462 power-domains = <&gcc UFS_CARD_GDSC>;
2376 1463
2377 iommus = <&apps_smmu 1464 iommus = <&apps_smmu 0x4a0 0x0>;
2378 dma-coherent; 1465 dma-coherent;
2379 1466
2380 clocks = <&gcc GCC_UF 1467 clocks = <&gcc GCC_UFS_CARD_AXI_CLK>,
2381 <&gcc GCC_AG 1468 <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>,
2382 <&gcc GCC_UF 1469 <&gcc GCC_UFS_CARD_AHB_CLK>,
2383 <&gcc GCC_UF 1470 <&gcc GCC_UFS_CARD_UNIPRO_CORE_CLK>,
2384 <&gcc GCC_UF 1471 <&gcc GCC_UFS_REF_CLKREF_CLK>,
2385 <&gcc GCC_UF 1472 <&gcc GCC_UFS_CARD_TX_SYMBOL_0_CLK>,
2386 <&gcc GCC_UF 1473 <&gcc GCC_UFS_CARD_RX_SYMBOL_0_CLK>,
2387 <&gcc GCC_UF 1474 <&gcc GCC_UFS_CARD_RX_SYMBOL_1_CLK>;
2388 clock-names = "core_c 1475 clock-names = "core_clk",
2389 "bus_ag 1476 "bus_aggr_clk",
2390 "iface_ 1477 "iface_clk",
2391 "core_c 1478 "core_clk_unipro",
2392 "ref_cl 1479 "ref_clk",
2393 "tx_lan 1480 "tx_lane0_sync_clk",
2394 "rx_lan 1481 "rx_lane0_sync_clk",
2395 "rx_lan 1482 "rx_lane1_sync_clk";
2396 freq-table-hz = <7500 1483 freq-table-hz = <75000000 300000000>,
2397 <0 0> 1484 <0 0>,
2398 <0 0> 1485 <0 0>,
2399 <7500 1486 <75000000 300000000>,
2400 <0 0> 1487 <0 0>,
2401 <0 0> 1488 <0 0>,
2402 <0 0> 1489 <0 0>,
2403 <0 0> 1490 <0 0>;
2404 status = "disabled"; 1491 status = "disabled";
2405 }; 1492 };
2406 1493
2407 ufs_card_phy: phy@1da7000 { 1494 ufs_card_phy: phy@1da7000 {
2408 compatible = "qcom,sc 1495 compatible = "qcom,sc8280xp-qmp-ufs-phy";
2409 reg = <0 0x01da7000 0 1496 reg = <0 0x01da7000 0 0x1000>;
2410 1497
2411 clocks = <&rpmhcc RPM !! 1498 clocks = <&gcc GCC_UFS_1_CARD_CLKREF_CLK>,
2412 <&gcc GCC_UF !! 1499 <&gcc GCC_UFS_CARD_PHY_AUX_CLK>;
2413 <&gcc GCC_UF !! 1500 clock-names = "ref", "ref_aux";
2414 clock-names = "ref", <<
2415 "ref_au <<
2416 "qref"; <<
2417 1501
2418 power-domains = <&gcc 1502 power-domains = <&gcc UFS_CARD_GDSC>;
2419 1503
2420 resets = <&ufs_card_h 1504 resets = <&ufs_card_hc 0>;
2421 reset-names = "ufsphy 1505 reset-names = "ufsphy";
2422 1506
2423 #phy-cells = <0>; 1507 #phy-cells = <0>;
2424 1508
2425 status = "disabled"; 1509 status = "disabled";
2426 }; 1510 };
2427 1511
2428 tcsr_mutex: hwlock@1f40000 { 1512 tcsr_mutex: hwlock@1f40000 {
2429 compatible = "qcom,tc 1513 compatible = "qcom,tcsr-mutex";
2430 reg = <0x0 0x01f40000 1514 reg = <0x0 0x01f40000 0x0 0x20000>;
2431 #hwlock-cells = <1>; 1515 #hwlock-cells = <1>;
2432 }; 1516 };
2433 1517
2434 tcsr: syscon@1fc0000 { 1518 tcsr: syscon@1fc0000 {
2435 compatible = "qcom,sc 1519 compatible = "qcom,sc8280xp-tcsr", "syscon";
2436 reg = <0x0 0x01fc0000 1520 reg = <0x0 0x01fc0000 0x0 0x30000>;
2437 }; 1521 };
2438 1522
2439 gpu: gpu@3d00000 { <<
2440 compatible = "qcom,ad <<
2441 <<
2442 reg = <0 0x03d00000 0 <<
2443 <0 0x03d9e000 0 <<
2444 <0 0x03d61000 0 <<
2445 reg-names = "kgsl_3d0 <<
2446 "cx_mem", <<
2447 "cx_dbgc" <<
2448 interrupts = <GIC_SPI <<
2449 iommus = <&gpu_smmu 0 <<
2450 operating-points-v2 = <<
2451 <<
2452 qcom,gmu = <&gmu>; <<
2453 interconnects = <&gem <<
2454 interconnect-names = <<
2455 #cooling-cells = <2>; <<
2456 <<
2457 status = "disabled"; <<
2458 <<
2459 gpu_opp_table: opp-ta <<
2460 compatible = <<
2461 <<
2462 opp-270000000 <<
2463 opp-h <<
2464 opp-l <<
2465 opp-p <<
2466 }; <<
2467 <<
2468 opp-410000000 <<
2469 opp-h <<
2470 opp-l <<
2471 opp-p <<
2472 }; <<
2473 <<
2474 opp-500000000 <<
2475 opp-h <<
2476 opp-l <<
2477 opp-p <<
2478 }; <<
2479 <<
2480 opp-547000000 <<
2481 opp-h <<
2482 opp-l <<
2483 opp-p <<
2484 }; <<
2485 <<
2486 opp-606000000 <<
2487 opp-h <<
2488 opp-l <<
2489 opp-p <<
2490 }; <<
2491 <<
2492 opp-640000000 <<
2493 opp-h <<
2494 opp-l <<
2495 opp-p <<
2496 }; <<
2497 <<
2498 opp-655000000 <<
2499 opp-h <<
2500 opp-l <<
2501 opp-p <<
2502 }; <<
2503 <<
2504 opp-690000000 <<
2505 opp-h <<
2506 opp-l <<
2507 opp-p <<
2508 }; <<
2509 }; <<
2510 }; <<
2511 <<
2512 gmu: gmu@3d6a000 { <<
2513 compatible = "qcom,ad <<
2514 reg = <0 0x03d6a000 0 <<
2515 <0 0x03de0000 0 <<
2516 <0 0x0b290000 0 <<
2517 reg-names = "gmu", "r <<
2518 interrupts = <GIC_SPI <<
2519 <GIC_SPI <<
2520 interrupt-names = "hf <<
2521 clocks = <&gpucc GPU_ <<
2522 <&gpucc GPU_ <<
2523 <&gcc GCC_DD <<
2524 <&gcc GCC_GP <<
2525 <&gpucc GPU_ <<
2526 <&gpucc GPU_ <<
2527 <&gpucc GPU_ <<
2528 clock-names = "gmu", <<
2529 "cxo", <<
2530 "axi", <<
2531 "memnoc <<
2532 "ahb", <<
2533 "hub", <<
2534 "smmu_v <<
2535 power-domains = <&gpu <<
2536 <&gpu <<
2537 power-domain-names = <<
2538 <<
2539 iommus = <&gpu_smmu 5 <<
2540 operating-points-v2 = <<
2541 <<
2542 gmu_opp_table: opp-ta <<
2543 compatible = <<
2544 <<
2545 opp-200000000 <<
2546 opp-h <<
2547 opp-l <<
2548 }; <<
2549 <<
2550 opp-500000000 <<
2551 opp-h <<
2552 opp-l <<
2553 }; <<
2554 }; <<
2555 }; <<
2556 <<
2557 gpucc: clock-controller@3d900 <<
2558 compatible = "qcom,sc <<
2559 reg = <0 0x03d90000 0 <<
2560 clocks = <&rpmhcc RPM <<
2561 <&gcc GCC_GP <<
2562 <&gcc GCC_GP <<
2563 clock-names = "bi_tcx <<
2564 "gcc_gp <<
2565 "gcc_gp <<
2566 <<
2567 power-domains = <&rpm <<
2568 #clock-cells = <1>; <<
2569 #reset-cells = <1>; <<
2570 #power-domain-cells = <<
2571 }; <<
2572 <<
2573 gpu_smmu: iommu@3da0000 { <<
2574 compatible = "qcom,sc <<
2575 "qcom,sm <<
2576 reg = <0 0x03da0000 0 <<
2577 #iommu-cells = <2>; <<
2578 #global-interrupts = <<
2579 interrupts = <GIC_SPI <<
2580 <GIC_SPI <<
2581 <GIC_SPI <<
2582 <GIC_SPI <<
2583 <GIC_SPI <<
2584 <GIC_SPI <<
2585 <GIC_SPI <<
2586 <GIC_SPI <<
2587 <GIC_SPI <<
2588 <GIC_SPI <<
2589 <GIC_SPI <<
2590 <GIC_SPI <<
2591 <GIC_SPI <<
2592 <GIC_SPI <<
2593 <<
2594 clocks = <&gcc GCC_GP <<
2595 <&gcc GCC_GP <<
2596 <&gpucc GPU_ <<
2597 <&gpucc GPU_ <<
2598 <&gpucc GPU_ <<
2599 <&gpucc GPU_ <<
2600 <&gpucc GPU_ <<
2601 clock-names = "gcc_gp <<
2602 "gcc_gp <<
2603 "gpu_cc <<
2604 "gpu_cc <<
2605 "gpu_cc <<
2606 "gpu_cc <<
2607 "gpu_cc <<
2608 <<
2609 power-domains = <&gpu <<
2610 dma-coherent; <<
2611 }; <<
2612 <<
2613 usb_0_hsphy: phy@88e5000 { 1523 usb_0_hsphy: phy@88e5000 {
2614 compatible = "qcom,sc 1524 compatible = "qcom,sc8280xp-usb-hs-phy",
2615 "qcom,us 1525 "qcom,usb-snps-hs-5nm-phy";
2616 reg = <0 0x088e5000 0 1526 reg = <0 0x088e5000 0 0x400>;
2617 clocks = <&rpmhcc RPM 1527 clocks = <&rpmhcc RPMH_CXO_CLK>;
2618 clock-names = "ref"; 1528 clock-names = "ref";
2619 resets = <&gcc GCC_QU 1529 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2620 1530
2621 #phy-cells = <0>; 1531 #phy-cells = <0>;
2622 1532
2623 status = "disabled"; 1533 status = "disabled";
2624 }; 1534 };
2625 1535
2626 usb_2_hsphy0: phy@88e7000 { 1536 usb_2_hsphy0: phy@88e7000 {
2627 compatible = "qcom,sc 1537 compatible = "qcom,sc8280xp-usb-hs-phy",
2628 "qcom,us 1538 "qcom,usb-snps-hs-5nm-phy";
2629 reg = <0 0x088e7000 0 1539 reg = <0 0x088e7000 0 0x400>;
2630 clocks = <&gcc GCC_US 1540 clocks = <&gcc GCC_USB2_HS0_CLKREF_CLK>;
2631 clock-names = "ref"; 1541 clock-names = "ref";
2632 resets = <&gcc GCC_QU 1542 resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>;
2633 1543
2634 #phy-cells = <0>; 1544 #phy-cells = <0>;
2635 1545
2636 status = "disabled"; 1546 status = "disabled";
2637 }; 1547 };
2638 1548
2639 usb_2_hsphy1: phy@88e8000 { 1549 usb_2_hsphy1: phy@88e8000 {
2640 compatible = "qcom,sc 1550 compatible = "qcom,sc8280xp-usb-hs-phy",
2641 "qcom,us 1551 "qcom,usb-snps-hs-5nm-phy";
2642 reg = <0 0x088e8000 0 1552 reg = <0 0x088e8000 0 0x400>;
2643 clocks = <&gcc GCC_US 1553 clocks = <&gcc GCC_USB2_HS1_CLKREF_CLK>;
2644 clock-names = "ref"; 1554 clock-names = "ref";
2645 resets = <&gcc GCC_QU 1555 resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>;
2646 1556
2647 #phy-cells = <0>; 1557 #phy-cells = <0>;
2648 1558
2649 status = "disabled"; 1559 status = "disabled";
2650 }; 1560 };
2651 1561
2652 usb_2_hsphy2: phy@88e9000 { 1562 usb_2_hsphy2: phy@88e9000 {
2653 compatible = "qcom,sc 1563 compatible = "qcom,sc8280xp-usb-hs-phy",
2654 "qcom,us 1564 "qcom,usb-snps-hs-5nm-phy";
2655 reg = <0 0x088e9000 0 1565 reg = <0 0x088e9000 0 0x400>;
2656 clocks = <&gcc GCC_US 1566 clocks = <&gcc GCC_USB2_HS2_CLKREF_CLK>;
2657 clock-names = "ref"; 1567 clock-names = "ref";
2658 resets = <&gcc GCC_QU 1568 resets = <&gcc GCC_QUSB2PHY_HS2_MP_BCR>;
2659 1569
2660 #phy-cells = <0>; 1570 #phy-cells = <0>;
2661 1571
2662 status = "disabled"; 1572 status = "disabled";
2663 }; 1573 };
2664 1574
2665 usb_2_hsphy3: phy@88ea000 { 1575 usb_2_hsphy3: phy@88ea000 {
2666 compatible = "qcom,sc 1576 compatible = "qcom,sc8280xp-usb-hs-phy",
2667 "qcom,us 1577 "qcom,usb-snps-hs-5nm-phy";
2668 reg = <0 0x088ea000 0 1578 reg = <0 0x088ea000 0 0x400>;
2669 clocks = <&gcc GCC_US 1579 clocks = <&gcc GCC_USB2_HS3_CLKREF_CLK>;
2670 clock-names = "ref"; 1580 clock-names = "ref";
2671 resets = <&gcc GCC_QU 1581 resets = <&gcc GCC_QUSB2PHY_HS3_MP_BCR>;
2672 1582
2673 #phy-cells = <0>; 1583 #phy-cells = <0>;
2674 1584
2675 status = "disabled"; 1585 status = "disabled";
2676 }; 1586 };
2677 1587
2678 usb_2_qmpphy0: phy@88ef000 { 1588 usb_2_qmpphy0: phy@88ef000 {
2679 compatible = "qcom,sc 1589 compatible = "qcom,sc8280xp-qmp-usb3-uni-phy";
2680 reg = <0 0x088ef000 0 1590 reg = <0 0x088ef000 0 0x2000>;
2681 1591
2682 clocks = <&gcc GCC_US 1592 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
2683 <&gcc GCC_US 1593 <&gcc GCC_USB3_MP0_CLKREF_CLK>,
2684 <&gcc GCC_US 1594 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
2685 <&gcc GCC_US 1595 <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>;
2686 clock-names = "aux", 1596 clock-names = "aux", "ref", "com_aux", "pipe";
2687 1597
2688 resets = <&gcc GCC_US 1598 resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>,
2689 <&gcc GCC_US 1599 <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>;
2690 reset-names = "phy", 1600 reset-names = "phy", "phy_phy";
2691 1601
2692 power-domains = <&gcc 1602 power-domains = <&gcc USB30_MP_GDSC>;
2693 1603
2694 #clock-cells = <0>; 1604 #clock-cells = <0>;
2695 clock-output-names = 1605 clock-output-names = "usb2_phy0_pipe_clk";
2696 1606
2697 #phy-cells = <0>; 1607 #phy-cells = <0>;
2698 1608
2699 status = "disabled"; 1609 status = "disabled";
2700 }; 1610 };
2701 1611
2702 usb_2_qmpphy1: phy@88f1000 { 1612 usb_2_qmpphy1: phy@88f1000 {
2703 compatible = "qcom,sc 1613 compatible = "qcom,sc8280xp-qmp-usb3-uni-phy";
2704 reg = <0 0x088f1000 0 1614 reg = <0 0x088f1000 0 0x2000>;
2705 1615
2706 clocks = <&gcc GCC_US 1616 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
2707 <&gcc GCC_US 1617 <&gcc GCC_USB3_MP1_CLKREF_CLK>,
2708 <&gcc GCC_US 1618 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
2709 <&gcc GCC_US 1619 <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>;
2710 clock-names = "aux", 1620 clock-names = "aux", "ref", "com_aux", "pipe";
2711 1621
2712 resets = <&gcc GCC_US 1622 resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>,
2713 <&gcc GCC_US 1623 <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>;
2714 reset-names = "phy", 1624 reset-names = "phy", "phy_phy";
2715 1625
2716 power-domains = <&gcc 1626 power-domains = <&gcc USB30_MP_GDSC>;
2717 1627
2718 #clock-cells = <0>; 1628 #clock-cells = <0>;
2719 clock-output-names = 1629 clock-output-names = "usb2_phy1_pipe_clk";
2720 1630
2721 #phy-cells = <0>; 1631 #phy-cells = <0>;
2722 1632
2723 status = "disabled"; 1633 status = "disabled";
2724 }; 1634 };
2725 1635
2726 remoteproc_adsp: remoteproc@3 1636 remoteproc_adsp: remoteproc@3000000 {
2727 compatible = "qcom,sc 1637 compatible = "qcom,sc8280xp-adsp-pas";
2728 reg = <0 0x03000000 0 1638 reg = <0 0x03000000 0 0x100>;
2729 1639
2730 interrupts-extended = !! 1640 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
2731 1641 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
2732 1642 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
2733 1643 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
2734 1644 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>,
2735 1645 <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>;
2736 interrupt-names = "wd 1646 interrupt-names = "wdog", "fatal", "ready",
2737 "ha 1647 "handover", "stop-ack", "shutdown-ack";
2738 1648
2739 clocks = <&rpmhcc RPM 1649 clocks = <&rpmhcc RPMH_CXO_CLK>;
2740 clock-names = "xo"; 1650 clock-names = "xo";
2741 1651
2742 power-domains = <&rpm 1652 power-domains = <&rpmhpd SC8280XP_LCX>,
2743 <&rpm 1653 <&rpmhpd SC8280XP_LMX>;
2744 power-domain-names = 1654 power-domain-names = "lcx", "lmx";
2745 1655
2746 memory-region = <&pil 1656 memory-region = <&pil_adsp_mem>;
2747 1657
2748 qcom,qmp = <&aoss_qmp 1658 qcom,qmp = <&aoss_qmp>;
2749 1659
2750 qcom,smem-states = <& 1660 qcom,smem-states = <&smp2p_adsp_out 0>;
2751 qcom,smem-state-names 1661 qcom,smem-state-names = "stop";
2752 1662
2753 status = "disabled"; 1663 status = "disabled";
2754 1664
2755 remoteproc_adsp_glink 1665 remoteproc_adsp_glink: glink-edge {
2756 interrupts-ex 1666 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
2757 1667 IPCC_MPROC_SIGNAL_GLINK_QMP
2758 1668 IRQ_TYPE_EDGE_RISING>;
2759 mboxes = <&ip 1669 mboxes = <&ipcc IPCC_CLIENT_LPASS
2760 1670 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2761 1671
2762 label = "lpas 1672 label = "lpass";
2763 qcom,remote-p 1673 qcom,remote-pid = <2>;
2764 <<
2765 gpr { <<
2766 compa <<
2767 qcom, <<
2768 qcom, <<
2769 qcom, <<
2770 #addr <<
2771 #size <<
2772 <<
2773 q6apm <<
2774 <<
2775 <<
2776 <<
2777 <<
2778 <<
2779 <<
2780 <<
2781 <<
2782 <<
2783 <<
2784 <<
2785 <<
2786 <<
2787 <<
2788 }; <<
2789 <<
2790 q6prm <<
2791 <<
2792 <<
2793 <<
2794 <<
2795 <<
2796 <<
2797 <<
2798 <<
2799 }; <<
2800 }; <<
2801 }; <<
2802 }; <<
2803 <<
2804 rxmacro: rxmacro@3200000 { <<
2805 compatible = "qcom,sc <<
2806 reg = <0 0x03200000 0 <<
2807 clocks = <&q6prmcc LP <<
2808 <&q6prmcc LP <<
2809 <&q6prmcc LP <<
2810 <&q6prmcc LP <<
2811 <&vamacro>; <<
2812 clock-names = "mclk", <<
2813 assigned-clocks = <&q <<
2814 <&q <<
2815 assigned-clock-rates <<
2816 <<
2817 clock-output-names = <<
2818 #clock-cells = <0>; <<
2819 #sound-dai-cells = <1 <<
2820 <<
2821 pinctrl-names = "defa <<
2822 pinctrl-0 = <&rx_swr_ <<
2823 <<
2824 status = "disabled"; <<
2825 }; <<
2826 <<
2827 swr1: soundwire@3210000 { <<
2828 compatible = "qcom,so <<
2829 reg = <0 0x03210000 0 <<
2830 interrupts = <GIC_SPI <<
2831 clocks = <&rxmacro>; <<
2832 clock-names = "iface" <<
2833 resets = <&lpass_audi <<
2834 reset-names = "swr_au <<
2835 label = "RX"; <<
2836 <<
2837 qcom,din-ports = <0>; <<
2838 qcom,dout-ports = <5> <<
2839 <<
2840 qcom,ports-sinterval- <<
2841 qcom,ports-offset1 = <<
2842 qcom,ports-offset2 = <<
2843 qcom,ports-hstart = <<
2844 qcom,ports-hstop = <<
2845 qcom,ports-word-lengt <<
2846 qcom,ports-block-pack <<
2847 qcom,ports-lane-contr <<
2848 qcom,ports-block-grou <<
2849 <<
2850 #sound-dai-cells = <1 <<
2851 #address-cells = <2>; <<
2852 #size-cells = <0>; <<
2853 <<
2854 status = "disabled"; <<
2855 }; <<
2856 <<
2857 txmacro: txmacro@3220000 { <<
2858 compatible = "qcom,sc <<
2859 reg = <0 0x03220000 0 <<
2860 pinctrl-names = "defa <<
2861 pinctrl-0 = <&tx_swr_ <<
2862 clocks = <&q6prmcc LP <<
2863 <&q6prmcc LP <<
2864 <&q6prmcc LP <<
2865 <&q6prmcc LP <<
2866 <&vamacro>; <<
2867 <<
2868 clock-names = "mclk", <<
2869 assigned-clocks = <&q <<
2870 <&q <<
2871 assigned-clock-rates <<
2872 clock-output-names = <<
2873 <<
2874 #clock-cells = <0>; <<
2875 #sound-dai-cells = <1 <<
2876 <<
2877 status = "disabled"; <<
2878 }; <<
2879 <<
2880 wsamacro: codec@3240000 { <<
2881 compatible = "qcom,sc <<
2882 reg = <0 0x03240000 0 <<
2883 clocks = <&q6prmcc LP <<
2884 <&q6prmcc LP <<
2885 <&q6prmcc LP <<
2886 <&q6prmcc LP <<
2887 <&vamacro>; <<
2888 clock-names = "mclk", <<
2889 assigned-clocks = <&q <<
2890 <&q <<
2891 assigned-clock-rates <<
2892 <<
2893 #clock-cells = <0>; <<
2894 clock-output-names = <<
2895 #sound-dai-cells = <1 <<
2896 <<
2897 pinctrl-names = "defa <<
2898 pinctrl-0 = <&wsa_swr <<
2899 <<
2900 status = "disabled"; <<
2901 }; <<
2902 <<
2903 swr0: soundwire@3250000 { <<
2904 reg = <0 0x03250000 0 <<
2905 compatible = "qcom,so <<
2906 interrupts = <GIC_SPI <<
2907 clocks = <&wsamacro>; <<
2908 clock-names = "iface" <<
2909 resets = <&lpass_audi <<
2910 reset-names = "swr_au <<
2911 label = "WSA"; <<
2912 <<
2913 qcom,din-ports = <2>; <<
2914 qcom,dout-ports = <6> <<
2915 <<
2916 qcom,ports-sinterval- <<
2917 qcom,ports-offset1 = <<
2918 qcom,ports-offset2 = <<
2919 qcom,ports-hstart = <<
2920 qcom,ports-hstop = <<
2921 qcom,ports-word-lengt <<
2922 qcom,ports-block-pack <<
2923 qcom,ports-block-grou <<
2924 qcom,ports-lane-contr <<
2925 <<
2926 #sound-dai-cells = <1 <<
2927 #address-cells = <2>; <<
2928 #size-cells = <0>; <<
2929 <<
2930 status = "disabled"; <<
2931 }; <<
2932 <<
2933 lpass_audiocc: clock-controll <<
2934 compatible = "qcom,sc <<
2935 reg = <0 0x032a9000 0 <<
2936 #clock-cells = <1>; <<
2937 #reset-cells = <1>; <<
2938 }; <<
2939 <<
2940 swr2: soundwire@3330000 { <<
2941 compatible = "qcom,so <<
2942 reg = <0 0x03330000 0 <<
2943 interrupts = <GIC_SPI <<
2944 <GIC_SPI <<
2945 interrupt-names = "co <<
2946 <<
2947 clocks = <&txmacro>; <<
2948 clock-names = "iface" <<
2949 resets = <&lpasscc LP <<
2950 reset-names = "swr_au <<
2951 label = "TX"; <<
2952 #sound-dai-cells = <1 <<
2953 #address-cells = <2>; <<
2954 #size-cells = <0>; <<
2955 <<
2956 qcom,din-ports = <4>; <<
2957 qcom,dout-ports = <0> <<
2958 qcom,ports-sinterval- <<
2959 qcom,ports-offset1 = <<
2960 qcom,ports-offset2 = <<
2961 qcom,ports-block-pack <<
2962 qcom,ports-hstart = <<
2963 qcom,ports-hstop = <<
2964 qcom,ports-word-lengt <<
2965 qcom,ports-block-grou <<
2966 qcom,ports-lane-contr <<
2967 <<
2968 status = "disabled"; <<
2969 }; <<
2970 <<
2971 vamacro: codec@3370000 { <<
2972 compatible = "qcom,sc <<
2973 reg = <0 0x03370000 0 <<
2974 clocks = <&q6prmcc LP <<
2975 <&q6prmcc LP <<
2976 <&q6prmcc LP <<
2977 <&q6prmcc LP <<
2978 clock-names = "mclk", <<
2979 assigned-clocks = <&q <<
2980 assigned-clock-rates <<
2981 <<
2982 #clock-cells = <0>; <<
2983 clock-output-names = <<
2984 #sound-dai-cells = <1 <<
2985 <<
2986 status = "disabled"; <<
2987 }; <<
2988 <<
2989 lpass_tlmm: pinctrl@33c0000 { <<
2990 compatible = "qcom,sc <<
2991 reg = <0 0x33c0000 0x <<
2992 <0 0x3550000 0x <<
2993 gpio-controller; <<
2994 #gpio-cells = <2>; <<
2995 gpio-ranges = <&lpass <<
2996 <<
2997 clocks = <&q6prmcc LP <<
2998 <&q6prmcc LP <<
2999 clock-names = "core", <<
3000 <<
3001 status = "disabled"; <<
3002 <<
3003 tx_swr_default: tx-sw <<
3004 clk-pins { <<
3005 pins <<
3006 funct <<
3007 drive <<
3008 slew- <<
3009 bias- <<
3010 }; <<
3011 <<
3012 data-pins { <<
3013 pins <<
3014 funct <<
3015 drive <<
3016 slew- <<
3017 bias- <<
3018 }; <<
3019 }; <<
3020 <<
3021 rx_swr_default: rx-sw <<
3022 clk-pins { <<
3023 pins <<
3024 funct <<
3025 drive <<
3026 slew- <<
3027 bias- <<
3028 }; <<
3029 <<
3030 data-pins { <<
3031 pins <<
3032 funct <<
3033 drive <<
3034 slew- <<
3035 bias- <<
3036 }; <<
3037 }; <<
3038 <<
3039 dmic01_default: dmic0 <<
3040 clk-pins { <<
3041 pins <<
3042 funct <<
3043 drive <<
3044 outpu <<
3045 }; <<
3046 <<
3047 data-pins { <<
3048 pins <<
3049 funct <<
3050 drive <<
3051 input <<
3052 }; <<
3053 }; <<
3054 <<
3055 dmic01_sleep: dmic01- <<
3056 clk-pins { <<
3057 pins <<
3058 funct <<
3059 drive <<
3060 bias- <<
3061 outpu <<
3062 }; <<
3063 <<
3064 data-pins { <<
3065 pins <<
3066 funct <<
3067 drive <<
3068 bias- <<
3069 input <<
3070 }; <<
3071 }; <<
3072 <<
3073 dmic23_default: dmic2 <<
3074 clk-pins { <<
3075 pins <<
3076 funct <<
3077 drive <<
3078 outpu <<
3079 }; <<
3080 <<
3081 data-pins { <<
3082 pins <<
3083 funct <<
3084 drive <<
3085 input <<
3086 }; <<
3087 }; <<
3088 <<
3089 dmic23_sleep: dmic23- <<
3090 clk-pins { <<
3091 pins <<
3092 funct <<
3093 drive <<
3094 bias- <<
3095 outpu <<
3096 }; <<
3097 <<
3098 data-pins { <<
3099 pins <<
3100 funct <<
3101 drive <<
3102 bias- <<
3103 input <<
3104 }; <<
3105 }; <<
3106 <<
3107 wsa_swr_default: wsa- <<
3108 clk-pins { <<
3109 pins <<
3110 funct <<
3111 drive <<
3112 slew- <<
3113 bias- <<
3114 }; <<
3115 <<
3116 data-pins { <<
3117 pins <<
3118 funct <<
3119 drive <<
3120 slew- <<
3121 bias- <<
3122 }; <<
3123 }; <<
3124 <<
3125 wsa2_swr_default: wsa <<
3126 clk-pins { <<
3127 pins <<
3128 funct <<
3129 drive <<
3130 slew- <<
3131 bias- <<
3132 }; <<
3133 <<
3134 data-pins { <<
3135 pins <<
3136 funct <<
3137 drive <<
3138 slew- <<
3139 bias- <<
3140 }; <<
3141 }; <<
3142 }; <<
3143 <<
3144 lpasscc: clock-controller@33e <<
3145 compatible = "qcom,sc <<
3146 reg = <0 0x033e0000 0 <<
3147 #clock-cells = <1>; <<
3148 #reset-cells = <1>; <<
3149 }; <<
3150 <<
3151 sdc2: mmc@8804000 { <<
3152 compatible = "qcom,sc <<
3153 reg = <0 0x08804000 0 <<
3154 <<
3155 interrupts = <GIC_SPI <<
3156 <GIC_SPI <<
3157 interrupt-names = "hc <<
3158 <<
3159 clocks = <&gcc GCC_SD <<
3160 <&gcc GCC_SD <<
3161 <&rpmhcc RPM <<
3162 clock-names = "iface" <<
3163 resets = <&gcc GCC_SD <<
3164 interconnects = <&agg <<
3165 <&gem <<
3166 interconnect-names = <<
3167 iommus = <&apps_smmu <<
3168 power-domains = <&rpm <<
3169 operating-points-v2 = <<
3170 bus-width = <4>; <<
3171 dma-coherent; <<
3172 <<
3173 status = "disabled"; <<
3174 <<
3175 sdc2_opp_table: opp-t <<
3176 compatible = <<
3177 <<
3178 opp-100000000 <<
3179 opp-h <<
3180 requi <<
3181 opp-p <<
3182 opp-a <<
3183 }; <<
3184 <<
3185 opp-202000000 <<
3186 opp-h <<
3187 requi <<
3188 opp-p <<
3189 opp-a <<
3190 }; <<
3191 }; 1674 };
3192 }; 1675 };
3193 1676
3194 usb_0_qmpphy: phy@88eb000 { 1677 usb_0_qmpphy: phy@88eb000 {
3195 compatible = "qcom,sc 1678 compatible = "qcom,sc8280xp-qmp-usb43dp-phy";
3196 reg = <0 0x088eb000 0 1679 reg = <0 0x088eb000 0 0x4000>;
3197 1680
3198 clocks = <&gcc GCC_US 1681 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
3199 <&gcc GCC_US 1682 <&gcc GCC_USB4_EUD_CLKREF_CLK>,
3200 <&gcc GCC_US 1683 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
3201 <&gcc GCC_US 1684 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3202 clock-names = "aux", 1685 clock-names = "aux", "ref", "com_aux", "usb3_pipe";
3203 1686
3204 power-domains = <&gcc 1687 power-domains = <&gcc USB30_PRIM_GDSC>;
3205 1688
3206 resets = <&gcc GCC_US 1689 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
3207 <&gcc GCC_US 1690 <&gcc GCC_USB4_DP_PHY_PRIM_BCR>;
3208 reset-names = "phy", 1691 reset-names = "phy", "common";
3209 1692
3210 #clock-cells = <1>; 1693 #clock-cells = <1>;
3211 #phy-cells = <1>; 1694 #phy-cells = <1>;
3212 1695
3213 status = "disabled"; 1696 status = "disabled";
3214 <<
3215 ports { <<
3216 #address-cell <<
3217 #size-cells = <<
3218 <<
3219 port@0 { <<
3220 reg = <<
3221 <<
3222 usb_0 <<
3223 }; <<
3224 <<
3225 port@1 { <<
3226 reg = <<
3227 <<
3228 usb_0 <<
3229 <<
3230 }; <<
3231 }; <<
3232 <<
3233 port@2 { <<
3234 reg = <<
3235 <<
3236 usb_0 <<
3237 }; <<
3238 }; <<
3239 }; 1697 };
3240 1698
3241 usb_1_hsphy: phy@8902000 { 1699 usb_1_hsphy: phy@8902000 {
3242 compatible = "qcom,sc 1700 compatible = "qcom,sc8280xp-usb-hs-phy",
3243 "qcom,us 1701 "qcom,usb-snps-hs-5nm-phy";
3244 reg = <0 0x08902000 0 1702 reg = <0 0x08902000 0 0x400>;
3245 #phy-cells = <0>; 1703 #phy-cells = <0>;
3246 1704
3247 clocks = <&rpmhcc RPM 1705 clocks = <&rpmhcc RPMH_CXO_CLK>;
3248 clock-names = "ref"; 1706 clock-names = "ref";
3249 1707
3250 resets = <&gcc GCC_QU 1708 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3251 1709
3252 status = "disabled"; 1710 status = "disabled";
3253 }; 1711 };
3254 1712
3255 usb_1_qmpphy: phy@8903000 { 1713 usb_1_qmpphy: phy@8903000 {
3256 compatible = "qcom,sc 1714 compatible = "qcom,sc8280xp-qmp-usb43dp-phy";
3257 reg = <0 0x08903000 0 1715 reg = <0 0x08903000 0 0x4000>;
3258 1716
3259 clocks = <&gcc GCC_US 1717 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
3260 <&gcc GCC_US 1718 <&gcc GCC_USB4_CLKREF_CLK>,
3261 <&gcc GCC_US 1719 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
3262 <&gcc GCC_US 1720 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
3263 clock-names = "aux", 1721 clock-names = "aux", "ref", "com_aux", "usb3_pipe";
3264 1722
3265 power-domains = <&gcc 1723 power-domains = <&gcc USB30_SEC_GDSC>;
3266 1724
3267 resets = <&gcc GCC_US 1725 resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
3268 <&gcc GCC_US 1726 <&gcc GCC_USB4_1_DP_PHY_PRIM_BCR>;
3269 reset-names = "phy", 1727 reset-names = "phy", "common";
3270 1728
3271 #clock-cells = <1>; 1729 #clock-cells = <1>;
3272 #phy-cells = <1>; 1730 #phy-cells = <1>;
3273 1731
3274 status = "disabled"; 1732 status = "disabled";
3275 <<
3276 ports { <<
3277 #address-cell <<
3278 #size-cells = <<
3279 <<
3280 port@0 { <<
3281 reg = <<
3282 <<
3283 usb_1 <<
3284 }; <<
3285 <<
3286 port@1 { <<
3287 reg = <<
3288 <<
3289 usb_1 <<
3290 <<
3291 }; <<
3292 }; <<
3293 <<
3294 port@2 { <<
3295 reg = <<
3296 <<
3297 usb_1 <<
3298 }; <<
3299 }; <<
3300 }; <<
3301 <<
3302 mdss1_dp0_phy: phy@8909a00 { <<
3303 compatible = "qcom,sc <<
3304 reg = <0 0x08909a00 0 <<
3305 <0 0x08909200 0 <<
3306 <0 0x08909600 0 <<
3307 <0 0x08909000 0 <<
3308 <<
3309 clocks = <&dispcc1 DI <<
3310 <&dispcc1 DI <<
3311 clock-names = "aux", <<
3312 power-domains = <&rpm <<
3313 <<
3314 #clock-cells = <1>; <<
3315 #phy-cells = <0>; <<
3316 <<
3317 status = "disabled"; <<
3318 }; <<
3319 <<
3320 mdss1_dp1_phy: phy@890ca00 { <<
3321 compatible = "qcom,sc <<
3322 reg = <0 0x0890ca00 0 <<
3323 <0 0x0890c200 0 <<
3324 <0 0x0890c600 0 <<
3325 <0 0x0890c000 0 <<
3326 <<
3327 clocks = <&dispcc1 DI <<
3328 <&dispcc1 DI <<
3329 clock-names = "aux", <<
3330 power-domains = <&rpm <<
3331 <<
3332 #clock-cells = <1>; <<
3333 #phy-cells = <0>; <<
3334 <<
3335 status = "disabled"; <<
3336 }; 1733 };
3337 1734
3338 pmu@9091000 { 1735 pmu@9091000 {
3339 compatible = "qcom,sc 1736 compatible = "qcom,sc8280xp-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
3340 reg = <0 0x09091000 0 !! 1737 reg = <0 0x9091000 0 0x1000>;
3341 1738
3342 interrupts = <GIC_SPI 1739 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
3343 1740
3344 interconnects = <&mc_ 1741 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>;
3345 1742
3346 operating-points-v2 = 1743 operating-points-v2 = <&llcc_bwmon_opp_table>;
3347 1744
3348 llcc_bwmon_opp_table: 1745 llcc_bwmon_opp_table: opp-table {
3349 compatible = 1746 compatible = "operating-points-v2";
3350 1747
3351 opp-0 { 1748 opp-0 {
3352 opp-p 1749 opp-peak-kBps = <762000>;
3353 }; 1750 };
3354 opp-1 { 1751 opp-1 {
3355 opp-p 1752 opp-peak-kBps = <1720000>;
3356 }; 1753 };
3357 opp-2 { 1754 opp-2 {
3358 opp-p 1755 opp-peak-kBps = <2086000>;
3359 }; 1756 };
3360 opp-3 { 1757 opp-3 {
3361 opp-p 1758 opp-peak-kBps = <2597000>;
3362 }; 1759 };
3363 opp-4 { 1760 opp-4 {
3364 opp-p 1761 opp-peak-kBps = <2929000>;
3365 }; 1762 };
3366 opp-5 { 1763 opp-5 {
3367 opp-p 1764 opp-peak-kBps = <3879000>;
3368 }; 1765 };
3369 opp-6 { 1766 opp-6 {
3370 opp-p 1767 opp-peak-kBps = <5161000>;
3371 }; 1768 };
3372 opp-7 { 1769 opp-7 {
3373 opp-p 1770 opp-peak-kBps = <5931000>;
3374 }; 1771 };
3375 opp-8 { 1772 opp-8 {
3376 opp-p 1773 opp-peak-kBps = <6515000>;
3377 }; 1774 };
3378 opp-9 { 1775 opp-9 {
3379 opp-p 1776 opp-peak-kBps = <7980000>;
3380 }; 1777 };
3381 opp-10 { 1778 opp-10 {
3382 opp-p 1779 opp-peak-kBps = <8136000>;
3383 }; 1780 };
3384 opp-11 { 1781 opp-11 {
3385 opp-p 1782 opp-peak-kBps = <10437000>;
3386 }; 1783 };
3387 opp-12 { 1784 opp-12 {
3388 opp-p 1785 opp-peak-kBps = <12191000>;
3389 }; 1786 };
3390 }; 1787 };
3391 }; 1788 };
3392 1789
3393 pmu@90b6400 { 1790 pmu@90b6400 {
3394 compatible = "qcom,sc !! 1791 compatible = "qcom,sc8280xp-cpu-bwmon", "qcom,msm8998-bwmon";
3395 reg = <0 0x090b6400 0 1792 reg = <0 0x090b6400 0 0x600>;
3396 1793
3397 interrupts = <GIC_SPI 1794 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
3398 1795
3399 interconnects = <&gem 1796 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>;
3400 operating-points-v2 = 1797 operating-points-v2 = <&cpu_bwmon_opp_table>;
3401 1798
3402 cpu_bwmon_opp_table: 1799 cpu_bwmon_opp_table: opp-table {
3403 compatible = 1800 compatible = "operating-points-v2";
3404 1801
3405 opp-0 { 1802 opp-0 {
3406 opp-p 1803 opp-peak-kBps = <2288000>;
3407 }; 1804 };
3408 opp-1 { 1805 opp-1 {
3409 opp-p 1806 opp-peak-kBps = <4577000>;
3410 }; 1807 };
3411 opp-2 { 1808 opp-2 {
3412 opp-p 1809 opp-peak-kBps = <7110000>;
3413 }; 1810 };
3414 opp-3 { 1811 opp-3 {
3415 opp-p 1812 opp-peak-kBps = <9155000>;
3416 }; 1813 };
3417 opp-4 { 1814 opp-4 {
3418 opp-p 1815 opp-peak-kBps = <12298000>;
3419 }; 1816 };
3420 opp-5 { 1817 opp-5 {
3421 opp-p 1818 opp-peak-kBps = <14236000>;
3422 }; 1819 };
3423 opp-6 { 1820 opp-6 {
3424 opp-p 1821 opp-peak-kBps = <15258001>;
3425 }; 1822 };
3426 }; 1823 };
3427 }; 1824 };
3428 1825
3429 system-cache-controller@92000 1826 system-cache-controller@9200000 {
3430 compatible = "qcom,sc 1827 compatible = "qcom,sc8280xp-llcc";
3431 reg = <0 0x09200000 0 !! 1828 reg = <0 0x09200000 0 0x58000>, <0 0x09600000 0 0x58000>;
3432 <0 0x09300000 0 !! 1829 reg-names = "llcc_base", "llcc_broadcast_base";
3433 <0 0x09400000 0 <<
3434 <0 0x09500000 0 <<
3435 <0 0x09600000 0 <<
3436 reg-names = "llcc0_ba <<
3437 "llcc3_ba <<
3438 "llcc6_ba <<
3439 interrupts = <GIC_SPI 1830 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
3440 }; 1831 };
3441 1832
3442 usb_2: usb@a4f8800 { <<
3443 compatible = "qcom,sc <<
3444 reg = <0 0x0a4f8800 0 <<
3445 #address-cells = <2>; <<
3446 #size-cells = <2>; <<
3447 ranges; <<
3448 <<
3449 clocks = <&gcc GCC_CF <<
3450 <&gcc GCC_US <<
3451 <&gcc GCC_AG <<
3452 <&gcc GCC_US <<
3453 <&gcc GCC_US <<
3454 <&gcc GCC_AG <<
3455 <&gcc GCC_AG <<
3456 <&gcc GCC_AG <<
3457 <&gcc GCC_SY <<
3458 clock-names = "cfg_no <<
3459 "noc_ag <<
3460 <<
3461 assigned-clocks = <&g <<
3462 <&g <<
3463 assigned-clock-rates <<
3464 <<
3465 interrupts-extended = <<
3466 <<
3467 <<
3468 <<
3469 <<
3470 <<
3471 <<
3472 <<
3473 <<
3474 <<
3475 <<
3476 <<
3477 <<
3478 <<
3479 <<
3480 <<
3481 <<
3482 <<
3483 <<
3484 interrupt-names = "pw <<
3485 "pw <<
3486 "hs <<
3487 "hs <<
3488 "dp <<
3489 "dp <<
3490 "dp <<
3491 "dp <<
3492 "ss <<
3493 <<
3494 power-domains = <&gcc <<
3495 required-opps = <&rpm <<
3496 <<
3497 resets = <&gcc GCC_US <<
3498 <<
3499 interconnects = <&agg <<
3500 <&gem <<
3501 interconnect-names = <<
3502 <<
3503 wakeup-source; <<
3504 <<
3505 status = "disabled"; <<
3506 <<
3507 usb_2_dwc3: usb@a4000 <<
3508 compatible = <<
3509 reg = <0 0x0a <<
3510 interrupts = <<
3511 iommus = <&ap <<
3512 phys = <&usb_ <<
3513 <&usb_ <<
3514 <&usb_ <<
3515 <&usb_ <<
3516 phy-names = " <<
3517 " <<
3518 " <<
3519 " <<
3520 dr_mode = "ho <<
3521 }; <<
3522 }; <<
3523 <<
3524 usb_0: usb@a6f8800 { 1833 usb_0: usb@a6f8800 {
3525 compatible = "qcom,sc 1834 compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3";
3526 reg = <0 0x0a6f8800 0 1835 reg = <0 0x0a6f8800 0 0x400>;
3527 #address-cells = <2>; 1836 #address-cells = <2>;
3528 #size-cells = <2>; 1837 #size-cells = <2>;
3529 ranges; 1838 ranges;
3530 1839
3531 clocks = <&gcc GCC_CF 1840 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
3532 <&gcc GCC_US 1841 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
3533 <&gcc GCC_AG 1842 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
3534 <&gcc GCC_US 1843 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
3535 <&gcc GCC_US 1844 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3536 <&gcc GCC_AG 1845 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
3537 <&gcc GCC_AG 1846 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>,
3538 <&gcc GCC_AG 1847 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>,
3539 <&gcc GCC_SY 1848 <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
3540 clock-names = "cfg_no 1849 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi",
3541 "noc_ag 1850 "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys";
3542 1851
3543 assigned-clocks = <&g 1852 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3544 <&g 1853 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
3545 assigned-clock-rates 1854 assigned-clock-rates = <19200000>, <200000000>;
3546 1855
3547 interrupts-extended = 1856 interrupts-extended = <&intc GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>,
3548 <<
3549 1857 <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
3550 1858 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
3551 1859 <&pdc 138 IRQ_TYPE_LEVEL_HIGH>;
3552 interrupt-names = "pw 1860 interrupt-names = "pwr_event",
3553 "hs <<
3554 "dp 1861 "dp_hs_phy_irq",
3555 "dm 1862 "dm_hs_phy_irq",
3556 "ss 1863 "ss_phy_irq";
3557 1864
3558 power-domains = <&gcc 1865 power-domains = <&gcc USB30_PRIM_GDSC>;
3559 required-opps = <&rpm 1866 required-opps = <&rpmhpd_opp_nom>;
3560 1867
3561 resets = <&gcc GCC_US 1868 resets = <&gcc GCC_USB30_PRIM_BCR>;
3562 1869
3563 interconnects = <&agg 1870 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
3564 <&gem 1871 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
3565 interconnect-names = 1872 interconnect-names = "usb-ddr", "apps-usb";
3566 1873
3567 wakeup-source; 1874 wakeup-source;
3568 1875
3569 status = "disabled"; 1876 status = "disabled";
3570 1877
3571 usb_0_dwc3: usb@a6000 1878 usb_0_dwc3: usb@a600000 {
3572 compatible = 1879 compatible = "snps,dwc3";
3573 reg = <0 0x0a 1880 reg = <0 0x0a600000 0 0xcd00>;
3574 interrupts = 1881 interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>;
3575 iommus = <&ap 1882 iommus = <&apps_smmu 0x820 0x0>;
3576 phys = <&usb_ 1883 phys = <&usb_0_hsphy>, <&usb_0_qmpphy QMP_USB43DP_USB3_PHY>;
3577 phy-names = " 1884 phy-names = "usb2-phy", "usb3-phy";
3578 <<
3579 ports { <<
3580 #addr <<
3581 #size <<
3582 <<
3583 port@ <<
3584 <<
3585 <<
3586 <<
3587 <<
3588 }; <<
3589 <<
3590 port@ <<
3591 <<
3592 <<
3593 <<
3594 <<
3595 <<
3596 }; <<
3597 }; <<
3598 }; 1885 };
3599 }; 1886 };
3600 1887
3601 usb_1: usb@a8f8800 { 1888 usb_1: usb@a8f8800 {
3602 compatible = "qcom,sc 1889 compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3";
3603 reg = <0 0x0a8f8800 0 1890 reg = <0 0x0a8f8800 0 0x400>;
3604 #address-cells = <2>; 1891 #address-cells = <2>;
3605 #size-cells = <2>; 1892 #size-cells = <2>;
3606 ranges; 1893 ranges;
3607 1894
3608 clocks = <&gcc GCC_CF 1895 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
3609 <&gcc GCC_US 1896 <&gcc GCC_USB30_SEC_MASTER_CLK>,
3610 <&gcc GCC_AG 1897 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
3611 <&gcc GCC_US 1898 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
3612 <&gcc GCC_US 1899 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3613 <&gcc GCC_AG 1900 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
3614 <&gcc GCC_AG 1901 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>,
3615 <&gcc GCC_AG 1902 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>,
3616 <&gcc GCC_SY 1903 <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
3617 clock-names = "cfg_no 1904 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi",
3618 "noc_ag 1905 "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys";
3619 1906
3620 assigned-clocks = <&g 1907 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3621 <&g 1908 <&gcc GCC_USB30_SEC_MASTER_CLK>;
3622 assigned-clock-rates 1909 assigned-clock-rates = <19200000>, <200000000>;
3623 1910
3624 interrupts-extended = 1911 interrupts-extended = <&intc GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>,
3625 <<
3626 1912 <&pdc 12 IRQ_TYPE_EDGE_BOTH>,
3627 1913 <&pdc 13 IRQ_TYPE_EDGE_BOTH>,
3628 1914 <&pdc 136 IRQ_TYPE_LEVEL_HIGH>;
3629 interrupt-names = "pw 1915 interrupt-names = "pwr_event",
3630 "hs <<
3631 "dp 1916 "dp_hs_phy_irq",
3632 "dm 1917 "dm_hs_phy_irq",
3633 "ss 1918 "ss_phy_irq";
3634 1919
3635 power-domains = <&gcc 1920 power-domains = <&gcc USB30_SEC_GDSC>;
3636 required-opps = <&rpm 1921 required-opps = <&rpmhpd_opp_nom>;
3637 1922
3638 resets = <&gcc GCC_US 1923 resets = <&gcc GCC_USB30_SEC_BCR>;
3639 1924
3640 interconnects = <&agg 1925 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>,
3641 <&gem 1926 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
3642 interconnect-names = 1927 interconnect-names = "usb-ddr", "apps-usb";
3643 1928
3644 wakeup-source; 1929 wakeup-source;
3645 1930
3646 status = "disabled"; 1931 status = "disabled";
3647 1932
3648 usb_1_dwc3: usb@a8000 1933 usb_1_dwc3: usb@a800000 {
3649 compatible = 1934 compatible = "snps,dwc3";
3650 reg = <0 0x0a 1935 reg = <0 0x0a800000 0 0xcd00>;
3651 interrupts = 1936 interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>;
3652 iommus = <&ap 1937 iommus = <&apps_smmu 0x860 0x0>;
3653 phys = <&usb_ 1938 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
3654 phy-names = " 1939 phy-names = "usb2-phy", "usb3-phy";
3655 <<
3656 ports { <<
3657 #addr <<
3658 #size <<
3659 <<
3660 port@ <<
3661 <<
3662 <<
3663 <<
3664 <<
3665 }; <<
3666 <<
3667 port@ <<
3668 <<
3669 <<
3670 <<
3671 <<
3672 <<
3673 }; <<
3674 }; <<
3675 }; <<
3676 }; <<
3677 <<
3678 cci0: cci@ac4a000 { <<
3679 compatible = "qcom,sc <<
3680 reg = <0 0x0ac4a000 0 <<
3681 <<
3682 interrupts = <GIC_SPI <<
3683 <<
3684 clocks = <&camcc CAMC <<
3685 <&camcc CAMC <<
3686 <&camcc CAMC <<
3687 <&camcc CAMC <<
3688 clock-names = "camnoc <<
3689 "slow_a <<
3690 "cpas_a <<
3691 "cci"; <<
3692 <<
3693 power-domains = <&cam <<
3694 <<
3695 pinctrl-0 = <&cci0_de <<
3696 pinctrl-1 = <&cci0_sl <<
3697 pinctrl-names = "defa <<
3698 <<
3699 #address-cells = <1>; <<
3700 #size-cells = <0>; <<
3701 <<
3702 status = "disabled"; <<
3703 <<
3704 cci0_i2c0: i2c-bus@0 <<
3705 reg = <0>; <<
3706 clock-frequen <<
3707 #address-cell <<
3708 #size-cells = <<
3709 }; <<
3710 <<
3711 cci0_i2c1: i2c-bus@1 <<
3712 reg = <1>; <<
3713 clock-frequen <<
3714 #address-cell <<
3715 #size-cells = <<
3716 }; <<
3717 }; <<
3718 <<
3719 cci1: cci@ac4b000 { <<
3720 compatible = "qcom,sc <<
3721 reg = <0 0x0ac4b000 0 <<
3722 <<
3723 interrupts = <GIC_SPI <<
3724 <<
3725 clocks = <&camcc CAMC <<
3726 <&camcc CAMC <<
3727 <&camcc CAMC <<
3728 <&camcc CAMC <<
3729 clock-names = "camnoc <<
3730 "slow_a <<
3731 "cpas_a <<
3732 "cci"; <<
3733 <<
3734 power-domains = <&cam <<
3735 <<
3736 pinctrl-0 = <&cci1_de <<
3737 pinctrl-1 = <&cci1_sl <<
3738 pinctrl-names = "defa <<
3739 <<
3740 #address-cells = <1>; <<
3741 #size-cells = <0>; <<
3742 <<
3743 status = "disabled"; <<
3744 <<
3745 cci1_i2c0: i2c-bus@0 <<
3746 reg = <0>; <<
3747 clock-frequen <<
3748 #address-cell <<
3749 #size-cells = <<
3750 }; <<
3751 <<
3752 cci1_i2c1: i2c-bus@1 <<
3753 reg = <1>; <<
3754 clock-frequen <<
3755 #address-cell <<
3756 #size-cells = <<
3757 }; <<
3758 }; <<
3759 <<
3760 cci2: cci@ac4c000 { <<
3761 compatible = "qcom,sc <<
3762 reg = <0 0x0ac4c000 0 <<
3763 <<
3764 interrupts = <GIC_SPI <<
3765 <<
3766 clocks = <&camcc CAMC <<
3767 <&camcc CAMC <<
3768 <&camcc CAMC <<
3769 <&camcc CAMC <<
3770 clock-names = "camnoc <<
3771 "slow_a <<
3772 "cpas_a <<
3773 "cci"; <<
3774 power-domains = <&cam <<
3775 <<
3776 pinctrl-0 = <&cci2_de <<
3777 pinctrl-1 = <&cci2_sl <<
3778 pinctrl-names = "defa <<
3779 <<
3780 #address-cells = <1>; <<
3781 #size-cells = <0>; <<
3782 <<
3783 status = "disabled"; <<
3784 <<
3785 cci2_i2c0: i2c-bus@0 <<
3786 reg = <0>; <<
3787 clock-frequen <<
3788 #address-cell <<
3789 #size-cells = <<
3790 }; <<
3791 <<
3792 cci2_i2c1: i2c-bus@1 <<
3793 reg = <1>; <<
3794 clock-frequen <<
3795 #address-cell <<
3796 #size-cells = <<
3797 }; <<
3798 }; <<
3799 <<
3800 cci3: cci@ac4d000 { <<
3801 compatible = "qcom,sc <<
3802 reg = <0 0x0ac4d000 0 <<
3803 <<
3804 interrupts = <GIC_SPI <<
3805 <<
3806 clocks = <&camcc CAMC <<
3807 <&camcc CAMC <<
3808 <&camcc CAMC <<
3809 <&camcc CAMC <<
3810 clock-names = "camnoc <<
3811 "slow_a <<
3812 "cpas_a <<
3813 "cci"; <<
3814 <<
3815 power-domains = <&cam <<
3816 <<
3817 pinctrl-0 = <&cci3_de <<
3818 pinctrl-1 = <&cci3_sl <<
3819 pinctrl-names = "defa <<
3820 <<
3821 #address-cells = <1>; <<
3822 #size-cells = <0>; <<
3823 <<
3824 status = "disabled"; <<
3825 <<
3826 cci3_i2c0: i2c-bus@0 <<
3827 reg = <0>; <<
3828 clock-frequen <<
3829 #address-cell <<
3830 #size-cells = <<
3831 }; <<
3832 <<
3833 cci3_i2c1: i2c-bus@1 <<
3834 reg = <1>; <<
3835 clock-frequen <<
3836 #address-cell <<
3837 #size-cells = <<
3838 }; <<
3839 }; <<
3840 <<
3841 camss: camss@ac5a000 { <<
3842 compatible = "qcom,sc <<
3843 <<
3844 reg = <0 0x0ac5a000 0 <<
3845 <0 0x0ac5c000 0 <<
3846 <0 0x0ac65000 0 <<
3847 <0 0x0ac67000 0 <<
3848 <0 0x0acaf000 0 <<
3849 <0 0x0acb3000 0 <<
3850 <0 0x0acb6000 0 <<
3851 <0 0x0acba000 0 <<
3852 <0 0x0acbd000 0 <<
3853 <0 0x0acc1000 0 <<
3854 <0 0x0acc4000 0 <<
3855 <0 0x0acc8000 0 <<
3856 <0 0x0accb000 0 <<
3857 <0 0x0accf000 0 <<
3858 <0 0x0acd2000 0 <<
3859 <0 0x0acd6000 0 <<
3860 <0 0x0acd9000 0 <<
3861 <0 0x0acdd000 0 <<
3862 <0 0x0ace0000 0 <<
3863 <0 0x0ace4000 0 <<
3864 reg-names = "csiphy2" <<
3865 "csiphy3" <<
3866 "csiphy0" <<
3867 "csiphy1" <<
3868 "vfe0", <<
3869 "csid0", <<
3870 "vfe1", <<
3871 "csid1", <<
3872 "vfe2", <<
3873 "csid2", <<
3874 "vfe_lite <<
3875 "csid0_li <<
3876 "vfe_lite <<
3877 "csid1_li <<
3878 "vfe_lite <<
3879 "csid2_li <<
3880 "vfe_lite <<
3881 "csid3_li <<
3882 "vfe3", <<
3883 "csid3"; <<
3884 <<
3885 interrupts = <GIC_SPI <<
3886 <GIC_SPI <<
3887 <GIC_SPI <<
3888 <GIC_SPI <<
3889 <GIC_SPI <<
3890 <GIC_SPI <<
3891 <GIC_SPI <<
3892 <GIC_SPI <<
3893 <GIC_SPI <<
3894 <GIC_SPI <<
3895 <GIC_SPI <<
3896 <GIC_SPI <<
3897 <GIC_SPI <<
3898 <GIC_SPI <<
3899 <GIC_SPI <<
3900 <GIC_SPI <<
3901 <GIC_SPI <<
3902 <GIC_SPI <<
3903 <GIC_SPI <<
3904 <GIC_SPI <<
3905 interrupt-names = "cs <<
3906 "vf <<
3907 "cs <<
3908 "cs <<
3909 "vf <<
3910 "cs <<
3911 "vf <<
3912 "cs <<
3913 "vf <<
3914 "cs <<
3915 "cs <<
3916 "cs <<
3917 "cs <<
3918 "vf <<
3919 "cs <<
3920 "cs <<
3921 "vf <<
3922 "vf <<
3923 "cs <<
3924 "vf <<
3925 <<
3926 power-domains = <&cam <<
3927 <&cam <<
3928 <&cam <<
3929 <&cam <<
3930 <&cam <<
3931 power-domain-names = <<
3932 <<
3933 <<
3934 <<
3935 <<
3936 <<
3937 clocks = <&camcc CAMC <<
3938 <&camcc CAMC <<
3939 <&camcc CAMC <<
3940 <&camcc CAMC <<
3941 <&camcc CAMC <<
3942 <&camcc CAMC <<
3943 <&camcc CAMC <<
3944 <&camcc CAMC <<
3945 <&camcc CAMC <<
3946 <&camcc CAMC <<
3947 <&camcc CAMC <<
3948 <&camcc CAMC <<
3949 <&camcc CAMC <<
3950 <&camcc CAMC <<
3951 <&camcc CAMC <<
3952 <&camcc CAMC <<
3953 <&camcc CAMC <<
3954 <&camcc CAMC <<
3955 <&camcc CAMC <<
3956 <&camcc CAMC <<
3957 <&camcc CAMC <<
3958 <&camcc CAMC <<
3959 <&camcc CAMC <<
3960 <&camcc CAMC <<
3961 <&camcc CAMC <<
3962 <&camcc CAMC <<
3963 <&camcc CAMC <<
3964 <&camcc CAMC <<
3965 <&camcc CAMC <<
3966 <&camcc CAMC <<
3967 <&camcc CAMC <<
3968 <&camcc CAMC <<
3969 <&camcc CAMC <<
3970 <&camcc CAMC <<
3971 <&camcc CAMC <<
3972 <&camcc CAMC <<
3973 <&camcc CAMC <<
3974 <&camcc CAMC <<
3975 <&gcc GCC_CA <<
3976 <&gcc GCC_CA <<
3977 clock-names = "camnoc <<
3978 "cpas_a <<
3979 "csiphy <<
3980 "csiphy <<
3981 "csiphy <<
3982 "csiphy <<
3983 "csiphy <<
3984 "csiphy <<
3985 "csiphy <<
3986 "csiphy <<
3987 "vfe0_a <<
3988 "vfe0", <<
3989 "vfe0_c <<
3990 "vfe0_c <<
3991 "vfe1_a <<
3992 "vfe1", <<
3993 "vfe1_c <<
3994 "vfe1_c <<
3995 "vfe2_a <<
3996 "vfe2", <<
3997 "vfe2_c <<
3998 "vfe2_c <<
3999 "vfe3_a <<
4000 "vfe3", <<
4001 "vfe3_c <<
4002 "vfe3_c <<
4003 "vfe_li <<
4004 "vfe_li <<
4005 "vfe_li <<
4006 "vfe_li <<
4007 "vfe_li <<
4008 "vfe_li <<
4009 "vfe_li <<
4010 "vfe_li <<
4011 "vfe_li <<
4012 "vfe_li <<
4013 "vfe_li <<
4014 "vfe_li <<
4015 "gcc_ax <<
4016 "gcc_ax <<
4017 <<
4018 iommus = <&apps_smmu <<
4019 <&apps_smmu <<
4020 <&apps_smmu <<
4021 <&apps_smmu <<
4022 <&apps_smmu <<
4023 <&apps_smmu <<
4024 <&apps_smmu <<
4025 <&apps_smmu <<
4026 <&apps_smmu <<
4027 <&apps_smmu <<
4028 <&apps_smmu <<
4029 <&apps_smmu <<
4030 <&apps_smmu <<
4031 <&apps_smmu <<
4032 <&apps_smmu <<
4033 <&apps_smmu <<
4034 <<
4035 interconnects = <&gem <<
4036 <&mms <<
4037 <&mms <<
4038 <&mms <<
4039 interconnect-names = <<
4040 <<
4041 <<
4042 <<
4043 <<
4044 status = "disabled"; <<
4045 <<
4046 ports { <<
4047 #address-cell <<
4048 #size-cells = <<
4049 <<
4050 port@0 { <<
4051 reg = <<
4052 #addr <<
4053 #size <<
4054 }; <<
4055 <<
4056 port@1 { <<
4057 reg = <<
4058 #addr <<
4059 #size <<
4060 }; <<
4061 <<
4062 port@2 { <<
4063 reg = <<
4064 #addr <<
4065 #size <<
4066 }; <<
4067 <<
4068 port@3 { <<
4069 reg = <<
4070 #addr <<
4071 #size <<
4072 }; <<
4073 }; 1940 };
4074 }; 1941 };
4075 1942
4076 camcc: clock-controller@ad000 <<
4077 compatible = "qcom,sc <<
4078 reg = <0 0x0ad00000 0 <<
4079 clocks = <&gcc GCC_CA <<
4080 <&rpmhcc RPM <<
4081 <&rpmhcc RPM <<
4082 <&sleep_clk> <<
4083 power-domains = <&rpm <<
4084 required-opps = <&rpm <<
4085 #clock-cells = <1>; <<
4086 #reset-cells = <1>; <<
4087 #power-domain-cells = <<
4088 }; <<
4089 <<
4090 mdss0: display-subsystem@ae00 <<
4091 compatible = "qcom,sc <<
4092 reg = <0 0x0ae00000 0 <<
4093 reg-names = "mdss"; <<
4094 <<
4095 clocks = <&gcc GCC_DI <<
4096 <&dispcc0 DI <<
4097 <&dispcc0 DI <<
4098 clock-names = "iface" <<
4099 "ahb", <<
4100 "core"; <<
4101 interrupts = <GIC_SPI <<
4102 interconnects = <&mms <<
4103 <&mms <<
4104 interconnect-names = <<
4105 iommus = <&apps_smmu <<
4106 power-domains = <&dis <<
4107 resets = <&dispcc0 DI <<
4108 <<
4109 interrupt-controller; <<
4110 #interrupt-cells = <1 <<
4111 #address-cells = <2>; <<
4112 #size-cells = <2>; <<
4113 ranges; <<
4114 <<
4115 status = "disabled"; <<
4116 <<
4117 mdss0_mdp: display-co <<
4118 compatible = <<
4119 reg = <0 0x0a <<
4120 <0 0x0a <<
4121 reg-names = " <<
4122 <<
4123 clocks = <&gc <<
4124 <&gc <<
4125 <&di <<
4126 <&di <<
4127 <&di <<
4128 <&di <<
4129 clock-names = <<
4130 <<
4131 <<
4132 <<
4133 <<
4134 <<
4135 interrupt-par <<
4136 interrupts = <<
4137 power-domains <<
4138 <<
4139 assigned-cloc <<
4140 assigned-cloc <<
4141 operating-poi <<
4142 <<
4143 ports { <<
4144 #addr <<
4145 #size <<
4146 <<
4147 port@ <<
4148 <<
4149 <<
4150 <<
4151 <<
4152 }; <<
4153 <<
4154 port@ <<
4155 <<
4156 <<
4157 <<
4158 <<
4159 }; <<
4160 <<
4161 port@ <<
4162 <<
4163 <<
4164 <<
4165 <<
4166 }; <<
4167 <<
4168 port@ <<
4169 <<
4170 <<
4171 <<
4172 <<
4173 }; <<
4174 }; <<
4175 <<
4176 mdss0_mdp_opp <<
4177 compa <<
4178 <<
4179 opp-2 <<
4180 <<
4181 <<
4182 }; <<
4183 <<
4184 opp-3 <<
4185 <<
4186 <<
4187 }; <<
4188 <<
4189 opp-3 <<
4190 <<
4191 <<
4192 }; <<
4193 <<
4194 opp-5 <<
4195 <<
4196 <<
4197 }; <<
4198 opp-6 <<
4199 <<
4200 <<
4201 }; <<
4202 }; <<
4203 }; <<
4204 <<
4205 mdss0_dp0: displaypor <<
4206 compatible = <<
4207 reg = <0 0xae <<
4208 <0 0xae <<
4209 <0 0xae <<
4210 <0 0xae <<
4211 <0 0xae <<
4212 interrupt-par <<
4213 interrupts = <<
4214 clocks = <&di <<
4215 <&di <<
4216 <&di <<
4217 <&di <<
4218 <&di <<
4219 clock-names = <<
4220 <<
4221 <<
4222 <<
4223 <<
4224 assigned-cloc <<
4225 <<
4226 assigned-cloc <<
4227 <<
4228 <<
4229 phys = <&usb_ <<
4230 phy-names = " <<
4231 <<
4232 #sound-dai-ce <<
4233 <<
4234 operating-poi <<
4235 power-domains <<
4236 <<
4237 status = "dis <<
4238 <<
4239 ports { <<
4240 #addr <<
4241 #size <<
4242 <<
4243 port@ <<
4244 <<
4245 <<
4246 <<
4247 <<
4248 <<
4249 }; <<
4250 <<
4251 port@ <<
4252 <<
4253 <<
4254 <<
4255 <<
4256 }; <<
4257 }; <<
4258 <<
4259 mdss0_dp0_opp <<
4260 compa <<
4261 <<
4262 opp-1 <<
4263 <<
4264 <<
4265 }; <<
4266 <<
4267 opp-2 <<
4268 <<
4269 <<
4270 }; <<
4271 <<
4272 opp-5 <<
4273 <<
4274 <<
4275 }; <<
4276 <<
4277 opp-8 <<
4278 <<
4279 <<
4280 }; <<
4281 }; <<
4282 }; <<
4283 <<
4284 mdss0_dp1: displaypor <<
4285 compatible = <<
4286 reg = <0 0xae <<
4287 <0 0xae <<
4288 <0 0xae <<
4289 <0 0xae <<
4290 <0 0xae <<
4291 interrupt-par <<
4292 interrupts = <<
4293 clocks = <&di <<
4294 <&di <<
4295 <&di <<
4296 <&di <<
4297 <&di <<
4298 clock-names = <<
4299 <<
4300 <<
4301 <<
4302 assigned-cloc <<
4303 <<
4304 assigned-cloc <<
4305 <<
4306 <<
4307 phys = <&usb_ <<
4308 phy-names = " <<
4309 <<
4310 #sound-dai-ce <<
4311 <<
4312 operating-poi <<
4313 power-domains <<
4314 <<
4315 status = "dis <<
4316 <<
4317 ports { <<
4318 #addr <<
4319 #size <<
4320 <<
4321 port@ <<
4322 <<
4323 <<
4324 <<
4325 <<
4326 <<
4327 }; <<
4328 <<
4329 port@ <<
4330 <<
4331 <<
4332 <<
4333 <<
4334 }; <<
4335 }; <<
4336 <<
4337 mdss0_dp1_opp <<
4338 compa <<
4339 <<
4340 opp-1 <<
4341 <<
4342 <<
4343 }; <<
4344 <<
4345 opp-2 <<
4346 <<
4347 <<
4348 }; <<
4349 <<
4350 opp-5 <<
4351 <<
4352 <<
4353 }; <<
4354 <<
4355 opp-8 <<
4356 <<
4357 <<
4358 }; <<
4359 }; <<
4360 }; <<
4361 <<
4362 mdss0_dp2: displaypor <<
4363 compatible = <<
4364 reg = <0 0xae <<
4365 <0 0xae <<
4366 <0 0xae <<
4367 <0 0xae <<
4368 <0 0xae <<
4369 <<
4370 clocks = <&di <<
4371 <&di <<
4372 <&di <<
4373 <&di <<
4374 <&di <<
4375 clock-names = <<
4376 <<
4377 <<
4378 interrupt-par <<
4379 interrupts = <<
4380 phys = <&mdss <<
4381 phy-names = " <<
4382 power-domains <<
4383 <<
4384 assigned-cloc <<
4385 <<
4386 assigned-cloc <<
4387 operating-poi <<
4388 <<
4389 #sound-dai-ce <<
4390 <<
4391 status = "dis <<
4392 <<
4393 ports { <<
4394 #addr <<
4395 #size <<
4396 <<
4397 port@ <<
4398 <<
4399 <<
4400 <<
4401 <<
4402 }; <<
4403 <<
4404 port@ <<
4405 <<
4406 }; <<
4407 }; <<
4408 <<
4409 mdss0_dp2_opp <<
4410 compa <<
4411 <<
4412 opp-1 <<
4413 <<
4414 <<
4415 }; <<
4416 <<
4417 opp-2 <<
4418 <<
4419 <<
4420 }; <<
4421 <<
4422 opp-5 <<
4423 <<
4424 <<
4425 }; <<
4426 <<
4427 opp-8 <<
4428 <<
4429 <<
4430 }; <<
4431 }; <<
4432 }; <<
4433 <<
4434 mdss0_dp3: displaypor <<
4435 compatible = <<
4436 reg = <0 0xae <<
4437 <0 0xae <<
4438 <0 0xae <<
4439 <0 0xae <<
4440 <0 0xae <<
4441 <<
4442 clocks = <&di <<
4443 <&di <<
4444 <&di <<
4445 <&di <<
4446 <&di <<
4447 clock-names = <<
4448 <<
4449 <<
4450 interrupt-par <<
4451 interrupts = <<
4452 phys = <&mdss <<
4453 phy-names = " <<
4454 power-domains <<
4455 <<
4456 assigned-cloc <<
4457 <<
4458 assigned-cloc <<
4459 operating-poi <<
4460 <<
4461 #sound-dai-ce <<
4462 <<
4463 status = "dis <<
4464 <<
4465 ports { <<
4466 #addr <<
4467 #size <<
4468 <<
4469 port@ <<
4470 <<
4471 <<
4472 <<
4473 <<
4474 }; <<
4475 <<
4476 port@ <<
4477 <<
4478 }; <<
4479 }; <<
4480 <<
4481 mdss0_dp3_opp <<
4482 compa <<
4483 <<
4484 opp-1 <<
4485 <<
4486 <<
4487 }; <<
4488 <<
4489 opp-2 <<
4490 <<
4491 <<
4492 }; <<
4493 <<
4494 opp-5 <<
4495 <<
4496 <<
4497 }; <<
4498 <<
4499 opp-8 <<
4500 <<
4501 <<
4502 }; <<
4503 }; <<
4504 }; <<
4505 }; <<
4506 <<
4507 mdss0_dp2_phy: phy@aec2a00 { <<
4508 compatible = "qcom,sc <<
4509 reg = <0 0x0aec2a00 0 <<
4510 <0 0x0aec2200 0 <<
4511 <0 0x0aec2600 0 <<
4512 <0 0x0aec2000 0 <<
4513 <<
4514 clocks = <&dispcc0 DI <<
4515 <&dispcc0 DI <<
4516 clock-names = "aux", <<
4517 power-domains = <&rpm <<
4518 <<
4519 #clock-cells = <1>; <<
4520 #phy-cells = <0>; <<
4521 <<
4522 status = "disabled"; <<
4523 }; <<
4524 <<
4525 mdss0_dp3_phy: phy@aec5a00 { <<
4526 compatible = "qcom,sc <<
4527 reg = <0 0x0aec5a00 0 <<
4528 <0 0x0aec5200 0 <<
4529 <0 0x0aec5600 0 <<
4530 <0 0x0aec5000 0 <<
4531 <<
4532 clocks = <&dispcc0 DI <<
4533 <&dispcc0 DI <<
4534 clock-names = "aux", <<
4535 power-domains = <&rpm <<
4536 <<
4537 #clock-cells = <1>; <<
4538 #phy-cells = <0>; <<
4539 <<
4540 status = "disabled"; <<
4541 }; <<
4542 <<
4543 dispcc0: clock-controller@af0 <<
4544 compatible = "qcom,sc <<
4545 reg = <0 0x0af00000 0 <<
4546 <<
4547 clocks = <&gcc GCC_DI <<
4548 <&rpmhcc RPM <<
4549 <&sleep_clk> <<
4550 <&usb_0_qmpp <<
4551 <&usb_0_qmpp <<
4552 <&usb_1_qmpp <<
4553 <&usb_1_qmpp <<
4554 <&mdss0_dp2_ <<
4555 <&mdss0_dp2_ <<
4556 <&mdss0_dp3_ <<
4557 <&mdss0_dp3_ <<
4558 <0>, <<
4559 <0>, <<
4560 <0>, <<
4561 <0>; <<
4562 power-domains = <&rpm <<
4563 <<
4564 #clock-cells = <1>; <<
4565 #power-domain-cells = <<
4566 #reset-cells = <1>; <<
4567 <<
4568 status = "disabled"; <<
4569 }; <<
4570 <<
4571 pdc: interrupt-controller@b22 1943 pdc: interrupt-controller@b220000 {
4572 compatible = "qcom,sc 1944 compatible = "qcom,sc8280xp-pdc", "qcom,pdc";
4573 reg = <0 0x0b220000 0 1945 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
4574 qcom,pdc-ranges = <0 1946 qcom,pdc-ranges = <0 480 40>,
4575 <40 1947 <40 140 14>,
4576 <54 1948 <54 263 1>,
4577 <55 1949 <55 306 4>,
4578 <59 1950 <59 312 3>,
4579 <62 1951 <62 374 2>,
4580 <64 1952 <64 434 2>,
4581 <66 1953 <66 438 3>,
4582 <69 1954 <69 86 1>,
4583 <70 1955 <70 520 54>,
4584 <12 1956 <124 609 28>,
4585 <15 1957 <159 638 1>,
4586 <16 1958 <160 720 8>,
4587 <16 1959 <168 801 1>,
4588 <16 1960 <169 728 30>,
4589 <19 1961 <199 416 2>,
4590 <20 1962 <201 449 1>,
4591 <20 1963 <202 89 1>,
4592 <20 1964 <203 451 1>,
4593 <20 1965 <204 462 1>,
4594 <20 1966 <205 264 1>,
4595 <20 1967 <206 579 1>,
4596 <20 1968 <207 653 1>,
4597 <20 1969 <208 656 1>,
4598 <20 1970 <209 659 1>,
4599 <21 1971 <210 122 1>,
4600 <21 1972 <211 699 1>,
4601 <21 1973 <212 705 1>,
4602 <21 1974 <213 450 1>,
4603 <21 1975 <214 643 1>,
4604 <21 1976 <216 646 5>,
4605 <22 1977 <221 390 5>,
4606 <22 1978 <226 700 3>,
4607 <22 1979 <229 240 3>,
4608 <23 1980 <232 269 1>,
4609 <23 1981 <233 377 1>,
4610 <23 1982 <234 372 1>,
4611 <23 1983 <235 138 1>,
4612 <23 1984 <236 857 1>,
4613 <23 1985 <237 860 1>,
4614 <23 1986 <238 137 1>,
4615 <23 1987 <239 668 1>,
4616 <24 1988 <240 366 1>,
4617 <24 1989 <241 949 1>,
4618 <24 1990 <242 815 5>,
4619 <24 1991 <247 769 1>,
4620 <24 1992 <248 768 1>,
4621 <24 1993 <249 663 1>,
4622 <25 1994 <250 799 2>,
4623 <25 1995 <252 798 1>,
4624 <25 1996 <253 765 1>,
4625 <25 1997 <254 763 1>,
4626 <25 1998 <255 454 1>,
4627 <25 1999 <258 139 1>,
4628 <25 2000 <259 786 2>,
4629 <26 2001 <261 370 2>,
4630 <26 2002 <263 158 2>;
4631 #interrupt-cells = <2 2003 #interrupt-cells = <2>;
4632 interrupt-parent = <& 2004 interrupt-parent = <&intc>;
4633 interrupt-controller; 2005 interrupt-controller;
4634 }; 2006 };
4635 2007
4636 tsens2: thermal-sensor@c25100 <<
4637 compatible = "qcom,sc <<
4638 reg = <0 0x0c251000 0 <<
4639 <0 0x0c224000 0 <<
4640 #qcom,sensors = <11>; <<
4641 interrupts-extended = <<
4642 <<
4643 interrupt-names = "up <<
4644 #thermal-sensor-cells <<
4645 }; <<
4646 <<
4647 tsens3: thermal-sensor@c25200 <<
4648 compatible = "qcom,sc <<
4649 reg = <0 0x0c252000 0 <<
4650 <0 0x0c225000 0 <<
4651 #qcom,sensors = <5>; <<
4652 interrupts-extended = <<
4653 <<
4654 interrupt-names = "up <<
4655 #thermal-sensor-cells <<
4656 }; <<
4657 <<
4658 tsens0: thermal-sensor@c26300 2008 tsens0: thermal-sensor@c263000 {
4659 compatible = "qcom,sc 2009 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2";
4660 reg = <0 0x0c263000 0 2010 reg = <0 0x0c263000 0 0x1ff>, /* TM */
4661 <0 0x0c222000 0 2011 <0 0x0c222000 0 0x8>; /* SROT */
4662 #qcom,sensors = <14>; 2012 #qcom,sensors = <14>;
4663 interrupts-extended = 2013 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
4664 2014 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>;
4665 interrupt-names = "up 2015 interrupt-names = "uplow", "critical";
4666 #thermal-sensor-cells 2016 #thermal-sensor-cells = <1>;
4667 }; 2017 };
4668 2018
4669 restart@c264000 { <<
4670 compatible = "qcom,ps <<
4671 reg = <0 0x0c264000 0 <<
4672 /* TZ seems to block <<
4673 status = "reserved"; <<
4674 }; <<
4675 <<
4676 tsens1: thermal-sensor@c26500 2019 tsens1: thermal-sensor@c265000 {
4677 compatible = "qcom,sc 2020 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2";
4678 reg = <0 0x0c265000 0 2021 reg = <0 0x0c265000 0 0x1ff>, /* TM */
4679 <0 0x0c223000 0 2022 <0 0x0c223000 0 0x8>; /* SROT */
4680 #qcom,sensors = <16>; 2023 #qcom,sensors = <16>;
4681 interrupts-extended = 2024 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
4682 2025 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>;
4683 interrupt-names = "up 2026 interrupt-names = "uplow", "critical";
4684 #thermal-sensor-cells 2027 #thermal-sensor-cells = <1>;
4685 }; 2028 };
4686 2029
4687 aoss_qmp: power-management@c3 !! 2030 aoss_qmp: power-controller@c300000 {
4688 compatible = "qcom,sc 2031 compatible = "qcom,sc8280xp-aoss-qmp", "qcom,aoss-qmp";
4689 reg = <0 0x0c300000 0 2032 reg = <0 0x0c300000 0 0x400>;
4690 interrupts-extended = 2033 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>;
4691 mboxes = <&ipcc IPCC_ 2034 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
4692 2035
4693 #clock-cells = <0>; 2036 #clock-cells = <0>;
4694 }; 2037 };
4695 2038
4696 sram@c3f0000 { 2039 sram@c3f0000 {
4697 compatible = "qcom,rp 2040 compatible = "qcom,rpmh-stats";
4698 reg = <0 0x0c3f0000 0 2041 reg = <0 0x0c3f0000 0 0x400>;
4699 qcom,qmp = <&aoss_qmp <<
4700 }; 2042 };
4701 2043
4702 spmi_bus: spmi@c440000 { 2044 spmi_bus: spmi@c440000 {
4703 compatible = "qcom,sp 2045 compatible = "qcom,spmi-pmic-arb";
4704 reg = <0 0x0c440000 0 2046 reg = <0 0x0c440000 0 0x1100>,
4705 <0 0x0c600000 0 2047 <0 0x0c600000 0 0x2000000>,
4706 <0 0x0e600000 0 2048 <0 0x0e600000 0 0x100000>,
4707 <0 0x0e700000 0 2049 <0 0x0e700000 0 0xa0000>,
4708 <0 0x0c40a000 0 2050 <0 0x0c40a000 0 0x26000>;
4709 reg-names = "core", " 2051 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
4710 interrupt-names = "pe 2052 interrupt-names = "periph_irq";
4711 interrupts-extended = 2053 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
4712 qcom,ee = <0>; 2054 qcom,ee = <0>;
4713 qcom,channel = <0>; 2055 qcom,channel = <0>;
4714 #address-cells = <2>; 2056 #address-cells = <2>;
4715 #size-cells = <0>; 2057 #size-cells = <0>;
4716 interrupt-controller; 2058 interrupt-controller;
4717 #interrupt-cells = <4 2059 #interrupt-cells = <4>;
4718 }; 2060 };
4719 2061
4720 tlmm: pinctrl@f100000 { 2062 tlmm: pinctrl@f100000 {
4721 compatible = "qcom,sc 2063 compatible = "qcom,sc8280xp-tlmm";
4722 reg = <0 0x0f100000 0 2064 reg = <0 0x0f100000 0 0x300000>;
4723 interrupts = <GIC_SPI 2065 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
4724 gpio-controller; 2066 gpio-controller;
4725 #gpio-cells = <2>; 2067 #gpio-cells = <2>;
4726 interrupt-controller; 2068 interrupt-controller;
4727 #interrupt-cells = <2 2069 #interrupt-cells = <2>;
4728 gpio-ranges = <&tlmm 2070 gpio-ranges = <&tlmm 0 0 230>;
4729 wakeup-parent = <&pdc <<
4730 <<
4731 cci0_default: cci0-de <<
4732 cci0_i2c0_def <<
4733 /* cc <<
4734 pins <<
4735 funct <<
4736 drive <<
4737 bias- <<
4738 }; <<
4739 <<
4740 cci0_i2c1_def <<
4741 /* cc <<
4742 pins <<
4743 funct <<
4744 drive <<
4745 bias- <<
4746 }; <<
4747 }; <<
4748 <<
4749 cci0_sleep: cci0-slee <<
4750 cci0_i2c0_sle <<
4751 /* cc <<
4752 pins <<
4753 funct <<
4754 drive <<
4755 bias- <<
4756 }; <<
4757 <<
4758 cci0_i2c1_sle <<
4759 /* cc <<
4760 pins <<
4761 funct <<
4762 drive <<
4763 bias- <<
4764 }; <<
4765 }; <<
4766 <<
4767 cci1_default: cci1-de <<
4768 cci1_i2c0_def <<
4769 /* cc <<
4770 pins <<
4771 funct <<
4772 drive <<
4773 bias- <<
4774 }; <<
4775 <<
4776 cci1_i2c1_def <<
4777 /* cc <<
4778 pins <<
4779 funct <<
4780 drive <<
4781 bias- <<
4782 }; <<
4783 }; <<
4784 <<
4785 cci1_sleep: cci1-slee <<
4786 cci1_i2c0_sle <<
4787 /* cc <<
4788 pins <<
4789 funct <<
4790 drive <<
4791 bias- <<
4792 }; <<
4793 <<
4794 cci1_i2c1_sle <<
4795 /* cc <<
4796 pins <<
4797 funct <<
4798 drive <<
4799 bias- <<
4800 }; <<
4801 }; <<
4802 <<
4803 cci2_default: cci2-de <<
4804 cci2_i2c0_def <<
4805 /* cc <<
4806 pins <<
4807 funct <<
4808 drive <<
4809 bias- <<
4810 }; <<
4811 <<
4812 cci2_i2c1_def <<
4813 /* cc <<
4814 pins <<
4815 funct <<
4816 drive <<
4817 bias- <<
4818 }; <<
4819 }; <<
4820 <<
4821 cci2_sleep: cci2-slee <<
4822 cci2_i2c0_sle <<
4823 /* cc <<
4824 pins <<
4825 funct <<
4826 drive <<
4827 bias- <<
4828 }; <<
4829 <<
4830 cci2_i2c1_sle <<
4831 /* cc <<
4832 pins <<
4833 funct <<
4834 drive <<
4835 bias- <<
4836 }; <<
4837 }; <<
4838 <<
4839 cci3_default: cci3-de <<
4840 cci3_i2c0_def <<
4841 /* cc <<
4842 pins <<
4843 funct <<
4844 drive <<
4845 bias- <<
4846 }; <<
4847 <<
4848 cci3_i2c1_def <<
4849 /* cc <<
4850 pins <<
4851 funct <<
4852 drive <<
4853 bias- <<
4854 }; <<
4855 }; <<
4856 <<
4857 cci3_sleep: cci3-slee <<
4858 cci3_i2c0_sle <<
4859 /* cc <<
4860 pins <<
4861 funct <<
4862 drive <<
4863 bias- <<
4864 }; <<
4865 <<
4866 cci3_i2c1_sle <<
4867 /* cc <<
4868 pins <<
4869 funct <<
4870 drive <<
4871 bias- <<
4872 }; <<
4873 }; <<
4874 }; 2071 };
4875 2072
4876 apps_smmu: iommu@15000000 { 2073 apps_smmu: iommu@15000000 {
4877 compatible = "qcom,sc 2074 compatible = "qcom,sc8280xp-smmu-500", "arm,mmu-500";
4878 reg = <0 0x15000000 0 2075 reg = <0 0x15000000 0 0x100000>;
4879 #iommu-cells = <2>; 2076 #iommu-cells = <2>;
4880 #global-interrupts = 2077 #global-interrupts = <2>;
4881 interrupts = <GIC_SPI 2078 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
4882 <GIC_SPI 2079 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
4883 <GIC_SPI 2080 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
4884 <GIC_SPI 2081 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
4885 <GIC_SPI 2082 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
4886 <GIC_SPI 2083 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
4887 <GIC_SPI 2084 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
4888 <GIC_SPI 2085 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
4889 <GIC_SPI 2086 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
4890 <GIC_SPI 2087 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
4891 <GIC_SPI 2088 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
4892 <GIC_SPI 2089 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
4893 <GIC_SPI 2090 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
4894 <GIC_SPI 2091 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
4895 <GIC_SPI 2092 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
4896 <GIC_SPI 2093 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
4897 <GIC_SPI 2094 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
4898 <GIC_SPI 2095 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
4899 <GIC_SPI 2096 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
4900 <GIC_SPI 2097 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
4901 <GIC_SPI 2098 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
4902 <GIC_SPI 2099 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
4903 <GIC_SPI 2100 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
4904 <GIC_SPI 2101 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
4905 <GIC_SPI 2102 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
4906 <GIC_SPI 2103 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
4907 <GIC_SPI 2104 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
4908 <GIC_SPI 2105 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
4909 <GIC_SPI 2106 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
4910 <GIC_SPI 2107 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
4911 <GIC_SPI 2108 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
4912 <GIC_SPI 2109 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
4913 <GIC_SPI 2110 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
4914 <GIC_SPI 2111 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
4915 <GIC_SPI 2112 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
4916 <GIC_SPI 2113 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
4917 <GIC_SPI 2114 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
4918 <GIC_SPI 2115 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
4919 <GIC_SPI 2116 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
4920 <GIC_SPI 2117 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
4921 <GIC_SPI 2118 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
4922 <GIC_SPI 2119 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
4923 <GIC_SPI 2120 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
4924 <GIC_SPI 2121 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
4925 <GIC_SPI 2122 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
4926 <GIC_SPI 2123 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
4927 <GIC_SPI 2124 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
4928 <GIC_SPI 2125 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
4929 <GIC_SPI 2126 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
4930 <GIC_SPI 2127 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
4931 <GIC_SPI 2128 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
4932 <GIC_SPI 2129 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
4933 <GIC_SPI 2130 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
4934 <GIC_SPI 2131 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
4935 <GIC_SPI 2132 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
4936 <GIC_SPI 2133 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
4937 <GIC_SPI 2134 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
4938 <GIC_SPI 2135 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
4939 <GIC_SPI 2136 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
4940 <GIC_SPI 2137 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
4941 <GIC_SPI 2138 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
4942 <GIC_SPI 2139 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
4943 <GIC_SPI 2140 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
4944 <GIC_SPI 2141 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
4945 <GIC_SPI 2142 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
4946 <GIC_SPI 2143 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
4947 <GIC_SPI 2144 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
4948 <GIC_SPI 2145 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
4949 <GIC_SPI 2146 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
4950 <GIC_SPI 2147 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
4951 <GIC_SPI 2148 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
4952 <GIC_SPI 2149 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
4953 <GIC_SPI 2150 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
4954 <GIC_SPI 2151 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
4955 <GIC_SPI 2152 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
4956 <GIC_SPI 2153 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
4957 <GIC_SPI 2154 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
4958 <GIC_SPI 2155 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
4959 <GIC_SPI 2156 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
4960 <GIC_SPI 2157 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
4961 <GIC_SPI 2158 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>,
4962 <GIC_SPI 2159 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
4963 <GIC_SPI 2160 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
4964 <GIC_SPI 2161 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
4965 <GIC_SPI 2162 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
4966 <GIC_SPI 2163 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
4967 <GIC_SPI 2164 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
4968 <GIC_SPI 2165 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
4969 <GIC_SPI 2166 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
4970 <GIC_SPI 2167 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
4971 <GIC_SPI 2168 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
4972 <GIC_SPI 2169 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
4973 <GIC_SPI 2170 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
4974 <GIC_SPI 2171 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
4975 <GIC_SPI 2172 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
4976 <GIC_SPI 2173 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
4977 <GIC_SPI 2174 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
4978 <GIC_SPI 2175 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
4979 <GIC_SPI 2176 <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>,
4980 <GIC_SPI 2177 <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>,
4981 <GIC_SPI 2178 <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>,
4982 <GIC_SPI 2179 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
4983 <GIC_SPI 2180 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
4984 <GIC_SPI 2181 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
4985 <GIC_SPI 2182 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>,
4986 <GIC_SPI 2183 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>,
4987 <GIC_SPI 2184 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>,
4988 <GIC_SPI 2185 <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>,
4989 <GIC_SPI 2186 <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>,
4990 <GIC_SPI 2187 <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>,
4991 <GIC_SPI 2188 <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>,
4992 <GIC_SPI 2189 <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>,
4993 <GIC_SPI 2190 <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>,
4994 <GIC_SPI 2191 <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>,
4995 <GIC_SPI 2192 <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>,
4996 <GIC_SPI 2193 <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>,
4997 <GIC_SPI 2194 <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>,
4998 <GIC_SPI 2195 <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>,
4999 <GIC_SPI 2196 <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>,
5000 <GIC_SPI 2197 <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>,
5001 <GIC_SPI 2198 <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>,
5002 <GIC_SPI 2199 <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>,
5003 <GIC_SPI 2200 <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>,
5004 <GIC_SPI 2201 <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>,
5005 <GIC_SPI 2202 <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>,
5006 <GIC_SPI 2203 <GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>,
5007 <GIC_SPI 2204 <GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>,
5008 <GIC_SPI 2205 <GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>,
5009 <GIC_SPI 2206 <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>,
5010 <GIC_SPI 2207 <GIC_SPI 890 IRQ_TYPE_LEVEL_HIGH>;
5011 }; 2208 };
5012 2209
5013 intc: interrupt-controller@17 2210 intc: interrupt-controller@17a00000 {
5014 compatible = "arm,gic 2211 compatible = "arm,gic-v3";
5015 interrupt-controller; 2212 interrupt-controller;
5016 #interrupt-cells = <3 2213 #interrupt-cells = <3>;
5017 reg = <0x0 0x17a00000 2214 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
5018 <0x0 0x17a60000 2215 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
5019 interrupts = <GIC_PPI 2216 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
5020 #redistributor-region 2217 #redistributor-regions = <1>;
5021 redistributor-stride 2218 redistributor-stride = <0 0x20000>;
5022 2219
5023 #address-cells = <2>; 2220 #address-cells = <2>;
5024 #size-cells = <2>; 2221 #size-cells = <2>;
5025 ranges; 2222 ranges;
5026 2223
5027 its: msi-controller@1 !! 2224 gic-its@17a40000 {
5028 compatible = 2225 compatible = "arm,gic-v3-its";
5029 reg = <0 0x17 2226 reg = <0 0x17a40000 0 0x20000>;
5030 msi-controlle 2227 msi-controller;
5031 #msi-cells = 2228 #msi-cells = <1>;
5032 }; 2229 };
5033 }; 2230 };
5034 2231
5035 watchdog@17c10000 { 2232 watchdog@17c10000 {
5036 compatible = "qcom,ap 2233 compatible = "qcom,apss-wdt-sc8280xp", "qcom,kpss-wdt";
5037 reg = <0 0x17c10000 0 2234 reg = <0 0x17c10000 0 0x1000>;
5038 clocks = <&sleep_clk> 2235 clocks = <&sleep_clk>;
5039 interrupts = <GIC_SPI !! 2236 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
5040 }; 2237 };
5041 2238
5042 timer@17c20000 { 2239 timer@17c20000 {
5043 compatible = "arm,arm 2240 compatible = "arm,armv7-timer-mem";
5044 reg = <0x0 0x17c20000 2241 reg = <0x0 0x17c20000 0x0 0x1000>;
5045 #address-cells = <1>; 2242 #address-cells = <1>;
5046 #size-cells = <1>; 2243 #size-cells = <1>;
5047 ranges = <0x0 0x0 0x0 2244 ranges = <0x0 0x0 0x0 0x20000000>;
5048 2245
5049 frame@17c21000 { 2246 frame@17c21000 {
5050 frame-number 2247 frame-number = <0>;
5051 interrupts = 2248 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
5052 2249 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
5053 reg = <0x17c2 2250 reg = <0x17c21000 0x1000>,
5054 <0x17c2 2251 <0x17c22000 0x1000>;
5055 }; 2252 };
5056 2253
5057 frame@17c23000 { 2254 frame@17c23000 {
5058 frame-number 2255 frame-number = <1>;
5059 interrupts = 2256 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
5060 reg = <0x17c2 2257 reg = <0x17c23000 0x1000>;
5061 status = "dis 2258 status = "disabled";
5062 }; 2259 };
5063 2260
5064 frame@17c25000 { 2261 frame@17c25000 {
5065 frame-number 2262 frame-number = <2>;
5066 interrupts = 2263 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
5067 reg = <0x17c2 2264 reg = <0x17c25000 0x1000>;
5068 status = "dis 2265 status = "disabled";
5069 }; 2266 };
5070 2267
5071 frame@17c27000 { 2268 frame@17c27000 {
5072 frame-number 2269 frame-number = <3>;
5073 interrupts = 2270 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
5074 reg = <0x17c2 2271 reg = <0x17c26000 0x1000>;
5075 status = "dis 2272 status = "disabled";
5076 }; 2273 };
5077 2274
5078 frame@17c29000 { 2275 frame@17c29000 {
5079 frame-number 2276 frame-number = <4>;
5080 interrupts = 2277 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
5081 reg = <0x17c2 2278 reg = <0x17c29000 0x1000>;
5082 status = "dis 2279 status = "disabled";
5083 }; 2280 };
5084 2281
5085 frame@17c2b000 { 2282 frame@17c2b000 {
5086 frame-number 2283 frame-number = <5>;
5087 interrupts = 2284 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
5088 reg = <0x17c2 2285 reg = <0x17c2b000 0x1000>;
5089 status = "dis 2286 status = "disabled";
5090 }; 2287 };
5091 2288
5092 frame@17c2d000 { 2289 frame@17c2d000 {
5093 frame-number 2290 frame-number = <6>;
5094 interrupts = 2291 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
5095 reg = <0x17c2 2292 reg = <0x17c2d000 0x1000>;
5096 status = "dis 2293 status = "disabled";
5097 }; 2294 };
5098 }; 2295 };
5099 2296
5100 apps_rsc: rsc@18200000 { 2297 apps_rsc: rsc@18200000 {
5101 compatible = "qcom,rp 2298 compatible = "qcom,rpmh-rsc";
5102 reg = <0x0 0x18200000 2299 reg = <0x0 0x18200000 0x0 0x10000>,
5103 <0x0 0x182100 2300 <0x0 0x18210000 0x0 0x10000>,
5104 <0x0 0x182200 2301 <0x0 0x18220000 0x0 0x10000>;
5105 reg-names = "drv-0", 2302 reg-names = "drv-0", "drv-1", "drv-2";
5106 interrupts = <GIC_SPI 2303 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
5107 <GIC_SPI 2304 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
5108 <GIC_SPI 2305 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
5109 qcom,tcs-offset = <0x 2306 qcom,tcs-offset = <0xd00>;
5110 qcom,drv-id = <2>; 2307 qcom,drv-id = <2>;
5111 qcom,tcs-config = <AC 2308 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
5112 <WA 2309 <WAKE_TCS 3>, <CONTROL_TCS 1>;
5113 label = "apps_rsc"; 2310 label = "apps_rsc";
5114 power-domains = <&CLU <<
5115 2311
5116 apps_bcm_voter: bcm-v 2312 apps_bcm_voter: bcm-voter {
5117 compatible = 2313 compatible = "qcom,bcm-voter";
5118 }; 2314 };
5119 2315
5120 rpmhcc: clock-control 2316 rpmhcc: clock-controller {
5121 compatible = 2317 compatible = "qcom,sc8280xp-rpmh-clk";
5122 #clock-cells 2318 #clock-cells = <1>;
5123 clock-names = 2319 clock-names = "xo";
5124 clocks = <&xo 2320 clocks = <&xo_board_clk>;
5125 }; 2321 };
5126 2322
5127 rpmhpd: power-control 2323 rpmhpd: power-controller {
5128 compatible = 2324 compatible = "qcom,sc8280xp-rpmhpd";
5129 #power-domain 2325 #power-domain-cells = <1>;
5130 operating-poi 2326 operating-points-v2 = <&rpmhpd_opp_table>;
5131 2327
5132 rpmhpd_opp_ta 2328 rpmhpd_opp_table: opp-table {
5133 compa 2329 compatible = "operating-points-v2";
5134 2330
5135 rpmhp 2331 rpmhpd_opp_ret: opp1 {
5136 2332 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
5137 }; 2333 };
5138 2334
5139 rpmhp 2335 rpmhpd_opp_min_svs: opp2 {
5140 2336 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
5141 }; 2337 };
5142 2338
5143 rpmhp 2339 rpmhpd_opp_low_svs: opp3 {
5144 2340 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
5145 }; 2341 };
5146 2342
5147 rpmhp 2343 rpmhpd_opp_svs: opp4 {
5148 2344 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
5149 }; 2345 };
5150 2346
5151 rpmhp 2347 rpmhpd_opp_svs_l1: opp5 {
5152 2348 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
5153 }; 2349 };
5154 2350
5155 rpmhp 2351 rpmhpd_opp_nom: opp6 {
5156 2352 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
5157 }; 2353 };
5158 2354
5159 rpmhp 2355 rpmhpd_opp_nom_l1: opp7 {
5160 2356 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
5161 }; 2357 };
5162 2358
5163 rpmhp 2359 rpmhpd_opp_nom_l2: opp8 {
5164 2360 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
5165 }; 2361 };
5166 2362
5167 rpmhp 2363 rpmhpd_opp_turbo: opp9 {
5168 2364 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
5169 }; 2365 };
5170 2366
5171 rpmhp 2367 rpmhpd_opp_turbo_l1: opp10 {
5172 2368 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
5173 }; 2369 };
5174 }; 2370 };
5175 }; 2371 };
5176 }; 2372 };
5177 2373
5178 epss_l3: interconnect@1859000 2374 epss_l3: interconnect@18590000 {
5179 compatible = "qcom,sc 2375 compatible = "qcom,sc8280xp-epss-l3", "qcom,epss-l3";
5180 reg = <0 0x18590000 0 2376 reg = <0 0x18590000 0 0x1000>;
5181 2377
5182 clocks = <&rpmhcc RPM 2378 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
5183 clock-names = "xo", " 2379 clock-names = "xo", "alternate";
5184 2380
5185 #interconnect-cells = 2381 #interconnect-cells = <1>;
5186 }; 2382 };
5187 2383
5188 cpufreq_hw: cpufreq@18591000 2384 cpufreq_hw: cpufreq@18591000 {
5189 compatible = "qcom,sc 2385 compatible = "qcom,sc8280xp-cpufreq-epss", "qcom,cpufreq-epss";
5190 reg = <0 0x18591000 0 2386 reg = <0 0x18591000 0 0x1000>,
5191 <0 0x18592000 0 2387 <0 0x18592000 0 0x1000>;
5192 reg-names = "freq-dom 2388 reg-names = "freq-domain0", "freq-domain1";
5193 2389
5194 interrupts = <GIC_SPI <<
5195 <GIC_SPI <<
5196 interrupt-names = "dc <<
5197 "dc <<
5198 <<
5199 clocks = <&rpmhcc RPM 2390 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
5200 clock-names = "xo", " 2391 clock-names = "xo", "alternate";
5201 2392
5202 #freq-domain-cells = 2393 #freq-domain-cells = <1>;
5203 #clock-cells = <1>; <<
5204 }; 2394 };
5205 2395
5206 remoteproc_nsp0: remoteproc@1 2396 remoteproc_nsp0: remoteproc@1b300000 {
5207 compatible = "qcom,sc 2397 compatible = "qcom,sc8280xp-nsp0-pas";
5208 reg = <0 0x1b300000 0 2398 reg = <0 0x1b300000 0 0x100>;
5209 2399
5210 interrupts-extended = !! 2400 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
5211 2401 <&smp2p_nsp0_in 0 IRQ_TYPE_EDGE_RISING>,
5212 2402 <&smp2p_nsp0_in 1 IRQ_TYPE_EDGE_RISING>,
5213 2403 <&smp2p_nsp0_in 2 IRQ_TYPE_EDGE_RISING>,
5214 2404 <&smp2p_nsp0_in 3 IRQ_TYPE_EDGE_RISING>;
5215 interrupt-names = "wd 2405 interrupt-names = "wdog", "fatal", "ready",
5216 "ha 2406 "handover", "stop-ack";
5217 2407
5218 clocks = <&rpmhcc RPM 2408 clocks = <&rpmhcc RPMH_CXO_CLK>;
5219 clock-names = "xo"; 2409 clock-names = "xo";
5220 2410
5221 power-domains = <&rpm 2411 power-domains = <&rpmhpd SC8280XP_NSP>;
5222 power-domain-names = 2412 power-domain-names = "nsp";
5223 2413
5224 memory-region = <&pil 2414 memory-region = <&pil_nsp0_mem>;
5225 2415
5226 qcom,smem-states = <& 2416 qcom,smem-states = <&smp2p_nsp0_out 0>;
5227 qcom,smem-state-names 2417 qcom,smem-state-names = "stop";
5228 2418
5229 interconnects = <&nsp 2419 interconnects = <&nspa_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>;
5230 2420
5231 status = "disabled"; 2421 status = "disabled";
5232 2422
5233 glink-edge { 2423 glink-edge {
5234 interrupts-ex 2424 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
5235 2425 IPCC_MPROC_SIGNAL_GLINK_QMP
5236 2426 IRQ_TYPE_EDGE_RISING>;
5237 mboxes = <&ip 2427 mboxes = <&ipcc IPCC_CLIENT_CDSP
5238 2428 IPCC_MPROC_SIGNAL_GLINK_QMP>;
5239 2429
5240 label = "nsp0 2430 label = "nsp0";
5241 qcom,remote-p 2431 qcom,remote-pid = <5>;
5242 2432
5243 fastrpc { 2433 fastrpc {
5244 compa 2434 compatible = "qcom,fastrpc";
5245 qcom, 2435 qcom,glink-channels = "fastrpcglink-apps-dsp";
5246 label 2436 label = "cdsp";
5247 #addr 2437 #address-cells = <1>;
5248 #size 2438 #size-cells = <0>;
5249 2439
5250 compu 2440 compute-cb@1 {
5251 2441 compatible = "qcom,fastrpc-compute-cb";
5252 2442 reg = <1>;
5253 2443 iommus = <&apps_smmu 0x3181 0x0420>;
5254 }; 2444 };
5255 2445
5256 compu 2446 compute-cb@2 {
5257 2447 compatible = "qcom,fastrpc-compute-cb";
5258 2448 reg = <2>;
5259 2449 iommus = <&apps_smmu 0x3182 0x0420>;
5260 }; 2450 };
5261 2451
5262 compu 2452 compute-cb@3 {
5263 2453 compatible = "qcom,fastrpc-compute-cb";
5264 2454 reg = <3>;
5265 2455 iommus = <&apps_smmu 0x3183 0x0420>;
5266 }; 2456 };
5267 2457
5268 compu 2458 compute-cb@4 {
5269 2459 compatible = "qcom,fastrpc-compute-cb";
5270 2460 reg = <4>;
5271 2461 iommus = <&apps_smmu 0x3184 0x0420>;
5272 }; 2462 };
5273 2463
5274 compu 2464 compute-cb@5 {
5275 2465 compatible = "qcom,fastrpc-compute-cb";
5276 2466 reg = <5>;
5277 2467 iommus = <&apps_smmu 0x3185 0x0420>;
5278 }; 2468 };
5279 2469
5280 compu 2470 compute-cb@6 {
5281 2471 compatible = "qcom,fastrpc-compute-cb";
5282 2472 reg = <6>;
5283 2473 iommus = <&apps_smmu 0x3186 0x0420>;
5284 }; 2474 };
5285 2475
5286 compu 2476 compute-cb@7 {
5287 2477 compatible = "qcom,fastrpc-compute-cb";
5288 2478 reg = <7>;
5289 2479 iommus = <&apps_smmu 0x3187 0x0420>;
5290 }; 2480 };
5291 2481
5292 compu 2482 compute-cb@8 {
5293 2483 compatible = "qcom,fastrpc-compute-cb";
5294 2484 reg = <8>;
5295 2485 iommus = <&apps_smmu 0x3188 0x0420>;
5296 }; 2486 };
5297 2487
5298 compu 2488 compute-cb@9 {
5299 2489 compatible = "qcom,fastrpc-compute-cb";
5300 2490 reg = <9>;
5301 2491 iommus = <&apps_smmu 0x318b 0x0420>;
5302 }; 2492 };
5303 2493
5304 compu 2494 compute-cb@10 {
5305 2495 compatible = "qcom,fastrpc-compute-cb";
5306 2496 reg = <10>;
5307 2497 iommus = <&apps_smmu 0x318b 0x0420>;
5308 }; 2498 };
5309 2499
5310 compu 2500 compute-cb@11 {
5311 2501 compatible = "qcom,fastrpc-compute-cb";
5312 2502 reg = <11>;
5313 2503 iommus = <&apps_smmu 0x318c 0x0420>;
5314 }; 2504 };
5315 2505
5316 compu 2506 compute-cb@12 {
5317 2507 compatible = "qcom,fastrpc-compute-cb";
5318 2508 reg = <12>;
5319 2509 iommus = <&apps_smmu 0x318d 0x0420>;
5320 }; 2510 };
5321 2511
5322 compu 2512 compute-cb@13 {
5323 2513 compatible = "qcom,fastrpc-compute-cb";
5324 2514 reg = <13>;
5325 2515 iommus = <&apps_smmu 0x318e 0x0420>;
5326 }; 2516 };
5327 2517
5328 compu 2518 compute-cb@14 {
5329 2519 compatible = "qcom,fastrpc-compute-cb";
5330 2520 reg = <14>;
5331 2521 iommus = <&apps_smmu 0x318f 0x0420>;
5332 }; 2522 };
5333 }; 2523 };
5334 }; 2524 };
5335 }; 2525 };
5336 2526
5337 remoteproc_nsp1: remoteproc@2 2527 remoteproc_nsp1: remoteproc@21300000 {
5338 compatible = "qcom,sc 2528 compatible = "qcom,sc8280xp-nsp1-pas";
5339 reg = <0 0x21300000 0 2529 reg = <0 0x21300000 0 0x100>;
5340 2530
5341 interrupts-extended = !! 2531 interrupts-extended = <&intc GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>,
5342 2532 <&smp2p_nsp1_in 0 IRQ_TYPE_EDGE_RISING>,
5343 2533 <&smp2p_nsp1_in 1 IRQ_TYPE_EDGE_RISING>,
5344 2534 <&smp2p_nsp1_in 2 IRQ_TYPE_EDGE_RISING>,
5345 2535 <&smp2p_nsp1_in 3 IRQ_TYPE_EDGE_RISING>;
5346 interrupt-names = "wd 2536 interrupt-names = "wdog", "fatal", "ready",
5347 "ha 2537 "handover", "stop-ack";
5348 2538
5349 clocks = <&rpmhcc RPM 2539 clocks = <&rpmhcc RPMH_CXO_CLK>;
5350 clock-names = "xo"; 2540 clock-names = "xo";
5351 2541
5352 power-domains = <&rpm 2542 power-domains = <&rpmhpd SC8280XP_NSP>;
5353 power-domain-names = 2543 power-domain-names = "nsp";
5354 2544
5355 memory-region = <&pil 2545 memory-region = <&pil_nsp1_mem>;
5356 2546
5357 qcom,smem-states = <& 2547 qcom,smem-states = <&smp2p_nsp1_out 0>;
5358 qcom,smem-state-names 2548 qcom,smem-state-names = "stop";
5359 2549
5360 interconnects = <&nsp 2550 interconnects = <&nspb_noc MASTER_CDSP_PROC_B 0 &mc_virt SLAVE_EBI1 0>;
5361 2551
5362 status = "disabled"; 2552 status = "disabled";
5363 2553
5364 glink-edge { 2554 glink-edge {
5365 interrupts-ex 2555 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1
5366 2556 IPCC_MPROC_SIGNAL_GLINK_QMP
5367 2557 IRQ_TYPE_EDGE_RISING>;
5368 mboxes = <&ip 2558 mboxes = <&ipcc IPCC_CLIENT_NSP1
5369 2559 IPCC_MPROC_SIGNAL_GLINK_QMP>;
5370 2560
5371 label = "nsp1 2561 label = "nsp1";
5372 qcom,remote-p 2562 qcom,remote-pid = <12>;
5373 }; 2563 };
5374 }; 2564 };
5375 <<
5376 mdss1: display-subsystem@2200 <<
5377 compatible = "qcom,sc <<
5378 reg = <0 0x22000000 0 <<
5379 reg-names = "mdss"; <<
5380 <<
5381 clocks = <&gcc GCC_DI <<
5382 <&dispcc1 DI <<
5383 <&dispcc1 DI <<
5384 clock-names = "iface" <<
5385 "ahb", <<
5386 "core"; <<
5387 interconnects = <&mms <<
5388 <&mms <<
5389 interconnect-names = <<
5390 interrupts = <GIC_SPI <<
5391 <<
5392 iommus = <&apps_smmu <<
5393 power-domains = <&dis <<
5394 resets = <&dispcc1 DI <<
5395 <<
5396 interrupt-controller; <<
5397 #interrupt-cells = <1 <<
5398 #address-cells = <2>; <<
5399 #size-cells = <2>; <<
5400 ranges; <<
5401 <<
5402 status = "disabled"; <<
5403 <<
5404 mdss1_mdp: display-co <<
5405 compatible = <<
5406 reg = <0 0x22 <<
5407 <0 0x22 <<
5408 reg-names = " <<
5409 <<
5410 clocks = <&gc <<
5411 <&gc <<
5412 <&di <<
5413 <&di <<
5414 <&di <<
5415 <&di <<
5416 clock-names = <<
5417 <<
5418 <<
5419 <<
5420 <<
5421 <<
5422 interrupt-par <<
5423 interrupts = <<
5424 power-domains <<
5425 <<
5426 assigned-cloc <<
5427 assigned-cloc <<
5428 operating-poi <<
5429 <<
5430 ports { <<
5431 #addr <<
5432 #size <<
5433 <<
5434 port@ <<
5435 <<
5436 <<
5437 <<
5438 <<
5439 }; <<
5440 <<
5441 port@ <<
5442 <<
5443 <<
5444 <<
5445 <<
5446 }; <<
5447 <<
5448 port@ <<
5449 <<
5450 <<
5451 <<
5452 <<
5453 }; <<
5454 <<
5455 port@ <<
5456 <<
5457 <<
5458 <<
5459 <<
5460 }; <<
5461 }; <<
5462 <<
5463 mdss1_mdp_opp <<
5464 compa <<
5465 <<
5466 opp-2 <<
5467 <<
5468 <<
5469 }; <<
5470 <<
5471 opp-3 <<
5472 <<
5473 <<
5474 }; <<
5475 <<
5476 opp-3 <<
5477 <<
5478 <<
5479 }; <<
5480 <<
5481 opp-5 <<
5482 <<
5483 <<
5484 }; <<
5485 opp-6 <<
5486 <<
5487 <<
5488 }; <<
5489 }; <<
5490 }; <<
5491 <<
5492 mdss1_dp0: displaypor <<
5493 compatible = <<
5494 reg = <0 0x22 <<
5495 <0 0x22 <<
5496 <0 0x22 <<
5497 <0 0x22 <<
5498 <0 0x22 <<
5499 <<
5500 clocks = <&di <<
5501 <&di <<
5502 <&di <<
5503 <&di <<
5504 <&di <<
5505 clock-names = <<
5506 <<
5507 <<
5508 interrupt-par <<
5509 interrupts = <<
5510 phys = <&mdss <<
5511 phy-names = " <<
5512 power-domains <<
5513 <<
5514 assigned-cloc <<
5515 <<
5516 assigned-cloc <<
5517 operating-poi <<
5518 <<
5519 #sound-dai-ce <<
5520 <<
5521 status = "dis <<
5522 <<
5523 ports { <<
5524 #addr <<
5525 #size <<
5526 <<
5527 port@ <<
5528 <<
5529 <<
5530 <<
5531 <<
5532 }; <<
5533 <<
5534 port@ <<
5535 <<
5536 }; <<
5537 }; <<
5538 <<
5539 mdss1_dp0_opp <<
5540 compa <<
5541 <<
5542 opp-1 <<
5543 <<
5544 <<
5545 }; <<
5546 <<
5547 opp-2 <<
5548 <<
5549 <<
5550 }; <<
5551 <<
5552 opp-5 <<
5553 <<
5554 <<
5555 }; <<
5556 <<
5557 opp-8 <<
5558 <<
5559 <<
5560 }; <<
5561 }; <<
5562 }; <<
5563 <<
5564 mdss1_dp1: displaypor <<
5565 compatible = <<
5566 reg = <0 0x22 <<
5567 <0 0x22 <<
5568 <0 0x22 <<
5569 <0 0x22 <<
5570 <0 0x22 <<
5571 <<
5572 clocks = <&di <<
5573 <&di <<
5574 <&di <<
5575 <&di <<
5576 <&di <<
5577 clock-names = <<
5578 <<
5579 <<
5580 interrupt-par <<
5581 interrupts = <<
5582 phys = <&mdss <<
5583 phy-names = " <<
5584 power-domains <<
5585 <<
5586 assigned-cloc <<
5587 <<
5588 assigned-cloc <<
5589 operating-poi <<
5590 <<
5591 #sound-dai-ce <<
5592 <<
5593 status = "dis <<
5594 <<
5595 ports { <<
5596 #addr <<
5597 #size <<
5598 <<
5599 port@ <<
5600 <<
5601 <<
5602 <<
5603 <<
5604 }; <<
5605 <<
5606 port@ <<
5607 <<
5608 }; <<
5609 }; <<
5610 <<
5611 mdss1_dp1_opp <<
5612 compa <<
5613 <<
5614 opp-1 <<
5615 <<
5616 <<
5617 }; <<
5618 <<
5619 opp-2 <<
5620 <<
5621 <<
5622 }; <<
5623 <<
5624 opp-5 <<
5625 <<
5626 <<
5627 }; <<
5628 <<
5629 opp-8 <<
5630 <<
5631 <<
5632 }; <<
5633 }; <<
5634 }; <<
5635 <<
5636 mdss1_dp2: displaypor <<
5637 compatible = <<
5638 reg = <0 0x22 <<
5639 <0 0x22 <<
5640 <0 0x22 <<
5641 <0 0x22 <<
5642 <0 0x22 <<
5643 <<
5644 clocks = <&di <<
5645 <&di <<
5646 <&di <<
5647 <&di <<
5648 <&di <<
5649 clock-names = <<
5650 <<
5651 <<
5652 interrupt-par <<
5653 interrupts = <<
5654 phys = <&mdss <<
5655 phy-names = " <<
5656 power-domains <<
5657 <<
5658 assigned-cloc <<
5659 <<
5660 assigned-cloc <<
5661 operating-poi <<
5662 <<
5663 #sound-dai-ce <<
5664 <<
5665 status = "dis <<
5666 <<
5667 ports { <<
5668 #addr <<
5669 #size <<
5670 <<
5671 port@ <<
5672 <<
5673 <<
5674 <<
5675 <<
5676 }; <<
5677 <<
5678 port@ <<
5679 <<
5680 }; <<
5681 }; <<
5682 <<
5683 mdss1_dp2_opp <<
5684 compa <<
5685 <<
5686 opp-1 <<
5687 <<
5688 <<
5689 }; <<
5690 <<
5691 opp-2 <<
5692 <<
5693 <<
5694 }; <<
5695 <<
5696 opp-5 <<
5697 <<
5698 <<
5699 }; <<
5700 <<
5701 opp-8 <<
5702 <<
5703 <<
5704 }; <<
5705 }; <<
5706 }; <<
5707 <<
5708 mdss1_dp3: displaypor <<
5709 compatible = <<
5710 reg = <0 0x22 <<
5711 <0 0x22 <<
5712 <0 0x22 <<
5713 <0 0x22 <<
5714 <0 0x22 <<
5715 <<
5716 clocks = <&di <<
5717 <&di <<
5718 <&di <<
5719 <&di <<
5720 <&di <<
5721 clock-names = <<
5722 <<
5723 <<
5724 interrupt-par <<
5725 interrupts = <<
5726 phys = <&mdss <<
5727 phy-names = " <<
5728 power-domains <<
5729 <<
5730 assigned-cloc <<
5731 <<
5732 assigned-cloc <<
5733 operating-poi <<
5734 <<
5735 #sound-dai-ce <<
5736 <<
5737 status = "dis <<
5738 <<
5739 ports { <<
5740 #addr <<
5741 #size <<
5742 <<
5743 port@ <<
5744 <<
5745 <<
5746 <<
5747 <<
5748 }; <<
5749 <<
5750 port@ <<
5751 <<
5752 }; <<
5753 }; <<
5754 <<
5755 mdss1_dp3_opp <<
5756 compa <<
5757 <<
5758 opp-1 <<
5759 <<
5760 <<
5761 }; <<
5762 <<
5763 opp-2 <<
5764 <<
5765 <<
5766 }; <<
5767 <<
5768 opp-5 <<
5769 <<
5770 <<
5771 }; <<
5772 <<
5773 opp-8 <<
5774 <<
5775 <<
5776 }; <<
5777 }; <<
5778 }; <<
5779 }; <<
5780 <<
5781 mdss1_dp2_phy: phy@220c2a00 { <<
5782 compatible = "qcom,sc <<
5783 reg = <0 0x220c2a00 0 <<
5784 <0 0x220c2200 0 <<
5785 <0 0x220c2600 0 <<
5786 <0 0x220c2000 0 <<
5787 <<
5788 clocks = <&dispcc1 DI <<
5789 <&dispcc1 DI <<
5790 clock-names = "aux", <<
5791 power-domains = <&rpm <<
5792 <<
5793 #clock-cells = <1>; <<
5794 #phy-cells = <0>; <<
5795 <<
5796 status = "disabled"; <<
5797 }; <<
5798 <<
5799 mdss1_dp3_phy: phy@220c5a00 { <<
5800 compatible = "qcom,sc <<
5801 reg = <0 0x220c5a00 0 <<
5802 <0 0x220c5200 0 <<
5803 <0 0x220c5600 0 <<
5804 <0 0x220c5000 0 <<
5805 <<
5806 clocks = <&dispcc1 DI <<
5807 <&dispcc1 DI <<
5808 clock-names = "aux", <<
5809 power-domains = <&rpm <<
5810 <<
5811 #clock-cells = <1>; <<
5812 #phy-cells = <0>; <<
5813 <<
5814 status = "disabled"; <<
5815 }; <<
5816 <<
5817 dispcc1: clock-controller@221 <<
5818 compatible = "qcom,sc <<
5819 reg = <0 0x22100000 0 <<
5820 <<
5821 clocks = <&gcc GCC_DI <<
5822 <&rpmhcc RPM <<
5823 <0>, <<
5824 <&mdss1_dp0_ <<
5825 <&mdss1_dp0_ <<
5826 <&mdss1_dp1_ <<
5827 <&mdss1_dp1_ <<
5828 <&mdss1_dp2_ <<
5829 <&mdss1_dp2_ <<
5830 <&mdss1_dp3_ <<
5831 <&mdss1_dp3_ <<
5832 <0>, <<
5833 <0>, <<
5834 <0>, <<
5835 <0>; <<
5836 power-domains = <&rpm <<
5837 <<
5838 #clock-cells = <1>; <<
5839 #power-domain-cells = <<
5840 #reset-cells = <1>; <<
5841 <<
5842 status = "disabled"; <<
5843 }; <<
5844 <<
5845 ethernet1: ethernet@23000000 <<
5846 compatible = "qcom,sc <<
5847 reg = <0x0 0x23000000 <<
5848 <0x0 0x23016000 <<
5849 reg-names = "stmmacet <<
5850 <<
5851 clocks = <&gcc GCC_EM <<
5852 <&gcc GCC_EM <<
5853 <&gcc GCC_EM <<
5854 <&gcc GCC_EM <<
5855 clock-names = "stmmac <<
5856 "pclk", <<
5857 "ptp_re <<
5858 "rgmii" <<
5859 <<
5860 interrupts = <GIC_SPI <<
5861 <GIC_SPI <<
5862 interrupt-names = "ma <<
5863 <<
5864 iommus = <&apps_smmu <<
5865 power-domains = <&gcc <<
5866 <<
5867 snps,tso; <<
5868 snps,pbl = <32>; <<
5869 rx-fifo-depth = <4096 <<
5870 tx-fifo-depth = <4096 <<
5871 <<
5872 status = "disabled"; <<
5873 }; <<
5874 }; <<
5875 <<
5876 sound: sound { <<
5877 }; 2565 };
5878 2566
5879 thermal-zones { 2567 thermal-zones {
5880 cpu0-thermal { 2568 cpu0-thermal {
5881 polling-delay-passive 2569 polling-delay-passive = <250>;
>> 2570 polling-delay = <1000>;
5882 2571
5883 thermal-sensors = <&t 2572 thermal-sensors = <&tsens0 1>;
5884 2573
5885 trips { 2574 trips {
5886 cpu-crit { 2575 cpu-crit {
5887 tempe 2576 temperature = <110000>;
5888 hyste 2577 hysteresis = <1000>;
5889 type 2578 type = "critical";
5890 }; 2579 };
5891 }; 2580 };
5892 }; 2581 };
5893 2582
5894 cpu1-thermal { 2583 cpu1-thermal {
5895 polling-delay-passive 2584 polling-delay-passive = <250>;
>> 2585 polling-delay = <1000>;
5896 2586
5897 thermal-sensors = <&t 2587 thermal-sensors = <&tsens0 2>;
5898 2588
5899 trips { 2589 trips {
5900 cpu-crit { 2590 cpu-crit {
5901 tempe 2591 temperature = <110000>;
5902 hyste 2592 hysteresis = <1000>;
5903 type 2593 type = "critical";
5904 }; 2594 };
5905 }; 2595 };
5906 }; 2596 };
5907 2597
5908 cpu2-thermal { 2598 cpu2-thermal {
5909 polling-delay-passive 2599 polling-delay-passive = <250>;
>> 2600 polling-delay = <1000>;
5910 2601
5911 thermal-sensors = <&t 2602 thermal-sensors = <&tsens0 3>;
5912 2603
5913 trips { 2604 trips {
5914 cpu-crit { 2605 cpu-crit {
5915 tempe 2606 temperature = <110000>;
5916 hyste 2607 hysteresis = <1000>;
5917 type 2608 type = "critical";
5918 }; 2609 };
5919 }; 2610 };
5920 }; 2611 };
5921 2612
5922 cpu3-thermal { 2613 cpu3-thermal {
5923 polling-delay-passive 2614 polling-delay-passive = <250>;
>> 2615 polling-delay = <1000>;
5924 2616
5925 thermal-sensors = <&t 2617 thermal-sensors = <&tsens0 4>;
5926 2618
5927 trips { 2619 trips {
5928 cpu-crit { 2620 cpu-crit {
5929 tempe 2621 temperature = <110000>;
5930 hyste 2622 hysteresis = <1000>;
5931 type 2623 type = "critical";
5932 }; 2624 };
5933 }; 2625 };
5934 }; 2626 };
5935 2627
5936 cpu4-thermal { 2628 cpu4-thermal {
5937 polling-delay-passive 2629 polling-delay-passive = <250>;
>> 2630 polling-delay = <1000>;
5938 2631
5939 thermal-sensors = <&t 2632 thermal-sensors = <&tsens0 5>;
5940 2633
5941 trips { 2634 trips {
5942 cpu-crit { 2635 cpu-crit {
5943 tempe 2636 temperature = <110000>;
5944 hyste 2637 hysteresis = <1000>;
5945 type 2638 type = "critical";
5946 }; 2639 };
5947 }; 2640 };
5948 }; 2641 };
5949 2642
5950 cpu5-thermal { 2643 cpu5-thermal {
5951 polling-delay-passive 2644 polling-delay-passive = <250>;
>> 2645 polling-delay = <1000>;
5952 2646
5953 thermal-sensors = <&t 2647 thermal-sensors = <&tsens0 6>;
5954 2648
5955 trips { 2649 trips {
5956 cpu-crit { 2650 cpu-crit {
5957 tempe 2651 temperature = <110000>;
5958 hyste 2652 hysteresis = <1000>;
5959 type 2653 type = "critical";
5960 }; 2654 };
5961 }; 2655 };
5962 }; 2656 };
5963 2657
5964 cpu6-thermal { 2658 cpu6-thermal {
5965 polling-delay-passive 2659 polling-delay-passive = <250>;
>> 2660 polling-delay = <1000>;
5966 2661
5967 thermal-sensors = <&t 2662 thermal-sensors = <&tsens0 7>;
5968 2663
5969 trips { 2664 trips {
5970 cpu-crit { 2665 cpu-crit {
5971 tempe 2666 temperature = <110000>;
5972 hyste 2667 hysteresis = <1000>;
5973 type 2668 type = "critical";
5974 }; 2669 };
5975 }; 2670 };
5976 }; 2671 };
5977 2672
5978 cpu7-thermal { 2673 cpu7-thermal {
5979 polling-delay-passive 2674 polling-delay-passive = <250>;
>> 2675 polling-delay = <1000>;
5980 2676
5981 thermal-sensors = <&t 2677 thermal-sensors = <&tsens0 8>;
5982 2678
5983 trips { 2679 trips {
5984 cpu-crit { 2680 cpu-crit {
5985 tempe 2681 temperature = <110000>;
5986 hyste 2682 hysteresis = <1000>;
5987 type 2683 type = "critical";
5988 }; 2684 };
5989 }; 2685 };
5990 }; 2686 };
5991 2687
5992 cluster0-thermal { 2688 cluster0-thermal {
5993 polling-delay-passive 2689 polling-delay-passive = <250>;
>> 2690 polling-delay = <1000>;
5994 2691
5995 thermal-sensors = <&t 2692 thermal-sensors = <&tsens0 9>;
5996 2693
5997 trips { 2694 trips {
5998 cpu-crit { 2695 cpu-crit {
5999 tempe 2696 temperature = <110000>;
6000 hyste 2697 hysteresis = <1000>;
6001 type 2698 type = "critical";
6002 }; 2699 };
6003 }; 2700 };
6004 }; 2701 };
6005 2702
6006 gpu-thermal { <<
6007 polling-delay-passive <<
6008 <<
6009 thermal-sensors = <&t <<
6010 <<
6011 cooling-maps { <<
6012 map0 { <<
6013 trip <<
6014 cooli <<
6015 }; <<
6016 }; <<
6017 <<
6018 trips { <<
6019 gpu_alert0: t <<
6020 tempe <<
6021 hyste <<
6022 type <<
6023 }; <<
6024 <<
6025 trip-point1 { <<
6026 tempe <<
6027 hyste <<
6028 type <<
6029 }; <<
6030 }; <<
6031 }; <<
6032 <<
6033 mem-thermal { 2703 mem-thermal {
6034 polling-delay-passive 2704 polling-delay-passive = <250>;
>> 2705 polling-delay = <1000>;
6035 2706
6036 thermal-sensors = <&t 2707 thermal-sensors = <&tsens1 15>;
6037 2708
6038 trips { 2709 trips {
6039 trip-point0 { 2710 trip-point0 {
6040 tempe 2711 temperature = <90000>;
6041 hyste 2712 hysteresis = <2000>;
6042 type 2713 type = "hot";
6043 }; 2714 };
6044 }; 2715 };
6045 }; 2716 };
6046 }; 2717 };
6047 2718
6048 timer { 2719 timer {
6049 compatible = "arm,armv8-timer 2720 compatible = "arm,armv8-timer";
6050 interrupts = <GIC_PPI 13 (GIC 2721 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
6051 <GIC_PPI 14 (GIC 2722 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
6052 <GIC_PPI 11 (GIC 2723 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
6053 <GIC_PPI 10 (GIC 2724 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
6054 }; 2725 };
6055 }; 2726 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.