1 // SPDX-License-Identifier: BSD-3-Clause 1 // SPDX-License-Identifier: BSD-3-Clause
2 /* 2 /*
3 * Copyright (c) 2021, The Linux Foundation. A 3 * Copyright (c) 2021, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2022, Linaro Limited 4 * Copyright (c) 2022, Linaro Limited
5 */ 5 */
6 6
7 #include <dt-bindings/clock/qcom,dispcc-sc8280 7 #include <dt-bindings/clock/qcom,dispcc-sc8280xp.h>
8 #include <dt-bindings/clock/qcom,gcc-sc8280xp. 8 #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
9 #include <dt-bindings/clock/qcom,gpucc-sc8280x <<
10 #include <dt-bindings/clock/qcom,rpmh.h> 9 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/clock/qcom,sc8280xp-camc <<
12 #include <dt-bindings/clock/qcom,sc8280xp-lpas <<
13 #include <dt-bindings/interconnect/qcom,osm-l3 10 #include <dt-bindings/interconnect/qcom,osm-l3.h>
14 #include <dt-bindings/interconnect/qcom,sc8280 11 #include <dt-bindings/interconnect/qcom,sc8280xp.h>
15 #include <dt-bindings/interrupt-controller/arm 12 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/mailbox/qcom-ipcc.h> 13 #include <dt-bindings/mailbox/qcom-ipcc.h>
17 #include <dt-bindings/phy/phy-qcom-qmp.h> 14 #include <dt-bindings/phy/phy-qcom-qmp.h>
18 #include <dt-bindings/power/qcom-rpmpd.h> 15 #include <dt-bindings/power/qcom-rpmpd.h>
19 #include <dt-bindings/soc/qcom,gpr.h> 16 #include <dt-bindings/soc/qcom,gpr.h>
20 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 17 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
21 #include <dt-bindings/sound/qcom,q6afe.h> 18 #include <dt-bindings/sound/qcom,q6afe.h>
22 #include <dt-bindings/thermal/thermal.h> 19 #include <dt-bindings/thermal/thermal.h>
23 20
24 / { 21 / {
25 interrupt-parent = <&intc>; 22 interrupt-parent = <&intc>;
26 23
27 #address-cells = <2>; 24 #address-cells = <2>;
28 #size-cells = <2>; 25 #size-cells = <2>;
29 26
30 clocks { 27 clocks {
31 xo_board_clk: xo-board-clk { 28 xo_board_clk: xo-board-clk {
32 compatible = "fixed-cl 29 compatible = "fixed-clock";
33 #clock-cells = <0>; 30 #clock-cells = <0>;
34 }; 31 };
35 32
36 sleep_clk: sleep-clk { 33 sleep_clk: sleep-clk {
37 compatible = "fixed-cl 34 compatible = "fixed-clock";
38 #clock-cells = <0>; 35 #clock-cells = <0>;
39 clock-frequency = <327 36 clock-frequency = <32764>;
40 }; 37 };
41 }; 38 };
42 39
43 cpus { 40 cpus {
44 #address-cells = <2>; 41 #address-cells = <2>;
45 #size-cells = <0>; 42 #size-cells = <0>;
46 43
47 CPU0: cpu@0 { 44 CPU0: cpu@0 {
48 device_type = "cpu"; 45 device_type = "cpu";
49 compatible = "arm,cort 46 compatible = "arm,cortex-a78c";
50 reg = <0x0 0x0>; 47 reg = <0x0 0x0>;
51 clocks = <&cpufreq_hw 48 clocks = <&cpufreq_hw 0>;
52 enable-method = "psci" 49 enable-method = "psci";
53 capacity-dmips-mhz = < !! 50 capacity-dmips-mhz = <602>;
54 dynamic-power-coeffici <<
55 next-level-cache = <&L 51 next-level-cache = <&L2_0>;
56 power-domains = <&CPU_ 52 power-domains = <&CPU_PD0>;
57 power-domain-names = " 53 power-domain-names = "psci";
58 qcom,freq-domain = <&c 54 qcom,freq-domain = <&cpufreq_hw 0>;
59 operating-points-v2 = 55 operating-points-v2 = <&cpu0_opp_table>;
60 interconnects = <&epss 56 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
61 #cooling-cells = <2>; 57 #cooling-cells = <2>;
62 L2_0: l2-cache { 58 L2_0: l2-cache {
63 compatible = " 59 compatible = "cache";
64 cache-level = 60 cache-level = <2>;
65 cache-unified; 61 cache-unified;
66 next-level-cac 62 next-level-cache = <&L3_0>;
67 L3_0: l3-cache 63 L3_0: l3-cache {
68 compat 64 compatible = "cache";
69 cache- 65 cache-level = <3>;
70 cache- 66 cache-unified;
71 }; 67 };
72 }; 68 };
73 }; 69 };
74 70
75 CPU1: cpu@100 { 71 CPU1: cpu@100 {
76 device_type = "cpu"; 72 device_type = "cpu";
77 compatible = "arm,cort 73 compatible = "arm,cortex-a78c";
78 reg = <0x0 0x100>; 74 reg = <0x0 0x100>;
79 clocks = <&cpufreq_hw 75 clocks = <&cpufreq_hw 0>;
80 enable-method = "psci" 76 enable-method = "psci";
81 capacity-dmips-mhz = < !! 77 capacity-dmips-mhz = <602>;
82 dynamic-power-coeffici <<
83 next-level-cache = <&L 78 next-level-cache = <&L2_100>;
84 power-domains = <&CPU_ 79 power-domains = <&CPU_PD1>;
85 power-domain-names = " 80 power-domain-names = "psci";
86 qcom,freq-domain = <&c 81 qcom,freq-domain = <&cpufreq_hw 0>;
87 operating-points-v2 = 82 operating-points-v2 = <&cpu0_opp_table>;
88 interconnects = <&epss 83 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
89 #cooling-cells = <2>; 84 #cooling-cells = <2>;
90 L2_100: l2-cache { 85 L2_100: l2-cache {
91 compatible = " 86 compatible = "cache";
92 cache-level = 87 cache-level = <2>;
93 cache-unified; 88 cache-unified;
94 next-level-cac 89 next-level-cache = <&L3_0>;
95 }; 90 };
96 }; 91 };
97 92
98 CPU2: cpu@200 { 93 CPU2: cpu@200 {
99 device_type = "cpu"; 94 device_type = "cpu";
100 compatible = "arm,cort 95 compatible = "arm,cortex-a78c";
101 reg = <0x0 0x200>; 96 reg = <0x0 0x200>;
102 clocks = <&cpufreq_hw 97 clocks = <&cpufreq_hw 0>;
103 enable-method = "psci" 98 enable-method = "psci";
104 capacity-dmips-mhz = < !! 99 capacity-dmips-mhz = <602>;
105 dynamic-power-coeffici <<
106 next-level-cache = <&L 100 next-level-cache = <&L2_200>;
107 power-domains = <&CPU_ 101 power-domains = <&CPU_PD2>;
108 power-domain-names = " 102 power-domain-names = "psci";
109 qcom,freq-domain = <&c 103 qcom,freq-domain = <&cpufreq_hw 0>;
110 operating-points-v2 = 104 operating-points-v2 = <&cpu0_opp_table>;
111 interconnects = <&epss 105 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
112 #cooling-cells = <2>; 106 #cooling-cells = <2>;
113 L2_200: l2-cache { 107 L2_200: l2-cache {
114 compatible = " 108 compatible = "cache";
115 cache-level = 109 cache-level = <2>;
116 cache-unified; 110 cache-unified;
117 next-level-cac 111 next-level-cache = <&L3_0>;
118 }; 112 };
119 }; 113 };
120 114
121 CPU3: cpu@300 { 115 CPU3: cpu@300 {
122 device_type = "cpu"; 116 device_type = "cpu";
123 compatible = "arm,cort 117 compatible = "arm,cortex-a78c";
124 reg = <0x0 0x300>; 118 reg = <0x0 0x300>;
125 clocks = <&cpufreq_hw 119 clocks = <&cpufreq_hw 0>;
126 enable-method = "psci" 120 enable-method = "psci";
127 capacity-dmips-mhz = < !! 121 capacity-dmips-mhz = <602>;
128 dynamic-power-coeffici <<
129 next-level-cache = <&L 122 next-level-cache = <&L2_300>;
130 power-domains = <&CPU_ 123 power-domains = <&CPU_PD3>;
131 power-domain-names = " 124 power-domain-names = "psci";
132 qcom,freq-domain = <&c 125 qcom,freq-domain = <&cpufreq_hw 0>;
133 operating-points-v2 = 126 operating-points-v2 = <&cpu0_opp_table>;
134 interconnects = <&epss 127 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
135 #cooling-cells = <2>; 128 #cooling-cells = <2>;
136 L2_300: l2-cache { 129 L2_300: l2-cache {
137 compatible = " 130 compatible = "cache";
138 cache-level = 131 cache-level = <2>;
139 cache-unified; 132 cache-unified;
140 next-level-cac 133 next-level-cache = <&L3_0>;
141 }; 134 };
142 }; 135 };
143 136
144 CPU4: cpu@400 { 137 CPU4: cpu@400 {
145 device_type = "cpu"; 138 device_type = "cpu";
146 compatible = "arm,cort 139 compatible = "arm,cortex-x1c";
147 reg = <0x0 0x400>; 140 reg = <0x0 0x400>;
148 clocks = <&cpufreq_hw 141 clocks = <&cpufreq_hw 1>;
149 enable-method = "psci" 142 enable-method = "psci";
150 capacity-dmips-mhz = < 143 capacity-dmips-mhz = <1024>;
151 dynamic-power-coeffici <<
152 next-level-cache = <&L 144 next-level-cache = <&L2_400>;
153 power-domains = <&CPU_ 145 power-domains = <&CPU_PD4>;
154 power-domain-names = " 146 power-domain-names = "psci";
155 qcom,freq-domain = <&c 147 qcom,freq-domain = <&cpufreq_hw 1>;
156 operating-points-v2 = 148 operating-points-v2 = <&cpu4_opp_table>;
157 interconnects = <&epss 149 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
158 #cooling-cells = <2>; 150 #cooling-cells = <2>;
159 L2_400: l2-cache { 151 L2_400: l2-cache {
160 compatible = " 152 compatible = "cache";
161 cache-level = 153 cache-level = <2>;
162 cache-unified; 154 cache-unified;
163 next-level-cac 155 next-level-cache = <&L3_0>;
164 }; 156 };
165 }; 157 };
166 158
167 CPU5: cpu@500 { 159 CPU5: cpu@500 {
168 device_type = "cpu"; 160 device_type = "cpu";
169 compatible = "arm,cort 161 compatible = "arm,cortex-x1c";
170 reg = <0x0 0x500>; 162 reg = <0x0 0x500>;
171 clocks = <&cpufreq_hw 163 clocks = <&cpufreq_hw 1>;
172 enable-method = "psci" 164 enable-method = "psci";
173 capacity-dmips-mhz = < 165 capacity-dmips-mhz = <1024>;
174 dynamic-power-coeffici <<
175 next-level-cache = <&L 166 next-level-cache = <&L2_500>;
176 power-domains = <&CPU_ 167 power-domains = <&CPU_PD5>;
177 power-domain-names = " 168 power-domain-names = "psci";
178 qcom,freq-domain = <&c 169 qcom,freq-domain = <&cpufreq_hw 1>;
179 operating-points-v2 = 170 operating-points-v2 = <&cpu4_opp_table>;
180 interconnects = <&epss 171 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
181 #cooling-cells = <2>; 172 #cooling-cells = <2>;
182 L2_500: l2-cache { 173 L2_500: l2-cache {
183 compatible = " 174 compatible = "cache";
184 cache-level = 175 cache-level = <2>;
185 cache-unified; 176 cache-unified;
186 next-level-cac 177 next-level-cache = <&L3_0>;
187 }; 178 };
188 }; 179 };
189 180
190 CPU6: cpu@600 { 181 CPU6: cpu@600 {
191 device_type = "cpu"; 182 device_type = "cpu";
192 compatible = "arm,cort 183 compatible = "arm,cortex-x1c";
193 reg = <0x0 0x600>; 184 reg = <0x0 0x600>;
194 clocks = <&cpufreq_hw 185 clocks = <&cpufreq_hw 1>;
195 enable-method = "psci" 186 enable-method = "psci";
196 capacity-dmips-mhz = < 187 capacity-dmips-mhz = <1024>;
197 dynamic-power-coeffici <<
198 next-level-cache = <&L 188 next-level-cache = <&L2_600>;
199 power-domains = <&CPU_ 189 power-domains = <&CPU_PD6>;
200 power-domain-names = " 190 power-domain-names = "psci";
201 qcom,freq-domain = <&c 191 qcom,freq-domain = <&cpufreq_hw 1>;
202 operating-points-v2 = 192 operating-points-v2 = <&cpu4_opp_table>;
203 interconnects = <&epss 193 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
204 #cooling-cells = <2>; 194 #cooling-cells = <2>;
205 L2_600: l2-cache { 195 L2_600: l2-cache {
206 compatible = " 196 compatible = "cache";
207 cache-level = 197 cache-level = <2>;
208 cache-unified; 198 cache-unified;
209 next-level-cac 199 next-level-cache = <&L3_0>;
210 }; 200 };
211 }; 201 };
212 202
213 CPU7: cpu@700 { 203 CPU7: cpu@700 {
214 device_type = "cpu"; 204 device_type = "cpu";
215 compatible = "arm,cort 205 compatible = "arm,cortex-x1c";
216 reg = <0x0 0x700>; 206 reg = <0x0 0x700>;
217 clocks = <&cpufreq_hw 207 clocks = <&cpufreq_hw 1>;
218 enable-method = "psci" 208 enable-method = "psci";
219 capacity-dmips-mhz = < 209 capacity-dmips-mhz = <1024>;
220 dynamic-power-coeffici <<
221 next-level-cache = <&L 210 next-level-cache = <&L2_700>;
222 power-domains = <&CPU_ 211 power-domains = <&CPU_PD7>;
223 power-domain-names = " 212 power-domain-names = "psci";
224 qcom,freq-domain = <&c 213 qcom,freq-domain = <&cpufreq_hw 1>;
225 operating-points-v2 = 214 operating-points-v2 = <&cpu4_opp_table>;
226 interconnects = <&epss 215 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
227 #cooling-cells = <2>; 216 #cooling-cells = <2>;
228 L2_700: l2-cache { 217 L2_700: l2-cache {
229 compatible = " 218 compatible = "cache";
230 cache-level = 219 cache-level = <2>;
231 cache-unified; 220 cache-unified;
232 next-level-cac 221 next-level-cache = <&L3_0>;
233 }; 222 };
234 }; 223 };
235 224
236 cpu-map { 225 cpu-map {
237 cluster0 { 226 cluster0 {
238 core0 { 227 core0 {
239 cpu = 228 cpu = <&CPU0>;
240 }; 229 };
241 230
242 core1 { 231 core1 {
243 cpu = 232 cpu = <&CPU1>;
244 }; 233 };
245 234
246 core2 { 235 core2 {
247 cpu = 236 cpu = <&CPU2>;
248 }; 237 };
249 238
250 core3 { 239 core3 {
251 cpu = 240 cpu = <&CPU3>;
252 }; 241 };
253 242
254 core4 { 243 core4 {
255 cpu = 244 cpu = <&CPU4>;
256 }; 245 };
257 246
258 core5 { 247 core5 {
259 cpu = 248 cpu = <&CPU5>;
260 }; 249 };
261 250
262 core6 { 251 core6 {
263 cpu = 252 cpu = <&CPU6>;
264 }; 253 };
265 254
266 core7 { 255 core7 {
267 cpu = 256 cpu = <&CPU7>;
268 }; 257 };
269 }; 258 };
270 }; 259 };
271 260
272 idle-states { 261 idle-states {
273 entry-method = "psci"; 262 entry-method = "psci";
274 263
275 LITTLE_CPU_SLEEP_0: cp 264 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
276 compatible = " 265 compatible = "arm,idle-state";
277 idle-state-nam 266 idle-state-name = "little-rail-power-collapse";
278 arm,psci-suspe 267 arm,psci-suspend-param = <0x40000004>;
279 entry-latency- 268 entry-latency-us = <355>;
280 exit-latency-u 269 exit-latency-us = <909>;
281 min-residency- 270 min-residency-us = <3934>;
282 local-timer-st 271 local-timer-stop;
283 }; 272 };
284 273
285 BIG_CPU_SLEEP_0: cpu-s 274 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
286 compatible = " 275 compatible = "arm,idle-state";
287 idle-state-nam 276 idle-state-name = "big-rail-power-collapse";
288 arm,psci-suspe 277 arm,psci-suspend-param = <0x40000004>;
289 entry-latency- 278 entry-latency-us = <241>;
290 exit-latency-u 279 exit-latency-us = <1461>;
291 min-residency- 280 min-residency-us = <4488>;
292 local-timer-st 281 local-timer-stop;
293 }; 282 };
294 }; 283 };
295 284
296 domain-idle-states { 285 domain-idle-states {
297 CLUSTER_SLEEP_0: clust 286 CLUSTER_SLEEP_0: cluster-sleep-0 {
298 compatible = " 287 compatible = "domain-idle-state";
299 arm,psci-suspe 288 arm,psci-suspend-param = <0x4100c344>;
300 entry-latency- 289 entry-latency-us = <3263>;
301 exit-latency-u 290 exit-latency-us = <6562>;
302 min-residency- 291 min-residency-us = <9987>;
303 }; 292 };
304 }; 293 };
305 }; 294 };
306 295
307 firmware { 296 firmware {
308 scm: scm { 297 scm: scm {
309 compatible = "qcom,scm 298 compatible = "qcom,scm-sc8280xp", "qcom,scm";
310 interconnects = <&aggr 299 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
311 qcom,dload-mode = <&tc <<
312 }; 300 };
313 }; 301 };
314 302
315 aggre1_noc: interconnect-aggre1-noc { 303 aggre1_noc: interconnect-aggre1-noc {
316 compatible = "qcom,sc8280xp-ag 304 compatible = "qcom,sc8280xp-aggre1-noc";
317 #interconnect-cells = <2>; 305 #interconnect-cells = <2>;
318 qcom,bcm-voters = <&apps_bcm_v 306 qcom,bcm-voters = <&apps_bcm_voter>;
319 }; 307 };
320 308
321 aggre2_noc: interconnect-aggre2-noc { 309 aggre2_noc: interconnect-aggre2-noc {
322 compatible = "qcom,sc8280xp-ag 310 compatible = "qcom,sc8280xp-aggre2-noc";
323 #interconnect-cells = <2>; 311 #interconnect-cells = <2>;
324 qcom,bcm-voters = <&apps_bcm_v 312 qcom,bcm-voters = <&apps_bcm_voter>;
325 }; 313 };
326 314
327 clk_virt: interconnect-clk-virt { 315 clk_virt: interconnect-clk-virt {
328 compatible = "qcom,sc8280xp-cl 316 compatible = "qcom,sc8280xp-clk-virt";
329 #interconnect-cells = <2>; 317 #interconnect-cells = <2>;
330 qcom,bcm-voters = <&apps_bcm_v 318 qcom,bcm-voters = <&apps_bcm_voter>;
331 }; 319 };
332 320
333 config_noc: interconnect-config-noc { 321 config_noc: interconnect-config-noc {
334 compatible = "qcom,sc8280xp-co 322 compatible = "qcom,sc8280xp-config-noc";
335 #interconnect-cells = <2>; 323 #interconnect-cells = <2>;
336 qcom,bcm-voters = <&apps_bcm_v 324 qcom,bcm-voters = <&apps_bcm_voter>;
337 }; 325 };
338 326
339 dc_noc: interconnect-dc-noc { 327 dc_noc: interconnect-dc-noc {
340 compatible = "qcom,sc8280xp-dc 328 compatible = "qcom,sc8280xp-dc-noc";
341 #interconnect-cells = <2>; 329 #interconnect-cells = <2>;
342 qcom,bcm-voters = <&apps_bcm_v 330 qcom,bcm-voters = <&apps_bcm_voter>;
343 }; 331 };
344 332
345 gem_noc: interconnect-gem-noc { 333 gem_noc: interconnect-gem-noc {
346 compatible = "qcom,sc8280xp-ge 334 compatible = "qcom,sc8280xp-gem-noc";
347 #interconnect-cells = <2>; 335 #interconnect-cells = <2>;
348 qcom,bcm-voters = <&apps_bcm_v 336 qcom,bcm-voters = <&apps_bcm_voter>;
349 }; 337 };
350 338
351 lpass_noc: interconnect-lpass-ag-noc { 339 lpass_noc: interconnect-lpass-ag-noc {
352 compatible = "qcom,sc8280xp-lp 340 compatible = "qcom,sc8280xp-lpass-ag-noc";
353 #interconnect-cells = <2>; 341 #interconnect-cells = <2>;
354 qcom,bcm-voters = <&apps_bcm_v 342 qcom,bcm-voters = <&apps_bcm_voter>;
355 }; 343 };
356 344
357 mc_virt: interconnect-mc-virt { 345 mc_virt: interconnect-mc-virt {
358 compatible = "qcom,sc8280xp-mc 346 compatible = "qcom,sc8280xp-mc-virt";
359 #interconnect-cells = <2>; 347 #interconnect-cells = <2>;
360 qcom,bcm-voters = <&apps_bcm_v 348 qcom,bcm-voters = <&apps_bcm_voter>;
361 }; 349 };
362 350
363 mmss_noc: interconnect-mmss-noc { 351 mmss_noc: interconnect-mmss-noc {
364 compatible = "qcom,sc8280xp-mm 352 compatible = "qcom,sc8280xp-mmss-noc";
365 #interconnect-cells = <2>; 353 #interconnect-cells = <2>;
366 qcom,bcm-voters = <&apps_bcm_v 354 qcom,bcm-voters = <&apps_bcm_voter>;
367 }; 355 };
368 356
369 nspa_noc: interconnect-nspa-noc { 357 nspa_noc: interconnect-nspa-noc {
370 compatible = "qcom,sc8280xp-ns 358 compatible = "qcom,sc8280xp-nspa-noc";
371 #interconnect-cells = <2>; 359 #interconnect-cells = <2>;
372 qcom,bcm-voters = <&apps_bcm_v 360 qcom,bcm-voters = <&apps_bcm_voter>;
373 }; 361 };
374 362
375 nspb_noc: interconnect-nspb-noc { 363 nspb_noc: interconnect-nspb-noc {
376 compatible = "qcom,sc8280xp-ns 364 compatible = "qcom,sc8280xp-nspb-noc";
377 #interconnect-cells = <2>; 365 #interconnect-cells = <2>;
378 qcom,bcm-voters = <&apps_bcm_v 366 qcom,bcm-voters = <&apps_bcm_voter>;
379 }; 367 };
380 368
381 system_noc: interconnect-system-noc { 369 system_noc: interconnect-system-noc {
382 compatible = "qcom,sc8280xp-sy 370 compatible = "qcom,sc8280xp-system-noc";
383 #interconnect-cells = <2>; 371 #interconnect-cells = <2>;
384 qcom,bcm-voters = <&apps_bcm_v 372 qcom,bcm-voters = <&apps_bcm_voter>;
385 }; 373 };
386 374
387 memory@80000000 { 375 memory@80000000 {
388 device_type = "memory"; 376 device_type = "memory";
389 /* We expect the bootloader to 377 /* We expect the bootloader to fill in the size */
390 reg = <0x0 0x80000000 0x0 0x0> 378 reg = <0x0 0x80000000 0x0 0x0>;
391 }; 379 };
392 380
393 cpu0_opp_table: opp-table-cpu0 { 381 cpu0_opp_table: opp-table-cpu0 {
394 compatible = "operating-points 382 compatible = "operating-points-v2";
395 opp-shared; 383 opp-shared;
396 384
397 opp-300000000 { 385 opp-300000000 {
398 opp-hz = /bits/ 64 <30 386 opp-hz = /bits/ 64 <300000000>;
399 opp-peak-kBps = <(3000 387 opp-peak-kBps = <(300000 * 32)>;
400 }; 388 };
401 opp-403200000 { 389 opp-403200000 {
402 opp-hz = /bits/ 64 <40 390 opp-hz = /bits/ 64 <403200000>;
403 opp-peak-kBps = <(3840 391 opp-peak-kBps = <(384000 * 32)>;
404 }; 392 };
405 opp-499200000 { 393 opp-499200000 {
406 opp-hz = /bits/ 64 <49 394 opp-hz = /bits/ 64 <499200000>;
407 opp-peak-kBps = <(4800 395 opp-peak-kBps = <(480000 * 32)>;
408 }; 396 };
409 opp-595200000 { 397 opp-595200000 {
410 opp-hz = /bits/ 64 <59 398 opp-hz = /bits/ 64 <595200000>;
411 opp-peak-kBps = <(5760 399 opp-peak-kBps = <(576000 * 32)>;
412 }; 400 };
413 opp-691200000 { 401 opp-691200000 {
414 opp-hz = /bits/ 64 <69 402 opp-hz = /bits/ 64 <691200000>;
415 opp-peak-kBps = <(6720 403 opp-peak-kBps = <(672000 * 32)>;
416 }; 404 };
417 opp-806400000 { 405 opp-806400000 {
418 opp-hz = /bits/ 64 <80 406 opp-hz = /bits/ 64 <806400000>;
419 opp-peak-kBps = <(7680 407 opp-peak-kBps = <(768000 * 32)>;
420 }; 408 };
421 opp-902400000 { 409 opp-902400000 {
422 opp-hz = /bits/ 64 <90 410 opp-hz = /bits/ 64 <902400000>;
423 opp-peak-kBps = <(8640 411 opp-peak-kBps = <(864000 * 32)>;
424 }; 412 };
425 opp-1017600000 { 413 opp-1017600000 {
426 opp-hz = /bits/ 64 <10 414 opp-hz = /bits/ 64 <1017600000>;
427 opp-peak-kBps = <(9600 415 opp-peak-kBps = <(960000 * 32)>;
428 }; 416 };
429 opp-1113600000 { 417 opp-1113600000 {
430 opp-hz = /bits/ 64 <11 418 opp-hz = /bits/ 64 <1113600000>;
431 opp-peak-kBps = <(1075 419 opp-peak-kBps = <(1075200 * 32)>;
432 }; 420 };
433 opp-1209600000 { 421 opp-1209600000 {
434 opp-hz = /bits/ 64 <12 422 opp-hz = /bits/ 64 <1209600000>;
435 opp-peak-kBps = <(1171 423 opp-peak-kBps = <(1171200 * 32)>;
436 }; 424 };
437 opp-1324800000 { 425 opp-1324800000 {
438 opp-hz = /bits/ 64 <13 426 opp-hz = /bits/ 64 <1324800000>;
439 opp-peak-kBps = <(1267 427 opp-peak-kBps = <(1267200 * 32)>;
440 }; 428 };
441 opp-1440000000 { 429 opp-1440000000 {
442 opp-hz = /bits/ 64 <14 430 opp-hz = /bits/ 64 <1440000000>;
443 opp-peak-kBps = <(1363 431 opp-peak-kBps = <(1363200 * 32)>;
444 }; 432 };
445 opp-1555200000 { 433 opp-1555200000 {
446 opp-hz = /bits/ 64 <15 434 opp-hz = /bits/ 64 <1555200000>;
447 opp-peak-kBps = <(1536 435 opp-peak-kBps = <(1536000 * 32)>;
448 }; 436 };
449 opp-1670400000 { 437 opp-1670400000 {
450 opp-hz = /bits/ 64 <16 438 opp-hz = /bits/ 64 <1670400000>;
451 opp-peak-kBps = <(1612 439 opp-peak-kBps = <(1612800 * 32)>;
452 }; 440 };
453 opp-1785600000 { 441 opp-1785600000 {
454 opp-hz = /bits/ 64 <17 442 opp-hz = /bits/ 64 <1785600000>;
455 opp-peak-kBps = <(1689 443 opp-peak-kBps = <(1689600 * 32)>;
456 }; 444 };
457 opp-1881600000 { 445 opp-1881600000 {
458 opp-hz = /bits/ 64 <18 446 opp-hz = /bits/ 64 <1881600000>;
459 opp-peak-kBps = <(1689 447 opp-peak-kBps = <(1689600 * 32)>;
460 }; 448 };
461 opp-1996800000 { 449 opp-1996800000 {
462 opp-hz = /bits/ 64 <19 450 opp-hz = /bits/ 64 <1996800000>;
463 opp-peak-kBps = <(1689 451 opp-peak-kBps = <(1689600 * 32)>;
464 }; 452 };
465 opp-2112000000 { 453 opp-2112000000 {
466 opp-hz = /bits/ 64 <21 454 opp-hz = /bits/ 64 <2112000000>;
467 opp-peak-kBps = <(1689 455 opp-peak-kBps = <(1689600 * 32)>;
468 }; 456 };
469 opp-2227200000 { 457 opp-2227200000 {
470 opp-hz = /bits/ 64 <22 458 opp-hz = /bits/ 64 <2227200000>;
471 opp-peak-kBps = <(1689 459 opp-peak-kBps = <(1689600 * 32)>;
472 }; 460 };
473 opp-2342400000 { 461 opp-2342400000 {
474 opp-hz = /bits/ 64 <23 462 opp-hz = /bits/ 64 <2342400000>;
475 opp-peak-kBps = <(1689 463 opp-peak-kBps = <(1689600 * 32)>;
476 }; 464 };
477 opp-2438400000 { 465 opp-2438400000 {
478 opp-hz = /bits/ 64 <24 466 opp-hz = /bits/ 64 <2438400000>;
479 opp-peak-kBps = <(1689 467 opp-peak-kBps = <(1689600 * 32)>;
480 }; 468 };
481 }; 469 };
482 470
483 cpu4_opp_table: opp-table-cpu4 { 471 cpu4_opp_table: opp-table-cpu4 {
484 compatible = "operating-points 472 compatible = "operating-points-v2";
485 opp-shared; 473 opp-shared;
486 474
487 opp-825600000 { 475 opp-825600000 {
488 opp-hz = /bits/ 64 <82 476 opp-hz = /bits/ 64 <825600000>;
489 opp-peak-kBps = <(7680 477 opp-peak-kBps = <(768000 * 32)>;
490 }; 478 };
491 opp-940800000 { 479 opp-940800000 {
492 opp-hz = /bits/ 64 <94 480 opp-hz = /bits/ 64 <940800000>;
493 opp-peak-kBps = <(8640 481 opp-peak-kBps = <(864000 * 32)>;
494 }; 482 };
495 opp-1056000000 { 483 opp-1056000000 {
496 opp-hz = /bits/ 64 <10 484 opp-hz = /bits/ 64 <1056000000>;
497 opp-peak-kBps = <(9600 485 opp-peak-kBps = <(960000 * 32)>;
498 }; 486 };
499 opp-1171200000 { 487 opp-1171200000 {
500 opp-hz = /bits/ 64 <11 488 opp-hz = /bits/ 64 <1171200000>;
501 opp-peak-kBps = <(1171 489 opp-peak-kBps = <(1171200 * 32)>;
502 }; 490 };
503 opp-1286400000 { 491 opp-1286400000 {
504 opp-hz = /bits/ 64 <12 492 opp-hz = /bits/ 64 <1286400000>;
505 opp-peak-kBps = <(1267 493 opp-peak-kBps = <(1267200 * 32)>;
506 }; 494 };
507 opp-1401600000 { 495 opp-1401600000 {
508 opp-hz = /bits/ 64 <14 496 opp-hz = /bits/ 64 <1401600000>;
509 opp-peak-kBps = <(1363 497 opp-peak-kBps = <(1363200 * 32)>;
510 }; 498 };
511 opp-1516800000 { 499 opp-1516800000 {
512 opp-hz = /bits/ 64 <15 500 opp-hz = /bits/ 64 <1516800000>;
513 opp-peak-kBps = <(1459 501 opp-peak-kBps = <(1459200 * 32)>;
514 }; 502 };
515 opp-1632000000 { 503 opp-1632000000 {
516 opp-hz = /bits/ 64 <16 504 opp-hz = /bits/ 64 <1632000000>;
517 opp-peak-kBps = <(1612 505 opp-peak-kBps = <(1612800 * 32)>;
518 }; 506 };
519 opp-1747200000 { 507 opp-1747200000 {
520 opp-hz = /bits/ 64 <17 508 opp-hz = /bits/ 64 <1747200000>;
521 opp-peak-kBps = <(1689 509 opp-peak-kBps = <(1689600 * 32)>;
522 }; 510 };
523 opp-1862400000 { 511 opp-1862400000 {
524 opp-hz = /bits/ 64 <18 512 opp-hz = /bits/ 64 <1862400000>;
525 opp-peak-kBps = <(1689 513 opp-peak-kBps = <(1689600 * 32)>;
526 }; 514 };
527 opp-1977600000 { 515 opp-1977600000 {
528 opp-hz = /bits/ 64 <19 516 opp-hz = /bits/ 64 <1977600000>;
529 opp-peak-kBps = <(1689 517 opp-peak-kBps = <(1689600 * 32)>;
530 }; 518 };
531 opp-2073600000 { 519 opp-2073600000 {
532 opp-hz = /bits/ 64 <20 520 opp-hz = /bits/ 64 <2073600000>;
533 opp-peak-kBps = <(1689 521 opp-peak-kBps = <(1689600 * 32)>;
534 }; 522 };
535 opp-2169600000 { 523 opp-2169600000 {
536 opp-hz = /bits/ 64 <21 524 opp-hz = /bits/ 64 <2169600000>;
537 opp-peak-kBps = <(1689 525 opp-peak-kBps = <(1689600 * 32)>;
538 }; 526 };
539 opp-2284800000 { 527 opp-2284800000 {
540 opp-hz = /bits/ 64 <22 528 opp-hz = /bits/ 64 <2284800000>;
541 opp-peak-kBps = <(1689 529 opp-peak-kBps = <(1689600 * 32)>;
542 }; 530 };
543 opp-2400000000 { 531 opp-2400000000 {
544 opp-hz = /bits/ 64 <24 532 opp-hz = /bits/ 64 <2400000000>;
545 opp-peak-kBps = <(1689 533 opp-peak-kBps = <(1689600 * 32)>;
546 }; 534 };
547 opp-2496000000 { 535 opp-2496000000 {
548 opp-hz = /bits/ 64 <24 536 opp-hz = /bits/ 64 <2496000000>;
549 opp-peak-kBps = <(1689 537 opp-peak-kBps = <(1689600 * 32)>;
550 }; 538 };
551 opp-2592000000 { 539 opp-2592000000 {
552 opp-hz = /bits/ 64 <25 540 opp-hz = /bits/ 64 <2592000000>;
553 opp-peak-kBps = <(1689 541 opp-peak-kBps = <(1689600 * 32)>;
554 }; 542 };
555 opp-2688000000 { 543 opp-2688000000 {
556 opp-hz = /bits/ 64 <26 544 opp-hz = /bits/ 64 <2688000000>;
557 opp-peak-kBps = <(1689 545 opp-peak-kBps = <(1689600 * 32)>;
558 }; 546 };
559 opp-2803200000 { 547 opp-2803200000 {
560 opp-hz = /bits/ 64 <28 548 opp-hz = /bits/ 64 <2803200000>;
561 opp-peak-kBps = <(1689 549 opp-peak-kBps = <(1689600 * 32)>;
562 }; 550 };
563 opp-2899200000 { 551 opp-2899200000 {
564 opp-hz = /bits/ 64 <28 552 opp-hz = /bits/ 64 <2899200000>;
565 opp-peak-kBps = <(1689 553 opp-peak-kBps = <(1689600 * 32)>;
566 }; 554 };
567 opp-2995200000 { 555 opp-2995200000 {
568 opp-hz = /bits/ 64 <29 556 opp-hz = /bits/ 64 <2995200000>;
569 opp-peak-kBps = <(1689 557 opp-peak-kBps = <(1689600 * 32)>;
570 }; 558 };
571 }; 559 };
572 560
573 qup_opp_table_100mhz: opp-table-qup100 561 qup_opp_table_100mhz: opp-table-qup100mhz {
574 compatible = "operating-points 562 compatible = "operating-points-v2";
575 563
576 opp-75000000 { 564 opp-75000000 {
577 opp-hz = /bits/ 64 <75 565 opp-hz = /bits/ 64 <75000000>;
578 required-opps = <&rpmh 566 required-opps = <&rpmhpd_opp_low_svs>;
579 }; 567 };
580 568
581 opp-100000000 { 569 opp-100000000 {
582 opp-hz = /bits/ 64 <10 570 opp-hz = /bits/ 64 <100000000>;
583 required-opps = <&rpmh 571 required-opps = <&rpmhpd_opp_svs>;
584 }; 572 };
585 }; 573 };
586 574
587 pmu { 575 pmu {
588 compatible = "arm,armv8-pmuv3" 576 compatible = "arm,armv8-pmuv3";
589 interrupts = <GIC_PPI 7 IRQ_TY 577 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
590 }; 578 };
591 579
592 psci { 580 psci {
593 compatible = "arm,psci-1.0"; 581 compatible = "arm,psci-1.0";
594 method = "smc"; 582 method = "smc";
595 583
596 CPU_PD0: power-domain-cpu0 { 584 CPU_PD0: power-domain-cpu0 {
597 #power-domain-cells = 585 #power-domain-cells = <0>;
598 power-domains = <&CLUS 586 power-domains = <&CLUSTER_PD>;
599 domain-idle-states = < 587 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
600 }; 588 };
601 589
602 CPU_PD1: power-domain-cpu1 { 590 CPU_PD1: power-domain-cpu1 {
603 #power-domain-cells = 591 #power-domain-cells = <0>;
604 power-domains = <&CLUS 592 power-domains = <&CLUSTER_PD>;
605 domain-idle-states = < 593 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
606 }; 594 };
607 595
608 CPU_PD2: power-domain-cpu2 { 596 CPU_PD2: power-domain-cpu2 {
609 #power-domain-cells = 597 #power-domain-cells = <0>;
610 power-domains = <&CLUS 598 power-domains = <&CLUSTER_PD>;
611 domain-idle-states = < 599 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
612 }; 600 };
613 601
614 CPU_PD3: power-domain-cpu3 { 602 CPU_PD3: power-domain-cpu3 {
615 #power-domain-cells = 603 #power-domain-cells = <0>;
616 power-domains = <&CLUS 604 power-domains = <&CLUSTER_PD>;
617 domain-idle-states = < 605 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
618 }; 606 };
619 607
620 CPU_PD4: power-domain-cpu4 { 608 CPU_PD4: power-domain-cpu4 {
621 #power-domain-cells = 609 #power-domain-cells = <0>;
622 power-domains = <&CLUS 610 power-domains = <&CLUSTER_PD>;
623 domain-idle-states = < 611 domain-idle-states = <&BIG_CPU_SLEEP_0>;
624 }; 612 };
625 613
626 CPU_PD5: power-domain-cpu5 { 614 CPU_PD5: power-domain-cpu5 {
627 #power-domain-cells = 615 #power-domain-cells = <0>;
628 power-domains = <&CLUS 616 power-domains = <&CLUSTER_PD>;
629 domain-idle-states = < 617 domain-idle-states = <&BIG_CPU_SLEEP_0>;
630 }; 618 };
631 619
632 CPU_PD6: power-domain-cpu6 { 620 CPU_PD6: power-domain-cpu6 {
633 #power-domain-cells = 621 #power-domain-cells = <0>;
634 power-domains = <&CLUS 622 power-domains = <&CLUSTER_PD>;
635 domain-idle-states = < 623 domain-idle-states = <&BIG_CPU_SLEEP_0>;
636 }; 624 };
637 625
638 CPU_PD7: power-domain-cpu7 { 626 CPU_PD7: power-domain-cpu7 {
639 #power-domain-cells = 627 #power-domain-cells = <0>;
640 power-domains = <&CLUS 628 power-domains = <&CLUSTER_PD>;
641 domain-idle-states = < 629 domain-idle-states = <&BIG_CPU_SLEEP_0>;
642 }; 630 };
643 631
644 CLUSTER_PD: power-domain-cpu-c 632 CLUSTER_PD: power-domain-cpu-cluster0 {
645 #power-domain-cells = 633 #power-domain-cells = <0>;
646 domain-idle-states = < 634 domain-idle-states = <&CLUSTER_SLEEP_0>;
647 }; 635 };
648 }; 636 };
649 637
650 reserved-memory { 638 reserved-memory {
651 #address-cells = <2>; 639 #address-cells = <2>;
652 #size-cells = <2>; 640 #size-cells = <2>;
653 ranges; 641 ranges;
654 642
655 reserved-region@80000000 { 643 reserved-region@80000000 {
656 reg = <0 0x80000000 0 644 reg = <0 0x80000000 0 0x860000>;
657 no-map; 645 no-map;
658 }; 646 };
659 647
660 cmd_db: cmd-db-region@80860000 648 cmd_db: cmd-db-region@80860000 {
661 compatible = "qcom,cmd 649 compatible = "qcom,cmd-db";
662 reg = <0 0x80860000 0 650 reg = <0 0x80860000 0 0x20000>;
663 no-map; 651 no-map;
664 }; 652 };
665 653
666 reserved-region@80880000 { 654 reserved-region@80880000 {
667 reg = <0 0x80880000 0 655 reg = <0 0x80880000 0 0x80000>;
668 no-map; 656 no-map;
669 }; 657 };
670 658
671 smem_mem: smem-region@80900000 659 smem_mem: smem-region@80900000 {
672 compatible = "qcom,sme 660 compatible = "qcom,smem";
673 reg = <0 0x80900000 0 661 reg = <0 0x80900000 0 0x200000>;
674 no-map; 662 no-map;
675 hwlocks = <&tcsr_mutex 663 hwlocks = <&tcsr_mutex 3>;
676 }; 664 };
677 665
678 reserved-region@80b00000 { 666 reserved-region@80b00000 {
679 reg = <0 0x80b00000 0 667 reg = <0 0x80b00000 0 0x100000>;
680 no-map; 668 no-map;
681 }; 669 };
682 670
683 reserved-region@83b00000 { 671 reserved-region@83b00000 {
684 reg = <0 0x83b00000 0 672 reg = <0 0x83b00000 0 0x1700000>;
685 no-map; 673 no-map;
686 }; 674 };
687 675
688 reserved-region@85b00000 { 676 reserved-region@85b00000 {
689 reg = <0 0x85b00000 0 677 reg = <0 0x85b00000 0 0xc00000>;
690 no-map; 678 no-map;
691 }; 679 };
692 680
693 pil_adsp_mem: adsp-region@86c0 681 pil_adsp_mem: adsp-region@86c00000 {
694 reg = <0 0x86c00000 0 682 reg = <0 0x86c00000 0 0x2000000>;
695 no-map; 683 no-map;
696 }; 684 };
697 685
698 pil_nsp0_mem: cdsp0-region@8a1 686 pil_nsp0_mem: cdsp0-region@8a100000 {
699 reg = <0 0x8a100000 0 687 reg = <0 0x8a100000 0 0x1e00000>;
700 no-map; 688 no-map;
701 }; 689 };
702 690
703 pil_nsp1_mem: cdsp1-region@8c6 691 pil_nsp1_mem: cdsp1-region@8c600000 {
704 reg = <0 0x8c600000 0 692 reg = <0 0x8c600000 0 0x1e00000>;
705 no-map; 693 no-map;
706 }; 694 };
707 695
708 reserved-region@aeb00000 { 696 reserved-region@aeb00000 {
709 reg = <0 0xaeb00000 0 697 reg = <0 0xaeb00000 0 0x16600000>;
710 no-map; 698 no-map;
711 }; 699 };
712 }; 700 };
713 701
714 smp2p-adsp { 702 smp2p-adsp {
715 compatible = "qcom,smp2p"; 703 compatible = "qcom,smp2p";
716 qcom,smem = <443>, <429>; 704 qcom,smem = <443>, <429>;
717 interrupts-extended = <&ipcc I 705 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
718 I 706 IPCC_MPROC_SIGNAL_SMP2P
719 I 707 IRQ_TYPE_EDGE_RISING>;
720 mboxes = <&ipcc IPCC_CLIENT_LP 708 mboxes = <&ipcc IPCC_CLIENT_LPASS
721 IPCC_MPROC_SIG 709 IPCC_MPROC_SIGNAL_SMP2P>;
722 710
723 qcom,local-pid = <0>; 711 qcom,local-pid = <0>;
724 qcom,remote-pid = <2>; 712 qcom,remote-pid = <2>;
725 713
726 smp2p_adsp_out: master-kernel 714 smp2p_adsp_out: master-kernel {
727 qcom,entry-name = "mas 715 qcom,entry-name = "master-kernel";
728 #qcom,smem-state-cells 716 #qcom,smem-state-cells = <1>;
729 }; 717 };
730 718
731 smp2p_adsp_in: slave-kernel { 719 smp2p_adsp_in: slave-kernel {
732 qcom,entry-name = "sla 720 qcom,entry-name = "slave-kernel";
733 interrupt-controller; 721 interrupt-controller;
734 #interrupt-cells = <2> 722 #interrupt-cells = <2>;
735 }; 723 };
736 }; 724 };
737 725
738 smp2p-nsp0 { 726 smp2p-nsp0 {
739 compatible = "qcom,smp2p"; 727 compatible = "qcom,smp2p";
740 qcom,smem = <94>, <432>; 728 qcom,smem = <94>, <432>;
741 interrupts-extended = <&ipcc I 729 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
742 I 730 IPCC_MPROC_SIGNAL_SMP2P
743 I 731 IRQ_TYPE_EDGE_RISING>;
744 mboxes = <&ipcc IPCC_CLIENT_CD 732 mboxes = <&ipcc IPCC_CLIENT_CDSP
745 IPCC_MPROC_SIG 733 IPCC_MPROC_SIGNAL_SMP2P>;
746 734
747 qcom,local-pid = <0>; 735 qcom,local-pid = <0>;
748 qcom,remote-pid = <5>; 736 qcom,remote-pid = <5>;
749 737
750 smp2p_nsp0_out: master-kernel 738 smp2p_nsp0_out: master-kernel {
751 qcom,entry-name = "mas 739 qcom,entry-name = "master-kernel";
752 #qcom,smem-state-cells 740 #qcom,smem-state-cells = <1>;
753 }; 741 };
754 742
755 smp2p_nsp0_in: slave-kernel { 743 smp2p_nsp0_in: slave-kernel {
756 qcom,entry-name = "sla 744 qcom,entry-name = "slave-kernel";
757 interrupt-controller; 745 interrupt-controller;
758 #interrupt-cells = <2> 746 #interrupt-cells = <2>;
759 }; 747 };
760 }; 748 };
761 749
762 smp2p-nsp1 { 750 smp2p-nsp1 {
763 compatible = "qcom,smp2p"; 751 compatible = "qcom,smp2p";
764 qcom,smem = <617>, <616>; 752 qcom,smem = <617>, <616>;
765 interrupts-extended = <&ipcc I 753 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1
766 I 754 IPCC_MPROC_SIGNAL_SMP2P
767 I 755 IRQ_TYPE_EDGE_RISING>;
768 mboxes = <&ipcc IPCC_CLIENT_NS 756 mboxes = <&ipcc IPCC_CLIENT_NSP1
769 IPCC_MPROC_SIG 757 IPCC_MPROC_SIGNAL_SMP2P>;
770 758
771 qcom,local-pid = <0>; 759 qcom,local-pid = <0>;
772 qcom,remote-pid = <12>; 760 qcom,remote-pid = <12>;
773 761
774 smp2p_nsp1_out: master-kernel 762 smp2p_nsp1_out: master-kernel {
775 qcom,entry-name = "mas 763 qcom,entry-name = "master-kernel";
776 #qcom,smem-state-cells 764 #qcom,smem-state-cells = <1>;
777 }; 765 };
778 766
779 smp2p_nsp1_in: slave-kernel { 767 smp2p_nsp1_in: slave-kernel {
780 qcom,entry-name = "sla 768 qcom,entry-name = "slave-kernel";
781 interrupt-controller; 769 interrupt-controller;
782 #interrupt-cells = <2> 770 #interrupt-cells = <2>;
783 }; 771 };
784 }; 772 };
785 773
786 soc: soc@0 { 774 soc: soc@0 {
787 compatible = "simple-bus"; 775 compatible = "simple-bus";
788 #address-cells = <2>; 776 #address-cells = <2>;
789 #size-cells = <2>; 777 #size-cells = <2>;
790 ranges = <0 0 0 0 0x10 0>; 778 ranges = <0 0 0 0 0x10 0>;
791 dma-ranges = <0 0 0 0 0x10 0>; 779 dma-ranges = <0 0 0 0 0x10 0>;
792 780
793 ethernet0: ethernet@20000 { <<
794 compatible = "qcom,sc8 <<
795 reg = <0x0 0x00020000 <<
796 <0x0 0x00036000 <<
797 reg-names = "stmmaceth <<
798 <<
799 clocks = <&gcc GCC_EMA <<
800 <&gcc GCC_EMA <<
801 <&gcc GCC_EMA <<
802 <&gcc GCC_EMA <<
803 clock-names = "stmmace <<
804 "pclk", <<
805 "ptp_ref <<
806 "rgmii"; <<
807 <<
808 interrupts = <GIC_SPI <<
809 <GIC_SPI <<
810 interrupt-names = "mac <<
811 <<
812 iommus = <&apps_smmu 0 <<
813 power-domains = <&gcc <<
814 <<
815 snps,tso; <<
816 snps,pbl = <32>; <<
817 rx-fifo-depth = <4096> <<
818 tx-fifo-depth = <4096> <<
819 <<
820 status = "disabled"; <<
821 }; <<
822 <<
823 gcc: clock-controller@100000 { 781 gcc: clock-controller@100000 {
824 compatible = "qcom,gcc 782 compatible = "qcom,gcc-sc8280xp";
825 reg = <0x0 0x00100000 783 reg = <0x0 0x00100000 0x0 0x1f0000>;
826 #clock-cells = <1>; 784 #clock-cells = <1>;
827 #reset-cells = <1>; 785 #reset-cells = <1>;
828 #power-domain-cells = 786 #power-domain-cells = <1>;
829 clocks = <&rpmhcc RPMH 787 clocks = <&rpmhcc RPMH_CXO_CLK>,
830 <&sleep_clk>, 788 <&sleep_clk>,
831 <0>, 789 <0>,
832 <0>, 790 <0>,
833 <0>, 791 <0>,
834 <0>, 792 <0>,
835 <0>, 793 <0>,
836 <0>, 794 <0>,
837 <&usb_0_qmpph 795 <&usb_0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
838 <0>, 796 <0>,
839 <0>, 797 <0>,
840 <0>, 798 <0>,
841 <0>, 799 <0>,
842 <0>, 800 <0>,
843 <0>, 801 <0>,
844 <0>, 802 <0>,
845 <&usb_1_qmpph 803 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
846 <0>, 804 <0>,
847 <0>, 805 <0>,
848 <0>, 806 <0>,
849 <0>, 807 <0>,
850 <0>, 808 <0>,
851 <0>, 809 <0>,
852 <0>, 810 <0>,
853 <0>, 811 <0>,
854 <0>, 812 <0>,
855 <&pcie2a_phy> 813 <&pcie2a_phy>,
856 <&pcie2b_phy> 814 <&pcie2b_phy>,
857 <&pcie3a_phy> 815 <&pcie3a_phy>,
858 <&pcie3b_phy> 816 <&pcie3b_phy>,
859 <&pcie4_phy>, 817 <&pcie4_phy>,
860 <0>, 818 <0>,
861 <0>; 819 <0>;
862 power-domains = <&rpmh 820 power-domains = <&rpmhpd SC8280XP_CX>;
863 }; 821 };
864 822
865 ipcc: mailbox@408000 { 823 ipcc: mailbox@408000 {
866 compatible = "qcom,sc8 824 compatible = "qcom,sc8280xp-ipcc", "qcom,ipcc";
867 reg = <0 0x00408000 0 825 reg = <0 0x00408000 0 0x1000>;
868 interrupts = <GIC_SPI 826 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
869 interrupt-controller; 827 interrupt-controller;
870 #interrupt-cells = <3> 828 #interrupt-cells = <3>;
871 #mbox-cells = <2>; 829 #mbox-cells = <2>;
872 }; 830 };
873 831
874 qfprom: efuse@784000 { <<
875 compatible = "qcom,sc8 <<
876 reg = <0 0x00784000 0 <<
877 #address-cells = <1>; <<
878 #size-cells = <1>; <<
879 <<
880 gpu_speed_bin: gpu-spe <<
881 reg = <0x18b 0 <<
882 bits = <5 3>; <<
883 }; <<
884 }; <<
885 <<
886 qup2: geniqup@8c0000 { 832 qup2: geniqup@8c0000 {
887 compatible = "qcom,gen 833 compatible = "qcom,geni-se-qup";
888 reg = <0 0x008c0000 0 834 reg = <0 0x008c0000 0 0x2000>;
889 clocks = <&gcc GCC_QUP 835 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
890 <&gcc GCC_QUP 836 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
891 clock-names = "m-ahb", 837 clock-names = "m-ahb", "s-ahb";
892 iommus = <&apps_smmu 0 838 iommus = <&apps_smmu 0xa3 0>;
893 839
894 #address-cells = <2>; 840 #address-cells = <2>;
895 #size-cells = <2>; 841 #size-cells = <2>;
896 ranges; 842 ranges;
897 843
898 status = "disabled"; 844 status = "disabled";
899 845
900 i2c16: i2c@880000 { 846 i2c16: i2c@880000 {
901 compatible = " 847 compatible = "qcom,geni-i2c";
902 reg = <0 0x008 848 reg = <0 0x00880000 0 0x4000>;
903 #address-cells 849 #address-cells = <1>;
904 #size-cells = 850 #size-cells = <0>;
905 clocks = <&gcc 851 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
906 clock-names = 852 clock-names = "se";
907 interrupts = < 853 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
908 power-domains 854 power-domains = <&rpmhpd SC8280XP_CX>;
909 interconnects 855 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
910 856 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
911 857 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
912 interconnect-n 858 interconnect-names = "qup-core", "qup-config", "qup-memory";
913 status = "disa 859 status = "disabled";
914 }; 860 };
915 861
916 spi16: spi@880000 { 862 spi16: spi@880000 {
917 compatible = " 863 compatible = "qcom,geni-spi";
918 reg = <0 0x008 864 reg = <0 0x00880000 0 0x4000>;
919 #address-cells 865 #address-cells = <1>;
920 #size-cells = 866 #size-cells = <0>;
921 clocks = <&gcc 867 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
922 clock-names = 868 clock-names = "se";
923 interrupts = < 869 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
924 power-domains 870 power-domains = <&rpmhpd SC8280XP_CX>;
925 interconnects 871 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
926 872 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
927 873 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
928 interconnect-n 874 interconnect-names = "qup-core", "qup-config", "qup-memory";
929 status = "disa 875 status = "disabled";
930 }; 876 };
931 877
932 i2c17: i2c@884000 { 878 i2c17: i2c@884000 {
933 compatible = " 879 compatible = "qcom,geni-i2c";
934 reg = <0 0x008 880 reg = <0 0x00884000 0 0x4000>;
935 #address-cells 881 #address-cells = <1>;
936 #size-cells = 882 #size-cells = <0>;
937 clocks = <&gcc 883 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
938 clock-names = 884 clock-names = "se";
939 interrupts = < 885 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
940 power-domains 886 power-domains = <&rpmhpd SC8280XP_CX>;
941 interconnects 887 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
942 888 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
943 889 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
944 interconnect-n 890 interconnect-names = "qup-core", "qup-config", "qup-memory";
945 status = "disa 891 status = "disabled";
946 }; 892 };
947 893
948 spi17: spi@884000 { 894 spi17: spi@884000 {
949 compatible = " 895 compatible = "qcom,geni-spi";
950 reg = <0 0x008 896 reg = <0 0x00884000 0 0x4000>;
951 #address-cells 897 #address-cells = <1>;
952 #size-cells = 898 #size-cells = <0>;
953 clocks = <&gcc 899 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
954 clock-names = 900 clock-names = "se";
955 interrupts = < 901 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
956 power-domains 902 power-domains = <&rpmhpd SC8280XP_CX>;
957 interconnects 903 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
958 904 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
959 905 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
960 interconnect-n 906 interconnect-names = "qup-core", "qup-config", "qup-memory";
961 status = "disa 907 status = "disabled";
962 }; 908 };
963 909
964 uart17: serial@884000 910 uart17: serial@884000 {
965 compatible = " 911 compatible = "qcom,geni-uart";
966 reg = <0 0x008 912 reg = <0 0x00884000 0 0x4000>;
967 clocks = <&gcc 913 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
968 clock-names = 914 clock-names = "se";
969 interrupts = < 915 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
970 operating-poin 916 operating-points-v2 = <&qup_opp_table_100mhz>;
971 power-domains 917 power-domains = <&rpmhpd SC8280XP_CX>;
972 interconnects 918 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
973 919 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>;
974 interconnect-n 920 interconnect-names = "qup-core", "qup-config";
975 status = "disa 921 status = "disabled";
976 }; 922 };
977 923
978 i2c18: i2c@888000 { 924 i2c18: i2c@888000 {
979 compatible = " 925 compatible = "qcom,geni-i2c";
980 reg = <0 0x008 926 reg = <0 0x00888000 0 0x4000>;
981 #address-cells 927 #address-cells = <1>;
982 #size-cells = 928 #size-cells = <0>;
983 clocks = <&gcc 929 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
984 clock-names = 930 clock-names = "se";
985 interrupts = < 931 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
986 power-domains 932 power-domains = <&rpmhpd SC8280XP_CX>;
987 interconnects 933 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
988 934 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
989 935 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
990 interconnect-n 936 interconnect-names = "qup-core", "qup-config", "qup-memory";
991 status = "disa 937 status = "disabled";
992 }; 938 };
993 939
994 spi18: spi@888000 { 940 spi18: spi@888000 {
995 compatible = " 941 compatible = "qcom,geni-spi";
996 reg = <0 0x008 942 reg = <0 0x00888000 0 0x4000>;
997 #address-cells 943 #address-cells = <1>;
998 #size-cells = 944 #size-cells = <0>;
999 clocks = <&gcc 945 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1000 clock-names = 946 clock-names = "se";
1001 interrupts = 947 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1002 power-domains 948 power-domains = <&rpmhpd SC8280XP_CX>;
1003 interconnects 949 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1004 950 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1005 951 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1006 interconnect- 952 interconnect-names = "qup-core", "qup-config", "qup-memory";
1007 status = "dis 953 status = "disabled";
1008 }; 954 };
1009 955
1010 i2c19: i2c@88c000 { 956 i2c19: i2c@88c000 {
1011 compatible = 957 compatible = "qcom,geni-i2c";
1012 reg = <0 0x00 958 reg = <0 0x0088c000 0 0x4000>;
1013 #address-cell 959 #address-cells = <1>;
1014 #size-cells = 960 #size-cells = <0>;
1015 clocks = <&gc 961 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1016 clock-names = 962 clock-names = "se";
1017 interrupts = 963 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1018 power-domains 964 power-domains = <&rpmhpd SC8280XP_CX>;
1019 interconnects 965 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1020 966 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1021 967 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1022 interconnect- 968 interconnect-names = "qup-core", "qup-config", "qup-memory";
1023 status = "dis 969 status = "disabled";
1024 }; 970 };
1025 971
1026 spi19: spi@88c000 { 972 spi19: spi@88c000 {
1027 compatible = 973 compatible = "qcom,geni-spi";
1028 reg = <0 0x00 974 reg = <0 0x0088c000 0 0x4000>;
1029 #address-cell 975 #address-cells = <1>;
1030 #size-cells = 976 #size-cells = <0>;
1031 clocks = <&gc 977 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1032 clock-names = 978 clock-names = "se";
1033 interrupts = 979 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1034 power-domains 980 power-domains = <&rpmhpd SC8280XP_CX>;
1035 interconnects 981 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1036 982 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1037 983 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1038 interconnect- 984 interconnect-names = "qup-core", "qup-config", "qup-memory";
1039 status = "dis 985 status = "disabled";
1040 }; 986 };
1041 987
1042 i2c20: i2c@890000 { 988 i2c20: i2c@890000 {
1043 compatible = 989 compatible = "qcom,geni-i2c";
1044 reg = <0 0x00 990 reg = <0 0x00890000 0 0x4000>;
1045 #address-cell 991 #address-cells = <1>;
1046 #size-cells = 992 #size-cells = <0>;
1047 clocks = <&gc 993 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1048 clock-names = 994 clock-names = "se";
1049 interrupts = 995 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1050 power-domains 996 power-domains = <&rpmhpd SC8280XP_CX>;
1051 interconnects 997 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1052 998 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1053 999 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1054 interconnect- 1000 interconnect-names = "qup-core", "qup-config", "qup-memory";
1055 status = "dis 1001 status = "disabled";
1056 }; 1002 };
1057 1003
1058 spi20: spi@890000 { 1004 spi20: spi@890000 {
1059 compatible = 1005 compatible = "qcom,geni-spi";
1060 reg = <0 0x00 1006 reg = <0 0x00890000 0 0x4000>;
1061 #address-cell 1007 #address-cells = <1>;
1062 #size-cells = 1008 #size-cells = <0>;
1063 clocks = <&gc 1009 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1064 clock-names = 1010 clock-names = "se";
1065 interrupts = 1011 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1066 power-domains 1012 power-domains = <&rpmhpd SC8280XP_CX>;
1067 interconnects 1013 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1068 1014 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1069 1015 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1070 interconnect- 1016 interconnect-names = "qup-core", "qup-config", "qup-memory";
1071 status = "dis 1017 status = "disabled";
1072 }; 1018 };
1073 1019
1074 i2c21: i2c@894000 { 1020 i2c21: i2c@894000 {
1075 compatible = 1021 compatible = "qcom,geni-i2c";
1076 reg = <0 0x00 1022 reg = <0 0x00894000 0 0x4000>;
1077 clock-names = 1023 clock-names = "se";
1078 clocks = <&gc 1024 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1079 interrupts = 1025 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1080 #address-cell 1026 #address-cells = <1>;
1081 #size-cells = 1027 #size-cells = <0>;
1082 power-domains 1028 power-domains = <&rpmhpd SC8280XP_CX>;
1083 interconnects 1029 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1084 1030 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1085 1031 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1086 interconnect- 1032 interconnect-names = "qup-core", "qup-config", "qup-memory";
1087 status = "dis 1033 status = "disabled";
1088 }; 1034 };
1089 1035
1090 spi21: spi@894000 { 1036 spi21: spi@894000 {
1091 compatible = 1037 compatible = "qcom,geni-spi";
1092 reg = <0 0x00 1038 reg = <0 0x00894000 0 0x4000>;
1093 #address-cell 1039 #address-cells = <1>;
1094 #size-cells = 1040 #size-cells = <0>;
1095 clocks = <&gc 1041 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1096 clock-names = 1042 clock-names = "se";
1097 interrupts = 1043 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1098 power-domains 1044 power-domains = <&rpmhpd SC8280XP_CX>;
1099 interconnects 1045 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1100 1046 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1101 1047 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1102 interconnect- 1048 interconnect-names = "qup-core", "qup-config", "qup-memory";
1103 status = "dis 1049 status = "disabled";
1104 }; 1050 };
1105 1051
1106 i2c22: i2c@898000 { 1052 i2c22: i2c@898000 {
1107 compatible = 1053 compatible = "qcom,geni-i2c";
1108 reg = <0 0x00 1054 reg = <0 0x00898000 0 0x4000>;
1109 #address-cell 1055 #address-cells = <1>;
1110 #size-cells = 1056 #size-cells = <0>;
1111 clock-names = 1057 clock-names = "se";
1112 clocks = <&gc 1058 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1113 interrupts = 1059 interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>;
1114 power-domains 1060 power-domains = <&rpmhpd SC8280XP_CX>;
1115 interconnects 1061 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1116 1062 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1117 1063 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1118 interconnect- 1064 interconnect-names = "qup-core", "qup-config", "qup-memory";
1119 status = "dis 1065 status = "disabled";
1120 }; 1066 };
1121 1067
1122 spi22: spi@898000 { 1068 spi22: spi@898000 {
1123 compatible = 1069 compatible = "qcom,geni-spi";
1124 reg = <0 0x00 1070 reg = <0 0x00898000 0 0x4000>;
1125 #address-cell 1071 #address-cells = <1>;
1126 #size-cells = 1072 #size-cells = <0>;
1127 clocks = <&gc 1073 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1128 clock-names = 1074 clock-names = "se";
1129 interrupts = 1075 interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>;
1130 power-domains 1076 power-domains = <&rpmhpd SC8280XP_CX>;
1131 interconnects 1077 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1132 1078 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1133 1079 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1134 interconnect- 1080 interconnect-names = "qup-core", "qup-config", "qup-memory";
1135 status = "dis 1081 status = "disabled";
1136 }; 1082 };
1137 1083
1138 i2c23: i2c@89c000 { 1084 i2c23: i2c@89c000 {
1139 compatible = 1085 compatible = "qcom,geni-i2c";
1140 reg = <0 0x00 1086 reg = <0 0x0089c000 0 0x4000>;
1141 #address-cell 1087 #address-cells = <1>;
1142 #size-cells = 1088 #size-cells = <0>;
1143 clock-names = 1089 clock-names = "se";
1144 clocks = <&gc 1090 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
1145 interrupts = 1091 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>;
1146 power-domains 1092 power-domains = <&rpmhpd SC8280XP_CX>;
1147 interconnects 1093 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1148 1094 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1149 1095 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1150 interconnect- 1096 interconnect-names = "qup-core", "qup-config", "qup-memory";
1151 status = "dis 1097 status = "disabled";
1152 }; 1098 };
1153 1099
1154 spi23: spi@89c000 { 1100 spi23: spi@89c000 {
1155 compatible = 1101 compatible = "qcom,geni-spi";
1156 reg = <0 0x00 1102 reg = <0 0x0089c000 0 0x4000>;
1157 #address-cell 1103 #address-cells = <1>;
1158 #size-cells = 1104 #size-cells = <0>;
1159 clocks = <&gc 1105 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
1160 clock-names = 1106 clock-names = "se";
1161 interrupts = 1107 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>;
1162 power-domains 1108 power-domains = <&rpmhpd SC8280XP_CX>;
1163 interconnects 1109 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1164 1110 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1165 1111 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1166 interconnect- 1112 interconnect-names = "qup-core", "qup-config", "qup-memory";
1167 status = "dis 1113 status = "disabled";
1168 }; 1114 };
1169 }; 1115 };
1170 1116
1171 qup0: geniqup@9c0000 { 1117 qup0: geniqup@9c0000 {
1172 compatible = "qcom,ge 1118 compatible = "qcom,geni-se-qup";
1173 reg = <0 0x009c0000 0 1119 reg = <0 0x009c0000 0 0x6000>;
1174 clocks = <&gcc GCC_QU 1120 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1175 <&gcc GCC_QU 1121 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1176 clock-names = "m-ahb" 1122 clock-names = "m-ahb", "s-ahb";
1177 iommus = <&apps_smmu 1123 iommus = <&apps_smmu 0x563 0>;
1178 1124
1179 #address-cells = <2>; 1125 #address-cells = <2>;
1180 #size-cells = <2>; 1126 #size-cells = <2>;
1181 ranges; 1127 ranges;
1182 1128
1183 status = "disabled"; 1129 status = "disabled";
1184 1130
1185 i2c0: i2c@980000 { 1131 i2c0: i2c@980000 {
1186 compatible = 1132 compatible = "qcom,geni-i2c";
1187 reg = <0 0x00 1133 reg = <0 0x00980000 0 0x4000>;
1188 #address-cell 1134 #address-cells = <1>;
1189 #size-cells = 1135 #size-cells = <0>;
1190 clock-names = 1136 clock-names = "se";
1191 clocks = <&gc 1137 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1192 interrupts = 1138 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1193 power-domains 1139 power-domains = <&rpmhpd SC8280XP_CX>;
1194 interconnects 1140 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1195 1141 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1196 1142 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1197 interconnect- 1143 interconnect-names = "qup-core", "qup-config", "qup-memory";
1198 status = "dis 1144 status = "disabled";
1199 }; 1145 };
1200 1146
1201 spi0: spi@980000 { 1147 spi0: spi@980000 {
1202 compatible = 1148 compatible = "qcom,geni-spi";
1203 reg = <0 0x00 1149 reg = <0 0x00980000 0 0x4000>;
1204 #address-cell 1150 #address-cells = <1>;
1205 #size-cells = 1151 #size-cells = <0>;
1206 clocks = <&gc 1152 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1207 clock-names = 1153 clock-names = "se";
1208 interrupts = 1154 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1209 power-domains 1155 power-domains = <&rpmhpd SC8280XP_CX>;
1210 interconnects 1156 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1211 1157 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1212 1158 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1213 interconnect- 1159 interconnect-names = "qup-core", "qup-config", "qup-memory";
1214 status = "dis 1160 status = "disabled";
1215 }; 1161 };
1216 1162
1217 i2c1: i2c@984000 { 1163 i2c1: i2c@984000 {
1218 compatible = 1164 compatible = "qcom,geni-i2c";
1219 reg = <0 0x00 1165 reg = <0 0x00984000 0 0x4000>;
1220 #address-cell 1166 #address-cells = <1>;
1221 #size-cells = 1167 #size-cells = <0>;
1222 clock-names = 1168 clock-names = "se";
1223 clocks = <&gc 1169 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1224 interrupts = 1170 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1225 power-domains 1171 power-domains = <&rpmhpd SC8280XP_CX>;
1226 interconnects 1172 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1227 1173 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1228 1174 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1229 interconnect- 1175 interconnect-names = "qup-core", "qup-config", "qup-memory";
1230 status = "dis 1176 status = "disabled";
1231 }; 1177 };
1232 1178
1233 spi1: spi@984000 { 1179 spi1: spi@984000 {
1234 compatible = 1180 compatible = "qcom,geni-spi";
1235 reg = <0 0x00 1181 reg = <0 0x00984000 0 0x4000>;
1236 #address-cell 1182 #address-cells = <1>;
1237 #size-cells = 1183 #size-cells = <0>;
1238 clocks = <&gc 1184 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1239 clock-names = 1185 clock-names = "se";
1240 interrupts = 1186 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1241 power-domains 1187 power-domains = <&rpmhpd SC8280XP_CX>;
1242 interconnects 1188 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1243 1189 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1244 1190 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1245 interconnect- 1191 interconnect-names = "qup-core", "qup-config", "qup-memory";
1246 status = "dis 1192 status = "disabled";
1247 }; 1193 };
1248 1194
1249 i2c2: i2c@988000 { 1195 i2c2: i2c@988000 {
1250 compatible = 1196 compatible = "qcom,geni-i2c";
1251 reg = <0 0x00 1197 reg = <0 0x00988000 0 0x4000>;
1252 #address-cell 1198 #address-cells = <1>;
1253 #size-cells = 1199 #size-cells = <0>;
1254 clock-names = 1200 clock-names = "se";
1255 clocks = <&gc 1201 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1256 interrupts = 1202 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1257 power-domains 1203 power-domains = <&rpmhpd SC8280XP_CX>;
1258 interconnects 1204 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1259 1205 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1260 1206 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1261 interconnect- 1207 interconnect-names = "qup-core", "qup-config", "qup-memory";
1262 status = "dis 1208 status = "disabled";
1263 }; 1209 };
1264 1210
1265 spi2: spi@988000 { 1211 spi2: spi@988000 {
1266 compatible = 1212 compatible = "qcom,geni-spi";
1267 reg = <0 0x00 1213 reg = <0 0x00988000 0 0x4000>;
1268 #address-cell 1214 #address-cells = <1>;
1269 #size-cells = 1215 #size-cells = <0>;
1270 clocks = <&gc 1216 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1271 clock-names = 1217 clock-names = "se";
1272 interrupts = 1218 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1273 power-domains 1219 power-domains = <&rpmhpd SC8280XP_CX>;
1274 interconnects 1220 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1275 1221 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1276 1222 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1277 interconnect- 1223 interconnect-names = "qup-core", "qup-config", "qup-memory";
1278 status = "dis 1224 status = "disabled";
1279 }; 1225 };
1280 1226
1281 uart2: serial@988000 1227 uart2: serial@988000 {
1282 compatible = 1228 compatible = "qcom,geni-uart";
1283 reg = <0 0x00 1229 reg = <0 0x00988000 0 0x4000>;
1284 clocks = <&gc 1230 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1285 clock-names = 1231 clock-names = "se";
1286 interrupts = 1232 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1287 operating-poi 1233 operating-points-v2 = <&qup_opp_table_100mhz>;
1288 power-domains 1234 power-domains = <&rpmhpd SC8280XP_CX>;
1289 interconnects 1235 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1290 1236 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1291 interconnect- 1237 interconnect-names = "qup-core", "qup-config";
1292 status = "dis 1238 status = "disabled";
1293 }; 1239 };
1294 1240
1295 i2c3: i2c@98c000 { 1241 i2c3: i2c@98c000 {
1296 compatible = 1242 compatible = "qcom,geni-i2c";
1297 reg = <0 0x00 1243 reg = <0 0x0098c000 0 0x4000>;
1298 #address-cell 1244 #address-cells = <1>;
1299 #size-cells = 1245 #size-cells = <0>;
1300 clock-names = 1246 clock-names = "se";
1301 clocks = <&gc 1247 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1302 interrupts = 1248 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1303 power-domains 1249 power-domains = <&rpmhpd SC8280XP_CX>;
1304 interconnects 1250 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1305 1251 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1306 1252 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1307 interconnect- 1253 interconnect-names = "qup-core", "qup-config", "qup-memory";
1308 status = "dis 1254 status = "disabled";
1309 }; 1255 };
1310 1256
1311 spi3: spi@98c000 { 1257 spi3: spi@98c000 {
1312 compatible = 1258 compatible = "qcom,geni-spi";
1313 reg = <0 0x00 1259 reg = <0 0x0098c000 0 0x4000>;
1314 #address-cell 1260 #address-cells = <1>;
1315 #size-cells = 1261 #size-cells = <0>;
1316 clocks = <&gc 1262 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1317 clock-names = 1263 clock-names = "se";
1318 interrupts = 1264 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1319 power-domains 1265 power-domains = <&rpmhpd SC8280XP_CX>;
1320 interconnects 1266 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1321 1267 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1322 1268 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1323 interconnect- 1269 interconnect-names = "qup-core", "qup-config", "qup-memory";
1324 status = "dis 1270 status = "disabled";
1325 }; 1271 };
1326 1272
1327 i2c4: i2c@990000 { 1273 i2c4: i2c@990000 {
1328 compatible = 1274 compatible = "qcom,geni-i2c";
1329 reg = <0 0x00 1275 reg = <0 0x00990000 0 0x4000>;
1330 clock-names = 1276 clock-names = "se";
1331 clocks = <&gc 1277 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1332 interrupts = 1278 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1333 #address-cell 1279 #address-cells = <1>;
1334 #size-cells = 1280 #size-cells = <0>;
1335 power-domains 1281 power-domains = <&rpmhpd SC8280XP_CX>;
1336 interconnects 1282 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1337 1283 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1338 1284 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1339 interconnect- 1285 interconnect-names = "qup-core", "qup-config", "qup-memory";
1340 status = "dis 1286 status = "disabled";
1341 }; 1287 };
1342 1288
1343 spi4: spi@990000 { 1289 spi4: spi@990000 {
1344 compatible = 1290 compatible = "qcom,geni-spi";
1345 reg = <0 0x00 1291 reg = <0 0x00990000 0 0x4000>;
1346 #address-cell 1292 #address-cells = <1>;
1347 #size-cells = 1293 #size-cells = <0>;
1348 clocks = <&gc 1294 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1349 clock-names = 1295 clock-names = "se";
1350 interrupts = 1296 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1351 power-domains 1297 power-domains = <&rpmhpd SC8280XP_CX>;
1352 interconnects 1298 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1353 1299 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1354 1300 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1355 interconnect- 1301 interconnect-names = "qup-core", "qup-config", "qup-memory";
1356 status = "dis 1302 status = "disabled";
1357 }; 1303 };
1358 1304
1359 i2c5: i2c@994000 { 1305 i2c5: i2c@994000 {
1360 compatible = 1306 compatible = "qcom,geni-i2c";
1361 reg = <0 0x00 1307 reg = <0 0x00994000 0 0x4000>;
1362 #address-cell 1308 #address-cells = <1>;
1363 #size-cells = 1309 #size-cells = <0>;
1364 clock-names = 1310 clock-names = "se";
1365 clocks = <&gc 1311 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1366 interrupts = 1312 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1367 power-domains 1313 power-domains = <&rpmhpd SC8280XP_CX>;
1368 interconnects 1314 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1369 1315 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1370 1316 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1371 interconnect- 1317 interconnect-names = "qup-core", "qup-config", "qup-memory";
1372 status = "dis 1318 status = "disabled";
1373 }; 1319 };
1374 1320
1375 spi5: spi@994000 { 1321 spi5: spi@994000 {
1376 compatible = 1322 compatible = "qcom,geni-spi";
1377 reg = <0 0x00 1323 reg = <0 0x00994000 0 0x4000>;
1378 #address-cell 1324 #address-cells = <1>;
1379 #size-cells = 1325 #size-cells = <0>;
1380 clocks = <&gc 1326 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1381 clock-names = 1327 clock-names = "se";
1382 interrupts = 1328 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1383 power-domains 1329 power-domains = <&rpmhpd SC8280XP_CX>;
1384 interconnects 1330 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1385 1331 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1386 1332 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1387 interconnect- 1333 interconnect-names = "qup-core", "qup-config", "qup-memory";
1388 status = "dis 1334 status = "disabled";
1389 }; 1335 };
1390 1336
1391 i2c6: i2c@998000 { 1337 i2c6: i2c@998000 {
1392 compatible = 1338 compatible = "qcom,geni-i2c";
1393 reg = <0 0x00 1339 reg = <0 0x00998000 0 0x4000>;
1394 #address-cell 1340 #address-cells = <1>;
1395 #size-cells = 1341 #size-cells = <0>;
1396 clock-names = 1342 clock-names = "se";
1397 clocks = <&gc 1343 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1398 interrupts = 1344 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1399 power-domains 1345 power-domains = <&rpmhpd SC8280XP_CX>;
1400 interconnects 1346 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1401 1347 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1402 1348 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1403 interconnect- 1349 interconnect-names = "qup-core", "qup-config", "qup-memory";
1404 status = "dis 1350 status = "disabled";
1405 }; 1351 };
1406 1352
1407 spi6: spi@998000 { 1353 spi6: spi@998000 {
1408 compatible = 1354 compatible = "qcom,geni-spi";
1409 reg = <0 0x00 1355 reg = <0 0x00998000 0 0x4000>;
1410 #address-cell 1356 #address-cells = <1>;
1411 #size-cells = 1357 #size-cells = <0>;
1412 clocks = <&gc 1358 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1413 clock-names = 1359 clock-names = "se";
1414 interrupts = 1360 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1415 power-domains 1361 power-domains = <&rpmhpd SC8280XP_CX>;
1416 interconnects 1362 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1417 1363 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1418 1364 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1419 interconnect- 1365 interconnect-names = "qup-core", "qup-config", "qup-memory";
1420 status = "dis 1366 status = "disabled";
1421 }; 1367 };
1422 1368
1423 i2c7: i2c@99c000 { 1369 i2c7: i2c@99c000 {
1424 compatible = 1370 compatible = "qcom,geni-i2c";
1425 reg = <0 0x00 1371 reg = <0 0x0099c000 0 0x4000>;
1426 #address-cell 1372 #address-cells = <1>;
1427 #size-cells = 1373 #size-cells = <0>;
1428 clock-names = 1374 clock-names = "se";
1429 clocks = <&gc 1375 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1430 interrupts = 1376 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1431 power-domains 1377 power-domains = <&rpmhpd SC8280XP_CX>;
1432 interconnects 1378 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1433 1379 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1434 1380 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1435 interconnect- 1381 interconnect-names = "qup-core", "qup-config", "qup-memory";
1436 status = "dis 1382 status = "disabled";
1437 }; 1383 };
1438 1384
1439 spi7: spi@99c000 { 1385 spi7: spi@99c000 {
1440 compatible = 1386 compatible = "qcom,geni-spi";
1441 reg = <0 0x00 1387 reg = <0 0x0099c000 0 0x4000>;
1442 #address-cell 1388 #address-cells = <1>;
1443 #size-cells = 1389 #size-cells = <0>;
1444 clocks = <&gc 1390 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
1445 clock-names = 1391 clock-names = "se";
1446 interrupts = 1392 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1447 power-domains 1393 power-domains = <&rpmhpd SC8280XP_CX>;
1448 interconnects 1394 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1449 1395 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1450 1396 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1451 interconnect- 1397 interconnect-names = "qup-core", "qup-config", "qup-memory";
1452 status = "dis 1398 status = "disabled";
1453 }; 1399 };
1454 }; 1400 };
1455 1401
1456 qup1: geniqup@ac0000 { 1402 qup1: geniqup@ac0000 {
1457 compatible = "qcom,ge 1403 compatible = "qcom,geni-se-qup";
1458 reg = <0 0x00ac0000 0 1404 reg = <0 0x00ac0000 0 0x6000>;
1459 clocks = <&gcc GCC_QU 1405 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1460 <&gcc GCC_QU 1406 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1461 clock-names = "m-ahb" 1407 clock-names = "m-ahb", "s-ahb";
1462 iommus = <&apps_smmu 1408 iommus = <&apps_smmu 0x83 0>;
1463 1409
1464 #address-cells = <2>; 1410 #address-cells = <2>;
1465 #size-cells = <2>; 1411 #size-cells = <2>;
1466 ranges; 1412 ranges;
1467 1413
1468 status = "disabled"; 1414 status = "disabled";
1469 1415
1470 i2c8: i2c@a80000 { 1416 i2c8: i2c@a80000 {
1471 compatible = 1417 compatible = "qcom,geni-i2c";
1472 reg = <0 0x00 1418 reg = <0 0x00a80000 0 0x4000>;
1473 #address-cell 1419 #address-cells = <1>;
1474 #size-cells = 1420 #size-cells = <0>;
1475 clocks = <&gc 1421 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1476 clock-names = 1422 clock-names = "se";
1477 interrupts = 1423 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1478 power-domains 1424 power-domains = <&rpmhpd SC8280XP_CX>;
1479 interconnects 1425 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1480 1426 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1481 1427 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1482 interconnect- 1428 interconnect-names = "qup-core", "qup-config", "qup-memory";
1483 status = "dis 1429 status = "disabled";
1484 }; 1430 };
1485 1431
1486 spi8: spi@a80000 { 1432 spi8: spi@a80000 {
1487 compatible = 1433 compatible = "qcom,geni-spi";
1488 reg = <0 0x00 1434 reg = <0 0x00a80000 0 0x4000>;
1489 #address-cell 1435 #address-cells = <1>;
1490 #size-cells = 1436 #size-cells = <0>;
1491 clocks = <&gc 1437 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1492 clock-names = 1438 clock-names = "se";
1493 interrupts = 1439 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1494 power-domains 1440 power-domains = <&rpmhpd SC8280XP_CX>;
1495 interconnects 1441 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1496 1442 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1497 1443 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1498 interconnect- 1444 interconnect-names = "qup-core", "qup-config", "qup-memory";
1499 status = "dis 1445 status = "disabled";
1500 }; 1446 };
1501 1447
1502 i2c9: i2c@a84000 { 1448 i2c9: i2c@a84000 {
1503 compatible = 1449 compatible = "qcom,geni-i2c";
1504 reg = <0 0x00 1450 reg = <0 0x00a84000 0 0x4000>;
1505 #address-cell 1451 #address-cells = <1>;
1506 #size-cells = 1452 #size-cells = <0>;
1507 clocks = <&gc 1453 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1508 clock-names = 1454 clock-names = "se";
1509 interrupts = 1455 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1510 power-domains 1456 power-domains = <&rpmhpd SC8280XP_CX>;
1511 interconnects 1457 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1512 1458 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1513 1459 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1514 interconnect- 1460 interconnect-names = "qup-core", "qup-config", "qup-memory";
1515 status = "dis 1461 status = "disabled";
1516 }; 1462 };
1517 1463
1518 spi9: spi@a84000 { 1464 spi9: spi@a84000 {
1519 compatible = 1465 compatible = "qcom,geni-spi";
1520 reg = <0 0x00 1466 reg = <0 0x00a84000 0 0x4000>;
1521 #address-cell 1467 #address-cells = <1>;
1522 #size-cells = 1468 #size-cells = <0>;
1523 clocks = <&gc 1469 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1524 clock-names = 1470 clock-names = "se";
1525 interrupts = 1471 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1526 power-domains 1472 power-domains = <&rpmhpd SC8280XP_CX>;
1527 interconnects 1473 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1528 1474 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1529 1475 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1530 interconnect- 1476 interconnect-names = "qup-core", "qup-config", "qup-memory";
1531 status = "dis 1477 status = "disabled";
1532 }; 1478 };
1533 1479
1534 i2c10: i2c@a88000 { 1480 i2c10: i2c@a88000 {
1535 compatible = 1481 compatible = "qcom,geni-i2c";
1536 reg = <0 0x00 1482 reg = <0 0x00a88000 0 0x4000>;
1537 #address-cell 1483 #address-cells = <1>;
1538 #size-cells = 1484 #size-cells = <0>;
1539 clocks = <&gc 1485 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1540 clock-names = 1486 clock-names = "se";
1541 interrupts = 1487 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1542 power-domains 1488 power-domains = <&rpmhpd SC8280XP_CX>;
1543 interconnects 1489 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1544 1490 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1545 1491 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1546 interconnect- 1492 interconnect-names = "qup-core", "qup-config", "qup-memory";
1547 status = "dis 1493 status = "disabled";
1548 }; 1494 };
1549 1495
1550 spi10: spi@a88000 { 1496 spi10: spi@a88000 {
1551 compatible = 1497 compatible = "qcom,geni-spi";
1552 reg = <0 0x00 1498 reg = <0 0x00a88000 0 0x4000>;
1553 #address-cell 1499 #address-cells = <1>;
1554 #size-cells = 1500 #size-cells = <0>;
1555 clocks = <&gc 1501 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1556 clock-names = 1502 clock-names = "se";
1557 interrupts = 1503 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1558 power-domains 1504 power-domains = <&rpmhpd SC8280XP_CX>;
1559 interconnects 1505 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1560 1506 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1561 1507 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1562 interconnect- 1508 interconnect-names = "qup-core", "qup-config", "qup-memory";
1563 status = "dis 1509 status = "disabled";
1564 }; 1510 };
1565 1511
1566 i2c11: i2c@a8c000 { 1512 i2c11: i2c@a8c000 {
1567 compatible = 1513 compatible = "qcom,geni-i2c";
1568 reg = <0 0x00 1514 reg = <0 0x00a8c000 0 0x4000>;
1569 #address-cell 1515 #address-cells = <1>;
1570 #size-cells = 1516 #size-cells = <0>;
1571 clocks = <&gc 1517 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1572 clock-names = 1518 clock-names = "se";
1573 interrupts = 1519 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1574 power-domains 1520 power-domains = <&rpmhpd SC8280XP_CX>;
1575 interconnects 1521 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1576 1522 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1577 1523 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1578 interconnect- 1524 interconnect-names = "qup-core", "qup-config", "qup-memory";
1579 status = "dis 1525 status = "disabled";
1580 }; 1526 };
1581 1527
1582 spi11: spi@a8c000 { 1528 spi11: spi@a8c000 {
1583 compatible = 1529 compatible = "qcom,geni-spi";
1584 reg = <0 0x00 1530 reg = <0 0x00a8c000 0 0x4000>;
1585 #address-cell 1531 #address-cells = <1>;
1586 #size-cells = 1532 #size-cells = <0>;
1587 clocks = <&gc 1533 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1588 clock-names = 1534 clock-names = "se";
1589 interrupts = 1535 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1590 power-domains 1536 power-domains = <&rpmhpd SC8280XP_CX>;
1591 interconnects 1537 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1592 1538 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1593 1539 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1594 interconnect- 1540 interconnect-names = "qup-core", "qup-config", "qup-memory";
1595 status = "dis 1541 status = "disabled";
1596 }; 1542 };
1597 1543
1598 i2c12: i2c@a90000 { 1544 i2c12: i2c@a90000 {
1599 compatible = 1545 compatible = "qcom,geni-i2c";
1600 reg = <0 0x00 1546 reg = <0 0x00a90000 0 0x4000>;
1601 #address-cell 1547 #address-cells = <1>;
1602 #size-cells = 1548 #size-cells = <0>;
1603 clocks = <&gc 1549 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1604 clock-names = 1550 clock-names = "se";
1605 interrupts = 1551 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1606 power-domains 1552 power-domains = <&rpmhpd SC8280XP_CX>;
1607 interconnects 1553 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1608 1554 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1609 1555 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1610 interconnect- 1556 interconnect-names = "qup-core", "qup-config", "qup-memory";
1611 status = "dis 1557 status = "disabled";
1612 }; 1558 };
1613 1559
1614 spi12: spi@a90000 { 1560 spi12: spi@a90000 {
1615 compatible = 1561 compatible = "qcom,geni-spi";
1616 reg = <0 0x00 1562 reg = <0 0x00a90000 0 0x4000>;
1617 #address-cell 1563 #address-cells = <1>;
1618 #size-cells = 1564 #size-cells = <0>;
1619 clocks = <&gc 1565 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1620 clock-names = 1566 clock-names = "se";
1621 interrupts = 1567 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1622 power-domains 1568 power-domains = <&rpmhpd SC8280XP_CX>;
1623 interconnects 1569 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1624 1570 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1625 1571 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1626 interconnect- 1572 interconnect-names = "qup-core", "qup-config", "qup-memory";
1627 status = "dis 1573 status = "disabled";
1628 }; 1574 };
1629 1575
1630 i2c13: i2c@a94000 { 1576 i2c13: i2c@a94000 {
1631 compatible = 1577 compatible = "qcom,geni-i2c";
1632 reg = <0 0x00 1578 reg = <0 0x00a94000 0 0x4000>;
1633 #address-cell 1579 #address-cells = <1>;
1634 #size-cells = 1580 #size-cells = <0>;
1635 clocks = <&gc 1581 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1636 clock-names = 1582 clock-names = "se";
1637 interrupts = 1583 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1638 power-domains 1584 power-domains = <&rpmhpd SC8280XP_CX>;
1639 interconnects 1585 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1640 1586 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1641 1587 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1642 interconnect- 1588 interconnect-names = "qup-core", "qup-config", "qup-memory";
1643 status = "dis 1589 status = "disabled";
1644 }; 1590 };
1645 1591
1646 spi13: spi@a94000 { 1592 spi13: spi@a94000 {
1647 compatible = 1593 compatible = "qcom,geni-spi";
1648 reg = <0 0x00 1594 reg = <0 0x00a94000 0 0x4000>;
1649 #address-cell 1595 #address-cells = <1>;
1650 #size-cells = 1596 #size-cells = <0>;
1651 clocks = <&gc 1597 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1652 clock-names = 1598 clock-names = "se";
1653 interrupts = 1599 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1654 power-domains 1600 power-domains = <&rpmhpd SC8280XP_CX>;
1655 interconnects 1601 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1656 1602 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1657 1603 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1658 interconnect- 1604 interconnect-names = "qup-core", "qup-config", "qup-memory";
1659 status = "dis 1605 status = "disabled";
1660 }; 1606 };
1661 1607
1662 i2c14: i2c@a98000 { 1608 i2c14: i2c@a98000 {
1663 compatible = 1609 compatible = "qcom,geni-i2c";
1664 reg = <0 0x00 1610 reg = <0 0x00a98000 0 0x4000>;
1665 #address-cell 1611 #address-cells = <1>;
1666 #size-cells = 1612 #size-cells = <0>;
1667 clocks = <&gc 1613 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1668 clock-names = 1614 clock-names = "se";
1669 interrupts = 1615 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>;
1670 power-domains 1616 power-domains = <&rpmhpd SC8280XP_CX>;
1671 interconnects 1617 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1672 1618 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1673 1619 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1674 interconnect- 1620 interconnect-names = "qup-core", "qup-config", "qup-memory";
1675 status = "dis 1621 status = "disabled";
1676 }; 1622 };
1677 1623
1678 spi14: spi@a98000 { 1624 spi14: spi@a98000 {
1679 compatible = 1625 compatible = "qcom,geni-spi";
1680 reg = <0 0x00 1626 reg = <0 0x00a98000 0 0x4000>;
1681 #address-cell 1627 #address-cells = <1>;
1682 #size-cells = 1628 #size-cells = <0>;
1683 clocks = <&gc 1629 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1684 clock-names = 1630 clock-names = "se";
1685 interrupts = 1631 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>;
1686 power-domains 1632 power-domains = <&rpmhpd SC8280XP_CX>;
1687 interconnects 1633 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1688 1634 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1689 1635 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1690 interconnect- 1636 interconnect-names = "qup-core", "qup-config", "qup-memory";
1691 status = "dis 1637 status = "disabled";
1692 }; 1638 };
1693 1639
1694 i2c15: i2c@a9c000 { 1640 i2c15: i2c@a9c000 {
1695 compatible = 1641 compatible = "qcom,geni-i2c";
1696 reg = <0 0x00 1642 reg = <0 0x00a9c000 0 0x4000>;
1697 #address-cell 1643 #address-cells = <1>;
1698 #size-cells = 1644 #size-cells = <0>;
1699 clocks = <&gc 1645 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1700 clock-names = 1646 clock-names = "se";
1701 interrupts = 1647 interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
1702 power-domains 1648 power-domains = <&rpmhpd SC8280XP_CX>;
1703 interconnects 1649 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1704 1650 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1705 1651 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1706 interconnect- 1652 interconnect-names = "qup-core", "qup-config", "qup-memory";
1707 status = "dis 1653 status = "disabled";
1708 }; 1654 };
1709 1655
1710 spi15: spi@a9c000 { 1656 spi15: spi@a9c000 {
1711 compatible = 1657 compatible = "qcom,geni-spi";
1712 reg = <0 0x00 1658 reg = <0 0x00a9c000 0 0x4000>;
1713 #address-cell 1659 #address-cells = <1>;
1714 #size-cells = 1660 #size-cells = <0>;
1715 clocks = <&gc 1661 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1716 clock-names = 1662 clock-names = "se";
1717 interrupts = 1663 interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
1718 power-domains 1664 power-domains = <&rpmhpd SC8280XP_CX>;
1719 interconnects 1665 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1720 1666 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1721 1667 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1722 interconnect- 1668 interconnect-names = "qup-core", "qup-config", "qup-memory";
1723 status = "dis 1669 status = "disabled";
1724 }; 1670 };
1725 }; 1671 };
1726 1672
1727 rng: rng@10d3000 { 1673 rng: rng@10d3000 {
1728 compatible = "qcom,pr 1674 compatible = "qcom,prng-ee";
1729 reg = <0 0x010d3000 0 1675 reg = <0 0x010d3000 0 0x1000>;
1730 clocks = <&rpmhcc RPM 1676 clocks = <&rpmhcc RPMH_HWKM_CLK>;
1731 clock-names = "core"; 1677 clock-names = "core";
1732 }; 1678 };
1733 1679
1734 pcie4: pcie@1c00000 { 1680 pcie4: pcie@1c00000 {
1735 device_type = "pci"; 1681 device_type = "pci";
1736 compatible = "qcom,pc 1682 compatible = "qcom,pcie-sc8280xp";
1737 reg = <0x0 0x01c00000 1683 reg = <0x0 0x01c00000 0x0 0x3000>,
1738 <0x0 0x30000000 1684 <0x0 0x30000000 0x0 0xf1d>,
1739 <0x0 0x30000f20 1685 <0x0 0x30000f20 0x0 0xa8>,
1740 <0x0 0x30001000 1686 <0x0 0x30001000 0x0 0x1000>,
1741 <0x0 0x30100000 1687 <0x0 0x30100000 0x0 0x100000>,
1742 <0x0 0x01c03000 1688 <0x0 0x01c03000 0x0 0x1000>;
1743 reg-names = "parf", " 1689 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
1744 #address-cells = <3>; 1690 #address-cells = <3>;
1745 #size-cells = <2>; 1691 #size-cells = <2>;
1746 ranges = <0x01000000 1692 ranges = <0x01000000 0x0 0x00000000 0x0 0x30200000 0x0 0x100000>,
1747 <0x02000000 1693 <0x02000000 0x0 0x30300000 0x0 0x30300000 0x0 0x1d00000>;
1748 bus-range = <0x00 0xf 1694 bus-range = <0x00 0xff>;
1749 1695
1750 dma-coherent; 1696 dma-coherent;
1751 1697
1752 linux,pci-domain = <6 1698 linux,pci-domain = <6>;
1753 num-lanes = <1>; 1699 num-lanes = <1>;
1754 1700
1755 msi-map = <0x0 &its 0 <<
1756 <<
1757 interrupts = <GIC_SPI 1701 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
1758 <GIC_SPI 1702 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
1759 <GIC_SPI 1703 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
1760 <GIC_SPI 1704 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
1761 interrupt-names = "ms 1705 interrupt-names = "msi0", "msi1", "msi2", "msi3";
1762 1706
1763 #interrupt-cells = <1 1707 #interrupt-cells = <1>;
1764 interrupt-map-mask = 1708 interrupt-map-mask = <0 0 0 0x7>;
1765 interrupt-map = <0 0 1709 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
1766 <0 0 1710 <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
1767 <0 0 1711 <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
1768 <0 0 1712 <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
1769 1713
1770 clocks = <&gcc GCC_PC 1714 clocks = <&gcc GCC_PCIE_4_AUX_CLK>,
1771 <&gcc GCC_PC 1715 <&gcc GCC_PCIE_4_CFG_AHB_CLK>,
1772 <&gcc GCC_PC 1716 <&gcc GCC_PCIE_4_MSTR_AXI_CLK>,
1773 <&gcc GCC_PC 1717 <&gcc GCC_PCIE_4_SLV_AXI_CLK>,
1774 <&gcc GCC_PC 1718 <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>,
1775 <&gcc GCC_DD 1719 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1776 <&gcc GCC_AG 1720 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
1777 <&gcc GCC_AG 1721 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>,
1778 <&gcc GCC_CN 1722 <&gcc GCC_CNOC_PCIE4_QX_CLK>;
1779 clock-names = "aux", 1723 clock-names = "aux",
1780 "cfg", 1724 "cfg",
1781 "bus_ma 1725 "bus_master",
1782 "bus_sl 1726 "bus_slave",
1783 "slave_ 1727 "slave_q2a",
1784 "ddrss_ 1728 "ddrss_sf_tbu",
1785 "noc_ag 1729 "noc_aggr_4",
1786 "noc_ag 1730 "noc_aggr_south_sf",
1787 "cnoc_q 1731 "cnoc_qx";
1788 1732
1789 assigned-clocks = <&g 1733 assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>;
1790 assigned-clock-rates 1734 assigned-clock-rates = <19200000>;
1791 1735
1792 interconnects = <&agg 1736 interconnects = <&aggre2_noc MASTER_PCIE_4 0 &mc_virt SLAVE_EBI1 0>,
1793 <&gem 1737 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_4 0>;
1794 interconnect-names = 1738 interconnect-names = "pcie-mem", "cpu-pcie";
1795 1739
1796 resets = <&gcc GCC_PC 1740 resets = <&gcc GCC_PCIE_4_BCR>;
1797 reset-names = "pci"; 1741 reset-names = "pci";
1798 1742
1799 power-domains = <&gcc 1743 power-domains = <&gcc PCIE_4_GDSC>;
1800 required-opps = <&rpm <<
1801 1744
1802 phys = <&pcie4_phy>; 1745 phys = <&pcie4_phy>;
1803 phy-names = "pciephy" 1746 phy-names = "pciephy";
1804 1747
1805 status = "disabled"; 1748 status = "disabled";
1806 <<
1807 pcie4_port0: pcie@0 { <<
1808 device_type = <<
1809 reg = <0x0 0x <<
1810 bus-range = < <<
1811 <<
1812 #address-cell <<
1813 #size-cells = <<
1814 ranges; <<
1815 }; <<
1816 }; 1749 };
1817 1750
1818 pcie4_phy: phy@1c06000 { 1751 pcie4_phy: phy@1c06000 {
1819 compatible = "qcom,sc 1752 compatible = "qcom,sc8280xp-qmp-gen3x1-pcie-phy";
1820 reg = <0x0 0x01c06000 1753 reg = <0x0 0x01c06000 0x0 0x2000>;
1821 1754
1822 clocks = <&gcc GCC_PC 1755 clocks = <&gcc GCC_PCIE_4_AUX_CLK>,
1823 <&gcc GCC_PC 1756 <&gcc GCC_PCIE_4_CFG_AHB_CLK>,
1824 <&gcc GCC_PC 1757 <&gcc GCC_PCIE_4_CLKREF_CLK>,
1825 <&gcc GCC_PC 1758 <&gcc GCC_PCIE4_PHY_RCHNG_CLK>,
1826 <&gcc GCC_PC 1759 <&gcc GCC_PCIE_4_PIPE_CLK>,
1827 <&gcc GCC_PC 1760 <&gcc GCC_PCIE_4_PIPEDIV2_CLK>;
1828 clock-names = "aux", 1761 clock-names = "aux", "cfg_ahb", "ref", "rchng",
1829 "pipe", 1762 "pipe", "pipediv2";
1830 1763
1831 assigned-clocks = <&g 1764 assigned-clocks = <&gcc GCC_PCIE4_PHY_RCHNG_CLK>;
1832 assigned-clock-rates 1765 assigned-clock-rates = <100000000>;
1833 1766
1834 power-domains = <&gcc 1767 power-domains = <&gcc PCIE_4_GDSC>;
1835 1768
1836 resets = <&gcc GCC_PC 1769 resets = <&gcc GCC_PCIE_4_PHY_BCR>;
1837 reset-names = "phy"; 1770 reset-names = "phy";
1838 1771
1839 #clock-cells = <0>; 1772 #clock-cells = <0>;
1840 clock-output-names = 1773 clock-output-names = "pcie_4_pipe_clk";
1841 1774
1842 #phy-cells = <0>; 1775 #phy-cells = <0>;
1843 1776
1844 status = "disabled"; 1777 status = "disabled";
1845 }; 1778 };
1846 1779
1847 pcie3b: pcie@1c08000 { 1780 pcie3b: pcie@1c08000 {
1848 device_type = "pci"; 1781 device_type = "pci";
1849 compatible = "qcom,pc 1782 compatible = "qcom,pcie-sc8280xp";
1850 reg = <0x0 0x01c08000 1783 reg = <0x0 0x01c08000 0x0 0x3000>,
1851 <0x0 0x32000000 1784 <0x0 0x32000000 0x0 0xf1d>,
1852 <0x0 0x32000f20 1785 <0x0 0x32000f20 0x0 0xa8>,
1853 <0x0 0x32001000 1786 <0x0 0x32001000 0x0 0x1000>,
1854 <0x0 0x32100000 1787 <0x0 0x32100000 0x0 0x100000>,
1855 <0x0 0x01c0b000 1788 <0x0 0x01c0b000 0x0 0x1000>;
1856 reg-names = "parf", " 1789 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
1857 #address-cells = <3>; 1790 #address-cells = <3>;
1858 #size-cells = <2>; 1791 #size-cells = <2>;
1859 ranges = <0x01000000 1792 ranges = <0x01000000 0x0 0x00000000 0x0 0x32200000 0x0 0x100000>,
1860 <0x02000000 1793 <0x02000000 0x0 0x32300000 0x0 0x32300000 0x0 0x1d00000>;
1861 bus-range = <0x00 0xf 1794 bus-range = <0x00 0xff>;
1862 1795
1863 dma-coherent; 1796 dma-coherent;
1864 1797
1865 linux,pci-domain = <5 1798 linux,pci-domain = <5>;
1866 num-lanes = <2>; 1799 num-lanes = <2>;
1867 1800
1868 msi-map = <0x0 &its 0 <<
1869 <<
1870 interrupts = <GIC_SPI 1801 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1871 <GIC_SPI 1802 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1872 <GIC_SPI 1803 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
1873 <GIC_SPI 1804 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
1874 interrupt-names = "ms 1805 interrupt-names = "msi0", "msi1", "msi2", "msi3";
1875 1806
1876 #interrupt-cells = <1 1807 #interrupt-cells = <1>;
1877 interrupt-map-mask = 1808 interrupt-map-mask = <0 0 0 0x7>;
1878 interrupt-map = <0 0 1809 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>,
1879 <0 0 1810 <0 0 0 2 &intc 0 0 GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>,
1880 <0 0 1811 <0 0 0 3 &intc 0 0 GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>,
1881 <0 0 1812 <0 0 0 4 &intc 0 0 GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>;
1882 1813
1883 clocks = <&gcc GCC_PC 1814 clocks = <&gcc GCC_PCIE_3B_AUX_CLK>,
1884 <&gcc GCC_PC 1815 <&gcc GCC_PCIE_3B_CFG_AHB_CLK>,
1885 <&gcc GCC_PC 1816 <&gcc GCC_PCIE_3B_MSTR_AXI_CLK>,
1886 <&gcc GCC_PC 1817 <&gcc GCC_PCIE_3B_SLV_AXI_CLK>,
1887 <&gcc GCC_PC 1818 <&gcc GCC_PCIE_3B_SLV_Q2A_AXI_CLK>,
1888 <&gcc GCC_DD 1819 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1889 <&gcc GCC_AG 1820 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
1890 <&gcc GCC_AG 1821 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
1891 clock-names = "aux", 1822 clock-names = "aux",
1892 "cfg", 1823 "cfg",
1893 "bus_ma 1824 "bus_master",
1894 "bus_sl 1825 "bus_slave",
1895 "slave_ 1826 "slave_q2a",
1896 "ddrss_ 1827 "ddrss_sf_tbu",
1897 "noc_ag 1828 "noc_aggr_4",
1898 "noc_ag 1829 "noc_aggr_south_sf";
1899 1830
1900 assigned-clocks = <&g 1831 assigned-clocks = <&gcc GCC_PCIE_3B_AUX_CLK>;
1901 assigned-clock-rates 1832 assigned-clock-rates = <19200000>;
1902 1833
1903 interconnects = <&agg 1834 interconnects = <&aggre2_noc MASTER_PCIE_3B 0 &mc_virt SLAVE_EBI1 0>,
1904 <&gem 1835 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3B 0>;
1905 interconnect-names = 1836 interconnect-names = "pcie-mem", "cpu-pcie";
1906 1837
1907 resets = <&gcc GCC_PC 1838 resets = <&gcc GCC_PCIE_3B_BCR>;
1908 reset-names = "pci"; 1839 reset-names = "pci";
1909 1840
1910 power-domains = <&gcc 1841 power-domains = <&gcc PCIE_3B_GDSC>;
1911 required-opps = <&rpm <<
1912 1842
1913 phys = <&pcie3b_phy>; 1843 phys = <&pcie3b_phy>;
1914 phy-names = "pciephy" 1844 phy-names = "pciephy";
1915 1845
1916 status = "disabled"; 1846 status = "disabled";
1917 <<
1918 pcie3b_port0: pcie@0 <<
1919 device_type = <<
1920 reg = <0x0 0x <<
1921 bus-range = < <<
1922 <<
1923 #address-cell <<
1924 #size-cells = <<
1925 ranges; <<
1926 }; <<
1927 }; 1847 };
1928 1848
1929 pcie3b_phy: phy@1c0e000 { 1849 pcie3b_phy: phy@1c0e000 {
1930 compatible = "qcom,sc 1850 compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy";
1931 reg = <0x0 0x01c0e000 1851 reg = <0x0 0x01c0e000 0x0 0x2000>;
1932 1852
1933 clocks = <&gcc GCC_PC 1853 clocks = <&gcc GCC_PCIE_3B_AUX_CLK>,
1934 <&gcc GCC_PC 1854 <&gcc GCC_PCIE_3B_CFG_AHB_CLK>,
1935 <&gcc GCC_PC 1855 <&gcc GCC_PCIE_3A3B_CLKREF_CLK>,
1936 <&gcc GCC_PC 1856 <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>,
1937 <&gcc GCC_PC 1857 <&gcc GCC_PCIE_3B_PIPE_CLK>,
1938 <&gcc GCC_PC 1858 <&gcc GCC_PCIE_3B_PIPEDIV2_CLK>;
1939 clock-names = "aux", 1859 clock-names = "aux", "cfg_ahb", "ref", "rchng",
1940 "pipe", 1860 "pipe", "pipediv2";
1941 1861
1942 assigned-clocks = <&g 1862 assigned-clocks = <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>;
1943 assigned-clock-rates 1863 assigned-clock-rates = <100000000>;
1944 1864
1945 power-domains = <&gcc 1865 power-domains = <&gcc PCIE_3B_GDSC>;
1946 1866
1947 resets = <&gcc GCC_PC 1867 resets = <&gcc GCC_PCIE_3B_PHY_BCR>;
1948 reset-names = "phy"; 1868 reset-names = "phy";
1949 1869
1950 #clock-cells = <0>; 1870 #clock-cells = <0>;
1951 clock-output-names = 1871 clock-output-names = "pcie_3b_pipe_clk";
1952 1872
1953 #phy-cells = <0>; 1873 #phy-cells = <0>;
1954 1874
1955 status = "disabled"; 1875 status = "disabled";
1956 }; 1876 };
1957 1877
1958 pcie3a: pcie@1c10000 { 1878 pcie3a: pcie@1c10000 {
1959 device_type = "pci"; 1879 device_type = "pci";
1960 compatible = "qcom,pc 1880 compatible = "qcom,pcie-sc8280xp";
1961 reg = <0x0 0x01c10000 1881 reg = <0x0 0x01c10000 0x0 0x3000>,
1962 <0x0 0x34000000 1882 <0x0 0x34000000 0x0 0xf1d>,
1963 <0x0 0x34000f20 1883 <0x0 0x34000f20 0x0 0xa8>,
1964 <0x0 0x34001000 1884 <0x0 0x34001000 0x0 0x1000>,
1965 <0x0 0x34100000 1885 <0x0 0x34100000 0x0 0x100000>,
1966 <0x0 0x01c13000 1886 <0x0 0x01c13000 0x0 0x1000>;
1967 reg-names = "parf", " 1887 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
1968 #address-cells = <3>; 1888 #address-cells = <3>;
1969 #size-cells = <2>; 1889 #size-cells = <2>;
1970 ranges = <0x01000000 1890 ranges = <0x01000000 0x0 0x00000000 0x0 0x34200000 0x0 0x100000>,
1971 <0x02000000 1891 <0x02000000 0x0 0x34300000 0x0 0x34300000 0x0 0x1d00000>;
1972 bus-range = <0x00 0xf 1892 bus-range = <0x00 0xff>;
1973 1893
1974 dma-coherent; 1894 dma-coherent;
1975 1895
1976 linux,pci-domain = <4 1896 linux,pci-domain = <4>;
1977 num-lanes = <4>; 1897 num-lanes = <4>;
1978 1898
1979 msi-map = <0x0 &its 0 <<
1980 <<
1981 interrupts = <GIC_SPI 1899 interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
1982 <GIC_SPI 1900 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
1983 <GIC_SPI 1901 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
1984 <GIC_SPI 1902 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1985 interrupt-names = "ms 1903 interrupt-names = "msi0", "msi1", "msi2", "msi3";
1986 1904
1987 #interrupt-cells = <1 1905 #interrupt-cells = <1>;
1988 interrupt-map-mask = 1906 interrupt-map-mask = <0 0 0 0x7>;
1989 interrupt-map = <0 0 1907 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>,
1990 <0 0 1908 <0 0 0 2 &intc 0 0 GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>,
1991 <0 0 1909 <0 0 0 3 &intc 0 0 GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>,
1992 <0 0 1910 <0 0 0 4 &intc 0 0 GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>;
1993 1911
1994 clocks = <&gcc GCC_PC 1912 clocks = <&gcc GCC_PCIE_3A_AUX_CLK>,
1995 <&gcc GCC_PC 1913 <&gcc GCC_PCIE_3A_CFG_AHB_CLK>,
1996 <&gcc GCC_PC 1914 <&gcc GCC_PCIE_3A_MSTR_AXI_CLK>,
1997 <&gcc GCC_PC 1915 <&gcc GCC_PCIE_3A_SLV_AXI_CLK>,
1998 <&gcc GCC_PC 1916 <&gcc GCC_PCIE_3A_SLV_Q2A_AXI_CLK>,
1999 <&gcc GCC_DD 1917 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
2000 <&gcc GCC_AG 1918 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
2001 <&gcc GCC_AG 1919 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
2002 clock-names = "aux", 1920 clock-names = "aux",
2003 "cfg", 1921 "cfg",
2004 "bus_ma 1922 "bus_master",
2005 "bus_sl 1923 "bus_slave",
2006 "slave_ 1924 "slave_q2a",
2007 "ddrss_ 1925 "ddrss_sf_tbu",
2008 "noc_ag 1926 "noc_aggr_4",
2009 "noc_ag 1927 "noc_aggr_south_sf";
2010 1928
2011 assigned-clocks = <&g 1929 assigned-clocks = <&gcc GCC_PCIE_3A_AUX_CLK>;
2012 assigned-clock-rates 1930 assigned-clock-rates = <19200000>;
2013 1931
2014 interconnects = <&agg 1932 interconnects = <&aggre2_noc MASTER_PCIE_3A 0 &mc_virt SLAVE_EBI1 0>,
2015 <&gem 1933 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3A 0>;
2016 interconnect-names = 1934 interconnect-names = "pcie-mem", "cpu-pcie";
2017 1935
2018 resets = <&gcc GCC_PC 1936 resets = <&gcc GCC_PCIE_3A_BCR>;
2019 reset-names = "pci"; 1937 reset-names = "pci";
2020 1938
2021 power-domains = <&gcc 1939 power-domains = <&gcc PCIE_3A_GDSC>;
2022 required-opps = <&rpm <<
2023 1940
2024 phys = <&pcie3a_phy>; 1941 phys = <&pcie3a_phy>;
2025 phy-names = "pciephy" 1942 phy-names = "pciephy";
2026 1943
2027 status = "disabled"; 1944 status = "disabled";
2028 <<
2029 pcie3a_port0: pcie@0 <<
2030 device_type = <<
2031 reg = <0x0 0x <<
2032 bus-range = < <<
2033 <<
2034 #address-cell <<
2035 #size-cells = <<
2036 ranges; <<
2037 }; <<
2038 }; 1945 };
2039 1946
2040 pcie3a_phy: phy@1c14000 { 1947 pcie3a_phy: phy@1c14000 {
2041 compatible = "qcom,sc 1948 compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy";
2042 reg = <0x0 0x01c14000 1949 reg = <0x0 0x01c14000 0x0 0x2000>,
2043 <0x0 0x01c16000 1950 <0x0 0x01c16000 0x0 0x2000>;
2044 1951
2045 clocks = <&gcc GCC_PC 1952 clocks = <&gcc GCC_PCIE_3A_AUX_CLK>,
2046 <&gcc GCC_PC 1953 <&gcc GCC_PCIE_3A_CFG_AHB_CLK>,
2047 <&gcc GCC_PC 1954 <&gcc GCC_PCIE_3A3B_CLKREF_CLK>,
2048 <&gcc GCC_PC 1955 <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>,
2049 <&gcc GCC_PC 1956 <&gcc GCC_PCIE_3A_PIPE_CLK>,
2050 <&gcc GCC_PC 1957 <&gcc GCC_PCIE_3A_PIPEDIV2_CLK>;
2051 clock-names = "aux", 1958 clock-names = "aux", "cfg_ahb", "ref", "rchng",
2052 "pipe", 1959 "pipe", "pipediv2";
2053 1960
2054 assigned-clocks = <&g 1961 assigned-clocks = <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>;
2055 assigned-clock-rates 1962 assigned-clock-rates = <100000000>;
2056 1963
2057 power-domains = <&gcc 1964 power-domains = <&gcc PCIE_3A_GDSC>;
2058 1965
2059 resets = <&gcc GCC_PC 1966 resets = <&gcc GCC_PCIE_3A_PHY_BCR>;
2060 reset-names = "phy"; 1967 reset-names = "phy";
2061 1968
2062 qcom,4ln-config-sel = 1969 qcom,4ln-config-sel = <&tcsr 0xa044 1>;
2063 1970
2064 #clock-cells = <0>; 1971 #clock-cells = <0>;
2065 clock-output-names = 1972 clock-output-names = "pcie_3a_pipe_clk";
2066 1973
2067 #phy-cells = <0>; 1974 #phy-cells = <0>;
2068 1975
2069 status = "disabled"; 1976 status = "disabled";
2070 }; 1977 };
2071 1978
2072 pcie2b: pcie@1c18000 { 1979 pcie2b: pcie@1c18000 {
2073 device_type = "pci"; 1980 device_type = "pci";
2074 compatible = "qcom,pc 1981 compatible = "qcom,pcie-sc8280xp";
2075 reg = <0x0 0x01c18000 1982 reg = <0x0 0x01c18000 0x0 0x3000>,
2076 <0x0 0x38000000 1983 <0x0 0x38000000 0x0 0xf1d>,
2077 <0x0 0x38000f20 1984 <0x0 0x38000f20 0x0 0xa8>,
2078 <0x0 0x38001000 1985 <0x0 0x38001000 0x0 0x1000>,
2079 <0x0 0x38100000 1986 <0x0 0x38100000 0x0 0x100000>,
2080 <0x0 0x01c1b000 1987 <0x0 0x01c1b000 0x0 0x1000>;
2081 reg-names = "parf", " 1988 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2082 #address-cells = <3>; 1989 #address-cells = <3>;
2083 #size-cells = <2>; 1990 #size-cells = <2>;
2084 ranges = <0x01000000 1991 ranges = <0x01000000 0x0 0x00000000 0x0 0x38200000 0x0 0x100000>,
2085 <0x02000000 1992 <0x02000000 0x0 0x38300000 0x0 0x38300000 0x0 0x1d00000>;
2086 bus-range = <0x00 0xf 1993 bus-range = <0x00 0xff>;
2087 1994
2088 dma-coherent; 1995 dma-coherent;
2089 1996
2090 linux,pci-domain = <3 1997 linux,pci-domain = <3>;
2091 num-lanes = <2>; 1998 num-lanes = <2>;
2092 1999
2093 msi-map = <0x0 &its 0 <<
2094 <<
2095 interrupts = <GIC_SPI 2000 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
2096 <GIC_SPI 2001 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
2097 <GIC_SPI 2002 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
2098 <GIC_SPI 2003 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
2099 interrupt-names = "ms 2004 interrupt-names = "msi0", "msi1", "msi2", "msi3";
2100 2005
2101 #interrupt-cells = <1 2006 #interrupt-cells = <1>;
2102 interrupt-map-mask = 2007 interrupt-map-mask = <0 0 0 0x7>;
2103 interrupt-map = <0 0 2008 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
2104 <0 0 2009 <0 0 0 2 &intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
2105 <0 0 2010 <0 0 0 3 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
2106 <0 0 2011 <0 0 0 4 &intc 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>;
2107 2012
2108 clocks = <&gcc GCC_PC 2013 clocks = <&gcc GCC_PCIE_2B_AUX_CLK>,
2109 <&gcc GCC_PC 2014 <&gcc GCC_PCIE_2B_CFG_AHB_CLK>,
2110 <&gcc GCC_PC 2015 <&gcc GCC_PCIE_2B_MSTR_AXI_CLK>,
2111 <&gcc GCC_PC 2016 <&gcc GCC_PCIE_2B_SLV_AXI_CLK>,
2112 <&gcc GCC_PC 2017 <&gcc GCC_PCIE_2B_SLV_Q2A_AXI_CLK>,
2113 <&gcc GCC_DD 2018 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
2114 <&gcc GCC_AG 2019 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
2115 <&gcc GCC_AG 2020 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
2116 clock-names = "aux", 2021 clock-names = "aux",
2117 "cfg", 2022 "cfg",
2118 "bus_ma 2023 "bus_master",
2119 "bus_sl 2024 "bus_slave",
2120 "slave_ 2025 "slave_q2a",
2121 "ddrss_ 2026 "ddrss_sf_tbu",
2122 "noc_ag 2027 "noc_aggr_4",
2123 "noc_ag 2028 "noc_aggr_south_sf";
2124 2029
2125 assigned-clocks = <&g 2030 assigned-clocks = <&gcc GCC_PCIE_2B_AUX_CLK>;
2126 assigned-clock-rates 2031 assigned-clock-rates = <19200000>;
2127 2032
2128 interconnects = <&agg 2033 interconnects = <&aggre2_noc MASTER_PCIE_2B 0 &mc_virt SLAVE_EBI1 0>,
2129 <&gem 2034 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2B 0>;
2130 interconnect-names = 2035 interconnect-names = "pcie-mem", "cpu-pcie";
2131 2036
2132 resets = <&gcc GCC_PC 2037 resets = <&gcc GCC_PCIE_2B_BCR>;
2133 reset-names = "pci"; 2038 reset-names = "pci";
2134 2039
2135 power-domains = <&gcc 2040 power-domains = <&gcc PCIE_2B_GDSC>;
2136 required-opps = <&rpm <<
2137 2041
2138 phys = <&pcie2b_phy>; 2042 phys = <&pcie2b_phy>;
2139 phy-names = "pciephy" 2043 phy-names = "pciephy";
2140 2044
2141 status = "disabled"; 2045 status = "disabled";
2142 <<
2143 pcie2b_port0: pcie@0 <<
2144 device_type = <<
2145 reg = <0x0 0x <<
2146 bus-range = < <<
2147 <<
2148 #address-cell <<
2149 #size-cells = <<
2150 ranges; <<
2151 }; <<
2152 }; 2046 };
2153 2047
2154 pcie2b_phy: phy@1c1e000 { 2048 pcie2b_phy: phy@1c1e000 {
2155 compatible = "qcom,sc 2049 compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy";
2156 reg = <0x0 0x01c1e000 2050 reg = <0x0 0x01c1e000 0x0 0x2000>;
2157 2051
2158 clocks = <&gcc GCC_PC 2052 clocks = <&gcc GCC_PCIE_2B_AUX_CLK>,
2159 <&gcc GCC_PC 2053 <&gcc GCC_PCIE_2B_CFG_AHB_CLK>,
2160 <&gcc GCC_PC 2054 <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
2161 <&gcc GCC_PC 2055 <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>,
2162 <&gcc GCC_PC 2056 <&gcc GCC_PCIE_2B_PIPE_CLK>,
2163 <&gcc GCC_PC 2057 <&gcc GCC_PCIE_2B_PIPEDIV2_CLK>;
2164 clock-names = "aux", 2058 clock-names = "aux", "cfg_ahb", "ref", "rchng",
2165 "pipe", 2059 "pipe", "pipediv2";
2166 2060
2167 assigned-clocks = <&g 2061 assigned-clocks = <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>;
2168 assigned-clock-rates 2062 assigned-clock-rates = <100000000>;
2169 2063
2170 power-domains = <&gcc 2064 power-domains = <&gcc PCIE_2B_GDSC>;
2171 2065
2172 resets = <&gcc GCC_PC 2066 resets = <&gcc GCC_PCIE_2B_PHY_BCR>;
2173 reset-names = "phy"; 2067 reset-names = "phy";
2174 2068
2175 #clock-cells = <0>; 2069 #clock-cells = <0>;
2176 clock-output-names = 2070 clock-output-names = "pcie_2b_pipe_clk";
2177 2071
2178 #phy-cells = <0>; 2072 #phy-cells = <0>;
2179 2073
2180 status = "disabled"; 2074 status = "disabled";
2181 }; 2075 };
2182 2076
2183 pcie2a: pcie@1c20000 { 2077 pcie2a: pcie@1c20000 {
2184 device_type = "pci"; 2078 device_type = "pci";
2185 compatible = "qcom,pc 2079 compatible = "qcom,pcie-sc8280xp";
2186 reg = <0x0 0x01c20000 2080 reg = <0x0 0x01c20000 0x0 0x3000>,
2187 <0x0 0x3c000000 2081 <0x0 0x3c000000 0x0 0xf1d>,
2188 <0x0 0x3c000f20 2082 <0x0 0x3c000f20 0x0 0xa8>,
2189 <0x0 0x3c001000 2083 <0x0 0x3c001000 0x0 0x1000>,
2190 <0x0 0x3c100000 2084 <0x0 0x3c100000 0x0 0x100000>,
2191 <0x0 0x01c23000 2085 <0x0 0x01c23000 0x0 0x1000>;
2192 reg-names = "parf", " 2086 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2193 #address-cells = <3>; 2087 #address-cells = <3>;
2194 #size-cells = <2>; 2088 #size-cells = <2>;
2195 ranges = <0x01000000 2089 ranges = <0x01000000 0x0 0x00000000 0x0 0x3c200000 0x0 0x100000>,
2196 <0x02000000 2090 <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>;
2197 bus-range = <0x00 0xf 2091 bus-range = <0x00 0xff>;
2198 2092
2199 dma-coherent; 2093 dma-coherent;
2200 2094
2201 linux,pci-domain = <2 2095 linux,pci-domain = <2>;
2202 num-lanes = <4>; 2096 num-lanes = <4>;
2203 2097
2204 msi-map = <0x0 &its 0 <<
2205 <<
2206 interrupts = <GIC_SPI 2098 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
2207 <GIC_SPI 2099 <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>,
2208 <GIC_SPI 2100 <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>,
2209 <GIC_SPI 2101 <GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH>;
2210 interrupt-names = "ms 2102 interrupt-names = "msi0", "msi1", "msi2", "msi3";
2211 2103
2212 #interrupt-cells = <1 2104 #interrupt-cells = <1>;
2213 interrupt-map-mask = 2105 interrupt-map-mask = <0 0 0 0x7>;
2214 interrupt-map = <0 0 2106 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>,
2215 <0 0 2107 <0 0 0 2 &intc 0 0 GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>,
2216 <0 0 2108 <0 0 0 3 &intc 0 0 GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>,
2217 <0 0 2109 <0 0 0 4 &intc 0 0 GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>;
2218 2110
2219 clocks = <&gcc GCC_PC 2111 clocks = <&gcc GCC_PCIE_2A_AUX_CLK>,
2220 <&gcc GCC_PC 2112 <&gcc GCC_PCIE_2A_CFG_AHB_CLK>,
2221 <&gcc GCC_PC 2113 <&gcc GCC_PCIE_2A_MSTR_AXI_CLK>,
2222 <&gcc GCC_PC 2114 <&gcc GCC_PCIE_2A_SLV_AXI_CLK>,
2223 <&gcc GCC_PC 2115 <&gcc GCC_PCIE_2A_SLV_Q2A_AXI_CLK>,
2224 <&gcc GCC_DD 2116 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
2225 <&gcc GCC_AG 2117 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
2226 <&gcc GCC_AG 2118 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
2227 clock-names = "aux", 2119 clock-names = "aux",
2228 "cfg", 2120 "cfg",
2229 "bus_ma 2121 "bus_master",
2230 "bus_sl 2122 "bus_slave",
2231 "slave_ 2123 "slave_q2a",
2232 "ddrss_ 2124 "ddrss_sf_tbu",
2233 "noc_ag 2125 "noc_aggr_4",
2234 "noc_ag 2126 "noc_aggr_south_sf";
2235 2127
2236 assigned-clocks = <&g 2128 assigned-clocks = <&gcc GCC_PCIE_2A_AUX_CLK>;
2237 assigned-clock-rates 2129 assigned-clock-rates = <19200000>;
2238 2130
2239 interconnects = <&agg 2131 interconnects = <&aggre2_noc MASTER_PCIE_2A 0 &mc_virt SLAVE_EBI1 0>,
2240 <&gem 2132 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2A 0>;
2241 interconnect-names = 2133 interconnect-names = "pcie-mem", "cpu-pcie";
2242 2134
2243 resets = <&gcc GCC_PC 2135 resets = <&gcc GCC_PCIE_2A_BCR>;
2244 reset-names = "pci"; 2136 reset-names = "pci";
2245 2137
2246 power-domains = <&gcc 2138 power-domains = <&gcc PCIE_2A_GDSC>;
2247 required-opps = <&rpm <<
2248 2139
2249 phys = <&pcie2a_phy>; 2140 phys = <&pcie2a_phy>;
2250 phy-names = "pciephy" 2141 phy-names = "pciephy";
2251 2142
2252 status = "disabled"; 2143 status = "disabled";
2253 <<
2254 pcie2a_port0: pcie@0 <<
2255 device_type = <<
2256 reg = <0x0 0x <<
2257 bus-range = < <<
2258 <<
2259 #address-cell <<
2260 #size-cells = <<
2261 ranges; <<
2262 }; <<
2263 }; 2144 };
2264 2145
2265 pcie2a_phy: phy@1c24000 { 2146 pcie2a_phy: phy@1c24000 {
2266 compatible = "qcom,sc 2147 compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy";
2267 reg = <0x0 0x01c24000 2148 reg = <0x0 0x01c24000 0x0 0x2000>,
2268 <0x0 0x01c26000 2149 <0x0 0x01c26000 0x0 0x2000>;
2269 2150
2270 clocks = <&gcc GCC_PC 2151 clocks = <&gcc GCC_PCIE_2A_AUX_CLK>,
2271 <&gcc GCC_PC 2152 <&gcc GCC_PCIE_2A_CFG_AHB_CLK>,
2272 <&gcc GCC_PC 2153 <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
2273 <&gcc GCC_PC 2154 <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>,
2274 <&gcc GCC_PC 2155 <&gcc GCC_PCIE_2A_PIPE_CLK>,
2275 <&gcc GCC_PC 2156 <&gcc GCC_PCIE_2A_PIPEDIV2_CLK>;
2276 clock-names = "aux", 2157 clock-names = "aux", "cfg_ahb", "ref", "rchng",
2277 "pipe", 2158 "pipe", "pipediv2";
2278 2159
2279 assigned-clocks = <&g 2160 assigned-clocks = <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>;
2280 assigned-clock-rates 2161 assigned-clock-rates = <100000000>;
2281 2162
2282 power-domains = <&gcc 2163 power-domains = <&gcc PCIE_2A_GDSC>;
2283 2164
2284 resets = <&gcc GCC_PC 2165 resets = <&gcc GCC_PCIE_2A_PHY_BCR>;
2285 reset-names = "phy"; 2166 reset-names = "phy";
2286 2167
2287 qcom,4ln-config-sel = 2168 qcom,4ln-config-sel = <&tcsr 0xa044 0>;
2288 2169
2289 #clock-cells = <0>; 2170 #clock-cells = <0>;
2290 clock-output-names = 2171 clock-output-names = "pcie_2a_pipe_clk";
2291 2172
2292 #phy-cells = <0>; 2173 #phy-cells = <0>;
2293 2174
2294 status = "disabled"; 2175 status = "disabled";
2295 }; 2176 };
2296 2177
2297 ufs_mem_hc: ufs@1d84000 { 2178 ufs_mem_hc: ufs@1d84000 {
2298 compatible = "qcom,sc 2179 compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc",
2299 "jedec,u 2180 "jedec,ufs-2.0";
2300 reg = <0 0x01d84000 0 2181 reg = <0 0x01d84000 0 0x3000>;
2301 interrupts = <GIC_SPI 2182 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2302 phys = <&ufs_mem_phy> 2183 phys = <&ufs_mem_phy>;
2303 phy-names = "ufsphy"; 2184 phy-names = "ufsphy";
2304 lanes-per-direction = 2185 lanes-per-direction = <2>;
2305 #reset-cells = <1>; 2186 #reset-cells = <1>;
2306 resets = <&gcc GCC_UF 2187 resets = <&gcc GCC_UFS_PHY_BCR>;
2307 reset-names = "rst"; 2188 reset-names = "rst";
2308 2189
2309 power-domains = <&gcc 2190 power-domains = <&gcc UFS_PHY_GDSC>;
2310 required-opps = <&rpm 2191 required-opps = <&rpmhpd_opp_nom>;
2311 2192
2312 iommus = <&apps_smmu 2193 iommus = <&apps_smmu 0xe0 0x0>;
2313 dma-coherent; 2194 dma-coherent;
2314 2195
2315 clocks = <&gcc GCC_UF 2196 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
2316 <&gcc GCC_AG 2197 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2317 <&gcc GCC_UF 2198 <&gcc GCC_UFS_PHY_AHB_CLK>,
2318 <&gcc GCC_UF 2199 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2319 <&gcc GCC_UF 2200 <&gcc GCC_UFS_REF_CLKREF_CLK>,
2320 <&gcc GCC_UF 2201 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2321 <&gcc GCC_UF 2202 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2322 <&gcc GCC_UF 2203 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
2323 clock-names = "core_c 2204 clock-names = "core_clk",
2324 "bus_ag 2205 "bus_aggr_clk",
2325 "iface_ 2206 "iface_clk",
2326 "core_c 2207 "core_clk_unipro",
2327 "ref_cl 2208 "ref_clk",
2328 "tx_lan 2209 "tx_lane0_sync_clk",
2329 "rx_lan 2210 "rx_lane0_sync_clk",
2330 "rx_lan 2211 "rx_lane1_sync_clk";
2331 freq-table-hz = <7500 2212 freq-table-hz = <75000000 300000000>,
2332 <0 0> 2213 <0 0>,
2333 <0 0> 2214 <0 0>,
2334 <7500 2215 <75000000 300000000>,
2335 <0 0> 2216 <0 0>,
2336 <0 0> 2217 <0 0>,
2337 <0 0> 2218 <0 0>,
2338 <0 0> 2219 <0 0>;
2339 status = "disabled"; 2220 status = "disabled";
2340 }; 2221 };
2341 2222
2342 ufs_mem_phy: phy@1d87000 { 2223 ufs_mem_phy: phy@1d87000 {
2343 compatible = "qcom,sc 2224 compatible = "qcom,sc8280xp-qmp-ufs-phy";
2344 reg = <0 0x01d87000 0 2225 reg = <0 0x01d87000 0 0x1000>;
2345 2226
2346 clocks = <&rpmhcc RPM !! 2227 clocks = <&gcc GCC_UFS_CARD_CLKREF_CLK>,
2347 <&gcc GCC_UF !! 2228 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
2348 <&gcc GCC_UF !! 2229 clock-names = "ref", "ref_aux";
2349 clock-names = "ref", <<
2350 "ref_au <<
2351 "qref"; <<
2352 2230
2353 power-domains = <&gcc 2231 power-domains = <&gcc UFS_PHY_GDSC>;
2354 2232
2355 resets = <&ufs_mem_hc 2233 resets = <&ufs_mem_hc 0>;
2356 reset-names = "ufsphy 2234 reset-names = "ufsphy";
2357 2235
2358 #phy-cells = <0>; 2236 #phy-cells = <0>;
2359 2237
2360 status = "disabled"; 2238 status = "disabled";
2361 }; 2239 };
2362 2240
2363 ufs_card_hc: ufs@1da4000 { 2241 ufs_card_hc: ufs@1da4000 {
2364 compatible = "qcom,sc 2242 compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc",
2365 "jedec,u 2243 "jedec,ufs-2.0";
2366 reg = <0 0x01da4000 0 2244 reg = <0 0x01da4000 0 0x3000>;
2367 interrupts = <GIC_SPI 2245 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
2368 phys = <&ufs_card_phy 2246 phys = <&ufs_card_phy>;
2369 phy-names = "ufsphy"; 2247 phy-names = "ufsphy";
2370 lanes-per-direction = 2248 lanes-per-direction = <2>;
2371 #reset-cells = <1>; 2249 #reset-cells = <1>;
2372 resets = <&gcc GCC_UF 2250 resets = <&gcc GCC_UFS_CARD_BCR>;
2373 reset-names = "rst"; 2251 reset-names = "rst";
2374 2252
2375 power-domains = <&gcc 2253 power-domains = <&gcc UFS_CARD_GDSC>;
2376 2254
2377 iommus = <&apps_smmu 2255 iommus = <&apps_smmu 0x4a0 0x0>;
2378 dma-coherent; 2256 dma-coherent;
2379 2257
2380 clocks = <&gcc GCC_UF 2258 clocks = <&gcc GCC_UFS_CARD_AXI_CLK>,
2381 <&gcc GCC_AG 2259 <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>,
2382 <&gcc GCC_UF 2260 <&gcc GCC_UFS_CARD_AHB_CLK>,
2383 <&gcc GCC_UF 2261 <&gcc GCC_UFS_CARD_UNIPRO_CORE_CLK>,
2384 <&gcc GCC_UF 2262 <&gcc GCC_UFS_REF_CLKREF_CLK>,
2385 <&gcc GCC_UF 2263 <&gcc GCC_UFS_CARD_TX_SYMBOL_0_CLK>,
2386 <&gcc GCC_UF 2264 <&gcc GCC_UFS_CARD_RX_SYMBOL_0_CLK>,
2387 <&gcc GCC_UF 2265 <&gcc GCC_UFS_CARD_RX_SYMBOL_1_CLK>;
2388 clock-names = "core_c 2266 clock-names = "core_clk",
2389 "bus_ag 2267 "bus_aggr_clk",
2390 "iface_ 2268 "iface_clk",
2391 "core_c 2269 "core_clk_unipro",
2392 "ref_cl 2270 "ref_clk",
2393 "tx_lan 2271 "tx_lane0_sync_clk",
2394 "rx_lan 2272 "rx_lane0_sync_clk",
2395 "rx_lan 2273 "rx_lane1_sync_clk";
2396 freq-table-hz = <7500 2274 freq-table-hz = <75000000 300000000>,
2397 <0 0> 2275 <0 0>,
2398 <0 0> 2276 <0 0>,
2399 <7500 2277 <75000000 300000000>,
2400 <0 0> 2278 <0 0>,
2401 <0 0> 2279 <0 0>,
2402 <0 0> 2280 <0 0>,
2403 <0 0> 2281 <0 0>;
2404 status = "disabled"; 2282 status = "disabled";
2405 }; 2283 };
2406 2284
2407 ufs_card_phy: phy@1da7000 { 2285 ufs_card_phy: phy@1da7000 {
2408 compatible = "qcom,sc 2286 compatible = "qcom,sc8280xp-qmp-ufs-phy";
2409 reg = <0 0x01da7000 0 2287 reg = <0 0x01da7000 0 0x1000>;
2410 2288
2411 clocks = <&rpmhcc RPM !! 2289 clocks = <&gcc GCC_UFS_1_CARD_CLKREF_CLK>,
2412 <&gcc GCC_UF !! 2290 <&gcc GCC_UFS_CARD_PHY_AUX_CLK>;
2413 <&gcc GCC_UF !! 2291 clock-names = "ref", "ref_aux";
2414 clock-names = "ref", <<
2415 "ref_au <<
2416 "qref"; <<
2417 2292
2418 power-domains = <&gcc 2293 power-domains = <&gcc UFS_CARD_GDSC>;
2419 2294
2420 resets = <&ufs_card_h 2295 resets = <&ufs_card_hc 0>;
2421 reset-names = "ufsphy 2296 reset-names = "ufsphy";
2422 2297
2423 #phy-cells = <0>; 2298 #phy-cells = <0>;
2424 2299
2425 status = "disabled"; 2300 status = "disabled";
2426 }; 2301 };
2427 2302
2428 tcsr_mutex: hwlock@1f40000 { 2303 tcsr_mutex: hwlock@1f40000 {
2429 compatible = "qcom,tc 2304 compatible = "qcom,tcsr-mutex";
2430 reg = <0x0 0x01f40000 2305 reg = <0x0 0x01f40000 0x0 0x20000>;
2431 #hwlock-cells = <1>; 2306 #hwlock-cells = <1>;
2432 }; 2307 };
2433 2308
2434 tcsr: syscon@1fc0000 { 2309 tcsr: syscon@1fc0000 {
2435 compatible = "qcom,sc 2310 compatible = "qcom,sc8280xp-tcsr", "syscon";
2436 reg = <0x0 0x01fc0000 2311 reg = <0x0 0x01fc0000 0x0 0x30000>;
2437 }; 2312 };
2438 2313
2439 gpu: gpu@3d00000 { <<
2440 compatible = "qcom,ad <<
2441 <<
2442 reg = <0 0x03d00000 0 <<
2443 <0 0x03d9e000 0 <<
2444 <0 0x03d61000 0 <<
2445 reg-names = "kgsl_3d0 <<
2446 "cx_mem", <<
2447 "cx_dbgc" <<
2448 interrupts = <GIC_SPI <<
2449 iommus = <&gpu_smmu 0 <<
2450 operating-points-v2 = <<
2451 <<
2452 qcom,gmu = <&gmu>; <<
2453 interconnects = <&gem <<
2454 interconnect-names = <<
2455 #cooling-cells = <2>; <<
2456 <<
2457 status = "disabled"; <<
2458 <<
2459 gpu_opp_table: opp-ta <<
2460 compatible = <<
2461 <<
2462 opp-270000000 <<
2463 opp-h <<
2464 opp-l <<
2465 opp-p <<
2466 }; <<
2467 <<
2468 opp-410000000 <<
2469 opp-h <<
2470 opp-l <<
2471 opp-p <<
2472 }; <<
2473 <<
2474 opp-500000000 <<
2475 opp-h <<
2476 opp-l <<
2477 opp-p <<
2478 }; <<
2479 <<
2480 opp-547000000 <<
2481 opp-h <<
2482 opp-l <<
2483 opp-p <<
2484 }; <<
2485 <<
2486 opp-606000000 <<
2487 opp-h <<
2488 opp-l <<
2489 opp-p <<
2490 }; <<
2491 <<
2492 opp-640000000 <<
2493 opp-h <<
2494 opp-l <<
2495 opp-p <<
2496 }; <<
2497 <<
2498 opp-655000000 <<
2499 opp-h <<
2500 opp-l <<
2501 opp-p <<
2502 }; <<
2503 <<
2504 opp-690000000 <<
2505 opp-h <<
2506 opp-l <<
2507 opp-p <<
2508 }; <<
2509 }; <<
2510 }; <<
2511 <<
2512 gmu: gmu@3d6a000 { <<
2513 compatible = "qcom,ad <<
2514 reg = <0 0x03d6a000 0 <<
2515 <0 0x03de0000 0 <<
2516 <0 0x0b290000 0 <<
2517 reg-names = "gmu", "r <<
2518 interrupts = <GIC_SPI <<
2519 <GIC_SPI <<
2520 interrupt-names = "hf <<
2521 clocks = <&gpucc GPU_ <<
2522 <&gpucc GPU_ <<
2523 <&gcc GCC_DD <<
2524 <&gcc GCC_GP <<
2525 <&gpucc GPU_ <<
2526 <&gpucc GPU_ <<
2527 <&gpucc GPU_ <<
2528 clock-names = "gmu", <<
2529 "cxo", <<
2530 "axi", <<
2531 "memnoc <<
2532 "ahb", <<
2533 "hub", <<
2534 "smmu_v <<
2535 power-domains = <&gpu <<
2536 <&gpu <<
2537 power-domain-names = <<
2538 <<
2539 iommus = <&gpu_smmu 5 <<
2540 operating-points-v2 = <<
2541 <<
2542 gmu_opp_table: opp-ta <<
2543 compatible = <<
2544 <<
2545 opp-200000000 <<
2546 opp-h <<
2547 opp-l <<
2548 }; <<
2549 <<
2550 opp-500000000 <<
2551 opp-h <<
2552 opp-l <<
2553 }; <<
2554 }; <<
2555 }; <<
2556 <<
2557 gpucc: clock-controller@3d900 <<
2558 compatible = "qcom,sc <<
2559 reg = <0 0x03d90000 0 <<
2560 clocks = <&rpmhcc RPM <<
2561 <&gcc GCC_GP <<
2562 <&gcc GCC_GP <<
2563 clock-names = "bi_tcx <<
2564 "gcc_gp <<
2565 "gcc_gp <<
2566 <<
2567 power-domains = <&rpm <<
2568 #clock-cells = <1>; <<
2569 #reset-cells = <1>; <<
2570 #power-domain-cells = <<
2571 }; <<
2572 <<
2573 gpu_smmu: iommu@3da0000 { <<
2574 compatible = "qcom,sc <<
2575 "qcom,sm <<
2576 reg = <0 0x03da0000 0 <<
2577 #iommu-cells = <2>; <<
2578 #global-interrupts = <<
2579 interrupts = <GIC_SPI <<
2580 <GIC_SPI <<
2581 <GIC_SPI <<
2582 <GIC_SPI <<
2583 <GIC_SPI <<
2584 <GIC_SPI <<
2585 <GIC_SPI <<
2586 <GIC_SPI <<
2587 <GIC_SPI <<
2588 <GIC_SPI <<
2589 <GIC_SPI <<
2590 <GIC_SPI <<
2591 <GIC_SPI <<
2592 <GIC_SPI <<
2593 <<
2594 clocks = <&gcc GCC_GP <<
2595 <&gcc GCC_GP <<
2596 <&gpucc GPU_ <<
2597 <&gpucc GPU_ <<
2598 <&gpucc GPU_ <<
2599 <&gpucc GPU_ <<
2600 <&gpucc GPU_ <<
2601 clock-names = "gcc_gp <<
2602 "gcc_gp <<
2603 "gpu_cc <<
2604 "gpu_cc <<
2605 "gpu_cc <<
2606 "gpu_cc <<
2607 "gpu_cc <<
2608 <<
2609 power-domains = <&gpu <<
2610 dma-coherent; <<
2611 }; <<
2612 <<
2613 usb_0_hsphy: phy@88e5000 { 2314 usb_0_hsphy: phy@88e5000 {
2614 compatible = "qcom,sc 2315 compatible = "qcom,sc8280xp-usb-hs-phy",
2615 "qcom,us 2316 "qcom,usb-snps-hs-5nm-phy";
2616 reg = <0 0x088e5000 0 2317 reg = <0 0x088e5000 0 0x400>;
2617 clocks = <&rpmhcc RPM 2318 clocks = <&rpmhcc RPMH_CXO_CLK>;
2618 clock-names = "ref"; 2319 clock-names = "ref";
2619 resets = <&gcc GCC_QU 2320 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2620 2321
2621 #phy-cells = <0>; 2322 #phy-cells = <0>;
2622 2323
2623 status = "disabled"; 2324 status = "disabled";
2624 }; 2325 };
2625 2326
2626 usb_2_hsphy0: phy@88e7000 { 2327 usb_2_hsphy0: phy@88e7000 {
2627 compatible = "qcom,sc 2328 compatible = "qcom,sc8280xp-usb-hs-phy",
2628 "qcom,us 2329 "qcom,usb-snps-hs-5nm-phy";
2629 reg = <0 0x088e7000 0 2330 reg = <0 0x088e7000 0 0x400>;
2630 clocks = <&gcc GCC_US 2331 clocks = <&gcc GCC_USB2_HS0_CLKREF_CLK>;
2631 clock-names = "ref"; 2332 clock-names = "ref";
2632 resets = <&gcc GCC_QU 2333 resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>;
2633 2334
2634 #phy-cells = <0>; 2335 #phy-cells = <0>;
2635 2336
2636 status = "disabled"; 2337 status = "disabled";
2637 }; 2338 };
2638 2339
2639 usb_2_hsphy1: phy@88e8000 { 2340 usb_2_hsphy1: phy@88e8000 {
2640 compatible = "qcom,sc 2341 compatible = "qcom,sc8280xp-usb-hs-phy",
2641 "qcom,us 2342 "qcom,usb-snps-hs-5nm-phy";
2642 reg = <0 0x088e8000 0 2343 reg = <0 0x088e8000 0 0x400>;
2643 clocks = <&gcc GCC_US 2344 clocks = <&gcc GCC_USB2_HS1_CLKREF_CLK>;
2644 clock-names = "ref"; 2345 clock-names = "ref";
2645 resets = <&gcc GCC_QU 2346 resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>;
2646 2347
2647 #phy-cells = <0>; 2348 #phy-cells = <0>;
2648 2349
2649 status = "disabled"; 2350 status = "disabled";
2650 }; 2351 };
2651 2352
2652 usb_2_hsphy2: phy@88e9000 { 2353 usb_2_hsphy2: phy@88e9000 {
2653 compatible = "qcom,sc 2354 compatible = "qcom,sc8280xp-usb-hs-phy",
2654 "qcom,us 2355 "qcom,usb-snps-hs-5nm-phy";
2655 reg = <0 0x088e9000 0 2356 reg = <0 0x088e9000 0 0x400>;
2656 clocks = <&gcc GCC_US 2357 clocks = <&gcc GCC_USB2_HS2_CLKREF_CLK>;
2657 clock-names = "ref"; 2358 clock-names = "ref";
2658 resets = <&gcc GCC_QU 2359 resets = <&gcc GCC_QUSB2PHY_HS2_MP_BCR>;
2659 2360
2660 #phy-cells = <0>; 2361 #phy-cells = <0>;
2661 2362
2662 status = "disabled"; 2363 status = "disabled";
2663 }; 2364 };
2664 2365
2665 usb_2_hsphy3: phy@88ea000 { 2366 usb_2_hsphy3: phy@88ea000 {
2666 compatible = "qcom,sc 2367 compatible = "qcom,sc8280xp-usb-hs-phy",
2667 "qcom,us 2368 "qcom,usb-snps-hs-5nm-phy";
2668 reg = <0 0x088ea000 0 2369 reg = <0 0x088ea000 0 0x400>;
2669 clocks = <&gcc GCC_US 2370 clocks = <&gcc GCC_USB2_HS3_CLKREF_CLK>;
2670 clock-names = "ref"; 2371 clock-names = "ref";
2671 resets = <&gcc GCC_QU 2372 resets = <&gcc GCC_QUSB2PHY_HS3_MP_BCR>;
2672 2373
2673 #phy-cells = <0>; 2374 #phy-cells = <0>;
2674 2375
2675 status = "disabled"; 2376 status = "disabled";
2676 }; 2377 };
2677 2378
2678 usb_2_qmpphy0: phy@88ef000 { 2379 usb_2_qmpphy0: phy@88ef000 {
2679 compatible = "qcom,sc 2380 compatible = "qcom,sc8280xp-qmp-usb3-uni-phy";
2680 reg = <0 0x088ef000 0 2381 reg = <0 0x088ef000 0 0x2000>;
2681 2382
2682 clocks = <&gcc GCC_US 2383 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
2683 <&gcc GCC_US 2384 <&gcc GCC_USB3_MP0_CLKREF_CLK>,
2684 <&gcc GCC_US 2385 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
2685 <&gcc GCC_US 2386 <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>;
2686 clock-names = "aux", 2387 clock-names = "aux", "ref", "com_aux", "pipe";
2687 2388
2688 resets = <&gcc GCC_US 2389 resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>,
2689 <&gcc GCC_US 2390 <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>;
2690 reset-names = "phy", 2391 reset-names = "phy", "phy_phy";
2691 2392
2692 power-domains = <&gcc 2393 power-domains = <&gcc USB30_MP_GDSC>;
2693 2394
2694 #clock-cells = <0>; 2395 #clock-cells = <0>;
2695 clock-output-names = 2396 clock-output-names = "usb2_phy0_pipe_clk";
2696 2397
2697 #phy-cells = <0>; 2398 #phy-cells = <0>;
2698 2399
2699 status = "disabled"; 2400 status = "disabled";
2700 }; 2401 };
2701 2402
2702 usb_2_qmpphy1: phy@88f1000 { 2403 usb_2_qmpphy1: phy@88f1000 {
2703 compatible = "qcom,sc 2404 compatible = "qcom,sc8280xp-qmp-usb3-uni-phy";
2704 reg = <0 0x088f1000 0 2405 reg = <0 0x088f1000 0 0x2000>;
2705 2406
2706 clocks = <&gcc GCC_US 2407 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
2707 <&gcc GCC_US 2408 <&gcc GCC_USB3_MP1_CLKREF_CLK>,
2708 <&gcc GCC_US 2409 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
2709 <&gcc GCC_US 2410 <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>;
2710 clock-names = "aux", 2411 clock-names = "aux", "ref", "com_aux", "pipe";
2711 2412
2712 resets = <&gcc GCC_US 2413 resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>,
2713 <&gcc GCC_US 2414 <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>;
2714 reset-names = "phy", 2415 reset-names = "phy", "phy_phy";
2715 2416
2716 power-domains = <&gcc 2417 power-domains = <&gcc USB30_MP_GDSC>;
2717 2418
2718 #clock-cells = <0>; 2419 #clock-cells = <0>;
2719 clock-output-names = 2420 clock-output-names = "usb2_phy1_pipe_clk";
2720 2421
2721 #phy-cells = <0>; 2422 #phy-cells = <0>;
2722 2423
2723 status = "disabled"; 2424 status = "disabled";
2724 }; 2425 };
2725 2426
2726 remoteproc_adsp: remoteproc@3 2427 remoteproc_adsp: remoteproc@3000000 {
2727 compatible = "qcom,sc 2428 compatible = "qcom,sc8280xp-adsp-pas";
2728 reg = <0 0x03000000 0 2429 reg = <0 0x03000000 0 0x100>;
2729 2430
2730 interrupts-extended = !! 2431 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
2731 2432 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
2732 2433 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
2733 2434 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
2734 2435 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>,
2735 2436 <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>;
2736 interrupt-names = "wd 2437 interrupt-names = "wdog", "fatal", "ready",
2737 "ha 2438 "handover", "stop-ack", "shutdown-ack";
2738 2439
2739 clocks = <&rpmhcc RPM 2440 clocks = <&rpmhcc RPMH_CXO_CLK>;
2740 clock-names = "xo"; 2441 clock-names = "xo";
2741 2442
2742 power-domains = <&rpm 2443 power-domains = <&rpmhpd SC8280XP_LCX>,
2743 <&rpm 2444 <&rpmhpd SC8280XP_LMX>;
2744 power-domain-names = 2445 power-domain-names = "lcx", "lmx";
2745 2446
2746 memory-region = <&pil 2447 memory-region = <&pil_adsp_mem>;
2747 2448
2748 qcom,qmp = <&aoss_qmp 2449 qcom,qmp = <&aoss_qmp>;
2749 2450
2750 qcom,smem-states = <& 2451 qcom,smem-states = <&smp2p_adsp_out 0>;
2751 qcom,smem-state-names 2452 qcom,smem-state-names = "stop";
2752 2453
2753 status = "disabled"; 2454 status = "disabled";
2754 2455
2755 remoteproc_adsp_glink 2456 remoteproc_adsp_glink: glink-edge {
2756 interrupts-ex 2457 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
2757 2458 IPCC_MPROC_SIGNAL_GLINK_QMP
2758 2459 IRQ_TYPE_EDGE_RISING>;
2759 mboxes = <&ip 2460 mboxes = <&ipcc IPCC_CLIENT_LPASS
2760 2461 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2761 2462
2762 label = "lpas 2463 label = "lpass";
2763 qcom,remote-p 2464 qcom,remote-pid = <2>;
2764 2465
2765 gpr { 2466 gpr {
2766 compa 2467 compatible = "qcom,gpr";
2767 qcom, 2468 qcom,glink-channels = "adsp_apps";
2768 qcom, 2469 qcom,domain = <GPR_DOMAIN_ID_ADSP>;
2769 qcom, 2470 qcom,intents = <512 20>;
2770 #addr 2471 #address-cells = <1>;
2771 #size 2472 #size-cells = <0>;
2772 2473
2773 q6apm 2474 q6apm: service@1 {
2774 2475 compatible = "qcom,q6apm";
2775 2476 reg = <GPR_APM_MODULE_IID>;
2776 2477 #sound-dai-cells = <0>;
2777 2478 qcom,protection-domain = "avs/audio",
2778 2479 "msm/adsp/audio_pd";
2779 2480 q6apmdai: dais {
2780 2481 compatible = "qcom,q6apm-dais";
2781 2482 iommus = <&apps_smmu 0x0c01 0x0>;
2782 2483 };
2783 2484
2784 2485 q6apmbedai: bedais {
2785 2486 compatible = "qcom,q6apm-lpass-dais";
2786 2487 #sound-dai-cells = <1>;
2787 2488 };
2788 }; 2489 };
2789 2490
2790 q6prm 2491 q6prm: service@2 {
2791 2492 compatible = "qcom,q6prm";
2792 2493 reg = <GPR_PRM_MODULE_IID>;
2793 2494 qcom,protection-domain = "avs/audio",
2794 2495 "msm/adsp/audio_pd";
2795 2496 q6prmcc: clock-controller {
2796 2497 compatible = "qcom,q6prm-lpass-clocks";
2797 2498 #clock-cells = <2>;
2798 2499 };
2799 }; 2500 };
2800 }; 2501 };
2801 }; 2502 };
2802 }; 2503 };
2803 2504
2804 rxmacro: rxmacro@3200000 { 2505 rxmacro: rxmacro@3200000 {
2805 compatible = "qcom,sc 2506 compatible = "qcom,sc8280xp-lpass-rx-macro";
2806 reg = <0 0x03200000 0 2507 reg = <0 0x03200000 0 0x1000>;
2807 clocks = <&q6prmcc LP 2508 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2808 <&q6prmcc LP 2509 <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2809 <&q6prmcc LP 2510 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2810 <&q6prmcc LP 2511 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2811 <&vamacro>; 2512 <&vamacro>;
2812 clock-names = "mclk", 2513 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2813 assigned-clocks = <&q 2514 assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2814 <&q 2515 <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2815 assigned-clock-rates 2516 assigned-clock-rates = <19200000>, <19200000>;
2816 2517
2817 clock-output-names = 2518 clock-output-names = "mclk";
2818 #clock-cells = <0>; 2519 #clock-cells = <0>;
2819 #sound-dai-cells = <1 2520 #sound-dai-cells = <1>;
2820 2521
2821 pinctrl-names = "defa 2522 pinctrl-names = "default";
2822 pinctrl-0 = <&rx_swr_ 2523 pinctrl-0 = <&rx_swr_default>;
2823 2524
2824 status = "disabled"; 2525 status = "disabled";
2825 }; 2526 };
2826 2527
2827 swr1: soundwire@3210000 { !! 2528 swr1: soundwire-controller@3210000 {
2828 compatible = "qcom,so 2529 compatible = "qcom,soundwire-v1.6.0";
2829 reg = <0 0x03210000 0 2530 reg = <0 0x03210000 0 0x2000>;
2830 interrupts = <GIC_SPI 2531 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
2831 clocks = <&rxmacro>; 2532 clocks = <&rxmacro>;
2832 clock-names = "iface" 2533 clock-names = "iface";
2833 resets = <&lpass_audi <<
2834 reset-names = "swr_au <<
2835 label = "RX"; 2534 label = "RX";
2836 2535
2837 qcom,din-ports = <0>; 2536 qcom,din-ports = <0>;
2838 qcom,dout-ports = <5> 2537 qcom,dout-ports = <5>;
2839 2538
2840 qcom,ports-sinterval- 2539 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
2841 qcom,ports-offset1 = 2540 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>;
2842 qcom,ports-offset2 = 2541 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>;
2843 qcom,ports-hstart = 2542 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0x00 0xff 0xff>;
2844 qcom,ports-hstop = 2543 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0x0f 0xff 0xff>;
2845 qcom,ports-word-lengt 2544 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2846 qcom,ports-block-pack 2545 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff>;
2847 qcom,ports-lane-contr 2546 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2848 qcom,ports-block-grou 2547 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2849 2548
2850 #sound-dai-cells = <1 2549 #sound-dai-cells = <1>;
2851 #address-cells = <2>; 2550 #address-cells = <2>;
2852 #size-cells = <0>; 2551 #size-cells = <0>;
2853 2552
2854 status = "disabled"; 2553 status = "disabled";
2855 }; 2554 };
2856 2555
2857 txmacro: txmacro@3220000 { 2556 txmacro: txmacro@3220000 {
2858 compatible = "qcom,sc 2557 compatible = "qcom,sc8280xp-lpass-tx-macro";
2859 reg = <0 0x03220000 0 2558 reg = <0 0x03220000 0 0x1000>;
2860 pinctrl-names = "defa 2559 pinctrl-names = "default";
2861 pinctrl-0 = <&tx_swr_ 2560 pinctrl-0 = <&tx_swr_default>;
2862 clocks = <&q6prmcc LP 2561 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2863 <&q6prmcc LP 2562 <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2864 <&q6prmcc LP 2563 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2865 <&q6prmcc LP 2564 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2866 <&vamacro>; 2565 <&vamacro>;
2867 2566
2868 clock-names = "mclk", 2567 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2869 assigned-clocks = <&q 2568 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2870 <&q 2569 <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2871 assigned-clock-rates 2570 assigned-clock-rates = <19200000>, <19200000>;
2872 clock-output-names = 2571 clock-output-names = "mclk";
2873 2572
2874 #clock-cells = <0>; 2573 #clock-cells = <0>;
2875 #sound-dai-cells = <1 2574 #sound-dai-cells = <1>;
2876 2575
2877 status = "disabled"; 2576 status = "disabled";
2878 }; 2577 };
2879 2578
2880 wsamacro: codec@3240000 { 2579 wsamacro: codec@3240000 {
2881 compatible = "qcom,sc 2580 compatible = "qcom,sc8280xp-lpass-wsa-macro";
2882 reg = <0 0x03240000 0 2581 reg = <0 0x03240000 0 0x1000>;
2883 clocks = <&q6prmcc LP 2582 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2884 <&q6prmcc LP 2583 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2885 <&q6prmcc LP 2584 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2886 <&q6prmcc LP 2585 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2887 <&vamacro>; 2586 <&vamacro>;
2888 clock-names = "mclk", 2587 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2889 assigned-clocks = <&q 2588 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2890 <&q 2589 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2891 assigned-clock-rates 2590 assigned-clock-rates = <19200000>, <19200000>;
2892 2591
2893 #clock-cells = <0>; 2592 #clock-cells = <0>;
2894 clock-output-names = 2593 clock-output-names = "mclk";
2895 #sound-dai-cells = <1 2594 #sound-dai-cells = <1>;
2896 2595
2897 pinctrl-names = "defa 2596 pinctrl-names = "default";
2898 pinctrl-0 = <&wsa_swr 2597 pinctrl-0 = <&wsa_swr_default>;
2899 2598
2900 status = "disabled"; 2599 status = "disabled";
2901 }; 2600 };
2902 2601
2903 swr0: soundwire@3250000 { !! 2602 swr0: soundwire-controller@3250000 {
2904 reg = <0 0x03250000 0 2603 reg = <0 0x03250000 0 0x2000>;
2905 compatible = "qcom,so 2604 compatible = "qcom,soundwire-v1.6.0";
2906 interrupts = <GIC_SPI 2605 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
2907 clocks = <&wsamacro>; 2606 clocks = <&wsamacro>;
2908 clock-names = "iface" 2607 clock-names = "iface";
2909 resets = <&lpass_audi <<
2910 reset-names = "swr_au <<
2911 label = "WSA"; 2608 label = "WSA";
2912 2609
2913 qcom,din-ports = <2>; 2610 qcom,din-ports = <2>;
2914 qcom,dout-ports = <6> 2611 qcom,dout-ports = <6>;
2915 2612
2916 qcom,ports-sinterval- 2613 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2917 qcom,ports-offset1 = 2614 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2918 qcom,ports-offset2 = 2615 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2919 qcom,ports-hstart = 2616 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2920 qcom,ports-hstop = 2617 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2921 qcom,ports-word-lengt 2618 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2922 qcom,ports-block-pack 2619 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
2923 qcom,ports-block-grou 2620 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2924 qcom,ports-lane-contr 2621 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2925 2622
2926 #sound-dai-cells = <1 2623 #sound-dai-cells = <1>;
2927 #address-cells = <2>; 2624 #address-cells = <2>;
2928 #size-cells = <0>; 2625 #size-cells = <0>;
2929 2626
2930 status = "disabled"; 2627 status = "disabled";
2931 }; 2628 };
2932 2629
2933 lpass_audiocc: clock-controll !! 2630 swr2: soundwire-controller@3330000 {
2934 compatible = "qcom,sc <<
2935 reg = <0 0x032a9000 0 <<
2936 #clock-cells = <1>; <<
2937 #reset-cells = <1>; <<
2938 }; <<
2939 <<
2940 swr2: soundwire@3330000 { <<
2941 compatible = "qcom,so 2631 compatible = "qcom,soundwire-v1.6.0";
2942 reg = <0 0x03330000 0 2632 reg = <0 0x03330000 0 0x2000>;
2943 interrupts = <GIC_SPI 2633 interrupts = <GIC_SPI 959 IRQ_TYPE_LEVEL_HIGH>,
2944 <GIC_SPI 2634 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>;
2945 interrupt-names = "co 2635 interrupt-names = "core", "wakeup";
2946 2636
2947 clocks = <&txmacro>; 2637 clocks = <&txmacro>;
2948 clock-names = "iface" 2638 clock-names = "iface";
2949 resets = <&lpasscc LP <<
2950 reset-names = "swr_au <<
2951 label = "TX"; 2639 label = "TX";
2952 #sound-dai-cells = <1 2640 #sound-dai-cells = <1>;
2953 #address-cells = <2>; 2641 #address-cells = <2>;
2954 #size-cells = <0>; 2642 #size-cells = <0>;
2955 2643
2956 qcom,din-ports = <4>; 2644 qcom,din-ports = <4>;
2957 qcom,dout-ports = <0> 2645 qcom,dout-ports = <0>;
2958 qcom,ports-sinterval- 2646 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
2959 qcom,ports-offset1 = 2647 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02 0x00>;
2960 qcom,ports-offset2 = 2648 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
2961 qcom,ports-block-pack 2649 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
2962 qcom,ports-hstart = 2650 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
2963 qcom,ports-hstop = 2651 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
2964 qcom,ports-word-lengt 2652 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
2965 qcom,ports-block-grou 2653 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
2966 qcom,ports-lane-contr 2654 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00 0x01>;
2967 2655
2968 status = "disabled"; 2656 status = "disabled";
2969 }; 2657 };
2970 2658
2971 vamacro: codec@3370000 { 2659 vamacro: codec@3370000 {
2972 compatible = "qcom,sc 2660 compatible = "qcom,sc8280xp-lpass-va-macro";
2973 reg = <0 0x03370000 0 2661 reg = <0 0x03370000 0 0x1000>;
2974 clocks = <&q6prmcc LP 2662 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2975 <&q6prmcc LP 2663 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2976 <&q6prmcc LP 2664 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2977 <&q6prmcc LP 2665 <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2978 clock-names = "mclk", 2666 clock-names = "mclk", "macro", "dcodec", "npl";
2979 assigned-clocks = <&q 2667 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2980 assigned-clock-rates 2668 assigned-clock-rates = <19200000>;
2981 2669
2982 #clock-cells = <0>; 2670 #clock-cells = <0>;
2983 clock-output-names = 2671 clock-output-names = "fsgen";
2984 #sound-dai-cells = <1 2672 #sound-dai-cells = <1>;
2985 2673
2986 status = "disabled"; 2674 status = "disabled";
2987 }; 2675 };
2988 2676
2989 lpass_tlmm: pinctrl@33c0000 { 2677 lpass_tlmm: pinctrl@33c0000 {
2990 compatible = "qcom,sc 2678 compatible = "qcom,sc8280xp-lpass-lpi-pinctrl";
2991 reg = <0 0x33c0000 0x 2679 reg = <0 0x33c0000 0x0 0x20000>,
2992 <0 0x3550000 0x 2680 <0 0x3550000 0x0 0x10000>;
2993 gpio-controller; 2681 gpio-controller;
2994 #gpio-cells = <2>; 2682 #gpio-cells = <2>;
2995 gpio-ranges = <&lpass 2683 gpio-ranges = <&lpass_tlmm 0 0 19>;
2996 2684
2997 clocks = <&q6prmcc LP 2685 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2998 <&q6prmcc LP 2686 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2999 clock-names = "core", 2687 clock-names = "core", "audio";
3000 2688
3001 status = "disabled"; 2689 status = "disabled";
3002 2690
3003 tx_swr_default: tx-sw 2691 tx_swr_default: tx-swr-default-state {
3004 clk-pins { 2692 clk-pins {
3005 pins 2693 pins = "gpio0";
3006 funct 2694 function = "swr_tx_clk";
3007 drive 2695 drive-strength = <2>;
3008 slew- 2696 slew-rate = <1>;
3009 bias- 2697 bias-disable;
3010 }; 2698 };
3011 2699
3012 data-pins { 2700 data-pins {
3013 pins 2701 pins = "gpio1", "gpio2";
3014 funct 2702 function = "swr_tx_data";
3015 drive 2703 drive-strength = <2>;
3016 slew- 2704 slew-rate = <1>;
3017 bias- 2705 bias-bus-hold;
3018 }; 2706 };
3019 }; 2707 };
3020 2708
3021 rx_swr_default: rx-sw 2709 rx_swr_default: rx-swr-default-state {
3022 clk-pins { 2710 clk-pins {
3023 pins 2711 pins = "gpio3";
3024 funct 2712 function = "swr_rx_clk";
3025 drive 2713 drive-strength = <2>;
3026 slew- 2714 slew-rate = <1>;
3027 bias- 2715 bias-disable;
3028 }; 2716 };
3029 2717
3030 data-pins { 2718 data-pins {
3031 pins 2719 pins = "gpio4", "gpio5";
3032 funct 2720 function = "swr_rx_data";
3033 drive 2721 drive-strength = <2>;
3034 slew- 2722 slew-rate = <1>;
3035 bias- 2723 bias-bus-hold;
3036 }; 2724 };
3037 }; 2725 };
3038 2726
3039 dmic01_default: dmic0 2727 dmic01_default: dmic01-default-state {
3040 clk-pins { 2728 clk-pins {
3041 pins 2729 pins = "gpio6";
3042 funct 2730 function = "dmic1_clk";
3043 drive 2731 drive-strength = <8>;
3044 outpu 2732 output-high;
3045 }; 2733 };
3046 2734
3047 data-pins { 2735 data-pins {
3048 pins 2736 pins = "gpio7";
3049 funct 2737 function = "dmic1_data";
3050 drive 2738 drive-strength = <8>;
3051 input 2739 input-enable;
3052 }; 2740 };
3053 }; 2741 };
3054 2742
3055 dmic01_sleep: dmic01- 2743 dmic01_sleep: dmic01-sleep-state {
3056 clk-pins { 2744 clk-pins {
3057 pins 2745 pins = "gpio6";
3058 funct 2746 function = "dmic1_clk";
3059 drive 2747 drive-strength = <2>;
3060 bias- 2748 bias-disable;
3061 outpu 2749 output-low;
3062 }; 2750 };
3063 2751
3064 data-pins { 2752 data-pins {
3065 pins 2753 pins = "gpio7";
3066 funct 2754 function = "dmic1_data";
3067 drive 2755 drive-strength = <2>;
3068 bias- 2756 bias-pull-down;
3069 input 2757 input-enable;
3070 }; 2758 };
3071 }; 2759 };
3072 2760
3073 dmic23_default: dmic2 !! 2761 dmic02_default: dmic02-default-state {
3074 clk-pins { 2762 clk-pins {
3075 pins 2763 pins = "gpio8";
3076 funct 2764 function = "dmic2_clk";
3077 drive 2765 drive-strength = <8>;
3078 outpu 2766 output-high;
3079 }; 2767 };
3080 2768
3081 data-pins { 2769 data-pins {
3082 pins 2770 pins = "gpio9";
3083 funct 2771 function = "dmic2_data";
3084 drive 2772 drive-strength = <8>;
3085 input 2773 input-enable;
3086 }; 2774 };
3087 }; 2775 };
3088 2776
3089 dmic23_sleep: dmic23- !! 2777 dmic02_sleep: dmic02-sleep-state {
3090 clk-pins { 2778 clk-pins {
3091 pins 2779 pins = "gpio8";
3092 funct 2780 function = "dmic2_clk";
3093 drive 2781 drive-strength = <2>;
3094 bias- 2782 bias-disable;
3095 outpu 2783 output-low;
3096 }; 2784 };
3097 2785
3098 data-pins { 2786 data-pins {
3099 pins 2787 pins = "gpio9";
3100 funct 2788 function = "dmic2_data";
3101 drive 2789 drive-strength = <2>;
3102 bias- 2790 bias-pull-down;
3103 input 2791 input-enable;
3104 }; 2792 };
3105 }; 2793 };
3106 2794
3107 wsa_swr_default: wsa- 2795 wsa_swr_default: wsa-swr-default-state {
3108 clk-pins { 2796 clk-pins {
3109 pins 2797 pins = "gpio10";
3110 funct 2798 function = "wsa_swr_clk";
3111 drive 2799 drive-strength = <2>;
3112 slew- 2800 slew-rate = <1>;
3113 bias- 2801 bias-disable;
3114 }; 2802 };
3115 2803
3116 data-pins { 2804 data-pins {
3117 pins 2805 pins = "gpio11";
3118 funct 2806 function = "wsa_swr_data";
3119 drive 2807 drive-strength = <2>;
3120 slew- 2808 slew-rate = <1>;
3121 bias- 2809 bias-bus-hold;
3122 }; 2810 };
3123 }; 2811 };
3124 2812
3125 wsa2_swr_default: wsa 2813 wsa2_swr_default: wsa2-swr-default-state {
3126 clk-pins { 2814 clk-pins {
3127 pins 2815 pins = "gpio15";
3128 funct 2816 function = "wsa2_swr_clk";
3129 drive 2817 drive-strength = <2>;
3130 slew- 2818 slew-rate = <1>;
3131 bias- 2819 bias-disable;
3132 }; 2820 };
3133 2821
3134 data-pins { 2822 data-pins {
3135 pins 2823 pins = "gpio16";
3136 funct 2824 function = "wsa2_swr_data";
3137 drive 2825 drive-strength = <2>;
3138 slew- 2826 slew-rate = <1>;
3139 bias- 2827 bias-bus-hold;
3140 }; 2828 };
3141 }; 2829 };
3142 }; 2830 };
3143 2831
3144 lpasscc: clock-controller@33e <<
3145 compatible = "qcom,sc <<
3146 reg = <0 0x033e0000 0 <<
3147 #clock-cells = <1>; <<
3148 #reset-cells = <1>; <<
3149 }; <<
3150 <<
3151 sdc2: mmc@8804000 { <<
3152 compatible = "qcom,sc <<
3153 reg = <0 0x08804000 0 <<
3154 <<
3155 interrupts = <GIC_SPI <<
3156 <GIC_SPI <<
3157 interrupt-names = "hc <<
3158 <<
3159 clocks = <&gcc GCC_SD <<
3160 <&gcc GCC_SD <<
3161 <&rpmhcc RPM <<
3162 clock-names = "iface" <<
3163 resets = <&gcc GCC_SD <<
3164 interconnects = <&agg <<
3165 <&gem <<
3166 interconnect-names = <<
3167 iommus = <&apps_smmu <<
3168 power-domains = <&rpm <<
3169 operating-points-v2 = <<
3170 bus-width = <4>; <<
3171 dma-coherent; <<
3172 <<
3173 status = "disabled"; <<
3174 <<
3175 sdc2_opp_table: opp-t <<
3176 compatible = <<
3177 <<
3178 opp-100000000 <<
3179 opp-h <<
3180 requi <<
3181 opp-p <<
3182 opp-a <<
3183 }; <<
3184 <<
3185 opp-202000000 <<
3186 opp-h <<
3187 requi <<
3188 opp-p <<
3189 opp-a <<
3190 }; <<
3191 }; <<
3192 }; <<
3193 <<
3194 usb_0_qmpphy: phy@88eb000 { 2832 usb_0_qmpphy: phy@88eb000 {
3195 compatible = "qcom,sc 2833 compatible = "qcom,sc8280xp-qmp-usb43dp-phy";
3196 reg = <0 0x088eb000 0 2834 reg = <0 0x088eb000 0 0x4000>;
3197 2835
3198 clocks = <&gcc GCC_US 2836 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
3199 <&gcc GCC_US 2837 <&gcc GCC_USB4_EUD_CLKREF_CLK>,
3200 <&gcc GCC_US 2838 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
3201 <&gcc GCC_US 2839 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3202 clock-names = "aux", 2840 clock-names = "aux", "ref", "com_aux", "usb3_pipe";
3203 2841
3204 power-domains = <&gcc 2842 power-domains = <&gcc USB30_PRIM_GDSC>;
3205 2843
3206 resets = <&gcc GCC_US 2844 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
3207 <&gcc GCC_US 2845 <&gcc GCC_USB4_DP_PHY_PRIM_BCR>;
3208 reset-names = "phy", 2846 reset-names = "phy", "common";
3209 2847
3210 #clock-cells = <1>; 2848 #clock-cells = <1>;
3211 #phy-cells = <1>; 2849 #phy-cells = <1>;
3212 2850
3213 status = "disabled"; 2851 status = "disabled";
3214 <<
3215 ports { <<
3216 #address-cell <<
3217 #size-cells = <<
3218 <<
3219 port@0 { <<
3220 reg = <<
3221 <<
3222 usb_0 <<
3223 }; <<
3224 <<
3225 port@1 { <<
3226 reg = <<
3227 <<
3228 usb_0 <<
3229 <<
3230 }; <<
3231 }; <<
3232 <<
3233 port@2 { <<
3234 reg = <<
3235 <<
3236 usb_0 <<
3237 }; <<
3238 }; <<
3239 }; 2852 };
3240 2853
3241 usb_1_hsphy: phy@8902000 { 2854 usb_1_hsphy: phy@8902000 {
3242 compatible = "qcom,sc 2855 compatible = "qcom,sc8280xp-usb-hs-phy",
3243 "qcom,us 2856 "qcom,usb-snps-hs-5nm-phy";
3244 reg = <0 0x08902000 0 2857 reg = <0 0x08902000 0 0x400>;
3245 #phy-cells = <0>; 2858 #phy-cells = <0>;
3246 2859
3247 clocks = <&rpmhcc RPM 2860 clocks = <&rpmhcc RPMH_CXO_CLK>;
3248 clock-names = "ref"; 2861 clock-names = "ref";
3249 2862
3250 resets = <&gcc GCC_QU 2863 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3251 2864
3252 status = "disabled"; 2865 status = "disabled";
3253 }; 2866 };
3254 2867
3255 usb_1_qmpphy: phy@8903000 { 2868 usb_1_qmpphy: phy@8903000 {
3256 compatible = "qcom,sc 2869 compatible = "qcom,sc8280xp-qmp-usb43dp-phy";
3257 reg = <0 0x08903000 0 2870 reg = <0 0x08903000 0 0x4000>;
3258 2871
3259 clocks = <&gcc GCC_US 2872 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
3260 <&gcc GCC_US 2873 <&gcc GCC_USB4_CLKREF_CLK>,
3261 <&gcc GCC_US 2874 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
3262 <&gcc GCC_US 2875 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
3263 clock-names = "aux", 2876 clock-names = "aux", "ref", "com_aux", "usb3_pipe";
3264 2877
3265 power-domains = <&gcc 2878 power-domains = <&gcc USB30_SEC_GDSC>;
3266 2879
3267 resets = <&gcc GCC_US 2880 resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
3268 <&gcc GCC_US 2881 <&gcc GCC_USB4_1_DP_PHY_PRIM_BCR>;
3269 reset-names = "phy", 2882 reset-names = "phy", "common";
3270 2883
3271 #clock-cells = <1>; 2884 #clock-cells = <1>;
3272 #phy-cells = <1>; 2885 #phy-cells = <1>;
3273 2886
3274 status = "disabled"; 2887 status = "disabled";
3275 <<
3276 ports { <<
3277 #address-cell <<
3278 #size-cells = <<
3279 <<
3280 port@0 { <<
3281 reg = <<
3282 <<
3283 usb_1 <<
3284 }; <<
3285 <<
3286 port@1 { <<
3287 reg = <<
3288 <<
3289 usb_1 <<
3290 <<
3291 }; <<
3292 }; <<
3293 <<
3294 port@2 { <<
3295 reg = <<
3296 <<
3297 usb_1 <<
3298 }; <<
3299 }; <<
3300 }; 2888 };
3301 2889
3302 mdss1_dp0_phy: phy@8909a00 { 2890 mdss1_dp0_phy: phy@8909a00 {
3303 compatible = "qcom,sc 2891 compatible = "qcom,sc8280xp-dp-phy";
3304 reg = <0 0x08909a00 0 2892 reg = <0 0x08909a00 0 0x19c>,
3305 <0 0x08909200 0 2893 <0 0x08909200 0 0xec>,
3306 <0 0x08909600 0 2894 <0 0x08909600 0 0xec>,
3307 <0 0x08909000 0 2895 <0 0x08909000 0 0x1c8>;
3308 2896
3309 clocks = <&dispcc1 DI 2897 clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>,
3310 <&dispcc1 DI 2898 <&dispcc1 DISP_CC_MDSS_AHB_CLK>;
3311 clock-names = "aux", 2899 clock-names = "aux", "cfg_ahb";
3312 power-domains = <&rpm 2900 power-domains = <&rpmhpd SC8280XP_MX>;
3313 2901
3314 #clock-cells = <1>; 2902 #clock-cells = <1>;
3315 #phy-cells = <0>; 2903 #phy-cells = <0>;
3316 2904
3317 status = "disabled"; 2905 status = "disabled";
3318 }; 2906 };
3319 2907
3320 mdss1_dp1_phy: phy@890ca00 { 2908 mdss1_dp1_phy: phy@890ca00 {
3321 compatible = "qcom,sc 2909 compatible = "qcom,sc8280xp-dp-phy";
3322 reg = <0 0x0890ca00 0 2910 reg = <0 0x0890ca00 0 0x19c>,
3323 <0 0x0890c200 0 2911 <0 0x0890c200 0 0xec>,
3324 <0 0x0890c600 0 2912 <0 0x0890c600 0 0xec>,
3325 <0 0x0890c000 0 2913 <0 0x0890c000 0 0x1c8>;
3326 2914
3327 clocks = <&dispcc1 DI 2915 clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>,
3328 <&dispcc1 DI 2916 <&dispcc1 DISP_CC_MDSS_AHB_CLK>;
3329 clock-names = "aux", 2917 clock-names = "aux", "cfg_ahb";
3330 power-domains = <&rpm 2918 power-domains = <&rpmhpd SC8280XP_MX>;
3331 2919
3332 #clock-cells = <1>; 2920 #clock-cells = <1>;
3333 #phy-cells = <0>; 2921 #phy-cells = <0>;
3334 2922
3335 status = "disabled"; 2923 status = "disabled";
3336 }; 2924 };
3337 2925
3338 pmu@9091000 { 2926 pmu@9091000 {
3339 compatible = "qcom,sc 2927 compatible = "qcom,sc8280xp-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
3340 reg = <0 0x09091000 0 2928 reg = <0 0x09091000 0 0x1000>;
3341 2929
3342 interrupts = <GIC_SPI 2930 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
3343 2931
3344 interconnects = <&mc_ 2932 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>;
3345 2933
3346 operating-points-v2 = 2934 operating-points-v2 = <&llcc_bwmon_opp_table>;
3347 2935
3348 llcc_bwmon_opp_table: 2936 llcc_bwmon_opp_table: opp-table {
3349 compatible = 2937 compatible = "operating-points-v2";
3350 2938
3351 opp-0 { 2939 opp-0 {
3352 opp-p 2940 opp-peak-kBps = <762000>;
3353 }; 2941 };
3354 opp-1 { 2942 opp-1 {
3355 opp-p 2943 opp-peak-kBps = <1720000>;
3356 }; 2944 };
3357 opp-2 { 2945 opp-2 {
3358 opp-p 2946 opp-peak-kBps = <2086000>;
3359 }; 2947 };
3360 opp-3 { 2948 opp-3 {
3361 opp-p 2949 opp-peak-kBps = <2597000>;
3362 }; 2950 };
3363 opp-4 { 2951 opp-4 {
3364 opp-p 2952 opp-peak-kBps = <2929000>;
3365 }; 2953 };
3366 opp-5 { 2954 opp-5 {
3367 opp-p 2955 opp-peak-kBps = <3879000>;
3368 }; 2956 };
3369 opp-6 { 2957 opp-6 {
3370 opp-p 2958 opp-peak-kBps = <5161000>;
3371 }; 2959 };
3372 opp-7 { 2960 opp-7 {
3373 opp-p 2961 opp-peak-kBps = <5931000>;
3374 }; 2962 };
3375 opp-8 { 2963 opp-8 {
3376 opp-p 2964 opp-peak-kBps = <6515000>;
3377 }; 2965 };
3378 opp-9 { 2966 opp-9 {
3379 opp-p 2967 opp-peak-kBps = <7980000>;
3380 }; 2968 };
3381 opp-10 { 2969 opp-10 {
3382 opp-p 2970 opp-peak-kBps = <8136000>;
3383 }; 2971 };
3384 opp-11 { 2972 opp-11 {
3385 opp-p 2973 opp-peak-kBps = <10437000>;
3386 }; 2974 };
3387 opp-12 { 2975 opp-12 {
3388 opp-p 2976 opp-peak-kBps = <12191000>;
3389 }; 2977 };
3390 }; 2978 };
3391 }; 2979 };
3392 2980
3393 pmu@90b6400 { 2981 pmu@90b6400 {
3394 compatible = "qcom,sc 2982 compatible = "qcom,sc8280xp-cpu-bwmon", "qcom,sdm845-bwmon";
3395 reg = <0 0x090b6400 0 2983 reg = <0 0x090b6400 0 0x600>;
3396 2984
3397 interrupts = <GIC_SPI 2985 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
3398 2986
3399 interconnects = <&gem 2987 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>;
3400 operating-points-v2 = 2988 operating-points-v2 = <&cpu_bwmon_opp_table>;
3401 2989
3402 cpu_bwmon_opp_table: 2990 cpu_bwmon_opp_table: opp-table {
3403 compatible = 2991 compatible = "operating-points-v2";
3404 2992
3405 opp-0 { 2993 opp-0 {
3406 opp-p 2994 opp-peak-kBps = <2288000>;
3407 }; 2995 };
3408 opp-1 { 2996 opp-1 {
3409 opp-p 2997 opp-peak-kBps = <4577000>;
3410 }; 2998 };
3411 opp-2 { 2999 opp-2 {
3412 opp-p 3000 opp-peak-kBps = <7110000>;
3413 }; 3001 };
3414 opp-3 { 3002 opp-3 {
3415 opp-p 3003 opp-peak-kBps = <9155000>;
3416 }; 3004 };
3417 opp-4 { 3005 opp-4 {
3418 opp-p 3006 opp-peak-kBps = <12298000>;
3419 }; 3007 };
3420 opp-5 { 3008 opp-5 {
3421 opp-p 3009 opp-peak-kBps = <14236000>;
3422 }; 3010 };
3423 opp-6 { 3011 opp-6 {
3424 opp-p 3012 opp-peak-kBps = <15258001>;
3425 }; 3013 };
3426 }; 3014 };
3427 }; 3015 };
3428 3016
3429 system-cache-controller@92000 3017 system-cache-controller@9200000 {
3430 compatible = "qcom,sc 3018 compatible = "qcom,sc8280xp-llcc";
3431 reg = <0 0x09200000 0 3019 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>,
3432 <0 0x09300000 0 3020 <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>,
3433 <0 0x09400000 0 3021 <0 0x09400000 0 0x58000>, <0 0x09480000 0 0x58000>,
3434 <0 0x09500000 0 3022 <0 0x09500000 0 0x58000>, <0 0x09580000 0 0x58000>,
3435 <0 0x09600000 0 3023 <0 0x09600000 0 0x58000>;
3436 reg-names = "llcc0_ba 3024 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
3437 "llcc3_ba 3025 "llcc3_base", "llcc4_base", "llcc5_base",
3438 "llcc6_ba 3026 "llcc6_base", "llcc7_base", "llcc_broadcast_base";
3439 interrupts = <GIC_SPI 3027 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
3440 }; 3028 };
3441 3029
3442 usb_2: usb@a4f8800 { <<
3443 compatible = "qcom,sc <<
3444 reg = <0 0x0a4f8800 0 <<
3445 #address-cells = <2>; <<
3446 #size-cells = <2>; <<
3447 ranges; <<
3448 <<
3449 clocks = <&gcc GCC_CF <<
3450 <&gcc GCC_US <<
3451 <&gcc GCC_AG <<
3452 <&gcc GCC_US <<
3453 <&gcc GCC_US <<
3454 <&gcc GCC_AG <<
3455 <&gcc GCC_AG <<
3456 <&gcc GCC_AG <<
3457 <&gcc GCC_SY <<
3458 clock-names = "cfg_no <<
3459 "noc_ag <<
3460 <<
3461 assigned-clocks = <&g <<
3462 <&g <<
3463 assigned-clock-rates <<
3464 <<
3465 interrupts-extended = <<
3466 <<
3467 <<
3468 <<
3469 <<
3470 <<
3471 <<
3472 <<
3473 <<
3474 <<
3475 <<
3476 <<
3477 <<
3478 <<
3479 <<
3480 <<
3481 <<
3482 <<
3483 <<
3484 interrupt-names = "pw <<
3485 "pw <<
3486 "hs <<
3487 "hs <<
3488 "dp <<
3489 "dp <<
3490 "dp <<
3491 "dp <<
3492 "ss <<
3493 <<
3494 power-domains = <&gcc <<
3495 required-opps = <&rpm <<
3496 <<
3497 resets = <&gcc GCC_US <<
3498 <<
3499 interconnects = <&agg <<
3500 <&gem <<
3501 interconnect-names = <<
3502 <<
3503 wakeup-source; <<
3504 <<
3505 status = "disabled"; <<
3506 <<
3507 usb_2_dwc3: usb@a4000 <<
3508 compatible = <<
3509 reg = <0 0x0a <<
3510 interrupts = <<
3511 iommus = <&ap <<
3512 phys = <&usb_ <<
3513 <&usb_ <<
3514 <&usb_ <<
3515 <&usb_ <<
3516 phy-names = " <<
3517 " <<
3518 " <<
3519 " <<
3520 dr_mode = "ho <<
3521 }; <<
3522 }; <<
3523 <<
3524 usb_0: usb@a6f8800 { 3030 usb_0: usb@a6f8800 {
3525 compatible = "qcom,sc 3031 compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3";
3526 reg = <0 0x0a6f8800 0 3032 reg = <0 0x0a6f8800 0 0x400>;
3527 #address-cells = <2>; 3033 #address-cells = <2>;
3528 #size-cells = <2>; 3034 #size-cells = <2>;
3529 ranges; 3035 ranges;
3530 3036
3531 clocks = <&gcc GCC_CF 3037 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
3532 <&gcc GCC_US 3038 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
3533 <&gcc GCC_AG 3039 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
3534 <&gcc GCC_US 3040 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
3535 <&gcc GCC_US 3041 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3536 <&gcc GCC_AG 3042 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
3537 <&gcc GCC_AG 3043 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>,
3538 <&gcc GCC_AG 3044 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>,
3539 <&gcc GCC_SY 3045 <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
3540 clock-names = "cfg_no 3046 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi",
3541 "noc_ag 3047 "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys";
3542 3048
3543 assigned-clocks = <&g 3049 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3544 <&g 3050 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
3545 assigned-clock-rates 3051 assigned-clock-rates = <19200000>, <200000000>;
3546 3052
3547 interrupts-extended = 3053 interrupts-extended = <&intc GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>,
3548 <<
3549 3054 <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
3550 3055 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
3551 3056 <&pdc 138 IRQ_TYPE_LEVEL_HIGH>;
3552 interrupt-names = "pw 3057 interrupt-names = "pwr_event",
3553 "hs <<
3554 "dp 3058 "dp_hs_phy_irq",
3555 "dm 3059 "dm_hs_phy_irq",
3556 "ss 3060 "ss_phy_irq";
3557 3061
3558 power-domains = <&gcc 3062 power-domains = <&gcc USB30_PRIM_GDSC>;
3559 required-opps = <&rpm 3063 required-opps = <&rpmhpd_opp_nom>;
3560 3064
3561 resets = <&gcc GCC_US 3065 resets = <&gcc GCC_USB30_PRIM_BCR>;
3562 3066
3563 interconnects = <&agg 3067 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
3564 <&gem 3068 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
3565 interconnect-names = 3069 interconnect-names = "usb-ddr", "apps-usb";
3566 3070
3567 wakeup-source; 3071 wakeup-source;
3568 3072
3569 status = "disabled"; 3073 status = "disabled";
3570 3074
3571 usb_0_dwc3: usb@a6000 3075 usb_0_dwc3: usb@a600000 {
3572 compatible = 3076 compatible = "snps,dwc3";
3573 reg = <0 0x0a 3077 reg = <0 0x0a600000 0 0xcd00>;
3574 interrupts = 3078 interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>;
3575 iommus = <&ap 3079 iommus = <&apps_smmu 0x820 0x0>;
3576 phys = <&usb_ 3080 phys = <&usb_0_hsphy>, <&usb_0_qmpphy QMP_USB43DP_USB3_PHY>;
3577 phy-names = " 3081 phy-names = "usb2-phy", "usb3-phy";
3578 3082
3579 ports { !! 3083 port {
3580 #addr !! 3084 usb_0_role_switch: endpoint {
3581 #size <<
3582 <<
3583 port@ <<
3584 <<
3585 <<
3586 <<
3587 <<
3588 }; <<
3589 <<
3590 port@ <<
3591 <<
3592 <<
3593 <<
3594 <<
3595 <<
3596 }; 3085 };
3597 }; 3086 };
3598 }; 3087 };
3599 }; 3088 };
3600 3089
3601 usb_1: usb@a8f8800 { 3090 usb_1: usb@a8f8800 {
3602 compatible = "qcom,sc 3091 compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3";
3603 reg = <0 0x0a8f8800 0 3092 reg = <0 0x0a8f8800 0 0x400>;
3604 #address-cells = <2>; 3093 #address-cells = <2>;
3605 #size-cells = <2>; 3094 #size-cells = <2>;
3606 ranges; 3095 ranges;
3607 3096
3608 clocks = <&gcc GCC_CF 3097 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
3609 <&gcc GCC_US 3098 <&gcc GCC_USB30_SEC_MASTER_CLK>,
3610 <&gcc GCC_AG 3099 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
3611 <&gcc GCC_US 3100 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
3612 <&gcc GCC_US 3101 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3613 <&gcc GCC_AG 3102 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
3614 <&gcc GCC_AG 3103 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>,
3615 <&gcc GCC_AG 3104 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>,
3616 <&gcc GCC_SY 3105 <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
3617 clock-names = "cfg_no 3106 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi",
3618 "noc_ag 3107 "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys";
3619 3108
3620 assigned-clocks = <&g 3109 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3621 <&g 3110 <&gcc GCC_USB30_SEC_MASTER_CLK>;
3622 assigned-clock-rates 3111 assigned-clock-rates = <19200000>, <200000000>;
3623 3112
3624 interrupts-extended = 3113 interrupts-extended = <&intc GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>,
3625 <<
3626 3114 <&pdc 12 IRQ_TYPE_EDGE_BOTH>,
3627 3115 <&pdc 13 IRQ_TYPE_EDGE_BOTH>,
3628 3116 <&pdc 136 IRQ_TYPE_LEVEL_HIGH>;
3629 interrupt-names = "pw 3117 interrupt-names = "pwr_event",
3630 "hs <<
3631 "dp 3118 "dp_hs_phy_irq",
3632 "dm 3119 "dm_hs_phy_irq",
3633 "ss 3120 "ss_phy_irq";
3634 3121
3635 power-domains = <&gcc 3122 power-domains = <&gcc USB30_SEC_GDSC>;
3636 required-opps = <&rpm 3123 required-opps = <&rpmhpd_opp_nom>;
3637 3124
3638 resets = <&gcc GCC_US 3125 resets = <&gcc GCC_USB30_SEC_BCR>;
3639 3126
3640 interconnects = <&agg 3127 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>,
3641 <&gem 3128 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
3642 interconnect-names = 3129 interconnect-names = "usb-ddr", "apps-usb";
3643 3130
3644 wakeup-source; 3131 wakeup-source;
3645 3132
3646 status = "disabled"; 3133 status = "disabled";
3647 3134
3648 usb_1_dwc3: usb@a8000 3135 usb_1_dwc3: usb@a800000 {
3649 compatible = 3136 compatible = "snps,dwc3";
3650 reg = <0 0x0a 3137 reg = <0 0x0a800000 0 0xcd00>;
3651 interrupts = 3138 interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>;
3652 iommus = <&ap 3139 iommus = <&apps_smmu 0x860 0x0>;
3653 phys = <&usb_ 3140 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
3654 phy-names = " 3141 phy-names = "usb2-phy", "usb3-phy";
3655 3142
3656 ports { !! 3143 port {
3657 #addr !! 3144 usb_1_role_switch: endpoint {
3658 #size <<
3659 <<
3660 port@ <<
3661 <<
3662 <<
3663 <<
3664 <<
3665 }; <<
3666 <<
3667 port@ <<
3668 <<
3669 <<
3670 <<
3671 <<
3672 <<
3673 }; 3145 };
3674 }; 3146 };
3675 }; 3147 };
3676 }; 3148 };
3677 3149
3678 cci0: cci@ac4a000 { <<
3679 compatible = "qcom,sc <<
3680 reg = <0 0x0ac4a000 0 <<
3681 <<
3682 interrupts = <GIC_SPI <<
3683 <<
3684 clocks = <&camcc CAMC <<
3685 <&camcc CAMC <<
3686 <&camcc CAMC <<
3687 <&camcc CAMC <<
3688 clock-names = "camnoc <<
3689 "slow_a <<
3690 "cpas_a <<
3691 "cci"; <<
3692 <<
3693 power-domains = <&cam <<
3694 <<
3695 pinctrl-0 = <&cci0_de <<
3696 pinctrl-1 = <&cci0_sl <<
3697 pinctrl-names = "defa <<
3698 <<
3699 #address-cells = <1>; <<
3700 #size-cells = <0>; <<
3701 <<
3702 status = "disabled"; <<
3703 <<
3704 cci0_i2c0: i2c-bus@0 <<
3705 reg = <0>; <<
3706 clock-frequen <<
3707 #address-cell <<
3708 #size-cells = <<
3709 }; <<
3710 <<
3711 cci0_i2c1: i2c-bus@1 <<
3712 reg = <1>; <<
3713 clock-frequen <<
3714 #address-cell <<
3715 #size-cells = <<
3716 }; <<
3717 }; <<
3718 <<
3719 cci1: cci@ac4b000 { <<
3720 compatible = "qcom,sc <<
3721 reg = <0 0x0ac4b000 0 <<
3722 <<
3723 interrupts = <GIC_SPI <<
3724 <<
3725 clocks = <&camcc CAMC <<
3726 <&camcc CAMC <<
3727 <&camcc CAMC <<
3728 <&camcc CAMC <<
3729 clock-names = "camnoc <<
3730 "slow_a <<
3731 "cpas_a <<
3732 "cci"; <<
3733 <<
3734 power-domains = <&cam <<
3735 <<
3736 pinctrl-0 = <&cci1_de <<
3737 pinctrl-1 = <&cci1_sl <<
3738 pinctrl-names = "defa <<
3739 <<
3740 #address-cells = <1>; <<
3741 #size-cells = <0>; <<
3742 <<
3743 status = "disabled"; <<
3744 <<
3745 cci1_i2c0: i2c-bus@0 <<
3746 reg = <0>; <<
3747 clock-frequen <<
3748 #address-cell <<
3749 #size-cells = <<
3750 }; <<
3751 <<
3752 cci1_i2c1: i2c-bus@1 <<
3753 reg = <1>; <<
3754 clock-frequen <<
3755 #address-cell <<
3756 #size-cells = <<
3757 }; <<
3758 }; <<
3759 <<
3760 cci2: cci@ac4c000 { <<
3761 compatible = "qcom,sc <<
3762 reg = <0 0x0ac4c000 0 <<
3763 <<
3764 interrupts = <GIC_SPI <<
3765 <<
3766 clocks = <&camcc CAMC <<
3767 <&camcc CAMC <<
3768 <&camcc CAMC <<
3769 <&camcc CAMC <<
3770 clock-names = "camnoc <<
3771 "slow_a <<
3772 "cpas_a <<
3773 "cci"; <<
3774 power-domains = <&cam <<
3775 <<
3776 pinctrl-0 = <&cci2_de <<
3777 pinctrl-1 = <&cci2_sl <<
3778 pinctrl-names = "defa <<
3779 <<
3780 #address-cells = <1>; <<
3781 #size-cells = <0>; <<
3782 <<
3783 status = "disabled"; <<
3784 <<
3785 cci2_i2c0: i2c-bus@0 <<
3786 reg = <0>; <<
3787 clock-frequen <<
3788 #address-cell <<
3789 #size-cells = <<
3790 }; <<
3791 <<
3792 cci2_i2c1: i2c-bus@1 <<
3793 reg = <1>; <<
3794 clock-frequen <<
3795 #address-cell <<
3796 #size-cells = <<
3797 }; <<
3798 }; <<
3799 <<
3800 cci3: cci@ac4d000 { <<
3801 compatible = "qcom,sc <<
3802 reg = <0 0x0ac4d000 0 <<
3803 <<
3804 interrupts = <GIC_SPI <<
3805 <<
3806 clocks = <&camcc CAMC <<
3807 <&camcc CAMC <<
3808 <&camcc CAMC <<
3809 <&camcc CAMC <<
3810 clock-names = "camnoc <<
3811 "slow_a <<
3812 "cpas_a <<
3813 "cci"; <<
3814 <<
3815 power-domains = <&cam <<
3816 <<
3817 pinctrl-0 = <&cci3_de <<
3818 pinctrl-1 = <&cci3_sl <<
3819 pinctrl-names = "defa <<
3820 <<
3821 #address-cells = <1>; <<
3822 #size-cells = <0>; <<
3823 <<
3824 status = "disabled"; <<
3825 <<
3826 cci3_i2c0: i2c-bus@0 <<
3827 reg = <0>; <<
3828 clock-frequen <<
3829 #address-cell <<
3830 #size-cells = <<
3831 }; <<
3832 <<
3833 cci3_i2c1: i2c-bus@1 <<
3834 reg = <1>; <<
3835 clock-frequen <<
3836 #address-cell <<
3837 #size-cells = <<
3838 }; <<
3839 }; <<
3840 <<
3841 camss: camss@ac5a000 { <<
3842 compatible = "qcom,sc <<
3843 <<
3844 reg = <0 0x0ac5a000 0 <<
3845 <0 0x0ac5c000 0 <<
3846 <0 0x0ac65000 0 <<
3847 <0 0x0ac67000 0 <<
3848 <0 0x0acaf000 0 <<
3849 <0 0x0acb3000 0 <<
3850 <0 0x0acb6000 0 <<
3851 <0 0x0acba000 0 <<
3852 <0 0x0acbd000 0 <<
3853 <0 0x0acc1000 0 <<
3854 <0 0x0acc4000 0 <<
3855 <0 0x0acc8000 0 <<
3856 <0 0x0accb000 0 <<
3857 <0 0x0accf000 0 <<
3858 <0 0x0acd2000 0 <<
3859 <0 0x0acd6000 0 <<
3860 <0 0x0acd9000 0 <<
3861 <0 0x0acdd000 0 <<
3862 <0 0x0ace0000 0 <<
3863 <0 0x0ace4000 0 <<
3864 reg-names = "csiphy2" <<
3865 "csiphy3" <<
3866 "csiphy0" <<
3867 "csiphy1" <<
3868 "vfe0", <<
3869 "csid0", <<
3870 "vfe1", <<
3871 "csid1", <<
3872 "vfe2", <<
3873 "csid2", <<
3874 "vfe_lite <<
3875 "csid0_li <<
3876 "vfe_lite <<
3877 "csid1_li <<
3878 "vfe_lite <<
3879 "csid2_li <<
3880 "vfe_lite <<
3881 "csid3_li <<
3882 "vfe3", <<
3883 "csid3"; <<
3884 <<
3885 interrupts = <GIC_SPI <<
3886 <GIC_SPI <<
3887 <GIC_SPI <<
3888 <GIC_SPI <<
3889 <GIC_SPI <<
3890 <GIC_SPI <<
3891 <GIC_SPI <<
3892 <GIC_SPI <<
3893 <GIC_SPI <<
3894 <GIC_SPI <<
3895 <GIC_SPI <<
3896 <GIC_SPI <<
3897 <GIC_SPI <<
3898 <GIC_SPI <<
3899 <GIC_SPI <<
3900 <GIC_SPI <<
3901 <GIC_SPI <<
3902 <GIC_SPI <<
3903 <GIC_SPI <<
3904 <GIC_SPI <<
3905 interrupt-names = "cs <<
3906 "vf <<
3907 "cs <<
3908 "cs <<
3909 "vf <<
3910 "cs <<
3911 "vf <<
3912 "cs <<
3913 "vf <<
3914 "cs <<
3915 "cs <<
3916 "cs <<
3917 "cs <<
3918 "vf <<
3919 "cs <<
3920 "cs <<
3921 "vf <<
3922 "vf <<
3923 "cs <<
3924 "vf <<
3925 <<
3926 power-domains = <&cam <<
3927 <&cam <<
3928 <&cam <<
3929 <&cam <<
3930 <&cam <<
3931 power-domain-names = <<
3932 <<
3933 <<
3934 <<
3935 <<
3936 <<
3937 clocks = <&camcc CAMC <<
3938 <&camcc CAMC <<
3939 <&camcc CAMC <<
3940 <&camcc CAMC <<
3941 <&camcc CAMC <<
3942 <&camcc CAMC <<
3943 <&camcc CAMC <<
3944 <&camcc CAMC <<
3945 <&camcc CAMC <<
3946 <&camcc CAMC <<
3947 <&camcc CAMC <<
3948 <&camcc CAMC <<
3949 <&camcc CAMC <<
3950 <&camcc CAMC <<
3951 <&camcc CAMC <<
3952 <&camcc CAMC <<
3953 <&camcc CAMC <<
3954 <&camcc CAMC <<
3955 <&camcc CAMC <<
3956 <&camcc CAMC <<
3957 <&camcc CAMC <<
3958 <&camcc CAMC <<
3959 <&camcc CAMC <<
3960 <&camcc CAMC <<
3961 <&camcc CAMC <<
3962 <&camcc CAMC <<
3963 <&camcc CAMC <<
3964 <&camcc CAMC <<
3965 <&camcc CAMC <<
3966 <&camcc CAMC <<
3967 <&camcc CAMC <<
3968 <&camcc CAMC <<
3969 <&camcc CAMC <<
3970 <&camcc CAMC <<
3971 <&camcc CAMC <<
3972 <&camcc CAMC <<
3973 <&camcc CAMC <<
3974 <&camcc CAMC <<
3975 <&gcc GCC_CA <<
3976 <&gcc GCC_CA <<
3977 clock-names = "camnoc <<
3978 "cpas_a <<
3979 "csiphy <<
3980 "csiphy <<
3981 "csiphy <<
3982 "csiphy <<
3983 "csiphy <<
3984 "csiphy <<
3985 "csiphy <<
3986 "csiphy <<
3987 "vfe0_a <<
3988 "vfe0", <<
3989 "vfe0_c <<
3990 "vfe0_c <<
3991 "vfe1_a <<
3992 "vfe1", <<
3993 "vfe1_c <<
3994 "vfe1_c <<
3995 "vfe2_a <<
3996 "vfe2", <<
3997 "vfe2_c <<
3998 "vfe2_c <<
3999 "vfe3_a <<
4000 "vfe3", <<
4001 "vfe3_c <<
4002 "vfe3_c <<
4003 "vfe_li <<
4004 "vfe_li <<
4005 "vfe_li <<
4006 "vfe_li <<
4007 "vfe_li <<
4008 "vfe_li <<
4009 "vfe_li <<
4010 "vfe_li <<
4011 "vfe_li <<
4012 "vfe_li <<
4013 "vfe_li <<
4014 "vfe_li <<
4015 "gcc_ax <<
4016 "gcc_ax <<
4017 <<
4018 iommus = <&apps_smmu <<
4019 <&apps_smmu <<
4020 <&apps_smmu <<
4021 <&apps_smmu <<
4022 <&apps_smmu <<
4023 <&apps_smmu <<
4024 <&apps_smmu <<
4025 <&apps_smmu <<
4026 <&apps_smmu <<
4027 <&apps_smmu <<
4028 <&apps_smmu <<
4029 <&apps_smmu <<
4030 <&apps_smmu <<
4031 <&apps_smmu <<
4032 <&apps_smmu <<
4033 <&apps_smmu <<
4034 <<
4035 interconnects = <&gem <<
4036 <&mms <<
4037 <&mms <<
4038 <&mms <<
4039 interconnect-names = <<
4040 <<
4041 <<
4042 <<
4043 <<
4044 status = "disabled"; <<
4045 <<
4046 ports { <<
4047 #address-cell <<
4048 #size-cells = <<
4049 <<
4050 port@0 { <<
4051 reg = <<
4052 #addr <<
4053 #size <<
4054 }; <<
4055 <<
4056 port@1 { <<
4057 reg = <<
4058 #addr <<
4059 #size <<
4060 }; <<
4061 <<
4062 port@2 { <<
4063 reg = <<
4064 #addr <<
4065 #size <<
4066 }; <<
4067 <<
4068 port@3 { <<
4069 reg = <<
4070 #addr <<
4071 #size <<
4072 }; <<
4073 }; <<
4074 }; <<
4075 <<
4076 camcc: clock-controller@ad000 <<
4077 compatible = "qcom,sc <<
4078 reg = <0 0x0ad00000 0 <<
4079 clocks = <&gcc GCC_CA <<
4080 <&rpmhcc RPM <<
4081 <&rpmhcc RPM <<
4082 <&sleep_clk> <<
4083 power-domains = <&rpm <<
4084 required-opps = <&rpm <<
4085 #clock-cells = <1>; <<
4086 #reset-cells = <1>; <<
4087 #power-domain-cells = <<
4088 }; <<
4089 <<
4090 mdss0: display-subsystem@ae00 3150 mdss0: display-subsystem@ae00000 {
4091 compatible = "qcom,sc 3151 compatible = "qcom,sc8280xp-mdss";
4092 reg = <0 0x0ae00000 0 3152 reg = <0 0x0ae00000 0 0x1000>;
4093 reg-names = "mdss"; 3153 reg-names = "mdss";
4094 3154
4095 clocks = <&gcc GCC_DI 3155 clocks = <&gcc GCC_DISP_AHB_CLK>,
4096 <&dispcc0 DI 3156 <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
4097 <&dispcc0 DI 3157 <&dispcc0 DISP_CC_MDSS_MDP_CLK>;
4098 clock-names = "iface" 3158 clock-names = "iface",
4099 "ahb", 3159 "ahb",
4100 "core"; 3160 "core";
4101 interrupts = <GIC_SPI 3161 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
4102 interconnects = <&mms 3162 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
4103 <&mms 3163 <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>;
4104 interconnect-names = 3164 interconnect-names = "mdp0-mem", "mdp1-mem";
4105 iommus = <&apps_smmu 3165 iommus = <&apps_smmu 0x1000 0x402>;
4106 power-domains = <&dis 3166 power-domains = <&dispcc0 MDSS_GDSC>;
4107 resets = <&dispcc0 DI 3167 resets = <&dispcc0 DISP_CC_MDSS_CORE_BCR>;
4108 3168
4109 interrupt-controller; 3169 interrupt-controller;
4110 #interrupt-cells = <1 3170 #interrupt-cells = <1>;
4111 #address-cells = <2>; 3171 #address-cells = <2>;
4112 #size-cells = <2>; 3172 #size-cells = <2>;
4113 ranges; 3173 ranges;
4114 3174
4115 status = "disabled"; 3175 status = "disabled";
4116 3176
4117 mdss0_mdp: display-co 3177 mdss0_mdp: display-controller@ae01000 {
4118 compatible = 3178 compatible = "qcom,sc8280xp-dpu";
4119 reg = <0 0x0a 3179 reg = <0 0x0ae01000 0 0x8f000>,
4120 <0 0x0a 3180 <0 0x0aeb0000 0 0x2008>;
4121 reg-names = " 3181 reg-names = "mdp", "vbif";
4122 3182
4123 clocks = <&gc 3183 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
4124 <&gc 3184 <&gcc GCC_DISP_SF_AXI_CLK>,
4125 <&di 3185 <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
4126 <&di 3186 <&dispcc0 DISP_CC_MDSS_MDP_LUT_CLK>,
4127 <&di 3187 <&dispcc0 DISP_CC_MDSS_MDP_CLK>,
4128 <&di 3188 <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;
4129 clock-names = 3189 clock-names = "bus",
4130 3190 "nrt_bus",
4131 3191 "iface",
4132 3192 "lut",
4133 3193 "core",
4134 3194 "vsync";
4135 interrupt-par 3195 interrupt-parent = <&mdss0>;
4136 interrupts = 3196 interrupts = <0>;
4137 power-domains 3197 power-domains = <&rpmhpd SC8280XP_MMCX>;
4138 3198
4139 assigned-cloc 3199 assigned-clocks = <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;
4140 assigned-cloc 3200 assigned-clock-rates = <19200000>;
4141 operating-poi 3201 operating-points-v2 = <&mdss0_mdp_opp_table>;
4142 3202
4143 ports { 3203 ports {
4144 #addr 3204 #address-cells = <1>;
4145 #size 3205 #size-cells = <0>;
4146 3206
4147 port@ 3207 port@0 {
4148 3208 reg = <0>;
4149 3209 mdss0_intf0_out: endpoint {
4150 3210 remote-endpoint = <&mdss0_dp0_in>;
4151 3211 };
4152 }; 3212 };
4153 3213
4154 port@ 3214 port@4 {
4155 3215 reg = <4>;
4156 3216 mdss0_intf4_out: endpoint {
4157 3217 remote-endpoint = <&mdss0_dp1_in>;
4158 3218 };
4159 }; 3219 };
4160 3220
4161 port@ 3221 port@5 {
4162 3222 reg = <5>;
4163 3223 mdss0_intf5_out: endpoint {
4164 3224 remote-endpoint = <&mdss0_dp3_in>;
4165 3225 };
4166 }; 3226 };
4167 3227
4168 port@ 3228 port@6 {
4169 3229 reg = <6>;
4170 3230 mdss0_intf6_out: endpoint {
4171 3231 remote-endpoint = <&mdss0_dp2_in>;
4172 3232 };
4173 }; 3233 };
4174 }; 3234 };
4175 3235
4176 mdss0_mdp_opp 3236 mdss0_mdp_opp_table: opp-table {
4177 compa 3237 compatible = "operating-points-v2";
4178 3238
4179 opp-2 3239 opp-200000000 {
4180 3240 opp-hz = /bits/ 64 <200000000>;
4181 3241 required-opps = <&rpmhpd_opp_low_svs>;
4182 }; 3242 };
4183 3243
4184 opp-3 3244 opp-300000000 {
4185 3245 opp-hz = /bits/ 64 <300000000>;
4186 3246 required-opps = <&rpmhpd_opp_svs>;
4187 }; 3247 };
4188 3248
4189 opp-3 3249 opp-375000000 {
4190 3250 opp-hz = /bits/ 64 <375000000>;
4191 3251 required-opps = <&rpmhpd_opp_svs_l1>;
4192 }; 3252 };
4193 3253
4194 opp-5 3254 opp-500000000 {
4195 3255 opp-hz = /bits/ 64 <500000000>;
4196 3256 required-opps = <&rpmhpd_opp_nom>;
4197 }; 3257 };
4198 opp-6 3258 opp-600000000 {
4199 3259 opp-hz = /bits/ 64 <600000000>;
4200 3260 required-opps = <&rpmhpd_opp_turbo_l1>;
4201 }; 3261 };
4202 }; 3262 };
4203 }; 3263 };
4204 3264
4205 mdss0_dp0: displaypor 3265 mdss0_dp0: displayport-controller@ae90000 {
4206 compatible = 3266 compatible = "qcom,sc8280xp-dp";
4207 reg = <0 0xae 3267 reg = <0 0xae90000 0 0x200>,
4208 <0 0xae 3268 <0 0xae90200 0 0x200>,
4209 <0 0xae 3269 <0 0xae90400 0 0x600>,
4210 <0 0xae 3270 <0 0xae91000 0 0x400>,
4211 <0 0xae 3271 <0 0xae91400 0 0x400>;
4212 interrupt-par 3272 interrupt-parent = <&mdss0>;
4213 interrupts = 3273 interrupts = <12>;
4214 clocks = <&di 3274 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
4215 <&di 3275 <&dispcc0 DISP_CC_MDSS_DPTX0_AUX_CLK>,
4216 <&di 3276 <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK>,
4217 <&di 3277 <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
4218 <&di 3278 <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
4219 clock-names = 3279 clock-names = "core_iface", "core_aux",
4220 3280 "ctrl_link",
4221 3281 "ctrl_link_iface",
4222 3282 "stream_pixel";
4223 3283
4224 assigned-cloc 3284 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
4225 3285 <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
4226 assigned-cloc 3286 assigned-clock-parents = <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4227 3287 <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
4228 3288
4229 phys = <&usb_ 3289 phys = <&usb_0_qmpphy QMP_USB43DP_DP_PHY>;
4230 phy-names = " 3290 phy-names = "dp";
4231 3291
4232 #sound-dai-ce 3292 #sound-dai-cells = <0>;
4233 3293
4234 operating-poi 3294 operating-points-v2 = <&mdss0_dp0_opp_table>;
4235 power-domains 3295 power-domains = <&rpmhpd SC8280XP_MMCX>;
4236 3296
4237 status = "dis 3297 status = "disabled";
4238 3298
4239 ports { 3299 ports {
4240 #addr 3300 #address-cells = <1>;
4241 #size 3301 #size-cells = <0>;
4242 3302
4243 port@ 3303 port@0 {
4244 3304 reg = <0>;
4245 3305
4246 3306 mdss0_dp0_in: endpoint {
4247 3307 remote-endpoint = <&mdss0_intf0_out>;
4248 3308 };
4249 }; 3309 };
4250 3310
4251 port@ 3311 port@1 {
4252 3312 reg = <1>;
4253 3313
4254 3314 mdss0_dp0_out: endpoint {
4255 3315 };
4256 }; 3316 };
4257 }; 3317 };
4258 3318
4259 mdss0_dp0_opp 3319 mdss0_dp0_opp_table: opp-table {
4260 compa 3320 compatible = "operating-points-v2";
4261 3321
4262 opp-1 3322 opp-160000000 {
4263 3323 opp-hz = /bits/ 64 <160000000>;
4264 3324 required-opps = <&rpmhpd_opp_low_svs>;
4265 }; 3325 };
4266 3326
4267 opp-2 3327 opp-270000000 {
4268 3328 opp-hz = /bits/ 64 <270000000>;
4269 3329 required-opps = <&rpmhpd_opp_svs>;
4270 }; 3330 };
4271 3331
4272 opp-5 3332 opp-540000000 {
4273 3333 opp-hz = /bits/ 64 <540000000>;
4274 3334 required-opps = <&rpmhpd_opp_svs_l1>;
4275 }; 3335 };
4276 3336
4277 opp-8 3337 opp-810000000 {
4278 3338 opp-hz = /bits/ 64 <810000000>;
4279 3339 required-opps = <&rpmhpd_opp_nom>;
4280 }; 3340 };
4281 }; 3341 };
4282 }; 3342 };
4283 3343
4284 mdss0_dp1: displaypor 3344 mdss0_dp1: displayport-controller@ae98000 {
4285 compatible = 3345 compatible = "qcom,sc8280xp-dp";
4286 reg = <0 0xae 3346 reg = <0 0xae98000 0 0x200>,
4287 <0 0xae 3347 <0 0xae98200 0 0x200>,
4288 <0 0xae 3348 <0 0xae98400 0 0x600>,
4289 <0 0xae 3349 <0 0xae99000 0 0x400>,
4290 <0 0xae 3350 <0 0xae99400 0 0x400>;
4291 interrupt-par 3351 interrupt-parent = <&mdss0>;
4292 interrupts = 3352 interrupts = <13>;
4293 clocks = <&di 3353 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
4294 <&di 3354 <&dispcc0 DISP_CC_MDSS_DPTX1_AUX_CLK>,
4295 <&di 3355 <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK>,
4296 <&di 3356 <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
4297 <&di 3357 <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>;
4298 clock-names = 3358 clock-names = "core_iface", "core_aux",
4299 3359 "ctrl_link",
4300 3360 "ctrl_link_iface", "stream_pixel";
4301 3361
4302 assigned-cloc 3362 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
4303 3363 <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>;
4304 assigned-cloc 3364 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4305 3365 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
4306 3366
4307 phys = <&usb_ 3367 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
4308 phy-names = " 3368 phy-names = "dp";
4309 3369
4310 #sound-dai-ce 3370 #sound-dai-cells = <0>;
4311 3371
4312 operating-poi 3372 operating-points-v2 = <&mdss0_dp1_opp_table>;
4313 power-domains 3373 power-domains = <&rpmhpd SC8280XP_MMCX>;
4314 3374
4315 status = "dis 3375 status = "disabled";
4316 3376
4317 ports { 3377 ports {
4318 #addr 3378 #address-cells = <1>;
4319 #size 3379 #size-cells = <0>;
4320 3380
4321 port@ 3381 port@0 {
4322 3382 reg = <0>;
4323 3383
4324 3384 mdss0_dp1_in: endpoint {
4325 3385 remote-endpoint = <&mdss0_intf4_out>;
4326 3386 };
4327 }; 3387 };
4328 3388
4329 port@ 3389 port@1 {
4330 3390 reg = <1>;
4331 3391
4332 3392 mdss0_dp1_out: endpoint {
4333 3393 };
4334 }; 3394 };
4335 }; 3395 };
4336 3396
4337 mdss0_dp1_opp 3397 mdss0_dp1_opp_table: opp-table {
4338 compa 3398 compatible = "operating-points-v2";
4339 3399
4340 opp-1 3400 opp-160000000 {
4341 3401 opp-hz = /bits/ 64 <160000000>;
4342 3402 required-opps = <&rpmhpd_opp_low_svs>;
4343 }; 3403 };
4344 3404
4345 opp-2 3405 opp-270000000 {
4346 3406 opp-hz = /bits/ 64 <270000000>;
4347 3407 required-opps = <&rpmhpd_opp_svs>;
4348 }; 3408 };
4349 3409
4350 opp-5 3410 opp-540000000 {
4351 3411 opp-hz = /bits/ 64 <540000000>;
4352 3412 required-opps = <&rpmhpd_opp_svs_l1>;
4353 }; 3413 };
4354 3414
4355 opp-8 3415 opp-810000000 {
4356 3416 opp-hz = /bits/ 64 <810000000>;
4357 3417 required-opps = <&rpmhpd_opp_nom>;
4358 }; 3418 };
4359 }; 3419 };
4360 }; 3420 };
4361 3421
4362 mdss0_dp2: displaypor 3422 mdss0_dp2: displayport-controller@ae9a000 {
4363 compatible = 3423 compatible = "qcom,sc8280xp-dp";
4364 reg = <0 0xae 3424 reg = <0 0xae9a000 0 0x200>,
4365 <0 0xae 3425 <0 0xae9a200 0 0x200>,
4366 <0 0xae 3426 <0 0xae9a400 0 0x600>,
4367 <0 0xae 3427 <0 0xae9b000 0 0x400>,
4368 <0 0xae 3428 <0 0xae9b400 0 0x400>;
4369 3429
4370 clocks = <&di 3430 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
4371 <&di 3431 <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>,
4372 <&di 3432 <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK>,
4373 <&di 3433 <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>,
4374 <&di 3434 <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>;
4375 clock-names = 3435 clock-names = "core_iface", "core_aux",
4376 3436 "ctrl_link",
4377 3437 "ctrl_link_iface", "stream_pixel";
4378 interrupt-par 3438 interrupt-parent = <&mdss0>;
4379 interrupts = 3439 interrupts = <14>;
4380 phys = <&mdss 3440 phys = <&mdss0_dp2_phy>;
4381 phy-names = " 3441 phy-names = "dp";
4382 power-domains 3442 power-domains = <&rpmhpd SC8280XP_MMCX>;
4383 3443
4384 assigned-cloc 3444 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
4385 3445 <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>;
4386 assigned-cloc 3446 assigned-clock-parents = <&mdss0_dp2_phy 0>, <&mdss0_dp2_phy 1>;
4387 operating-poi 3447 operating-points-v2 = <&mdss0_dp2_opp_table>;
4388 3448
4389 #sound-dai-ce 3449 #sound-dai-cells = <0>;
4390 3450
4391 status = "dis 3451 status = "disabled";
4392 3452
4393 ports { 3453 ports {
4394 #addr 3454 #address-cells = <1>;
4395 #size 3455 #size-cells = <0>;
4396 3456
4397 port@ 3457 port@0 {
4398 3458 reg = <0>;
4399 3459 mdss0_dp2_in: endpoint {
4400 3460 remote-endpoint = <&mdss0_intf6_out>;
4401 3461 };
4402 }; 3462 };
4403 3463
4404 port@ 3464 port@1 {
4405 3465 reg = <1>;
4406 }; 3466 };
4407 }; 3467 };
4408 3468
4409 mdss0_dp2_opp 3469 mdss0_dp2_opp_table: opp-table {
4410 compa 3470 compatible = "operating-points-v2";
4411 3471
4412 opp-1 3472 opp-160000000 {
4413 3473 opp-hz = /bits/ 64 <160000000>;
4414 3474 required-opps = <&rpmhpd_opp_low_svs>;
4415 }; 3475 };
4416 3476
4417 opp-2 3477 opp-270000000 {
4418 3478 opp-hz = /bits/ 64 <270000000>;
4419 3479 required-opps = <&rpmhpd_opp_svs>;
4420 }; 3480 };
4421 3481
4422 opp-5 3482 opp-540000000 {
4423 3483 opp-hz = /bits/ 64 <540000000>;
4424 3484 required-opps = <&rpmhpd_opp_svs_l1>;
4425 }; 3485 };
4426 3486
4427 opp-8 3487 opp-810000000 {
4428 3488 opp-hz = /bits/ 64 <810000000>;
4429 3489 required-opps = <&rpmhpd_opp_nom>;
4430 }; 3490 };
4431 }; 3491 };
4432 }; 3492 };
4433 3493
4434 mdss0_dp3: displaypor 3494 mdss0_dp3: displayport-controller@aea0000 {
4435 compatible = 3495 compatible = "qcom,sc8280xp-dp";
4436 reg = <0 0xae 3496 reg = <0 0xaea0000 0 0x200>,
4437 <0 0xae 3497 <0 0xaea0200 0 0x200>,
4438 <0 0xae 3498 <0 0xaea0400 0 0x600>,
4439 <0 0xae 3499 <0 0xaea1000 0 0x400>,
4440 <0 0xae 3500 <0 0xaea1400 0 0x400>;
4441 3501
4442 clocks = <&di 3502 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
4443 <&di 3503 <&dispcc0 DISP_CC_MDSS_DPTX3_AUX_CLK>,
4444 <&di 3504 <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_CLK>,
4445 <&di 3505 <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>,
4446 <&di 3506 <&dispcc0 DISP_CC_MDSS_DPTX3_PIXEL0_CLK>;
4447 clock-names = 3507 clock-names = "core_iface", "core_aux",
4448 3508 "ctrl_link",
4449 3509 "ctrl_link_iface", "stream_pixel";
4450 interrupt-par 3510 interrupt-parent = <&mdss0>;
4451 interrupts = 3511 interrupts = <15>;
4452 phys = <&mdss 3512 phys = <&mdss0_dp3_phy>;
4453 phy-names = " 3513 phy-names = "dp";
4454 power-domains 3514 power-domains = <&rpmhpd SC8280XP_MMCX>;
4455 3515
4456 assigned-cloc 3516 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>,
4457 3517 <&dispcc0 DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>;
4458 assigned-cloc 3518 assigned-clock-parents = <&mdss0_dp3_phy 0>, <&mdss0_dp3_phy 1>;
4459 operating-poi 3519 operating-points-v2 = <&mdss0_dp3_opp_table>;
4460 3520
4461 #sound-dai-ce 3521 #sound-dai-cells = <0>;
4462 3522
4463 status = "dis 3523 status = "disabled";
4464 3524
4465 ports { 3525 ports {
4466 #addr 3526 #address-cells = <1>;
4467 #size 3527 #size-cells = <0>;
4468 3528
4469 port@ 3529 port@0 {
4470 3530 reg = <0>;
4471 3531 mdss0_dp3_in: endpoint {
4472 3532 remote-endpoint = <&mdss0_intf5_out>;
4473 3533 };
4474 }; 3534 };
4475 3535
4476 port@ 3536 port@1 {
4477 3537 reg = <1>;
4478 }; 3538 };
4479 }; 3539 };
4480 3540
4481 mdss0_dp3_opp 3541 mdss0_dp3_opp_table: opp-table {
4482 compa 3542 compatible = "operating-points-v2";
4483 3543
4484 opp-1 3544 opp-160000000 {
4485 3545 opp-hz = /bits/ 64 <160000000>;
4486 3546 required-opps = <&rpmhpd_opp_low_svs>;
4487 }; 3547 };
4488 3548
4489 opp-2 3549 opp-270000000 {
4490 3550 opp-hz = /bits/ 64 <270000000>;
4491 3551 required-opps = <&rpmhpd_opp_svs>;
4492 }; 3552 };
4493 3553
4494 opp-5 3554 opp-540000000 {
4495 3555 opp-hz = /bits/ 64 <540000000>;
4496 3556 required-opps = <&rpmhpd_opp_svs_l1>;
4497 }; 3557 };
4498 3558
4499 opp-8 3559 opp-810000000 {
4500 3560 opp-hz = /bits/ 64 <810000000>;
4501 3561 required-opps = <&rpmhpd_opp_nom>;
4502 }; 3562 };
4503 }; 3563 };
4504 }; 3564 };
4505 }; 3565 };
4506 3566
4507 mdss0_dp2_phy: phy@aec2a00 { 3567 mdss0_dp2_phy: phy@aec2a00 {
4508 compatible = "qcom,sc 3568 compatible = "qcom,sc8280xp-dp-phy";
4509 reg = <0 0x0aec2a00 0 3569 reg = <0 0x0aec2a00 0 0x19c>,
4510 <0 0x0aec2200 0 3570 <0 0x0aec2200 0 0xec>,
4511 <0 0x0aec2600 0 3571 <0 0x0aec2600 0 0xec>,
4512 <0 0x0aec2000 0 3572 <0 0x0aec2000 0 0x1c8>;
4513 3573
4514 clocks = <&dispcc0 DI 3574 clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>,
4515 <&dispcc0 DI 3575 <&dispcc0 DISP_CC_MDSS_AHB_CLK>;
4516 clock-names = "aux", 3576 clock-names = "aux", "cfg_ahb";
4517 power-domains = <&rpm 3577 power-domains = <&rpmhpd SC8280XP_MX>;
4518 3578
4519 #clock-cells = <1>; 3579 #clock-cells = <1>;
4520 #phy-cells = <0>; 3580 #phy-cells = <0>;
4521 3581
4522 status = "disabled"; 3582 status = "disabled";
4523 }; 3583 };
4524 3584
4525 mdss0_dp3_phy: phy@aec5a00 { 3585 mdss0_dp3_phy: phy@aec5a00 {
4526 compatible = "qcom,sc 3586 compatible = "qcom,sc8280xp-dp-phy";
4527 reg = <0 0x0aec5a00 0 3587 reg = <0 0x0aec5a00 0 0x19c>,
4528 <0 0x0aec5200 0 3588 <0 0x0aec5200 0 0xec>,
4529 <0 0x0aec5600 0 3589 <0 0x0aec5600 0 0xec>,
4530 <0 0x0aec5000 0 3590 <0 0x0aec5000 0 0x1c8>;
4531 3591
4532 clocks = <&dispcc0 DI 3592 clocks = <&dispcc0 DISP_CC_MDSS_DPTX3_AUX_CLK>,
4533 <&dispcc0 DI 3593 <&dispcc0 DISP_CC_MDSS_AHB_CLK>;
4534 clock-names = "aux", 3594 clock-names = "aux", "cfg_ahb";
4535 power-domains = <&rpm 3595 power-domains = <&rpmhpd SC8280XP_MX>;
4536 3596
4537 #clock-cells = <1>; 3597 #clock-cells = <1>;
4538 #phy-cells = <0>; 3598 #phy-cells = <0>;
4539 3599
4540 status = "disabled"; 3600 status = "disabled";
4541 }; 3601 };
4542 3602
4543 dispcc0: clock-controller@af0 3603 dispcc0: clock-controller@af00000 {
4544 compatible = "qcom,sc 3604 compatible = "qcom,sc8280xp-dispcc0";
4545 reg = <0 0x0af00000 0 3605 reg = <0 0x0af00000 0 0x20000>;
4546 3606
4547 clocks = <&gcc GCC_DI 3607 clocks = <&gcc GCC_DISP_AHB_CLK>,
4548 <&rpmhcc RPM 3608 <&rpmhcc RPMH_CXO_CLK>,
4549 <&sleep_clk> 3609 <&sleep_clk>,
4550 <&usb_0_qmpp 3610 <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4551 <&usb_0_qmpp 3611 <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
4552 <&usb_1_qmpp 3612 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4553 <&usb_1_qmpp 3613 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
4554 <&mdss0_dp2_ 3614 <&mdss0_dp2_phy 0>,
4555 <&mdss0_dp2_ 3615 <&mdss0_dp2_phy 1>,
4556 <&mdss0_dp3_ 3616 <&mdss0_dp3_phy 0>,
4557 <&mdss0_dp3_ 3617 <&mdss0_dp3_phy 1>,
4558 <0>, 3618 <0>,
4559 <0>, 3619 <0>,
4560 <0>, 3620 <0>,
4561 <0>; 3621 <0>;
4562 power-domains = <&rpm 3622 power-domains = <&rpmhpd SC8280XP_MMCX>;
4563 3623
4564 #clock-cells = <1>; 3624 #clock-cells = <1>;
4565 #power-domain-cells = 3625 #power-domain-cells = <1>;
4566 #reset-cells = <1>; 3626 #reset-cells = <1>;
4567 3627
4568 status = "disabled"; 3628 status = "disabled";
4569 }; 3629 };
4570 3630
4571 pdc: interrupt-controller@b22 3631 pdc: interrupt-controller@b220000 {
4572 compatible = "qcom,sc 3632 compatible = "qcom,sc8280xp-pdc", "qcom,pdc";
4573 reg = <0 0x0b220000 0 3633 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
4574 qcom,pdc-ranges = <0 3634 qcom,pdc-ranges = <0 480 40>,
4575 <40 3635 <40 140 14>,
4576 <54 3636 <54 263 1>,
4577 <55 3637 <55 306 4>,
4578 <59 3638 <59 312 3>,
4579 <62 3639 <62 374 2>,
4580 <64 3640 <64 434 2>,
4581 <66 3641 <66 438 3>,
4582 <69 3642 <69 86 1>,
4583 <70 3643 <70 520 54>,
4584 <12 3644 <124 609 28>,
4585 <15 3645 <159 638 1>,
4586 <16 3646 <160 720 8>,
4587 <16 3647 <168 801 1>,
4588 <16 3648 <169 728 30>,
4589 <19 3649 <199 416 2>,
4590 <20 3650 <201 449 1>,
4591 <20 3651 <202 89 1>,
4592 <20 3652 <203 451 1>,
4593 <20 3653 <204 462 1>,
4594 <20 3654 <205 264 1>,
4595 <20 3655 <206 579 1>,
4596 <20 3656 <207 653 1>,
4597 <20 3657 <208 656 1>,
4598 <20 3658 <209 659 1>,
4599 <21 3659 <210 122 1>,
4600 <21 3660 <211 699 1>,
4601 <21 3661 <212 705 1>,
4602 <21 3662 <213 450 1>,
4603 <21 3663 <214 643 1>,
4604 <21 3664 <216 646 5>,
4605 <22 3665 <221 390 5>,
4606 <22 3666 <226 700 3>,
4607 <22 3667 <229 240 3>,
4608 <23 3668 <232 269 1>,
4609 <23 3669 <233 377 1>,
4610 <23 3670 <234 372 1>,
4611 <23 3671 <235 138 1>,
4612 <23 3672 <236 857 1>,
4613 <23 3673 <237 860 1>,
4614 <23 3674 <238 137 1>,
4615 <23 3675 <239 668 1>,
4616 <24 3676 <240 366 1>,
4617 <24 3677 <241 949 1>,
4618 <24 3678 <242 815 5>,
4619 <24 3679 <247 769 1>,
4620 <24 3680 <248 768 1>,
4621 <24 3681 <249 663 1>,
4622 <25 3682 <250 799 2>,
4623 <25 3683 <252 798 1>,
4624 <25 3684 <253 765 1>,
4625 <25 3685 <254 763 1>,
4626 <25 3686 <255 454 1>,
4627 <25 3687 <258 139 1>,
4628 <25 3688 <259 786 2>,
4629 <26 3689 <261 370 2>,
4630 <26 3690 <263 158 2>;
4631 #interrupt-cells = <2 3691 #interrupt-cells = <2>;
4632 interrupt-parent = <& 3692 interrupt-parent = <&intc>;
4633 interrupt-controller; 3693 interrupt-controller;
4634 }; 3694 };
4635 3695
4636 tsens2: thermal-sensor@c25100 <<
4637 compatible = "qcom,sc <<
4638 reg = <0 0x0c251000 0 <<
4639 <0 0x0c224000 0 <<
4640 #qcom,sensors = <11>; <<
4641 interrupts-extended = <<
4642 <<
4643 interrupt-names = "up <<
4644 #thermal-sensor-cells <<
4645 }; <<
4646 <<
4647 tsens3: thermal-sensor@c25200 <<
4648 compatible = "qcom,sc <<
4649 reg = <0 0x0c252000 0 <<
4650 <0 0x0c225000 0 <<
4651 #qcom,sensors = <5>; <<
4652 interrupts-extended = <<
4653 <<
4654 interrupt-names = "up <<
4655 #thermal-sensor-cells <<
4656 }; <<
4657 <<
4658 tsens0: thermal-sensor@c26300 3696 tsens0: thermal-sensor@c263000 {
4659 compatible = "qcom,sc 3697 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2";
4660 reg = <0 0x0c263000 0 3698 reg = <0 0x0c263000 0 0x1ff>, /* TM */
4661 <0 0x0c222000 0 3699 <0 0x0c222000 0 0x8>; /* SROT */
4662 #qcom,sensors = <14>; 3700 #qcom,sensors = <14>;
4663 interrupts-extended = 3701 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
4664 3702 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>;
4665 interrupt-names = "up 3703 interrupt-names = "uplow", "critical";
4666 #thermal-sensor-cells 3704 #thermal-sensor-cells = <1>;
4667 }; 3705 };
4668 3706
4669 restart@c264000 { <<
4670 compatible = "qcom,ps <<
4671 reg = <0 0x0c264000 0 <<
4672 /* TZ seems to block <<
4673 status = "reserved"; <<
4674 }; <<
4675 <<
4676 tsens1: thermal-sensor@c26500 3707 tsens1: thermal-sensor@c265000 {
4677 compatible = "qcom,sc 3708 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2";
4678 reg = <0 0x0c265000 0 3709 reg = <0 0x0c265000 0 0x1ff>, /* TM */
4679 <0 0x0c223000 0 3710 <0 0x0c223000 0 0x8>; /* SROT */
4680 #qcom,sensors = <16>; 3711 #qcom,sensors = <16>;
4681 interrupts-extended = 3712 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
4682 3713 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>;
4683 interrupt-names = "up 3714 interrupt-names = "uplow", "critical";
4684 #thermal-sensor-cells 3715 #thermal-sensor-cells = <1>;
4685 }; 3716 };
4686 3717
4687 aoss_qmp: power-management@c3 3718 aoss_qmp: power-management@c300000 {
4688 compatible = "qcom,sc 3719 compatible = "qcom,sc8280xp-aoss-qmp", "qcom,aoss-qmp";
4689 reg = <0 0x0c300000 0 3720 reg = <0 0x0c300000 0 0x400>;
4690 interrupts-extended = 3721 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>;
4691 mboxes = <&ipcc IPCC_ 3722 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
4692 3723
4693 #clock-cells = <0>; 3724 #clock-cells = <0>;
4694 }; 3725 };
4695 3726
4696 sram@c3f0000 { 3727 sram@c3f0000 {
4697 compatible = "qcom,rp 3728 compatible = "qcom,rpmh-stats";
4698 reg = <0 0x0c3f0000 0 3729 reg = <0 0x0c3f0000 0 0x400>;
4699 qcom,qmp = <&aoss_qmp <<
4700 }; 3730 };
4701 3731
4702 spmi_bus: spmi@c440000 { 3732 spmi_bus: spmi@c440000 {
4703 compatible = "qcom,sp 3733 compatible = "qcom,spmi-pmic-arb";
4704 reg = <0 0x0c440000 0 3734 reg = <0 0x0c440000 0 0x1100>,
4705 <0 0x0c600000 0 3735 <0 0x0c600000 0 0x2000000>,
4706 <0 0x0e600000 0 3736 <0 0x0e600000 0 0x100000>,
4707 <0 0x0e700000 0 3737 <0 0x0e700000 0 0xa0000>,
4708 <0 0x0c40a000 0 3738 <0 0x0c40a000 0 0x26000>;
4709 reg-names = "core", " 3739 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
4710 interrupt-names = "pe 3740 interrupt-names = "periph_irq";
4711 interrupts-extended = 3741 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
4712 qcom,ee = <0>; 3742 qcom,ee = <0>;
4713 qcom,channel = <0>; 3743 qcom,channel = <0>;
4714 #address-cells = <2>; 3744 #address-cells = <2>;
4715 #size-cells = <0>; 3745 #size-cells = <0>;
4716 interrupt-controller; 3746 interrupt-controller;
4717 #interrupt-cells = <4 3747 #interrupt-cells = <4>;
4718 }; 3748 };
4719 3749
4720 tlmm: pinctrl@f100000 { 3750 tlmm: pinctrl@f100000 {
4721 compatible = "qcom,sc 3751 compatible = "qcom,sc8280xp-tlmm";
4722 reg = <0 0x0f100000 0 3752 reg = <0 0x0f100000 0 0x300000>;
4723 interrupts = <GIC_SPI 3753 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
4724 gpio-controller; 3754 gpio-controller;
4725 #gpio-cells = <2>; 3755 #gpio-cells = <2>;
4726 interrupt-controller; 3756 interrupt-controller;
4727 #interrupt-cells = <2 3757 #interrupt-cells = <2>;
4728 gpio-ranges = <&tlmm 3758 gpio-ranges = <&tlmm 0 0 230>;
4729 wakeup-parent = <&pdc <<
4730 <<
4731 cci0_default: cci0-de <<
4732 cci0_i2c0_def <<
4733 /* cc <<
4734 pins <<
4735 funct <<
4736 drive <<
4737 bias- <<
4738 }; <<
4739 <<
4740 cci0_i2c1_def <<
4741 /* cc <<
4742 pins <<
4743 funct <<
4744 drive <<
4745 bias- <<
4746 }; <<
4747 }; <<
4748 <<
4749 cci0_sleep: cci0-slee <<
4750 cci0_i2c0_sle <<
4751 /* cc <<
4752 pins <<
4753 funct <<
4754 drive <<
4755 bias- <<
4756 }; <<
4757 <<
4758 cci0_i2c1_sle <<
4759 /* cc <<
4760 pins <<
4761 funct <<
4762 drive <<
4763 bias- <<
4764 }; <<
4765 }; <<
4766 <<
4767 cci1_default: cci1-de <<
4768 cci1_i2c0_def <<
4769 /* cc <<
4770 pins <<
4771 funct <<
4772 drive <<
4773 bias- <<
4774 }; <<
4775 <<
4776 cci1_i2c1_def <<
4777 /* cc <<
4778 pins <<
4779 funct <<
4780 drive <<
4781 bias- <<
4782 }; <<
4783 }; <<
4784 <<
4785 cci1_sleep: cci1-slee <<
4786 cci1_i2c0_sle <<
4787 /* cc <<
4788 pins <<
4789 funct <<
4790 drive <<
4791 bias- <<
4792 }; <<
4793 <<
4794 cci1_i2c1_sle <<
4795 /* cc <<
4796 pins <<
4797 funct <<
4798 drive <<
4799 bias- <<
4800 }; <<
4801 }; <<
4802 <<
4803 cci2_default: cci2-de <<
4804 cci2_i2c0_def <<
4805 /* cc <<
4806 pins <<
4807 funct <<
4808 drive <<
4809 bias- <<
4810 }; <<
4811 <<
4812 cci2_i2c1_def <<
4813 /* cc <<
4814 pins <<
4815 funct <<
4816 drive <<
4817 bias- <<
4818 }; <<
4819 }; <<
4820 <<
4821 cci2_sleep: cci2-slee <<
4822 cci2_i2c0_sle <<
4823 /* cc <<
4824 pins <<
4825 funct <<
4826 drive <<
4827 bias- <<
4828 }; <<
4829 <<
4830 cci2_i2c1_sle <<
4831 /* cc <<
4832 pins <<
4833 funct <<
4834 drive <<
4835 bias- <<
4836 }; <<
4837 }; <<
4838 <<
4839 cci3_default: cci3-de <<
4840 cci3_i2c0_def <<
4841 /* cc <<
4842 pins <<
4843 funct <<
4844 drive <<
4845 bias- <<
4846 }; <<
4847 <<
4848 cci3_i2c1_def <<
4849 /* cc <<
4850 pins <<
4851 funct <<
4852 drive <<
4853 bias- <<
4854 }; <<
4855 }; <<
4856 <<
4857 cci3_sleep: cci3-slee <<
4858 cci3_i2c0_sle <<
4859 /* cc <<
4860 pins <<
4861 funct <<
4862 drive <<
4863 bias- <<
4864 }; <<
4865 <<
4866 cci3_i2c1_sle <<
4867 /* cc <<
4868 pins <<
4869 funct <<
4870 drive <<
4871 bias- <<
4872 }; <<
4873 }; <<
4874 }; 3759 };
4875 3760
4876 apps_smmu: iommu@15000000 { 3761 apps_smmu: iommu@15000000 {
4877 compatible = "qcom,sc 3762 compatible = "qcom,sc8280xp-smmu-500", "arm,mmu-500";
4878 reg = <0 0x15000000 0 3763 reg = <0 0x15000000 0 0x100000>;
4879 #iommu-cells = <2>; 3764 #iommu-cells = <2>;
4880 #global-interrupts = 3765 #global-interrupts = <2>;
4881 interrupts = <GIC_SPI 3766 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
4882 <GIC_SPI 3767 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
4883 <GIC_SPI 3768 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
4884 <GIC_SPI 3769 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
4885 <GIC_SPI 3770 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
4886 <GIC_SPI 3771 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
4887 <GIC_SPI 3772 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
4888 <GIC_SPI 3773 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
4889 <GIC_SPI 3774 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
4890 <GIC_SPI 3775 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
4891 <GIC_SPI 3776 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
4892 <GIC_SPI 3777 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
4893 <GIC_SPI 3778 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
4894 <GIC_SPI 3779 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
4895 <GIC_SPI 3780 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
4896 <GIC_SPI 3781 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
4897 <GIC_SPI 3782 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
4898 <GIC_SPI 3783 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
4899 <GIC_SPI 3784 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
4900 <GIC_SPI 3785 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
4901 <GIC_SPI 3786 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
4902 <GIC_SPI 3787 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
4903 <GIC_SPI 3788 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
4904 <GIC_SPI 3789 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
4905 <GIC_SPI 3790 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
4906 <GIC_SPI 3791 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
4907 <GIC_SPI 3792 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
4908 <GIC_SPI 3793 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
4909 <GIC_SPI 3794 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
4910 <GIC_SPI 3795 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
4911 <GIC_SPI 3796 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
4912 <GIC_SPI 3797 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
4913 <GIC_SPI 3798 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
4914 <GIC_SPI 3799 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
4915 <GIC_SPI 3800 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
4916 <GIC_SPI 3801 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
4917 <GIC_SPI 3802 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
4918 <GIC_SPI 3803 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
4919 <GIC_SPI 3804 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
4920 <GIC_SPI 3805 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
4921 <GIC_SPI 3806 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
4922 <GIC_SPI 3807 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
4923 <GIC_SPI 3808 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
4924 <GIC_SPI 3809 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
4925 <GIC_SPI 3810 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
4926 <GIC_SPI 3811 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
4927 <GIC_SPI 3812 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
4928 <GIC_SPI 3813 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
4929 <GIC_SPI 3814 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
4930 <GIC_SPI 3815 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
4931 <GIC_SPI 3816 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
4932 <GIC_SPI 3817 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
4933 <GIC_SPI 3818 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
4934 <GIC_SPI 3819 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
4935 <GIC_SPI 3820 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
4936 <GIC_SPI 3821 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
4937 <GIC_SPI 3822 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
4938 <GIC_SPI 3823 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
4939 <GIC_SPI 3824 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
4940 <GIC_SPI 3825 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
4941 <GIC_SPI 3826 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
4942 <GIC_SPI 3827 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
4943 <GIC_SPI 3828 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
4944 <GIC_SPI 3829 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
4945 <GIC_SPI 3830 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
4946 <GIC_SPI 3831 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
4947 <GIC_SPI 3832 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
4948 <GIC_SPI 3833 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
4949 <GIC_SPI 3834 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
4950 <GIC_SPI 3835 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
4951 <GIC_SPI 3836 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
4952 <GIC_SPI 3837 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
4953 <GIC_SPI 3838 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
4954 <GIC_SPI 3839 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
4955 <GIC_SPI 3840 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
4956 <GIC_SPI 3841 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
4957 <GIC_SPI 3842 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
4958 <GIC_SPI 3843 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
4959 <GIC_SPI 3844 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
4960 <GIC_SPI 3845 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
4961 <GIC_SPI 3846 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>,
4962 <GIC_SPI 3847 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
4963 <GIC_SPI 3848 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
4964 <GIC_SPI 3849 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
4965 <GIC_SPI 3850 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
4966 <GIC_SPI 3851 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
4967 <GIC_SPI 3852 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
4968 <GIC_SPI 3853 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
4969 <GIC_SPI 3854 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
4970 <GIC_SPI 3855 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
4971 <GIC_SPI 3856 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
4972 <GIC_SPI 3857 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
4973 <GIC_SPI 3858 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
4974 <GIC_SPI 3859 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
4975 <GIC_SPI 3860 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
4976 <GIC_SPI 3861 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
4977 <GIC_SPI 3862 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
4978 <GIC_SPI 3863 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
4979 <GIC_SPI 3864 <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>,
4980 <GIC_SPI 3865 <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>,
4981 <GIC_SPI 3866 <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>,
4982 <GIC_SPI 3867 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
4983 <GIC_SPI 3868 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
4984 <GIC_SPI 3869 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
4985 <GIC_SPI 3870 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>,
4986 <GIC_SPI 3871 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>,
4987 <GIC_SPI 3872 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>,
4988 <GIC_SPI 3873 <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>,
4989 <GIC_SPI 3874 <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>,
4990 <GIC_SPI 3875 <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>,
4991 <GIC_SPI 3876 <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>,
4992 <GIC_SPI 3877 <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>,
4993 <GIC_SPI 3878 <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>,
4994 <GIC_SPI 3879 <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>,
4995 <GIC_SPI 3880 <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>,
4996 <GIC_SPI 3881 <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>,
4997 <GIC_SPI 3882 <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>,
4998 <GIC_SPI 3883 <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>,
4999 <GIC_SPI 3884 <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>,
5000 <GIC_SPI 3885 <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>,
5001 <GIC_SPI 3886 <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>,
5002 <GIC_SPI 3887 <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>,
5003 <GIC_SPI 3888 <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>,
5004 <GIC_SPI 3889 <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>,
5005 <GIC_SPI 3890 <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>,
5006 <GIC_SPI 3891 <GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>,
5007 <GIC_SPI 3892 <GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>,
5008 <GIC_SPI 3893 <GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>,
5009 <GIC_SPI 3894 <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>,
5010 <GIC_SPI 3895 <GIC_SPI 890 IRQ_TYPE_LEVEL_HIGH>;
5011 }; 3896 };
5012 3897
5013 intc: interrupt-controller@17 3898 intc: interrupt-controller@17a00000 {
5014 compatible = "arm,gic 3899 compatible = "arm,gic-v3";
5015 interrupt-controller; 3900 interrupt-controller;
5016 #interrupt-cells = <3 3901 #interrupt-cells = <3>;
5017 reg = <0x0 0x17a00000 3902 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
5018 <0x0 0x17a60000 3903 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
5019 interrupts = <GIC_PPI 3904 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
5020 #redistributor-region 3905 #redistributor-regions = <1>;
5021 redistributor-stride 3906 redistributor-stride = <0 0x20000>;
5022 3907
5023 #address-cells = <2>; 3908 #address-cells = <2>;
5024 #size-cells = <2>; 3909 #size-cells = <2>;
5025 ranges; 3910 ranges;
5026 3911
5027 its: msi-controller@1 !! 3912 gic-its@17a40000 {
5028 compatible = 3913 compatible = "arm,gic-v3-its";
5029 reg = <0 0x17 3914 reg = <0 0x17a40000 0 0x20000>;
5030 msi-controlle 3915 msi-controller;
5031 #msi-cells = 3916 #msi-cells = <1>;
5032 }; 3917 };
5033 }; 3918 };
5034 3919
5035 watchdog@17c10000 { 3920 watchdog@17c10000 {
5036 compatible = "qcom,ap 3921 compatible = "qcom,apss-wdt-sc8280xp", "qcom,kpss-wdt";
5037 reg = <0 0x17c10000 0 3922 reg = <0 0x17c10000 0 0x1000>;
5038 clocks = <&sleep_clk> 3923 clocks = <&sleep_clk>;
5039 interrupts = <GIC_SPI !! 3924 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
5040 }; 3925 };
5041 3926
5042 timer@17c20000 { 3927 timer@17c20000 {
5043 compatible = "arm,arm 3928 compatible = "arm,armv7-timer-mem";
5044 reg = <0x0 0x17c20000 3929 reg = <0x0 0x17c20000 0x0 0x1000>;
5045 #address-cells = <1>; 3930 #address-cells = <1>;
5046 #size-cells = <1>; 3931 #size-cells = <1>;
5047 ranges = <0x0 0x0 0x0 3932 ranges = <0x0 0x0 0x0 0x20000000>;
5048 3933
5049 frame@17c21000 { 3934 frame@17c21000 {
5050 frame-number 3935 frame-number = <0>;
5051 interrupts = 3936 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
5052 3937 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
5053 reg = <0x17c2 3938 reg = <0x17c21000 0x1000>,
5054 <0x17c2 3939 <0x17c22000 0x1000>;
5055 }; 3940 };
5056 3941
5057 frame@17c23000 { 3942 frame@17c23000 {
5058 frame-number 3943 frame-number = <1>;
5059 interrupts = 3944 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
5060 reg = <0x17c2 3945 reg = <0x17c23000 0x1000>;
5061 status = "dis 3946 status = "disabled";
5062 }; 3947 };
5063 3948
5064 frame@17c25000 { 3949 frame@17c25000 {
5065 frame-number 3950 frame-number = <2>;
5066 interrupts = 3951 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
5067 reg = <0x17c2 3952 reg = <0x17c25000 0x1000>;
5068 status = "dis 3953 status = "disabled";
5069 }; 3954 };
5070 3955
5071 frame@17c27000 { 3956 frame@17c27000 {
5072 frame-number 3957 frame-number = <3>;
5073 interrupts = 3958 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
5074 reg = <0x17c2 3959 reg = <0x17c26000 0x1000>;
5075 status = "dis 3960 status = "disabled";
5076 }; 3961 };
5077 3962
5078 frame@17c29000 { 3963 frame@17c29000 {
5079 frame-number 3964 frame-number = <4>;
5080 interrupts = 3965 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
5081 reg = <0x17c2 3966 reg = <0x17c29000 0x1000>;
5082 status = "dis 3967 status = "disabled";
5083 }; 3968 };
5084 3969
5085 frame@17c2b000 { 3970 frame@17c2b000 {
5086 frame-number 3971 frame-number = <5>;
5087 interrupts = 3972 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
5088 reg = <0x17c2 3973 reg = <0x17c2b000 0x1000>;
5089 status = "dis 3974 status = "disabled";
5090 }; 3975 };
5091 3976
5092 frame@17c2d000 { 3977 frame@17c2d000 {
5093 frame-number 3978 frame-number = <6>;
5094 interrupts = 3979 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
5095 reg = <0x17c2 3980 reg = <0x17c2d000 0x1000>;
5096 status = "dis 3981 status = "disabled";
5097 }; 3982 };
5098 }; 3983 };
5099 3984
5100 apps_rsc: rsc@18200000 { 3985 apps_rsc: rsc@18200000 {
5101 compatible = "qcom,rp 3986 compatible = "qcom,rpmh-rsc";
5102 reg = <0x0 0x18200000 3987 reg = <0x0 0x18200000 0x0 0x10000>,
5103 <0x0 0x182100 3988 <0x0 0x18210000 0x0 0x10000>,
5104 <0x0 0x182200 3989 <0x0 0x18220000 0x0 0x10000>;
5105 reg-names = "drv-0", 3990 reg-names = "drv-0", "drv-1", "drv-2";
5106 interrupts = <GIC_SPI 3991 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
5107 <GIC_SPI 3992 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
5108 <GIC_SPI 3993 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
5109 qcom,tcs-offset = <0x 3994 qcom,tcs-offset = <0xd00>;
5110 qcom,drv-id = <2>; 3995 qcom,drv-id = <2>;
5111 qcom,tcs-config = <AC 3996 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
5112 <WA 3997 <WAKE_TCS 3>, <CONTROL_TCS 1>;
5113 label = "apps_rsc"; 3998 label = "apps_rsc";
5114 power-domains = <&CLU 3999 power-domains = <&CLUSTER_PD>;
5115 4000
5116 apps_bcm_voter: bcm-v 4001 apps_bcm_voter: bcm-voter {
5117 compatible = 4002 compatible = "qcom,bcm-voter";
5118 }; 4003 };
5119 4004
5120 rpmhcc: clock-control 4005 rpmhcc: clock-controller {
5121 compatible = 4006 compatible = "qcom,sc8280xp-rpmh-clk";
5122 #clock-cells 4007 #clock-cells = <1>;
5123 clock-names = 4008 clock-names = "xo";
5124 clocks = <&xo 4009 clocks = <&xo_board_clk>;
5125 }; 4010 };
5126 4011
5127 rpmhpd: power-control 4012 rpmhpd: power-controller {
5128 compatible = 4013 compatible = "qcom,sc8280xp-rpmhpd";
5129 #power-domain 4014 #power-domain-cells = <1>;
5130 operating-poi 4015 operating-points-v2 = <&rpmhpd_opp_table>;
5131 4016
5132 rpmhpd_opp_ta 4017 rpmhpd_opp_table: opp-table {
5133 compa 4018 compatible = "operating-points-v2";
5134 4019
5135 rpmhp 4020 rpmhpd_opp_ret: opp1 {
5136 4021 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
5137 }; 4022 };
5138 4023
5139 rpmhp 4024 rpmhpd_opp_min_svs: opp2 {
5140 4025 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
5141 }; 4026 };
5142 4027
5143 rpmhp 4028 rpmhpd_opp_low_svs: opp3 {
5144 4029 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
5145 }; 4030 };
5146 4031
5147 rpmhp 4032 rpmhpd_opp_svs: opp4 {
5148 4033 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
5149 }; 4034 };
5150 4035
5151 rpmhp 4036 rpmhpd_opp_svs_l1: opp5 {
5152 4037 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
5153 }; 4038 };
5154 4039
5155 rpmhp 4040 rpmhpd_opp_nom: opp6 {
5156 4041 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
5157 }; 4042 };
5158 4043
5159 rpmhp 4044 rpmhpd_opp_nom_l1: opp7 {
5160 4045 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
5161 }; 4046 };
5162 4047
5163 rpmhp 4048 rpmhpd_opp_nom_l2: opp8 {
5164 4049 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
5165 }; 4050 };
5166 4051
5167 rpmhp 4052 rpmhpd_opp_turbo: opp9 {
5168 4053 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
5169 }; 4054 };
5170 4055
5171 rpmhp 4056 rpmhpd_opp_turbo_l1: opp10 {
5172 4057 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
5173 }; 4058 };
5174 }; 4059 };
5175 }; 4060 };
5176 }; 4061 };
5177 4062
5178 epss_l3: interconnect@1859000 4063 epss_l3: interconnect@18590000 {
5179 compatible = "qcom,sc 4064 compatible = "qcom,sc8280xp-epss-l3", "qcom,epss-l3";
5180 reg = <0 0x18590000 0 4065 reg = <0 0x18590000 0 0x1000>;
5181 4066
5182 clocks = <&rpmhcc RPM 4067 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
5183 clock-names = "xo", " 4068 clock-names = "xo", "alternate";
5184 4069
5185 #interconnect-cells = 4070 #interconnect-cells = <1>;
5186 }; 4071 };
5187 4072
5188 cpufreq_hw: cpufreq@18591000 4073 cpufreq_hw: cpufreq@18591000 {
5189 compatible = "qcom,sc 4074 compatible = "qcom,sc8280xp-cpufreq-epss", "qcom,cpufreq-epss";
5190 reg = <0 0x18591000 0 4075 reg = <0 0x18591000 0 0x1000>,
5191 <0 0x18592000 0 4076 <0 0x18592000 0 0x1000>;
5192 reg-names = "freq-dom 4077 reg-names = "freq-domain0", "freq-domain1";
5193 4078
5194 interrupts = <GIC_SPI <<
5195 <GIC_SPI <<
5196 interrupt-names = "dc <<
5197 "dc <<
5198 <<
5199 clocks = <&rpmhcc RPM 4079 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
5200 clock-names = "xo", " 4080 clock-names = "xo", "alternate";
5201 4081
5202 #freq-domain-cells = 4082 #freq-domain-cells = <1>;
5203 #clock-cells = <1>; 4083 #clock-cells = <1>;
5204 }; 4084 };
5205 4085
5206 remoteproc_nsp0: remoteproc@1 4086 remoteproc_nsp0: remoteproc@1b300000 {
5207 compatible = "qcom,sc 4087 compatible = "qcom,sc8280xp-nsp0-pas";
5208 reg = <0 0x1b300000 0 4088 reg = <0 0x1b300000 0 0x100>;
5209 4089
5210 interrupts-extended = !! 4090 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
5211 4091 <&smp2p_nsp0_in 0 IRQ_TYPE_EDGE_RISING>,
5212 4092 <&smp2p_nsp0_in 1 IRQ_TYPE_EDGE_RISING>,
5213 4093 <&smp2p_nsp0_in 2 IRQ_TYPE_EDGE_RISING>,
5214 4094 <&smp2p_nsp0_in 3 IRQ_TYPE_EDGE_RISING>;
5215 interrupt-names = "wd 4095 interrupt-names = "wdog", "fatal", "ready",
5216 "ha 4096 "handover", "stop-ack";
5217 4097
5218 clocks = <&rpmhcc RPM 4098 clocks = <&rpmhcc RPMH_CXO_CLK>;
5219 clock-names = "xo"; 4099 clock-names = "xo";
5220 4100
5221 power-domains = <&rpm 4101 power-domains = <&rpmhpd SC8280XP_NSP>;
5222 power-domain-names = 4102 power-domain-names = "nsp";
5223 4103
5224 memory-region = <&pil 4104 memory-region = <&pil_nsp0_mem>;
5225 4105
5226 qcom,smem-states = <& 4106 qcom,smem-states = <&smp2p_nsp0_out 0>;
5227 qcom,smem-state-names 4107 qcom,smem-state-names = "stop";
5228 4108
5229 interconnects = <&nsp 4109 interconnects = <&nspa_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>;
5230 4110
5231 status = "disabled"; 4111 status = "disabled";
5232 4112
5233 glink-edge { 4113 glink-edge {
5234 interrupts-ex 4114 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
5235 4115 IPCC_MPROC_SIGNAL_GLINK_QMP
5236 4116 IRQ_TYPE_EDGE_RISING>;
5237 mboxes = <&ip 4117 mboxes = <&ipcc IPCC_CLIENT_CDSP
5238 4118 IPCC_MPROC_SIGNAL_GLINK_QMP>;
5239 4119
5240 label = "nsp0 4120 label = "nsp0";
5241 qcom,remote-p 4121 qcom,remote-pid = <5>;
5242 4122
5243 fastrpc { 4123 fastrpc {
5244 compa 4124 compatible = "qcom,fastrpc";
5245 qcom, 4125 qcom,glink-channels = "fastrpcglink-apps-dsp";
5246 label 4126 label = "cdsp";
5247 #addr 4127 #address-cells = <1>;
5248 #size 4128 #size-cells = <0>;
5249 4129
5250 compu 4130 compute-cb@1 {
5251 4131 compatible = "qcom,fastrpc-compute-cb";
5252 4132 reg = <1>;
5253 4133 iommus = <&apps_smmu 0x3181 0x0420>;
5254 }; 4134 };
5255 4135
5256 compu 4136 compute-cb@2 {
5257 4137 compatible = "qcom,fastrpc-compute-cb";
5258 4138 reg = <2>;
5259 4139 iommus = <&apps_smmu 0x3182 0x0420>;
5260 }; 4140 };
5261 4141
5262 compu 4142 compute-cb@3 {
5263 4143 compatible = "qcom,fastrpc-compute-cb";
5264 4144 reg = <3>;
5265 4145 iommus = <&apps_smmu 0x3183 0x0420>;
5266 }; 4146 };
5267 4147
5268 compu 4148 compute-cb@4 {
5269 4149 compatible = "qcom,fastrpc-compute-cb";
5270 4150 reg = <4>;
5271 4151 iommus = <&apps_smmu 0x3184 0x0420>;
5272 }; 4152 };
5273 4153
5274 compu 4154 compute-cb@5 {
5275 4155 compatible = "qcom,fastrpc-compute-cb";
5276 4156 reg = <5>;
5277 4157 iommus = <&apps_smmu 0x3185 0x0420>;
5278 }; 4158 };
5279 4159
5280 compu 4160 compute-cb@6 {
5281 4161 compatible = "qcom,fastrpc-compute-cb";
5282 4162 reg = <6>;
5283 4163 iommus = <&apps_smmu 0x3186 0x0420>;
5284 }; 4164 };
5285 4165
5286 compu 4166 compute-cb@7 {
5287 4167 compatible = "qcom,fastrpc-compute-cb";
5288 4168 reg = <7>;
5289 4169 iommus = <&apps_smmu 0x3187 0x0420>;
5290 }; 4170 };
5291 4171
5292 compu 4172 compute-cb@8 {
5293 4173 compatible = "qcom,fastrpc-compute-cb";
5294 4174 reg = <8>;
5295 4175 iommus = <&apps_smmu 0x3188 0x0420>;
5296 }; 4176 };
5297 4177
5298 compu 4178 compute-cb@9 {
5299 4179 compatible = "qcom,fastrpc-compute-cb";
5300 4180 reg = <9>;
5301 4181 iommus = <&apps_smmu 0x318b 0x0420>;
5302 }; 4182 };
5303 4183
5304 compu 4184 compute-cb@10 {
5305 4185 compatible = "qcom,fastrpc-compute-cb";
5306 4186 reg = <10>;
5307 4187 iommus = <&apps_smmu 0x318b 0x0420>;
5308 }; 4188 };
5309 4189
5310 compu 4190 compute-cb@11 {
5311 4191 compatible = "qcom,fastrpc-compute-cb";
5312 4192 reg = <11>;
5313 4193 iommus = <&apps_smmu 0x318c 0x0420>;
5314 }; 4194 };
5315 4195
5316 compu 4196 compute-cb@12 {
5317 4197 compatible = "qcom,fastrpc-compute-cb";
5318 4198 reg = <12>;
5319 4199 iommus = <&apps_smmu 0x318d 0x0420>;
5320 }; 4200 };
5321 4201
5322 compu 4202 compute-cb@13 {
5323 4203 compatible = "qcom,fastrpc-compute-cb";
5324 4204 reg = <13>;
5325 4205 iommus = <&apps_smmu 0x318e 0x0420>;
5326 }; 4206 };
5327 4207
5328 compu 4208 compute-cb@14 {
5329 4209 compatible = "qcom,fastrpc-compute-cb";
5330 4210 reg = <14>;
5331 4211 iommus = <&apps_smmu 0x318f 0x0420>;
5332 }; 4212 };
5333 }; 4213 };
5334 }; 4214 };
5335 }; 4215 };
5336 4216
5337 remoteproc_nsp1: remoteproc@2 4217 remoteproc_nsp1: remoteproc@21300000 {
5338 compatible = "qcom,sc 4218 compatible = "qcom,sc8280xp-nsp1-pas";
5339 reg = <0 0x21300000 0 4219 reg = <0 0x21300000 0 0x100>;
5340 4220
5341 interrupts-extended = !! 4221 interrupts-extended = <&intc GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>,
5342 4222 <&smp2p_nsp1_in 0 IRQ_TYPE_EDGE_RISING>,
5343 4223 <&smp2p_nsp1_in 1 IRQ_TYPE_EDGE_RISING>,
5344 4224 <&smp2p_nsp1_in 2 IRQ_TYPE_EDGE_RISING>,
5345 4225 <&smp2p_nsp1_in 3 IRQ_TYPE_EDGE_RISING>;
5346 interrupt-names = "wd 4226 interrupt-names = "wdog", "fatal", "ready",
5347 "ha 4227 "handover", "stop-ack";
5348 4228
5349 clocks = <&rpmhcc RPM 4229 clocks = <&rpmhcc RPMH_CXO_CLK>;
5350 clock-names = "xo"; 4230 clock-names = "xo";
5351 4231
5352 power-domains = <&rpm 4232 power-domains = <&rpmhpd SC8280XP_NSP>;
5353 power-domain-names = 4233 power-domain-names = "nsp";
5354 4234
5355 memory-region = <&pil 4235 memory-region = <&pil_nsp1_mem>;
5356 4236
5357 qcom,smem-states = <& 4237 qcom,smem-states = <&smp2p_nsp1_out 0>;
5358 qcom,smem-state-names 4238 qcom,smem-state-names = "stop";
5359 4239
5360 interconnects = <&nsp 4240 interconnects = <&nspb_noc MASTER_CDSP_PROC_B 0 &mc_virt SLAVE_EBI1 0>;
5361 4241
5362 status = "disabled"; 4242 status = "disabled";
5363 4243
5364 glink-edge { 4244 glink-edge {
5365 interrupts-ex 4245 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1
5366 4246 IPCC_MPROC_SIGNAL_GLINK_QMP
5367 4247 IRQ_TYPE_EDGE_RISING>;
5368 mboxes = <&ip 4248 mboxes = <&ipcc IPCC_CLIENT_NSP1
5369 4249 IPCC_MPROC_SIGNAL_GLINK_QMP>;
5370 4250
5371 label = "nsp1 4251 label = "nsp1";
5372 qcom,remote-p 4252 qcom,remote-pid = <12>;
5373 }; 4253 };
5374 }; 4254 };
5375 4255
5376 mdss1: display-subsystem@2200 4256 mdss1: display-subsystem@22000000 {
5377 compatible = "qcom,sc 4257 compatible = "qcom,sc8280xp-mdss";
5378 reg = <0 0x22000000 0 4258 reg = <0 0x22000000 0 0x1000>;
5379 reg-names = "mdss"; 4259 reg-names = "mdss";
5380 4260
5381 clocks = <&gcc GCC_DI 4261 clocks = <&gcc GCC_DISP_AHB_CLK>,
5382 <&dispcc1 DI 4262 <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
5383 <&dispcc1 DI 4263 <&dispcc1 DISP_CC_MDSS_MDP_CLK>;
5384 clock-names = "iface" 4264 clock-names = "iface",
5385 "ahb", 4265 "ahb",
5386 "core"; 4266 "core";
5387 interconnects = <&mms 4267 interconnects = <&mmss_noc MASTER_MDP_CORE1_0 0 &mc_virt SLAVE_EBI1 0>,
5388 <&mms 4268 <&mmss_noc MASTER_MDP_CORE1_1 0 &mc_virt SLAVE_EBI1 0>;
5389 interconnect-names = 4269 interconnect-names = "mdp0-mem", "mdp1-mem";
5390 interrupts = <GIC_SPI 4270 interrupts = <GIC_SPI 865 IRQ_TYPE_LEVEL_HIGH>;
5391 4271
5392 iommus = <&apps_smmu 4272 iommus = <&apps_smmu 0x1800 0x402>;
5393 power-domains = <&dis 4273 power-domains = <&dispcc1 MDSS_GDSC>;
5394 resets = <&dispcc1 DI 4274 resets = <&dispcc1 DISP_CC_MDSS_CORE_BCR>;
5395 4275
5396 interrupt-controller; 4276 interrupt-controller;
5397 #interrupt-cells = <1 4277 #interrupt-cells = <1>;
5398 #address-cells = <2>; 4278 #address-cells = <2>;
5399 #size-cells = <2>; 4279 #size-cells = <2>;
5400 ranges; 4280 ranges;
5401 4281
5402 status = "disabled"; 4282 status = "disabled";
5403 4283
5404 mdss1_mdp: display-co 4284 mdss1_mdp: display-controller@22001000 {
5405 compatible = 4285 compatible = "qcom,sc8280xp-dpu";
5406 reg = <0 0x22 4286 reg = <0 0x22001000 0 0x8f000>,
5407 <0 0x22 4287 <0 0x220b0000 0 0x2008>;
5408 reg-names = " 4288 reg-names = "mdp", "vbif";
5409 4289
5410 clocks = <&gc 4290 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
5411 <&gc 4291 <&gcc GCC_DISP_SF_AXI_CLK>,
5412 <&di 4292 <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
5413 <&di 4293 <&dispcc1 DISP_CC_MDSS_MDP_LUT_CLK>,
5414 <&di 4294 <&dispcc1 DISP_CC_MDSS_MDP_CLK>,
5415 <&di 4295 <&dispcc1 DISP_CC_MDSS_VSYNC_CLK>;
5416 clock-names = 4296 clock-names = "bus",
5417 4297 "nrt_bus",
5418 4298 "iface",
5419 4299 "lut",
5420 4300 "core",
5421 4301 "vsync";
5422 interrupt-par 4302 interrupt-parent = <&mdss1>;
5423 interrupts = 4303 interrupts = <0>;
5424 power-domains 4304 power-domains = <&rpmhpd SC8280XP_MMCX>;
5425 4305
5426 assigned-cloc 4306 assigned-clocks = <&dispcc1 DISP_CC_MDSS_VSYNC_CLK>;
5427 assigned-cloc 4307 assigned-clock-rates = <19200000>;
5428 operating-poi 4308 operating-points-v2 = <&mdss1_mdp_opp_table>;
5429 4309
5430 ports { 4310 ports {
5431 #addr 4311 #address-cells = <1>;
5432 #size 4312 #size-cells = <0>;
5433 4313
5434 port@ 4314 port@0 {
5435 4315 reg = <0>;
5436 4316 mdss1_intf0_out: endpoint {
5437 4317 remote-endpoint = <&mdss1_dp0_in>;
5438 4318 };
5439 }; 4319 };
5440 4320
5441 port@ 4321 port@4 {
5442 4322 reg = <4>;
5443 4323 mdss1_intf4_out: endpoint {
5444 4324 remote-endpoint = <&mdss1_dp1_in>;
5445 4325 };
5446 }; 4326 };
5447 4327
5448 port@ 4328 port@5 {
5449 4329 reg = <5>;
5450 4330 mdss1_intf5_out: endpoint {
5451 4331 remote-endpoint = <&mdss1_dp3_in>;
5452 4332 };
5453 }; 4333 };
5454 4334
5455 port@ 4335 port@6 {
5456 4336 reg = <6>;
5457 4337 mdss1_intf6_out: endpoint {
5458 4338 remote-endpoint = <&mdss1_dp2_in>;
5459 4339 };
5460 }; 4340 };
5461 }; 4341 };
5462 4342
5463 mdss1_mdp_opp 4343 mdss1_mdp_opp_table: opp-table {
5464 compa 4344 compatible = "operating-points-v2";
5465 4345
5466 opp-2 4346 opp-200000000 {
5467 4347 opp-hz = /bits/ 64 <200000000>;
5468 4348 required-opps = <&rpmhpd_opp_low_svs>;
5469 }; 4349 };
5470 4350
5471 opp-3 4351 opp-300000000 {
5472 4352 opp-hz = /bits/ 64 <300000000>;
5473 4353 required-opps = <&rpmhpd_opp_svs>;
5474 }; 4354 };
5475 4355
5476 opp-3 4356 opp-375000000 {
5477 4357 opp-hz = /bits/ 64 <375000000>;
5478 4358 required-opps = <&rpmhpd_opp_svs_l1>;
5479 }; 4359 };
5480 4360
5481 opp-5 4361 opp-500000000 {
5482 4362 opp-hz = /bits/ 64 <500000000>;
5483 4363 required-opps = <&rpmhpd_opp_nom>;
5484 }; 4364 };
5485 opp-6 4365 opp-600000000 {
5486 4366 opp-hz = /bits/ 64 <600000000>;
5487 4367 required-opps = <&rpmhpd_opp_turbo_l1>;
5488 }; 4368 };
5489 }; 4369 };
5490 }; 4370 };
5491 4371
5492 mdss1_dp0: displaypor 4372 mdss1_dp0: displayport-controller@22090000 {
5493 compatible = 4373 compatible = "qcom,sc8280xp-dp";
5494 reg = <0 0x22 4374 reg = <0 0x22090000 0 0x200>,
5495 <0 0x22 4375 <0 0x22090200 0 0x200>,
5496 <0 0x22 4376 <0 0x22090400 0 0x600>,
5497 <0 0x22 4377 <0 0x22091000 0 0x400>,
5498 <0 0x22 4378 <0 0x22091400 0 0x400>;
5499 4379
5500 clocks = <&di 4380 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
5501 <&di 4381 <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>,
5502 <&di 4382 <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK>,
5503 <&di 4383 <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
5504 <&di 4384 <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
5505 clock-names = 4385 clock-names = "core_iface", "core_aux",
5506 4386 "ctrl_link",
5507 4387 "ctrl_link_iface", "stream_pixel";
5508 interrupt-par 4388 interrupt-parent = <&mdss1>;
5509 interrupts = 4389 interrupts = <12>;
5510 phys = <&mdss 4390 phys = <&mdss1_dp0_phy>;
5511 phy-names = " 4391 phy-names = "dp";
5512 power-domains 4392 power-domains = <&rpmhpd SC8280XP_MMCX>;
5513 4393
5514 assigned-cloc 4394 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
5515 4395 <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
5516 assigned-cloc 4396 assigned-clock-parents = <&mdss1_dp0_phy 0>, <&mdss1_dp0_phy 1>;
5517 operating-poi 4397 operating-points-v2 = <&mdss1_dp0_opp_table>;
5518 4398
5519 #sound-dai-ce 4399 #sound-dai-cells = <0>;
5520 4400
5521 status = "dis 4401 status = "disabled";
5522 4402
5523 ports { 4403 ports {
5524 #addr 4404 #address-cells = <1>;
5525 #size 4405 #size-cells = <0>;
5526 4406
5527 port@ 4407 port@0 {
5528 4408 reg = <0>;
5529 4409 mdss1_dp0_in: endpoint {
5530 4410 remote-endpoint = <&mdss1_intf0_out>;
5531 4411 };
5532 }; 4412 };
5533 4413
5534 port@ 4414 port@1 {
5535 4415 reg = <1>;
5536 }; 4416 };
5537 }; 4417 };
5538 4418
5539 mdss1_dp0_opp 4419 mdss1_dp0_opp_table: opp-table {
5540 compa 4420 compatible = "operating-points-v2";
5541 4421
5542 opp-1 4422 opp-160000000 {
5543 4423 opp-hz = /bits/ 64 <160000000>;
5544 4424 required-opps = <&rpmhpd_opp_low_svs>;
5545 }; 4425 };
5546 4426
5547 opp-2 4427 opp-270000000 {
5548 4428 opp-hz = /bits/ 64 <270000000>;
5549 4429 required-opps = <&rpmhpd_opp_svs>;
5550 }; 4430 };
5551 4431
5552 opp-5 4432 opp-540000000 {
5553 4433 opp-hz = /bits/ 64 <540000000>;
5554 4434 required-opps = <&rpmhpd_opp_svs_l1>;
5555 }; 4435 };
5556 4436
5557 opp-8 4437 opp-810000000 {
5558 4438 opp-hz = /bits/ 64 <810000000>;
5559 4439 required-opps = <&rpmhpd_opp_nom>;
5560 }; 4440 };
5561 }; 4441 };
5562 }; 4442 };
5563 4443
5564 mdss1_dp1: displaypor 4444 mdss1_dp1: displayport-controller@22098000 {
5565 compatible = 4445 compatible = "qcom,sc8280xp-dp";
5566 reg = <0 0x22 4446 reg = <0 0x22098000 0 0x200>,
5567 <0 0x22 4447 <0 0x22098200 0 0x200>,
5568 <0 0x22 4448 <0 0x22098400 0 0x600>,
5569 <0 0x22 4449 <0 0x22099000 0 0x400>,
5570 <0 0x22 4450 <0 0x22099400 0 0x400>;
5571 4451
5572 clocks = <&di 4452 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
5573 <&di 4453 <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>,
5574 <&di 4454 <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK>,
5575 <&di 4455 <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
5576 <&di 4456 <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>;
5577 clock-names = 4457 clock-names = "core_iface", "core_aux",
5578 4458 "ctrl_link",
5579 4459 "ctrl_link_iface", "stream_pixel";
5580 interrupt-par 4460 interrupt-parent = <&mdss1>;
5581 interrupts = 4461 interrupts = <13>;
5582 phys = <&mdss 4462 phys = <&mdss1_dp1_phy>;
5583 phy-names = " 4463 phy-names = "dp";
5584 power-domains 4464 power-domains = <&rpmhpd SC8280XP_MMCX>;
5585 4465
5586 assigned-cloc 4466 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
5587 4467 <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>;
5588 assigned-cloc 4468 assigned-clock-parents = <&mdss1_dp1_phy 0>, <&mdss1_dp1_phy 1>;
5589 operating-poi 4469 operating-points-v2 = <&mdss1_dp1_opp_table>;
5590 4470
5591 #sound-dai-ce 4471 #sound-dai-cells = <0>;
5592 4472
5593 status = "dis 4473 status = "disabled";
5594 4474
5595 ports { 4475 ports {
5596 #addr 4476 #address-cells = <1>;
5597 #size 4477 #size-cells = <0>;
5598 4478
5599 port@ 4479 port@0 {
5600 4480 reg = <0>;
5601 4481 mdss1_dp1_in: endpoint {
5602 4482 remote-endpoint = <&mdss1_intf4_out>;
5603 4483 };
5604 }; 4484 };
5605 4485
5606 port@ 4486 port@1 {
5607 4487 reg = <1>;
5608 }; 4488 };
5609 }; 4489 };
5610 4490
5611 mdss1_dp1_opp 4491 mdss1_dp1_opp_table: opp-table {
5612 compa 4492 compatible = "operating-points-v2";
5613 4493
5614 opp-1 4494 opp-160000000 {
5615 4495 opp-hz = /bits/ 64 <160000000>;
5616 4496 required-opps = <&rpmhpd_opp_low_svs>;
5617 }; 4497 };
5618 4498
5619 opp-2 4499 opp-270000000 {
5620 4500 opp-hz = /bits/ 64 <270000000>;
5621 4501 required-opps = <&rpmhpd_opp_svs>;
5622 }; 4502 };
5623 4503
5624 opp-5 4504 opp-540000000 {
5625 4505 opp-hz = /bits/ 64 <540000000>;
5626 4506 required-opps = <&rpmhpd_opp_svs_l1>;
5627 }; 4507 };
5628 4508
5629 opp-8 4509 opp-810000000 {
5630 4510 opp-hz = /bits/ 64 <810000000>;
5631 4511 required-opps = <&rpmhpd_opp_nom>;
5632 }; 4512 };
5633 }; 4513 };
5634 }; 4514 };
5635 4515
5636 mdss1_dp2: displaypor 4516 mdss1_dp2: displayport-controller@2209a000 {
5637 compatible = 4517 compatible = "qcom,sc8280xp-dp";
5638 reg = <0 0x22 4518 reg = <0 0x2209a000 0 0x200>,
5639 <0 0x22 4519 <0 0x2209a200 0 0x200>,
5640 <0 0x22 4520 <0 0x2209a400 0 0x600>,
5641 <0 0x22 4521 <0 0x2209b000 0 0x400>,
5642 <0 0x22 4522 <0 0x2209b400 0 0x400>;
5643 4523
5644 clocks = <&di 4524 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
5645 <&di 4525 <&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>,
5646 <&di 4526 <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK>,
5647 <&di 4527 <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>,
5648 <&di 4528 <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>;
5649 clock-names = 4529 clock-names = "core_iface", "core_aux",
5650 4530 "ctrl_link",
5651 4531 "ctrl_link_iface", "stream_pixel";
5652 interrupt-par 4532 interrupt-parent = <&mdss1>;
5653 interrupts = 4533 interrupts = <14>;
5654 phys = <&mdss 4534 phys = <&mdss1_dp2_phy>;
5655 phy-names = " 4535 phy-names = "dp";
5656 power-domains 4536 power-domains = <&rpmhpd SC8280XP_MMCX>;
5657 4537
5658 assigned-cloc 4538 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
5659 4539 <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>;
5660 assigned-cloc 4540 assigned-clock-parents = <&mdss1_dp2_phy 0>, <&mdss1_dp2_phy 1>;
5661 operating-poi 4541 operating-points-v2 = <&mdss1_dp2_opp_table>;
5662 4542
5663 #sound-dai-ce 4543 #sound-dai-cells = <0>;
5664 4544
5665 status = "dis 4545 status = "disabled";
5666 4546
5667 ports { 4547 ports {
5668 #addr 4548 #address-cells = <1>;
5669 #size 4549 #size-cells = <0>;
5670 4550
5671 port@ 4551 port@0 {
5672 4552 reg = <0>;
5673 4553 mdss1_dp2_in: endpoint {
5674 4554 remote-endpoint = <&mdss1_intf6_out>;
5675 4555 };
5676 }; 4556 };
5677 4557
5678 port@ 4558 port@1 {
5679 4559 reg = <1>;
5680 }; 4560 };
5681 }; 4561 };
5682 4562
5683 mdss1_dp2_opp 4563 mdss1_dp2_opp_table: opp-table {
5684 compa 4564 compatible = "operating-points-v2";
5685 4565
5686 opp-1 4566 opp-160000000 {
5687 4567 opp-hz = /bits/ 64 <160000000>;
5688 4568 required-opps = <&rpmhpd_opp_low_svs>;
5689 }; 4569 };
5690 4570
5691 opp-2 4571 opp-270000000 {
5692 4572 opp-hz = /bits/ 64 <270000000>;
5693 4573 required-opps = <&rpmhpd_opp_svs>;
5694 }; 4574 };
5695 4575
5696 opp-5 4576 opp-540000000 {
5697 4577 opp-hz = /bits/ 64 <540000000>;
5698 4578 required-opps = <&rpmhpd_opp_svs_l1>;
5699 }; 4579 };
5700 4580
5701 opp-8 4581 opp-810000000 {
5702 4582 opp-hz = /bits/ 64 <810000000>;
5703 4583 required-opps = <&rpmhpd_opp_nom>;
5704 }; 4584 };
5705 }; 4585 };
5706 }; 4586 };
5707 4587
5708 mdss1_dp3: displaypor 4588 mdss1_dp3: displayport-controller@220a0000 {
5709 compatible = 4589 compatible = "qcom,sc8280xp-dp";
5710 reg = <0 0x22 4590 reg = <0 0x220a0000 0 0x200>,
5711 <0 0x22 4591 <0 0x220a0200 0 0x200>,
5712 <0 0x22 4592 <0 0x220a0400 0 0x600>,
5713 <0 0x22 4593 <0 0x220a1000 0 0x400>,
5714 <0 0x22 4594 <0 0x220a1400 0 0x400>;
5715 4595
5716 clocks = <&di 4596 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
5717 <&di 4597 <&dispcc1 DISP_CC_MDSS_DPTX3_AUX_CLK>,
5718 <&di 4598 <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_CLK>,
5719 <&di 4599 <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>,
5720 <&di 4600 <&dispcc1 DISP_CC_MDSS_DPTX3_PIXEL0_CLK>;
5721 clock-names = 4601 clock-names = "core_iface", "core_aux",
5722 4602 "ctrl_link",
5723 4603 "ctrl_link_iface", "stream_pixel";
5724 interrupt-par 4604 interrupt-parent = <&mdss1>;
5725 interrupts = 4605 interrupts = <15>;
5726 phys = <&mdss 4606 phys = <&mdss1_dp3_phy>;
5727 phy-names = " 4607 phy-names = "dp";
5728 power-domains 4608 power-domains = <&rpmhpd SC8280XP_MMCX>;
5729 4609
5730 assigned-cloc 4610 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>,
5731 4611 <&dispcc1 DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>;
5732 assigned-cloc 4612 assigned-clock-parents = <&mdss1_dp3_phy 0>, <&mdss1_dp3_phy 1>;
5733 operating-poi 4613 operating-points-v2 = <&mdss1_dp3_opp_table>;
5734 4614
5735 #sound-dai-ce 4615 #sound-dai-cells = <0>;
5736 4616
5737 status = "dis 4617 status = "disabled";
5738 4618
5739 ports { 4619 ports {
5740 #addr 4620 #address-cells = <1>;
5741 #size 4621 #size-cells = <0>;
5742 4622
5743 port@ 4623 port@0 {
5744 4624 reg = <0>;
5745 4625 mdss1_dp3_in: endpoint {
5746 4626 remote-endpoint = <&mdss1_intf5_out>;
5747 4627 };
5748 }; 4628 };
5749 4629
5750 port@ 4630 port@1 {
5751 4631 reg = <1>;
5752 }; 4632 };
5753 }; 4633 };
5754 4634
5755 mdss1_dp3_opp 4635 mdss1_dp3_opp_table: opp-table {
5756 compa 4636 compatible = "operating-points-v2";
5757 4637
5758 opp-1 4638 opp-160000000 {
5759 4639 opp-hz = /bits/ 64 <160000000>;
5760 4640 required-opps = <&rpmhpd_opp_low_svs>;
5761 }; 4641 };
5762 4642
5763 opp-2 4643 opp-270000000 {
5764 4644 opp-hz = /bits/ 64 <270000000>;
5765 4645 required-opps = <&rpmhpd_opp_svs>;
5766 }; 4646 };
5767 4647
5768 opp-5 4648 opp-540000000 {
5769 4649 opp-hz = /bits/ 64 <540000000>;
5770 4650 required-opps = <&rpmhpd_opp_svs_l1>;
5771 }; 4651 };
5772 4652
5773 opp-8 4653 opp-810000000 {
5774 4654 opp-hz = /bits/ 64 <810000000>;
5775 4655 required-opps = <&rpmhpd_opp_nom>;
5776 }; 4656 };
5777 }; 4657 };
5778 }; 4658 };
5779 }; 4659 };
5780 4660
5781 mdss1_dp2_phy: phy@220c2a00 { 4661 mdss1_dp2_phy: phy@220c2a00 {
5782 compatible = "qcom,sc 4662 compatible = "qcom,sc8280xp-dp-phy";
5783 reg = <0 0x220c2a00 0 4663 reg = <0 0x220c2a00 0 0x19c>,
5784 <0 0x220c2200 0 4664 <0 0x220c2200 0 0xec>,
5785 <0 0x220c2600 0 4665 <0 0x220c2600 0 0xec>,
5786 <0 0x220c2000 0 4666 <0 0x220c2000 0 0x1c8>;
5787 4667
5788 clocks = <&dispcc1 DI 4668 clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>,
5789 <&dispcc1 DI 4669 <&dispcc1 DISP_CC_MDSS_AHB_CLK>;
5790 clock-names = "aux", 4670 clock-names = "aux", "cfg_ahb";
5791 power-domains = <&rpm 4671 power-domains = <&rpmhpd SC8280XP_MX>;
5792 4672
5793 #clock-cells = <1>; 4673 #clock-cells = <1>;
5794 #phy-cells = <0>; 4674 #phy-cells = <0>;
5795 4675
5796 status = "disabled"; 4676 status = "disabled";
5797 }; 4677 };
5798 4678
5799 mdss1_dp3_phy: phy@220c5a00 { 4679 mdss1_dp3_phy: phy@220c5a00 {
5800 compatible = "qcom,sc 4680 compatible = "qcom,sc8280xp-dp-phy";
5801 reg = <0 0x220c5a00 0 4681 reg = <0 0x220c5a00 0 0x19c>,
5802 <0 0x220c5200 0 4682 <0 0x220c5200 0 0xec>,
5803 <0 0x220c5600 0 4683 <0 0x220c5600 0 0xec>,
5804 <0 0x220c5000 0 4684 <0 0x220c5000 0 0x1c8>;
5805 4685
5806 clocks = <&dispcc1 DI 4686 clocks = <&dispcc1 DISP_CC_MDSS_DPTX3_AUX_CLK>,
5807 <&dispcc1 DI 4687 <&dispcc1 DISP_CC_MDSS_AHB_CLK>;
5808 clock-names = "aux", 4688 clock-names = "aux", "cfg_ahb";
5809 power-domains = <&rpm 4689 power-domains = <&rpmhpd SC8280XP_MX>;
5810 4690
5811 #clock-cells = <1>; 4691 #clock-cells = <1>;
5812 #phy-cells = <0>; 4692 #phy-cells = <0>;
5813 4693
5814 status = "disabled"; 4694 status = "disabled";
5815 }; 4695 };
5816 4696
5817 dispcc1: clock-controller@221 4697 dispcc1: clock-controller@22100000 {
5818 compatible = "qcom,sc 4698 compatible = "qcom,sc8280xp-dispcc1";
5819 reg = <0 0x22100000 0 4699 reg = <0 0x22100000 0 0x20000>;
5820 4700
5821 clocks = <&gcc GCC_DI 4701 clocks = <&gcc GCC_DISP_AHB_CLK>,
5822 <&rpmhcc RPM 4702 <&rpmhcc RPMH_CXO_CLK>,
5823 <0>, 4703 <0>,
5824 <&mdss1_dp0_ 4704 <&mdss1_dp0_phy 0>,
5825 <&mdss1_dp0_ 4705 <&mdss1_dp0_phy 1>,
5826 <&mdss1_dp1_ 4706 <&mdss1_dp1_phy 0>,
5827 <&mdss1_dp1_ 4707 <&mdss1_dp1_phy 1>,
5828 <&mdss1_dp2_ 4708 <&mdss1_dp2_phy 0>,
5829 <&mdss1_dp2_ 4709 <&mdss1_dp2_phy 1>,
5830 <&mdss1_dp3_ 4710 <&mdss1_dp3_phy 0>,
5831 <&mdss1_dp3_ 4711 <&mdss1_dp3_phy 1>,
5832 <0>, 4712 <0>,
5833 <0>, 4713 <0>,
5834 <0>, 4714 <0>,
5835 <0>; 4715 <0>;
5836 power-domains = <&rpm 4716 power-domains = <&rpmhpd SC8280XP_MMCX>;
5837 4717
5838 #clock-cells = <1>; 4718 #clock-cells = <1>;
5839 #power-domain-cells = 4719 #power-domain-cells = <1>;
5840 #reset-cells = <1>; 4720 #reset-cells = <1>;
5841 4721
5842 status = "disabled"; 4722 status = "disabled";
5843 }; 4723 };
5844 <<
5845 ethernet1: ethernet@23000000 <<
5846 compatible = "qcom,sc <<
5847 reg = <0x0 0x23000000 <<
5848 <0x0 0x23016000 <<
5849 reg-names = "stmmacet <<
5850 <<
5851 clocks = <&gcc GCC_EM <<
5852 <&gcc GCC_EM <<
5853 <&gcc GCC_EM <<
5854 <&gcc GCC_EM <<
5855 clock-names = "stmmac <<
5856 "pclk", <<
5857 "ptp_re <<
5858 "rgmii" <<
5859 <<
5860 interrupts = <GIC_SPI <<
5861 <GIC_SPI <<
5862 interrupt-names = "ma <<
5863 <<
5864 iommus = <&apps_smmu <<
5865 power-domains = <&gcc <<
5866 <<
5867 snps,tso; <<
5868 snps,pbl = <32>; <<
5869 rx-fifo-depth = <4096 <<
5870 tx-fifo-depth = <4096 <<
5871 <<
5872 status = "disabled"; <<
5873 }; <<
5874 }; 4724 };
5875 4725
5876 sound: sound { 4726 sound: sound {
5877 }; 4727 };
5878 4728
5879 thermal-zones { 4729 thermal-zones {
5880 cpu0-thermal { 4730 cpu0-thermal {
5881 polling-delay-passive 4731 polling-delay-passive = <250>;
>> 4732 polling-delay = <1000>;
5882 4733
5883 thermal-sensors = <&t 4734 thermal-sensors = <&tsens0 1>;
5884 4735
5885 trips { 4736 trips {
5886 cpu-crit { 4737 cpu-crit {
5887 tempe 4738 temperature = <110000>;
5888 hyste 4739 hysteresis = <1000>;
5889 type 4740 type = "critical";
5890 }; 4741 };
5891 }; 4742 };
5892 }; 4743 };
5893 4744
5894 cpu1-thermal { 4745 cpu1-thermal {
5895 polling-delay-passive 4746 polling-delay-passive = <250>;
>> 4747 polling-delay = <1000>;
5896 4748
5897 thermal-sensors = <&t 4749 thermal-sensors = <&tsens0 2>;
5898 4750
5899 trips { 4751 trips {
5900 cpu-crit { 4752 cpu-crit {
5901 tempe 4753 temperature = <110000>;
5902 hyste 4754 hysteresis = <1000>;
5903 type 4755 type = "critical";
5904 }; 4756 };
5905 }; 4757 };
5906 }; 4758 };
5907 4759
5908 cpu2-thermal { 4760 cpu2-thermal {
5909 polling-delay-passive 4761 polling-delay-passive = <250>;
>> 4762 polling-delay = <1000>;
5910 4763
5911 thermal-sensors = <&t 4764 thermal-sensors = <&tsens0 3>;
5912 4765
5913 trips { 4766 trips {
5914 cpu-crit { 4767 cpu-crit {
5915 tempe 4768 temperature = <110000>;
5916 hyste 4769 hysteresis = <1000>;
5917 type 4770 type = "critical";
5918 }; 4771 };
5919 }; 4772 };
5920 }; 4773 };
5921 4774
5922 cpu3-thermal { 4775 cpu3-thermal {
5923 polling-delay-passive 4776 polling-delay-passive = <250>;
>> 4777 polling-delay = <1000>;
5924 4778
5925 thermal-sensors = <&t 4779 thermal-sensors = <&tsens0 4>;
5926 4780
5927 trips { 4781 trips {
5928 cpu-crit { 4782 cpu-crit {
5929 tempe 4783 temperature = <110000>;
5930 hyste 4784 hysteresis = <1000>;
5931 type 4785 type = "critical";
5932 }; 4786 };
5933 }; 4787 };
5934 }; 4788 };
5935 4789
5936 cpu4-thermal { 4790 cpu4-thermal {
5937 polling-delay-passive 4791 polling-delay-passive = <250>;
>> 4792 polling-delay = <1000>;
5938 4793
5939 thermal-sensors = <&t 4794 thermal-sensors = <&tsens0 5>;
5940 4795
5941 trips { 4796 trips {
5942 cpu-crit { 4797 cpu-crit {
5943 tempe 4798 temperature = <110000>;
5944 hyste 4799 hysteresis = <1000>;
5945 type 4800 type = "critical";
5946 }; 4801 };
5947 }; 4802 };
5948 }; 4803 };
5949 4804
5950 cpu5-thermal { 4805 cpu5-thermal {
5951 polling-delay-passive 4806 polling-delay-passive = <250>;
>> 4807 polling-delay = <1000>;
5952 4808
5953 thermal-sensors = <&t 4809 thermal-sensors = <&tsens0 6>;
5954 4810
5955 trips { 4811 trips {
5956 cpu-crit { 4812 cpu-crit {
5957 tempe 4813 temperature = <110000>;
5958 hyste 4814 hysteresis = <1000>;
5959 type 4815 type = "critical";
5960 }; 4816 };
5961 }; 4817 };
5962 }; 4818 };
5963 4819
5964 cpu6-thermal { 4820 cpu6-thermal {
5965 polling-delay-passive 4821 polling-delay-passive = <250>;
>> 4822 polling-delay = <1000>;
5966 4823
5967 thermal-sensors = <&t 4824 thermal-sensors = <&tsens0 7>;
5968 4825
5969 trips { 4826 trips {
5970 cpu-crit { 4827 cpu-crit {
5971 tempe 4828 temperature = <110000>;
5972 hyste 4829 hysteresis = <1000>;
5973 type 4830 type = "critical";
5974 }; 4831 };
5975 }; 4832 };
5976 }; 4833 };
5977 4834
5978 cpu7-thermal { 4835 cpu7-thermal {
5979 polling-delay-passive 4836 polling-delay-passive = <250>;
>> 4837 polling-delay = <1000>;
5980 4838
5981 thermal-sensors = <&t 4839 thermal-sensors = <&tsens0 8>;
5982 4840
5983 trips { 4841 trips {
5984 cpu-crit { 4842 cpu-crit {
5985 tempe 4843 temperature = <110000>;
5986 hyste 4844 hysteresis = <1000>;
5987 type 4845 type = "critical";
5988 }; 4846 };
5989 }; 4847 };
5990 }; 4848 };
5991 4849
5992 cluster0-thermal { 4850 cluster0-thermal {
5993 polling-delay-passive 4851 polling-delay-passive = <250>;
>> 4852 polling-delay = <1000>;
5994 4853
5995 thermal-sensors = <&t 4854 thermal-sensors = <&tsens0 9>;
5996 4855
5997 trips { 4856 trips {
5998 cpu-crit { 4857 cpu-crit {
5999 tempe 4858 temperature = <110000>;
6000 hyste 4859 hysteresis = <1000>;
6001 type 4860 type = "critical";
6002 }; 4861 };
6003 }; 4862 };
6004 }; 4863 };
6005 4864
6006 gpu-thermal { <<
6007 polling-delay-passive <<
6008 <<
6009 thermal-sensors = <&t <<
6010 <<
6011 cooling-maps { <<
6012 map0 { <<
6013 trip <<
6014 cooli <<
6015 }; <<
6016 }; <<
6017 <<
6018 trips { <<
6019 gpu_alert0: t <<
6020 tempe <<
6021 hyste <<
6022 type <<
6023 }; <<
6024 <<
6025 trip-point1 { <<
6026 tempe <<
6027 hyste <<
6028 type <<
6029 }; <<
6030 }; <<
6031 }; <<
6032 <<
6033 mem-thermal { 4865 mem-thermal {
6034 polling-delay-passive 4866 polling-delay-passive = <250>;
>> 4867 polling-delay = <1000>;
6035 4868
6036 thermal-sensors = <&t 4869 thermal-sensors = <&tsens1 15>;
6037 4870
6038 trips { 4871 trips {
6039 trip-point0 { 4872 trip-point0 {
6040 tempe 4873 temperature = <90000>;
6041 hyste 4874 hysteresis = <2000>;
6042 type 4875 type = "hot";
6043 }; 4876 };
6044 }; 4877 };
6045 }; 4878 };
6046 }; 4879 };
6047 4880
6048 timer { 4881 timer {
6049 compatible = "arm,armv8-timer 4882 compatible = "arm,armv8-timer";
6050 interrupts = <GIC_PPI 13 (GIC 4883 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
6051 <GIC_PPI 14 (GIC 4884 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
6052 <GIC_PPI 11 (GIC 4885 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
6053 <GIC_PPI 10 (GIC 4886 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
6054 }; 4887 };
6055 }; 4888 };
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