1 // SPDX-License-Identifier: BSD-3-Clause 1 // SPDX-License-Identifier: BSD-3-Clause
2 /* 2 /*
3 * Copyright (c) 2021, The Linux Foundation. A 3 * Copyright (c) 2021, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2022, Linaro Limited 4 * Copyright (c) 2022, Linaro Limited
5 */ 5 */
6 6
7 #include <dt-bindings/clock/qcom,dispcc-sc8280 7 #include <dt-bindings/clock/qcom,dispcc-sc8280xp.h>
8 #include <dt-bindings/clock/qcom,gcc-sc8280xp. 8 #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
9 #include <dt-bindings/clock/qcom,gpucc-sc8280x 9 #include <dt-bindings/clock/qcom,gpucc-sc8280xp.h>
10 #include <dt-bindings/clock/qcom,rpmh.h> 10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/clock/qcom,sc8280xp-camc <<
12 #include <dt-bindings/clock/qcom,sc8280xp-lpas 11 #include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>
13 #include <dt-bindings/interconnect/qcom,osm-l3 12 #include <dt-bindings/interconnect/qcom,osm-l3.h>
14 #include <dt-bindings/interconnect/qcom,sc8280 13 #include <dt-bindings/interconnect/qcom,sc8280xp.h>
15 #include <dt-bindings/interrupt-controller/arm 14 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/mailbox/qcom-ipcc.h> 15 #include <dt-bindings/mailbox/qcom-ipcc.h>
17 #include <dt-bindings/phy/phy-qcom-qmp.h> 16 #include <dt-bindings/phy/phy-qcom-qmp.h>
18 #include <dt-bindings/power/qcom-rpmpd.h> 17 #include <dt-bindings/power/qcom-rpmpd.h>
19 #include <dt-bindings/soc/qcom,gpr.h> 18 #include <dt-bindings/soc/qcom,gpr.h>
20 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 19 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
21 #include <dt-bindings/sound/qcom,q6afe.h> 20 #include <dt-bindings/sound/qcom,q6afe.h>
22 #include <dt-bindings/thermal/thermal.h> 21 #include <dt-bindings/thermal/thermal.h>
23 22
24 / { 23 / {
25 interrupt-parent = <&intc>; 24 interrupt-parent = <&intc>;
26 25
27 #address-cells = <2>; 26 #address-cells = <2>;
28 #size-cells = <2>; 27 #size-cells = <2>;
29 28
30 clocks { 29 clocks {
31 xo_board_clk: xo-board-clk { 30 xo_board_clk: xo-board-clk {
32 compatible = "fixed-cl 31 compatible = "fixed-clock";
33 #clock-cells = <0>; 32 #clock-cells = <0>;
34 }; 33 };
35 34
36 sleep_clk: sleep-clk { 35 sleep_clk: sleep-clk {
37 compatible = "fixed-cl 36 compatible = "fixed-clock";
38 #clock-cells = <0>; 37 #clock-cells = <0>;
39 clock-frequency = <327 38 clock-frequency = <32764>;
40 }; 39 };
41 }; 40 };
42 41
43 cpus { 42 cpus {
44 #address-cells = <2>; 43 #address-cells = <2>;
45 #size-cells = <0>; 44 #size-cells = <0>;
46 45
47 CPU0: cpu@0 { 46 CPU0: cpu@0 {
48 device_type = "cpu"; 47 device_type = "cpu";
49 compatible = "arm,cort 48 compatible = "arm,cortex-a78c";
50 reg = <0x0 0x0>; 49 reg = <0x0 0x0>;
51 clocks = <&cpufreq_hw 50 clocks = <&cpufreq_hw 0>;
52 enable-method = "psci" 51 enable-method = "psci";
53 capacity-dmips-mhz = < !! 52 capacity-dmips-mhz = <602>;
54 dynamic-power-coeffici <<
55 next-level-cache = <&L 53 next-level-cache = <&L2_0>;
56 power-domains = <&CPU_ 54 power-domains = <&CPU_PD0>;
57 power-domain-names = " 55 power-domain-names = "psci";
58 qcom,freq-domain = <&c 56 qcom,freq-domain = <&cpufreq_hw 0>;
59 operating-points-v2 = 57 operating-points-v2 = <&cpu0_opp_table>;
60 interconnects = <&epss 58 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
61 #cooling-cells = <2>; 59 #cooling-cells = <2>;
62 L2_0: l2-cache { 60 L2_0: l2-cache {
63 compatible = " 61 compatible = "cache";
64 cache-level = 62 cache-level = <2>;
65 cache-unified; 63 cache-unified;
66 next-level-cac 64 next-level-cache = <&L3_0>;
67 L3_0: l3-cache 65 L3_0: l3-cache {
68 compat 66 compatible = "cache";
69 cache- 67 cache-level = <3>;
70 cache- 68 cache-unified;
71 }; 69 };
72 }; 70 };
73 }; 71 };
74 72
75 CPU1: cpu@100 { 73 CPU1: cpu@100 {
76 device_type = "cpu"; 74 device_type = "cpu";
77 compatible = "arm,cort 75 compatible = "arm,cortex-a78c";
78 reg = <0x0 0x100>; 76 reg = <0x0 0x100>;
79 clocks = <&cpufreq_hw 77 clocks = <&cpufreq_hw 0>;
80 enable-method = "psci" 78 enable-method = "psci";
81 capacity-dmips-mhz = < !! 79 capacity-dmips-mhz = <602>;
82 dynamic-power-coeffici <<
83 next-level-cache = <&L 80 next-level-cache = <&L2_100>;
84 power-domains = <&CPU_ 81 power-domains = <&CPU_PD1>;
85 power-domain-names = " 82 power-domain-names = "psci";
86 qcom,freq-domain = <&c 83 qcom,freq-domain = <&cpufreq_hw 0>;
87 operating-points-v2 = 84 operating-points-v2 = <&cpu0_opp_table>;
88 interconnects = <&epss 85 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
89 #cooling-cells = <2>; 86 #cooling-cells = <2>;
90 L2_100: l2-cache { 87 L2_100: l2-cache {
91 compatible = " 88 compatible = "cache";
92 cache-level = 89 cache-level = <2>;
93 cache-unified; 90 cache-unified;
94 next-level-cac 91 next-level-cache = <&L3_0>;
95 }; 92 };
96 }; 93 };
97 94
98 CPU2: cpu@200 { 95 CPU2: cpu@200 {
99 device_type = "cpu"; 96 device_type = "cpu";
100 compatible = "arm,cort 97 compatible = "arm,cortex-a78c";
101 reg = <0x0 0x200>; 98 reg = <0x0 0x200>;
102 clocks = <&cpufreq_hw 99 clocks = <&cpufreq_hw 0>;
103 enable-method = "psci" 100 enable-method = "psci";
104 capacity-dmips-mhz = < !! 101 capacity-dmips-mhz = <602>;
105 dynamic-power-coeffici <<
106 next-level-cache = <&L 102 next-level-cache = <&L2_200>;
107 power-domains = <&CPU_ 103 power-domains = <&CPU_PD2>;
108 power-domain-names = " 104 power-domain-names = "psci";
109 qcom,freq-domain = <&c 105 qcom,freq-domain = <&cpufreq_hw 0>;
110 operating-points-v2 = 106 operating-points-v2 = <&cpu0_opp_table>;
111 interconnects = <&epss 107 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
112 #cooling-cells = <2>; 108 #cooling-cells = <2>;
113 L2_200: l2-cache { 109 L2_200: l2-cache {
114 compatible = " 110 compatible = "cache";
115 cache-level = 111 cache-level = <2>;
116 cache-unified; 112 cache-unified;
117 next-level-cac 113 next-level-cache = <&L3_0>;
118 }; 114 };
119 }; 115 };
120 116
121 CPU3: cpu@300 { 117 CPU3: cpu@300 {
122 device_type = "cpu"; 118 device_type = "cpu";
123 compatible = "arm,cort 119 compatible = "arm,cortex-a78c";
124 reg = <0x0 0x300>; 120 reg = <0x0 0x300>;
125 clocks = <&cpufreq_hw 121 clocks = <&cpufreq_hw 0>;
126 enable-method = "psci" 122 enable-method = "psci";
127 capacity-dmips-mhz = < !! 123 capacity-dmips-mhz = <602>;
128 dynamic-power-coeffici <<
129 next-level-cache = <&L 124 next-level-cache = <&L2_300>;
130 power-domains = <&CPU_ 125 power-domains = <&CPU_PD3>;
131 power-domain-names = " 126 power-domain-names = "psci";
132 qcom,freq-domain = <&c 127 qcom,freq-domain = <&cpufreq_hw 0>;
133 operating-points-v2 = 128 operating-points-v2 = <&cpu0_opp_table>;
134 interconnects = <&epss 129 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
135 #cooling-cells = <2>; 130 #cooling-cells = <2>;
136 L2_300: l2-cache { 131 L2_300: l2-cache {
137 compatible = " 132 compatible = "cache";
138 cache-level = 133 cache-level = <2>;
139 cache-unified; 134 cache-unified;
140 next-level-cac 135 next-level-cache = <&L3_0>;
141 }; 136 };
142 }; 137 };
143 138
144 CPU4: cpu@400 { 139 CPU4: cpu@400 {
145 device_type = "cpu"; 140 device_type = "cpu";
146 compatible = "arm,cort 141 compatible = "arm,cortex-x1c";
147 reg = <0x0 0x400>; 142 reg = <0x0 0x400>;
148 clocks = <&cpufreq_hw 143 clocks = <&cpufreq_hw 1>;
149 enable-method = "psci" 144 enable-method = "psci";
150 capacity-dmips-mhz = < 145 capacity-dmips-mhz = <1024>;
151 dynamic-power-coeffici <<
152 next-level-cache = <&L 146 next-level-cache = <&L2_400>;
153 power-domains = <&CPU_ 147 power-domains = <&CPU_PD4>;
154 power-domain-names = " 148 power-domain-names = "psci";
155 qcom,freq-domain = <&c 149 qcom,freq-domain = <&cpufreq_hw 1>;
156 operating-points-v2 = 150 operating-points-v2 = <&cpu4_opp_table>;
157 interconnects = <&epss 151 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
158 #cooling-cells = <2>; 152 #cooling-cells = <2>;
159 L2_400: l2-cache { 153 L2_400: l2-cache {
160 compatible = " 154 compatible = "cache";
161 cache-level = 155 cache-level = <2>;
162 cache-unified; 156 cache-unified;
163 next-level-cac 157 next-level-cache = <&L3_0>;
164 }; 158 };
165 }; 159 };
166 160
167 CPU5: cpu@500 { 161 CPU5: cpu@500 {
168 device_type = "cpu"; 162 device_type = "cpu";
169 compatible = "arm,cort 163 compatible = "arm,cortex-x1c";
170 reg = <0x0 0x500>; 164 reg = <0x0 0x500>;
171 clocks = <&cpufreq_hw 165 clocks = <&cpufreq_hw 1>;
172 enable-method = "psci" 166 enable-method = "psci";
173 capacity-dmips-mhz = < 167 capacity-dmips-mhz = <1024>;
174 dynamic-power-coeffici <<
175 next-level-cache = <&L 168 next-level-cache = <&L2_500>;
176 power-domains = <&CPU_ 169 power-domains = <&CPU_PD5>;
177 power-domain-names = " 170 power-domain-names = "psci";
178 qcom,freq-domain = <&c 171 qcom,freq-domain = <&cpufreq_hw 1>;
179 operating-points-v2 = 172 operating-points-v2 = <&cpu4_opp_table>;
180 interconnects = <&epss 173 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
181 #cooling-cells = <2>; 174 #cooling-cells = <2>;
182 L2_500: l2-cache { 175 L2_500: l2-cache {
183 compatible = " 176 compatible = "cache";
184 cache-level = 177 cache-level = <2>;
185 cache-unified; 178 cache-unified;
186 next-level-cac 179 next-level-cache = <&L3_0>;
187 }; 180 };
188 }; 181 };
189 182
190 CPU6: cpu@600 { 183 CPU6: cpu@600 {
191 device_type = "cpu"; 184 device_type = "cpu";
192 compatible = "arm,cort 185 compatible = "arm,cortex-x1c";
193 reg = <0x0 0x600>; 186 reg = <0x0 0x600>;
194 clocks = <&cpufreq_hw 187 clocks = <&cpufreq_hw 1>;
195 enable-method = "psci" 188 enable-method = "psci";
196 capacity-dmips-mhz = < 189 capacity-dmips-mhz = <1024>;
197 dynamic-power-coeffici <<
198 next-level-cache = <&L 190 next-level-cache = <&L2_600>;
199 power-domains = <&CPU_ 191 power-domains = <&CPU_PD6>;
200 power-domain-names = " 192 power-domain-names = "psci";
201 qcom,freq-domain = <&c 193 qcom,freq-domain = <&cpufreq_hw 1>;
202 operating-points-v2 = 194 operating-points-v2 = <&cpu4_opp_table>;
203 interconnects = <&epss 195 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
204 #cooling-cells = <2>; 196 #cooling-cells = <2>;
205 L2_600: l2-cache { 197 L2_600: l2-cache {
206 compatible = " 198 compatible = "cache";
207 cache-level = 199 cache-level = <2>;
208 cache-unified; 200 cache-unified;
209 next-level-cac 201 next-level-cache = <&L3_0>;
210 }; 202 };
211 }; 203 };
212 204
213 CPU7: cpu@700 { 205 CPU7: cpu@700 {
214 device_type = "cpu"; 206 device_type = "cpu";
215 compatible = "arm,cort 207 compatible = "arm,cortex-x1c";
216 reg = <0x0 0x700>; 208 reg = <0x0 0x700>;
217 clocks = <&cpufreq_hw 209 clocks = <&cpufreq_hw 1>;
218 enable-method = "psci" 210 enable-method = "psci";
219 capacity-dmips-mhz = < 211 capacity-dmips-mhz = <1024>;
220 dynamic-power-coeffici <<
221 next-level-cache = <&L 212 next-level-cache = <&L2_700>;
222 power-domains = <&CPU_ 213 power-domains = <&CPU_PD7>;
223 power-domain-names = " 214 power-domain-names = "psci";
224 qcom,freq-domain = <&c 215 qcom,freq-domain = <&cpufreq_hw 1>;
225 operating-points-v2 = 216 operating-points-v2 = <&cpu4_opp_table>;
226 interconnects = <&epss 217 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
227 #cooling-cells = <2>; 218 #cooling-cells = <2>;
228 L2_700: l2-cache { 219 L2_700: l2-cache {
229 compatible = " 220 compatible = "cache";
230 cache-level = 221 cache-level = <2>;
231 cache-unified; 222 cache-unified;
232 next-level-cac 223 next-level-cache = <&L3_0>;
233 }; 224 };
234 }; 225 };
235 226
236 cpu-map { 227 cpu-map {
237 cluster0 { 228 cluster0 {
238 core0 { 229 core0 {
239 cpu = 230 cpu = <&CPU0>;
240 }; 231 };
241 232
242 core1 { 233 core1 {
243 cpu = 234 cpu = <&CPU1>;
244 }; 235 };
245 236
246 core2 { 237 core2 {
247 cpu = 238 cpu = <&CPU2>;
248 }; 239 };
249 240
250 core3 { 241 core3 {
251 cpu = 242 cpu = <&CPU3>;
252 }; 243 };
253 244
254 core4 { 245 core4 {
255 cpu = 246 cpu = <&CPU4>;
256 }; 247 };
257 248
258 core5 { 249 core5 {
259 cpu = 250 cpu = <&CPU5>;
260 }; 251 };
261 252
262 core6 { 253 core6 {
263 cpu = 254 cpu = <&CPU6>;
264 }; 255 };
265 256
266 core7 { 257 core7 {
267 cpu = 258 cpu = <&CPU7>;
268 }; 259 };
269 }; 260 };
270 }; 261 };
271 262
272 idle-states { 263 idle-states {
273 entry-method = "psci"; 264 entry-method = "psci";
274 265
275 LITTLE_CPU_SLEEP_0: cp 266 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
276 compatible = " 267 compatible = "arm,idle-state";
277 idle-state-nam 268 idle-state-name = "little-rail-power-collapse";
278 arm,psci-suspe 269 arm,psci-suspend-param = <0x40000004>;
279 entry-latency- 270 entry-latency-us = <355>;
280 exit-latency-u 271 exit-latency-us = <909>;
281 min-residency- 272 min-residency-us = <3934>;
282 local-timer-st 273 local-timer-stop;
283 }; 274 };
284 275
285 BIG_CPU_SLEEP_0: cpu-s 276 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
286 compatible = " 277 compatible = "arm,idle-state";
287 idle-state-nam 278 idle-state-name = "big-rail-power-collapse";
288 arm,psci-suspe 279 arm,psci-suspend-param = <0x40000004>;
289 entry-latency- 280 entry-latency-us = <241>;
290 exit-latency-u 281 exit-latency-us = <1461>;
291 min-residency- 282 min-residency-us = <4488>;
292 local-timer-st 283 local-timer-stop;
293 }; 284 };
294 }; 285 };
295 286
296 domain-idle-states { 287 domain-idle-states {
297 CLUSTER_SLEEP_0: clust 288 CLUSTER_SLEEP_0: cluster-sleep-0 {
298 compatible = " 289 compatible = "domain-idle-state";
299 arm,psci-suspe 290 arm,psci-suspend-param = <0x4100c344>;
300 entry-latency- 291 entry-latency-us = <3263>;
301 exit-latency-u 292 exit-latency-us = <6562>;
302 min-residency- 293 min-residency-us = <9987>;
303 }; 294 };
304 }; 295 };
305 }; 296 };
306 297
307 firmware { 298 firmware {
308 scm: scm { 299 scm: scm {
309 compatible = "qcom,scm 300 compatible = "qcom,scm-sc8280xp", "qcom,scm";
310 interconnects = <&aggr 301 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
311 qcom,dload-mode = <&tc <<
312 }; 302 };
313 }; 303 };
314 304
315 aggre1_noc: interconnect-aggre1-noc { 305 aggre1_noc: interconnect-aggre1-noc {
316 compatible = "qcom,sc8280xp-ag 306 compatible = "qcom,sc8280xp-aggre1-noc";
317 #interconnect-cells = <2>; 307 #interconnect-cells = <2>;
318 qcom,bcm-voters = <&apps_bcm_v 308 qcom,bcm-voters = <&apps_bcm_voter>;
319 }; 309 };
320 310
321 aggre2_noc: interconnect-aggre2-noc { 311 aggre2_noc: interconnect-aggre2-noc {
322 compatible = "qcom,sc8280xp-ag 312 compatible = "qcom,sc8280xp-aggre2-noc";
323 #interconnect-cells = <2>; 313 #interconnect-cells = <2>;
324 qcom,bcm-voters = <&apps_bcm_v 314 qcom,bcm-voters = <&apps_bcm_voter>;
325 }; 315 };
326 316
327 clk_virt: interconnect-clk-virt { 317 clk_virt: interconnect-clk-virt {
328 compatible = "qcom,sc8280xp-cl 318 compatible = "qcom,sc8280xp-clk-virt";
329 #interconnect-cells = <2>; 319 #interconnect-cells = <2>;
330 qcom,bcm-voters = <&apps_bcm_v 320 qcom,bcm-voters = <&apps_bcm_voter>;
331 }; 321 };
332 322
333 config_noc: interconnect-config-noc { 323 config_noc: interconnect-config-noc {
334 compatible = "qcom,sc8280xp-co 324 compatible = "qcom,sc8280xp-config-noc";
335 #interconnect-cells = <2>; 325 #interconnect-cells = <2>;
336 qcom,bcm-voters = <&apps_bcm_v 326 qcom,bcm-voters = <&apps_bcm_voter>;
337 }; 327 };
338 328
339 dc_noc: interconnect-dc-noc { 329 dc_noc: interconnect-dc-noc {
340 compatible = "qcom,sc8280xp-dc 330 compatible = "qcom,sc8280xp-dc-noc";
341 #interconnect-cells = <2>; 331 #interconnect-cells = <2>;
342 qcom,bcm-voters = <&apps_bcm_v 332 qcom,bcm-voters = <&apps_bcm_voter>;
343 }; 333 };
344 334
345 gem_noc: interconnect-gem-noc { 335 gem_noc: interconnect-gem-noc {
346 compatible = "qcom,sc8280xp-ge 336 compatible = "qcom,sc8280xp-gem-noc";
347 #interconnect-cells = <2>; 337 #interconnect-cells = <2>;
348 qcom,bcm-voters = <&apps_bcm_v 338 qcom,bcm-voters = <&apps_bcm_voter>;
349 }; 339 };
350 340
351 lpass_noc: interconnect-lpass-ag-noc { 341 lpass_noc: interconnect-lpass-ag-noc {
352 compatible = "qcom,sc8280xp-lp 342 compatible = "qcom,sc8280xp-lpass-ag-noc";
353 #interconnect-cells = <2>; 343 #interconnect-cells = <2>;
354 qcom,bcm-voters = <&apps_bcm_v 344 qcom,bcm-voters = <&apps_bcm_voter>;
355 }; 345 };
356 346
357 mc_virt: interconnect-mc-virt { 347 mc_virt: interconnect-mc-virt {
358 compatible = "qcom,sc8280xp-mc 348 compatible = "qcom,sc8280xp-mc-virt";
359 #interconnect-cells = <2>; 349 #interconnect-cells = <2>;
360 qcom,bcm-voters = <&apps_bcm_v 350 qcom,bcm-voters = <&apps_bcm_voter>;
361 }; 351 };
362 352
363 mmss_noc: interconnect-mmss-noc { 353 mmss_noc: interconnect-mmss-noc {
364 compatible = "qcom,sc8280xp-mm 354 compatible = "qcom,sc8280xp-mmss-noc";
365 #interconnect-cells = <2>; 355 #interconnect-cells = <2>;
366 qcom,bcm-voters = <&apps_bcm_v 356 qcom,bcm-voters = <&apps_bcm_voter>;
367 }; 357 };
368 358
369 nspa_noc: interconnect-nspa-noc { 359 nspa_noc: interconnect-nspa-noc {
370 compatible = "qcom,sc8280xp-ns 360 compatible = "qcom,sc8280xp-nspa-noc";
371 #interconnect-cells = <2>; 361 #interconnect-cells = <2>;
372 qcom,bcm-voters = <&apps_bcm_v 362 qcom,bcm-voters = <&apps_bcm_voter>;
373 }; 363 };
374 364
375 nspb_noc: interconnect-nspb-noc { 365 nspb_noc: interconnect-nspb-noc {
376 compatible = "qcom,sc8280xp-ns 366 compatible = "qcom,sc8280xp-nspb-noc";
377 #interconnect-cells = <2>; 367 #interconnect-cells = <2>;
378 qcom,bcm-voters = <&apps_bcm_v 368 qcom,bcm-voters = <&apps_bcm_voter>;
379 }; 369 };
380 370
381 system_noc: interconnect-system-noc { 371 system_noc: interconnect-system-noc {
382 compatible = "qcom,sc8280xp-sy 372 compatible = "qcom,sc8280xp-system-noc";
383 #interconnect-cells = <2>; 373 #interconnect-cells = <2>;
384 qcom,bcm-voters = <&apps_bcm_v 374 qcom,bcm-voters = <&apps_bcm_voter>;
385 }; 375 };
386 376
387 memory@80000000 { 377 memory@80000000 {
388 device_type = "memory"; 378 device_type = "memory";
389 /* We expect the bootloader to 379 /* We expect the bootloader to fill in the size */
390 reg = <0x0 0x80000000 0x0 0x0> 380 reg = <0x0 0x80000000 0x0 0x0>;
391 }; 381 };
392 382
393 cpu0_opp_table: opp-table-cpu0 { 383 cpu0_opp_table: opp-table-cpu0 {
394 compatible = "operating-points 384 compatible = "operating-points-v2";
395 opp-shared; 385 opp-shared;
396 386
397 opp-300000000 { 387 opp-300000000 {
398 opp-hz = /bits/ 64 <30 388 opp-hz = /bits/ 64 <300000000>;
399 opp-peak-kBps = <(3000 389 opp-peak-kBps = <(300000 * 32)>;
400 }; 390 };
401 opp-403200000 { 391 opp-403200000 {
402 opp-hz = /bits/ 64 <40 392 opp-hz = /bits/ 64 <403200000>;
403 opp-peak-kBps = <(3840 393 opp-peak-kBps = <(384000 * 32)>;
404 }; 394 };
405 opp-499200000 { 395 opp-499200000 {
406 opp-hz = /bits/ 64 <49 396 opp-hz = /bits/ 64 <499200000>;
407 opp-peak-kBps = <(4800 397 opp-peak-kBps = <(480000 * 32)>;
408 }; 398 };
409 opp-595200000 { 399 opp-595200000 {
410 opp-hz = /bits/ 64 <59 400 opp-hz = /bits/ 64 <595200000>;
411 opp-peak-kBps = <(5760 401 opp-peak-kBps = <(576000 * 32)>;
412 }; 402 };
413 opp-691200000 { 403 opp-691200000 {
414 opp-hz = /bits/ 64 <69 404 opp-hz = /bits/ 64 <691200000>;
415 opp-peak-kBps = <(6720 405 opp-peak-kBps = <(672000 * 32)>;
416 }; 406 };
417 opp-806400000 { 407 opp-806400000 {
418 opp-hz = /bits/ 64 <80 408 opp-hz = /bits/ 64 <806400000>;
419 opp-peak-kBps = <(7680 409 opp-peak-kBps = <(768000 * 32)>;
420 }; 410 };
421 opp-902400000 { 411 opp-902400000 {
422 opp-hz = /bits/ 64 <90 412 opp-hz = /bits/ 64 <902400000>;
423 opp-peak-kBps = <(8640 413 opp-peak-kBps = <(864000 * 32)>;
424 }; 414 };
425 opp-1017600000 { 415 opp-1017600000 {
426 opp-hz = /bits/ 64 <10 416 opp-hz = /bits/ 64 <1017600000>;
427 opp-peak-kBps = <(9600 417 opp-peak-kBps = <(960000 * 32)>;
428 }; 418 };
429 opp-1113600000 { 419 opp-1113600000 {
430 opp-hz = /bits/ 64 <11 420 opp-hz = /bits/ 64 <1113600000>;
431 opp-peak-kBps = <(1075 421 opp-peak-kBps = <(1075200 * 32)>;
432 }; 422 };
433 opp-1209600000 { 423 opp-1209600000 {
434 opp-hz = /bits/ 64 <12 424 opp-hz = /bits/ 64 <1209600000>;
435 opp-peak-kBps = <(1171 425 opp-peak-kBps = <(1171200 * 32)>;
436 }; 426 };
437 opp-1324800000 { 427 opp-1324800000 {
438 opp-hz = /bits/ 64 <13 428 opp-hz = /bits/ 64 <1324800000>;
439 opp-peak-kBps = <(1267 429 opp-peak-kBps = <(1267200 * 32)>;
440 }; 430 };
441 opp-1440000000 { 431 opp-1440000000 {
442 opp-hz = /bits/ 64 <14 432 opp-hz = /bits/ 64 <1440000000>;
443 opp-peak-kBps = <(1363 433 opp-peak-kBps = <(1363200 * 32)>;
444 }; 434 };
445 opp-1555200000 { 435 opp-1555200000 {
446 opp-hz = /bits/ 64 <15 436 opp-hz = /bits/ 64 <1555200000>;
447 opp-peak-kBps = <(1536 437 opp-peak-kBps = <(1536000 * 32)>;
448 }; 438 };
449 opp-1670400000 { 439 opp-1670400000 {
450 opp-hz = /bits/ 64 <16 440 opp-hz = /bits/ 64 <1670400000>;
451 opp-peak-kBps = <(1612 441 opp-peak-kBps = <(1612800 * 32)>;
452 }; 442 };
453 opp-1785600000 { 443 opp-1785600000 {
454 opp-hz = /bits/ 64 <17 444 opp-hz = /bits/ 64 <1785600000>;
455 opp-peak-kBps = <(1689 445 opp-peak-kBps = <(1689600 * 32)>;
456 }; 446 };
457 opp-1881600000 { 447 opp-1881600000 {
458 opp-hz = /bits/ 64 <18 448 opp-hz = /bits/ 64 <1881600000>;
459 opp-peak-kBps = <(1689 449 opp-peak-kBps = <(1689600 * 32)>;
460 }; 450 };
461 opp-1996800000 { 451 opp-1996800000 {
462 opp-hz = /bits/ 64 <19 452 opp-hz = /bits/ 64 <1996800000>;
463 opp-peak-kBps = <(1689 453 opp-peak-kBps = <(1689600 * 32)>;
464 }; 454 };
465 opp-2112000000 { 455 opp-2112000000 {
466 opp-hz = /bits/ 64 <21 456 opp-hz = /bits/ 64 <2112000000>;
467 opp-peak-kBps = <(1689 457 opp-peak-kBps = <(1689600 * 32)>;
468 }; 458 };
469 opp-2227200000 { 459 opp-2227200000 {
470 opp-hz = /bits/ 64 <22 460 opp-hz = /bits/ 64 <2227200000>;
471 opp-peak-kBps = <(1689 461 opp-peak-kBps = <(1689600 * 32)>;
472 }; 462 };
473 opp-2342400000 { 463 opp-2342400000 {
474 opp-hz = /bits/ 64 <23 464 opp-hz = /bits/ 64 <2342400000>;
475 opp-peak-kBps = <(1689 465 opp-peak-kBps = <(1689600 * 32)>;
476 }; 466 };
477 opp-2438400000 { 467 opp-2438400000 {
478 opp-hz = /bits/ 64 <24 468 opp-hz = /bits/ 64 <2438400000>;
479 opp-peak-kBps = <(1689 469 opp-peak-kBps = <(1689600 * 32)>;
480 }; 470 };
481 }; 471 };
482 472
483 cpu4_opp_table: opp-table-cpu4 { 473 cpu4_opp_table: opp-table-cpu4 {
484 compatible = "operating-points 474 compatible = "operating-points-v2";
485 opp-shared; 475 opp-shared;
486 476
487 opp-825600000 { 477 opp-825600000 {
488 opp-hz = /bits/ 64 <82 478 opp-hz = /bits/ 64 <825600000>;
489 opp-peak-kBps = <(7680 479 opp-peak-kBps = <(768000 * 32)>;
490 }; 480 };
491 opp-940800000 { 481 opp-940800000 {
492 opp-hz = /bits/ 64 <94 482 opp-hz = /bits/ 64 <940800000>;
493 opp-peak-kBps = <(8640 483 opp-peak-kBps = <(864000 * 32)>;
494 }; 484 };
495 opp-1056000000 { 485 opp-1056000000 {
496 opp-hz = /bits/ 64 <10 486 opp-hz = /bits/ 64 <1056000000>;
497 opp-peak-kBps = <(9600 487 opp-peak-kBps = <(960000 * 32)>;
498 }; 488 };
499 opp-1171200000 { 489 opp-1171200000 {
500 opp-hz = /bits/ 64 <11 490 opp-hz = /bits/ 64 <1171200000>;
501 opp-peak-kBps = <(1171 491 opp-peak-kBps = <(1171200 * 32)>;
502 }; 492 };
503 opp-1286400000 { 493 opp-1286400000 {
504 opp-hz = /bits/ 64 <12 494 opp-hz = /bits/ 64 <1286400000>;
505 opp-peak-kBps = <(1267 495 opp-peak-kBps = <(1267200 * 32)>;
506 }; 496 };
507 opp-1401600000 { 497 opp-1401600000 {
508 opp-hz = /bits/ 64 <14 498 opp-hz = /bits/ 64 <1401600000>;
509 opp-peak-kBps = <(1363 499 opp-peak-kBps = <(1363200 * 32)>;
510 }; 500 };
511 opp-1516800000 { 501 opp-1516800000 {
512 opp-hz = /bits/ 64 <15 502 opp-hz = /bits/ 64 <1516800000>;
513 opp-peak-kBps = <(1459 503 opp-peak-kBps = <(1459200 * 32)>;
514 }; 504 };
515 opp-1632000000 { 505 opp-1632000000 {
516 opp-hz = /bits/ 64 <16 506 opp-hz = /bits/ 64 <1632000000>;
517 opp-peak-kBps = <(1612 507 opp-peak-kBps = <(1612800 * 32)>;
518 }; 508 };
519 opp-1747200000 { 509 opp-1747200000 {
520 opp-hz = /bits/ 64 <17 510 opp-hz = /bits/ 64 <1747200000>;
521 opp-peak-kBps = <(1689 511 opp-peak-kBps = <(1689600 * 32)>;
522 }; 512 };
523 opp-1862400000 { 513 opp-1862400000 {
524 opp-hz = /bits/ 64 <18 514 opp-hz = /bits/ 64 <1862400000>;
525 opp-peak-kBps = <(1689 515 opp-peak-kBps = <(1689600 * 32)>;
526 }; 516 };
527 opp-1977600000 { 517 opp-1977600000 {
528 opp-hz = /bits/ 64 <19 518 opp-hz = /bits/ 64 <1977600000>;
529 opp-peak-kBps = <(1689 519 opp-peak-kBps = <(1689600 * 32)>;
530 }; 520 };
531 opp-2073600000 { 521 opp-2073600000 {
532 opp-hz = /bits/ 64 <20 522 opp-hz = /bits/ 64 <2073600000>;
533 opp-peak-kBps = <(1689 523 opp-peak-kBps = <(1689600 * 32)>;
534 }; 524 };
535 opp-2169600000 { 525 opp-2169600000 {
536 opp-hz = /bits/ 64 <21 526 opp-hz = /bits/ 64 <2169600000>;
537 opp-peak-kBps = <(1689 527 opp-peak-kBps = <(1689600 * 32)>;
538 }; 528 };
539 opp-2284800000 { 529 opp-2284800000 {
540 opp-hz = /bits/ 64 <22 530 opp-hz = /bits/ 64 <2284800000>;
541 opp-peak-kBps = <(1689 531 opp-peak-kBps = <(1689600 * 32)>;
542 }; 532 };
543 opp-2400000000 { 533 opp-2400000000 {
544 opp-hz = /bits/ 64 <24 534 opp-hz = /bits/ 64 <2400000000>;
545 opp-peak-kBps = <(1689 535 opp-peak-kBps = <(1689600 * 32)>;
546 }; 536 };
547 opp-2496000000 { 537 opp-2496000000 {
548 opp-hz = /bits/ 64 <24 538 opp-hz = /bits/ 64 <2496000000>;
549 opp-peak-kBps = <(1689 539 opp-peak-kBps = <(1689600 * 32)>;
550 }; 540 };
551 opp-2592000000 { 541 opp-2592000000 {
552 opp-hz = /bits/ 64 <25 542 opp-hz = /bits/ 64 <2592000000>;
553 opp-peak-kBps = <(1689 543 opp-peak-kBps = <(1689600 * 32)>;
554 }; 544 };
555 opp-2688000000 { 545 opp-2688000000 {
556 opp-hz = /bits/ 64 <26 546 opp-hz = /bits/ 64 <2688000000>;
557 opp-peak-kBps = <(1689 547 opp-peak-kBps = <(1689600 * 32)>;
558 }; 548 };
559 opp-2803200000 { 549 opp-2803200000 {
560 opp-hz = /bits/ 64 <28 550 opp-hz = /bits/ 64 <2803200000>;
561 opp-peak-kBps = <(1689 551 opp-peak-kBps = <(1689600 * 32)>;
562 }; 552 };
563 opp-2899200000 { 553 opp-2899200000 {
564 opp-hz = /bits/ 64 <28 554 opp-hz = /bits/ 64 <2899200000>;
565 opp-peak-kBps = <(1689 555 opp-peak-kBps = <(1689600 * 32)>;
566 }; 556 };
567 opp-2995200000 { 557 opp-2995200000 {
568 opp-hz = /bits/ 64 <29 558 opp-hz = /bits/ 64 <2995200000>;
569 opp-peak-kBps = <(1689 559 opp-peak-kBps = <(1689600 * 32)>;
570 }; 560 };
571 }; 561 };
572 562
573 qup_opp_table_100mhz: opp-table-qup100 563 qup_opp_table_100mhz: opp-table-qup100mhz {
574 compatible = "operating-points 564 compatible = "operating-points-v2";
575 565
576 opp-75000000 { 566 opp-75000000 {
577 opp-hz = /bits/ 64 <75 567 opp-hz = /bits/ 64 <75000000>;
578 required-opps = <&rpmh 568 required-opps = <&rpmhpd_opp_low_svs>;
579 }; 569 };
580 570
581 opp-100000000 { 571 opp-100000000 {
582 opp-hz = /bits/ 64 <10 572 opp-hz = /bits/ 64 <100000000>;
583 required-opps = <&rpmh 573 required-opps = <&rpmhpd_opp_svs>;
584 }; 574 };
585 }; 575 };
586 576
587 pmu { 577 pmu {
588 compatible = "arm,armv8-pmuv3" 578 compatible = "arm,armv8-pmuv3";
589 interrupts = <GIC_PPI 7 IRQ_TY 579 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
590 }; 580 };
591 581
592 psci { 582 psci {
593 compatible = "arm,psci-1.0"; 583 compatible = "arm,psci-1.0";
594 method = "smc"; 584 method = "smc";
595 585
596 CPU_PD0: power-domain-cpu0 { 586 CPU_PD0: power-domain-cpu0 {
597 #power-domain-cells = 587 #power-domain-cells = <0>;
598 power-domains = <&CLUS 588 power-domains = <&CLUSTER_PD>;
599 domain-idle-states = < 589 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
600 }; 590 };
601 591
602 CPU_PD1: power-domain-cpu1 { 592 CPU_PD1: power-domain-cpu1 {
603 #power-domain-cells = 593 #power-domain-cells = <0>;
604 power-domains = <&CLUS 594 power-domains = <&CLUSTER_PD>;
605 domain-idle-states = < 595 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
606 }; 596 };
607 597
608 CPU_PD2: power-domain-cpu2 { 598 CPU_PD2: power-domain-cpu2 {
609 #power-domain-cells = 599 #power-domain-cells = <0>;
610 power-domains = <&CLUS 600 power-domains = <&CLUSTER_PD>;
611 domain-idle-states = < 601 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
612 }; 602 };
613 603
614 CPU_PD3: power-domain-cpu3 { 604 CPU_PD3: power-domain-cpu3 {
615 #power-domain-cells = 605 #power-domain-cells = <0>;
616 power-domains = <&CLUS 606 power-domains = <&CLUSTER_PD>;
617 domain-idle-states = < 607 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
618 }; 608 };
619 609
620 CPU_PD4: power-domain-cpu4 { 610 CPU_PD4: power-domain-cpu4 {
621 #power-domain-cells = 611 #power-domain-cells = <0>;
622 power-domains = <&CLUS 612 power-domains = <&CLUSTER_PD>;
623 domain-idle-states = < 613 domain-idle-states = <&BIG_CPU_SLEEP_0>;
624 }; 614 };
625 615
626 CPU_PD5: power-domain-cpu5 { 616 CPU_PD5: power-domain-cpu5 {
627 #power-domain-cells = 617 #power-domain-cells = <0>;
628 power-domains = <&CLUS 618 power-domains = <&CLUSTER_PD>;
629 domain-idle-states = < 619 domain-idle-states = <&BIG_CPU_SLEEP_0>;
630 }; 620 };
631 621
632 CPU_PD6: power-domain-cpu6 { 622 CPU_PD6: power-domain-cpu6 {
633 #power-domain-cells = 623 #power-domain-cells = <0>;
634 power-domains = <&CLUS 624 power-domains = <&CLUSTER_PD>;
635 domain-idle-states = < 625 domain-idle-states = <&BIG_CPU_SLEEP_0>;
636 }; 626 };
637 627
638 CPU_PD7: power-domain-cpu7 { 628 CPU_PD7: power-domain-cpu7 {
639 #power-domain-cells = 629 #power-domain-cells = <0>;
640 power-domains = <&CLUS 630 power-domains = <&CLUSTER_PD>;
641 domain-idle-states = < 631 domain-idle-states = <&BIG_CPU_SLEEP_0>;
642 }; 632 };
643 633
644 CLUSTER_PD: power-domain-cpu-c 634 CLUSTER_PD: power-domain-cpu-cluster0 {
645 #power-domain-cells = 635 #power-domain-cells = <0>;
646 domain-idle-states = < 636 domain-idle-states = <&CLUSTER_SLEEP_0>;
647 }; 637 };
648 }; 638 };
649 639
650 reserved-memory { 640 reserved-memory {
651 #address-cells = <2>; 641 #address-cells = <2>;
652 #size-cells = <2>; 642 #size-cells = <2>;
653 ranges; 643 ranges;
654 644
655 reserved-region@80000000 { 645 reserved-region@80000000 {
656 reg = <0 0x80000000 0 646 reg = <0 0x80000000 0 0x860000>;
657 no-map; 647 no-map;
658 }; 648 };
659 649
660 cmd_db: cmd-db-region@80860000 650 cmd_db: cmd-db-region@80860000 {
661 compatible = "qcom,cmd 651 compatible = "qcom,cmd-db";
662 reg = <0 0x80860000 0 652 reg = <0 0x80860000 0 0x20000>;
663 no-map; 653 no-map;
664 }; 654 };
665 655
666 reserved-region@80880000 { 656 reserved-region@80880000 {
667 reg = <0 0x80880000 0 657 reg = <0 0x80880000 0 0x80000>;
668 no-map; 658 no-map;
669 }; 659 };
670 660
671 smem_mem: smem-region@80900000 661 smem_mem: smem-region@80900000 {
672 compatible = "qcom,sme 662 compatible = "qcom,smem";
673 reg = <0 0x80900000 0 663 reg = <0 0x80900000 0 0x200000>;
674 no-map; 664 no-map;
675 hwlocks = <&tcsr_mutex 665 hwlocks = <&tcsr_mutex 3>;
676 }; 666 };
677 667
678 reserved-region@80b00000 { 668 reserved-region@80b00000 {
679 reg = <0 0x80b00000 0 669 reg = <0 0x80b00000 0 0x100000>;
680 no-map; 670 no-map;
681 }; 671 };
682 672
683 reserved-region@83b00000 { 673 reserved-region@83b00000 {
684 reg = <0 0x83b00000 0 674 reg = <0 0x83b00000 0 0x1700000>;
685 no-map; 675 no-map;
686 }; 676 };
687 677
688 reserved-region@85b00000 { 678 reserved-region@85b00000 {
689 reg = <0 0x85b00000 0 679 reg = <0 0x85b00000 0 0xc00000>;
690 no-map; 680 no-map;
691 }; 681 };
692 682
693 pil_adsp_mem: adsp-region@86c0 683 pil_adsp_mem: adsp-region@86c00000 {
694 reg = <0 0x86c00000 0 684 reg = <0 0x86c00000 0 0x2000000>;
695 no-map; 685 no-map;
696 }; 686 };
697 687
698 pil_nsp0_mem: cdsp0-region@8a1 688 pil_nsp0_mem: cdsp0-region@8a100000 {
699 reg = <0 0x8a100000 0 689 reg = <0 0x8a100000 0 0x1e00000>;
700 no-map; 690 no-map;
701 }; 691 };
702 692
703 pil_nsp1_mem: cdsp1-region@8c6 693 pil_nsp1_mem: cdsp1-region@8c600000 {
704 reg = <0 0x8c600000 0 694 reg = <0 0x8c600000 0 0x1e00000>;
705 no-map; 695 no-map;
706 }; 696 };
707 697
708 reserved-region@aeb00000 { 698 reserved-region@aeb00000 {
709 reg = <0 0xaeb00000 0 699 reg = <0 0xaeb00000 0 0x16600000>;
710 no-map; 700 no-map;
711 }; 701 };
712 }; 702 };
713 703
714 smp2p-adsp { 704 smp2p-adsp {
715 compatible = "qcom,smp2p"; 705 compatible = "qcom,smp2p";
716 qcom,smem = <443>, <429>; 706 qcom,smem = <443>, <429>;
717 interrupts-extended = <&ipcc I 707 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
718 I 708 IPCC_MPROC_SIGNAL_SMP2P
719 I 709 IRQ_TYPE_EDGE_RISING>;
720 mboxes = <&ipcc IPCC_CLIENT_LP 710 mboxes = <&ipcc IPCC_CLIENT_LPASS
721 IPCC_MPROC_SIG 711 IPCC_MPROC_SIGNAL_SMP2P>;
722 712
723 qcom,local-pid = <0>; 713 qcom,local-pid = <0>;
724 qcom,remote-pid = <2>; 714 qcom,remote-pid = <2>;
725 715
726 smp2p_adsp_out: master-kernel 716 smp2p_adsp_out: master-kernel {
727 qcom,entry-name = "mas 717 qcom,entry-name = "master-kernel";
728 #qcom,smem-state-cells 718 #qcom,smem-state-cells = <1>;
729 }; 719 };
730 720
731 smp2p_adsp_in: slave-kernel { 721 smp2p_adsp_in: slave-kernel {
732 qcom,entry-name = "sla 722 qcom,entry-name = "slave-kernel";
733 interrupt-controller; 723 interrupt-controller;
734 #interrupt-cells = <2> 724 #interrupt-cells = <2>;
735 }; 725 };
736 }; 726 };
737 727
738 smp2p-nsp0 { 728 smp2p-nsp0 {
739 compatible = "qcom,smp2p"; 729 compatible = "qcom,smp2p";
740 qcom,smem = <94>, <432>; 730 qcom,smem = <94>, <432>;
741 interrupts-extended = <&ipcc I 731 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
742 I 732 IPCC_MPROC_SIGNAL_SMP2P
743 I 733 IRQ_TYPE_EDGE_RISING>;
744 mboxes = <&ipcc IPCC_CLIENT_CD 734 mboxes = <&ipcc IPCC_CLIENT_CDSP
745 IPCC_MPROC_SIG 735 IPCC_MPROC_SIGNAL_SMP2P>;
746 736
747 qcom,local-pid = <0>; 737 qcom,local-pid = <0>;
748 qcom,remote-pid = <5>; 738 qcom,remote-pid = <5>;
749 739
750 smp2p_nsp0_out: master-kernel 740 smp2p_nsp0_out: master-kernel {
751 qcom,entry-name = "mas 741 qcom,entry-name = "master-kernel";
752 #qcom,smem-state-cells 742 #qcom,smem-state-cells = <1>;
753 }; 743 };
754 744
755 smp2p_nsp0_in: slave-kernel { 745 smp2p_nsp0_in: slave-kernel {
756 qcom,entry-name = "sla 746 qcom,entry-name = "slave-kernel";
757 interrupt-controller; 747 interrupt-controller;
758 #interrupt-cells = <2> 748 #interrupt-cells = <2>;
759 }; 749 };
760 }; 750 };
761 751
762 smp2p-nsp1 { 752 smp2p-nsp1 {
763 compatible = "qcom,smp2p"; 753 compatible = "qcom,smp2p";
764 qcom,smem = <617>, <616>; 754 qcom,smem = <617>, <616>;
765 interrupts-extended = <&ipcc I 755 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1
766 I 756 IPCC_MPROC_SIGNAL_SMP2P
767 I 757 IRQ_TYPE_EDGE_RISING>;
768 mboxes = <&ipcc IPCC_CLIENT_NS 758 mboxes = <&ipcc IPCC_CLIENT_NSP1
769 IPCC_MPROC_SIG 759 IPCC_MPROC_SIGNAL_SMP2P>;
770 760
771 qcom,local-pid = <0>; 761 qcom,local-pid = <0>;
772 qcom,remote-pid = <12>; 762 qcom,remote-pid = <12>;
773 763
774 smp2p_nsp1_out: master-kernel 764 smp2p_nsp1_out: master-kernel {
775 qcom,entry-name = "mas 765 qcom,entry-name = "master-kernel";
776 #qcom,smem-state-cells 766 #qcom,smem-state-cells = <1>;
777 }; 767 };
778 768
779 smp2p_nsp1_in: slave-kernel { 769 smp2p_nsp1_in: slave-kernel {
780 qcom,entry-name = "sla 770 qcom,entry-name = "slave-kernel";
781 interrupt-controller; 771 interrupt-controller;
782 #interrupt-cells = <2> 772 #interrupt-cells = <2>;
783 }; 773 };
784 }; 774 };
785 775
786 soc: soc@0 { 776 soc: soc@0 {
787 compatible = "simple-bus"; 777 compatible = "simple-bus";
788 #address-cells = <2>; 778 #address-cells = <2>;
789 #size-cells = <2>; 779 #size-cells = <2>;
790 ranges = <0 0 0 0 0x10 0>; 780 ranges = <0 0 0 0 0x10 0>;
791 dma-ranges = <0 0 0 0 0x10 0>; 781 dma-ranges = <0 0 0 0 0x10 0>;
792 782
793 ethernet0: ethernet@20000 { 783 ethernet0: ethernet@20000 {
794 compatible = "qcom,sc8 784 compatible = "qcom,sc8280xp-ethqos";
795 reg = <0x0 0x00020000 785 reg = <0x0 0x00020000 0x0 0x10000>,
796 <0x0 0x00036000 786 <0x0 0x00036000 0x0 0x100>;
797 reg-names = "stmmaceth 787 reg-names = "stmmaceth", "rgmii";
798 788
799 clocks = <&gcc GCC_EMA 789 clocks = <&gcc GCC_EMAC0_AXI_CLK>,
800 <&gcc GCC_EMA 790 <&gcc GCC_EMAC0_SLV_AHB_CLK>,
801 <&gcc GCC_EMA 791 <&gcc GCC_EMAC0_PTP_CLK>,
802 <&gcc GCC_EMA 792 <&gcc GCC_EMAC0_RGMII_CLK>;
803 clock-names = "stmmace 793 clock-names = "stmmaceth",
804 "pclk", 794 "pclk",
805 "ptp_ref 795 "ptp_ref",
806 "rgmii"; 796 "rgmii";
807 797
808 interrupts = <GIC_SPI 798 interrupts = <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>,
809 <GIC_SPI 799 <GIC_SPI 936 IRQ_TYPE_LEVEL_HIGH>;
810 interrupt-names = "mac 800 interrupt-names = "macirq", "eth_lpi";
811 801
812 iommus = <&apps_smmu 0 802 iommus = <&apps_smmu 0x4c0 0xf>;
813 power-domains = <&gcc 803 power-domains = <&gcc EMAC_0_GDSC>;
814 804
815 snps,tso; 805 snps,tso;
816 snps,pbl = <32>; 806 snps,pbl = <32>;
817 rx-fifo-depth = <4096> 807 rx-fifo-depth = <4096>;
818 tx-fifo-depth = <4096> 808 tx-fifo-depth = <4096>;
819 809
820 status = "disabled"; 810 status = "disabled";
821 }; 811 };
822 812
823 gcc: clock-controller@100000 { 813 gcc: clock-controller@100000 {
824 compatible = "qcom,gcc 814 compatible = "qcom,gcc-sc8280xp";
825 reg = <0x0 0x00100000 815 reg = <0x0 0x00100000 0x0 0x1f0000>;
826 #clock-cells = <1>; 816 #clock-cells = <1>;
827 #reset-cells = <1>; 817 #reset-cells = <1>;
828 #power-domain-cells = 818 #power-domain-cells = <1>;
829 clocks = <&rpmhcc RPMH 819 clocks = <&rpmhcc RPMH_CXO_CLK>,
830 <&sleep_clk>, 820 <&sleep_clk>,
831 <0>, 821 <0>,
832 <0>, 822 <0>,
833 <0>, 823 <0>,
834 <0>, 824 <0>,
835 <0>, 825 <0>,
836 <0>, 826 <0>,
837 <&usb_0_qmpph 827 <&usb_0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
838 <0>, 828 <0>,
839 <0>, 829 <0>,
840 <0>, 830 <0>,
841 <0>, 831 <0>,
842 <0>, 832 <0>,
843 <0>, 833 <0>,
844 <0>, 834 <0>,
845 <&usb_1_qmpph 835 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
846 <0>, 836 <0>,
847 <0>, 837 <0>,
848 <0>, 838 <0>,
849 <0>, 839 <0>,
850 <0>, 840 <0>,
851 <0>, 841 <0>,
852 <0>, 842 <0>,
853 <0>, 843 <0>,
854 <0>, 844 <0>,
855 <&pcie2a_phy> 845 <&pcie2a_phy>,
856 <&pcie2b_phy> 846 <&pcie2b_phy>,
857 <&pcie3a_phy> 847 <&pcie3a_phy>,
858 <&pcie3b_phy> 848 <&pcie3b_phy>,
859 <&pcie4_phy>, 849 <&pcie4_phy>,
860 <0>, 850 <0>,
861 <0>; 851 <0>;
862 power-domains = <&rpmh 852 power-domains = <&rpmhpd SC8280XP_CX>;
863 }; 853 };
864 854
865 ipcc: mailbox@408000 { 855 ipcc: mailbox@408000 {
866 compatible = "qcom,sc8 856 compatible = "qcom,sc8280xp-ipcc", "qcom,ipcc";
867 reg = <0 0x00408000 0 857 reg = <0 0x00408000 0 0x1000>;
868 interrupts = <GIC_SPI 858 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
869 interrupt-controller; 859 interrupt-controller;
870 #interrupt-cells = <3> 860 #interrupt-cells = <3>;
871 #mbox-cells = <2>; 861 #mbox-cells = <2>;
872 }; 862 };
873 863
874 qfprom: efuse@784000 { <<
875 compatible = "qcom,sc8 <<
876 reg = <0 0x00784000 0 <<
877 #address-cells = <1>; <<
878 #size-cells = <1>; <<
879 <<
880 gpu_speed_bin: gpu-spe <<
881 reg = <0x18b 0 <<
882 bits = <5 3>; <<
883 }; <<
884 }; <<
885 <<
886 qup2: geniqup@8c0000 { 864 qup2: geniqup@8c0000 {
887 compatible = "qcom,gen 865 compatible = "qcom,geni-se-qup";
888 reg = <0 0x008c0000 0 866 reg = <0 0x008c0000 0 0x2000>;
889 clocks = <&gcc GCC_QUP 867 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
890 <&gcc GCC_QUP 868 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
891 clock-names = "m-ahb", 869 clock-names = "m-ahb", "s-ahb";
892 iommus = <&apps_smmu 0 870 iommus = <&apps_smmu 0xa3 0>;
893 871
894 #address-cells = <2>; 872 #address-cells = <2>;
895 #size-cells = <2>; 873 #size-cells = <2>;
896 ranges; 874 ranges;
897 875
898 status = "disabled"; 876 status = "disabled";
899 877
900 i2c16: i2c@880000 { 878 i2c16: i2c@880000 {
901 compatible = " 879 compatible = "qcom,geni-i2c";
902 reg = <0 0x008 880 reg = <0 0x00880000 0 0x4000>;
903 #address-cells 881 #address-cells = <1>;
904 #size-cells = 882 #size-cells = <0>;
905 clocks = <&gcc 883 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
906 clock-names = 884 clock-names = "se";
907 interrupts = < 885 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
908 power-domains 886 power-domains = <&rpmhpd SC8280XP_CX>;
909 interconnects 887 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
910 888 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
911 889 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
912 interconnect-n 890 interconnect-names = "qup-core", "qup-config", "qup-memory";
913 status = "disa 891 status = "disabled";
914 }; 892 };
915 893
916 spi16: spi@880000 { 894 spi16: spi@880000 {
917 compatible = " 895 compatible = "qcom,geni-spi";
918 reg = <0 0x008 896 reg = <0 0x00880000 0 0x4000>;
919 #address-cells 897 #address-cells = <1>;
920 #size-cells = 898 #size-cells = <0>;
921 clocks = <&gcc 899 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
922 clock-names = 900 clock-names = "se";
923 interrupts = < 901 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
924 power-domains 902 power-domains = <&rpmhpd SC8280XP_CX>;
925 interconnects 903 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
926 904 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
927 905 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
928 interconnect-n 906 interconnect-names = "qup-core", "qup-config", "qup-memory";
929 status = "disa 907 status = "disabled";
930 }; 908 };
931 909
932 i2c17: i2c@884000 { 910 i2c17: i2c@884000 {
933 compatible = " 911 compatible = "qcom,geni-i2c";
934 reg = <0 0x008 912 reg = <0 0x00884000 0 0x4000>;
935 #address-cells 913 #address-cells = <1>;
936 #size-cells = 914 #size-cells = <0>;
937 clocks = <&gcc 915 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
938 clock-names = 916 clock-names = "se";
939 interrupts = < 917 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
940 power-domains 918 power-domains = <&rpmhpd SC8280XP_CX>;
941 interconnects 919 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
942 920 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
943 921 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
944 interconnect-n 922 interconnect-names = "qup-core", "qup-config", "qup-memory";
945 status = "disa 923 status = "disabled";
946 }; 924 };
947 925
948 spi17: spi@884000 { 926 spi17: spi@884000 {
949 compatible = " 927 compatible = "qcom,geni-spi";
950 reg = <0 0x008 928 reg = <0 0x00884000 0 0x4000>;
951 #address-cells 929 #address-cells = <1>;
952 #size-cells = 930 #size-cells = <0>;
953 clocks = <&gcc 931 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
954 clock-names = 932 clock-names = "se";
955 interrupts = < 933 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
956 power-domains 934 power-domains = <&rpmhpd SC8280XP_CX>;
957 interconnects 935 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
958 936 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
959 937 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
960 interconnect-n 938 interconnect-names = "qup-core", "qup-config", "qup-memory";
961 status = "disa 939 status = "disabled";
962 }; 940 };
963 941
964 uart17: serial@884000 942 uart17: serial@884000 {
965 compatible = " 943 compatible = "qcom,geni-uart";
966 reg = <0 0x008 944 reg = <0 0x00884000 0 0x4000>;
967 clocks = <&gcc 945 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
968 clock-names = 946 clock-names = "se";
969 interrupts = < 947 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
970 operating-poin 948 operating-points-v2 = <&qup_opp_table_100mhz>;
971 power-domains 949 power-domains = <&rpmhpd SC8280XP_CX>;
972 interconnects 950 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
973 951 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>;
974 interconnect-n 952 interconnect-names = "qup-core", "qup-config";
975 status = "disa 953 status = "disabled";
976 }; 954 };
977 955
978 i2c18: i2c@888000 { 956 i2c18: i2c@888000 {
979 compatible = " 957 compatible = "qcom,geni-i2c";
980 reg = <0 0x008 958 reg = <0 0x00888000 0 0x4000>;
981 #address-cells 959 #address-cells = <1>;
982 #size-cells = 960 #size-cells = <0>;
983 clocks = <&gcc 961 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
984 clock-names = 962 clock-names = "se";
985 interrupts = < 963 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
986 power-domains 964 power-domains = <&rpmhpd SC8280XP_CX>;
987 interconnects 965 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
988 966 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
989 967 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
990 interconnect-n 968 interconnect-names = "qup-core", "qup-config", "qup-memory";
991 status = "disa 969 status = "disabled";
992 }; 970 };
993 971
994 spi18: spi@888000 { 972 spi18: spi@888000 {
995 compatible = " 973 compatible = "qcom,geni-spi";
996 reg = <0 0x008 974 reg = <0 0x00888000 0 0x4000>;
997 #address-cells 975 #address-cells = <1>;
998 #size-cells = 976 #size-cells = <0>;
999 clocks = <&gcc 977 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1000 clock-names = 978 clock-names = "se";
1001 interrupts = 979 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1002 power-domains 980 power-domains = <&rpmhpd SC8280XP_CX>;
1003 interconnects 981 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1004 982 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1005 983 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1006 interconnect- 984 interconnect-names = "qup-core", "qup-config", "qup-memory";
1007 status = "dis 985 status = "disabled";
1008 }; 986 };
1009 987
1010 i2c19: i2c@88c000 { 988 i2c19: i2c@88c000 {
1011 compatible = 989 compatible = "qcom,geni-i2c";
1012 reg = <0 0x00 990 reg = <0 0x0088c000 0 0x4000>;
1013 #address-cell 991 #address-cells = <1>;
1014 #size-cells = 992 #size-cells = <0>;
1015 clocks = <&gc 993 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1016 clock-names = 994 clock-names = "se";
1017 interrupts = 995 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1018 power-domains 996 power-domains = <&rpmhpd SC8280XP_CX>;
1019 interconnects 997 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1020 998 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1021 999 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1022 interconnect- 1000 interconnect-names = "qup-core", "qup-config", "qup-memory";
1023 status = "dis 1001 status = "disabled";
1024 }; 1002 };
1025 1003
1026 spi19: spi@88c000 { 1004 spi19: spi@88c000 {
1027 compatible = 1005 compatible = "qcom,geni-spi";
1028 reg = <0 0x00 1006 reg = <0 0x0088c000 0 0x4000>;
1029 #address-cell 1007 #address-cells = <1>;
1030 #size-cells = 1008 #size-cells = <0>;
1031 clocks = <&gc 1009 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1032 clock-names = 1010 clock-names = "se";
1033 interrupts = 1011 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1034 power-domains 1012 power-domains = <&rpmhpd SC8280XP_CX>;
1035 interconnects 1013 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1036 1014 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1037 1015 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1038 interconnect- 1016 interconnect-names = "qup-core", "qup-config", "qup-memory";
1039 status = "dis 1017 status = "disabled";
1040 }; 1018 };
1041 1019
1042 i2c20: i2c@890000 { 1020 i2c20: i2c@890000 {
1043 compatible = 1021 compatible = "qcom,geni-i2c";
1044 reg = <0 0x00 1022 reg = <0 0x00890000 0 0x4000>;
1045 #address-cell 1023 #address-cells = <1>;
1046 #size-cells = 1024 #size-cells = <0>;
1047 clocks = <&gc 1025 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1048 clock-names = 1026 clock-names = "se";
1049 interrupts = 1027 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1050 power-domains 1028 power-domains = <&rpmhpd SC8280XP_CX>;
1051 interconnects 1029 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1052 1030 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1053 1031 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1054 interconnect- 1032 interconnect-names = "qup-core", "qup-config", "qup-memory";
1055 status = "dis 1033 status = "disabled";
1056 }; 1034 };
1057 1035
1058 spi20: spi@890000 { 1036 spi20: spi@890000 {
1059 compatible = 1037 compatible = "qcom,geni-spi";
1060 reg = <0 0x00 1038 reg = <0 0x00890000 0 0x4000>;
1061 #address-cell 1039 #address-cells = <1>;
1062 #size-cells = 1040 #size-cells = <0>;
1063 clocks = <&gc 1041 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1064 clock-names = 1042 clock-names = "se";
1065 interrupts = 1043 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1066 power-domains 1044 power-domains = <&rpmhpd SC8280XP_CX>;
1067 interconnects 1045 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1068 1046 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1069 1047 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1070 interconnect- 1048 interconnect-names = "qup-core", "qup-config", "qup-memory";
1071 status = "dis 1049 status = "disabled";
1072 }; 1050 };
1073 1051
1074 i2c21: i2c@894000 { 1052 i2c21: i2c@894000 {
1075 compatible = 1053 compatible = "qcom,geni-i2c";
1076 reg = <0 0x00 1054 reg = <0 0x00894000 0 0x4000>;
1077 clock-names = 1055 clock-names = "se";
1078 clocks = <&gc 1056 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1079 interrupts = 1057 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1080 #address-cell 1058 #address-cells = <1>;
1081 #size-cells = 1059 #size-cells = <0>;
1082 power-domains 1060 power-domains = <&rpmhpd SC8280XP_CX>;
1083 interconnects 1061 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1084 1062 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1085 1063 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1086 interconnect- 1064 interconnect-names = "qup-core", "qup-config", "qup-memory";
1087 status = "dis 1065 status = "disabled";
1088 }; 1066 };
1089 1067
1090 spi21: spi@894000 { 1068 spi21: spi@894000 {
1091 compatible = 1069 compatible = "qcom,geni-spi";
1092 reg = <0 0x00 1070 reg = <0 0x00894000 0 0x4000>;
1093 #address-cell 1071 #address-cells = <1>;
1094 #size-cells = 1072 #size-cells = <0>;
1095 clocks = <&gc 1073 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1096 clock-names = 1074 clock-names = "se";
1097 interrupts = 1075 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1098 power-domains 1076 power-domains = <&rpmhpd SC8280XP_CX>;
1099 interconnects 1077 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1100 1078 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1101 1079 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1102 interconnect- 1080 interconnect-names = "qup-core", "qup-config", "qup-memory";
1103 status = "dis 1081 status = "disabled";
1104 }; 1082 };
1105 1083
1106 i2c22: i2c@898000 { 1084 i2c22: i2c@898000 {
1107 compatible = 1085 compatible = "qcom,geni-i2c";
1108 reg = <0 0x00 1086 reg = <0 0x00898000 0 0x4000>;
1109 #address-cell 1087 #address-cells = <1>;
1110 #size-cells = 1088 #size-cells = <0>;
1111 clock-names = 1089 clock-names = "se";
1112 clocks = <&gc 1090 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1113 interrupts = 1091 interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>;
1114 power-domains 1092 power-domains = <&rpmhpd SC8280XP_CX>;
1115 interconnects 1093 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1116 1094 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1117 1095 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1118 interconnect- 1096 interconnect-names = "qup-core", "qup-config", "qup-memory";
1119 status = "dis 1097 status = "disabled";
1120 }; 1098 };
1121 1099
1122 spi22: spi@898000 { 1100 spi22: spi@898000 {
1123 compatible = 1101 compatible = "qcom,geni-spi";
1124 reg = <0 0x00 1102 reg = <0 0x00898000 0 0x4000>;
1125 #address-cell 1103 #address-cells = <1>;
1126 #size-cells = 1104 #size-cells = <0>;
1127 clocks = <&gc 1105 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1128 clock-names = 1106 clock-names = "se";
1129 interrupts = 1107 interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>;
1130 power-domains 1108 power-domains = <&rpmhpd SC8280XP_CX>;
1131 interconnects 1109 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1132 1110 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1133 1111 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1134 interconnect- 1112 interconnect-names = "qup-core", "qup-config", "qup-memory";
1135 status = "dis 1113 status = "disabled";
1136 }; 1114 };
1137 1115
1138 i2c23: i2c@89c000 { 1116 i2c23: i2c@89c000 {
1139 compatible = 1117 compatible = "qcom,geni-i2c";
1140 reg = <0 0x00 1118 reg = <0 0x0089c000 0 0x4000>;
1141 #address-cell 1119 #address-cells = <1>;
1142 #size-cells = 1120 #size-cells = <0>;
1143 clock-names = 1121 clock-names = "se";
1144 clocks = <&gc 1122 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
1145 interrupts = 1123 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>;
1146 power-domains 1124 power-domains = <&rpmhpd SC8280XP_CX>;
1147 interconnects 1125 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1148 1126 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1149 1127 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1150 interconnect- 1128 interconnect-names = "qup-core", "qup-config", "qup-memory";
1151 status = "dis 1129 status = "disabled";
1152 }; 1130 };
1153 1131
1154 spi23: spi@89c000 { 1132 spi23: spi@89c000 {
1155 compatible = 1133 compatible = "qcom,geni-spi";
1156 reg = <0 0x00 1134 reg = <0 0x0089c000 0 0x4000>;
1157 #address-cell 1135 #address-cells = <1>;
1158 #size-cells = 1136 #size-cells = <0>;
1159 clocks = <&gc 1137 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
1160 clock-names = 1138 clock-names = "se";
1161 interrupts = 1139 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>;
1162 power-domains 1140 power-domains = <&rpmhpd SC8280XP_CX>;
1163 interconnects 1141 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1164 1142 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1165 1143 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1166 interconnect- 1144 interconnect-names = "qup-core", "qup-config", "qup-memory";
1167 status = "dis 1145 status = "disabled";
1168 }; 1146 };
1169 }; 1147 };
1170 1148
1171 qup0: geniqup@9c0000 { 1149 qup0: geniqup@9c0000 {
1172 compatible = "qcom,ge 1150 compatible = "qcom,geni-se-qup";
1173 reg = <0 0x009c0000 0 1151 reg = <0 0x009c0000 0 0x6000>;
1174 clocks = <&gcc GCC_QU 1152 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1175 <&gcc GCC_QU 1153 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1176 clock-names = "m-ahb" 1154 clock-names = "m-ahb", "s-ahb";
1177 iommus = <&apps_smmu 1155 iommus = <&apps_smmu 0x563 0>;
1178 1156
1179 #address-cells = <2>; 1157 #address-cells = <2>;
1180 #size-cells = <2>; 1158 #size-cells = <2>;
1181 ranges; 1159 ranges;
1182 1160
1183 status = "disabled"; 1161 status = "disabled";
1184 1162
1185 i2c0: i2c@980000 { 1163 i2c0: i2c@980000 {
1186 compatible = 1164 compatible = "qcom,geni-i2c";
1187 reg = <0 0x00 1165 reg = <0 0x00980000 0 0x4000>;
1188 #address-cell 1166 #address-cells = <1>;
1189 #size-cells = 1167 #size-cells = <0>;
1190 clock-names = 1168 clock-names = "se";
1191 clocks = <&gc 1169 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1192 interrupts = 1170 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1193 power-domains 1171 power-domains = <&rpmhpd SC8280XP_CX>;
1194 interconnects 1172 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1195 1173 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1196 1174 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1197 interconnect- 1175 interconnect-names = "qup-core", "qup-config", "qup-memory";
1198 status = "dis 1176 status = "disabled";
1199 }; 1177 };
1200 1178
1201 spi0: spi@980000 { 1179 spi0: spi@980000 {
1202 compatible = 1180 compatible = "qcom,geni-spi";
1203 reg = <0 0x00 1181 reg = <0 0x00980000 0 0x4000>;
1204 #address-cell 1182 #address-cells = <1>;
1205 #size-cells = 1183 #size-cells = <0>;
1206 clocks = <&gc 1184 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1207 clock-names = 1185 clock-names = "se";
1208 interrupts = 1186 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1209 power-domains 1187 power-domains = <&rpmhpd SC8280XP_CX>;
1210 interconnects 1188 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1211 1189 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1212 1190 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1213 interconnect- 1191 interconnect-names = "qup-core", "qup-config", "qup-memory";
1214 status = "dis 1192 status = "disabled";
1215 }; 1193 };
1216 1194
1217 i2c1: i2c@984000 { 1195 i2c1: i2c@984000 {
1218 compatible = 1196 compatible = "qcom,geni-i2c";
1219 reg = <0 0x00 1197 reg = <0 0x00984000 0 0x4000>;
1220 #address-cell 1198 #address-cells = <1>;
1221 #size-cells = 1199 #size-cells = <0>;
1222 clock-names = 1200 clock-names = "se";
1223 clocks = <&gc 1201 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1224 interrupts = 1202 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1225 power-domains 1203 power-domains = <&rpmhpd SC8280XP_CX>;
1226 interconnects 1204 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1227 1205 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1228 1206 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1229 interconnect- 1207 interconnect-names = "qup-core", "qup-config", "qup-memory";
1230 status = "dis 1208 status = "disabled";
1231 }; 1209 };
1232 1210
1233 spi1: spi@984000 { 1211 spi1: spi@984000 {
1234 compatible = 1212 compatible = "qcom,geni-spi";
1235 reg = <0 0x00 1213 reg = <0 0x00984000 0 0x4000>;
1236 #address-cell 1214 #address-cells = <1>;
1237 #size-cells = 1215 #size-cells = <0>;
1238 clocks = <&gc 1216 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1239 clock-names = 1217 clock-names = "se";
1240 interrupts = 1218 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1241 power-domains 1219 power-domains = <&rpmhpd SC8280XP_CX>;
1242 interconnects 1220 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1243 1221 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1244 1222 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1245 interconnect- 1223 interconnect-names = "qup-core", "qup-config", "qup-memory";
1246 status = "dis 1224 status = "disabled";
1247 }; 1225 };
1248 1226
1249 i2c2: i2c@988000 { 1227 i2c2: i2c@988000 {
1250 compatible = 1228 compatible = "qcom,geni-i2c";
1251 reg = <0 0x00 1229 reg = <0 0x00988000 0 0x4000>;
1252 #address-cell 1230 #address-cells = <1>;
1253 #size-cells = 1231 #size-cells = <0>;
1254 clock-names = 1232 clock-names = "se";
1255 clocks = <&gc 1233 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1256 interrupts = 1234 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1257 power-domains 1235 power-domains = <&rpmhpd SC8280XP_CX>;
1258 interconnects 1236 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1259 1237 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1260 1238 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1261 interconnect- 1239 interconnect-names = "qup-core", "qup-config", "qup-memory";
1262 status = "dis 1240 status = "disabled";
1263 }; 1241 };
1264 1242
1265 spi2: spi@988000 { 1243 spi2: spi@988000 {
1266 compatible = 1244 compatible = "qcom,geni-spi";
1267 reg = <0 0x00 1245 reg = <0 0x00988000 0 0x4000>;
1268 #address-cell 1246 #address-cells = <1>;
1269 #size-cells = 1247 #size-cells = <0>;
1270 clocks = <&gc 1248 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1271 clock-names = 1249 clock-names = "se";
1272 interrupts = 1250 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1273 power-domains 1251 power-domains = <&rpmhpd SC8280XP_CX>;
1274 interconnects 1252 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1275 1253 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1276 1254 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1277 interconnect- 1255 interconnect-names = "qup-core", "qup-config", "qup-memory";
1278 status = "dis 1256 status = "disabled";
1279 }; 1257 };
1280 1258
1281 uart2: serial@988000 1259 uart2: serial@988000 {
1282 compatible = 1260 compatible = "qcom,geni-uart";
1283 reg = <0 0x00 1261 reg = <0 0x00988000 0 0x4000>;
1284 clocks = <&gc 1262 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1285 clock-names = 1263 clock-names = "se";
1286 interrupts = 1264 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1287 operating-poi 1265 operating-points-v2 = <&qup_opp_table_100mhz>;
1288 power-domains 1266 power-domains = <&rpmhpd SC8280XP_CX>;
1289 interconnects 1267 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1290 1268 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1291 interconnect- 1269 interconnect-names = "qup-core", "qup-config";
1292 status = "dis 1270 status = "disabled";
1293 }; 1271 };
1294 1272
1295 i2c3: i2c@98c000 { 1273 i2c3: i2c@98c000 {
1296 compatible = 1274 compatible = "qcom,geni-i2c";
1297 reg = <0 0x00 1275 reg = <0 0x0098c000 0 0x4000>;
1298 #address-cell 1276 #address-cells = <1>;
1299 #size-cells = 1277 #size-cells = <0>;
1300 clock-names = 1278 clock-names = "se";
1301 clocks = <&gc 1279 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1302 interrupts = 1280 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1303 power-domains 1281 power-domains = <&rpmhpd SC8280XP_CX>;
1304 interconnects 1282 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1305 1283 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1306 1284 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1307 interconnect- 1285 interconnect-names = "qup-core", "qup-config", "qup-memory";
1308 status = "dis 1286 status = "disabled";
1309 }; 1287 };
1310 1288
1311 spi3: spi@98c000 { 1289 spi3: spi@98c000 {
1312 compatible = 1290 compatible = "qcom,geni-spi";
1313 reg = <0 0x00 1291 reg = <0 0x0098c000 0 0x4000>;
1314 #address-cell 1292 #address-cells = <1>;
1315 #size-cells = 1293 #size-cells = <0>;
1316 clocks = <&gc 1294 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1317 clock-names = 1295 clock-names = "se";
1318 interrupts = 1296 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1319 power-domains 1297 power-domains = <&rpmhpd SC8280XP_CX>;
1320 interconnects 1298 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1321 1299 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1322 1300 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1323 interconnect- 1301 interconnect-names = "qup-core", "qup-config", "qup-memory";
1324 status = "dis 1302 status = "disabled";
1325 }; 1303 };
1326 1304
1327 i2c4: i2c@990000 { 1305 i2c4: i2c@990000 {
1328 compatible = 1306 compatible = "qcom,geni-i2c";
1329 reg = <0 0x00 1307 reg = <0 0x00990000 0 0x4000>;
1330 clock-names = 1308 clock-names = "se";
1331 clocks = <&gc 1309 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1332 interrupts = 1310 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1333 #address-cell 1311 #address-cells = <1>;
1334 #size-cells = 1312 #size-cells = <0>;
1335 power-domains 1313 power-domains = <&rpmhpd SC8280XP_CX>;
1336 interconnects 1314 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1337 1315 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1338 1316 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1339 interconnect- 1317 interconnect-names = "qup-core", "qup-config", "qup-memory";
1340 status = "dis 1318 status = "disabled";
1341 }; 1319 };
1342 1320
1343 spi4: spi@990000 { 1321 spi4: spi@990000 {
1344 compatible = 1322 compatible = "qcom,geni-spi";
1345 reg = <0 0x00 1323 reg = <0 0x00990000 0 0x4000>;
1346 #address-cell 1324 #address-cells = <1>;
1347 #size-cells = 1325 #size-cells = <0>;
1348 clocks = <&gc 1326 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1349 clock-names = 1327 clock-names = "se";
1350 interrupts = 1328 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1351 power-domains 1329 power-domains = <&rpmhpd SC8280XP_CX>;
1352 interconnects 1330 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1353 1331 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1354 1332 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1355 interconnect- 1333 interconnect-names = "qup-core", "qup-config", "qup-memory";
1356 status = "dis 1334 status = "disabled";
1357 }; 1335 };
1358 1336
1359 i2c5: i2c@994000 { 1337 i2c5: i2c@994000 {
1360 compatible = 1338 compatible = "qcom,geni-i2c";
1361 reg = <0 0x00 1339 reg = <0 0x00994000 0 0x4000>;
1362 #address-cell 1340 #address-cells = <1>;
1363 #size-cells = 1341 #size-cells = <0>;
1364 clock-names = 1342 clock-names = "se";
1365 clocks = <&gc 1343 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1366 interrupts = 1344 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1367 power-domains 1345 power-domains = <&rpmhpd SC8280XP_CX>;
1368 interconnects 1346 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1369 1347 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1370 1348 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1371 interconnect- 1349 interconnect-names = "qup-core", "qup-config", "qup-memory";
1372 status = "dis 1350 status = "disabled";
1373 }; 1351 };
1374 1352
1375 spi5: spi@994000 { 1353 spi5: spi@994000 {
1376 compatible = 1354 compatible = "qcom,geni-spi";
1377 reg = <0 0x00 1355 reg = <0 0x00994000 0 0x4000>;
1378 #address-cell 1356 #address-cells = <1>;
1379 #size-cells = 1357 #size-cells = <0>;
1380 clocks = <&gc 1358 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1381 clock-names = 1359 clock-names = "se";
1382 interrupts = 1360 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1383 power-domains 1361 power-domains = <&rpmhpd SC8280XP_CX>;
1384 interconnects 1362 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1385 1363 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1386 1364 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1387 interconnect- 1365 interconnect-names = "qup-core", "qup-config", "qup-memory";
1388 status = "dis 1366 status = "disabled";
1389 }; 1367 };
1390 1368
1391 i2c6: i2c@998000 { 1369 i2c6: i2c@998000 {
1392 compatible = 1370 compatible = "qcom,geni-i2c";
1393 reg = <0 0x00 1371 reg = <0 0x00998000 0 0x4000>;
1394 #address-cell 1372 #address-cells = <1>;
1395 #size-cells = 1373 #size-cells = <0>;
1396 clock-names = 1374 clock-names = "se";
1397 clocks = <&gc 1375 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1398 interrupts = 1376 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1399 power-domains 1377 power-domains = <&rpmhpd SC8280XP_CX>;
1400 interconnects 1378 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1401 1379 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1402 1380 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1403 interconnect- 1381 interconnect-names = "qup-core", "qup-config", "qup-memory";
1404 status = "dis 1382 status = "disabled";
1405 }; 1383 };
1406 1384
1407 spi6: spi@998000 { 1385 spi6: spi@998000 {
1408 compatible = 1386 compatible = "qcom,geni-spi";
1409 reg = <0 0x00 1387 reg = <0 0x00998000 0 0x4000>;
1410 #address-cell 1388 #address-cells = <1>;
1411 #size-cells = 1389 #size-cells = <0>;
1412 clocks = <&gc 1390 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1413 clock-names = 1391 clock-names = "se";
1414 interrupts = 1392 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1415 power-domains 1393 power-domains = <&rpmhpd SC8280XP_CX>;
1416 interconnects 1394 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1417 1395 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1418 1396 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1419 interconnect- 1397 interconnect-names = "qup-core", "qup-config", "qup-memory";
1420 status = "dis 1398 status = "disabled";
1421 }; 1399 };
1422 1400
1423 i2c7: i2c@99c000 { 1401 i2c7: i2c@99c000 {
1424 compatible = 1402 compatible = "qcom,geni-i2c";
1425 reg = <0 0x00 1403 reg = <0 0x0099c000 0 0x4000>;
1426 #address-cell 1404 #address-cells = <1>;
1427 #size-cells = 1405 #size-cells = <0>;
1428 clock-names = 1406 clock-names = "se";
1429 clocks = <&gc 1407 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1430 interrupts = 1408 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1431 power-domains 1409 power-domains = <&rpmhpd SC8280XP_CX>;
1432 interconnects 1410 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1433 1411 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1434 1412 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1435 interconnect- 1413 interconnect-names = "qup-core", "qup-config", "qup-memory";
1436 status = "dis 1414 status = "disabled";
1437 }; 1415 };
1438 1416
1439 spi7: spi@99c000 { 1417 spi7: spi@99c000 {
1440 compatible = 1418 compatible = "qcom,geni-spi";
1441 reg = <0 0x00 1419 reg = <0 0x0099c000 0 0x4000>;
1442 #address-cell 1420 #address-cells = <1>;
1443 #size-cells = 1421 #size-cells = <0>;
1444 clocks = <&gc 1422 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
1445 clock-names = 1423 clock-names = "se";
1446 interrupts = 1424 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1447 power-domains 1425 power-domains = <&rpmhpd SC8280XP_CX>;
1448 interconnects 1426 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1449 1427 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1450 1428 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1451 interconnect- 1429 interconnect-names = "qup-core", "qup-config", "qup-memory";
1452 status = "dis 1430 status = "disabled";
1453 }; 1431 };
1454 }; 1432 };
1455 1433
1456 qup1: geniqup@ac0000 { 1434 qup1: geniqup@ac0000 {
1457 compatible = "qcom,ge 1435 compatible = "qcom,geni-se-qup";
1458 reg = <0 0x00ac0000 0 1436 reg = <0 0x00ac0000 0 0x6000>;
1459 clocks = <&gcc GCC_QU 1437 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1460 <&gcc GCC_QU 1438 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1461 clock-names = "m-ahb" 1439 clock-names = "m-ahb", "s-ahb";
1462 iommus = <&apps_smmu 1440 iommus = <&apps_smmu 0x83 0>;
1463 1441
1464 #address-cells = <2>; 1442 #address-cells = <2>;
1465 #size-cells = <2>; 1443 #size-cells = <2>;
1466 ranges; 1444 ranges;
1467 1445
1468 status = "disabled"; 1446 status = "disabled";
1469 1447
1470 i2c8: i2c@a80000 { 1448 i2c8: i2c@a80000 {
1471 compatible = 1449 compatible = "qcom,geni-i2c";
1472 reg = <0 0x00 1450 reg = <0 0x00a80000 0 0x4000>;
1473 #address-cell 1451 #address-cells = <1>;
1474 #size-cells = 1452 #size-cells = <0>;
1475 clocks = <&gc 1453 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1476 clock-names = 1454 clock-names = "se";
1477 interrupts = 1455 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1478 power-domains 1456 power-domains = <&rpmhpd SC8280XP_CX>;
1479 interconnects 1457 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1480 1458 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1481 1459 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1482 interconnect- 1460 interconnect-names = "qup-core", "qup-config", "qup-memory";
1483 status = "dis 1461 status = "disabled";
1484 }; 1462 };
1485 1463
1486 spi8: spi@a80000 { 1464 spi8: spi@a80000 {
1487 compatible = 1465 compatible = "qcom,geni-spi";
1488 reg = <0 0x00 1466 reg = <0 0x00a80000 0 0x4000>;
1489 #address-cell 1467 #address-cells = <1>;
1490 #size-cells = 1468 #size-cells = <0>;
1491 clocks = <&gc 1469 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1492 clock-names = 1470 clock-names = "se";
1493 interrupts = 1471 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1494 power-domains 1472 power-domains = <&rpmhpd SC8280XP_CX>;
1495 interconnects 1473 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1496 1474 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1497 1475 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1498 interconnect- 1476 interconnect-names = "qup-core", "qup-config", "qup-memory";
1499 status = "dis 1477 status = "disabled";
1500 }; 1478 };
1501 1479
1502 i2c9: i2c@a84000 { 1480 i2c9: i2c@a84000 {
1503 compatible = 1481 compatible = "qcom,geni-i2c";
1504 reg = <0 0x00 1482 reg = <0 0x00a84000 0 0x4000>;
1505 #address-cell 1483 #address-cells = <1>;
1506 #size-cells = 1484 #size-cells = <0>;
1507 clocks = <&gc 1485 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1508 clock-names = 1486 clock-names = "se";
1509 interrupts = 1487 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1510 power-domains 1488 power-domains = <&rpmhpd SC8280XP_CX>;
1511 interconnects 1489 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1512 1490 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1513 1491 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1514 interconnect- 1492 interconnect-names = "qup-core", "qup-config", "qup-memory";
1515 status = "dis 1493 status = "disabled";
1516 }; 1494 };
1517 1495
1518 spi9: spi@a84000 { 1496 spi9: spi@a84000 {
1519 compatible = 1497 compatible = "qcom,geni-spi";
1520 reg = <0 0x00 1498 reg = <0 0x00a84000 0 0x4000>;
1521 #address-cell 1499 #address-cells = <1>;
1522 #size-cells = 1500 #size-cells = <0>;
1523 clocks = <&gc 1501 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1524 clock-names = 1502 clock-names = "se";
1525 interrupts = 1503 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1526 power-domains 1504 power-domains = <&rpmhpd SC8280XP_CX>;
1527 interconnects 1505 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1528 1506 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1529 1507 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1530 interconnect- 1508 interconnect-names = "qup-core", "qup-config", "qup-memory";
1531 status = "dis 1509 status = "disabled";
1532 }; 1510 };
1533 1511
1534 i2c10: i2c@a88000 { 1512 i2c10: i2c@a88000 {
1535 compatible = 1513 compatible = "qcom,geni-i2c";
1536 reg = <0 0x00 1514 reg = <0 0x00a88000 0 0x4000>;
1537 #address-cell 1515 #address-cells = <1>;
1538 #size-cells = 1516 #size-cells = <0>;
1539 clocks = <&gc 1517 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1540 clock-names = 1518 clock-names = "se";
1541 interrupts = 1519 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1542 power-domains 1520 power-domains = <&rpmhpd SC8280XP_CX>;
1543 interconnects 1521 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1544 1522 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1545 1523 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1546 interconnect- 1524 interconnect-names = "qup-core", "qup-config", "qup-memory";
1547 status = "dis 1525 status = "disabled";
1548 }; 1526 };
1549 1527
1550 spi10: spi@a88000 { 1528 spi10: spi@a88000 {
1551 compatible = 1529 compatible = "qcom,geni-spi";
1552 reg = <0 0x00 1530 reg = <0 0x00a88000 0 0x4000>;
1553 #address-cell 1531 #address-cells = <1>;
1554 #size-cells = 1532 #size-cells = <0>;
1555 clocks = <&gc 1533 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1556 clock-names = 1534 clock-names = "se";
1557 interrupts = 1535 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1558 power-domains 1536 power-domains = <&rpmhpd SC8280XP_CX>;
1559 interconnects 1537 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1560 1538 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1561 1539 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1562 interconnect- 1540 interconnect-names = "qup-core", "qup-config", "qup-memory";
1563 status = "dis 1541 status = "disabled";
1564 }; 1542 };
1565 1543
1566 i2c11: i2c@a8c000 { 1544 i2c11: i2c@a8c000 {
1567 compatible = 1545 compatible = "qcom,geni-i2c";
1568 reg = <0 0x00 1546 reg = <0 0x00a8c000 0 0x4000>;
1569 #address-cell 1547 #address-cells = <1>;
1570 #size-cells = 1548 #size-cells = <0>;
1571 clocks = <&gc 1549 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1572 clock-names = 1550 clock-names = "se";
1573 interrupts = 1551 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1574 power-domains 1552 power-domains = <&rpmhpd SC8280XP_CX>;
1575 interconnects 1553 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1576 1554 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1577 1555 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1578 interconnect- 1556 interconnect-names = "qup-core", "qup-config", "qup-memory";
1579 status = "dis 1557 status = "disabled";
1580 }; 1558 };
1581 1559
1582 spi11: spi@a8c000 { 1560 spi11: spi@a8c000 {
1583 compatible = 1561 compatible = "qcom,geni-spi";
1584 reg = <0 0x00 1562 reg = <0 0x00a8c000 0 0x4000>;
1585 #address-cell 1563 #address-cells = <1>;
1586 #size-cells = 1564 #size-cells = <0>;
1587 clocks = <&gc 1565 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1588 clock-names = 1566 clock-names = "se";
1589 interrupts = 1567 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1590 power-domains 1568 power-domains = <&rpmhpd SC8280XP_CX>;
1591 interconnects 1569 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1592 1570 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1593 1571 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1594 interconnect- 1572 interconnect-names = "qup-core", "qup-config", "qup-memory";
1595 status = "dis 1573 status = "disabled";
1596 }; 1574 };
1597 1575
1598 i2c12: i2c@a90000 { 1576 i2c12: i2c@a90000 {
1599 compatible = 1577 compatible = "qcom,geni-i2c";
1600 reg = <0 0x00 1578 reg = <0 0x00a90000 0 0x4000>;
1601 #address-cell 1579 #address-cells = <1>;
1602 #size-cells = 1580 #size-cells = <0>;
1603 clocks = <&gc 1581 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1604 clock-names = 1582 clock-names = "se";
1605 interrupts = 1583 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1606 power-domains 1584 power-domains = <&rpmhpd SC8280XP_CX>;
1607 interconnects 1585 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1608 1586 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1609 1587 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1610 interconnect- 1588 interconnect-names = "qup-core", "qup-config", "qup-memory";
1611 status = "dis 1589 status = "disabled";
1612 }; 1590 };
1613 1591
1614 spi12: spi@a90000 { 1592 spi12: spi@a90000 {
1615 compatible = 1593 compatible = "qcom,geni-spi";
1616 reg = <0 0x00 1594 reg = <0 0x00a90000 0 0x4000>;
1617 #address-cell 1595 #address-cells = <1>;
1618 #size-cells = 1596 #size-cells = <0>;
1619 clocks = <&gc 1597 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1620 clock-names = 1598 clock-names = "se";
1621 interrupts = 1599 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1622 power-domains 1600 power-domains = <&rpmhpd SC8280XP_CX>;
1623 interconnects 1601 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1624 1602 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1625 1603 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1626 interconnect- 1604 interconnect-names = "qup-core", "qup-config", "qup-memory";
1627 status = "dis 1605 status = "disabled";
1628 }; 1606 };
1629 1607
1630 i2c13: i2c@a94000 { 1608 i2c13: i2c@a94000 {
1631 compatible = 1609 compatible = "qcom,geni-i2c";
1632 reg = <0 0x00 1610 reg = <0 0x00a94000 0 0x4000>;
1633 #address-cell 1611 #address-cells = <1>;
1634 #size-cells = 1612 #size-cells = <0>;
1635 clocks = <&gc 1613 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1636 clock-names = 1614 clock-names = "se";
1637 interrupts = 1615 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1638 power-domains 1616 power-domains = <&rpmhpd SC8280XP_CX>;
1639 interconnects 1617 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1640 1618 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1641 1619 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1642 interconnect- 1620 interconnect-names = "qup-core", "qup-config", "qup-memory";
1643 status = "dis 1621 status = "disabled";
1644 }; 1622 };
1645 1623
1646 spi13: spi@a94000 { 1624 spi13: spi@a94000 {
1647 compatible = 1625 compatible = "qcom,geni-spi";
1648 reg = <0 0x00 1626 reg = <0 0x00a94000 0 0x4000>;
1649 #address-cell 1627 #address-cells = <1>;
1650 #size-cells = 1628 #size-cells = <0>;
1651 clocks = <&gc 1629 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1652 clock-names = 1630 clock-names = "se";
1653 interrupts = 1631 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1654 power-domains 1632 power-domains = <&rpmhpd SC8280XP_CX>;
1655 interconnects 1633 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1656 1634 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1657 1635 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1658 interconnect- 1636 interconnect-names = "qup-core", "qup-config", "qup-memory";
1659 status = "dis 1637 status = "disabled";
1660 }; 1638 };
1661 1639
1662 i2c14: i2c@a98000 { 1640 i2c14: i2c@a98000 {
1663 compatible = 1641 compatible = "qcom,geni-i2c";
1664 reg = <0 0x00 1642 reg = <0 0x00a98000 0 0x4000>;
1665 #address-cell 1643 #address-cells = <1>;
1666 #size-cells = 1644 #size-cells = <0>;
1667 clocks = <&gc 1645 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1668 clock-names = 1646 clock-names = "se";
1669 interrupts = 1647 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>;
1670 power-domains 1648 power-domains = <&rpmhpd SC8280XP_CX>;
1671 interconnects 1649 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1672 1650 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1673 1651 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1674 interconnect- 1652 interconnect-names = "qup-core", "qup-config", "qup-memory";
1675 status = "dis 1653 status = "disabled";
1676 }; 1654 };
1677 1655
1678 spi14: spi@a98000 { 1656 spi14: spi@a98000 {
1679 compatible = 1657 compatible = "qcom,geni-spi";
1680 reg = <0 0x00 1658 reg = <0 0x00a98000 0 0x4000>;
1681 #address-cell 1659 #address-cells = <1>;
1682 #size-cells = 1660 #size-cells = <0>;
1683 clocks = <&gc 1661 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1684 clock-names = 1662 clock-names = "se";
1685 interrupts = 1663 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>;
1686 power-domains 1664 power-domains = <&rpmhpd SC8280XP_CX>;
1687 interconnects 1665 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1688 1666 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1689 1667 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1690 interconnect- 1668 interconnect-names = "qup-core", "qup-config", "qup-memory";
1691 status = "dis 1669 status = "disabled";
1692 }; 1670 };
1693 1671
1694 i2c15: i2c@a9c000 { 1672 i2c15: i2c@a9c000 {
1695 compatible = 1673 compatible = "qcom,geni-i2c";
1696 reg = <0 0x00 1674 reg = <0 0x00a9c000 0 0x4000>;
1697 #address-cell 1675 #address-cells = <1>;
1698 #size-cells = 1676 #size-cells = <0>;
1699 clocks = <&gc 1677 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1700 clock-names = 1678 clock-names = "se";
1701 interrupts = 1679 interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
1702 power-domains 1680 power-domains = <&rpmhpd SC8280XP_CX>;
1703 interconnects 1681 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1704 1682 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1705 1683 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1706 interconnect- 1684 interconnect-names = "qup-core", "qup-config", "qup-memory";
1707 status = "dis 1685 status = "disabled";
1708 }; 1686 };
1709 1687
1710 spi15: spi@a9c000 { 1688 spi15: spi@a9c000 {
1711 compatible = 1689 compatible = "qcom,geni-spi";
1712 reg = <0 0x00 1690 reg = <0 0x00a9c000 0 0x4000>;
1713 #address-cell 1691 #address-cells = <1>;
1714 #size-cells = 1692 #size-cells = <0>;
1715 clocks = <&gc 1693 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1716 clock-names = 1694 clock-names = "se";
1717 interrupts = 1695 interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
1718 power-domains 1696 power-domains = <&rpmhpd SC8280XP_CX>;
1719 interconnects 1697 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1720 1698 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1721 1699 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1722 interconnect- 1700 interconnect-names = "qup-core", "qup-config", "qup-memory";
1723 status = "dis 1701 status = "disabled";
1724 }; 1702 };
1725 }; 1703 };
1726 1704
1727 rng: rng@10d3000 { 1705 rng: rng@10d3000 {
1728 compatible = "qcom,pr 1706 compatible = "qcom,prng-ee";
1729 reg = <0 0x010d3000 0 1707 reg = <0 0x010d3000 0 0x1000>;
1730 clocks = <&rpmhcc RPM 1708 clocks = <&rpmhcc RPMH_HWKM_CLK>;
1731 clock-names = "core"; 1709 clock-names = "core";
1732 }; 1710 };
1733 1711
1734 pcie4: pcie@1c00000 { 1712 pcie4: pcie@1c00000 {
1735 device_type = "pci"; 1713 device_type = "pci";
1736 compatible = "qcom,pc 1714 compatible = "qcom,pcie-sc8280xp";
1737 reg = <0x0 0x01c00000 1715 reg = <0x0 0x01c00000 0x0 0x3000>,
1738 <0x0 0x30000000 1716 <0x0 0x30000000 0x0 0xf1d>,
1739 <0x0 0x30000f20 1717 <0x0 0x30000f20 0x0 0xa8>,
1740 <0x0 0x30001000 1718 <0x0 0x30001000 0x0 0x1000>,
1741 <0x0 0x30100000 1719 <0x0 0x30100000 0x0 0x100000>,
1742 <0x0 0x01c03000 1720 <0x0 0x01c03000 0x0 0x1000>;
1743 reg-names = "parf", " 1721 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
1744 #address-cells = <3>; 1722 #address-cells = <3>;
1745 #size-cells = <2>; 1723 #size-cells = <2>;
1746 ranges = <0x01000000 1724 ranges = <0x01000000 0x0 0x00000000 0x0 0x30200000 0x0 0x100000>,
1747 <0x02000000 1725 <0x02000000 0x0 0x30300000 0x0 0x30300000 0x0 0x1d00000>;
1748 bus-range = <0x00 0xf 1726 bus-range = <0x00 0xff>;
1749 1727
1750 dma-coherent; 1728 dma-coherent;
1751 1729
1752 linux,pci-domain = <6 1730 linux,pci-domain = <6>;
1753 num-lanes = <1>; 1731 num-lanes = <1>;
1754 1732
1755 msi-map = <0x0 &its 0 <<
1756 <<
1757 interrupts = <GIC_SPI 1733 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
1758 <GIC_SPI 1734 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
1759 <GIC_SPI 1735 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
1760 <GIC_SPI 1736 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
1761 interrupt-names = "ms 1737 interrupt-names = "msi0", "msi1", "msi2", "msi3";
1762 1738
1763 #interrupt-cells = <1 1739 #interrupt-cells = <1>;
1764 interrupt-map-mask = 1740 interrupt-map-mask = <0 0 0 0x7>;
1765 interrupt-map = <0 0 1741 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
1766 <0 0 1742 <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
1767 <0 0 1743 <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
1768 <0 0 1744 <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
1769 1745
1770 clocks = <&gcc GCC_PC 1746 clocks = <&gcc GCC_PCIE_4_AUX_CLK>,
1771 <&gcc GCC_PC 1747 <&gcc GCC_PCIE_4_CFG_AHB_CLK>,
1772 <&gcc GCC_PC 1748 <&gcc GCC_PCIE_4_MSTR_AXI_CLK>,
1773 <&gcc GCC_PC 1749 <&gcc GCC_PCIE_4_SLV_AXI_CLK>,
1774 <&gcc GCC_PC 1750 <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>,
1775 <&gcc GCC_DD 1751 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1776 <&gcc GCC_AG 1752 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
1777 <&gcc GCC_AG 1753 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>,
1778 <&gcc GCC_CN 1754 <&gcc GCC_CNOC_PCIE4_QX_CLK>;
1779 clock-names = "aux", 1755 clock-names = "aux",
1780 "cfg", 1756 "cfg",
1781 "bus_ma 1757 "bus_master",
1782 "bus_sl 1758 "bus_slave",
1783 "slave_ 1759 "slave_q2a",
1784 "ddrss_ 1760 "ddrss_sf_tbu",
1785 "noc_ag 1761 "noc_aggr_4",
1786 "noc_ag 1762 "noc_aggr_south_sf",
1787 "cnoc_q 1763 "cnoc_qx";
1788 1764
1789 assigned-clocks = <&g 1765 assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>;
1790 assigned-clock-rates 1766 assigned-clock-rates = <19200000>;
1791 1767
1792 interconnects = <&agg 1768 interconnects = <&aggre2_noc MASTER_PCIE_4 0 &mc_virt SLAVE_EBI1 0>,
1793 <&gem 1769 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_4 0>;
1794 interconnect-names = 1770 interconnect-names = "pcie-mem", "cpu-pcie";
1795 1771
1796 resets = <&gcc GCC_PC 1772 resets = <&gcc GCC_PCIE_4_BCR>;
1797 reset-names = "pci"; 1773 reset-names = "pci";
1798 1774
1799 power-domains = <&gcc 1775 power-domains = <&gcc PCIE_4_GDSC>;
1800 required-opps = <&rpm 1776 required-opps = <&rpmhpd_opp_nom>;
1801 1777
1802 phys = <&pcie4_phy>; 1778 phys = <&pcie4_phy>;
1803 phy-names = "pciephy" 1779 phy-names = "pciephy";
1804 1780
1805 status = "disabled"; 1781 status = "disabled";
1806 <<
1807 pcie4_port0: pcie@0 { <<
1808 device_type = <<
1809 reg = <0x0 0x <<
1810 bus-range = < <<
1811 <<
1812 #address-cell <<
1813 #size-cells = <<
1814 ranges; <<
1815 }; <<
1816 }; 1782 };
1817 1783
1818 pcie4_phy: phy@1c06000 { 1784 pcie4_phy: phy@1c06000 {
1819 compatible = "qcom,sc 1785 compatible = "qcom,sc8280xp-qmp-gen3x1-pcie-phy";
1820 reg = <0x0 0x01c06000 1786 reg = <0x0 0x01c06000 0x0 0x2000>;
1821 1787
1822 clocks = <&gcc GCC_PC 1788 clocks = <&gcc GCC_PCIE_4_AUX_CLK>,
1823 <&gcc GCC_PC 1789 <&gcc GCC_PCIE_4_CFG_AHB_CLK>,
1824 <&gcc GCC_PC 1790 <&gcc GCC_PCIE_4_CLKREF_CLK>,
1825 <&gcc GCC_PC 1791 <&gcc GCC_PCIE4_PHY_RCHNG_CLK>,
1826 <&gcc GCC_PC 1792 <&gcc GCC_PCIE_4_PIPE_CLK>,
1827 <&gcc GCC_PC 1793 <&gcc GCC_PCIE_4_PIPEDIV2_CLK>;
1828 clock-names = "aux", 1794 clock-names = "aux", "cfg_ahb", "ref", "rchng",
1829 "pipe", 1795 "pipe", "pipediv2";
1830 1796
1831 assigned-clocks = <&g 1797 assigned-clocks = <&gcc GCC_PCIE4_PHY_RCHNG_CLK>;
1832 assigned-clock-rates 1798 assigned-clock-rates = <100000000>;
1833 1799
1834 power-domains = <&gcc 1800 power-domains = <&gcc PCIE_4_GDSC>;
>> 1801 required-opps = <&rpmhpd_opp_nom>;
1835 1802
1836 resets = <&gcc GCC_PC 1803 resets = <&gcc GCC_PCIE_4_PHY_BCR>;
1837 reset-names = "phy"; 1804 reset-names = "phy";
1838 1805
1839 #clock-cells = <0>; 1806 #clock-cells = <0>;
1840 clock-output-names = 1807 clock-output-names = "pcie_4_pipe_clk";
1841 1808
1842 #phy-cells = <0>; 1809 #phy-cells = <0>;
1843 1810
1844 status = "disabled"; 1811 status = "disabled";
1845 }; 1812 };
1846 1813
1847 pcie3b: pcie@1c08000 { 1814 pcie3b: pcie@1c08000 {
1848 device_type = "pci"; 1815 device_type = "pci";
1849 compatible = "qcom,pc 1816 compatible = "qcom,pcie-sc8280xp";
1850 reg = <0x0 0x01c08000 1817 reg = <0x0 0x01c08000 0x0 0x3000>,
1851 <0x0 0x32000000 1818 <0x0 0x32000000 0x0 0xf1d>,
1852 <0x0 0x32000f20 1819 <0x0 0x32000f20 0x0 0xa8>,
1853 <0x0 0x32001000 1820 <0x0 0x32001000 0x0 0x1000>,
1854 <0x0 0x32100000 1821 <0x0 0x32100000 0x0 0x100000>,
1855 <0x0 0x01c0b000 1822 <0x0 0x01c0b000 0x0 0x1000>;
1856 reg-names = "parf", " 1823 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
1857 #address-cells = <3>; 1824 #address-cells = <3>;
1858 #size-cells = <2>; 1825 #size-cells = <2>;
1859 ranges = <0x01000000 1826 ranges = <0x01000000 0x0 0x00000000 0x0 0x32200000 0x0 0x100000>,
1860 <0x02000000 1827 <0x02000000 0x0 0x32300000 0x0 0x32300000 0x0 0x1d00000>;
1861 bus-range = <0x00 0xf 1828 bus-range = <0x00 0xff>;
1862 1829
1863 dma-coherent; 1830 dma-coherent;
1864 1831
1865 linux,pci-domain = <5 1832 linux,pci-domain = <5>;
1866 num-lanes = <2>; 1833 num-lanes = <2>;
1867 1834
1868 msi-map = <0x0 &its 0 <<
1869 <<
1870 interrupts = <GIC_SPI 1835 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1871 <GIC_SPI 1836 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1872 <GIC_SPI 1837 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
1873 <GIC_SPI 1838 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
1874 interrupt-names = "ms 1839 interrupt-names = "msi0", "msi1", "msi2", "msi3";
1875 1840
1876 #interrupt-cells = <1 1841 #interrupt-cells = <1>;
1877 interrupt-map-mask = 1842 interrupt-map-mask = <0 0 0 0x7>;
1878 interrupt-map = <0 0 1843 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>,
1879 <0 0 1844 <0 0 0 2 &intc 0 0 GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>,
1880 <0 0 1845 <0 0 0 3 &intc 0 0 GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>,
1881 <0 0 1846 <0 0 0 4 &intc 0 0 GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>;
1882 1847
1883 clocks = <&gcc GCC_PC 1848 clocks = <&gcc GCC_PCIE_3B_AUX_CLK>,
1884 <&gcc GCC_PC 1849 <&gcc GCC_PCIE_3B_CFG_AHB_CLK>,
1885 <&gcc GCC_PC 1850 <&gcc GCC_PCIE_3B_MSTR_AXI_CLK>,
1886 <&gcc GCC_PC 1851 <&gcc GCC_PCIE_3B_SLV_AXI_CLK>,
1887 <&gcc GCC_PC 1852 <&gcc GCC_PCIE_3B_SLV_Q2A_AXI_CLK>,
1888 <&gcc GCC_DD 1853 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1889 <&gcc GCC_AG 1854 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
1890 <&gcc GCC_AG 1855 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
1891 clock-names = "aux", 1856 clock-names = "aux",
1892 "cfg", 1857 "cfg",
1893 "bus_ma 1858 "bus_master",
1894 "bus_sl 1859 "bus_slave",
1895 "slave_ 1860 "slave_q2a",
1896 "ddrss_ 1861 "ddrss_sf_tbu",
1897 "noc_ag 1862 "noc_aggr_4",
1898 "noc_ag 1863 "noc_aggr_south_sf";
1899 1864
1900 assigned-clocks = <&g 1865 assigned-clocks = <&gcc GCC_PCIE_3B_AUX_CLK>;
1901 assigned-clock-rates 1866 assigned-clock-rates = <19200000>;
1902 1867
1903 interconnects = <&agg 1868 interconnects = <&aggre2_noc MASTER_PCIE_3B 0 &mc_virt SLAVE_EBI1 0>,
1904 <&gem 1869 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3B 0>;
1905 interconnect-names = 1870 interconnect-names = "pcie-mem", "cpu-pcie";
1906 1871
1907 resets = <&gcc GCC_PC 1872 resets = <&gcc GCC_PCIE_3B_BCR>;
1908 reset-names = "pci"; 1873 reset-names = "pci";
1909 1874
1910 power-domains = <&gcc 1875 power-domains = <&gcc PCIE_3B_GDSC>;
1911 required-opps = <&rpm 1876 required-opps = <&rpmhpd_opp_nom>;
1912 1877
1913 phys = <&pcie3b_phy>; 1878 phys = <&pcie3b_phy>;
1914 phy-names = "pciephy" 1879 phy-names = "pciephy";
1915 1880
1916 status = "disabled"; 1881 status = "disabled";
1917 <<
1918 pcie3b_port0: pcie@0 <<
1919 device_type = <<
1920 reg = <0x0 0x <<
1921 bus-range = < <<
1922 <<
1923 #address-cell <<
1924 #size-cells = <<
1925 ranges; <<
1926 }; <<
1927 }; 1882 };
1928 1883
1929 pcie3b_phy: phy@1c0e000 { 1884 pcie3b_phy: phy@1c0e000 {
1930 compatible = "qcom,sc 1885 compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy";
1931 reg = <0x0 0x01c0e000 1886 reg = <0x0 0x01c0e000 0x0 0x2000>;
1932 1887
1933 clocks = <&gcc GCC_PC 1888 clocks = <&gcc GCC_PCIE_3B_AUX_CLK>,
1934 <&gcc GCC_PC 1889 <&gcc GCC_PCIE_3B_CFG_AHB_CLK>,
1935 <&gcc GCC_PC 1890 <&gcc GCC_PCIE_3A3B_CLKREF_CLK>,
1936 <&gcc GCC_PC 1891 <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>,
1937 <&gcc GCC_PC 1892 <&gcc GCC_PCIE_3B_PIPE_CLK>,
1938 <&gcc GCC_PC 1893 <&gcc GCC_PCIE_3B_PIPEDIV2_CLK>;
1939 clock-names = "aux", 1894 clock-names = "aux", "cfg_ahb", "ref", "rchng",
1940 "pipe", 1895 "pipe", "pipediv2";
1941 1896
1942 assigned-clocks = <&g 1897 assigned-clocks = <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>;
1943 assigned-clock-rates 1898 assigned-clock-rates = <100000000>;
1944 1899
1945 power-domains = <&gcc 1900 power-domains = <&gcc PCIE_3B_GDSC>;
>> 1901 required-opps = <&rpmhpd_opp_nom>;
1946 1902
1947 resets = <&gcc GCC_PC 1903 resets = <&gcc GCC_PCIE_3B_PHY_BCR>;
1948 reset-names = "phy"; 1904 reset-names = "phy";
1949 1905
1950 #clock-cells = <0>; 1906 #clock-cells = <0>;
1951 clock-output-names = 1907 clock-output-names = "pcie_3b_pipe_clk";
1952 1908
1953 #phy-cells = <0>; 1909 #phy-cells = <0>;
1954 1910
1955 status = "disabled"; 1911 status = "disabled";
1956 }; 1912 };
1957 1913
1958 pcie3a: pcie@1c10000 { 1914 pcie3a: pcie@1c10000 {
1959 device_type = "pci"; 1915 device_type = "pci";
1960 compatible = "qcom,pc 1916 compatible = "qcom,pcie-sc8280xp";
1961 reg = <0x0 0x01c10000 1917 reg = <0x0 0x01c10000 0x0 0x3000>,
1962 <0x0 0x34000000 1918 <0x0 0x34000000 0x0 0xf1d>,
1963 <0x0 0x34000f20 1919 <0x0 0x34000f20 0x0 0xa8>,
1964 <0x0 0x34001000 1920 <0x0 0x34001000 0x0 0x1000>,
1965 <0x0 0x34100000 1921 <0x0 0x34100000 0x0 0x100000>,
1966 <0x0 0x01c13000 1922 <0x0 0x01c13000 0x0 0x1000>;
1967 reg-names = "parf", " 1923 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
1968 #address-cells = <3>; 1924 #address-cells = <3>;
1969 #size-cells = <2>; 1925 #size-cells = <2>;
1970 ranges = <0x01000000 1926 ranges = <0x01000000 0x0 0x00000000 0x0 0x34200000 0x0 0x100000>,
1971 <0x02000000 1927 <0x02000000 0x0 0x34300000 0x0 0x34300000 0x0 0x1d00000>;
1972 bus-range = <0x00 0xf 1928 bus-range = <0x00 0xff>;
1973 1929
1974 dma-coherent; 1930 dma-coherent;
1975 1931
1976 linux,pci-domain = <4 1932 linux,pci-domain = <4>;
1977 num-lanes = <4>; 1933 num-lanes = <4>;
1978 1934
1979 msi-map = <0x0 &its 0 <<
1980 <<
1981 interrupts = <GIC_SPI 1935 interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
1982 <GIC_SPI 1936 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
1983 <GIC_SPI 1937 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
1984 <GIC_SPI 1938 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1985 interrupt-names = "ms 1939 interrupt-names = "msi0", "msi1", "msi2", "msi3";
1986 1940
1987 #interrupt-cells = <1 1941 #interrupt-cells = <1>;
1988 interrupt-map-mask = 1942 interrupt-map-mask = <0 0 0 0x7>;
1989 interrupt-map = <0 0 1943 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>,
1990 <0 0 1944 <0 0 0 2 &intc 0 0 GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>,
1991 <0 0 1945 <0 0 0 3 &intc 0 0 GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>,
1992 <0 0 1946 <0 0 0 4 &intc 0 0 GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>;
1993 1947
1994 clocks = <&gcc GCC_PC 1948 clocks = <&gcc GCC_PCIE_3A_AUX_CLK>,
1995 <&gcc GCC_PC 1949 <&gcc GCC_PCIE_3A_CFG_AHB_CLK>,
1996 <&gcc GCC_PC 1950 <&gcc GCC_PCIE_3A_MSTR_AXI_CLK>,
1997 <&gcc GCC_PC 1951 <&gcc GCC_PCIE_3A_SLV_AXI_CLK>,
1998 <&gcc GCC_PC 1952 <&gcc GCC_PCIE_3A_SLV_Q2A_AXI_CLK>,
1999 <&gcc GCC_DD 1953 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
2000 <&gcc GCC_AG 1954 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
2001 <&gcc GCC_AG 1955 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
2002 clock-names = "aux", 1956 clock-names = "aux",
2003 "cfg", 1957 "cfg",
2004 "bus_ma 1958 "bus_master",
2005 "bus_sl 1959 "bus_slave",
2006 "slave_ 1960 "slave_q2a",
2007 "ddrss_ 1961 "ddrss_sf_tbu",
2008 "noc_ag 1962 "noc_aggr_4",
2009 "noc_ag 1963 "noc_aggr_south_sf";
2010 1964
2011 assigned-clocks = <&g 1965 assigned-clocks = <&gcc GCC_PCIE_3A_AUX_CLK>;
2012 assigned-clock-rates 1966 assigned-clock-rates = <19200000>;
2013 1967
2014 interconnects = <&agg 1968 interconnects = <&aggre2_noc MASTER_PCIE_3A 0 &mc_virt SLAVE_EBI1 0>,
2015 <&gem 1969 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3A 0>;
2016 interconnect-names = 1970 interconnect-names = "pcie-mem", "cpu-pcie";
2017 1971
2018 resets = <&gcc GCC_PC 1972 resets = <&gcc GCC_PCIE_3A_BCR>;
2019 reset-names = "pci"; 1973 reset-names = "pci";
2020 1974
2021 power-domains = <&gcc 1975 power-domains = <&gcc PCIE_3A_GDSC>;
2022 required-opps = <&rpm 1976 required-opps = <&rpmhpd_opp_nom>;
2023 1977
2024 phys = <&pcie3a_phy>; 1978 phys = <&pcie3a_phy>;
2025 phy-names = "pciephy" 1979 phy-names = "pciephy";
2026 1980
2027 status = "disabled"; 1981 status = "disabled";
2028 <<
2029 pcie3a_port0: pcie@0 <<
2030 device_type = <<
2031 reg = <0x0 0x <<
2032 bus-range = < <<
2033 <<
2034 #address-cell <<
2035 #size-cells = <<
2036 ranges; <<
2037 }; <<
2038 }; 1982 };
2039 1983
2040 pcie3a_phy: phy@1c14000 { 1984 pcie3a_phy: phy@1c14000 {
2041 compatible = "qcom,sc 1985 compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy";
2042 reg = <0x0 0x01c14000 1986 reg = <0x0 0x01c14000 0x0 0x2000>,
2043 <0x0 0x01c16000 1987 <0x0 0x01c16000 0x0 0x2000>;
2044 1988
2045 clocks = <&gcc GCC_PC 1989 clocks = <&gcc GCC_PCIE_3A_AUX_CLK>,
2046 <&gcc GCC_PC 1990 <&gcc GCC_PCIE_3A_CFG_AHB_CLK>,
2047 <&gcc GCC_PC 1991 <&gcc GCC_PCIE_3A3B_CLKREF_CLK>,
2048 <&gcc GCC_PC 1992 <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>,
2049 <&gcc GCC_PC 1993 <&gcc GCC_PCIE_3A_PIPE_CLK>,
2050 <&gcc GCC_PC 1994 <&gcc GCC_PCIE_3A_PIPEDIV2_CLK>;
2051 clock-names = "aux", 1995 clock-names = "aux", "cfg_ahb", "ref", "rchng",
2052 "pipe", 1996 "pipe", "pipediv2";
2053 1997
2054 assigned-clocks = <&g 1998 assigned-clocks = <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>;
2055 assigned-clock-rates 1999 assigned-clock-rates = <100000000>;
2056 2000
2057 power-domains = <&gcc 2001 power-domains = <&gcc PCIE_3A_GDSC>;
>> 2002 required-opps = <&rpmhpd_opp_nom>;
2058 2003
2059 resets = <&gcc GCC_PC 2004 resets = <&gcc GCC_PCIE_3A_PHY_BCR>;
2060 reset-names = "phy"; 2005 reset-names = "phy";
2061 2006
2062 qcom,4ln-config-sel = 2007 qcom,4ln-config-sel = <&tcsr 0xa044 1>;
2063 2008
2064 #clock-cells = <0>; 2009 #clock-cells = <0>;
2065 clock-output-names = 2010 clock-output-names = "pcie_3a_pipe_clk";
2066 2011
2067 #phy-cells = <0>; 2012 #phy-cells = <0>;
2068 2013
2069 status = "disabled"; 2014 status = "disabled";
2070 }; 2015 };
2071 2016
2072 pcie2b: pcie@1c18000 { 2017 pcie2b: pcie@1c18000 {
2073 device_type = "pci"; 2018 device_type = "pci";
2074 compatible = "qcom,pc 2019 compatible = "qcom,pcie-sc8280xp";
2075 reg = <0x0 0x01c18000 2020 reg = <0x0 0x01c18000 0x0 0x3000>,
2076 <0x0 0x38000000 2021 <0x0 0x38000000 0x0 0xf1d>,
2077 <0x0 0x38000f20 2022 <0x0 0x38000f20 0x0 0xa8>,
2078 <0x0 0x38001000 2023 <0x0 0x38001000 0x0 0x1000>,
2079 <0x0 0x38100000 2024 <0x0 0x38100000 0x0 0x100000>,
2080 <0x0 0x01c1b000 2025 <0x0 0x01c1b000 0x0 0x1000>;
2081 reg-names = "parf", " 2026 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2082 #address-cells = <3>; 2027 #address-cells = <3>;
2083 #size-cells = <2>; 2028 #size-cells = <2>;
2084 ranges = <0x01000000 2029 ranges = <0x01000000 0x0 0x00000000 0x0 0x38200000 0x0 0x100000>,
2085 <0x02000000 2030 <0x02000000 0x0 0x38300000 0x0 0x38300000 0x0 0x1d00000>;
2086 bus-range = <0x00 0xf 2031 bus-range = <0x00 0xff>;
2087 2032
2088 dma-coherent; 2033 dma-coherent;
2089 2034
2090 linux,pci-domain = <3 2035 linux,pci-domain = <3>;
2091 num-lanes = <2>; 2036 num-lanes = <2>;
2092 2037
2093 msi-map = <0x0 &its 0 <<
2094 <<
2095 interrupts = <GIC_SPI 2038 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
2096 <GIC_SPI 2039 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
2097 <GIC_SPI 2040 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
2098 <GIC_SPI 2041 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
2099 interrupt-names = "ms 2042 interrupt-names = "msi0", "msi1", "msi2", "msi3";
2100 2043
2101 #interrupt-cells = <1 2044 #interrupt-cells = <1>;
2102 interrupt-map-mask = 2045 interrupt-map-mask = <0 0 0 0x7>;
2103 interrupt-map = <0 0 2046 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
2104 <0 0 2047 <0 0 0 2 &intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
2105 <0 0 2048 <0 0 0 3 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
2106 <0 0 2049 <0 0 0 4 &intc 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>;
2107 2050
2108 clocks = <&gcc GCC_PC 2051 clocks = <&gcc GCC_PCIE_2B_AUX_CLK>,
2109 <&gcc GCC_PC 2052 <&gcc GCC_PCIE_2B_CFG_AHB_CLK>,
2110 <&gcc GCC_PC 2053 <&gcc GCC_PCIE_2B_MSTR_AXI_CLK>,
2111 <&gcc GCC_PC 2054 <&gcc GCC_PCIE_2B_SLV_AXI_CLK>,
2112 <&gcc GCC_PC 2055 <&gcc GCC_PCIE_2B_SLV_Q2A_AXI_CLK>,
2113 <&gcc GCC_DD 2056 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
2114 <&gcc GCC_AG 2057 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
2115 <&gcc GCC_AG 2058 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
2116 clock-names = "aux", 2059 clock-names = "aux",
2117 "cfg", 2060 "cfg",
2118 "bus_ma 2061 "bus_master",
2119 "bus_sl 2062 "bus_slave",
2120 "slave_ 2063 "slave_q2a",
2121 "ddrss_ 2064 "ddrss_sf_tbu",
2122 "noc_ag 2065 "noc_aggr_4",
2123 "noc_ag 2066 "noc_aggr_south_sf";
2124 2067
2125 assigned-clocks = <&g 2068 assigned-clocks = <&gcc GCC_PCIE_2B_AUX_CLK>;
2126 assigned-clock-rates 2069 assigned-clock-rates = <19200000>;
2127 2070
2128 interconnects = <&agg 2071 interconnects = <&aggre2_noc MASTER_PCIE_2B 0 &mc_virt SLAVE_EBI1 0>,
2129 <&gem 2072 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2B 0>;
2130 interconnect-names = 2073 interconnect-names = "pcie-mem", "cpu-pcie";
2131 2074
2132 resets = <&gcc GCC_PC 2075 resets = <&gcc GCC_PCIE_2B_BCR>;
2133 reset-names = "pci"; 2076 reset-names = "pci";
2134 2077
2135 power-domains = <&gcc 2078 power-domains = <&gcc PCIE_2B_GDSC>;
2136 required-opps = <&rpm 2079 required-opps = <&rpmhpd_opp_nom>;
2137 2080
2138 phys = <&pcie2b_phy>; 2081 phys = <&pcie2b_phy>;
2139 phy-names = "pciephy" 2082 phy-names = "pciephy";
2140 2083
2141 status = "disabled"; 2084 status = "disabled";
2142 <<
2143 pcie2b_port0: pcie@0 <<
2144 device_type = <<
2145 reg = <0x0 0x <<
2146 bus-range = < <<
2147 <<
2148 #address-cell <<
2149 #size-cells = <<
2150 ranges; <<
2151 }; <<
2152 }; 2085 };
2153 2086
2154 pcie2b_phy: phy@1c1e000 { 2087 pcie2b_phy: phy@1c1e000 {
2155 compatible = "qcom,sc 2088 compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy";
2156 reg = <0x0 0x01c1e000 2089 reg = <0x0 0x01c1e000 0x0 0x2000>;
2157 2090
2158 clocks = <&gcc GCC_PC 2091 clocks = <&gcc GCC_PCIE_2B_AUX_CLK>,
2159 <&gcc GCC_PC 2092 <&gcc GCC_PCIE_2B_CFG_AHB_CLK>,
2160 <&gcc GCC_PC 2093 <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
2161 <&gcc GCC_PC 2094 <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>,
2162 <&gcc GCC_PC 2095 <&gcc GCC_PCIE_2B_PIPE_CLK>,
2163 <&gcc GCC_PC 2096 <&gcc GCC_PCIE_2B_PIPEDIV2_CLK>;
2164 clock-names = "aux", 2097 clock-names = "aux", "cfg_ahb", "ref", "rchng",
2165 "pipe", 2098 "pipe", "pipediv2";
2166 2099
2167 assigned-clocks = <&g 2100 assigned-clocks = <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>;
2168 assigned-clock-rates 2101 assigned-clock-rates = <100000000>;
2169 2102
2170 power-domains = <&gcc 2103 power-domains = <&gcc PCIE_2B_GDSC>;
>> 2104 required-opps = <&rpmhpd_opp_nom>;
2171 2105
2172 resets = <&gcc GCC_PC 2106 resets = <&gcc GCC_PCIE_2B_PHY_BCR>;
2173 reset-names = "phy"; 2107 reset-names = "phy";
2174 2108
2175 #clock-cells = <0>; 2109 #clock-cells = <0>;
2176 clock-output-names = 2110 clock-output-names = "pcie_2b_pipe_clk";
2177 2111
2178 #phy-cells = <0>; 2112 #phy-cells = <0>;
2179 2113
2180 status = "disabled"; 2114 status = "disabled";
2181 }; 2115 };
2182 2116
2183 pcie2a: pcie@1c20000 { 2117 pcie2a: pcie@1c20000 {
2184 device_type = "pci"; 2118 device_type = "pci";
2185 compatible = "qcom,pc 2119 compatible = "qcom,pcie-sc8280xp";
2186 reg = <0x0 0x01c20000 2120 reg = <0x0 0x01c20000 0x0 0x3000>,
2187 <0x0 0x3c000000 2121 <0x0 0x3c000000 0x0 0xf1d>,
2188 <0x0 0x3c000f20 2122 <0x0 0x3c000f20 0x0 0xa8>,
2189 <0x0 0x3c001000 2123 <0x0 0x3c001000 0x0 0x1000>,
2190 <0x0 0x3c100000 2124 <0x0 0x3c100000 0x0 0x100000>,
2191 <0x0 0x01c23000 2125 <0x0 0x01c23000 0x0 0x1000>;
2192 reg-names = "parf", " 2126 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2193 #address-cells = <3>; 2127 #address-cells = <3>;
2194 #size-cells = <2>; 2128 #size-cells = <2>;
2195 ranges = <0x01000000 2129 ranges = <0x01000000 0x0 0x00000000 0x0 0x3c200000 0x0 0x100000>,
2196 <0x02000000 2130 <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>;
2197 bus-range = <0x00 0xf 2131 bus-range = <0x00 0xff>;
2198 2132
2199 dma-coherent; 2133 dma-coherent;
2200 2134
2201 linux,pci-domain = <2 2135 linux,pci-domain = <2>;
2202 num-lanes = <4>; 2136 num-lanes = <4>;
2203 2137
2204 msi-map = <0x0 &its 0 <<
2205 <<
2206 interrupts = <GIC_SPI 2138 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
2207 <GIC_SPI 2139 <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>,
2208 <GIC_SPI 2140 <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>,
2209 <GIC_SPI 2141 <GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH>;
2210 interrupt-names = "ms 2142 interrupt-names = "msi0", "msi1", "msi2", "msi3";
2211 2143
2212 #interrupt-cells = <1 2144 #interrupt-cells = <1>;
2213 interrupt-map-mask = 2145 interrupt-map-mask = <0 0 0 0x7>;
2214 interrupt-map = <0 0 2146 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>,
2215 <0 0 2147 <0 0 0 2 &intc 0 0 GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>,
2216 <0 0 2148 <0 0 0 3 &intc 0 0 GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>,
2217 <0 0 2149 <0 0 0 4 &intc 0 0 GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>;
2218 2150
2219 clocks = <&gcc GCC_PC 2151 clocks = <&gcc GCC_PCIE_2A_AUX_CLK>,
2220 <&gcc GCC_PC 2152 <&gcc GCC_PCIE_2A_CFG_AHB_CLK>,
2221 <&gcc GCC_PC 2153 <&gcc GCC_PCIE_2A_MSTR_AXI_CLK>,
2222 <&gcc GCC_PC 2154 <&gcc GCC_PCIE_2A_SLV_AXI_CLK>,
2223 <&gcc GCC_PC 2155 <&gcc GCC_PCIE_2A_SLV_Q2A_AXI_CLK>,
2224 <&gcc GCC_DD 2156 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
2225 <&gcc GCC_AG 2157 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
2226 <&gcc GCC_AG 2158 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
2227 clock-names = "aux", 2159 clock-names = "aux",
2228 "cfg", 2160 "cfg",
2229 "bus_ma 2161 "bus_master",
2230 "bus_sl 2162 "bus_slave",
2231 "slave_ 2163 "slave_q2a",
2232 "ddrss_ 2164 "ddrss_sf_tbu",
2233 "noc_ag 2165 "noc_aggr_4",
2234 "noc_ag 2166 "noc_aggr_south_sf";
2235 2167
2236 assigned-clocks = <&g 2168 assigned-clocks = <&gcc GCC_PCIE_2A_AUX_CLK>;
2237 assigned-clock-rates 2169 assigned-clock-rates = <19200000>;
2238 2170
2239 interconnects = <&agg 2171 interconnects = <&aggre2_noc MASTER_PCIE_2A 0 &mc_virt SLAVE_EBI1 0>,
2240 <&gem 2172 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2A 0>;
2241 interconnect-names = 2173 interconnect-names = "pcie-mem", "cpu-pcie";
2242 2174
2243 resets = <&gcc GCC_PC 2175 resets = <&gcc GCC_PCIE_2A_BCR>;
2244 reset-names = "pci"; 2176 reset-names = "pci";
2245 2177
2246 power-domains = <&gcc 2178 power-domains = <&gcc PCIE_2A_GDSC>;
2247 required-opps = <&rpm 2179 required-opps = <&rpmhpd_opp_nom>;
2248 2180
2249 phys = <&pcie2a_phy>; 2181 phys = <&pcie2a_phy>;
2250 phy-names = "pciephy" 2182 phy-names = "pciephy";
2251 2183
2252 status = "disabled"; 2184 status = "disabled";
2253 <<
2254 pcie2a_port0: pcie@0 <<
2255 device_type = <<
2256 reg = <0x0 0x <<
2257 bus-range = < <<
2258 <<
2259 #address-cell <<
2260 #size-cells = <<
2261 ranges; <<
2262 }; <<
2263 }; 2185 };
2264 2186
2265 pcie2a_phy: phy@1c24000 { 2187 pcie2a_phy: phy@1c24000 {
2266 compatible = "qcom,sc 2188 compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy";
2267 reg = <0x0 0x01c24000 2189 reg = <0x0 0x01c24000 0x0 0x2000>,
2268 <0x0 0x01c26000 2190 <0x0 0x01c26000 0x0 0x2000>;
2269 2191
2270 clocks = <&gcc GCC_PC 2192 clocks = <&gcc GCC_PCIE_2A_AUX_CLK>,
2271 <&gcc GCC_PC 2193 <&gcc GCC_PCIE_2A_CFG_AHB_CLK>,
2272 <&gcc GCC_PC 2194 <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
2273 <&gcc GCC_PC 2195 <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>,
2274 <&gcc GCC_PC 2196 <&gcc GCC_PCIE_2A_PIPE_CLK>,
2275 <&gcc GCC_PC 2197 <&gcc GCC_PCIE_2A_PIPEDIV2_CLK>;
2276 clock-names = "aux", 2198 clock-names = "aux", "cfg_ahb", "ref", "rchng",
2277 "pipe", 2199 "pipe", "pipediv2";
2278 2200
2279 assigned-clocks = <&g 2201 assigned-clocks = <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>;
2280 assigned-clock-rates 2202 assigned-clock-rates = <100000000>;
2281 2203
2282 power-domains = <&gcc 2204 power-domains = <&gcc PCIE_2A_GDSC>;
>> 2205 required-opps = <&rpmhpd_opp_nom>;
2283 2206
2284 resets = <&gcc GCC_PC 2207 resets = <&gcc GCC_PCIE_2A_PHY_BCR>;
2285 reset-names = "phy"; 2208 reset-names = "phy";
2286 2209
2287 qcom,4ln-config-sel = 2210 qcom,4ln-config-sel = <&tcsr 0xa044 0>;
2288 2211
2289 #clock-cells = <0>; 2212 #clock-cells = <0>;
2290 clock-output-names = 2213 clock-output-names = "pcie_2a_pipe_clk";
2291 2214
2292 #phy-cells = <0>; 2215 #phy-cells = <0>;
2293 2216
2294 status = "disabled"; 2217 status = "disabled";
2295 }; 2218 };
2296 2219
2297 ufs_mem_hc: ufs@1d84000 { 2220 ufs_mem_hc: ufs@1d84000 {
2298 compatible = "qcom,sc 2221 compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc",
2299 "jedec,u 2222 "jedec,ufs-2.0";
2300 reg = <0 0x01d84000 0 2223 reg = <0 0x01d84000 0 0x3000>;
2301 interrupts = <GIC_SPI 2224 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2302 phys = <&ufs_mem_phy> 2225 phys = <&ufs_mem_phy>;
2303 phy-names = "ufsphy"; 2226 phy-names = "ufsphy";
2304 lanes-per-direction = 2227 lanes-per-direction = <2>;
2305 #reset-cells = <1>; 2228 #reset-cells = <1>;
2306 resets = <&gcc GCC_UF 2229 resets = <&gcc GCC_UFS_PHY_BCR>;
2307 reset-names = "rst"; 2230 reset-names = "rst";
2308 2231
2309 power-domains = <&gcc 2232 power-domains = <&gcc UFS_PHY_GDSC>;
2310 required-opps = <&rpm 2233 required-opps = <&rpmhpd_opp_nom>;
2311 2234
2312 iommus = <&apps_smmu 2235 iommus = <&apps_smmu 0xe0 0x0>;
2313 dma-coherent; 2236 dma-coherent;
2314 2237
2315 clocks = <&gcc GCC_UF 2238 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
2316 <&gcc GCC_AG 2239 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2317 <&gcc GCC_UF 2240 <&gcc GCC_UFS_PHY_AHB_CLK>,
2318 <&gcc GCC_UF 2241 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2319 <&gcc GCC_UF 2242 <&gcc GCC_UFS_REF_CLKREF_CLK>,
2320 <&gcc GCC_UF 2243 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2321 <&gcc GCC_UF 2244 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2322 <&gcc GCC_UF 2245 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
2323 clock-names = "core_c 2246 clock-names = "core_clk",
2324 "bus_ag 2247 "bus_aggr_clk",
2325 "iface_ 2248 "iface_clk",
2326 "core_c 2249 "core_clk_unipro",
2327 "ref_cl 2250 "ref_clk",
2328 "tx_lan 2251 "tx_lane0_sync_clk",
2329 "rx_lan 2252 "rx_lane0_sync_clk",
2330 "rx_lan 2253 "rx_lane1_sync_clk";
2331 freq-table-hz = <7500 2254 freq-table-hz = <75000000 300000000>,
2332 <0 0> 2255 <0 0>,
2333 <0 0> 2256 <0 0>,
2334 <7500 2257 <75000000 300000000>,
2335 <0 0> 2258 <0 0>,
2336 <0 0> 2259 <0 0>,
2337 <0 0> 2260 <0 0>,
2338 <0 0> 2261 <0 0>;
2339 status = "disabled"; 2262 status = "disabled";
2340 }; 2263 };
2341 2264
2342 ufs_mem_phy: phy@1d87000 { 2265 ufs_mem_phy: phy@1d87000 {
2343 compatible = "qcom,sc 2266 compatible = "qcom,sc8280xp-qmp-ufs-phy";
2344 reg = <0 0x01d87000 0 2267 reg = <0 0x01d87000 0 0x1000>;
2345 2268
2346 clocks = <&rpmhcc RPM !! 2269 clocks = <&gcc GCC_UFS_CARD_CLKREF_CLK>,
2347 <&gcc GCC_UF !! 2270 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
2348 <&gcc GCC_UF !! 2271 clock-names = "ref", "ref_aux";
2349 clock-names = "ref", <<
2350 "ref_au <<
2351 "qref"; <<
2352 2272
2353 power-domains = <&gcc 2273 power-domains = <&gcc UFS_PHY_GDSC>;
2354 2274
2355 resets = <&ufs_mem_hc 2275 resets = <&ufs_mem_hc 0>;
2356 reset-names = "ufsphy 2276 reset-names = "ufsphy";
2357 2277
2358 #phy-cells = <0>; 2278 #phy-cells = <0>;
2359 2279
2360 status = "disabled"; 2280 status = "disabled";
2361 }; 2281 };
2362 2282
2363 ufs_card_hc: ufs@1da4000 { 2283 ufs_card_hc: ufs@1da4000 {
2364 compatible = "qcom,sc 2284 compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc",
2365 "jedec,u 2285 "jedec,ufs-2.0";
2366 reg = <0 0x01da4000 0 2286 reg = <0 0x01da4000 0 0x3000>;
2367 interrupts = <GIC_SPI 2287 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
2368 phys = <&ufs_card_phy 2288 phys = <&ufs_card_phy>;
2369 phy-names = "ufsphy"; 2289 phy-names = "ufsphy";
2370 lanes-per-direction = 2290 lanes-per-direction = <2>;
2371 #reset-cells = <1>; 2291 #reset-cells = <1>;
2372 resets = <&gcc GCC_UF 2292 resets = <&gcc GCC_UFS_CARD_BCR>;
2373 reset-names = "rst"; 2293 reset-names = "rst";
2374 2294
2375 power-domains = <&gcc 2295 power-domains = <&gcc UFS_CARD_GDSC>;
2376 2296
2377 iommus = <&apps_smmu 2297 iommus = <&apps_smmu 0x4a0 0x0>;
2378 dma-coherent; 2298 dma-coherent;
2379 2299
2380 clocks = <&gcc GCC_UF 2300 clocks = <&gcc GCC_UFS_CARD_AXI_CLK>,
2381 <&gcc GCC_AG 2301 <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>,
2382 <&gcc GCC_UF 2302 <&gcc GCC_UFS_CARD_AHB_CLK>,
2383 <&gcc GCC_UF 2303 <&gcc GCC_UFS_CARD_UNIPRO_CORE_CLK>,
2384 <&gcc GCC_UF 2304 <&gcc GCC_UFS_REF_CLKREF_CLK>,
2385 <&gcc GCC_UF 2305 <&gcc GCC_UFS_CARD_TX_SYMBOL_0_CLK>,
2386 <&gcc GCC_UF 2306 <&gcc GCC_UFS_CARD_RX_SYMBOL_0_CLK>,
2387 <&gcc GCC_UF 2307 <&gcc GCC_UFS_CARD_RX_SYMBOL_1_CLK>;
2388 clock-names = "core_c 2308 clock-names = "core_clk",
2389 "bus_ag 2309 "bus_aggr_clk",
2390 "iface_ 2310 "iface_clk",
2391 "core_c 2311 "core_clk_unipro",
2392 "ref_cl 2312 "ref_clk",
2393 "tx_lan 2313 "tx_lane0_sync_clk",
2394 "rx_lan 2314 "rx_lane0_sync_clk",
2395 "rx_lan 2315 "rx_lane1_sync_clk";
2396 freq-table-hz = <7500 2316 freq-table-hz = <75000000 300000000>,
2397 <0 0> 2317 <0 0>,
2398 <0 0> 2318 <0 0>,
2399 <7500 2319 <75000000 300000000>,
2400 <0 0> 2320 <0 0>,
2401 <0 0> 2321 <0 0>,
2402 <0 0> 2322 <0 0>,
2403 <0 0> 2323 <0 0>;
2404 status = "disabled"; 2324 status = "disabled";
2405 }; 2325 };
2406 2326
2407 ufs_card_phy: phy@1da7000 { 2327 ufs_card_phy: phy@1da7000 {
2408 compatible = "qcom,sc 2328 compatible = "qcom,sc8280xp-qmp-ufs-phy";
2409 reg = <0 0x01da7000 0 2329 reg = <0 0x01da7000 0 0x1000>;
2410 2330
2411 clocks = <&rpmhcc RPM !! 2331 clocks = <&gcc GCC_UFS_1_CARD_CLKREF_CLK>,
2412 <&gcc GCC_UF !! 2332 <&gcc GCC_UFS_CARD_PHY_AUX_CLK>;
2413 <&gcc GCC_UF !! 2333 clock-names = "ref", "ref_aux";
2414 clock-names = "ref", <<
2415 "ref_au <<
2416 "qref"; <<
2417 2334
2418 power-domains = <&gcc 2335 power-domains = <&gcc UFS_CARD_GDSC>;
2419 2336
2420 resets = <&ufs_card_h 2337 resets = <&ufs_card_hc 0>;
2421 reset-names = "ufsphy 2338 reset-names = "ufsphy";
2422 2339
2423 #phy-cells = <0>; 2340 #phy-cells = <0>;
2424 2341
2425 status = "disabled"; 2342 status = "disabled";
2426 }; 2343 };
2427 2344
2428 tcsr_mutex: hwlock@1f40000 { 2345 tcsr_mutex: hwlock@1f40000 {
2429 compatible = "qcom,tc 2346 compatible = "qcom,tcsr-mutex";
2430 reg = <0x0 0x01f40000 2347 reg = <0x0 0x01f40000 0x0 0x20000>;
2431 #hwlock-cells = <1>; 2348 #hwlock-cells = <1>;
2432 }; 2349 };
2433 2350
2434 tcsr: syscon@1fc0000 { 2351 tcsr: syscon@1fc0000 {
2435 compatible = "qcom,sc 2352 compatible = "qcom,sc8280xp-tcsr", "syscon";
2436 reg = <0x0 0x01fc0000 2353 reg = <0x0 0x01fc0000 0x0 0x30000>;
2437 }; 2354 };
2438 2355
2439 gpu: gpu@3d00000 { 2356 gpu: gpu@3d00000 {
2440 compatible = "qcom,ad 2357 compatible = "qcom,adreno-690.0", "qcom,adreno";
2441 2358
2442 reg = <0 0x03d00000 0 2359 reg = <0 0x03d00000 0 0x40000>,
2443 <0 0x03d9e000 0 2360 <0 0x03d9e000 0 0x1000>,
2444 <0 0x03d61000 0 2361 <0 0x03d61000 0 0x800>;
2445 reg-names = "kgsl_3d0 2362 reg-names = "kgsl_3d0_reg_memory",
2446 "cx_mem", 2363 "cx_mem",
2447 "cx_dbgc" 2364 "cx_dbgc";
2448 interrupts = <GIC_SPI 2365 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2449 iommus = <&gpu_smmu 0 2366 iommus = <&gpu_smmu 0 0xc00>, <&gpu_smmu 1 0xc00>;
2450 operating-points-v2 = 2367 operating-points-v2 = <&gpu_opp_table>;
2451 2368
2452 qcom,gmu = <&gmu>; 2369 qcom,gmu = <&gmu>;
2453 interconnects = <&gem 2370 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
2454 interconnect-names = 2371 interconnect-names = "gfx-mem";
2455 #cooling-cells = <2>; 2372 #cooling-cells = <2>;
2456 2373
2457 status = "disabled"; 2374 status = "disabled";
2458 2375
2459 gpu_opp_table: opp-ta 2376 gpu_opp_table: opp-table {
2460 compatible = 2377 compatible = "operating-points-v2";
2461 2378
2462 opp-270000000 2379 opp-270000000 {
2463 opp-h 2380 opp-hz = /bits/ 64 <270000000>;
2464 opp-l 2381 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2465 opp-p 2382 opp-peak-kBps = <451000>;
2466 }; 2383 };
2467 2384
2468 opp-410000000 2385 opp-410000000 {
2469 opp-h 2386 opp-hz = /bits/ 64 <410000000>;
2470 opp-l 2387 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2471 opp-p 2388 opp-peak-kBps = <1555000>;
2472 }; 2389 };
2473 2390
2474 opp-500000000 2391 opp-500000000 {
2475 opp-h 2392 opp-hz = /bits/ 64 <500000000>;
2476 opp-l 2393 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2477 opp-p 2394 opp-peak-kBps = <1555000>;
2478 }; 2395 };
2479 2396
2480 opp-547000000 2397 opp-547000000 {
2481 opp-h 2398 opp-hz = /bits/ 64 <547000000>;
2482 opp-l 2399 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2483 opp-p 2400 opp-peak-kBps = <1555000>;
2484 }; 2401 };
2485 2402
2486 opp-606000000 2403 opp-606000000 {
2487 opp-h 2404 opp-hz = /bits/ 64 <606000000>;
2488 opp-l 2405 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2489 opp-p 2406 opp-peak-kBps = <2736000>;
2490 }; 2407 };
2491 2408
2492 opp-640000000 2409 opp-640000000 {
2493 opp-h 2410 opp-hz = /bits/ 64 <640000000>;
2494 opp-l 2411 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2495 opp-p 2412 opp-peak-kBps = <2736000>;
2496 }; 2413 };
2497 2414
2498 opp-655000000 2415 opp-655000000 {
2499 opp-h 2416 opp-hz = /bits/ 64 <655000000>;
2500 opp-l 2417 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2501 opp-p 2418 opp-peak-kBps = <2736000>;
2502 }; 2419 };
2503 2420
2504 opp-690000000 2421 opp-690000000 {
2505 opp-h 2422 opp-hz = /bits/ 64 <690000000>;
2506 opp-l 2423 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2507 opp-p 2424 opp-peak-kBps = <2736000>;
2508 }; 2425 };
2509 }; 2426 };
2510 }; 2427 };
2511 2428
2512 gmu: gmu@3d6a000 { 2429 gmu: gmu@3d6a000 {
2513 compatible = "qcom,ad 2430 compatible = "qcom,adreno-gmu-690.0", "qcom,adreno-gmu";
2514 reg = <0 0x03d6a000 0 2431 reg = <0 0x03d6a000 0 0x34000>,
2515 <0 0x03de0000 0 2432 <0 0x03de0000 0 0x10000>,
2516 <0 0x0b290000 0 2433 <0 0x0b290000 0 0x10000>;
2517 reg-names = "gmu", "r 2434 reg-names = "gmu", "rscc", "gmu_pdc";
2518 interrupts = <GIC_SPI 2435 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2519 <GIC_SPI 2436 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2520 interrupt-names = "hf 2437 interrupt-names = "hfi", "gmu";
2521 clocks = <&gpucc GPU_ 2438 clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
2522 <&gpucc GPU_ 2439 <&gpucc GPU_CC_CXO_CLK>,
2523 <&gcc GCC_DD 2440 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2524 <&gcc GCC_GP 2441 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2525 <&gpucc GPU_ 2442 <&gpucc GPU_CC_AHB_CLK>,
2526 <&gpucc GPU_ 2443 <&gpucc GPU_CC_HUB_CX_INT_CLK>,
2527 <&gpucc GPU_ 2444 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
2528 clock-names = "gmu", 2445 clock-names = "gmu",
2529 "cxo", 2446 "cxo",
2530 "axi", 2447 "axi",
2531 "memnoc 2448 "memnoc",
2532 "ahb", 2449 "ahb",
2533 "hub", 2450 "hub",
2534 "smmu_v 2451 "smmu_vote";
2535 power-domains = <&gpu 2452 power-domains = <&gpucc GPU_CC_CX_GDSC>,
2536 <&gpu 2453 <&gpucc GPU_CC_GX_GDSC>;
2537 power-domain-names = 2454 power-domain-names = "cx",
2538 2455 "gx";
2539 iommus = <&gpu_smmu 5 2456 iommus = <&gpu_smmu 5 0xc00>;
2540 operating-points-v2 = 2457 operating-points-v2 = <&gmu_opp_table>;
2541 2458
2542 gmu_opp_table: opp-ta 2459 gmu_opp_table: opp-table {
2543 compatible = 2460 compatible = "operating-points-v2";
2544 2461
2545 opp-200000000 2462 opp-200000000 {
2546 opp-h 2463 opp-hz = /bits/ 64 <200000000>;
2547 opp-l 2464 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2548 }; 2465 };
2549 2466
2550 opp-500000000 2467 opp-500000000 {
2551 opp-h 2468 opp-hz = /bits/ 64 <500000000>;
2552 opp-l 2469 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2553 }; 2470 };
2554 }; 2471 };
2555 }; 2472 };
2556 2473
2557 gpucc: clock-controller@3d900 2474 gpucc: clock-controller@3d90000 {
2558 compatible = "qcom,sc 2475 compatible = "qcom,sc8280xp-gpucc";
2559 reg = <0 0x03d90000 0 2476 reg = <0 0x03d90000 0 0x9000>;
2560 clocks = <&rpmhcc RPM 2477 clocks = <&rpmhcc RPMH_CXO_CLK>,
2561 <&gcc GCC_GP 2478 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2562 <&gcc GCC_GP 2479 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2563 clock-names = "bi_tcx 2480 clock-names = "bi_tcxo",
2564 "gcc_gp 2481 "gcc_gpu_gpll0_clk_src",
2565 "gcc_gp 2482 "gcc_gpu_gpll0_div_clk_src";
2566 2483
2567 power-domains = <&rpm 2484 power-domains = <&rpmhpd SC8280XP_GFX>;
2568 #clock-cells = <1>; 2485 #clock-cells = <1>;
2569 #reset-cells = <1>; 2486 #reset-cells = <1>;
2570 #power-domain-cells = 2487 #power-domain-cells = <1>;
2571 }; 2488 };
2572 2489
2573 gpu_smmu: iommu@3da0000 { 2490 gpu_smmu: iommu@3da0000 {
2574 compatible = "qcom,sc 2491 compatible = "qcom,sc8280xp-smmu-500", "qcom,adreno-smmu",
2575 "qcom,sm 2492 "qcom,smmu-500", "arm,mmu-500";
2576 reg = <0 0x03da0000 0 2493 reg = <0 0x03da0000 0 0x20000>;
2577 #iommu-cells = <2>; 2494 #iommu-cells = <2>;
2578 #global-interrupts = 2495 #global-interrupts = <2>;
2579 interrupts = <GIC_SPI 2496 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
2580 <GIC_SPI 2497 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
2581 <GIC_SPI 2498 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
2582 <GIC_SPI 2499 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
2583 <GIC_SPI 2500 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
2584 <GIC_SPI 2501 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
2585 <GIC_SPI 2502 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
2586 <GIC_SPI 2503 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
2587 <GIC_SPI 2504 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
2588 <GIC_SPI 2505 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
2589 <GIC_SPI 2506 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
2590 <GIC_SPI 2507 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
2591 <GIC_SPI 2508 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>,
2592 <GIC_SPI 2509 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>;
2593 2510
2594 clocks = <&gcc GCC_GP 2511 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2595 <&gcc GCC_GP 2512 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
2596 <&gpucc GPU_ 2513 <&gpucc GPU_CC_AHB_CLK>,
2597 <&gpucc GPU_ 2514 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
2598 <&gpucc GPU_ 2515 <&gpucc GPU_CC_CX_GMU_CLK>,
2599 <&gpucc GPU_ 2516 <&gpucc GPU_CC_HUB_CX_INT_CLK>,
2600 <&gpucc GPU_ 2517 <&gpucc GPU_CC_HUB_AON_CLK>;
2601 clock-names = "gcc_gp 2518 clock-names = "gcc_gpu_memnoc_gfx_clk",
2602 "gcc_gp 2519 "gcc_gpu_snoc_dvm_gfx_clk",
2603 "gpu_cc 2520 "gpu_cc_ahb_clk",
2604 "gpu_cc 2521 "gpu_cc_hlos1_vote_gpu_smmu_clk",
2605 "gpu_cc 2522 "gpu_cc_cx_gmu_clk",
2606 "gpu_cc 2523 "gpu_cc_hub_cx_int_clk",
2607 "gpu_cc 2524 "gpu_cc_hub_aon_clk";
2608 2525
2609 power-domains = <&gpu 2526 power-domains = <&gpucc GPU_CC_CX_GDSC>;
2610 dma-coherent; 2527 dma-coherent;
2611 }; 2528 };
2612 2529
2613 usb_0_hsphy: phy@88e5000 { 2530 usb_0_hsphy: phy@88e5000 {
2614 compatible = "qcom,sc 2531 compatible = "qcom,sc8280xp-usb-hs-phy",
2615 "qcom,us 2532 "qcom,usb-snps-hs-5nm-phy";
2616 reg = <0 0x088e5000 0 2533 reg = <0 0x088e5000 0 0x400>;
2617 clocks = <&rpmhcc RPM 2534 clocks = <&rpmhcc RPMH_CXO_CLK>;
2618 clock-names = "ref"; 2535 clock-names = "ref";
2619 resets = <&gcc GCC_QU 2536 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2620 2537
2621 #phy-cells = <0>; 2538 #phy-cells = <0>;
2622 2539
2623 status = "disabled"; 2540 status = "disabled";
2624 }; 2541 };
2625 2542
2626 usb_2_hsphy0: phy@88e7000 { 2543 usb_2_hsphy0: phy@88e7000 {
2627 compatible = "qcom,sc 2544 compatible = "qcom,sc8280xp-usb-hs-phy",
2628 "qcom,us 2545 "qcom,usb-snps-hs-5nm-phy";
2629 reg = <0 0x088e7000 0 2546 reg = <0 0x088e7000 0 0x400>;
2630 clocks = <&gcc GCC_US 2547 clocks = <&gcc GCC_USB2_HS0_CLKREF_CLK>;
2631 clock-names = "ref"; 2548 clock-names = "ref";
2632 resets = <&gcc GCC_QU 2549 resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>;
2633 2550
2634 #phy-cells = <0>; 2551 #phy-cells = <0>;
2635 2552
2636 status = "disabled"; 2553 status = "disabled";
2637 }; 2554 };
2638 2555
2639 usb_2_hsphy1: phy@88e8000 { 2556 usb_2_hsphy1: phy@88e8000 {
2640 compatible = "qcom,sc 2557 compatible = "qcom,sc8280xp-usb-hs-phy",
2641 "qcom,us 2558 "qcom,usb-snps-hs-5nm-phy";
2642 reg = <0 0x088e8000 0 2559 reg = <0 0x088e8000 0 0x400>;
2643 clocks = <&gcc GCC_US 2560 clocks = <&gcc GCC_USB2_HS1_CLKREF_CLK>;
2644 clock-names = "ref"; 2561 clock-names = "ref";
2645 resets = <&gcc GCC_QU 2562 resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>;
2646 2563
2647 #phy-cells = <0>; 2564 #phy-cells = <0>;
2648 2565
2649 status = "disabled"; 2566 status = "disabled";
2650 }; 2567 };
2651 2568
2652 usb_2_hsphy2: phy@88e9000 { 2569 usb_2_hsphy2: phy@88e9000 {
2653 compatible = "qcom,sc 2570 compatible = "qcom,sc8280xp-usb-hs-phy",
2654 "qcom,us 2571 "qcom,usb-snps-hs-5nm-phy";
2655 reg = <0 0x088e9000 0 2572 reg = <0 0x088e9000 0 0x400>;
2656 clocks = <&gcc GCC_US 2573 clocks = <&gcc GCC_USB2_HS2_CLKREF_CLK>;
2657 clock-names = "ref"; 2574 clock-names = "ref";
2658 resets = <&gcc GCC_QU 2575 resets = <&gcc GCC_QUSB2PHY_HS2_MP_BCR>;
2659 2576
2660 #phy-cells = <0>; 2577 #phy-cells = <0>;
2661 2578
2662 status = "disabled"; 2579 status = "disabled";
2663 }; 2580 };
2664 2581
2665 usb_2_hsphy3: phy@88ea000 { 2582 usb_2_hsphy3: phy@88ea000 {
2666 compatible = "qcom,sc 2583 compatible = "qcom,sc8280xp-usb-hs-phy",
2667 "qcom,us 2584 "qcom,usb-snps-hs-5nm-phy";
2668 reg = <0 0x088ea000 0 2585 reg = <0 0x088ea000 0 0x400>;
2669 clocks = <&gcc GCC_US 2586 clocks = <&gcc GCC_USB2_HS3_CLKREF_CLK>;
2670 clock-names = "ref"; 2587 clock-names = "ref";
2671 resets = <&gcc GCC_QU 2588 resets = <&gcc GCC_QUSB2PHY_HS3_MP_BCR>;
2672 2589
2673 #phy-cells = <0>; 2590 #phy-cells = <0>;
2674 2591
2675 status = "disabled"; 2592 status = "disabled";
2676 }; 2593 };
2677 2594
2678 usb_2_qmpphy0: phy@88ef000 { 2595 usb_2_qmpphy0: phy@88ef000 {
2679 compatible = "qcom,sc 2596 compatible = "qcom,sc8280xp-qmp-usb3-uni-phy";
2680 reg = <0 0x088ef000 0 2597 reg = <0 0x088ef000 0 0x2000>;
2681 2598
2682 clocks = <&gcc GCC_US 2599 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
2683 <&gcc GCC_US 2600 <&gcc GCC_USB3_MP0_CLKREF_CLK>,
2684 <&gcc GCC_US 2601 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
2685 <&gcc GCC_US 2602 <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>;
2686 clock-names = "aux", 2603 clock-names = "aux", "ref", "com_aux", "pipe";
2687 2604
2688 resets = <&gcc GCC_US 2605 resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>,
2689 <&gcc GCC_US 2606 <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>;
2690 reset-names = "phy", 2607 reset-names = "phy", "phy_phy";
2691 2608
2692 power-domains = <&gcc 2609 power-domains = <&gcc USB30_MP_GDSC>;
2693 2610
2694 #clock-cells = <0>; 2611 #clock-cells = <0>;
2695 clock-output-names = 2612 clock-output-names = "usb2_phy0_pipe_clk";
2696 2613
2697 #phy-cells = <0>; 2614 #phy-cells = <0>;
2698 2615
2699 status = "disabled"; 2616 status = "disabled";
2700 }; 2617 };
2701 2618
2702 usb_2_qmpphy1: phy@88f1000 { 2619 usb_2_qmpphy1: phy@88f1000 {
2703 compatible = "qcom,sc 2620 compatible = "qcom,sc8280xp-qmp-usb3-uni-phy";
2704 reg = <0 0x088f1000 0 2621 reg = <0 0x088f1000 0 0x2000>;
2705 2622
2706 clocks = <&gcc GCC_US 2623 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
2707 <&gcc GCC_US 2624 <&gcc GCC_USB3_MP1_CLKREF_CLK>,
2708 <&gcc GCC_US 2625 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
2709 <&gcc GCC_US 2626 <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>;
2710 clock-names = "aux", 2627 clock-names = "aux", "ref", "com_aux", "pipe";
2711 2628
2712 resets = <&gcc GCC_US 2629 resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>,
2713 <&gcc GCC_US 2630 <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>;
2714 reset-names = "phy", 2631 reset-names = "phy", "phy_phy";
2715 2632
2716 power-domains = <&gcc 2633 power-domains = <&gcc USB30_MP_GDSC>;
2717 2634
2718 #clock-cells = <0>; 2635 #clock-cells = <0>;
2719 clock-output-names = 2636 clock-output-names = "usb2_phy1_pipe_clk";
2720 2637
2721 #phy-cells = <0>; 2638 #phy-cells = <0>;
2722 2639
2723 status = "disabled"; 2640 status = "disabled";
2724 }; 2641 };
2725 2642
2726 remoteproc_adsp: remoteproc@3 2643 remoteproc_adsp: remoteproc@3000000 {
2727 compatible = "qcom,sc 2644 compatible = "qcom,sc8280xp-adsp-pas";
2728 reg = <0 0x03000000 0 2645 reg = <0 0x03000000 0 0x100>;
2729 2646
2730 interrupts-extended = !! 2647 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
2731 2648 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
2732 2649 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
2733 2650 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
2734 2651 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>,
2735 2652 <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>;
2736 interrupt-names = "wd 2653 interrupt-names = "wdog", "fatal", "ready",
2737 "ha 2654 "handover", "stop-ack", "shutdown-ack";
2738 2655
2739 clocks = <&rpmhcc RPM 2656 clocks = <&rpmhcc RPMH_CXO_CLK>;
2740 clock-names = "xo"; 2657 clock-names = "xo";
2741 2658
2742 power-domains = <&rpm 2659 power-domains = <&rpmhpd SC8280XP_LCX>,
2743 <&rpm 2660 <&rpmhpd SC8280XP_LMX>;
2744 power-domain-names = 2661 power-domain-names = "lcx", "lmx";
2745 2662
2746 memory-region = <&pil 2663 memory-region = <&pil_adsp_mem>;
2747 2664
2748 qcom,qmp = <&aoss_qmp 2665 qcom,qmp = <&aoss_qmp>;
2749 2666
2750 qcom,smem-states = <& 2667 qcom,smem-states = <&smp2p_adsp_out 0>;
2751 qcom,smem-state-names 2668 qcom,smem-state-names = "stop";
2752 2669
2753 status = "disabled"; 2670 status = "disabled";
2754 2671
2755 remoteproc_adsp_glink 2672 remoteproc_adsp_glink: glink-edge {
2756 interrupts-ex 2673 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
2757 2674 IPCC_MPROC_SIGNAL_GLINK_QMP
2758 2675 IRQ_TYPE_EDGE_RISING>;
2759 mboxes = <&ip 2676 mboxes = <&ipcc IPCC_CLIENT_LPASS
2760 2677 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2761 2678
2762 label = "lpas 2679 label = "lpass";
2763 qcom,remote-p 2680 qcom,remote-pid = <2>;
2764 2681
2765 gpr { 2682 gpr {
2766 compa 2683 compatible = "qcom,gpr";
2767 qcom, 2684 qcom,glink-channels = "adsp_apps";
2768 qcom, 2685 qcom,domain = <GPR_DOMAIN_ID_ADSP>;
2769 qcom, 2686 qcom,intents = <512 20>;
2770 #addr 2687 #address-cells = <1>;
2771 #size 2688 #size-cells = <0>;
2772 2689
2773 q6apm 2690 q6apm: service@1 {
2774 2691 compatible = "qcom,q6apm";
2775 2692 reg = <GPR_APM_MODULE_IID>;
2776 2693 #sound-dai-cells = <0>;
2777 2694 qcom,protection-domain = "avs/audio",
2778 2695 "msm/adsp/audio_pd";
2779 2696 q6apmdai: dais {
2780 2697 compatible = "qcom,q6apm-dais";
2781 2698 iommus = <&apps_smmu 0x0c01 0x0>;
2782 2699 };
2783 2700
2784 2701 q6apmbedai: bedais {
2785 2702 compatible = "qcom,q6apm-lpass-dais";
2786 2703 #sound-dai-cells = <1>;
2787 2704 };
2788 }; 2705 };
2789 2706
2790 q6prm 2707 q6prm: service@2 {
2791 2708 compatible = "qcom,q6prm";
2792 2709 reg = <GPR_PRM_MODULE_IID>;
2793 2710 qcom,protection-domain = "avs/audio",
2794 2711 "msm/adsp/audio_pd";
2795 2712 q6prmcc: clock-controller {
2796 2713 compatible = "qcom,q6prm-lpass-clocks";
2797 2714 #clock-cells = <2>;
2798 2715 };
2799 }; 2716 };
2800 }; 2717 };
2801 }; 2718 };
2802 }; 2719 };
2803 2720
2804 rxmacro: rxmacro@3200000 { 2721 rxmacro: rxmacro@3200000 {
2805 compatible = "qcom,sc 2722 compatible = "qcom,sc8280xp-lpass-rx-macro";
2806 reg = <0 0x03200000 0 2723 reg = <0 0x03200000 0 0x1000>;
2807 clocks = <&q6prmcc LP 2724 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2808 <&q6prmcc LP 2725 <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2809 <&q6prmcc LP 2726 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2810 <&q6prmcc LP 2727 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2811 <&vamacro>; 2728 <&vamacro>;
2812 clock-names = "mclk", 2729 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2813 assigned-clocks = <&q 2730 assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2814 <&q 2731 <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2815 assigned-clock-rates 2732 assigned-clock-rates = <19200000>, <19200000>;
2816 2733
2817 clock-output-names = 2734 clock-output-names = "mclk";
2818 #clock-cells = <0>; 2735 #clock-cells = <0>;
2819 #sound-dai-cells = <1 2736 #sound-dai-cells = <1>;
2820 2737
2821 pinctrl-names = "defa 2738 pinctrl-names = "default";
2822 pinctrl-0 = <&rx_swr_ 2739 pinctrl-0 = <&rx_swr_default>;
2823 2740
2824 status = "disabled"; 2741 status = "disabled";
2825 }; 2742 };
2826 2743
2827 swr1: soundwire@3210000 { !! 2744 swr1: soundwire-controller@3210000 {
2828 compatible = "qcom,so 2745 compatible = "qcom,soundwire-v1.6.0";
2829 reg = <0 0x03210000 0 2746 reg = <0 0x03210000 0 0x2000>;
2830 interrupts = <GIC_SPI 2747 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
2831 clocks = <&rxmacro>; 2748 clocks = <&rxmacro>;
2832 clock-names = "iface" 2749 clock-names = "iface";
2833 resets = <&lpass_audi 2750 resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>;
2834 reset-names = "swr_au 2751 reset-names = "swr_audio_cgcr";
2835 label = "RX"; 2752 label = "RX";
2836 2753
2837 qcom,din-ports = <0>; 2754 qcom,din-ports = <0>;
2838 qcom,dout-ports = <5> 2755 qcom,dout-ports = <5>;
2839 2756
2840 qcom,ports-sinterval- 2757 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
2841 qcom,ports-offset1 = 2758 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>;
2842 qcom,ports-offset2 = 2759 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>;
2843 qcom,ports-hstart = 2760 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0x00 0xff 0xff>;
2844 qcom,ports-hstop = 2761 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0x0f 0xff 0xff>;
2845 qcom,ports-word-lengt 2762 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2846 qcom,ports-block-pack 2763 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff>;
2847 qcom,ports-lane-contr 2764 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2848 qcom,ports-block-grou 2765 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2849 2766
2850 #sound-dai-cells = <1 2767 #sound-dai-cells = <1>;
2851 #address-cells = <2>; 2768 #address-cells = <2>;
2852 #size-cells = <0>; 2769 #size-cells = <0>;
2853 2770
2854 status = "disabled"; 2771 status = "disabled";
2855 }; 2772 };
2856 2773
2857 txmacro: txmacro@3220000 { 2774 txmacro: txmacro@3220000 {
2858 compatible = "qcom,sc 2775 compatible = "qcom,sc8280xp-lpass-tx-macro";
2859 reg = <0 0x03220000 0 2776 reg = <0 0x03220000 0 0x1000>;
2860 pinctrl-names = "defa 2777 pinctrl-names = "default";
2861 pinctrl-0 = <&tx_swr_ 2778 pinctrl-0 = <&tx_swr_default>;
2862 clocks = <&q6prmcc LP 2779 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2863 <&q6prmcc LP 2780 <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2864 <&q6prmcc LP 2781 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2865 <&q6prmcc LP 2782 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2866 <&vamacro>; 2783 <&vamacro>;
2867 2784
2868 clock-names = "mclk", 2785 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2869 assigned-clocks = <&q 2786 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2870 <&q 2787 <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2871 assigned-clock-rates 2788 assigned-clock-rates = <19200000>, <19200000>;
2872 clock-output-names = 2789 clock-output-names = "mclk";
2873 2790
2874 #clock-cells = <0>; 2791 #clock-cells = <0>;
2875 #sound-dai-cells = <1 2792 #sound-dai-cells = <1>;
2876 2793
2877 status = "disabled"; 2794 status = "disabled";
2878 }; 2795 };
2879 2796
2880 wsamacro: codec@3240000 { 2797 wsamacro: codec@3240000 {
2881 compatible = "qcom,sc 2798 compatible = "qcom,sc8280xp-lpass-wsa-macro";
2882 reg = <0 0x03240000 0 2799 reg = <0 0x03240000 0 0x1000>;
2883 clocks = <&q6prmcc LP 2800 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2884 <&q6prmcc LP 2801 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2885 <&q6prmcc LP 2802 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2886 <&q6prmcc LP 2803 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2887 <&vamacro>; 2804 <&vamacro>;
2888 clock-names = "mclk", 2805 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2889 assigned-clocks = <&q 2806 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2890 <&q 2807 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2891 assigned-clock-rates 2808 assigned-clock-rates = <19200000>, <19200000>;
2892 2809
2893 #clock-cells = <0>; 2810 #clock-cells = <0>;
2894 clock-output-names = 2811 clock-output-names = "mclk";
2895 #sound-dai-cells = <1 2812 #sound-dai-cells = <1>;
2896 2813
2897 pinctrl-names = "defa 2814 pinctrl-names = "default";
2898 pinctrl-0 = <&wsa_swr 2815 pinctrl-0 = <&wsa_swr_default>;
2899 2816
2900 status = "disabled"; 2817 status = "disabled";
2901 }; 2818 };
2902 2819
2903 swr0: soundwire@3250000 { !! 2820 swr0: soundwire-controller@3250000 {
2904 reg = <0 0x03250000 0 2821 reg = <0 0x03250000 0 0x2000>;
2905 compatible = "qcom,so 2822 compatible = "qcom,soundwire-v1.6.0";
2906 interrupts = <GIC_SPI 2823 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
2907 clocks = <&wsamacro>; 2824 clocks = <&wsamacro>;
2908 clock-names = "iface" 2825 clock-names = "iface";
2909 resets = <&lpass_audi 2826 resets = <&lpass_audiocc LPASS_AUDIO_SWR_WSA_CGCR>;
2910 reset-names = "swr_au 2827 reset-names = "swr_audio_cgcr";
2911 label = "WSA"; 2828 label = "WSA";
2912 2829
2913 qcom,din-ports = <2>; 2830 qcom,din-ports = <2>;
2914 qcom,dout-ports = <6> 2831 qcom,dout-ports = <6>;
2915 2832
2916 qcom,ports-sinterval- 2833 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2917 qcom,ports-offset1 = 2834 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2918 qcom,ports-offset2 = 2835 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2919 qcom,ports-hstart = 2836 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2920 qcom,ports-hstop = 2837 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2921 qcom,ports-word-lengt 2838 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2922 qcom,ports-block-pack 2839 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
2923 qcom,ports-block-grou 2840 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2924 qcom,ports-lane-contr 2841 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2925 2842
2926 #sound-dai-cells = <1 2843 #sound-dai-cells = <1>;
2927 #address-cells = <2>; 2844 #address-cells = <2>;
2928 #size-cells = <0>; 2845 #size-cells = <0>;
2929 2846
2930 status = "disabled"; 2847 status = "disabled";
2931 }; 2848 };
2932 2849
2933 lpass_audiocc: clock-controll 2850 lpass_audiocc: clock-controller@32a9000 {
2934 compatible = "qcom,sc 2851 compatible = "qcom,sc8280xp-lpassaudiocc";
2935 reg = <0 0x032a9000 0 2852 reg = <0 0x032a9000 0 0x1000>;
2936 #clock-cells = <1>; 2853 #clock-cells = <1>;
2937 #reset-cells = <1>; 2854 #reset-cells = <1>;
2938 }; 2855 };
2939 2856
2940 swr2: soundwire@3330000 { !! 2857 swr2: soundwire-controller@3330000 {
2941 compatible = "qcom,so 2858 compatible = "qcom,soundwire-v1.6.0";
2942 reg = <0 0x03330000 0 2859 reg = <0 0x03330000 0 0x2000>;
2943 interrupts = <GIC_SPI 2860 interrupts = <GIC_SPI 959 IRQ_TYPE_LEVEL_HIGH>,
2944 <GIC_SPI 2861 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>;
2945 interrupt-names = "co 2862 interrupt-names = "core", "wakeup";
2946 2863
2947 clocks = <&txmacro>; 2864 clocks = <&txmacro>;
2948 clock-names = "iface" 2865 clock-names = "iface";
2949 resets = <&lpasscc LP 2866 resets = <&lpasscc LPASS_AUDIO_SWR_TX_CGCR>;
2950 reset-names = "swr_au 2867 reset-names = "swr_audio_cgcr";
2951 label = "TX"; 2868 label = "TX";
2952 #sound-dai-cells = <1 2869 #sound-dai-cells = <1>;
2953 #address-cells = <2>; 2870 #address-cells = <2>;
2954 #size-cells = <0>; 2871 #size-cells = <0>;
2955 2872
2956 qcom,din-ports = <4>; 2873 qcom,din-ports = <4>;
2957 qcom,dout-ports = <0> 2874 qcom,dout-ports = <0>;
2958 qcom,ports-sinterval- 2875 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
2959 qcom,ports-offset1 = 2876 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02 0x00>;
2960 qcom,ports-offset2 = 2877 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
2961 qcom,ports-block-pack 2878 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
2962 qcom,ports-hstart = 2879 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
2963 qcom,ports-hstop = 2880 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
2964 qcom,ports-word-lengt 2881 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
2965 qcom,ports-block-grou 2882 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
2966 qcom,ports-lane-contr 2883 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00 0x01>;
2967 2884
2968 status = "disabled"; 2885 status = "disabled";
2969 }; 2886 };
2970 2887
2971 vamacro: codec@3370000 { 2888 vamacro: codec@3370000 {
2972 compatible = "qcom,sc 2889 compatible = "qcom,sc8280xp-lpass-va-macro";
2973 reg = <0 0x03370000 0 2890 reg = <0 0x03370000 0 0x1000>;
2974 clocks = <&q6prmcc LP 2891 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2975 <&q6prmcc LP 2892 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2976 <&q6prmcc LP 2893 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2977 <&q6prmcc LP 2894 <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2978 clock-names = "mclk", 2895 clock-names = "mclk", "macro", "dcodec", "npl";
2979 assigned-clocks = <&q 2896 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2980 assigned-clock-rates 2897 assigned-clock-rates = <19200000>;
2981 2898
2982 #clock-cells = <0>; 2899 #clock-cells = <0>;
2983 clock-output-names = 2900 clock-output-names = "fsgen";
2984 #sound-dai-cells = <1 2901 #sound-dai-cells = <1>;
2985 2902
2986 status = "disabled"; 2903 status = "disabled";
2987 }; 2904 };
2988 2905
2989 lpass_tlmm: pinctrl@33c0000 { 2906 lpass_tlmm: pinctrl@33c0000 {
2990 compatible = "qcom,sc 2907 compatible = "qcom,sc8280xp-lpass-lpi-pinctrl";
2991 reg = <0 0x33c0000 0x 2908 reg = <0 0x33c0000 0x0 0x20000>,
2992 <0 0x3550000 0x 2909 <0 0x3550000 0x0 0x10000>;
2993 gpio-controller; 2910 gpio-controller;
2994 #gpio-cells = <2>; 2911 #gpio-cells = <2>;
2995 gpio-ranges = <&lpass 2912 gpio-ranges = <&lpass_tlmm 0 0 19>;
2996 2913
2997 clocks = <&q6prmcc LP 2914 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2998 <&q6prmcc LP 2915 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2999 clock-names = "core", 2916 clock-names = "core", "audio";
3000 2917
3001 status = "disabled"; 2918 status = "disabled";
3002 2919
3003 tx_swr_default: tx-sw 2920 tx_swr_default: tx-swr-default-state {
3004 clk-pins { 2921 clk-pins {
3005 pins 2922 pins = "gpio0";
3006 funct 2923 function = "swr_tx_clk";
3007 drive 2924 drive-strength = <2>;
3008 slew- 2925 slew-rate = <1>;
3009 bias- 2926 bias-disable;
3010 }; 2927 };
3011 2928
3012 data-pins { 2929 data-pins {
3013 pins 2930 pins = "gpio1", "gpio2";
3014 funct 2931 function = "swr_tx_data";
3015 drive 2932 drive-strength = <2>;
3016 slew- 2933 slew-rate = <1>;
3017 bias- 2934 bias-bus-hold;
3018 }; 2935 };
3019 }; 2936 };
3020 2937
3021 rx_swr_default: rx-sw 2938 rx_swr_default: rx-swr-default-state {
3022 clk-pins { 2939 clk-pins {
3023 pins 2940 pins = "gpio3";
3024 funct 2941 function = "swr_rx_clk";
3025 drive 2942 drive-strength = <2>;
3026 slew- 2943 slew-rate = <1>;
3027 bias- 2944 bias-disable;
3028 }; 2945 };
3029 2946
3030 data-pins { 2947 data-pins {
3031 pins 2948 pins = "gpio4", "gpio5";
3032 funct 2949 function = "swr_rx_data";
3033 drive 2950 drive-strength = <2>;
3034 slew- 2951 slew-rate = <1>;
3035 bias- 2952 bias-bus-hold;
3036 }; 2953 };
3037 }; 2954 };
3038 2955
3039 dmic01_default: dmic0 2956 dmic01_default: dmic01-default-state {
3040 clk-pins { 2957 clk-pins {
3041 pins 2958 pins = "gpio6";
3042 funct 2959 function = "dmic1_clk";
3043 drive 2960 drive-strength = <8>;
3044 outpu 2961 output-high;
3045 }; 2962 };
3046 2963
3047 data-pins { 2964 data-pins {
3048 pins 2965 pins = "gpio7";
3049 funct 2966 function = "dmic1_data";
3050 drive 2967 drive-strength = <8>;
3051 input 2968 input-enable;
3052 }; 2969 };
3053 }; 2970 };
3054 2971
3055 dmic01_sleep: dmic01- 2972 dmic01_sleep: dmic01-sleep-state {
3056 clk-pins { 2973 clk-pins {
3057 pins 2974 pins = "gpio6";
3058 funct 2975 function = "dmic1_clk";
3059 drive 2976 drive-strength = <2>;
3060 bias- 2977 bias-disable;
3061 outpu 2978 output-low;
3062 }; 2979 };
3063 2980
3064 data-pins { 2981 data-pins {
3065 pins 2982 pins = "gpio7";
3066 funct 2983 function = "dmic1_data";
3067 drive 2984 drive-strength = <2>;
3068 bias- 2985 bias-pull-down;
3069 input 2986 input-enable;
3070 }; 2987 };
3071 }; 2988 };
3072 2989
3073 dmic23_default: dmic2 !! 2990 dmic02_default: dmic02-default-state {
3074 clk-pins { 2991 clk-pins {
3075 pins 2992 pins = "gpio8";
3076 funct 2993 function = "dmic2_clk";
3077 drive 2994 drive-strength = <8>;
3078 outpu 2995 output-high;
3079 }; 2996 };
3080 2997
3081 data-pins { 2998 data-pins {
3082 pins 2999 pins = "gpio9";
3083 funct 3000 function = "dmic2_data";
3084 drive 3001 drive-strength = <8>;
3085 input 3002 input-enable;
3086 }; 3003 };
3087 }; 3004 };
3088 3005
3089 dmic23_sleep: dmic23- !! 3006 dmic02_sleep: dmic02-sleep-state {
3090 clk-pins { 3007 clk-pins {
3091 pins 3008 pins = "gpio8";
3092 funct 3009 function = "dmic2_clk";
3093 drive 3010 drive-strength = <2>;
3094 bias- 3011 bias-disable;
3095 outpu 3012 output-low;
3096 }; 3013 };
3097 3014
3098 data-pins { 3015 data-pins {
3099 pins 3016 pins = "gpio9";
3100 funct 3017 function = "dmic2_data";
3101 drive 3018 drive-strength = <2>;
3102 bias- 3019 bias-pull-down;
3103 input 3020 input-enable;
3104 }; 3021 };
3105 }; 3022 };
3106 3023
3107 wsa_swr_default: wsa- 3024 wsa_swr_default: wsa-swr-default-state {
3108 clk-pins { 3025 clk-pins {
3109 pins 3026 pins = "gpio10";
3110 funct 3027 function = "wsa_swr_clk";
3111 drive 3028 drive-strength = <2>;
3112 slew- 3029 slew-rate = <1>;
3113 bias- 3030 bias-disable;
3114 }; 3031 };
3115 3032
3116 data-pins { 3033 data-pins {
3117 pins 3034 pins = "gpio11";
3118 funct 3035 function = "wsa_swr_data";
3119 drive 3036 drive-strength = <2>;
3120 slew- 3037 slew-rate = <1>;
3121 bias- 3038 bias-bus-hold;
3122 }; 3039 };
3123 }; 3040 };
3124 3041
3125 wsa2_swr_default: wsa 3042 wsa2_swr_default: wsa2-swr-default-state {
3126 clk-pins { 3043 clk-pins {
3127 pins 3044 pins = "gpio15";
3128 funct 3045 function = "wsa2_swr_clk";
3129 drive 3046 drive-strength = <2>;
3130 slew- 3047 slew-rate = <1>;
3131 bias- 3048 bias-disable;
3132 }; 3049 };
3133 3050
3134 data-pins { 3051 data-pins {
3135 pins 3052 pins = "gpio16";
3136 funct 3053 function = "wsa2_swr_data";
3137 drive 3054 drive-strength = <2>;
3138 slew- 3055 slew-rate = <1>;
3139 bias- 3056 bias-bus-hold;
3140 }; 3057 };
3141 }; 3058 };
3142 }; 3059 };
3143 3060
3144 lpasscc: clock-controller@33e 3061 lpasscc: clock-controller@33e0000 {
3145 compatible = "qcom,sc 3062 compatible = "qcom,sc8280xp-lpasscc";
3146 reg = <0 0x033e0000 0 3063 reg = <0 0x033e0000 0 0x12000>;
3147 #clock-cells = <1>; 3064 #clock-cells = <1>;
3148 #reset-cells = <1>; 3065 #reset-cells = <1>;
3149 }; 3066 };
3150 3067
3151 sdc2: mmc@8804000 { 3068 sdc2: mmc@8804000 {
3152 compatible = "qcom,sc 3069 compatible = "qcom,sc8280xp-sdhci", "qcom,sdhci-msm-v5";
3153 reg = <0 0x08804000 0 3070 reg = <0 0x08804000 0 0x1000>;
3154 3071
3155 interrupts = <GIC_SPI 3072 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
3156 <GIC_SPI 3073 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
3157 interrupt-names = "hc 3074 interrupt-names = "hc_irq", "pwr_irq";
3158 3075
3159 clocks = <&gcc GCC_SD 3076 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3160 <&gcc GCC_SD 3077 <&gcc GCC_SDCC2_APPS_CLK>,
3161 <&rpmhcc RPM 3078 <&rpmhcc RPMH_CXO_CLK>;
3162 clock-names = "iface" 3079 clock-names = "iface", "core", "xo";
3163 resets = <&gcc GCC_SD 3080 resets = <&gcc GCC_SDCC2_BCR>;
3164 interconnects = <&agg 3081 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
3165 <&gem 3082 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
3166 interconnect-names = 3083 interconnect-names = "sdhc-ddr","cpu-sdhc";
3167 iommus = <&apps_smmu 3084 iommus = <&apps_smmu 0x4e0 0x0>;
3168 power-domains = <&rpm 3085 power-domains = <&rpmhpd SC8280XP_CX>;
3169 operating-points-v2 = 3086 operating-points-v2 = <&sdc2_opp_table>;
3170 bus-width = <4>; 3087 bus-width = <4>;
3171 dma-coherent; 3088 dma-coherent;
3172 3089
3173 status = "disabled"; 3090 status = "disabled";
3174 3091
3175 sdc2_opp_table: opp-t 3092 sdc2_opp_table: opp-table {
3176 compatible = 3093 compatible = "operating-points-v2";
3177 3094
3178 opp-100000000 3095 opp-100000000 {
3179 opp-h 3096 opp-hz = /bits/ 64 <100000000>;
3180 requi 3097 required-opps = <&rpmhpd_opp_low_svs>;
3181 opp-p 3098 opp-peak-kBps = <1800000 400000>;
3182 opp-a 3099 opp-avg-kBps = <100000 0>;
3183 }; 3100 };
3184 3101
3185 opp-202000000 3102 opp-202000000 {
3186 opp-h 3103 opp-hz = /bits/ 64 <202000000>;
3187 requi 3104 required-opps = <&rpmhpd_opp_svs_l1>;
3188 opp-p 3105 opp-peak-kBps = <5400000 1600000>;
3189 opp-a 3106 opp-avg-kBps = <200000 0>;
3190 }; 3107 };
3191 }; 3108 };
3192 }; 3109 };
3193 3110
3194 usb_0_qmpphy: phy@88eb000 { 3111 usb_0_qmpphy: phy@88eb000 {
3195 compatible = "qcom,sc 3112 compatible = "qcom,sc8280xp-qmp-usb43dp-phy";
3196 reg = <0 0x088eb000 0 3113 reg = <0 0x088eb000 0 0x4000>;
3197 3114
3198 clocks = <&gcc GCC_US 3115 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
3199 <&gcc GCC_US 3116 <&gcc GCC_USB4_EUD_CLKREF_CLK>,
3200 <&gcc GCC_US 3117 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
3201 <&gcc GCC_US 3118 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3202 clock-names = "aux", 3119 clock-names = "aux", "ref", "com_aux", "usb3_pipe";
3203 3120
3204 power-domains = <&gcc 3121 power-domains = <&gcc USB30_PRIM_GDSC>;
3205 3122
3206 resets = <&gcc GCC_US 3123 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
3207 <&gcc GCC_US 3124 <&gcc GCC_USB4_DP_PHY_PRIM_BCR>;
3208 reset-names = "phy", 3125 reset-names = "phy", "common";
3209 3126
3210 #clock-cells = <1>; 3127 #clock-cells = <1>;
3211 #phy-cells = <1>; 3128 #phy-cells = <1>;
3212 3129
3213 status = "disabled"; 3130 status = "disabled";
3214 3131
3215 ports { 3132 ports {
3216 #address-cell 3133 #address-cells = <1>;
3217 #size-cells = 3134 #size-cells = <0>;
3218 3135
3219 port@0 { 3136 port@0 {
3220 reg = 3137 reg = <0>;
3221 3138
3222 usb_0 3139 usb_0_qmpphy_out: endpoint {};
3223 }; 3140 };
3224 3141
3225 port@1 { <<
3226 reg = <<
3227 <<
3228 usb_0 <<
3229 <<
3230 }; <<
3231 }; <<
3232 <<
3233 port@2 { 3142 port@2 {
3234 reg = 3143 reg = <2>;
3235 3144
3236 usb_0 3145 usb_0_qmpphy_dp_in: endpoint {};
3237 }; 3146 };
3238 }; 3147 };
3239 }; 3148 };
3240 3149
3241 usb_1_hsphy: phy@8902000 { 3150 usb_1_hsphy: phy@8902000 {
3242 compatible = "qcom,sc 3151 compatible = "qcom,sc8280xp-usb-hs-phy",
3243 "qcom,us 3152 "qcom,usb-snps-hs-5nm-phy";
3244 reg = <0 0x08902000 0 3153 reg = <0 0x08902000 0 0x400>;
3245 #phy-cells = <0>; 3154 #phy-cells = <0>;
3246 3155
3247 clocks = <&rpmhcc RPM 3156 clocks = <&rpmhcc RPMH_CXO_CLK>;
3248 clock-names = "ref"; 3157 clock-names = "ref";
3249 3158
3250 resets = <&gcc GCC_QU 3159 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3251 3160
3252 status = "disabled"; 3161 status = "disabled";
3253 }; 3162 };
3254 3163
3255 usb_1_qmpphy: phy@8903000 { 3164 usb_1_qmpphy: phy@8903000 {
3256 compatible = "qcom,sc 3165 compatible = "qcom,sc8280xp-qmp-usb43dp-phy";
3257 reg = <0 0x08903000 0 3166 reg = <0 0x08903000 0 0x4000>;
3258 3167
3259 clocks = <&gcc GCC_US 3168 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
3260 <&gcc GCC_US 3169 <&gcc GCC_USB4_CLKREF_CLK>,
3261 <&gcc GCC_US 3170 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
3262 <&gcc GCC_US 3171 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
3263 clock-names = "aux", 3172 clock-names = "aux", "ref", "com_aux", "usb3_pipe";
3264 3173
3265 power-domains = <&gcc 3174 power-domains = <&gcc USB30_SEC_GDSC>;
3266 3175
3267 resets = <&gcc GCC_US 3176 resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
3268 <&gcc GCC_US 3177 <&gcc GCC_USB4_1_DP_PHY_PRIM_BCR>;
3269 reset-names = "phy", 3178 reset-names = "phy", "common";
3270 3179
3271 #clock-cells = <1>; 3180 #clock-cells = <1>;
3272 #phy-cells = <1>; 3181 #phy-cells = <1>;
3273 3182
3274 status = "disabled"; 3183 status = "disabled";
3275 3184
3276 ports { 3185 ports {
3277 #address-cell 3186 #address-cells = <1>;
3278 #size-cells = 3187 #size-cells = <0>;
3279 3188
3280 port@0 { 3189 port@0 {
3281 reg = 3190 reg = <0>;
3282 3191
3283 usb_1 3192 usb_1_qmpphy_out: endpoint {};
3284 }; 3193 };
3285 3194
3286 port@1 { <<
3287 reg = <<
3288 <<
3289 usb_1 <<
3290 <<
3291 }; <<
3292 }; <<
3293 <<
3294 port@2 { 3195 port@2 {
3295 reg = 3196 reg = <2>;
3296 3197
3297 usb_1 3198 usb_1_qmpphy_dp_in: endpoint {};
3298 }; 3199 };
3299 }; 3200 };
3300 }; 3201 };
3301 3202
3302 mdss1_dp0_phy: phy@8909a00 { 3203 mdss1_dp0_phy: phy@8909a00 {
3303 compatible = "qcom,sc 3204 compatible = "qcom,sc8280xp-dp-phy";
3304 reg = <0 0x08909a00 0 3205 reg = <0 0x08909a00 0 0x19c>,
3305 <0 0x08909200 0 3206 <0 0x08909200 0 0xec>,
3306 <0 0x08909600 0 3207 <0 0x08909600 0 0xec>,
3307 <0 0x08909000 0 3208 <0 0x08909000 0 0x1c8>;
3308 3209
3309 clocks = <&dispcc1 DI 3210 clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>,
3310 <&dispcc1 DI 3211 <&dispcc1 DISP_CC_MDSS_AHB_CLK>;
3311 clock-names = "aux", 3212 clock-names = "aux", "cfg_ahb";
3312 power-domains = <&rpm 3213 power-domains = <&rpmhpd SC8280XP_MX>;
3313 3214
3314 #clock-cells = <1>; 3215 #clock-cells = <1>;
3315 #phy-cells = <0>; 3216 #phy-cells = <0>;
3316 3217
3317 status = "disabled"; 3218 status = "disabled";
3318 }; 3219 };
3319 3220
3320 mdss1_dp1_phy: phy@890ca00 { 3221 mdss1_dp1_phy: phy@890ca00 {
3321 compatible = "qcom,sc 3222 compatible = "qcom,sc8280xp-dp-phy";
3322 reg = <0 0x0890ca00 0 3223 reg = <0 0x0890ca00 0 0x19c>,
3323 <0 0x0890c200 0 3224 <0 0x0890c200 0 0xec>,
3324 <0 0x0890c600 0 3225 <0 0x0890c600 0 0xec>,
3325 <0 0x0890c000 0 3226 <0 0x0890c000 0 0x1c8>;
3326 3227
3327 clocks = <&dispcc1 DI 3228 clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>,
3328 <&dispcc1 DI 3229 <&dispcc1 DISP_CC_MDSS_AHB_CLK>;
3329 clock-names = "aux", 3230 clock-names = "aux", "cfg_ahb";
3330 power-domains = <&rpm 3231 power-domains = <&rpmhpd SC8280XP_MX>;
3331 3232
3332 #clock-cells = <1>; 3233 #clock-cells = <1>;
3333 #phy-cells = <0>; 3234 #phy-cells = <0>;
3334 3235
3335 status = "disabled"; 3236 status = "disabled";
3336 }; 3237 };
3337 3238
3338 pmu@9091000 { 3239 pmu@9091000 {
3339 compatible = "qcom,sc 3240 compatible = "qcom,sc8280xp-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
3340 reg = <0 0x09091000 0 3241 reg = <0 0x09091000 0 0x1000>;
3341 3242
3342 interrupts = <GIC_SPI 3243 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
3343 3244
3344 interconnects = <&mc_ 3245 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>;
3345 3246
3346 operating-points-v2 = 3247 operating-points-v2 = <&llcc_bwmon_opp_table>;
3347 3248
3348 llcc_bwmon_opp_table: 3249 llcc_bwmon_opp_table: opp-table {
3349 compatible = 3250 compatible = "operating-points-v2";
3350 3251
3351 opp-0 { 3252 opp-0 {
3352 opp-p 3253 opp-peak-kBps = <762000>;
3353 }; 3254 };
3354 opp-1 { 3255 opp-1 {
3355 opp-p 3256 opp-peak-kBps = <1720000>;
3356 }; 3257 };
3357 opp-2 { 3258 opp-2 {
3358 opp-p 3259 opp-peak-kBps = <2086000>;
3359 }; 3260 };
3360 opp-3 { 3261 opp-3 {
3361 opp-p 3262 opp-peak-kBps = <2597000>;
3362 }; 3263 };
3363 opp-4 { 3264 opp-4 {
3364 opp-p 3265 opp-peak-kBps = <2929000>;
3365 }; 3266 };
3366 opp-5 { 3267 opp-5 {
3367 opp-p 3268 opp-peak-kBps = <3879000>;
3368 }; 3269 };
3369 opp-6 { 3270 opp-6 {
3370 opp-p 3271 opp-peak-kBps = <5161000>;
3371 }; 3272 };
3372 opp-7 { 3273 opp-7 {
3373 opp-p 3274 opp-peak-kBps = <5931000>;
3374 }; 3275 };
3375 opp-8 { 3276 opp-8 {
3376 opp-p 3277 opp-peak-kBps = <6515000>;
3377 }; 3278 };
3378 opp-9 { 3279 opp-9 {
3379 opp-p 3280 opp-peak-kBps = <7980000>;
3380 }; 3281 };
3381 opp-10 { 3282 opp-10 {
3382 opp-p 3283 opp-peak-kBps = <8136000>;
3383 }; 3284 };
3384 opp-11 { 3285 opp-11 {
3385 opp-p 3286 opp-peak-kBps = <10437000>;
3386 }; 3287 };
3387 opp-12 { 3288 opp-12 {
3388 opp-p 3289 opp-peak-kBps = <12191000>;
3389 }; 3290 };
3390 }; 3291 };
3391 }; 3292 };
3392 3293
3393 pmu@90b6400 { 3294 pmu@90b6400 {
3394 compatible = "qcom,sc 3295 compatible = "qcom,sc8280xp-cpu-bwmon", "qcom,sdm845-bwmon";
3395 reg = <0 0x090b6400 0 3296 reg = <0 0x090b6400 0 0x600>;
3396 3297
3397 interrupts = <GIC_SPI 3298 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
3398 3299
3399 interconnects = <&gem 3300 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>;
3400 operating-points-v2 = 3301 operating-points-v2 = <&cpu_bwmon_opp_table>;
3401 3302
3402 cpu_bwmon_opp_table: 3303 cpu_bwmon_opp_table: opp-table {
3403 compatible = 3304 compatible = "operating-points-v2";
3404 3305
3405 opp-0 { 3306 opp-0 {
3406 opp-p 3307 opp-peak-kBps = <2288000>;
3407 }; 3308 };
3408 opp-1 { 3309 opp-1 {
3409 opp-p 3310 opp-peak-kBps = <4577000>;
3410 }; 3311 };
3411 opp-2 { 3312 opp-2 {
3412 opp-p 3313 opp-peak-kBps = <7110000>;
3413 }; 3314 };
3414 opp-3 { 3315 opp-3 {
3415 opp-p 3316 opp-peak-kBps = <9155000>;
3416 }; 3317 };
3417 opp-4 { 3318 opp-4 {
3418 opp-p 3319 opp-peak-kBps = <12298000>;
3419 }; 3320 };
3420 opp-5 { 3321 opp-5 {
3421 opp-p 3322 opp-peak-kBps = <14236000>;
3422 }; 3323 };
3423 opp-6 { 3324 opp-6 {
3424 opp-p 3325 opp-peak-kBps = <15258001>;
3425 }; 3326 };
3426 }; 3327 };
3427 }; 3328 };
3428 3329
3429 system-cache-controller@92000 3330 system-cache-controller@9200000 {
3430 compatible = "qcom,sc 3331 compatible = "qcom,sc8280xp-llcc";
3431 reg = <0 0x09200000 0 3332 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>,
3432 <0 0x09300000 0 3333 <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>,
3433 <0 0x09400000 0 3334 <0 0x09400000 0 0x58000>, <0 0x09480000 0 0x58000>,
3434 <0 0x09500000 0 3335 <0 0x09500000 0 0x58000>, <0 0x09580000 0 0x58000>,
3435 <0 0x09600000 0 3336 <0 0x09600000 0 0x58000>;
3436 reg-names = "llcc0_ba 3337 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
3437 "llcc3_ba 3338 "llcc3_base", "llcc4_base", "llcc5_base",
3438 "llcc6_ba 3339 "llcc6_base", "llcc7_base", "llcc_broadcast_base";
3439 interrupts = <GIC_SPI 3340 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
3440 }; 3341 };
3441 3342
3442 usb_2: usb@a4f8800 { <<
3443 compatible = "qcom,sc <<
3444 reg = <0 0x0a4f8800 0 <<
3445 #address-cells = <2>; <<
3446 #size-cells = <2>; <<
3447 ranges; <<
3448 <<
3449 clocks = <&gcc GCC_CF <<
3450 <&gcc GCC_US <<
3451 <&gcc GCC_AG <<
3452 <&gcc GCC_US <<
3453 <&gcc GCC_US <<
3454 <&gcc GCC_AG <<
3455 <&gcc GCC_AG <<
3456 <&gcc GCC_AG <<
3457 <&gcc GCC_SY <<
3458 clock-names = "cfg_no <<
3459 "noc_ag <<
3460 <<
3461 assigned-clocks = <&g <<
3462 <&g <<
3463 assigned-clock-rates <<
3464 <<
3465 interrupts-extended = <<
3466 <<
3467 <<
3468 <<
3469 <<
3470 <<
3471 <<
3472 <<
3473 <<
3474 <<
3475 <<
3476 <<
3477 <<
3478 <<
3479 <<
3480 <<
3481 <<
3482 <<
3483 <<
3484 interrupt-names = "pw <<
3485 "pw <<
3486 "hs <<
3487 "hs <<
3488 "dp <<
3489 "dp <<
3490 "dp <<
3491 "dp <<
3492 "ss <<
3493 <<
3494 power-domains = <&gcc <<
3495 required-opps = <&rpm <<
3496 <<
3497 resets = <&gcc GCC_US <<
3498 <<
3499 interconnects = <&agg <<
3500 <&gem <<
3501 interconnect-names = <<
3502 <<
3503 wakeup-source; <<
3504 <<
3505 status = "disabled"; <<
3506 <<
3507 usb_2_dwc3: usb@a4000 <<
3508 compatible = <<
3509 reg = <0 0x0a <<
3510 interrupts = <<
3511 iommus = <&ap <<
3512 phys = <&usb_ <<
3513 <&usb_ <<
3514 <&usb_ <<
3515 <&usb_ <<
3516 phy-names = " <<
3517 " <<
3518 " <<
3519 " <<
3520 dr_mode = "ho <<
3521 }; <<
3522 }; <<
3523 <<
3524 usb_0: usb@a6f8800 { 3343 usb_0: usb@a6f8800 {
3525 compatible = "qcom,sc 3344 compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3";
3526 reg = <0 0x0a6f8800 0 3345 reg = <0 0x0a6f8800 0 0x400>;
3527 #address-cells = <2>; 3346 #address-cells = <2>;
3528 #size-cells = <2>; 3347 #size-cells = <2>;
3529 ranges; 3348 ranges;
3530 3349
3531 clocks = <&gcc GCC_CF 3350 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
3532 <&gcc GCC_US 3351 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
3533 <&gcc GCC_AG 3352 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
3534 <&gcc GCC_US 3353 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
3535 <&gcc GCC_US 3354 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3536 <&gcc GCC_AG 3355 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
3537 <&gcc GCC_AG 3356 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>,
3538 <&gcc GCC_AG 3357 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>,
3539 <&gcc GCC_SY 3358 <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
3540 clock-names = "cfg_no 3359 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi",
3541 "noc_ag 3360 "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys";
3542 3361
3543 assigned-clocks = <&g 3362 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3544 <&g 3363 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
3545 assigned-clock-rates 3364 assigned-clock-rates = <19200000>, <200000000>;
3546 3365
3547 interrupts-extended = 3366 interrupts-extended = <&intc GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>,
3548 <<
3549 3367 <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
3550 3368 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
3551 3369 <&pdc 138 IRQ_TYPE_LEVEL_HIGH>;
3552 interrupt-names = "pw 3370 interrupt-names = "pwr_event",
3553 "hs <<
3554 "dp 3371 "dp_hs_phy_irq",
3555 "dm 3372 "dm_hs_phy_irq",
3556 "ss 3373 "ss_phy_irq";
3557 3374
3558 power-domains = <&gcc 3375 power-domains = <&gcc USB30_PRIM_GDSC>;
3559 required-opps = <&rpm 3376 required-opps = <&rpmhpd_opp_nom>;
3560 3377
3561 resets = <&gcc GCC_US 3378 resets = <&gcc GCC_USB30_PRIM_BCR>;
3562 3379
3563 interconnects = <&agg 3380 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
3564 <&gem 3381 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
3565 interconnect-names = 3382 interconnect-names = "usb-ddr", "apps-usb";
3566 3383
3567 wakeup-source; 3384 wakeup-source;
3568 3385
3569 status = "disabled"; 3386 status = "disabled";
3570 3387
3571 usb_0_dwc3: usb@a6000 3388 usb_0_dwc3: usb@a600000 {
3572 compatible = 3389 compatible = "snps,dwc3";
3573 reg = <0 0x0a 3390 reg = <0 0x0a600000 0 0xcd00>;
3574 interrupts = 3391 interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>;
3575 iommus = <&ap 3392 iommus = <&apps_smmu 0x820 0x0>;
3576 phys = <&usb_ 3393 phys = <&usb_0_hsphy>, <&usb_0_qmpphy QMP_USB43DP_USB3_PHY>;
3577 phy-names = " 3394 phy-names = "usb2-phy", "usb3-phy";
3578 3395
3579 ports { !! 3396 port {
3580 #addr !! 3397 usb_0_role_switch: endpoint {
3581 #size <<
3582 <<
3583 port@ <<
3584 <<
3585 <<
3586 <<
3587 <<
3588 }; <<
3589 <<
3590 port@ <<
3591 <<
3592 <<
3593 <<
3594 <<
3595 <<
3596 }; 3398 };
3597 }; 3399 };
3598 }; 3400 };
3599 }; 3401 };
3600 3402
3601 usb_1: usb@a8f8800 { 3403 usb_1: usb@a8f8800 {
3602 compatible = "qcom,sc 3404 compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3";
3603 reg = <0 0x0a8f8800 0 3405 reg = <0 0x0a8f8800 0 0x400>;
3604 #address-cells = <2>; 3406 #address-cells = <2>;
3605 #size-cells = <2>; 3407 #size-cells = <2>;
3606 ranges; 3408 ranges;
3607 3409
3608 clocks = <&gcc GCC_CF 3410 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
3609 <&gcc GCC_US 3411 <&gcc GCC_USB30_SEC_MASTER_CLK>,
3610 <&gcc GCC_AG 3412 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
3611 <&gcc GCC_US 3413 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
3612 <&gcc GCC_US 3414 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3613 <&gcc GCC_AG 3415 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
3614 <&gcc GCC_AG 3416 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>,
3615 <&gcc GCC_AG 3417 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>,
3616 <&gcc GCC_SY 3418 <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
3617 clock-names = "cfg_no 3419 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi",
3618 "noc_ag 3420 "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys";
3619 3421
3620 assigned-clocks = <&g 3422 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3621 <&g 3423 <&gcc GCC_USB30_SEC_MASTER_CLK>;
3622 assigned-clock-rates 3424 assigned-clock-rates = <19200000>, <200000000>;
3623 3425
3624 interrupts-extended = 3426 interrupts-extended = <&intc GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>,
3625 <<
3626 3427 <&pdc 12 IRQ_TYPE_EDGE_BOTH>,
3627 3428 <&pdc 13 IRQ_TYPE_EDGE_BOTH>,
3628 3429 <&pdc 136 IRQ_TYPE_LEVEL_HIGH>;
3629 interrupt-names = "pw 3430 interrupt-names = "pwr_event",
3630 "hs <<
3631 "dp 3431 "dp_hs_phy_irq",
3632 "dm 3432 "dm_hs_phy_irq",
3633 "ss 3433 "ss_phy_irq";
3634 3434
3635 power-domains = <&gcc 3435 power-domains = <&gcc USB30_SEC_GDSC>;
3636 required-opps = <&rpm 3436 required-opps = <&rpmhpd_opp_nom>;
3637 3437
3638 resets = <&gcc GCC_US 3438 resets = <&gcc GCC_USB30_SEC_BCR>;
3639 3439
3640 interconnects = <&agg 3440 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>,
3641 <&gem 3441 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
3642 interconnect-names = 3442 interconnect-names = "usb-ddr", "apps-usb";
3643 3443
3644 wakeup-source; 3444 wakeup-source;
3645 3445
3646 status = "disabled"; 3446 status = "disabled";
3647 3447
3648 usb_1_dwc3: usb@a8000 3448 usb_1_dwc3: usb@a800000 {
3649 compatible = 3449 compatible = "snps,dwc3";
3650 reg = <0 0x0a 3450 reg = <0 0x0a800000 0 0xcd00>;
3651 interrupts = 3451 interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>;
3652 iommus = <&ap 3452 iommus = <&apps_smmu 0x860 0x0>;
3653 phys = <&usb_ 3453 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
3654 phy-names = " 3454 phy-names = "usb2-phy", "usb3-phy";
3655 3455
3656 ports { !! 3456 port {
3657 #addr !! 3457 usb_1_role_switch: endpoint {
3658 #size <<
3659 <<
3660 port@ <<
3661 <<
3662 <<
3663 <<
3664 <<
3665 }; <<
3666 <<
3667 port@ <<
3668 <<
3669 <<
3670 <<
3671 <<
3672 <<
3673 }; 3458 };
3674 }; 3459 };
3675 }; 3460 };
3676 }; 3461 };
3677 3462
3678 cci0: cci@ac4a000 { <<
3679 compatible = "qcom,sc <<
3680 reg = <0 0x0ac4a000 0 <<
3681 <<
3682 interrupts = <GIC_SPI <<
3683 <<
3684 clocks = <&camcc CAMC <<
3685 <&camcc CAMC <<
3686 <&camcc CAMC <<
3687 <&camcc CAMC <<
3688 clock-names = "camnoc <<
3689 "slow_a <<
3690 "cpas_a <<
3691 "cci"; <<
3692 <<
3693 power-domains = <&cam <<
3694 <<
3695 pinctrl-0 = <&cci0_de <<
3696 pinctrl-1 = <&cci0_sl <<
3697 pinctrl-names = "defa <<
3698 <<
3699 #address-cells = <1>; <<
3700 #size-cells = <0>; <<
3701 <<
3702 status = "disabled"; <<
3703 <<
3704 cci0_i2c0: i2c-bus@0 <<
3705 reg = <0>; <<
3706 clock-frequen <<
3707 #address-cell <<
3708 #size-cells = <<
3709 }; <<
3710 <<
3711 cci0_i2c1: i2c-bus@1 <<
3712 reg = <1>; <<
3713 clock-frequen <<
3714 #address-cell <<
3715 #size-cells = <<
3716 }; <<
3717 }; <<
3718 <<
3719 cci1: cci@ac4b000 { <<
3720 compatible = "qcom,sc <<
3721 reg = <0 0x0ac4b000 0 <<
3722 <<
3723 interrupts = <GIC_SPI <<
3724 <<
3725 clocks = <&camcc CAMC <<
3726 <&camcc CAMC <<
3727 <&camcc CAMC <<
3728 <&camcc CAMC <<
3729 clock-names = "camnoc <<
3730 "slow_a <<
3731 "cpas_a <<
3732 "cci"; <<
3733 <<
3734 power-domains = <&cam <<
3735 <<
3736 pinctrl-0 = <&cci1_de <<
3737 pinctrl-1 = <&cci1_sl <<
3738 pinctrl-names = "defa <<
3739 <<
3740 #address-cells = <1>; <<
3741 #size-cells = <0>; <<
3742 <<
3743 status = "disabled"; <<
3744 <<
3745 cci1_i2c0: i2c-bus@0 <<
3746 reg = <0>; <<
3747 clock-frequen <<
3748 #address-cell <<
3749 #size-cells = <<
3750 }; <<
3751 <<
3752 cci1_i2c1: i2c-bus@1 <<
3753 reg = <1>; <<
3754 clock-frequen <<
3755 #address-cell <<
3756 #size-cells = <<
3757 }; <<
3758 }; <<
3759 <<
3760 cci2: cci@ac4c000 { <<
3761 compatible = "qcom,sc <<
3762 reg = <0 0x0ac4c000 0 <<
3763 <<
3764 interrupts = <GIC_SPI <<
3765 <<
3766 clocks = <&camcc CAMC <<
3767 <&camcc CAMC <<
3768 <&camcc CAMC <<
3769 <&camcc CAMC <<
3770 clock-names = "camnoc <<
3771 "slow_a <<
3772 "cpas_a <<
3773 "cci"; <<
3774 power-domains = <&cam <<
3775 <<
3776 pinctrl-0 = <&cci2_de <<
3777 pinctrl-1 = <&cci2_sl <<
3778 pinctrl-names = "defa <<
3779 <<
3780 #address-cells = <1>; <<
3781 #size-cells = <0>; <<
3782 <<
3783 status = "disabled"; <<
3784 <<
3785 cci2_i2c0: i2c-bus@0 <<
3786 reg = <0>; <<
3787 clock-frequen <<
3788 #address-cell <<
3789 #size-cells = <<
3790 }; <<
3791 <<
3792 cci2_i2c1: i2c-bus@1 <<
3793 reg = <1>; <<
3794 clock-frequen <<
3795 #address-cell <<
3796 #size-cells = <<
3797 }; <<
3798 }; <<
3799 <<
3800 cci3: cci@ac4d000 { <<
3801 compatible = "qcom,sc <<
3802 reg = <0 0x0ac4d000 0 <<
3803 <<
3804 interrupts = <GIC_SPI <<
3805 <<
3806 clocks = <&camcc CAMC <<
3807 <&camcc CAMC <<
3808 <&camcc CAMC <<
3809 <&camcc CAMC <<
3810 clock-names = "camnoc <<
3811 "slow_a <<
3812 "cpas_a <<
3813 "cci"; <<
3814 <<
3815 power-domains = <&cam <<
3816 <<
3817 pinctrl-0 = <&cci3_de <<
3818 pinctrl-1 = <&cci3_sl <<
3819 pinctrl-names = "defa <<
3820 <<
3821 #address-cells = <1>; <<
3822 #size-cells = <0>; <<
3823 <<
3824 status = "disabled"; <<
3825 <<
3826 cci3_i2c0: i2c-bus@0 <<
3827 reg = <0>; <<
3828 clock-frequen <<
3829 #address-cell <<
3830 #size-cells = <<
3831 }; <<
3832 <<
3833 cci3_i2c1: i2c-bus@1 <<
3834 reg = <1>; <<
3835 clock-frequen <<
3836 #address-cell <<
3837 #size-cells = <<
3838 }; <<
3839 }; <<
3840 <<
3841 camss: camss@ac5a000 { <<
3842 compatible = "qcom,sc <<
3843 <<
3844 reg = <0 0x0ac5a000 0 <<
3845 <0 0x0ac5c000 0 <<
3846 <0 0x0ac65000 0 <<
3847 <0 0x0ac67000 0 <<
3848 <0 0x0acaf000 0 <<
3849 <0 0x0acb3000 0 <<
3850 <0 0x0acb6000 0 <<
3851 <0 0x0acba000 0 <<
3852 <0 0x0acbd000 0 <<
3853 <0 0x0acc1000 0 <<
3854 <0 0x0acc4000 0 <<
3855 <0 0x0acc8000 0 <<
3856 <0 0x0accb000 0 <<
3857 <0 0x0accf000 0 <<
3858 <0 0x0acd2000 0 <<
3859 <0 0x0acd6000 0 <<
3860 <0 0x0acd9000 0 <<
3861 <0 0x0acdd000 0 <<
3862 <0 0x0ace0000 0 <<
3863 <0 0x0ace4000 0 <<
3864 reg-names = "csiphy2" <<
3865 "csiphy3" <<
3866 "csiphy0" <<
3867 "csiphy1" <<
3868 "vfe0", <<
3869 "csid0", <<
3870 "vfe1", <<
3871 "csid1", <<
3872 "vfe2", <<
3873 "csid2", <<
3874 "vfe_lite <<
3875 "csid0_li <<
3876 "vfe_lite <<
3877 "csid1_li <<
3878 "vfe_lite <<
3879 "csid2_li <<
3880 "vfe_lite <<
3881 "csid3_li <<
3882 "vfe3", <<
3883 "csid3"; <<
3884 <<
3885 interrupts = <GIC_SPI <<
3886 <GIC_SPI <<
3887 <GIC_SPI <<
3888 <GIC_SPI <<
3889 <GIC_SPI <<
3890 <GIC_SPI <<
3891 <GIC_SPI <<
3892 <GIC_SPI <<
3893 <GIC_SPI <<
3894 <GIC_SPI <<
3895 <GIC_SPI <<
3896 <GIC_SPI <<
3897 <GIC_SPI <<
3898 <GIC_SPI <<
3899 <GIC_SPI <<
3900 <GIC_SPI <<
3901 <GIC_SPI <<
3902 <GIC_SPI <<
3903 <GIC_SPI <<
3904 <GIC_SPI <<
3905 interrupt-names = "cs <<
3906 "vf <<
3907 "cs <<
3908 "cs <<
3909 "vf <<
3910 "cs <<
3911 "vf <<
3912 "cs <<
3913 "vf <<
3914 "cs <<
3915 "cs <<
3916 "cs <<
3917 "cs <<
3918 "vf <<
3919 "cs <<
3920 "cs <<
3921 "vf <<
3922 "vf <<
3923 "cs <<
3924 "vf <<
3925 <<
3926 power-domains = <&cam <<
3927 <&cam <<
3928 <&cam <<
3929 <&cam <<
3930 <&cam <<
3931 power-domain-names = <<
3932 <<
3933 <<
3934 <<
3935 <<
3936 <<
3937 clocks = <&camcc CAMC <<
3938 <&camcc CAMC <<
3939 <&camcc CAMC <<
3940 <&camcc CAMC <<
3941 <&camcc CAMC <<
3942 <&camcc CAMC <<
3943 <&camcc CAMC <<
3944 <&camcc CAMC <<
3945 <&camcc CAMC <<
3946 <&camcc CAMC <<
3947 <&camcc CAMC <<
3948 <&camcc CAMC <<
3949 <&camcc CAMC <<
3950 <&camcc CAMC <<
3951 <&camcc CAMC <<
3952 <&camcc CAMC <<
3953 <&camcc CAMC <<
3954 <&camcc CAMC <<
3955 <&camcc CAMC <<
3956 <&camcc CAMC <<
3957 <&camcc CAMC <<
3958 <&camcc CAMC <<
3959 <&camcc CAMC <<
3960 <&camcc CAMC <<
3961 <&camcc CAMC <<
3962 <&camcc CAMC <<
3963 <&camcc CAMC <<
3964 <&camcc CAMC <<
3965 <&camcc CAMC <<
3966 <&camcc CAMC <<
3967 <&camcc CAMC <<
3968 <&camcc CAMC <<
3969 <&camcc CAMC <<
3970 <&camcc CAMC <<
3971 <&camcc CAMC <<
3972 <&camcc CAMC <<
3973 <&camcc CAMC <<
3974 <&camcc CAMC <<
3975 <&gcc GCC_CA <<
3976 <&gcc GCC_CA <<
3977 clock-names = "camnoc <<
3978 "cpas_a <<
3979 "csiphy <<
3980 "csiphy <<
3981 "csiphy <<
3982 "csiphy <<
3983 "csiphy <<
3984 "csiphy <<
3985 "csiphy <<
3986 "csiphy <<
3987 "vfe0_a <<
3988 "vfe0", <<
3989 "vfe0_c <<
3990 "vfe0_c <<
3991 "vfe1_a <<
3992 "vfe1", <<
3993 "vfe1_c <<
3994 "vfe1_c <<
3995 "vfe2_a <<
3996 "vfe2", <<
3997 "vfe2_c <<
3998 "vfe2_c <<
3999 "vfe3_a <<
4000 "vfe3", <<
4001 "vfe3_c <<
4002 "vfe3_c <<
4003 "vfe_li <<
4004 "vfe_li <<
4005 "vfe_li <<
4006 "vfe_li <<
4007 "vfe_li <<
4008 "vfe_li <<
4009 "vfe_li <<
4010 "vfe_li <<
4011 "vfe_li <<
4012 "vfe_li <<
4013 "vfe_li <<
4014 "vfe_li <<
4015 "gcc_ax <<
4016 "gcc_ax <<
4017 <<
4018 iommus = <&apps_smmu <<
4019 <&apps_smmu <<
4020 <&apps_smmu <<
4021 <&apps_smmu <<
4022 <&apps_smmu <<
4023 <&apps_smmu <<
4024 <&apps_smmu <<
4025 <&apps_smmu <<
4026 <&apps_smmu <<
4027 <&apps_smmu <<
4028 <&apps_smmu <<
4029 <&apps_smmu <<
4030 <&apps_smmu <<
4031 <&apps_smmu <<
4032 <&apps_smmu <<
4033 <&apps_smmu <<
4034 <<
4035 interconnects = <&gem <<
4036 <&mms <<
4037 <&mms <<
4038 <&mms <<
4039 interconnect-names = <<
4040 <<
4041 <<
4042 <<
4043 <<
4044 status = "disabled"; <<
4045 <<
4046 ports { <<
4047 #address-cell <<
4048 #size-cells = <<
4049 <<
4050 port@0 { <<
4051 reg = <<
4052 #addr <<
4053 #size <<
4054 }; <<
4055 <<
4056 port@1 { <<
4057 reg = <<
4058 #addr <<
4059 #size <<
4060 }; <<
4061 <<
4062 port@2 { <<
4063 reg = <<
4064 #addr <<
4065 #size <<
4066 }; <<
4067 <<
4068 port@3 { <<
4069 reg = <<
4070 #addr <<
4071 #size <<
4072 }; <<
4073 }; <<
4074 }; <<
4075 <<
4076 camcc: clock-controller@ad000 <<
4077 compatible = "qcom,sc <<
4078 reg = <0 0x0ad00000 0 <<
4079 clocks = <&gcc GCC_CA <<
4080 <&rpmhcc RPM <<
4081 <&rpmhcc RPM <<
4082 <&sleep_clk> <<
4083 power-domains = <&rpm <<
4084 required-opps = <&rpm <<
4085 #clock-cells = <1>; <<
4086 #reset-cells = <1>; <<
4087 #power-domain-cells = <<
4088 }; <<
4089 <<
4090 mdss0: display-subsystem@ae00 3463 mdss0: display-subsystem@ae00000 {
4091 compatible = "qcom,sc 3464 compatible = "qcom,sc8280xp-mdss";
4092 reg = <0 0x0ae00000 0 3465 reg = <0 0x0ae00000 0 0x1000>;
4093 reg-names = "mdss"; 3466 reg-names = "mdss";
4094 3467
4095 clocks = <&gcc GCC_DI 3468 clocks = <&gcc GCC_DISP_AHB_CLK>,
4096 <&dispcc0 DI 3469 <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
4097 <&dispcc0 DI 3470 <&dispcc0 DISP_CC_MDSS_MDP_CLK>;
4098 clock-names = "iface" 3471 clock-names = "iface",
4099 "ahb", 3472 "ahb",
4100 "core"; 3473 "core";
4101 interrupts = <GIC_SPI 3474 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
4102 interconnects = <&mms 3475 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
4103 <&mms 3476 <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>;
4104 interconnect-names = 3477 interconnect-names = "mdp0-mem", "mdp1-mem";
4105 iommus = <&apps_smmu 3478 iommus = <&apps_smmu 0x1000 0x402>;
4106 power-domains = <&dis 3479 power-domains = <&dispcc0 MDSS_GDSC>;
4107 resets = <&dispcc0 DI 3480 resets = <&dispcc0 DISP_CC_MDSS_CORE_BCR>;
4108 3481
4109 interrupt-controller; 3482 interrupt-controller;
4110 #interrupt-cells = <1 3483 #interrupt-cells = <1>;
4111 #address-cells = <2>; 3484 #address-cells = <2>;
4112 #size-cells = <2>; 3485 #size-cells = <2>;
4113 ranges; 3486 ranges;
4114 3487
4115 status = "disabled"; 3488 status = "disabled";
4116 3489
4117 mdss0_mdp: display-co 3490 mdss0_mdp: display-controller@ae01000 {
4118 compatible = 3491 compatible = "qcom,sc8280xp-dpu";
4119 reg = <0 0x0a 3492 reg = <0 0x0ae01000 0 0x8f000>,
4120 <0 0x0a 3493 <0 0x0aeb0000 0 0x2008>;
4121 reg-names = " 3494 reg-names = "mdp", "vbif";
4122 3495
4123 clocks = <&gc 3496 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
4124 <&gc 3497 <&gcc GCC_DISP_SF_AXI_CLK>,
4125 <&di 3498 <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
4126 <&di 3499 <&dispcc0 DISP_CC_MDSS_MDP_LUT_CLK>,
4127 <&di 3500 <&dispcc0 DISP_CC_MDSS_MDP_CLK>,
4128 <&di 3501 <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;
4129 clock-names = 3502 clock-names = "bus",
4130 3503 "nrt_bus",
4131 3504 "iface",
4132 3505 "lut",
4133 3506 "core",
4134 3507 "vsync";
4135 interrupt-par 3508 interrupt-parent = <&mdss0>;
4136 interrupts = 3509 interrupts = <0>;
4137 power-domains 3510 power-domains = <&rpmhpd SC8280XP_MMCX>;
4138 3511
4139 assigned-cloc 3512 assigned-clocks = <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;
4140 assigned-cloc 3513 assigned-clock-rates = <19200000>;
4141 operating-poi 3514 operating-points-v2 = <&mdss0_mdp_opp_table>;
4142 3515
4143 ports { 3516 ports {
4144 #addr 3517 #address-cells = <1>;
4145 #size 3518 #size-cells = <0>;
4146 3519
4147 port@ 3520 port@0 {
4148 3521 reg = <0>;
4149 3522 mdss0_intf0_out: endpoint {
4150 3523 remote-endpoint = <&mdss0_dp0_in>;
4151 3524 };
4152 }; 3525 };
4153 3526
4154 port@ 3527 port@4 {
4155 3528 reg = <4>;
4156 3529 mdss0_intf4_out: endpoint {
4157 3530 remote-endpoint = <&mdss0_dp1_in>;
4158 3531 };
4159 }; 3532 };
4160 3533
4161 port@ 3534 port@5 {
4162 3535 reg = <5>;
4163 3536 mdss0_intf5_out: endpoint {
4164 3537 remote-endpoint = <&mdss0_dp3_in>;
4165 3538 };
4166 }; 3539 };
4167 3540
4168 port@ 3541 port@6 {
4169 3542 reg = <6>;
4170 3543 mdss0_intf6_out: endpoint {
4171 3544 remote-endpoint = <&mdss0_dp2_in>;
4172 3545 };
4173 }; 3546 };
4174 }; 3547 };
4175 3548
4176 mdss0_mdp_opp 3549 mdss0_mdp_opp_table: opp-table {
4177 compa 3550 compatible = "operating-points-v2";
4178 3551
4179 opp-2 3552 opp-200000000 {
4180 3553 opp-hz = /bits/ 64 <200000000>;
4181 3554 required-opps = <&rpmhpd_opp_low_svs>;
4182 }; 3555 };
4183 3556
4184 opp-3 3557 opp-300000000 {
4185 3558 opp-hz = /bits/ 64 <300000000>;
4186 3559 required-opps = <&rpmhpd_opp_svs>;
4187 }; 3560 };
4188 3561
4189 opp-3 3562 opp-375000000 {
4190 3563 opp-hz = /bits/ 64 <375000000>;
4191 3564 required-opps = <&rpmhpd_opp_svs_l1>;
4192 }; 3565 };
4193 3566
4194 opp-5 3567 opp-500000000 {
4195 3568 opp-hz = /bits/ 64 <500000000>;
4196 3569 required-opps = <&rpmhpd_opp_nom>;
4197 }; 3570 };
4198 opp-6 3571 opp-600000000 {
4199 3572 opp-hz = /bits/ 64 <600000000>;
4200 3573 required-opps = <&rpmhpd_opp_turbo_l1>;
4201 }; 3574 };
4202 }; 3575 };
4203 }; 3576 };
4204 3577
4205 mdss0_dp0: displaypor 3578 mdss0_dp0: displayport-controller@ae90000 {
4206 compatible = 3579 compatible = "qcom,sc8280xp-dp";
4207 reg = <0 0xae 3580 reg = <0 0xae90000 0 0x200>,
4208 <0 0xae 3581 <0 0xae90200 0 0x200>,
4209 <0 0xae 3582 <0 0xae90400 0 0x600>,
4210 <0 0xae 3583 <0 0xae91000 0 0x400>,
4211 <0 0xae 3584 <0 0xae91400 0 0x400>;
4212 interrupt-par 3585 interrupt-parent = <&mdss0>;
4213 interrupts = 3586 interrupts = <12>;
4214 clocks = <&di 3587 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
4215 <&di 3588 <&dispcc0 DISP_CC_MDSS_DPTX0_AUX_CLK>,
4216 <&di 3589 <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK>,
4217 <&di 3590 <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
4218 <&di 3591 <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
4219 clock-names = 3592 clock-names = "core_iface", "core_aux",
4220 3593 "ctrl_link",
4221 3594 "ctrl_link_iface",
4222 3595 "stream_pixel";
4223 3596
4224 assigned-cloc 3597 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
4225 3598 <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
4226 assigned-cloc 3599 assigned-clock-parents = <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4227 3600 <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
4228 3601
4229 phys = <&usb_ 3602 phys = <&usb_0_qmpphy QMP_USB43DP_DP_PHY>;
4230 phy-names = " 3603 phy-names = "dp";
4231 3604
4232 #sound-dai-ce 3605 #sound-dai-cells = <0>;
4233 3606
4234 operating-poi 3607 operating-points-v2 = <&mdss0_dp0_opp_table>;
4235 power-domains 3608 power-domains = <&rpmhpd SC8280XP_MMCX>;
4236 3609
4237 status = "dis 3610 status = "disabled";
4238 3611
4239 ports { 3612 ports {
4240 #addr 3613 #address-cells = <1>;
4241 #size 3614 #size-cells = <0>;
4242 3615
4243 port@ 3616 port@0 {
4244 3617 reg = <0>;
4245 3618
4246 3619 mdss0_dp0_in: endpoint {
4247 3620 remote-endpoint = <&mdss0_intf0_out>;
4248 3621 };
4249 }; 3622 };
4250 3623
4251 port@ 3624 port@1 {
4252 3625 reg = <1>;
4253 3626
4254 3627 mdss0_dp0_out: endpoint {
4255 3628 };
4256 }; 3629 };
4257 }; 3630 };
4258 3631
4259 mdss0_dp0_opp 3632 mdss0_dp0_opp_table: opp-table {
4260 compa 3633 compatible = "operating-points-v2";
4261 3634
4262 opp-1 3635 opp-160000000 {
4263 3636 opp-hz = /bits/ 64 <160000000>;
4264 3637 required-opps = <&rpmhpd_opp_low_svs>;
4265 }; 3638 };
4266 3639
4267 opp-2 3640 opp-270000000 {
4268 3641 opp-hz = /bits/ 64 <270000000>;
4269 3642 required-opps = <&rpmhpd_opp_svs>;
4270 }; 3643 };
4271 3644
4272 opp-5 3645 opp-540000000 {
4273 3646 opp-hz = /bits/ 64 <540000000>;
4274 3647 required-opps = <&rpmhpd_opp_svs_l1>;
4275 }; 3648 };
4276 3649
4277 opp-8 3650 opp-810000000 {
4278 3651 opp-hz = /bits/ 64 <810000000>;
4279 3652 required-opps = <&rpmhpd_opp_nom>;
4280 }; 3653 };
4281 }; 3654 };
4282 }; 3655 };
4283 3656
4284 mdss0_dp1: displaypor 3657 mdss0_dp1: displayport-controller@ae98000 {
4285 compatible = 3658 compatible = "qcom,sc8280xp-dp";
4286 reg = <0 0xae 3659 reg = <0 0xae98000 0 0x200>,
4287 <0 0xae 3660 <0 0xae98200 0 0x200>,
4288 <0 0xae 3661 <0 0xae98400 0 0x600>,
4289 <0 0xae 3662 <0 0xae99000 0 0x400>,
4290 <0 0xae 3663 <0 0xae99400 0 0x400>;
4291 interrupt-par 3664 interrupt-parent = <&mdss0>;
4292 interrupts = 3665 interrupts = <13>;
4293 clocks = <&di 3666 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
4294 <&di 3667 <&dispcc0 DISP_CC_MDSS_DPTX1_AUX_CLK>,
4295 <&di 3668 <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK>,
4296 <&di 3669 <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
4297 <&di 3670 <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>;
4298 clock-names = 3671 clock-names = "core_iface", "core_aux",
4299 3672 "ctrl_link",
4300 3673 "ctrl_link_iface", "stream_pixel";
4301 3674
4302 assigned-cloc 3675 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
4303 3676 <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>;
4304 assigned-cloc 3677 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4305 3678 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
4306 3679
4307 phys = <&usb_ 3680 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
4308 phy-names = " 3681 phy-names = "dp";
4309 3682
4310 #sound-dai-ce 3683 #sound-dai-cells = <0>;
4311 3684
4312 operating-poi 3685 operating-points-v2 = <&mdss0_dp1_opp_table>;
4313 power-domains 3686 power-domains = <&rpmhpd SC8280XP_MMCX>;
4314 3687
4315 status = "dis 3688 status = "disabled";
4316 3689
4317 ports { 3690 ports {
4318 #addr 3691 #address-cells = <1>;
4319 #size 3692 #size-cells = <0>;
4320 3693
4321 port@ 3694 port@0 {
4322 3695 reg = <0>;
4323 3696
4324 3697 mdss0_dp1_in: endpoint {
4325 3698 remote-endpoint = <&mdss0_intf4_out>;
4326 3699 };
4327 }; 3700 };
4328 3701
4329 port@ 3702 port@1 {
4330 3703 reg = <1>;
4331 3704
4332 3705 mdss0_dp1_out: endpoint {
4333 3706 };
4334 }; 3707 };
4335 }; 3708 };
4336 3709
4337 mdss0_dp1_opp 3710 mdss0_dp1_opp_table: opp-table {
4338 compa 3711 compatible = "operating-points-v2";
4339 3712
4340 opp-1 3713 opp-160000000 {
4341 3714 opp-hz = /bits/ 64 <160000000>;
4342 3715 required-opps = <&rpmhpd_opp_low_svs>;
4343 }; 3716 };
4344 3717
4345 opp-2 3718 opp-270000000 {
4346 3719 opp-hz = /bits/ 64 <270000000>;
4347 3720 required-opps = <&rpmhpd_opp_svs>;
4348 }; 3721 };
4349 3722
4350 opp-5 3723 opp-540000000 {
4351 3724 opp-hz = /bits/ 64 <540000000>;
4352 3725 required-opps = <&rpmhpd_opp_svs_l1>;
4353 }; 3726 };
4354 3727
4355 opp-8 3728 opp-810000000 {
4356 3729 opp-hz = /bits/ 64 <810000000>;
4357 3730 required-opps = <&rpmhpd_opp_nom>;
4358 }; 3731 };
4359 }; 3732 };
4360 }; 3733 };
4361 3734
4362 mdss0_dp2: displaypor 3735 mdss0_dp2: displayport-controller@ae9a000 {
4363 compatible = 3736 compatible = "qcom,sc8280xp-dp";
4364 reg = <0 0xae 3737 reg = <0 0xae9a000 0 0x200>,
4365 <0 0xae 3738 <0 0xae9a200 0 0x200>,
4366 <0 0xae 3739 <0 0xae9a400 0 0x600>,
4367 <0 0xae 3740 <0 0xae9b000 0 0x400>,
4368 <0 0xae 3741 <0 0xae9b400 0 0x400>;
4369 3742
4370 clocks = <&di 3743 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
4371 <&di 3744 <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>,
4372 <&di 3745 <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK>,
4373 <&di 3746 <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>,
4374 <&di 3747 <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>;
4375 clock-names = 3748 clock-names = "core_iface", "core_aux",
4376 3749 "ctrl_link",
4377 3750 "ctrl_link_iface", "stream_pixel";
4378 interrupt-par 3751 interrupt-parent = <&mdss0>;
4379 interrupts = 3752 interrupts = <14>;
4380 phys = <&mdss 3753 phys = <&mdss0_dp2_phy>;
4381 phy-names = " 3754 phy-names = "dp";
4382 power-domains 3755 power-domains = <&rpmhpd SC8280XP_MMCX>;
4383 3756
4384 assigned-cloc 3757 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
4385 3758 <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>;
4386 assigned-cloc 3759 assigned-clock-parents = <&mdss0_dp2_phy 0>, <&mdss0_dp2_phy 1>;
4387 operating-poi 3760 operating-points-v2 = <&mdss0_dp2_opp_table>;
4388 3761
4389 #sound-dai-ce 3762 #sound-dai-cells = <0>;
4390 3763
4391 status = "dis 3764 status = "disabled";
4392 3765
4393 ports { 3766 ports {
4394 #addr 3767 #address-cells = <1>;
4395 #size 3768 #size-cells = <0>;
4396 3769
4397 port@ 3770 port@0 {
4398 3771 reg = <0>;
4399 3772 mdss0_dp2_in: endpoint {
4400 3773 remote-endpoint = <&mdss0_intf6_out>;
4401 3774 };
4402 }; 3775 };
4403 3776
4404 port@ 3777 port@1 {
4405 3778 reg = <1>;
4406 }; 3779 };
4407 }; 3780 };
4408 3781
4409 mdss0_dp2_opp 3782 mdss0_dp2_opp_table: opp-table {
4410 compa 3783 compatible = "operating-points-v2";
4411 3784
4412 opp-1 3785 opp-160000000 {
4413 3786 opp-hz = /bits/ 64 <160000000>;
4414 3787 required-opps = <&rpmhpd_opp_low_svs>;
4415 }; 3788 };
4416 3789
4417 opp-2 3790 opp-270000000 {
4418 3791 opp-hz = /bits/ 64 <270000000>;
4419 3792 required-opps = <&rpmhpd_opp_svs>;
4420 }; 3793 };
4421 3794
4422 opp-5 3795 opp-540000000 {
4423 3796 opp-hz = /bits/ 64 <540000000>;
4424 3797 required-opps = <&rpmhpd_opp_svs_l1>;
4425 }; 3798 };
4426 3799
4427 opp-8 3800 opp-810000000 {
4428 3801 opp-hz = /bits/ 64 <810000000>;
4429 3802 required-opps = <&rpmhpd_opp_nom>;
4430 }; 3803 };
4431 }; 3804 };
4432 }; 3805 };
4433 3806
4434 mdss0_dp3: displaypor 3807 mdss0_dp3: displayport-controller@aea0000 {
4435 compatible = 3808 compatible = "qcom,sc8280xp-dp";
4436 reg = <0 0xae 3809 reg = <0 0xaea0000 0 0x200>,
4437 <0 0xae 3810 <0 0xaea0200 0 0x200>,
4438 <0 0xae 3811 <0 0xaea0400 0 0x600>,
4439 <0 0xae 3812 <0 0xaea1000 0 0x400>,
4440 <0 0xae 3813 <0 0xaea1400 0 0x400>;
4441 3814
4442 clocks = <&di 3815 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
4443 <&di 3816 <&dispcc0 DISP_CC_MDSS_DPTX3_AUX_CLK>,
4444 <&di 3817 <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_CLK>,
4445 <&di 3818 <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>,
4446 <&di 3819 <&dispcc0 DISP_CC_MDSS_DPTX3_PIXEL0_CLK>;
4447 clock-names = 3820 clock-names = "core_iface", "core_aux",
4448 3821 "ctrl_link",
4449 3822 "ctrl_link_iface", "stream_pixel";
4450 interrupt-par 3823 interrupt-parent = <&mdss0>;
4451 interrupts = 3824 interrupts = <15>;
4452 phys = <&mdss 3825 phys = <&mdss0_dp3_phy>;
4453 phy-names = " 3826 phy-names = "dp";
4454 power-domains 3827 power-domains = <&rpmhpd SC8280XP_MMCX>;
4455 3828
4456 assigned-cloc 3829 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>,
4457 3830 <&dispcc0 DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>;
4458 assigned-cloc 3831 assigned-clock-parents = <&mdss0_dp3_phy 0>, <&mdss0_dp3_phy 1>;
4459 operating-poi 3832 operating-points-v2 = <&mdss0_dp3_opp_table>;
4460 3833
4461 #sound-dai-ce 3834 #sound-dai-cells = <0>;
4462 3835
4463 status = "dis 3836 status = "disabled";
4464 3837
4465 ports { 3838 ports {
4466 #addr 3839 #address-cells = <1>;
4467 #size 3840 #size-cells = <0>;
4468 3841
4469 port@ 3842 port@0 {
4470 3843 reg = <0>;
4471 3844 mdss0_dp3_in: endpoint {
4472 3845 remote-endpoint = <&mdss0_intf5_out>;
4473 3846 };
4474 }; 3847 };
4475 3848
4476 port@ 3849 port@1 {
4477 3850 reg = <1>;
4478 }; 3851 };
4479 }; 3852 };
4480 3853
4481 mdss0_dp3_opp 3854 mdss0_dp3_opp_table: opp-table {
4482 compa 3855 compatible = "operating-points-v2";
4483 3856
4484 opp-1 3857 opp-160000000 {
4485 3858 opp-hz = /bits/ 64 <160000000>;
4486 3859 required-opps = <&rpmhpd_opp_low_svs>;
4487 }; 3860 };
4488 3861
4489 opp-2 3862 opp-270000000 {
4490 3863 opp-hz = /bits/ 64 <270000000>;
4491 3864 required-opps = <&rpmhpd_opp_svs>;
4492 }; 3865 };
4493 3866
4494 opp-5 3867 opp-540000000 {
4495 3868 opp-hz = /bits/ 64 <540000000>;
4496 3869 required-opps = <&rpmhpd_opp_svs_l1>;
4497 }; 3870 };
4498 3871
4499 opp-8 3872 opp-810000000 {
4500 3873 opp-hz = /bits/ 64 <810000000>;
4501 3874 required-opps = <&rpmhpd_opp_nom>;
4502 }; 3875 };
4503 }; 3876 };
4504 }; 3877 };
4505 }; 3878 };
4506 3879
4507 mdss0_dp2_phy: phy@aec2a00 { 3880 mdss0_dp2_phy: phy@aec2a00 {
4508 compatible = "qcom,sc 3881 compatible = "qcom,sc8280xp-dp-phy";
4509 reg = <0 0x0aec2a00 0 3882 reg = <0 0x0aec2a00 0 0x19c>,
4510 <0 0x0aec2200 0 3883 <0 0x0aec2200 0 0xec>,
4511 <0 0x0aec2600 0 3884 <0 0x0aec2600 0 0xec>,
4512 <0 0x0aec2000 0 3885 <0 0x0aec2000 0 0x1c8>;
4513 3886
4514 clocks = <&dispcc0 DI 3887 clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>,
4515 <&dispcc0 DI 3888 <&dispcc0 DISP_CC_MDSS_AHB_CLK>;
4516 clock-names = "aux", 3889 clock-names = "aux", "cfg_ahb";
4517 power-domains = <&rpm 3890 power-domains = <&rpmhpd SC8280XP_MX>;
4518 3891
4519 #clock-cells = <1>; 3892 #clock-cells = <1>;
4520 #phy-cells = <0>; 3893 #phy-cells = <0>;
4521 3894
4522 status = "disabled"; 3895 status = "disabled";
4523 }; 3896 };
4524 3897
4525 mdss0_dp3_phy: phy@aec5a00 { 3898 mdss0_dp3_phy: phy@aec5a00 {
4526 compatible = "qcom,sc 3899 compatible = "qcom,sc8280xp-dp-phy";
4527 reg = <0 0x0aec5a00 0 3900 reg = <0 0x0aec5a00 0 0x19c>,
4528 <0 0x0aec5200 0 3901 <0 0x0aec5200 0 0xec>,
4529 <0 0x0aec5600 0 3902 <0 0x0aec5600 0 0xec>,
4530 <0 0x0aec5000 0 3903 <0 0x0aec5000 0 0x1c8>;
4531 3904
4532 clocks = <&dispcc0 DI 3905 clocks = <&dispcc0 DISP_CC_MDSS_DPTX3_AUX_CLK>,
4533 <&dispcc0 DI 3906 <&dispcc0 DISP_CC_MDSS_AHB_CLK>;
4534 clock-names = "aux", 3907 clock-names = "aux", "cfg_ahb";
4535 power-domains = <&rpm 3908 power-domains = <&rpmhpd SC8280XP_MX>;
4536 3909
4537 #clock-cells = <1>; 3910 #clock-cells = <1>;
4538 #phy-cells = <0>; 3911 #phy-cells = <0>;
4539 3912
4540 status = "disabled"; 3913 status = "disabled";
4541 }; 3914 };
4542 3915
4543 dispcc0: clock-controller@af0 3916 dispcc0: clock-controller@af00000 {
4544 compatible = "qcom,sc 3917 compatible = "qcom,sc8280xp-dispcc0";
4545 reg = <0 0x0af00000 0 3918 reg = <0 0x0af00000 0 0x20000>;
4546 3919
4547 clocks = <&gcc GCC_DI 3920 clocks = <&gcc GCC_DISP_AHB_CLK>,
4548 <&rpmhcc RPM 3921 <&rpmhcc RPMH_CXO_CLK>,
4549 <&sleep_clk> 3922 <&sleep_clk>,
4550 <&usb_0_qmpp 3923 <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4551 <&usb_0_qmpp 3924 <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
4552 <&usb_1_qmpp 3925 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4553 <&usb_1_qmpp 3926 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
4554 <&mdss0_dp2_ 3927 <&mdss0_dp2_phy 0>,
4555 <&mdss0_dp2_ 3928 <&mdss0_dp2_phy 1>,
4556 <&mdss0_dp3_ 3929 <&mdss0_dp3_phy 0>,
4557 <&mdss0_dp3_ 3930 <&mdss0_dp3_phy 1>,
4558 <0>, 3931 <0>,
4559 <0>, 3932 <0>,
4560 <0>, 3933 <0>,
4561 <0>; 3934 <0>;
4562 power-domains = <&rpm 3935 power-domains = <&rpmhpd SC8280XP_MMCX>;
4563 3936
4564 #clock-cells = <1>; 3937 #clock-cells = <1>;
4565 #power-domain-cells = 3938 #power-domain-cells = <1>;
4566 #reset-cells = <1>; 3939 #reset-cells = <1>;
4567 3940
4568 status = "disabled"; 3941 status = "disabled";
4569 }; 3942 };
4570 3943
4571 pdc: interrupt-controller@b22 3944 pdc: interrupt-controller@b220000 {
4572 compatible = "qcom,sc 3945 compatible = "qcom,sc8280xp-pdc", "qcom,pdc";
4573 reg = <0 0x0b220000 0 3946 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
4574 qcom,pdc-ranges = <0 3947 qcom,pdc-ranges = <0 480 40>,
4575 <40 3948 <40 140 14>,
4576 <54 3949 <54 263 1>,
4577 <55 3950 <55 306 4>,
4578 <59 3951 <59 312 3>,
4579 <62 3952 <62 374 2>,
4580 <64 3953 <64 434 2>,
4581 <66 3954 <66 438 3>,
4582 <69 3955 <69 86 1>,
4583 <70 3956 <70 520 54>,
4584 <12 3957 <124 609 28>,
4585 <15 3958 <159 638 1>,
4586 <16 3959 <160 720 8>,
4587 <16 3960 <168 801 1>,
4588 <16 3961 <169 728 30>,
4589 <19 3962 <199 416 2>,
4590 <20 3963 <201 449 1>,
4591 <20 3964 <202 89 1>,
4592 <20 3965 <203 451 1>,
4593 <20 3966 <204 462 1>,
4594 <20 3967 <205 264 1>,
4595 <20 3968 <206 579 1>,
4596 <20 3969 <207 653 1>,
4597 <20 3970 <208 656 1>,
4598 <20 3971 <209 659 1>,
4599 <21 3972 <210 122 1>,
4600 <21 3973 <211 699 1>,
4601 <21 3974 <212 705 1>,
4602 <21 3975 <213 450 1>,
4603 <21 3976 <214 643 1>,
4604 <21 3977 <216 646 5>,
4605 <22 3978 <221 390 5>,
4606 <22 3979 <226 700 3>,
4607 <22 3980 <229 240 3>,
4608 <23 3981 <232 269 1>,
4609 <23 3982 <233 377 1>,
4610 <23 3983 <234 372 1>,
4611 <23 3984 <235 138 1>,
4612 <23 3985 <236 857 1>,
4613 <23 3986 <237 860 1>,
4614 <23 3987 <238 137 1>,
4615 <23 3988 <239 668 1>,
4616 <24 3989 <240 366 1>,
4617 <24 3990 <241 949 1>,
4618 <24 3991 <242 815 5>,
4619 <24 3992 <247 769 1>,
4620 <24 3993 <248 768 1>,
4621 <24 3994 <249 663 1>,
4622 <25 3995 <250 799 2>,
4623 <25 3996 <252 798 1>,
4624 <25 3997 <253 765 1>,
4625 <25 3998 <254 763 1>,
4626 <25 3999 <255 454 1>,
4627 <25 4000 <258 139 1>,
4628 <25 4001 <259 786 2>,
4629 <26 4002 <261 370 2>,
4630 <26 4003 <263 158 2>;
4631 #interrupt-cells = <2 4004 #interrupt-cells = <2>;
4632 interrupt-parent = <& 4005 interrupt-parent = <&intc>;
4633 interrupt-controller; 4006 interrupt-controller;
4634 }; 4007 };
4635 4008
4636 tsens2: thermal-sensor@c25100 <<
4637 compatible = "qcom,sc <<
4638 reg = <0 0x0c251000 0 <<
4639 <0 0x0c224000 0 <<
4640 #qcom,sensors = <11>; <<
4641 interrupts-extended = <<
4642 <<
4643 interrupt-names = "up <<
4644 #thermal-sensor-cells <<
4645 }; <<
4646 <<
4647 tsens3: thermal-sensor@c25200 <<
4648 compatible = "qcom,sc <<
4649 reg = <0 0x0c252000 0 <<
4650 <0 0x0c225000 0 <<
4651 #qcom,sensors = <5>; <<
4652 interrupts-extended = <<
4653 <<
4654 interrupt-names = "up <<
4655 #thermal-sensor-cells <<
4656 }; <<
4657 <<
4658 tsens0: thermal-sensor@c26300 4009 tsens0: thermal-sensor@c263000 {
4659 compatible = "qcom,sc 4010 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2";
4660 reg = <0 0x0c263000 0 4011 reg = <0 0x0c263000 0 0x1ff>, /* TM */
4661 <0 0x0c222000 0 4012 <0 0x0c222000 0 0x8>; /* SROT */
4662 #qcom,sensors = <14>; 4013 #qcom,sensors = <14>;
4663 interrupts-extended = 4014 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
4664 4015 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>;
4665 interrupt-names = "up 4016 interrupt-names = "uplow", "critical";
4666 #thermal-sensor-cells 4017 #thermal-sensor-cells = <1>;
4667 }; 4018 };
4668 4019
4669 restart@c264000 { <<
4670 compatible = "qcom,ps <<
4671 reg = <0 0x0c264000 0 <<
4672 /* TZ seems to block <<
4673 status = "reserved"; <<
4674 }; <<
4675 <<
4676 tsens1: thermal-sensor@c26500 4020 tsens1: thermal-sensor@c265000 {
4677 compatible = "qcom,sc 4021 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2";
4678 reg = <0 0x0c265000 0 4022 reg = <0 0x0c265000 0 0x1ff>, /* TM */
4679 <0 0x0c223000 0 4023 <0 0x0c223000 0 0x8>; /* SROT */
4680 #qcom,sensors = <16>; 4024 #qcom,sensors = <16>;
4681 interrupts-extended = 4025 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
4682 4026 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>;
4683 interrupt-names = "up 4027 interrupt-names = "uplow", "critical";
4684 #thermal-sensor-cells 4028 #thermal-sensor-cells = <1>;
4685 }; 4029 };
4686 4030
4687 aoss_qmp: power-management@c3 4031 aoss_qmp: power-management@c300000 {
4688 compatible = "qcom,sc 4032 compatible = "qcom,sc8280xp-aoss-qmp", "qcom,aoss-qmp";
4689 reg = <0 0x0c300000 0 4033 reg = <0 0x0c300000 0 0x400>;
4690 interrupts-extended = 4034 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>;
4691 mboxes = <&ipcc IPCC_ 4035 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
4692 4036
4693 #clock-cells = <0>; 4037 #clock-cells = <0>;
4694 }; 4038 };
4695 4039
4696 sram@c3f0000 { 4040 sram@c3f0000 {
4697 compatible = "qcom,rp 4041 compatible = "qcom,rpmh-stats";
4698 reg = <0 0x0c3f0000 0 4042 reg = <0 0x0c3f0000 0 0x400>;
4699 qcom,qmp = <&aoss_qmp <<
4700 }; 4043 };
4701 4044
4702 spmi_bus: spmi@c440000 { 4045 spmi_bus: spmi@c440000 {
4703 compatible = "qcom,sp 4046 compatible = "qcom,spmi-pmic-arb";
4704 reg = <0 0x0c440000 0 4047 reg = <0 0x0c440000 0 0x1100>,
4705 <0 0x0c600000 0 4048 <0 0x0c600000 0 0x2000000>,
4706 <0 0x0e600000 0 4049 <0 0x0e600000 0 0x100000>,
4707 <0 0x0e700000 0 4050 <0 0x0e700000 0 0xa0000>,
4708 <0 0x0c40a000 0 4051 <0 0x0c40a000 0 0x26000>;
4709 reg-names = "core", " 4052 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
4710 interrupt-names = "pe 4053 interrupt-names = "periph_irq";
4711 interrupts-extended = 4054 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
4712 qcom,ee = <0>; 4055 qcom,ee = <0>;
4713 qcom,channel = <0>; 4056 qcom,channel = <0>;
4714 #address-cells = <2>; 4057 #address-cells = <2>;
4715 #size-cells = <0>; 4058 #size-cells = <0>;
4716 interrupt-controller; 4059 interrupt-controller;
4717 #interrupt-cells = <4 4060 #interrupt-cells = <4>;
4718 }; 4061 };
4719 4062
4720 tlmm: pinctrl@f100000 { 4063 tlmm: pinctrl@f100000 {
4721 compatible = "qcom,sc 4064 compatible = "qcom,sc8280xp-tlmm";
4722 reg = <0 0x0f100000 0 4065 reg = <0 0x0f100000 0 0x300000>;
4723 interrupts = <GIC_SPI 4066 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
4724 gpio-controller; 4067 gpio-controller;
4725 #gpio-cells = <2>; 4068 #gpio-cells = <2>;
4726 interrupt-controller; 4069 interrupt-controller;
4727 #interrupt-cells = <2 4070 #interrupt-cells = <2>;
4728 gpio-ranges = <&tlmm 4071 gpio-ranges = <&tlmm 0 0 230>;
4729 wakeup-parent = <&pdc 4072 wakeup-parent = <&pdc>;
4730 <<
4731 cci0_default: cci0-de <<
4732 cci0_i2c0_def <<
4733 /* cc <<
4734 pins <<
4735 funct <<
4736 drive <<
4737 bias- <<
4738 }; <<
4739 <<
4740 cci0_i2c1_def <<
4741 /* cc <<
4742 pins <<
4743 funct <<
4744 drive <<
4745 bias- <<
4746 }; <<
4747 }; <<
4748 <<
4749 cci0_sleep: cci0-slee <<
4750 cci0_i2c0_sle <<
4751 /* cc <<
4752 pins <<
4753 funct <<
4754 drive <<
4755 bias- <<
4756 }; <<
4757 <<
4758 cci0_i2c1_sle <<
4759 /* cc <<
4760 pins <<
4761 funct <<
4762 drive <<
4763 bias- <<
4764 }; <<
4765 }; <<
4766 <<
4767 cci1_default: cci1-de <<
4768 cci1_i2c0_def <<
4769 /* cc <<
4770 pins <<
4771 funct <<
4772 drive <<
4773 bias- <<
4774 }; <<
4775 <<
4776 cci1_i2c1_def <<
4777 /* cc <<
4778 pins <<
4779 funct <<
4780 drive <<
4781 bias- <<
4782 }; <<
4783 }; <<
4784 <<
4785 cci1_sleep: cci1-slee <<
4786 cci1_i2c0_sle <<
4787 /* cc <<
4788 pins <<
4789 funct <<
4790 drive <<
4791 bias- <<
4792 }; <<
4793 <<
4794 cci1_i2c1_sle <<
4795 /* cc <<
4796 pins <<
4797 funct <<
4798 drive <<
4799 bias- <<
4800 }; <<
4801 }; <<
4802 <<
4803 cci2_default: cci2-de <<
4804 cci2_i2c0_def <<
4805 /* cc <<
4806 pins <<
4807 funct <<
4808 drive <<
4809 bias- <<
4810 }; <<
4811 <<
4812 cci2_i2c1_def <<
4813 /* cc <<
4814 pins <<
4815 funct <<
4816 drive <<
4817 bias- <<
4818 }; <<
4819 }; <<
4820 <<
4821 cci2_sleep: cci2-slee <<
4822 cci2_i2c0_sle <<
4823 /* cc <<
4824 pins <<
4825 funct <<
4826 drive <<
4827 bias- <<
4828 }; <<
4829 <<
4830 cci2_i2c1_sle <<
4831 /* cc <<
4832 pins <<
4833 funct <<
4834 drive <<
4835 bias- <<
4836 }; <<
4837 }; <<
4838 <<
4839 cci3_default: cci3-de <<
4840 cci3_i2c0_def <<
4841 /* cc <<
4842 pins <<
4843 funct <<
4844 drive <<
4845 bias- <<
4846 }; <<
4847 <<
4848 cci3_i2c1_def <<
4849 /* cc <<
4850 pins <<
4851 funct <<
4852 drive <<
4853 bias- <<
4854 }; <<
4855 }; <<
4856 <<
4857 cci3_sleep: cci3-slee <<
4858 cci3_i2c0_sle <<
4859 /* cc <<
4860 pins <<
4861 funct <<
4862 drive <<
4863 bias- <<
4864 }; <<
4865 <<
4866 cci3_i2c1_sle <<
4867 /* cc <<
4868 pins <<
4869 funct <<
4870 drive <<
4871 bias- <<
4872 }; <<
4873 }; <<
4874 }; 4073 };
4875 4074
4876 apps_smmu: iommu@15000000 { 4075 apps_smmu: iommu@15000000 {
4877 compatible = "qcom,sc 4076 compatible = "qcom,sc8280xp-smmu-500", "arm,mmu-500";
4878 reg = <0 0x15000000 0 4077 reg = <0 0x15000000 0 0x100000>;
4879 #iommu-cells = <2>; 4078 #iommu-cells = <2>;
4880 #global-interrupts = 4079 #global-interrupts = <2>;
4881 interrupts = <GIC_SPI 4080 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
4882 <GIC_SPI 4081 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
4883 <GIC_SPI 4082 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
4884 <GIC_SPI 4083 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
4885 <GIC_SPI 4084 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
4886 <GIC_SPI 4085 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
4887 <GIC_SPI 4086 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
4888 <GIC_SPI 4087 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
4889 <GIC_SPI 4088 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
4890 <GIC_SPI 4089 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
4891 <GIC_SPI 4090 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
4892 <GIC_SPI 4091 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
4893 <GIC_SPI 4092 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
4894 <GIC_SPI 4093 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
4895 <GIC_SPI 4094 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
4896 <GIC_SPI 4095 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
4897 <GIC_SPI 4096 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
4898 <GIC_SPI 4097 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
4899 <GIC_SPI 4098 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
4900 <GIC_SPI 4099 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
4901 <GIC_SPI 4100 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
4902 <GIC_SPI 4101 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
4903 <GIC_SPI 4102 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
4904 <GIC_SPI 4103 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
4905 <GIC_SPI 4104 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
4906 <GIC_SPI 4105 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
4907 <GIC_SPI 4106 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
4908 <GIC_SPI 4107 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
4909 <GIC_SPI 4108 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
4910 <GIC_SPI 4109 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
4911 <GIC_SPI 4110 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
4912 <GIC_SPI 4111 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
4913 <GIC_SPI 4112 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
4914 <GIC_SPI 4113 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
4915 <GIC_SPI 4114 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
4916 <GIC_SPI 4115 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
4917 <GIC_SPI 4116 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
4918 <GIC_SPI 4117 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
4919 <GIC_SPI 4118 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
4920 <GIC_SPI 4119 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
4921 <GIC_SPI 4120 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
4922 <GIC_SPI 4121 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
4923 <GIC_SPI 4122 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
4924 <GIC_SPI 4123 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
4925 <GIC_SPI 4124 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
4926 <GIC_SPI 4125 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
4927 <GIC_SPI 4126 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
4928 <GIC_SPI 4127 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
4929 <GIC_SPI 4128 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
4930 <GIC_SPI 4129 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
4931 <GIC_SPI 4130 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
4932 <GIC_SPI 4131 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
4933 <GIC_SPI 4132 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
4934 <GIC_SPI 4133 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
4935 <GIC_SPI 4134 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
4936 <GIC_SPI 4135 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
4937 <GIC_SPI 4136 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
4938 <GIC_SPI 4137 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
4939 <GIC_SPI 4138 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
4940 <GIC_SPI 4139 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
4941 <GIC_SPI 4140 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
4942 <GIC_SPI 4141 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
4943 <GIC_SPI 4142 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
4944 <GIC_SPI 4143 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
4945 <GIC_SPI 4144 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
4946 <GIC_SPI 4145 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
4947 <GIC_SPI 4146 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
4948 <GIC_SPI 4147 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
4949 <GIC_SPI 4148 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
4950 <GIC_SPI 4149 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
4951 <GIC_SPI 4150 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
4952 <GIC_SPI 4151 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
4953 <GIC_SPI 4152 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
4954 <GIC_SPI 4153 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
4955 <GIC_SPI 4154 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
4956 <GIC_SPI 4155 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
4957 <GIC_SPI 4156 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
4958 <GIC_SPI 4157 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
4959 <GIC_SPI 4158 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
4960 <GIC_SPI 4159 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
4961 <GIC_SPI 4160 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>,
4962 <GIC_SPI 4161 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
4963 <GIC_SPI 4162 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
4964 <GIC_SPI 4163 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
4965 <GIC_SPI 4164 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
4966 <GIC_SPI 4165 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
4967 <GIC_SPI 4166 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
4968 <GIC_SPI 4167 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
4969 <GIC_SPI 4168 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
4970 <GIC_SPI 4169 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
4971 <GIC_SPI 4170 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
4972 <GIC_SPI 4171 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
4973 <GIC_SPI 4172 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
4974 <GIC_SPI 4173 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
4975 <GIC_SPI 4174 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
4976 <GIC_SPI 4175 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
4977 <GIC_SPI 4176 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
4978 <GIC_SPI 4177 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
4979 <GIC_SPI 4178 <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>,
4980 <GIC_SPI 4179 <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>,
4981 <GIC_SPI 4180 <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>,
4982 <GIC_SPI 4181 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
4983 <GIC_SPI 4182 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
4984 <GIC_SPI 4183 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
4985 <GIC_SPI 4184 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>,
4986 <GIC_SPI 4185 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>,
4987 <GIC_SPI 4186 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>,
4988 <GIC_SPI 4187 <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>,
4989 <GIC_SPI 4188 <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>,
4990 <GIC_SPI 4189 <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>,
4991 <GIC_SPI 4190 <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>,
4992 <GIC_SPI 4191 <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>,
4993 <GIC_SPI 4192 <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>,
4994 <GIC_SPI 4193 <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>,
4995 <GIC_SPI 4194 <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>,
4996 <GIC_SPI 4195 <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>,
4997 <GIC_SPI 4196 <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>,
4998 <GIC_SPI 4197 <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>,
4999 <GIC_SPI 4198 <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>,
5000 <GIC_SPI 4199 <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>,
5001 <GIC_SPI 4200 <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>,
5002 <GIC_SPI 4201 <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>,
5003 <GIC_SPI 4202 <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>,
5004 <GIC_SPI 4203 <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>,
5005 <GIC_SPI 4204 <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>,
5006 <GIC_SPI 4205 <GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>,
5007 <GIC_SPI 4206 <GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>,
5008 <GIC_SPI 4207 <GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>,
5009 <GIC_SPI 4208 <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>,
5010 <GIC_SPI 4209 <GIC_SPI 890 IRQ_TYPE_LEVEL_HIGH>;
5011 }; 4210 };
5012 4211
5013 intc: interrupt-controller@17 4212 intc: interrupt-controller@17a00000 {
5014 compatible = "arm,gic 4213 compatible = "arm,gic-v3";
5015 interrupt-controller; 4214 interrupt-controller;
5016 #interrupt-cells = <3 4215 #interrupt-cells = <3>;
5017 reg = <0x0 0x17a00000 4216 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
5018 <0x0 0x17a60000 4217 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
5019 interrupts = <GIC_PPI 4218 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
5020 #redistributor-region 4219 #redistributor-regions = <1>;
5021 redistributor-stride 4220 redistributor-stride = <0 0x20000>;
5022 4221
5023 #address-cells = <2>; 4222 #address-cells = <2>;
5024 #size-cells = <2>; 4223 #size-cells = <2>;
5025 ranges; 4224 ranges;
5026 4225
5027 its: msi-controller@1 !! 4226 msi-controller@17a40000 {
5028 compatible = 4227 compatible = "arm,gic-v3-its";
5029 reg = <0 0x17 4228 reg = <0 0x17a40000 0 0x20000>;
5030 msi-controlle 4229 msi-controller;
5031 #msi-cells = 4230 #msi-cells = <1>;
5032 }; 4231 };
5033 }; 4232 };
5034 4233
5035 watchdog@17c10000 { 4234 watchdog@17c10000 {
5036 compatible = "qcom,ap 4235 compatible = "qcom,apss-wdt-sc8280xp", "qcom,kpss-wdt";
5037 reg = <0 0x17c10000 0 4236 reg = <0 0x17c10000 0 0x1000>;
5038 clocks = <&sleep_clk> 4237 clocks = <&sleep_clk>;
5039 interrupts = <GIC_SPI 4238 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
5040 }; 4239 };
5041 4240
5042 timer@17c20000 { 4241 timer@17c20000 {
5043 compatible = "arm,arm 4242 compatible = "arm,armv7-timer-mem";
5044 reg = <0x0 0x17c20000 4243 reg = <0x0 0x17c20000 0x0 0x1000>;
5045 #address-cells = <1>; 4244 #address-cells = <1>;
5046 #size-cells = <1>; 4245 #size-cells = <1>;
5047 ranges = <0x0 0x0 0x0 4246 ranges = <0x0 0x0 0x0 0x20000000>;
5048 4247
5049 frame@17c21000 { 4248 frame@17c21000 {
5050 frame-number 4249 frame-number = <0>;
5051 interrupts = 4250 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
5052 4251 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
5053 reg = <0x17c2 4252 reg = <0x17c21000 0x1000>,
5054 <0x17c2 4253 <0x17c22000 0x1000>;
5055 }; 4254 };
5056 4255
5057 frame@17c23000 { 4256 frame@17c23000 {
5058 frame-number 4257 frame-number = <1>;
5059 interrupts = 4258 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
5060 reg = <0x17c2 4259 reg = <0x17c23000 0x1000>;
5061 status = "dis 4260 status = "disabled";
5062 }; 4261 };
5063 4262
5064 frame@17c25000 { 4263 frame@17c25000 {
5065 frame-number 4264 frame-number = <2>;
5066 interrupts = 4265 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
5067 reg = <0x17c2 4266 reg = <0x17c25000 0x1000>;
5068 status = "dis 4267 status = "disabled";
5069 }; 4268 };
5070 4269
5071 frame@17c27000 { 4270 frame@17c27000 {
5072 frame-number 4271 frame-number = <3>;
5073 interrupts = 4272 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
5074 reg = <0x17c2 4273 reg = <0x17c26000 0x1000>;
5075 status = "dis 4274 status = "disabled";
5076 }; 4275 };
5077 4276
5078 frame@17c29000 { 4277 frame@17c29000 {
5079 frame-number 4278 frame-number = <4>;
5080 interrupts = 4279 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
5081 reg = <0x17c2 4280 reg = <0x17c29000 0x1000>;
5082 status = "dis 4281 status = "disabled";
5083 }; 4282 };
5084 4283
5085 frame@17c2b000 { 4284 frame@17c2b000 {
5086 frame-number 4285 frame-number = <5>;
5087 interrupts = 4286 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
5088 reg = <0x17c2 4287 reg = <0x17c2b000 0x1000>;
5089 status = "dis 4288 status = "disabled";
5090 }; 4289 };
5091 4290
5092 frame@17c2d000 { 4291 frame@17c2d000 {
5093 frame-number 4292 frame-number = <6>;
5094 interrupts = 4293 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
5095 reg = <0x17c2 4294 reg = <0x17c2d000 0x1000>;
5096 status = "dis 4295 status = "disabled";
5097 }; 4296 };
5098 }; 4297 };
5099 4298
5100 apps_rsc: rsc@18200000 { 4299 apps_rsc: rsc@18200000 {
5101 compatible = "qcom,rp 4300 compatible = "qcom,rpmh-rsc";
5102 reg = <0x0 0x18200000 4301 reg = <0x0 0x18200000 0x0 0x10000>,
5103 <0x0 0x182100 4302 <0x0 0x18210000 0x0 0x10000>,
5104 <0x0 0x182200 4303 <0x0 0x18220000 0x0 0x10000>;
5105 reg-names = "drv-0", 4304 reg-names = "drv-0", "drv-1", "drv-2";
5106 interrupts = <GIC_SPI 4305 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
5107 <GIC_SPI 4306 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
5108 <GIC_SPI 4307 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
5109 qcom,tcs-offset = <0x 4308 qcom,tcs-offset = <0xd00>;
5110 qcom,drv-id = <2>; 4309 qcom,drv-id = <2>;
5111 qcom,tcs-config = <AC 4310 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
5112 <WA 4311 <WAKE_TCS 3>, <CONTROL_TCS 1>;
5113 label = "apps_rsc"; 4312 label = "apps_rsc";
5114 power-domains = <&CLU 4313 power-domains = <&CLUSTER_PD>;
5115 4314
5116 apps_bcm_voter: bcm-v 4315 apps_bcm_voter: bcm-voter {
5117 compatible = 4316 compatible = "qcom,bcm-voter";
5118 }; 4317 };
5119 4318
5120 rpmhcc: clock-control 4319 rpmhcc: clock-controller {
5121 compatible = 4320 compatible = "qcom,sc8280xp-rpmh-clk";
5122 #clock-cells 4321 #clock-cells = <1>;
5123 clock-names = 4322 clock-names = "xo";
5124 clocks = <&xo 4323 clocks = <&xo_board_clk>;
5125 }; 4324 };
5126 4325
5127 rpmhpd: power-control 4326 rpmhpd: power-controller {
5128 compatible = 4327 compatible = "qcom,sc8280xp-rpmhpd";
5129 #power-domain 4328 #power-domain-cells = <1>;
5130 operating-poi 4329 operating-points-v2 = <&rpmhpd_opp_table>;
5131 4330
5132 rpmhpd_opp_ta 4331 rpmhpd_opp_table: opp-table {
5133 compa 4332 compatible = "operating-points-v2";
5134 4333
5135 rpmhp 4334 rpmhpd_opp_ret: opp1 {
5136 4335 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
5137 }; 4336 };
5138 4337
5139 rpmhp 4338 rpmhpd_opp_min_svs: opp2 {
5140 4339 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
5141 }; 4340 };
5142 4341
5143 rpmhp 4342 rpmhpd_opp_low_svs: opp3 {
5144 4343 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
5145 }; 4344 };
5146 4345
5147 rpmhp 4346 rpmhpd_opp_svs: opp4 {
5148 4347 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
5149 }; 4348 };
5150 4349
5151 rpmhp 4350 rpmhpd_opp_svs_l1: opp5 {
5152 4351 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
5153 }; 4352 };
5154 4353
5155 rpmhp 4354 rpmhpd_opp_nom: opp6 {
5156 4355 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
5157 }; 4356 };
5158 4357
5159 rpmhp 4358 rpmhpd_opp_nom_l1: opp7 {
5160 4359 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
5161 }; 4360 };
5162 4361
5163 rpmhp 4362 rpmhpd_opp_nom_l2: opp8 {
5164 4363 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
5165 }; 4364 };
5166 4365
5167 rpmhp 4366 rpmhpd_opp_turbo: opp9 {
5168 4367 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
5169 }; 4368 };
5170 4369
5171 rpmhp 4370 rpmhpd_opp_turbo_l1: opp10 {
5172 4371 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
5173 }; 4372 };
5174 }; 4373 };
5175 }; 4374 };
5176 }; 4375 };
5177 4376
5178 epss_l3: interconnect@1859000 4377 epss_l3: interconnect@18590000 {
5179 compatible = "qcom,sc 4378 compatible = "qcom,sc8280xp-epss-l3", "qcom,epss-l3";
5180 reg = <0 0x18590000 0 4379 reg = <0 0x18590000 0 0x1000>;
5181 4380
5182 clocks = <&rpmhcc RPM 4381 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
5183 clock-names = "xo", " 4382 clock-names = "xo", "alternate";
5184 4383
5185 #interconnect-cells = 4384 #interconnect-cells = <1>;
5186 }; 4385 };
5187 4386
5188 cpufreq_hw: cpufreq@18591000 4387 cpufreq_hw: cpufreq@18591000 {
5189 compatible = "qcom,sc 4388 compatible = "qcom,sc8280xp-cpufreq-epss", "qcom,cpufreq-epss";
5190 reg = <0 0x18591000 0 4389 reg = <0 0x18591000 0 0x1000>,
5191 <0 0x18592000 0 4390 <0 0x18592000 0 0x1000>;
5192 reg-names = "freq-dom 4391 reg-names = "freq-domain0", "freq-domain1";
5193 4392
5194 interrupts = <GIC_SPI <<
5195 <GIC_SPI <<
5196 interrupt-names = "dc <<
5197 "dc <<
5198 <<
5199 clocks = <&rpmhcc RPM 4393 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
5200 clock-names = "xo", " 4394 clock-names = "xo", "alternate";
5201 4395
5202 #freq-domain-cells = 4396 #freq-domain-cells = <1>;
5203 #clock-cells = <1>; 4397 #clock-cells = <1>;
5204 }; 4398 };
5205 4399
5206 remoteproc_nsp0: remoteproc@1 4400 remoteproc_nsp0: remoteproc@1b300000 {
5207 compatible = "qcom,sc 4401 compatible = "qcom,sc8280xp-nsp0-pas";
5208 reg = <0 0x1b300000 0 4402 reg = <0 0x1b300000 0 0x100>;
5209 4403
5210 interrupts-extended = !! 4404 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
5211 4405 <&smp2p_nsp0_in 0 IRQ_TYPE_EDGE_RISING>,
5212 4406 <&smp2p_nsp0_in 1 IRQ_TYPE_EDGE_RISING>,
5213 4407 <&smp2p_nsp0_in 2 IRQ_TYPE_EDGE_RISING>,
5214 4408 <&smp2p_nsp0_in 3 IRQ_TYPE_EDGE_RISING>;
5215 interrupt-names = "wd 4409 interrupt-names = "wdog", "fatal", "ready",
5216 "ha 4410 "handover", "stop-ack";
5217 4411
5218 clocks = <&rpmhcc RPM 4412 clocks = <&rpmhcc RPMH_CXO_CLK>;
5219 clock-names = "xo"; 4413 clock-names = "xo";
5220 4414
5221 power-domains = <&rpm 4415 power-domains = <&rpmhpd SC8280XP_NSP>;
5222 power-domain-names = 4416 power-domain-names = "nsp";
5223 4417
5224 memory-region = <&pil 4418 memory-region = <&pil_nsp0_mem>;
5225 4419
5226 qcom,smem-states = <& 4420 qcom,smem-states = <&smp2p_nsp0_out 0>;
5227 qcom,smem-state-names 4421 qcom,smem-state-names = "stop";
5228 4422
5229 interconnects = <&nsp 4423 interconnects = <&nspa_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>;
5230 4424
5231 status = "disabled"; 4425 status = "disabled";
5232 4426
5233 glink-edge { 4427 glink-edge {
5234 interrupts-ex 4428 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
5235 4429 IPCC_MPROC_SIGNAL_GLINK_QMP
5236 4430 IRQ_TYPE_EDGE_RISING>;
5237 mboxes = <&ip 4431 mboxes = <&ipcc IPCC_CLIENT_CDSP
5238 4432 IPCC_MPROC_SIGNAL_GLINK_QMP>;
5239 4433
5240 label = "nsp0 4434 label = "nsp0";
5241 qcom,remote-p 4435 qcom,remote-pid = <5>;
5242 4436
5243 fastrpc { 4437 fastrpc {
5244 compa 4438 compatible = "qcom,fastrpc";
5245 qcom, 4439 qcom,glink-channels = "fastrpcglink-apps-dsp";
5246 label 4440 label = "cdsp";
5247 #addr 4441 #address-cells = <1>;
5248 #size 4442 #size-cells = <0>;
5249 4443
5250 compu 4444 compute-cb@1 {
5251 4445 compatible = "qcom,fastrpc-compute-cb";
5252 4446 reg = <1>;
5253 4447 iommus = <&apps_smmu 0x3181 0x0420>;
5254 }; 4448 };
5255 4449
5256 compu 4450 compute-cb@2 {
5257 4451 compatible = "qcom,fastrpc-compute-cb";
5258 4452 reg = <2>;
5259 4453 iommus = <&apps_smmu 0x3182 0x0420>;
5260 }; 4454 };
5261 4455
5262 compu 4456 compute-cb@3 {
5263 4457 compatible = "qcom,fastrpc-compute-cb";
5264 4458 reg = <3>;
5265 4459 iommus = <&apps_smmu 0x3183 0x0420>;
5266 }; 4460 };
5267 4461
5268 compu 4462 compute-cb@4 {
5269 4463 compatible = "qcom,fastrpc-compute-cb";
5270 4464 reg = <4>;
5271 4465 iommus = <&apps_smmu 0x3184 0x0420>;
5272 }; 4466 };
5273 4467
5274 compu 4468 compute-cb@5 {
5275 4469 compatible = "qcom,fastrpc-compute-cb";
5276 4470 reg = <5>;
5277 4471 iommus = <&apps_smmu 0x3185 0x0420>;
5278 }; 4472 };
5279 4473
5280 compu 4474 compute-cb@6 {
5281 4475 compatible = "qcom,fastrpc-compute-cb";
5282 4476 reg = <6>;
5283 4477 iommus = <&apps_smmu 0x3186 0x0420>;
5284 }; 4478 };
5285 4479
5286 compu 4480 compute-cb@7 {
5287 4481 compatible = "qcom,fastrpc-compute-cb";
5288 4482 reg = <7>;
5289 4483 iommus = <&apps_smmu 0x3187 0x0420>;
5290 }; 4484 };
5291 4485
5292 compu 4486 compute-cb@8 {
5293 4487 compatible = "qcom,fastrpc-compute-cb";
5294 4488 reg = <8>;
5295 4489 iommus = <&apps_smmu 0x3188 0x0420>;
5296 }; 4490 };
5297 4491
5298 compu 4492 compute-cb@9 {
5299 4493 compatible = "qcom,fastrpc-compute-cb";
5300 4494 reg = <9>;
5301 4495 iommus = <&apps_smmu 0x318b 0x0420>;
5302 }; 4496 };
5303 4497
5304 compu 4498 compute-cb@10 {
5305 4499 compatible = "qcom,fastrpc-compute-cb";
5306 4500 reg = <10>;
5307 4501 iommus = <&apps_smmu 0x318b 0x0420>;
5308 }; 4502 };
5309 4503
5310 compu 4504 compute-cb@11 {
5311 4505 compatible = "qcom,fastrpc-compute-cb";
5312 4506 reg = <11>;
5313 4507 iommus = <&apps_smmu 0x318c 0x0420>;
5314 }; 4508 };
5315 4509
5316 compu 4510 compute-cb@12 {
5317 4511 compatible = "qcom,fastrpc-compute-cb";
5318 4512 reg = <12>;
5319 4513 iommus = <&apps_smmu 0x318d 0x0420>;
5320 }; 4514 };
5321 4515
5322 compu 4516 compute-cb@13 {
5323 4517 compatible = "qcom,fastrpc-compute-cb";
5324 4518 reg = <13>;
5325 4519 iommus = <&apps_smmu 0x318e 0x0420>;
5326 }; 4520 };
5327 4521
5328 compu 4522 compute-cb@14 {
5329 4523 compatible = "qcom,fastrpc-compute-cb";
5330 4524 reg = <14>;
5331 4525 iommus = <&apps_smmu 0x318f 0x0420>;
5332 }; 4526 };
5333 }; 4527 };
5334 }; 4528 };
5335 }; 4529 };
5336 4530
5337 remoteproc_nsp1: remoteproc@2 4531 remoteproc_nsp1: remoteproc@21300000 {
5338 compatible = "qcom,sc 4532 compatible = "qcom,sc8280xp-nsp1-pas";
5339 reg = <0 0x21300000 0 4533 reg = <0 0x21300000 0 0x100>;
5340 4534
5341 interrupts-extended = !! 4535 interrupts-extended = <&intc GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>,
5342 4536 <&smp2p_nsp1_in 0 IRQ_TYPE_EDGE_RISING>,
5343 4537 <&smp2p_nsp1_in 1 IRQ_TYPE_EDGE_RISING>,
5344 4538 <&smp2p_nsp1_in 2 IRQ_TYPE_EDGE_RISING>,
5345 4539 <&smp2p_nsp1_in 3 IRQ_TYPE_EDGE_RISING>;
5346 interrupt-names = "wd 4540 interrupt-names = "wdog", "fatal", "ready",
5347 "ha 4541 "handover", "stop-ack";
5348 4542
5349 clocks = <&rpmhcc RPM 4543 clocks = <&rpmhcc RPMH_CXO_CLK>;
5350 clock-names = "xo"; 4544 clock-names = "xo";
5351 4545
5352 power-domains = <&rpm 4546 power-domains = <&rpmhpd SC8280XP_NSP>;
5353 power-domain-names = 4547 power-domain-names = "nsp";
5354 4548
5355 memory-region = <&pil 4549 memory-region = <&pil_nsp1_mem>;
5356 4550
5357 qcom,smem-states = <& 4551 qcom,smem-states = <&smp2p_nsp1_out 0>;
5358 qcom,smem-state-names 4552 qcom,smem-state-names = "stop";
5359 4553
5360 interconnects = <&nsp 4554 interconnects = <&nspb_noc MASTER_CDSP_PROC_B 0 &mc_virt SLAVE_EBI1 0>;
5361 4555
5362 status = "disabled"; 4556 status = "disabled";
5363 4557
5364 glink-edge { 4558 glink-edge {
5365 interrupts-ex 4559 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1
5366 4560 IPCC_MPROC_SIGNAL_GLINK_QMP
5367 4561 IRQ_TYPE_EDGE_RISING>;
5368 mboxes = <&ip 4562 mboxes = <&ipcc IPCC_CLIENT_NSP1
5369 4563 IPCC_MPROC_SIGNAL_GLINK_QMP>;
5370 4564
5371 label = "nsp1 4565 label = "nsp1";
5372 qcom,remote-p 4566 qcom,remote-pid = <12>;
5373 }; 4567 };
5374 }; 4568 };
5375 4569
5376 mdss1: display-subsystem@2200 4570 mdss1: display-subsystem@22000000 {
5377 compatible = "qcom,sc 4571 compatible = "qcom,sc8280xp-mdss";
5378 reg = <0 0x22000000 0 4572 reg = <0 0x22000000 0 0x1000>;
5379 reg-names = "mdss"; 4573 reg-names = "mdss";
5380 4574
5381 clocks = <&gcc GCC_DI 4575 clocks = <&gcc GCC_DISP_AHB_CLK>,
5382 <&dispcc1 DI 4576 <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
5383 <&dispcc1 DI 4577 <&dispcc1 DISP_CC_MDSS_MDP_CLK>;
5384 clock-names = "iface" 4578 clock-names = "iface",
5385 "ahb", 4579 "ahb",
5386 "core"; 4580 "core";
5387 interconnects = <&mms 4581 interconnects = <&mmss_noc MASTER_MDP_CORE1_0 0 &mc_virt SLAVE_EBI1 0>,
5388 <&mms 4582 <&mmss_noc MASTER_MDP_CORE1_1 0 &mc_virt SLAVE_EBI1 0>;
5389 interconnect-names = 4583 interconnect-names = "mdp0-mem", "mdp1-mem";
5390 interrupts = <GIC_SPI 4584 interrupts = <GIC_SPI 865 IRQ_TYPE_LEVEL_HIGH>;
5391 4585
5392 iommus = <&apps_smmu 4586 iommus = <&apps_smmu 0x1800 0x402>;
5393 power-domains = <&dis 4587 power-domains = <&dispcc1 MDSS_GDSC>;
5394 resets = <&dispcc1 DI 4588 resets = <&dispcc1 DISP_CC_MDSS_CORE_BCR>;
5395 4589
5396 interrupt-controller; 4590 interrupt-controller;
5397 #interrupt-cells = <1 4591 #interrupt-cells = <1>;
5398 #address-cells = <2>; 4592 #address-cells = <2>;
5399 #size-cells = <2>; 4593 #size-cells = <2>;
5400 ranges; 4594 ranges;
5401 4595
5402 status = "disabled"; 4596 status = "disabled";
5403 4597
5404 mdss1_mdp: display-co 4598 mdss1_mdp: display-controller@22001000 {
5405 compatible = 4599 compatible = "qcom,sc8280xp-dpu";
5406 reg = <0 0x22 4600 reg = <0 0x22001000 0 0x8f000>,
5407 <0 0x22 4601 <0 0x220b0000 0 0x2008>;
5408 reg-names = " 4602 reg-names = "mdp", "vbif";
5409 4603
5410 clocks = <&gc 4604 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
5411 <&gc 4605 <&gcc GCC_DISP_SF_AXI_CLK>,
5412 <&di 4606 <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
5413 <&di 4607 <&dispcc1 DISP_CC_MDSS_MDP_LUT_CLK>,
5414 <&di 4608 <&dispcc1 DISP_CC_MDSS_MDP_CLK>,
5415 <&di 4609 <&dispcc1 DISP_CC_MDSS_VSYNC_CLK>;
5416 clock-names = 4610 clock-names = "bus",
5417 4611 "nrt_bus",
5418 4612 "iface",
5419 4613 "lut",
5420 4614 "core",
5421 4615 "vsync";
5422 interrupt-par 4616 interrupt-parent = <&mdss1>;
5423 interrupts = 4617 interrupts = <0>;
5424 power-domains 4618 power-domains = <&rpmhpd SC8280XP_MMCX>;
5425 4619
5426 assigned-cloc 4620 assigned-clocks = <&dispcc1 DISP_CC_MDSS_VSYNC_CLK>;
5427 assigned-cloc 4621 assigned-clock-rates = <19200000>;
5428 operating-poi 4622 operating-points-v2 = <&mdss1_mdp_opp_table>;
5429 4623
5430 ports { 4624 ports {
5431 #addr 4625 #address-cells = <1>;
5432 #size 4626 #size-cells = <0>;
5433 4627
5434 port@ 4628 port@0 {
5435 4629 reg = <0>;
5436 4630 mdss1_intf0_out: endpoint {
5437 4631 remote-endpoint = <&mdss1_dp0_in>;
5438 4632 };
5439 }; 4633 };
5440 4634
5441 port@ 4635 port@4 {
5442 4636 reg = <4>;
5443 4637 mdss1_intf4_out: endpoint {
5444 4638 remote-endpoint = <&mdss1_dp1_in>;
5445 4639 };
5446 }; 4640 };
5447 4641
5448 port@ 4642 port@5 {
5449 4643 reg = <5>;
5450 4644 mdss1_intf5_out: endpoint {
5451 4645 remote-endpoint = <&mdss1_dp3_in>;
5452 4646 };
5453 }; 4647 };
5454 4648
5455 port@ 4649 port@6 {
5456 4650 reg = <6>;
5457 4651 mdss1_intf6_out: endpoint {
5458 4652 remote-endpoint = <&mdss1_dp2_in>;
5459 4653 };
5460 }; 4654 };
5461 }; 4655 };
5462 4656
5463 mdss1_mdp_opp 4657 mdss1_mdp_opp_table: opp-table {
5464 compa 4658 compatible = "operating-points-v2";
5465 4659
5466 opp-2 4660 opp-200000000 {
5467 4661 opp-hz = /bits/ 64 <200000000>;
5468 4662 required-opps = <&rpmhpd_opp_low_svs>;
5469 }; 4663 };
5470 4664
5471 opp-3 4665 opp-300000000 {
5472 4666 opp-hz = /bits/ 64 <300000000>;
5473 4667 required-opps = <&rpmhpd_opp_svs>;
5474 }; 4668 };
5475 4669
5476 opp-3 4670 opp-375000000 {
5477 4671 opp-hz = /bits/ 64 <375000000>;
5478 4672 required-opps = <&rpmhpd_opp_svs_l1>;
5479 }; 4673 };
5480 4674
5481 opp-5 4675 opp-500000000 {
5482 4676 opp-hz = /bits/ 64 <500000000>;
5483 4677 required-opps = <&rpmhpd_opp_nom>;
5484 }; 4678 };
5485 opp-6 4679 opp-600000000 {
5486 4680 opp-hz = /bits/ 64 <600000000>;
5487 4681 required-opps = <&rpmhpd_opp_turbo_l1>;
5488 }; 4682 };
5489 }; 4683 };
5490 }; 4684 };
5491 4685
5492 mdss1_dp0: displaypor 4686 mdss1_dp0: displayport-controller@22090000 {
5493 compatible = 4687 compatible = "qcom,sc8280xp-dp";
5494 reg = <0 0x22 4688 reg = <0 0x22090000 0 0x200>,
5495 <0 0x22 4689 <0 0x22090200 0 0x200>,
5496 <0 0x22 4690 <0 0x22090400 0 0x600>,
5497 <0 0x22 4691 <0 0x22091000 0 0x400>,
5498 <0 0x22 4692 <0 0x22091400 0 0x400>;
5499 4693
5500 clocks = <&di 4694 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
5501 <&di 4695 <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>,
5502 <&di 4696 <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK>,
5503 <&di 4697 <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
5504 <&di 4698 <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
5505 clock-names = 4699 clock-names = "core_iface", "core_aux",
5506 4700 "ctrl_link",
5507 4701 "ctrl_link_iface", "stream_pixel";
5508 interrupt-par 4702 interrupt-parent = <&mdss1>;
5509 interrupts = 4703 interrupts = <12>;
5510 phys = <&mdss 4704 phys = <&mdss1_dp0_phy>;
5511 phy-names = " 4705 phy-names = "dp";
5512 power-domains 4706 power-domains = <&rpmhpd SC8280XP_MMCX>;
5513 4707
5514 assigned-cloc 4708 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
5515 4709 <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
5516 assigned-cloc 4710 assigned-clock-parents = <&mdss1_dp0_phy 0>, <&mdss1_dp0_phy 1>;
5517 operating-poi 4711 operating-points-v2 = <&mdss1_dp0_opp_table>;
5518 4712
5519 #sound-dai-ce 4713 #sound-dai-cells = <0>;
5520 4714
5521 status = "dis 4715 status = "disabled";
5522 4716
5523 ports { 4717 ports {
5524 #addr 4718 #address-cells = <1>;
5525 #size 4719 #size-cells = <0>;
5526 4720
5527 port@ 4721 port@0 {
5528 4722 reg = <0>;
5529 4723 mdss1_dp0_in: endpoint {
5530 4724 remote-endpoint = <&mdss1_intf0_out>;
5531 4725 };
5532 }; 4726 };
5533 4727
5534 port@ 4728 port@1 {
5535 4729 reg = <1>;
5536 }; 4730 };
5537 }; 4731 };
5538 4732
5539 mdss1_dp0_opp 4733 mdss1_dp0_opp_table: opp-table {
5540 compa 4734 compatible = "operating-points-v2";
5541 4735
5542 opp-1 4736 opp-160000000 {
5543 4737 opp-hz = /bits/ 64 <160000000>;
5544 4738 required-opps = <&rpmhpd_opp_low_svs>;
5545 }; 4739 };
5546 4740
5547 opp-2 4741 opp-270000000 {
5548 4742 opp-hz = /bits/ 64 <270000000>;
5549 4743 required-opps = <&rpmhpd_opp_svs>;
5550 }; 4744 };
5551 4745
5552 opp-5 4746 opp-540000000 {
5553 4747 opp-hz = /bits/ 64 <540000000>;
5554 4748 required-opps = <&rpmhpd_opp_svs_l1>;
5555 }; 4749 };
5556 4750
5557 opp-8 4751 opp-810000000 {
5558 4752 opp-hz = /bits/ 64 <810000000>;
5559 4753 required-opps = <&rpmhpd_opp_nom>;
5560 }; 4754 };
5561 }; 4755 };
5562 }; 4756 };
5563 4757
5564 mdss1_dp1: displaypor 4758 mdss1_dp1: displayport-controller@22098000 {
5565 compatible = 4759 compatible = "qcom,sc8280xp-dp";
5566 reg = <0 0x22 4760 reg = <0 0x22098000 0 0x200>,
5567 <0 0x22 4761 <0 0x22098200 0 0x200>,
5568 <0 0x22 4762 <0 0x22098400 0 0x600>,
5569 <0 0x22 4763 <0 0x22099000 0 0x400>,
5570 <0 0x22 4764 <0 0x22099400 0 0x400>;
5571 4765
5572 clocks = <&di 4766 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
5573 <&di 4767 <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>,
5574 <&di 4768 <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK>,
5575 <&di 4769 <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
5576 <&di 4770 <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>;
5577 clock-names = 4771 clock-names = "core_iface", "core_aux",
5578 4772 "ctrl_link",
5579 4773 "ctrl_link_iface", "stream_pixel";
5580 interrupt-par 4774 interrupt-parent = <&mdss1>;
5581 interrupts = 4775 interrupts = <13>;
5582 phys = <&mdss 4776 phys = <&mdss1_dp1_phy>;
5583 phy-names = " 4777 phy-names = "dp";
5584 power-domains 4778 power-domains = <&rpmhpd SC8280XP_MMCX>;
5585 4779
5586 assigned-cloc 4780 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
5587 4781 <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>;
5588 assigned-cloc 4782 assigned-clock-parents = <&mdss1_dp1_phy 0>, <&mdss1_dp1_phy 1>;
5589 operating-poi 4783 operating-points-v2 = <&mdss1_dp1_opp_table>;
5590 4784
5591 #sound-dai-ce 4785 #sound-dai-cells = <0>;
5592 4786
5593 status = "dis 4787 status = "disabled";
5594 4788
5595 ports { 4789 ports {
5596 #addr 4790 #address-cells = <1>;
5597 #size 4791 #size-cells = <0>;
5598 4792
5599 port@ 4793 port@0 {
5600 4794 reg = <0>;
5601 4795 mdss1_dp1_in: endpoint {
5602 4796 remote-endpoint = <&mdss1_intf4_out>;
5603 4797 };
5604 }; 4798 };
5605 4799
5606 port@ 4800 port@1 {
5607 4801 reg = <1>;
5608 }; 4802 };
5609 }; 4803 };
5610 4804
5611 mdss1_dp1_opp 4805 mdss1_dp1_opp_table: opp-table {
5612 compa 4806 compatible = "operating-points-v2";
5613 4807
5614 opp-1 4808 opp-160000000 {
5615 4809 opp-hz = /bits/ 64 <160000000>;
5616 4810 required-opps = <&rpmhpd_opp_low_svs>;
5617 }; 4811 };
5618 4812
5619 opp-2 4813 opp-270000000 {
5620 4814 opp-hz = /bits/ 64 <270000000>;
5621 4815 required-opps = <&rpmhpd_opp_svs>;
5622 }; 4816 };
5623 4817
5624 opp-5 4818 opp-540000000 {
5625 4819 opp-hz = /bits/ 64 <540000000>;
5626 4820 required-opps = <&rpmhpd_opp_svs_l1>;
5627 }; 4821 };
5628 4822
5629 opp-8 4823 opp-810000000 {
5630 4824 opp-hz = /bits/ 64 <810000000>;
5631 4825 required-opps = <&rpmhpd_opp_nom>;
5632 }; 4826 };
5633 }; 4827 };
5634 }; 4828 };
5635 4829
5636 mdss1_dp2: displaypor 4830 mdss1_dp2: displayport-controller@2209a000 {
5637 compatible = 4831 compatible = "qcom,sc8280xp-dp";
5638 reg = <0 0x22 4832 reg = <0 0x2209a000 0 0x200>,
5639 <0 0x22 4833 <0 0x2209a200 0 0x200>,
5640 <0 0x22 4834 <0 0x2209a400 0 0x600>,
5641 <0 0x22 4835 <0 0x2209b000 0 0x400>,
5642 <0 0x22 4836 <0 0x2209b400 0 0x400>;
5643 4837
5644 clocks = <&di 4838 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
5645 <&di 4839 <&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>,
5646 <&di 4840 <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK>,
5647 <&di 4841 <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>,
5648 <&di 4842 <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>;
5649 clock-names = 4843 clock-names = "core_iface", "core_aux",
5650 4844 "ctrl_link",
5651 4845 "ctrl_link_iface", "stream_pixel";
5652 interrupt-par 4846 interrupt-parent = <&mdss1>;
5653 interrupts = 4847 interrupts = <14>;
5654 phys = <&mdss 4848 phys = <&mdss1_dp2_phy>;
5655 phy-names = " 4849 phy-names = "dp";
5656 power-domains 4850 power-domains = <&rpmhpd SC8280XP_MMCX>;
5657 4851
5658 assigned-cloc 4852 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
5659 4853 <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>;
5660 assigned-cloc 4854 assigned-clock-parents = <&mdss1_dp2_phy 0>, <&mdss1_dp2_phy 1>;
5661 operating-poi 4855 operating-points-v2 = <&mdss1_dp2_opp_table>;
5662 4856
5663 #sound-dai-ce 4857 #sound-dai-cells = <0>;
5664 4858
5665 status = "dis 4859 status = "disabled";
5666 4860
5667 ports { 4861 ports {
5668 #addr 4862 #address-cells = <1>;
5669 #size 4863 #size-cells = <0>;
5670 4864
5671 port@ 4865 port@0 {
5672 4866 reg = <0>;
5673 4867 mdss1_dp2_in: endpoint {
5674 4868 remote-endpoint = <&mdss1_intf6_out>;
5675 4869 };
5676 }; 4870 };
5677 4871
5678 port@ 4872 port@1 {
5679 4873 reg = <1>;
5680 }; 4874 };
5681 }; 4875 };
5682 4876
5683 mdss1_dp2_opp 4877 mdss1_dp2_opp_table: opp-table {
5684 compa 4878 compatible = "operating-points-v2";
5685 4879
5686 opp-1 4880 opp-160000000 {
5687 4881 opp-hz = /bits/ 64 <160000000>;
5688 4882 required-opps = <&rpmhpd_opp_low_svs>;
5689 }; 4883 };
5690 4884
5691 opp-2 4885 opp-270000000 {
5692 4886 opp-hz = /bits/ 64 <270000000>;
5693 4887 required-opps = <&rpmhpd_opp_svs>;
5694 }; 4888 };
5695 4889
5696 opp-5 4890 opp-540000000 {
5697 4891 opp-hz = /bits/ 64 <540000000>;
5698 4892 required-opps = <&rpmhpd_opp_svs_l1>;
5699 }; 4893 };
5700 4894
5701 opp-8 4895 opp-810000000 {
5702 4896 opp-hz = /bits/ 64 <810000000>;
5703 4897 required-opps = <&rpmhpd_opp_nom>;
5704 }; 4898 };
5705 }; 4899 };
5706 }; 4900 };
5707 4901
5708 mdss1_dp3: displaypor 4902 mdss1_dp3: displayport-controller@220a0000 {
5709 compatible = 4903 compatible = "qcom,sc8280xp-dp";
5710 reg = <0 0x22 4904 reg = <0 0x220a0000 0 0x200>,
5711 <0 0x22 4905 <0 0x220a0200 0 0x200>,
5712 <0 0x22 4906 <0 0x220a0400 0 0x600>,
5713 <0 0x22 4907 <0 0x220a1000 0 0x400>,
5714 <0 0x22 4908 <0 0x220a1400 0 0x400>;
5715 4909
5716 clocks = <&di 4910 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
5717 <&di 4911 <&dispcc1 DISP_CC_MDSS_DPTX3_AUX_CLK>,
5718 <&di 4912 <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_CLK>,
5719 <&di 4913 <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>,
5720 <&di 4914 <&dispcc1 DISP_CC_MDSS_DPTX3_PIXEL0_CLK>;
5721 clock-names = 4915 clock-names = "core_iface", "core_aux",
5722 4916 "ctrl_link",
5723 4917 "ctrl_link_iface", "stream_pixel";
5724 interrupt-par 4918 interrupt-parent = <&mdss1>;
5725 interrupts = 4919 interrupts = <15>;
5726 phys = <&mdss 4920 phys = <&mdss1_dp3_phy>;
5727 phy-names = " 4921 phy-names = "dp";
5728 power-domains 4922 power-domains = <&rpmhpd SC8280XP_MMCX>;
5729 4923
5730 assigned-cloc 4924 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>,
5731 4925 <&dispcc1 DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>;
5732 assigned-cloc 4926 assigned-clock-parents = <&mdss1_dp3_phy 0>, <&mdss1_dp3_phy 1>;
5733 operating-poi 4927 operating-points-v2 = <&mdss1_dp3_opp_table>;
5734 4928
5735 #sound-dai-ce 4929 #sound-dai-cells = <0>;
5736 4930
5737 status = "dis 4931 status = "disabled";
5738 4932
5739 ports { 4933 ports {
5740 #addr 4934 #address-cells = <1>;
5741 #size 4935 #size-cells = <0>;
5742 4936
5743 port@ 4937 port@0 {
5744 4938 reg = <0>;
5745 4939 mdss1_dp3_in: endpoint {
5746 4940 remote-endpoint = <&mdss1_intf5_out>;
5747 4941 };
5748 }; 4942 };
5749 4943
5750 port@ 4944 port@1 {
5751 4945 reg = <1>;
5752 }; 4946 };
5753 }; 4947 };
5754 4948
5755 mdss1_dp3_opp 4949 mdss1_dp3_opp_table: opp-table {
5756 compa 4950 compatible = "operating-points-v2";
5757 4951
5758 opp-1 4952 opp-160000000 {
5759 4953 opp-hz = /bits/ 64 <160000000>;
5760 4954 required-opps = <&rpmhpd_opp_low_svs>;
5761 }; 4955 };
5762 4956
5763 opp-2 4957 opp-270000000 {
5764 4958 opp-hz = /bits/ 64 <270000000>;
5765 4959 required-opps = <&rpmhpd_opp_svs>;
5766 }; 4960 };
5767 4961
5768 opp-5 4962 opp-540000000 {
5769 4963 opp-hz = /bits/ 64 <540000000>;
5770 4964 required-opps = <&rpmhpd_opp_svs_l1>;
5771 }; 4965 };
5772 4966
5773 opp-8 4967 opp-810000000 {
5774 4968 opp-hz = /bits/ 64 <810000000>;
5775 4969 required-opps = <&rpmhpd_opp_nom>;
5776 }; 4970 };
5777 }; 4971 };
5778 }; 4972 };
5779 }; 4973 };
5780 4974
5781 mdss1_dp2_phy: phy@220c2a00 { 4975 mdss1_dp2_phy: phy@220c2a00 {
5782 compatible = "qcom,sc 4976 compatible = "qcom,sc8280xp-dp-phy";
5783 reg = <0 0x220c2a00 0 4977 reg = <0 0x220c2a00 0 0x19c>,
5784 <0 0x220c2200 0 4978 <0 0x220c2200 0 0xec>,
5785 <0 0x220c2600 0 4979 <0 0x220c2600 0 0xec>,
5786 <0 0x220c2000 0 4980 <0 0x220c2000 0 0x1c8>;
5787 4981
5788 clocks = <&dispcc1 DI 4982 clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>,
5789 <&dispcc1 DI 4983 <&dispcc1 DISP_CC_MDSS_AHB_CLK>;
5790 clock-names = "aux", 4984 clock-names = "aux", "cfg_ahb";
5791 power-domains = <&rpm 4985 power-domains = <&rpmhpd SC8280XP_MX>;
5792 4986
5793 #clock-cells = <1>; 4987 #clock-cells = <1>;
5794 #phy-cells = <0>; 4988 #phy-cells = <0>;
5795 4989
5796 status = "disabled"; 4990 status = "disabled";
5797 }; 4991 };
5798 4992
5799 mdss1_dp3_phy: phy@220c5a00 { 4993 mdss1_dp3_phy: phy@220c5a00 {
5800 compatible = "qcom,sc 4994 compatible = "qcom,sc8280xp-dp-phy";
5801 reg = <0 0x220c5a00 0 4995 reg = <0 0x220c5a00 0 0x19c>,
5802 <0 0x220c5200 0 4996 <0 0x220c5200 0 0xec>,
5803 <0 0x220c5600 0 4997 <0 0x220c5600 0 0xec>,
5804 <0 0x220c5000 0 4998 <0 0x220c5000 0 0x1c8>;
5805 4999
5806 clocks = <&dispcc1 DI 5000 clocks = <&dispcc1 DISP_CC_MDSS_DPTX3_AUX_CLK>,
5807 <&dispcc1 DI 5001 <&dispcc1 DISP_CC_MDSS_AHB_CLK>;
5808 clock-names = "aux", 5002 clock-names = "aux", "cfg_ahb";
5809 power-domains = <&rpm 5003 power-domains = <&rpmhpd SC8280XP_MX>;
5810 5004
5811 #clock-cells = <1>; 5005 #clock-cells = <1>;
5812 #phy-cells = <0>; 5006 #phy-cells = <0>;
5813 5007
5814 status = "disabled"; 5008 status = "disabled";
5815 }; 5009 };
5816 5010
5817 dispcc1: clock-controller@221 5011 dispcc1: clock-controller@22100000 {
5818 compatible = "qcom,sc 5012 compatible = "qcom,sc8280xp-dispcc1";
5819 reg = <0 0x22100000 0 5013 reg = <0 0x22100000 0 0x20000>;
5820 5014
5821 clocks = <&gcc GCC_DI 5015 clocks = <&gcc GCC_DISP_AHB_CLK>,
5822 <&rpmhcc RPM 5016 <&rpmhcc RPMH_CXO_CLK>,
5823 <0>, 5017 <0>,
5824 <&mdss1_dp0_ 5018 <&mdss1_dp0_phy 0>,
5825 <&mdss1_dp0_ 5019 <&mdss1_dp0_phy 1>,
5826 <&mdss1_dp1_ 5020 <&mdss1_dp1_phy 0>,
5827 <&mdss1_dp1_ 5021 <&mdss1_dp1_phy 1>,
5828 <&mdss1_dp2_ 5022 <&mdss1_dp2_phy 0>,
5829 <&mdss1_dp2_ 5023 <&mdss1_dp2_phy 1>,
5830 <&mdss1_dp3_ 5024 <&mdss1_dp3_phy 0>,
5831 <&mdss1_dp3_ 5025 <&mdss1_dp3_phy 1>,
5832 <0>, 5026 <0>,
5833 <0>, 5027 <0>,
5834 <0>, 5028 <0>,
5835 <0>; 5029 <0>;
5836 power-domains = <&rpm 5030 power-domains = <&rpmhpd SC8280XP_MMCX>;
5837 5031
5838 #clock-cells = <1>; 5032 #clock-cells = <1>;
5839 #power-domain-cells = 5033 #power-domain-cells = <1>;
5840 #reset-cells = <1>; 5034 #reset-cells = <1>;
5841 5035
5842 status = "disabled"; 5036 status = "disabled";
5843 }; 5037 };
5844 5038
5845 ethernet1: ethernet@23000000 5039 ethernet1: ethernet@23000000 {
5846 compatible = "qcom,sc 5040 compatible = "qcom,sc8280xp-ethqos";
5847 reg = <0x0 0x23000000 5041 reg = <0x0 0x23000000 0x0 0x10000>,
5848 <0x0 0x23016000 5042 <0x0 0x23016000 0x0 0x100>;
5849 reg-names = "stmmacet 5043 reg-names = "stmmaceth", "rgmii";
5850 5044
5851 clocks = <&gcc GCC_EM 5045 clocks = <&gcc GCC_EMAC1_AXI_CLK>,
5852 <&gcc GCC_EM 5046 <&gcc GCC_EMAC1_SLV_AHB_CLK>,
5853 <&gcc GCC_EM 5047 <&gcc GCC_EMAC1_PTP_CLK>,
5854 <&gcc GCC_EM 5048 <&gcc GCC_EMAC1_RGMII_CLK>;
5855 clock-names = "stmmac 5049 clock-names = "stmmaceth",
5856 "pclk", 5050 "pclk",
5857 "ptp_re 5051 "ptp_ref",
5858 "rgmii" 5052 "rgmii";
5859 5053
5860 interrupts = <GIC_SPI 5054 interrupts = <GIC_SPI 929 IRQ_TYPE_LEVEL_HIGH>,
5861 <GIC_SPI 5055 <GIC_SPI 919 IRQ_TYPE_LEVEL_HIGH>;
5862 interrupt-names = "ma 5056 interrupt-names = "macirq", "eth_lpi";
5863 5057
5864 iommus = <&apps_smmu 5058 iommus = <&apps_smmu 0x40 0xf>;
5865 power-domains = <&gcc 5059 power-domains = <&gcc EMAC_1_GDSC>;
5866 5060
5867 snps,tso; 5061 snps,tso;
5868 snps,pbl = <32>; 5062 snps,pbl = <32>;
5869 rx-fifo-depth = <4096 5063 rx-fifo-depth = <4096>;
5870 tx-fifo-depth = <4096 5064 tx-fifo-depth = <4096>;
5871 5065
5872 status = "disabled"; 5066 status = "disabled";
5873 }; 5067 };
5874 }; 5068 };
5875 5069
5876 sound: sound { 5070 sound: sound {
5877 }; 5071 };
5878 5072
5879 thermal-zones { 5073 thermal-zones {
5880 cpu0-thermal { 5074 cpu0-thermal {
5881 polling-delay-passive 5075 polling-delay-passive = <250>;
>> 5076 polling-delay = <1000>;
5882 5077
5883 thermal-sensors = <&t 5078 thermal-sensors = <&tsens0 1>;
5884 5079
5885 trips { 5080 trips {
5886 cpu-crit { 5081 cpu-crit {
5887 tempe 5082 temperature = <110000>;
5888 hyste 5083 hysteresis = <1000>;
5889 type 5084 type = "critical";
5890 }; 5085 };
5891 }; 5086 };
5892 }; 5087 };
5893 5088
5894 cpu1-thermal { 5089 cpu1-thermal {
5895 polling-delay-passive 5090 polling-delay-passive = <250>;
>> 5091 polling-delay = <1000>;
5896 5092
5897 thermal-sensors = <&t 5093 thermal-sensors = <&tsens0 2>;
5898 5094
5899 trips { 5095 trips {
5900 cpu-crit { 5096 cpu-crit {
5901 tempe 5097 temperature = <110000>;
5902 hyste 5098 hysteresis = <1000>;
5903 type 5099 type = "critical";
5904 }; 5100 };
5905 }; 5101 };
5906 }; 5102 };
5907 5103
5908 cpu2-thermal { 5104 cpu2-thermal {
5909 polling-delay-passive 5105 polling-delay-passive = <250>;
>> 5106 polling-delay = <1000>;
5910 5107
5911 thermal-sensors = <&t 5108 thermal-sensors = <&tsens0 3>;
5912 5109
5913 trips { 5110 trips {
5914 cpu-crit { 5111 cpu-crit {
5915 tempe 5112 temperature = <110000>;
5916 hyste 5113 hysteresis = <1000>;
5917 type 5114 type = "critical";
5918 }; 5115 };
5919 }; 5116 };
5920 }; 5117 };
5921 5118
5922 cpu3-thermal { 5119 cpu3-thermal {
5923 polling-delay-passive 5120 polling-delay-passive = <250>;
>> 5121 polling-delay = <1000>;
5924 5122
5925 thermal-sensors = <&t 5123 thermal-sensors = <&tsens0 4>;
5926 5124
5927 trips { 5125 trips {
5928 cpu-crit { 5126 cpu-crit {
5929 tempe 5127 temperature = <110000>;
5930 hyste 5128 hysteresis = <1000>;
5931 type 5129 type = "critical";
5932 }; 5130 };
5933 }; 5131 };
5934 }; 5132 };
5935 5133
5936 cpu4-thermal { 5134 cpu4-thermal {
5937 polling-delay-passive 5135 polling-delay-passive = <250>;
>> 5136 polling-delay = <1000>;
5938 5137
5939 thermal-sensors = <&t 5138 thermal-sensors = <&tsens0 5>;
5940 5139
5941 trips { 5140 trips {
5942 cpu-crit { 5141 cpu-crit {
5943 tempe 5142 temperature = <110000>;
5944 hyste 5143 hysteresis = <1000>;
5945 type 5144 type = "critical";
5946 }; 5145 };
5947 }; 5146 };
5948 }; 5147 };
5949 5148
5950 cpu5-thermal { 5149 cpu5-thermal {
5951 polling-delay-passive 5150 polling-delay-passive = <250>;
>> 5151 polling-delay = <1000>;
5952 5152
5953 thermal-sensors = <&t 5153 thermal-sensors = <&tsens0 6>;
5954 5154
5955 trips { 5155 trips {
5956 cpu-crit { 5156 cpu-crit {
5957 tempe 5157 temperature = <110000>;
5958 hyste 5158 hysteresis = <1000>;
5959 type 5159 type = "critical";
5960 }; 5160 };
5961 }; 5161 };
5962 }; 5162 };
5963 5163
5964 cpu6-thermal { 5164 cpu6-thermal {
5965 polling-delay-passive 5165 polling-delay-passive = <250>;
>> 5166 polling-delay = <1000>;
5966 5167
5967 thermal-sensors = <&t 5168 thermal-sensors = <&tsens0 7>;
5968 5169
5969 trips { 5170 trips {
5970 cpu-crit { 5171 cpu-crit {
5971 tempe 5172 temperature = <110000>;
5972 hyste 5173 hysteresis = <1000>;
5973 type 5174 type = "critical";
5974 }; 5175 };
5975 }; 5176 };
5976 }; 5177 };
5977 5178
5978 cpu7-thermal { 5179 cpu7-thermal {
5979 polling-delay-passive 5180 polling-delay-passive = <250>;
>> 5181 polling-delay = <1000>;
5980 5182
5981 thermal-sensors = <&t 5183 thermal-sensors = <&tsens0 8>;
5982 5184
5983 trips { 5185 trips {
5984 cpu-crit { 5186 cpu-crit {
5985 tempe 5187 temperature = <110000>;
5986 hyste 5188 hysteresis = <1000>;
5987 type 5189 type = "critical";
5988 }; 5190 };
5989 }; 5191 };
5990 }; 5192 };
5991 5193
5992 cluster0-thermal { 5194 cluster0-thermal {
5993 polling-delay-passive 5195 polling-delay-passive = <250>;
>> 5196 polling-delay = <1000>;
5994 5197
5995 thermal-sensors = <&t 5198 thermal-sensors = <&tsens0 9>;
5996 5199
5997 trips { 5200 trips {
5998 cpu-crit { 5201 cpu-crit {
5999 tempe 5202 temperature = <110000>;
6000 hyste 5203 hysteresis = <1000>;
6001 type 5204 type = "critical";
6002 }; 5205 };
6003 }; 5206 };
6004 }; 5207 };
6005 5208
6006 gpu-thermal { <<
6007 polling-delay-passive <<
6008 <<
6009 thermal-sensors = <&t <<
6010 <<
6011 cooling-maps { <<
6012 map0 { <<
6013 trip <<
6014 cooli <<
6015 }; <<
6016 }; <<
6017 <<
6018 trips { <<
6019 gpu_alert0: t <<
6020 tempe <<
6021 hyste <<
6022 type <<
6023 }; <<
6024 <<
6025 trip-point1 { <<
6026 tempe <<
6027 hyste <<
6028 type <<
6029 }; <<
6030 }; <<
6031 }; <<
6032 <<
6033 mem-thermal { 5209 mem-thermal {
6034 polling-delay-passive 5210 polling-delay-passive = <250>;
>> 5211 polling-delay = <1000>;
6035 5212
6036 thermal-sensors = <&t 5213 thermal-sensors = <&tsens1 15>;
6037 5214
6038 trips { 5215 trips {
6039 trip-point0 { 5216 trip-point0 {
6040 tempe 5217 temperature = <90000>;
6041 hyste 5218 hysteresis = <2000>;
6042 type 5219 type = "hot";
6043 }; 5220 };
6044 }; 5221 };
6045 }; 5222 };
6046 }; 5223 };
6047 5224
6048 timer { 5225 timer {
6049 compatible = "arm,armv8-timer 5226 compatible = "arm,armv8-timer";
6050 interrupts = <GIC_PPI 13 (GIC 5227 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
6051 <GIC_PPI 14 (GIC 5228 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
6052 <GIC_PPI 11 (GIC 5229 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
6053 <GIC_PPI 10 (GIC 5230 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
6054 }; 5231 };
6055 }; 5232 };
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