1 // SPDX-License-Identifier: BSD-3-Clause 1 // SPDX-License-Identifier: BSD-3-Clause
2 /* 2 /*
3 * Copyright (c) 2021, The Linux Foundation. A 3 * Copyright (c) 2021, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2022, Linaro Limited 4 * Copyright (c) 2022, Linaro Limited
5 */ 5 */
6 6
7 #include <dt-bindings/clock/qcom,dispcc-sc8280 7 #include <dt-bindings/clock/qcom,dispcc-sc8280xp.h>
8 #include <dt-bindings/clock/qcom,gcc-sc8280xp. 8 #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
9 #include <dt-bindings/clock/qcom,gpucc-sc8280x 9 #include <dt-bindings/clock/qcom,gpucc-sc8280xp.h>
10 #include <dt-bindings/clock/qcom,rpmh.h> 10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/clock/qcom,sc8280xp-camc 11 #include <dt-bindings/clock/qcom,sc8280xp-camcc.h>
12 #include <dt-bindings/clock/qcom,sc8280xp-lpas 12 #include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>
13 #include <dt-bindings/interconnect/qcom,osm-l3 13 #include <dt-bindings/interconnect/qcom,osm-l3.h>
14 #include <dt-bindings/interconnect/qcom,sc8280 14 #include <dt-bindings/interconnect/qcom,sc8280xp.h>
15 #include <dt-bindings/interrupt-controller/arm 15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/mailbox/qcom-ipcc.h> 16 #include <dt-bindings/mailbox/qcom-ipcc.h>
17 #include <dt-bindings/phy/phy-qcom-qmp.h> 17 #include <dt-bindings/phy/phy-qcom-qmp.h>
18 #include <dt-bindings/power/qcom-rpmpd.h> 18 #include <dt-bindings/power/qcom-rpmpd.h>
19 #include <dt-bindings/soc/qcom,gpr.h> 19 #include <dt-bindings/soc/qcom,gpr.h>
20 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 20 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
21 #include <dt-bindings/sound/qcom,q6afe.h> 21 #include <dt-bindings/sound/qcom,q6afe.h>
22 #include <dt-bindings/thermal/thermal.h> 22 #include <dt-bindings/thermal/thermal.h>
23 23
24 / { 24 / {
25 interrupt-parent = <&intc>; 25 interrupt-parent = <&intc>;
26 26
27 #address-cells = <2>; 27 #address-cells = <2>;
28 #size-cells = <2>; 28 #size-cells = <2>;
29 29
30 clocks { 30 clocks {
31 xo_board_clk: xo-board-clk { 31 xo_board_clk: xo-board-clk {
32 compatible = "fixed-cl 32 compatible = "fixed-clock";
33 #clock-cells = <0>; 33 #clock-cells = <0>;
34 }; 34 };
35 35
36 sleep_clk: sleep-clk { 36 sleep_clk: sleep-clk {
37 compatible = "fixed-cl 37 compatible = "fixed-clock";
38 #clock-cells = <0>; 38 #clock-cells = <0>;
39 clock-frequency = <327 39 clock-frequency = <32764>;
40 }; 40 };
41 }; 41 };
42 42
43 cpus { 43 cpus {
44 #address-cells = <2>; 44 #address-cells = <2>;
45 #size-cells = <0>; 45 #size-cells = <0>;
46 46
47 CPU0: cpu@0 { 47 CPU0: cpu@0 {
48 device_type = "cpu"; 48 device_type = "cpu";
49 compatible = "arm,cort 49 compatible = "arm,cortex-a78c";
50 reg = <0x0 0x0>; 50 reg = <0x0 0x0>;
51 clocks = <&cpufreq_hw 51 clocks = <&cpufreq_hw 0>;
52 enable-method = "psci" 52 enable-method = "psci";
53 capacity-dmips-mhz = < !! 53 capacity-dmips-mhz = <602>;
54 dynamic-power-coeffici <<
55 next-level-cache = <&L 54 next-level-cache = <&L2_0>;
56 power-domains = <&CPU_ 55 power-domains = <&CPU_PD0>;
57 power-domain-names = " 56 power-domain-names = "psci";
58 qcom,freq-domain = <&c 57 qcom,freq-domain = <&cpufreq_hw 0>;
59 operating-points-v2 = 58 operating-points-v2 = <&cpu0_opp_table>;
60 interconnects = <&epss 59 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
61 #cooling-cells = <2>; 60 #cooling-cells = <2>;
62 L2_0: l2-cache { 61 L2_0: l2-cache {
63 compatible = " 62 compatible = "cache";
64 cache-level = 63 cache-level = <2>;
65 cache-unified; 64 cache-unified;
66 next-level-cac 65 next-level-cache = <&L3_0>;
67 L3_0: l3-cache 66 L3_0: l3-cache {
68 compat 67 compatible = "cache";
69 cache- 68 cache-level = <3>;
70 cache- 69 cache-unified;
71 }; 70 };
72 }; 71 };
73 }; 72 };
74 73
75 CPU1: cpu@100 { 74 CPU1: cpu@100 {
76 device_type = "cpu"; 75 device_type = "cpu";
77 compatible = "arm,cort 76 compatible = "arm,cortex-a78c";
78 reg = <0x0 0x100>; 77 reg = <0x0 0x100>;
79 clocks = <&cpufreq_hw 78 clocks = <&cpufreq_hw 0>;
80 enable-method = "psci" 79 enable-method = "psci";
81 capacity-dmips-mhz = < !! 80 capacity-dmips-mhz = <602>;
82 dynamic-power-coeffici <<
83 next-level-cache = <&L 81 next-level-cache = <&L2_100>;
84 power-domains = <&CPU_ 82 power-domains = <&CPU_PD1>;
85 power-domain-names = " 83 power-domain-names = "psci";
86 qcom,freq-domain = <&c 84 qcom,freq-domain = <&cpufreq_hw 0>;
87 operating-points-v2 = 85 operating-points-v2 = <&cpu0_opp_table>;
88 interconnects = <&epss 86 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
89 #cooling-cells = <2>; 87 #cooling-cells = <2>;
90 L2_100: l2-cache { 88 L2_100: l2-cache {
91 compatible = " 89 compatible = "cache";
92 cache-level = 90 cache-level = <2>;
93 cache-unified; 91 cache-unified;
94 next-level-cac 92 next-level-cache = <&L3_0>;
95 }; 93 };
96 }; 94 };
97 95
98 CPU2: cpu@200 { 96 CPU2: cpu@200 {
99 device_type = "cpu"; 97 device_type = "cpu";
100 compatible = "arm,cort 98 compatible = "arm,cortex-a78c";
101 reg = <0x0 0x200>; 99 reg = <0x0 0x200>;
102 clocks = <&cpufreq_hw 100 clocks = <&cpufreq_hw 0>;
103 enable-method = "psci" 101 enable-method = "psci";
104 capacity-dmips-mhz = < !! 102 capacity-dmips-mhz = <602>;
105 dynamic-power-coeffici <<
106 next-level-cache = <&L 103 next-level-cache = <&L2_200>;
107 power-domains = <&CPU_ 104 power-domains = <&CPU_PD2>;
108 power-domain-names = " 105 power-domain-names = "psci";
109 qcom,freq-domain = <&c 106 qcom,freq-domain = <&cpufreq_hw 0>;
110 operating-points-v2 = 107 operating-points-v2 = <&cpu0_opp_table>;
111 interconnects = <&epss 108 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
112 #cooling-cells = <2>; 109 #cooling-cells = <2>;
113 L2_200: l2-cache { 110 L2_200: l2-cache {
114 compatible = " 111 compatible = "cache";
115 cache-level = 112 cache-level = <2>;
116 cache-unified; 113 cache-unified;
117 next-level-cac 114 next-level-cache = <&L3_0>;
118 }; 115 };
119 }; 116 };
120 117
121 CPU3: cpu@300 { 118 CPU3: cpu@300 {
122 device_type = "cpu"; 119 device_type = "cpu";
123 compatible = "arm,cort 120 compatible = "arm,cortex-a78c";
124 reg = <0x0 0x300>; 121 reg = <0x0 0x300>;
125 clocks = <&cpufreq_hw 122 clocks = <&cpufreq_hw 0>;
126 enable-method = "psci" 123 enable-method = "psci";
127 capacity-dmips-mhz = < !! 124 capacity-dmips-mhz = <602>;
128 dynamic-power-coeffici <<
129 next-level-cache = <&L 125 next-level-cache = <&L2_300>;
130 power-domains = <&CPU_ 126 power-domains = <&CPU_PD3>;
131 power-domain-names = " 127 power-domain-names = "psci";
132 qcom,freq-domain = <&c 128 qcom,freq-domain = <&cpufreq_hw 0>;
133 operating-points-v2 = 129 operating-points-v2 = <&cpu0_opp_table>;
134 interconnects = <&epss 130 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
135 #cooling-cells = <2>; 131 #cooling-cells = <2>;
136 L2_300: l2-cache { 132 L2_300: l2-cache {
137 compatible = " 133 compatible = "cache";
138 cache-level = 134 cache-level = <2>;
139 cache-unified; 135 cache-unified;
140 next-level-cac 136 next-level-cache = <&L3_0>;
141 }; 137 };
142 }; 138 };
143 139
144 CPU4: cpu@400 { 140 CPU4: cpu@400 {
145 device_type = "cpu"; 141 device_type = "cpu";
146 compatible = "arm,cort 142 compatible = "arm,cortex-x1c";
147 reg = <0x0 0x400>; 143 reg = <0x0 0x400>;
148 clocks = <&cpufreq_hw 144 clocks = <&cpufreq_hw 1>;
149 enable-method = "psci" 145 enable-method = "psci";
150 capacity-dmips-mhz = < 146 capacity-dmips-mhz = <1024>;
151 dynamic-power-coeffici <<
152 next-level-cache = <&L 147 next-level-cache = <&L2_400>;
153 power-domains = <&CPU_ 148 power-domains = <&CPU_PD4>;
154 power-domain-names = " 149 power-domain-names = "psci";
155 qcom,freq-domain = <&c 150 qcom,freq-domain = <&cpufreq_hw 1>;
156 operating-points-v2 = 151 operating-points-v2 = <&cpu4_opp_table>;
157 interconnects = <&epss 152 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
158 #cooling-cells = <2>; 153 #cooling-cells = <2>;
159 L2_400: l2-cache { 154 L2_400: l2-cache {
160 compatible = " 155 compatible = "cache";
161 cache-level = 156 cache-level = <2>;
162 cache-unified; 157 cache-unified;
163 next-level-cac 158 next-level-cache = <&L3_0>;
164 }; 159 };
165 }; 160 };
166 161
167 CPU5: cpu@500 { 162 CPU5: cpu@500 {
168 device_type = "cpu"; 163 device_type = "cpu";
169 compatible = "arm,cort 164 compatible = "arm,cortex-x1c";
170 reg = <0x0 0x500>; 165 reg = <0x0 0x500>;
171 clocks = <&cpufreq_hw 166 clocks = <&cpufreq_hw 1>;
172 enable-method = "psci" 167 enable-method = "psci";
173 capacity-dmips-mhz = < 168 capacity-dmips-mhz = <1024>;
174 dynamic-power-coeffici <<
175 next-level-cache = <&L 169 next-level-cache = <&L2_500>;
176 power-domains = <&CPU_ 170 power-domains = <&CPU_PD5>;
177 power-domain-names = " 171 power-domain-names = "psci";
178 qcom,freq-domain = <&c 172 qcom,freq-domain = <&cpufreq_hw 1>;
179 operating-points-v2 = 173 operating-points-v2 = <&cpu4_opp_table>;
180 interconnects = <&epss 174 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
181 #cooling-cells = <2>; 175 #cooling-cells = <2>;
182 L2_500: l2-cache { 176 L2_500: l2-cache {
183 compatible = " 177 compatible = "cache";
184 cache-level = 178 cache-level = <2>;
185 cache-unified; 179 cache-unified;
186 next-level-cac 180 next-level-cache = <&L3_0>;
187 }; 181 };
188 }; 182 };
189 183
190 CPU6: cpu@600 { 184 CPU6: cpu@600 {
191 device_type = "cpu"; 185 device_type = "cpu";
192 compatible = "arm,cort 186 compatible = "arm,cortex-x1c";
193 reg = <0x0 0x600>; 187 reg = <0x0 0x600>;
194 clocks = <&cpufreq_hw 188 clocks = <&cpufreq_hw 1>;
195 enable-method = "psci" 189 enable-method = "psci";
196 capacity-dmips-mhz = < 190 capacity-dmips-mhz = <1024>;
197 dynamic-power-coeffici <<
198 next-level-cache = <&L 191 next-level-cache = <&L2_600>;
199 power-domains = <&CPU_ 192 power-domains = <&CPU_PD6>;
200 power-domain-names = " 193 power-domain-names = "psci";
201 qcom,freq-domain = <&c 194 qcom,freq-domain = <&cpufreq_hw 1>;
202 operating-points-v2 = 195 operating-points-v2 = <&cpu4_opp_table>;
203 interconnects = <&epss 196 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
204 #cooling-cells = <2>; 197 #cooling-cells = <2>;
205 L2_600: l2-cache { 198 L2_600: l2-cache {
206 compatible = " 199 compatible = "cache";
207 cache-level = 200 cache-level = <2>;
208 cache-unified; 201 cache-unified;
209 next-level-cac 202 next-level-cache = <&L3_0>;
210 }; 203 };
211 }; 204 };
212 205
213 CPU7: cpu@700 { 206 CPU7: cpu@700 {
214 device_type = "cpu"; 207 device_type = "cpu";
215 compatible = "arm,cort 208 compatible = "arm,cortex-x1c";
216 reg = <0x0 0x700>; 209 reg = <0x0 0x700>;
217 clocks = <&cpufreq_hw 210 clocks = <&cpufreq_hw 1>;
218 enable-method = "psci" 211 enable-method = "psci";
219 capacity-dmips-mhz = < 212 capacity-dmips-mhz = <1024>;
220 dynamic-power-coeffici <<
221 next-level-cache = <&L 213 next-level-cache = <&L2_700>;
222 power-domains = <&CPU_ 214 power-domains = <&CPU_PD7>;
223 power-domain-names = " 215 power-domain-names = "psci";
224 qcom,freq-domain = <&c 216 qcom,freq-domain = <&cpufreq_hw 1>;
225 operating-points-v2 = 217 operating-points-v2 = <&cpu4_opp_table>;
226 interconnects = <&epss 218 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
227 #cooling-cells = <2>; 219 #cooling-cells = <2>;
228 L2_700: l2-cache { 220 L2_700: l2-cache {
229 compatible = " 221 compatible = "cache";
230 cache-level = 222 cache-level = <2>;
231 cache-unified; 223 cache-unified;
232 next-level-cac 224 next-level-cache = <&L3_0>;
233 }; 225 };
234 }; 226 };
235 227
236 cpu-map { 228 cpu-map {
237 cluster0 { 229 cluster0 {
238 core0 { 230 core0 {
239 cpu = 231 cpu = <&CPU0>;
240 }; 232 };
241 233
242 core1 { 234 core1 {
243 cpu = 235 cpu = <&CPU1>;
244 }; 236 };
245 237
246 core2 { 238 core2 {
247 cpu = 239 cpu = <&CPU2>;
248 }; 240 };
249 241
250 core3 { 242 core3 {
251 cpu = 243 cpu = <&CPU3>;
252 }; 244 };
253 245
254 core4 { 246 core4 {
255 cpu = 247 cpu = <&CPU4>;
256 }; 248 };
257 249
258 core5 { 250 core5 {
259 cpu = 251 cpu = <&CPU5>;
260 }; 252 };
261 253
262 core6 { 254 core6 {
263 cpu = 255 cpu = <&CPU6>;
264 }; 256 };
265 257
266 core7 { 258 core7 {
267 cpu = 259 cpu = <&CPU7>;
268 }; 260 };
269 }; 261 };
270 }; 262 };
271 263
272 idle-states { 264 idle-states {
273 entry-method = "psci"; 265 entry-method = "psci";
274 266
275 LITTLE_CPU_SLEEP_0: cp 267 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
276 compatible = " 268 compatible = "arm,idle-state";
277 idle-state-nam 269 idle-state-name = "little-rail-power-collapse";
278 arm,psci-suspe 270 arm,psci-suspend-param = <0x40000004>;
279 entry-latency- 271 entry-latency-us = <355>;
280 exit-latency-u 272 exit-latency-us = <909>;
281 min-residency- 273 min-residency-us = <3934>;
282 local-timer-st 274 local-timer-stop;
283 }; 275 };
284 276
285 BIG_CPU_SLEEP_0: cpu-s 277 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
286 compatible = " 278 compatible = "arm,idle-state";
287 idle-state-nam 279 idle-state-name = "big-rail-power-collapse";
288 arm,psci-suspe 280 arm,psci-suspend-param = <0x40000004>;
289 entry-latency- 281 entry-latency-us = <241>;
290 exit-latency-u 282 exit-latency-us = <1461>;
291 min-residency- 283 min-residency-us = <4488>;
292 local-timer-st 284 local-timer-stop;
293 }; 285 };
294 }; 286 };
295 287
296 domain-idle-states { 288 domain-idle-states {
297 CLUSTER_SLEEP_0: clust 289 CLUSTER_SLEEP_0: cluster-sleep-0 {
298 compatible = " 290 compatible = "domain-idle-state";
299 arm,psci-suspe 291 arm,psci-suspend-param = <0x4100c344>;
300 entry-latency- 292 entry-latency-us = <3263>;
301 exit-latency-u 293 exit-latency-us = <6562>;
302 min-residency- 294 min-residency-us = <9987>;
303 }; 295 };
304 }; 296 };
305 }; 297 };
306 298
307 firmware { 299 firmware {
308 scm: scm { 300 scm: scm {
309 compatible = "qcom,scm 301 compatible = "qcom,scm-sc8280xp", "qcom,scm";
310 interconnects = <&aggr 302 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
311 qcom,dload-mode = <&tc <<
312 }; 303 };
313 }; 304 };
314 305
315 aggre1_noc: interconnect-aggre1-noc { 306 aggre1_noc: interconnect-aggre1-noc {
316 compatible = "qcom,sc8280xp-ag 307 compatible = "qcom,sc8280xp-aggre1-noc";
317 #interconnect-cells = <2>; 308 #interconnect-cells = <2>;
318 qcom,bcm-voters = <&apps_bcm_v 309 qcom,bcm-voters = <&apps_bcm_voter>;
319 }; 310 };
320 311
321 aggre2_noc: interconnect-aggre2-noc { 312 aggre2_noc: interconnect-aggre2-noc {
322 compatible = "qcom,sc8280xp-ag 313 compatible = "qcom,sc8280xp-aggre2-noc";
323 #interconnect-cells = <2>; 314 #interconnect-cells = <2>;
324 qcom,bcm-voters = <&apps_bcm_v 315 qcom,bcm-voters = <&apps_bcm_voter>;
325 }; 316 };
326 317
327 clk_virt: interconnect-clk-virt { 318 clk_virt: interconnect-clk-virt {
328 compatible = "qcom,sc8280xp-cl 319 compatible = "qcom,sc8280xp-clk-virt";
329 #interconnect-cells = <2>; 320 #interconnect-cells = <2>;
330 qcom,bcm-voters = <&apps_bcm_v 321 qcom,bcm-voters = <&apps_bcm_voter>;
331 }; 322 };
332 323
333 config_noc: interconnect-config-noc { 324 config_noc: interconnect-config-noc {
334 compatible = "qcom,sc8280xp-co 325 compatible = "qcom,sc8280xp-config-noc";
335 #interconnect-cells = <2>; 326 #interconnect-cells = <2>;
336 qcom,bcm-voters = <&apps_bcm_v 327 qcom,bcm-voters = <&apps_bcm_voter>;
337 }; 328 };
338 329
339 dc_noc: interconnect-dc-noc { 330 dc_noc: interconnect-dc-noc {
340 compatible = "qcom,sc8280xp-dc 331 compatible = "qcom,sc8280xp-dc-noc";
341 #interconnect-cells = <2>; 332 #interconnect-cells = <2>;
342 qcom,bcm-voters = <&apps_bcm_v 333 qcom,bcm-voters = <&apps_bcm_voter>;
343 }; 334 };
344 335
345 gem_noc: interconnect-gem-noc { 336 gem_noc: interconnect-gem-noc {
346 compatible = "qcom,sc8280xp-ge 337 compatible = "qcom,sc8280xp-gem-noc";
347 #interconnect-cells = <2>; 338 #interconnect-cells = <2>;
348 qcom,bcm-voters = <&apps_bcm_v 339 qcom,bcm-voters = <&apps_bcm_voter>;
349 }; 340 };
350 341
351 lpass_noc: interconnect-lpass-ag-noc { 342 lpass_noc: interconnect-lpass-ag-noc {
352 compatible = "qcom,sc8280xp-lp 343 compatible = "qcom,sc8280xp-lpass-ag-noc";
353 #interconnect-cells = <2>; 344 #interconnect-cells = <2>;
354 qcom,bcm-voters = <&apps_bcm_v 345 qcom,bcm-voters = <&apps_bcm_voter>;
355 }; 346 };
356 347
357 mc_virt: interconnect-mc-virt { 348 mc_virt: interconnect-mc-virt {
358 compatible = "qcom,sc8280xp-mc 349 compatible = "qcom,sc8280xp-mc-virt";
359 #interconnect-cells = <2>; 350 #interconnect-cells = <2>;
360 qcom,bcm-voters = <&apps_bcm_v 351 qcom,bcm-voters = <&apps_bcm_voter>;
361 }; 352 };
362 353
363 mmss_noc: interconnect-mmss-noc { 354 mmss_noc: interconnect-mmss-noc {
364 compatible = "qcom,sc8280xp-mm 355 compatible = "qcom,sc8280xp-mmss-noc";
365 #interconnect-cells = <2>; 356 #interconnect-cells = <2>;
366 qcom,bcm-voters = <&apps_bcm_v 357 qcom,bcm-voters = <&apps_bcm_voter>;
367 }; 358 };
368 359
369 nspa_noc: interconnect-nspa-noc { 360 nspa_noc: interconnect-nspa-noc {
370 compatible = "qcom,sc8280xp-ns 361 compatible = "qcom,sc8280xp-nspa-noc";
371 #interconnect-cells = <2>; 362 #interconnect-cells = <2>;
372 qcom,bcm-voters = <&apps_bcm_v 363 qcom,bcm-voters = <&apps_bcm_voter>;
373 }; 364 };
374 365
375 nspb_noc: interconnect-nspb-noc { 366 nspb_noc: interconnect-nspb-noc {
376 compatible = "qcom,sc8280xp-ns 367 compatible = "qcom,sc8280xp-nspb-noc";
377 #interconnect-cells = <2>; 368 #interconnect-cells = <2>;
378 qcom,bcm-voters = <&apps_bcm_v 369 qcom,bcm-voters = <&apps_bcm_voter>;
379 }; 370 };
380 371
381 system_noc: interconnect-system-noc { 372 system_noc: interconnect-system-noc {
382 compatible = "qcom,sc8280xp-sy 373 compatible = "qcom,sc8280xp-system-noc";
383 #interconnect-cells = <2>; 374 #interconnect-cells = <2>;
384 qcom,bcm-voters = <&apps_bcm_v 375 qcom,bcm-voters = <&apps_bcm_voter>;
385 }; 376 };
386 377
387 memory@80000000 { 378 memory@80000000 {
388 device_type = "memory"; 379 device_type = "memory";
389 /* We expect the bootloader to 380 /* We expect the bootloader to fill in the size */
390 reg = <0x0 0x80000000 0x0 0x0> 381 reg = <0x0 0x80000000 0x0 0x0>;
391 }; 382 };
392 383
393 cpu0_opp_table: opp-table-cpu0 { 384 cpu0_opp_table: opp-table-cpu0 {
394 compatible = "operating-points 385 compatible = "operating-points-v2";
395 opp-shared; 386 opp-shared;
396 387
397 opp-300000000 { 388 opp-300000000 {
398 opp-hz = /bits/ 64 <30 389 opp-hz = /bits/ 64 <300000000>;
399 opp-peak-kBps = <(3000 390 opp-peak-kBps = <(300000 * 32)>;
400 }; 391 };
401 opp-403200000 { 392 opp-403200000 {
402 opp-hz = /bits/ 64 <40 393 opp-hz = /bits/ 64 <403200000>;
403 opp-peak-kBps = <(3840 394 opp-peak-kBps = <(384000 * 32)>;
404 }; 395 };
405 opp-499200000 { 396 opp-499200000 {
406 opp-hz = /bits/ 64 <49 397 opp-hz = /bits/ 64 <499200000>;
407 opp-peak-kBps = <(4800 398 opp-peak-kBps = <(480000 * 32)>;
408 }; 399 };
409 opp-595200000 { 400 opp-595200000 {
410 opp-hz = /bits/ 64 <59 401 opp-hz = /bits/ 64 <595200000>;
411 opp-peak-kBps = <(5760 402 opp-peak-kBps = <(576000 * 32)>;
412 }; 403 };
413 opp-691200000 { 404 opp-691200000 {
414 opp-hz = /bits/ 64 <69 405 opp-hz = /bits/ 64 <691200000>;
415 opp-peak-kBps = <(6720 406 opp-peak-kBps = <(672000 * 32)>;
416 }; 407 };
417 opp-806400000 { 408 opp-806400000 {
418 opp-hz = /bits/ 64 <80 409 opp-hz = /bits/ 64 <806400000>;
419 opp-peak-kBps = <(7680 410 opp-peak-kBps = <(768000 * 32)>;
420 }; 411 };
421 opp-902400000 { 412 opp-902400000 {
422 opp-hz = /bits/ 64 <90 413 opp-hz = /bits/ 64 <902400000>;
423 opp-peak-kBps = <(8640 414 opp-peak-kBps = <(864000 * 32)>;
424 }; 415 };
425 opp-1017600000 { 416 opp-1017600000 {
426 opp-hz = /bits/ 64 <10 417 opp-hz = /bits/ 64 <1017600000>;
427 opp-peak-kBps = <(9600 418 opp-peak-kBps = <(960000 * 32)>;
428 }; 419 };
429 opp-1113600000 { 420 opp-1113600000 {
430 opp-hz = /bits/ 64 <11 421 opp-hz = /bits/ 64 <1113600000>;
431 opp-peak-kBps = <(1075 422 opp-peak-kBps = <(1075200 * 32)>;
432 }; 423 };
433 opp-1209600000 { 424 opp-1209600000 {
434 opp-hz = /bits/ 64 <12 425 opp-hz = /bits/ 64 <1209600000>;
435 opp-peak-kBps = <(1171 426 opp-peak-kBps = <(1171200 * 32)>;
436 }; 427 };
437 opp-1324800000 { 428 opp-1324800000 {
438 opp-hz = /bits/ 64 <13 429 opp-hz = /bits/ 64 <1324800000>;
439 opp-peak-kBps = <(1267 430 opp-peak-kBps = <(1267200 * 32)>;
440 }; 431 };
441 opp-1440000000 { 432 opp-1440000000 {
442 opp-hz = /bits/ 64 <14 433 opp-hz = /bits/ 64 <1440000000>;
443 opp-peak-kBps = <(1363 434 opp-peak-kBps = <(1363200 * 32)>;
444 }; 435 };
445 opp-1555200000 { 436 opp-1555200000 {
446 opp-hz = /bits/ 64 <15 437 opp-hz = /bits/ 64 <1555200000>;
447 opp-peak-kBps = <(1536 438 opp-peak-kBps = <(1536000 * 32)>;
448 }; 439 };
449 opp-1670400000 { 440 opp-1670400000 {
450 opp-hz = /bits/ 64 <16 441 opp-hz = /bits/ 64 <1670400000>;
451 opp-peak-kBps = <(1612 442 opp-peak-kBps = <(1612800 * 32)>;
452 }; 443 };
453 opp-1785600000 { 444 opp-1785600000 {
454 opp-hz = /bits/ 64 <17 445 opp-hz = /bits/ 64 <1785600000>;
455 opp-peak-kBps = <(1689 446 opp-peak-kBps = <(1689600 * 32)>;
456 }; 447 };
457 opp-1881600000 { 448 opp-1881600000 {
458 opp-hz = /bits/ 64 <18 449 opp-hz = /bits/ 64 <1881600000>;
459 opp-peak-kBps = <(1689 450 opp-peak-kBps = <(1689600 * 32)>;
460 }; 451 };
461 opp-1996800000 { 452 opp-1996800000 {
462 opp-hz = /bits/ 64 <19 453 opp-hz = /bits/ 64 <1996800000>;
463 opp-peak-kBps = <(1689 454 opp-peak-kBps = <(1689600 * 32)>;
464 }; 455 };
465 opp-2112000000 { 456 opp-2112000000 {
466 opp-hz = /bits/ 64 <21 457 opp-hz = /bits/ 64 <2112000000>;
467 opp-peak-kBps = <(1689 458 opp-peak-kBps = <(1689600 * 32)>;
468 }; 459 };
469 opp-2227200000 { 460 opp-2227200000 {
470 opp-hz = /bits/ 64 <22 461 opp-hz = /bits/ 64 <2227200000>;
471 opp-peak-kBps = <(1689 462 opp-peak-kBps = <(1689600 * 32)>;
472 }; 463 };
473 opp-2342400000 { 464 opp-2342400000 {
474 opp-hz = /bits/ 64 <23 465 opp-hz = /bits/ 64 <2342400000>;
475 opp-peak-kBps = <(1689 466 opp-peak-kBps = <(1689600 * 32)>;
476 }; 467 };
477 opp-2438400000 { 468 opp-2438400000 {
478 opp-hz = /bits/ 64 <24 469 opp-hz = /bits/ 64 <2438400000>;
479 opp-peak-kBps = <(1689 470 opp-peak-kBps = <(1689600 * 32)>;
480 }; 471 };
481 }; 472 };
482 473
483 cpu4_opp_table: opp-table-cpu4 { 474 cpu4_opp_table: opp-table-cpu4 {
484 compatible = "operating-points 475 compatible = "operating-points-v2";
485 opp-shared; 476 opp-shared;
486 477
487 opp-825600000 { 478 opp-825600000 {
488 opp-hz = /bits/ 64 <82 479 opp-hz = /bits/ 64 <825600000>;
489 opp-peak-kBps = <(7680 480 opp-peak-kBps = <(768000 * 32)>;
490 }; 481 };
491 opp-940800000 { 482 opp-940800000 {
492 opp-hz = /bits/ 64 <94 483 opp-hz = /bits/ 64 <940800000>;
493 opp-peak-kBps = <(8640 484 opp-peak-kBps = <(864000 * 32)>;
494 }; 485 };
495 opp-1056000000 { 486 opp-1056000000 {
496 opp-hz = /bits/ 64 <10 487 opp-hz = /bits/ 64 <1056000000>;
497 opp-peak-kBps = <(9600 488 opp-peak-kBps = <(960000 * 32)>;
498 }; 489 };
499 opp-1171200000 { 490 opp-1171200000 {
500 opp-hz = /bits/ 64 <11 491 opp-hz = /bits/ 64 <1171200000>;
501 opp-peak-kBps = <(1171 492 opp-peak-kBps = <(1171200 * 32)>;
502 }; 493 };
503 opp-1286400000 { 494 opp-1286400000 {
504 opp-hz = /bits/ 64 <12 495 opp-hz = /bits/ 64 <1286400000>;
505 opp-peak-kBps = <(1267 496 opp-peak-kBps = <(1267200 * 32)>;
506 }; 497 };
507 opp-1401600000 { 498 opp-1401600000 {
508 opp-hz = /bits/ 64 <14 499 opp-hz = /bits/ 64 <1401600000>;
509 opp-peak-kBps = <(1363 500 opp-peak-kBps = <(1363200 * 32)>;
510 }; 501 };
511 opp-1516800000 { 502 opp-1516800000 {
512 opp-hz = /bits/ 64 <15 503 opp-hz = /bits/ 64 <1516800000>;
513 opp-peak-kBps = <(1459 504 opp-peak-kBps = <(1459200 * 32)>;
514 }; 505 };
515 opp-1632000000 { 506 opp-1632000000 {
516 opp-hz = /bits/ 64 <16 507 opp-hz = /bits/ 64 <1632000000>;
517 opp-peak-kBps = <(1612 508 opp-peak-kBps = <(1612800 * 32)>;
518 }; 509 };
519 opp-1747200000 { 510 opp-1747200000 {
520 opp-hz = /bits/ 64 <17 511 opp-hz = /bits/ 64 <1747200000>;
521 opp-peak-kBps = <(1689 512 opp-peak-kBps = <(1689600 * 32)>;
522 }; 513 };
523 opp-1862400000 { 514 opp-1862400000 {
524 opp-hz = /bits/ 64 <18 515 opp-hz = /bits/ 64 <1862400000>;
525 opp-peak-kBps = <(1689 516 opp-peak-kBps = <(1689600 * 32)>;
526 }; 517 };
527 opp-1977600000 { 518 opp-1977600000 {
528 opp-hz = /bits/ 64 <19 519 opp-hz = /bits/ 64 <1977600000>;
529 opp-peak-kBps = <(1689 520 opp-peak-kBps = <(1689600 * 32)>;
530 }; 521 };
531 opp-2073600000 { 522 opp-2073600000 {
532 opp-hz = /bits/ 64 <20 523 opp-hz = /bits/ 64 <2073600000>;
533 opp-peak-kBps = <(1689 524 opp-peak-kBps = <(1689600 * 32)>;
534 }; 525 };
535 opp-2169600000 { 526 opp-2169600000 {
536 opp-hz = /bits/ 64 <21 527 opp-hz = /bits/ 64 <2169600000>;
537 opp-peak-kBps = <(1689 528 opp-peak-kBps = <(1689600 * 32)>;
538 }; 529 };
539 opp-2284800000 { 530 opp-2284800000 {
540 opp-hz = /bits/ 64 <22 531 opp-hz = /bits/ 64 <2284800000>;
541 opp-peak-kBps = <(1689 532 opp-peak-kBps = <(1689600 * 32)>;
542 }; 533 };
543 opp-2400000000 { 534 opp-2400000000 {
544 opp-hz = /bits/ 64 <24 535 opp-hz = /bits/ 64 <2400000000>;
545 opp-peak-kBps = <(1689 536 opp-peak-kBps = <(1689600 * 32)>;
546 }; 537 };
547 opp-2496000000 { 538 opp-2496000000 {
548 opp-hz = /bits/ 64 <24 539 opp-hz = /bits/ 64 <2496000000>;
549 opp-peak-kBps = <(1689 540 opp-peak-kBps = <(1689600 * 32)>;
550 }; 541 };
551 opp-2592000000 { 542 opp-2592000000 {
552 opp-hz = /bits/ 64 <25 543 opp-hz = /bits/ 64 <2592000000>;
553 opp-peak-kBps = <(1689 544 opp-peak-kBps = <(1689600 * 32)>;
554 }; 545 };
555 opp-2688000000 { 546 opp-2688000000 {
556 opp-hz = /bits/ 64 <26 547 opp-hz = /bits/ 64 <2688000000>;
557 opp-peak-kBps = <(1689 548 opp-peak-kBps = <(1689600 * 32)>;
558 }; 549 };
559 opp-2803200000 { 550 opp-2803200000 {
560 opp-hz = /bits/ 64 <28 551 opp-hz = /bits/ 64 <2803200000>;
561 opp-peak-kBps = <(1689 552 opp-peak-kBps = <(1689600 * 32)>;
562 }; 553 };
563 opp-2899200000 { 554 opp-2899200000 {
564 opp-hz = /bits/ 64 <28 555 opp-hz = /bits/ 64 <2899200000>;
565 opp-peak-kBps = <(1689 556 opp-peak-kBps = <(1689600 * 32)>;
566 }; 557 };
567 opp-2995200000 { 558 opp-2995200000 {
568 opp-hz = /bits/ 64 <29 559 opp-hz = /bits/ 64 <2995200000>;
569 opp-peak-kBps = <(1689 560 opp-peak-kBps = <(1689600 * 32)>;
570 }; 561 };
571 }; 562 };
572 563
573 qup_opp_table_100mhz: opp-table-qup100 564 qup_opp_table_100mhz: opp-table-qup100mhz {
574 compatible = "operating-points 565 compatible = "operating-points-v2";
575 566
576 opp-75000000 { 567 opp-75000000 {
577 opp-hz = /bits/ 64 <75 568 opp-hz = /bits/ 64 <75000000>;
578 required-opps = <&rpmh 569 required-opps = <&rpmhpd_opp_low_svs>;
579 }; 570 };
580 571
581 opp-100000000 { 572 opp-100000000 {
582 opp-hz = /bits/ 64 <10 573 opp-hz = /bits/ 64 <100000000>;
583 required-opps = <&rpmh 574 required-opps = <&rpmhpd_opp_svs>;
584 }; 575 };
585 }; 576 };
586 577
587 pmu { 578 pmu {
588 compatible = "arm,armv8-pmuv3" 579 compatible = "arm,armv8-pmuv3";
589 interrupts = <GIC_PPI 7 IRQ_TY 580 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
590 }; 581 };
591 582
592 psci { 583 psci {
593 compatible = "arm,psci-1.0"; 584 compatible = "arm,psci-1.0";
594 method = "smc"; 585 method = "smc";
595 586
596 CPU_PD0: power-domain-cpu0 { 587 CPU_PD0: power-domain-cpu0 {
597 #power-domain-cells = 588 #power-domain-cells = <0>;
598 power-domains = <&CLUS 589 power-domains = <&CLUSTER_PD>;
599 domain-idle-states = < 590 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
600 }; 591 };
601 592
602 CPU_PD1: power-domain-cpu1 { 593 CPU_PD1: power-domain-cpu1 {
603 #power-domain-cells = 594 #power-domain-cells = <0>;
604 power-domains = <&CLUS 595 power-domains = <&CLUSTER_PD>;
605 domain-idle-states = < 596 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
606 }; 597 };
607 598
608 CPU_PD2: power-domain-cpu2 { 599 CPU_PD2: power-domain-cpu2 {
609 #power-domain-cells = 600 #power-domain-cells = <0>;
610 power-domains = <&CLUS 601 power-domains = <&CLUSTER_PD>;
611 domain-idle-states = < 602 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
612 }; 603 };
613 604
614 CPU_PD3: power-domain-cpu3 { 605 CPU_PD3: power-domain-cpu3 {
615 #power-domain-cells = 606 #power-domain-cells = <0>;
616 power-domains = <&CLUS 607 power-domains = <&CLUSTER_PD>;
617 domain-idle-states = < 608 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
618 }; 609 };
619 610
620 CPU_PD4: power-domain-cpu4 { 611 CPU_PD4: power-domain-cpu4 {
621 #power-domain-cells = 612 #power-domain-cells = <0>;
622 power-domains = <&CLUS 613 power-domains = <&CLUSTER_PD>;
623 domain-idle-states = < 614 domain-idle-states = <&BIG_CPU_SLEEP_0>;
624 }; 615 };
625 616
626 CPU_PD5: power-domain-cpu5 { 617 CPU_PD5: power-domain-cpu5 {
627 #power-domain-cells = 618 #power-domain-cells = <0>;
628 power-domains = <&CLUS 619 power-domains = <&CLUSTER_PD>;
629 domain-idle-states = < 620 domain-idle-states = <&BIG_CPU_SLEEP_0>;
630 }; 621 };
631 622
632 CPU_PD6: power-domain-cpu6 { 623 CPU_PD6: power-domain-cpu6 {
633 #power-domain-cells = 624 #power-domain-cells = <0>;
634 power-domains = <&CLUS 625 power-domains = <&CLUSTER_PD>;
635 domain-idle-states = < 626 domain-idle-states = <&BIG_CPU_SLEEP_0>;
636 }; 627 };
637 628
638 CPU_PD7: power-domain-cpu7 { 629 CPU_PD7: power-domain-cpu7 {
639 #power-domain-cells = 630 #power-domain-cells = <0>;
640 power-domains = <&CLUS 631 power-domains = <&CLUSTER_PD>;
641 domain-idle-states = < 632 domain-idle-states = <&BIG_CPU_SLEEP_0>;
642 }; 633 };
643 634
644 CLUSTER_PD: power-domain-cpu-c 635 CLUSTER_PD: power-domain-cpu-cluster0 {
645 #power-domain-cells = 636 #power-domain-cells = <0>;
646 domain-idle-states = < 637 domain-idle-states = <&CLUSTER_SLEEP_0>;
647 }; 638 };
648 }; 639 };
649 640
650 reserved-memory { 641 reserved-memory {
651 #address-cells = <2>; 642 #address-cells = <2>;
652 #size-cells = <2>; 643 #size-cells = <2>;
653 ranges; 644 ranges;
654 645
655 reserved-region@80000000 { 646 reserved-region@80000000 {
656 reg = <0 0x80000000 0 647 reg = <0 0x80000000 0 0x860000>;
657 no-map; 648 no-map;
658 }; 649 };
659 650
660 cmd_db: cmd-db-region@80860000 651 cmd_db: cmd-db-region@80860000 {
661 compatible = "qcom,cmd 652 compatible = "qcom,cmd-db";
662 reg = <0 0x80860000 0 653 reg = <0 0x80860000 0 0x20000>;
663 no-map; 654 no-map;
664 }; 655 };
665 656
666 reserved-region@80880000 { 657 reserved-region@80880000 {
667 reg = <0 0x80880000 0 658 reg = <0 0x80880000 0 0x80000>;
668 no-map; 659 no-map;
669 }; 660 };
670 661
671 smem_mem: smem-region@80900000 662 smem_mem: smem-region@80900000 {
672 compatible = "qcom,sme 663 compatible = "qcom,smem";
673 reg = <0 0x80900000 0 664 reg = <0 0x80900000 0 0x200000>;
674 no-map; 665 no-map;
675 hwlocks = <&tcsr_mutex 666 hwlocks = <&tcsr_mutex 3>;
676 }; 667 };
677 668
678 reserved-region@80b00000 { 669 reserved-region@80b00000 {
679 reg = <0 0x80b00000 0 670 reg = <0 0x80b00000 0 0x100000>;
680 no-map; 671 no-map;
681 }; 672 };
682 673
683 reserved-region@83b00000 { 674 reserved-region@83b00000 {
684 reg = <0 0x83b00000 0 675 reg = <0 0x83b00000 0 0x1700000>;
685 no-map; 676 no-map;
686 }; 677 };
687 678
688 reserved-region@85b00000 { 679 reserved-region@85b00000 {
689 reg = <0 0x85b00000 0 680 reg = <0 0x85b00000 0 0xc00000>;
690 no-map; 681 no-map;
691 }; 682 };
692 683
693 pil_adsp_mem: adsp-region@86c0 684 pil_adsp_mem: adsp-region@86c00000 {
694 reg = <0 0x86c00000 0 685 reg = <0 0x86c00000 0 0x2000000>;
695 no-map; 686 no-map;
696 }; 687 };
697 688
698 pil_nsp0_mem: cdsp0-region@8a1 689 pil_nsp0_mem: cdsp0-region@8a100000 {
699 reg = <0 0x8a100000 0 690 reg = <0 0x8a100000 0 0x1e00000>;
700 no-map; 691 no-map;
701 }; 692 };
702 693
703 pil_nsp1_mem: cdsp1-region@8c6 694 pil_nsp1_mem: cdsp1-region@8c600000 {
704 reg = <0 0x8c600000 0 695 reg = <0 0x8c600000 0 0x1e00000>;
705 no-map; 696 no-map;
706 }; 697 };
707 698
708 reserved-region@aeb00000 { 699 reserved-region@aeb00000 {
709 reg = <0 0xaeb00000 0 700 reg = <0 0xaeb00000 0 0x16600000>;
710 no-map; 701 no-map;
711 }; 702 };
712 }; 703 };
713 704
714 smp2p-adsp { 705 smp2p-adsp {
715 compatible = "qcom,smp2p"; 706 compatible = "qcom,smp2p";
716 qcom,smem = <443>, <429>; 707 qcom,smem = <443>, <429>;
717 interrupts-extended = <&ipcc I 708 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
718 I 709 IPCC_MPROC_SIGNAL_SMP2P
719 I 710 IRQ_TYPE_EDGE_RISING>;
720 mboxes = <&ipcc IPCC_CLIENT_LP 711 mboxes = <&ipcc IPCC_CLIENT_LPASS
721 IPCC_MPROC_SIG 712 IPCC_MPROC_SIGNAL_SMP2P>;
722 713
723 qcom,local-pid = <0>; 714 qcom,local-pid = <0>;
724 qcom,remote-pid = <2>; 715 qcom,remote-pid = <2>;
725 716
726 smp2p_adsp_out: master-kernel 717 smp2p_adsp_out: master-kernel {
727 qcom,entry-name = "mas 718 qcom,entry-name = "master-kernel";
728 #qcom,smem-state-cells 719 #qcom,smem-state-cells = <1>;
729 }; 720 };
730 721
731 smp2p_adsp_in: slave-kernel { 722 smp2p_adsp_in: slave-kernel {
732 qcom,entry-name = "sla 723 qcom,entry-name = "slave-kernel";
733 interrupt-controller; 724 interrupt-controller;
734 #interrupt-cells = <2> 725 #interrupt-cells = <2>;
735 }; 726 };
736 }; 727 };
737 728
738 smp2p-nsp0 { 729 smp2p-nsp0 {
739 compatible = "qcom,smp2p"; 730 compatible = "qcom,smp2p";
740 qcom,smem = <94>, <432>; 731 qcom,smem = <94>, <432>;
741 interrupts-extended = <&ipcc I 732 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
742 I 733 IPCC_MPROC_SIGNAL_SMP2P
743 I 734 IRQ_TYPE_EDGE_RISING>;
744 mboxes = <&ipcc IPCC_CLIENT_CD 735 mboxes = <&ipcc IPCC_CLIENT_CDSP
745 IPCC_MPROC_SIG 736 IPCC_MPROC_SIGNAL_SMP2P>;
746 737
747 qcom,local-pid = <0>; 738 qcom,local-pid = <0>;
748 qcom,remote-pid = <5>; 739 qcom,remote-pid = <5>;
749 740
750 smp2p_nsp0_out: master-kernel 741 smp2p_nsp0_out: master-kernel {
751 qcom,entry-name = "mas 742 qcom,entry-name = "master-kernel";
752 #qcom,smem-state-cells 743 #qcom,smem-state-cells = <1>;
753 }; 744 };
754 745
755 smp2p_nsp0_in: slave-kernel { 746 smp2p_nsp0_in: slave-kernel {
756 qcom,entry-name = "sla 747 qcom,entry-name = "slave-kernel";
757 interrupt-controller; 748 interrupt-controller;
758 #interrupt-cells = <2> 749 #interrupt-cells = <2>;
759 }; 750 };
760 }; 751 };
761 752
762 smp2p-nsp1 { 753 smp2p-nsp1 {
763 compatible = "qcom,smp2p"; 754 compatible = "qcom,smp2p";
764 qcom,smem = <617>, <616>; 755 qcom,smem = <617>, <616>;
765 interrupts-extended = <&ipcc I 756 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1
766 I 757 IPCC_MPROC_SIGNAL_SMP2P
767 I 758 IRQ_TYPE_EDGE_RISING>;
768 mboxes = <&ipcc IPCC_CLIENT_NS 759 mboxes = <&ipcc IPCC_CLIENT_NSP1
769 IPCC_MPROC_SIG 760 IPCC_MPROC_SIGNAL_SMP2P>;
770 761
771 qcom,local-pid = <0>; 762 qcom,local-pid = <0>;
772 qcom,remote-pid = <12>; 763 qcom,remote-pid = <12>;
773 764
774 smp2p_nsp1_out: master-kernel 765 smp2p_nsp1_out: master-kernel {
775 qcom,entry-name = "mas 766 qcom,entry-name = "master-kernel";
776 #qcom,smem-state-cells 767 #qcom,smem-state-cells = <1>;
777 }; 768 };
778 769
779 smp2p_nsp1_in: slave-kernel { 770 smp2p_nsp1_in: slave-kernel {
780 qcom,entry-name = "sla 771 qcom,entry-name = "slave-kernel";
781 interrupt-controller; 772 interrupt-controller;
782 #interrupt-cells = <2> 773 #interrupt-cells = <2>;
783 }; 774 };
784 }; 775 };
785 776
786 soc: soc@0 { 777 soc: soc@0 {
787 compatible = "simple-bus"; 778 compatible = "simple-bus";
788 #address-cells = <2>; 779 #address-cells = <2>;
789 #size-cells = <2>; 780 #size-cells = <2>;
790 ranges = <0 0 0 0 0x10 0>; 781 ranges = <0 0 0 0 0x10 0>;
791 dma-ranges = <0 0 0 0 0x10 0>; 782 dma-ranges = <0 0 0 0 0x10 0>;
792 783
793 ethernet0: ethernet@20000 { 784 ethernet0: ethernet@20000 {
794 compatible = "qcom,sc8 785 compatible = "qcom,sc8280xp-ethqos";
795 reg = <0x0 0x00020000 786 reg = <0x0 0x00020000 0x0 0x10000>,
796 <0x0 0x00036000 787 <0x0 0x00036000 0x0 0x100>;
797 reg-names = "stmmaceth 788 reg-names = "stmmaceth", "rgmii";
798 789
799 clocks = <&gcc GCC_EMA 790 clocks = <&gcc GCC_EMAC0_AXI_CLK>,
800 <&gcc GCC_EMA 791 <&gcc GCC_EMAC0_SLV_AHB_CLK>,
801 <&gcc GCC_EMA 792 <&gcc GCC_EMAC0_PTP_CLK>,
802 <&gcc GCC_EMA 793 <&gcc GCC_EMAC0_RGMII_CLK>;
803 clock-names = "stmmace 794 clock-names = "stmmaceth",
804 "pclk", 795 "pclk",
805 "ptp_ref 796 "ptp_ref",
806 "rgmii"; 797 "rgmii";
807 798
808 interrupts = <GIC_SPI 799 interrupts = <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>,
809 <GIC_SPI 800 <GIC_SPI 936 IRQ_TYPE_LEVEL_HIGH>;
810 interrupt-names = "mac 801 interrupt-names = "macirq", "eth_lpi";
811 802
812 iommus = <&apps_smmu 0 803 iommus = <&apps_smmu 0x4c0 0xf>;
813 power-domains = <&gcc 804 power-domains = <&gcc EMAC_0_GDSC>;
814 805
815 snps,tso; 806 snps,tso;
816 snps,pbl = <32>; 807 snps,pbl = <32>;
817 rx-fifo-depth = <4096> 808 rx-fifo-depth = <4096>;
818 tx-fifo-depth = <4096> 809 tx-fifo-depth = <4096>;
819 810
820 status = "disabled"; 811 status = "disabled";
821 }; 812 };
822 813
823 gcc: clock-controller@100000 { 814 gcc: clock-controller@100000 {
824 compatible = "qcom,gcc 815 compatible = "qcom,gcc-sc8280xp";
825 reg = <0x0 0x00100000 816 reg = <0x0 0x00100000 0x0 0x1f0000>;
826 #clock-cells = <1>; 817 #clock-cells = <1>;
827 #reset-cells = <1>; 818 #reset-cells = <1>;
828 #power-domain-cells = 819 #power-domain-cells = <1>;
829 clocks = <&rpmhcc RPMH 820 clocks = <&rpmhcc RPMH_CXO_CLK>,
830 <&sleep_clk>, 821 <&sleep_clk>,
831 <0>, 822 <0>,
832 <0>, 823 <0>,
833 <0>, 824 <0>,
834 <0>, 825 <0>,
835 <0>, 826 <0>,
836 <0>, 827 <0>,
837 <&usb_0_qmpph 828 <&usb_0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
838 <0>, 829 <0>,
839 <0>, 830 <0>,
840 <0>, 831 <0>,
841 <0>, 832 <0>,
842 <0>, 833 <0>,
843 <0>, 834 <0>,
844 <0>, 835 <0>,
845 <&usb_1_qmpph 836 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
846 <0>, 837 <0>,
847 <0>, 838 <0>,
848 <0>, 839 <0>,
849 <0>, 840 <0>,
850 <0>, 841 <0>,
851 <0>, 842 <0>,
852 <0>, 843 <0>,
853 <0>, 844 <0>,
854 <0>, 845 <0>,
855 <&pcie2a_phy> 846 <&pcie2a_phy>,
856 <&pcie2b_phy> 847 <&pcie2b_phy>,
857 <&pcie3a_phy> 848 <&pcie3a_phy>,
858 <&pcie3b_phy> 849 <&pcie3b_phy>,
859 <&pcie4_phy>, 850 <&pcie4_phy>,
860 <0>, 851 <0>,
861 <0>; 852 <0>;
862 power-domains = <&rpmh 853 power-domains = <&rpmhpd SC8280XP_CX>;
863 }; 854 };
864 855
865 ipcc: mailbox@408000 { 856 ipcc: mailbox@408000 {
866 compatible = "qcom,sc8 857 compatible = "qcom,sc8280xp-ipcc", "qcom,ipcc";
867 reg = <0 0x00408000 0 858 reg = <0 0x00408000 0 0x1000>;
868 interrupts = <GIC_SPI 859 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
869 interrupt-controller; 860 interrupt-controller;
870 #interrupt-cells = <3> 861 #interrupt-cells = <3>;
871 #mbox-cells = <2>; 862 #mbox-cells = <2>;
872 }; 863 };
873 864
874 qfprom: efuse@784000 { <<
875 compatible = "qcom,sc8 <<
876 reg = <0 0x00784000 0 <<
877 #address-cells = <1>; <<
878 #size-cells = <1>; <<
879 <<
880 gpu_speed_bin: gpu-spe <<
881 reg = <0x18b 0 <<
882 bits = <5 3>; <<
883 }; <<
884 }; <<
885 <<
886 qup2: geniqup@8c0000 { 865 qup2: geniqup@8c0000 {
887 compatible = "qcom,gen 866 compatible = "qcom,geni-se-qup";
888 reg = <0 0x008c0000 0 867 reg = <0 0x008c0000 0 0x2000>;
889 clocks = <&gcc GCC_QUP 868 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
890 <&gcc GCC_QUP 869 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
891 clock-names = "m-ahb", 870 clock-names = "m-ahb", "s-ahb";
892 iommus = <&apps_smmu 0 871 iommus = <&apps_smmu 0xa3 0>;
893 872
894 #address-cells = <2>; 873 #address-cells = <2>;
895 #size-cells = <2>; 874 #size-cells = <2>;
896 ranges; 875 ranges;
897 876
898 status = "disabled"; 877 status = "disabled";
899 878
900 i2c16: i2c@880000 { 879 i2c16: i2c@880000 {
901 compatible = " 880 compatible = "qcom,geni-i2c";
902 reg = <0 0x008 881 reg = <0 0x00880000 0 0x4000>;
903 #address-cells 882 #address-cells = <1>;
904 #size-cells = 883 #size-cells = <0>;
905 clocks = <&gcc 884 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
906 clock-names = 885 clock-names = "se";
907 interrupts = < 886 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
908 power-domains 887 power-domains = <&rpmhpd SC8280XP_CX>;
909 interconnects 888 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
910 889 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
911 890 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
912 interconnect-n 891 interconnect-names = "qup-core", "qup-config", "qup-memory";
913 status = "disa 892 status = "disabled";
914 }; 893 };
915 894
916 spi16: spi@880000 { 895 spi16: spi@880000 {
917 compatible = " 896 compatible = "qcom,geni-spi";
918 reg = <0 0x008 897 reg = <0 0x00880000 0 0x4000>;
919 #address-cells 898 #address-cells = <1>;
920 #size-cells = 899 #size-cells = <0>;
921 clocks = <&gcc 900 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
922 clock-names = 901 clock-names = "se";
923 interrupts = < 902 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
924 power-domains 903 power-domains = <&rpmhpd SC8280XP_CX>;
925 interconnects 904 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
926 905 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
927 906 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
928 interconnect-n 907 interconnect-names = "qup-core", "qup-config", "qup-memory";
929 status = "disa 908 status = "disabled";
930 }; 909 };
931 910
932 i2c17: i2c@884000 { 911 i2c17: i2c@884000 {
933 compatible = " 912 compatible = "qcom,geni-i2c";
934 reg = <0 0x008 913 reg = <0 0x00884000 0 0x4000>;
935 #address-cells 914 #address-cells = <1>;
936 #size-cells = 915 #size-cells = <0>;
937 clocks = <&gcc 916 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
938 clock-names = 917 clock-names = "se";
939 interrupts = < 918 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
940 power-domains 919 power-domains = <&rpmhpd SC8280XP_CX>;
941 interconnects 920 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
942 921 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
943 922 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
944 interconnect-n 923 interconnect-names = "qup-core", "qup-config", "qup-memory";
945 status = "disa 924 status = "disabled";
946 }; 925 };
947 926
948 spi17: spi@884000 { 927 spi17: spi@884000 {
949 compatible = " 928 compatible = "qcom,geni-spi";
950 reg = <0 0x008 929 reg = <0 0x00884000 0 0x4000>;
951 #address-cells 930 #address-cells = <1>;
952 #size-cells = 931 #size-cells = <0>;
953 clocks = <&gcc 932 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
954 clock-names = 933 clock-names = "se";
955 interrupts = < 934 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
956 power-domains 935 power-domains = <&rpmhpd SC8280XP_CX>;
957 interconnects 936 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
958 937 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
959 938 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
960 interconnect-n 939 interconnect-names = "qup-core", "qup-config", "qup-memory";
961 status = "disa 940 status = "disabled";
962 }; 941 };
963 942
964 uart17: serial@884000 943 uart17: serial@884000 {
965 compatible = " 944 compatible = "qcom,geni-uart";
966 reg = <0 0x008 945 reg = <0 0x00884000 0 0x4000>;
967 clocks = <&gcc 946 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
968 clock-names = 947 clock-names = "se";
969 interrupts = < 948 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
970 operating-poin 949 operating-points-v2 = <&qup_opp_table_100mhz>;
971 power-domains 950 power-domains = <&rpmhpd SC8280XP_CX>;
972 interconnects 951 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
973 952 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>;
974 interconnect-n 953 interconnect-names = "qup-core", "qup-config";
975 status = "disa 954 status = "disabled";
976 }; 955 };
977 956
978 i2c18: i2c@888000 { 957 i2c18: i2c@888000 {
979 compatible = " 958 compatible = "qcom,geni-i2c";
980 reg = <0 0x008 959 reg = <0 0x00888000 0 0x4000>;
981 #address-cells 960 #address-cells = <1>;
982 #size-cells = 961 #size-cells = <0>;
983 clocks = <&gcc 962 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
984 clock-names = 963 clock-names = "se";
985 interrupts = < 964 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
986 power-domains 965 power-domains = <&rpmhpd SC8280XP_CX>;
987 interconnects 966 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
988 967 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
989 968 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
990 interconnect-n 969 interconnect-names = "qup-core", "qup-config", "qup-memory";
991 status = "disa 970 status = "disabled";
992 }; 971 };
993 972
994 spi18: spi@888000 { 973 spi18: spi@888000 {
995 compatible = " 974 compatible = "qcom,geni-spi";
996 reg = <0 0x008 975 reg = <0 0x00888000 0 0x4000>;
997 #address-cells 976 #address-cells = <1>;
998 #size-cells = 977 #size-cells = <0>;
999 clocks = <&gcc 978 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1000 clock-names = 979 clock-names = "se";
1001 interrupts = 980 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1002 power-domains 981 power-domains = <&rpmhpd SC8280XP_CX>;
1003 interconnects 982 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1004 983 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1005 984 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1006 interconnect- 985 interconnect-names = "qup-core", "qup-config", "qup-memory";
1007 status = "dis 986 status = "disabled";
1008 }; 987 };
1009 988
1010 i2c19: i2c@88c000 { 989 i2c19: i2c@88c000 {
1011 compatible = 990 compatible = "qcom,geni-i2c";
1012 reg = <0 0x00 991 reg = <0 0x0088c000 0 0x4000>;
1013 #address-cell 992 #address-cells = <1>;
1014 #size-cells = 993 #size-cells = <0>;
1015 clocks = <&gc 994 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1016 clock-names = 995 clock-names = "se";
1017 interrupts = 996 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1018 power-domains 997 power-domains = <&rpmhpd SC8280XP_CX>;
1019 interconnects 998 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1020 999 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1021 1000 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1022 interconnect- 1001 interconnect-names = "qup-core", "qup-config", "qup-memory";
1023 status = "dis 1002 status = "disabled";
1024 }; 1003 };
1025 1004
1026 spi19: spi@88c000 { 1005 spi19: spi@88c000 {
1027 compatible = 1006 compatible = "qcom,geni-spi";
1028 reg = <0 0x00 1007 reg = <0 0x0088c000 0 0x4000>;
1029 #address-cell 1008 #address-cells = <1>;
1030 #size-cells = 1009 #size-cells = <0>;
1031 clocks = <&gc 1010 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1032 clock-names = 1011 clock-names = "se";
1033 interrupts = 1012 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1034 power-domains 1013 power-domains = <&rpmhpd SC8280XP_CX>;
1035 interconnects 1014 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1036 1015 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1037 1016 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1038 interconnect- 1017 interconnect-names = "qup-core", "qup-config", "qup-memory";
1039 status = "dis 1018 status = "disabled";
1040 }; 1019 };
1041 1020
1042 i2c20: i2c@890000 { 1021 i2c20: i2c@890000 {
1043 compatible = 1022 compatible = "qcom,geni-i2c";
1044 reg = <0 0x00 1023 reg = <0 0x00890000 0 0x4000>;
1045 #address-cell 1024 #address-cells = <1>;
1046 #size-cells = 1025 #size-cells = <0>;
1047 clocks = <&gc 1026 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1048 clock-names = 1027 clock-names = "se";
1049 interrupts = 1028 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1050 power-domains 1029 power-domains = <&rpmhpd SC8280XP_CX>;
1051 interconnects 1030 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1052 1031 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1053 1032 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1054 interconnect- 1033 interconnect-names = "qup-core", "qup-config", "qup-memory";
1055 status = "dis 1034 status = "disabled";
1056 }; 1035 };
1057 1036
1058 spi20: spi@890000 { 1037 spi20: spi@890000 {
1059 compatible = 1038 compatible = "qcom,geni-spi";
1060 reg = <0 0x00 1039 reg = <0 0x00890000 0 0x4000>;
1061 #address-cell 1040 #address-cells = <1>;
1062 #size-cells = 1041 #size-cells = <0>;
1063 clocks = <&gc 1042 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1064 clock-names = 1043 clock-names = "se";
1065 interrupts = 1044 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1066 power-domains 1045 power-domains = <&rpmhpd SC8280XP_CX>;
1067 interconnects 1046 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1068 1047 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1069 1048 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1070 interconnect- 1049 interconnect-names = "qup-core", "qup-config", "qup-memory";
1071 status = "dis 1050 status = "disabled";
1072 }; 1051 };
1073 1052
1074 i2c21: i2c@894000 { 1053 i2c21: i2c@894000 {
1075 compatible = 1054 compatible = "qcom,geni-i2c";
1076 reg = <0 0x00 1055 reg = <0 0x00894000 0 0x4000>;
1077 clock-names = 1056 clock-names = "se";
1078 clocks = <&gc 1057 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1079 interrupts = 1058 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1080 #address-cell 1059 #address-cells = <1>;
1081 #size-cells = 1060 #size-cells = <0>;
1082 power-domains 1061 power-domains = <&rpmhpd SC8280XP_CX>;
1083 interconnects 1062 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1084 1063 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1085 1064 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1086 interconnect- 1065 interconnect-names = "qup-core", "qup-config", "qup-memory";
1087 status = "dis 1066 status = "disabled";
1088 }; 1067 };
1089 1068
1090 spi21: spi@894000 { 1069 spi21: spi@894000 {
1091 compatible = 1070 compatible = "qcom,geni-spi";
1092 reg = <0 0x00 1071 reg = <0 0x00894000 0 0x4000>;
1093 #address-cell 1072 #address-cells = <1>;
1094 #size-cells = 1073 #size-cells = <0>;
1095 clocks = <&gc 1074 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1096 clock-names = 1075 clock-names = "se";
1097 interrupts = 1076 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1098 power-domains 1077 power-domains = <&rpmhpd SC8280XP_CX>;
1099 interconnects 1078 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1100 1079 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1101 1080 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1102 interconnect- 1081 interconnect-names = "qup-core", "qup-config", "qup-memory";
1103 status = "dis 1082 status = "disabled";
1104 }; 1083 };
1105 1084
1106 i2c22: i2c@898000 { 1085 i2c22: i2c@898000 {
1107 compatible = 1086 compatible = "qcom,geni-i2c";
1108 reg = <0 0x00 1087 reg = <0 0x00898000 0 0x4000>;
1109 #address-cell 1088 #address-cells = <1>;
1110 #size-cells = 1089 #size-cells = <0>;
1111 clock-names = 1090 clock-names = "se";
1112 clocks = <&gc 1091 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1113 interrupts = 1092 interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>;
1114 power-domains 1093 power-domains = <&rpmhpd SC8280XP_CX>;
1115 interconnects 1094 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1116 1095 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1117 1096 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1118 interconnect- 1097 interconnect-names = "qup-core", "qup-config", "qup-memory";
1119 status = "dis 1098 status = "disabled";
1120 }; 1099 };
1121 1100
1122 spi22: spi@898000 { 1101 spi22: spi@898000 {
1123 compatible = 1102 compatible = "qcom,geni-spi";
1124 reg = <0 0x00 1103 reg = <0 0x00898000 0 0x4000>;
1125 #address-cell 1104 #address-cells = <1>;
1126 #size-cells = 1105 #size-cells = <0>;
1127 clocks = <&gc 1106 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1128 clock-names = 1107 clock-names = "se";
1129 interrupts = 1108 interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>;
1130 power-domains 1109 power-domains = <&rpmhpd SC8280XP_CX>;
1131 interconnects 1110 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1132 1111 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1133 1112 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1134 interconnect- 1113 interconnect-names = "qup-core", "qup-config", "qup-memory";
1135 status = "dis 1114 status = "disabled";
1136 }; 1115 };
1137 1116
1138 i2c23: i2c@89c000 { 1117 i2c23: i2c@89c000 {
1139 compatible = 1118 compatible = "qcom,geni-i2c";
1140 reg = <0 0x00 1119 reg = <0 0x0089c000 0 0x4000>;
1141 #address-cell 1120 #address-cells = <1>;
1142 #size-cells = 1121 #size-cells = <0>;
1143 clock-names = 1122 clock-names = "se";
1144 clocks = <&gc 1123 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
1145 interrupts = 1124 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>;
1146 power-domains 1125 power-domains = <&rpmhpd SC8280XP_CX>;
1147 interconnects 1126 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1148 1127 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1149 1128 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1150 interconnect- 1129 interconnect-names = "qup-core", "qup-config", "qup-memory";
1151 status = "dis 1130 status = "disabled";
1152 }; 1131 };
1153 1132
1154 spi23: spi@89c000 { 1133 spi23: spi@89c000 {
1155 compatible = 1134 compatible = "qcom,geni-spi";
1156 reg = <0 0x00 1135 reg = <0 0x0089c000 0 0x4000>;
1157 #address-cell 1136 #address-cells = <1>;
1158 #size-cells = 1137 #size-cells = <0>;
1159 clocks = <&gc 1138 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
1160 clock-names = 1139 clock-names = "se";
1161 interrupts = 1140 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>;
1162 power-domains 1141 power-domains = <&rpmhpd SC8280XP_CX>;
1163 interconnects 1142 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1164 1143 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1165 1144 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1166 interconnect- 1145 interconnect-names = "qup-core", "qup-config", "qup-memory";
1167 status = "dis 1146 status = "disabled";
1168 }; 1147 };
1169 }; 1148 };
1170 1149
1171 qup0: geniqup@9c0000 { 1150 qup0: geniqup@9c0000 {
1172 compatible = "qcom,ge 1151 compatible = "qcom,geni-se-qup";
1173 reg = <0 0x009c0000 0 1152 reg = <0 0x009c0000 0 0x6000>;
1174 clocks = <&gcc GCC_QU 1153 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1175 <&gcc GCC_QU 1154 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1176 clock-names = "m-ahb" 1155 clock-names = "m-ahb", "s-ahb";
1177 iommus = <&apps_smmu 1156 iommus = <&apps_smmu 0x563 0>;
1178 1157
1179 #address-cells = <2>; 1158 #address-cells = <2>;
1180 #size-cells = <2>; 1159 #size-cells = <2>;
1181 ranges; 1160 ranges;
1182 1161
1183 status = "disabled"; 1162 status = "disabled";
1184 1163
1185 i2c0: i2c@980000 { 1164 i2c0: i2c@980000 {
1186 compatible = 1165 compatible = "qcom,geni-i2c";
1187 reg = <0 0x00 1166 reg = <0 0x00980000 0 0x4000>;
1188 #address-cell 1167 #address-cells = <1>;
1189 #size-cells = 1168 #size-cells = <0>;
1190 clock-names = 1169 clock-names = "se";
1191 clocks = <&gc 1170 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1192 interrupts = 1171 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1193 power-domains 1172 power-domains = <&rpmhpd SC8280XP_CX>;
1194 interconnects 1173 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1195 1174 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1196 1175 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1197 interconnect- 1176 interconnect-names = "qup-core", "qup-config", "qup-memory";
1198 status = "dis 1177 status = "disabled";
1199 }; 1178 };
1200 1179
1201 spi0: spi@980000 { 1180 spi0: spi@980000 {
1202 compatible = 1181 compatible = "qcom,geni-spi";
1203 reg = <0 0x00 1182 reg = <0 0x00980000 0 0x4000>;
1204 #address-cell 1183 #address-cells = <1>;
1205 #size-cells = 1184 #size-cells = <0>;
1206 clocks = <&gc 1185 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1207 clock-names = 1186 clock-names = "se";
1208 interrupts = 1187 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1209 power-domains 1188 power-domains = <&rpmhpd SC8280XP_CX>;
1210 interconnects 1189 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1211 1190 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1212 1191 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1213 interconnect- 1192 interconnect-names = "qup-core", "qup-config", "qup-memory";
1214 status = "dis 1193 status = "disabled";
1215 }; 1194 };
1216 1195
1217 i2c1: i2c@984000 { 1196 i2c1: i2c@984000 {
1218 compatible = 1197 compatible = "qcom,geni-i2c";
1219 reg = <0 0x00 1198 reg = <0 0x00984000 0 0x4000>;
1220 #address-cell 1199 #address-cells = <1>;
1221 #size-cells = 1200 #size-cells = <0>;
1222 clock-names = 1201 clock-names = "se";
1223 clocks = <&gc 1202 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1224 interrupts = 1203 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1225 power-domains 1204 power-domains = <&rpmhpd SC8280XP_CX>;
1226 interconnects 1205 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1227 1206 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1228 1207 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1229 interconnect- 1208 interconnect-names = "qup-core", "qup-config", "qup-memory";
1230 status = "dis 1209 status = "disabled";
1231 }; 1210 };
1232 1211
1233 spi1: spi@984000 { 1212 spi1: spi@984000 {
1234 compatible = 1213 compatible = "qcom,geni-spi";
1235 reg = <0 0x00 1214 reg = <0 0x00984000 0 0x4000>;
1236 #address-cell 1215 #address-cells = <1>;
1237 #size-cells = 1216 #size-cells = <0>;
1238 clocks = <&gc 1217 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1239 clock-names = 1218 clock-names = "se";
1240 interrupts = 1219 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1241 power-domains 1220 power-domains = <&rpmhpd SC8280XP_CX>;
1242 interconnects 1221 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1243 1222 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1244 1223 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1245 interconnect- 1224 interconnect-names = "qup-core", "qup-config", "qup-memory";
1246 status = "dis 1225 status = "disabled";
1247 }; 1226 };
1248 1227
1249 i2c2: i2c@988000 { 1228 i2c2: i2c@988000 {
1250 compatible = 1229 compatible = "qcom,geni-i2c";
1251 reg = <0 0x00 1230 reg = <0 0x00988000 0 0x4000>;
1252 #address-cell 1231 #address-cells = <1>;
1253 #size-cells = 1232 #size-cells = <0>;
1254 clock-names = 1233 clock-names = "se";
1255 clocks = <&gc 1234 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1256 interrupts = 1235 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1257 power-domains 1236 power-domains = <&rpmhpd SC8280XP_CX>;
1258 interconnects 1237 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1259 1238 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1260 1239 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1261 interconnect- 1240 interconnect-names = "qup-core", "qup-config", "qup-memory";
1262 status = "dis 1241 status = "disabled";
1263 }; 1242 };
1264 1243
1265 spi2: spi@988000 { 1244 spi2: spi@988000 {
1266 compatible = 1245 compatible = "qcom,geni-spi";
1267 reg = <0 0x00 1246 reg = <0 0x00988000 0 0x4000>;
1268 #address-cell 1247 #address-cells = <1>;
1269 #size-cells = 1248 #size-cells = <0>;
1270 clocks = <&gc 1249 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1271 clock-names = 1250 clock-names = "se";
1272 interrupts = 1251 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1273 power-domains 1252 power-domains = <&rpmhpd SC8280XP_CX>;
1274 interconnects 1253 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1275 1254 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1276 1255 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1277 interconnect- 1256 interconnect-names = "qup-core", "qup-config", "qup-memory";
1278 status = "dis 1257 status = "disabled";
1279 }; 1258 };
1280 1259
1281 uart2: serial@988000 1260 uart2: serial@988000 {
1282 compatible = 1261 compatible = "qcom,geni-uart";
1283 reg = <0 0x00 1262 reg = <0 0x00988000 0 0x4000>;
1284 clocks = <&gc 1263 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1285 clock-names = 1264 clock-names = "se";
1286 interrupts = 1265 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1287 operating-poi 1266 operating-points-v2 = <&qup_opp_table_100mhz>;
1288 power-domains 1267 power-domains = <&rpmhpd SC8280XP_CX>;
1289 interconnects 1268 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1290 1269 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1291 interconnect- 1270 interconnect-names = "qup-core", "qup-config";
1292 status = "dis 1271 status = "disabled";
1293 }; 1272 };
1294 1273
1295 i2c3: i2c@98c000 { 1274 i2c3: i2c@98c000 {
1296 compatible = 1275 compatible = "qcom,geni-i2c";
1297 reg = <0 0x00 1276 reg = <0 0x0098c000 0 0x4000>;
1298 #address-cell 1277 #address-cells = <1>;
1299 #size-cells = 1278 #size-cells = <0>;
1300 clock-names = 1279 clock-names = "se";
1301 clocks = <&gc 1280 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1302 interrupts = 1281 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1303 power-domains 1282 power-domains = <&rpmhpd SC8280XP_CX>;
1304 interconnects 1283 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1305 1284 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1306 1285 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1307 interconnect- 1286 interconnect-names = "qup-core", "qup-config", "qup-memory";
1308 status = "dis 1287 status = "disabled";
1309 }; 1288 };
1310 1289
1311 spi3: spi@98c000 { 1290 spi3: spi@98c000 {
1312 compatible = 1291 compatible = "qcom,geni-spi";
1313 reg = <0 0x00 1292 reg = <0 0x0098c000 0 0x4000>;
1314 #address-cell 1293 #address-cells = <1>;
1315 #size-cells = 1294 #size-cells = <0>;
1316 clocks = <&gc 1295 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1317 clock-names = 1296 clock-names = "se";
1318 interrupts = 1297 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1319 power-domains 1298 power-domains = <&rpmhpd SC8280XP_CX>;
1320 interconnects 1299 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1321 1300 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1322 1301 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1323 interconnect- 1302 interconnect-names = "qup-core", "qup-config", "qup-memory";
1324 status = "dis 1303 status = "disabled";
1325 }; 1304 };
1326 1305
1327 i2c4: i2c@990000 { 1306 i2c4: i2c@990000 {
1328 compatible = 1307 compatible = "qcom,geni-i2c";
1329 reg = <0 0x00 1308 reg = <0 0x00990000 0 0x4000>;
1330 clock-names = 1309 clock-names = "se";
1331 clocks = <&gc 1310 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1332 interrupts = 1311 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1333 #address-cell 1312 #address-cells = <1>;
1334 #size-cells = 1313 #size-cells = <0>;
1335 power-domains 1314 power-domains = <&rpmhpd SC8280XP_CX>;
1336 interconnects 1315 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1337 1316 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1338 1317 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1339 interconnect- 1318 interconnect-names = "qup-core", "qup-config", "qup-memory";
1340 status = "dis 1319 status = "disabled";
1341 }; 1320 };
1342 1321
1343 spi4: spi@990000 { 1322 spi4: spi@990000 {
1344 compatible = 1323 compatible = "qcom,geni-spi";
1345 reg = <0 0x00 1324 reg = <0 0x00990000 0 0x4000>;
1346 #address-cell 1325 #address-cells = <1>;
1347 #size-cells = 1326 #size-cells = <0>;
1348 clocks = <&gc 1327 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1349 clock-names = 1328 clock-names = "se";
1350 interrupts = 1329 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1351 power-domains 1330 power-domains = <&rpmhpd SC8280XP_CX>;
1352 interconnects 1331 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1353 1332 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1354 1333 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1355 interconnect- 1334 interconnect-names = "qup-core", "qup-config", "qup-memory";
1356 status = "dis 1335 status = "disabled";
1357 }; 1336 };
1358 1337
1359 i2c5: i2c@994000 { 1338 i2c5: i2c@994000 {
1360 compatible = 1339 compatible = "qcom,geni-i2c";
1361 reg = <0 0x00 1340 reg = <0 0x00994000 0 0x4000>;
1362 #address-cell 1341 #address-cells = <1>;
1363 #size-cells = 1342 #size-cells = <0>;
1364 clock-names = 1343 clock-names = "se";
1365 clocks = <&gc 1344 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1366 interrupts = 1345 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1367 power-domains 1346 power-domains = <&rpmhpd SC8280XP_CX>;
1368 interconnects 1347 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1369 1348 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1370 1349 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1371 interconnect- 1350 interconnect-names = "qup-core", "qup-config", "qup-memory";
1372 status = "dis 1351 status = "disabled";
1373 }; 1352 };
1374 1353
1375 spi5: spi@994000 { 1354 spi5: spi@994000 {
1376 compatible = 1355 compatible = "qcom,geni-spi";
1377 reg = <0 0x00 1356 reg = <0 0x00994000 0 0x4000>;
1378 #address-cell 1357 #address-cells = <1>;
1379 #size-cells = 1358 #size-cells = <0>;
1380 clocks = <&gc 1359 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1381 clock-names = 1360 clock-names = "se";
1382 interrupts = 1361 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1383 power-domains 1362 power-domains = <&rpmhpd SC8280XP_CX>;
1384 interconnects 1363 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1385 1364 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1386 1365 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1387 interconnect- 1366 interconnect-names = "qup-core", "qup-config", "qup-memory";
1388 status = "dis 1367 status = "disabled";
1389 }; 1368 };
1390 1369
1391 i2c6: i2c@998000 { 1370 i2c6: i2c@998000 {
1392 compatible = 1371 compatible = "qcom,geni-i2c";
1393 reg = <0 0x00 1372 reg = <0 0x00998000 0 0x4000>;
1394 #address-cell 1373 #address-cells = <1>;
1395 #size-cells = 1374 #size-cells = <0>;
1396 clock-names = 1375 clock-names = "se";
1397 clocks = <&gc 1376 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1398 interrupts = 1377 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1399 power-domains 1378 power-domains = <&rpmhpd SC8280XP_CX>;
1400 interconnects 1379 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1401 1380 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1402 1381 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1403 interconnect- 1382 interconnect-names = "qup-core", "qup-config", "qup-memory";
1404 status = "dis 1383 status = "disabled";
1405 }; 1384 };
1406 1385
1407 spi6: spi@998000 { 1386 spi6: spi@998000 {
1408 compatible = 1387 compatible = "qcom,geni-spi";
1409 reg = <0 0x00 1388 reg = <0 0x00998000 0 0x4000>;
1410 #address-cell 1389 #address-cells = <1>;
1411 #size-cells = 1390 #size-cells = <0>;
1412 clocks = <&gc 1391 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1413 clock-names = 1392 clock-names = "se";
1414 interrupts = 1393 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1415 power-domains 1394 power-domains = <&rpmhpd SC8280XP_CX>;
1416 interconnects 1395 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1417 1396 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1418 1397 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1419 interconnect- 1398 interconnect-names = "qup-core", "qup-config", "qup-memory";
1420 status = "dis 1399 status = "disabled";
1421 }; 1400 };
1422 1401
1423 i2c7: i2c@99c000 { 1402 i2c7: i2c@99c000 {
1424 compatible = 1403 compatible = "qcom,geni-i2c";
1425 reg = <0 0x00 1404 reg = <0 0x0099c000 0 0x4000>;
1426 #address-cell 1405 #address-cells = <1>;
1427 #size-cells = 1406 #size-cells = <0>;
1428 clock-names = 1407 clock-names = "se";
1429 clocks = <&gc 1408 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1430 interrupts = 1409 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1431 power-domains 1410 power-domains = <&rpmhpd SC8280XP_CX>;
1432 interconnects 1411 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1433 1412 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1434 1413 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1435 interconnect- 1414 interconnect-names = "qup-core", "qup-config", "qup-memory";
1436 status = "dis 1415 status = "disabled";
1437 }; 1416 };
1438 1417
1439 spi7: spi@99c000 { 1418 spi7: spi@99c000 {
1440 compatible = 1419 compatible = "qcom,geni-spi";
1441 reg = <0 0x00 1420 reg = <0 0x0099c000 0 0x4000>;
1442 #address-cell 1421 #address-cells = <1>;
1443 #size-cells = 1422 #size-cells = <0>;
1444 clocks = <&gc 1423 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
1445 clock-names = 1424 clock-names = "se";
1446 interrupts = 1425 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1447 power-domains 1426 power-domains = <&rpmhpd SC8280XP_CX>;
1448 interconnects 1427 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1449 1428 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1450 1429 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1451 interconnect- 1430 interconnect-names = "qup-core", "qup-config", "qup-memory";
1452 status = "dis 1431 status = "disabled";
1453 }; 1432 };
1454 }; 1433 };
1455 1434
1456 qup1: geniqup@ac0000 { 1435 qup1: geniqup@ac0000 {
1457 compatible = "qcom,ge 1436 compatible = "qcom,geni-se-qup";
1458 reg = <0 0x00ac0000 0 1437 reg = <0 0x00ac0000 0 0x6000>;
1459 clocks = <&gcc GCC_QU 1438 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1460 <&gcc GCC_QU 1439 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1461 clock-names = "m-ahb" 1440 clock-names = "m-ahb", "s-ahb";
1462 iommus = <&apps_smmu 1441 iommus = <&apps_smmu 0x83 0>;
1463 1442
1464 #address-cells = <2>; 1443 #address-cells = <2>;
1465 #size-cells = <2>; 1444 #size-cells = <2>;
1466 ranges; 1445 ranges;
1467 1446
1468 status = "disabled"; 1447 status = "disabled";
1469 1448
1470 i2c8: i2c@a80000 { 1449 i2c8: i2c@a80000 {
1471 compatible = 1450 compatible = "qcom,geni-i2c";
1472 reg = <0 0x00 1451 reg = <0 0x00a80000 0 0x4000>;
1473 #address-cell 1452 #address-cells = <1>;
1474 #size-cells = 1453 #size-cells = <0>;
1475 clocks = <&gc 1454 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1476 clock-names = 1455 clock-names = "se";
1477 interrupts = 1456 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1478 power-domains 1457 power-domains = <&rpmhpd SC8280XP_CX>;
1479 interconnects 1458 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1480 1459 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1481 1460 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1482 interconnect- 1461 interconnect-names = "qup-core", "qup-config", "qup-memory";
1483 status = "dis 1462 status = "disabled";
1484 }; 1463 };
1485 1464
1486 spi8: spi@a80000 { 1465 spi8: spi@a80000 {
1487 compatible = 1466 compatible = "qcom,geni-spi";
1488 reg = <0 0x00 1467 reg = <0 0x00a80000 0 0x4000>;
1489 #address-cell 1468 #address-cells = <1>;
1490 #size-cells = 1469 #size-cells = <0>;
1491 clocks = <&gc 1470 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1492 clock-names = 1471 clock-names = "se";
1493 interrupts = 1472 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1494 power-domains 1473 power-domains = <&rpmhpd SC8280XP_CX>;
1495 interconnects 1474 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1496 1475 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1497 1476 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1498 interconnect- 1477 interconnect-names = "qup-core", "qup-config", "qup-memory";
1499 status = "dis 1478 status = "disabled";
1500 }; 1479 };
1501 1480
1502 i2c9: i2c@a84000 { 1481 i2c9: i2c@a84000 {
1503 compatible = 1482 compatible = "qcom,geni-i2c";
1504 reg = <0 0x00 1483 reg = <0 0x00a84000 0 0x4000>;
1505 #address-cell 1484 #address-cells = <1>;
1506 #size-cells = 1485 #size-cells = <0>;
1507 clocks = <&gc 1486 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1508 clock-names = 1487 clock-names = "se";
1509 interrupts = 1488 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1510 power-domains 1489 power-domains = <&rpmhpd SC8280XP_CX>;
1511 interconnects 1490 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1512 1491 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1513 1492 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1514 interconnect- 1493 interconnect-names = "qup-core", "qup-config", "qup-memory";
1515 status = "dis 1494 status = "disabled";
1516 }; 1495 };
1517 1496
1518 spi9: spi@a84000 { 1497 spi9: spi@a84000 {
1519 compatible = 1498 compatible = "qcom,geni-spi";
1520 reg = <0 0x00 1499 reg = <0 0x00a84000 0 0x4000>;
1521 #address-cell 1500 #address-cells = <1>;
1522 #size-cells = 1501 #size-cells = <0>;
1523 clocks = <&gc 1502 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1524 clock-names = 1503 clock-names = "se";
1525 interrupts = 1504 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1526 power-domains 1505 power-domains = <&rpmhpd SC8280XP_CX>;
1527 interconnects 1506 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1528 1507 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1529 1508 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1530 interconnect- 1509 interconnect-names = "qup-core", "qup-config", "qup-memory";
1531 status = "dis 1510 status = "disabled";
1532 }; 1511 };
1533 1512
1534 i2c10: i2c@a88000 { 1513 i2c10: i2c@a88000 {
1535 compatible = 1514 compatible = "qcom,geni-i2c";
1536 reg = <0 0x00 1515 reg = <0 0x00a88000 0 0x4000>;
1537 #address-cell 1516 #address-cells = <1>;
1538 #size-cells = 1517 #size-cells = <0>;
1539 clocks = <&gc 1518 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1540 clock-names = 1519 clock-names = "se";
1541 interrupts = 1520 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1542 power-domains 1521 power-domains = <&rpmhpd SC8280XP_CX>;
1543 interconnects 1522 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1544 1523 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1545 1524 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1546 interconnect- 1525 interconnect-names = "qup-core", "qup-config", "qup-memory";
1547 status = "dis 1526 status = "disabled";
1548 }; 1527 };
1549 1528
1550 spi10: spi@a88000 { 1529 spi10: spi@a88000 {
1551 compatible = 1530 compatible = "qcom,geni-spi";
1552 reg = <0 0x00 1531 reg = <0 0x00a88000 0 0x4000>;
1553 #address-cell 1532 #address-cells = <1>;
1554 #size-cells = 1533 #size-cells = <0>;
1555 clocks = <&gc 1534 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1556 clock-names = 1535 clock-names = "se";
1557 interrupts = 1536 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1558 power-domains 1537 power-domains = <&rpmhpd SC8280XP_CX>;
1559 interconnects 1538 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1560 1539 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1561 1540 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1562 interconnect- 1541 interconnect-names = "qup-core", "qup-config", "qup-memory";
1563 status = "dis 1542 status = "disabled";
1564 }; 1543 };
1565 1544
1566 i2c11: i2c@a8c000 { 1545 i2c11: i2c@a8c000 {
1567 compatible = 1546 compatible = "qcom,geni-i2c";
1568 reg = <0 0x00 1547 reg = <0 0x00a8c000 0 0x4000>;
1569 #address-cell 1548 #address-cells = <1>;
1570 #size-cells = 1549 #size-cells = <0>;
1571 clocks = <&gc 1550 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1572 clock-names = 1551 clock-names = "se";
1573 interrupts = 1552 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1574 power-domains 1553 power-domains = <&rpmhpd SC8280XP_CX>;
1575 interconnects 1554 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1576 1555 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1577 1556 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1578 interconnect- 1557 interconnect-names = "qup-core", "qup-config", "qup-memory";
1579 status = "dis 1558 status = "disabled";
1580 }; 1559 };
1581 1560
1582 spi11: spi@a8c000 { 1561 spi11: spi@a8c000 {
1583 compatible = 1562 compatible = "qcom,geni-spi";
1584 reg = <0 0x00 1563 reg = <0 0x00a8c000 0 0x4000>;
1585 #address-cell 1564 #address-cells = <1>;
1586 #size-cells = 1565 #size-cells = <0>;
1587 clocks = <&gc 1566 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1588 clock-names = 1567 clock-names = "se";
1589 interrupts = 1568 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1590 power-domains 1569 power-domains = <&rpmhpd SC8280XP_CX>;
1591 interconnects 1570 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1592 1571 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1593 1572 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1594 interconnect- 1573 interconnect-names = "qup-core", "qup-config", "qup-memory";
1595 status = "dis 1574 status = "disabled";
1596 }; 1575 };
1597 1576
1598 i2c12: i2c@a90000 { 1577 i2c12: i2c@a90000 {
1599 compatible = 1578 compatible = "qcom,geni-i2c";
1600 reg = <0 0x00 1579 reg = <0 0x00a90000 0 0x4000>;
1601 #address-cell 1580 #address-cells = <1>;
1602 #size-cells = 1581 #size-cells = <0>;
1603 clocks = <&gc 1582 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1604 clock-names = 1583 clock-names = "se";
1605 interrupts = 1584 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1606 power-domains 1585 power-domains = <&rpmhpd SC8280XP_CX>;
1607 interconnects 1586 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1608 1587 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1609 1588 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1610 interconnect- 1589 interconnect-names = "qup-core", "qup-config", "qup-memory";
1611 status = "dis 1590 status = "disabled";
1612 }; 1591 };
1613 1592
1614 spi12: spi@a90000 { 1593 spi12: spi@a90000 {
1615 compatible = 1594 compatible = "qcom,geni-spi";
1616 reg = <0 0x00 1595 reg = <0 0x00a90000 0 0x4000>;
1617 #address-cell 1596 #address-cells = <1>;
1618 #size-cells = 1597 #size-cells = <0>;
1619 clocks = <&gc 1598 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1620 clock-names = 1599 clock-names = "se";
1621 interrupts = 1600 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1622 power-domains 1601 power-domains = <&rpmhpd SC8280XP_CX>;
1623 interconnects 1602 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1624 1603 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1625 1604 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1626 interconnect- 1605 interconnect-names = "qup-core", "qup-config", "qup-memory";
1627 status = "dis 1606 status = "disabled";
1628 }; 1607 };
1629 1608
1630 i2c13: i2c@a94000 { 1609 i2c13: i2c@a94000 {
1631 compatible = 1610 compatible = "qcom,geni-i2c";
1632 reg = <0 0x00 1611 reg = <0 0x00a94000 0 0x4000>;
1633 #address-cell 1612 #address-cells = <1>;
1634 #size-cells = 1613 #size-cells = <0>;
1635 clocks = <&gc 1614 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1636 clock-names = 1615 clock-names = "se";
1637 interrupts = 1616 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1638 power-domains 1617 power-domains = <&rpmhpd SC8280XP_CX>;
1639 interconnects 1618 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1640 1619 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1641 1620 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1642 interconnect- 1621 interconnect-names = "qup-core", "qup-config", "qup-memory";
1643 status = "dis 1622 status = "disabled";
1644 }; 1623 };
1645 1624
1646 spi13: spi@a94000 { 1625 spi13: spi@a94000 {
1647 compatible = 1626 compatible = "qcom,geni-spi";
1648 reg = <0 0x00 1627 reg = <0 0x00a94000 0 0x4000>;
1649 #address-cell 1628 #address-cells = <1>;
1650 #size-cells = 1629 #size-cells = <0>;
1651 clocks = <&gc 1630 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1652 clock-names = 1631 clock-names = "se";
1653 interrupts = 1632 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1654 power-domains 1633 power-domains = <&rpmhpd SC8280XP_CX>;
1655 interconnects 1634 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1656 1635 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1657 1636 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1658 interconnect- 1637 interconnect-names = "qup-core", "qup-config", "qup-memory";
1659 status = "dis 1638 status = "disabled";
1660 }; 1639 };
1661 1640
1662 i2c14: i2c@a98000 { 1641 i2c14: i2c@a98000 {
1663 compatible = 1642 compatible = "qcom,geni-i2c";
1664 reg = <0 0x00 1643 reg = <0 0x00a98000 0 0x4000>;
1665 #address-cell 1644 #address-cells = <1>;
1666 #size-cells = 1645 #size-cells = <0>;
1667 clocks = <&gc 1646 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1668 clock-names = 1647 clock-names = "se";
1669 interrupts = 1648 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>;
1670 power-domains 1649 power-domains = <&rpmhpd SC8280XP_CX>;
1671 interconnects 1650 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1672 1651 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1673 1652 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1674 interconnect- 1653 interconnect-names = "qup-core", "qup-config", "qup-memory";
1675 status = "dis 1654 status = "disabled";
1676 }; 1655 };
1677 1656
1678 spi14: spi@a98000 { 1657 spi14: spi@a98000 {
1679 compatible = 1658 compatible = "qcom,geni-spi";
1680 reg = <0 0x00 1659 reg = <0 0x00a98000 0 0x4000>;
1681 #address-cell 1660 #address-cells = <1>;
1682 #size-cells = 1661 #size-cells = <0>;
1683 clocks = <&gc 1662 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1684 clock-names = 1663 clock-names = "se";
1685 interrupts = 1664 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>;
1686 power-domains 1665 power-domains = <&rpmhpd SC8280XP_CX>;
1687 interconnects 1666 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1688 1667 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1689 1668 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1690 interconnect- 1669 interconnect-names = "qup-core", "qup-config", "qup-memory";
1691 status = "dis 1670 status = "disabled";
1692 }; 1671 };
1693 1672
1694 i2c15: i2c@a9c000 { 1673 i2c15: i2c@a9c000 {
1695 compatible = 1674 compatible = "qcom,geni-i2c";
1696 reg = <0 0x00 1675 reg = <0 0x00a9c000 0 0x4000>;
1697 #address-cell 1676 #address-cells = <1>;
1698 #size-cells = 1677 #size-cells = <0>;
1699 clocks = <&gc 1678 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1700 clock-names = 1679 clock-names = "se";
1701 interrupts = 1680 interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
1702 power-domains 1681 power-domains = <&rpmhpd SC8280XP_CX>;
1703 interconnects 1682 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1704 1683 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1705 1684 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1706 interconnect- 1685 interconnect-names = "qup-core", "qup-config", "qup-memory";
1707 status = "dis 1686 status = "disabled";
1708 }; 1687 };
1709 1688
1710 spi15: spi@a9c000 { 1689 spi15: spi@a9c000 {
1711 compatible = 1690 compatible = "qcom,geni-spi";
1712 reg = <0 0x00 1691 reg = <0 0x00a9c000 0 0x4000>;
1713 #address-cell 1692 #address-cells = <1>;
1714 #size-cells = 1693 #size-cells = <0>;
1715 clocks = <&gc 1694 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1716 clock-names = 1695 clock-names = "se";
1717 interrupts = 1696 interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
1718 power-domains 1697 power-domains = <&rpmhpd SC8280XP_CX>;
1719 interconnects 1698 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1720 1699 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1721 1700 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1722 interconnect- 1701 interconnect-names = "qup-core", "qup-config", "qup-memory";
1723 status = "dis 1702 status = "disabled";
1724 }; 1703 };
1725 }; 1704 };
1726 1705
1727 rng: rng@10d3000 { 1706 rng: rng@10d3000 {
1728 compatible = "qcom,pr 1707 compatible = "qcom,prng-ee";
1729 reg = <0 0x010d3000 0 1708 reg = <0 0x010d3000 0 0x1000>;
1730 clocks = <&rpmhcc RPM 1709 clocks = <&rpmhcc RPMH_HWKM_CLK>;
1731 clock-names = "core"; 1710 clock-names = "core";
1732 }; 1711 };
1733 1712
1734 pcie4: pcie@1c00000 { 1713 pcie4: pcie@1c00000 {
1735 device_type = "pci"; 1714 device_type = "pci";
1736 compatible = "qcom,pc 1715 compatible = "qcom,pcie-sc8280xp";
1737 reg = <0x0 0x01c00000 1716 reg = <0x0 0x01c00000 0x0 0x3000>,
1738 <0x0 0x30000000 1717 <0x0 0x30000000 0x0 0xf1d>,
1739 <0x0 0x30000f20 1718 <0x0 0x30000f20 0x0 0xa8>,
1740 <0x0 0x30001000 1719 <0x0 0x30001000 0x0 0x1000>,
1741 <0x0 0x30100000 1720 <0x0 0x30100000 0x0 0x100000>,
1742 <0x0 0x01c03000 1721 <0x0 0x01c03000 0x0 0x1000>;
1743 reg-names = "parf", " 1722 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
1744 #address-cells = <3>; 1723 #address-cells = <3>;
1745 #size-cells = <2>; 1724 #size-cells = <2>;
1746 ranges = <0x01000000 1725 ranges = <0x01000000 0x0 0x00000000 0x0 0x30200000 0x0 0x100000>,
1747 <0x02000000 1726 <0x02000000 0x0 0x30300000 0x0 0x30300000 0x0 0x1d00000>;
1748 bus-range = <0x00 0xf 1727 bus-range = <0x00 0xff>;
1749 1728
1750 dma-coherent; 1729 dma-coherent;
1751 1730
1752 linux,pci-domain = <6 1731 linux,pci-domain = <6>;
1753 num-lanes = <1>; 1732 num-lanes = <1>;
1754 1733
1755 msi-map = <0x0 &its 0 <<
1756 <<
1757 interrupts = <GIC_SPI 1734 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
1758 <GIC_SPI 1735 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
1759 <GIC_SPI 1736 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
1760 <GIC_SPI 1737 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
1761 interrupt-names = "ms 1738 interrupt-names = "msi0", "msi1", "msi2", "msi3";
1762 1739
1763 #interrupt-cells = <1 1740 #interrupt-cells = <1>;
1764 interrupt-map-mask = 1741 interrupt-map-mask = <0 0 0 0x7>;
1765 interrupt-map = <0 0 1742 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
1766 <0 0 1743 <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
1767 <0 0 1744 <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
1768 <0 0 1745 <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
1769 1746
1770 clocks = <&gcc GCC_PC 1747 clocks = <&gcc GCC_PCIE_4_AUX_CLK>,
1771 <&gcc GCC_PC 1748 <&gcc GCC_PCIE_4_CFG_AHB_CLK>,
1772 <&gcc GCC_PC 1749 <&gcc GCC_PCIE_4_MSTR_AXI_CLK>,
1773 <&gcc GCC_PC 1750 <&gcc GCC_PCIE_4_SLV_AXI_CLK>,
1774 <&gcc GCC_PC 1751 <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>,
1775 <&gcc GCC_DD 1752 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1776 <&gcc GCC_AG 1753 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
1777 <&gcc GCC_AG 1754 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>,
1778 <&gcc GCC_CN 1755 <&gcc GCC_CNOC_PCIE4_QX_CLK>;
1779 clock-names = "aux", 1756 clock-names = "aux",
1780 "cfg", 1757 "cfg",
1781 "bus_ma 1758 "bus_master",
1782 "bus_sl 1759 "bus_slave",
1783 "slave_ 1760 "slave_q2a",
1784 "ddrss_ 1761 "ddrss_sf_tbu",
1785 "noc_ag 1762 "noc_aggr_4",
1786 "noc_ag 1763 "noc_aggr_south_sf",
1787 "cnoc_q 1764 "cnoc_qx";
1788 1765
1789 assigned-clocks = <&g 1766 assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>;
1790 assigned-clock-rates 1767 assigned-clock-rates = <19200000>;
1791 1768
1792 interconnects = <&agg 1769 interconnects = <&aggre2_noc MASTER_PCIE_4 0 &mc_virt SLAVE_EBI1 0>,
1793 <&gem 1770 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_4 0>;
1794 interconnect-names = 1771 interconnect-names = "pcie-mem", "cpu-pcie";
1795 1772
1796 resets = <&gcc GCC_PC 1773 resets = <&gcc GCC_PCIE_4_BCR>;
1797 reset-names = "pci"; 1774 reset-names = "pci";
1798 1775
1799 power-domains = <&gcc 1776 power-domains = <&gcc PCIE_4_GDSC>;
1800 required-opps = <&rpm 1777 required-opps = <&rpmhpd_opp_nom>;
1801 1778
1802 phys = <&pcie4_phy>; 1779 phys = <&pcie4_phy>;
1803 phy-names = "pciephy" 1780 phy-names = "pciephy";
1804 1781
1805 status = "disabled"; 1782 status = "disabled";
1806 <<
1807 pcie4_port0: pcie@0 { <<
1808 device_type = <<
1809 reg = <0x0 0x <<
1810 bus-range = < <<
1811 <<
1812 #address-cell <<
1813 #size-cells = <<
1814 ranges; <<
1815 }; <<
1816 }; 1783 };
1817 1784
1818 pcie4_phy: phy@1c06000 { 1785 pcie4_phy: phy@1c06000 {
1819 compatible = "qcom,sc 1786 compatible = "qcom,sc8280xp-qmp-gen3x1-pcie-phy";
1820 reg = <0x0 0x01c06000 1787 reg = <0x0 0x01c06000 0x0 0x2000>;
1821 1788
1822 clocks = <&gcc GCC_PC 1789 clocks = <&gcc GCC_PCIE_4_AUX_CLK>,
1823 <&gcc GCC_PC 1790 <&gcc GCC_PCIE_4_CFG_AHB_CLK>,
1824 <&gcc GCC_PC 1791 <&gcc GCC_PCIE_4_CLKREF_CLK>,
1825 <&gcc GCC_PC 1792 <&gcc GCC_PCIE4_PHY_RCHNG_CLK>,
1826 <&gcc GCC_PC 1793 <&gcc GCC_PCIE_4_PIPE_CLK>,
1827 <&gcc GCC_PC 1794 <&gcc GCC_PCIE_4_PIPEDIV2_CLK>;
1828 clock-names = "aux", 1795 clock-names = "aux", "cfg_ahb", "ref", "rchng",
1829 "pipe", 1796 "pipe", "pipediv2";
1830 1797
1831 assigned-clocks = <&g 1798 assigned-clocks = <&gcc GCC_PCIE4_PHY_RCHNG_CLK>;
1832 assigned-clock-rates 1799 assigned-clock-rates = <100000000>;
1833 1800
1834 power-domains = <&gcc 1801 power-domains = <&gcc PCIE_4_GDSC>;
1835 1802
1836 resets = <&gcc GCC_PC 1803 resets = <&gcc GCC_PCIE_4_PHY_BCR>;
1837 reset-names = "phy"; 1804 reset-names = "phy";
1838 1805
1839 #clock-cells = <0>; 1806 #clock-cells = <0>;
1840 clock-output-names = 1807 clock-output-names = "pcie_4_pipe_clk";
1841 1808
1842 #phy-cells = <0>; 1809 #phy-cells = <0>;
1843 1810
1844 status = "disabled"; 1811 status = "disabled";
1845 }; 1812 };
1846 1813
1847 pcie3b: pcie@1c08000 { 1814 pcie3b: pcie@1c08000 {
1848 device_type = "pci"; 1815 device_type = "pci";
1849 compatible = "qcom,pc 1816 compatible = "qcom,pcie-sc8280xp";
1850 reg = <0x0 0x01c08000 1817 reg = <0x0 0x01c08000 0x0 0x3000>,
1851 <0x0 0x32000000 1818 <0x0 0x32000000 0x0 0xf1d>,
1852 <0x0 0x32000f20 1819 <0x0 0x32000f20 0x0 0xa8>,
1853 <0x0 0x32001000 1820 <0x0 0x32001000 0x0 0x1000>,
1854 <0x0 0x32100000 1821 <0x0 0x32100000 0x0 0x100000>,
1855 <0x0 0x01c0b000 1822 <0x0 0x01c0b000 0x0 0x1000>;
1856 reg-names = "parf", " 1823 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
1857 #address-cells = <3>; 1824 #address-cells = <3>;
1858 #size-cells = <2>; 1825 #size-cells = <2>;
1859 ranges = <0x01000000 1826 ranges = <0x01000000 0x0 0x00000000 0x0 0x32200000 0x0 0x100000>,
1860 <0x02000000 1827 <0x02000000 0x0 0x32300000 0x0 0x32300000 0x0 0x1d00000>;
1861 bus-range = <0x00 0xf 1828 bus-range = <0x00 0xff>;
1862 1829
1863 dma-coherent; 1830 dma-coherent;
1864 1831
1865 linux,pci-domain = <5 1832 linux,pci-domain = <5>;
1866 num-lanes = <2>; 1833 num-lanes = <2>;
1867 1834
1868 msi-map = <0x0 &its 0 <<
1869 <<
1870 interrupts = <GIC_SPI 1835 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1871 <GIC_SPI 1836 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1872 <GIC_SPI 1837 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
1873 <GIC_SPI 1838 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
1874 interrupt-names = "ms 1839 interrupt-names = "msi0", "msi1", "msi2", "msi3";
1875 1840
1876 #interrupt-cells = <1 1841 #interrupt-cells = <1>;
1877 interrupt-map-mask = 1842 interrupt-map-mask = <0 0 0 0x7>;
1878 interrupt-map = <0 0 1843 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>,
1879 <0 0 1844 <0 0 0 2 &intc 0 0 GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>,
1880 <0 0 1845 <0 0 0 3 &intc 0 0 GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>,
1881 <0 0 1846 <0 0 0 4 &intc 0 0 GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>;
1882 1847
1883 clocks = <&gcc GCC_PC 1848 clocks = <&gcc GCC_PCIE_3B_AUX_CLK>,
1884 <&gcc GCC_PC 1849 <&gcc GCC_PCIE_3B_CFG_AHB_CLK>,
1885 <&gcc GCC_PC 1850 <&gcc GCC_PCIE_3B_MSTR_AXI_CLK>,
1886 <&gcc GCC_PC 1851 <&gcc GCC_PCIE_3B_SLV_AXI_CLK>,
1887 <&gcc GCC_PC 1852 <&gcc GCC_PCIE_3B_SLV_Q2A_AXI_CLK>,
1888 <&gcc GCC_DD 1853 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1889 <&gcc GCC_AG 1854 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
1890 <&gcc GCC_AG 1855 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
1891 clock-names = "aux", 1856 clock-names = "aux",
1892 "cfg", 1857 "cfg",
1893 "bus_ma 1858 "bus_master",
1894 "bus_sl 1859 "bus_slave",
1895 "slave_ 1860 "slave_q2a",
1896 "ddrss_ 1861 "ddrss_sf_tbu",
1897 "noc_ag 1862 "noc_aggr_4",
1898 "noc_ag 1863 "noc_aggr_south_sf";
1899 1864
1900 assigned-clocks = <&g 1865 assigned-clocks = <&gcc GCC_PCIE_3B_AUX_CLK>;
1901 assigned-clock-rates 1866 assigned-clock-rates = <19200000>;
1902 1867
1903 interconnects = <&agg 1868 interconnects = <&aggre2_noc MASTER_PCIE_3B 0 &mc_virt SLAVE_EBI1 0>,
1904 <&gem 1869 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3B 0>;
1905 interconnect-names = 1870 interconnect-names = "pcie-mem", "cpu-pcie";
1906 1871
1907 resets = <&gcc GCC_PC 1872 resets = <&gcc GCC_PCIE_3B_BCR>;
1908 reset-names = "pci"; 1873 reset-names = "pci";
1909 1874
1910 power-domains = <&gcc 1875 power-domains = <&gcc PCIE_3B_GDSC>;
1911 required-opps = <&rpm 1876 required-opps = <&rpmhpd_opp_nom>;
1912 1877
1913 phys = <&pcie3b_phy>; 1878 phys = <&pcie3b_phy>;
1914 phy-names = "pciephy" 1879 phy-names = "pciephy";
1915 1880
1916 status = "disabled"; 1881 status = "disabled";
1917 <<
1918 pcie3b_port0: pcie@0 <<
1919 device_type = <<
1920 reg = <0x0 0x <<
1921 bus-range = < <<
1922 <<
1923 #address-cell <<
1924 #size-cells = <<
1925 ranges; <<
1926 }; <<
1927 }; 1882 };
1928 1883
1929 pcie3b_phy: phy@1c0e000 { 1884 pcie3b_phy: phy@1c0e000 {
1930 compatible = "qcom,sc 1885 compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy";
1931 reg = <0x0 0x01c0e000 1886 reg = <0x0 0x01c0e000 0x0 0x2000>;
1932 1887
1933 clocks = <&gcc GCC_PC 1888 clocks = <&gcc GCC_PCIE_3B_AUX_CLK>,
1934 <&gcc GCC_PC 1889 <&gcc GCC_PCIE_3B_CFG_AHB_CLK>,
1935 <&gcc GCC_PC 1890 <&gcc GCC_PCIE_3A3B_CLKREF_CLK>,
1936 <&gcc GCC_PC 1891 <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>,
1937 <&gcc GCC_PC 1892 <&gcc GCC_PCIE_3B_PIPE_CLK>,
1938 <&gcc GCC_PC 1893 <&gcc GCC_PCIE_3B_PIPEDIV2_CLK>;
1939 clock-names = "aux", 1894 clock-names = "aux", "cfg_ahb", "ref", "rchng",
1940 "pipe", 1895 "pipe", "pipediv2";
1941 1896
1942 assigned-clocks = <&g 1897 assigned-clocks = <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>;
1943 assigned-clock-rates 1898 assigned-clock-rates = <100000000>;
1944 1899
1945 power-domains = <&gcc 1900 power-domains = <&gcc PCIE_3B_GDSC>;
1946 1901
1947 resets = <&gcc GCC_PC 1902 resets = <&gcc GCC_PCIE_3B_PHY_BCR>;
1948 reset-names = "phy"; 1903 reset-names = "phy";
1949 1904
1950 #clock-cells = <0>; 1905 #clock-cells = <0>;
1951 clock-output-names = 1906 clock-output-names = "pcie_3b_pipe_clk";
1952 1907
1953 #phy-cells = <0>; 1908 #phy-cells = <0>;
1954 1909
1955 status = "disabled"; 1910 status = "disabled";
1956 }; 1911 };
1957 1912
1958 pcie3a: pcie@1c10000 { 1913 pcie3a: pcie@1c10000 {
1959 device_type = "pci"; 1914 device_type = "pci";
1960 compatible = "qcom,pc 1915 compatible = "qcom,pcie-sc8280xp";
1961 reg = <0x0 0x01c10000 1916 reg = <0x0 0x01c10000 0x0 0x3000>,
1962 <0x0 0x34000000 1917 <0x0 0x34000000 0x0 0xf1d>,
1963 <0x0 0x34000f20 1918 <0x0 0x34000f20 0x0 0xa8>,
1964 <0x0 0x34001000 1919 <0x0 0x34001000 0x0 0x1000>,
1965 <0x0 0x34100000 1920 <0x0 0x34100000 0x0 0x100000>,
1966 <0x0 0x01c13000 1921 <0x0 0x01c13000 0x0 0x1000>;
1967 reg-names = "parf", " 1922 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
1968 #address-cells = <3>; 1923 #address-cells = <3>;
1969 #size-cells = <2>; 1924 #size-cells = <2>;
1970 ranges = <0x01000000 1925 ranges = <0x01000000 0x0 0x00000000 0x0 0x34200000 0x0 0x100000>,
1971 <0x02000000 1926 <0x02000000 0x0 0x34300000 0x0 0x34300000 0x0 0x1d00000>;
1972 bus-range = <0x00 0xf 1927 bus-range = <0x00 0xff>;
1973 1928
1974 dma-coherent; 1929 dma-coherent;
1975 1930
1976 linux,pci-domain = <4 1931 linux,pci-domain = <4>;
1977 num-lanes = <4>; 1932 num-lanes = <4>;
1978 1933
1979 msi-map = <0x0 &its 0 <<
1980 <<
1981 interrupts = <GIC_SPI 1934 interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
1982 <GIC_SPI 1935 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
1983 <GIC_SPI 1936 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
1984 <GIC_SPI 1937 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1985 interrupt-names = "ms 1938 interrupt-names = "msi0", "msi1", "msi2", "msi3";
1986 1939
1987 #interrupt-cells = <1 1940 #interrupt-cells = <1>;
1988 interrupt-map-mask = 1941 interrupt-map-mask = <0 0 0 0x7>;
1989 interrupt-map = <0 0 1942 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>,
1990 <0 0 1943 <0 0 0 2 &intc 0 0 GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>,
1991 <0 0 1944 <0 0 0 3 &intc 0 0 GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>,
1992 <0 0 1945 <0 0 0 4 &intc 0 0 GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>;
1993 1946
1994 clocks = <&gcc GCC_PC 1947 clocks = <&gcc GCC_PCIE_3A_AUX_CLK>,
1995 <&gcc GCC_PC 1948 <&gcc GCC_PCIE_3A_CFG_AHB_CLK>,
1996 <&gcc GCC_PC 1949 <&gcc GCC_PCIE_3A_MSTR_AXI_CLK>,
1997 <&gcc GCC_PC 1950 <&gcc GCC_PCIE_3A_SLV_AXI_CLK>,
1998 <&gcc GCC_PC 1951 <&gcc GCC_PCIE_3A_SLV_Q2A_AXI_CLK>,
1999 <&gcc GCC_DD 1952 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
2000 <&gcc GCC_AG 1953 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
2001 <&gcc GCC_AG 1954 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
2002 clock-names = "aux", 1955 clock-names = "aux",
2003 "cfg", 1956 "cfg",
2004 "bus_ma 1957 "bus_master",
2005 "bus_sl 1958 "bus_slave",
2006 "slave_ 1959 "slave_q2a",
2007 "ddrss_ 1960 "ddrss_sf_tbu",
2008 "noc_ag 1961 "noc_aggr_4",
2009 "noc_ag 1962 "noc_aggr_south_sf";
2010 1963
2011 assigned-clocks = <&g 1964 assigned-clocks = <&gcc GCC_PCIE_3A_AUX_CLK>;
2012 assigned-clock-rates 1965 assigned-clock-rates = <19200000>;
2013 1966
2014 interconnects = <&agg 1967 interconnects = <&aggre2_noc MASTER_PCIE_3A 0 &mc_virt SLAVE_EBI1 0>,
2015 <&gem 1968 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3A 0>;
2016 interconnect-names = 1969 interconnect-names = "pcie-mem", "cpu-pcie";
2017 1970
2018 resets = <&gcc GCC_PC 1971 resets = <&gcc GCC_PCIE_3A_BCR>;
2019 reset-names = "pci"; 1972 reset-names = "pci";
2020 1973
2021 power-domains = <&gcc 1974 power-domains = <&gcc PCIE_3A_GDSC>;
2022 required-opps = <&rpm 1975 required-opps = <&rpmhpd_opp_nom>;
2023 1976
2024 phys = <&pcie3a_phy>; 1977 phys = <&pcie3a_phy>;
2025 phy-names = "pciephy" 1978 phy-names = "pciephy";
2026 1979
2027 status = "disabled"; 1980 status = "disabled";
2028 <<
2029 pcie3a_port0: pcie@0 <<
2030 device_type = <<
2031 reg = <0x0 0x <<
2032 bus-range = < <<
2033 <<
2034 #address-cell <<
2035 #size-cells = <<
2036 ranges; <<
2037 }; <<
2038 }; 1981 };
2039 1982
2040 pcie3a_phy: phy@1c14000 { 1983 pcie3a_phy: phy@1c14000 {
2041 compatible = "qcom,sc 1984 compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy";
2042 reg = <0x0 0x01c14000 1985 reg = <0x0 0x01c14000 0x0 0x2000>,
2043 <0x0 0x01c16000 1986 <0x0 0x01c16000 0x0 0x2000>;
2044 1987
2045 clocks = <&gcc GCC_PC 1988 clocks = <&gcc GCC_PCIE_3A_AUX_CLK>,
2046 <&gcc GCC_PC 1989 <&gcc GCC_PCIE_3A_CFG_AHB_CLK>,
2047 <&gcc GCC_PC 1990 <&gcc GCC_PCIE_3A3B_CLKREF_CLK>,
2048 <&gcc GCC_PC 1991 <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>,
2049 <&gcc GCC_PC 1992 <&gcc GCC_PCIE_3A_PIPE_CLK>,
2050 <&gcc GCC_PC 1993 <&gcc GCC_PCIE_3A_PIPEDIV2_CLK>;
2051 clock-names = "aux", 1994 clock-names = "aux", "cfg_ahb", "ref", "rchng",
2052 "pipe", 1995 "pipe", "pipediv2";
2053 1996
2054 assigned-clocks = <&g 1997 assigned-clocks = <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>;
2055 assigned-clock-rates 1998 assigned-clock-rates = <100000000>;
2056 1999
2057 power-domains = <&gcc 2000 power-domains = <&gcc PCIE_3A_GDSC>;
2058 2001
2059 resets = <&gcc GCC_PC 2002 resets = <&gcc GCC_PCIE_3A_PHY_BCR>;
2060 reset-names = "phy"; 2003 reset-names = "phy";
2061 2004
2062 qcom,4ln-config-sel = 2005 qcom,4ln-config-sel = <&tcsr 0xa044 1>;
2063 2006
2064 #clock-cells = <0>; 2007 #clock-cells = <0>;
2065 clock-output-names = 2008 clock-output-names = "pcie_3a_pipe_clk";
2066 2009
2067 #phy-cells = <0>; 2010 #phy-cells = <0>;
2068 2011
2069 status = "disabled"; 2012 status = "disabled";
2070 }; 2013 };
2071 2014
2072 pcie2b: pcie@1c18000 { 2015 pcie2b: pcie@1c18000 {
2073 device_type = "pci"; 2016 device_type = "pci";
2074 compatible = "qcom,pc 2017 compatible = "qcom,pcie-sc8280xp";
2075 reg = <0x0 0x01c18000 2018 reg = <0x0 0x01c18000 0x0 0x3000>,
2076 <0x0 0x38000000 2019 <0x0 0x38000000 0x0 0xf1d>,
2077 <0x0 0x38000f20 2020 <0x0 0x38000f20 0x0 0xa8>,
2078 <0x0 0x38001000 2021 <0x0 0x38001000 0x0 0x1000>,
2079 <0x0 0x38100000 2022 <0x0 0x38100000 0x0 0x100000>,
2080 <0x0 0x01c1b000 2023 <0x0 0x01c1b000 0x0 0x1000>;
2081 reg-names = "parf", " 2024 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2082 #address-cells = <3>; 2025 #address-cells = <3>;
2083 #size-cells = <2>; 2026 #size-cells = <2>;
2084 ranges = <0x01000000 2027 ranges = <0x01000000 0x0 0x00000000 0x0 0x38200000 0x0 0x100000>,
2085 <0x02000000 2028 <0x02000000 0x0 0x38300000 0x0 0x38300000 0x0 0x1d00000>;
2086 bus-range = <0x00 0xf 2029 bus-range = <0x00 0xff>;
2087 2030
2088 dma-coherent; 2031 dma-coherent;
2089 2032
2090 linux,pci-domain = <3 2033 linux,pci-domain = <3>;
2091 num-lanes = <2>; 2034 num-lanes = <2>;
2092 2035
2093 msi-map = <0x0 &its 0 <<
2094 <<
2095 interrupts = <GIC_SPI 2036 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
2096 <GIC_SPI 2037 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
2097 <GIC_SPI 2038 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
2098 <GIC_SPI 2039 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
2099 interrupt-names = "ms 2040 interrupt-names = "msi0", "msi1", "msi2", "msi3";
2100 2041
2101 #interrupt-cells = <1 2042 #interrupt-cells = <1>;
2102 interrupt-map-mask = 2043 interrupt-map-mask = <0 0 0 0x7>;
2103 interrupt-map = <0 0 2044 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
2104 <0 0 2045 <0 0 0 2 &intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
2105 <0 0 2046 <0 0 0 3 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
2106 <0 0 2047 <0 0 0 4 &intc 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>;
2107 2048
2108 clocks = <&gcc GCC_PC 2049 clocks = <&gcc GCC_PCIE_2B_AUX_CLK>,
2109 <&gcc GCC_PC 2050 <&gcc GCC_PCIE_2B_CFG_AHB_CLK>,
2110 <&gcc GCC_PC 2051 <&gcc GCC_PCIE_2B_MSTR_AXI_CLK>,
2111 <&gcc GCC_PC 2052 <&gcc GCC_PCIE_2B_SLV_AXI_CLK>,
2112 <&gcc GCC_PC 2053 <&gcc GCC_PCIE_2B_SLV_Q2A_AXI_CLK>,
2113 <&gcc GCC_DD 2054 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
2114 <&gcc GCC_AG 2055 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
2115 <&gcc GCC_AG 2056 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
2116 clock-names = "aux", 2057 clock-names = "aux",
2117 "cfg", 2058 "cfg",
2118 "bus_ma 2059 "bus_master",
2119 "bus_sl 2060 "bus_slave",
2120 "slave_ 2061 "slave_q2a",
2121 "ddrss_ 2062 "ddrss_sf_tbu",
2122 "noc_ag 2063 "noc_aggr_4",
2123 "noc_ag 2064 "noc_aggr_south_sf";
2124 2065
2125 assigned-clocks = <&g 2066 assigned-clocks = <&gcc GCC_PCIE_2B_AUX_CLK>;
2126 assigned-clock-rates 2067 assigned-clock-rates = <19200000>;
2127 2068
2128 interconnects = <&agg 2069 interconnects = <&aggre2_noc MASTER_PCIE_2B 0 &mc_virt SLAVE_EBI1 0>,
2129 <&gem 2070 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2B 0>;
2130 interconnect-names = 2071 interconnect-names = "pcie-mem", "cpu-pcie";
2131 2072
2132 resets = <&gcc GCC_PC 2073 resets = <&gcc GCC_PCIE_2B_BCR>;
2133 reset-names = "pci"; 2074 reset-names = "pci";
2134 2075
2135 power-domains = <&gcc 2076 power-domains = <&gcc PCIE_2B_GDSC>;
2136 required-opps = <&rpm 2077 required-opps = <&rpmhpd_opp_nom>;
2137 2078
2138 phys = <&pcie2b_phy>; 2079 phys = <&pcie2b_phy>;
2139 phy-names = "pciephy" 2080 phy-names = "pciephy";
2140 2081
2141 status = "disabled"; 2082 status = "disabled";
2142 <<
2143 pcie2b_port0: pcie@0 <<
2144 device_type = <<
2145 reg = <0x0 0x <<
2146 bus-range = < <<
2147 <<
2148 #address-cell <<
2149 #size-cells = <<
2150 ranges; <<
2151 }; <<
2152 }; 2083 };
2153 2084
2154 pcie2b_phy: phy@1c1e000 { 2085 pcie2b_phy: phy@1c1e000 {
2155 compatible = "qcom,sc 2086 compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy";
2156 reg = <0x0 0x01c1e000 2087 reg = <0x0 0x01c1e000 0x0 0x2000>;
2157 2088
2158 clocks = <&gcc GCC_PC 2089 clocks = <&gcc GCC_PCIE_2B_AUX_CLK>,
2159 <&gcc GCC_PC 2090 <&gcc GCC_PCIE_2B_CFG_AHB_CLK>,
2160 <&gcc GCC_PC 2091 <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
2161 <&gcc GCC_PC 2092 <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>,
2162 <&gcc GCC_PC 2093 <&gcc GCC_PCIE_2B_PIPE_CLK>,
2163 <&gcc GCC_PC 2094 <&gcc GCC_PCIE_2B_PIPEDIV2_CLK>;
2164 clock-names = "aux", 2095 clock-names = "aux", "cfg_ahb", "ref", "rchng",
2165 "pipe", 2096 "pipe", "pipediv2";
2166 2097
2167 assigned-clocks = <&g 2098 assigned-clocks = <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>;
2168 assigned-clock-rates 2099 assigned-clock-rates = <100000000>;
2169 2100
2170 power-domains = <&gcc 2101 power-domains = <&gcc PCIE_2B_GDSC>;
2171 2102
2172 resets = <&gcc GCC_PC 2103 resets = <&gcc GCC_PCIE_2B_PHY_BCR>;
2173 reset-names = "phy"; 2104 reset-names = "phy";
2174 2105
2175 #clock-cells = <0>; 2106 #clock-cells = <0>;
2176 clock-output-names = 2107 clock-output-names = "pcie_2b_pipe_clk";
2177 2108
2178 #phy-cells = <0>; 2109 #phy-cells = <0>;
2179 2110
2180 status = "disabled"; 2111 status = "disabled";
2181 }; 2112 };
2182 2113
2183 pcie2a: pcie@1c20000 { 2114 pcie2a: pcie@1c20000 {
2184 device_type = "pci"; 2115 device_type = "pci";
2185 compatible = "qcom,pc 2116 compatible = "qcom,pcie-sc8280xp";
2186 reg = <0x0 0x01c20000 2117 reg = <0x0 0x01c20000 0x0 0x3000>,
2187 <0x0 0x3c000000 2118 <0x0 0x3c000000 0x0 0xf1d>,
2188 <0x0 0x3c000f20 2119 <0x0 0x3c000f20 0x0 0xa8>,
2189 <0x0 0x3c001000 2120 <0x0 0x3c001000 0x0 0x1000>,
2190 <0x0 0x3c100000 2121 <0x0 0x3c100000 0x0 0x100000>,
2191 <0x0 0x01c23000 2122 <0x0 0x01c23000 0x0 0x1000>;
2192 reg-names = "parf", " 2123 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2193 #address-cells = <3>; 2124 #address-cells = <3>;
2194 #size-cells = <2>; 2125 #size-cells = <2>;
2195 ranges = <0x01000000 2126 ranges = <0x01000000 0x0 0x00000000 0x0 0x3c200000 0x0 0x100000>,
2196 <0x02000000 2127 <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>;
2197 bus-range = <0x00 0xf 2128 bus-range = <0x00 0xff>;
2198 2129
2199 dma-coherent; 2130 dma-coherent;
2200 2131
2201 linux,pci-domain = <2 2132 linux,pci-domain = <2>;
2202 num-lanes = <4>; 2133 num-lanes = <4>;
2203 2134
2204 msi-map = <0x0 &its 0 <<
2205 <<
2206 interrupts = <GIC_SPI 2135 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
2207 <GIC_SPI 2136 <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>,
2208 <GIC_SPI 2137 <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>,
2209 <GIC_SPI 2138 <GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH>;
2210 interrupt-names = "ms 2139 interrupt-names = "msi0", "msi1", "msi2", "msi3";
2211 2140
2212 #interrupt-cells = <1 2141 #interrupt-cells = <1>;
2213 interrupt-map-mask = 2142 interrupt-map-mask = <0 0 0 0x7>;
2214 interrupt-map = <0 0 2143 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>,
2215 <0 0 2144 <0 0 0 2 &intc 0 0 GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>,
2216 <0 0 2145 <0 0 0 3 &intc 0 0 GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>,
2217 <0 0 2146 <0 0 0 4 &intc 0 0 GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>;
2218 2147
2219 clocks = <&gcc GCC_PC 2148 clocks = <&gcc GCC_PCIE_2A_AUX_CLK>,
2220 <&gcc GCC_PC 2149 <&gcc GCC_PCIE_2A_CFG_AHB_CLK>,
2221 <&gcc GCC_PC 2150 <&gcc GCC_PCIE_2A_MSTR_AXI_CLK>,
2222 <&gcc GCC_PC 2151 <&gcc GCC_PCIE_2A_SLV_AXI_CLK>,
2223 <&gcc GCC_PC 2152 <&gcc GCC_PCIE_2A_SLV_Q2A_AXI_CLK>,
2224 <&gcc GCC_DD 2153 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
2225 <&gcc GCC_AG 2154 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
2226 <&gcc GCC_AG 2155 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
2227 clock-names = "aux", 2156 clock-names = "aux",
2228 "cfg", 2157 "cfg",
2229 "bus_ma 2158 "bus_master",
2230 "bus_sl 2159 "bus_slave",
2231 "slave_ 2160 "slave_q2a",
2232 "ddrss_ 2161 "ddrss_sf_tbu",
2233 "noc_ag 2162 "noc_aggr_4",
2234 "noc_ag 2163 "noc_aggr_south_sf";
2235 2164
2236 assigned-clocks = <&g 2165 assigned-clocks = <&gcc GCC_PCIE_2A_AUX_CLK>;
2237 assigned-clock-rates 2166 assigned-clock-rates = <19200000>;
2238 2167
2239 interconnects = <&agg 2168 interconnects = <&aggre2_noc MASTER_PCIE_2A 0 &mc_virt SLAVE_EBI1 0>,
2240 <&gem 2169 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2A 0>;
2241 interconnect-names = 2170 interconnect-names = "pcie-mem", "cpu-pcie";
2242 2171
2243 resets = <&gcc GCC_PC 2172 resets = <&gcc GCC_PCIE_2A_BCR>;
2244 reset-names = "pci"; 2173 reset-names = "pci";
2245 2174
2246 power-domains = <&gcc 2175 power-domains = <&gcc PCIE_2A_GDSC>;
2247 required-opps = <&rpm 2176 required-opps = <&rpmhpd_opp_nom>;
2248 2177
2249 phys = <&pcie2a_phy>; 2178 phys = <&pcie2a_phy>;
2250 phy-names = "pciephy" 2179 phy-names = "pciephy";
2251 2180
2252 status = "disabled"; 2181 status = "disabled";
2253 <<
2254 pcie2a_port0: pcie@0 <<
2255 device_type = <<
2256 reg = <0x0 0x <<
2257 bus-range = < <<
2258 <<
2259 #address-cell <<
2260 #size-cells = <<
2261 ranges; <<
2262 }; <<
2263 }; 2182 };
2264 2183
2265 pcie2a_phy: phy@1c24000 { 2184 pcie2a_phy: phy@1c24000 {
2266 compatible = "qcom,sc 2185 compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy";
2267 reg = <0x0 0x01c24000 2186 reg = <0x0 0x01c24000 0x0 0x2000>,
2268 <0x0 0x01c26000 2187 <0x0 0x01c26000 0x0 0x2000>;
2269 2188
2270 clocks = <&gcc GCC_PC 2189 clocks = <&gcc GCC_PCIE_2A_AUX_CLK>,
2271 <&gcc GCC_PC 2190 <&gcc GCC_PCIE_2A_CFG_AHB_CLK>,
2272 <&gcc GCC_PC 2191 <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
2273 <&gcc GCC_PC 2192 <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>,
2274 <&gcc GCC_PC 2193 <&gcc GCC_PCIE_2A_PIPE_CLK>,
2275 <&gcc GCC_PC 2194 <&gcc GCC_PCIE_2A_PIPEDIV2_CLK>;
2276 clock-names = "aux", 2195 clock-names = "aux", "cfg_ahb", "ref", "rchng",
2277 "pipe", 2196 "pipe", "pipediv2";
2278 2197
2279 assigned-clocks = <&g 2198 assigned-clocks = <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>;
2280 assigned-clock-rates 2199 assigned-clock-rates = <100000000>;
2281 2200
2282 power-domains = <&gcc 2201 power-domains = <&gcc PCIE_2A_GDSC>;
2283 2202
2284 resets = <&gcc GCC_PC 2203 resets = <&gcc GCC_PCIE_2A_PHY_BCR>;
2285 reset-names = "phy"; 2204 reset-names = "phy";
2286 2205
2287 qcom,4ln-config-sel = 2206 qcom,4ln-config-sel = <&tcsr 0xa044 0>;
2288 2207
2289 #clock-cells = <0>; 2208 #clock-cells = <0>;
2290 clock-output-names = 2209 clock-output-names = "pcie_2a_pipe_clk";
2291 2210
2292 #phy-cells = <0>; 2211 #phy-cells = <0>;
2293 2212
2294 status = "disabled"; 2213 status = "disabled";
2295 }; 2214 };
2296 2215
2297 ufs_mem_hc: ufs@1d84000 { 2216 ufs_mem_hc: ufs@1d84000 {
2298 compatible = "qcom,sc 2217 compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc",
2299 "jedec,u 2218 "jedec,ufs-2.0";
2300 reg = <0 0x01d84000 0 2219 reg = <0 0x01d84000 0 0x3000>;
2301 interrupts = <GIC_SPI 2220 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2302 phys = <&ufs_mem_phy> 2221 phys = <&ufs_mem_phy>;
2303 phy-names = "ufsphy"; 2222 phy-names = "ufsphy";
2304 lanes-per-direction = 2223 lanes-per-direction = <2>;
2305 #reset-cells = <1>; 2224 #reset-cells = <1>;
2306 resets = <&gcc GCC_UF 2225 resets = <&gcc GCC_UFS_PHY_BCR>;
2307 reset-names = "rst"; 2226 reset-names = "rst";
2308 2227
2309 power-domains = <&gcc 2228 power-domains = <&gcc UFS_PHY_GDSC>;
2310 required-opps = <&rpm 2229 required-opps = <&rpmhpd_opp_nom>;
2311 2230
2312 iommus = <&apps_smmu 2231 iommus = <&apps_smmu 0xe0 0x0>;
2313 dma-coherent; 2232 dma-coherent;
2314 2233
2315 clocks = <&gcc GCC_UF 2234 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
2316 <&gcc GCC_AG 2235 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2317 <&gcc GCC_UF 2236 <&gcc GCC_UFS_PHY_AHB_CLK>,
2318 <&gcc GCC_UF 2237 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2319 <&gcc GCC_UF 2238 <&gcc GCC_UFS_REF_CLKREF_CLK>,
2320 <&gcc GCC_UF 2239 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2321 <&gcc GCC_UF 2240 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2322 <&gcc GCC_UF 2241 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
2323 clock-names = "core_c 2242 clock-names = "core_clk",
2324 "bus_ag 2243 "bus_aggr_clk",
2325 "iface_ 2244 "iface_clk",
2326 "core_c 2245 "core_clk_unipro",
2327 "ref_cl 2246 "ref_clk",
2328 "tx_lan 2247 "tx_lane0_sync_clk",
2329 "rx_lan 2248 "rx_lane0_sync_clk",
2330 "rx_lan 2249 "rx_lane1_sync_clk";
2331 freq-table-hz = <7500 2250 freq-table-hz = <75000000 300000000>,
2332 <0 0> 2251 <0 0>,
2333 <0 0> 2252 <0 0>,
2334 <7500 2253 <75000000 300000000>,
2335 <0 0> 2254 <0 0>,
2336 <0 0> 2255 <0 0>,
2337 <0 0> 2256 <0 0>,
2338 <0 0> 2257 <0 0>;
2339 status = "disabled"; 2258 status = "disabled";
2340 }; 2259 };
2341 2260
2342 ufs_mem_phy: phy@1d87000 { 2261 ufs_mem_phy: phy@1d87000 {
2343 compatible = "qcom,sc 2262 compatible = "qcom,sc8280xp-qmp-ufs-phy";
2344 reg = <0 0x01d87000 0 2263 reg = <0 0x01d87000 0 0x1000>;
2345 2264
2346 clocks = <&rpmhcc RPM !! 2265 clocks = <&gcc GCC_UFS_CARD_CLKREF_CLK>,
2347 <&gcc GCC_UF !! 2266 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
2348 <&gcc GCC_UF !! 2267 clock-names = "ref", "ref_aux";
2349 clock-names = "ref", <<
2350 "ref_au <<
2351 "qref"; <<
2352 2268
2353 power-domains = <&gcc 2269 power-domains = <&gcc UFS_PHY_GDSC>;
2354 2270
2355 resets = <&ufs_mem_hc 2271 resets = <&ufs_mem_hc 0>;
2356 reset-names = "ufsphy 2272 reset-names = "ufsphy";
2357 2273
2358 #phy-cells = <0>; 2274 #phy-cells = <0>;
2359 2275
2360 status = "disabled"; 2276 status = "disabled";
2361 }; 2277 };
2362 2278
2363 ufs_card_hc: ufs@1da4000 { 2279 ufs_card_hc: ufs@1da4000 {
2364 compatible = "qcom,sc 2280 compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc",
2365 "jedec,u 2281 "jedec,ufs-2.0";
2366 reg = <0 0x01da4000 0 2282 reg = <0 0x01da4000 0 0x3000>;
2367 interrupts = <GIC_SPI 2283 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
2368 phys = <&ufs_card_phy 2284 phys = <&ufs_card_phy>;
2369 phy-names = "ufsphy"; 2285 phy-names = "ufsphy";
2370 lanes-per-direction = 2286 lanes-per-direction = <2>;
2371 #reset-cells = <1>; 2287 #reset-cells = <1>;
2372 resets = <&gcc GCC_UF 2288 resets = <&gcc GCC_UFS_CARD_BCR>;
2373 reset-names = "rst"; 2289 reset-names = "rst";
2374 2290
2375 power-domains = <&gcc 2291 power-domains = <&gcc UFS_CARD_GDSC>;
2376 2292
2377 iommus = <&apps_smmu 2293 iommus = <&apps_smmu 0x4a0 0x0>;
2378 dma-coherent; 2294 dma-coherent;
2379 2295
2380 clocks = <&gcc GCC_UF 2296 clocks = <&gcc GCC_UFS_CARD_AXI_CLK>,
2381 <&gcc GCC_AG 2297 <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>,
2382 <&gcc GCC_UF 2298 <&gcc GCC_UFS_CARD_AHB_CLK>,
2383 <&gcc GCC_UF 2299 <&gcc GCC_UFS_CARD_UNIPRO_CORE_CLK>,
2384 <&gcc GCC_UF 2300 <&gcc GCC_UFS_REF_CLKREF_CLK>,
2385 <&gcc GCC_UF 2301 <&gcc GCC_UFS_CARD_TX_SYMBOL_0_CLK>,
2386 <&gcc GCC_UF 2302 <&gcc GCC_UFS_CARD_RX_SYMBOL_0_CLK>,
2387 <&gcc GCC_UF 2303 <&gcc GCC_UFS_CARD_RX_SYMBOL_1_CLK>;
2388 clock-names = "core_c 2304 clock-names = "core_clk",
2389 "bus_ag 2305 "bus_aggr_clk",
2390 "iface_ 2306 "iface_clk",
2391 "core_c 2307 "core_clk_unipro",
2392 "ref_cl 2308 "ref_clk",
2393 "tx_lan 2309 "tx_lane0_sync_clk",
2394 "rx_lan 2310 "rx_lane0_sync_clk",
2395 "rx_lan 2311 "rx_lane1_sync_clk";
2396 freq-table-hz = <7500 2312 freq-table-hz = <75000000 300000000>,
2397 <0 0> 2313 <0 0>,
2398 <0 0> 2314 <0 0>,
2399 <7500 2315 <75000000 300000000>,
2400 <0 0> 2316 <0 0>,
2401 <0 0> 2317 <0 0>,
2402 <0 0> 2318 <0 0>,
2403 <0 0> 2319 <0 0>;
2404 status = "disabled"; 2320 status = "disabled";
2405 }; 2321 };
2406 2322
2407 ufs_card_phy: phy@1da7000 { 2323 ufs_card_phy: phy@1da7000 {
2408 compatible = "qcom,sc 2324 compatible = "qcom,sc8280xp-qmp-ufs-phy";
2409 reg = <0 0x01da7000 0 2325 reg = <0 0x01da7000 0 0x1000>;
2410 2326
2411 clocks = <&rpmhcc RPM !! 2327 clocks = <&gcc GCC_UFS_1_CARD_CLKREF_CLK>,
2412 <&gcc GCC_UF !! 2328 <&gcc GCC_UFS_CARD_PHY_AUX_CLK>;
2413 <&gcc GCC_UF !! 2329 clock-names = "ref", "ref_aux";
2414 clock-names = "ref", <<
2415 "ref_au <<
2416 "qref"; <<
2417 2330
2418 power-domains = <&gcc 2331 power-domains = <&gcc UFS_CARD_GDSC>;
2419 2332
2420 resets = <&ufs_card_h 2333 resets = <&ufs_card_hc 0>;
2421 reset-names = "ufsphy 2334 reset-names = "ufsphy";
2422 2335
2423 #phy-cells = <0>; 2336 #phy-cells = <0>;
2424 2337
2425 status = "disabled"; 2338 status = "disabled";
2426 }; 2339 };
2427 2340
2428 tcsr_mutex: hwlock@1f40000 { 2341 tcsr_mutex: hwlock@1f40000 {
2429 compatible = "qcom,tc 2342 compatible = "qcom,tcsr-mutex";
2430 reg = <0x0 0x01f40000 2343 reg = <0x0 0x01f40000 0x0 0x20000>;
2431 #hwlock-cells = <1>; 2344 #hwlock-cells = <1>;
2432 }; 2345 };
2433 2346
2434 tcsr: syscon@1fc0000 { 2347 tcsr: syscon@1fc0000 {
2435 compatible = "qcom,sc 2348 compatible = "qcom,sc8280xp-tcsr", "syscon";
2436 reg = <0x0 0x01fc0000 2349 reg = <0x0 0x01fc0000 0x0 0x30000>;
2437 }; 2350 };
2438 2351
2439 gpu: gpu@3d00000 { 2352 gpu: gpu@3d00000 {
2440 compatible = "qcom,ad 2353 compatible = "qcom,adreno-690.0", "qcom,adreno";
2441 2354
2442 reg = <0 0x03d00000 0 2355 reg = <0 0x03d00000 0 0x40000>,
2443 <0 0x03d9e000 0 2356 <0 0x03d9e000 0 0x1000>,
2444 <0 0x03d61000 0 2357 <0 0x03d61000 0 0x800>;
2445 reg-names = "kgsl_3d0 2358 reg-names = "kgsl_3d0_reg_memory",
2446 "cx_mem", 2359 "cx_mem",
2447 "cx_dbgc" 2360 "cx_dbgc";
2448 interrupts = <GIC_SPI 2361 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2449 iommus = <&gpu_smmu 0 2362 iommus = <&gpu_smmu 0 0xc00>, <&gpu_smmu 1 0xc00>;
2450 operating-points-v2 = 2363 operating-points-v2 = <&gpu_opp_table>;
2451 2364
2452 qcom,gmu = <&gmu>; 2365 qcom,gmu = <&gmu>;
2453 interconnects = <&gem 2366 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
2454 interconnect-names = 2367 interconnect-names = "gfx-mem";
2455 #cooling-cells = <2>; 2368 #cooling-cells = <2>;
2456 2369
2457 status = "disabled"; 2370 status = "disabled";
2458 2371
2459 gpu_opp_table: opp-ta 2372 gpu_opp_table: opp-table {
2460 compatible = 2373 compatible = "operating-points-v2";
2461 2374
2462 opp-270000000 2375 opp-270000000 {
2463 opp-h 2376 opp-hz = /bits/ 64 <270000000>;
2464 opp-l 2377 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2465 opp-p 2378 opp-peak-kBps = <451000>;
2466 }; 2379 };
2467 2380
2468 opp-410000000 2381 opp-410000000 {
2469 opp-h 2382 opp-hz = /bits/ 64 <410000000>;
2470 opp-l 2383 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2471 opp-p 2384 opp-peak-kBps = <1555000>;
2472 }; 2385 };
2473 2386
2474 opp-500000000 2387 opp-500000000 {
2475 opp-h 2388 opp-hz = /bits/ 64 <500000000>;
2476 opp-l 2389 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2477 opp-p 2390 opp-peak-kBps = <1555000>;
2478 }; 2391 };
2479 2392
2480 opp-547000000 2393 opp-547000000 {
2481 opp-h 2394 opp-hz = /bits/ 64 <547000000>;
2482 opp-l 2395 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2483 opp-p 2396 opp-peak-kBps = <1555000>;
2484 }; 2397 };
2485 2398
2486 opp-606000000 2399 opp-606000000 {
2487 opp-h 2400 opp-hz = /bits/ 64 <606000000>;
2488 opp-l 2401 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2489 opp-p 2402 opp-peak-kBps = <2736000>;
2490 }; 2403 };
2491 2404
2492 opp-640000000 2405 opp-640000000 {
2493 opp-h 2406 opp-hz = /bits/ 64 <640000000>;
2494 opp-l 2407 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2495 opp-p 2408 opp-peak-kBps = <2736000>;
2496 }; 2409 };
2497 2410
2498 opp-655000000 2411 opp-655000000 {
2499 opp-h 2412 opp-hz = /bits/ 64 <655000000>;
2500 opp-l 2413 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2501 opp-p 2414 opp-peak-kBps = <2736000>;
2502 }; 2415 };
2503 2416
2504 opp-690000000 2417 opp-690000000 {
2505 opp-h 2418 opp-hz = /bits/ 64 <690000000>;
2506 opp-l 2419 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2507 opp-p 2420 opp-peak-kBps = <2736000>;
2508 }; 2421 };
2509 }; 2422 };
2510 }; 2423 };
2511 2424
2512 gmu: gmu@3d6a000 { 2425 gmu: gmu@3d6a000 {
2513 compatible = "qcom,ad 2426 compatible = "qcom,adreno-gmu-690.0", "qcom,adreno-gmu";
2514 reg = <0 0x03d6a000 0 2427 reg = <0 0x03d6a000 0 0x34000>,
2515 <0 0x03de0000 0 2428 <0 0x03de0000 0 0x10000>,
2516 <0 0x0b290000 0 2429 <0 0x0b290000 0 0x10000>;
2517 reg-names = "gmu", "r 2430 reg-names = "gmu", "rscc", "gmu_pdc";
2518 interrupts = <GIC_SPI 2431 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2519 <GIC_SPI 2432 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2520 interrupt-names = "hf 2433 interrupt-names = "hfi", "gmu";
2521 clocks = <&gpucc GPU_ 2434 clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
2522 <&gpucc GPU_ 2435 <&gpucc GPU_CC_CXO_CLK>,
2523 <&gcc GCC_DD 2436 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2524 <&gcc GCC_GP 2437 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2525 <&gpucc GPU_ 2438 <&gpucc GPU_CC_AHB_CLK>,
2526 <&gpucc GPU_ 2439 <&gpucc GPU_CC_HUB_CX_INT_CLK>,
2527 <&gpucc GPU_ 2440 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
2528 clock-names = "gmu", 2441 clock-names = "gmu",
2529 "cxo", 2442 "cxo",
2530 "axi", 2443 "axi",
2531 "memnoc 2444 "memnoc",
2532 "ahb", 2445 "ahb",
2533 "hub", 2446 "hub",
2534 "smmu_v 2447 "smmu_vote";
2535 power-domains = <&gpu 2448 power-domains = <&gpucc GPU_CC_CX_GDSC>,
2536 <&gpu 2449 <&gpucc GPU_CC_GX_GDSC>;
2537 power-domain-names = 2450 power-domain-names = "cx",
2538 2451 "gx";
2539 iommus = <&gpu_smmu 5 2452 iommus = <&gpu_smmu 5 0xc00>;
2540 operating-points-v2 = 2453 operating-points-v2 = <&gmu_opp_table>;
2541 2454
2542 gmu_opp_table: opp-ta 2455 gmu_opp_table: opp-table {
2543 compatible = 2456 compatible = "operating-points-v2";
2544 2457
2545 opp-200000000 2458 opp-200000000 {
2546 opp-h 2459 opp-hz = /bits/ 64 <200000000>;
2547 opp-l 2460 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2548 }; 2461 };
2549 2462
2550 opp-500000000 2463 opp-500000000 {
2551 opp-h 2464 opp-hz = /bits/ 64 <500000000>;
2552 opp-l 2465 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2553 }; 2466 };
2554 }; 2467 };
2555 }; 2468 };
2556 2469
2557 gpucc: clock-controller@3d900 2470 gpucc: clock-controller@3d90000 {
2558 compatible = "qcom,sc 2471 compatible = "qcom,sc8280xp-gpucc";
2559 reg = <0 0x03d90000 0 2472 reg = <0 0x03d90000 0 0x9000>;
2560 clocks = <&rpmhcc RPM 2473 clocks = <&rpmhcc RPMH_CXO_CLK>,
2561 <&gcc GCC_GP 2474 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2562 <&gcc GCC_GP 2475 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2563 clock-names = "bi_tcx 2476 clock-names = "bi_tcxo",
2564 "gcc_gp 2477 "gcc_gpu_gpll0_clk_src",
2565 "gcc_gp 2478 "gcc_gpu_gpll0_div_clk_src";
2566 2479
2567 power-domains = <&rpm 2480 power-domains = <&rpmhpd SC8280XP_GFX>;
2568 #clock-cells = <1>; 2481 #clock-cells = <1>;
2569 #reset-cells = <1>; 2482 #reset-cells = <1>;
2570 #power-domain-cells = 2483 #power-domain-cells = <1>;
2571 }; 2484 };
2572 2485
2573 gpu_smmu: iommu@3da0000 { 2486 gpu_smmu: iommu@3da0000 {
2574 compatible = "qcom,sc 2487 compatible = "qcom,sc8280xp-smmu-500", "qcom,adreno-smmu",
2575 "qcom,sm 2488 "qcom,smmu-500", "arm,mmu-500";
2576 reg = <0 0x03da0000 0 2489 reg = <0 0x03da0000 0 0x20000>;
2577 #iommu-cells = <2>; 2490 #iommu-cells = <2>;
2578 #global-interrupts = 2491 #global-interrupts = <2>;
2579 interrupts = <GIC_SPI 2492 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
2580 <GIC_SPI 2493 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
2581 <GIC_SPI 2494 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
2582 <GIC_SPI 2495 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
2583 <GIC_SPI 2496 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
2584 <GIC_SPI 2497 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
2585 <GIC_SPI 2498 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
2586 <GIC_SPI 2499 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
2587 <GIC_SPI 2500 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
2588 <GIC_SPI 2501 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
2589 <GIC_SPI 2502 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
2590 <GIC_SPI 2503 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
2591 <GIC_SPI 2504 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>,
2592 <GIC_SPI 2505 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>;
2593 2506
2594 clocks = <&gcc GCC_GP 2507 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2595 <&gcc GCC_GP 2508 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
2596 <&gpucc GPU_ 2509 <&gpucc GPU_CC_AHB_CLK>,
2597 <&gpucc GPU_ 2510 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
2598 <&gpucc GPU_ 2511 <&gpucc GPU_CC_CX_GMU_CLK>,
2599 <&gpucc GPU_ 2512 <&gpucc GPU_CC_HUB_CX_INT_CLK>,
2600 <&gpucc GPU_ 2513 <&gpucc GPU_CC_HUB_AON_CLK>;
2601 clock-names = "gcc_gp 2514 clock-names = "gcc_gpu_memnoc_gfx_clk",
2602 "gcc_gp 2515 "gcc_gpu_snoc_dvm_gfx_clk",
2603 "gpu_cc 2516 "gpu_cc_ahb_clk",
2604 "gpu_cc 2517 "gpu_cc_hlos1_vote_gpu_smmu_clk",
2605 "gpu_cc 2518 "gpu_cc_cx_gmu_clk",
2606 "gpu_cc 2519 "gpu_cc_hub_cx_int_clk",
2607 "gpu_cc 2520 "gpu_cc_hub_aon_clk";
2608 2521
2609 power-domains = <&gpu 2522 power-domains = <&gpucc GPU_CC_CX_GDSC>;
2610 dma-coherent; 2523 dma-coherent;
2611 }; 2524 };
2612 2525
2613 usb_0_hsphy: phy@88e5000 { 2526 usb_0_hsphy: phy@88e5000 {
2614 compatible = "qcom,sc 2527 compatible = "qcom,sc8280xp-usb-hs-phy",
2615 "qcom,us 2528 "qcom,usb-snps-hs-5nm-phy";
2616 reg = <0 0x088e5000 0 2529 reg = <0 0x088e5000 0 0x400>;
2617 clocks = <&rpmhcc RPM 2530 clocks = <&rpmhcc RPMH_CXO_CLK>;
2618 clock-names = "ref"; 2531 clock-names = "ref";
2619 resets = <&gcc GCC_QU 2532 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2620 2533
2621 #phy-cells = <0>; 2534 #phy-cells = <0>;
2622 2535
2623 status = "disabled"; 2536 status = "disabled";
2624 }; 2537 };
2625 2538
2626 usb_2_hsphy0: phy@88e7000 { 2539 usb_2_hsphy0: phy@88e7000 {
2627 compatible = "qcom,sc 2540 compatible = "qcom,sc8280xp-usb-hs-phy",
2628 "qcom,us 2541 "qcom,usb-snps-hs-5nm-phy";
2629 reg = <0 0x088e7000 0 2542 reg = <0 0x088e7000 0 0x400>;
2630 clocks = <&gcc GCC_US 2543 clocks = <&gcc GCC_USB2_HS0_CLKREF_CLK>;
2631 clock-names = "ref"; 2544 clock-names = "ref";
2632 resets = <&gcc GCC_QU 2545 resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>;
2633 2546
2634 #phy-cells = <0>; 2547 #phy-cells = <0>;
2635 2548
2636 status = "disabled"; 2549 status = "disabled";
2637 }; 2550 };
2638 2551
2639 usb_2_hsphy1: phy@88e8000 { 2552 usb_2_hsphy1: phy@88e8000 {
2640 compatible = "qcom,sc 2553 compatible = "qcom,sc8280xp-usb-hs-phy",
2641 "qcom,us 2554 "qcom,usb-snps-hs-5nm-phy";
2642 reg = <0 0x088e8000 0 2555 reg = <0 0x088e8000 0 0x400>;
2643 clocks = <&gcc GCC_US 2556 clocks = <&gcc GCC_USB2_HS1_CLKREF_CLK>;
2644 clock-names = "ref"; 2557 clock-names = "ref";
2645 resets = <&gcc GCC_QU 2558 resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>;
2646 2559
2647 #phy-cells = <0>; 2560 #phy-cells = <0>;
2648 2561
2649 status = "disabled"; 2562 status = "disabled";
2650 }; 2563 };
2651 2564
2652 usb_2_hsphy2: phy@88e9000 { 2565 usb_2_hsphy2: phy@88e9000 {
2653 compatible = "qcom,sc 2566 compatible = "qcom,sc8280xp-usb-hs-phy",
2654 "qcom,us 2567 "qcom,usb-snps-hs-5nm-phy";
2655 reg = <0 0x088e9000 0 2568 reg = <0 0x088e9000 0 0x400>;
2656 clocks = <&gcc GCC_US 2569 clocks = <&gcc GCC_USB2_HS2_CLKREF_CLK>;
2657 clock-names = "ref"; 2570 clock-names = "ref";
2658 resets = <&gcc GCC_QU 2571 resets = <&gcc GCC_QUSB2PHY_HS2_MP_BCR>;
2659 2572
2660 #phy-cells = <0>; 2573 #phy-cells = <0>;
2661 2574
2662 status = "disabled"; 2575 status = "disabled";
2663 }; 2576 };
2664 2577
2665 usb_2_hsphy3: phy@88ea000 { 2578 usb_2_hsphy3: phy@88ea000 {
2666 compatible = "qcom,sc 2579 compatible = "qcom,sc8280xp-usb-hs-phy",
2667 "qcom,us 2580 "qcom,usb-snps-hs-5nm-phy";
2668 reg = <0 0x088ea000 0 2581 reg = <0 0x088ea000 0 0x400>;
2669 clocks = <&gcc GCC_US 2582 clocks = <&gcc GCC_USB2_HS3_CLKREF_CLK>;
2670 clock-names = "ref"; 2583 clock-names = "ref";
2671 resets = <&gcc GCC_QU 2584 resets = <&gcc GCC_QUSB2PHY_HS3_MP_BCR>;
2672 2585
2673 #phy-cells = <0>; 2586 #phy-cells = <0>;
2674 2587
2675 status = "disabled"; 2588 status = "disabled";
2676 }; 2589 };
2677 2590
2678 usb_2_qmpphy0: phy@88ef000 { 2591 usb_2_qmpphy0: phy@88ef000 {
2679 compatible = "qcom,sc 2592 compatible = "qcom,sc8280xp-qmp-usb3-uni-phy";
2680 reg = <0 0x088ef000 0 2593 reg = <0 0x088ef000 0 0x2000>;
2681 2594
2682 clocks = <&gcc GCC_US 2595 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
2683 <&gcc GCC_US 2596 <&gcc GCC_USB3_MP0_CLKREF_CLK>,
2684 <&gcc GCC_US 2597 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
2685 <&gcc GCC_US 2598 <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>;
2686 clock-names = "aux", 2599 clock-names = "aux", "ref", "com_aux", "pipe";
2687 2600
2688 resets = <&gcc GCC_US 2601 resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>,
2689 <&gcc GCC_US 2602 <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>;
2690 reset-names = "phy", 2603 reset-names = "phy", "phy_phy";
2691 2604
2692 power-domains = <&gcc 2605 power-domains = <&gcc USB30_MP_GDSC>;
2693 2606
2694 #clock-cells = <0>; 2607 #clock-cells = <0>;
2695 clock-output-names = 2608 clock-output-names = "usb2_phy0_pipe_clk";
2696 2609
2697 #phy-cells = <0>; 2610 #phy-cells = <0>;
2698 2611
2699 status = "disabled"; 2612 status = "disabled";
2700 }; 2613 };
2701 2614
2702 usb_2_qmpphy1: phy@88f1000 { 2615 usb_2_qmpphy1: phy@88f1000 {
2703 compatible = "qcom,sc 2616 compatible = "qcom,sc8280xp-qmp-usb3-uni-phy";
2704 reg = <0 0x088f1000 0 2617 reg = <0 0x088f1000 0 0x2000>;
2705 2618
2706 clocks = <&gcc GCC_US 2619 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
2707 <&gcc GCC_US 2620 <&gcc GCC_USB3_MP1_CLKREF_CLK>,
2708 <&gcc GCC_US 2621 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
2709 <&gcc GCC_US 2622 <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>;
2710 clock-names = "aux", 2623 clock-names = "aux", "ref", "com_aux", "pipe";
2711 2624
2712 resets = <&gcc GCC_US 2625 resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>,
2713 <&gcc GCC_US 2626 <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>;
2714 reset-names = "phy", 2627 reset-names = "phy", "phy_phy";
2715 2628
2716 power-domains = <&gcc 2629 power-domains = <&gcc USB30_MP_GDSC>;
2717 2630
2718 #clock-cells = <0>; 2631 #clock-cells = <0>;
2719 clock-output-names = 2632 clock-output-names = "usb2_phy1_pipe_clk";
2720 2633
2721 #phy-cells = <0>; 2634 #phy-cells = <0>;
2722 2635
2723 status = "disabled"; 2636 status = "disabled";
2724 }; 2637 };
2725 2638
2726 remoteproc_adsp: remoteproc@3 2639 remoteproc_adsp: remoteproc@3000000 {
2727 compatible = "qcom,sc 2640 compatible = "qcom,sc8280xp-adsp-pas";
2728 reg = <0 0x03000000 0 2641 reg = <0 0x03000000 0 0x100>;
2729 2642
2730 interrupts-extended = 2643 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
2731 2644 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
2732 2645 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
2733 2646 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
2734 2647 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>,
2735 2648 <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>;
2736 interrupt-names = "wd 2649 interrupt-names = "wdog", "fatal", "ready",
2737 "ha 2650 "handover", "stop-ack", "shutdown-ack";
2738 2651
2739 clocks = <&rpmhcc RPM 2652 clocks = <&rpmhcc RPMH_CXO_CLK>;
2740 clock-names = "xo"; 2653 clock-names = "xo";
2741 2654
2742 power-domains = <&rpm 2655 power-domains = <&rpmhpd SC8280XP_LCX>,
2743 <&rpm 2656 <&rpmhpd SC8280XP_LMX>;
2744 power-domain-names = 2657 power-domain-names = "lcx", "lmx";
2745 2658
2746 memory-region = <&pil 2659 memory-region = <&pil_adsp_mem>;
2747 2660
2748 qcom,qmp = <&aoss_qmp 2661 qcom,qmp = <&aoss_qmp>;
2749 2662
2750 qcom,smem-states = <& 2663 qcom,smem-states = <&smp2p_adsp_out 0>;
2751 qcom,smem-state-names 2664 qcom,smem-state-names = "stop";
2752 2665
2753 status = "disabled"; 2666 status = "disabled";
2754 2667
2755 remoteproc_adsp_glink 2668 remoteproc_adsp_glink: glink-edge {
2756 interrupts-ex 2669 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
2757 2670 IPCC_MPROC_SIGNAL_GLINK_QMP
2758 2671 IRQ_TYPE_EDGE_RISING>;
2759 mboxes = <&ip 2672 mboxes = <&ipcc IPCC_CLIENT_LPASS
2760 2673 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2761 2674
2762 label = "lpas 2675 label = "lpass";
2763 qcom,remote-p 2676 qcom,remote-pid = <2>;
2764 2677
2765 gpr { 2678 gpr {
2766 compa 2679 compatible = "qcom,gpr";
2767 qcom, 2680 qcom,glink-channels = "adsp_apps";
2768 qcom, 2681 qcom,domain = <GPR_DOMAIN_ID_ADSP>;
2769 qcom, 2682 qcom,intents = <512 20>;
2770 #addr 2683 #address-cells = <1>;
2771 #size 2684 #size-cells = <0>;
2772 2685
2773 q6apm 2686 q6apm: service@1 {
2774 2687 compatible = "qcom,q6apm";
2775 2688 reg = <GPR_APM_MODULE_IID>;
2776 2689 #sound-dai-cells = <0>;
2777 2690 qcom,protection-domain = "avs/audio",
2778 2691 "msm/adsp/audio_pd";
2779 2692 q6apmdai: dais {
2780 2693 compatible = "qcom,q6apm-dais";
2781 2694 iommus = <&apps_smmu 0x0c01 0x0>;
2782 2695 };
2783 2696
2784 2697 q6apmbedai: bedais {
2785 2698 compatible = "qcom,q6apm-lpass-dais";
2786 2699 #sound-dai-cells = <1>;
2787 2700 };
2788 }; 2701 };
2789 2702
2790 q6prm 2703 q6prm: service@2 {
2791 2704 compatible = "qcom,q6prm";
2792 2705 reg = <GPR_PRM_MODULE_IID>;
2793 2706 qcom,protection-domain = "avs/audio",
2794 2707 "msm/adsp/audio_pd";
2795 2708 q6prmcc: clock-controller {
2796 2709 compatible = "qcom,q6prm-lpass-clocks";
2797 2710 #clock-cells = <2>;
2798 2711 };
2799 }; 2712 };
2800 }; 2713 };
2801 }; 2714 };
2802 }; 2715 };
2803 2716
2804 rxmacro: rxmacro@3200000 { 2717 rxmacro: rxmacro@3200000 {
2805 compatible = "qcom,sc 2718 compatible = "qcom,sc8280xp-lpass-rx-macro";
2806 reg = <0 0x03200000 0 2719 reg = <0 0x03200000 0 0x1000>;
2807 clocks = <&q6prmcc LP 2720 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2808 <&q6prmcc LP 2721 <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2809 <&q6prmcc LP 2722 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2810 <&q6prmcc LP 2723 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2811 <&vamacro>; 2724 <&vamacro>;
2812 clock-names = "mclk", 2725 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2813 assigned-clocks = <&q 2726 assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2814 <&q 2727 <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2815 assigned-clock-rates 2728 assigned-clock-rates = <19200000>, <19200000>;
2816 2729
2817 clock-output-names = 2730 clock-output-names = "mclk";
2818 #clock-cells = <0>; 2731 #clock-cells = <0>;
2819 #sound-dai-cells = <1 2732 #sound-dai-cells = <1>;
2820 2733
2821 pinctrl-names = "defa 2734 pinctrl-names = "default";
2822 pinctrl-0 = <&rx_swr_ 2735 pinctrl-0 = <&rx_swr_default>;
2823 2736
2824 status = "disabled"; 2737 status = "disabled";
2825 }; 2738 };
2826 2739
2827 swr1: soundwire@3210000 { 2740 swr1: soundwire@3210000 {
2828 compatible = "qcom,so 2741 compatible = "qcom,soundwire-v1.6.0";
2829 reg = <0 0x03210000 0 2742 reg = <0 0x03210000 0 0x2000>;
2830 interrupts = <GIC_SPI 2743 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
2831 clocks = <&rxmacro>; 2744 clocks = <&rxmacro>;
2832 clock-names = "iface" 2745 clock-names = "iface";
2833 resets = <&lpass_audi 2746 resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>;
2834 reset-names = "swr_au 2747 reset-names = "swr_audio_cgcr";
2835 label = "RX"; 2748 label = "RX";
2836 2749
2837 qcom,din-ports = <0>; 2750 qcom,din-ports = <0>;
2838 qcom,dout-ports = <5> 2751 qcom,dout-ports = <5>;
2839 2752
2840 qcom,ports-sinterval- 2753 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
2841 qcom,ports-offset1 = 2754 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>;
2842 qcom,ports-offset2 = 2755 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>;
2843 qcom,ports-hstart = 2756 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0x00 0xff 0xff>;
2844 qcom,ports-hstop = 2757 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0x0f 0xff 0xff>;
2845 qcom,ports-word-lengt 2758 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2846 qcom,ports-block-pack 2759 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff>;
2847 qcom,ports-lane-contr 2760 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2848 qcom,ports-block-grou 2761 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2849 2762
2850 #sound-dai-cells = <1 2763 #sound-dai-cells = <1>;
2851 #address-cells = <2>; 2764 #address-cells = <2>;
2852 #size-cells = <0>; 2765 #size-cells = <0>;
2853 2766
2854 status = "disabled"; 2767 status = "disabled";
2855 }; 2768 };
2856 2769
2857 txmacro: txmacro@3220000 { 2770 txmacro: txmacro@3220000 {
2858 compatible = "qcom,sc 2771 compatible = "qcom,sc8280xp-lpass-tx-macro";
2859 reg = <0 0x03220000 0 2772 reg = <0 0x03220000 0 0x1000>;
2860 pinctrl-names = "defa 2773 pinctrl-names = "default";
2861 pinctrl-0 = <&tx_swr_ 2774 pinctrl-0 = <&tx_swr_default>;
2862 clocks = <&q6prmcc LP 2775 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2863 <&q6prmcc LP 2776 <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2864 <&q6prmcc LP 2777 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2865 <&q6prmcc LP 2778 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2866 <&vamacro>; 2779 <&vamacro>;
2867 2780
2868 clock-names = "mclk", 2781 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2869 assigned-clocks = <&q 2782 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2870 <&q 2783 <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2871 assigned-clock-rates 2784 assigned-clock-rates = <19200000>, <19200000>;
2872 clock-output-names = 2785 clock-output-names = "mclk";
2873 2786
2874 #clock-cells = <0>; 2787 #clock-cells = <0>;
2875 #sound-dai-cells = <1 2788 #sound-dai-cells = <1>;
2876 2789
2877 status = "disabled"; 2790 status = "disabled";
2878 }; 2791 };
2879 2792
2880 wsamacro: codec@3240000 { 2793 wsamacro: codec@3240000 {
2881 compatible = "qcom,sc 2794 compatible = "qcom,sc8280xp-lpass-wsa-macro";
2882 reg = <0 0x03240000 0 2795 reg = <0 0x03240000 0 0x1000>;
2883 clocks = <&q6prmcc LP 2796 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2884 <&q6prmcc LP 2797 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2885 <&q6prmcc LP 2798 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2886 <&q6prmcc LP 2799 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2887 <&vamacro>; 2800 <&vamacro>;
2888 clock-names = "mclk", 2801 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2889 assigned-clocks = <&q 2802 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2890 <&q 2803 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2891 assigned-clock-rates 2804 assigned-clock-rates = <19200000>, <19200000>;
2892 2805
2893 #clock-cells = <0>; 2806 #clock-cells = <0>;
2894 clock-output-names = 2807 clock-output-names = "mclk";
2895 #sound-dai-cells = <1 2808 #sound-dai-cells = <1>;
2896 2809
2897 pinctrl-names = "defa 2810 pinctrl-names = "default";
2898 pinctrl-0 = <&wsa_swr 2811 pinctrl-0 = <&wsa_swr_default>;
2899 2812
2900 status = "disabled"; 2813 status = "disabled";
2901 }; 2814 };
2902 2815
2903 swr0: soundwire@3250000 { 2816 swr0: soundwire@3250000 {
2904 reg = <0 0x03250000 0 2817 reg = <0 0x03250000 0 0x2000>;
2905 compatible = "qcom,so 2818 compatible = "qcom,soundwire-v1.6.0";
2906 interrupts = <GIC_SPI 2819 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
2907 clocks = <&wsamacro>; 2820 clocks = <&wsamacro>;
2908 clock-names = "iface" 2821 clock-names = "iface";
2909 resets = <&lpass_audi 2822 resets = <&lpass_audiocc LPASS_AUDIO_SWR_WSA_CGCR>;
2910 reset-names = "swr_au 2823 reset-names = "swr_audio_cgcr";
2911 label = "WSA"; 2824 label = "WSA";
2912 2825
2913 qcom,din-ports = <2>; 2826 qcom,din-ports = <2>;
2914 qcom,dout-ports = <6> 2827 qcom,dout-ports = <6>;
2915 2828
2916 qcom,ports-sinterval- 2829 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2917 qcom,ports-offset1 = 2830 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2918 qcom,ports-offset2 = 2831 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2919 qcom,ports-hstart = 2832 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2920 qcom,ports-hstop = 2833 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2921 qcom,ports-word-lengt 2834 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2922 qcom,ports-block-pack 2835 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
2923 qcom,ports-block-grou 2836 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2924 qcom,ports-lane-contr 2837 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2925 2838
2926 #sound-dai-cells = <1 2839 #sound-dai-cells = <1>;
2927 #address-cells = <2>; 2840 #address-cells = <2>;
2928 #size-cells = <0>; 2841 #size-cells = <0>;
2929 2842
2930 status = "disabled"; 2843 status = "disabled";
2931 }; 2844 };
2932 2845
2933 lpass_audiocc: clock-controll 2846 lpass_audiocc: clock-controller@32a9000 {
2934 compatible = "qcom,sc 2847 compatible = "qcom,sc8280xp-lpassaudiocc";
2935 reg = <0 0x032a9000 0 2848 reg = <0 0x032a9000 0 0x1000>;
2936 #clock-cells = <1>; 2849 #clock-cells = <1>;
2937 #reset-cells = <1>; 2850 #reset-cells = <1>;
2938 }; 2851 };
2939 2852
2940 swr2: soundwire@3330000 { 2853 swr2: soundwire@3330000 {
2941 compatible = "qcom,so 2854 compatible = "qcom,soundwire-v1.6.0";
2942 reg = <0 0x03330000 0 2855 reg = <0 0x03330000 0 0x2000>;
2943 interrupts = <GIC_SPI 2856 interrupts = <GIC_SPI 959 IRQ_TYPE_LEVEL_HIGH>,
2944 <GIC_SPI 2857 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>;
2945 interrupt-names = "co 2858 interrupt-names = "core", "wakeup";
2946 2859
2947 clocks = <&txmacro>; 2860 clocks = <&txmacro>;
2948 clock-names = "iface" 2861 clock-names = "iface";
2949 resets = <&lpasscc LP 2862 resets = <&lpasscc LPASS_AUDIO_SWR_TX_CGCR>;
2950 reset-names = "swr_au 2863 reset-names = "swr_audio_cgcr";
2951 label = "TX"; 2864 label = "TX";
2952 #sound-dai-cells = <1 2865 #sound-dai-cells = <1>;
2953 #address-cells = <2>; 2866 #address-cells = <2>;
2954 #size-cells = <0>; 2867 #size-cells = <0>;
2955 2868
2956 qcom,din-ports = <4>; 2869 qcom,din-ports = <4>;
2957 qcom,dout-ports = <0> 2870 qcom,dout-ports = <0>;
2958 qcom,ports-sinterval- 2871 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
2959 qcom,ports-offset1 = 2872 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02 0x00>;
2960 qcom,ports-offset2 = 2873 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
2961 qcom,ports-block-pack 2874 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
2962 qcom,ports-hstart = 2875 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
2963 qcom,ports-hstop = 2876 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
2964 qcom,ports-word-lengt 2877 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
2965 qcom,ports-block-grou 2878 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
2966 qcom,ports-lane-contr 2879 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00 0x01>;
2967 2880
2968 status = "disabled"; 2881 status = "disabled";
2969 }; 2882 };
2970 2883
2971 vamacro: codec@3370000 { 2884 vamacro: codec@3370000 {
2972 compatible = "qcom,sc 2885 compatible = "qcom,sc8280xp-lpass-va-macro";
2973 reg = <0 0x03370000 0 2886 reg = <0 0x03370000 0 0x1000>;
2974 clocks = <&q6prmcc LP 2887 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2975 <&q6prmcc LP 2888 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2976 <&q6prmcc LP 2889 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2977 <&q6prmcc LP 2890 <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2978 clock-names = "mclk", 2891 clock-names = "mclk", "macro", "dcodec", "npl";
2979 assigned-clocks = <&q 2892 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2980 assigned-clock-rates 2893 assigned-clock-rates = <19200000>;
2981 2894
2982 #clock-cells = <0>; 2895 #clock-cells = <0>;
2983 clock-output-names = 2896 clock-output-names = "fsgen";
2984 #sound-dai-cells = <1 2897 #sound-dai-cells = <1>;
2985 2898
2986 status = "disabled"; 2899 status = "disabled";
2987 }; 2900 };
2988 2901
2989 lpass_tlmm: pinctrl@33c0000 { 2902 lpass_tlmm: pinctrl@33c0000 {
2990 compatible = "qcom,sc 2903 compatible = "qcom,sc8280xp-lpass-lpi-pinctrl";
2991 reg = <0 0x33c0000 0x 2904 reg = <0 0x33c0000 0x0 0x20000>,
2992 <0 0x3550000 0x 2905 <0 0x3550000 0x0 0x10000>;
2993 gpio-controller; 2906 gpio-controller;
2994 #gpio-cells = <2>; 2907 #gpio-cells = <2>;
2995 gpio-ranges = <&lpass 2908 gpio-ranges = <&lpass_tlmm 0 0 19>;
2996 2909
2997 clocks = <&q6prmcc LP 2910 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2998 <&q6prmcc LP 2911 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2999 clock-names = "core", 2912 clock-names = "core", "audio";
3000 2913
3001 status = "disabled"; 2914 status = "disabled";
3002 2915
3003 tx_swr_default: tx-sw 2916 tx_swr_default: tx-swr-default-state {
3004 clk-pins { 2917 clk-pins {
3005 pins 2918 pins = "gpio0";
3006 funct 2919 function = "swr_tx_clk";
3007 drive 2920 drive-strength = <2>;
3008 slew- 2921 slew-rate = <1>;
3009 bias- 2922 bias-disable;
3010 }; 2923 };
3011 2924
3012 data-pins { 2925 data-pins {
3013 pins 2926 pins = "gpio1", "gpio2";
3014 funct 2927 function = "swr_tx_data";
3015 drive 2928 drive-strength = <2>;
3016 slew- 2929 slew-rate = <1>;
3017 bias- 2930 bias-bus-hold;
3018 }; 2931 };
3019 }; 2932 };
3020 2933
3021 rx_swr_default: rx-sw 2934 rx_swr_default: rx-swr-default-state {
3022 clk-pins { 2935 clk-pins {
3023 pins 2936 pins = "gpio3";
3024 funct 2937 function = "swr_rx_clk";
3025 drive 2938 drive-strength = <2>;
3026 slew- 2939 slew-rate = <1>;
3027 bias- 2940 bias-disable;
3028 }; 2941 };
3029 2942
3030 data-pins { 2943 data-pins {
3031 pins 2944 pins = "gpio4", "gpio5";
3032 funct 2945 function = "swr_rx_data";
3033 drive 2946 drive-strength = <2>;
3034 slew- 2947 slew-rate = <1>;
3035 bias- 2948 bias-bus-hold;
3036 }; 2949 };
3037 }; 2950 };
3038 2951
3039 dmic01_default: dmic0 2952 dmic01_default: dmic01-default-state {
3040 clk-pins { 2953 clk-pins {
3041 pins 2954 pins = "gpio6";
3042 funct 2955 function = "dmic1_clk";
3043 drive 2956 drive-strength = <8>;
3044 outpu 2957 output-high;
3045 }; 2958 };
3046 2959
3047 data-pins { 2960 data-pins {
3048 pins 2961 pins = "gpio7";
3049 funct 2962 function = "dmic1_data";
3050 drive 2963 drive-strength = <8>;
3051 input 2964 input-enable;
3052 }; 2965 };
3053 }; 2966 };
3054 2967
3055 dmic01_sleep: dmic01- 2968 dmic01_sleep: dmic01-sleep-state {
3056 clk-pins { 2969 clk-pins {
3057 pins 2970 pins = "gpio6";
3058 funct 2971 function = "dmic1_clk";
3059 drive 2972 drive-strength = <2>;
3060 bias- 2973 bias-disable;
3061 outpu 2974 output-low;
3062 }; 2975 };
3063 2976
3064 data-pins { 2977 data-pins {
3065 pins 2978 pins = "gpio7";
3066 funct 2979 function = "dmic1_data";
3067 drive 2980 drive-strength = <2>;
3068 bias- 2981 bias-pull-down;
3069 input 2982 input-enable;
3070 }; 2983 };
3071 }; 2984 };
3072 2985
3073 dmic23_default: dmic2 !! 2986 dmic02_default: dmic02-default-state {
3074 clk-pins { 2987 clk-pins {
3075 pins 2988 pins = "gpio8";
3076 funct 2989 function = "dmic2_clk";
3077 drive 2990 drive-strength = <8>;
3078 outpu 2991 output-high;
3079 }; 2992 };
3080 2993
3081 data-pins { 2994 data-pins {
3082 pins 2995 pins = "gpio9";
3083 funct 2996 function = "dmic2_data";
3084 drive 2997 drive-strength = <8>;
3085 input 2998 input-enable;
3086 }; 2999 };
3087 }; 3000 };
3088 3001
3089 dmic23_sleep: dmic23- !! 3002 dmic02_sleep: dmic02-sleep-state {
3090 clk-pins { 3003 clk-pins {
3091 pins 3004 pins = "gpio8";
3092 funct 3005 function = "dmic2_clk";
3093 drive 3006 drive-strength = <2>;
3094 bias- 3007 bias-disable;
3095 outpu 3008 output-low;
3096 }; 3009 };
3097 3010
3098 data-pins { 3011 data-pins {
3099 pins 3012 pins = "gpio9";
3100 funct 3013 function = "dmic2_data";
3101 drive 3014 drive-strength = <2>;
3102 bias- 3015 bias-pull-down;
3103 input 3016 input-enable;
3104 }; 3017 };
3105 }; 3018 };
3106 3019
3107 wsa_swr_default: wsa- 3020 wsa_swr_default: wsa-swr-default-state {
3108 clk-pins { 3021 clk-pins {
3109 pins 3022 pins = "gpio10";
3110 funct 3023 function = "wsa_swr_clk";
3111 drive 3024 drive-strength = <2>;
3112 slew- 3025 slew-rate = <1>;
3113 bias- 3026 bias-disable;
3114 }; 3027 };
3115 3028
3116 data-pins { 3029 data-pins {
3117 pins 3030 pins = "gpio11";
3118 funct 3031 function = "wsa_swr_data";
3119 drive 3032 drive-strength = <2>;
3120 slew- 3033 slew-rate = <1>;
3121 bias- 3034 bias-bus-hold;
3122 }; 3035 };
3123 }; 3036 };
3124 3037
3125 wsa2_swr_default: wsa 3038 wsa2_swr_default: wsa2-swr-default-state {
3126 clk-pins { 3039 clk-pins {
3127 pins 3040 pins = "gpio15";
3128 funct 3041 function = "wsa2_swr_clk";
3129 drive 3042 drive-strength = <2>;
3130 slew- 3043 slew-rate = <1>;
3131 bias- 3044 bias-disable;
3132 }; 3045 };
3133 3046
3134 data-pins { 3047 data-pins {
3135 pins 3048 pins = "gpio16";
3136 funct 3049 function = "wsa2_swr_data";
3137 drive 3050 drive-strength = <2>;
3138 slew- 3051 slew-rate = <1>;
3139 bias- 3052 bias-bus-hold;
3140 }; 3053 };
3141 }; 3054 };
3142 }; 3055 };
3143 3056
3144 lpasscc: clock-controller@33e 3057 lpasscc: clock-controller@33e0000 {
3145 compatible = "qcom,sc 3058 compatible = "qcom,sc8280xp-lpasscc";
3146 reg = <0 0x033e0000 0 3059 reg = <0 0x033e0000 0 0x12000>;
3147 #clock-cells = <1>; 3060 #clock-cells = <1>;
3148 #reset-cells = <1>; 3061 #reset-cells = <1>;
3149 }; 3062 };
3150 3063
3151 sdc2: mmc@8804000 { 3064 sdc2: mmc@8804000 {
3152 compatible = "qcom,sc 3065 compatible = "qcom,sc8280xp-sdhci", "qcom,sdhci-msm-v5";
3153 reg = <0 0x08804000 0 3066 reg = <0 0x08804000 0 0x1000>;
3154 3067
3155 interrupts = <GIC_SPI 3068 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
3156 <GIC_SPI 3069 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
3157 interrupt-names = "hc 3070 interrupt-names = "hc_irq", "pwr_irq";
3158 3071
3159 clocks = <&gcc GCC_SD 3072 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3160 <&gcc GCC_SD 3073 <&gcc GCC_SDCC2_APPS_CLK>,
3161 <&rpmhcc RPM 3074 <&rpmhcc RPMH_CXO_CLK>;
3162 clock-names = "iface" 3075 clock-names = "iface", "core", "xo";
3163 resets = <&gcc GCC_SD 3076 resets = <&gcc GCC_SDCC2_BCR>;
3164 interconnects = <&agg 3077 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
3165 <&gem 3078 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
3166 interconnect-names = 3079 interconnect-names = "sdhc-ddr","cpu-sdhc";
3167 iommus = <&apps_smmu 3080 iommus = <&apps_smmu 0x4e0 0x0>;
3168 power-domains = <&rpm 3081 power-domains = <&rpmhpd SC8280XP_CX>;
3169 operating-points-v2 = 3082 operating-points-v2 = <&sdc2_opp_table>;
3170 bus-width = <4>; 3083 bus-width = <4>;
3171 dma-coherent; 3084 dma-coherent;
3172 3085
3173 status = "disabled"; 3086 status = "disabled";
3174 3087
3175 sdc2_opp_table: opp-t 3088 sdc2_opp_table: opp-table {
3176 compatible = 3089 compatible = "operating-points-v2";
3177 3090
3178 opp-100000000 3091 opp-100000000 {
3179 opp-h 3092 opp-hz = /bits/ 64 <100000000>;
3180 requi 3093 required-opps = <&rpmhpd_opp_low_svs>;
3181 opp-p 3094 opp-peak-kBps = <1800000 400000>;
3182 opp-a 3095 opp-avg-kBps = <100000 0>;
3183 }; 3096 };
3184 3097
3185 opp-202000000 3098 opp-202000000 {
3186 opp-h 3099 opp-hz = /bits/ 64 <202000000>;
3187 requi 3100 required-opps = <&rpmhpd_opp_svs_l1>;
3188 opp-p 3101 opp-peak-kBps = <5400000 1600000>;
3189 opp-a 3102 opp-avg-kBps = <200000 0>;
3190 }; 3103 };
3191 }; 3104 };
3192 }; 3105 };
3193 3106
3194 usb_0_qmpphy: phy@88eb000 { 3107 usb_0_qmpphy: phy@88eb000 {
3195 compatible = "qcom,sc 3108 compatible = "qcom,sc8280xp-qmp-usb43dp-phy";
3196 reg = <0 0x088eb000 0 3109 reg = <0 0x088eb000 0 0x4000>;
3197 3110
3198 clocks = <&gcc GCC_US 3111 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
3199 <&gcc GCC_US 3112 <&gcc GCC_USB4_EUD_CLKREF_CLK>,
3200 <&gcc GCC_US 3113 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
3201 <&gcc GCC_US 3114 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3202 clock-names = "aux", 3115 clock-names = "aux", "ref", "com_aux", "usb3_pipe";
3203 3116
3204 power-domains = <&gcc 3117 power-domains = <&gcc USB30_PRIM_GDSC>;
3205 3118
3206 resets = <&gcc GCC_US 3119 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
3207 <&gcc GCC_US 3120 <&gcc GCC_USB4_DP_PHY_PRIM_BCR>;
3208 reset-names = "phy", 3121 reset-names = "phy", "common";
3209 3122
3210 #clock-cells = <1>; 3123 #clock-cells = <1>;
3211 #phy-cells = <1>; 3124 #phy-cells = <1>;
3212 3125
3213 status = "disabled"; 3126 status = "disabled";
3214 3127
3215 ports { 3128 ports {
3216 #address-cell 3129 #address-cells = <1>;
3217 #size-cells = 3130 #size-cells = <0>;
3218 3131
3219 port@0 { 3132 port@0 {
3220 reg = 3133 reg = <0>;
3221 3134
3222 usb_0 3135 usb_0_qmpphy_out: endpoint {};
3223 }; 3136 };
3224 3137
3225 port@1 { <<
3226 reg = <<
3227 <<
3228 usb_0 <<
3229 <<
3230 }; <<
3231 }; <<
3232 <<
3233 port@2 { 3138 port@2 {
3234 reg = 3139 reg = <2>;
3235 3140
3236 usb_0 3141 usb_0_qmpphy_dp_in: endpoint {};
3237 }; 3142 };
3238 }; 3143 };
3239 }; 3144 };
3240 3145
3241 usb_1_hsphy: phy@8902000 { 3146 usb_1_hsphy: phy@8902000 {
3242 compatible = "qcom,sc 3147 compatible = "qcom,sc8280xp-usb-hs-phy",
3243 "qcom,us 3148 "qcom,usb-snps-hs-5nm-phy";
3244 reg = <0 0x08902000 0 3149 reg = <0 0x08902000 0 0x400>;
3245 #phy-cells = <0>; 3150 #phy-cells = <0>;
3246 3151
3247 clocks = <&rpmhcc RPM 3152 clocks = <&rpmhcc RPMH_CXO_CLK>;
3248 clock-names = "ref"; 3153 clock-names = "ref";
3249 3154
3250 resets = <&gcc GCC_QU 3155 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3251 3156
3252 status = "disabled"; 3157 status = "disabled";
3253 }; 3158 };
3254 3159
3255 usb_1_qmpphy: phy@8903000 { 3160 usb_1_qmpphy: phy@8903000 {
3256 compatible = "qcom,sc 3161 compatible = "qcom,sc8280xp-qmp-usb43dp-phy";
3257 reg = <0 0x08903000 0 3162 reg = <0 0x08903000 0 0x4000>;
3258 3163
3259 clocks = <&gcc GCC_US 3164 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
3260 <&gcc GCC_US 3165 <&gcc GCC_USB4_CLKREF_CLK>,
3261 <&gcc GCC_US 3166 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
3262 <&gcc GCC_US 3167 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
3263 clock-names = "aux", 3168 clock-names = "aux", "ref", "com_aux", "usb3_pipe";
3264 3169
3265 power-domains = <&gcc 3170 power-domains = <&gcc USB30_SEC_GDSC>;
3266 3171
3267 resets = <&gcc GCC_US 3172 resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
3268 <&gcc GCC_US 3173 <&gcc GCC_USB4_1_DP_PHY_PRIM_BCR>;
3269 reset-names = "phy", 3174 reset-names = "phy", "common";
3270 3175
3271 #clock-cells = <1>; 3176 #clock-cells = <1>;
3272 #phy-cells = <1>; 3177 #phy-cells = <1>;
3273 3178
3274 status = "disabled"; 3179 status = "disabled";
3275 3180
3276 ports { 3181 ports {
3277 #address-cell 3182 #address-cells = <1>;
3278 #size-cells = 3183 #size-cells = <0>;
3279 3184
3280 port@0 { 3185 port@0 {
3281 reg = 3186 reg = <0>;
3282 3187
3283 usb_1 3188 usb_1_qmpphy_out: endpoint {};
3284 }; 3189 };
3285 3190
3286 port@1 { <<
3287 reg = <<
3288 <<
3289 usb_1 <<
3290 <<
3291 }; <<
3292 }; <<
3293 <<
3294 port@2 { 3191 port@2 {
3295 reg = 3192 reg = <2>;
3296 3193
3297 usb_1 3194 usb_1_qmpphy_dp_in: endpoint {};
3298 }; 3195 };
3299 }; 3196 };
3300 }; 3197 };
3301 3198
3302 mdss1_dp0_phy: phy@8909a00 { 3199 mdss1_dp0_phy: phy@8909a00 {
3303 compatible = "qcom,sc 3200 compatible = "qcom,sc8280xp-dp-phy";
3304 reg = <0 0x08909a00 0 3201 reg = <0 0x08909a00 0 0x19c>,
3305 <0 0x08909200 0 3202 <0 0x08909200 0 0xec>,
3306 <0 0x08909600 0 3203 <0 0x08909600 0 0xec>,
3307 <0 0x08909000 0 3204 <0 0x08909000 0 0x1c8>;
3308 3205
3309 clocks = <&dispcc1 DI 3206 clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>,
3310 <&dispcc1 DI 3207 <&dispcc1 DISP_CC_MDSS_AHB_CLK>;
3311 clock-names = "aux", 3208 clock-names = "aux", "cfg_ahb";
3312 power-domains = <&rpm 3209 power-domains = <&rpmhpd SC8280XP_MX>;
3313 3210
3314 #clock-cells = <1>; 3211 #clock-cells = <1>;
3315 #phy-cells = <0>; 3212 #phy-cells = <0>;
3316 3213
3317 status = "disabled"; 3214 status = "disabled";
3318 }; 3215 };
3319 3216
3320 mdss1_dp1_phy: phy@890ca00 { 3217 mdss1_dp1_phy: phy@890ca00 {
3321 compatible = "qcom,sc 3218 compatible = "qcom,sc8280xp-dp-phy";
3322 reg = <0 0x0890ca00 0 3219 reg = <0 0x0890ca00 0 0x19c>,
3323 <0 0x0890c200 0 3220 <0 0x0890c200 0 0xec>,
3324 <0 0x0890c600 0 3221 <0 0x0890c600 0 0xec>,
3325 <0 0x0890c000 0 3222 <0 0x0890c000 0 0x1c8>;
3326 3223
3327 clocks = <&dispcc1 DI 3224 clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>,
3328 <&dispcc1 DI 3225 <&dispcc1 DISP_CC_MDSS_AHB_CLK>;
3329 clock-names = "aux", 3226 clock-names = "aux", "cfg_ahb";
3330 power-domains = <&rpm 3227 power-domains = <&rpmhpd SC8280XP_MX>;
3331 3228
3332 #clock-cells = <1>; 3229 #clock-cells = <1>;
3333 #phy-cells = <0>; 3230 #phy-cells = <0>;
3334 3231
3335 status = "disabled"; 3232 status = "disabled";
3336 }; 3233 };
3337 3234
3338 pmu@9091000 { 3235 pmu@9091000 {
3339 compatible = "qcom,sc 3236 compatible = "qcom,sc8280xp-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
3340 reg = <0 0x09091000 0 3237 reg = <0 0x09091000 0 0x1000>;
3341 3238
3342 interrupts = <GIC_SPI 3239 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
3343 3240
3344 interconnects = <&mc_ 3241 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>;
3345 3242
3346 operating-points-v2 = 3243 operating-points-v2 = <&llcc_bwmon_opp_table>;
3347 3244
3348 llcc_bwmon_opp_table: 3245 llcc_bwmon_opp_table: opp-table {
3349 compatible = 3246 compatible = "operating-points-v2";
3350 3247
3351 opp-0 { 3248 opp-0 {
3352 opp-p 3249 opp-peak-kBps = <762000>;
3353 }; 3250 };
3354 opp-1 { 3251 opp-1 {
3355 opp-p 3252 opp-peak-kBps = <1720000>;
3356 }; 3253 };
3357 opp-2 { 3254 opp-2 {
3358 opp-p 3255 opp-peak-kBps = <2086000>;
3359 }; 3256 };
3360 opp-3 { 3257 opp-3 {
3361 opp-p 3258 opp-peak-kBps = <2597000>;
3362 }; 3259 };
3363 opp-4 { 3260 opp-4 {
3364 opp-p 3261 opp-peak-kBps = <2929000>;
3365 }; 3262 };
3366 opp-5 { 3263 opp-5 {
3367 opp-p 3264 opp-peak-kBps = <3879000>;
3368 }; 3265 };
3369 opp-6 { 3266 opp-6 {
3370 opp-p 3267 opp-peak-kBps = <5161000>;
3371 }; 3268 };
3372 opp-7 { 3269 opp-7 {
3373 opp-p 3270 opp-peak-kBps = <5931000>;
3374 }; 3271 };
3375 opp-8 { 3272 opp-8 {
3376 opp-p 3273 opp-peak-kBps = <6515000>;
3377 }; 3274 };
3378 opp-9 { 3275 opp-9 {
3379 opp-p 3276 opp-peak-kBps = <7980000>;
3380 }; 3277 };
3381 opp-10 { 3278 opp-10 {
3382 opp-p 3279 opp-peak-kBps = <8136000>;
3383 }; 3280 };
3384 opp-11 { 3281 opp-11 {
3385 opp-p 3282 opp-peak-kBps = <10437000>;
3386 }; 3283 };
3387 opp-12 { 3284 opp-12 {
3388 opp-p 3285 opp-peak-kBps = <12191000>;
3389 }; 3286 };
3390 }; 3287 };
3391 }; 3288 };
3392 3289
3393 pmu@90b6400 { 3290 pmu@90b6400 {
3394 compatible = "qcom,sc 3291 compatible = "qcom,sc8280xp-cpu-bwmon", "qcom,sdm845-bwmon";
3395 reg = <0 0x090b6400 0 3292 reg = <0 0x090b6400 0 0x600>;
3396 3293
3397 interrupts = <GIC_SPI 3294 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
3398 3295
3399 interconnects = <&gem 3296 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>;
3400 operating-points-v2 = 3297 operating-points-v2 = <&cpu_bwmon_opp_table>;
3401 3298
3402 cpu_bwmon_opp_table: 3299 cpu_bwmon_opp_table: opp-table {
3403 compatible = 3300 compatible = "operating-points-v2";
3404 3301
3405 opp-0 { 3302 opp-0 {
3406 opp-p 3303 opp-peak-kBps = <2288000>;
3407 }; 3304 };
3408 opp-1 { 3305 opp-1 {
3409 opp-p 3306 opp-peak-kBps = <4577000>;
3410 }; 3307 };
3411 opp-2 { 3308 opp-2 {
3412 opp-p 3309 opp-peak-kBps = <7110000>;
3413 }; 3310 };
3414 opp-3 { 3311 opp-3 {
3415 opp-p 3312 opp-peak-kBps = <9155000>;
3416 }; 3313 };
3417 opp-4 { 3314 opp-4 {
3418 opp-p 3315 opp-peak-kBps = <12298000>;
3419 }; 3316 };
3420 opp-5 { 3317 opp-5 {
3421 opp-p 3318 opp-peak-kBps = <14236000>;
3422 }; 3319 };
3423 opp-6 { 3320 opp-6 {
3424 opp-p 3321 opp-peak-kBps = <15258001>;
3425 }; 3322 };
3426 }; 3323 };
3427 }; 3324 };
3428 3325
3429 system-cache-controller@92000 3326 system-cache-controller@9200000 {
3430 compatible = "qcom,sc 3327 compatible = "qcom,sc8280xp-llcc";
3431 reg = <0 0x09200000 0 3328 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>,
3432 <0 0x09300000 0 3329 <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>,
3433 <0 0x09400000 0 3330 <0 0x09400000 0 0x58000>, <0 0x09480000 0 0x58000>,
3434 <0 0x09500000 0 3331 <0 0x09500000 0 0x58000>, <0 0x09580000 0 0x58000>,
3435 <0 0x09600000 0 3332 <0 0x09600000 0 0x58000>;
3436 reg-names = "llcc0_ba 3333 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
3437 "llcc3_ba 3334 "llcc3_base", "llcc4_base", "llcc5_base",
3438 "llcc6_ba 3335 "llcc6_base", "llcc7_base", "llcc_broadcast_base";
3439 interrupts = <GIC_SPI 3336 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
3440 }; 3337 };
3441 3338
3442 usb_2: usb@a4f8800 { <<
3443 compatible = "qcom,sc <<
3444 reg = <0 0x0a4f8800 0 <<
3445 #address-cells = <2>; <<
3446 #size-cells = <2>; <<
3447 ranges; <<
3448 <<
3449 clocks = <&gcc GCC_CF <<
3450 <&gcc GCC_US <<
3451 <&gcc GCC_AG <<
3452 <&gcc GCC_US <<
3453 <&gcc GCC_US <<
3454 <&gcc GCC_AG <<
3455 <&gcc GCC_AG <<
3456 <&gcc GCC_AG <<
3457 <&gcc GCC_SY <<
3458 clock-names = "cfg_no <<
3459 "noc_ag <<
3460 <<
3461 assigned-clocks = <&g <<
3462 <&g <<
3463 assigned-clock-rates <<
3464 <<
3465 interrupts-extended = <<
3466 <<
3467 <<
3468 <<
3469 <<
3470 <<
3471 <<
3472 <<
3473 <<
3474 <<
3475 <<
3476 <<
3477 <<
3478 <<
3479 <<
3480 <<
3481 <<
3482 <<
3483 <<
3484 interrupt-names = "pw <<
3485 "pw <<
3486 "hs <<
3487 "hs <<
3488 "dp <<
3489 "dp <<
3490 "dp <<
3491 "dp <<
3492 "ss <<
3493 <<
3494 power-domains = <&gcc <<
3495 required-opps = <&rpm <<
3496 <<
3497 resets = <&gcc GCC_US <<
3498 <<
3499 interconnects = <&agg <<
3500 <&gem <<
3501 interconnect-names = <<
3502 <<
3503 wakeup-source; <<
3504 <<
3505 status = "disabled"; <<
3506 <<
3507 usb_2_dwc3: usb@a4000 <<
3508 compatible = <<
3509 reg = <0 0x0a <<
3510 interrupts = <<
3511 iommus = <&ap <<
3512 phys = <&usb_ <<
3513 <&usb_ <<
3514 <&usb_ <<
3515 <&usb_ <<
3516 phy-names = " <<
3517 " <<
3518 " <<
3519 " <<
3520 dr_mode = "ho <<
3521 }; <<
3522 }; <<
3523 <<
3524 usb_0: usb@a6f8800 { 3339 usb_0: usb@a6f8800 {
3525 compatible = "qcom,sc 3340 compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3";
3526 reg = <0 0x0a6f8800 0 3341 reg = <0 0x0a6f8800 0 0x400>;
3527 #address-cells = <2>; 3342 #address-cells = <2>;
3528 #size-cells = <2>; 3343 #size-cells = <2>;
3529 ranges; 3344 ranges;
3530 3345
3531 clocks = <&gcc GCC_CF 3346 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
3532 <&gcc GCC_US 3347 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
3533 <&gcc GCC_AG 3348 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
3534 <&gcc GCC_US 3349 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
3535 <&gcc GCC_US 3350 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3536 <&gcc GCC_AG 3351 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
3537 <&gcc GCC_AG 3352 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>,
3538 <&gcc GCC_AG 3353 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>,
3539 <&gcc GCC_SY 3354 <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
3540 clock-names = "cfg_no 3355 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi",
3541 "noc_ag 3356 "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys";
3542 3357
3543 assigned-clocks = <&g 3358 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3544 <&g 3359 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
3545 assigned-clock-rates 3360 assigned-clock-rates = <19200000>, <200000000>;
3546 3361
3547 interrupts-extended = 3362 interrupts-extended = <&intc GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>,
3548 <<
3549 3363 <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
3550 3364 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
3551 3365 <&pdc 138 IRQ_TYPE_LEVEL_HIGH>;
3552 interrupt-names = "pw 3366 interrupt-names = "pwr_event",
3553 "hs <<
3554 "dp 3367 "dp_hs_phy_irq",
3555 "dm 3368 "dm_hs_phy_irq",
3556 "ss 3369 "ss_phy_irq";
3557 3370
3558 power-domains = <&gcc 3371 power-domains = <&gcc USB30_PRIM_GDSC>;
3559 required-opps = <&rpm 3372 required-opps = <&rpmhpd_opp_nom>;
3560 3373
3561 resets = <&gcc GCC_US 3374 resets = <&gcc GCC_USB30_PRIM_BCR>;
3562 3375
3563 interconnects = <&agg 3376 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
3564 <&gem 3377 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
3565 interconnect-names = 3378 interconnect-names = "usb-ddr", "apps-usb";
3566 3379
3567 wakeup-source; 3380 wakeup-source;
3568 3381
3569 status = "disabled"; 3382 status = "disabled";
3570 3383
3571 usb_0_dwc3: usb@a6000 3384 usb_0_dwc3: usb@a600000 {
3572 compatible = 3385 compatible = "snps,dwc3";
3573 reg = <0 0x0a 3386 reg = <0 0x0a600000 0 0xcd00>;
3574 interrupts = 3387 interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>;
3575 iommus = <&ap 3388 iommus = <&apps_smmu 0x820 0x0>;
3576 phys = <&usb_ 3389 phys = <&usb_0_hsphy>, <&usb_0_qmpphy QMP_USB43DP_USB3_PHY>;
3577 phy-names = " 3390 phy-names = "usb2-phy", "usb3-phy";
3578 3391
3579 ports { !! 3392 port {
3580 #addr !! 3393 usb_0_role_switch: endpoint {
3581 #size <<
3582 <<
3583 port@ <<
3584 <<
3585 <<
3586 <<
3587 <<
3588 }; <<
3589 <<
3590 port@ <<
3591 <<
3592 <<
3593 <<
3594 <<
3595 <<
3596 }; 3394 };
3597 }; 3395 };
3598 }; 3396 };
3599 }; 3397 };
3600 3398
3601 usb_1: usb@a8f8800 { 3399 usb_1: usb@a8f8800 {
3602 compatible = "qcom,sc 3400 compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3";
3603 reg = <0 0x0a8f8800 0 3401 reg = <0 0x0a8f8800 0 0x400>;
3604 #address-cells = <2>; 3402 #address-cells = <2>;
3605 #size-cells = <2>; 3403 #size-cells = <2>;
3606 ranges; 3404 ranges;
3607 3405
3608 clocks = <&gcc GCC_CF 3406 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
3609 <&gcc GCC_US 3407 <&gcc GCC_USB30_SEC_MASTER_CLK>,
3610 <&gcc GCC_AG 3408 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
3611 <&gcc GCC_US 3409 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
3612 <&gcc GCC_US 3410 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3613 <&gcc GCC_AG 3411 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
3614 <&gcc GCC_AG 3412 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>,
3615 <&gcc GCC_AG 3413 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>,
3616 <&gcc GCC_SY 3414 <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
3617 clock-names = "cfg_no 3415 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi",
3618 "noc_ag 3416 "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys";
3619 3417
3620 assigned-clocks = <&g 3418 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3621 <&g 3419 <&gcc GCC_USB30_SEC_MASTER_CLK>;
3622 assigned-clock-rates 3420 assigned-clock-rates = <19200000>, <200000000>;
3623 3421
3624 interrupts-extended = 3422 interrupts-extended = <&intc GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>,
3625 <<
3626 3423 <&pdc 12 IRQ_TYPE_EDGE_BOTH>,
3627 3424 <&pdc 13 IRQ_TYPE_EDGE_BOTH>,
3628 3425 <&pdc 136 IRQ_TYPE_LEVEL_HIGH>;
3629 interrupt-names = "pw 3426 interrupt-names = "pwr_event",
3630 "hs <<
3631 "dp 3427 "dp_hs_phy_irq",
3632 "dm 3428 "dm_hs_phy_irq",
3633 "ss 3429 "ss_phy_irq";
3634 3430
3635 power-domains = <&gcc 3431 power-domains = <&gcc USB30_SEC_GDSC>;
3636 required-opps = <&rpm 3432 required-opps = <&rpmhpd_opp_nom>;
3637 3433
3638 resets = <&gcc GCC_US 3434 resets = <&gcc GCC_USB30_SEC_BCR>;
3639 3435
3640 interconnects = <&agg 3436 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>,
3641 <&gem 3437 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
3642 interconnect-names = 3438 interconnect-names = "usb-ddr", "apps-usb";
3643 3439
3644 wakeup-source; 3440 wakeup-source;
3645 3441
3646 status = "disabled"; 3442 status = "disabled";
3647 3443
3648 usb_1_dwc3: usb@a8000 3444 usb_1_dwc3: usb@a800000 {
3649 compatible = 3445 compatible = "snps,dwc3";
3650 reg = <0 0x0a 3446 reg = <0 0x0a800000 0 0xcd00>;
3651 interrupts = 3447 interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>;
3652 iommus = <&ap 3448 iommus = <&apps_smmu 0x860 0x0>;
3653 phys = <&usb_ 3449 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
3654 phy-names = " 3450 phy-names = "usb2-phy", "usb3-phy";
3655 3451
3656 ports { !! 3452 port {
3657 #addr !! 3453 usb_1_role_switch: endpoint {
3658 #size <<
3659 <<
3660 port@ <<
3661 <<
3662 <<
3663 <<
3664 <<
3665 }; <<
3666 <<
3667 port@ <<
3668 <<
3669 <<
3670 <<
3671 <<
3672 <<
3673 }; 3454 };
3674 }; 3455 };
3675 }; 3456 };
3676 }; 3457 };
3677 3458
3678 cci0: cci@ac4a000 { <<
3679 compatible = "qcom,sc <<
3680 reg = <0 0x0ac4a000 0 <<
3681 <<
3682 interrupts = <GIC_SPI <<
3683 <<
3684 clocks = <&camcc CAMC <<
3685 <&camcc CAMC <<
3686 <&camcc CAMC <<
3687 <&camcc CAMC <<
3688 clock-names = "camnoc <<
3689 "slow_a <<
3690 "cpas_a <<
3691 "cci"; <<
3692 <<
3693 power-domains = <&cam <<
3694 <<
3695 pinctrl-0 = <&cci0_de <<
3696 pinctrl-1 = <&cci0_sl <<
3697 pinctrl-names = "defa <<
3698 <<
3699 #address-cells = <1>; <<
3700 #size-cells = <0>; <<
3701 <<
3702 status = "disabled"; <<
3703 <<
3704 cci0_i2c0: i2c-bus@0 <<
3705 reg = <0>; <<
3706 clock-frequen <<
3707 #address-cell <<
3708 #size-cells = <<
3709 }; <<
3710 <<
3711 cci0_i2c1: i2c-bus@1 <<
3712 reg = <1>; <<
3713 clock-frequen <<
3714 #address-cell <<
3715 #size-cells = <<
3716 }; <<
3717 }; <<
3718 <<
3719 cci1: cci@ac4b000 { <<
3720 compatible = "qcom,sc <<
3721 reg = <0 0x0ac4b000 0 <<
3722 <<
3723 interrupts = <GIC_SPI <<
3724 <<
3725 clocks = <&camcc CAMC <<
3726 <&camcc CAMC <<
3727 <&camcc CAMC <<
3728 <&camcc CAMC <<
3729 clock-names = "camnoc <<
3730 "slow_a <<
3731 "cpas_a <<
3732 "cci"; <<
3733 <<
3734 power-domains = <&cam <<
3735 <<
3736 pinctrl-0 = <&cci1_de <<
3737 pinctrl-1 = <&cci1_sl <<
3738 pinctrl-names = "defa <<
3739 <<
3740 #address-cells = <1>; <<
3741 #size-cells = <0>; <<
3742 <<
3743 status = "disabled"; <<
3744 <<
3745 cci1_i2c0: i2c-bus@0 <<
3746 reg = <0>; <<
3747 clock-frequen <<
3748 #address-cell <<
3749 #size-cells = <<
3750 }; <<
3751 <<
3752 cci1_i2c1: i2c-bus@1 <<
3753 reg = <1>; <<
3754 clock-frequen <<
3755 #address-cell <<
3756 #size-cells = <<
3757 }; <<
3758 }; <<
3759 <<
3760 cci2: cci@ac4c000 { <<
3761 compatible = "qcom,sc <<
3762 reg = <0 0x0ac4c000 0 <<
3763 <<
3764 interrupts = <GIC_SPI <<
3765 <<
3766 clocks = <&camcc CAMC <<
3767 <&camcc CAMC <<
3768 <&camcc CAMC <<
3769 <&camcc CAMC <<
3770 clock-names = "camnoc <<
3771 "slow_a <<
3772 "cpas_a <<
3773 "cci"; <<
3774 power-domains = <&cam <<
3775 <<
3776 pinctrl-0 = <&cci2_de <<
3777 pinctrl-1 = <&cci2_sl <<
3778 pinctrl-names = "defa <<
3779 <<
3780 #address-cells = <1>; <<
3781 #size-cells = <0>; <<
3782 <<
3783 status = "disabled"; <<
3784 <<
3785 cci2_i2c0: i2c-bus@0 <<
3786 reg = <0>; <<
3787 clock-frequen <<
3788 #address-cell <<
3789 #size-cells = <<
3790 }; <<
3791 <<
3792 cci2_i2c1: i2c-bus@1 <<
3793 reg = <1>; <<
3794 clock-frequen <<
3795 #address-cell <<
3796 #size-cells = <<
3797 }; <<
3798 }; <<
3799 <<
3800 cci3: cci@ac4d000 { <<
3801 compatible = "qcom,sc <<
3802 reg = <0 0x0ac4d000 0 <<
3803 <<
3804 interrupts = <GIC_SPI <<
3805 <<
3806 clocks = <&camcc CAMC <<
3807 <&camcc CAMC <<
3808 <&camcc CAMC <<
3809 <&camcc CAMC <<
3810 clock-names = "camnoc <<
3811 "slow_a <<
3812 "cpas_a <<
3813 "cci"; <<
3814 <<
3815 power-domains = <&cam <<
3816 <<
3817 pinctrl-0 = <&cci3_de <<
3818 pinctrl-1 = <&cci3_sl <<
3819 pinctrl-names = "defa <<
3820 <<
3821 #address-cells = <1>; <<
3822 #size-cells = <0>; <<
3823 <<
3824 status = "disabled"; <<
3825 <<
3826 cci3_i2c0: i2c-bus@0 <<
3827 reg = <0>; <<
3828 clock-frequen <<
3829 #address-cell <<
3830 #size-cells = <<
3831 }; <<
3832 <<
3833 cci3_i2c1: i2c-bus@1 <<
3834 reg = <1>; <<
3835 clock-frequen <<
3836 #address-cell <<
3837 #size-cells = <<
3838 }; <<
3839 }; <<
3840 <<
3841 camss: camss@ac5a000 { <<
3842 compatible = "qcom,sc <<
3843 <<
3844 reg = <0 0x0ac5a000 0 <<
3845 <0 0x0ac5c000 0 <<
3846 <0 0x0ac65000 0 <<
3847 <0 0x0ac67000 0 <<
3848 <0 0x0acaf000 0 <<
3849 <0 0x0acb3000 0 <<
3850 <0 0x0acb6000 0 <<
3851 <0 0x0acba000 0 <<
3852 <0 0x0acbd000 0 <<
3853 <0 0x0acc1000 0 <<
3854 <0 0x0acc4000 0 <<
3855 <0 0x0acc8000 0 <<
3856 <0 0x0accb000 0 <<
3857 <0 0x0accf000 0 <<
3858 <0 0x0acd2000 0 <<
3859 <0 0x0acd6000 0 <<
3860 <0 0x0acd9000 0 <<
3861 <0 0x0acdd000 0 <<
3862 <0 0x0ace0000 0 <<
3863 <0 0x0ace4000 0 <<
3864 reg-names = "csiphy2" <<
3865 "csiphy3" <<
3866 "csiphy0" <<
3867 "csiphy1" <<
3868 "vfe0", <<
3869 "csid0", <<
3870 "vfe1", <<
3871 "csid1", <<
3872 "vfe2", <<
3873 "csid2", <<
3874 "vfe_lite <<
3875 "csid0_li <<
3876 "vfe_lite <<
3877 "csid1_li <<
3878 "vfe_lite <<
3879 "csid2_li <<
3880 "vfe_lite <<
3881 "csid3_li <<
3882 "vfe3", <<
3883 "csid3"; <<
3884 <<
3885 interrupts = <GIC_SPI <<
3886 <GIC_SPI <<
3887 <GIC_SPI <<
3888 <GIC_SPI <<
3889 <GIC_SPI <<
3890 <GIC_SPI <<
3891 <GIC_SPI <<
3892 <GIC_SPI <<
3893 <GIC_SPI <<
3894 <GIC_SPI <<
3895 <GIC_SPI <<
3896 <GIC_SPI <<
3897 <GIC_SPI <<
3898 <GIC_SPI <<
3899 <GIC_SPI <<
3900 <GIC_SPI <<
3901 <GIC_SPI <<
3902 <GIC_SPI <<
3903 <GIC_SPI <<
3904 <GIC_SPI <<
3905 interrupt-names = "cs <<
3906 "vf <<
3907 "cs <<
3908 "cs <<
3909 "vf <<
3910 "cs <<
3911 "vf <<
3912 "cs <<
3913 "vf <<
3914 "cs <<
3915 "cs <<
3916 "cs <<
3917 "cs <<
3918 "vf <<
3919 "cs <<
3920 "cs <<
3921 "vf <<
3922 "vf <<
3923 "cs <<
3924 "vf <<
3925 <<
3926 power-domains = <&cam <<
3927 <&cam <<
3928 <&cam <<
3929 <&cam <<
3930 <&cam <<
3931 power-domain-names = <<
3932 <<
3933 <<
3934 <<
3935 <<
3936 <<
3937 clocks = <&camcc CAMC <<
3938 <&camcc CAMC <<
3939 <&camcc CAMC <<
3940 <&camcc CAMC <<
3941 <&camcc CAMC <<
3942 <&camcc CAMC <<
3943 <&camcc CAMC <<
3944 <&camcc CAMC <<
3945 <&camcc CAMC <<
3946 <&camcc CAMC <<
3947 <&camcc CAMC <<
3948 <&camcc CAMC <<
3949 <&camcc CAMC <<
3950 <&camcc CAMC <<
3951 <&camcc CAMC <<
3952 <&camcc CAMC <<
3953 <&camcc CAMC <<
3954 <&camcc CAMC <<
3955 <&camcc CAMC <<
3956 <&camcc CAMC <<
3957 <&camcc CAMC <<
3958 <&camcc CAMC <<
3959 <&camcc CAMC <<
3960 <&camcc CAMC <<
3961 <&camcc CAMC <<
3962 <&camcc CAMC <<
3963 <&camcc CAMC <<
3964 <&camcc CAMC <<
3965 <&camcc CAMC <<
3966 <&camcc CAMC <<
3967 <&camcc CAMC <<
3968 <&camcc CAMC <<
3969 <&camcc CAMC <<
3970 <&camcc CAMC <<
3971 <&camcc CAMC <<
3972 <&camcc CAMC <<
3973 <&camcc CAMC <<
3974 <&camcc CAMC <<
3975 <&gcc GCC_CA <<
3976 <&gcc GCC_CA <<
3977 clock-names = "camnoc <<
3978 "cpas_a <<
3979 "csiphy <<
3980 "csiphy <<
3981 "csiphy <<
3982 "csiphy <<
3983 "csiphy <<
3984 "csiphy <<
3985 "csiphy <<
3986 "csiphy <<
3987 "vfe0_a <<
3988 "vfe0", <<
3989 "vfe0_c <<
3990 "vfe0_c <<
3991 "vfe1_a <<
3992 "vfe1", <<
3993 "vfe1_c <<
3994 "vfe1_c <<
3995 "vfe2_a <<
3996 "vfe2", <<
3997 "vfe2_c <<
3998 "vfe2_c <<
3999 "vfe3_a <<
4000 "vfe3", <<
4001 "vfe3_c <<
4002 "vfe3_c <<
4003 "vfe_li <<
4004 "vfe_li <<
4005 "vfe_li <<
4006 "vfe_li <<
4007 "vfe_li <<
4008 "vfe_li <<
4009 "vfe_li <<
4010 "vfe_li <<
4011 "vfe_li <<
4012 "vfe_li <<
4013 "vfe_li <<
4014 "vfe_li <<
4015 "gcc_ax <<
4016 "gcc_ax <<
4017 <<
4018 iommus = <&apps_smmu <<
4019 <&apps_smmu <<
4020 <&apps_smmu <<
4021 <&apps_smmu <<
4022 <&apps_smmu <<
4023 <&apps_smmu <<
4024 <&apps_smmu <<
4025 <&apps_smmu <<
4026 <&apps_smmu <<
4027 <&apps_smmu <<
4028 <&apps_smmu <<
4029 <&apps_smmu <<
4030 <&apps_smmu <<
4031 <&apps_smmu <<
4032 <&apps_smmu <<
4033 <&apps_smmu <<
4034 <<
4035 interconnects = <&gem <<
4036 <&mms <<
4037 <&mms <<
4038 <&mms <<
4039 interconnect-names = <<
4040 <<
4041 <<
4042 <<
4043 <<
4044 status = "disabled"; <<
4045 <<
4046 ports { <<
4047 #address-cell <<
4048 #size-cells = <<
4049 <<
4050 port@0 { <<
4051 reg = <<
4052 #addr <<
4053 #size <<
4054 }; <<
4055 <<
4056 port@1 { <<
4057 reg = <<
4058 #addr <<
4059 #size <<
4060 }; <<
4061 <<
4062 port@2 { <<
4063 reg = <<
4064 #addr <<
4065 #size <<
4066 }; <<
4067 <<
4068 port@3 { <<
4069 reg = <<
4070 #addr <<
4071 #size <<
4072 }; <<
4073 }; <<
4074 }; <<
4075 <<
4076 camcc: clock-controller@ad000 3459 camcc: clock-controller@ad00000 {
4077 compatible = "qcom,sc 3460 compatible = "qcom,sc8280xp-camcc";
4078 reg = <0 0x0ad00000 0 3461 reg = <0 0x0ad00000 0 0x20000>;
4079 clocks = <&gcc GCC_CA 3462 clocks = <&gcc GCC_CAMERA_AHB_CLK>,
4080 <&rpmhcc RPM 3463 <&rpmhcc RPMH_CXO_CLK>,
4081 <&rpmhcc RPM 3464 <&rpmhcc RPMH_CXO_CLK_A>,
4082 <&sleep_clk> 3465 <&sleep_clk>;
4083 power-domains = <&rpm 3466 power-domains = <&rpmhpd SC8280XP_MMCX>;
4084 required-opps = <&rpm 3467 required-opps = <&rpmhpd_opp_low_svs>;
4085 #clock-cells = <1>; 3468 #clock-cells = <1>;
4086 #reset-cells = <1>; 3469 #reset-cells = <1>;
4087 #power-domain-cells = 3470 #power-domain-cells = <1>;
4088 }; 3471 };
4089 3472
4090 mdss0: display-subsystem@ae00 3473 mdss0: display-subsystem@ae00000 {
4091 compatible = "qcom,sc 3474 compatible = "qcom,sc8280xp-mdss";
4092 reg = <0 0x0ae00000 0 3475 reg = <0 0x0ae00000 0 0x1000>;
4093 reg-names = "mdss"; 3476 reg-names = "mdss";
4094 3477
4095 clocks = <&gcc GCC_DI 3478 clocks = <&gcc GCC_DISP_AHB_CLK>,
4096 <&dispcc0 DI 3479 <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
4097 <&dispcc0 DI 3480 <&dispcc0 DISP_CC_MDSS_MDP_CLK>;
4098 clock-names = "iface" 3481 clock-names = "iface",
4099 "ahb", 3482 "ahb",
4100 "core"; 3483 "core";
4101 interrupts = <GIC_SPI 3484 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
4102 interconnects = <&mms 3485 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
4103 <&mms 3486 <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>;
4104 interconnect-names = 3487 interconnect-names = "mdp0-mem", "mdp1-mem";
4105 iommus = <&apps_smmu 3488 iommus = <&apps_smmu 0x1000 0x402>;
4106 power-domains = <&dis 3489 power-domains = <&dispcc0 MDSS_GDSC>;
4107 resets = <&dispcc0 DI 3490 resets = <&dispcc0 DISP_CC_MDSS_CORE_BCR>;
4108 3491
4109 interrupt-controller; 3492 interrupt-controller;
4110 #interrupt-cells = <1 3493 #interrupt-cells = <1>;
4111 #address-cells = <2>; 3494 #address-cells = <2>;
4112 #size-cells = <2>; 3495 #size-cells = <2>;
4113 ranges; 3496 ranges;
4114 3497
4115 status = "disabled"; 3498 status = "disabled";
4116 3499
4117 mdss0_mdp: display-co 3500 mdss0_mdp: display-controller@ae01000 {
4118 compatible = 3501 compatible = "qcom,sc8280xp-dpu";
4119 reg = <0 0x0a 3502 reg = <0 0x0ae01000 0 0x8f000>,
4120 <0 0x0a 3503 <0 0x0aeb0000 0 0x2008>;
4121 reg-names = " 3504 reg-names = "mdp", "vbif";
4122 3505
4123 clocks = <&gc 3506 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
4124 <&gc 3507 <&gcc GCC_DISP_SF_AXI_CLK>,
4125 <&di 3508 <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
4126 <&di 3509 <&dispcc0 DISP_CC_MDSS_MDP_LUT_CLK>,
4127 <&di 3510 <&dispcc0 DISP_CC_MDSS_MDP_CLK>,
4128 <&di 3511 <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;
4129 clock-names = 3512 clock-names = "bus",
4130 3513 "nrt_bus",
4131 3514 "iface",
4132 3515 "lut",
4133 3516 "core",
4134 3517 "vsync";
4135 interrupt-par 3518 interrupt-parent = <&mdss0>;
4136 interrupts = 3519 interrupts = <0>;
4137 power-domains 3520 power-domains = <&rpmhpd SC8280XP_MMCX>;
4138 3521
4139 assigned-cloc 3522 assigned-clocks = <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;
4140 assigned-cloc 3523 assigned-clock-rates = <19200000>;
4141 operating-poi 3524 operating-points-v2 = <&mdss0_mdp_opp_table>;
4142 3525
4143 ports { 3526 ports {
4144 #addr 3527 #address-cells = <1>;
4145 #size 3528 #size-cells = <0>;
4146 3529
4147 port@ 3530 port@0 {
4148 3531 reg = <0>;
4149 3532 mdss0_intf0_out: endpoint {
4150 3533 remote-endpoint = <&mdss0_dp0_in>;
4151 3534 };
4152 }; 3535 };
4153 3536
4154 port@ 3537 port@4 {
4155 3538 reg = <4>;
4156 3539 mdss0_intf4_out: endpoint {
4157 3540 remote-endpoint = <&mdss0_dp1_in>;
4158 3541 };
4159 }; 3542 };
4160 3543
4161 port@ 3544 port@5 {
4162 3545 reg = <5>;
4163 3546 mdss0_intf5_out: endpoint {
4164 3547 remote-endpoint = <&mdss0_dp3_in>;
4165 3548 };
4166 }; 3549 };
4167 3550
4168 port@ 3551 port@6 {
4169 3552 reg = <6>;
4170 3553 mdss0_intf6_out: endpoint {
4171 3554 remote-endpoint = <&mdss0_dp2_in>;
4172 3555 };
4173 }; 3556 };
4174 }; 3557 };
4175 3558
4176 mdss0_mdp_opp 3559 mdss0_mdp_opp_table: opp-table {
4177 compa 3560 compatible = "operating-points-v2";
4178 3561
4179 opp-2 3562 opp-200000000 {
4180 3563 opp-hz = /bits/ 64 <200000000>;
4181 3564 required-opps = <&rpmhpd_opp_low_svs>;
4182 }; 3565 };
4183 3566
4184 opp-3 3567 opp-300000000 {
4185 3568 opp-hz = /bits/ 64 <300000000>;
4186 3569 required-opps = <&rpmhpd_opp_svs>;
4187 }; 3570 };
4188 3571
4189 opp-3 3572 opp-375000000 {
4190 3573 opp-hz = /bits/ 64 <375000000>;
4191 3574 required-opps = <&rpmhpd_opp_svs_l1>;
4192 }; 3575 };
4193 3576
4194 opp-5 3577 opp-500000000 {
4195 3578 opp-hz = /bits/ 64 <500000000>;
4196 3579 required-opps = <&rpmhpd_opp_nom>;
4197 }; 3580 };
4198 opp-6 3581 opp-600000000 {
4199 3582 opp-hz = /bits/ 64 <600000000>;
4200 3583 required-opps = <&rpmhpd_opp_turbo_l1>;
4201 }; 3584 };
4202 }; 3585 };
4203 }; 3586 };
4204 3587
4205 mdss0_dp0: displaypor 3588 mdss0_dp0: displayport-controller@ae90000 {
4206 compatible = 3589 compatible = "qcom,sc8280xp-dp";
4207 reg = <0 0xae 3590 reg = <0 0xae90000 0 0x200>,
4208 <0 0xae 3591 <0 0xae90200 0 0x200>,
4209 <0 0xae 3592 <0 0xae90400 0 0x600>,
4210 <0 0xae 3593 <0 0xae91000 0 0x400>,
4211 <0 0xae 3594 <0 0xae91400 0 0x400>;
4212 interrupt-par 3595 interrupt-parent = <&mdss0>;
4213 interrupts = 3596 interrupts = <12>;
4214 clocks = <&di 3597 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
4215 <&di 3598 <&dispcc0 DISP_CC_MDSS_DPTX0_AUX_CLK>,
4216 <&di 3599 <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK>,
4217 <&di 3600 <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
4218 <&di 3601 <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
4219 clock-names = 3602 clock-names = "core_iface", "core_aux",
4220 3603 "ctrl_link",
4221 3604 "ctrl_link_iface",
4222 3605 "stream_pixel";
4223 3606
4224 assigned-cloc 3607 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
4225 3608 <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
4226 assigned-cloc 3609 assigned-clock-parents = <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4227 3610 <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
4228 3611
4229 phys = <&usb_ 3612 phys = <&usb_0_qmpphy QMP_USB43DP_DP_PHY>;
4230 phy-names = " 3613 phy-names = "dp";
4231 3614
4232 #sound-dai-ce 3615 #sound-dai-cells = <0>;
4233 3616
4234 operating-poi 3617 operating-points-v2 = <&mdss0_dp0_opp_table>;
4235 power-domains 3618 power-domains = <&rpmhpd SC8280XP_MMCX>;
4236 3619
4237 status = "dis 3620 status = "disabled";
4238 3621
4239 ports { 3622 ports {
4240 #addr 3623 #address-cells = <1>;
4241 #size 3624 #size-cells = <0>;
4242 3625
4243 port@ 3626 port@0 {
4244 3627 reg = <0>;
4245 3628
4246 3629 mdss0_dp0_in: endpoint {
4247 3630 remote-endpoint = <&mdss0_intf0_out>;
4248 3631 };
4249 }; 3632 };
4250 3633
4251 port@ 3634 port@1 {
4252 3635 reg = <1>;
4253 3636
4254 3637 mdss0_dp0_out: endpoint {
4255 3638 };
4256 }; 3639 };
4257 }; 3640 };
4258 3641
4259 mdss0_dp0_opp 3642 mdss0_dp0_opp_table: opp-table {
4260 compa 3643 compatible = "operating-points-v2";
4261 3644
4262 opp-1 3645 opp-160000000 {
4263 3646 opp-hz = /bits/ 64 <160000000>;
4264 3647 required-opps = <&rpmhpd_opp_low_svs>;
4265 }; 3648 };
4266 3649
4267 opp-2 3650 opp-270000000 {
4268 3651 opp-hz = /bits/ 64 <270000000>;
4269 3652 required-opps = <&rpmhpd_opp_svs>;
4270 }; 3653 };
4271 3654
4272 opp-5 3655 opp-540000000 {
4273 3656 opp-hz = /bits/ 64 <540000000>;
4274 3657 required-opps = <&rpmhpd_opp_svs_l1>;
4275 }; 3658 };
4276 3659
4277 opp-8 3660 opp-810000000 {
4278 3661 opp-hz = /bits/ 64 <810000000>;
4279 3662 required-opps = <&rpmhpd_opp_nom>;
4280 }; 3663 };
4281 }; 3664 };
4282 }; 3665 };
4283 3666
4284 mdss0_dp1: displaypor 3667 mdss0_dp1: displayport-controller@ae98000 {
4285 compatible = 3668 compatible = "qcom,sc8280xp-dp";
4286 reg = <0 0xae 3669 reg = <0 0xae98000 0 0x200>,
4287 <0 0xae 3670 <0 0xae98200 0 0x200>,
4288 <0 0xae 3671 <0 0xae98400 0 0x600>,
4289 <0 0xae 3672 <0 0xae99000 0 0x400>,
4290 <0 0xae 3673 <0 0xae99400 0 0x400>;
4291 interrupt-par 3674 interrupt-parent = <&mdss0>;
4292 interrupts = 3675 interrupts = <13>;
4293 clocks = <&di 3676 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
4294 <&di 3677 <&dispcc0 DISP_CC_MDSS_DPTX1_AUX_CLK>,
4295 <&di 3678 <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK>,
4296 <&di 3679 <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
4297 <&di 3680 <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>;
4298 clock-names = 3681 clock-names = "core_iface", "core_aux",
4299 3682 "ctrl_link",
4300 3683 "ctrl_link_iface", "stream_pixel";
4301 3684
4302 assigned-cloc 3685 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
4303 3686 <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>;
4304 assigned-cloc 3687 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4305 3688 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
4306 3689
4307 phys = <&usb_ 3690 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
4308 phy-names = " 3691 phy-names = "dp";
4309 3692
4310 #sound-dai-ce 3693 #sound-dai-cells = <0>;
4311 3694
4312 operating-poi 3695 operating-points-v2 = <&mdss0_dp1_opp_table>;
4313 power-domains 3696 power-domains = <&rpmhpd SC8280XP_MMCX>;
4314 3697
4315 status = "dis 3698 status = "disabled";
4316 3699
4317 ports { 3700 ports {
4318 #addr 3701 #address-cells = <1>;
4319 #size 3702 #size-cells = <0>;
4320 3703
4321 port@ 3704 port@0 {
4322 3705 reg = <0>;
4323 3706
4324 3707 mdss0_dp1_in: endpoint {
4325 3708 remote-endpoint = <&mdss0_intf4_out>;
4326 3709 };
4327 }; 3710 };
4328 3711
4329 port@ 3712 port@1 {
4330 3713 reg = <1>;
4331 3714
4332 3715 mdss0_dp1_out: endpoint {
4333 3716 };
4334 }; 3717 };
4335 }; 3718 };
4336 3719
4337 mdss0_dp1_opp 3720 mdss0_dp1_opp_table: opp-table {
4338 compa 3721 compatible = "operating-points-v2";
4339 3722
4340 opp-1 3723 opp-160000000 {
4341 3724 opp-hz = /bits/ 64 <160000000>;
4342 3725 required-opps = <&rpmhpd_opp_low_svs>;
4343 }; 3726 };
4344 3727
4345 opp-2 3728 opp-270000000 {
4346 3729 opp-hz = /bits/ 64 <270000000>;
4347 3730 required-opps = <&rpmhpd_opp_svs>;
4348 }; 3731 };
4349 3732
4350 opp-5 3733 opp-540000000 {
4351 3734 opp-hz = /bits/ 64 <540000000>;
4352 3735 required-opps = <&rpmhpd_opp_svs_l1>;
4353 }; 3736 };
4354 3737
4355 opp-8 3738 opp-810000000 {
4356 3739 opp-hz = /bits/ 64 <810000000>;
4357 3740 required-opps = <&rpmhpd_opp_nom>;
4358 }; 3741 };
4359 }; 3742 };
4360 }; 3743 };
4361 3744
4362 mdss0_dp2: displaypor 3745 mdss0_dp2: displayport-controller@ae9a000 {
4363 compatible = 3746 compatible = "qcom,sc8280xp-dp";
4364 reg = <0 0xae 3747 reg = <0 0xae9a000 0 0x200>,
4365 <0 0xae 3748 <0 0xae9a200 0 0x200>,
4366 <0 0xae 3749 <0 0xae9a400 0 0x600>,
4367 <0 0xae 3750 <0 0xae9b000 0 0x400>,
4368 <0 0xae 3751 <0 0xae9b400 0 0x400>;
4369 3752
4370 clocks = <&di 3753 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
4371 <&di 3754 <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>,
4372 <&di 3755 <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK>,
4373 <&di 3756 <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>,
4374 <&di 3757 <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>;
4375 clock-names = 3758 clock-names = "core_iface", "core_aux",
4376 3759 "ctrl_link",
4377 3760 "ctrl_link_iface", "stream_pixel";
4378 interrupt-par 3761 interrupt-parent = <&mdss0>;
4379 interrupts = 3762 interrupts = <14>;
4380 phys = <&mdss 3763 phys = <&mdss0_dp2_phy>;
4381 phy-names = " 3764 phy-names = "dp";
4382 power-domains 3765 power-domains = <&rpmhpd SC8280XP_MMCX>;
4383 3766
4384 assigned-cloc 3767 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
4385 3768 <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>;
4386 assigned-cloc 3769 assigned-clock-parents = <&mdss0_dp2_phy 0>, <&mdss0_dp2_phy 1>;
4387 operating-poi 3770 operating-points-v2 = <&mdss0_dp2_opp_table>;
4388 3771
4389 #sound-dai-ce 3772 #sound-dai-cells = <0>;
4390 3773
4391 status = "dis 3774 status = "disabled";
4392 3775
4393 ports { 3776 ports {
4394 #addr 3777 #address-cells = <1>;
4395 #size 3778 #size-cells = <0>;
4396 3779
4397 port@ 3780 port@0 {
4398 3781 reg = <0>;
4399 3782 mdss0_dp2_in: endpoint {
4400 3783 remote-endpoint = <&mdss0_intf6_out>;
4401 3784 };
4402 }; 3785 };
4403 3786
4404 port@ 3787 port@1 {
4405 3788 reg = <1>;
4406 }; 3789 };
4407 }; 3790 };
4408 3791
4409 mdss0_dp2_opp 3792 mdss0_dp2_opp_table: opp-table {
4410 compa 3793 compatible = "operating-points-v2";
4411 3794
4412 opp-1 3795 opp-160000000 {
4413 3796 opp-hz = /bits/ 64 <160000000>;
4414 3797 required-opps = <&rpmhpd_opp_low_svs>;
4415 }; 3798 };
4416 3799
4417 opp-2 3800 opp-270000000 {
4418 3801 opp-hz = /bits/ 64 <270000000>;
4419 3802 required-opps = <&rpmhpd_opp_svs>;
4420 }; 3803 };
4421 3804
4422 opp-5 3805 opp-540000000 {
4423 3806 opp-hz = /bits/ 64 <540000000>;
4424 3807 required-opps = <&rpmhpd_opp_svs_l1>;
4425 }; 3808 };
4426 3809
4427 opp-8 3810 opp-810000000 {
4428 3811 opp-hz = /bits/ 64 <810000000>;
4429 3812 required-opps = <&rpmhpd_opp_nom>;
4430 }; 3813 };
4431 }; 3814 };
4432 }; 3815 };
4433 3816
4434 mdss0_dp3: displaypor 3817 mdss0_dp3: displayport-controller@aea0000 {
4435 compatible = 3818 compatible = "qcom,sc8280xp-dp";
4436 reg = <0 0xae 3819 reg = <0 0xaea0000 0 0x200>,
4437 <0 0xae 3820 <0 0xaea0200 0 0x200>,
4438 <0 0xae 3821 <0 0xaea0400 0 0x600>,
4439 <0 0xae 3822 <0 0xaea1000 0 0x400>,
4440 <0 0xae 3823 <0 0xaea1400 0 0x400>;
4441 3824
4442 clocks = <&di 3825 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
4443 <&di 3826 <&dispcc0 DISP_CC_MDSS_DPTX3_AUX_CLK>,
4444 <&di 3827 <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_CLK>,
4445 <&di 3828 <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>,
4446 <&di 3829 <&dispcc0 DISP_CC_MDSS_DPTX3_PIXEL0_CLK>;
4447 clock-names = 3830 clock-names = "core_iface", "core_aux",
4448 3831 "ctrl_link",
4449 3832 "ctrl_link_iface", "stream_pixel";
4450 interrupt-par 3833 interrupt-parent = <&mdss0>;
4451 interrupts = 3834 interrupts = <15>;
4452 phys = <&mdss 3835 phys = <&mdss0_dp3_phy>;
4453 phy-names = " 3836 phy-names = "dp";
4454 power-domains 3837 power-domains = <&rpmhpd SC8280XP_MMCX>;
4455 3838
4456 assigned-cloc 3839 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>,
4457 3840 <&dispcc0 DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>;
4458 assigned-cloc 3841 assigned-clock-parents = <&mdss0_dp3_phy 0>, <&mdss0_dp3_phy 1>;
4459 operating-poi 3842 operating-points-v2 = <&mdss0_dp3_opp_table>;
4460 3843
4461 #sound-dai-ce 3844 #sound-dai-cells = <0>;
4462 3845
4463 status = "dis 3846 status = "disabled";
4464 3847
4465 ports { 3848 ports {
4466 #addr 3849 #address-cells = <1>;
4467 #size 3850 #size-cells = <0>;
4468 3851
4469 port@ 3852 port@0 {
4470 3853 reg = <0>;
4471 3854 mdss0_dp3_in: endpoint {
4472 3855 remote-endpoint = <&mdss0_intf5_out>;
4473 3856 };
4474 }; 3857 };
4475 3858
4476 port@ 3859 port@1 {
4477 3860 reg = <1>;
4478 }; 3861 };
4479 }; 3862 };
4480 3863
4481 mdss0_dp3_opp 3864 mdss0_dp3_opp_table: opp-table {
4482 compa 3865 compatible = "operating-points-v2";
4483 3866
4484 opp-1 3867 opp-160000000 {
4485 3868 opp-hz = /bits/ 64 <160000000>;
4486 3869 required-opps = <&rpmhpd_opp_low_svs>;
4487 }; 3870 };
4488 3871
4489 opp-2 3872 opp-270000000 {
4490 3873 opp-hz = /bits/ 64 <270000000>;
4491 3874 required-opps = <&rpmhpd_opp_svs>;
4492 }; 3875 };
4493 3876
4494 opp-5 3877 opp-540000000 {
4495 3878 opp-hz = /bits/ 64 <540000000>;
4496 3879 required-opps = <&rpmhpd_opp_svs_l1>;
4497 }; 3880 };
4498 3881
4499 opp-8 3882 opp-810000000 {
4500 3883 opp-hz = /bits/ 64 <810000000>;
4501 3884 required-opps = <&rpmhpd_opp_nom>;
4502 }; 3885 };
4503 }; 3886 };
4504 }; 3887 };
4505 }; 3888 };
4506 3889
4507 mdss0_dp2_phy: phy@aec2a00 { 3890 mdss0_dp2_phy: phy@aec2a00 {
4508 compatible = "qcom,sc 3891 compatible = "qcom,sc8280xp-dp-phy";
4509 reg = <0 0x0aec2a00 0 3892 reg = <0 0x0aec2a00 0 0x19c>,
4510 <0 0x0aec2200 0 3893 <0 0x0aec2200 0 0xec>,
4511 <0 0x0aec2600 0 3894 <0 0x0aec2600 0 0xec>,
4512 <0 0x0aec2000 0 3895 <0 0x0aec2000 0 0x1c8>;
4513 3896
4514 clocks = <&dispcc0 DI 3897 clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>,
4515 <&dispcc0 DI 3898 <&dispcc0 DISP_CC_MDSS_AHB_CLK>;
4516 clock-names = "aux", 3899 clock-names = "aux", "cfg_ahb";
4517 power-domains = <&rpm 3900 power-domains = <&rpmhpd SC8280XP_MX>;
4518 3901
4519 #clock-cells = <1>; 3902 #clock-cells = <1>;
4520 #phy-cells = <0>; 3903 #phy-cells = <0>;
4521 3904
4522 status = "disabled"; 3905 status = "disabled";
4523 }; 3906 };
4524 3907
4525 mdss0_dp3_phy: phy@aec5a00 { 3908 mdss0_dp3_phy: phy@aec5a00 {
4526 compatible = "qcom,sc 3909 compatible = "qcom,sc8280xp-dp-phy";
4527 reg = <0 0x0aec5a00 0 3910 reg = <0 0x0aec5a00 0 0x19c>,
4528 <0 0x0aec5200 0 3911 <0 0x0aec5200 0 0xec>,
4529 <0 0x0aec5600 0 3912 <0 0x0aec5600 0 0xec>,
4530 <0 0x0aec5000 0 3913 <0 0x0aec5000 0 0x1c8>;
4531 3914
4532 clocks = <&dispcc0 DI 3915 clocks = <&dispcc0 DISP_CC_MDSS_DPTX3_AUX_CLK>,
4533 <&dispcc0 DI 3916 <&dispcc0 DISP_CC_MDSS_AHB_CLK>;
4534 clock-names = "aux", 3917 clock-names = "aux", "cfg_ahb";
4535 power-domains = <&rpm 3918 power-domains = <&rpmhpd SC8280XP_MX>;
4536 3919
4537 #clock-cells = <1>; 3920 #clock-cells = <1>;
4538 #phy-cells = <0>; 3921 #phy-cells = <0>;
4539 3922
4540 status = "disabled"; 3923 status = "disabled";
4541 }; 3924 };
4542 3925
4543 dispcc0: clock-controller@af0 3926 dispcc0: clock-controller@af00000 {
4544 compatible = "qcom,sc 3927 compatible = "qcom,sc8280xp-dispcc0";
4545 reg = <0 0x0af00000 0 3928 reg = <0 0x0af00000 0 0x20000>;
4546 3929
4547 clocks = <&gcc GCC_DI 3930 clocks = <&gcc GCC_DISP_AHB_CLK>,
4548 <&rpmhcc RPM 3931 <&rpmhcc RPMH_CXO_CLK>,
4549 <&sleep_clk> 3932 <&sleep_clk>,
4550 <&usb_0_qmpp 3933 <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4551 <&usb_0_qmpp 3934 <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
4552 <&usb_1_qmpp 3935 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4553 <&usb_1_qmpp 3936 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
4554 <&mdss0_dp2_ 3937 <&mdss0_dp2_phy 0>,
4555 <&mdss0_dp2_ 3938 <&mdss0_dp2_phy 1>,
4556 <&mdss0_dp3_ 3939 <&mdss0_dp3_phy 0>,
4557 <&mdss0_dp3_ 3940 <&mdss0_dp3_phy 1>,
4558 <0>, 3941 <0>,
4559 <0>, 3942 <0>,
4560 <0>, 3943 <0>,
4561 <0>; 3944 <0>;
4562 power-domains = <&rpm 3945 power-domains = <&rpmhpd SC8280XP_MMCX>;
4563 3946
4564 #clock-cells = <1>; 3947 #clock-cells = <1>;
4565 #power-domain-cells = 3948 #power-domain-cells = <1>;
4566 #reset-cells = <1>; 3949 #reset-cells = <1>;
4567 3950
4568 status = "disabled"; 3951 status = "disabled";
4569 }; 3952 };
4570 3953
4571 pdc: interrupt-controller@b22 3954 pdc: interrupt-controller@b220000 {
4572 compatible = "qcom,sc 3955 compatible = "qcom,sc8280xp-pdc", "qcom,pdc";
4573 reg = <0 0x0b220000 0 3956 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
4574 qcom,pdc-ranges = <0 3957 qcom,pdc-ranges = <0 480 40>,
4575 <40 3958 <40 140 14>,
4576 <54 3959 <54 263 1>,
4577 <55 3960 <55 306 4>,
4578 <59 3961 <59 312 3>,
4579 <62 3962 <62 374 2>,
4580 <64 3963 <64 434 2>,
4581 <66 3964 <66 438 3>,
4582 <69 3965 <69 86 1>,
4583 <70 3966 <70 520 54>,
4584 <12 3967 <124 609 28>,
4585 <15 3968 <159 638 1>,
4586 <16 3969 <160 720 8>,
4587 <16 3970 <168 801 1>,
4588 <16 3971 <169 728 30>,
4589 <19 3972 <199 416 2>,
4590 <20 3973 <201 449 1>,
4591 <20 3974 <202 89 1>,
4592 <20 3975 <203 451 1>,
4593 <20 3976 <204 462 1>,
4594 <20 3977 <205 264 1>,
4595 <20 3978 <206 579 1>,
4596 <20 3979 <207 653 1>,
4597 <20 3980 <208 656 1>,
4598 <20 3981 <209 659 1>,
4599 <21 3982 <210 122 1>,
4600 <21 3983 <211 699 1>,
4601 <21 3984 <212 705 1>,
4602 <21 3985 <213 450 1>,
4603 <21 3986 <214 643 1>,
4604 <21 3987 <216 646 5>,
4605 <22 3988 <221 390 5>,
4606 <22 3989 <226 700 3>,
4607 <22 3990 <229 240 3>,
4608 <23 3991 <232 269 1>,
4609 <23 3992 <233 377 1>,
4610 <23 3993 <234 372 1>,
4611 <23 3994 <235 138 1>,
4612 <23 3995 <236 857 1>,
4613 <23 3996 <237 860 1>,
4614 <23 3997 <238 137 1>,
4615 <23 3998 <239 668 1>,
4616 <24 3999 <240 366 1>,
4617 <24 4000 <241 949 1>,
4618 <24 4001 <242 815 5>,
4619 <24 4002 <247 769 1>,
4620 <24 4003 <248 768 1>,
4621 <24 4004 <249 663 1>,
4622 <25 4005 <250 799 2>,
4623 <25 4006 <252 798 1>,
4624 <25 4007 <253 765 1>,
4625 <25 4008 <254 763 1>,
4626 <25 4009 <255 454 1>,
4627 <25 4010 <258 139 1>,
4628 <25 4011 <259 786 2>,
4629 <26 4012 <261 370 2>,
4630 <26 4013 <263 158 2>;
4631 #interrupt-cells = <2 4014 #interrupt-cells = <2>;
4632 interrupt-parent = <& 4015 interrupt-parent = <&intc>;
4633 interrupt-controller; 4016 interrupt-controller;
4634 }; 4017 };
4635 4018
4636 tsens2: thermal-sensor@c25100 <<
4637 compatible = "qcom,sc <<
4638 reg = <0 0x0c251000 0 <<
4639 <0 0x0c224000 0 <<
4640 #qcom,sensors = <11>; <<
4641 interrupts-extended = <<
4642 <<
4643 interrupt-names = "up <<
4644 #thermal-sensor-cells <<
4645 }; <<
4646 <<
4647 tsens3: thermal-sensor@c25200 <<
4648 compatible = "qcom,sc <<
4649 reg = <0 0x0c252000 0 <<
4650 <0 0x0c225000 0 <<
4651 #qcom,sensors = <5>; <<
4652 interrupts-extended = <<
4653 <<
4654 interrupt-names = "up <<
4655 #thermal-sensor-cells <<
4656 }; <<
4657 <<
4658 tsens0: thermal-sensor@c26300 4019 tsens0: thermal-sensor@c263000 {
4659 compatible = "qcom,sc 4020 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2";
4660 reg = <0 0x0c263000 0 4021 reg = <0 0x0c263000 0 0x1ff>, /* TM */
4661 <0 0x0c222000 0 4022 <0 0x0c222000 0 0x8>; /* SROT */
4662 #qcom,sensors = <14>; 4023 #qcom,sensors = <14>;
4663 interrupts-extended = 4024 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
4664 4025 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>;
4665 interrupt-names = "up 4026 interrupt-names = "uplow", "critical";
4666 #thermal-sensor-cells 4027 #thermal-sensor-cells = <1>;
4667 }; 4028 };
4668 4029
4669 restart@c264000 { <<
4670 compatible = "qcom,ps <<
4671 reg = <0 0x0c264000 0 <<
4672 /* TZ seems to block <<
4673 status = "reserved"; <<
4674 }; <<
4675 <<
4676 tsens1: thermal-sensor@c26500 4030 tsens1: thermal-sensor@c265000 {
4677 compatible = "qcom,sc 4031 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2";
4678 reg = <0 0x0c265000 0 4032 reg = <0 0x0c265000 0 0x1ff>, /* TM */
4679 <0 0x0c223000 0 4033 <0 0x0c223000 0 0x8>; /* SROT */
4680 #qcom,sensors = <16>; 4034 #qcom,sensors = <16>;
4681 interrupts-extended = 4035 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
4682 4036 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>;
4683 interrupt-names = "up 4037 interrupt-names = "uplow", "critical";
4684 #thermal-sensor-cells 4038 #thermal-sensor-cells = <1>;
4685 }; 4039 };
4686 4040
4687 aoss_qmp: power-management@c3 4041 aoss_qmp: power-management@c300000 {
4688 compatible = "qcom,sc 4042 compatible = "qcom,sc8280xp-aoss-qmp", "qcom,aoss-qmp";
4689 reg = <0 0x0c300000 0 4043 reg = <0 0x0c300000 0 0x400>;
4690 interrupts-extended = 4044 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>;
4691 mboxes = <&ipcc IPCC_ 4045 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
4692 4046
4693 #clock-cells = <0>; 4047 #clock-cells = <0>;
4694 }; 4048 };
4695 4049
4696 sram@c3f0000 { 4050 sram@c3f0000 {
4697 compatible = "qcom,rp 4051 compatible = "qcom,rpmh-stats";
4698 reg = <0 0x0c3f0000 0 4052 reg = <0 0x0c3f0000 0 0x400>;
4699 qcom,qmp = <&aoss_qmp 4053 qcom,qmp = <&aoss_qmp>;
4700 }; 4054 };
4701 4055
4702 spmi_bus: spmi@c440000 { 4056 spmi_bus: spmi@c440000 {
4703 compatible = "qcom,sp 4057 compatible = "qcom,spmi-pmic-arb";
4704 reg = <0 0x0c440000 0 4058 reg = <0 0x0c440000 0 0x1100>,
4705 <0 0x0c600000 0 4059 <0 0x0c600000 0 0x2000000>,
4706 <0 0x0e600000 0 4060 <0 0x0e600000 0 0x100000>,
4707 <0 0x0e700000 0 4061 <0 0x0e700000 0 0xa0000>,
4708 <0 0x0c40a000 0 4062 <0 0x0c40a000 0 0x26000>;
4709 reg-names = "core", " 4063 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
4710 interrupt-names = "pe 4064 interrupt-names = "periph_irq";
4711 interrupts-extended = 4065 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
4712 qcom,ee = <0>; 4066 qcom,ee = <0>;
4713 qcom,channel = <0>; 4067 qcom,channel = <0>;
4714 #address-cells = <2>; 4068 #address-cells = <2>;
4715 #size-cells = <0>; 4069 #size-cells = <0>;
4716 interrupt-controller; 4070 interrupt-controller;
4717 #interrupt-cells = <4 4071 #interrupt-cells = <4>;
4718 }; 4072 };
4719 4073
4720 tlmm: pinctrl@f100000 { 4074 tlmm: pinctrl@f100000 {
4721 compatible = "qcom,sc 4075 compatible = "qcom,sc8280xp-tlmm";
4722 reg = <0 0x0f100000 0 4076 reg = <0 0x0f100000 0 0x300000>;
4723 interrupts = <GIC_SPI 4077 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
4724 gpio-controller; 4078 gpio-controller;
4725 #gpio-cells = <2>; 4079 #gpio-cells = <2>;
4726 interrupt-controller; 4080 interrupt-controller;
4727 #interrupt-cells = <2 4081 #interrupt-cells = <2>;
4728 gpio-ranges = <&tlmm 4082 gpio-ranges = <&tlmm 0 0 230>;
4729 wakeup-parent = <&pdc 4083 wakeup-parent = <&pdc>;
4730 <<
4731 cci0_default: cci0-de <<
4732 cci0_i2c0_def <<
4733 /* cc <<
4734 pins <<
4735 funct <<
4736 drive <<
4737 bias- <<
4738 }; <<
4739 <<
4740 cci0_i2c1_def <<
4741 /* cc <<
4742 pins <<
4743 funct <<
4744 drive <<
4745 bias- <<
4746 }; <<
4747 }; <<
4748 <<
4749 cci0_sleep: cci0-slee <<
4750 cci0_i2c0_sle <<
4751 /* cc <<
4752 pins <<
4753 funct <<
4754 drive <<
4755 bias- <<
4756 }; <<
4757 <<
4758 cci0_i2c1_sle <<
4759 /* cc <<
4760 pins <<
4761 funct <<
4762 drive <<
4763 bias- <<
4764 }; <<
4765 }; <<
4766 <<
4767 cci1_default: cci1-de <<
4768 cci1_i2c0_def <<
4769 /* cc <<
4770 pins <<
4771 funct <<
4772 drive <<
4773 bias- <<
4774 }; <<
4775 <<
4776 cci1_i2c1_def <<
4777 /* cc <<
4778 pins <<
4779 funct <<
4780 drive <<
4781 bias- <<
4782 }; <<
4783 }; <<
4784 <<
4785 cci1_sleep: cci1-slee <<
4786 cci1_i2c0_sle <<
4787 /* cc <<
4788 pins <<
4789 funct <<
4790 drive <<
4791 bias- <<
4792 }; <<
4793 <<
4794 cci1_i2c1_sle <<
4795 /* cc <<
4796 pins <<
4797 funct <<
4798 drive <<
4799 bias- <<
4800 }; <<
4801 }; <<
4802 <<
4803 cci2_default: cci2-de <<
4804 cci2_i2c0_def <<
4805 /* cc <<
4806 pins <<
4807 funct <<
4808 drive <<
4809 bias- <<
4810 }; <<
4811 <<
4812 cci2_i2c1_def <<
4813 /* cc <<
4814 pins <<
4815 funct <<
4816 drive <<
4817 bias- <<
4818 }; <<
4819 }; <<
4820 <<
4821 cci2_sleep: cci2-slee <<
4822 cci2_i2c0_sle <<
4823 /* cc <<
4824 pins <<
4825 funct <<
4826 drive <<
4827 bias- <<
4828 }; <<
4829 <<
4830 cci2_i2c1_sle <<
4831 /* cc <<
4832 pins <<
4833 funct <<
4834 drive <<
4835 bias- <<
4836 }; <<
4837 }; <<
4838 <<
4839 cci3_default: cci3-de <<
4840 cci3_i2c0_def <<
4841 /* cc <<
4842 pins <<
4843 funct <<
4844 drive <<
4845 bias- <<
4846 }; <<
4847 <<
4848 cci3_i2c1_def <<
4849 /* cc <<
4850 pins <<
4851 funct <<
4852 drive <<
4853 bias- <<
4854 }; <<
4855 }; <<
4856 <<
4857 cci3_sleep: cci3-slee <<
4858 cci3_i2c0_sle <<
4859 /* cc <<
4860 pins <<
4861 funct <<
4862 drive <<
4863 bias- <<
4864 }; <<
4865 <<
4866 cci3_i2c1_sle <<
4867 /* cc <<
4868 pins <<
4869 funct <<
4870 drive <<
4871 bias- <<
4872 }; <<
4873 }; <<
4874 }; 4084 };
4875 4085
4876 apps_smmu: iommu@15000000 { 4086 apps_smmu: iommu@15000000 {
4877 compatible = "qcom,sc 4087 compatible = "qcom,sc8280xp-smmu-500", "arm,mmu-500";
4878 reg = <0 0x15000000 0 4088 reg = <0 0x15000000 0 0x100000>;
4879 #iommu-cells = <2>; 4089 #iommu-cells = <2>;
4880 #global-interrupts = 4090 #global-interrupts = <2>;
4881 interrupts = <GIC_SPI 4091 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
4882 <GIC_SPI 4092 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
4883 <GIC_SPI 4093 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
4884 <GIC_SPI 4094 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
4885 <GIC_SPI 4095 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
4886 <GIC_SPI 4096 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
4887 <GIC_SPI 4097 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
4888 <GIC_SPI 4098 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
4889 <GIC_SPI 4099 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
4890 <GIC_SPI 4100 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
4891 <GIC_SPI 4101 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
4892 <GIC_SPI 4102 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
4893 <GIC_SPI 4103 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
4894 <GIC_SPI 4104 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
4895 <GIC_SPI 4105 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
4896 <GIC_SPI 4106 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
4897 <GIC_SPI 4107 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
4898 <GIC_SPI 4108 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
4899 <GIC_SPI 4109 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
4900 <GIC_SPI 4110 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
4901 <GIC_SPI 4111 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
4902 <GIC_SPI 4112 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
4903 <GIC_SPI 4113 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
4904 <GIC_SPI 4114 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
4905 <GIC_SPI 4115 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
4906 <GIC_SPI 4116 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
4907 <GIC_SPI 4117 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
4908 <GIC_SPI 4118 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
4909 <GIC_SPI 4119 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
4910 <GIC_SPI 4120 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
4911 <GIC_SPI 4121 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
4912 <GIC_SPI 4122 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
4913 <GIC_SPI 4123 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
4914 <GIC_SPI 4124 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
4915 <GIC_SPI 4125 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
4916 <GIC_SPI 4126 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
4917 <GIC_SPI 4127 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
4918 <GIC_SPI 4128 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
4919 <GIC_SPI 4129 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
4920 <GIC_SPI 4130 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
4921 <GIC_SPI 4131 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
4922 <GIC_SPI 4132 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
4923 <GIC_SPI 4133 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
4924 <GIC_SPI 4134 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
4925 <GIC_SPI 4135 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
4926 <GIC_SPI 4136 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
4927 <GIC_SPI 4137 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
4928 <GIC_SPI 4138 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
4929 <GIC_SPI 4139 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
4930 <GIC_SPI 4140 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
4931 <GIC_SPI 4141 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
4932 <GIC_SPI 4142 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
4933 <GIC_SPI 4143 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
4934 <GIC_SPI 4144 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
4935 <GIC_SPI 4145 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
4936 <GIC_SPI 4146 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
4937 <GIC_SPI 4147 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
4938 <GIC_SPI 4148 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
4939 <GIC_SPI 4149 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
4940 <GIC_SPI 4150 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
4941 <GIC_SPI 4151 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
4942 <GIC_SPI 4152 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
4943 <GIC_SPI 4153 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
4944 <GIC_SPI 4154 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
4945 <GIC_SPI 4155 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
4946 <GIC_SPI 4156 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
4947 <GIC_SPI 4157 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
4948 <GIC_SPI 4158 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
4949 <GIC_SPI 4159 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
4950 <GIC_SPI 4160 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
4951 <GIC_SPI 4161 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
4952 <GIC_SPI 4162 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
4953 <GIC_SPI 4163 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
4954 <GIC_SPI 4164 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
4955 <GIC_SPI 4165 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
4956 <GIC_SPI 4166 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
4957 <GIC_SPI 4167 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
4958 <GIC_SPI 4168 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
4959 <GIC_SPI 4169 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
4960 <GIC_SPI 4170 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
4961 <GIC_SPI 4171 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>,
4962 <GIC_SPI 4172 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
4963 <GIC_SPI 4173 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
4964 <GIC_SPI 4174 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
4965 <GIC_SPI 4175 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
4966 <GIC_SPI 4176 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
4967 <GIC_SPI 4177 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
4968 <GIC_SPI 4178 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
4969 <GIC_SPI 4179 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
4970 <GIC_SPI 4180 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
4971 <GIC_SPI 4181 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
4972 <GIC_SPI 4182 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
4973 <GIC_SPI 4183 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
4974 <GIC_SPI 4184 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
4975 <GIC_SPI 4185 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
4976 <GIC_SPI 4186 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
4977 <GIC_SPI 4187 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
4978 <GIC_SPI 4188 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
4979 <GIC_SPI 4189 <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>,
4980 <GIC_SPI 4190 <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>,
4981 <GIC_SPI 4191 <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>,
4982 <GIC_SPI 4192 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
4983 <GIC_SPI 4193 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
4984 <GIC_SPI 4194 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
4985 <GIC_SPI 4195 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>,
4986 <GIC_SPI 4196 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>,
4987 <GIC_SPI 4197 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>,
4988 <GIC_SPI 4198 <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>,
4989 <GIC_SPI 4199 <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>,
4990 <GIC_SPI 4200 <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>,
4991 <GIC_SPI 4201 <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>,
4992 <GIC_SPI 4202 <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>,
4993 <GIC_SPI 4203 <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>,
4994 <GIC_SPI 4204 <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>,
4995 <GIC_SPI 4205 <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>,
4996 <GIC_SPI 4206 <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>,
4997 <GIC_SPI 4207 <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>,
4998 <GIC_SPI 4208 <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>,
4999 <GIC_SPI 4209 <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>,
5000 <GIC_SPI 4210 <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>,
5001 <GIC_SPI 4211 <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>,
5002 <GIC_SPI 4212 <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>,
5003 <GIC_SPI 4213 <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>,
5004 <GIC_SPI 4214 <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>,
5005 <GIC_SPI 4215 <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>,
5006 <GIC_SPI 4216 <GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>,
5007 <GIC_SPI 4217 <GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>,
5008 <GIC_SPI 4218 <GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>,
5009 <GIC_SPI 4219 <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>,
5010 <GIC_SPI 4220 <GIC_SPI 890 IRQ_TYPE_LEVEL_HIGH>;
5011 }; 4221 };
5012 4222
5013 intc: interrupt-controller@17 4223 intc: interrupt-controller@17a00000 {
5014 compatible = "arm,gic 4224 compatible = "arm,gic-v3";
5015 interrupt-controller; 4225 interrupt-controller;
5016 #interrupt-cells = <3 4226 #interrupt-cells = <3>;
5017 reg = <0x0 0x17a00000 4227 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
5018 <0x0 0x17a60000 4228 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
5019 interrupts = <GIC_PPI 4229 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
5020 #redistributor-region 4230 #redistributor-regions = <1>;
5021 redistributor-stride 4231 redistributor-stride = <0 0x20000>;
5022 4232
5023 #address-cells = <2>; 4233 #address-cells = <2>;
5024 #size-cells = <2>; 4234 #size-cells = <2>;
5025 ranges; 4235 ranges;
5026 4236
5027 its: msi-controller@1 !! 4237 msi-controller@17a40000 {
5028 compatible = 4238 compatible = "arm,gic-v3-its";
5029 reg = <0 0x17 4239 reg = <0 0x17a40000 0 0x20000>;
5030 msi-controlle 4240 msi-controller;
5031 #msi-cells = 4241 #msi-cells = <1>;
5032 }; 4242 };
5033 }; 4243 };
5034 4244
5035 watchdog@17c10000 { 4245 watchdog@17c10000 {
5036 compatible = "qcom,ap 4246 compatible = "qcom,apss-wdt-sc8280xp", "qcom,kpss-wdt";
5037 reg = <0 0x17c10000 0 4247 reg = <0 0x17c10000 0 0x1000>;
5038 clocks = <&sleep_clk> 4248 clocks = <&sleep_clk>;
5039 interrupts = <GIC_SPI 4249 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
5040 }; 4250 };
5041 4251
5042 timer@17c20000 { 4252 timer@17c20000 {
5043 compatible = "arm,arm 4253 compatible = "arm,armv7-timer-mem";
5044 reg = <0x0 0x17c20000 4254 reg = <0x0 0x17c20000 0x0 0x1000>;
5045 #address-cells = <1>; 4255 #address-cells = <1>;
5046 #size-cells = <1>; 4256 #size-cells = <1>;
5047 ranges = <0x0 0x0 0x0 4257 ranges = <0x0 0x0 0x0 0x20000000>;
5048 4258
5049 frame@17c21000 { 4259 frame@17c21000 {
5050 frame-number 4260 frame-number = <0>;
5051 interrupts = 4261 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
5052 4262 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
5053 reg = <0x17c2 4263 reg = <0x17c21000 0x1000>,
5054 <0x17c2 4264 <0x17c22000 0x1000>;
5055 }; 4265 };
5056 4266
5057 frame@17c23000 { 4267 frame@17c23000 {
5058 frame-number 4268 frame-number = <1>;
5059 interrupts = 4269 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
5060 reg = <0x17c2 4270 reg = <0x17c23000 0x1000>;
5061 status = "dis 4271 status = "disabled";
5062 }; 4272 };
5063 4273
5064 frame@17c25000 { 4274 frame@17c25000 {
5065 frame-number 4275 frame-number = <2>;
5066 interrupts = 4276 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
5067 reg = <0x17c2 4277 reg = <0x17c25000 0x1000>;
5068 status = "dis 4278 status = "disabled";
5069 }; 4279 };
5070 4280
5071 frame@17c27000 { 4281 frame@17c27000 {
5072 frame-number 4282 frame-number = <3>;
5073 interrupts = 4283 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
5074 reg = <0x17c2 4284 reg = <0x17c26000 0x1000>;
5075 status = "dis 4285 status = "disabled";
5076 }; 4286 };
5077 4287
5078 frame@17c29000 { 4288 frame@17c29000 {
5079 frame-number 4289 frame-number = <4>;
5080 interrupts = 4290 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
5081 reg = <0x17c2 4291 reg = <0x17c29000 0x1000>;
5082 status = "dis 4292 status = "disabled";
5083 }; 4293 };
5084 4294
5085 frame@17c2b000 { 4295 frame@17c2b000 {
5086 frame-number 4296 frame-number = <5>;
5087 interrupts = 4297 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
5088 reg = <0x17c2 4298 reg = <0x17c2b000 0x1000>;
5089 status = "dis 4299 status = "disabled";
5090 }; 4300 };
5091 4301
5092 frame@17c2d000 { 4302 frame@17c2d000 {
5093 frame-number 4303 frame-number = <6>;
5094 interrupts = 4304 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
5095 reg = <0x17c2 4305 reg = <0x17c2d000 0x1000>;
5096 status = "dis 4306 status = "disabled";
5097 }; 4307 };
5098 }; 4308 };
5099 4309
5100 apps_rsc: rsc@18200000 { 4310 apps_rsc: rsc@18200000 {
5101 compatible = "qcom,rp 4311 compatible = "qcom,rpmh-rsc";
5102 reg = <0x0 0x18200000 4312 reg = <0x0 0x18200000 0x0 0x10000>,
5103 <0x0 0x182100 4313 <0x0 0x18210000 0x0 0x10000>,
5104 <0x0 0x182200 4314 <0x0 0x18220000 0x0 0x10000>;
5105 reg-names = "drv-0", 4315 reg-names = "drv-0", "drv-1", "drv-2";
5106 interrupts = <GIC_SPI 4316 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
5107 <GIC_SPI 4317 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
5108 <GIC_SPI 4318 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
5109 qcom,tcs-offset = <0x 4319 qcom,tcs-offset = <0xd00>;
5110 qcom,drv-id = <2>; 4320 qcom,drv-id = <2>;
5111 qcom,tcs-config = <AC 4321 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
5112 <WA 4322 <WAKE_TCS 3>, <CONTROL_TCS 1>;
5113 label = "apps_rsc"; 4323 label = "apps_rsc";
5114 power-domains = <&CLU 4324 power-domains = <&CLUSTER_PD>;
5115 4325
5116 apps_bcm_voter: bcm-v 4326 apps_bcm_voter: bcm-voter {
5117 compatible = 4327 compatible = "qcom,bcm-voter";
5118 }; 4328 };
5119 4329
5120 rpmhcc: clock-control 4330 rpmhcc: clock-controller {
5121 compatible = 4331 compatible = "qcom,sc8280xp-rpmh-clk";
5122 #clock-cells 4332 #clock-cells = <1>;
5123 clock-names = 4333 clock-names = "xo";
5124 clocks = <&xo 4334 clocks = <&xo_board_clk>;
5125 }; 4335 };
5126 4336
5127 rpmhpd: power-control 4337 rpmhpd: power-controller {
5128 compatible = 4338 compatible = "qcom,sc8280xp-rpmhpd";
5129 #power-domain 4339 #power-domain-cells = <1>;
5130 operating-poi 4340 operating-points-v2 = <&rpmhpd_opp_table>;
5131 4341
5132 rpmhpd_opp_ta 4342 rpmhpd_opp_table: opp-table {
5133 compa 4343 compatible = "operating-points-v2";
5134 4344
5135 rpmhp 4345 rpmhpd_opp_ret: opp1 {
5136 4346 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
5137 }; 4347 };
5138 4348
5139 rpmhp 4349 rpmhpd_opp_min_svs: opp2 {
5140 4350 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
5141 }; 4351 };
5142 4352
5143 rpmhp 4353 rpmhpd_opp_low_svs: opp3 {
5144 4354 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
5145 }; 4355 };
5146 4356
5147 rpmhp 4357 rpmhpd_opp_svs: opp4 {
5148 4358 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
5149 }; 4359 };
5150 4360
5151 rpmhp 4361 rpmhpd_opp_svs_l1: opp5 {
5152 4362 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
5153 }; 4363 };
5154 4364
5155 rpmhp 4365 rpmhpd_opp_nom: opp6 {
5156 4366 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
5157 }; 4367 };
5158 4368
5159 rpmhp 4369 rpmhpd_opp_nom_l1: opp7 {
5160 4370 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
5161 }; 4371 };
5162 4372
5163 rpmhp 4373 rpmhpd_opp_nom_l2: opp8 {
5164 4374 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
5165 }; 4375 };
5166 4376
5167 rpmhp 4377 rpmhpd_opp_turbo: opp9 {
5168 4378 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
5169 }; 4379 };
5170 4380
5171 rpmhp 4381 rpmhpd_opp_turbo_l1: opp10 {
5172 4382 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
5173 }; 4383 };
5174 }; 4384 };
5175 }; 4385 };
5176 }; 4386 };
5177 4387
5178 epss_l3: interconnect@1859000 4388 epss_l3: interconnect@18590000 {
5179 compatible = "qcom,sc 4389 compatible = "qcom,sc8280xp-epss-l3", "qcom,epss-l3";
5180 reg = <0 0x18590000 0 4390 reg = <0 0x18590000 0 0x1000>;
5181 4391
5182 clocks = <&rpmhcc RPM 4392 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
5183 clock-names = "xo", " 4393 clock-names = "xo", "alternate";
5184 4394
5185 #interconnect-cells = 4395 #interconnect-cells = <1>;
5186 }; 4396 };
5187 4397
5188 cpufreq_hw: cpufreq@18591000 4398 cpufreq_hw: cpufreq@18591000 {
5189 compatible = "qcom,sc 4399 compatible = "qcom,sc8280xp-cpufreq-epss", "qcom,cpufreq-epss";
5190 reg = <0 0x18591000 0 4400 reg = <0 0x18591000 0 0x1000>,
5191 <0 0x18592000 0 4401 <0 0x18592000 0 0x1000>;
5192 reg-names = "freq-dom 4402 reg-names = "freq-domain0", "freq-domain1";
5193 4403
5194 interrupts = <GIC_SPI <<
5195 <GIC_SPI <<
5196 interrupt-names = "dc <<
5197 "dc <<
5198 <<
5199 clocks = <&rpmhcc RPM 4404 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
5200 clock-names = "xo", " 4405 clock-names = "xo", "alternate";
5201 4406
5202 #freq-domain-cells = 4407 #freq-domain-cells = <1>;
5203 #clock-cells = <1>; 4408 #clock-cells = <1>;
5204 }; 4409 };
5205 4410
5206 remoteproc_nsp0: remoteproc@1 4411 remoteproc_nsp0: remoteproc@1b300000 {
5207 compatible = "qcom,sc 4412 compatible = "qcom,sc8280xp-nsp0-pas";
5208 reg = <0 0x1b300000 0 4413 reg = <0 0x1b300000 0 0x100>;
5209 4414
5210 interrupts-extended = 4415 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
5211 4416 <&smp2p_nsp0_in 0 IRQ_TYPE_EDGE_RISING>,
5212 4417 <&smp2p_nsp0_in 1 IRQ_TYPE_EDGE_RISING>,
5213 4418 <&smp2p_nsp0_in 2 IRQ_TYPE_EDGE_RISING>,
5214 4419 <&smp2p_nsp0_in 3 IRQ_TYPE_EDGE_RISING>;
5215 interrupt-names = "wd 4420 interrupt-names = "wdog", "fatal", "ready",
5216 "ha 4421 "handover", "stop-ack";
5217 4422
5218 clocks = <&rpmhcc RPM 4423 clocks = <&rpmhcc RPMH_CXO_CLK>;
5219 clock-names = "xo"; 4424 clock-names = "xo";
5220 4425
5221 power-domains = <&rpm 4426 power-domains = <&rpmhpd SC8280XP_NSP>;
5222 power-domain-names = 4427 power-domain-names = "nsp";
5223 4428
5224 memory-region = <&pil 4429 memory-region = <&pil_nsp0_mem>;
5225 4430
5226 qcom,smem-states = <& 4431 qcom,smem-states = <&smp2p_nsp0_out 0>;
5227 qcom,smem-state-names 4432 qcom,smem-state-names = "stop";
5228 4433
5229 interconnects = <&nsp 4434 interconnects = <&nspa_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>;
5230 4435
5231 status = "disabled"; 4436 status = "disabled";
5232 4437
5233 glink-edge { 4438 glink-edge {
5234 interrupts-ex 4439 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
5235 4440 IPCC_MPROC_SIGNAL_GLINK_QMP
5236 4441 IRQ_TYPE_EDGE_RISING>;
5237 mboxes = <&ip 4442 mboxes = <&ipcc IPCC_CLIENT_CDSP
5238 4443 IPCC_MPROC_SIGNAL_GLINK_QMP>;
5239 4444
5240 label = "nsp0 4445 label = "nsp0";
5241 qcom,remote-p 4446 qcom,remote-pid = <5>;
5242 4447
5243 fastrpc { 4448 fastrpc {
5244 compa 4449 compatible = "qcom,fastrpc";
5245 qcom, 4450 qcom,glink-channels = "fastrpcglink-apps-dsp";
5246 label 4451 label = "cdsp";
5247 #addr 4452 #address-cells = <1>;
5248 #size 4453 #size-cells = <0>;
5249 4454
5250 compu 4455 compute-cb@1 {
5251 4456 compatible = "qcom,fastrpc-compute-cb";
5252 4457 reg = <1>;
5253 4458 iommus = <&apps_smmu 0x3181 0x0420>;
5254 }; 4459 };
5255 4460
5256 compu 4461 compute-cb@2 {
5257 4462 compatible = "qcom,fastrpc-compute-cb";
5258 4463 reg = <2>;
5259 4464 iommus = <&apps_smmu 0x3182 0x0420>;
5260 }; 4465 };
5261 4466
5262 compu 4467 compute-cb@3 {
5263 4468 compatible = "qcom,fastrpc-compute-cb";
5264 4469 reg = <3>;
5265 4470 iommus = <&apps_smmu 0x3183 0x0420>;
5266 }; 4471 };
5267 4472
5268 compu 4473 compute-cb@4 {
5269 4474 compatible = "qcom,fastrpc-compute-cb";
5270 4475 reg = <4>;
5271 4476 iommus = <&apps_smmu 0x3184 0x0420>;
5272 }; 4477 };
5273 4478
5274 compu 4479 compute-cb@5 {
5275 4480 compatible = "qcom,fastrpc-compute-cb";
5276 4481 reg = <5>;
5277 4482 iommus = <&apps_smmu 0x3185 0x0420>;
5278 }; 4483 };
5279 4484
5280 compu 4485 compute-cb@6 {
5281 4486 compatible = "qcom,fastrpc-compute-cb";
5282 4487 reg = <6>;
5283 4488 iommus = <&apps_smmu 0x3186 0x0420>;
5284 }; 4489 };
5285 4490
5286 compu 4491 compute-cb@7 {
5287 4492 compatible = "qcom,fastrpc-compute-cb";
5288 4493 reg = <7>;
5289 4494 iommus = <&apps_smmu 0x3187 0x0420>;
5290 }; 4495 };
5291 4496
5292 compu 4497 compute-cb@8 {
5293 4498 compatible = "qcom,fastrpc-compute-cb";
5294 4499 reg = <8>;
5295 4500 iommus = <&apps_smmu 0x3188 0x0420>;
5296 }; 4501 };
5297 4502
5298 compu 4503 compute-cb@9 {
5299 4504 compatible = "qcom,fastrpc-compute-cb";
5300 4505 reg = <9>;
5301 4506 iommus = <&apps_smmu 0x318b 0x0420>;
5302 }; 4507 };
5303 4508
5304 compu 4509 compute-cb@10 {
5305 4510 compatible = "qcom,fastrpc-compute-cb";
5306 4511 reg = <10>;
5307 4512 iommus = <&apps_smmu 0x318b 0x0420>;
5308 }; 4513 };
5309 4514
5310 compu 4515 compute-cb@11 {
5311 4516 compatible = "qcom,fastrpc-compute-cb";
5312 4517 reg = <11>;
5313 4518 iommus = <&apps_smmu 0x318c 0x0420>;
5314 }; 4519 };
5315 4520
5316 compu 4521 compute-cb@12 {
5317 4522 compatible = "qcom,fastrpc-compute-cb";
5318 4523 reg = <12>;
5319 4524 iommus = <&apps_smmu 0x318d 0x0420>;
5320 }; 4525 };
5321 4526
5322 compu 4527 compute-cb@13 {
5323 4528 compatible = "qcom,fastrpc-compute-cb";
5324 4529 reg = <13>;
5325 4530 iommus = <&apps_smmu 0x318e 0x0420>;
5326 }; 4531 };
5327 4532
5328 compu 4533 compute-cb@14 {
5329 4534 compatible = "qcom,fastrpc-compute-cb";
5330 4535 reg = <14>;
5331 4536 iommus = <&apps_smmu 0x318f 0x0420>;
5332 }; 4537 };
5333 }; 4538 };
5334 }; 4539 };
5335 }; 4540 };
5336 4541
5337 remoteproc_nsp1: remoteproc@2 4542 remoteproc_nsp1: remoteproc@21300000 {
5338 compatible = "qcom,sc 4543 compatible = "qcom,sc8280xp-nsp1-pas";
5339 reg = <0 0x21300000 0 4544 reg = <0 0x21300000 0 0x100>;
5340 4545
5341 interrupts-extended = 4546 interrupts-extended = <&intc GIC_SPI 887 IRQ_TYPE_EDGE_RISING>,
5342 4547 <&smp2p_nsp1_in 0 IRQ_TYPE_EDGE_RISING>,
5343 4548 <&smp2p_nsp1_in 1 IRQ_TYPE_EDGE_RISING>,
5344 4549 <&smp2p_nsp1_in 2 IRQ_TYPE_EDGE_RISING>,
5345 4550 <&smp2p_nsp1_in 3 IRQ_TYPE_EDGE_RISING>;
5346 interrupt-names = "wd 4551 interrupt-names = "wdog", "fatal", "ready",
5347 "ha 4552 "handover", "stop-ack";
5348 4553
5349 clocks = <&rpmhcc RPM 4554 clocks = <&rpmhcc RPMH_CXO_CLK>;
5350 clock-names = "xo"; 4555 clock-names = "xo";
5351 4556
5352 power-domains = <&rpm 4557 power-domains = <&rpmhpd SC8280XP_NSP>;
5353 power-domain-names = 4558 power-domain-names = "nsp";
5354 4559
5355 memory-region = <&pil 4560 memory-region = <&pil_nsp1_mem>;
5356 4561
5357 qcom,smem-states = <& 4562 qcom,smem-states = <&smp2p_nsp1_out 0>;
5358 qcom,smem-state-names 4563 qcom,smem-state-names = "stop";
5359 4564
5360 interconnects = <&nsp 4565 interconnects = <&nspb_noc MASTER_CDSP_PROC_B 0 &mc_virt SLAVE_EBI1 0>;
5361 4566
5362 status = "disabled"; 4567 status = "disabled";
5363 4568
5364 glink-edge { 4569 glink-edge {
5365 interrupts-ex 4570 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1
5366 4571 IPCC_MPROC_SIGNAL_GLINK_QMP
5367 4572 IRQ_TYPE_EDGE_RISING>;
5368 mboxes = <&ip 4573 mboxes = <&ipcc IPCC_CLIENT_NSP1
5369 4574 IPCC_MPROC_SIGNAL_GLINK_QMP>;
5370 4575
5371 label = "nsp1 4576 label = "nsp1";
5372 qcom,remote-p 4577 qcom,remote-pid = <12>;
5373 }; 4578 };
5374 }; 4579 };
5375 4580
5376 mdss1: display-subsystem@2200 4581 mdss1: display-subsystem@22000000 {
5377 compatible = "qcom,sc 4582 compatible = "qcom,sc8280xp-mdss";
5378 reg = <0 0x22000000 0 4583 reg = <0 0x22000000 0 0x1000>;
5379 reg-names = "mdss"; 4584 reg-names = "mdss";
5380 4585
5381 clocks = <&gcc GCC_DI 4586 clocks = <&gcc GCC_DISP_AHB_CLK>,
5382 <&dispcc1 DI 4587 <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
5383 <&dispcc1 DI 4588 <&dispcc1 DISP_CC_MDSS_MDP_CLK>;
5384 clock-names = "iface" 4589 clock-names = "iface",
5385 "ahb", 4590 "ahb",
5386 "core"; 4591 "core";
5387 interconnects = <&mms 4592 interconnects = <&mmss_noc MASTER_MDP_CORE1_0 0 &mc_virt SLAVE_EBI1 0>,
5388 <&mms 4593 <&mmss_noc MASTER_MDP_CORE1_1 0 &mc_virt SLAVE_EBI1 0>;
5389 interconnect-names = 4594 interconnect-names = "mdp0-mem", "mdp1-mem";
5390 interrupts = <GIC_SPI 4595 interrupts = <GIC_SPI 865 IRQ_TYPE_LEVEL_HIGH>;
5391 4596
5392 iommus = <&apps_smmu 4597 iommus = <&apps_smmu 0x1800 0x402>;
5393 power-domains = <&dis 4598 power-domains = <&dispcc1 MDSS_GDSC>;
5394 resets = <&dispcc1 DI 4599 resets = <&dispcc1 DISP_CC_MDSS_CORE_BCR>;
5395 4600
5396 interrupt-controller; 4601 interrupt-controller;
5397 #interrupt-cells = <1 4602 #interrupt-cells = <1>;
5398 #address-cells = <2>; 4603 #address-cells = <2>;
5399 #size-cells = <2>; 4604 #size-cells = <2>;
5400 ranges; 4605 ranges;
5401 4606
5402 status = "disabled"; 4607 status = "disabled";
5403 4608
5404 mdss1_mdp: display-co 4609 mdss1_mdp: display-controller@22001000 {
5405 compatible = 4610 compatible = "qcom,sc8280xp-dpu";
5406 reg = <0 0x22 4611 reg = <0 0x22001000 0 0x8f000>,
5407 <0 0x22 4612 <0 0x220b0000 0 0x2008>;
5408 reg-names = " 4613 reg-names = "mdp", "vbif";
5409 4614
5410 clocks = <&gc 4615 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
5411 <&gc 4616 <&gcc GCC_DISP_SF_AXI_CLK>,
5412 <&di 4617 <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
5413 <&di 4618 <&dispcc1 DISP_CC_MDSS_MDP_LUT_CLK>,
5414 <&di 4619 <&dispcc1 DISP_CC_MDSS_MDP_CLK>,
5415 <&di 4620 <&dispcc1 DISP_CC_MDSS_VSYNC_CLK>;
5416 clock-names = 4621 clock-names = "bus",
5417 4622 "nrt_bus",
5418 4623 "iface",
5419 4624 "lut",
5420 4625 "core",
5421 4626 "vsync";
5422 interrupt-par 4627 interrupt-parent = <&mdss1>;
5423 interrupts = 4628 interrupts = <0>;
5424 power-domains 4629 power-domains = <&rpmhpd SC8280XP_MMCX>;
5425 4630
5426 assigned-cloc 4631 assigned-clocks = <&dispcc1 DISP_CC_MDSS_VSYNC_CLK>;
5427 assigned-cloc 4632 assigned-clock-rates = <19200000>;
5428 operating-poi 4633 operating-points-v2 = <&mdss1_mdp_opp_table>;
5429 4634
5430 ports { 4635 ports {
5431 #addr 4636 #address-cells = <1>;
5432 #size 4637 #size-cells = <0>;
5433 4638
5434 port@ 4639 port@0 {
5435 4640 reg = <0>;
5436 4641 mdss1_intf0_out: endpoint {
5437 4642 remote-endpoint = <&mdss1_dp0_in>;
5438 4643 };
5439 }; 4644 };
5440 4645
5441 port@ 4646 port@4 {
5442 4647 reg = <4>;
5443 4648 mdss1_intf4_out: endpoint {
5444 4649 remote-endpoint = <&mdss1_dp1_in>;
5445 4650 };
5446 }; 4651 };
5447 4652
5448 port@ 4653 port@5 {
5449 4654 reg = <5>;
5450 4655 mdss1_intf5_out: endpoint {
5451 4656 remote-endpoint = <&mdss1_dp3_in>;
5452 4657 };
5453 }; 4658 };
5454 4659
5455 port@ 4660 port@6 {
5456 4661 reg = <6>;
5457 4662 mdss1_intf6_out: endpoint {
5458 4663 remote-endpoint = <&mdss1_dp2_in>;
5459 4664 };
5460 }; 4665 };
5461 }; 4666 };
5462 4667
5463 mdss1_mdp_opp 4668 mdss1_mdp_opp_table: opp-table {
5464 compa 4669 compatible = "operating-points-v2";
5465 4670
5466 opp-2 4671 opp-200000000 {
5467 4672 opp-hz = /bits/ 64 <200000000>;
5468 4673 required-opps = <&rpmhpd_opp_low_svs>;
5469 }; 4674 };
5470 4675
5471 opp-3 4676 opp-300000000 {
5472 4677 opp-hz = /bits/ 64 <300000000>;
5473 4678 required-opps = <&rpmhpd_opp_svs>;
5474 }; 4679 };
5475 4680
5476 opp-3 4681 opp-375000000 {
5477 4682 opp-hz = /bits/ 64 <375000000>;
5478 4683 required-opps = <&rpmhpd_opp_svs_l1>;
5479 }; 4684 };
5480 4685
5481 opp-5 4686 opp-500000000 {
5482 4687 opp-hz = /bits/ 64 <500000000>;
5483 4688 required-opps = <&rpmhpd_opp_nom>;
5484 }; 4689 };
5485 opp-6 4690 opp-600000000 {
5486 4691 opp-hz = /bits/ 64 <600000000>;
5487 4692 required-opps = <&rpmhpd_opp_turbo_l1>;
5488 }; 4693 };
5489 }; 4694 };
5490 }; 4695 };
5491 4696
5492 mdss1_dp0: displaypor 4697 mdss1_dp0: displayport-controller@22090000 {
5493 compatible = 4698 compatible = "qcom,sc8280xp-dp";
5494 reg = <0 0x22 4699 reg = <0 0x22090000 0 0x200>,
5495 <0 0x22 4700 <0 0x22090200 0 0x200>,
5496 <0 0x22 4701 <0 0x22090400 0 0x600>,
5497 <0 0x22 4702 <0 0x22091000 0 0x400>,
5498 <0 0x22 4703 <0 0x22091400 0 0x400>;
5499 4704
5500 clocks = <&di 4705 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
5501 <&di 4706 <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>,
5502 <&di 4707 <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK>,
5503 <&di 4708 <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
5504 <&di 4709 <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
5505 clock-names = 4710 clock-names = "core_iface", "core_aux",
5506 4711 "ctrl_link",
5507 4712 "ctrl_link_iface", "stream_pixel";
5508 interrupt-par 4713 interrupt-parent = <&mdss1>;
5509 interrupts = 4714 interrupts = <12>;
5510 phys = <&mdss 4715 phys = <&mdss1_dp0_phy>;
5511 phy-names = " 4716 phy-names = "dp";
5512 power-domains 4717 power-domains = <&rpmhpd SC8280XP_MMCX>;
5513 4718
5514 assigned-cloc 4719 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
5515 4720 <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
5516 assigned-cloc 4721 assigned-clock-parents = <&mdss1_dp0_phy 0>, <&mdss1_dp0_phy 1>;
5517 operating-poi 4722 operating-points-v2 = <&mdss1_dp0_opp_table>;
5518 4723
5519 #sound-dai-ce 4724 #sound-dai-cells = <0>;
5520 4725
5521 status = "dis 4726 status = "disabled";
5522 4727
5523 ports { 4728 ports {
5524 #addr 4729 #address-cells = <1>;
5525 #size 4730 #size-cells = <0>;
5526 4731
5527 port@ 4732 port@0 {
5528 4733 reg = <0>;
5529 4734 mdss1_dp0_in: endpoint {
5530 4735 remote-endpoint = <&mdss1_intf0_out>;
5531 4736 };
5532 }; 4737 };
5533 4738
5534 port@ 4739 port@1 {
5535 4740 reg = <1>;
5536 }; 4741 };
5537 }; 4742 };
5538 4743
5539 mdss1_dp0_opp 4744 mdss1_dp0_opp_table: opp-table {
5540 compa 4745 compatible = "operating-points-v2";
5541 4746
5542 opp-1 4747 opp-160000000 {
5543 4748 opp-hz = /bits/ 64 <160000000>;
5544 4749 required-opps = <&rpmhpd_opp_low_svs>;
5545 }; 4750 };
5546 4751
5547 opp-2 4752 opp-270000000 {
5548 4753 opp-hz = /bits/ 64 <270000000>;
5549 4754 required-opps = <&rpmhpd_opp_svs>;
5550 }; 4755 };
5551 4756
5552 opp-5 4757 opp-540000000 {
5553 4758 opp-hz = /bits/ 64 <540000000>;
5554 4759 required-opps = <&rpmhpd_opp_svs_l1>;
5555 }; 4760 };
5556 4761
5557 opp-8 4762 opp-810000000 {
5558 4763 opp-hz = /bits/ 64 <810000000>;
5559 4764 required-opps = <&rpmhpd_opp_nom>;
5560 }; 4765 };
5561 }; 4766 };
5562 }; 4767 };
5563 4768
5564 mdss1_dp1: displaypor 4769 mdss1_dp1: displayport-controller@22098000 {
5565 compatible = 4770 compatible = "qcom,sc8280xp-dp";
5566 reg = <0 0x22 4771 reg = <0 0x22098000 0 0x200>,
5567 <0 0x22 4772 <0 0x22098200 0 0x200>,
5568 <0 0x22 4773 <0 0x22098400 0 0x600>,
5569 <0 0x22 4774 <0 0x22099000 0 0x400>,
5570 <0 0x22 4775 <0 0x22099400 0 0x400>;
5571 4776
5572 clocks = <&di 4777 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
5573 <&di 4778 <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>,
5574 <&di 4779 <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK>,
5575 <&di 4780 <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
5576 <&di 4781 <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>;
5577 clock-names = 4782 clock-names = "core_iface", "core_aux",
5578 4783 "ctrl_link",
5579 4784 "ctrl_link_iface", "stream_pixel";
5580 interrupt-par 4785 interrupt-parent = <&mdss1>;
5581 interrupts = 4786 interrupts = <13>;
5582 phys = <&mdss 4787 phys = <&mdss1_dp1_phy>;
5583 phy-names = " 4788 phy-names = "dp";
5584 power-domains 4789 power-domains = <&rpmhpd SC8280XP_MMCX>;
5585 4790
5586 assigned-cloc 4791 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
5587 4792 <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>;
5588 assigned-cloc 4793 assigned-clock-parents = <&mdss1_dp1_phy 0>, <&mdss1_dp1_phy 1>;
5589 operating-poi 4794 operating-points-v2 = <&mdss1_dp1_opp_table>;
5590 4795
5591 #sound-dai-ce 4796 #sound-dai-cells = <0>;
5592 4797
5593 status = "dis 4798 status = "disabled";
5594 4799
5595 ports { 4800 ports {
5596 #addr 4801 #address-cells = <1>;
5597 #size 4802 #size-cells = <0>;
5598 4803
5599 port@ 4804 port@0 {
5600 4805 reg = <0>;
5601 4806 mdss1_dp1_in: endpoint {
5602 4807 remote-endpoint = <&mdss1_intf4_out>;
5603 4808 };
5604 }; 4809 };
5605 4810
5606 port@ 4811 port@1 {
5607 4812 reg = <1>;
5608 }; 4813 };
5609 }; 4814 };
5610 4815
5611 mdss1_dp1_opp 4816 mdss1_dp1_opp_table: opp-table {
5612 compa 4817 compatible = "operating-points-v2";
5613 4818
5614 opp-1 4819 opp-160000000 {
5615 4820 opp-hz = /bits/ 64 <160000000>;
5616 4821 required-opps = <&rpmhpd_opp_low_svs>;
5617 }; 4822 };
5618 4823
5619 opp-2 4824 opp-270000000 {
5620 4825 opp-hz = /bits/ 64 <270000000>;
5621 4826 required-opps = <&rpmhpd_opp_svs>;
5622 }; 4827 };
5623 4828
5624 opp-5 4829 opp-540000000 {
5625 4830 opp-hz = /bits/ 64 <540000000>;
5626 4831 required-opps = <&rpmhpd_opp_svs_l1>;
5627 }; 4832 };
5628 4833
5629 opp-8 4834 opp-810000000 {
5630 4835 opp-hz = /bits/ 64 <810000000>;
5631 4836 required-opps = <&rpmhpd_opp_nom>;
5632 }; 4837 };
5633 }; 4838 };
5634 }; 4839 };
5635 4840
5636 mdss1_dp2: displaypor 4841 mdss1_dp2: displayport-controller@2209a000 {
5637 compatible = 4842 compatible = "qcom,sc8280xp-dp";
5638 reg = <0 0x22 4843 reg = <0 0x2209a000 0 0x200>,
5639 <0 0x22 4844 <0 0x2209a200 0 0x200>,
5640 <0 0x22 4845 <0 0x2209a400 0 0x600>,
5641 <0 0x22 4846 <0 0x2209b000 0 0x400>,
5642 <0 0x22 4847 <0 0x2209b400 0 0x400>;
5643 4848
5644 clocks = <&di 4849 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
5645 <&di 4850 <&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>,
5646 <&di 4851 <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK>,
5647 <&di 4852 <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>,
5648 <&di 4853 <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>;
5649 clock-names = 4854 clock-names = "core_iface", "core_aux",
5650 4855 "ctrl_link",
5651 4856 "ctrl_link_iface", "stream_pixel";
5652 interrupt-par 4857 interrupt-parent = <&mdss1>;
5653 interrupts = 4858 interrupts = <14>;
5654 phys = <&mdss 4859 phys = <&mdss1_dp2_phy>;
5655 phy-names = " 4860 phy-names = "dp";
5656 power-domains 4861 power-domains = <&rpmhpd SC8280XP_MMCX>;
5657 4862
5658 assigned-cloc 4863 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
5659 4864 <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>;
5660 assigned-cloc 4865 assigned-clock-parents = <&mdss1_dp2_phy 0>, <&mdss1_dp2_phy 1>;
5661 operating-poi 4866 operating-points-v2 = <&mdss1_dp2_opp_table>;
5662 4867
5663 #sound-dai-ce 4868 #sound-dai-cells = <0>;
5664 4869
5665 status = "dis 4870 status = "disabled";
5666 4871
5667 ports { 4872 ports {
5668 #addr 4873 #address-cells = <1>;
5669 #size 4874 #size-cells = <0>;
5670 4875
5671 port@ 4876 port@0 {
5672 4877 reg = <0>;
5673 4878 mdss1_dp2_in: endpoint {
5674 4879 remote-endpoint = <&mdss1_intf6_out>;
5675 4880 };
5676 }; 4881 };
5677 4882
5678 port@ 4883 port@1 {
5679 4884 reg = <1>;
5680 }; 4885 };
5681 }; 4886 };
5682 4887
5683 mdss1_dp2_opp 4888 mdss1_dp2_opp_table: opp-table {
5684 compa 4889 compatible = "operating-points-v2";
5685 4890
5686 opp-1 4891 opp-160000000 {
5687 4892 opp-hz = /bits/ 64 <160000000>;
5688 4893 required-opps = <&rpmhpd_opp_low_svs>;
5689 }; 4894 };
5690 4895
5691 opp-2 4896 opp-270000000 {
5692 4897 opp-hz = /bits/ 64 <270000000>;
5693 4898 required-opps = <&rpmhpd_opp_svs>;
5694 }; 4899 };
5695 4900
5696 opp-5 4901 opp-540000000 {
5697 4902 opp-hz = /bits/ 64 <540000000>;
5698 4903 required-opps = <&rpmhpd_opp_svs_l1>;
5699 }; 4904 };
5700 4905
5701 opp-8 4906 opp-810000000 {
5702 4907 opp-hz = /bits/ 64 <810000000>;
5703 4908 required-opps = <&rpmhpd_opp_nom>;
5704 }; 4909 };
5705 }; 4910 };
5706 }; 4911 };
5707 4912
5708 mdss1_dp3: displaypor 4913 mdss1_dp3: displayport-controller@220a0000 {
5709 compatible = 4914 compatible = "qcom,sc8280xp-dp";
5710 reg = <0 0x22 4915 reg = <0 0x220a0000 0 0x200>,
5711 <0 0x22 4916 <0 0x220a0200 0 0x200>,
5712 <0 0x22 4917 <0 0x220a0400 0 0x600>,
5713 <0 0x22 4918 <0 0x220a1000 0 0x400>,
5714 <0 0x22 4919 <0 0x220a1400 0 0x400>;
5715 4920
5716 clocks = <&di 4921 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
5717 <&di 4922 <&dispcc1 DISP_CC_MDSS_DPTX3_AUX_CLK>,
5718 <&di 4923 <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_CLK>,
5719 <&di 4924 <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>,
5720 <&di 4925 <&dispcc1 DISP_CC_MDSS_DPTX3_PIXEL0_CLK>;
5721 clock-names = 4926 clock-names = "core_iface", "core_aux",
5722 4927 "ctrl_link",
5723 4928 "ctrl_link_iface", "stream_pixel";
5724 interrupt-par 4929 interrupt-parent = <&mdss1>;
5725 interrupts = 4930 interrupts = <15>;
5726 phys = <&mdss 4931 phys = <&mdss1_dp3_phy>;
5727 phy-names = " 4932 phy-names = "dp";
5728 power-domains 4933 power-domains = <&rpmhpd SC8280XP_MMCX>;
5729 4934
5730 assigned-cloc 4935 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>,
5731 4936 <&dispcc1 DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>;
5732 assigned-cloc 4937 assigned-clock-parents = <&mdss1_dp3_phy 0>, <&mdss1_dp3_phy 1>;
5733 operating-poi 4938 operating-points-v2 = <&mdss1_dp3_opp_table>;
5734 4939
5735 #sound-dai-ce 4940 #sound-dai-cells = <0>;
5736 4941
5737 status = "dis 4942 status = "disabled";
5738 4943
5739 ports { 4944 ports {
5740 #addr 4945 #address-cells = <1>;
5741 #size 4946 #size-cells = <0>;
5742 4947
5743 port@ 4948 port@0 {
5744 4949 reg = <0>;
5745 4950 mdss1_dp3_in: endpoint {
5746 4951 remote-endpoint = <&mdss1_intf5_out>;
5747 4952 };
5748 }; 4953 };
5749 4954
5750 port@ 4955 port@1 {
5751 4956 reg = <1>;
5752 }; 4957 };
5753 }; 4958 };
5754 4959
5755 mdss1_dp3_opp 4960 mdss1_dp3_opp_table: opp-table {
5756 compa 4961 compatible = "operating-points-v2";
5757 4962
5758 opp-1 4963 opp-160000000 {
5759 4964 opp-hz = /bits/ 64 <160000000>;
5760 4965 required-opps = <&rpmhpd_opp_low_svs>;
5761 }; 4966 };
5762 4967
5763 opp-2 4968 opp-270000000 {
5764 4969 opp-hz = /bits/ 64 <270000000>;
5765 4970 required-opps = <&rpmhpd_opp_svs>;
5766 }; 4971 };
5767 4972
5768 opp-5 4973 opp-540000000 {
5769 4974 opp-hz = /bits/ 64 <540000000>;
5770 4975 required-opps = <&rpmhpd_opp_svs_l1>;
5771 }; 4976 };
5772 4977
5773 opp-8 4978 opp-810000000 {
5774 4979 opp-hz = /bits/ 64 <810000000>;
5775 4980 required-opps = <&rpmhpd_opp_nom>;
5776 }; 4981 };
5777 }; 4982 };
5778 }; 4983 };
5779 }; 4984 };
5780 4985
5781 mdss1_dp2_phy: phy@220c2a00 { 4986 mdss1_dp2_phy: phy@220c2a00 {
5782 compatible = "qcom,sc 4987 compatible = "qcom,sc8280xp-dp-phy";
5783 reg = <0 0x220c2a00 0 4988 reg = <0 0x220c2a00 0 0x19c>,
5784 <0 0x220c2200 0 4989 <0 0x220c2200 0 0xec>,
5785 <0 0x220c2600 0 4990 <0 0x220c2600 0 0xec>,
5786 <0 0x220c2000 0 4991 <0 0x220c2000 0 0x1c8>;
5787 4992
5788 clocks = <&dispcc1 DI 4993 clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>,
5789 <&dispcc1 DI 4994 <&dispcc1 DISP_CC_MDSS_AHB_CLK>;
5790 clock-names = "aux", 4995 clock-names = "aux", "cfg_ahb";
5791 power-domains = <&rpm 4996 power-domains = <&rpmhpd SC8280XP_MX>;
5792 4997
5793 #clock-cells = <1>; 4998 #clock-cells = <1>;
5794 #phy-cells = <0>; 4999 #phy-cells = <0>;
5795 5000
5796 status = "disabled"; 5001 status = "disabled";
5797 }; 5002 };
5798 5003
5799 mdss1_dp3_phy: phy@220c5a00 { 5004 mdss1_dp3_phy: phy@220c5a00 {
5800 compatible = "qcom,sc 5005 compatible = "qcom,sc8280xp-dp-phy";
5801 reg = <0 0x220c5a00 0 5006 reg = <0 0x220c5a00 0 0x19c>,
5802 <0 0x220c5200 0 5007 <0 0x220c5200 0 0xec>,
5803 <0 0x220c5600 0 5008 <0 0x220c5600 0 0xec>,
5804 <0 0x220c5000 0 5009 <0 0x220c5000 0 0x1c8>;
5805 5010
5806 clocks = <&dispcc1 DI 5011 clocks = <&dispcc1 DISP_CC_MDSS_DPTX3_AUX_CLK>,
5807 <&dispcc1 DI 5012 <&dispcc1 DISP_CC_MDSS_AHB_CLK>;
5808 clock-names = "aux", 5013 clock-names = "aux", "cfg_ahb";
5809 power-domains = <&rpm 5014 power-domains = <&rpmhpd SC8280XP_MX>;
5810 5015
5811 #clock-cells = <1>; 5016 #clock-cells = <1>;
5812 #phy-cells = <0>; 5017 #phy-cells = <0>;
5813 5018
5814 status = "disabled"; 5019 status = "disabled";
5815 }; 5020 };
5816 5021
5817 dispcc1: clock-controller@221 5022 dispcc1: clock-controller@22100000 {
5818 compatible = "qcom,sc 5023 compatible = "qcom,sc8280xp-dispcc1";
5819 reg = <0 0x22100000 0 5024 reg = <0 0x22100000 0 0x20000>;
5820 5025
5821 clocks = <&gcc GCC_DI 5026 clocks = <&gcc GCC_DISP_AHB_CLK>,
5822 <&rpmhcc RPM 5027 <&rpmhcc RPMH_CXO_CLK>,
5823 <0>, 5028 <0>,
5824 <&mdss1_dp0_ 5029 <&mdss1_dp0_phy 0>,
5825 <&mdss1_dp0_ 5030 <&mdss1_dp0_phy 1>,
5826 <&mdss1_dp1_ 5031 <&mdss1_dp1_phy 0>,
5827 <&mdss1_dp1_ 5032 <&mdss1_dp1_phy 1>,
5828 <&mdss1_dp2_ 5033 <&mdss1_dp2_phy 0>,
5829 <&mdss1_dp2_ 5034 <&mdss1_dp2_phy 1>,
5830 <&mdss1_dp3_ 5035 <&mdss1_dp3_phy 0>,
5831 <&mdss1_dp3_ 5036 <&mdss1_dp3_phy 1>,
5832 <0>, 5037 <0>,
5833 <0>, 5038 <0>,
5834 <0>, 5039 <0>,
5835 <0>; 5040 <0>;
5836 power-domains = <&rpm 5041 power-domains = <&rpmhpd SC8280XP_MMCX>;
5837 5042
5838 #clock-cells = <1>; 5043 #clock-cells = <1>;
5839 #power-domain-cells = 5044 #power-domain-cells = <1>;
5840 #reset-cells = <1>; 5045 #reset-cells = <1>;
5841 5046
5842 status = "disabled"; 5047 status = "disabled";
5843 }; 5048 };
5844 5049
5845 ethernet1: ethernet@23000000 5050 ethernet1: ethernet@23000000 {
5846 compatible = "qcom,sc 5051 compatible = "qcom,sc8280xp-ethqos";
5847 reg = <0x0 0x23000000 5052 reg = <0x0 0x23000000 0x0 0x10000>,
5848 <0x0 0x23016000 5053 <0x0 0x23016000 0x0 0x100>;
5849 reg-names = "stmmacet 5054 reg-names = "stmmaceth", "rgmii";
5850 5055
5851 clocks = <&gcc GCC_EM 5056 clocks = <&gcc GCC_EMAC1_AXI_CLK>,
5852 <&gcc GCC_EM 5057 <&gcc GCC_EMAC1_SLV_AHB_CLK>,
5853 <&gcc GCC_EM 5058 <&gcc GCC_EMAC1_PTP_CLK>,
5854 <&gcc GCC_EM 5059 <&gcc GCC_EMAC1_RGMII_CLK>;
5855 clock-names = "stmmac 5060 clock-names = "stmmaceth",
5856 "pclk", 5061 "pclk",
5857 "ptp_re 5062 "ptp_ref",
5858 "rgmii" 5063 "rgmii";
5859 5064
5860 interrupts = <GIC_SPI 5065 interrupts = <GIC_SPI 929 IRQ_TYPE_LEVEL_HIGH>,
5861 <GIC_SPI 5066 <GIC_SPI 919 IRQ_TYPE_LEVEL_HIGH>;
5862 interrupt-names = "ma 5067 interrupt-names = "macirq", "eth_lpi";
5863 5068
5864 iommus = <&apps_smmu 5069 iommus = <&apps_smmu 0x40 0xf>;
5865 power-domains = <&gcc 5070 power-domains = <&gcc EMAC_1_GDSC>;
5866 5071
5867 snps,tso; 5072 snps,tso;
5868 snps,pbl = <32>; 5073 snps,pbl = <32>;
5869 rx-fifo-depth = <4096 5074 rx-fifo-depth = <4096>;
5870 tx-fifo-depth = <4096 5075 tx-fifo-depth = <4096>;
5871 5076
5872 status = "disabled"; 5077 status = "disabled";
5873 }; 5078 };
5874 }; 5079 };
5875 5080
5876 sound: sound { 5081 sound: sound {
5877 }; 5082 };
5878 5083
5879 thermal-zones { 5084 thermal-zones {
5880 cpu0-thermal { 5085 cpu0-thermal {
5881 polling-delay-passive 5086 polling-delay-passive = <250>;
>> 5087 polling-delay = <1000>;
5882 5088
5883 thermal-sensors = <&t 5089 thermal-sensors = <&tsens0 1>;
5884 5090
5885 trips { 5091 trips {
5886 cpu-crit { 5092 cpu-crit {
5887 tempe 5093 temperature = <110000>;
5888 hyste 5094 hysteresis = <1000>;
5889 type 5095 type = "critical";
5890 }; 5096 };
5891 }; 5097 };
5892 }; 5098 };
5893 5099
5894 cpu1-thermal { 5100 cpu1-thermal {
5895 polling-delay-passive 5101 polling-delay-passive = <250>;
>> 5102 polling-delay = <1000>;
5896 5103
5897 thermal-sensors = <&t 5104 thermal-sensors = <&tsens0 2>;
5898 5105
5899 trips { 5106 trips {
5900 cpu-crit { 5107 cpu-crit {
5901 tempe 5108 temperature = <110000>;
5902 hyste 5109 hysteresis = <1000>;
5903 type 5110 type = "critical";
5904 }; 5111 };
5905 }; 5112 };
5906 }; 5113 };
5907 5114
5908 cpu2-thermal { 5115 cpu2-thermal {
5909 polling-delay-passive 5116 polling-delay-passive = <250>;
>> 5117 polling-delay = <1000>;
5910 5118
5911 thermal-sensors = <&t 5119 thermal-sensors = <&tsens0 3>;
5912 5120
5913 trips { 5121 trips {
5914 cpu-crit { 5122 cpu-crit {
5915 tempe 5123 temperature = <110000>;
5916 hyste 5124 hysteresis = <1000>;
5917 type 5125 type = "critical";
5918 }; 5126 };
5919 }; 5127 };
5920 }; 5128 };
5921 5129
5922 cpu3-thermal { 5130 cpu3-thermal {
5923 polling-delay-passive 5131 polling-delay-passive = <250>;
>> 5132 polling-delay = <1000>;
5924 5133
5925 thermal-sensors = <&t 5134 thermal-sensors = <&tsens0 4>;
5926 5135
5927 trips { 5136 trips {
5928 cpu-crit { 5137 cpu-crit {
5929 tempe 5138 temperature = <110000>;
5930 hyste 5139 hysteresis = <1000>;
5931 type 5140 type = "critical";
5932 }; 5141 };
5933 }; 5142 };
5934 }; 5143 };
5935 5144
5936 cpu4-thermal { 5145 cpu4-thermal {
5937 polling-delay-passive 5146 polling-delay-passive = <250>;
>> 5147 polling-delay = <1000>;
5938 5148
5939 thermal-sensors = <&t 5149 thermal-sensors = <&tsens0 5>;
5940 5150
5941 trips { 5151 trips {
5942 cpu-crit { 5152 cpu-crit {
5943 tempe 5153 temperature = <110000>;
5944 hyste 5154 hysteresis = <1000>;
5945 type 5155 type = "critical";
5946 }; 5156 };
5947 }; 5157 };
5948 }; 5158 };
5949 5159
5950 cpu5-thermal { 5160 cpu5-thermal {
5951 polling-delay-passive 5161 polling-delay-passive = <250>;
>> 5162 polling-delay = <1000>;
5952 5163
5953 thermal-sensors = <&t 5164 thermal-sensors = <&tsens0 6>;
5954 5165
5955 trips { 5166 trips {
5956 cpu-crit { 5167 cpu-crit {
5957 tempe 5168 temperature = <110000>;
5958 hyste 5169 hysteresis = <1000>;
5959 type 5170 type = "critical";
5960 }; 5171 };
5961 }; 5172 };
5962 }; 5173 };
5963 5174
5964 cpu6-thermal { 5175 cpu6-thermal {
5965 polling-delay-passive 5176 polling-delay-passive = <250>;
>> 5177 polling-delay = <1000>;
5966 5178
5967 thermal-sensors = <&t 5179 thermal-sensors = <&tsens0 7>;
5968 5180
5969 trips { 5181 trips {
5970 cpu-crit { 5182 cpu-crit {
5971 tempe 5183 temperature = <110000>;
5972 hyste 5184 hysteresis = <1000>;
5973 type 5185 type = "critical";
5974 }; 5186 };
5975 }; 5187 };
5976 }; 5188 };
5977 5189
5978 cpu7-thermal { 5190 cpu7-thermal {
5979 polling-delay-passive 5191 polling-delay-passive = <250>;
>> 5192 polling-delay = <1000>;
5980 5193
5981 thermal-sensors = <&t 5194 thermal-sensors = <&tsens0 8>;
5982 5195
5983 trips { 5196 trips {
5984 cpu-crit { 5197 cpu-crit {
5985 tempe 5198 temperature = <110000>;
5986 hyste 5199 hysteresis = <1000>;
5987 type 5200 type = "critical";
5988 }; 5201 };
5989 }; 5202 };
5990 }; 5203 };
5991 5204
5992 cluster0-thermal { 5205 cluster0-thermal {
5993 polling-delay-passive 5206 polling-delay-passive = <250>;
>> 5207 polling-delay = <1000>;
5994 5208
5995 thermal-sensors = <&t 5209 thermal-sensors = <&tsens0 9>;
5996 5210
5997 trips { 5211 trips {
5998 cpu-crit { 5212 cpu-crit {
5999 tempe 5213 temperature = <110000>;
6000 hyste 5214 hysteresis = <1000>;
6001 type 5215 type = "critical";
6002 }; 5216 };
6003 }; 5217 };
6004 }; 5218 };
6005 5219
6006 gpu-thermal { <<
6007 polling-delay-passive <<
6008 <<
6009 thermal-sensors = <&t <<
6010 <<
6011 cooling-maps { <<
6012 map0 { <<
6013 trip <<
6014 cooli <<
6015 }; <<
6016 }; <<
6017 <<
6018 trips { <<
6019 gpu_alert0: t <<
6020 tempe <<
6021 hyste <<
6022 type <<
6023 }; <<
6024 <<
6025 trip-point1 { <<
6026 tempe <<
6027 hyste <<
6028 type <<
6029 }; <<
6030 }; <<
6031 }; <<
6032 <<
6033 mem-thermal { 5220 mem-thermal {
6034 polling-delay-passive 5221 polling-delay-passive = <250>;
>> 5222 polling-delay = <1000>;
6035 5223
6036 thermal-sensors = <&t 5224 thermal-sensors = <&tsens1 15>;
6037 5225
6038 trips { 5226 trips {
6039 trip-point0 { 5227 trip-point0 {
6040 tempe 5228 temperature = <90000>;
6041 hyste 5229 hysteresis = <2000>;
6042 type 5230 type = "hot";
6043 }; 5231 };
6044 }; 5232 };
6045 }; 5233 };
6046 }; 5234 };
6047 5235
6048 timer { 5236 timer {
6049 compatible = "arm,armv8-timer 5237 compatible = "arm,armv8-timer";
6050 interrupts = <GIC_PPI 13 (GIC 5238 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
6051 <GIC_PPI 14 (GIC 5239 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
6052 <GIC_PPI 11 (GIC 5240 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
6053 <GIC_PPI 10 (GIC 5241 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
6054 }; 5242 };
6055 }; 5243 };
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