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Linux/scripts/dtc/include-prefixes/arm64/qcom/sc8280xp.dtsi

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Diff markup

Differences between /scripts/dtc/include-prefixes/arm64/qcom/sc8280xp.dtsi (Architecture i386) and /scripts/dtc/include-prefixes/arm64/qcom/sc8280xp.dtsi (Architecture mips)


  1 // SPDX-License-Identifier: BSD-3-Clause            1 // SPDX-License-Identifier: BSD-3-Clause
  2 /*                                                  2 /*
  3  * Copyright (c) 2021, The Linux Foundation. A      3  * Copyright (c) 2021, The Linux Foundation. All rights reserved.
  4  * Copyright (c) 2022, Linaro Limited               4  * Copyright (c) 2022, Linaro Limited
  5  */                                                 5  */
  6                                                     6 
  7 #include <dt-bindings/clock/qcom,dispcc-sc8280      7 #include <dt-bindings/clock/qcom,dispcc-sc8280xp.h>
  8 #include <dt-bindings/clock/qcom,gcc-sc8280xp.      8 #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
  9 #include <dt-bindings/clock/qcom,gpucc-sc8280x      9 #include <dt-bindings/clock/qcom,gpucc-sc8280xp.h>
 10 #include <dt-bindings/clock/qcom,rpmh.h>           10 #include <dt-bindings/clock/qcom,rpmh.h>
 11 #include <dt-bindings/clock/qcom,sc8280xp-camc     11 #include <dt-bindings/clock/qcom,sc8280xp-camcc.h>
 12 #include <dt-bindings/clock/qcom,sc8280xp-lpas     12 #include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>
 13 #include <dt-bindings/interconnect/qcom,osm-l3     13 #include <dt-bindings/interconnect/qcom,osm-l3.h>
 14 #include <dt-bindings/interconnect/qcom,sc8280     14 #include <dt-bindings/interconnect/qcom,sc8280xp.h>
 15 #include <dt-bindings/interrupt-controller/arm     15 #include <dt-bindings/interrupt-controller/arm-gic.h>
 16 #include <dt-bindings/mailbox/qcom-ipcc.h>         16 #include <dt-bindings/mailbox/qcom-ipcc.h>
 17 #include <dt-bindings/phy/phy-qcom-qmp.h>          17 #include <dt-bindings/phy/phy-qcom-qmp.h>
 18 #include <dt-bindings/power/qcom-rpmpd.h>          18 #include <dt-bindings/power/qcom-rpmpd.h>
 19 #include <dt-bindings/soc/qcom,gpr.h>              19 #include <dt-bindings/soc/qcom,gpr.h>
 20 #include <dt-bindings/soc/qcom,rpmh-rsc.h>         20 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
 21 #include <dt-bindings/sound/qcom,q6afe.h>          21 #include <dt-bindings/sound/qcom,q6afe.h>
 22 #include <dt-bindings/thermal/thermal.h>           22 #include <dt-bindings/thermal/thermal.h>
 23                                                    23 
 24 / {                                                24 / {
 25         interrupt-parent = <&intc>;                25         interrupt-parent = <&intc>;
 26                                                    26 
 27         #address-cells = <2>;                      27         #address-cells = <2>;
 28         #size-cells = <2>;                         28         #size-cells = <2>;
 29                                                    29 
 30         clocks {                                   30         clocks {
 31                 xo_board_clk: xo-board-clk {       31                 xo_board_clk: xo-board-clk {
 32                         compatible = "fixed-cl     32                         compatible = "fixed-clock";
 33                         #clock-cells = <0>;        33                         #clock-cells = <0>;
 34                 };                                 34                 };
 35                                                    35 
 36                 sleep_clk: sleep-clk {             36                 sleep_clk: sleep-clk {
 37                         compatible = "fixed-cl     37                         compatible = "fixed-clock";
 38                         #clock-cells = <0>;        38                         #clock-cells = <0>;
 39                         clock-frequency = <327     39                         clock-frequency = <32764>;
 40                 };                                 40                 };
 41         };                                         41         };
 42                                                    42 
 43         cpus {                                     43         cpus {
 44                 #address-cells = <2>;              44                 #address-cells = <2>;
 45                 #size-cells = <0>;                 45                 #size-cells = <0>;
 46                                                    46 
 47                 CPU0: cpu@0 {                      47                 CPU0: cpu@0 {
 48                         device_type = "cpu";       48                         device_type = "cpu";
 49                         compatible = "arm,cort     49                         compatible = "arm,cortex-a78c";
 50                         reg = <0x0 0x0>;           50                         reg = <0x0 0x0>;
 51                         clocks = <&cpufreq_hw      51                         clocks = <&cpufreq_hw 0>;
 52                         enable-method = "psci"     52                         enable-method = "psci";
 53                         capacity-dmips-mhz = <     53                         capacity-dmips-mhz = <981>;
 54                         dynamic-power-coeffici     54                         dynamic-power-coefficient = <549>;
 55                         next-level-cache = <&L     55                         next-level-cache = <&L2_0>;
 56                         power-domains = <&CPU_     56                         power-domains = <&CPU_PD0>;
 57                         power-domain-names = "     57                         power-domain-names = "psci";
 58                         qcom,freq-domain = <&c     58                         qcom,freq-domain = <&cpufreq_hw 0>;
 59                         operating-points-v2 =      59                         operating-points-v2 = <&cpu0_opp_table>;
 60                         interconnects = <&epss     60                         interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
 61                         #cooling-cells = <2>;      61                         #cooling-cells = <2>;
 62                         L2_0: l2-cache {           62                         L2_0: l2-cache {
 63                                 compatible = "     63                                 compatible = "cache";
 64                                 cache-level =      64                                 cache-level = <2>;
 65                                 cache-unified;     65                                 cache-unified;
 66                                 next-level-cac     66                                 next-level-cache = <&L3_0>;
 67                                 L3_0: l3-cache     67                                 L3_0: l3-cache {
 68                                         compat     68                                         compatible = "cache";
 69                                         cache-     69                                         cache-level = <3>;
 70                                         cache-     70                                         cache-unified;
 71                                 };                 71                                 };
 72                         };                         72                         };
 73                 };                                 73                 };
 74                                                    74 
 75                 CPU1: cpu@100 {                    75                 CPU1: cpu@100 {
 76                         device_type = "cpu";       76                         device_type = "cpu";
 77                         compatible = "arm,cort     77                         compatible = "arm,cortex-a78c";
 78                         reg = <0x0 0x100>;         78                         reg = <0x0 0x100>;
 79                         clocks = <&cpufreq_hw      79                         clocks = <&cpufreq_hw 0>;
 80                         enable-method = "psci"     80                         enable-method = "psci";
 81                         capacity-dmips-mhz = <     81                         capacity-dmips-mhz = <981>;
 82                         dynamic-power-coeffici     82                         dynamic-power-coefficient = <549>;
 83                         next-level-cache = <&L     83                         next-level-cache = <&L2_100>;
 84                         power-domains = <&CPU_     84                         power-domains = <&CPU_PD1>;
 85                         power-domain-names = "     85                         power-domain-names = "psci";
 86                         qcom,freq-domain = <&c     86                         qcom,freq-domain = <&cpufreq_hw 0>;
 87                         operating-points-v2 =      87                         operating-points-v2 = <&cpu0_opp_table>;
 88                         interconnects = <&epss     88                         interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
 89                         #cooling-cells = <2>;      89                         #cooling-cells = <2>;
 90                         L2_100: l2-cache {         90                         L2_100: l2-cache {
 91                                 compatible = "     91                                 compatible = "cache";
 92                                 cache-level =      92                                 cache-level = <2>;
 93                                 cache-unified;     93                                 cache-unified;
 94                                 next-level-cac     94                                 next-level-cache = <&L3_0>;
 95                         };                         95                         };
 96                 };                                 96                 };
 97                                                    97 
 98                 CPU2: cpu@200 {                    98                 CPU2: cpu@200 {
 99                         device_type = "cpu";       99                         device_type = "cpu";
100                         compatible = "arm,cort    100                         compatible = "arm,cortex-a78c";
101                         reg = <0x0 0x200>;        101                         reg = <0x0 0x200>;
102                         clocks = <&cpufreq_hw     102                         clocks = <&cpufreq_hw 0>;
103                         enable-method = "psci"    103                         enable-method = "psci";
104                         capacity-dmips-mhz = <    104                         capacity-dmips-mhz = <981>;
105                         dynamic-power-coeffici    105                         dynamic-power-coefficient = <549>;
106                         next-level-cache = <&L    106                         next-level-cache = <&L2_200>;
107                         power-domains = <&CPU_    107                         power-domains = <&CPU_PD2>;
108                         power-domain-names = "    108                         power-domain-names = "psci";
109                         qcom,freq-domain = <&c    109                         qcom,freq-domain = <&cpufreq_hw 0>;
110                         operating-points-v2 =     110                         operating-points-v2 = <&cpu0_opp_table>;
111                         interconnects = <&epss    111                         interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
112                         #cooling-cells = <2>;     112                         #cooling-cells = <2>;
113                         L2_200: l2-cache {        113                         L2_200: l2-cache {
114                                 compatible = "    114                                 compatible = "cache";
115                                 cache-level =     115                                 cache-level = <2>;
116                                 cache-unified;    116                                 cache-unified;
117                                 next-level-cac    117                                 next-level-cache = <&L3_0>;
118                         };                        118                         };
119                 };                                119                 };
120                                                   120 
121                 CPU3: cpu@300 {                   121                 CPU3: cpu@300 {
122                         device_type = "cpu";      122                         device_type = "cpu";
123                         compatible = "arm,cort    123                         compatible = "arm,cortex-a78c";
124                         reg = <0x0 0x300>;        124                         reg = <0x0 0x300>;
125                         clocks = <&cpufreq_hw     125                         clocks = <&cpufreq_hw 0>;
126                         enable-method = "psci"    126                         enable-method = "psci";
127                         capacity-dmips-mhz = <    127                         capacity-dmips-mhz = <981>;
128                         dynamic-power-coeffici    128                         dynamic-power-coefficient = <549>;
129                         next-level-cache = <&L    129                         next-level-cache = <&L2_300>;
130                         power-domains = <&CPU_    130                         power-domains = <&CPU_PD3>;
131                         power-domain-names = "    131                         power-domain-names = "psci";
132                         qcom,freq-domain = <&c    132                         qcom,freq-domain = <&cpufreq_hw 0>;
133                         operating-points-v2 =     133                         operating-points-v2 = <&cpu0_opp_table>;
134                         interconnects = <&epss    134                         interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
135                         #cooling-cells = <2>;     135                         #cooling-cells = <2>;
136                         L2_300: l2-cache {        136                         L2_300: l2-cache {
137                                 compatible = "    137                                 compatible = "cache";
138                                 cache-level =     138                                 cache-level = <2>;
139                                 cache-unified;    139                                 cache-unified;
140                                 next-level-cac    140                                 next-level-cache = <&L3_0>;
141                         };                        141                         };
142                 };                                142                 };
143                                                   143 
144                 CPU4: cpu@400 {                   144                 CPU4: cpu@400 {
145                         device_type = "cpu";      145                         device_type = "cpu";
146                         compatible = "arm,cort    146                         compatible = "arm,cortex-x1c";
147                         reg = <0x0 0x400>;        147                         reg = <0x0 0x400>;
148                         clocks = <&cpufreq_hw     148                         clocks = <&cpufreq_hw 1>;
149                         enable-method = "psci"    149                         enable-method = "psci";
150                         capacity-dmips-mhz = <    150                         capacity-dmips-mhz = <1024>;
151                         dynamic-power-coeffici    151                         dynamic-power-coefficient = <590>;
152                         next-level-cache = <&L    152                         next-level-cache = <&L2_400>;
153                         power-domains = <&CPU_    153                         power-domains = <&CPU_PD4>;
154                         power-domain-names = "    154                         power-domain-names = "psci";
155                         qcom,freq-domain = <&c    155                         qcom,freq-domain = <&cpufreq_hw 1>;
156                         operating-points-v2 =     156                         operating-points-v2 = <&cpu4_opp_table>;
157                         interconnects = <&epss    157                         interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
158                         #cooling-cells = <2>;     158                         #cooling-cells = <2>;
159                         L2_400: l2-cache {        159                         L2_400: l2-cache {
160                                 compatible = "    160                                 compatible = "cache";
161                                 cache-level =     161                                 cache-level = <2>;
162                                 cache-unified;    162                                 cache-unified;
163                                 next-level-cac    163                                 next-level-cache = <&L3_0>;
164                         };                        164                         };
165                 };                                165                 };
166                                                   166 
167                 CPU5: cpu@500 {                   167                 CPU5: cpu@500 {
168                         device_type = "cpu";      168                         device_type = "cpu";
169                         compatible = "arm,cort    169                         compatible = "arm,cortex-x1c";
170                         reg = <0x0 0x500>;        170                         reg = <0x0 0x500>;
171                         clocks = <&cpufreq_hw     171                         clocks = <&cpufreq_hw 1>;
172                         enable-method = "psci"    172                         enable-method = "psci";
173                         capacity-dmips-mhz = <    173                         capacity-dmips-mhz = <1024>;
174                         dynamic-power-coeffici    174                         dynamic-power-coefficient = <590>;
175                         next-level-cache = <&L    175                         next-level-cache = <&L2_500>;
176                         power-domains = <&CPU_    176                         power-domains = <&CPU_PD5>;
177                         power-domain-names = "    177                         power-domain-names = "psci";
178                         qcom,freq-domain = <&c    178                         qcom,freq-domain = <&cpufreq_hw 1>;
179                         operating-points-v2 =     179                         operating-points-v2 = <&cpu4_opp_table>;
180                         interconnects = <&epss    180                         interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
181                         #cooling-cells = <2>;     181                         #cooling-cells = <2>;
182                         L2_500: l2-cache {        182                         L2_500: l2-cache {
183                                 compatible = "    183                                 compatible = "cache";
184                                 cache-level =     184                                 cache-level = <2>;
185                                 cache-unified;    185                                 cache-unified;
186                                 next-level-cac    186                                 next-level-cache = <&L3_0>;
187                         };                        187                         };
188                 };                                188                 };
189                                                   189 
190                 CPU6: cpu@600 {                   190                 CPU6: cpu@600 {
191                         device_type = "cpu";      191                         device_type = "cpu";
192                         compatible = "arm,cort    192                         compatible = "arm,cortex-x1c";
193                         reg = <0x0 0x600>;        193                         reg = <0x0 0x600>;
194                         clocks = <&cpufreq_hw     194                         clocks = <&cpufreq_hw 1>;
195                         enable-method = "psci"    195                         enable-method = "psci";
196                         capacity-dmips-mhz = <    196                         capacity-dmips-mhz = <1024>;
197                         dynamic-power-coeffici    197                         dynamic-power-coefficient = <590>;
198                         next-level-cache = <&L    198                         next-level-cache = <&L2_600>;
199                         power-domains = <&CPU_    199                         power-domains = <&CPU_PD6>;
200                         power-domain-names = "    200                         power-domain-names = "psci";
201                         qcom,freq-domain = <&c    201                         qcom,freq-domain = <&cpufreq_hw 1>;
202                         operating-points-v2 =     202                         operating-points-v2 = <&cpu4_opp_table>;
203                         interconnects = <&epss    203                         interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
204                         #cooling-cells = <2>;     204                         #cooling-cells = <2>;
205                         L2_600: l2-cache {        205                         L2_600: l2-cache {
206                                 compatible = "    206                                 compatible = "cache";
207                                 cache-level =     207                                 cache-level = <2>;
208                                 cache-unified;    208                                 cache-unified;
209                                 next-level-cac    209                                 next-level-cache = <&L3_0>;
210                         };                        210                         };
211                 };                                211                 };
212                                                   212 
213                 CPU7: cpu@700 {                   213                 CPU7: cpu@700 {
214                         device_type = "cpu";      214                         device_type = "cpu";
215                         compatible = "arm,cort    215                         compatible = "arm,cortex-x1c";
216                         reg = <0x0 0x700>;        216                         reg = <0x0 0x700>;
217                         clocks = <&cpufreq_hw     217                         clocks = <&cpufreq_hw 1>;
218                         enable-method = "psci"    218                         enable-method = "psci";
219                         capacity-dmips-mhz = <    219                         capacity-dmips-mhz = <1024>;
220                         dynamic-power-coeffici    220                         dynamic-power-coefficient = <590>;
221                         next-level-cache = <&L    221                         next-level-cache = <&L2_700>;
222                         power-domains = <&CPU_    222                         power-domains = <&CPU_PD7>;
223                         power-domain-names = "    223                         power-domain-names = "psci";
224                         qcom,freq-domain = <&c    224                         qcom,freq-domain = <&cpufreq_hw 1>;
225                         operating-points-v2 =     225                         operating-points-v2 = <&cpu4_opp_table>;
226                         interconnects = <&epss    226                         interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
227                         #cooling-cells = <2>;     227                         #cooling-cells = <2>;
228                         L2_700: l2-cache {        228                         L2_700: l2-cache {
229                                 compatible = "    229                                 compatible = "cache";
230                                 cache-level =     230                                 cache-level = <2>;
231                                 cache-unified;    231                                 cache-unified;
232                                 next-level-cac    232                                 next-level-cache = <&L3_0>;
233                         };                        233                         };
234                 };                                234                 };
235                                                   235 
236                 cpu-map {                         236                 cpu-map {
237                         cluster0 {                237                         cluster0 {
238                                 core0 {           238                                 core0 {
239                                         cpu =     239                                         cpu = <&CPU0>;
240                                 };                240                                 };
241                                                   241 
242                                 core1 {           242                                 core1 {
243                                         cpu =     243                                         cpu = <&CPU1>;
244                                 };                244                                 };
245                                                   245 
246                                 core2 {           246                                 core2 {
247                                         cpu =     247                                         cpu = <&CPU2>;
248                                 };                248                                 };
249                                                   249 
250                                 core3 {           250                                 core3 {
251                                         cpu =     251                                         cpu = <&CPU3>;
252                                 };                252                                 };
253                                                   253 
254                                 core4 {           254                                 core4 {
255                                         cpu =     255                                         cpu = <&CPU4>;
256                                 };                256                                 };
257                                                   257 
258                                 core5 {           258                                 core5 {
259                                         cpu =     259                                         cpu = <&CPU5>;
260                                 };                260                                 };
261                                                   261 
262                                 core6 {           262                                 core6 {
263                                         cpu =     263                                         cpu = <&CPU6>;
264                                 };                264                                 };
265                                                   265 
266                                 core7 {           266                                 core7 {
267                                         cpu =     267                                         cpu = <&CPU7>;
268                                 };                268                                 };
269                         };                        269                         };
270                 };                                270                 };
271                                                   271 
272                 idle-states {                     272                 idle-states {
273                         entry-method = "psci";    273                         entry-method = "psci";
274                                                   274 
275                         LITTLE_CPU_SLEEP_0: cp    275                         LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
276                                 compatible = "    276                                 compatible = "arm,idle-state";
277                                 idle-state-nam    277                                 idle-state-name = "little-rail-power-collapse";
278                                 arm,psci-suspe    278                                 arm,psci-suspend-param = <0x40000004>;
279                                 entry-latency-    279                                 entry-latency-us = <355>;
280                                 exit-latency-u    280                                 exit-latency-us = <909>;
281                                 min-residency-    281                                 min-residency-us = <3934>;
282                                 local-timer-st    282                                 local-timer-stop;
283                         };                        283                         };
284                                                   284 
285                         BIG_CPU_SLEEP_0: cpu-s    285                         BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
286                                 compatible = "    286                                 compatible = "arm,idle-state";
287                                 idle-state-nam    287                                 idle-state-name = "big-rail-power-collapse";
288                                 arm,psci-suspe    288                                 arm,psci-suspend-param = <0x40000004>;
289                                 entry-latency-    289                                 entry-latency-us = <241>;
290                                 exit-latency-u    290                                 exit-latency-us = <1461>;
291                                 min-residency-    291                                 min-residency-us = <4488>;
292                                 local-timer-st    292                                 local-timer-stop;
293                         };                        293                         };
294                 };                                294                 };
295                                                   295 
296                 domain-idle-states {              296                 domain-idle-states {
297                         CLUSTER_SLEEP_0: clust    297                         CLUSTER_SLEEP_0: cluster-sleep-0 {
298                                 compatible = "    298                                 compatible = "domain-idle-state";
299                                 arm,psci-suspe    299                                 arm,psci-suspend-param = <0x4100c344>;
300                                 entry-latency-    300                                 entry-latency-us = <3263>;
301                                 exit-latency-u    301                                 exit-latency-us = <6562>;
302                                 min-residency-    302                                 min-residency-us = <9987>;
303                         };                        303                         };
304                 };                                304                 };
305         };                                        305         };
306                                                   306 
307         firmware {                                307         firmware {
308                 scm: scm {                        308                 scm: scm {
309                         compatible = "qcom,scm    309                         compatible = "qcom,scm-sc8280xp", "qcom,scm";
310                         interconnects = <&aggr    310                         interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
311                         qcom,dload-mode = <&tc    311                         qcom,dload-mode = <&tcsr 0x13000>;
312                 };                                312                 };
313         };                                        313         };
314                                                   314 
315         aggre1_noc: interconnect-aggre1-noc {     315         aggre1_noc: interconnect-aggre1-noc {
316                 compatible = "qcom,sc8280xp-ag    316                 compatible = "qcom,sc8280xp-aggre1-noc";
317                 #interconnect-cells = <2>;        317                 #interconnect-cells = <2>;
318                 qcom,bcm-voters = <&apps_bcm_v    318                 qcom,bcm-voters = <&apps_bcm_voter>;
319         };                                        319         };
320                                                   320 
321         aggre2_noc: interconnect-aggre2-noc {     321         aggre2_noc: interconnect-aggre2-noc {
322                 compatible = "qcom,sc8280xp-ag    322                 compatible = "qcom,sc8280xp-aggre2-noc";
323                 #interconnect-cells = <2>;        323                 #interconnect-cells = <2>;
324                 qcom,bcm-voters = <&apps_bcm_v    324                 qcom,bcm-voters = <&apps_bcm_voter>;
325         };                                        325         };
326                                                   326 
327         clk_virt: interconnect-clk-virt {         327         clk_virt: interconnect-clk-virt {
328                 compatible = "qcom,sc8280xp-cl    328                 compatible = "qcom,sc8280xp-clk-virt";
329                 #interconnect-cells = <2>;        329                 #interconnect-cells = <2>;
330                 qcom,bcm-voters = <&apps_bcm_v    330                 qcom,bcm-voters = <&apps_bcm_voter>;
331         };                                        331         };
332                                                   332 
333         config_noc: interconnect-config-noc {     333         config_noc: interconnect-config-noc {
334                 compatible = "qcom,sc8280xp-co    334                 compatible = "qcom,sc8280xp-config-noc";
335                 #interconnect-cells = <2>;        335                 #interconnect-cells = <2>;
336                 qcom,bcm-voters = <&apps_bcm_v    336                 qcom,bcm-voters = <&apps_bcm_voter>;
337         };                                        337         };
338                                                   338 
339         dc_noc: interconnect-dc-noc {             339         dc_noc: interconnect-dc-noc {
340                 compatible = "qcom,sc8280xp-dc    340                 compatible = "qcom,sc8280xp-dc-noc";
341                 #interconnect-cells = <2>;        341                 #interconnect-cells = <2>;
342                 qcom,bcm-voters = <&apps_bcm_v    342                 qcom,bcm-voters = <&apps_bcm_voter>;
343         };                                        343         };
344                                                   344 
345         gem_noc: interconnect-gem-noc {           345         gem_noc: interconnect-gem-noc {
346                 compatible = "qcom,sc8280xp-ge    346                 compatible = "qcom,sc8280xp-gem-noc";
347                 #interconnect-cells = <2>;        347                 #interconnect-cells = <2>;
348                 qcom,bcm-voters = <&apps_bcm_v    348                 qcom,bcm-voters = <&apps_bcm_voter>;
349         };                                        349         };
350                                                   350 
351         lpass_noc: interconnect-lpass-ag-noc {    351         lpass_noc: interconnect-lpass-ag-noc {
352                 compatible = "qcom,sc8280xp-lp    352                 compatible = "qcom,sc8280xp-lpass-ag-noc";
353                 #interconnect-cells = <2>;        353                 #interconnect-cells = <2>;
354                 qcom,bcm-voters = <&apps_bcm_v    354                 qcom,bcm-voters = <&apps_bcm_voter>;
355         };                                        355         };
356                                                   356 
357         mc_virt: interconnect-mc-virt {           357         mc_virt: interconnect-mc-virt {
358                 compatible = "qcom,sc8280xp-mc    358                 compatible = "qcom,sc8280xp-mc-virt";
359                 #interconnect-cells = <2>;        359                 #interconnect-cells = <2>;
360                 qcom,bcm-voters = <&apps_bcm_v    360                 qcom,bcm-voters = <&apps_bcm_voter>;
361         };                                        361         };
362                                                   362 
363         mmss_noc: interconnect-mmss-noc {         363         mmss_noc: interconnect-mmss-noc {
364                 compatible = "qcom,sc8280xp-mm    364                 compatible = "qcom,sc8280xp-mmss-noc";
365                 #interconnect-cells = <2>;        365                 #interconnect-cells = <2>;
366                 qcom,bcm-voters = <&apps_bcm_v    366                 qcom,bcm-voters = <&apps_bcm_voter>;
367         };                                        367         };
368                                                   368 
369         nspa_noc: interconnect-nspa-noc {         369         nspa_noc: interconnect-nspa-noc {
370                 compatible = "qcom,sc8280xp-ns    370                 compatible = "qcom,sc8280xp-nspa-noc";
371                 #interconnect-cells = <2>;        371                 #interconnect-cells = <2>;
372                 qcom,bcm-voters = <&apps_bcm_v    372                 qcom,bcm-voters = <&apps_bcm_voter>;
373         };                                        373         };
374                                                   374 
375         nspb_noc: interconnect-nspb-noc {         375         nspb_noc: interconnect-nspb-noc {
376                 compatible = "qcom,sc8280xp-ns    376                 compatible = "qcom,sc8280xp-nspb-noc";
377                 #interconnect-cells = <2>;        377                 #interconnect-cells = <2>;
378                 qcom,bcm-voters = <&apps_bcm_v    378                 qcom,bcm-voters = <&apps_bcm_voter>;
379         };                                        379         };
380                                                   380 
381         system_noc: interconnect-system-noc {     381         system_noc: interconnect-system-noc {
382                 compatible = "qcom,sc8280xp-sy    382                 compatible = "qcom,sc8280xp-system-noc";
383                 #interconnect-cells = <2>;        383                 #interconnect-cells = <2>;
384                 qcom,bcm-voters = <&apps_bcm_v    384                 qcom,bcm-voters = <&apps_bcm_voter>;
385         };                                        385         };
386                                                   386 
387         memory@80000000 {                         387         memory@80000000 {
388                 device_type = "memory";           388                 device_type = "memory";
389                 /* We expect the bootloader to    389                 /* We expect the bootloader to fill in the size */
390                 reg = <0x0 0x80000000 0x0 0x0>    390                 reg = <0x0 0x80000000 0x0 0x0>;
391         };                                        391         };
392                                                   392 
393         cpu0_opp_table: opp-table-cpu0 {          393         cpu0_opp_table: opp-table-cpu0 {
394                 compatible = "operating-points    394                 compatible = "operating-points-v2";
395                 opp-shared;                       395                 opp-shared;
396                                                   396 
397                 opp-300000000 {                   397                 opp-300000000 {
398                         opp-hz = /bits/ 64 <30    398                         opp-hz = /bits/ 64 <300000000>;
399                         opp-peak-kBps = <(3000    399                         opp-peak-kBps = <(300000 * 32)>;
400                 };                                400                 };
401                 opp-403200000 {                   401                 opp-403200000 {
402                         opp-hz = /bits/ 64 <40    402                         opp-hz = /bits/ 64 <403200000>;
403                         opp-peak-kBps = <(3840    403                         opp-peak-kBps = <(384000 * 32)>;
404                 };                                404                 };
405                 opp-499200000 {                   405                 opp-499200000 {
406                         opp-hz = /bits/ 64 <49    406                         opp-hz = /bits/ 64 <499200000>;
407                         opp-peak-kBps = <(4800    407                         opp-peak-kBps = <(480000 * 32)>;
408                 };                                408                 };
409                 opp-595200000 {                   409                 opp-595200000 {
410                         opp-hz = /bits/ 64 <59    410                         opp-hz = /bits/ 64 <595200000>;
411                         opp-peak-kBps = <(5760    411                         opp-peak-kBps = <(576000 * 32)>;
412                 };                                412                 };
413                 opp-691200000 {                   413                 opp-691200000 {
414                         opp-hz = /bits/ 64 <69    414                         opp-hz = /bits/ 64 <691200000>;
415                         opp-peak-kBps = <(6720    415                         opp-peak-kBps = <(672000 * 32)>;
416                 };                                416                 };
417                 opp-806400000 {                   417                 opp-806400000 {
418                         opp-hz = /bits/ 64 <80    418                         opp-hz = /bits/ 64 <806400000>;
419                         opp-peak-kBps = <(7680    419                         opp-peak-kBps = <(768000 * 32)>;
420                 };                                420                 };
421                 opp-902400000 {                   421                 opp-902400000 {
422                         opp-hz = /bits/ 64 <90    422                         opp-hz = /bits/ 64 <902400000>;
423                         opp-peak-kBps = <(8640    423                         opp-peak-kBps = <(864000 * 32)>;
424                 };                                424                 };
425                 opp-1017600000 {                  425                 opp-1017600000 {
426                         opp-hz = /bits/ 64 <10    426                         opp-hz = /bits/ 64 <1017600000>;
427                         opp-peak-kBps = <(9600    427                         opp-peak-kBps = <(960000 * 32)>;
428                 };                                428                 };
429                 opp-1113600000 {                  429                 opp-1113600000 {
430                         opp-hz = /bits/ 64 <11    430                         opp-hz = /bits/ 64 <1113600000>;
431                         opp-peak-kBps = <(1075    431                         opp-peak-kBps = <(1075200 * 32)>;
432                 };                                432                 };
433                 opp-1209600000 {                  433                 opp-1209600000 {
434                         opp-hz = /bits/ 64 <12    434                         opp-hz = /bits/ 64 <1209600000>;
435                         opp-peak-kBps = <(1171    435                         opp-peak-kBps = <(1171200 * 32)>;
436                 };                                436                 };
437                 opp-1324800000 {                  437                 opp-1324800000 {
438                         opp-hz = /bits/ 64 <13    438                         opp-hz = /bits/ 64 <1324800000>;
439                         opp-peak-kBps = <(1267    439                         opp-peak-kBps = <(1267200 * 32)>;
440                 };                                440                 };
441                 opp-1440000000 {                  441                 opp-1440000000 {
442                         opp-hz = /bits/ 64 <14    442                         opp-hz = /bits/ 64 <1440000000>;
443                         opp-peak-kBps = <(1363    443                         opp-peak-kBps = <(1363200 * 32)>;
444                 };                                444                 };
445                 opp-1555200000 {                  445                 opp-1555200000 {
446                         opp-hz = /bits/ 64 <15    446                         opp-hz = /bits/ 64 <1555200000>;
447                         opp-peak-kBps = <(1536    447                         opp-peak-kBps = <(1536000 * 32)>;
448                 };                                448                 };
449                 opp-1670400000 {                  449                 opp-1670400000 {
450                         opp-hz = /bits/ 64 <16    450                         opp-hz = /bits/ 64 <1670400000>;
451                         opp-peak-kBps = <(1612    451                         opp-peak-kBps = <(1612800 * 32)>;
452                 };                                452                 };
453                 opp-1785600000 {                  453                 opp-1785600000 {
454                         opp-hz = /bits/ 64 <17    454                         opp-hz = /bits/ 64 <1785600000>;
455                         opp-peak-kBps = <(1689    455                         opp-peak-kBps = <(1689600 * 32)>;
456                 };                                456                 };
457                 opp-1881600000 {                  457                 opp-1881600000 {
458                         opp-hz = /bits/ 64 <18    458                         opp-hz = /bits/ 64 <1881600000>;
459                         opp-peak-kBps = <(1689    459                         opp-peak-kBps = <(1689600 * 32)>;
460                 };                                460                 };
461                 opp-1996800000 {                  461                 opp-1996800000 {
462                         opp-hz = /bits/ 64 <19    462                         opp-hz = /bits/ 64 <1996800000>;
463                         opp-peak-kBps = <(1689    463                         opp-peak-kBps = <(1689600 * 32)>;
464                 };                                464                 };
465                 opp-2112000000 {                  465                 opp-2112000000 {
466                         opp-hz = /bits/ 64 <21    466                         opp-hz = /bits/ 64 <2112000000>;
467                         opp-peak-kBps = <(1689    467                         opp-peak-kBps = <(1689600 * 32)>;
468                 };                                468                 };
469                 opp-2227200000 {                  469                 opp-2227200000 {
470                         opp-hz = /bits/ 64 <22    470                         opp-hz = /bits/ 64 <2227200000>;
471                         opp-peak-kBps = <(1689    471                         opp-peak-kBps = <(1689600 * 32)>;
472                 };                                472                 };
473                 opp-2342400000 {                  473                 opp-2342400000 {
474                         opp-hz = /bits/ 64 <23    474                         opp-hz = /bits/ 64 <2342400000>;
475                         opp-peak-kBps = <(1689    475                         opp-peak-kBps = <(1689600 * 32)>;
476                 };                                476                 };
477                 opp-2438400000 {                  477                 opp-2438400000 {
478                         opp-hz = /bits/ 64 <24    478                         opp-hz = /bits/ 64 <2438400000>;
479                         opp-peak-kBps = <(1689    479                         opp-peak-kBps = <(1689600 * 32)>;
480                 };                                480                 };
481         };                                        481         };
482                                                   482 
483         cpu4_opp_table: opp-table-cpu4 {          483         cpu4_opp_table: opp-table-cpu4 {
484                 compatible = "operating-points    484                 compatible = "operating-points-v2";
485                 opp-shared;                       485                 opp-shared;
486                                                   486 
487                 opp-825600000 {                   487                 opp-825600000 {
488                         opp-hz = /bits/ 64 <82    488                         opp-hz = /bits/ 64 <825600000>;
489                         opp-peak-kBps = <(7680    489                         opp-peak-kBps = <(768000 * 32)>;
490                 };                                490                 };
491                 opp-940800000 {                   491                 opp-940800000 {
492                         opp-hz = /bits/ 64 <94    492                         opp-hz = /bits/ 64 <940800000>;
493                         opp-peak-kBps = <(8640    493                         opp-peak-kBps = <(864000 * 32)>;
494                 };                                494                 };
495                 opp-1056000000 {                  495                 opp-1056000000 {
496                         opp-hz = /bits/ 64 <10    496                         opp-hz = /bits/ 64 <1056000000>;
497                         opp-peak-kBps = <(9600    497                         opp-peak-kBps = <(960000 * 32)>;
498                 };                                498                 };
499                 opp-1171200000 {                  499                 opp-1171200000 {
500                         opp-hz = /bits/ 64 <11    500                         opp-hz = /bits/ 64 <1171200000>;
501                         opp-peak-kBps = <(1171    501                         opp-peak-kBps = <(1171200 * 32)>;
502                 };                                502                 };
503                 opp-1286400000 {                  503                 opp-1286400000 {
504                         opp-hz = /bits/ 64 <12    504                         opp-hz = /bits/ 64 <1286400000>;
505                         opp-peak-kBps = <(1267    505                         opp-peak-kBps = <(1267200 * 32)>;
506                 };                                506                 };
507                 opp-1401600000 {                  507                 opp-1401600000 {
508                         opp-hz = /bits/ 64 <14    508                         opp-hz = /bits/ 64 <1401600000>;
509                         opp-peak-kBps = <(1363    509                         opp-peak-kBps = <(1363200 * 32)>;
510                 };                                510                 };
511                 opp-1516800000 {                  511                 opp-1516800000 {
512                         opp-hz = /bits/ 64 <15    512                         opp-hz = /bits/ 64 <1516800000>;
513                         opp-peak-kBps = <(1459    513                         opp-peak-kBps = <(1459200 * 32)>;
514                 };                                514                 };
515                 opp-1632000000 {                  515                 opp-1632000000 {
516                         opp-hz = /bits/ 64 <16    516                         opp-hz = /bits/ 64 <1632000000>;
517                         opp-peak-kBps = <(1612    517                         opp-peak-kBps = <(1612800 * 32)>;
518                 };                                518                 };
519                 opp-1747200000 {                  519                 opp-1747200000 {
520                         opp-hz = /bits/ 64 <17    520                         opp-hz = /bits/ 64 <1747200000>;
521                         opp-peak-kBps = <(1689    521                         opp-peak-kBps = <(1689600 * 32)>;
522                 };                                522                 };
523                 opp-1862400000 {                  523                 opp-1862400000 {
524                         opp-hz = /bits/ 64 <18    524                         opp-hz = /bits/ 64 <1862400000>;
525                         opp-peak-kBps = <(1689    525                         opp-peak-kBps = <(1689600 * 32)>;
526                 };                                526                 };
527                 opp-1977600000 {                  527                 opp-1977600000 {
528                         opp-hz = /bits/ 64 <19    528                         opp-hz = /bits/ 64 <1977600000>;
529                         opp-peak-kBps = <(1689    529                         opp-peak-kBps = <(1689600 * 32)>;
530                 };                                530                 };
531                 opp-2073600000 {                  531                 opp-2073600000 {
532                         opp-hz = /bits/ 64 <20    532                         opp-hz = /bits/ 64 <2073600000>;
533                         opp-peak-kBps = <(1689    533                         opp-peak-kBps = <(1689600 * 32)>;
534                 };                                534                 };
535                 opp-2169600000 {                  535                 opp-2169600000 {
536                         opp-hz = /bits/ 64 <21    536                         opp-hz = /bits/ 64 <2169600000>;
537                         opp-peak-kBps = <(1689    537                         opp-peak-kBps = <(1689600 * 32)>;
538                 };                                538                 };
539                 opp-2284800000 {                  539                 opp-2284800000 {
540                         opp-hz = /bits/ 64 <22    540                         opp-hz = /bits/ 64 <2284800000>;
541                         opp-peak-kBps = <(1689    541                         opp-peak-kBps = <(1689600 * 32)>;
542                 };                                542                 };
543                 opp-2400000000 {                  543                 opp-2400000000 {
544                         opp-hz = /bits/ 64 <24    544                         opp-hz = /bits/ 64 <2400000000>;
545                         opp-peak-kBps = <(1689    545                         opp-peak-kBps = <(1689600 * 32)>;
546                 };                                546                 };
547                 opp-2496000000 {                  547                 opp-2496000000 {
548                         opp-hz = /bits/ 64 <24    548                         opp-hz = /bits/ 64 <2496000000>;
549                         opp-peak-kBps = <(1689    549                         opp-peak-kBps = <(1689600 * 32)>;
550                 };                                550                 };
551                 opp-2592000000 {                  551                 opp-2592000000 {
552                         opp-hz = /bits/ 64 <25    552                         opp-hz = /bits/ 64 <2592000000>;
553                         opp-peak-kBps = <(1689    553                         opp-peak-kBps = <(1689600 * 32)>;
554                 };                                554                 };
555                 opp-2688000000 {                  555                 opp-2688000000 {
556                         opp-hz = /bits/ 64 <26    556                         opp-hz = /bits/ 64 <2688000000>;
557                         opp-peak-kBps = <(1689    557                         opp-peak-kBps = <(1689600 * 32)>;
558                 };                                558                 };
559                 opp-2803200000 {                  559                 opp-2803200000 {
560                         opp-hz = /bits/ 64 <28    560                         opp-hz = /bits/ 64 <2803200000>;
561                         opp-peak-kBps = <(1689    561                         opp-peak-kBps = <(1689600 * 32)>;
562                 };                                562                 };
563                 opp-2899200000 {                  563                 opp-2899200000 {
564                         opp-hz = /bits/ 64 <28    564                         opp-hz = /bits/ 64 <2899200000>;
565                         opp-peak-kBps = <(1689    565                         opp-peak-kBps = <(1689600 * 32)>;
566                 };                                566                 };
567                 opp-2995200000 {                  567                 opp-2995200000 {
568                         opp-hz = /bits/ 64 <29    568                         opp-hz = /bits/ 64 <2995200000>;
569                         opp-peak-kBps = <(1689    569                         opp-peak-kBps = <(1689600 * 32)>;
570                 };                                570                 };
571         };                                        571         };
572                                                   572 
573         qup_opp_table_100mhz: opp-table-qup100    573         qup_opp_table_100mhz: opp-table-qup100mhz {
574                 compatible = "operating-points    574                 compatible = "operating-points-v2";
575                                                   575 
576                 opp-75000000 {                    576                 opp-75000000 {
577                         opp-hz = /bits/ 64 <75    577                         opp-hz = /bits/ 64 <75000000>;
578                         required-opps = <&rpmh    578                         required-opps = <&rpmhpd_opp_low_svs>;
579                 };                                579                 };
580                                                   580 
581                 opp-100000000 {                   581                 opp-100000000 {
582                         opp-hz = /bits/ 64 <10    582                         opp-hz = /bits/ 64 <100000000>;
583                         required-opps = <&rpmh    583                         required-opps = <&rpmhpd_opp_svs>;
584                 };                                584                 };
585         };                                        585         };
586                                                   586 
587         pmu {                                     587         pmu {
588                 compatible = "arm,armv8-pmuv3"    588                 compatible = "arm,armv8-pmuv3";
589                 interrupts = <GIC_PPI 7 IRQ_TY    589                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
590         };                                        590         };
591                                                   591 
592         psci {                                    592         psci {
593                 compatible = "arm,psci-1.0";      593                 compatible = "arm,psci-1.0";
594                 method = "smc";                   594                 method = "smc";
595                                                   595 
596                 CPU_PD0: power-domain-cpu0 {      596                 CPU_PD0: power-domain-cpu0 {
597                         #power-domain-cells =     597                         #power-domain-cells = <0>;
598                         power-domains = <&CLUS    598                         power-domains = <&CLUSTER_PD>;
599                         domain-idle-states = <    599                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
600                 };                                600                 };
601                                                   601 
602                 CPU_PD1: power-domain-cpu1 {      602                 CPU_PD1: power-domain-cpu1 {
603                         #power-domain-cells =     603                         #power-domain-cells = <0>;
604                         power-domains = <&CLUS    604                         power-domains = <&CLUSTER_PD>;
605                         domain-idle-states = <    605                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
606                 };                                606                 };
607                                                   607 
608                 CPU_PD2: power-domain-cpu2 {      608                 CPU_PD2: power-domain-cpu2 {
609                         #power-domain-cells =     609                         #power-domain-cells = <0>;
610                         power-domains = <&CLUS    610                         power-domains = <&CLUSTER_PD>;
611                         domain-idle-states = <    611                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
612                 };                                612                 };
613                                                   613 
614                 CPU_PD3: power-domain-cpu3 {      614                 CPU_PD3: power-domain-cpu3 {
615                         #power-domain-cells =     615                         #power-domain-cells = <0>;
616                         power-domains = <&CLUS    616                         power-domains = <&CLUSTER_PD>;
617                         domain-idle-states = <    617                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
618                 };                                618                 };
619                                                   619 
620                 CPU_PD4: power-domain-cpu4 {      620                 CPU_PD4: power-domain-cpu4 {
621                         #power-domain-cells =     621                         #power-domain-cells = <0>;
622                         power-domains = <&CLUS    622                         power-domains = <&CLUSTER_PD>;
623                         domain-idle-states = <    623                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
624                 };                                624                 };
625                                                   625 
626                 CPU_PD5: power-domain-cpu5 {      626                 CPU_PD5: power-domain-cpu5 {
627                         #power-domain-cells =     627                         #power-domain-cells = <0>;
628                         power-domains = <&CLUS    628                         power-domains = <&CLUSTER_PD>;
629                         domain-idle-states = <    629                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
630                 };                                630                 };
631                                                   631 
632                 CPU_PD6: power-domain-cpu6 {      632                 CPU_PD6: power-domain-cpu6 {
633                         #power-domain-cells =     633                         #power-domain-cells = <0>;
634                         power-domains = <&CLUS    634                         power-domains = <&CLUSTER_PD>;
635                         domain-idle-states = <    635                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
636                 };                                636                 };
637                                                   637 
638                 CPU_PD7: power-domain-cpu7 {      638                 CPU_PD7: power-domain-cpu7 {
639                         #power-domain-cells =     639                         #power-domain-cells = <0>;
640                         power-domains = <&CLUS    640                         power-domains = <&CLUSTER_PD>;
641                         domain-idle-states = <    641                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
642                 };                                642                 };
643                                                   643 
644                 CLUSTER_PD: power-domain-cpu-c    644                 CLUSTER_PD: power-domain-cpu-cluster0 {
645                         #power-domain-cells =     645                         #power-domain-cells = <0>;
646                         domain-idle-states = <    646                         domain-idle-states = <&CLUSTER_SLEEP_0>;
647                 };                                647                 };
648         };                                        648         };
649                                                   649 
650         reserved-memory {                         650         reserved-memory {
651                 #address-cells = <2>;             651                 #address-cells = <2>;
652                 #size-cells = <2>;                652                 #size-cells = <2>;
653                 ranges;                           653                 ranges;
654                                                   654 
655                 reserved-region@80000000 {        655                 reserved-region@80000000 {
656                         reg = <0 0x80000000 0     656                         reg = <0 0x80000000 0 0x860000>;
657                         no-map;                   657                         no-map;
658                 };                                658                 };
659                                                   659 
660                 cmd_db: cmd-db-region@80860000    660                 cmd_db: cmd-db-region@80860000 {
661                         compatible = "qcom,cmd    661                         compatible = "qcom,cmd-db";
662                         reg = <0 0x80860000 0     662                         reg = <0 0x80860000 0 0x20000>;
663                         no-map;                   663                         no-map;
664                 };                                664                 };
665                                                   665 
666                 reserved-region@80880000 {        666                 reserved-region@80880000 {
667                         reg = <0 0x80880000 0     667                         reg = <0 0x80880000 0 0x80000>;
668                         no-map;                   668                         no-map;
669                 };                                669                 };
670                                                   670 
671                 smem_mem: smem-region@80900000    671                 smem_mem: smem-region@80900000 {
672                         compatible = "qcom,sme    672                         compatible = "qcom,smem";
673                         reg = <0 0x80900000 0     673                         reg = <0 0x80900000 0 0x200000>;
674                         no-map;                   674                         no-map;
675                         hwlocks = <&tcsr_mutex    675                         hwlocks = <&tcsr_mutex 3>;
676                 };                                676                 };
677                                                   677 
678                 reserved-region@80b00000 {        678                 reserved-region@80b00000 {
679                         reg = <0 0x80b00000 0     679                         reg = <0 0x80b00000 0 0x100000>;
680                         no-map;                   680                         no-map;
681                 };                                681                 };
682                                                   682 
683                 reserved-region@83b00000 {        683                 reserved-region@83b00000 {
684                         reg = <0 0x83b00000 0     684                         reg = <0 0x83b00000 0 0x1700000>;
685                         no-map;                   685                         no-map;
686                 };                                686                 };
687                                                   687 
688                 reserved-region@85b00000 {        688                 reserved-region@85b00000 {
689                         reg = <0 0x85b00000 0     689                         reg = <0 0x85b00000 0 0xc00000>;
690                         no-map;                   690                         no-map;
691                 };                                691                 };
692                                                   692 
693                 pil_adsp_mem: adsp-region@86c0    693                 pil_adsp_mem: adsp-region@86c00000 {
694                         reg = <0 0x86c00000 0     694                         reg = <0 0x86c00000 0 0x2000000>;
695                         no-map;                   695                         no-map;
696                 };                                696                 };
697                                                   697 
698                 pil_nsp0_mem: cdsp0-region@8a1    698                 pil_nsp0_mem: cdsp0-region@8a100000 {
699                         reg = <0 0x8a100000 0     699                         reg = <0 0x8a100000 0 0x1e00000>;
700                         no-map;                   700                         no-map;
701                 };                                701                 };
702                                                   702 
703                 pil_nsp1_mem: cdsp1-region@8c6    703                 pil_nsp1_mem: cdsp1-region@8c600000 {
704                         reg = <0 0x8c600000 0     704                         reg = <0 0x8c600000 0 0x1e00000>;
705                         no-map;                   705                         no-map;
706                 };                                706                 };
707                                                   707 
708                 reserved-region@aeb00000 {        708                 reserved-region@aeb00000 {
709                         reg = <0 0xaeb00000 0     709                         reg = <0 0xaeb00000 0 0x16600000>;
710                         no-map;                   710                         no-map;
711                 };                                711                 };
712         };                                        712         };
713                                                   713 
714         smp2p-adsp {                              714         smp2p-adsp {
715                 compatible = "qcom,smp2p";        715                 compatible = "qcom,smp2p";
716                 qcom,smem = <443>, <429>;         716                 qcom,smem = <443>, <429>;
717                 interrupts-extended = <&ipcc I    717                 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
718                                              I    718                                              IPCC_MPROC_SIGNAL_SMP2P
719                                              I    719                                              IRQ_TYPE_EDGE_RISING>;
720                 mboxes = <&ipcc IPCC_CLIENT_LP    720                 mboxes = <&ipcc IPCC_CLIENT_LPASS
721                                 IPCC_MPROC_SIG    721                                 IPCC_MPROC_SIGNAL_SMP2P>;
722                                                   722 
723                 qcom,local-pid = <0>;             723                 qcom,local-pid = <0>;
724                 qcom,remote-pid = <2>;            724                 qcom,remote-pid = <2>;
725                                                   725 
726                 smp2p_adsp_out: master-kernel     726                 smp2p_adsp_out: master-kernel {
727                         qcom,entry-name = "mas    727                         qcom,entry-name = "master-kernel";
728                         #qcom,smem-state-cells    728                         #qcom,smem-state-cells = <1>;
729                 };                                729                 };
730                                                   730 
731                 smp2p_adsp_in: slave-kernel {     731                 smp2p_adsp_in: slave-kernel {
732                         qcom,entry-name = "sla    732                         qcom,entry-name = "slave-kernel";
733                         interrupt-controller;     733                         interrupt-controller;
734                         #interrupt-cells = <2>    734                         #interrupt-cells = <2>;
735                 };                                735                 };
736         };                                        736         };
737                                                   737 
738         smp2p-nsp0 {                              738         smp2p-nsp0 {
739                 compatible = "qcom,smp2p";        739                 compatible = "qcom,smp2p";
740                 qcom,smem = <94>, <432>;          740                 qcom,smem = <94>, <432>;
741                 interrupts-extended = <&ipcc I    741                 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
742                                              I    742                                              IPCC_MPROC_SIGNAL_SMP2P
743                                              I    743                                              IRQ_TYPE_EDGE_RISING>;
744                 mboxes = <&ipcc IPCC_CLIENT_CD    744                 mboxes = <&ipcc IPCC_CLIENT_CDSP
745                                 IPCC_MPROC_SIG    745                                 IPCC_MPROC_SIGNAL_SMP2P>;
746                                                   746 
747                 qcom,local-pid = <0>;             747                 qcom,local-pid = <0>;
748                 qcom,remote-pid = <5>;            748                 qcom,remote-pid = <5>;
749                                                   749 
750                 smp2p_nsp0_out: master-kernel     750                 smp2p_nsp0_out: master-kernel {
751                         qcom,entry-name = "mas    751                         qcom,entry-name = "master-kernel";
752                         #qcom,smem-state-cells    752                         #qcom,smem-state-cells = <1>;
753                 };                                753                 };
754                                                   754 
755                 smp2p_nsp0_in: slave-kernel {     755                 smp2p_nsp0_in: slave-kernel {
756                         qcom,entry-name = "sla    756                         qcom,entry-name = "slave-kernel";
757                         interrupt-controller;     757                         interrupt-controller;
758                         #interrupt-cells = <2>    758                         #interrupt-cells = <2>;
759                 };                                759                 };
760         };                                        760         };
761                                                   761 
762         smp2p-nsp1 {                              762         smp2p-nsp1 {
763                 compatible = "qcom,smp2p";        763                 compatible = "qcom,smp2p";
764                 qcom,smem = <617>, <616>;         764                 qcom,smem = <617>, <616>;
765                 interrupts-extended = <&ipcc I    765                 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1
766                                              I    766                                              IPCC_MPROC_SIGNAL_SMP2P
767                                              I    767                                              IRQ_TYPE_EDGE_RISING>;
768                 mboxes = <&ipcc IPCC_CLIENT_NS    768                 mboxes = <&ipcc IPCC_CLIENT_NSP1
769                                 IPCC_MPROC_SIG    769                                 IPCC_MPROC_SIGNAL_SMP2P>;
770                                                   770 
771                 qcom,local-pid = <0>;             771                 qcom,local-pid = <0>;
772                 qcom,remote-pid = <12>;           772                 qcom,remote-pid = <12>;
773                                                   773 
774                 smp2p_nsp1_out: master-kernel     774                 smp2p_nsp1_out: master-kernel {
775                         qcom,entry-name = "mas    775                         qcom,entry-name = "master-kernel";
776                         #qcom,smem-state-cells    776                         #qcom,smem-state-cells = <1>;
777                 };                                777                 };
778                                                   778 
779                 smp2p_nsp1_in: slave-kernel {     779                 smp2p_nsp1_in: slave-kernel {
780                         qcom,entry-name = "sla    780                         qcom,entry-name = "slave-kernel";
781                         interrupt-controller;     781                         interrupt-controller;
782                         #interrupt-cells = <2>    782                         #interrupt-cells = <2>;
783                 };                                783                 };
784         };                                        784         };
785                                                   785 
786         soc: soc@0 {                              786         soc: soc@0 {
787                 compatible = "simple-bus";        787                 compatible = "simple-bus";
788                 #address-cells = <2>;             788                 #address-cells = <2>;
789                 #size-cells = <2>;                789                 #size-cells = <2>;
790                 ranges = <0 0 0 0 0x10 0>;        790                 ranges = <0 0 0 0 0x10 0>;
791                 dma-ranges = <0 0 0 0 0x10 0>;    791                 dma-ranges = <0 0 0 0 0x10 0>;
792                                                   792 
793                 ethernet0: ethernet@20000 {       793                 ethernet0: ethernet@20000 {
794                         compatible = "qcom,sc8    794                         compatible = "qcom,sc8280xp-ethqos";
795                         reg = <0x0 0x00020000     795                         reg = <0x0 0x00020000 0x0 0x10000>,
796                               <0x0 0x00036000     796                               <0x0 0x00036000 0x0 0x100>;
797                         reg-names = "stmmaceth    797                         reg-names = "stmmaceth", "rgmii";
798                                                   798 
799                         clocks = <&gcc GCC_EMA    799                         clocks = <&gcc GCC_EMAC0_AXI_CLK>,
800                                  <&gcc GCC_EMA    800                                  <&gcc GCC_EMAC0_SLV_AHB_CLK>,
801                                  <&gcc GCC_EMA    801                                  <&gcc GCC_EMAC0_PTP_CLK>,
802                                  <&gcc GCC_EMA    802                                  <&gcc GCC_EMAC0_RGMII_CLK>;
803                         clock-names = "stmmace    803                         clock-names = "stmmaceth",
804                                       "pclk",     804                                       "pclk",
805                                       "ptp_ref    805                                       "ptp_ref",
806                                       "rgmii";    806                                       "rgmii";
807                                                   807 
808                         interrupts = <GIC_SPI     808                         interrupts = <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>,
809                                      <GIC_SPI     809                                      <GIC_SPI 936 IRQ_TYPE_LEVEL_HIGH>;
810                         interrupt-names = "mac    810                         interrupt-names = "macirq", "eth_lpi";
811                                                   811 
812                         iommus = <&apps_smmu 0    812                         iommus = <&apps_smmu 0x4c0 0xf>;
813                         power-domains = <&gcc     813                         power-domains = <&gcc EMAC_0_GDSC>;
814                                                   814 
815                         snps,tso;                 815                         snps,tso;
816                         snps,pbl = <32>;          816                         snps,pbl = <32>;
817                         rx-fifo-depth = <4096>    817                         rx-fifo-depth = <4096>;
818                         tx-fifo-depth = <4096>    818                         tx-fifo-depth = <4096>;
819                                                   819 
820                         status = "disabled";      820                         status = "disabled";
821                 };                                821                 };
822                                                   822 
823                 gcc: clock-controller@100000 {    823                 gcc: clock-controller@100000 {
824                         compatible = "qcom,gcc    824                         compatible = "qcom,gcc-sc8280xp";
825                         reg = <0x0 0x00100000     825                         reg = <0x0 0x00100000 0x0 0x1f0000>;
826                         #clock-cells = <1>;       826                         #clock-cells = <1>;
827                         #reset-cells = <1>;       827                         #reset-cells = <1>;
828                         #power-domain-cells =     828                         #power-domain-cells = <1>;
829                         clocks = <&rpmhcc RPMH    829                         clocks = <&rpmhcc RPMH_CXO_CLK>,
830                                  <&sleep_clk>,    830                                  <&sleep_clk>,
831                                  <0>,             831                                  <0>,
832                                  <0>,             832                                  <0>,
833                                  <0>,             833                                  <0>,
834                                  <0>,             834                                  <0>,
835                                  <0>,             835                                  <0>,
836                                  <0>,             836                                  <0>,
837                                  <&usb_0_qmpph    837                                  <&usb_0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
838                                  <0>,             838                                  <0>,
839                                  <0>,             839                                  <0>,
840                                  <0>,             840                                  <0>,
841                                  <0>,             841                                  <0>,
842                                  <0>,             842                                  <0>,
843                                  <0>,             843                                  <0>,
844                                  <0>,             844                                  <0>,
845                                  <&usb_1_qmpph    845                                  <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
846                                  <0>,             846                                  <0>,
847                                  <0>,             847                                  <0>,
848                                  <0>,             848                                  <0>,
849                                  <0>,             849                                  <0>,
850                                  <0>,             850                                  <0>,
851                                  <0>,             851                                  <0>,
852                                  <0>,             852                                  <0>,
853                                  <0>,             853                                  <0>,
854                                  <0>,             854                                  <0>,
855                                  <&pcie2a_phy>    855                                  <&pcie2a_phy>,
856                                  <&pcie2b_phy>    856                                  <&pcie2b_phy>,
857                                  <&pcie3a_phy>    857                                  <&pcie3a_phy>,
858                                  <&pcie3b_phy>    858                                  <&pcie3b_phy>,
859                                  <&pcie4_phy>,    859                                  <&pcie4_phy>,
860                                  <0>,             860                                  <0>,
861                                  <0>;             861                                  <0>;
862                         power-domains = <&rpmh    862                         power-domains = <&rpmhpd SC8280XP_CX>;
863                 };                                863                 };
864                                                   864 
865                 ipcc: mailbox@408000 {            865                 ipcc: mailbox@408000 {
866                         compatible = "qcom,sc8    866                         compatible = "qcom,sc8280xp-ipcc", "qcom,ipcc";
867                         reg = <0 0x00408000 0     867                         reg = <0 0x00408000 0 0x1000>;
868                         interrupts = <GIC_SPI     868                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
869                         interrupt-controller;     869                         interrupt-controller;
870                         #interrupt-cells = <3>    870                         #interrupt-cells = <3>;
871                         #mbox-cells = <2>;        871                         #mbox-cells = <2>;
872                 };                                872                 };
873                                                   873 
874                 qfprom: efuse@784000 {            874                 qfprom: efuse@784000 {
875                         compatible = "qcom,sc8    875                         compatible = "qcom,sc8280xp-qfprom", "qcom,qfprom";
876                         reg = <0 0x00784000 0     876                         reg = <0 0x00784000 0 0x3000>;
877                         #address-cells = <1>;     877                         #address-cells = <1>;
878                         #size-cells = <1>;        878                         #size-cells = <1>;
879                                                   879 
880                         gpu_speed_bin: gpu-spe    880                         gpu_speed_bin: gpu-speed-bin@18b {
881                                 reg = <0x18b 0    881                                 reg = <0x18b 0x1>;
882                                 bits = <5 3>;     882                                 bits = <5 3>;
883                         };                        883                         };
884                 };                                884                 };
885                                                   885 
886                 qup2: geniqup@8c0000 {            886                 qup2: geniqup@8c0000 {
887                         compatible = "qcom,gen    887                         compatible = "qcom,geni-se-qup";
888                         reg = <0 0x008c0000 0     888                         reg = <0 0x008c0000 0 0x2000>;
889                         clocks = <&gcc GCC_QUP    889                         clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
890                                  <&gcc GCC_QUP    890                                  <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
891                         clock-names = "m-ahb",    891                         clock-names = "m-ahb", "s-ahb";
892                         iommus = <&apps_smmu 0    892                         iommus = <&apps_smmu 0xa3 0>;
893                                                   893 
894                         #address-cells = <2>;     894                         #address-cells = <2>;
895                         #size-cells = <2>;        895                         #size-cells = <2>;
896                         ranges;                   896                         ranges;
897                                                   897 
898                         status = "disabled";      898                         status = "disabled";
899                                                   899 
900                         i2c16: i2c@880000 {       900                         i2c16: i2c@880000 {
901                                 compatible = "    901                                 compatible = "qcom,geni-i2c";
902                                 reg = <0 0x008    902                                 reg = <0 0x00880000 0 0x4000>;
903                                 #address-cells    903                                 #address-cells = <1>;
904                                 #size-cells =     904                                 #size-cells = <0>;
905                                 clocks = <&gcc    905                                 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
906                                 clock-names =     906                                 clock-names = "se";
907                                 interrupts = <    907                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
908                                 power-domains     908                                 power-domains = <&rpmhpd SC8280XP_CX>;
909                                 interconnects     909                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
910                                                   910                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
911                                                   911                                                 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
912                                 interconnect-n    912                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
913                                 status = "disa    913                                 status = "disabled";
914                         };                        914                         };
915                                                   915 
916                         spi16: spi@880000 {       916                         spi16: spi@880000 {
917                                 compatible = "    917                                 compatible = "qcom,geni-spi";
918                                 reg = <0 0x008    918                                 reg = <0 0x00880000 0 0x4000>;
919                                 #address-cells    919                                 #address-cells = <1>;
920                                 #size-cells =     920                                 #size-cells = <0>;
921                                 clocks = <&gcc    921                                 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
922                                 clock-names =     922                                 clock-names = "se";
923                                 interrupts = <    923                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
924                                 power-domains     924                                 power-domains = <&rpmhpd SC8280XP_CX>;
925                                 interconnects     925                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
926                                                   926                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
927                                                   927                                                 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
928                                 interconnect-n    928                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
929                                 status = "disa    929                                 status = "disabled";
930                         };                        930                         };
931                                                   931 
932                         i2c17: i2c@884000 {       932                         i2c17: i2c@884000 {
933                                 compatible = "    933                                 compatible = "qcom,geni-i2c";
934                                 reg = <0 0x008    934                                 reg = <0 0x00884000 0 0x4000>;
935                                 #address-cells    935                                 #address-cells = <1>;
936                                 #size-cells =     936                                 #size-cells = <0>;
937                                 clocks = <&gcc    937                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
938                                 clock-names =     938                                 clock-names = "se";
939                                 interrupts = <    939                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
940                                 power-domains     940                                 power-domains = <&rpmhpd SC8280XP_CX>;
941                                 interconnects     941                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
942                                                   942                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
943                                                   943                                                 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
944                                 interconnect-n    944                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
945                                 status = "disa    945                                 status = "disabled";
946                         };                        946                         };
947                                                   947 
948                         spi17: spi@884000 {       948                         spi17: spi@884000 {
949                                 compatible = "    949                                 compatible = "qcom,geni-spi";
950                                 reg = <0 0x008    950                                 reg = <0 0x00884000 0 0x4000>;
951                                 #address-cells    951                                 #address-cells = <1>;
952                                 #size-cells =     952                                 #size-cells = <0>;
953                                 clocks = <&gcc    953                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
954                                 clock-names =     954                                 clock-names = "se";
955                                 interrupts = <    955                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
956                                 power-domains     956                                 power-domains = <&rpmhpd SC8280XP_CX>;
957                                 interconnects     957                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
958                                                   958                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
959                                                   959                                                 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
960                                 interconnect-n    960                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
961                                 status = "disa    961                                 status = "disabled";
962                         };                        962                         };
963                                                   963 
964                         uart17: serial@884000     964                         uart17: serial@884000 {
965                                 compatible = "    965                                 compatible = "qcom,geni-uart";
966                                 reg = <0 0x008    966                                 reg = <0 0x00884000 0 0x4000>;
967                                 clocks = <&gcc    967                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
968                                 clock-names =     968                                 clock-names = "se";
969                                 interrupts = <    969                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
970                                 operating-poin    970                                 operating-points-v2 = <&qup_opp_table_100mhz>;
971                                 power-domains     971                                 power-domains = <&rpmhpd SC8280XP_CX>;
972                                 interconnects     972                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
973                                                   973                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>;
974                                 interconnect-n    974                                 interconnect-names = "qup-core", "qup-config";
975                                 status = "disa    975                                 status = "disabled";
976                         };                        976                         };
977                                                   977 
978                         i2c18: i2c@888000 {       978                         i2c18: i2c@888000 {
979                                 compatible = "    979                                 compatible = "qcom,geni-i2c";
980                                 reg = <0 0x008    980                                 reg = <0 0x00888000 0 0x4000>;
981                                 #address-cells    981                                 #address-cells = <1>;
982                                 #size-cells =     982                                 #size-cells = <0>;
983                                 clocks = <&gcc    983                                 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
984                                 clock-names =     984                                 clock-names = "se";
985                                 interrupts = <    985                                 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
986                                 power-domains     986                                 power-domains = <&rpmhpd SC8280XP_CX>;
987                                 interconnects     987                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
988                                                   988                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
989                                                   989                                                 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
990                                 interconnect-n    990                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
991                                 status = "disa    991                                 status = "disabled";
992                         };                        992                         };
993                                                   993 
994                         spi18: spi@888000 {       994                         spi18: spi@888000 {
995                                 compatible = "    995                                 compatible = "qcom,geni-spi";
996                                 reg = <0 0x008    996                                 reg = <0 0x00888000 0 0x4000>;
997                                 #address-cells    997                                 #address-cells = <1>;
998                                 #size-cells =     998                                 #size-cells = <0>;
999                                 clocks = <&gcc    999                                 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1000                                 clock-names =    1000                                 clock-names = "se";
1001                                 interrupts =     1001                                 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1002                                 power-domains    1002                                 power-domains = <&rpmhpd SC8280XP_CX>;
1003                                 interconnects    1003                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1004                                                  1004                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1005                                                  1005                                                 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1006                                 interconnect-    1006                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1007                                 status = "dis    1007                                 status = "disabled";
1008                         };                       1008                         };
1009                                                  1009 
1010                         i2c19: i2c@88c000 {      1010                         i2c19: i2c@88c000 {
1011                                 compatible =     1011                                 compatible = "qcom,geni-i2c";
1012                                 reg = <0 0x00    1012                                 reg = <0 0x0088c000 0 0x4000>;
1013                                 #address-cell    1013                                 #address-cells = <1>;
1014                                 #size-cells =    1014                                 #size-cells = <0>;
1015                                 clocks = <&gc    1015                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1016                                 clock-names =    1016                                 clock-names = "se";
1017                                 interrupts =     1017                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1018                                 power-domains    1018                                 power-domains = <&rpmhpd SC8280XP_CX>;
1019                                 interconnects    1019                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1020                                                  1020                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1021                                                  1021                                                 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1022                                 interconnect-    1022                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1023                                 status = "dis    1023                                 status = "disabled";
1024                         };                       1024                         };
1025                                                  1025 
1026                         spi19: spi@88c000 {      1026                         spi19: spi@88c000 {
1027                                 compatible =     1027                                 compatible = "qcom,geni-spi";
1028                                 reg = <0 0x00    1028                                 reg = <0 0x0088c000 0 0x4000>;
1029                                 #address-cell    1029                                 #address-cells = <1>;
1030                                 #size-cells =    1030                                 #size-cells = <0>;
1031                                 clocks = <&gc    1031                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1032                                 clock-names =    1032                                 clock-names = "se";
1033                                 interrupts =     1033                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1034                                 power-domains    1034                                 power-domains = <&rpmhpd SC8280XP_CX>;
1035                                 interconnects    1035                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1036                                                  1036                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1037                                                  1037                                                 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1038                                 interconnect-    1038                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1039                                 status = "dis    1039                                 status = "disabled";
1040                         };                       1040                         };
1041                                                  1041 
1042                         i2c20: i2c@890000 {      1042                         i2c20: i2c@890000 {
1043                                 compatible =     1043                                 compatible = "qcom,geni-i2c";
1044                                 reg = <0 0x00    1044                                 reg = <0 0x00890000 0 0x4000>;
1045                                 #address-cell    1045                                 #address-cells = <1>;
1046                                 #size-cells =    1046                                 #size-cells = <0>;
1047                                 clocks = <&gc    1047                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1048                                 clock-names =    1048                                 clock-names = "se";
1049                                 interrupts =     1049                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1050                                 power-domains    1050                                 power-domains = <&rpmhpd SC8280XP_CX>;
1051                                 interconnects    1051                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1052                                                  1052                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1053                                                  1053                                                 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1054                                 interconnect-    1054                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1055                                 status = "dis    1055                                 status = "disabled";
1056                         };                       1056                         };
1057                                                  1057 
1058                         spi20: spi@890000 {      1058                         spi20: spi@890000 {
1059                                 compatible =     1059                                 compatible = "qcom,geni-spi";
1060                                 reg = <0 0x00    1060                                 reg = <0 0x00890000 0 0x4000>;
1061                                 #address-cell    1061                                 #address-cells = <1>;
1062                                 #size-cells =    1062                                 #size-cells = <0>;
1063                                 clocks = <&gc    1063                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1064                                 clock-names =    1064                                 clock-names = "se";
1065                                 interrupts =     1065                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1066                                 power-domains    1066                                 power-domains = <&rpmhpd SC8280XP_CX>;
1067                                 interconnects    1067                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1068                                                  1068                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1069                                                  1069                                                 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1070                                 interconnect-    1070                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1071                                 status = "dis    1071                                 status = "disabled";
1072                         };                       1072                         };
1073                                                  1073 
1074                         i2c21: i2c@894000 {      1074                         i2c21: i2c@894000 {
1075                                 compatible =     1075                                 compatible = "qcom,geni-i2c";
1076                                 reg = <0 0x00    1076                                 reg = <0 0x00894000 0 0x4000>;
1077                                 clock-names =    1077                                 clock-names = "se";
1078                                 clocks = <&gc    1078                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1079                                 interrupts =     1079                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1080                                 #address-cell    1080                                 #address-cells = <1>;
1081                                 #size-cells =    1081                                 #size-cells = <0>;
1082                                 power-domains    1082                                 power-domains = <&rpmhpd SC8280XP_CX>;
1083                                 interconnects    1083                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1084                                                  1084                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1085                                                  1085                                                 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1086                                 interconnect-    1086                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1087                                 status = "dis    1087                                 status = "disabled";
1088                         };                       1088                         };
1089                                                  1089 
1090                         spi21: spi@894000 {      1090                         spi21: spi@894000 {
1091                                 compatible =     1091                                 compatible = "qcom,geni-spi";
1092                                 reg = <0 0x00    1092                                 reg = <0 0x00894000 0 0x4000>;
1093                                 #address-cell    1093                                 #address-cells = <1>;
1094                                 #size-cells =    1094                                 #size-cells = <0>;
1095                                 clocks = <&gc    1095                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1096                                 clock-names =    1096                                 clock-names = "se";
1097                                 interrupts =     1097                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1098                                 power-domains    1098                                 power-domains = <&rpmhpd SC8280XP_CX>;
1099                                 interconnects    1099                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1100                                                  1100                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1101                                                  1101                                                 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1102                                 interconnect-    1102                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1103                                 status = "dis    1103                                 status = "disabled";
1104                         };                       1104                         };
1105                                                  1105 
1106                         i2c22: i2c@898000 {      1106                         i2c22: i2c@898000 {
1107                                 compatible =     1107                                 compatible = "qcom,geni-i2c";
1108                                 reg = <0 0x00    1108                                 reg = <0 0x00898000 0 0x4000>;
1109                                 #address-cell    1109                                 #address-cells = <1>;
1110                                 #size-cells =    1110                                 #size-cells = <0>;
1111                                 clock-names =    1111                                 clock-names = "se";
1112                                 clocks = <&gc    1112                                 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1113                                 interrupts =     1113                                 interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>;
1114                                 power-domains    1114                                 power-domains = <&rpmhpd SC8280XP_CX>;
1115                                 interconnects    1115                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1116                                                  1116                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1117                                                  1117                                                 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1118                                 interconnect-    1118                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1119                                 status = "dis    1119                                 status = "disabled";
1120                         };                       1120                         };
1121                                                  1121 
1122                         spi22: spi@898000 {      1122                         spi22: spi@898000 {
1123                                 compatible =     1123                                 compatible = "qcom,geni-spi";
1124                                 reg = <0 0x00    1124                                 reg = <0 0x00898000 0 0x4000>;
1125                                 #address-cell    1125                                 #address-cells = <1>;
1126                                 #size-cells =    1126                                 #size-cells = <0>;
1127                                 clocks = <&gc    1127                                 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1128                                 clock-names =    1128                                 clock-names = "se";
1129                                 interrupts =     1129                                 interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>;
1130                                 power-domains    1130                                 power-domains = <&rpmhpd SC8280XP_CX>;
1131                                 interconnects    1131                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1132                                                  1132                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1133                                                  1133                                                 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1134                                 interconnect-    1134                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1135                                 status = "dis    1135                                 status = "disabled";
1136                         };                       1136                         };
1137                                                  1137 
1138                         i2c23: i2c@89c000 {      1138                         i2c23: i2c@89c000 {
1139                                 compatible =     1139                                 compatible = "qcom,geni-i2c";
1140                                 reg = <0 0x00    1140                                 reg = <0 0x0089c000 0 0x4000>;
1141                                 #address-cell    1141                                 #address-cells = <1>;
1142                                 #size-cells =    1142                                 #size-cells = <0>;
1143                                 clock-names =    1143                                 clock-names = "se";
1144                                 clocks = <&gc    1144                                 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
1145                                 interrupts =     1145                                 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>;
1146                                 power-domains    1146                                 power-domains = <&rpmhpd SC8280XP_CX>;
1147                                 interconnects    1147                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1148                                                  1148                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1149                                                  1149                                                 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1150                                 interconnect-    1150                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1151                                 status = "dis    1151                                 status = "disabled";
1152                         };                       1152                         };
1153                                                  1153 
1154                         spi23: spi@89c000 {      1154                         spi23: spi@89c000 {
1155                                 compatible =     1155                                 compatible = "qcom,geni-spi";
1156                                 reg = <0 0x00    1156                                 reg = <0 0x0089c000 0 0x4000>;
1157                                 #address-cell    1157                                 #address-cells = <1>;
1158                                 #size-cells =    1158                                 #size-cells = <0>;
1159                                 clocks = <&gc    1159                                 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
1160                                 clock-names =    1160                                 clock-names = "se";
1161                                 interrupts =     1161                                 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>;
1162                                 power-domains    1162                                 power-domains = <&rpmhpd SC8280XP_CX>;
1163                                 interconnects    1163                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1164                                                  1164                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1165                                                  1165                                                 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1166                                 interconnect-    1166                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1167                                 status = "dis    1167                                 status = "disabled";
1168                         };                       1168                         };
1169                 };                               1169                 };
1170                                                  1170 
1171                 qup0: geniqup@9c0000 {           1171                 qup0: geniqup@9c0000 {
1172                         compatible = "qcom,ge    1172                         compatible = "qcom,geni-se-qup";
1173                         reg = <0 0x009c0000 0    1173                         reg = <0 0x009c0000 0 0x6000>;
1174                         clocks = <&gcc GCC_QU    1174                         clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1175                                  <&gcc GCC_QU    1175                                  <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1176                         clock-names = "m-ahb"    1176                         clock-names = "m-ahb", "s-ahb";
1177                         iommus = <&apps_smmu     1177                         iommus = <&apps_smmu 0x563 0>;
1178                                                  1178 
1179                         #address-cells = <2>;    1179                         #address-cells = <2>;
1180                         #size-cells = <2>;       1180                         #size-cells = <2>;
1181                         ranges;                  1181                         ranges;
1182                                                  1182 
1183                         status = "disabled";     1183                         status = "disabled";
1184                                                  1184 
1185                         i2c0: i2c@980000 {       1185                         i2c0: i2c@980000 {
1186                                 compatible =     1186                                 compatible = "qcom,geni-i2c";
1187                                 reg = <0 0x00    1187                                 reg = <0 0x00980000 0 0x4000>;
1188                                 #address-cell    1188                                 #address-cells = <1>;
1189                                 #size-cells =    1189                                 #size-cells = <0>;
1190                                 clock-names =    1190                                 clock-names = "se";
1191                                 clocks = <&gc    1191                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1192                                 interrupts =     1192                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1193                                 power-domains    1193                                 power-domains = <&rpmhpd SC8280XP_CX>;
1194                                 interconnects    1194                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1195                                                  1195                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1196                                                  1196                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1197                                 interconnect-    1197                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1198                                 status = "dis    1198                                 status = "disabled";
1199                         };                       1199                         };
1200                                                  1200 
1201                         spi0: spi@980000 {       1201                         spi0: spi@980000 {
1202                                 compatible =     1202                                 compatible = "qcom,geni-spi";
1203                                 reg = <0 0x00    1203                                 reg = <0 0x00980000 0 0x4000>;
1204                                 #address-cell    1204                                 #address-cells = <1>;
1205                                 #size-cells =    1205                                 #size-cells = <0>;
1206                                 clocks = <&gc    1206                                 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1207                                 clock-names =    1207                                 clock-names = "se";
1208                                 interrupts =     1208                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1209                                 power-domains    1209                                 power-domains = <&rpmhpd SC8280XP_CX>;
1210                                 interconnects    1210                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1211                                                  1211                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1212                                                  1212                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1213                                 interconnect-    1213                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1214                                 status = "dis    1214                                 status = "disabled";
1215                         };                       1215                         };
1216                                                  1216 
1217                         i2c1: i2c@984000 {       1217                         i2c1: i2c@984000 {
1218                                 compatible =     1218                                 compatible = "qcom,geni-i2c";
1219                                 reg = <0 0x00    1219                                 reg = <0 0x00984000 0 0x4000>;
1220                                 #address-cell    1220                                 #address-cells = <1>;
1221                                 #size-cells =    1221                                 #size-cells = <0>;
1222                                 clock-names =    1222                                 clock-names = "se";
1223                                 clocks = <&gc    1223                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1224                                 interrupts =     1224                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1225                                 power-domains    1225                                 power-domains = <&rpmhpd SC8280XP_CX>;
1226                                 interconnects    1226                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1227                                                  1227                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1228                                                  1228                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1229                                 interconnect-    1229                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1230                                 status = "dis    1230                                 status = "disabled";
1231                         };                       1231                         };
1232                                                  1232 
1233                         spi1: spi@984000 {       1233                         spi1: spi@984000 {
1234                                 compatible =     1234                                 compatible = "qcom,geni-spi";
1235                                 reg = <0 0x00    1235                                 reg = <0 0x00984000 0 0x4000>;
1236                                 #address-cell    1236                                 #address-cells = <1>;
1237                                 #size-cells =    1237                                 #size-cells = <0>;
1238                                 clocks = <&gc    1238                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1239                                 clock-names =    1239                                 clock-names = "se";
1240                                 interrupts =     1240                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1241                                 power-domains    1241                                 power-domains = <&rpmhpd SC8280XP_CX>;
1242                                 interconnects    1242                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1243                                                  1243                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1244                                                  1244                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1245                                 interconnect-    1245                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1246                                 status = "dis    1246                                 status = "disabled";
1247                         };                       1247                         };
1248                                                  1248 
1249                         i2c2: i2c@988000 {       1249                         i2c2: i2c@988000 {
1250                                 compatible =     1250                                 compatible = "qcom,geni-i2c";
1251                                 reg = <0 0x00    1251                                 reg = <0 0x00988000 0 0x4000>;
1252                                 #address-cell    1252                                 #address-cells = <1>;
1253                                 #size-cells =    1253                                 #size-cells = <0>;
1254                                 clock-names =    1254                                 clock-names = "se";
1255                                 clocks = <&gc    1255                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1256                                 interrupts =     1256                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1257                                 power-domains    1257                                 power-domains = <&rpmhpd SC8280XP_CX>;
1258                                 interconnects    1258                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1259                                                  1259                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1260                                                  1260                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1261                                 interconnect-    1261                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1262                                 status = "dis    1262                                 status = "disabled";
1263                         };                       1263                         };
1264                                                  1264 
1265                         spi2: spi@988000 {       1265                         spi2: spi@988000 {
1266                                 compatible =     1266                                 compatible = "qcom,geni-spi";
1267                                 reg = <0 0x00    1267                                 reg = <0 0x00988000 0 0x4000>;
1268                                 #address-cell    1268                                 #address-cells = <1>;
1269                                 #size-cells =    1269                                 #size-cells = <0>;
1270                                 clocks = <&gc    1270                                 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1271                                 clock-names =    1271                                 clock-names = "se";
1272                                 interrupts =     1272                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1273                                 power-domains    1273                                 power-domains = <&rpmhpd SC8280XP_CX>;
1274                                 interconnects    1274                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1275                                                  1275                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1276                                                  1276                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1277                                 interconnect-    1277                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1278                                 status = "dis    1278                                 status = "disabled";
1279                         };                       1279                         };
1280                                                  1280 
1281                         uart2: serial@988000     1281                         uart2: serial@988000 {
1282                                 compatible =     1282                                 compatible = "qcom,geni-uart";
1283                                 reg = <0 0x00    1283                                 reg = <0 0x00988000 0 0x4000>;
1284                                 clocks = <&gc    1284                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1285                                 clock-names =    1285                                 clock-names = "se";
1286                                 interrupts =     1286                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1287                                 operating-poi    1287                                 operating-points-v2 = <&qup_opp_table_100mhz>;
1288                                 power-domains    1288                                 power-domains = <&rpmhpd SC8280XP_CX>;
1289                                 interconnects    1289                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1290                                                  1290                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1291                                 interconnect-    1291                                 interconnect-names = "qup-core", "qup-config";
1292                                 status = "dis    1292                                 status = "disabled";
1293                         };                       1293                         };
1294                                                  1294 
1295                         i2c3: i2c@98c000 {       1295                         i2c3: i2c@98c000 {
1296                                 compatible =     1296                                 compatible = "qcom,geni-i2c";
1297                                 reg = <0 0x00    1297                                 reg = <0 0x0098c000 0 0x4000>;
1298                                 #address-cell    1298                                 #address-cells = <1>;
1299                                 #size-cells =    1299                                 #size-cells = <0>;
1300                                 clock-names =    1300                                 clock-names = "se";
1301                                 clocks = <&gc    1301                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1302                                 interrupts =     1302                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1303                                 power-domains    1303                                 power-domains = <&rpmhpd SC8280XP_CX>;
1304                                 interconnects    1304                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1305                                                  1305                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1306                                                  1306                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1307                                 interconnect-    1307                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1308                                 status = "dis    1308                                 status = "disabled";
1309                         };                       1309                         };
1310                                                  1310 
1311                         spi3: spi@98c000 {       1311                         spi3: spi@98c000 {
1312                                 compatible =     1312                                 compatible = "qcom,geni-spi";
1313                                 reg = <0 0x00    1313                                 reg = <0 0x0098c000 0 0x4000>;
1314                                 #address-cell    1314                                 #address-cells = <1>;
1315                                 #size-cells =    1315                                 #size-cells = <0>;
1316                                 clocks = <&gc    1316                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1317                                 clock-names =    1317                                 clock-names = "se";
1318                                 interrupts =     1318                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1319                                 power-domains    1319                                 power-domains = <&rpmhpd SC8280XP_CX>;
1320                                 interconnects    1320                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1321                                                  1321                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1322                                                  1322                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1323                                 interconnect-    1323                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1324                                 status = "dis    1324                                 status = "disabled";
1325                         };                       1325                         };
1326                                                  1326 
1327                         i2c4: i2c@990000 {       1327                         i2c4: i2c@990000 {
1328                                 compatible =     1328                                 compatible = "qcom,geni-i2c";
1329                                 reg = <0 0x00    1329                                 reg = <0 0x00990000 0 0x4000>;
1330                                 clock-names =    1330                                 clock-names = "se";
1331                                 clocks = <&gc    1331                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1332                                 interrupts =     1332                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1333                                 #address-cell    1333                                 #address-cells = <1>;
1334                                 #size-cells =    1334                                 #size-cells = <0>;
1335                                 power-domains    1335                                 power-domains = <&rpmhpd SC8280XP_CX>;
1336                                 interconnects    1336                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1337                                                  1337                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1338                                                  1338                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1339                                 interconnect-    1339                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1340                                 status = "dis    1340                                 status = "disabled";
1341                         };                       1341                         };
1342                                                  1342 
1343                         spi4: spi@990000 {       1343                         spi4: spi@990000 {
1344                                 compatible =     1344                                 compatible = "qcom,geni-spi";
1345                                 reg = <0 0x00    1345                                 reg = <0 0x00990000 0 0x4000>;
1346                                 #address-cell    1346                                 #address-cells = <1>;
1347                                 #size-cells =    1347                                 #size-cells = <0>;
1348                                 clocks = <&gc    1348                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1349                                 clock-names =    1349                                 clock-names = "se";
1350                                 interrupts =     1350                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1351                                 power-domains    1351                                 power-domains = <&rpmhpd SC8280XP_CX>;
1352                                 interconnects    1352                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1353                                                  1353                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1354                                                  1354                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1355                                 interconnect-    1355                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1356                                 status = "dis    1356                                 status = "disabled";
1357                         };                       1357                         };
1358                                                  1358 
1359                         i2c5: i2c@994000 {       1359                         i2c5: i2c@994000 {
1360                                 compatible =     1360                                 compatible = "qcom,geni-i2c";
1361                                 reg = <0 0x00    1361                                 reg = <0 0x00994000 0 0x4000>;
1362                                 #address-cell    1362                                 #address-cells = <1>;
1363                                 #size-cells =    1363                                 #size-cells = <0>;
1364                                 clock-names =    1364                                 clock-names = "se";
1365                                 clocks = <&gc    1365                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1366                                 interrupts =     1366                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1367                                 power-domains    1367                                 power-domains = <&rpmhpd SC8280XP_CX>;
1368                                 interconnects    1368                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1369                                                  1369                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1370                                                  1370                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1371                                 interconnect-    1371                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1372                                 status = "dis    1372                                 status = "disabled";
1373                         };                       1373                         };
1374                                                  1374 
1375                         spi5: spi@994000 {       1375                         spi5: spi@994000 {
1376                                 compatible =     1376                                 compatible = "qcom,geni-spi";
1377                                 reg = <0 0x00    1377                                 reg = <0 0x00994000 0 0x4000>;
1378                                 #address-cell    1378                                 #address-cells = <1>;
1379                                 #size-cells =    1379                                 #size-cells = <0>;
1380                                 clocks = <&gc    1380                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1381                                 clock-names =    1381                                 clock-names = "se";
1382                                 interrupts =     1382                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1383                                 power-domains    1383                                 power-domains = <&rpmhpd SC8280XP_CX>;
1384                                 interconnects    1384                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1385                                                  1385                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1386                                                  1386                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1387                                 interconnect-    1387                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1388                                 status = "dis    1388                                 status = "disabled";
1389                         };                       1389                         };
1390                                                  1390 
1391                         i2c6: i2c@998000 {       1391                         i2c6: i2c@998000 {
1392                                 compatible =     1392                                 compatible = "qcom,geni-i2c";
1393                                 reg = <0 0x00    1393                                 reg = <0 0x00998000 0 0x4000>;
1394                                 #address-cell    1394                                 #address-cells = <1>;
1395                                 #size-cells =    1395                                 #size-cells = <0>;
1396                                 clock-names =    1396                                 clock-names = "se";
1397                                 clocks = <&gc    1397                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1398                                 interrupts =     1398                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1399                                 power-domains    1399                                 power-domains = <&rpmhpd SC8280XP_CX>;
1400                                 interconnects    1400                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1401                                                  1401                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1402                                                  1402                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1403                                 interconnect-    1403                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1404                                 status = "dis    1404                                 status = "disabled";
1405                         };                       1405                         };
1406                                                  1406 
1407                         spi6: spi@998000 {       1407                         spi6: spi@998000 {
1408                                 compatible =     1408                                 compatible = "qcom,geni-spi";
1409                                 reg = <0 0x00    1409                                 reg = <0 0x00998000 0 0x4000>;
1410                                 #address-cell    1410                                 #address-cells = <1>;
1411                                 #size-cells =    1411                                 #size-cells = <0>;
1412                                 clocks = <&gc    1412                                 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1413                                 clock-names =    1413                                 clock-names = "se";
1414                                 interrupts =     1414                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1415                                 power-domains    1415                                 power-domains = <&rpmhpd SC8280XP_CX>;
1416                                 interconnects    1416                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1417                                                  1417                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1418                                                  1418                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1419                                 interconnect-    1419                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1420                                 status = "dis    1420                                 status = "disabled";
1421                         };                       1421                         };
1422                                                  1422 
1423                         i2c7: i2c@99c000 {       1423                         i2c7: i2c@99c000 {
1424                                 compatible =     1424                                 compatible = "qcom,geni-i2c";
1425                                 reg = <0 0x00    1425                                 reg = <0 0x0099c000 0 0x4000>;
1426                                 #address-cell    1426                                 #address-cells = <1>;
1427                                 #size-cells =    1427                                 #size-cells = <0>;
1428                                 clock-names =    1428                                 clock-names = "se";
1429                                 clocks = <&gc    1429                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1430                                 interrupts =     1430                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1431                                 power-domains    1431                                 power-domains = <&rpmhpd SC8280XP_CX>;
1432                                 interconnects    1432                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1433                                                  1433                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1434                                                  1434                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1435                                 interconnect-    1435                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1436                                 status = "dis    1436                                 status = "disabled";
1437                         };                       1437                         };
1438                                                  1438 
1439                         spi7: spi@99c000 {       1439                         spi7: spi@99c000 {
1440                                 compatible =     1440                                 compatible = "qcom,geni-spi";
1441                                 reg = <0 0x00    1441                                 reg = <0 0x0099c000 0 0x4000>;
1442                                 #address-cell    1442                                 #address-cells = <1>;
1443                                 #size-cells =    1443                                 #size-cells = <0>;
1444                                 clocks = <&gc    1444                                 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
1445                                 clock-names =    1445                                 clock-names = "se";
1446                                 interrupts =     1446                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1447                                 power-domains    1447                                 power-domains = <&rpmhpd SC8280XP_CX>;
1448                                 interconnects    1448                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1449                                                  1449                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1450                                                  1450                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1451                                 interconnect-    1451                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1452                                 status = "dis    1452                                 status = "disabled";
1453                         };                       1453                         };
1454                 };                               1454                 };
1455                                                  1455 
1456                 qup1: geniqup@ac0000 {           1456                 qup1: geniqup@ac0000 {
1457                         compatible = "qcom,ge    1457                         compatible = "qcom,geni-se-qup";
1458                         reg = <0 0x00ac0000 0    1458                         reg = <0 0x00ac0000 0 0x6000>;
1459                         clocks = <&gcc GCC_QU    1459                         clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1460                                  <&gcc GCC_QU    1460                                  <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1461                         clock-names = "m-ahb"    1461                         clock-names = "m-ahb", "s-ahb";
1462                         iommus = <&apps_smmu     1462                         iommus = <&apps_smmu 0x83 0>;
1463                                                  1463 
1464                         #address-cells = <2>;    1464                         #address-cells = <2>;
1465                         #size-cells = <2>;       1465                         #size-cells = <2>;
1466                         ranges;                  1466                         ranges;
1467                                                  1467 
1468                         status = "disabled";     1468                         status = "disabled";
1469                                                  1469 
1470                         i2c8: i2c@a80000 {       1470                         i2c8: i2c@a80000 {
1471                                 compatible =     1471                                 compatible = "qcom,geni-i2c";
1472                                 reg = <0 0x00    1472                                 reg = <0 0x00a80000 0 0x4000>;
1473                                 #address-cell    1473                                 #address-cells = <1>;
1474                                 #size-cells =    1474                                 #size-cells = <0>;
1475                                 clocks = <&gc    1475                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1476                                 clock-names =    1476                                 clock-names = "se";
1477                                 interrupts =     1477                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1478                                 power-domains    1478                                 power-domains = <&rpmhpd SC8280XP_CX>;
1479                                 interconnects    1479                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1480                                                  1480                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1481                                                  1481                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1482                                 interconnect-    1482                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1483                                 status = "dis    1483                                 status = "disabled";
1484                         };                       1484                         };
1485                                                  1485 
1486                         spi8: spi@a80000 {       1486                         spi8: spi@a80000 {
1487                                 compatible =     1487                                 compatible = "qcom,geni-spi";
1488                                 reg = <0 0x00    1488                                 reg = <0 0x00a80000 0 0x4000>;
1489                                 #address-cell    1489                                 #address-cells = <1>;
1490                                 #size-cells =    1490                                 #size-cells = <0>;
1491                                 clocks = <&gc    1491                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1492                                 clock-names =    1492                                 clock-names = "se";
1493                                 interrupts =     1493                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1494                                 power-domains    1494                                 power-domains = <&rpmhpd SC8280XP_CX>;
1495                                 interconnects    1495                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1496                                                  1496                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1497                                                  1497                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1498                                 interconnect-    1498                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1499                                 status = "dis    1499                                 status = "disabled";
1500                         };                       1500                         };
1501                                                  1501 
1502                         i2c9: i2c@a84000 {       1502                         i2c9: i2c@a84000 {
1503                                 compatible =     1503                                 compatible = "qcom,geni-i2c";
1504                                 reg = <0 0x00    1504                                 reg = <0 0x00a84000 0 0x4000>;
1505                                 #address-cell    1505                                 #address-cells = <1>;
1506                                 #size-cells =    1506                                 #size-cells = <0>;
1507                                 clocks = <&gc    1507                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1508                                 clock-names =    1508                                 clock-names = "se";
1509                                 interrupts =     1509                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1510                                 power-domains    1510                                 power-domains = <&rpmhpd SC8280XP_CX>;
1511                                 interconnects    1511                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1512                                                  1512                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1513                                                  1513                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1514                                 interconnect-    1514                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1515                                 status = "dis    1515                                 status = "disabled";
1516                         };                       1516                         };
1517                                                  1517 
1518                         spi9: spi@a84000 {       1518                         spi9: spi@a84000 {
1519                                 compatible =     1519                                 compatible = "qcom,geni-spi";
1520                                 reg = <0 0x00    1520                                 reg = <0 0x00a84000 0 0x4000>;
1521                                 #address-cell    1521                                 #address-cells = <1>;
1522                                 #size-cells =    1522                                 #size-cells = <0>;
1523                                 clocks = <&gc    1523                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1524                                 clock-names =    1524                                 clock-names = "se";
1525                                 interrupts =     1525                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1526                                 power-domains    1526                                 power-domains = <&rpmhpd SC8280XP_CX>;
1527                                 interconnects    1527                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1528                                                  1528                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1529                                                  1529                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1530                                 interconnect-    1530                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1531                                 status = "dis    1531                                 status = "disabled";
1532                         };                       1532                         };
1533                                                  1533 
1534                         i2c10: i2c@a88000 {      1534                         i2c10: i2c@a88000 {
1535                                 compatible =     1535                                 compatible = "qcom,geni-i2c";
1536                                 reg = <0 0x00    1536                                 reg = <0 0x00a88000 0 0x4000>;
1537                                 #address-cell    1537                                 #address-cells = <1>;
1538                                 #size-cells =    1538                                 #size-cells = <0>;
1539                                 clocks = <&gc    1539                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1540                                 clock-names =    1540                                 clock-names = "se";
1541                                 interrupts =     1541                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1542                                 power-domains    1542                                 power-domains = <&rpmhpd SC8280XP_CX>;
1543                                 interconnects    1543                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1544                                                  1544                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1545                                                  1545                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1546                                 interconnect-    1546                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1547                                 status = "dis    1547                                 status = "disabled";
1548                         };                       1548                         };
1549                                                  1549 
1550                         spi10: spi@a88000 {      1550                         spi10: spi@a88000 {
1551                                 compatible =     1551                                 compatible = "qcom,geni-spi";
1552                                 reg = <0 0x00    1552                                 reg = <0 0x00a88000 0 0x4000>;
1553                                 #address-cell    1553                                 #address-cells = <1>;
1554                                 #size-cells =    1554                                 #size-cells = <0>;
1555                                 clocks = <&gc    1555                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1556                                 clock-names =    1556                                 clock-names = "se";
1557                                 interrupts =     1557                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1558                                 power-domains    1558                                 power-domains = <&rpmhpd SC8280XP_CX>;
1559                                 interconnects    1559                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1560                                                  1560                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1561                                                  1561                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1562                                 interconnect-    1562                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1563                                 status = "dis    1563                                 status = "disabled";
1564                         };                       1564                         };
1565                                                  1565 
1566                         i2c11: i2c@a8c000 {      1566                         i2c11: i2c@a8c000 {
1567                                 compatible =     1567                                 compatible = "qcom,geni-i2c";
1568                                 reg = <0 0x00    1568                                 reg = <0 0x00a8c000 0 0x4000>;
1569                                 #address-cell    1569                                 #address-cells = <1>;
1570                                 #size-cells =    1570                                 #size-cells = <0>;
1571                                 clocks = <&gc    1571                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1572                                 clock-names =    1572                                 clock-names = "se";
1573                                 interrupts =     1573                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1574                                 power-domains    1574                                 power-domains = <&rpmhpd SC8280XP_CX>;
1575                                 interconnects    1575                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1576                                                  1576                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1577                                                  1577                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1578                                 interconnect-    1578                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1579                                 status = "dis    1579                                 status = "disabled";
1580                         };                       1580                         };
1581                                                  1581 
1582                         spi11: spi@a8c000 {      1582                         spi11: spi@a8c000 {
1583                                 compatible =     1583                                 compatible = "qcom,geni-spi";
1584                                 reg = <0 0x00    1584                                 reg = <0 0x00a8c000 0 0x4000>;
1585                                 #address-cell    1585                                 #address-cells = <1>;
1586                                 #size-cells =    1586                                 #size-cells = <0>;
1587                                 clocks = <&gc    1587                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1588                                 clock-names =    1588                                 clock-names = "se";
1589                                 interrupts =     1589                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1590                                 power-domains    1590                                 power-domains = <&rpmhpd SC8280XP_CX>;
1591                                 interconnects    1591                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1592                                                  1592                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1593                                                  1593                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1594                                 interconnect-    1594                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1595                                 status = "dis    1595                                 status = "disabled";
1596                         };                       1596                         };
1597                                                  1597 
1598                         i2c12: i2c@a90000 {      1598                         i2c12: i2c@a90000 {
1599                                 compatible =     1599                                 compatible = "qcom,geni-i2c";
1600                                 reg = <0 0x00    1600                                 reg = <0 0x00a90000 0 0x4000>;
1601                                 #address-cell    1601                                 #address-cells = <1>;
1602                                 #size-cells =    1602                                 #size-cells = <0>;
1603                                 clocks = <&gc    1603                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1604                                 clock-names =    1604                                 clock-names = "se";
1605                                 interrupts =     1605                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1606                                 power-domains    1606                                 power-domains = <&rpmhpd SC8280XP_CX>;
1607                                 interconnects    1607                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1608                                                  1608                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1609                                                  1609                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1610                                 interconnect-    1610                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1611                                 status = "dis    1611                                 status = "disabled";
1612                         };                       1612                         };
1613                                                  1613 
1614                         spi12: spi@a90000 {      1614                         spi12: spi@a90000 {
1615                                 compatible =     1615                                 compatible = "qcom,geni-spi";
1616                                 reg = <0 0x00    1616                                 reg = <0 0x00a90000 0 0x4000>;
1617                                 #address-cell    1617                                 #address-cells = <1>;
1618                                 #size-cells =    1618                                 #size-cells = <0>;
1619                                 clocks = <&gc    1619                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1620                                 clock-names =    1620                                 clock-names = "se";
1621                                 interrupts =     1621                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1622                                 power-domains    1622                                 power-domains = <&rpmhpd SC8280XP_CX>;
1623                                 interconnects    1623                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1624                                                  1624                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1625                                                  1625                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1626                                 interconnect-    1626                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1627                                 status = "dis    1627                                 status = "disabled";
1628                         };                       1628                         };
1629                                                  1629 
1630                         i2c13: i2c@a94000 {      1630                         i2c13: i2c@a94000 {
1631                                 compatible =     1631                                 compatible = "qcom,geni-i2c";
1632                                 reg = <0 0x00    1632                                 reg = <0 0x00a94000 0 0x4000>;
1633                                 #address-cell    1633                                 #address-cells = <1>;
1634                                 #size-cells =    1634                                 #size-cells = <0>;
1635                                 clocks = <&gc    1635                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1636                                 clock-names =    1636                                 clock-names = "se";
1637                                 interrupts =     1637                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1638                                 power-domains    1638                                 power-domains = <&rpmhpd SC8280XP_CX>;
1639                                 interconnects    1639                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1640                                                  1640                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1641                                                  1641                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1642                                 interconnect-    1642                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1643                                 status = "dis    1643                                 status = "disabled";
1644                         };                       1644                         };
1645                                                  1645 
1646                         spi13: spi@a94000 {      1646                         spi13: spi@a94000 {
1647                                 compatible =     1647                                 compatible = "qcom,geni-spi";
1648                                 reg = <0 0x00    1648                                 reg = <0 0x00a94000 0 0x4000>;
1649                                 #address-cell    1649                                 #address-cells = <1>;
1650                                 #size-cells =    1650                                 #size-cells = <0>;
1651                                 clocks = <&gc    1651                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1652                                 clock-names =    1652                                 clock-names = "se";
1653                                 interrupts =     1653                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1654                                 power-domains    1654                                 power-domains = <&rpmhpd SC8280XP_CX>;
1655                                 interconnects    1655                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1656                                                  1656                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1657                                                  1657                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1658                                 interconnect-    1658                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1659                                 status = "dis    1659                                 status = "disabled";
1660                         };                       1660                         };
1661                                                  1661 
1662                         i2c14: i2c@a98000 {      1662                         i2c14: i2c@a98000 {
1663                                 compatible =     1663                                 compatible = "qcom,geni-i2c";
1664                                 reg = <0 0x00    1664                                 reg = <0 0x00a98000 0 0x4000>;
1665                                 #address-cell    1665                                 #address-cells = <1>;
1666                                 #size-cells =    1666                                 #size-cells = <0>;
1667                                 clocks = <&gc    1667                                 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1668                                 clock-names =    1668                                 clock-names = "se";
1669                                 interrupts =     1669                                 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>;
1670                                 power-domains    1670                                 power-domains = <&rpmhpd SC8280XP_CX>;
1671                                 interconnects    1671                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1672                                                  1672                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1673                                                  1673                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1674                                 interconnect-    1674                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1675                                 status = "dis    1675                                 status = "disabled";
1676                         };                       1676                         };
1677                                                  1677 
1678                         spi14: spi@a98000 {      1678                         spi14: spi@a98000 {
1679                                 compatible =     1679                                 compatible = "qcom,geni-spi";
1680                                 reg = <0 0x00    1680                                 reg = <0 0x00a98000 0 0x4000>;
1681                                 #address-cell    1681                                 #address-cells = <1>;
1682                                 #size-cells =    1682                                 #size-cells = <0>;
1683                                 clocks = <&gc    1683                                 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1684                                 clock-names =    1684                                 clock-names = "se";
1685                                 interrupts =     1685                                 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>;
1686                                 power-domains    1686                                 power-domains = <&rpmhpd SC8280XP_CX>;
1687                                 interconnects    1687                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1688                                                  1688                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1689                                                  1689                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1690                                 interconnect-    1690                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1691                                 status = "dis    1691                                 status = "disabled";
1692                         };                       1692                         };
1693                                                  1693 
1694                         i2c15: i2c@a9c000 {      1694                         i2c15: i2c@a9c000 {
1695                                 compatible =     1695                                 compatible = "qcom,geni-i2c";
1696                                 reg = <0 0x00    1696                                 reg = <0 0x00a9c000 0 0x4000>;
1697                                 #address-cell    1697                                 #address-cells = <1>;
1698                                 #size-cells =    1698                                 #size-cells = <0>;
1699                                 clocks = <&gc    1699                                 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1700                                 clock-names =    1700                                 clock-names = "se";
1701                                 interrupts =     1701                                 interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
1702                                 power-domains    1702                                 power-domains = <&rpmhpd SC8280XP_CX>;
1703                                 interconnects    1703                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1704                                                  1704                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1705                                                  1705                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1706                                 interconnect-    1706                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1707                                 status = "dis    1707                                 status = "disabled";
1708                         };                       1708                         };
1709                                                  1709 
1710                         spi15: spi@a9c000 {      1710                         spi15: spi@a9c000 {
1711                                 compatible =     1711                                 compatible = "qcom,geni-spi";
1712                                 reg = <0 0x00    1712                                 reg = <0 0x00a9c000 0 0x4000>;
1713                                 #address-cell    1713                                 #address-cells = <1>;
1714                                 #size-cells =    1714                                 #size-cells = <0>;
1715                                 clocks = <&gc    1715                                 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1716                                 clock-names =    1716                                 clock-names = "se";
1717                                 interrupts =     1717                                 interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
1718                                 power-domains    1718                                 power-domains = <&rpmhpd SC8280XP_CX>;
1719                                 interconnects    1719                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1720                                                  1720                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1721                                                  1721                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1722                                 interconnect-    1722                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1723                                 status = "dis    1723                                 status = "disabled";
1724                         };                       1724                         };
1725                 };                               1725                 };
1726                                                  1726 
1727                 rng: rng@10d3000 {               1727                 rng: rng@10d3000 {
1728                         compatible = "qcom,pr    1728                         compatible = "qcom,prng-ee";
1729                         reg = <0 0x010d3000 0    1729                         reg = <0 0x010d3000 0 0x1000>;
1730                         clocks = <&rpmhcc RPM    1730                         clocks = <&rpmhcc RPMH_HWKM_CLK>;
1731                         clock-names = "core";    1731                         clock-names = "core";
1732                 };                               1732                 };
1733                                                  1733 
1734                 pcie4: pcie@1c00000 {            1734                 pcie4: pcie@1c00000 {
1735                         device_type = "pci";     1735                         device_type = "pci";
1736                         compatible = "qcom,pc    1736                         compatible = "qcom,pcie-sc8280xp";
1737                         reg = <0x0 0x01c00000    1737                         reg = <0x0 0x01c00000 0x0 0x3000>,
1738                               <0x0 0x30000000    1738                               <0x0 0x30000000 0x0 0xf1d>,
1739                               <0x0 0x30000f20    1739                               <0x0 0x30000f20 0x0 0xa8>,
1740                               <0x0 0x30001000    1740                               <0x0 0x30001000 0x0 0x1000>,
1741                               <0x0 0x30100000    1741                               <0x0 0x30100000 0x0 0x100000>,
1742                               <0x0 0x01c03000    1742                               <0x0 0x01c03000 0x0 0x1000>;
1743                         reg-names = "parf", "    1743                         reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
1744                         #address-cells = <3>;    1744                         #address-cells = <3>;
1745                         #size-cells = <2>;       1745                         #size-cells = <2>;
1746                         ranges = <0x01000000     1746                         ranges = <0x01000000 0x0 0x00000000 0x0 0x30200000 0x0 0x100000>,
1747                                  <0x02000000     1747                                  <0x02000000 0x0 0x30300000 0x0 0x30300000 0x0 0x1d00000>;
1748                         bus-range = <0x00 0xf    1748                         bus-range = <0x00 0xff>;
1749                                                  1749 
1750                         dma-coherent;            1750                         dma-coherent;
1751                                                  1751 
1752                         linux,pci-domain = <6    1752                         linux,pci-domain = <6>;
1753                         num-lanes = <1>;         1753                         num-lanes = <1>;
1754                                                  1754 
1755                         msi-map = <0x0 &its 0    1755                         msi-map = <0x0 &its 0xe0000 0x10000>;
1756                                                  1756 
1757                         interrupts = <GIC_SPI    1757                         interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
1758                                      <GIC_SPI    1758                                      <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
1759                                      <GIC_SPI    1759                                      <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
1760                                      <GIC_SPI    1760                                      <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
1761                         interrupt-names = "ms    1761                         interrupt-names = "msi0", "msi1", "msi2", "msi3";
1762                                                  1762 
1763                         #interrupt-cells = <1    1763                         #interrupt-cells = <1>;
1764                         interrupt-map-mask =     1764                         interrupt-map-mask = <0 0 0 0x7>;
1765                         interrupt-map = <0 0     1765                         interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
1766                                         <0 0     1766                                         <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
1767                                         <0 0     1767                                         <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
1768                                         <0 0     1768                                         <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
1769                                                  1769 
1770                         clocks = <&gcc GCC_PC    1770                         clocks = <&gcc GCC_PCIE_4_AUX_CLK>,
1771                                  <&gcc GCC_PC    1771                                  <&gcc GCC_PCIE_4_CFG_AHB_CLK>,
1772                                  <&gcc GCC_PC    1772                                  <&gcc GCC_PCIE_4_MSTR_AXI_CLK>,
1773                                  <&gcc GCC_PC    1773                                  <&gcc GCC_PCIE_4_SLV_AXI_CLK>,
1774                                  <&gcc GCC_PC    1774                                  <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>,
1775                                  <&gcc GCC_DD    1775                                  <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1776                                  <&gcc GCC_AG    1776                                  <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
1777                                  <&gcc GCC_AG    1777                                  <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>,
1778                                  <&gcc GCC_CN    1778                                  <&gcc GCC_CNOC_PCIE4_QX_CLK>;
1779                         clock-names = "aux",     1779                         clock-names = "aux",
1780                                       "cfg",     1780                                       "cfg",
1781                                       "bus_ma    1781                                       "bus_master",
1782                                       "bus_sl    1782                                       "bus_slave",
1783                                       "slave_    1783                                       "slave_q2a",
1784                                       "ddrss_    1784                                       "ddrss_sf_tbu",
1785                                       "noc_ag    1785                                       "noc_aggr_4",
1786                                       "noc_ag    1786                                       "noc_aggr_south_sf",
1787                                       "cnoc_q    1787                                       "cnoc_qx";
1788                                                  1788 
1789                         assigned-clocks = <&g    1789                         assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>;
1790                         assigned-clock-rates     1790                         assigned-clock-rates = <19200000>;
1791                                                  1791 
1792                         interconnects = <&agg    1792                         interconnects = <&aggre2_noc MASTER_PCIE_4 0 &mc_virt SLAVE_EBI1 0>,
1793                                         <&gem    1793                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_4 0>;
1794                         interconnect-names =     1794                         interconnect-names = "pcie-mem", "cpu-pcie";
1795                                                  1795 
1796                         resets = <&gcc GCC_PC    1796                         resets = <&gcc GCC_PCIE_4_BCR>;
1797                         reset-names = "pci";     1797                         reset-names = "pci";
1798                                                  1798 
1799                         power-domains = <&gcc    1799                         power-domains = <&gcc PCIE_4_GDSC>;
1800                         required-opps = <&rpm    1800                         required-opps = <&rpmhpd_opp_nom>;
1801                                                  1801 
1802                         phys = <&pcie4_phy>;     1802                         phys = <&pcie4_phy>;
1803                         phy-names = "pciephy"    1803                         phy-names = "pciephy";
1804                                                  1804 
1805                         status = "disabled";     1805                         status = "disabled";
1806                                                  1806 
1807                         pcie4_port0: pcie@0 {    1807                         pcie4_port0: pcie@0 {
1808                                 device_type =    1808                                 device_type = "pci";
1809                                 reg = <0x0 0x    1809                                 reg = <0x0 0x0 0x0 0x0 0x0>;
1810                                 bus-range = <    1810                                 bus-range = <0x01 0xff>;
1811                                                  1811 
1812                                 #address-cell    1812                                 #address-cells = <3>;
1813                                 #size-cells =    1813                                 #size-cells = <2>;
1814                                 ranges;          1814                                 ranges;
1815                         };                       1815                         };
1816                 };                               1816                 };
1817                                                  1817 
1818                 pcie4_phy: phy@1c06000 {         1818                 pcie4_phy: phy@1c06000 {
1819                         compatible = "qcom,sc    1819                         compatible = "qcom,sc8280xp-qmp-gen3x1-pcie-phy";
1820                         reg = <0x0 0x01c06000    1820                         reg = <0x0 0x01c06000 0x0 0x2000>;
1821                                                  1821 
1822                         clocks = <&gcc GCC_PC    1822                         clocks = <&gcc GCC_PCIE_4_AUX_CLK>,
1823                                  <&gcc GCC_PC    1823                                  <&gcc GCC_PCIE_4_CFG_AHB_CLK>,
1824                                  <&gcc GCC_PC    1824                                  <&gcc GCC_PCIE_4_CLKREF_CLK>,
1825                                  <&gcc GCC_PC    1825                                  <&gcc GCC_PCIE4_PHY_RCHNG_CLK>,
1826                                  <&gcc GCC_PC    1826                                  <&gcc GCC_PCIE_4_PIPE_CLK>,
1827                                  <&gcc GCC_PC    1827                                  <&gcc GCC_PCIE_4_PIPEDIV2_CLK>;
1828                         clock-names = "aux",     1828                         clock-names = "aux", "cfg_ahb", "ref", "rchng",
1829                                       "pipe",    1829                                       "pipe", "pipediv2";
1830                                                  1830 
1831                         assigned-clocks = <&g    1831                         assigned-clocks = <&gcc GCC_PCIE4_PHY_RCHNG_CLK>;
1832                         assigned-clock-rates     1832                         assigned-clock-rates = <100000000>;
1833                                                  1833 
1834                         power-domains = <&gcc    1834                         power-domains = <&gcc PCIE_4_GDSC>;
1835                                                  1835 
1836                         resets = <&gcc GCC_PC    1836                         resets = <&gcc GCC_PCIE_4_PHY_BCR>;
1837                         reset-names = "phy";     1837                         reset-names = "phy";
1838                                                  1838 
1839                         #clock-cells = <0>;      1839                         #clock-cells = <0>;
1840                         clock-output-names =     1840                         clock-output-names = "pcie_4_pipe_clk";
1841                                                  1841 
1842                         #phy-cells = <0>;        1842                         #phy-cells = <0>;
1843                                                  1843 
1844                         status = "disabled";     1844                         status = "disabled";
1845                 };                               1845                 };
1846                                                  1846 
1847                 pcie3b: pcie@1c08000 {           1847                 pcie3b: pcie@1c08000 {
1848                         device_type = "pci";     1848                         device_type = "pci";
1849                         compatible = "qcom,pc    1849                         compatible = "qcom,pcie-sc8280xp";
1850                         reg = <0x0 0x01c08000    1850                         reg = <0x0 0x01c08000 0x0 0x3000>,
1851                               <0x0 0x32000000    1851                               <0x0 0x32000000 0x0 0xf1d>,
1852                               <0x0 0x32000f20    1852                               <0x0 0x32000f20 0x0 0xa8>,
1853                               <0x0 0x32001000    1853                               <0x0 0x32001000 0x0 0x1000>,
1854                               <0x0 0x32100000    1854                               <0x0 0x32100000 0x0 0x100000>,
1855                               <0x0 0x01c0b000    1855                               <0x0 0x01c0b000 0x0 0x1000>;
1856                         reg-names = "parf", "    1856                         reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
1857                         #address-cells = <3>;    1857                         #address-cells = <3>;
1858                         #size-cells = <2>;       1858                         #size-cells = <2>;
1859                         ranges = <0x01000000     1859                         ranges = <0x01000000 0x0 0x00000000 0x0 0x32200000 0x0 0x100000>,
1860                                  <0x02000000     1860                                  <0x02000000 0x0 0x32300000 0x0 0x32300000 0x0 0x1d00000>;
1861                         bus-range = <0x00 0xf    1861                         bus-range = <0x00 0xff>;
1862                                                  1862 
1863                         dma-coherent;            1863                         dma-coherent;
1864                                                  1864 
1865                         linux,pci-domain = <5    1865                         linux,pci-domain = <5>;
1866                         num-lanes = <2>;         1866                         num-lanes = <2>;
1867                                                  1867 
1868                         msi-map = <0x0 &its 0    1868                         msi-map = <0x0 &its 0xd0000 0x10000>;
1869                                                  1869 
1870                         interrupts = <GIC_SPI    1870                         interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1871                                      <GIC_SPI    1871                                      <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1872                                      <GIC_SPI    1872                                      <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
1873                                      <GIC_SPI    1873                                      <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
1874                         interrupt-names = "ms    1874                         interrupt-names = "msi0", "msi1", "msi2", "msi3";
1875                                                  1875 
1876                         #interrupt-cells = <1    1876                         #interrupt-cells = <1>;
1877                         interrupt-map-mask =     1877                         interrupt-map-mask = <0 0 0 0x7>;
1878                         interrupt-map = <0 0     1878                         interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>,
1879                                         <0 0     1879                                         <0 0 0 2 &intc 0 0 GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>,
1880                                         <0 0     1880                                         <0 0 0 3 &intc 0 0 GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>,
1881                                         <0 0     1881                                         <0 0 0 4 &intc 0 0 GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>;
1882                                                  1882 
1883                         clocks = <&gcc GCC_PC    1883                         clocks = <&gcc GCC_PCIE_3B_AUX_CLK>,
1884                                  <&gcc GCC_PC    1884                                  <&gcc GCC_PCIE_3B_CFG_AHB_CLK>,
1885                                  <&gcc GCC_PC    1885                                  <&gcc GCC_PCIE_3B_MSTR_AXI_CLK>,
1886                                  <&gcc GCC_PC    1886                                  <&gcc GCC_PCIE_3B_SLV_AXI_CLK>,
1887                                  <&gcc GCC_PC    1887                                  <&gcc GCC_PCIE_3B_SLV_Q2A_AXI_CLK>,
1888                                  <&gcc GCC_DD    1888                                  <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1889                                  <&gcc GCC_AG    1889                                  <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
1890                                  <&gcc GCC_AG    1890                                  <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
1891                         clock-names = "aux",     1891                         clock-names = "aux",
1892                                       "cfg",     1892                                       "cfg",
1893                                       "bus_ma    1893                                       "bus_master",
1894                                       "bus_sl    1894                                       "bus_slave",
1895                                       "slave_    1895                                       "slave_q2a",
1896                                       "ddrss_    1896                                       "ddrss_sf_tbu",
1897                                       "noc_ag    1897                                       "noc_aggr_4",
1898                                       "noc_ag    1898                                       "noc_aggr_south_sf";
1899                                                  1899 
1900                         assigned-clocks = <&g    1900                         assigned-clocks = <&gcc GCC_PCIE_3B_AUX_CLK>;
1901                         assigned-clock-rates     1901                         assigned-clock-rates = <19200000>;
1902                                                  1902 
1903                         interconnects = <&agg    1903                         interconnects = <&aggre2_noc MASTER_PCIE_3B 0 &mc_virt SLAVE_EBI1 0>,
1904                                         <&gem    1904                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3B 0>;
1905                         interconnect-names =     1905                         interconnect-names = "pcie-mem", "cpu-pcie";
1906                                                  1906 
1907                         resets = <&gcc GCC_PC    1907                         resets = <&gcc GCC_PCIE_3B_BCR>;
1908                         reset-names = "pci";     1908                         reset-names = "pci";
1909                                                  1909 
1910                         power-domains = <&gcc    1910                         power-domains = <&gcc PCIE_3B_GDSC>;
1911                         required-opps = <&rpm    1911                         required-opps = <&rpmhpd_opp_nom>;
1912                                                  1912 
1913                         phys = <&pcie3b_phy>;    1913                         phys = <&pcie3b_phy>;
1914                         phy-names = "pciephy"    1914                         phy-names = "pciephy";
1915                                                  1915 
1916                         status = "disabled";     1916                         status = "disabled";
1917                                                  1917 
1918                         pcie3b_port0: pcie@0     1918                         pcie3b_port0: pcie@0 {
1919                                 device_type =    1919                                 device_type = "pci";
1920                                 reg = <0x0 0x    1920                                 reg = <0x0 0x0 0x0 0x0 0x0>;
1921                                 bus-range = <    1921                                 bus-range = <0x01 0xff>;
1922                                                  1922 
1923                                 #address-cell    1923                                 #address-cells = <3>;
1924                                 #size-cells =    1924                                 #size-cells = <2>;
1925                                 ranges;          1925                                 ranges;
1926                         };                       1926                         };
1927                 };                               1927                 };
1928                                                  1928 
1929                 pcie3b_phy: phy@1c0e000 {        1929                 pcie3b_phy: phy@1c0e000 {
1930                         compatible = "qcom,sc    1930                         compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy";
1931                         reg = <0x0 0x01c0e000    1931                         reg = <0x0 0x01c0e000 0x0 0x2000>;
1932                                                  1932 
1933                         clocks = <&gcc GCC_PC    1933                         clocks = <&gcc GCC_PCIE_3B_AUX_CLK>,
1934                                  <&gcc GCC_PC    1934                                  <&gcc GCC_PCIE_3B_CFG_AHB_CLK>,
1935                                  <&gcc GCC_PC    1935                                  <&gcc GCC_PCIE_3A3B_CLKREF_CLK>,
1936                                  <&gcc GCC_PC    1936                                  <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>,
1937                                  <&gcc GCC_PC    1937                                  <&gcc GCC_PCIE_3B_PIPE_CLK>,
1938                                  <&gcc GCC_PC    1938                                  <&gcc GCC_PCIE_3B_PIPEDIV2_CLK>;
1939                         clock-names = "aux",     1939                         clock-names = "aux", "cfg_ahb", "ref", "rchng",
1940                                       "pipe",    1940                                       "pipe", "pipediv2";
1941                                                  1941 
1942                         assigned-clocks = <&g    1942                         assigned-clocks = <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>;
1943                         assigned-clock-rates     1943                         assigned-clock-rates = <100000000>;
1944                                                  1944 
1945                         power-domains = <&gcc    1945                         power-domains = <&gcc PCIE_3B_GDSC>;
1946                                                  1946 
1947                         resets = <&gcc GCC_PC    1947                         resets = <&gcc GCC_PCIE_3B_PHY_BCR>;
1948                         reset-names = "phy";     1948                         reset-names = "phy";
1949                                                  1949 
1950                         #clock-cells = <0>;      1950                         #clock-cells = <0>;
1951                         clock-output-names =     1951                         clock-output-names = "pcie_3b_pipe_clk";
1952                                                  1952 
1953                         #phy-cells = <0>;        1953                         #phy-cells = <0>;
1954                                                  1954 
1955                         status = "disabled";     1955                         status = "disabled";
1956                 };                               1956                 };
1957                                                  1957 
1958                 pcie3a: pcie@1c10000 {           1958                 pcie3a: pcie@1c10000 {
1959                         device_type = "pci";     1959                         device_type = "pci";
1960                         compatible = "qcom,pc    1960                         compatible = "qcom,pcie-sc8280xp";
1961                         reg = <0x0 0x01c10000    1961                         reg = <0x0 0x01c10000 0x0 0x3000>,
1962                               <0x0 0x34000000    1962                               <0x0 0x34000000 0x0 0xf1d>,
1963                               <0x0 0x34000f20    1963                               <0x0 0x34000f20 0x0 0xa8>,
1964                               <0x0 0x34001000    1964                               <0x0 0x34001000 0x0 0x1000>,
1965                               <0x0 0x34100000    1965                               <0x0 0x34100000 0x0 0x100000>,
1966                               <0x0 0x01c13000    1966                               <0x0 0x01c13000 0x0 0x1000>;
1967                         reg-names = "parf", "    1967                         reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
1968                         #address-cells = <3>;    1968                         #address-cells = <3>;
1969                         #size-cells = <2>;       1969                         #size-cells = <2>;
1970                         ranges = <0x01000000     1970                         ranges = <0x01000000 0x0 0x00000000 0x0 0x34200000 0x0 0x100000>,
1971                                  <0x02000000     1971                                  <0x02000000 0x0 0x34300000 0x0 0x34300000 0x0 0x1d00000>;
1972                         bus-range = <0x00 0xf    1972                         bus-range = <0x00 0xff>;
1973                                                  1973 
1974                         dma-coherent;            1974                         dma-coherent;
1975                                                  1975 
1976                         linux,pci-domain = <4    1976                         linux,pci-domain = <4>;
1977                         num-lanes = <4>;         1977                         num-lanes = <4>;
1978                                                  1978 
1979                         msi-map = <0x0 &its 0    1979                         msi-map = <0x0 &its 0xc0000 0x10000>;
1980                                                  1980 
1981                         interrupts = <GIC_SPI    1981                         interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
1982                                      <GIC_SPI    1982                                      <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
1983                                      <GIC_SPI    1983                                      <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
1984                                      <GIC_SPI    1984                                      <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1985                         interrupt-names = "ms    1985                         interrupt-names = "msi0", "msi1", "msi2", "msi3";
1986                                                  1986 
1987                         #interrupt-cells = <1    1987                         #interrupt-cells = <1>;
1988                         interrupt-map-mask =     1988                         interrupt-map-mask = <0 0 0 0x7>;
1989                         interrupt-map = <0 0     1989                         interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>,
1990                                         <0 0     1990                                         <0 0 0 2 &intc 0 0 GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>,
1991                                         <0 0     1991                                         <0 0 0 3 &intc 0 0 GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>,
1992                                         <0 0     1992                                         <0 0 0 4 &intc 0 0 GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>;
1993                                                  1993 
1994                         clocks = <&gcc GCC_PC    1994                         clocks = <&gcc GCC_PCIE_3A_AUX_CLK>,
1995                                  <&gcc GCC_PC    1995                                  <&gcc GCC_PCIE_3A_CFG_AHB_CLK>,
1996                                  <&gcc GCC_PC    1996                                  <&gcc GCC_PCIE_3A_MSTR_AXI_CLK>,
1997                                  <&gcc GCC_PC    1997                                  <&gcc GCC_PCIE_3A_SLV_AXI_CLK>,
1998                                  <&gcc GCC_PC    1998                                  <&gcc GCC_PCIE_3A_SLV_Q2A_AXI_CLK>,
1999                                  <&gcc GCC_DD    1999                                  <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
2000                                  <&gcc GCC_AG    2000                                  <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
2001                                  <&gcc GCC_AG    2001                                  <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
2002                         clock-names = "aux",     2002                         clock-names = "aux",
2003                                       "cfg",     2003                                       "cfg",
2004                                       "bus_ma    2004                                       "bus_master",
2005                                       "bus_sl    2005                                       "bus_slave",
2006                                       "slave_    2006                                       "slave_q2a",
2007                                       "ddrss_    2007                                       "ddrss_sf_tbu",
2008                                       "noc_ag    2008                                       "noc_aggr_4",
2009                                       "noc_ag    2009                                       "noc_aggr_south_sf";
2010                                                  2010 
2011                         assigned-clocks = <&g    2011                         assigned-clocks = <&gcc GCC_PCIE_3A_AUX_CLK>;
2012                         assigned-clock-rates     2012                         assigned-clock-rates = <19200000>;
2013                                                  2013 
2014                         interconnects = <&agg    2014                         interconnects = <&aggre2_noc MASTER_PCIE_3A 0 &mc_virt SLAVE_EBI1 0>,
2015                                         <&gem    2015                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3A 0>;
2016                         interconnect-names =     2016                         interconnect-names = "pcie-mem", "cpu-pcie";
2017                                                  2017 
2018                         resets = <&gcc GCC_PC    2018                         resets = <&gcc GCC_PCIE_3A_BCR>;
2019                         reset-names = "pci";     2019                         reset-names = "pci";
2020                                                  2020 
2021                         power-domains = <&gcc    2021                         power-domains = <&gcc PCIE_3A_GDSC>;
2022                         required-opps = <&rpm    2022                         required-opps = <&rpmhpd_opp_nom>;
2023                                                  2023 
2024                         phys = <&pcie3a_phy>;    2024                         phys = <&pcie3a_phy>;
2025                         phy-names = "pciephy"    2025                         phy-names = "pciephy";
2026                                                  2026 
2027                         status = "disabled";     2027                         status = "disabled";
2028                                                  2028 
2029                         pcie3a_port0: pcie@0     2029                         pcie3a_port0: pcie@0 {
2030                                 device_type =    2030                                 device_type = "pci";
2031                                 reg = <0x0 0x    2031                                 reg = <0x0 0x0 0x0 0x0 0x0>;
2032                                 bus-range = <    2032                                 bus-range = <0x01 0xff>;
2033                                                  2033 
2034                                 #address-cell    2034                                 #address-cells = <3>;
2035                                 #size-cells =    2035                                 #size-cells = <2>;
2036                                 ranges;          2036                                 ranges;
2037                         };                       2037                         };
2038                 };                               2038                 };
2039                                                  2039 
2040                 pcie3a_phy: phy@1c14000 {        2040                 pcie3a_phy: phy@1c14000 {
2041                         compatible = "qcom,sc    2041                         compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy";
2042                         reg = <0x0 0x01c14000    2042                         reg = <0x0 0x01c14000 0x0 0x2000>,
2043                               <0x0 0x01c16000    2043                               <0x0 0x01c16000 0x0 0x2000>;
2044                                                  2044 
2045                         clocks = <&gcc GCC_PC    2045                         clocks = <&gcc GCC_PCIE_3A_AUX_CLK>,
2046                                  <&gcc GCC_PC    2046                                  <&gcc GCC_PCIE_3A_CFG_AHB_CLK>,
2047                                  <&gcc GCC_PC    2047                                  <&gcc GCC_PCIE_3A3B_CLKREF_CLK>,
2048                                  <&gcc GCC_PC    2048                                  <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>,
2049                                  <&gcc GCC_PC    2049                                  <&gcc GCC_PCIE_3A_PIPE_CLK>,
2050                                  <&gcc GCC_PC    2050                                  <&gcc GCC_PCIE_3A_PIPEDIV2_CLK>;
2051                         clock-names = "aux",     2051                         clock-names = "aux", "cfg_ahb", "ref", "rchng",
2052                                       "pipe",    2052                                       "pipe", "pipediv2";
2053                                                  2053 
2054                         assigned-clocks = <&g    2054                         assigned-clocks = <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>;
2055                         assigned-clock-rates     2055                         assigned-clock-rates = <100000000>;
2056                                                  2056 
2057                         power-domains = <&gcc    2057                         power-domains = <&gcc PCIE_3A_GDSC>;
2058                                                  2058 
2059                         resets = <&gcc GCC_PC    2059                         resets = <&gcc GCC_PCIE_3A_PHY_BCR>;
2060                         reset-names = "phy";     2060                         reset-names = "phy";
2061                                                  2061 
2062                         qcom,4ln-config-sel =    2062                         qcom,4ln-config-sel = <&tcsr 0xa044 1>;
2063                                                  2063 
2064                         #clock-cells = <0>;      2064                         #clock-cells = <0>;
2065                         clock-output-names =     2065                         clock-output-names = "pcie_3a_pipe_clk";
2066                                                  2066 
2067                         #phy-cells = <0>;        2067                         #phy-cells = <0>;
2068                                                  2068 
2069                         status = "disabled";     2069                         status = "disabled";
2070                 };                               2070                 };
2071                                                  2071 
2072                 pcie2b: pcie@1c18000 {           2072                 pcie2b: pcie@1c18000 {
2073                         device_type = "pci";     2073                         device_type = "pci";
2074                         compatible = "qcom,pc    2074                         compatible = "qcom,pcie-sc8280xp";
2075                         reg = <0x0 0x01c18000    2075                         reg = <0x0 0x01c18000 0x0 0x3000>,
2076                               <0x0 0x38000000    2076                               <0x0 0x38000000 0x0 0xf1d>,
2077                               <0x0 0x38000f20    2077                               <0x0 0x38000f20 0x0 0xa8>,
2078                               <0x0 0x38001000    2078                               <0x0 0x38001000 0x0 0x1000>,
2079                               <0x0 0x38100000    2079                               <0x0 0x38100000 0x0 0x100000>,
2080                               <0x0 0x01c1b000    2080                               <0x0 0x01c1b000 0x0 0x1000>;
2081                         reg-names = "parf", "    2081                         reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2082                         #address-cells = <3>;    2082                         #address-cells = <3>;
2083                         #size-cells = <2>;       2083                         #size-cells = <2>;
2084                         ranges = <0x01000000     2084                         ranges = <0x01000000 0x0 0x00000000 0x0 0x38200000 0x0 0x100000>,
2085                                  <0x02000000     2085                                  <0x02000000 0x0 0x38300000 0x0 0x38300000 0x0 0x1d00000>;
2086                         bus-range = <0x00 0xf    2086                         bus-range = <0x00 0xff>;
2087                                                  2087 
2088                         dma-coherent;            2088                         dma-coherent;
2089                                                  2089 
2090                         linux,pci-domain = <3    2090                         linux,pci-domain = <3>;
2091                         num-lanes = <2>;         2091                         num-lanes = <2>;
2092                                                  2092 
2093                         msi-map = <0x0 &its 0    2093                         msi-map = <0x0 &its 0xb0000 0x10000>;
2094                                                  2094 
2095                         interrupts = <GIC_SPI    2095                         interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
2096                                      <GIC_SPI    2096                                      <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
2097                                      <GIC_SPI    2097                                      <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
2098                                      <GIC_SPI    2098                                      <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
2099                         interrupt-names = "ms    2099                         interrupt-names = "msi0", "msi1", "msi2", "msi3";
2100                                                  2100 
2101                         #interrupt-cells = <1    2101                         #interrupt-cells = <1>;
2102                         interrupt-map-mask =     2102                         interrupt-map-mask = <0 0 0 0x7>;
2103                         interrupt-map = <0 0     2103                         interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
2104                                         <0 0     2104                                         <0 0 0 2 &intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
2105                                         <0 0     2105                                         <0 0 0 3 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
2106                                         <0 0     2106                                         <0 0 0 4 &intc 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>;
2107                                                  2107 
2108                         clocks = <&gcc GCC_PC    2108                         clocks = <&gcc GCC_PCIE_2B_AUX_CLK>,
2109                                  <&gcc GCC_PC    2109                                  <&gcc GCC_PCIE_2B_CFG_AHB_CLK>,
2110                                  <&gcc GCC_PC    2110                                  <&gcc GCC_PCIE_2B_MSTR_AXI_CLK>,
2111                                  <&gcc GCC_PC    2111                                  <&gcc GCC_PCIE_2B_SLV_AXI_CLK>,
2112                                  <&gcc GCC_PC    2112                                  <&gcc GCC_PCIE_2B_SLV_Q2A_AXI_CLK>,
2113                                  <&gcc GCC_DD    2113                                  <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
2114                                  <&gcc GCC_AG    2114                                  <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
2115                                  <&gcc GCC_AG    2115                                  <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
2116                         clock-names = "aux",     2116                         clock-names = "aux",
2117                                       "cfg",     2117                                       "cfg",
2118                                       "bus_ma    2118                                       "bus_master",
2119                                       "bus_sl    2119                                       "bus_slave",
2120                                       "slave_    2120                                       "slave_q2a",
2121                                       "ddrss_    2121                                       "ddrss_sf_tbu",
2122                                       "noc_ag    2122                                       "noc_aggr_4",
2123                                       "noc_ag    2123                                       "noc_aggr_south_sf";
2124                                                  2124 
2125                         assigned-clocks = <&g    2125                         assigned-clocks = <&gcc GCC_PCIE_2B_AUX_CLK>;
2126                         assigned-clock-rates     2126                         assigned-clock-rates = <19200000>;
2127                                                  2127 
2128                         interconnects = <&agg    2128                         interconnects = <&aggre2_noc MASTER_PCIE_2B 0 &mc_virt SLAVE_EBI1 0>,
2129                                         <&gem    2129                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2B 0>;
2130                         interconnect-names =     2130                         interconnect-names = "pcie-mem", "cpu-pcie";
2131                                                  2131 
2132                         resets = <&gcc GCC_PC    2132                         resets = <&gcc GCC_PCIE_2B_BCR>;
2133                         reset-names = "pci";     2133                         reset-names = "pci";
2134                                                  2134 
2135                         power-domains = <&gcc    2135                         power-domains = <&gcc PCIE_2B_GDSC>;
2136                         required-opps = <&rpm    2136                         required-opps = <&rpmhpd_opp_nom>;
2137                                                  2137 
2138                         phys = <&pcie2b_phy>;    2138                         phys = <&pcie2b_phy>;
2139                         phy-names = "pciephy"    2139                         phy-names = "pciephy";
2140                                                  2140 
2141                         status = "disabled";     2141                         status = "disabled";
2142                                                  2142 
2143                         pcie2b_port0: pcie@0     2143                         pcie2b_port0: pcie@0 {
2144                                 device_type =    2144                                 device_type = "pci";
2145                                 reg = <0x0 0x    2145                                 reg = <0x0 0x0 0x0 0x0 0x0>;
2146                                 bus-range = <    2146                                 bus-range = <0x01 0xff>;
2147                                                  2147 
2148                                 #address-cell    2148                                 #address-cells = <3>;
2149                                 #size-cells =    2149                                 #size-cells = <2>;
2150                                 ranges;          2150                                 ranges;
2151                         };                       2151                         };
2152                 };                               2152                 };
2153                                                  2153 
2154                 pcie2b_phy: phy@1c1e000 {        2154                 pcie2b_phy: phy@1c1e000 {
2155                         compatible = "qcom,sc    2155                         compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy";
2156                         reg = <0x0 0x01c1e000    2156                         reg = <0x0 0x01c1e000 0x0 0x2000>;
2157                                                  2157 
2158                         clocks = <&gcc GCC_PC    2158                         clocks = <&gcc GCC_PCIE_2B_AUX_CLK>,
2159                                  <&gcc GCC_PC    2159                                  <&gcc GCC_PCIE_2B_CFG_AHB_CLK>,
2160                                  <&gcc GCC_PC    2160                                  <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
2161                                  <&gcc GCC_PC    2161                                  <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>,
2162                                  <&gcc GCC_PC    2162                                  <&gcc GCC_PCIE_2B_PIPE_CLK>,
2163                                  <&gcc GCC_PC    2163                                  <&gcc GCC_PCIE_2B_PIPEDIV2_CLK>;
2164                         clock-names = "aux",     2164                         clock-names = "aux", "cfg_ahb", "ref", "rchng",
2165                                       "pipe",    2165                                       "pipe", "pipediv2";
2166                                                  2166 
2167                         assigned-clocks = <&g    2167                         assigned-clocks = <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>;
2168                         assigned-clock-rates     2168                         assigned-clock-rates = <100000000>;
2169                                                  2169 
2170                         power-domains = <&gcc    2170                         power-domains = <&gcc PCIE_2B_GDSC>;
2171                                                  2171 
2172                         resets = <&gcc GCC_PC    2172                         resets = <&gcc GCC_PCIE_2B_PHY_BCR>;
2173                         reset-names = "phy";     2173                         reset-names = "phy";
2174                                                  2174 
2175                         #clock-cells = <0>;      2175                         #clock-cells = <0>;
2176                         clock-output-names =     2176                         clock-output-names = "pcie_2b_pipe_clk";
2177                                                  2177 
2178                         #phy-cells = <0>;        2178                         #phy-cells = <0>;
2179                                                  2179 
2180                         status = "disabled";     2180                         status = "disabled";
2181                 };                               2181                 };
2182                                                  2182 
2183                 pcie2a: pcie@1c20000 {           2183                 pcie2a: pcie@1c20000 {
2184                         device_type = "pci";     2184                         device_type = "pci";
2185                         compatible = "qcom,pc    2185                         compatible = "qcom,pcie-sc8280xp";
2186                         reg = <0x0 0x01c20000    2186                         reg = <0x0 0x01c20000 0x0 0x3000>,
2187                               <0x0 0x3c000000    2187                               <0x0 0x3c000000 0x0 0xf1d>,
2188                               <0x0 0x3c000f20    2188                               <0x0 0x3c000f20 0x0 0xa8>,
2189                               <0x0 0x3c001000    2189                               <0x0 0x3c001000 0x0 0x1000>,
2190                               <0x0 0x3c100000    2190                               <0x0 0x3c100000 0x0 0x100000>,
2191                               <0x0 0x01c23000    2191                               <0x0 0x01c23000 0x0 0x1000>;
2192                         reg-names = "parf", "    2192                         reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2193                         #address-cells = <3>;    2193                         #address-cells = <3>;
2194                         #size-cells = <2>;       2194                         #size-cells = <2>;
2195                         ranges = <0x01000000     2195                         ranges = <0x01000000 0x0 0x00000000 0x0 0x3c200000 0x0 0x100000>,
2196                                  <0x02000000     2196                                  <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>;
2197                         bus-range = <0x00 0xf    2197                         bus-range = <0x00 0xff>;
2198                                                  2198 
2199                         dma-coherent;            2199                         dma-coherent;
2200                                                  2200 
2201                         linux,pci-domain = <2    2201                         linux,pci-domain = <2>;
2202                         num-lanes = <4>;         2202                         num-lanes = <4>;
2203                                                  2203 
2204                         msi-map = <0x0 &its 0    2204                         msi-map = <0x0 &its 0xa0000 0x10000>;
2205                                                  2205 
2206                         interrupts = <GIC_SPI    2206                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
2207                                      <GIC_SPI    2207                                      <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>,
2208                                      <GIC_SPI    2208                                      <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>,
2209                                      <GIC_SPI    2209                                      <GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH>;
2210                         interrupt-names = "ms    2210                         interrupt-names = "msi0", "msi1", "msi2", "msi3";
2211                                                  2211 
2212                         #interrupt-cells = <1    2212                         #interrupt-cells = <1>;
2213                         interrupt-map-mask =     2213                         interrupt-map-mask = <0 0 0 0x7>;
2214                         interrupt-map = <0 0     2214                         interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>,
2215                                         <0 0     2215                                         <0 0 0 2 &intc 0 0 GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>,
2216                                         <0 0     2216                                         <0 0 0 3 &intc 0 0 GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>,
2217                                         <0 0     2217                                         <0 0 0 4 &intc 0 0 GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>;
2218                                                  2218 
2219                         clocks = <&gcc GCC_PC    2219                         clocks = <&gcc GCC_PCIE_2A_AUX_CLK>,
2220                                  <&gcc GCC_PC    2220                                  <&gcc GCC_PCIE_2A_CFG_AHB_CLK>,
2221                                  <&gcc GCC_PC    2221                                  <&gcc GCC_PCIE_2A_MSTR_AXI_CLK>,
2222                                  <&gcc GCC_PC    2222                                  <&gcc GCC_PCIE_2A_SLV_AXI_CLK>,
2223                                  <&gcc GCC_PC    2223                                  <&gcc GCC_PCIE_2A_SLV_Q2A_AXI_CLK>,
2224                                  <&gcc GCC_DD    2224                                  <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
2225                                  <&gcc GCC_AG    2225                                  <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
2226                                  <&gcc GCC_AG    2226                                  <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
2227                         clock-names = "aux",     2227                         clock-names = "aux",
2228                                       "cfg",     2228                                       "cfg",
2229                                       "bus_ma    2229                                       "bus_master",
2230                                       "bus_sl    2230                                       "bus_slave",
2231                                       "slave_    2231                                       "slave_q2a",
2232                                       "ddrss_    2232                                       "ddrss_sf_tbu",
2233                                       "noc_ag    2233                                       "noc_aggr_4",
2234                                       "noc_ag    2234                                       "noc_aggr_south_sf";
2235                                                  2235 
2236                         assigned-clocks = <&g    2236                         assigned-clocks = <&gcc GCC_PCIE_2A_AUX_CLK>;
2237                         assigned-clock-rates     2237                         assigned-clock-rates = <19200000>;
2238                                                  2238 
2239                         interconnects = <&agg    2239                         interconnects = <&aggre2_noc MASTER_PCIE_2A 0 &mc_virt SLAVE_EBI1 0>,
2240                                         <&gem    2240                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2A 0>;
2241                         interconnect-names =     2241                         interconnect-names = "pcie-mem", "cpu-pcie";
2242                                                  2242 
2243                         resets = <&gcc GCC_PC    2243                         resets = <&gcc GCC_PCIE_2A_BCR>;
2244                         reset-names = "pci";     2244                         reset-names = "pci";
2245                                                  2245 
2246                         power-domains = <&gcc    2246                         power-domains = <&gcc PCIE_2A_GDSC>;
2247                         required-opps = <&rpm    2247                         required-opps = <&rpmhpd_opp_nom>;
2248                                                  2248 
2249                         phys = <&pcie2a_phy>;    2249                         phys = <&pcie2a_phy>;
2250                         phy-names = "pciephy"    2250                         phy-names = "pciephy";
2251                                                  2251 
2252                         status = "disabled";     2252                         status = "disabled";
2253                                                  2253 
2254                         pcie2a_port0: pcie@0     2254                         pcie2a_port0: pcie@0 {
2255                                 device_type =    2255                                 device_type = "pci";
2256                                 reg = <0x0 0x    2256                                 reg = <0x0 0x0 0x0 0x0 0x0>;
2257                                 bus-range = <    2257                                 bus-range = <0x01 0xff>;
2258                                                  2258 
2259                                 #address-cell    2259                                 #address-cells = <3>;
2260                                 #size-cells =    2260                                 #size-cells = <2>;
2261                                 ranges;          2261                                 ranges;
2262                         };                       2262                         };
2263                 };                               2263                 };
2264                                                  2264 
2265                 pcie2a_phy: phy@1c24000 {        2265                 pcie2a_phy: phy@1c24000 {
2266                         compatible = "qcom,sc    2266                         compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy";
2267                         reg = <0x0 0x01c24000    2267                         reg = <0x0 0x01c24000 0x0 0x2000>,
2268                               <0x0 0x01c26000    2268                               <0x0 0x01c26000 0x0 0x2000>;
2269                                                  2269 
2270                         clocks = <&gcc GCC_PC    2270                         clocks = <&gcc GCC_PCIE_2A_AUX_CLK>,
2271                                  <&gcc GCC_PC    2271                                  <&gcc GCC_PCIE_2A_CFG_AHB_CLK>,
2272                                  <&gcc GCC_PC    2272                                  <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
2273                                  <&gcc GCC_PC    2273                                  <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>,
2274                                  <&gcc GCC_PC    2274                                  <&gcc GCC_PCIE_2A_PIPE_CLK>,
2275                                  <&gcc GCC_PC    2275                                  <&gcc GCC_PCIE_2A_PIPEDIV2_CLK>;
2276                         clock-names = "aux",     2276                         clock-names = "aux", "cfg_ahb", "ref", "rchng",
2277                                       "pipe",    2277                                       "pipe", "pipediv2";
2278                                                  2278 
2279                         assigned-clocks = <&g    2279                         assigned-clocks = <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>;
2280                         assigned-clock-rates     2280                         assigned-clock-rates = <100000000>;
2281                                                  2281 
2282                         power-domains = <&gcc    2282                         power-domains = <&gcc PCIE_2A_GDSC>;
2283                                                  2283 
2284                         resets = <&gcc GCC_PC    2284                         resets = <&gcc GCC_PCIE_2A_PHY_BCR>;
2285                         reset-names = "phy";     2285                         reset-names = "phy";
2286                                                  2286 
2287                         qcom,4ln-config-sel =    2287                         qcom,4ln-config-sel = <&tcsr 0xa044 0>;
2288                                                  2288 
2289                         #clock-cells = <0>;      2289                         #clock-cells = <0>;
2290                         clock-output-names =     2290                         clock-output-names = "pcie_2a_pipe_clk";
2291                                                  2291 
2292                         #phy-cells = <0>;        2292                         #phy-cells = <0>;
2293                                                  2293 
2294                         status = "disabled";     2294                         status = "disabled";
2295                 };                               2295                 };
2296                                                  2296 
2297                 ufs_mem_hc: ufs@1d84000 {        2297                 ufs_mem_hc: ufs@1d84000 {
2298                         compatible = "qcom,sc    2298                         compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc",
2299                                      "jedec,u    2299                                      "jedec,ufs-2.0";
2300                         reg = <0 0x01d84000 0    2300                         reg = <0 0x01d84000 0 0x3000>;
2301                         interrupts = <GIC_SPI    2301                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2302                         phys = <&ufs_mem_phy>    2302                         phys = <&ufs_mem_phy>;
2303                         phy-names = "ufsphy";    2303                         phy-names = "ufsphy";
2304                         lanes-per-direction =    2304                         lanes-per-direction = <2>;
2305                         #reset-cells = <1>;      2305                         #reset-cells = <1>;
2306                         resets = <&gcc GCC_UF    2306                         resets = <&gcc GCC_UFS_PHY_BCR>;
2307                         reset-names = "rst";     2307                         reset-names = "rst";
2308                                                  2308 
2309                         power-domains = <&gcc    2309                         power-domains = <&gcc UFS_PHY_GDSC>;
2310                         required-opps = <&rpm    2310                         required-opps = <&rpmhpd_opp_nom>;
2311                                                  2311 
2312                         iommus = <&apps_smmu     2312                         iommus = <&apps_smmu 0xe0 0x0>;
2313                         dma-coherent;            2313                         dma-coherent;
2314                                                  2314 
2315                         clocks = <&gcc GCC_UF    2315                         clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
2316                                  <&gcc GCC_AG    2316                                  <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2317                                  <&gcc GCC_UF    2317                                  <&gcc GCC_UFS_PHY_AHB_CLK>,
2318                                  <&gcc GCC_UF    2318                                  <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2319                                  <&gcc GCC_UF    2319                                  <&gcc GCC_UFS_REF_CLKREF_CLK>,
2320                                  <&gcc GCC_UF    2320                                  <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2321                                  <&gcc GCC_UF    2321                                  <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2322                                  <&gcc GCC_UF    2322                                  <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
2323                         clock-names = "core_c    2323                         clock-names = "core_clk",
2324                                       "bus_ag    2324                                       "bus_aggr_clk",
2325                                       "iface_    2325                                       "iface_clk",
2326                                       "core_c    2326                                       "core_clk_unipro",
2327                                       "ref_cl    2327                                       "ref_clk",
2328                                       "tx_lan    2328                                       "tx_lane0_sync_clk",
2329                                       "rx_lan    2329                                       "rx_lane0_sync_clk",
2330                                       "rx_lan    2330                                       "rx_lane1_sync_clk";
2331                         freq-table-hz = <7500    2331                         freq-table-hz = <75000000 300000000>,
2332                                         <0 0>    2332                                         <0 0>,
2333                                         <0 0>    2333                                         <0 0>,
2334                                         <7500    2334                                         <75000000 300000000>,
2335                                         <0 0>    2335                                         <0 0>,
2336                                         <0 0>    2336                                         <0 0>,
2337                                         <0 0>    2337                                         <0 0>,
2338                                         <0 0>    2338                                         <0 0>;
2339                         status = "disabled";     2339                         status = "disabled";
2340                 };                               2340                 };
2341                                                  2341 
2342                 ufs_mem_phy: phy@1d87000 {       2342                 ufs_mem_phy: phy@1d87000 {
2343                         compatible = "qcom,sc    2343                         compatible = "qcom,sc8280xp-qmp-ufs-phy";
2344                         reg = <0 0x01d87000 0    2344                         reg = <0 0x01d87000 0 0x1000>;
2345                                                  2345 
2346                         clocks = <&rpmhcc RPM    2346                         clocks = <&rpmhcc RPMH_CXO_CLK>,
2347                                  <&gcc GCC_UF    2347                                  <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
2348                                  <&gcc GCC_UF    2348                                  <&gcc GCC_UFS_CARD_CLKREF_CLK>;
2349                         clock-names = "ref",     2349                         clock-names = "ref",
2350                                       "ref_au    2350                                       "ref_aux",
2351                                       "qref";    2351                                       "qref";
2352                                                  2352 
2353                         power-domains = <&gcc    2353                         power-domains = <&gcc UFS_PHY_GDSC>;
2354                                                  2354 
2355                         resets = <&ufs_mem_hc    2355                         resets = <&ufs_mem_hc 0>;
2356                         reset-names = "ufsphy    2356                         reset-names = "ufsphy";
2357                                                  2357 
2358                         #phy-cells = <0>;        2358                         #phy-cells = <0>;
2359                                                  2359 
2360                         status = "disabled";     2360                         status = "disabled";
2361                 };                               2361                 };
2362                                                  2362 
2363                 ufs_card_hc: ufs@1da4000 {       2363                 ufs_card_hc: ufs@1da4000 {
2364                         compatible = "qcom,sc    2364                         compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc",
2365                                      "jedec,u    2365                                      "jedec,ufs-2.0";
2366                         reg = <0 0x01da4000 0    2366                         reg = <0 0x01da4000 0 0x3000>;
2367                         interrupts = <GIC_SPI    2367                         interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
2368                         phys = <&ufs_card_phy    2368                         phys = <&ufs_card_phy>;
2369                         phy-names = "ufsphy";    2369                         phy-names = "ufsphy";
2370                         lanes-per-direction =    2370                         lanes-per-direction = <2>;
2371                         #reset-cells = <1>;      2371                         #reset-cells = <1>;
2372                         resets = <&gcc GCC_UF    2372                         resets = <&gcc GCC_UFS_CARD_BCR>;
2373                         reset-names = "rst";     2373                         reset-names = "rst";
2374                                                  2374 
2375                         power-domains = <&gcc    2375                         power-domains = <&gcc UFS_CARD_GDSC>;
2376                                                  2376 
2377                         iommus = <&apps_smmu     2377                         iommus = <&apps_smmu 0x4a0 0x0>;
2378                         dma-coherent;            2378                         dma-coherent;
2379                                                  2379 
2380                         clocks = <&gcc GCC_UF    2380                         clocks = <&gcc GCC_UFS_CARD_AXI_CLK>,
2381                                  <&gcc GCC_AG    2381                                  <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>,
2382                                  <&gcc GCC_UF    2382                                  <&gcc GCC_UFS_CARD_AHB_CLK>,
2383                                  <&gcc GCC_UF    2383                                  <&gcc GCC_UFS_CARD_UNIPRO_CORE_CLK>,
2384                                  <&gcc GCC_UF    2384                                  <&gcc GCC_UFS_REF_CLKREF_CLK>,
2385                                  <&gcc GCC_UF    2385                                  <&gcc GCC_UFS_CARD_TX_SYMBOL_0_CLK>,
2386                                  <&gcc GCC_UF    2386                                  <&gcc GCC_UFS_CARD_RX_SYMBOL_0_CLK>,
2387                                  <&gcc GCC_UF    2387                                  <&gcc GCC_UFS_CARD_RX_SYMBOL_1_CLK>;
2388                         clock-names = "core_c    2388                         clock-names = "core_clk",
2389                                       "bus_ag    2389                                       "bus_aggr_clk",
2390                                       "iface_    2390                                       "iface_clk",
2391                                       "core_c    2391                                       "core_clk_unipro",
2392                                       "ref_cl    2392                                       "ref_clk",
2393                                       "tx_lan    2393                                       "tx_lane0_sync_clk",
2394                                       "rx_lan    2394                                       "rx_lane0_sync_clk",
2395                                       "rx_lan    2395                                       "rx_lane1_sync_clk";
2396                         freq-table-hz = <7500    2396                         freq-table-hz = <75000000 300000000>,
2397                                         <0 0>    2397                                         <0 0>,
2398                                         <0 0>    2398                                         <0 0>,
2399                                         <7500    2399                                         <75000000 300000000>,
2400                                         <0 0>    2400                                         <0 0>,
2401                                         <0 0>    2401                                         <0 0>,
2402                                         <0 0>    2402                                         <0 0>,
2403                                         <0 0>    2403                                         <0 0>;
2404                         status = "disabled";     2404                         status = "disabled";
2405                 };                               2405                 };
2406                                                  2406 
2407                 ufs_card_phy: phy@1da7000 {      2407                 ufs_card_phy: phy@1da7000 {
2408                         compatible = "qcom,sc    2408                         compatible = "qcom,sc8280xp-qmp-ufs-phy";
2409                         reg = <0 0x01da7000 0    2409                         reg = <0 0x01da7000 0 0x1000>;
2410                                                  2410 
2411                         clocks = <&rpmhcc RPM    2411                         clocks = <&rpmhcc RPMH_CXO_CLK>,
2412                                  <&gcc GCC_UF    2412                                  <&gcc GCC_UFS_CARD_PHY_AUX_CLK>,
2413                                  <&gcc GCC_UF    2413                                  <&gcc GCC_UFS_1_CARD_CLKREF_CLK>;
2414                         clock-names = "ref",     2414                         clock-names = "ref",
2415                                       "ref_au    2415                                       "ref_aux",
2416                                       "qref";    2416                                       "qref";
2417                                                  2417 
2418                         power-domains = <&gcc    2418                         power-domains = <&gcc UFS_CARD_GDSC>;
2419                                                  2419 
2420                         resets = <&ufs_card_h    2420                         resets = <&ufs_card_hc 0>;
2421                         reset-names = "ufsphy    2421                         reset-names = "ufsphy";
2422                                                  2422 
2423                         #phy-cells = <0>;        2423                         #phy-cells = <0>;
2424                                                  2424 
2425                         status = "disabled";     2425                         status = "disabled";
2426                 };                               2426                 };
2427                                                  2427 
2428                 tcsr_mutex: hwlock@1f40000 {     2428                 tcsr_mutex: hwlock@1f40000 {
2429                         compatible = "qcom,tc    2429                         compatible = "qcom,tcsr-mutex";
2430                         reg = <0x0 0x01f40000    2430                         reg = <0x0 0x01f40000 0x0 0x20000>;
2431                         #hwlock-cells = <1>;     2431                         #hwlock-cells = <1>;
2432                 };                               2432                 };
2433                                                  2433 
2434                 tcsr: syscon@1fc0000 {           2434                 tcsr: syscon@1fc0000 {
2435                         compatible = "qcom,sc    2435                         compatible = "qcom,sc8280xp-tcsr", "syscon";
2436                         reg = <0x0 0x01fc0000    2436                         reg = <0x0 0x01fc0000 0x0 0x30000>;
2437                 };                               2437                 };
2438                                                  2438 
2439                 gpu: gpu@3d00000 {               2439                 gpu: gpu@3d00000 {
2440                         compatible = "qcom,ad    2440                         compatible = "qcom,adreno-690.0", "qcom,adreno";
2441                                                  2441 
2442                         reg = <0 0x03d00000 0    2442                         reg = <0 0x03d00000 0 0x40000>,
2443                               <0 0x03d9e000 0    2443                               <0 0x03d9e000 0 0x1000>,
2444                               <0 0x03d61000 0    2444                               <0 0x03d61000 0 0x800>;
2445                         reg-names = "kgsl_3d0    2445                         reg-names = "kgsl_3d0_reg_memory",
2446                                     "cx_mem",    2446                                     "cx_mem",
2447                                     "cx_dbgc"    2447                                     "cx_dbgc";
2448                         interrupts = <GIC_SPI    2448                         interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2449                         iommus = <&gpu_smmu 0    2449                         iommus = <&gpu_smmu 0 0xc00>, <&gpu_smmu 1 0xc00>;
2450                         operating-points-v2 =    2450                         operating-points-v2 = <&gpu_opp_table>;
2451                                                  2451 
2452                         qcom,gmu = <&gmu>;       2452                         qcom,gmu = <&gmu>;
2453                         interconnects = <&gem    2453                         interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
2454                         interconnect-names =     2454                         interconnect-names = "gfx-mem";
2455                         #cooling-cells = <2>;    2455                         #cooling-cells = <2>;
2456                                                  2456 
2457                         status = "disabled";     2457                         status = "disabled";
2458                                                  2458 
2459                         gpu_opp_table: opp-ta    2459                         gpu_opp_table: opp-table {
2460                                 compatible =     2460                                 compatible = "operating-points-v2";
2461                                                  2461 
2462                                 opp-270000000    2462                                 opp-270000000 {
2463                                         opp-h    2463                                         opp-hz = /bits/ 64 <270000000>;
2464                                         opp-l    2464                                         opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2465                                         opp-p    2465                                         opp-peak-kBps = <451000>;
2466                                 };               2466                                 };
2467                                                  2467 
2468                                 opp-410000000    2468                                 opp-410000000 {
2469                                         opp-h    2469                                         opp-hz = /bits/ 64 <410000000>;
2470                                         opp-l    2470                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2471                                         opp-p    2471                                         opp-peak-kBps = <1555000>;
2472                                 };               2472                                 };
2473                                                  2473 
2474                                 opp-500000000    2474                                 opp-500000000 {
2475                                         opp-h    2475                                         opp-hz = /bits/ 64 <500000000>;
2476                                         opp-l    2476                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2477                                         opp-p    2477                                         opp-peak-kBps = <1555000>;
2478                                 };               2478                                 };
2479                                                  2479 
2480                                 opp-547000000    2480                                 opp-547000000 {
2481                                         opp-h    2481                                         opp-hz = /bits/ 64 <547000000>;
2482                                         opp-l    2482                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2483                                         opp-p    2483                                         opp-peak-kBps = <1555000>;
2484                                 };               2484                                 };
2485                                                  2485 
2486                                 opp-606000000    2486                                 opp-606000000 {
2487                                         opp-h    2487                                         opp-hz = /bits/ 64 <606000000>;
2488                                         opp-l    2488                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2489                                         opp-p    2489                                         opp-peak-kBps = <2736000>;
2490                                 };               2490                                 };
2491                                                  2491 
2492                                 opp-640000000    2492                                 opp-640000000 {
2493                                         opp-h    2493                                         opp-hz = /bits/ 64 <640000000>;
2494                                         opp-l    2494                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2495                                         opp-p    2495                                         opp-peak-kBps = <2736000>;
2496                                 };               2496                                 };
2497                                                  2497 
2498                                 opp-655000000    2498                                 opp-655000000 {
2499                                         opp-h    2499                                         opp-hz = /bits/ 64 <655000000>;
2500                                         opp-l    2500                                         opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2501                                         opp-p    2501                                         opp-peak-kBps = <2736000>;
2502                                 };               2502                                 };
2503                                                  2503 
2504                                 opp-690000000    2504                                 opp-690000000 {
2505                                         opp-h    2505                                         opp-hz = /bits/ 64 <690000000>;
2506                                         opp-l    2506                                         opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2507                                         opp-p    2507                                         opp-peak-kBps = <2736000>;
2508                                 };               2508                                 };
2509                         };                       2509                         };
2510                 };                               2510                 };
2511                                                  2511 
2512                 gmu: gmu@3d6a000 {               2512                 gmu: gmu@3d6a000 {
2513                         compatible = "qcom,ad    2513                         compatible = "qcom,adreno-gmu-690.0", "qcom,adreno-gmu";
2514                         reg = <0 0x03d6a000 0    2514                         reg = <0 0x03d6a000 0 0x34000>,
2515                               <0 0x03de0000 0    2515                               <0 0x03de0000 0 0x10000>,
2516                               <0 0x0b290000 0    2516                               <0 0x0b290000 0 0x10000>;
2517                         reg-names = "gmu", "r    2517                         reg-names = "gmu", "rscc", "gmu_pdc";
2518                         interrupts = <GIC_SPI    2518                         interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2519                                      <GIC_SPI    2519                                      <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2520                         interrupt-names = "hf    2520                         interrupt-names = "hfi", "gmu";
2521                         clocks = <&gpucc GPU_    2521                         clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
2522                                  <&gpucc GPU_    2522                                  <&gpucc GPU_CC_CXO_CLK>,
2523                                  <&gcc GCC_DD    2523                                  <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2524                                  <&gcc GCC_GP    2524                                  <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2525                                  <&gpucc GPU_    2525                                  <&gpucc GPU_CC_AHB_CLK>,
2526                                  <&gpucc GPU_    2526                                  <&gpucc GPU_CC_HUB_CX_INT_CLK>,
2527                                  <&gpucc GPU_    2527                                  <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
2528                         clock-names = "gmu",     2528                         clock-names = "gmu",
2529                                       "cxo",     2529                                       "cxo",
2530                                       "axi",     2530                                       "axi",
2531                                       "memnoc    2531                                       "memnoc",
2532                                       "ahb",     2532                                       "ahb",
2533                                       "hub",     2533                                       "hub",
2534                                       "smmu_v    2534                                       "smmu_vote";
2535                         power-domains = <&gpu    2535                         power-domains = <&gpucc GPU_CC_CX_GDSC>,
2536                                         <&gpu    2536                                         <&gpucc GPU_CC_GX_GDSC>;
2537                         power-domain-names =     2537                         power-domain-names = "cx",
2538                                                  2538                                              "gx";
2539                         iommus = <&gpu_smmu 5    2539                         iommus = <&gpu_smmu 5 0xc00>;
2540                         operating-points-v2 =    2540                         operating-points-v2 = <&gmu_opp_table>;
2541                                                  2541 
2542                         gmu_opp_table: opp-ta    2542                         gmu_opp_table: opp-table {
2543                                 compatible =     2543                                 compatible = "operating-points-v2";
2544                                                  2544 
2545                                 opp-200000000    2545                                 opp-200000000 {
2546                                         opp-h    2546                                         opp-hz = /bits/ 64 <200000000>;
2547                                         opp-l    2547                                         opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2548                                 };               2548                                 };
2549                                                  2549 
2550                                 opp-500000000    2550                                 opp-500000000 {
2551                                         opp-h    2551                                         opp-hz = /bits/ 64 <500000000>;
2552                                         opp-l    2552                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2553                                 };               2553                                 };
2554                         };                       2554                         };
2555                 };                               2555                 };
2556                                                  2556 
2557                 gpucc: clock-controller@3d900    2557                 gpucc: clock-controller@3d90000 {
2558                         compatible = "qcom,sc    2558                         compatible = "qcom,sc8280xp-gpucc";
2559                         reg = <0 0x03d90000 0    2559                         reg = <0 0x03d90000 0 0x9000>;
2560                         clocks = <&rpmhcc RPM    2560                         clocks = <&rpmhcc RPMH_CXO_CLK>,
2561                                  <&gcc GCC_GP    2561                                  <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2562                                  <&gcc GCC_GP    2562                                  <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2563                         clock-names = "bi_tcx    2563                         clock-names = "bi_tcxo",
2564                                       "gcc_gp    2564                                       "gcc_gpu_gpll0_clk_src",
2565                                       "gcc_gp    2565                                       "gcc_gpu_gpll0_div_clk_src";
2566                                                  2566 
2567                         power-domains = <&rpm    2567                         power-domains = <&rpmhpd SC8280XP_GFX>;
2568                         #clock-cells = <1>;      2568                         #clock-cells = <1>;
2569                         #reset-cells = <1>;      2569                         #reset-cells = <1>;
2570                         #power-domain-cells =    2570                         #power-domain-cells = <1>;
2571                 };                               2571                 };
2572                                                  2572 
2573                 gpu_smmu: iommu@3da0000 {        2573                 gpu_smmu: iommu@3da0000 {
2574                         compatible = "qcom,sc    2574                         compatible = "qcom,sc8280xp-smmu-500", "qcom,adreno-smmu",
2575                                      "qcom,sm    2575                                      "qcom,smmu-500", "arm,mmu-500";
2576                         reg = <0 0x03da0000 0    2576                         reg = <0 0x03da0000 0 0x20000>;
2577                         #iommu-cells = <2>;      2577                         #iommu-cells = <2>;
2578                         #global-interrupts =     2578                         #global-interrupts = <2>;
2579                         interrupts = <GIC_SPI    2579                         interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
2580                                      <GIC_SPI    2580                                      <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
2581                                      <GIC_SPI    2581                                      <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
2582                                      <GIC_SPI    2582                                      <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
2583                                      <GIC_SPI    2583                                      <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
2584                                      <GIC_SPI    2584                                      <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
2585                                      <GIC_SPI    2585                                      <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
2586                                      <GIC_SPI    2586                                      <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
2587                                      <GIC_SPI    2587                                      <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
2588                                      <GIC_SPI    2588                                      <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
2589                                      <GIC_SPI    2589                                      <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
2590                                      <GIC_SPI    2590                                      <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
2591                                      <GIC_SPI    2591                                      <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>,
2592                                      <GIC_SPI    2592                                      <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>;
2593                                                  2593 
2594                         clocks = <&gcc GCC_GP    2594                         clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2595                                  <&gcc GCC_GP    2595                                  <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
2596                                  <&gpucc GPU_    2596                                  <&gpucc GPU_CC_AHB_CLK>,
2597                                  <&gpucc GPU_    2597                                  <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
2598                                  <&gpucc GPU_    2598                                  <&gpucc GPU_CC_CX_GMU_CLK>,
2599                                  <&gpucc GPU_    2599                                  <&gpucc GPU_CC_HUB_CX_INT_CLK>,
2600                                  <&gpucc GPU_    2600                                  <&gpucc GPU_CC_HUB_AON_CLK>;
2601                         clock-names = "gcc_gp    2601                         clock-names = "gcc_gpu_memnoc_gfx_clk",
2602                                       "gcc_gp    2602                                       "gcc_gpu_snoc_dvm_gfx_clk",
2603                                       "gpu_cc    2603                                       "gpu_cc_ahb_clk",
2604                                       "gpu_cc    2604                                       "gpu_cc_hlos1_vote_gpu_smmu_clk",
2605                                       "gpu_cc    2605                                       "gpu_cc_cx_gmu_clk",
2606                                       "gpu_cc    2606                                       "gpu_cc_hub_cx_int_clk",
2607                                       "gpu_cc    2607                                       "gpu_cc_hub_aon_clk";
2608                                                  2608 
2609                         power-domains = <&gpu    2609                         power-domains = <&gpucc GPU_CC_CX_GDSC>;
2610                         dma-coherent;            2610                         dma-coherent;
2611                 };                               2611                 };
2612                                                  2612 
2613                 usb_0_hsphy: phy@88e5000 {       2613                 usb_0_hsphy: phy@88e5000 {
2614                         compatible = "qcom,sc    2614                         compatible = "qcom,sc8280xp-usb-hs-phy",
2615                                      "qcom,us    2615                                      "qcom,usb-snps-hs-5nm-phy";
2616                         reg = <0 0x088e5000 0    2616                         reg = <0 0x088e5000 0 0x400>;
2617                         clocks = <&rpmhcc RPM    2617                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2618                         clock-names = "ref";     2618                         clock-names = "ref";
2619                         resets = <&gcc GCC_QU    2619                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2620                                                  2620 
2621                         #phy-cells = <0>;        2621                         #phy-cells = <0>;
2622                                                  2622 
2623                         status = "disabled";     2623                         status = "disabled";
2624                 };                               2624                 };
2625                                                  2625 
2626                 usb_2_hsphy0: phy@88e7000 {      2626                 usb_2_hsphy0: phy@88e7000 {
2627                         compatible = "qcom,sc    2627                         compatible = "qcom,sc8280xp-usb-hs-phy",
2628                                      "qcom,us    2628                                      "qcom,usb-snps-hs-5nm-phy";
2629                         reg = <0 0x088e7000 0    2629                         reg = <0 0x088e7000 0 0x400>;
2630                         clocks = <&gcc GCC_US    2630                         clocks = <&gcc GCC_USB2_HS0_CLKREF_CLK>;
2631                         clock-names = "ref";     2631                         clock-names = "ref";
2632                         resets = <&gcc GCC_QU    2632                         resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>;
2633                                                  2633 
2634                         #phy-cells = <0>;        2634                         #phy-cells = <0>;
2635                                                  2635 
2636                         status = "disabled";     2636                         status = "disabled";
2637                 };                               2637                 };
2638                                                  2638 
2639                 usb_2_hsphy1: phy@88e8000 {      2639                 usb_2_hsphy1: phy@88e8000 {
2640                         compatible = "qcom,sc    2640                         compatible = "qcom,sc8280xp-usb-hs-phy",
2641                                      "qcom,us    2641                                      "qcom,usb-snps-hs-5nm-phy";
2642                         reg = <0 0x088e8000 0    2642                         reg = <0 0x088e8000 0 0x400>;
2643                         clocks = <&gcc GCC_US    2643                         clocks = <&gcc GCC_USB2_HS1_CLKREF_CLK>;
2644                         clock-names = "ref";     2644                         clock-names = "ref";
2645                         resets = <&gcc GCC_QU    2645                         resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>;
2646                                                  2646 
2647                         #phy-cells = <0>;        2647                         #phy-cells = <0>;
2648                                                  2648 
2649                         status = "disabled";     2649                         status = "disabled";
2650                 };                               2650                 };
2651                                                  2651 
2652                 usb_2_hsphy2: phy@88e9000 {      2652                 usb_2_hsphy2: phy@88e9000 {
2653                         compatible = "qcom,sc    2653                         compatible = "qcom,sc8280xp-usb-hs-phy",
2654                                      "qcom,us    2654                                      "qcom,usb-snps-hs-5nm-phy";
2655                         reg = <0 0x088e9000 0    2655                         reg = <0 0x088e9000 0 0x400>;
2656                         clocks = <&gcc GCC_US    2656                         clocks = <&gcc GCC_USB2_HS2_CLKREF_CLK>;
2657                         clock-names = "ref";     2657                         clock-names = "ref";
2658                         resets = <&gcc GCC_QU    2658                         resets = <&gcc GCC_QUSB2PHY_HS2_MP_BCR>;
2659                                                  2659 
2660                         #phy-cells = <0>;        2660                         #phy-cells = <0>;
2661                                                  2661 
2662                         status = "disabled";     2662                         status = "disabled";
2663                 };                               2663                 };
2664                                                  2664 
2665                 usb_2_hsphy3: phy@88ea000 {      2665                 usb_2_hsphy3: phy@88ea000 {
2666                         compatible = "qcom,sc    2666                         compatible = "qcom,sc8280xp-usb-hs-phy",
2667                                      "qcom,us    2667                                      "qcom,usb-snps-hs-5nm-phy";
2668                         reg = <0 0x088ea000 0    2668                         reg = <0 0x088ea000 0 0x400>;
2669                         clocks = <&gcc GCC_US    2669                         clocks = <&gcc GCC_USB2_HS3_CLKREF_CLK>;
2670                         clock-names = "ref";     2670                         clock-names = "ref";
2671                         resets = <&gcc GCC_QU    2671                         resets = <&gcc GCC_QUSB2PHY_HS3_MP_BCR>;
2672                                                  2672 
2673                         #phy-cells = <0>;        2673                         #phy-cells = <0>;
2674                                                  2674 
2675                         status = "disabled";     2675                         status = "disabled";
2676                 };                               2676                 };
2677                                                  2677 
2678                 usb_2_qmpphy0: phy@88ef000 {     2678                 usb_2_qmpphy0: phy@88ef000 {
2679                         compatible = "qcom,sc    2679                         compatible = "qcom,sc8280xp-qmp-usb3-uni-phy";
2680                         reg = <0 0x088ef000 0    2680                         reg = <0 0x088ef000 0 0x2000>;
2681                                                  2681 
2682                         clocks = <&gcc GCC_US    2682                         clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
2683                                  <&gcc GCC_US    2683                                  <&gcc GCC_USB3_MP0_CLKREF_CLK>,
2684                                  <&gcc GCC_US    2684                                  <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
2685                                  <&gcc GCC_US    2685                                  <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>;
2686                         clock-names = "aux",     2686                         clock-names = "aux", "ref", "com_aux", "pipe";
2687                                                  2687 
2688                         resets = <&gcc GCC_US    2688                         resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>,
2689                                  <&gcc GCC_US    2689                                  <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>;
2690                         reset-names = "phy",     2690                         reset-names = "phy", "phy_phy";
2691                                                  2691 
2692                         power-domains = <&gcc    2692                         power-domains = <&gcc USB30_MP_GDSC>;
2693                                                  2693 
2694                         #clock-cells = <0>;      2694                         #clock-cells = <0>;
2695                         clock-output-names =     2695                         clock-output-names = "usb2_phy0_pipe_clk";
2696                                                  2696 
2697                         #phy-cells = <0>;        2697                         #phy-cells = <0>;
2698                                                  2698 
2699                         status = "disabled";     2699                         status = "disabled";
2700                 };                               2700                 };
2701                                                  2701 
2702                 usb_2_qmpphy1: phy@88f1000 {     2702                 usb_2_qmpphy1: phy@88f1000 {
2703                         compatible = "qcom,sc    2703                         compatible = "qcom,sc8280xp-qmp-usb3-uni-phy";
2704                         reg = <0 0x088f1000 0    2704                         reg = <0 0x088f1000 0 0x2000>;
2705                                                  2705 
2706                         clocks = <&gcc GCC_US    2706                         clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
2707                                  <&gcc GCC_US    2707                                  <&gcc GCC_USB3_MP1_CLKREF_CLK>,
2708                                  <&gcc GCC_US    2708                                  <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
2709                                  <&gcc GCC_US    2709                                  <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>;
2710                         clock-names = "aux",     2710                         clock-names = "aux", "ref", "com_aux", "pipe";
2711                                                  2711 
2712                         resets = <&gcc GCC_US    2712                         resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>,
2713                                  <&gcc GCC_US    2713                                  <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>;
2714                         reset-names = "phy",     2714                         reset-names = "phy", "phy_phy";
2715                                                  2715 
2716                         power-domains = <&gcc    2716                         power-domains = <&gcc USB30_MP_GDSC>;
2717                                                  2717 
2718                         #clock-cells = <0>;      2718                         #clock-cells = <0>;
2719                         clock-output-names =     2719                         clock-output-names = "usb2_phy1_pipe_clk";
2720                                                  2720 
2721                         #phy-cells = <0>;        2721                         #phy-cells = <0>;
2722                                                  2722 
2723                         status = "disabled";     2723                         status = "disabled";
2724                 };                               2724                 };
2725                                                  2725 
2726                 remoteproc_adsp: remoteproc@3    2726                 remoteproc_adsp: remoteproc@3000000 {
2727                         compatible = "qcom,sc    2727                         compatible = "qcom,sc8280xp-adsp-pas";
2728                         reg = <0 0x03000000 0    2728                         reg = <0 0x03000000 0 0x100>;
2729                                                  2729 
2730                         interrupts-extended =    2730                         interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
2731                                                  2731                                               <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
2732                                                  2732                                               <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
2733                                                  2733                                               <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
2734                                                  2734                                               <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>,
2735                                                  2735                                               <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>;
2736                         interrupt-names = "wd    2736                         interrupt-names = "wdog", "fatal", "ready",
2737                                           "ha    2737                                           "handover", "stop-ack", "shutdown-ack";
2738                                                  2738 
2739                         clocks = <&rpmhcc RPM    2739                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2740                         clock-names = "xo";      2740                         clock-names = "xo";
2741                                                  2741 
2742                         power-domains = <&rpm    2742                         power-domains = <&rpmhpd SC8280XP_LCX>,
2743                                         <&rpm    2743                                         <&rpmhpd SC8280XP_LMX>;
2744                         power-domain-names =     2744                         power-domain-names = "lcx", "lmx";
2745                                                  2745 
2746                         memory-region = <&pil    2746                         memory-region = <&pil_adsp_mem>;
2747                                                  2747 
2748                         qcom,qmp = <&aoss_qmp    2748                         qcom,qmp = <&aoss_qmp>;
2749                                                  2749 
2750                         qcom,smem-states = <&    2750                         qcom,smem-states = <&smp2p_adsp_out 0>;
2751                         qcom,smem-state-names    2751                         qcom,smem-state-names = "stop";
2752                                                  2752 
2753                         status = "disabled";     2753                         status = "disabled";
2754                                                  2754 
2755                         remoteproc_adsp_glink    2755                         remoteproc_adsp_glink: glink-edge {
2756                                 interrupts-ex    2756                                 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
2757                                                  2757                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
2758                                                  2758                                                              IRQ_TYPE_EDGE_RISING>;
2759                                 mboxes = <&ip    2759                                 mboxes = <&ipcc IPCC_CLIENT_LPASS
2760                                                  2760                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2761                                                  2761 
2762                                 label = "lpas    2762                                 label = "lpass";
2763                                 qcom,remote-p    2763                                 qcom,remote-pid = <2>;
2764                                                  2764 
2765                                 gpr {            2765                                 gpr {
2766                                         compa    2766                                         compatible = "qcom,gpr";
2767                                         qcom,    2767                                         qcom,glink-channels = "adsp_apps";
2768                                         qcom,    2768                                         qcom,domain = <GPR_DOMAIN_ID_ADSP>;
2769                                         qcom,    2769                                         qcom,intents = <512 20>;
2770                                         #addr    2770                                         #address-cells = <1>;
2771                                         #size    2771                                         #size-cells = <0>;
2772                                                  2772 
2773                                         q6apm    2773                                         q6apm: service@1 {
2774                                                  2774                                                 compatible = "qcom,q6apm";
2775                                                  2775                                                 reg = <GPR_APM_MODULE_IID>;
2776                                                  2776                                                 #sound-dai-cells = <0>;
2777                                                  2777                                                 qcom,protection-domain = "avs/audio",
2778                                                  2778                                                                          "msm/adsp/audio_pd";
2779                                                  2779                                                 q6apmdai: dais {
2780                                                  2780                                                         compatible = "qcom,q6apm-dais";
2781                                                  2781                                                         iommus = <&apps_smmu 0x0c01 0x0>;
2782                                                  2782                                                 };
2783                                                  2783 
2784                                                  2784                                                 q6apmbedai: bedais {
2785                                                  2785                                                         compatible = "qcom,q6apm-lpass-dais";
2786                                                  2786                                                         #sound-dai-cells = <1>;
2787                                                  2787                                                 };
2788                                         };       2788                                         };
2789                                                  2789 
2790                                         q6prm    2790                                         q6prm: service@2 {
2791                                                  2791                                                 compatible = "qcom,q6prm";
2792                                                  2792                                                 reg = <GPR_PRM_MODULE_IID>;
2793                                                  2793                                                 qcom,protection-domain = "avs/audio",
2794                                                  2794                                                                          "msm/adsp/audio_pd";
2795                                                  2795                                                 q6prmcc: clock-controller {
2796                                                  2796                                                         compatible = "qcom,q6prm-lpass-clocks";
2797                                                  2797                                                         #clock-cells = <2>;
2798                                                  2798                                                 };
2799                                         };       2799                                         };
2800                                 };               2800                                 };
2801                         };                       2801                         };
2802                 };                               2802                 };
2803                                                  2803 
2804                 rxmacro: rxmacro@3200000 {       2804                 rxmacro: rxmacro@3200000 {
2805                         compatible = "qcom,sc    2805                         compatible = "qcom,sc8280xp-lpass-rx-macro";
2806                         reg = <0 0x03200000 0    2806                         reg = <0 0x03200000 0 0x1000>;
2807                         clocks = <&q6prmcc LP    2807                         clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2808                                  <&q6prmcc LP    2808                                  <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2809                                  <&q6prmcc LP    2809                                  <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2810                                  <&q6prmcc LP    2810                                  <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2811                                  <&vamacro>;     2811                                  <&vamacro>;
2812                         clock-names = "mclk",    2812                         clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2813                         assigned-clocks = <&q    2813                         assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2814                                           <&q    2814                                           <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2815                         assigned-clock-rates     2815                         assigned-clock-rates = <19200000>, <19200000>;
2816                                                  2816 
2817                         clock-output-names =     2817                         clock-output-names = "mclk";
2818                         #clock-cells = <0>;      2818                         #clock-cells = <0>;
2819                         #sound-dai-cells = <1    2819                         #sound-dai-cells = <1>;
2820                                                  2820 
2821                         pinctrl-names = "defa    2821                         pinctrl-names = "default";
2822                         pinctrl-0 = <&rx_swr_    2822                         pinctrl-0 = <&rx_swr_default>;
2823                                                  2823 
2824                         status = "disabled";     2824                         status = "disabled";
2825                 };                               2825                 };
2826                                                  2826 
2827                 swr1: soundwire@3210000 {        2827                 swr1: soundwire@3210000 {
2828                         compatible = "qcom,so    2828                         compatible = "qcom,soundwire-v1.6.0";
2829                         reg = <0 0x03210000 0    2829                         reg = <0 0x03210000 0 0x2000>;
2830                         interrupts = <GIC_SPI    2830                         interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
2831                         clocks = <&rxmacro>;     2831                         clocks = <&rxmacro>;
2832                         clock-names = "iface"    2832                         clock-names = "iface";
2833                         resets = <&lpass_audi    2833                         resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>;
2834                         reset-names = "swr_au    2834                         reset-names = "swr_audio_cgcr";
2835                         label = "RX";            2835                         label = "RX";
2836                                                  2836 
2837                         qcom,din-ports = <0>;    2837                         qcom,din-ports = <0>;
2838                         qcom,dout-ports = <5>    2838                         qcom,dout-ports = <5>;
2839                                                  2839 
2840                         qcom,ports-sinterval-    2840                         qcom,ports-sinterval-low =      /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
2841                         qcom,ports-offset1 =     2841                         qcom,ports-offset1 =            /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>;
2842                         qcom,ports-offset2 =     2842                         qcom,ports-offset2 =            /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>;
2843                         qcom,ports-hstart =      2843                         qcom,ports-hstart =             /bits/ 8 <0xff 0x03 0x00 0xff 0xff>;
2844                         qcom,ports-hstop =       2844                         qcom,ports-hstop =              /bits/ 8 <0xff 0x06 0x0f 0xff 0xff>;
2845                         qcom,ports-word-lengt    2845                         qcom,ports-word-length =        /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2846                         qcom,ports-block-pack    2846                         qcom,ports-block-pack-mode =    /bits/ 8 <0xff 0xff 0x01 0xff 0xff>;
2847                         qcom,ports-lane-contr    2847                         qcom,ports-lane-control =       /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2848                         qcom,ports-block-grou    2848                         qcom,ports-block-group-count =  /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2849                                                  2849 
2850                         #sound-dai-cells = <1    2850                         #sound-dai-cells = <1>;
2851                         #address-cells = <2>;    2851                         #address-cells = <2>;
2852                         #size-cells = <0>;       2852                         #size-cells = <0>;
2853                                                  2853 
2854                         status = "disabled";     2854                         status = "disabled";
2855                 };                               2855                 };
2856                                                  2856 
2857                 txmacro: txmacro@3220000 {       2857                 txmacro: txmacro@3220000 {
2858                         compatible = "qcom,sc    2858                         compatible = "qcom,sc8280xp-lpass-tx-macro";
2859                         reg = <0 0x03220000 0    2859                         reg = <0 0x03220000 0 0x1000>;
2860                         pinctrl-names = "defa    2860                         pinctrl-names = "default";
2861                         pinctrl-0 = <&tx_swr_    2861                         pinctrl-0 = <&tx_swr_default>;
2862                         clocks = <&q6prmcc LP    2862                         clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2863                                  <&q6prmcc LP    2863                                  <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2864                                  <&q6prmcc LP    2864                                  <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2865                                  <&q6prmcc LP    2865                                  <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2866                                  <&vamacro>;     2866                                  <&vamacro>;
2867                                                  2867 
2868                         clock-names = "mclk",    2868                         clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2869                         assigned-clocks = <&q    2869                         assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2870                                           <&q    2870                                           <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2871                         assigned-clock-rates     2871                         assigned-clock-rates = <19200000>, <19200000>;
2872                         clock-output-names =     2872                         clock-output-names = "mclk";
2873                                                  2873 
2874                         #clock-cells = <0>;      2874                         #clock-cells = <0>;
2875                         #sound-dai-cells = <1    2875                         #sound-dai-cells = <1>;
2876                                                  2876 
2877                         status = "disabled";     2877                         status = "disabled";
2878                 };                               2878                 };
2879                                                  2879 
2880                 wsamacro: codec@3240000 {        2880                 wsamacro: codec@3240000 {
2881                         compatible = "qcom,sc    2881                         compatible = "qcom,sc8280xp-lpass-wsa-macro";
2882                         reg = <0 0x03240000 0    2882                         reg = <0 0x03240000 0 0x1000>;
2883                         clocks = <&q6prmcc LP    2883                         clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2884                                  <&q6prmcc LP    2884                                  <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2885                                  <&q6prmcc LP    2885                                  <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2886                                  <&q6prmcc LP    2886                                  <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2887                                  <&vamacro>;     2887                                  <&vamacro>;
2888                         clock-names = "mclk",    2888                         clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2889                         assigned-clocks = <&q    2889                         assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2890                                           <&q    2890                                           <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2891                         assigned-clock-rates     2891                         assigned-clock-rates = <19200000>, <19200000>;
2892                                                  2892 
2893                         #clock-cells = <0>;      2893                         #clock-cells = <0>;
2894                         clock-output-names =     2894                         clock-output-names = "mclk";
2895                         #sound-dai-cells = <1    2895                         #sound-dai-cells = <1>;
2896                                                  2896 
2897                         pinctrl-names = "defa    2897                         pinctrl-names = "default";
2898                         pinctrl-0 = <&wsa_swr    2898                         pinctrl-0 = <&wsa_swr_default>;
2899                                                  2899 
2900                         status = "disabled";     2900                         status = "disabled";
2901                 };                               2901                 };
2902                                                  2902 
2903                 swr0: soundwire@3250000 {        2903                 swr0: soundwire@3250000 {
2904                         reg = <0 0x03250000 0    2904                         reg = <0 0x03250000 0 0x2000>;
2905                         compatible = "qcom,so    2905                         compatible = "qcom,soundwire-v1.6.0";
2906                         interrupts = <GIC_SPI    2906                         interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
2907                         clocks = <&wsamacro>;    2907                         clocks = <&wsamacro>;
2908                         clock-names = "iface"    2908                         clock-names = "iface";
2909                         resets = <&lpass_audi    2909                         resets = <&lpass_audiocc LPASS_AUDIO_SWR_WSA_CGCR>;
2910                         reset-names = "swr_au    2910                         reset-names = "swr_audio_cgcr";
2911                         label = "WSA";           2911                         label = "WSA";
2912                                                  2912 
2913                         qcom,din-ports = <2>;    2913                         qcom,din-ports = <2>;
2914                         qcom,dout-ports = <6>    2914                         qcom,dout-ports = <6>;
2915                                                  2915 
2916                         qcom,ports-sinterval-    2916                         qcom,ports-sinterval-low =      /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2917                         qcom,ports-offset1 =     2917                         qcom,ports-offset1 =            /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2918                         qcom,ports-offset2 =     2918                         qcom,ports-offset2 =            /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2919                         qcom,ports-hstart =      2919                         qcom,ports-hstart =             /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2920                         qcom,ports-hstop =       2920                         qcom,ports-hstop =              /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2921                         qcom,ports-word-lengt    2921                         qcom,ports-word-length =        /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2922                         qcom,ports-block-pack    2922                         qcom,ports-block-pack-mode =    /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
2923                         qcom,ports-block-grou    2923                         qcom,ports-block-group-count =  /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2924                         qcom,ports-lane-contr    2924                         qcom,ports-lane-control =       /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2925                                                  2925 
2926                         #sound-dai-cells = <1    2926                         #sound-dai-cells = <1>;
2927                         #address-cells = <2>;    2927                         #address-cells = <2>;
2928                         #size-cells = <0>;       2928                         #size-cells = <0>;
2929                                                  2929 
2930                         status = "disabled";     2930                         status = "disabled";
2931                 };                               2931                 };
2932                                                  2932 
2933                 lpass_audiocc: clock-controll    2933                 lpass_audiocc: clock-controller@32a9000 {
2934                         compatible = "qcom,sc    2934                         compatible = "qcom,sc8280xp-lpassaudiocc";
2935                         reg = <0 0x032a9000 0    2935                         reg = <0 0x032a9000 0 0x1000>;
2936                         #clock-cells = <1>;      2936                         #clock-cells = <1>;
2937                         #reset-cells = <1>;      2937                         #reset-cells = <1>;
2938                 };                               2938                 };
2939                                                  2939 
2940                 swr2: soundwire@3330000 {        2940                 swr2: soundwire@3330000 {
2941                         compatible = "qcom,so    2941                         compatible = "qcom,soundwire-v1.6.0";
2942                         reg = <0 0x03330000 0    2942                         reg = <0 0x03330000 0 0x2000>;
2943                         interrupts = <GIC_SPI    2943                         interrupts = <GIC_SPI 959 IRQ_TYPE_LEVEL_HIGH>,
2944                                      <GIC_SPI    2944                                      <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>;
2945                         interrupt-names = "co    2945                         interrupt-names = "core", "wakeup";
2946                                                  2946 
2947                         clocks = <&txmacro>;     2947                         clocks = <&txmacro>;
2948                         clock-names = "iface"    2948                         clock-names = "iface";
2949                         resets = <&lpasscc LP    2949                         resets = <&lpasscc LPASS_AUDIO_SWR_TX_CGCR>;
2950                         reset-names = "swr_au    2950                         reset-names = "swr_audio_cgcr";
2951                         label = "TX";            2951                         label = "TX";
2952                         #sound-dai-cells = <1    2952                         #sound-dai-cells = <1>;
2953                         #address-cells = <2>;    2953                         #address-cells = <2>;
2954                         #size-cells = <0>;       2954                         #size-cells = <0>;
2955                                                  2955 
2956                         qcom,din-ports = <4>;    2956                         qcom,din-ports = <4>;
2957                         qcom,dout-ports = <0>    2957                         qcom,dout-ports = <0>;
2958                         qcom,ports-sinterval-    2958                         qcom,ports-sinterval-low =      /bits/ 8 <0x01 0x01 0x03 0x03>;
2959                         qcom,ports-offset1 =     2959                         qcom,ports-offset1 =            /bits/ 8 <0x01 0x00 0x02 0x00>;
2960                         qcom,ports-offset2 =     2960                         qcom,ports-offset2 =            /bits/ 8 <0x00 0x00 0x00 0x00>;
2961                         qcom,ports-block-pack    2961                         qcom,ports-block-pack-mode =    /bits/ 8 <0xff 0xff 0xff 0xff>;
2962                         qcom,ports-hstart =      2962                         qcom,ports-hstart =             /bits/ 8 <0xff 0xff 0xff 0xff>;
2963                         qcom,ports-hstop =       2963                         qcom,ports-hstop =              /bits/ 8 <0xff 0xff 0xff 0xff>;
2964                         qcom,ports-word-lengt    2964                         qcom,ports-word-length =        /bits/ 8 <0xff 0xff 0xff 0xff>;
2965                         qcom,ports-block-grou    2965                         qcom,ports-block-group-count =  /bits/ 8 <0xff 0xff 0xff 0xff>;
2966                         qcom,ports-lane-contr    2966                         qcom,ports-lane-control =       /bits/ 8 <0x00 0x01 0x00 0x01>;
2967                                                  2967 
2968                         status = "disabled";     2968                         status = "disabled";
2969                 };                               2969                 };
2970                                                  2970 
2971                 vamacro: codec@3370000 {         2971                 vamacro: codec@3370000 {
2972                         compatible = "qcom,sc    2972                         compatible = "qcom,sc8280xp-lpass-va-macro";
2973                         reg = <0 0x03370000 0    2973                         reg = <0 0x03370000 0 0x1000>;
2974                         clocks = <&q6prmcc LP    2974                         clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2975                                  <&q6prmcc LP    2975                                  <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2976                                  <&q6prmcc LP    2976                                  <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2977                                  <&q6prmcc LP    2977                                  <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2978                         clock-names = "mclk",    2978                         clock-names = "mclk", "macro", "dcodec", "npl";
2979                         assigned-clocks = <&q    2979                         assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2980                         assigned-clock-rates     2980                         assigned-clock-rates = <19200000>;
2981                                                  2981 
2982                         #clock-cells = <0>;      2982                         #clock-cells = <0>;
2983                         clock-output-names =     2983                         clock-output-names = "fsgen";
2984                         #sound-dai-cells = <1    2984                         #sound-dai-cells = <1>;
2985                                                  2985 
2986                         status = "disabled";     2986                         status = "disabled";
2987                 };                               2987                 };
2988                                                  2988 
2989                 lpass_tlmm: pinctrl@33c0000 {    2989                 lpass_tlmm: pinctrl@33c0000 {
2990                         compatible = "qcom,sc    2990                         compatible = "qcom,sc8280xp-lpass-lpi-pinctrl";
2991                         reg = <0 0x33c0000 0x    2991                         reg = <0 0x33c0000 0x0 0x20000>,
2992                               <0 0x3550000 0x    2992                               <0 0x3550000 0x0 0x10000>;
2993                         gpio-controller;         2993                         gpio-controller;
2994                         #gpio-cells = <2>;       2994                         #gpio-cells = <2>;
2995                         gpio-ranges = <&lpass    2995                         gpio-ranges = <&lpass_tlmm 0 0 19>;
2996                                                  2996 
2997                         clocks = <&q6prmcc LP    2997                         clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2998                                  <&q6prmcc LP    2998                                  <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2999                         clock-names = "core",    2999                         clock-names = "core", "audio";
3000                                                  3000 
3001                         status = "disabled";     3001                         status = "disabled";
3002                                                  3002 
3003                         tx_swr_default: tx-sw    3003                         tx_swr_default: tx-swr-default-state {
3004                                 clk-pins {       3004                                 clk-pins {
3005                                         pins     3005                                         pins = "gpio0";
3006                                         funct    3006                                         function = "swr_tx_clk";
3007                                         drive    3007                                         drive-strength = <2>;
3008                                         slew-    3008                                         slew-rate = <1>;
3009                                         bias-    3009                                         bias-disable;
3010                                 };               3010                                 };
3011                                                  3011 
3012                                 data-pins {      3012                                 data-pins {
3013                                         pins     3013                                         pins = "gpio1", "gpio2";
3014                                         funct    3014                                         function = "swr_tx_data";
3015                                         drive    3015                                         drive-strength = <2>;
3016                                         slew-    3016                                         slew-rate = <1>;
3017                                         bias-    3017                                         bias-bus-hold;
3018                                 };               3018                                 };
3019                         };                       3019                         };
3020                                                  3020 
3021                         rx_swr_default: rx-sw    3021                         rx_swr_default: rx-swr-default-state {
3022                                 clk-pins {       3022                                 clk-pins {
3023                                         pins     3023                                         pins = "gpio3";
3024                                         funct    3024                                         function = "swr_rx_clk";
3025                                         drive    3025                                         drive-strength = <2>;
3026                                         slew-    3026                                         slew-rate = <1>;
3027                                         bias-    3027                                         bias-disable;
3028                                 };               3028                                 };
3029                                                  3029 
3030                                 data-pins {      3030                                 data-pins {
3031                                         pins     3031                                         pins = "gpio4", "gpio5";
3032                                         funct    3032                                         function = "swr_rx_data";
3033                                         drive    3033                                         drive-strength = <2>;
3034                                         slew-    3034                                         slew-rate = <1>;
3035                                         bias-    3035                                         bias-bus-hold;
3036                                 };               3036                                 };
3037                         };                       3037                         };
3038                                                  3038 
3039                         dmic01_default: dmic0    3039                         dmic01_default: dmic01-default-state {
3040                                 clk-pins {       3040                                 clk-pins {
3041                                         pins     3041                                         pins = "gpio6";
3042                                         funct    3042                                         function = "dmic1_clk";
3043                                         drive    3043                                         drive-strength = <8>;
3044                                         outpu    3044                                         output-high;
3045                                 };               3045                                 };
3046                                                  3046 
3047                                 data-pins {      3047                                 data-pins {
3048                                         pins     3048                                         pins = "gpio7";
3049                                         funct    3049                                         function = "dmic1_data";
3050                                         drive    3050                                         drive-strength = <8>;
3051                                         input    3051                                         input-enable;
3052                                 };               3052                                 };
3053                         };                       3053                         };
3054                                                  3054 
3055                         dmic01_sleep: dmic01-    3055                         dmic01_sleep: dmic01-sleep-state {
3056                                 clk-pins {       3056                                 clk-pins {
3057                                         pins     3057                                         pins = "gpio6";
3058                                         funct    3058                                         function = "dmic1_clk";
3059                                         drive    3059                                         drive-strength = <2>;
3060                                         bias-    3060                                         bias-disable;
3061                                         outpu    3061                                         output-low;
3062                                 };               3062                                 };
3063                                                  3063 
3064                                 data-pins {      3064                                 data-pins {
3065                                         pins     3065                                         pins = "gpio7";
3066                                         funct    3066                                         function = "dmic1_data";
3067                                         drive    3067                                         drive-strength = <2>;
3068                                         bias-    3068                                         bias-pull-down;
3069                                         input    3069                                         input-enable;
3070                                 };               3070                                 };
3071                         };                       3071                         };
3072                                                  3072 
3073                         dmic23_default: dmic2    3073                         dmic23_default: dmic23-default-state {
3074                                 clk-pins {       3074                                 clk-pins {
3075                                         pins     3075                                         pins = "gpio8";
3076                                         funct    3076                                         function = "dmic2_clk";
3077                                         drive    3077                                         drive-strength = <8>;
3078                                         outpu    3078                                         output-high;
3079                                 };               3079                                 };
3080                                                  3080 
3081                                 data-pins {      3081                                 data-pins {
3082                                         pins     3082                                         pins = "gpio9";
3083                                         funct    3083                                         function = "dmic2_data";
3084                                         drive    3084                                         drive-strength = <8>;
3085                                         input    3085                                         input-enable;
3086                                 };               3086                                 };
3087                         };                       3087                         };
3088                                                  3088 
3089                         dmic23_sleep: dmic23-    3089                         dmic23_sleep: dmic23-sleep-state {
3090                                 clk-pins {       3090                                 clk-pins {
3091                                         pins     3091                                         pins = "gpio8";
3092                                         funct    3092                                         function = "dmic2_clk";
3093                                         drive    3093                                         drive-strength = <2>;
3094                                         bias-    3094                                         bias-disable;
3095                                         outpu    3095                                         output-low;
3096                                 };               3096                                 };
3097                                                  3097 
3098                                 data-pins {      3098                                 data-pins {
3099                                         pins     3099                                         pins = "gpio9";
3100                                         funct    3100                                         function = "dmic2_data";
3101                                         drive    3101                                         drive-strength = <2>;
3102                                         bias-    3102                                         bias-pull-down;
3103                                         input    3103                                         input-enable;
3104                                 };               3104                                 };
3105                         };                       3105                         };
3106                                                  3106 
3107                         wsa_swr_default: wsa-    3107                         wsa_swr_default: wsa-swr-default-state {
3108                                 clk-pins {       3108                                 clk-pins {
3109                                         pins     3109                                         pins = "gpio10";
3110                                         funct    3110                                         function = "wsa_swr_clk";
3111                                         drive    3111                                         drive-strength = <2>;
3112                                         slew-    3112                                         slew-rate = <1>;
3113                                         bias-    3113                                         bias-disable;
3114                                 };               3114                                 };
3115                                                  3115 
3116                                 data-pins {      3116                                 data-pins {
3117                                         pins     3117                                         pins = "gpio11";
3118                                         funct    3118                                         function = "wsa_swr_data";
3119                                         drive    3119                                         drive-strength = <2>;
3120                                         slew-    3120                                         slew-rate = <1>;
3121                                         bias-    3121                                         bias-bus-hold;
3122                                 };               3122                                 };
3123                         };                       3123                         };
3124                                                  3124 
3125                         wsa2_swr_default: wsa    3125                         wsa2_swr_default: wsa2-swr-default-state {
3126                                 clk-pins {       3126                                 clk-pins {
3127                                         pins     3127                                         pins = "gpio15";
3128                                         funct    3128                                         function = "wsa2_swr_clk";
3129                                         drive    3129                                         drive-strength = <2>;
3130                                         slew-    3130                                         slew-rate = <1>;
3131                                         bias-    3131                                         bias-disable;
3132                                 };               3132                                 };
3133                                                  3133 
3134                                 data-pins {      3134                                 data-pins {
3135                                         pins     3135                                         pins = "gpio16";
3136                                         funct    3136                                         function = "wsa2_swr_data";
3137                                         drive    3137                                         drive-strength = <2>;
3138                                         slew-    3138                                         slew-rate = <1>;
3139                                         bias-    3139                                         bias-bus-hold;
3140                                 };               3140                                 };
3141                         };                       3141                         };
3142                 };                               3142                 };
3143                                                  3143 
3144                 lpasscc: clock-controller@33e    3144                 lpasscc: clock-controller@33e0000 {
3145                         compatible = "qcom,sc    3145                         compatible = "qcom,sc8280xp-lpasscc";
3146                         reg = <0 0x033e0000 0    3146                         reg = <0 0x033e0000 0 0x12000>;
3147                         #clock-cells = <1>;      3147                         #clock-cells = <1>;
3148                         #reset-cells = <1>;      3148                         #reset-cells = <1>;
3149                 };                               3149                 };
3150                                                  3150 
3151                 sdc2: mmc@8804000 {              3151                 sdc2: mmc@8804000 {
3152                         compatible = "qcom,sc    3152                         compatible = "qcom,sc8280xp-sdhci", "qcom,sdhci-msm-v5";
3153                         reg = <0 0x08804000 0    3153                         reg = <0 0x08804000 0 0x1000>;
3154                                                  3154 
3155                         interrupts = <GIC_SPI    3155                         interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
3156                                      <GIC_SPI    3156                                      <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
3157                         interrupt-names = "hc    3157                         interrupt-names = "hc_irq", "pwr_irq";
3158                                                  3158 
3159                         clocks = <&gcc GCC_SD    3159                         clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3160                                  <&gcc GCC_SD    3160                                  <&gcc GCC_SDCC2_APPS_CLK>,
3161                                  <&rpmhcc RPM    3161                                  <&rpmhcc RPMH_CXO_CLK>;
3162                         clock-names = "iface"    3162                         clock-names = "iface", "core", "xo";
3163                         resets = <&gcc GCC_SD    3163                         resets = <&gcc GCC_SDCC2_BCR>;
3164                         interconnects = <&agg    3164                         interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
3165                                         <&gem    3165                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
3166                         interconnect-names =     3166                         interconnect-names = "sdhc-ddr","cpu-sdhc";
3167                         iommus = <&apps_smmu     3167                         iommus = <&apps_smmu 0x4e0 0x0>;
3168                         power-domains = <&rpm    3168                         power-domains = <&rpmhpd SC8280XP_CX>;
3169                         operating-points-v2 =    3169                         operating-points-v2 = <&sdc2_opp_table>;
3170                         bus-width = <4>;         3170                         bus-width = <4>;
3171                         dma-coherent;            3171                         dma-coherent;
3172                                                  3172 
3173                         status = "disabled";     3173                         status = "disabled";
3174                                                  3174 
3175                         sdc2_opp_table: opp-t    3175                         sdc2_opp_table: opp-table {
3176                                 compatible =     3176                                 compatible = "operating-points-v2";
3177                                                  3177 
3178                                 opp-100000000    3178                                 opp-100000000 {
3179                                         opp-h    3179                                         opp-hz = /bits/ 64 <100000000>;
3180                                         requi    3180                                         required-opps = <&rpmhpd_opp_low_svs>;
3181                                         opp-p    3181                                         opp-peak-kBps = <1800000 400000>;
3182                                         opp-a    3182                                         opp-avg-kBps = <100000 0>;
3183                                 };               3183                                 };
3184                                                  3184 
3185                                 opp-202000000    3185                                 opp-202000000 {
3186                                         opp-h    3186                                         opp-hz = /bits/ 64 <202000000>;
3187                                         requi    3187                                         required-opps = <&rpmhpd_opp_svs_l1>;
3188                                         opp-p    3188                                         opp-peak-kBps = <5400000 1600000>;
3189                                         opp-a    3189                                         opp-avg-kBps = <200000 0>;
3190                                 };               3190                                 };
3191                         };                       3191                         };
3192                 };                               3192                 };
3193                                                  3193 
3194                 usb_0_qmpphy: phy@88eb000 {      3194                 usb_0_qmpphy: phy@88eb000 {
3195                         compatible = "qcom,sc    3195                         compatible = "qcom,sc8280xp-qmp-usb43dp-phy";
3196                         reg = <0 0x088eb000 0    3196                         reg = <0 0x088eb000 0 0x4000>;
3197                                                  3197 
3198                         clocks = <&gcc GCC_US    3198                         clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
3199                                  <&gcc GCC_US    3199                                  <&gcc GCC_USB4_EUD_CLKREF_CLK>,
3200                                  <&gcc GCC_US    3200                                  <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
3201                                  <&gcc GCC_US    3201                                  <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3202                         clock-names = "aux",     3202                         clock-names = "aux", "ref", "com_aux", "usb3_pipe";
3203                                                  3203 
3204                         power-domains = <&gcc    3204                         power-domains = <&gcc USB30_PRIM_GDSC>;
3205                                                  3205 
3206                         resets = <&gcc GCC_US    3206                         resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
3207                                  <&gcc GCC_US    3207                                  <&gcc GCC_USB4_DP_PHY_PRIM_BCR>;
3208                         reset-names = "phy",     3208                         reset-names = "phy", "common";
3209                                                  3209 
3210                         #clock-cells = <1>;      3210                         #clock-cells = <1>;
3211                         #phy-cells = <1>;        3211                         #phy-cells = <1>;
3212                                                  3212 
3213                         status = "disabled";     3213                         status = "disabled";
3214                                                  3214 
3215                         ports {                  3215                         ports {
3216                                 #address-cell    3216                                 #address-cells = <1>;
3217                                 #size-cells =    3217                                 #size-cells = <0>;
3218                                                  3218 
3219                                 port@0 {         3219                                 port@0 {
3220                                         reg =    3220                                         reg = <0>;
3221                                                  3221 
3222                                         usb_0    3222                                         usb_0_qmpphy_out: endpoint {};
3223                                 };               3223                                 };
3224                                                  3224 
3225                                 port@1 {         3225                                 port@1 {
3226                                         reg =    3226                                         reg = <1>;
3227                                                  3227 
3228                                         usb_0    3228                                         usb_0_qmpphy_usb_ss_in: endpoint {
3229                                                  3229                                                 remote-endpoint = <&usb_0_dwc3_ss>;
3230                                         };       3230                                         };
3231                                 };               3231                                 };
3232                                                  3232 
3233                                 port@2 {         3233                                 port@2 {
3234                                         reg =    3234                                         reg = <2>;
3235                                                  3235 
3236                                         usb_0    3236                                         usb_0_qmpphy_dp_in: endpoint {};
3237                                 };               3237                                 };
3238                         };                       3238                         };
3239                 };                               3239                 };
3240                                                  3240 
3241                 usb_1_hsphy: phy@8902000 {       3241                 usb_1_hsphy: phy@8902000 {
3242                         compatible = "qcom,sc    3242                         compatible = "qcom,sc8280xp-usb-hs-phy",
3243                                      "qcom,us    3243                                      "qcom,usb-snps-hs-5nm-phy";
3244                         reg = <0 0x08902000 0    3244                         reg = <0 0x08902000 0 0x400>;
3245                         #phy-cells = <0>;        3245                         #phy-cells = <0>;
3246                                                  3246 
3247                         clocks = <&rpmhcc RPM    3247                         clocks = <&rpmhcc RPMH_CXO_CLK>;
3248                         clock-names = "ref";     3248                         clock-names = "ref";
3249                                                  3249 
3250                         resets = <&gcc GCC_QU    3250                         resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3251                                                  3251 
3252                         status = "disabled";     3252                         status = "disabled";
3253                 };                               3253                 };
3254                                                  3254 
3255                 usb_1_qmpphy: phy@8903000 {      3255                 usb_1_qmpphy: phy@8903000 {
3256                         compatible = "qcom,sc    3256                         compatible = "qcom,sc8280xp-qmp-usb43dp-phy";
3257                         reg = <0 0x08903000 0    3257                         reg = <0 0x08903000 0 0x4000>;
3258                                                  3258 
3259                         clocks = <&gcc GCC_US    3259                         clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
3260                                  <&gcc GCC_US    3260                                  <&gcc GCC_USB4_CLKREF_CLK>,
3261                                  <&gcc GCC_US    3261                                  <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
3262                                  <&gcc GCC_US    3262                                  <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
3263                         clock-names = "aux",     3263                         clock-names = "aux", "ref", "com_aux", "usb3_pipe";
3264                                                  3264 
3265                         power-domains = <&gcc    3265                         power-domains = <&gcc USB30_SEC_GDSC>;
3266                                                  3266 
3267                         resets = <&gcc GCC_US    3267                         resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
3268                                  <&gcc GCC_US    3268                                  <&gcc GCC_USB4_1_DP_PHY_PRIM_BCR>;
3269                         reset-names = "phy",     3269                         reset-names = "phy", "common";
3270                                                  3270 
3271                         #clock-cells = <1>;      3271                         #clock-cells = <1>;
3272                         #phy-cells = <1>;        3272                         #phy-cells = <1>;
3273                                                  3273 
3274                         status = "disabled";     3274                         status = "disabled";
3275                                                  3275 
3276                         ports {                  3276                         ports {
3277                                 #address-cell    3277                                 #address-cells = <1>;
3278                                 #size-cells =    3278                                 #size-cells = <0>;
3279                                                  3279 
3280                                 port@0 {         3280                                 port@0 {
3281                                         reg =    3281                                         reg = <0>;
3282                                                  3282 
3283                                         usb_1    3283                                         usb_1_qmpphy_out: endpoint {};
3284                                 };               3284                                 };
3285                                                  3285 
3286                                 port@1 {         3286                                 port@1 {
3287                                         reg =    3287                                         reg = <1>;
3288                                                  3288 
3289                                         usb_1    3289                                         usb_1_qmpphy_usb_ss_in: endpoint {
3290                                                  3290                                                 remote-endpoint = <&usb_1_dwc3_ss>;
3291                                         };       3291                                         };
3292                                 };               3292                                 };
3293                                                  3293 
3294                                 port@2 {         3294                                 port@2 {
3295                                         reg =    3295                                         reg = <2>;
3296                                                  3296 
3297                                         usb_1    3297                                         usb_1_qmpphy_dp_in: endpoint {};
3298                                 };               3298                                 };
3299                         };                       3299                         };
3300                 };                               3300                 };
3301                                                  3301 
3302                 mdss1_dp0_phy: phy@8909a00 {     3302                 mdss1_dp0_phy: phy@8909a00 {
3303                         compatible = "qcom,sc    3303                         compatible = "qcom,sc8280xp-dp-phy";
3304                         reg = <0 0x08909a00 0    3304                         reg = <0 0x08909a00 0 0x19c>,
3305                               <0 0x08909200 0    3305                               <0 0x08909200 0 0xec>,
3306                               <0 0x08909600 0    3306                               <0 0x08909600 0 0xec>,
3307                               <0 0x08909000 0    3307                               <0 0x08909000 0 0x1c8>;
3308                                                  3308 
3309                         clocks = <&dispcc1 DI    3309                         clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>,
3310                                  <&dispcc1 DI    3310                                  <&dispcc1 DISP_CC_MDSS_AHB_CLK>;
3311                         clock-names = "aux",     3311                         clock-names = "aux", "cfg_ahb";
3312                         power-domains = <&rpm    3312                         power-domains = <&rpmhpd SC8280XP_MX>;
3313                                                  3313 
3314                         #clock-cells = <1>;      3314                         #clock-cells = <1>;
3315                         #phy-cells = <0>;        3315                         #phy-cells = <0>;
3316                                                  3316 
3317                         status = "disabled";     3317                         status = "disabled";
3318                 };                               3318                 };
3319                                                  3319 
3320                 mdss1_dp1_phy: phy@890ca00 {     3320                 mdss1_dp1_phy: phy@890ca00 {
3321                         compatible = "qcom,sc    3321                         compatible = "qcom,sc8280xp-dp-phy";
3322                         reg = <0 0x0890ca00 0    3322                         reg = <0 0x0890ca00 0 0x19c>,
3323                               <0 0x0890c200 0    3323                               <0 0x0890c200 0 0xec>,
3324                               <0 0x0890c600 0    3324                               <0 0x0890c600 0 0xec>,
3325                               <0 0x0890c000 0    3325                               <0 0x0890c000 0 0x1c8>;
3326                                                  3326 
3327                         clocks = <&dispcc1 DI    3327                         clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>,
3328                                  <&dispcc1 DI    3328                                  <&dispcc1 DISP_CC_MDSS_AHB_CLK>;
3329                         clock-names = "aux",     3329                         clock-names = "aux", "cfg_ahb";
3330                         power-domains = <&rpm    3330                         power-domains = <&rpmhpd SC8280XP_MX>;
3331                                                  3331 
3332                         #clock-cells = <1>;      3332                         #clock-cells = <1>;
3333                         #phy-cells = <0>;        3333                         #phy-cells = <0>;
3334                                                  3334 
3335                         status = "disabled";     3335                         status = "disabled";
3336                 };                               3336                 };
3337                                                  3337 
3338                 pmu@9091000 {                    3338                 pmu@9091000 {
3339                         compatible = "qcom,sc    3339                         compatible = "qcom,sc8280xp-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
3340                         reg = <0 0x09091000 0    3340                         reg = <0 0x09091000 0 0x1000>;
3341                                                  3341 
3342                         interrupts = <GIC_SPI    3342                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
3343                                                  3343 
3344                         interconnects = <&mc_    3344                         interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>;
3345                                                  3345 
3346                         operating-points-v2 =    3346                         operating-points-v2 = <&llcc_bwmon_opp_table>;
3347                                                  3347 
3348                         llcc_bwmon_opp_table:    3348                         llcc_bwmon_opp_table: opp-table {
3349                                 compatible =     3349                                 compatible = "operating-points-v2";
3350                                                  3350 
3351                                 opp-0 {          3351                                 opp-0 {
3352                                         opp-p    3352                                         opp-peak-kBps = <762000>;
3353                                 };               3353                                 };
3354                                 opp-1 {          3354                                 opp-1 {
3355                                         opp-p    3355                                         opp-peak-kBps = <1720000>;
3356                                 };               3356                                 };
3357                                 opp-2 {          3357                                 opp-2 {
3358                                         opp-p    3358                                         opp-peak-kBps = <2086000>;
3359                                 };               3359                                 };
3360                                 opp-3 {          3360                                 opp-3 {
3361                                         opp-p    3361                                         opp-peak-kBps = <2597000>;
3362                                 };               3362                                 };
3363                                 opp-4 {          3363                                 opp-4 {
3364                                         opp-p    3364                                         opp-peak-kBps = <2929000>;
3365                                 };               3365                                 };
3366                                 opp-5 {          3366                                 opp-5 {
3367                                         opp-p    3367                                         opp-peak-kBps = <3879000>;
3368                                 };               3368                                 };
3369                                 opp-6 {          3369                                 opp-6 {
3370                                         opp-p    3370                                         opp-peak-kBps = <5161000>;
3371                                 };               3371                                 };
3372                                 opp-7 {          3372                                 opp-7 {
3373                                         opp-p    3373                                         opp-peak-kBps = <5931000>;
3374                                 };               3374                                 };
3375                                 opp-8 {          3375                                 opp-8 {
3376                                         opp-p    3376                                         opp-peak-kBps = <6515000>;
3377                                 };               3377                                 };
3378                                 opp-9 {          3378                                 opp-9 {
3379                                         opp-p    3379                                         opp-peak-kBps = <7980000>;
3380                                 };               3380                                 };
3381                                 opp-10 {         3381                                 opp-10 {
3382                                         opp-p    3382                                         opp-peak-kBps = <8136000>;
3383                                 };               3383                                 };
3384                                 opp-11 {         3384                                 opp-11 {
3385                                         opp-p    3385                                         opp-peak-kBps = <10437000>;
3386                                 };               3386                                 };
3387                                 opp-12 {         3387                                 opp-12 {
3388                                         opp-p    3388                                         opp-peak-kBps = <12191000>;
3389                                 };               3389                                 };
3390                         };                       3390                         };
3391                 };                               3391                 };
3392                                                  3392 
3393                 pmu@90b6400 {                    3393                 pmu@90b6400 {
3394                         compatible = "qcom,sc    3394                         compatible = "qcom,sc8280xp-cpu-bwmon", "qcom,sdm845-bwmon";
3395                         reg = <0 0x090b6400 0    3395                         reg = <0 0x090b6400 0 0x600>;
3396                                                  3396 
3397                         interrupts = <GIC_SPI    3397                         interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
3398                                                  3398 
3399                         interconnects = <&gem    3399                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>;
3400                         operating-points-v2 =    3400                         operating-points-v2 = <&cpu_bwmon_opp_table>;
3401                                                  3401 
3402                         cpu_bwmon_opp_table:     3402                         cpu_bwmon_opp_table: opp-table {
3403                                 compatible =     3403                                 compatible = "operating-points-v2";
3404                                                  3404 
3405                                 opp-0 {          3405                                 opp-0 {
3406                                         opp-p    3406                                         opp-peak-kBps = <2288000>;
3407                                 };               3407                                 };
3408                                 opp-1 {          3408                                 opp-1 {
3409                                         opp-p    3409                                         opp-peak-kBps = <4577000>;
3410                                 };               3410                                 };
3411                                 opp-2 {          3411                                 opp-2 {
3412                                         opp-p    3412                                         opp-peak-kBps = <7110000>;
3413                                 };               3413                                 };
3414                                 opp-3 {          3414                                 opp-3 {
3415                                         opp-p    3415                                         opp-peak-kBps = <9155000>;
3416                                 };               3416                                 };
3417                                 opp-4 {          3417                                 opp-4 {
3418                                         opp-p    3418                                         opp-peak-kBps = <12298000>;
3419                                 };               3419                                 };
3420                                 opp-5 {          3420                                 opp-5 {
3421                                         opp-p    3421                                         opp-peak-kBps = <14236000>;
3422                                 };               3422                                 };
3423                                 opp-6 {          3423                                 opp-6 {
3424                                         opp-p    3424                                         opp-peak-kBps = <15258001>;
3425                                 };               3425                                 };
3426                         };                       3426                         };
3427                 };                               3427                 };
3428                                                  3428 
3429                 system-cache-controller@92000    3429                 system-cache-controller@9200000 {
3430                         compatible = "qcom,sc    3430                         compatible = "qcom,sc8280xp-llcc";
3431                         reg = <0 0x09200000 0    3431                         reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>,
3432                               <0 0x09300000 0    3432                               <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>,
3433                               <0 0x09400000 0    3433                               <0 0x09400000 0 0x58000>, <0 0x09480000 0 0x58000>,
3434                               <0 0x09500000 0    3434                               <0 0x09500000 0 0x58000>, <0 0x09580000 0 0x58000>,
3435                               <0 0x09600000 0    3435                               <0 0x09600000 0 0x58000>;
3436                         reg-names = "llcc0_ba    3436                         reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
3437                                     "llcc3_ba    3437                                     "llcc3_base", "llcc4_base", "llcc5_base",
3438                                     "llcc6_ba    3438                                     "llcc6_base", "llcc7_base",  "llcc_broadcast_base";
3439                         interrupts = <GIC_SPI    3439                         interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
3440                 };                               3440                 };
3441                                                  3441 
3442                 usb_2: usb@a4f8800 {             3442                 usb_2: usb@a4f8800 {
3443                         compatible = "qcom,sc    3443                         compatible = "qcom,sc8280xp-dwc3-mp", "qcom,dwc3";
3444                         reg = <0 0x0a4f8800 0    3444                         reg = <0 0x0a4f8800 0 0x400>;
3445                         #address-cells = <2>;    3445                         #address-cells = <2>;
3446                         #size-cells = <2>;       3446                         #size-cells = <2>;
3447                         ranges;                  3447                         ranges;
3448                                                  3448 
3449                         clocks = <&gcc GCC_CF    3449                         clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>,
3450                                  <&gcc GCC_US    3450                                  <&gcc GCC_USB30_MP_MASTER_CLK>,
3451                                  <&gcc GCC_AG    3451                                  <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>,
3452                                  <&gcc GCC_US    3452                                  <&gcc GCC_USB30_MP_SLEEP_CLK>,
3453                                  <&gcc GCC_US    3453                                  <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
3454                                  <&gcc GCC_AG    3454                                  <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
3455                                  <&gcc GCC_AG    3455                                  <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>,
3456                                  <&gcc GCC_AG    3456                                  <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>,
3457                                  <&gcc GCC_SY    3457                                  <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
3458                         clock-names = "cfg_no    3458                         clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi",
3459                                       "noc_ag    3459                                       "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys";
3460                                                  3460 
3461                         assigned-clocks = <&g    3461                         assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
3462                                           <&g    3462                                           <&gcc GCC_USB30_MP_MASTER_CLK>;
3463                         assigned-clock-rates     3463                         assigned-clock-rates = <19200000>, <200000000>;
3464                                                  3464 
3465                         interrupts-extended =    3465                         interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
3466                                                  3466                                               <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
3467                                                  3467                                               <&intc GIC_SPI 857 IRQ_TYPE_LEVEL_HIGH>,
3468                                                  3468                                               <&intc GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>,
3469                                                  3469                                               <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
3470                                                  3470                                               <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
3471                                                  3471                                               <&intc GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>,
3472                                                  3472                                               <&intc GIC_SPI 859 IRQ_TYPE_LEVEL_HIGH>,
3473                                                  3473                                               <&pdc 127 IRQ_TYPE_EDGE_BOTH>,
3474                                                  3474                                               <&pdc 126 IRQ_TYPE_EDGE_BOTH>,
3475                                                  3475                                               <&pdc 129 IRQ_TYPE_EDGE_BOTH>,
3476                                                  3476                                               <&pdc 128 IRQ_TYPE_EDGE_BOTH>,
3477                                                  3477                                               <&pdc 131 IRQ_TYPE_EDGE_BOTH>,
3478                                                  3478                                               <&pdc 130 IRQ_TYPE_EDGE_BOTH>,
3479                                                  3479                                               <&pdc 133 IRQ_TYPE_EDGE_BOTH>,
3480                                                  3480                                               <&pdc 132 IRQ_TYPE_EDGE_BOTH>,
3481                                                  3481                                               <&pdc 16 IRQ_TYPE_LEVEL_HIGH>,
3482                                                  3482                                               <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
3483                                                  3483 
3484                         interrupt-names = "pw    3484                         interrupt-names = "pwr_event_1", "pwr_event_2",
3485                                           "pw    3485                                           "pwr_event_3", "pwr_event_4",
3486                                           "hs    3486                                           "hs_phy_1",    "hs_phy_2",
3487                                           "hs    3487                                           "hs_phy_3",    "hs_phy_4",
3488                                           "dp    3488                                           "dp_hs_phy_1", "dm_hs_phy_1",
3489                                           "dp    3489                                           "dp_hs_phy_2", "dm_hs_phy_2",
3490                                           "dp    3490                                           "dp_hs_phy_3", "dm_hs_phy_3",
3491                                           "dp    3491                                           "dp_hs_phy_4", "dm_hs_phy_4",
3492                                           "ss    3492                                           "ss_phy_1",    "ss_phy_2";
3493                                                  3493 
3494                         power-domains = <&gcc    3494                         power-domains = <&gcc USB30_MP_GDSC>;
3495                         required-opps = <&rpm    3495                         required-opps = <&rpmhpd_opp_nom>;
3496                                                  3496 
3497                         resets = <&gcc GCC_US    3497                         resets = <&gcc GCC_USB30_MP_BCR>;
3498                                                  3498 
3499                         interconnects = <&agg    3499                         interconnects = <&aggre1_noc MASTER_USB3_MP 0 &mc_virt SLAVE_EBI1 0>,
3500                                         <&gem    3500                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_MP 0>;
3501                         interconnect-names =     3501                         interconnect-names = "usb-ddr", "apps-usb";
3502                                                  3502 
3503                         wakeup-source;           3503                         wakeup-source;
3504                                                  3504 
3505                         status = "disabled";     3505                         status = "disabled";
3506                                                  3506 
3507                         usb_2_dwc3: usb@a4000    3507                         usb_2_dwc3: usb@a400000 {
3508                                 compatible =     3508                                 compatible = "snps,dwc3";
3509                                 reg = <0 0x0a    3509                                 reg = <0 0x0a400000 0 0xcd00>;
3510                                 interrupts =     3510                                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
3511                                 iommus = <&ap    3511                                 iommus = <&apps_smmu 0x800 0x0>;
3512                                 phys = <&usb_    3512                                 phys = <&usb_2_hsphy0>, <&usb_2_qmpphy0>,
3513                                        <&usb_    3513                                        <&usb_2_hsphy1>, <&usb_2_qmpphy1>,
3514                                        <&usb_    3514                                        <&usb_2_hsphy2>,
3515                                        <&usb_    3515                                        <&usb_2_hsphy3>;
3516                                 phy-names = "    3516                                 phy-names = "usb2-0", "usb3-0",
3517                                             "    3517                                             "usb2-1", "usb3-1",
3518                                             "    3518                                             "usb2-2",
3519                                             "    3519                                             "usb2-3";
3520                                 dr_mode = "ho    3520                                 dr_mode = "host";
3521                         };                       3521                         };
3522                 };                               3522                 };
3523                                                  3523 
3524                 usb_0: usb@a6f8800 {             3524                 usb_0: usb@a6f8800 {
3525                         compatible = "qcom,sc    3525                         compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3";
3526                         reg = <0 0x0a6f8800 0    3526                         reg = <0 0x0a6f8800 0 0x400>;
3527                         #address-cells = <2>;    3527                         #address-cells = <2>;
3528                         #size-cells = <2>;       3528                         #size-cells = <2>;
3529                         ranges;                  3529                         ranges;
3530                                                  3530 
3531                         clocks = <&gcc GCC_CF    3531                         clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
3532                                  <&gcc GCC_US    3532                                  <&gcc GCC_USB30_PRIM_MASTER_CLK>,
3533                                  <&gcc GCC_AG    3533                                  <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
3534                                  <&gcc GCC_US    3534                                  <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
3535                                  <&gcc GCC_US    3535                                  <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3536                                  <&gcc GCC_AG    3536                                  <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
3537                                  <&gcc GCC_AG    3537                                  <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>,
3538                                  <&gcc GCC_AG    3538                                  <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>,
3539                                  <&gcc GCC_SY    3539                                  <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
3540                         clock-names = "cfg_no    3540                         clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi",
3541                                       "noc_ag    3541                                       "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys";
3542                                                  3542 
3543                         assigned-clocks = <&g    3543                         assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3544                                           <&g    3544                                           <&gcc GCC_USB30_PRIM_MASTER_CLK>;
3545                         assigned-clock-rates     3545                         assigned-clock-rates = <19200000>, <200000000>;
3546                                                  3546 
3547                         interrupts-extended =    3547                         interrupts-extended = <&intc GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>,
3548                                                  3548                                               <&intc GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>,
3549                                                  3549                                               <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
3550                                                  3550                                               <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
3551                                                  3551                                               <&pdc 138 IRQ_TYPE_LEVEL_HIGH>;
3552                         interrupt-names = "pw    3552                         interrupt-names = "pwr_event",
3553                                           "hs    3553                                           "hs_phy_irq",
3554                                           "dp    3554                                           "dp_hs_phy_irq",
3555                                           "dm    3555                                           "dm_hs_phy_irq",
3556                                           "ss    3556                                           "ss_phy_irq";
3557                                                  3557 
3558                         power-domains = <&gcc    3558                         power-domains = <&gcc USB30_PRIM_GDSC>;
3559                         required-opps = <&rpm    3559                         required-opps = <&rpmhpd_opp_nom>;
3560                                                  3560 
3561                         resets = <&gcc GCC_US    3561                         resets = <&gcc GCC_USB30_PRIM_BCR>;
3562                                                  3562 
3563                         interconnects = <&agg    3563                         interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
3564                                         <&gem    3564                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
3565                         interconnect-names =     3565                         interconnect-names = "usb-ddr", "apps-usb";
3566                                                  3566 
3567                         wakeup-source;           3567                         wakeup-source;
3568                                                  3568 
3569                         status = "disabled";     3569                         status = "disabled";
3570                                                  3570 
3571                         usb_0_dwc3: usb@a6000    3571                         usb_0_dwc3: usb@a600000 {
3572                                 compatible =     3572                                 compatible = "snps,dwc3";
3573                                 reg = <0 0x0a    3573                                 reg = <0 0x0a600000 0 0xcd00>;
3574                                 interrupts =     3574                                 interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>;
3575                                 iommus = <&ap    3575                                 iommus = <&apps_smmu 0x820 0x0>;
3576                                 phys = <&usb_    3576                                 phys = <&usb_0_hsphy>, <&usb_0_qmpphy QMP_USB43DP_USB3_PHY>;
3577                                 phy-names = "    3577                                 phy-names = "usb2-phy", "usb3-phy";
3578                                                  3578 
3579                                 ports {          3579                                 ports {
3580                                         #addr    3580                                         #address-cells = <1>;
3581                                         #size    3581                                         #size-cells = <0>;
3582                                                  3582 
3583                                         port@    3583                                         port@0 {
3584                                                  3584                                                 reg = <0>;
3585                                                  3585 
3586                                                  3586                                                 usb_0_dwc3_hs: endpoint {
3587                                                  3587                                                 };
3588                                         };       3588                                         };
3589                                                  3589 
3590                                         port@    3590                                         port@1 {
3591                                                  3591                                                 reg = <1>;
3592                                                  3592 
3593                                                  3593                                                 usb_0_dwc3_ss: endpoint {
3594                                                  3594                                                         remote-endpoint = <&usb_0_qmpphy_usb_ss_in>;
3595                                                  3595                                                 };
3596                                         };       3596                                         };
3597                                 };               3597                                 };
3598                         };                       3598                         };
3599                 };                               3599                 };
3600                                                  3600 
3601                 usb_1: usb@a8f8800 {             3601                 usb_1: usb@a8f8800 {
3602                         compatible = "qcom,sc    3602                         compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3";
3603                         reg = <0 0x0a8f8800 0    3603                         reg = <0 0x0a8f8800 0 0x400>;
3604                         #address-cells = <2>;    3604                         #address-cells = <2>;
3605                         #size-cells = <2>;       3605                         #size-cells = <2>;
3606                         ranges;                  3606                         ranges;
3607                                                  3607 
3608                         clocks = <&gcc GCC_CF    3608                         clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
3609                                  <&gcc GCC_US    3609                                  <&gcc GCC_USB30_SEC_MASTER_CLK>,
3610                                  <&gcc GCC_AG    3610                                  <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
3611                                  <&gcc GCC_US    3611                                  <&gcc GCC_USB30_SEC_SLEEP_CLK>,
3612                                  <&gcc GCC_US    3612                                  <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3613                                  <&gcc GCC_AG    3613                                  <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
3614                                  <&gcc GCC_AG    3614                                  <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>,
3615                                  <&gcc GCC_AG    3615                                  <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>,
3616                                  <&gcc GCC_SY    3616                                  <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
3617                         clock-names = "cfg_no    3617                         clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi",
3618                                       "noc_ag    3618                                       "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys";
3619                                                  3619 
3620                         assigned-clocks = <&g    3620                         assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3621                                           <&g    3621                                           <&gcc GCC_USB30_SEC_MASTER_CLK>;
3622                         assigned-clock-rates     3622                         assigned-clock-rates = <19200000>, <200000000>;
3623                                                  3623 
3624                         interrupts-extended =    3624                         interrupts-extended = <&intc GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>,
3625                                                  3625                                               <&intc GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>,
3626                                                  3626                                               <&pdc 12 IRQ_TYPE_EDGE_BOTH>,
3627                                                  3627                                               <&pdc 13 IRQ_TYPE_EDGE_BOTH>,
3628                                                  3628                                               <&pdc 136 IRQ_TYPE_LEVEL_HIGH>;
3629                         interrupt-names = "pw    3629                         interrupt-names = "pwr_event",
3630                                           "hs    3630                                           "hs_phy_irq",
3631                                           "dp    3631                                           "dp_hs_phy_irq",
3632                                           "dm    3632                                           "dm_hs_phy_irq",
3633                                           "ss    3633                                           "ss_phy_irq";
3634                                                  3634 
3635                         power-domains = <&gcc    3635                         power-domains = <&gcc USB30_SEC_GDSC>;
3636                         required-opps = <&rpm    3636                         required-opps = <&rpmhpd_opp_nom>;
3637                                                  3637 
3638                         resets = <&gcc GCC_US    3638                         resets = <&gcc GCC_USB30_SEC_BCR>;
3639                                                  3639 
3640                         interconnects = <&agg    3640                         interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>,
3641                                         <&gem    3641                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
3642                         interconnect-names =     3642                         interconnect-names = "usb-ddr", "apps-usb";
3643                                                  3643 
3644                         wakeup-source;           3644                         wakeup-source;
3645                                                  3645 
3646                         status = "disabled";     3646                         status = "disabled";
3647                                                  3647 
3648                         usb_1_dwc3: usb@a8000    3648                         usb_1_dwc3: usb@a800000 {
3649                                 compatible =     3649                                 compatible = "snps,dwc3";
3650                                 reg = <0 0x0a    3650                                 reg = <0 0x0a800000 0 0xcd00>;
3651                                 interrupts =     3651                                 interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>;
3652                                 iommus = <&ap    3652                                 iommus = <&apps_smmu 0x860 0x0>;
3653                                 phys = <&usb_    3653                                 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
3654                                 phy-names = "    3654                                 phy-names = "usb2-phy", "usb3-phy";
3655                                                  3655 
3656                                 ports {          3656                                 ports {
3657                                         #addr    3657                                         #address-cells = <1>;
3658                                         #size    3658                                         #size-cells = <0>;
3659                                                  3659 
3660                                         port@    3660                                         port@0 {
3661                                                  3661                                                 reg = <0>;
3662                                                  3662 
3663                                                  3663                                                 usb_1_dwc3_hs: endpoint {
3664                                                  3664                                                 };
3665                                         };       3665                                         };
3666                                                  3666 
3667                                         port@    3667                                         port@1 {
3668                                                  3668                                                 reg = <1>;
3669                                                  3669 
3670                                                  3670                                                 usb_1_dwc3_ss: endpoint {
3671                                                  3671                                                         remote-endpoint = <&usb_1_qmpphy_usb_ss_in>;
3672                                                  3672                                                 };
3673                                         };       3673                                         };
3674                                 };               3674                                 };
3675                         };                       3675                         };
3676                 };                               3676                 };
3677                                                  3677 
3678                 cci0: cci@ac4a000 {              3678                 cci0: cci@ac4a000 {
3679                         compatible = "qcom,sc    3679                         compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci";
3680                         reg = <0 0x0ac4a000 0    3680                         reg = <0 0x0ac4a000 0 0x1000>;
3681                                                  3681 
3682                         interrupts = <GIC_SPI    3682                         interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
3683                                                  3683 
3684                         clocks = <&camcc CAMC    3684                         clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>,
3685                                  <&camcc CAMC    3685                                  <&camcc CAMCC_SLOW_AHB_CLK_SRC>,
3686                                  <&camcc CAMC    3686                                  <&camcc CAMCC_CPAS_AHB_CLK>,
3687                                  <&camcc CAMC    3687                                  <&camcc CAMCC_CCI_0_CLK>;
3688                         clock-names = "camnoc    3688                         clock-names = "camnoc_axi",
3689                                       "slow_a    3689                                       "slow_ahb_src",
3690                                       "cpas_a    3690                                       "cpas_ahb",
3691                                       "cci";     3691                                       "cci";
3692                                                  3692 
3693                         power-domains = <&cam    3693                         power-domains = <&camcc TITAN_TOP_GDSC>;
3694                                                  3694 
3695                         pinctrl-0 = <&cci0_de    3695                         pinctrl-0 = <&cci0_default>;
3696                         pinctrl-1 = <&cci0_sl    3696                         pinctrl-1 = <&cci0_sleep>;
3697                         pinctrl-names = "defa    3697                         pinctrl-names = "default", "sleep";
3698                                                  3698 
3699                         #address-cells = <1>;    3699                         #address-cells = <1>;
3700                         #size-cells = <0>;       3700                         #size-cells = <0>;
3701                                                  3701 
3702                         status = "disabled";     3702                         status = "disabled";
3703                                                  3703 
3704                         cci0_i2c0: i2c-bus@0     3704                         cci0_i2c0: i2c-bus@0 {
3705                                 reg = <0>;       3705                                 reg = <0>;
3706                                 clock-frequen    3706                                 clock-frequency = <1000000>;
3707                                 #address-cell    3707                                 #address-cells = <1>;
3708                                 #size-cells =    3708                                 #size-cells = <0>;
3709                         };                       3709                         };
3710                                                  3710 
3711                         cci0_i2c1: i2c-bus@1     3711                         cci0_i2c1: i2c-bus@1 {
3712                                 reg = <1>;       3712                                 reg = <1>;
3713                                 clock-frequen    3713                                 clock-frequency = <1000000>;
3714                                 #address-cell    3714                                 #address-cells = <1>;
3715                                 #size-cells =    3715                                 #size-cells = <0>;
3716                         };                       3716                         };
3717                 };                               3717                 };
3718                                                  3718 
3719                 cci1: cci@ac4b000 {              3719                 cci1: cci@ac4b000 {
3720                         compatible = "qcom,sc    3720                         compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci";
3721                         reg = <0 0x0ac4b000 0    3721                         reg = <0 0x0ac4b000 0 0x1000>;
3722                                                  3722 
3723                         interrupts = <GIC_SPI    3723                         interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>;
3724                                                  3724 
3725                         clocks = <&camcc CAMC    3725                         clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>,
3726                                  <&camcc CAMC    3726                                  <&camcc CAMCC_SLOW_AHB_CLK_SRC>,
3727                                  <&camcc CAMC    3727                                  <&camcc CAMCC_CPAS_AHB_CLK>,
3728                                  <&camcc CAMC    3728                                  <&camcc CAMCC_CCI_1_CLK>;
3729                         clock-names = "camnoc    3729                         clock-names = "camnoc_axi",
3730                                       "slow_a    3730                                       "slow_ahb_src",
3731                                       "cpas_a    3731                                       "cpas_ahb",
3732                                       "cci";     3732                                       "cci";
3733                                                  3733 
3734                         power-domains = <&cam    3734                         power-domains = <&camcc TITAN_TOP_GDSC>;
3735                                                  3735 
3736                         pinctrl-0 = <&cci1_de    3736                         pinctrl-0 = <&cci1_default>;
3737                         pinctrl-1 = <&cci1_sl    3737                         pinctrl-1 = <&cci1_sleep>;
3738                         pinctrl-names = "defa    3738                         pinctrl-names = "default", "sleep";
3739                                                  3739 
3740                         #address-cells = <1>;    3740                         #address-cells = <1>;
3741                         #size-cells = <0>;       3741                         #size-cells = <0>;
3742                                                  3742 
3743                         status = "disabled";     3743                         status = "disabled";
3744                                                  3744 
3745                         cci1_i2c0: i2c-bus@0     3745                         cci1_i2c0: i2c-bus@0 {
3746                                 reg = <0>;       3746                                 reg = <0>;
3747                                 clock-frequen    3747                                 clock-frequency = <1000000>;
3748                                 #address-cell    3748                                 #address-cells = <1>;
3749                                 #size-cells =    3749                                 #size-cells = <0>;
3750                         };                       3750                         };
3751                                                  3751 
3752                         cci1_i2c1: i2c-bus@1     3752                         cci1_i2c1: i2c-bus@1 {
3753                                 reg = <1>;       3753                                 reg = <1>;
3754                                 clock-frequen    3754                                 clock-frequency = <1000000>;
3755                                 #address-cell    3755                                 #address-cells = <1>;
3756                                 #size-cells =    3756                                 #size-cells = <0>;
3757                         };                       3757                         };
3758                 };                               3758                 };
3759                                                  3759 
3760                 cci2: cci@ac4c000 {              3760                 cci2: cci@ac4c000 {
3761                         compatible = "qcom,sc    3761                         compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci";
3762                         reg = <0 0x0ac4c000 0    3762                         reg = <0 0x0ac4c000 0 0x1000>;
3763                                                  3763 
3764                         interrupts = <GIC_SPI    3764                         interrupts = <GIC_SPI 651 IRQ_TYPE_EDGE_RISING>;
3765                                                  3765 
3766                         clocks = <&camcc CAMC    3766                         clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>,
3767                                  <&camcc CAMC    3767                                  <&camcc CAMCC_SLOW_AHB_CLK_SRC>,
3768                                  <&camcc CAMC    3768                                  <&camcc CAMCC_CPAS_AHB_CLK>,
3769                                  <&camcc CAMC    3769                                  <&camcc CAMCC_CCI_2_CLK>;
3770                         clock-names = "camnoc    3770                         clock-names = "camnoc_axi",
3771                                       "slow_a    3771                                       "slow_ahb_src",
3772                                       "cpas_a    3772                                       "cpas_ahb",
3773                                       "cci";     3773                                       "cci";
3774                         power-domains = <&cam    3774                         power-domains = <&camcc TITAN_TOP_GDSC>;
3775                                                  3775 
3776                         pinctrl-0 = <&cci2_de    3776                         pinctrl-0 = <&cci2_default>;
3777                         pinctrl-1 = <&cci2_sl    3777                         pinctrl-1 = <&cci2_sleep>;
3778                         pinctrl-names = "defa    3778                         pinctrl-names = "default", "sleep";
3779                                                  3779 
3780                         #address-cells = <1>;    3780                         #address-cells = <1>;
3781                         #size-cells = <0>;       3781                         #size-cells = <0>;
3782                                                  3782 
3783                         status = "disabled";     3783                         status = "disabled";
3784                                                  3784 
3785                         cci2_i2c0: i2c-bus@0     3785                         cci2_i2c0: i2c-bus@0 {
3786                                 reg = <0>;       3786                                 reg = <0>;
3787                                 clock-frequen    3787                                 clock-frequency = <1000000>;
3788                                 #address-cell    3788                                 #address-cells = <1>;
3789                                 #size-cells =    3789                                 #size-cells = <0>;
3790                         };                       3790                         };
3791                                                  3791 
3792                         cci2_i2c1: i2c-bus@1     3792                         cci2_i2c1: i2c-bus@1 {
3793                                 reg = <1>;       3793                                 reg = <1>;
3794                                 clock-frequen    3794                                 clock-frequency = <1000000>;
3795                                 #address-cell    3795                                 #address-cells = <1>;
3796                                 #size-cells =    3796                                 #size-cells = <0>;
3797                         };                       3797                         };
3798                 };                               3798                 };
3799                                                  3799 
3800                 cci3: cci@ac4d000 {              3800                 cci3: cci@ac4d000 {
3801                         compatible = "qcom,sc    3801                         compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci";
3802                         reg = <0 0x0ac4d000 0    3802                         reg = <0 0x0ac4d000 0 0x1000>;
3803                                                  3803 
3804                         interrupts = <GIC_SPI    3804                         interrupts = <GIC_SPI 650 IRQ_TYPE_EDGE_RISING>;
3805                                                  3805 
3806                         clocks = <&camcc CAMC    3806                         clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>,
3807                                  <&camcc CAMC    3807                                  <&camcc CAMCC_SLOW_AHB_CLK_SRC>,
3808                                  <&camcc CAMC    3808                                  <&camcc CAMCC_CPAS_AHB_CLK>,
3809                                  <&camcc CAMC    3809                                  <&camcc CAMCC_CCI_3_CLK>;
3810                         clock-names = "camnoc    3810                         clock-names = "camnoc_axi",
3811                                       "slow_a    3811                                       "slow_ahb_src",
3812                                       "cpas_a    3812                                       "cpas_ahb",
3813                                       "cci";     3813                                       "cci";
3814                                                  3814 
3815                         power-domains = <&cam    3815                         power-domains = <&camcc TITAN_TOP_GDSC>;
3816                                                  3816 
3817                         pinctrl-0 = <&cci3_de    3817                         pinctrl-0 = <&cci3_default>;
3818                         pinctrl-1 = <&cci3_sl    3818                         pinctrl-1 = <&cci3_sleep>;
3819                         pinctrl-names = "defa    3819                         pinctrl-names = "default", "sleep";
3820                                                  3820 
3821                         #address-cells = <1>;    3821                         #address-cells = <1>;
3822                         #size-cells = <0>;       3822                         #size-cells = <0>;
3823                                                  3823 
3824                         status = "disabled";     3824                         status = "disabled";
3825                                                  3825 
3826                         cci3_i2c0: i2c-bus@0     3826                         cci3_i2c0: i2c-bus@0 {
3827                                 reg = <0>;       3827                                 reg = <0>;
3828                                 clock-frequen    3828                                 clock-frequency = <1000000>;
3829                                 #address-cell    3829                                 #address-cells = <1>;
3830                                 #size-cells =    3830                                 #size-cells = <0>;
3831                         };                       3831                         };
3832                                                  3832 
3833                         cci3_i2c1: i2c-bus@1     3833                         cci3_i2c1: i2c-bus@1 {
3834                                 reg = <1>;       3834                                 reg = <1>;
3835                                 clock-frequen    3835                                 clock-frequency = <1000000>;
3836                                 #address-cell    3836                                 #address-cells = <1>;
3837                                 #size-cells =    3837                                 #size-cells = <0>;
3838                         };                       3838                         };
3839                 };                               3839                 };
3840                                                  3840 
3841                 camss: camss@ac5a000 {           3841                 camss: camss@ac5a000 {
3842                         compatible = "qcom,sc    3842                         compatible = "qcom,sc8280xp-camss";
3843                                                  3843 
3844                         reg = <0 0x0ac5a000 0    3844                         reg = <0 0x0ac5a000 0 0x2000>,
3845                               <0 0x0ac5c000 0    3845                               <0 0x0ac5c000 0 0x2000>,
3846                               <0 0x0ac65000 0    3846                               <0 0x0ac65000 0 0x2000>,
3847                               <0 0x0ac67000 0    3847                               <0 0x0ac67000 0 0x2000>,
3848                               <0 0x0acaf000 0    3848                               <0 0x0acaf000 0 0x4000>,
3849                               <0 0x0acb3000 0    3849                               <0 0x0acb3000 0 0x1000>,
3850                               <0 0x0acb6000 0    3850                               <0 0x0acb6000 0 0x4000>,
3851                               <0 0x0acba000 0    3851                               <0 0x0acba000 0 0x1000>,
3852                               <0 0x0acbd000 0    3852                               <0 0x0acbd000 0 0x4000>,
3853                               <0 0x0acc1000 0    3853                               <0 0x0acc1000 0 0x1000>,
3854                               <0 0x0acc4000 0    3854                               <0 0x0acc4000 0 0x4000>,
3855                               <0 0x0acc8000 0    3855                               <0 0x0acc8000 0 0x1000>,
3856                               <0 0x0accb000 0    3856                               <0 0x0accb000 0 0x4000>,
3857                               <0 0x0accf000 0    3857                               <0 0x0accf000 0 0x1000>,
3858                               <0 0x0acd2000 0    3858                               <0 0x0acd2000 0 0x4000>,
3859                               <0 0x0acd6000 0    3859                               <0 0x0acd6000 0 0x1000>,
3860                               <0 0x0acd9000 0    3860                               <0 0x0acd9000 0 0x4000>,
3861                               <0 0x0acdd000 0    3861                               <0 0x0acdd000 0 0x1000>,
3862                               <0 0x0ace0000 0    3862                               <0 0x0ace0000 0 0x4000>,
3863                               <0 0x0ace4000 0    3863                               <0 0x0ace4000 0 0x1000>;
3864                         reg-names = "csiphy2"    3864                         reg-names = "csiphy2",
3865                                     "csiphy3"    3865                                     "csiphy3",
3866                                     "csiphy0"    3866                                     "csiphy0",
3867                                     "csiphy1"    3867                                     "csiphy1",
3868                                     "vfe0",      3868                                     "vfe0",
3869                                     "csid0",     3869                                     "csid0",
3870                                     "vfe1",      3870                                     "vfe1",
3871                                     "csid1",     3871                                     "csid1",
3872                                     "vfe2",      3872                                     "vfe2",
3873                                     "csid2",     3873                                     "csid2",
3874                                     "vfe_lite    3874                                     "vfe_lite0",
3875                                     "csid0_li    3875                                     "csid0_lite",
3876                                     "vfe_lite    3876                                     "vfe_lite1",
3877                                     "csid1_li    3877                                     "csid1_lite",
3878                                     "vfe_lite    3878                                     "vfe_lite2",
3879                                     "csid2_li    3879                                     "csid2_lite",
3880                                     "vfe_lite    3880                                     "vfe_lite3",
3881                                     "csid3_li    3881                                     "csid3_lite",
3882                                     "vfe3",      3882                                     "vfe3",
3883                                     "csid3";     3883                                     "csid3";
3884                                                  3884 
3885                         interrupts = <GIC_SPI    3885                         interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
3886                                      <GIC_SPI    3886                                      <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
3887                                      <GIC_SPI    3887                                      <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
3888                                      <GIC_SPI    3888                                      <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
3889                                      <GIC_SPI    3889                                      <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
3890                                      <GIC_SPI    3890                                      <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
3891                                      <GIC_SPI    3891                                      <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
3892                                      <GIC_SPI    3892                                      <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
3893                                      <GIC_SPI    3893                                      <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
3894                                      <GIC_SPI    3894                                      <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
3895                                      <GIC_SPI    3895                                      <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
3896                                      <GIC_SPI    3896                                      <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
3897                                      <GIC_SPI    3897                                      <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>,
3898                                      <GIC_SPI    3898                                      <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
3899                                      <GIC_SPI    3899                                      <GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH>,
3900                                      <GIC_SPI    3900                                      <GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH>,
3901                                      <GIC_SPI    3901                                      <GIC_SPI 760 IRQ_TYPE_LEVEL_HIGH>,
3902                                      <GIC_SPI    3902                                      <GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH>,
3903                                      <GIC_SPI    3903                                      <GIC_SPI 762 IRQ_TYPE_LEVEL_HIGH>,
3904                                      <GIC_SPI    3904                                      <GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH>;
3905                         interrupt-names = "cs    3905                         interrupt-names = "csid1_lite",
3906                                           "vf    3906                                           "vfe_lite1",
3907                                           "cs    3907                                           "csiphy3",
3908                                           "cs    3908                                           "csid0",
3909                                           "vf    3909                                           "vfe0",
3910                                           "cs    3910                                           "csid1",
3911                                           "vf    3911                                           "vfe1",
3912                                           "cs    3912                                           "csid0_lite",
3913                                           "vf    3913                                           "vfe_lite0",
3914                                           "cs    3914                                           "csiphy0",
3915                                           "cs    3915                                           "csiphy1",
3916                                           "cs    3916                                           "csiphy2",
3917                                           "cs    3917                                           "csid2",
3918                                           "vf    3918                                           "vfe2",
3919                                           "cs    3919                                           "csid3_lite",
3920                                           "cs    3920                                           "csid2_lite",
3921                                           "vf    3921                                           "vfe_lite3",
3922                                           "vf    3922                                           "vfe_lite2",
3923                                           "cs    3923                                           "csid3",
3924                                           "vf    3924                                           "vfe3";
3925                                                  3925 
3926                         power-domains = <&cam    3926                         power-domains = <&camcc IFE_0_GDSC>,
3927                                         <&cam    3927                                         <&camcc IFE_1_GDSC>,
3928                                         <&cam    3928                                         <&camcc IFE_2_GDSC>,
3929                                         <&cam    3929                                         <&camcc IFE_3_GDSC>,
3930                                         <&cam    3930                                         <&camcc TITAN_TOP_GDSC>;
3931                         power-domain-names =     3931                         power-domain-names = "ife0",
3932                                                  3932                                              "ife1",
3933                                                  3933                                              "ife2",
3934                                                  3934                                              "ife3",
3935                                                  3935                                              "top";
3936                                                  3936 
3937                         clocks = <&camcc CAMC    3937                         clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>,
3938                                  <&camcc CAMC    3938                                  <&camcc CAMCC_CPAS_AHB_CLK>,
3939                                  <&camcc CAMC    3939                                  <&camcc CAMCC_CSIPHY0_CLK>,
3940                                  <&camcc CAMC    3940                                  <&camcc CAMCC_CSI0PHYTIMER_CLK>,
3941                                  <&camcc CAMC    3941                                  <&camcc CAMCC_CSIPHY1_CLK>,
3942                                  <&camcc CAMC    3942                                  <&camcc CAMCC_CSI1PHYTIMER_CLK>,
3943                                  <&camcc CAMC    3943                                  <&camcc CAMCC_CSIPHY2_CLK>,
3944                                  <&camcc CAMC    3944                                  <&camcc CAMCC_CSI2PHYTIMER_CLK>,
3945                                  <&camcc CAMC    3945                                  <&camcc CAMCC_CSIPHY3_CLK>,
3946                                  <&camcc CAMC    3946                                  <&camcc CAMCC_CSI3PHYTIMER_CLK>,
3947                                  <&camcc CAMC    3947                                  <&camcc CAMCC_IFE_0_AXI_CLK>,
3948                                  <&camcc CAMC    3948                                  <&camcc CAMCC_IFE_0_CLK>,
3949                                  <&camcc CAMC    3949                                  <&camcc CAMCC_IFE_0_CPHY_RX_CLK>,
3950                                  <&camcc CAMC    3950                                  <&camcc CAMCC_IFE_0_CSID_CLK>,
3951                                  <&camcc CAMC    3951                                  <&camcc CAMCC_IFE_1_AXI_CLK>,
3952                                  <&camcc CAMC    3952                                  <&camcc CAMCC_IFE_1_CLK>,
3953                                  <&camcc CAMC    3953                                  <&camcc CAMCC_IFE_1_CPHY_RX_CLK>,
3954                                  <&camcc CAMC    3954                                  <&camcc CAMCC_IFE_1_CSID_CLK>,
3955                                  <&camcc CAMC    3955                                  <&camcc CAMCC_IFE_2_AXI_CLK>,
3956                                  <&camcc CAMC    3956                                  <&camcc CAMCC_IFE_2_CLK>,
3957                                  <&camcc CAMC    3957                                  <&camcc CAMCC_IFE_2_CPHY_RX_CLK>,
3958                                  <&camcc CAMC    3958                                  <&camcc CAMCC_IFE_2_CSID_CLK>,
3959                                  <&camcc CAMC    3959                                  <&camcc CAMCC_IFE_3_AXI_CLK>,
3960                                  <&camcc CAMC    3960                                  <&camcc CAMCC_IFE_3_CLK>,
3961                                  <&camcc CAMC    3961                                  <&camcc CAMCC_IFE_3_CPHY_RX_CLK>,
3962                                  <&camcc CAMC    3962                                  <&camcc CAMCC_IFE_3_CSID_CLK>,
3963                                  <&camcc CAMC    3963                                  <&camcc CAMCC_IFE_LITE_0_CLK>,
3964                                  <&camcc CAMC    3964                                  <&camcc CAMCC_IFE_LITE_0_CPHY_RX_CLK>,
3965                                  <&camcc CAMC    3965                                  <&camcc CAMCC_IFE_LITE_0_CSID_CLK>,
3966                                  <&camcc CAMC    3966                                  <&camcc CAMCC_IFE_LITE_1_CLK>,
3967                                  <&camcc CAMC    3967                                  <&camcc CAMCC_IFE_LITE_1_CPHY_RX_CLK>,
3968                                  <&camcc CAMC    3968                                  <&camcc CAMCC_IFE_LITE_1_CSID_CLK>,
3969                                  <&camcc CAMC    3969                                  <&camcc CAMCC_IFE_LITE_2_CLK>,
3970                                  <&camcc CAMC    3970                                  <&camcc CAMCC_IFE_LITE_2_CPHY_RX_CLK>,
3971                                  <&camcc CAMC    3971                                  <&camcc CAMCC_IFE_LITE_2_CSID_CLK>,
3972                                  <&camcc CAMC    3972                                  <&camcc CAMCC_IFE_LITE_3_CLK>,
3973                                  <&camcc CAMC    3973                                  <&camcc CAMCC_IFE_LITE_3_CPHY_RX_CLK>,
3974                                  <&camcc CAMC    3974                                  <&camcc CAMCC_IFE_LITE_3_CSID_CLK>,
3975                                  <&gcc GCC_CA    3975                                  <&gcc GCC_CAMERA_HF_AXI_CLK>,
3976                                  <&gcc GCC_CA    3976                                  <&gcc GCC_CAMERA_SF_AXI_CLK>;
3977                         clock-names = "camnoc    3977                         clock-names = "camnoc_axi",
3978                                       "cpas_a    3978                                       "cpas_ahb",
3979                                       "csiphy    3979                                       "csiphy0",
3980                                       "csiphy    3980                                       "csiphy0_timer",
3981                                       "csiphy    3981                                       "csiphy1",
3982                                       "csiphy    3982                                       "csiphy1_timer",
3983                                       "csiphy    3983                                       "csiphy2",
3984                                       "csiphy    3984                                       "csiphy2_timer",
3985                                       "csiphy    3985                                       "csiphy3",
3986                                       "csiphy    3986                                       "csiphy3_timer",
3987                                       "vfe0_a    3987                                       "vfe0_axi",
3988                                       "vfe0",    3988                                       "vfe0",
3989                                       "vfe0_c    3989                                       "vfe0_cphy_rx",
3990                                       "vfe0_c    3990                                       "vfe0_csid",
3991                                       "vfe1_a    3991                                       "vfe1_axi",
3992                                       "vfe1",    3992                                       "vfe1",
3993                                       "vfe1_c    3993                                       "vfe1_cphy_rx",
3994                                       "vfe1_c    3994                                       "vfe1_csid",
3995                                       "vfe2_a    3995                                       "vfe2_axi",
3996                                       "vfe2",    3996                                       "vfe2",
3997                                       "vfe2_c    3997                                       "vfe2_cphy_rx",
3998                                       "vfe2_c    3998                                       "vfe2_csid",
3999                                       "vfe3_a    3999                                       "vfe3_axi",
4000                                       "vfe3",    4000                                       "vfe3",
4001                                       "vfe3_c    4001                                       "vfe3_cphy_rx",
4002                                       "vfe3_c    4002                                       "vfe3_csid",
4003                                       "vfe_li    4003                                       "vfe_lite0",
4004                                       "vfe_li    4004                                       "vfe_lite0_cphy_rx",
4005                                       "vfe_li    4005                                       "vfe_lite0_csid",
4006                                       "vfe_li    4006                                       "vfe_lite1",
4007                                       "vfe_li    4007                                       "vfe_lite1_cphy_rx",
4008                                       "vfe_li    4008                                       "vfe_lite1_csid",
4009                                       "vfe_li    4009                                       "vfe_lite2",
4010                                       "vfe_li    4010                                       "vfe_lite2_cphy_rx",
4011                                       "vfe_li    4011                                       "vfe_lite2_csid",
4012                                       "vfe_li    4012                                       "vfe_lite3",
4013                                       "vfe_li    4013                                       "vfe_lite3_cphy_rx",
4014                                       "vfe_li    4014                                       "vfe_lite3_csid",
4015                                       "gcc_ax    4015                                       "gcc_axi_hf",
4016                                       "gcc_ax    4016                                       "gcc_axi_sf";
4017                                                  4017 
4018                         iommus = <&apps_smmu     4018                         iommus = <&apps_smmu 0x2000 0x4e0>,
4019                                  <&apps_smmu     4019                                  <&apps_smmu 0x2020 0x4e0>,
4020                                  <&apps_smmu     4020                                  <&apps_smmu 0x2040 0x4e0>,
4021                                  <&apps_smmu     4021                                  <&apps_smmu 0x2060 0x4e0>,
4022                                  <&apps_smmu     4022                                  <&apps_smmu 0x2080 0x4e0>,
4023                                  <&apps_smmu     4023                                  <&apps_smmu 0x20e0 0x4e0>,
4024                                  <&apps_smmu     4024                                  <&apps_smmu 0x20c0 0x4e0>,
4025                                  <&apps_smmu     4025                                  <&apps_smmu 0x20a0 0x4e0>,
4026                                  <&apps_smmu     4026                                  <&apps_smmu 0x2400 0x4e0>,
4027                                  <&apps_smmu     4027                                  <&apps_smmu 0x2420 0x4e0>,
4028                                  <&apps_smmu     4028                                  <&apps_smmu 0x2440 0x4e0>,
4029                                  <&apps_smmu     4029                                  <&apps_smmu 0x2460 0x4e0>,
4030                                  <&apps_smmu     4030                                  <&apps_smmu 0x2480 0x4e0>,
4031                                  <&apps_smmu     4031                                  <&apps_smmu 0x24e0 0x4e0>,
4032                                  <&apps_smmu     4032                                  <&apps_smmu 0x24c0 0x4e0>,
4033                                  <&apps_smmu     4033                                  <&apps_smmu 0x24a0 0x4e0>;
4034                                                  4034 
4035                         interconnects = <&gem    4035                         interconnects = <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_CAMERA_CFG 0>,
4036                                         <&mms    4036                                         <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI1 0>,
4037                                         <&mms    4037                                         <&mmss_noc MASTER_CAMNOC_SF 0 &mc_virt SLAVE_EBI1 0>,
4038                                         <&mms    4038                                         <&mmss_noc MASTER_CAMNOC_ICP 0 &mc_virt SLAVE_EBI1 0>;
4039                         interconnect-names =     4039                         interconnect-names = "cam_ahb",
4040                                                  4040                                              "cam_hf_mnoc",
4041                                                  4041                                              "cam_sf_mnoc",
4042                                                  4042                                              "cam_sf_icp_mnoc";
4043                                                  4043 
4044                         status = "disabled";     4044                         status = "disabled";
4045                                                  4045 
4046                         ports {                  4046                         ports {
4047                                 #address-cell    4047                                 #address-cells = <1>;
4048                                 #size-cells =    4048                                 #size-cells = <0>;
4049                                                  4049 
4050                                 port@0 {         4050                                 port@0 {
4051                                         reg =    4051                                         reg = <0>;
4052                                         #addr    4052                                         #address-cells = <1>;
4053                                         #size    4053                                         #size-cells = <0>;
4054                                 };               4054                                 };
4055                                                  4055 
4056                                 port@1 {         4056                                 port@1 {
4057                                         reg =    4057                                         reg = <1>;
4058                                         #addr    4058                                         #address-cells = <1>;
4059                                         #size    4059                                         #size-cells = <0>;
4060                                 };               4060                                 };
4061                                                  4061 
4062                                 port@2 {         4062                                 port@2 {
4063                                         reg =    4063                                         reg = <2>;
4064                                         #addr    4064                                         #address-cells = <1>;
4065                                         #size    4065                                         #size-cells = <0>;
4066                                 };               4066                                 };
4067                                                  4067 
4068                                 port@3 {         4068                                 port@3 {
4069                                         reg =    4069                                         reg = <3>;
4070                                         #addr    4070                                         #address-cells = <1>;
4071                                         #size    4071                                         #size-cells = <0>;
4072                                 };               4072                                 };
4073                         };                       4073                         };
4074                 };                               4074                 };
4075                                                  4075 
4076                 camcc: clock-controller@ad000    4076                 camcc: clock-controller@ad00000 {
4077                         compatible = "qcom,sc    4077                         compatible = "qcom,sc8280xp-camcc";
4078                         reg = <0 0x0ad00000 0    4078                         reg = <0 0x0ad00000 0 0x20000>;
4079                         clocks = <&gcc GCC_CA    4079                         clocks = <&gcc GCC_CAMERA_AHB_CLK>,
4080                                  <&rpmhcc RPM    4080                                  <&rpmhcc RPMH_CXO_CLK>,
4081                                  <&rpmhcc RPM    4081                                  <&rpmhcc RPMH_CXO_CLK_A>,
4082                                  <&sleep_clk>    4082                                  <&sleep_clk>;
4083                         power-domains = <&rpm    4083                         power-domains = <&rpmhpd SC8280XP_MMCX>;
4084                         required-opps = <&rpm    4084                         required-opps = <&rpmhpd_opp_low_svs>;
4085                         #clock-cells = <1>;      4085                         #clock-cells = <1>;
4086                         #reset-cells = <1>;      4086                         #reset-cells = <1>;
4087                         #power-domain-cells =    4087                         #power-domain-cells = <1>;
4088                 };                               4088                 };
4089                                                  4089 
4090                 mdss0: display-subsystem@ae00    4090                 mdss0: display-subsystem@ae00000 {
4091                         compatible = "qcom,sc    4091                         compatible = "qcom,sc8280xp-mdss";
4092                         reg = <0 0x0ae00000 0    4092                         reg = <0 0x0ae00000 0 0x1000>;
4093                         reg-names = "mdss";      4093                         reg-names = "mdss";
4094                                                  4094 
4095                         clocks = <&gcc GCC_DI    4095                         clocks = <&gcc GCC_DISP_AHB_CLK>,
4096                                  <&dispcc0 DI    4096                                  <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
4097                                  <&dispcc0 DI    4097                                  <&dispcc0 DISP_CC_MDSS_MDP_CLK>;
4098                         clock-names = "iface"    4098                         clock-names = "iface",
4099                                       "ahb",     4099                                       "ahb",
4100                                       "core";    4100                                       "core";
4101                         interrupts = <GIC_SPI    4101                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
4102                         interconnects = <&mms    4102                         interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
4103                                         <&mms    4103                                         <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>;
4104                         interconnect-names =     4104                         interconnect-names = "mdp0-mem", "mdp1-mem";
4105                         iommus = <&apps_smmu     4105                         iommus = <&apps_smmu 0x1000 0x402>;
4106                         power-domains = <&dis    4106                         power-domains = <&dispcc0 MDSS_GDSC>;
4107                         resets = <&dispcc0 DI    4107                         resets = <&dispcc0 DISP_CC_MDSS_CORE_BCR>;
4108                                                  4108 
4109                         interrupt-controller;    4109                         interrupt-controller;
4110                         #interrupt-cells = <1    4110                         #interrupt-cells = <1>;
4111                         #address-cells = <2>;    4111                         #address-cells = <2>;
4112                         #size-cells = <2>;       4112                         #size-cells = <2>;
4113                         ranges;                  4113                         ranges;
4114                                                  4114 
4115                         status = "disabled";     4115                         status = "disabled";
4116                                                  4116 
4117                         mdss0_mdp: display-co    4117                         mdss0_mdp: display-controller@ae01000 {
4118                                 compatible =     4118                                 compatible = "qcom,sc8280xp-dpu";
4119                                 reg = <0 0x0a    4119                                 reg = <0 0x0ae01000 0 0x8f000>,
4120                                       <0 0x0a    4120                                       <0 0x0aeb0000 0 0x2008>;
4121                                 reg-names = "    4121                                 reg-names = "mdp", "vbif";
4122                                                  4122 
4123                                 clocks = <&gc    4123                                 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
4124                                          <&gc    4124                                          <&gcc GCC_DISP_SF_AXI_CLK>,
4125                                          <&di    4125                                          <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
4126                                          <&di    4126                                          <&dispcc0 DISP_CC_MDSS_MDP_LUT_CLK>,
4127                                          <&di    4127                                          <&dispcc0 DISP_CC_MDSS_MDP_CLK>,
4128                                          <&di    4128                                          <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;
4129                                 clock-names =    4129                                 clock-names = "bus",
4130                                                  4130                                               "nrt_bus",
4131                                                  4131                                               "iface",
4132                                                  4132                                               "lut",
4133                                                  4133                                               "core",
4134                                                  4134                                               "vsync";
4135                                 interrupt-par    4135                                 interrupt-parent = <&mdss0>;
4136                                 interrupts =     4136                                 interrupts = <0>;
4137                                 power-domains    4137                                 power-domains = <&rpmhpd SC8280XP_MMCX>;
4138                                                  4138 
4139                                 assigned-cloc    4139                                 assigned-clocks = <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;
4140                                 assigned-cloc    4140                                 assigned-clock-rates = <19200000>;
4141                                 operating-poi    4141                                 operating-points-v2 = <&mdss0_mdp_opp_table>;
4142                                                  4142 
4143                                 ports {          4143                                 ports {
4144                                         #addr    4144                                         #address-cells = <1>;
4145                                         #size    4145                                         #size-cells = <0>;
4146                                                  4146 
4147                                         port@    4147                                         port@0 {
4148                                                  4148                                                 reg = <0>;
4149                                                  4149                                                 mdss0_intf0_out: endpoint {
4150                                                  4150                                                         remote-endpoint = <&mdss0_dp0_in>;
4151                                                  4151                                                 };
4152                                         };       4152                                         };
4153                                                  4153 
4154                                         port@    4154                                         port@4 {
4155                                                  4155                                                 reg = <4>;
4156                                                  4156                                                 mdss0_intf4_out: endpoint {
4157                                                  4157                                                         remote-endpoint = <&mdss0_dp1_in>;
4158                                                  4158                                                 };
4159                                         };       4159                                         };
4160                                                  4160 
4161                                         port@    4161                                         port@5 {
4162                                                  4162                                                 reg = <5>;
4163                                                  4163                                                 mdss0_intf5_out: endpoint {
4164                                                  4164                                                         remote-endpoint = <&mdss0_dp3_in>;
4165                                                  4165                                                 };
4166                                         };       4166                                         };
4167                                                  4167 
4168                                         port@    4168                                         port@6 {
4169                                                  4169                                                 reg = <6>;
4170                                                  4170                                                 mdss0_intf6_out: endpoint {
4171                                                  4171                                                         remote-endpoint = <&mdss0_dp2_in>;
4172                                                  4172                                                 };
4173                                         };       4173                                         };
4174                                 };               4174                                 };
4175                                                  4175 
4176                                 mdss0_mdp_opp    4176                                 mdss0_mdp_opp_table: opp-table {
4177                                         compa    4177                                         compatible = "operating-points-v2";
4178                                                  4178 
4179                                         opp-2    4179                                         opp-200000000 {
4180                                                  4180                                                 opp-hz = /bits/ 64 <200000000>;
4181                                                  4181                                                 required-opps = <&rpmhpd_opp_low_svs>;
4182                                         };       4182                                         };
4183                                                  4183 
4184                                         opp-3    4184                                         opp-300000000 {
4185                                                  4185                                                 opp-hz = /bits/ 64 <300000000>;
4186                                                  4186                                                 required-opps = <&rpmhpd_opp_svs>;
4187                                         };       4187                                         };
4188                                                  4188 
4189                                         opp-3    4189                                         opp-375000000 {
4190                                                  4190                                                 opp-hz = /bits/ 64 <375000000>;
4191                                                  4191                                                 required-opps = <&rpmhpd_opp_svs_l1>;
4192                                         };       4192                                         };
4193                                                  4193 
4194                                         opp-5    4194                                         opp-500000000 {
4195                                                  4195                                                 opp-hz = /bits/ 64 <500000000>;
4196                                                  4196                                                 required-opps = <&rpmhpd_opp_nom>;
4197                                         };       4197                                         };
4198                                         opp-6    4198                                         opp-600000000 {
4199                                                  4199                                                 opp-hz = /bits/ 64 <600000000>;
4200                                                  4200                                                 required-opps = <&rpmhpd_opp_turbo_l1>;
4201                                         };       4201                                         };
4202                                 };               4202                                 };
4203                         };                       4203                         };
4204                                                  4204 
4205                         mdss0_dp0: displaypor    4205                         mdss0_dp0: displayport-controller@ae90000 {
4206                                 compatible =     4206                                 compatible = "qcom,sc8280xp-dp";
4207                                 reg = <0 0xae    4207                                 reg = <0 0xae90000 0 0x200>,
4208                                       <0 0xae    4208                                       <0 0xae90200 0 0x200>,
4209                                       <0 0xae    4209                                       <0 0xae90400 0 0x600>,
4210                                       <0 0xae    4210                                       <0 0xae91000 0 0x400>,
4211                                       <0 0xae    4211                                       <0 0xae91400 0 0x400>;
4212                                 interrupt-par    4212                                 interrupt-parent = <&mdss0>;
4213                                 interrupts =     4213                                 interrupts = <12>;
4214                                 clocks = <&di    4214                                 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
4215                                          <&di    4215                                          <&dispcc0 DISP_CC_MDSS_DPTX0_AUX_CLK>,
4216                                          <&di    4216                                          <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK>,
4217                                          <&di    4217                                          <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
4218                                          <&di    4218                                          <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
4219                                 clock-names =    4219                                 clock-names = "core_iface", "core_aux",
4220                                                  4220                                               "ctrl_link",
4221                                                  4221                                               "ctrl_link_iface",
4222                                                  4222                                               "stream_pixel";
4223                                                  4223 
4224                                 assigned-cloc    4224                                 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
4225                                                  4225                                                   <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
4226                                 assigned-cloc    4226                                 assigned-clock-parents = <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4227                                                  4227                                                          <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
4228                                                  4228 
4229                                 phys = <&usb_    4229                                 phys = <&usb_0_qmpphy QMP_USB43DP_DP_PHY>;
4230                                 phy-names = "    4230                                 phy-names = "dp";
4231                                                  4231 
4232                                 #sound-dai-ce    4232                                 #sound-dai-cells = <0>;
4233                                                  4233 
4234                                 operating-poi    4234                                 operating-points-v2 = <&mdss0_dp0_opp_table>;
4235                                 power-domains    4235                                 power-domains = <&rpmhpd SC8280XP_MMCX>;
4236                                                  4236 
4237                                 status = "dis    4237                                 status = "disabled";
4238                                                  4238 
4239                                 ports {          4239                                 ports {
4240                                         #addr    4240                                         #address-cells = <1>;
4241                                         #size    4241                                         #size-cells = <0>;
4242                                                  4242 
4243                                         port@    4243                                         port@0 {
4244                                                  4244                                                 reg = <0>;
4245                                                  4245 
4246                                                  4246                                                 mdss0_dp0_in: endpoint {
4247                                                  4247                                                         remote-endpoint = <&mdss0_intf0_out>;
4248                                                  4248                                                 };
4249                                         };       4249                                         };
4250                                                  4250 
4251                                         port@    4251                                         port@1 {
4252                                                  4252                                                 reg = <1>;
4253                                                  4253 
4254                                                  4254                                                 mdss0_dp0_out: endpoint {
4255                                                  4255                                                 };
4256                                         };       4256                                         };
4257                                 };               4257                                 };
4258                                                  4258 
4259                                 mdss0_dp0_opp    4259                                 mdss0_dp0_opp_table: opp-table {
4260                                         compa    4260                                         compatible = "operating-points-v2";
4261                                                  4261 
4262                                         opp-1    4262                                         opp-160000000 {
4263                                                  4263                                                 opp-hz = /bits/ 64 <160000000>;
4264                                                  4264                                                 required-opps = <&rpmhpd_opp_low_svs>;
4265                                         };       4265                                         };
4266                                                  4266 
4267                                         opp-2    4267                                         opp-270000000 {
4268                                                  4268                                                 opp-hz = /bits/ 64 <270000000>;
4269                                                  4269                                                 required-opps = <&rpmhpd_opp_svs>;
4270                                         };       4270                                         };
4271                                                  4271 
4272                                         opp-5    4272                                         opp-540000000 {
4273                                                  4273                                                 opp-hz = /bits/ 64 <540000000>;
4274                                                  4274                                                 required-opps = <&rpmhpd_opp_svs_l1>;
4275                                         };       4275                                         };
4276                                                  4276 
4277                                         opp-8    4277                                         opp-810000000 {
4278                                                  4278                                                 opp-hz = /bits/ 64 <810000000>;
4279                                                  4279                                                 required-opps = <&rpmhpd_opp_nom>;
4280                                         };       4280                                         };
4281                                 };               4281                                 };
4282                         };                       4282                         };
4283                                                  4283 
4284                         mdss0_dp1: displaypor    4284                         mdss0_dp1: displayport-controller@ae98000 {
4285                                 compatible =     4285                                 compatible = "qcom,sc8280xp-dp";
4286                                 reg = <0 0xae    4286                                 reg = <0 0xae98000 0 0x200>,
4287                                       <0 0xae    4287                                       <0 0xae98200 0 0x200>,
4288                                       <0 0xae    4288                                       <0 0xae98400 0 0x600>,
4289                                       <0 0xae    4289                                       <0 0xae99000 0 0x400>,
4290                                       <0 0xae    4290                                       <0 0xae99400 0 0x400>;
4291                                 interrupt-par    4291                                 interrupt-parent = <&mdss0>;
4292                                 interrupts =     4292                                 interrupts = <13>;
4293                                 clocks = <&di    4293                                 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
4294                                          <&di    4294                                          <&dispcc0 DISP_CC_MDSS_DPTX1_AUX_CLK>,
4295                                          <&di    4295                                          <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK>,
4296                                          <&di    4296                                          <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
4297                                          <&di    4297                                          <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>;
4298                                 clock-names =    4298                                 clock-names = "core_iface", "core_aux",
4299                                                  4299                                               "ctrl_link",
4300                                                  4300                                               "ctrl_link_iface", "stream_pixel";
4301                                                  4301 
4302                                 assigned-cloc    4302                                 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
4303                                                  4303                                                   <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>;
4304                                 assigned-cloc    4304                                 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4305                                                  4305                                                          <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
4306                                                  4306 
4307                                 phys = <&usb_    4307                                 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
4308                                 phy-names = "    4308                                 phy-names = "dp";
4309                                                  4309 
4310                                 #sound-dai-ce    4310                                 #sound-dai-cells = <0>;
4311                                                  4311 
4312                                 operating-poi    4312                                 operating-points-v2 = <&mdss0_dp1_opp_table>;
4313                                 power-domains    4313                                 power-domains = <&rpmhpd SC8280XP_MMCX>;
4314                                                  4314 
4315                                 status = "dis    4315                                 status = "disabled";
4316                                                  4316 
4317                                 ports {          4317                                 ports {
4318                                         #addr    4318                                         #address-cells = <1>;
4319                                         #size    4319                                         #size-cells = <0>;
4320                                                  4320 
4321                                         port@    4321                                         port@0 {
4322                                                  4322                                                 reg = <0>;
4323                                                  4323 
4324                                                  4324                                                 mdss0_dp1_in: endpoint {
4325                                                  4325                                                         remote-endpoint = <&mdss0_intf4_out>;
4326                                                  4326                                                 };
4327                                         };       4327                                         };
4328                                                  4328 
4329                                         port@    4329                                         port@1 {
4330                                                  4330                                                 reg = <1>;
4331                                                  4331 
4332                                                  4332                                                 mdss0_dp1_out: endpoint {
4333                                                  4333                                                 };
4334                                         };       4334                                         };
4335                                 };               4335                                 };
4336                                                  4336 
4337                                 mdss0_dp1_opp    4337                                 mdss0_dp1_opp_table: opp-table {
4338                                         compa    4338                                         compatible = "operating-points-v2";
4339                                                  4339 
4340                                         opp-1    4340                                         opp-160000000 {
4341                                                  4341                                                 opp-hz = /bits/ 64 <160000000>;
4342                                                  4342                                                 required-opps = <&rpmhpd_opp_low_svs>;
4343                                         };       4343                                         };
4344                                                  4344 
4345                                         opp-2    4345                                         opp-270000000 {
4346                                                  4346                                                 opp-hz = /bits/ 64 <270000000>;
4347                                                  4347                                                 required-opps = <&rpmhpd_opp_svs>;
4348                                         };       4348                                         };
4349                                                  4349 
4350                                         opp-5    4350                                         opp-540000000 {
4351                                                  4351                                                 opp-hz = /bits/ 64 <540000000>;
4352                                                  4352                                                 required-opps = <&rpmhpd_opp_svs_l1>;
4353                                         };       4353                                         };
4354                                                  4354 
4355                                         opp-8    4355                                         opp-810000000 {
4356                                                  4356                                                 opp-hz = /bits/ 64 <810000000>;
4357                                                  4357                                                 required-opps = <&rpmhpd_opp_nom>;
4358                                         };       4358                                         };
4359                                 };               4359                                 };
4360                         };                       4360                         };
4361                                                  4361 
4362                         mdss0_dp2: displaypor    4362                         mdss0_dp2: displayport-controller@ae9a000 {
4363                                 compatible =     4363                                 compatible = "qcom,sc8280xp-dp";
4364                                 reg = <0 0xae    4364                                 reg = <0 0xae9a000 0 0x200>,
4365                                       <0 0xae    4365                                       <0 0xae9a200 0 0x200>,
4366                                       <0 0xae    4366                                       <0 0xae9a400 0 0x600>,
4367                                       <0 0xae    4367                                       <0 0xae9b000 0 0x400>,
4368                                       <0 0xae    4368                                       <0 0xae9b400 0 0x400>;
4369                                                  4369 
4370                                 clocks = <&di    4370                                 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
4371                                          <&di    4371                                          <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>,
4372                                          <&di    4372                                          <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK>,
4373                                          <&di    4373                                          <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>,
4374                                          <&di    4374                                          <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>;
4375                                 clock-names =    4375                                 clock-names = "core_iface", "core_aux",
4376                                                  4376                                               "ctrl_link",
4377                                                  4377                                               "ctrl_link_iface", "stream_pixel";
4378                                 interrupt-par    4378                                 interrupt-parent = <&mdss0>;
4379                                 interrupts =     4379                                 interrupts = <14>;
4380                                 phys = <&mdss    4380                                 phys = <&mdss0_dp2_phy>;
4381                                 phy-names = "    4381                                 phy-names = "dp";
4382                                 power-domains    4382                                 power-domains = <&rpmhpd SC8280XP_MMCX>;
4383                                                  4383 
4384                                 assigned-cloc    4384                                 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
4385                                                  4385                                                   <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>;
4386                                 assigned-cloc    4386                                 assigned-clock-parents = <&mdss0_dp2_phy 0>, <&mdss0_dp2_phy 1>;
4387                                 operating-poi    4387                                 operating-points-v2 = <&mdss0_dp2_opp_table>;
4388                                                  4388 
4389                                 #sound-dai-ce    4389                                 #sound-dai-cells = <0>;
4390                                                  4390 
4391                                 status = "dis    4391                                 status = "disabled";
4392                                                  4392 
4393                                 ports {          4393                                 ports {
4394                                         #addr    4394                                         #address-cells = <1>;
4395                                         #size    4395                                         #size-cells = <0>;
4396                                                  4396 
4397                                         port@    4397                                         port@0 {
4398                                                  4398                                                 reg = <0>;
4399                                                  4399                                                 mdss0_dp2_in: endpoint {
4400                                                  4400                                                         remote-endpoint = <&mdss0_intf6_out>;
4401                                                  4401                                                 };
4402                                         };       4402                                         };
4403                                                  4403 
4404                                         port@    4404                                         port@1 {
4405                                                  4405                                                 reg = <1>;
4406                                         };       4406                                         };
4407                                 };               4407                                 };
4408                                                  4408 
4409                                 mdss0_dp2_opp    4409                                 mdss0_dp2_opp_table: opp-table {
4410                                         compa    4410                                         compatible = "operating-points-v2";
4411                                                  4411 
4412                                         opp-1    4412                                         opp-160000000 {
4413                                                  4413                                                 opp-hz = /bits/ 64 <160000000>;
4414                                                  4414                                                 required-opps = <&rpmhpd_opp_low_svs>;
4415                                         };       4415                                         };
4416                                                  4416 
4417                                         opp-2    4417                                         opp-270000000 {
4418                                                  4418                                                 opp-hz = /bits/ 64 <270000000>;
4419                                                  4419                                                 required-opps = <&rpmhpd_opp_svs>;
4420                                         };       4420                                         };
4421                                                  4421 
4422                                         opp-5    4422                                         opp-540000000 {
4423                                                  4423                                                 opp-hz = /bits/ 64 <540000000>;
4424                                                  4424                                                 required-opps = <&rpmhpd_opp_svs_l1>;
4425                                         };       4425                                         };
4426                                                  4426 
4427                                         opp-8    4427                                         opp-810000000 {
4428                                                  4428                                                 opp-hz = /bits/ 64 <810000000>;
4429                                                  4429                                                 required-opps = <&rpmhpd_opp_nom>;
4430                                         };       4430                                         };
4431                                 };               4431                                 };
4432                         };                       4432                         };
4433                                                  4433 
4434                         mdss0_dp3: displaypor    4434                         mdss0_dp3: displayport-controller@aea0000 {
4435                                 compatible =     4435                                 compatible = "qcom,sc8280xp-dp";
4436                                 reg = <0 0xae    4436                                 reg = <0 0xaea0000 0 0x200>,
4437                                       <0 0xae    4437                                       <0 0xaea0200 0 0x200>,
4438                                       <0 0xae    4438                                       <0 0xaea0400 0 0x600>,
4439                                       <0 0xae    4439                                       <0 0xaea1000 0 0x400>,
4440                                       <0 0xae    4440                                       <0 0xaea1400 0 0x400>;
4441                                                  4441 
4442                                 clocks = <&di    4442                                 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
4443                                          <&di    4443                                          <&dispcc0 DISP_CC_MDSS_DPTX3_AUX_CLK>,
4444                                          <&di    4444                                          <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_CLK>,
4445                                          <&di    4445                                          <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>,
4446                                          <&di    4446                                          <&dispcc0 DISP_CC_MDSS_DPTX3_PIXEL0_CLK>;
4447                                 clock-names =    4447                                 clock-names = "core_iface", "core_aux",
4448                                                  4448                                               "ctrl_link",
4449                                                  4449                                               "ctrl_link_iface", "stream_pixel";
4450                                 interrupt-par    4450                                 interrupt-parent = <&mdss0>;
4451                                 interrupts =     4451                                 interrupts = <15>;
4452                                 phys = <&mdss    4452                                 phys = <&mdss0_dp3_phy>;
4453                                 phy-names = "    4453                                 phy-names = "dp";
4454                                 power-domains    4454                                 power-domains = <&rpmhpd SC8280XP_MMCX>;
4455                                                  4455 
4456                                 assigned-cloc    4456                                 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>,
4457                                                  4457                                                   <&dispcc0 DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>;
4458                                 assigned-cloc    4458                                 assigned-clock-parents = <&mdss0_dp3_phy 0>, <&mdss0_dp3_phy 1>;
4459                                 operating-poi    4459                                 operating-points-v2 = <&mdss0_dp3_opp_table>;
4460                                                  4460 
4461                                 #sound-dai-ce    4461                                 #sound-dai-cells = <0>;
4462                                                  4462 
4463                                 status = "dis    4463                                 status = "disabled";
4464                                                  4464 
4465                                 ports {          4465                                 ports {
4466                                         #addr    4466                                         #address-cells = <1>;
4467                                         #size    4467                                         #size-cells = <0>;
4468                                                  4468 
4469                                         port@    4469                                         port@0 {
4470                                                  4470                                                 reg = <0>;
4471                                                  4471                                                 mdss0_dp3_in: endpoint {
4472                                                  4472                                                         remote-endpoint = <&mdss0_intf5_out>;
4473                                                  4473                                                 };
4474                                         };       4474                                         };
4475                                                  4475 
4476                                         port@    4476                                         port@1 {
4477                                                  4477                                                 reg = <1>;
4478                                         };       4478                                         };
4479                                 };               4479                                 };
4480                                                  4480 
4481                                 mdss0_dp3_opp    4481                                 mdss0_dp3_opp_table: opp-table {
4482                                         compa    4482                                         compatible = "operating-points-v2";
4483                                                  4483 
4484                                         opp-1    4484                                         opp-160000000 {
4485                                                  4485                                                 opp-hz = /bits/ 64 <160000000>;
4486                                                  4486                                                 required-opps = <&rpmhpd_opp_low_svs>;
4487                                         };       4487                                         };
4488                                                  4488 
4489                                         opp-2    4489                                         opp-270000000 {
4490                                                  4490                                                 opp-hz = /bits/ 64 <270000000>;
4491                                                  4491                                                 required-opps = <&rpmhpd_opp_svs>;
4492                                         };       4492                                         };
4493                                                  4493 
4494                                         opp-5    4494                                         opp-540000000 {
4495                                                  4495                                                 opp-hz = /bits/ 64 <540000000>;
4496                                                  4496                                                 required-opps = <&rpmhpd_opp_svs_l1>;
4497                                         };       4497                                         };
4498                                                  4498 
4499                                         opp-8    4499                                         opp-810000000 {
4500                                                  4500                                                 opp-hz = /bits/ 64 <810000000>;
4501                                                  4501                                                 required-opps = <&rpmhpd_opp_nom>;
4502                                         };       4502                                         };
4503                                 };               4503                                 };
4504                         };                       4504                         };
4505                 };                               4505                 };
4506                                                  4506 
4507                 mdss0_dp2_phy: phy@aec2a00 {     4507                 mdss0_dp2_phy: phy@aec2a00 {
4508                         compatible = "qcom,sc    4508                         compatible = "qcom,sc8280xp-dp-phy";
4509                         reg = <0 0x0aec2a00 0    4509                         reg = <0 0x0aec2a00 0 0x19c>,
4510                               <0 0x0aec2200 0    4510                               <0 0x0aec2200 0 0xec>,
4511                               <0 0x0aec2600 0    4511                               <0 0x0aec2600 0 0xec>,
4512                               <0 0x0aec2000 0    4512                               <0 0x0aec2000 0 0x1c8>;
4513                                                  4513 
4514                         clocks = <&dispcc0 DI    4514                         clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>,
4515                                  <&dispcc0 DI    4515                                  <&dispcc0 DISP_CC_MDSS_AHB_CLK>;
4516                         clock-names = "aux",     4516                         clock-names = "aux", "cfg_ahb";
4517                         power-domains = <&rpm    4517                         power-domains = <&rpmhpd SC8280XP_MX>;
4518                                                  4518 
4519                         #clock-cells = <1>;      4519                         #clock-cells = <1>;
4520                         #phy-cells = <0>;        4520                         #phy-cells = <0>;
4521                                                  4521 
4522                         status = "disabled";     4522                         status = "disabled";
4523                 };                               4523                 };
4524                                                  4524 
4525                 mdss0_dp3_phy: phy@aec5a00 {     4525                 mdss0_dp3_phy: phy@aec5a00 {
4526                         compatible = "qcom,sc    4526                         compatible = "qcom,sc8280xp-dp-phy";
4527                         reg = <0 0x0aec5a00 0    4527                         reg = <0 0x0aec5a00 0 0x19c>,
4528                               <0 0x0aec5200 0    4528                               <0 0x0aec5200 0 0xec>,
4529                               <0 0x0aec5600 0    4529                               <0 0x0aec5600 0 0xec>,
4530                               <0 0x0aec5000 0    4530                               <0 0x0aec5000 0 0x1c8>;
4531                                                  4531 
4532                         clocks = <&dispcc0 DI    4532                         clocks = <&dispcc0 DISP_CC_MDSS_DPTX3_AUX_CLK>,
4533                                  <&dispcc0 DI    4533                                  <&dispcc0 DISP_CC_MDSS_AHB_CLK>;
4534                         clock-names = "aux",     4534                         clock-names = "aux", "cfg_ahb";
4535                         power-domains = <&rpm    4535                         power-domains = <&rpmhpd SC8280XP_MX>;
4536                                                  4536 
4537                         #clock-cells = <1>;      4537                         #clock-cells = <1>;
4538                         #phy-cells = <0>;        4538                         #phy-cells = <0>;
4539                                                  4539 
4540                         status = "disabled";     4540                         status = "disabled";
4541                 };                               4541                 };
4542                                                  4542 
4543                 dispcc0: clock-controller@af0    4543                 dispcc0: clock-controller@af00000 {
4544                         compatible = "qcom,sc    4544                         compatible = "qcom,sc8280xp-dispcc0";
4545                         reg = <0 0x0af00000 0    4545                         reg = <0 0x0af00000 0 0x20000>;
4546                                                  4546 
4547                         clocks = <&gcc GCC_DI    4547                         clocks = <&gcc GCC_DISP_AHB_CLK>,
4548                                  <&rpmhcc RPM    4548                                  <&rpmhcc RPMH_CXO_CLK>,
4549                                  <&sleep_clk>    4549                                  <&sleep_clk>,
4550                                  <&usb_0_qmpp    4550                                  <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4551                                  <&usb_0_qmpp    4551                                  <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
4552                                  <&usb_1_qmpp    4552                                  <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4553                                  <&usb_1_qmpp    4553                                  <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
4554                                  <&mdss0_dp2_    4554                                  <&mdss0_dp2_phy 0>,
4555                                  <&mdss0_dp2_    4555                                  <&mdss0_dp2_phy 1>,
4556                                  <&mdss0_dp3_    4556                                  <&mdss0_dp3_phy 0>,
4557                                  <&mdss0_dp3_    4557                                  <&mdss0_dp3_phy 1>,
4558                                  <0>,            4558                                  <0>,
4559                                  <0>,            4559                                  <0>,
4560                                  <0>,            4560                                  <0>,
4561                                  <0>;            4561                                  <0>;
4562                         power-domains = <&rpm    4562                         power-domains = <&rpmhpd SC8280XP_MMCX>;
4563                                                  4563 
4564                         #clock-cells = <1>;      4564                         #clock-cells = <1>;
4565                         #power-domain-cells =    4565                         #power-domain-cells = <1>;
4566                         #reset-cells = <1>;      4566                         #reset-cells = <1>;
4567                                                  4567 
4568                         status = "disabled";     4568                         status = "disabled";
4569                 };                               4569                 };
4570                                                  4570 
4571                 pdc: interrupt-controller@b22    4571                 pdc: interrupt-controller@b220000 {
4572                         compatible = "qcom,sc    4572                         compatible = "qcom,sc8280xp-pdc", "qcom,pdc";
4573                         reg = <0 0x0b220000 0    4573                         reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
4574                         qcom,pdc-ranges = <0     4574                         qcom,pdc-ranges = <0 480 40>,
4575                                           <40    4575                                           <40 140 14>,
4576                                           <54    4576                                           <54 263 1>,
4577                                           <55    4577                                           <55 306 4>,
4578                                           <59    4578                                           <59 312 3>,
4579                                           <62    4579                                           <62 374 2>,
4580                                           <64    4580                                           <64 434 2>,
4581                                           <66    4581                                           <66 438 3>,
4582                                           <69    4582                                           <69 86 1>,
4583                                           <70    4583                                           <70 520 54>,
4584                                           <12    4584                                           <124 609 28>,
4585                                           <15    4585                                           <159 638 1>,
4586                                           <16    4586                                           <160 720 8>,
4587                                           <16    4587                                           <168 801 1>,
4588                                           <16    4588                                           <169 728 30>,
4589                                           <19    4589                                           <199 416 2>,
4590                                           <20    4590                                           <201 449 1>,
4591                                           <20    4591                                           <202 89 1>,
4592                                           <20    4592                                           <203 451 1>,
4593                                           <20    4593                                           <204 462 1>,
4594                                           <20    4594                                           <205 264 1>,
4595                                           <20    4595                                           <206 579 1>,
4596                                           <20    4596                                           <207 653 1>,
4597                                           <20    4597                                           <208 656 1>,
4598                                           <20    4598                                           <209 659 1>,
4599                                           <21    4599                                           <210 122 1>,
4600                                           <21    4600                                           <211 699 1>,
4601                                           <21    4601                                           <212 705 1>,
4602                                           <21    4602                                           <213 450 1>,
4603                                           <21    4603                                           <214 643 1>,
4604                                           <21    4604                                           <216 646 5>,
4605                                           <22    4605                                           <221 390 5>,
4606                                           <22    4606                                           <226 700 3>,
4607                                           <22    4607                                           <229 240 3>,
4608                                           <23    4608                                           <232 269 1>,
4609                                           <23    4609                                           <233 377 1>,
4610                                           <23    4610                                           <234 372 1>,
4611                                           <23    4611                                           <235 138 1>,
4612                                           <23    4612                                           <236 857 1>,
4613                                           <23    4613                                           <237 860 1>,
4614                                           <23    4614                                           <238 137 1>,
4615                                           <23    4615                                           <239 668 1>,
4616                                           <24    4616                                           <240 366 1>,
4617                                           <24    4617                                           <241 949 1>,
4618                                           <24    4618                                           <242 815 5>,
4619                                           <24    4619                                           <247 769 1>,
4620                                           <24    4620                                           <248 768 1>,
4621                                           <24    4621                                           <249 663 1>,
4622                                           <25    4622                                           <250 799 2>,
4623                                           <25    4623                                           <252 798 1>,
4624                                           <25    4624                                           <253 765 1>,
4625                                           <25    4625                                           <254 763 1>,
4626                                           <25    4626                                           <255 454 1>,
4627                                           <25    4627                                           <258 139 1>,
4628                                           <25    4628                                           <259 786 2>,
4629                                           <26    4629                                           <261 370 2>,
4630                                           <26    4630                                           <263 158 2>;
4631                         #interrupt-cells = <2    4631                         #interrupt-cells = <2>;
4632                         interrupt-parent = <&    4632                         interrupt-parent = <&intc>;
4633                         interrupt-controller;    4633                         interrupt-controller;
4634                 };                               4634                 };
4635                                                  4635 
4636                 tsens2: thermal-sensor@c25100    4636                 tsens2: thermal-sensor@c251000 {
4637                         compatible = "qcom,sc    4637                         compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2";
4638                         reg = <0 0x0c251000 0    4638                         reg = <0 0x0c251000 0 0x1ff>,
4639                               <0 0x0c224000 0    4639                               <0 0x0c224000 0 0x8>;
4640                         #qcom,sensors = <11>;    4640                         #qcom,sensors = <11>;
4641                         interrupts-extended =    4641                         interrupts-extended = <&pdc 122 IRQ_TYPE_LEVEL_HIGH>,
4642                                                  4642                                               <&pdc 124 IRQ_TYPE_LEVEL_HIGH>;
4643                         interrupt-names = "up    4643                         interrupt-names = "uplow", "critical";
4644                         #thermal-sensor-cells    4644                         #thermal-sensor-cells = <1>;
4645                 };                               4645                 };
4646                                                  4646 
4647                 tsens3: thermal-sensor@c25200    4647                 tsens3: thermal-sensor@c252000 {
4648                         compatible = "qcom,sc    4648                         compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2";
4649                         reg = <0 0x0c252000 0    4649                         reg = <0 0x0c252000 0 0x1ff>,
4650                               <0 0x0c225000 0    4650                               <0 0x0c225000 0 0x8>;
4651                         #qcom,sensors = <5>;     4651                         #qcom,sensors = <5>;
4652                         interrupts-extended =    4652                         interrupts-extended = <&pdc 123 IRQ_TYPE_LEVEL_HIGH>,
4653                                                  4653                                               <&pdc 125 IRQ_TYPE_LEVEL_HIGH>;
4654                         interrupt-names = "up    4654                         interrupt-names = "uplow", "critical";
4655                         #thermal-sensor-cells    4655                         #thermal-sensor-cells = <1>;
4656                 };                               4656                 };
4657                                                  4657 
4658                 tsens0: thermal-sensor@c26300    4658                 tsens0: thermal-sensor@c263000 {
4659                         compatible = "qcom,sc    4659                         compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2";
4660                         reg = <0 0x0c263000 0    4660                         reg = <0 0x0c263000 0 0x1ff>, /* TM */
4661                               <0 0x0c222000 0    4661                               <0 0x0c222000 0 0x8>; /* SROT */
4662                         #qcom,sensors = <14>;    4662                         #qcom,sensors = <14>;
4663                         interrupts-extended =    4663                         interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
4664                                                  4664                                               <&pdc 28 IRQ_TYPE_LEVEL_HIGH>;
4665                         interrupt-names = "up    4665                         interrupt-names = "uplow", "critical";
4666                         #thermal-sensor-cells    4666                         #thermal-sensor-cells = <1>;
4667                 };                               4667                 };
4668                                                  4668 
4669                 restart@c264000 {                4669                 restart@c264000 {
4670                         compatible = "qcom,ps    4670                         compatible = "qcom,pshold";
4671                         reg = <0 0x0c264000 0    4671                         reg = <0 0x0c264000 0 0x4>;
4672                         /* TZ seems to block     4672                         /* TZ seems to block access */
4673                         status = "reserved";     4673                         status = "reserved";
4674                 };                               4674                 };
4675                                                  4675 
4676                 tsens1: thermal-sensor@c26500    4676                 tsens1: thermal-sensor@c265000 {
4677                         compatible = "qcom,sc    4677                         compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2";
4678                         reg = <0 0x0c265000 0    4678                         reg = <0 0x0c265000 0 0x1ff>, /* TM */
4679                               <0 0x0c223000 0    4679                               <0 0x0c223000 0 0x8>; /* SROT */
4680                         #qcom,sensors = <16>;    4680                         #qcom,sensors = <16>;
4681                         interrupts-extended =    4681                         interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
4682                                                  4682                                               <&pdc 29 IRQ_TYPE_LEVEL_HIGH>;
4683                         interrupt-names = "up    4683                         interrupt-names = "uplow", "critical";
4684                         #thermal-sensor-cells    4684                         #thermal-sensor-cells = <1>;
4685                 };                               4685                 };
4686                                                  4686 
4687                 aoss_qmp: power-management@c3    4687                 aoss_qmp: power-management@c300000 {
4688                         compatible = "qcom,sc    4688                         compatible = "qcom,sc8280xp-aoss-qmp", "qcom,aoss-qmp";
4689                         reg = <0 0x0c300000 0    4689                         reg = <0 0x0c300000 0 0x400>;
4690                         interrupts-extended =    4690                         interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>;
4691                         mboxes = <&ipcc IPCC_    4691                         mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
4692                                                  4692 
4693                         #clock-cells = <0>;      4693                         #clock-cells = <0>;
4694                 };                               4694                 };
4695                                                  4695 
4696                 sram@c3f0000 {                   4696                 sram@c3f0000 {
4697                         compatible = "qcom,rp    4697                         compatible = "qcom,rpmh-stats";
4698                         reg = <0 0x0c3f0000 0    4698                         reg = <0 0x0c3f0000 0 0x400>;
4699                         qcom,qmp = <&aoss_qmp    4699                         qcom,qmp = <&aoss_qmp>;
4700                 };                               4700                 };
4701                                                  4701 
4702                 spmi_bus: spmi@c440000 {         4702                 spmi_bus: spmi@c440000 {
4703                         compatible = "qcom,sp    4703                         compatible = "qcom,spmi-pmic-arb";
4704                         reg = <0 0x0c440000 0    4704                         reg = <0 0x0c440000 0 0x1100>,
4705                               <0 0x0c600000 0    4705                               <0 0x0c600000 0 0x2000000>,
4706                               <0 0x0e600000 0    4706                               <0 0x0e600000 0 0x100000>,
4707                               <0 0x0e700000 0    4707                               <0 0x0e700000 0 0xa0000>,
4708                               <0 0x0c40a000 0    4708                               <0 0x0c40a000 0 0x26000>;
4709                         reg-names = "core", "    4709                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
4710                         interrupt-names = "pe    4710                         interrupt-names = "periph_irq";
4711                         interrupts-extended =    4711                         interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
4712                         qcom,ee = <0>;           4712                         qcom,ee = <0>;
4713                         qcom,channel = <0>;      4713                         qcom,channel = <0>;
4714                         #address-cells = <2>;    4714                         #address-cells = <2>;
4715                         #size-cells = <0>;       4715                         #size-cells = <0>;
4716                         interrupt-controller;    4716                         interrupt-controller;
4717                         #interrupt-cells = <4    4717                         #interrupt-cells = <4>;
4718                 };                               4718                 };
4719                                                  4719 
4720                 tlmm: pinctrl@f100000 {          4720                 tlmm: pinctrl@f100000 {
4721                         compatible = "qcom,sc    4721                         compatible = "qcom,sc8280xp-tlmm";
4722                         reg = <0 0x0f100000 0    4722                         reg = <0 0x0f100000 0 0x300000>;
4723                         interrupts = <GIC_SPI    4723                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
4724                         gpio-controller;         4724                         gpio-controller;
4725                         #gpio-cells = <2>;       4725                         #gpio-cells = <2>;
4726                         interrupt-controller;    4726                         interrupt-controller;
4727                         #interrupt-cells = <2    4727                         #interrupt-cells = <2>;
4728                         gpio-ranges = <&tlmm     4728                         gpio-ranges = <&tlmm 0 0 230>;
4729                         wakeup-parent = <&pdc    4729                         wakeup-parent = <&pdc>;
4730                                                  4730 
4731                         cci0_default: cci0-de    4731                         cci0_default: cci0-default-state {
4732                                 cci0_i2c0_def    4732                                 cci0_i2c0_default: cci0-i2c0-default-pins {
4733                                         /* cc    4733                                         /* cci_i2c_sda0, cci_i2c_scl0 */
4734                                         pins     4734                                         pins = "gpio113", "gpio114";
4735                                         funct    4735                                         function = "cci_i2c";
4736                                         drive    4736                                         drive-strength = <2>;
4737                                         bias-    4737                                         bias-pull-up;
4738                                 };               4738                                 };
4739                                                  4739 
4740                                 cci0_i2c1_def    4740                                 cci0_i2c1_default: cci0-i2c1-default-pins {
4741                                         /* cc    4741                                         /* cci_i2c_sda1, cci_i2c_scl1 */
4742                                         pins     4742                                         pins = "gpio115", "gpio116";
4743                                         funct    4743                                         function = "cci_i2c";
4744                                         drive    4744                                         drive-strength = <2>;
4745                                         bias-    4745                                         bias-pull-up;
4746                                 };               4746                                 };
4747                         };                       4747                         };
4748                                                  4748 
4749                         cci0_sleep: cci0-slee    4749                         cci0_sleep: cci0-sleep-state {
4750                                 cci0_i2c0_sle    4750                                 cci0_i2c0_sleep: cci0-i2c0-sleep-pins {
4751                                         /* cc    4751                                         /* cci_i2c_sda0, cci_i2c_scl0 */
4752                                         pins     4752                                         pins = "gpio113", "gpio114";
4753                                         funct    4753                                         function = "cci_i2c";
4754                                         drive    4754                                         drive-strength = <2>;
4755                                         bias-    4755                                         bias-pull-down;
4756                                 };               4756                                 };
4757                                                  4757 
4758                                 cci0_i2c1_sle    4758                                 cci0_i2c1_sleep: cci0-i2c1-sleep-pins {
4759                                         /* cc    4759                                         /* cci_i2c_sda1, cci_i2c_scl1 */
4760                                         pins     4760                                         pins = "gpio115", "gpio116";
4761                                         funct    4761                                         function = "cci_i2c";
4762                                         drive    4762                                         drive-strength = <2>;
4763                                         bias-    4763                                         bias-pull-down;
4764                                 };               4764                                 };
4765                         };                       4765                         };
4766                                                  4766 
4767                         cci1_default: cci1-de    4767                         cci1_default: cci1-default-state {
4768                                 cci1_i2c0_def    4768                                 cci1_i2c0_default: cci1-i2c0-default-pins {
4769                                         /* cc    4769                                         /* cci_i2c_sda2, cci_i2c_scl2 */
4770                                         pins     4770                                         pins = "gpio10","gpio11";
4771                                         funct    4771                                         function = "cci_i2c";
4772                                         drive    4772                                         drive-strength = <2>;
4773                                         bias-    4773                                         bias-pull-up;
4774                                 };               4774                                 };
4775                                                  4775 
4776                                 cci1_i2c1_def    4776                                 cci1_i2c1_default: cci1-i2c1-default-pins {
4777                                         /* cc    4777                                         /* cci_i2c_sda3, cci_i2c_scl3 */
4778                                         pins     4778                                         pins = "gpio123","gpio124";
4779                                         funct    4779                                         function = "cci_i2c";
4780                                         drive    4780                                         drive-strength = <2>;
4781                                         bias-    4781                                         bias-pull-up;
4782                                 };               4782                                 };
4783                         };                       4783                         };
4784                                                  4784 
4785                         cci1_sleep: cci1-slee    4785                         cci1_sleep: cci1-sleep-state {
4786                                 cci1_i2c0_sle    4786                                 cci1_i2c0_sleep: cci1-i2c0-sleep-pins {
4787                                         /* cc    4787                                         /* cci_i2c_sda2, cci_i2c_scl2 */
4788                                         pins     4788                                         pins = "gpio10","gpio11";
4789                                         funct    4789                                         function = "cci_i2c";
4790                                         drive    4790                                         drive-strength = <2>;
4791                                         bias-    4791                                         bias-pull-down;
4792                                 };               4792                                 };
4793                                                  4793 
4794                                 cci1_i2c1_sle    4794                                 cci1_i2c1_sleep: cci1-i2c1-sleep-pins {
4795                                         /* cc    4795                                         /* cci_i2c_sda3, cci_i2c_scl3 */
4796                                         pins     4796                                         pins = "gpio123","gpio124";
4797                                         funct    4797                                         function = "cci_i2c";
4798                                         drive    4798                                         drive-strength = <2>;
4799                                         bias-    4799                                         bias-pull-down;
4800                                 };               4800                                 };
4801                         };                       4801                         };
4802                                                  4802 
4803                         cci2_default: cci2-de    4803                         cci2_default: cci2-default-state {
4804                                 cci2_i2c0_def    4804                                 cci2_i2c0_default: cci2-i2c0-default-pins {
4805                                         /* cc    4805                                         /* cci_i2c_sda4, cci_i2c_scl4 */
4806                                         pins     4806                                         pins = "gpio117","gpio118";
4807                                         funct    4807                                         function = "cci_i2c";
4808                                         drive    4808                                         drive-strength = <2>;
4809                                         bias-    4809                                         bias-pull-up;
4810                                 };               4810                                 };
4811                                                  4811 
4812                                 cci2_i2c1_def    4812                                 cci2_i2c1_default: cci2-i2c1-default-pins {
4813                                         /* cc    4813                                         /* cci_i2c_sda5, cci_i2c_scl5 */
4814                                         pins     4814                                         pins = "gpio12","gpio13";
4815                                         funct    4815                                         function = "cci_i2c";
4816                                         drive    4816                                         drive-strength = <2>;
4817                                         bias-    4817                                         bias-pull-up;
4818                                 };               4818                                 };
4819                         };                       4819                         };
4820                                                  4820 
4821                         cci2_sleep: cci2-slee    4821                         cci2_sleep: cci2-sleep-state {
4822                                 cci2_i2c0_sle    4822                                 cci2_i2c0_sleep: cci2-i2c0-sleep-pins {
4823                                         /* cc    4823                                         /* cci_i2c_sda4, cci_i2c_scl4 */
4824                                         pins     4824                                         pins = "gpio117","gpio118";
4825                                         funct    4825                                         function = "cci_i2c";
4826                                         drive    4826                                         drive-strength = <2>;
4827                                         bias-    4827                                         bias-pull-down;
4828                                 };               4828                                 };
4829                                                  4829 
4830                                 cci2_i2c1_sle    4830                                 cci2_i2c1_sleep: cci2-i2c1-sleep-pins {
4831                                         /* cc    4831                                         /* cci_i2c_sda5, cci_i2c_scl5 */
4832                                         pins     4832                                         pins = "gpio12","gpio13";
4833                                         funct    4833                                         function = "cci_i2c";
4834                                         drive    4834                                         drive-strength = <2>;
4835                                         bias-    4835                                         bias-pull-down;
4836                                 };               4836                                 };
4837                         };                       4837                         };
4838                                                  4838 
4839                         cci3_default: cci3-de    4839                         cci3_default: cci3-default-state {
4840                                 cci3_i2c0_def    4840                                 cci3_i2c0_default: cci3-i2c0-default-pins {
4841                                         /* cc    4841                                         /* cci_i2c_sda6, cci_i2c_scl6 */
4842                                         pins     4842                                         pins = "gpio145","gpio146";
4843                                         funct    4843                                         function = "cci_i2c";
4844                                         drive    4844                                         drive-strength = <2>;
4845                                         bias-    4845                                         bias-pull-up;
4846                                 };               4846                                 };
4847                                                  4847 
4848                                 cci3_i2c1_def    4848                                 cci3_i2c1_default: cci3-i2c1-default-pins {
4849                                         /* cc    4849                                         /* cci_i2c_sda7, cci_i2c_scl7 */
4850                                         pins     4850                                         pins = "gpio164","gpio165";
4851                                         funct    4851                                         function = "cci_i2c";
4852                                         drive    4852                                         drive-strength = <2>;
4853                                         bias-    4853                                         bias-pull-up;
4854                                 };               4854                                 };
4855                         };                       4855                         };
4856                                                  4856 
4857                         cci3_sleep: cci3-slee    4857                         cci3_sleep: cci3-sleep-state {
4858                                 cci3_i2c0_sle    4858                                 cci3_i2c0_sleep: cci3-i2c0-sleep-pins {
4859                                         /* cc    4859                                         /* cci_i2c_sda6, cci_i2c_scl6 */
4860                                         pins     4860                                         pins = "gpio145","gpio146";
4861                                         funct    4861                                         function = "cci_i2c";
4862                                         drive    4862                                         drive-strength = <2>;
4863                                         bias-    4863                                         bias-pull-down;
4864                                 };               4864                                 };
4865                                                  4865 
4866                                 cci3_i2c1_sle    4866                                 cci3_i2c1_sleep: cci3-i2c1-sleep-pins {
4867                                         /* cc    4867                                         /* cci_i2c_sda7, cci_i2c_scl7 */
4868                                         pins     4868                                         pins = "gpio164","gpio165";
4869                                         funct    4869                                         function = "cci_i2c";
4870                                         drive    4870                                         drive-strength = <2>;
4871                                         bias-    4871                                         bias-pull-down;
4872                                 };               4872                                 };
4873                         };                       4873                         };
4874                 };                               4874                 };
4875                                                  4875 
4876                 apps_smmu: iommu@15000000 {      4876                 apps_smmu: iommu@15000000 {
4877                         compatible = "qcom,sc    4877                         compatible = "qcom,sc8280xp-smmu-500", "arm,mmu-500";
4878                         reg = <0 0x15000000 0    4878                         reg = <0 0x15000000 0 0x100000>;
4879                         #iommu-cells = <2>;      4879                         #iommu-cells = <2>;
4880                         #global-interrupts =     4880                         #global-interrupts = <2>;
4881                         interrupts = <GIC_SPI    4881                         interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
4882                                      <GIC_SPI    4882                                      <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
4883                                      <GIC_SPI    4883                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
4884                                      <GIC_SPI    4884                                      <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
4885                                      <GIC_SPI    4885                                      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
4886                                      <GIC_SPI    4886                                      <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
4887                                      <GIC_SPI    4887                                      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
4888                                      <GIC_SPI    4888                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
4889                                      <GIC_SPI    4889                                      <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
4890                                      <GIC_SPI    4890                                      <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
4891                                      <GIC_SPI    4891                                      <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
4892                                      <GIC_SPI    4892                                      <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
4893                                      <GIC_SPI    4893                                      <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
4894                                      <GIC_SPI    4894                                      <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
4895                                      <GIC_SPI    4895                                      <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
4896                                      <GIC_SPI    4896                                      <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
4897                                      <GIC_SPI    4897                                      <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
4898                                      <GIC_SPI    4898                                      <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
4899                                      <GIC_SPI    4899                                      <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
4900                                      <GIC_SPI    4900                                      <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
4901                                      <GIC_SPI    4901                                      <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
4902                                      <GIC_SPI    4902                                      <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
4903                                      <GIC_SPI    4903                                      <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
4904                                      <GIC_SPI    4904                                      <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
4905                                      <GIC_SPI    4905                                      <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
4906                                      <GIC_SPI    4906                                      <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
4907                                      <GIC_SPI    4907                                      <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
4908                                      <GIC_SPI    4908                                      <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
4909                                      <GIC_SPI    4909                                      <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
4910                                      <GIC_SPI    4910                                      <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
4911                                      <GIC_SPI    4911                                      <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
4912                                      <GIC_SPI    4912                                      <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
4913                                      <GIC_SPI    4913                                      <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
4914                                      <GIC_SPI    4914                                      <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
4915                                      <GIC_SPI    4915                                      <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
4916                                      <GIC_SPI    4916                                      <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
4917                                      <GIC_SPI    4917                                      <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
4918                                      <GIC_SPI    4918                                      <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
4919                                      <GIC_SPI    4919                                      <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
4920                                      <GIC_SPI    4920                                      <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
4921                                      <GIC_SPI    4921                                      <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
4922                                      <GIC_SPI    4922                                      <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
4923                                      <GIC_SPI    4923                                      <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
4924                                      <GIC_SPI    4924                                      <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
4925                                      <GIC_SPI    4925                                      <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
4926                                      <GIC_SPI    4926                                      <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
4927                                      <GIC_SPI    4927                                      <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
4928                                      <GIC_SPI    4928                                      <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
4929                                      <GIC_SPI    4929                                      <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
4930                                      <GIC_SPI    4930                                      <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
4931                                      <GIC_SPI    4931                                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
4932                                      <GIC_SPI    4932                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
4933                                      <GIC_SPI    4933                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
4934                                      <GIC_SPI    4934                                      <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
4935                                      <GIC_SPI    4935                                      <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
4936                                      <GIC_SPI    4936                                      <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
4937                                      <GIC_SPI    4937                                      <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
4938                                      <GIC_SPI    4938                                      <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
4939                                      <GIC_SPI    4939                                      <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
4940                                      <GIC_SPI    4940                                      <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
4941                                      <GIC_SPI    4941                                      <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
4942                                      <GIC_SPI    4942                                      <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
4943                                      <GIC_SPI    4943                                      <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
4944                                      <GIC_SPI    4944                                      <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
4945                                      <GIC_SPI    4945                                      <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
4946                                      <GIC_SPI    4946                                      <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
4947                                      <GIC_SPI    4947                                      <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
4948                                      <GIC_SPI    4948                                      <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
4949                                      <GIC_SPI    4949                                      <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
4950                                      <GIC_SPI    4950                                      <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
4951                                      <GIC_SPI    4951                                      <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
4952                                      <GIC_SPI    4952                                      <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
4953                                      <GIC_SPI    4953                                      <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
4954                                      <GIC_SPI    4954                                      <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
4955                                      <GIC_SPI    4955                                      <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
4956                                      <GIC_SPI    4956                                      <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
4957                                      <GIC_SPI    4957                                      <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
4958                                      <GIC_SPI    4958                                      <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
4959                                      <GIC_SPI    4959                                      <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
4960                                      <GIC_SPI    4960                                      <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
4961                                      <GIC_SPI    4961                                      <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>,
4962                                      <GIC_SPI    4962                                      <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
4963                                      <GIC_SPI    4963                                      <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
4964                                      <GIC_SPI    4964                                      <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
4965                                      <GIC_SPI    4965                                      <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
4966                                      <GIC_SPI    4966                                      <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
4967                                      <GIC_SPI    4967                                      <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
4968                                      <GIC_SPI    4968                                      <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
4969                                      <GIC_SPI    4969                                      <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
4970                                      <GIC_SPI    4970                                      <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
4971                                      <GIC_SPI    4971                                      <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
4972                                      <GIC_SPI    4972                                      <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
4973                                      <GIC_SPI    4973                                      <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
4974                                      <GIC_SPI    4974                                      <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
4975                                      <GIC_SPI    4975                                      <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
4976                                      <GIC_SPI    4976                                      <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
4977                                      <GIC_SPI    4977                                      <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
4978                                      <GIC_SPI    4978                                      <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
4979                                      <GIC_SPI    4979                                      <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>,
4980                                      <GIC_SPI    4980                                      <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>,
4981                                      <GIC_SPI    4981                                      <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>,
4982                                      <GIC_SPI    4982                                      <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
4983                                      <GIC_SPI    4983                                      <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
4984                                      <GIC_SPI    4984                                      <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
4985                                      <GIC_SPI    4985                                      <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>,
4986                                      <GIC_SPI    4986                                      <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>,
4987                                      <GIC_SPI    4987                                      <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>,
4988                                      <GIC_SPI    4988                                      <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>,
4989                                      <GIC_SPI    4989                                      <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>,
4990                                      <GIC_SPI    4990                                      <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>,
4991                                      <GIC_SPI    4991                                      <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>,
4992                                      <GIC_SPI    4992                                      <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>,
4993                                      <GIC_SPI    4993                                      <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>,
4994                                      <GIC_SPI    4994                                      <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>,
4995                                      <GIC_SPI    4995                                      <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>,
4996                                      <GIC_SPI    4996                                      <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>,
4997                                      <GIC_SPI    4997                                      <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>,
4998                                      <GIC_SPI    4998                                      <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>,
4999                                      <GIC_SPI    4999                                      <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>,
5000                                      <GIC_SPI    5000                                      <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>,
5001                                      <GIC_SPI    5001                                      <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>,
5002                                      <GIC_SPI    5002                                      <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>,
5003                                      <GIC_SPI    5003                                      <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>,
5004                                      <GIC_SPI    5004                                      <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>,
5005                                      <GIC_SPI    5005                                      <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>,
5006                                      <GIC_SPI    5006                                      <GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>,
5007                                      <GIC_SPI    5007                                      <GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>,
5008                                      <GIC_SPI    5008                                      <GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>,
5009                                      <GIC_SPI    5009                                      <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>,
5010                                      <GIC_SPI    5010                                      <GIC_SPI 890 IRQ_TYPE_LEVEL_HIGH>;
5011                 };                               5011                 };
5012                                                  5012 
5013                 intc: interrupt-controller@17    5013                 intc: interrupt-controller@17a00000 {
5014                         compatible = "arm,gic    5014                         compatible = "arm,gic-v3";
5015                         interrupt-controller;    5015                         interrupt-controller;
5016                         #interrupt-cells = <3    5016                         #interrupt-cells = <3>;
5017                         reg = <0x0 0x17a00000    5017                         reg = <0x0 0x17a00000 0x0 0x10000>,     /* GICD */
5018                               <0x0 0x17a60000    5018                               <0x0 0x17a60000 0x0 0x100000>;    /* GICR * 8 */
5019                         interrupts = <GIC_PPI    5019                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
5020                         #redistributor-region    5020                         #redistributor-regions = <1>;
5021                         redistributor-stride     5021                         redistributor-stride = <0 0x20000>;
5022                                                  5022 
5023                         #address-cells = <2>;    5023                         #address-cells = <2>;
5024                         #size-cells = <2>;       5024                         #size-cells = <2>;
5025                         ranges;                  5025                         ranges;
5026                                                  5026 
5027                         its: msi-controller@1    5027                         its: msi-controller@17a40000 {
5028                                 compatible =     5028                                 compatible = "arm,gic-v3-its";
5029                                 reg = <0 0x17    5029                                 reg = <0 0x17a40000 0 0x20000>;
5030                                 msi-controlle    5030                                 msi-controller;
5031                                 #msi-cells =     5031                                 #msi-cells = <1>;
5032                         };                       5032                         };
5033                 };                               5033                 };
5034                                                  5034 
5035                 watchdog@17c10000 {              5035                 watchdog@17c10000 {
5036                         compatible = "qcom,ap    5036                         compatible = "qcom,apss-wdt-sc8280xp", "qcom,kpss-wdt";
5037                         reg = <0 0x17c10000 0    5037                         reg = <0 0x17c10000 0 0x1000>;
5038                         clocks = <&sleep_clk>    5038                         clocks = <&sleep_clk>;
5039                         interrupts = <GIC_SPI    5039                         interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
5040                 };                               5040                 };
5041                                                  5041 
5042                 timer@17c20000 {                 5042                 timer@17c20000 {
5043                         compatible = "arm,arm    5043                         compatible = "arm,armv7-timer-mem";
5044                         reg = <0x0 0x17c20000    5044                         reg = <0x0 0x17c20000 0x0 0x1000>;
5045                         #address-cells = <1>;    5045                         #address-cells = <1>;
5046                         #size-cells = <1>;       5046                         #size-cells = <1>;
5047                         ranges = <0x0 0x0 0x0    5047                         ranges = <0x0 0x0 0x0 0x20000000>;
5048                                                  5048 
5049                         frame@17c21000 {         5049                         frame@17c21000 {
5050                                 frame-number     5050                                 frame-number = <0>;
5051                                 interrupts =     5051                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
5052                                                  5052                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
5053                                 reg = <0x17c2    5053                                 reg = <0x17c21000 0x1000>,
5054                                       <0x17c2    5054                                       <0x17c22000 0x1000>;
5055                         };                       5055                         };
5056                                                  5056 
5057                         frame@17c23000 {         5057                         frame@17c23000 {
5058                                 frame-number     5058                                 frame-number = <1>;
5059                                 interrupts =     5059                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
5060                                 reg = <0x17c2    5060                                 reg = <0x17c23000 0x1000>;
5061                                 status = "dis    5061                                 status = "disabled";
5062                         };                       5062                         };
5063                                                  5063 
5064                         frame@17c25000 {         5064                         frame@17c25000 {
5065                                 frame-number     5065                                 frame-number = <2>;
5066                                 interrupts =     5066                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
5067                                 reg = <0x17c2    5067                                 reg = <0x17c25000 0x1000>;
5068                                 status = "dis    5068                                 status = "disabled";
5069                         };                       5069                         };
5070                                                  5070 
5071                         frame@17c27000 {         5071                         frame@17c27000 {
5072                                 frame-number     5072                                 frame-number = <3>;
5073                                 interrupts =     5073                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
5074                                 reg = <0x17c2    5074                                 reg = <0x17c26000 0x1000>;
5075                                 status = "dis    5075                                 status = "disabled";
5076                         };                       5076                         };
5077                                                  5077 
5078                         frame@17c29000 {         5078                         frame@17c29000 {
5079                                 frame-number     5079                                 frame-number = <4>;
5080                                 interrupts =     5080                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
5081                                 reg = <0x17c2    5081                                 reg = <0x17c29000 0x1000>;
5082                                 status = "dis    5082                                 status = "disabled";
5083                         };                       5083                         };
5084                                                  5084 
5085                         frame@17c2b000 {         5085                         frame@17c2b000 {
5086                                 frame-number     5086                                 frame-number = <5>;
5087                                 interrupts =     5087                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
5088                                 reg = <0x17c2    5088                                 reg = <0x17c2b000 0x1000>;
5089                                 status = "dis    5089                                 status = "disabled";
5090                         };                       5090                         };
5091                                                  5091 
5092                         frame@17c2d000 {         5092                         frame@17c2d000 {
5093                                 frame-number     5093                                 frame-number = <6>;
5094                                 interrupts =     5094                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
5095                                 reg = <0x17c2    5095                                 reg = <0x17c2d000 0x1000>;
5096                                 status = "dis    5096                                 status = "disabled";
5097                         };                       5097                         };
5098                 };                               5098                 };
5099                                                  5099 
5100                 apps_rsc: rsc@18200000 {         5100                 apps_rsc: rsc@18200000 {
5101                         compatible = "qcom,rp    5101                         compatible = "qcom,rpmh-rsc";
5102                         reg = <0x0 0x18200000    5102                         reg = <0x0 0x18200000 0x0 0x10000>,
5103                                 <0x0 0x182100    5103                                 <0x0 0x18210000 0x0 0x10000>,
5104                                 <0x0 0x182200    5104                                 <0x0 0x18220000 0x0 0x10000>;
5105                         reg-names = "drv-0",     5105                         reg-names = "drv-0", "drv-1", "drv-2";
5106                         interrupts = <GIC_SPI    5106                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
5107                                      <GIC_SPI    5107                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
5108                                      <GIC_SPI    5108                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
5109                         qcom,tcs-offset = <0x    5109                         qcom,tcs-offset = <0xd00>;
5110                         qcom,drv-id = <2>;       5110                         qcom,drv-id = <2>;
5111                         qcom,tcs-config = <AC    5111                         qcom,tcs-config = <ACTIVE_TCS  2>, <SLEEP_TCS   3>,
5112                                           <WA    5112                                           <WAKE_TCS    3>, <CONTROL_TCS 1>;
5113                         label = "apps_rsc";      5113                         label = "apps_rsc";
5114                         power-domains = <&CLU    5114                         power-domains = <&CLUSTER_PD>;
5115                                                  5115 
5116                         apps_bcm_voter: bcm-v    5116                         apps_bcm_voter: bcm-voter {
5117                                 compatible =     5117                                 compatible = "qcom,bcm-voter";
5118                         };                       5118                         };
5119                                                  5119 
5120                         rpmhcc: clock-control    5120                         rpmhcc: clock-controller {
5121                                 compatible =     5121                                 compatible = "qcom,sc8280xp-rpmh-clk";
5122                                 #clock-cells     5122                                 #clock-cells = <1>;
5123                                 clock-names =    5123                                 clock-names = "xo";
5124                                 clocks = <&xo    5124                                 clocks = <&xo_board_clk>;
5125                         };                       5125                         };
5126                                                  5126 
5127                         rpmhpd: power-control    5127                         rpmhpd: power-controller {
5128                                 compatible =     5128                                 compatible = "qcom,sc8280xp-rpmhpd";
5129                                 #power-domain    5129                                 #power-domain-cells = <1>;
5130                                 operating-poi    5130                                 operating-points-v2 = <&rpmhpd_opp_table>;
5131                                                  5131 
5132                                 rpmhpd_opp_ta    5132                                 rpmhpd_opp_table: opp-table {
5133                                         compa    5133                                         compatible = "operating-points-v2";
5134                                                  5134 
5135                                         rpmhp    5135                                         rpmhpd_opp_ret: opp1 {
5136                                                  5136                                                 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
5137                                         };       5137                                         };
5138                                                  5138 
5139                                         rpmhp    5139                                         rpmhpd_opp_min_svs: opp2 {
5140                                                  5140                                                 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
5141                                         };       5141                                         };
5142                                                  5142 
5143                                         rpmhp    5143                                         rpmhpd_opp_low_svs: opp3 {
5144                                                  5144                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
5145                                         };       5145                                         };
5146                                                  5146 
5147                                         rpmhp    5147                                         rpmhpd_opp_svs: opp4 {
5148                                                  5148                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
5149                                         };       5149                                         };
5150                                                  5150 
5151                                         rpmhp    5151                                         rpmhpd_opp_svs_l1: opp5 {
5152                                                  5152                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
5153                                         };       5153                                         };
5154                                                  5154 
5155                                         rpmhp    5155                                         rpmhpd_opp_nom: opp6 {
5156                                                  5156                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
5157                                         };       5157                                         };
5158                                                  5158 
5159                                         rpmhp    5159                                         rpmhpd_opp_nom_l1: opp7 {
5160                                                  5160                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
5161                                         };       5161                                         };
5162                                                  5162 
5163                                         rpmhp    5163                                         rpmhpd_opp_nom_l2: opp8 {
5164                                                  5164                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
5165                                         };       5165                                         };
5166                                                  5166 
5167                                         rpmhp    5167                                         rpmhpd_opp_turbo: opp9 {
5168                                                  5168                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
5169                                         };       5169                                         };
5170                                                  5170 
5171                                         rpmhp    5171                                         rpmhpd_opp_turbo_l1: opp10 {
5172                                                  5172                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
5173                                         };       5173                                         };
5174                                 };               5174                                 };
5175                         };                       5175                         };
5176                 };                               5176                 };
5177                                                  5177 
5178                 epss_l3: interconnect@1859000    5178                 epss_l3: interconnect@18590000 {
5179                         compatible = "qcom,sc    5179                         compatible = "qcom,sc8280xp-epss-l3", "qcom,epss-l3";
5180                         reg = <0 0x18590000 0    5180                         reg = <0 0x18590000 0 0x1000>;
5181                                                  5181 
5182                         clocks = <&rpmhcc RPM    5182                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
5183                         clock-names = "xo", "    5183                         clock-names = "xo", "alternate";
5184                                                  5184 
5185                         #interconnect-cells =    5185                         #interconnect-cells = <1>;
5186                 };                               5186                 };
5187                                                  5187 
5188                 cpufreq_hw: cpufreq@18591000     5188                 cpufreq_hw: cpufreq@18591000 {
5189                         compatible = "qcom,sc    5189                         compatible = "qcom,sc8280xp-cpufreq-epss", "qcom,cpufreq-epss";
5190                         reg = <0 0x18591000 0    5190                         reg = <0 0x18591000 0 0x1000>,
5191                               <0 0x18592000 0    5191                               <0 0x18592000 0 0x1000>;
5192                         reg-names = "freq-dom    5192                         reg-names = "freq-domain0", "freq-domain1";
5193                                                  5193 
5194                         interrupts = <GIC_SPI    5194                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
5195                                      <GIC_SPI    5195                                      <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
5196                         interrupt-names = "dc    5196                         interrupt-names = "dcvsh-irq-0",
5197                                           "dc    5197                                           "dcvsh-irq-1";
5198                                                  5198 
5199                         clocks = <&rpmhcc RPM    5199                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
5200                         clock-names = "xo", "    5200                         clock-names = "xo", "alternate";
5201                                                  5201 
5202                         #freq-domain-cells =     5202                         #freq-domain-cells = <1>;
5203                         #clock-cells = <1>;      5203                         #clock-cells = <1>;
5204                 };                               5204                 };
5205                                                  5205 
5206                 remoteproc_nsp0: remoteproc@1    5206                 remoteproc_nsp0: remoteproc@1b300000 {
5207                         compatible = "qcom,sc    5207                         compatible = "qcom,sc8280xp-nsp0-pas";
5208                         reg = <0 0x1b300000 0    5208                         reg = <0 0x1b300000 0 0x100>;
5209                                                  5209 
5210                         interrupts-extended =    5210                         interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
5211                                                  5211                                               <&smp2p_nsp0_in 0 IRQ_TYPE_EDGE_RISING>,
5212                                                  5212                                               <&smp2p_nsp0_in 1 IRQ_TYPE_EDGE_RISING>,
5213                                                  5213                                               <&smp2p_nsp0_in 2 IRQ_TYPE_EDGE_RISING>,
5214                                                  5214                                               <&smp2p_nsp0_in 3 IRQ_TYPE_EDGE_RISING>;
5215                         interrupt-names = "wd    5215                         interrupt-names = "wdog", "fatal", "ready",
5216                                           "ha    5216                                           "handover", "stop-ack";
5217                                                  5217 
5218                         clocks = <&rpmhcc RPM    5218                         clocks = <&rpmhcc RPMH_CXO_CLK>;
5219                         clock-names = "xo";      5219                         clock-names = "xo";
5220                                                  5220 
5221                         power-domains = <&rpm    5221                         power-domains = <&rpmhpd SC8280XP_NSP>;
5222                         power-domain-names =     5222                         power-domain-names = "nsp";
5223                                                  5223 
5224                         memory-region = <&pil    5224                         memory-region = <&pil_nsp0_mem>;
5225                                                  5225 
5226                         qcom,smem-states = <&    5226                         qcom,smem-states = <&smp2p_nsp0_out 0>;
5227                         qcom,smem-state-names    5227                         qcom,smem-state-names = "stop";
5228                                                  5228 
5229                         interconnects = <&nsp    5229                         interconnects = <&nspa_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>;
5230                                                  5230 
5231                         status = "disabled";     5231                         status = "disabled";
5232                                                  5232 
5233                         glink-edge {             5233                         glink-edge {
5234                                 interrupts-ex    5234                                 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
5235                                                  5235                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
5236                                                  5236                                                              IRQ_TYPE_EDGE_RISING>;
5237                                 mboxes = <&ip    5237                                 mboxes = <&ipcc IPCC_CLIENT_CDSP
5238                                                  5238                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
5239                                                  5239 
5240                                 label = "nsp0    5240                                 label = "nsp0";
5241                                 qcom,remote-p    5241                                 qcom,remote-pid = <5>;
5242                                                  5242 
5243                                 fastrpc {        5243                                 fastrpc {
5244                                         compa    5244                                         compatible = "qcom,fastrpc";
5245                                         qcom,    5245                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
5246                                         label    5246                                         label = "cdsp";
5247                                         #addr    5247                                         #address-cells = <1>;
5248                                         #size    5248                                         #size-cells = <0>;
5249                                                  5249 
5250                                         compu    5250                                         compute-cb@1 {
5251                                                  5251                                                 compatible = "qcom,fastrpc-compute-cb";
5252                                                  5252                                                 reg = <1>;
5253                                                  5253                                                 iommus = <&apps_smmu 0x3181 0x0420>;
5254                                         };       5254                                         };
5255                                                  5255 
5256                                         compu    5256                                         compute-cb@2 {
5257                                                  5257                                                 compatible = "qcom,fastrpc-compute-cb";
5258                                                  5258                                                 reg = <2>;
5259                                                  5259                                                 iommus = <&apps_smmu 0x3182 0x0420>;
5260                                         };       5260                                         };
5261                                                  5261 
5262                                         compu    5262                                         compute-cb@3 {
5263                                                  5263                                                 compatible = "qcom,fastrpc-compute-cb";
5264                                                  5264                                                 reg = <3>;
5265                                                  5265                                                 iommus = <&apps_smmu 0x3183 0x0420>;
5266                                         };       5266                                         };
5267                                                  5267 
5268                                         compu    5268                                         compute-cb@4 {
5269                                                  5269                                                 compatible = "qcom,fastrpc-compute-cb";
5270                                                  5270                                                 reg = <4>;
5271                                                  5271                                                 iommus = <&apps_smmu 0x3184 0x0420>;
5272                                         };       5272                                         };
5273                                                  5273 
5274                                         compu    5274                                         compute-cb@5 {
5275                                                  5275                                                 compatible = "qcom,fastrpc-compute-cb";
5276                                                  5276                                                 reg = <5>;
5277                                                  5277                                                 iommus = <&apps_smmu 0x3185 0x0420>;
5278                                         };       5278                                         };
5279                                                  5279 
5280                                         compu    5280                                         compute-cb@6 {
5281                                                  5281                                                 compatible = "qcom,fastrpc-compute-cb";
5282                                                  5282                                                 reg = <6>;
5283                                                  5283                                                 iommus = <&apps_smmu 0x3186 0x0420>;
5284                                         };       5284                                         };
5285                                                  5285 
5286                                         compu    5286                                         compute-cb@7 {
5287                                                  5287                                                 compatible = "qcom,fastrpc-compute-cb";
5288                                                  5288                                                 reg = <7>;
5289                                                  5289                                                 iommus = <&apps_smmu 0x3187 0x0420>;
5290                                         };       5290                                         };
5291                                                  5291 
5292                                         compu    5292                                         compute-cb@8 {
5293                                                  5293                                                 compatible = "qcom,fastrpc-compute-cb";
5294                                                  5294                                                 reg = <8>;
5295                                                  5295                                                 iommus = <&apps_smmu 0x3188 0x0420>;
5296                                         };       5296                                         };
5297                                                  5297 
5298                                         compu    5298                                         compute-cb@9 {
5299                                                  5299                                                 compatible = "qcom,fastrpc-compute-cb";
5300                                                  5300                                                 reg = <9>;
5301                                                  5301                                                 iommus = <&apps_smmu 0x318b 0x0420>;
5302                                         };       5302                                         };
5303                                                  5303 
5304                                         compu    5304                                         compute-cb@10 {
5305                                                  5305                                                 compatible = "qcom,fastrpc-compute-cb";
5306                                                  5306                                                 reg = <10>;
5307                                                  5307                                                 iommus = <&apps_smmu 0x318b 0x0420>;
5308                                         };       5308                                         };
5309                                                  5309 
5310                                         compu    5310                                         compute-cb@11 {
5311                                                  5311                                                 compatible = "qcom,fastrpc-compute-cb";
5312                                                  5312                                                 reg = <11>;
5313                                                  5313                                                 iommus = <&apps_smmu 0x318c 0x0420>;
5314                                         };       5314                                         };
5315                                                  5315 
5316                                         compu    5316                                         compute-cb@12 {
5317                                                  5317                                                 compatible = "qcom,fastrpc-compute-cb";
5318                                                  5318                                                 reg = <12>;
5319                                                  5319                                                 iommus = <&apps_smmu 0x318d 0x0420>;
5320                                         };       5320                                         };
5321                                                  5321 
5322                                         compu    5322                                         compute-cb@13 {
5323                                                  5323                                                 compatible = "qcom,fastrpc-compute-cb";
5324                                                  5324                                                 reg = <13>;
5325                                                  5325                                                 iommus = <&apps_smmu 0x318e 0x0420>;
5326                                         };       5326                                         };
5327                                                  5327 
5328                                         compu    5328                                         compute-cb@14 {
5329                                                  5329                                                 compatible = "qcom,fastrpc-compute-cb";
5330                                                  5330                                                 reg = <14>;
5331                                                  5331                                                 iommus = <&apps_smmu 0x318f 0x0420>;
5332                                         };       5332                                         };
5333                                 };               5333                                 };
5334                         };                       5334                         };
5335                 };                               5335                 };
5336                                                  5336 
5337                 remoteproc_nsp1: remoteproc@2    5337                 remoteproc_nsp1: remoteproc@21300000 {
5338                         compatible = "qcom,sc    5338                         compatible = "qcom,sc8280xp-nsp1-pas";
5339                         reg = <0 0x21300000 0    5339                         reg = <0 0x21300000 0 0x100>;
5340                                                  5340 
5341                         interrupts-extended =    5341                         interrupts-extended = <&intc GIC_SPI 887 IRQ_TYPE_EDGE_RISING>,
5342                                                  5342                                               <&smp2p_nsp1_in 0 IRQ_TYPE_EDGE_RISING>,
5343                                                  5343                                               <&smp2p_nsp1_in 1 IRQ_TYPE_EDGE_RISING>,
5344                                                  5344                                               <&smp2p_nsp1_in 2 IRQ_TYPE_EDGE_RISING>,
5345                                                  5345                                               <&smp2p_nsp1_in 3 IRQ_TYPE_EDGE_RISING>;
5346                         interrupt-names = "wd    5346                         interrupt-names = "wdog", "fatal", "ready",
5347                                           "ha    5347                                           "handover", "stop-ack";
5348                                                  5348 
5349                         clocks = <&rpmhcc RPM    5349                         clocks = <&rpmhcc RPMH_CXO_CLK>;
5350                         clock-names = "xo";      5350                         clock-names = "xo";
5351                                                  5351 
5352                         power-domains = <&rpm    5352                         power-domains = <&rpmhpd SC8280XP_NSP>;
5353                         power-domain-names =     5353                         power-domain-names = "nsp";
5354                                                  5354 
5355                         memory-region = <&pil    5355                         memory-region = <&pil_nsp1_mem>;
5356                                                  5356 
5357                         qcom,smem-states = <&    5357                         qcom,smem-states = <&smp2p_nsp1_out 0>;
5358                         qcom,smem-state-names    5358                         qcom,smem-state-names = "stop";
5359                                                  5359 
5360                         interconnects = <&nsp    5360                         interconnects = <&nspb_noc MASTER_CDSP_PROC_B 0 &mc_virt SLAVE_EBI1 0>;
5361                                                  5361 
5362                         status = "disabled";     5362                         status = "disabled";
5363                                                  5363 
5364                         glink-edge {             5364                         glink-edge {
5365                                 interrupts-ex    5365                                 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1
5366                                                  5366                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
5367                                                  5367                                                              IRQ_TYPE_EDGE_RISING>;
5368                                 mboxes = <&ip    5368                                 mboxes = <&ipcc IPCC_CLIENT_NSP1
5369                                                  5369                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
5370                                                  5370 
5371                                 label = "nsp1    5371                                 label = "nsp1";
5372                                 qcom,remote-p    5372                                 qcom,remote-pid = <12>;
5373                         };                       5373                         };
5374                 };                               5374                 };
5375                                                  5375 
5376                 mdss1: display-subsystem@2200    5376                 mdss1: display-subsystem@22000000 {
5377                         compatible = "qcom,sc    5377                         compatible = "qcom,sc8280xp-mdss";
5378                         reg = <0 0x22000000 0    5378                         reg = <0 0x22000000 0 0x1000>;
5379                         reg-names = "mdss";      5379                         reg-names = "mdss";
5380                                                  5380 
5381                         clocks = <&gcc GCC_DI    5381                         clocks = <&gcc GCC_DISP_AHB_CLK>,
5382                                  <&dispcc1 DI    5382                                  <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
5383                                  <&dispcc1 DI    5383                                  <&dispcc1 DISP_CC_MDSS_MDP_CLK>;
5384                         clock-names = "iface"    5384                         clock-names = "iface",
5385                                       "ahb",     5385                                       "ahb",
5386                                       "core";    5386                                       "core";
5387                         interconnects = <&mms    5387                         interconnects = <&mmss_noc MASTER_MDP_CORE1_0 0 &mc_virt SLAVE_EBI1 0>,
5388                                         <&mms    5388                                         <&mmss_noc MASTER_MDP_CORE1_1 0 &mc_virt SLAVE_EBI1 0>;
5389                         interconnect-names =     5389                         interconnect-names = "mdp0-mem", "mdp1-mem";
5390                         interrupts = <GIC_SPI    5390                         interrupts = <GIC_SPI 865 IRQ_TYPE_LEVEL_HIGH>;
5391                                                  5391 
5392                         iommus = <&apps_smmu     5392                         iommus = <&apps_smmu 0x1800 0x402>;
5393                         power-domains = <&dis    5393                         power-domains = <&dispcc1 MDSS_GDSC>;
5394                         resets = <&dispcc1 DI    5394                         resets = <&dispcc1 DISP_CC_MDSS_CORE_BCR>;
5395                                                  5395 
5396                         interrupt-controller;    5396                         interrupt-controller;
5397                         #interrupt-cells = <1    5397                         #interrupt-cells = <1>;
5398                         #address-cells = <2>;    5398                         #address-cells = <2>;
5399                         #size-cells = <2>;       5399                         #size-cells = <2>;
5400                         ranges;                  5400                         ranges;
5401                                                  5401 
5402                         status = "disabled";     5402                         status = "disabled";
5403                                                  5403 
5404                         mdss1_mdp: display-co    5404                         mdss1_mdp: display-controller@22001000 {
5405                                 compatible =     5405                                 compatible = "qcom,sc8280xp-dpu";
5406                                 reg = <0 0x22    5406                                 reg = <0 0x22001000 0 0x8f000>,
5407                                       <0 0x22    5407                                       <0 0x220b0000 0 0x2008>;
5408                                 reg-names = "    5408                                 reg-names = "mdp", "vbif";
5409                                                  5409 
5410                                 clocks = <&gc    5410                                 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
5411                                          <&gc    5411                                          <&gcc GCC_DISP_SF_AXI_CLK>,
5412                                          <&di    5412                                          <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
5413                                          <&di    5413                                          <&dispcc1 DISP_CC_MDSS_MDP_LUT_CLK>,
5414                                          <&di    5414                                          <&dispcc1 DISP_CC_MDSS_MDP_CLK>,
5415                                          <&di    5415                                          <&dispcc1 DISP_CC_MDSS_VSYNC_CLK>;
5416                                 clock-names =    5416                                 clock-names = "bus",
5417                                                  5417                                               "nrt_bus",
5418                                                  5418                                               "iface",
5419                                                  5419                                               "lut",
5420                                                  5420                                               "core",
5421                                                  5421                                               "vsync";
5422                                 interrupt-par    5422                                 interrupt-parent = <&mdss1>;
5423                                 interrupts =     5423                                 interrupts = <0>;
5424                                 power-domains    5424                                 power-domains = <&rpmhpd SC8280XP_MMCX>;
5425                                                  5425 
5426                                 assigned-cloc    5426                                 assigned-clocks = <&dispcc1 DISP_CC_MDSS_VSYNC_CLK>;
5427                                 assigned-cloc    5427                                 assigned-clock-rates = <19200000>;
5428                                 operating-poi    5428                                 operating-points-v2 = <&mdss1_mdp_opp_table>;
5429                                                  5429 
5430                                 ports {          5430                                 ports {
5431                                         #addr    5431                                         #address-cells = <1>;
5432                                         #size    5432                                         #size-cells = <0>;
5433                                                  5433 
5434                                         port@    5434                                         port@0 {
5435                                                  5435                                                 reg = <0>;
5436                                                  5436                                                 mdss1_intf0_out: endpoint {
5437                                                  5437                                                         remote-endpoint = <&mdss1_dp0_in>;
5438                                                  5438                                                 };
5439                                         };       5439                                         };
5440                                                  5440 
5441                                         port@    5441                                         port@4 {
5442                                                  5442                                                 reg = <4>;
5443                                                  5443                                                 mdss1_intf4_out: endpoint {
5444                                                  5444                                                         remote-endpoint = <&mdss1_dp1_in>;
5445                                                  5445                                                 };
5446                                         };       5446                                         };
5447                                                  5447 
5448                                         port@    5448                                         port@5 {
5449                                                  5449                                                 reg = <5>;
5450                                                  5450                                                 mdss1_intf5_out: endpoint {
5451                                                  5451                                                         remote-endpoint = <&mdss1_dp3_in>;
5452                                                  5452                                                 };
5453                                         };       5453                                         };
5454                                                  5454 
5455                                         port@    5455                                         port@6 {
5456                                                  5456                                                 reg = <6>;
5457                                                  5457                                                 mdss1_intf6_out: endpoint {
5458                                                  5458                                                         remote-endpoint = <&mdss1_dp2_in>;
5459                                                  5459                                                 };
5460                                         };       5460                                         };
5461                                 };               5461                                 };
5462                                                  5462 
5463                                 mdss1_mdp_opp    5463                                 mdss1_mdp_opp_table: opp-table {
5464                                         compa    5464                                         compatible = "operating-points-v2";
5465                                                  5465 
5466                                         opp-2    5466                                         opp-200000000 {
5467                                                  5467                                                 opp-hz = /bits/ 64 <200000000>;
5468                                                  5468                                                 required-opps = <&rpmhpd_opp_low_svs>;
5469                                         };       5469                                         };
5470                                                  5470 
5471                                         opp-3    5471                                         opp-300000000 {
5472                                                  5472                                                 opp-hz = /bits/ 64 <300000000>;
5473                                                  5473                                                 required-opps = <&rpmhpd_opp_svs>;
5474                                         };       5474                                         };
5475                                                  5475 
5476                                         opp-3    5476                                         opp-375000000 {
5477                                                  5477                                                 opp-hz = /bits/ 64 <375000000>;
5478                                                  5478                                                 required-opps = <&rpmhpd_opp_svs_l1>;
5479                                         };       5479                                         };
5480                                                  5480 
5481                                         opp-5    5481                                         opp-500000000 {
5482                                                  5482                                                 opp-hz = /bits/ 64 <500000000>;
5483                                                  5483                                                 required-opps = <&rpmhpd_opp_nom>;
5484                                         };       5484                                         };
5485                                         opp-6    5485                                         opp-600000000 {
5486                                                  5486                                                 opp-hz = /bits/ 64 <600000000>;
5487                                                  5487                                                 required-opps = <&rpmhpd_opp_turbo_l1>;
5488                                         };       5488                                         };
5489                                 };               5489                                 };
5490                         };                       5490                         };
5491                                                  5491 
5492                         mdss1_dp0: displaypor    5492                         mdss1_dp0: displayport-controller@22090000 {
5493                                 compatible =     5493                                 compatible = "qcom,sc8280xp-dp";
5494                                 reg = <0 0x22    5494                                 reg = <0 0x22090000 0 0x200>,
5495                                       <0 0x22    5495                                       <0 0x22090200 0 0x200>,
5496                                       <0 0x22    5496                                       <0 0x22090400 0 0x600>,
5497                                       <0 0x22    5497                                       <0 0x22091000 0 0x400>,
5498                                       <0 0x22    5498                                       <0 0x22091400 0 0x400>;
5499                                                  5499 
5500                                 clocks = <&di    5500                                 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
5501                                          <&di    5501                                          <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>,
5502                                          <&di    5502                                          <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK>,
5503                                          <&di    5503                                          <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
5504                                          <&di    5504                                          <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
5505                                 clock-names =    5505                                 clock-names = "core_iface", "core_aux",
5506                                                  5506                                               "ctrl_link",
5507                                                  5507                                               "ctrl_link_iface", "stream_pixel";
5508                                 interrupt-par    5508                                 interrupt-parent = <&mdss1>;
5509                                 interrupts =     5509                                 interrupts = <12>;
5510                                 phys = <&mdss    5510                                 phys = <&mdss1_dp0_phy>;
5511                                 phy-names = "    5511                                 phy-names = "dp";
5512                                 power-domains    5512                                 power-domains = <&rpmhpd SC8280XP_MMCX>;
5513                                                  5513 
5514                                 assigned-cloc    5514                                 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
5515                                                  5515                                                   <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
5516                                 assigned-cloc    5516                                 assigned-clock-parents = <&mdss1_dp0_phy 0>, <&mdss1_dp0_phy 1>;
5517                                 operating-poi    5517                                 operating-points-v2 = <&mdss1_dp0_opp_table>;
5518                                                  5518 
5519                                 #sound-dai-ce    5519                                 #sound-dai-cells = <0>;
5520                                                  5520 
5521                                 status = "dis    5521                                 status = "disabled";
5522                                                  5522 
5523                                 ports {          5523                                 ports {
5524                                         #addr    5524                                         #address-cells = <1>;
5525                                         #size    5525                                         #size-cells = <0>;
5526                                                  5526 
5527                                         port@    5527                                         port@0 {
5528                                                  5528                                                 reg = <0>;
5529                                                  5529                                                 mdss1_dp0_in: endpoint {
5530                                                  5530                                                         remote-endpoint = <&mdss1_intf0_out>;
5531                                                  5531                                                 };
5532                                         };       5532                                         };
5533                                                  5533 
5534                                         port@    5534                                         port@1 {
5535                                                  5535                                                 reg = <1>;
5536                                         };       5536                                         };
5537                                 };               5537                                 };
5538                                                  5538 
5539                                 mdss1_dp0_opp    5539                                 mdss1_dp0_opp_table: opp-table {
5540                                         compa    5540                                         compatible = "operating-points-v2";
5541                                                  5541 
5542                                         opp-1    5542                                         opp-160000000 {
5543                                                  5543                                                 opp-hz = /bits/ 64 <160000000>;
5544                                                  5544                                                 required-opps = <&rpmhpd_opp_low_svs>;
5545                                         };       5545                                         };
5546                                                  5546 
5547                                         opp-2    5547                                         opp-270000000 {
5548                                                  5548                                                 opp-hz = /bits/ 64 <270000000>;
5549                                                  5549                                                 required-opps = <&rpmhpd_opp_svs>;
5550                                         };       5550                                         };
5551                                                  5551 
5552                                         opp-5    5552                                         opp-540000000 {
5553                                                  5553                                                 opp-hz = /bits/ 64 <540000000>;
5554                                                  5554                                                 required-opps = <&rpmhpd_opp_svs_l1>;
5555                                         };       5555                                         };
5556                                                  5556 
5557                                         opp-8    5557                                         opp-810000000 {
5558                                                  5558                                                 opp-hz = /bits/ 64 <810000000>;
5559                                                  5559                                                 required-opps = <&rpmhpd_opp_nom>;
5560                                         };       5560                                         };
5561                                 };               5561                                 };
5562                         };                       5562                         };
5563                                                  5563 
5564                         mdss1_dp1: displaypor    5564                         mdss1_dp1: displayport-controller@22098000 {
5565                                 compatible =     5565                                 compatible = "qcom,sc8280xp-dp";
5566                                 reg = <0 0x22    5566                                 reg = <0 0x22098000 0 0x200>,
5567                                       <0 0x22    5567                                       <0 0x22098200 0 0x200>,
5568                                       <0 0x22    5568                                       <0 0x22098400 0 0x600>,
5569                                       <0 0x22    5569                                       <0 0x22099000 0 0x400>,
5570                                       <0 0x22    5570                                       <0 0x22099400 0 0x400>;
5571                                                  5571 
5572                                 clocks = <&di    5572                                 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
5573                                          <&di    5573                                          <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>,
5574                                          <&di    5574                                          <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK>,
5575                                          <&di    5575                                          <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
5576                                          <&di    5576                                          <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>;
5577                                 clock-names =    5577                                 clock-names = "core_iface", "core_aux",
5578                                                  5578                                               "ctrl_link",
5579                                                  5579                                               "ctrl_link_iface", "stream_pixel";
5580                                 interrupt-par    5580                                 interrupt-parent = <&mdss1>;
5581                                 interrupts =     5581                                 interrupts = <13>;
5582                                 phys = <&mdss    5582                                 phys = <&mdss1_dp1_phy>;
5583                                 phy-names = "    5583                                 phy-names = "dp";
5584                                 power-domains    5584                                 power-domains = <&rpmhpd SC8280XP_MMCX>;
5585                                                  5585 
5586                                 assigned-cloc    5586                                 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
5587                                                  5587                                                   <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>;
5588                                 assigned-cloc    5588                                 assigned-clock-parents = <&mdss1_dp1_phy 0>, <&mdss1_dp1_phy 1>;
5589                                 operating-poi    5589                                 operating-points-v2 = <&mdss1_dp1_opp_table>;
5590                                                  5590 
5591                                 #sound-dai-ce    5591                                 #sound-dai-cells = <0>;
5592                                                  5592 
5593                                 status = "dis    5593                                 status = "disabled";
5594                                                  5594 
5595                                 ports {          5595                                 ports {
5596                                         #addr    5596                                         #address-cells = <1>;
5597                                         #size    5597                                         #size-cells = <0>;
5598                                                  5598 
5599                                         port@    5599                                         port@0 {
5600                                                  5600                                                 reg = <0>;
5601                                                  5601                                                 mdss1_dp1_in: endpoint {
5602                                                  5602                                                         remote-endpoint = <&mdss1_intf4_out>;
5603                                                  5603                                                 };
5604                                         };       5604                                         };
5605                                                  5605 
5606                                         port@    5606                                         port@1 {
5607                                                  5607                                                 reg = <1>;
5608                                         };       5608                                         };
5609                                 };               5609                                 };
5610                                                  5610 
5611                                 mdss1_dp1_opp    5611                                 mdss1_dp1_opp_table: opp-table {
5612                                         compa    5612                                         compatible = "operating-points-v2";
5613                                                  5613 
5614                                         opp-1    5614                                         opp-160000000 {
5615                                                  5615                                                 opp-hz = /bits/ 64 <160000000>;
5616                                                  5616                                                 required-opps = <&rpmhpd_opp_low_svs>;
5617                                         };       5617                                         };
5618                                                  5618 
5619                                         opp-2    5619                                         opp-270000000 {
5620                                                  5620                                                 opp-hz = /bits/ 64 <270000000>;
5621                                                  5621                                                 required-opps = <&rpmhpd_opp_svs>;
5622                                         };       5622                                         };
5623                                                  5623 
5624                                         opp-5    5624                                         opp-540000000 {
5625                                                  5625                                                 opp-hz = /bits/ 64 <540000000>;
5626                                                  5626                                                 required-opps = <&rpmhpd_opp_svs_l1>;
5627                                         };       5627                                         };
5628                                                  5628 
5629                                         opp-8    5629                                         opp-810000000 {
5630                                                  5630                                                 opp-hz = /bits/ 64 <810000000>;
5631                                                  5631                                                 required-opps = <&rpmhpd_opp_nom>;
5632                                         };       5632                                         };
5633                                 };               5633                                 };
5634                         };                       5634                         };
5635                                                  5635 
5636                         mdss1_dp2: displaypor    5636                         mdss1_dp2: displayport-controller@2209a000 {
5637                                 compatible =     5637                                 compatible = "qcom,sc8280xp-dp";
5638                                 reg = <0 0x22    5638                                 reg = <0 0x2209a000 0 0x200>,
5639                                       <0 0x22    5639                                       <0 0x2209a200 0 0x200>,
5640                                       <0 0x22    5640                                       <0 0x2209a400 0 0x600>,
5641                                       <0 0x22    5641                                       <0 0x2209b000 0 0x400>,
5642                                       <0 0x22    5642                                       <0 0x2209b400 0 0x400>;
5643                                                  5643 
5644                                 clocks = <&di    5644                                 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
5645                                          <&di    5645                                          <&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>,
5646                                          <&di    5646                                          <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK>,
5647                                          <&di    5647                                          <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>,
5648                                          <&di    5648                                          <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>;
5649                                 clock-names =    5649                                 clock-names = "core_iface", "core_aux",
5650                                                  5650                                               "ctrl_link",
5651                                                  5651                                               "ctrl_link_iface", "stream_pixel";
5652                                 interrupt-par    5652                                 interrupt-parent = <&mdss1>;
5653                                 interrupts =     5653                                 interrupts = <14>;
5654                                 phys = <&mdss    5654                                 phys = <&mdss1_dp2_phy>;
5655                                 phy-names = "    5655                                 phy-names = "dp";
5656                                 power-domains    5656                                 power-domains = <&rpmhpd SC8280XP_MMCX>;
5657                                                  5657 
5658                                 assigned-cloc    5658                                 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
5659                                                  5659                                                   <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>;
5660                                 assigned-cloc    5660                                 assigned-clock-parents = <&mdss1_dp2_phy 0>, <&mdss1_dp2_phy 1>;
5661                                 operating-poi    5661                                 operating-points-v2 = <&mdss1_dp2_opp_table>;
5662                                                  5662 
5663                                 #sound-dai-ce    5663                                 #sound-dai-cells = <0>;
5664                                                  5664 
5665                                 status = "dis    5665                                 status = "disabled";
5666                                                  5666 
5667                                 ports {          5667                                 ports {
5668                                         #addr    5668                                         #address-cells = <1>;
5669                                         #size    5669                                         #size-cells = <0>;
5670                                                  5670 
5671                                         port@    5671                                         port@0 {
5672                                                  5672                                                 reg = <0>;
5673                                                  5673                                                 mdss1_dp2_in: endpoint {
5674                                                  5674                                                         remote-endpoint = <&mdss1_intf6_out>;
5675                                                  5675                                                 };
5676                                         };       5676                                         };
5677                                                  5677 
5678                                         port@    5678                                         port@1 {
5679                                                  5679                                                 reg = <1>;
5680                                         };       5680                                         };
5681                                 };               5681                                 };
5682                                                  5682 
5683                                 mdss1_dp2_opp    5683                                 mdss1_dp2_opp_table: opp-table {
5684                                         compa    5684                                         compatible = "operating-points-v2";
5685                                                  5685 
5686                                         opp-1    5686                                         opp-160000000 {
5687                                                  5687                                                 opp-hz = /bits/ 64 <160000000>;
5688                                                  5688                                                 required-opps = <&rpmhpd_opp_low_svs>;
5689                                         };       5689                                         };
5690                                                  5690 
5691                                         opp-2    5691                                         opp-270000000 {
5692                                                  5692                                                 opp-hz = /bits/ 64 <270000000>;
5693                                                  5693                                                 required-opps = <&rpmhpd_opp_svs>;
5694                                         };       5694                                         };
5695                                                  5695 
5696                                         opp-5    5696                                         opp-540000000 {
5697                                                  5697                                                 opp-hz = /bits/ 64 <540000000>;
5698                                                  5698                                                 required-opps = <&rpmhpd_opp_svs_l1>;
5699                                         };       5699                                         };
5700                                                  5700 
5701                                         opp-8    5701                                         opp-810000000 {
5702                                                  5702                                                 opp-hz = /bits/ 64 <810000000>;
5703                                                  5703                                                 required-opps = <&rpmhpd_opp_nom>;
5704                                         };       5704                                         };
5705                                 };               5705                                 };
5706                         };                       5706                         };
5707                                                  5707 
5708                         mdss1_dp3: displaypor    5708                         mdss1_dp3: displayport-controller@220a0000 {
5709                                 compatible =     5709                                 compatible = "qcom,sc8280xp-dp";
5710                                 reg = <0 0x22    5710                                 reg = <0 0x220a0000 0 0x200>,
5711                                       <0 0x22    5711                                       <0 0x220a0200 0 0x200>,
5712                                       <0 0x22    5712                                       <0 0x220a0400 0 0x600>,
5713                                       <0 0x22    5713                                       <0 0x220a1000 0 0x400>,
5714                                       <0 0x22    5714                                       <0 0x220a1400 0 0x400>;
5715                                                  5715 
5716                                 clocks = <&di    5716                                 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
5717                                          <&di    5717                                          <&dispcc1 DISP_CC_MDSS_DPTX3_AUX_CLK>,
5718                                          <&di    5718                                          <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_CLK>,
5719                                          <&di    5719                                          <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>,
5720                                          <&di    5720                                          <&dispcc1 DISP_CC_MDSS_DPTX3_PIXEL0_CLK>;
5721                                 clock-names =    5721                                 clock-names = "core_iface", "core_aux",
5722                                                  5722                                               "ctrl_link",
5723                                                  5723                                               "ctrl_link_iface", "stream_pixel";
5724                                 interrupt-par    5724                                 interrupt-parent = <&mdss1>;
5725                                 interrupts =     5725                                 interrupts = <15>;
5726                                 phys = <&mdss    5726                                 phys = <&mdss1_dp3_phy>;
5727                                 phy-names = "    5727                                 phy-names = "dp";
5728                                 power-domains    5728                                 power-domains = <&rpmhpd SC8280XP_MMCX>;
5729                                                  5729 
5730                                 assigned-cloc    5730                                 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>,
5731                                                  5731                                                   <&dispcc1 DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>;
5732                                 assigned-cloc    5732                                 assigned-clock-parents = <&mdss1_dp3_phy 0>, <&mdss1_dp3_phy 1>;
5733                                 operating-poi    5733                                 operating-points-v2 = <&mdss1_dp3_opp_table>;
5734                                                  5734 
5735                                 #sound-dai-ce    5735                                 #sound-dai-cells = <0>;
5736                                                  5736 
5737                                 status = "dis    5737                                 status = "disabled";
5738                                                  5738 
5739                                 ports {          5739                                 ports {
5740                                         #addr    5740                                         #address-cells = <1>;
5741                                         #size    5741                                         #size-cells = <0>;
5742                                                  5742 
5743                                         port@    5743                                         port@0 {
5744                                                  5744                                                 reg = <0>;
5745                                                  5745                                                 mdss1_dp3_in: endpoint {
5746                                                  5746                                                         remote-endpoint = <&mdss1_intf5_out>;
5747                                                  5747                                                 };
5748                                         };       5748                                         };
5749                                                  5749 
5750                                         port@    5750                                         port@1 {
5751                                                  5751                                                 reg = <1>;
5752                                         };       5752                                         };
5753                                 };               5753                                 };
5754                                                  5754 
5755                                 mdss1_dp3_opp    5755                                 mdss1_dp3_opp_table: opp-table {
5756                                         compa    5756                                         compatible = "operating-points-v2";
5757                                                  5757 
5758                                         opp-1    5758                                         opp-160000000 {
5759                                                  5759                                                 opp-hz = /bits/ 64 <160000000>;
5760                                                  5760                                                 required-opps = <&rpmhpd_opp_low_svs>;
5761                                         };       5761                                         };
5762                                                  5762 
5763                                         opp-2    5763                                         opp-270000000 {
5764                                                  5764                                                 opp-hz = /bits/ 64 <270000000>;
5765                                                  5765                                                 required-opps = <&rpmhpd_opp_svs>;
5766                                         };       5766                                         };
5767                                                  5767 
5768                                         opp-5    5768                                         opp-540000000 {
5769                                                  5769                                                 opp-hz = /bits/ 64 <540000000>;
5770                                                  5770                                                 required-opps = <&rpmhpd_opp_svs_l1>;
5771                                         };       5771                                         };
5772                                                  5772 
5773                                         opp-8    5773                                         opp-810000000 {
5774                                                  5774                                                 opp-hz = /bits/ 64 <810000000>;
5775                                                  5775                                                 required-opps = <&rpmhpd_opp_nom>;
5776                                         };       5776                                         };
5777                                 };               5777                                 };
5778                         };                       5778                         };
5779                 };                               5779                 };
5780                                                  5780 
5781                 mdss1_dp2_phy: phy@220c2a00 {    5781                 mdss1_dp2_phy: phy@220c2a00 {
5782                         compatible = "qcom,sc    5782                         compatible = "qcom,sc8280xp-dp-phy";
5783                         reg = <0 0x220c2a00 0    5783                         reg = <0 0x220c2a00 0 0x19c>,
5784                               <0 0x220c2200 0    5784                               <0 0x220c2200 0 0xec>,
5785                               <0 0x220c2600 0    5785                               <0 0x220c2600 0 0xec>,
5786                               <0 0x220c2000 0    5786                               <0 0x220c2000 0 0x1c8>;
5787                                                  5787 
5788                         clocks = <&dispcc1 DI    5788                         clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>,
5789                                  <&dispcc1 DI    5789                                  <&dispcc1 DISP_CC_MDSS_AHB_CLK>;
5790                         clock-names = "aux",     5790                         clock-names = "aux", "cfg_ahb";
5791                         power-domains = <&rpm    5791                         power-domains = <&rpmhpd SC8280XP_MX>;
5792                                                  5792 
5793                         #clock-cells = <1>;      5793                         #clock-cells = <1>;
5794                         #phy-cells = <0>;        5794                         #phy-cells = <0>;
5795                                                  5795 
5796                         status = "disabled";     5796                         status = "disabled";
5797                 };                               5797                 };
5798                                                  5798 
5799                 mdss1_dp3_phy: phy@220c5a00 {    5799                 mdss1_dp3_phy: phy@220c5a00 {
5800                         compatible = "qcom,sc    5800                         compatible = "qcom,sc8280xp-dp-phy";
5801                         reg = <0 0x220c5a00 0    5801                         reg = <0 0x220c5a00 0 0x19c>,
5802                               <0 0x220c5200 0    5802                               <0 0x220c5200 0 0xec>,
5803                               <0 0x220c5600 0    5803                               <0 0x220c5600 0 0xec>,
5804                               <0 0x220c5000 0    5804                               <0 0x220c5000 0 0x1c8>;
5805                                                  5805 
5806                         clocks = <&dispcc1 DI    5806                         clocks = <&dispcc1 DISP_CC_MDSS_DPTX3_AUX_CLK>,
5807                                  <&dispcc1 DI    5807                                  <&dispcc1 DISP_CC_MDSS_AHB_CLK>;
5808                         clock-names = "aux",     5808                         clock-names = "aux", "cfg_ahb";
5809                         power-domains = <&rpm    5809                         power-domains = <&rpmhpd SC8280XP_MX>;
5810                                                  5810 
5811                         #clock-cells = <1>;      5811                         #clock-cells = <1>;
5812                         #phy-cells = <0>;        5812                         #phy-cells = <0>;
5813                                                  5813 
5814                         status = "disabled";     5814                         status = "disabled";
5815                 };                               5815                 };
5816                                                  5816 
5817                 dispcc1: clock-controller@221    5817                 dispcc1: clock-controller@22100000 {
5818                         compatible = "qcom,sc    5818                         compatible = "qcom,sc8280xp-dispcc1";
5819                         reg = <0 0x22100000 0    5819                         reg = <0 0x22100000 0 0x20000>;
5820                                                  5820 
5821                         clocks = <&gcc GCC_DI    5821                         clocks = <&gcc GCC_DISP_AHB_CLK>,
5822                                  <&rpmhcc RPM    5822                                  <&rpmhcc RPMH_CXO_CLK>,
5823                                  <0>,            5823                                  <0>,
5824                                  <&mdss1_dp0_    5824                                  <&mdss1_dp0_phy 0>,
5825                                  <&mdss1_dp0_    5825                                  <&mdss1_dp0_phy 1>,
5826                                  <&mdss1_dp1_    5826                                  <&mdss1_dp1_phy 0>,
5827                                  <&mdss1_dp1_    5827                                  <&mdss1_dp1_phy 1>,
5828                                  <&mdss1_dp2_    5828                                  <&mdss1_dp2_phy 0>,
5829                                  <&mdss1_dp2_    5829                                  <&mdss1_dp2_phy 1>,
5830                                  <&mdss1_dp3_    5830                                  <&mdss1_dp3_phy 0>,
5831                                  <&mdss1_dp3_    5831                                  <&mdss1_dp3_phy 1>,
5832                                  <0>,            5832                                  <0>,
5833                                  <0>,            5833                                  <0>,
5834                                  <0>,            5834                                  <0>,
5835                                  <0>;            5835                                  <0>;
5836                         power-domains = <&rpm    5836                         power-domains = <&rpmhpd SC8280XP_MMCX>;
5837                                                  5837 
5838                         #clock-cells = <1>;      5838                         #clock-cells = <1>;
5839                         #power-domain-cells =    5839                         #power-domain-cells = <1>;
5840                         #reset-cells = <1>;      5840                         #reset-cells = <1>;
5841                                                  5841 
5842                         status = "disabled";     5842                         status = "disabled";
5843                 };                               5843                 };
5844                                                  5844 
5845                 ethernet1: ethernet@23000000     5845                 ethernet1: ethernet@23000000 {
5846                         compatible = "qcom,sc    5846                         compatible = "qcom,sc8280xp-ethqos";
5847                         reg = <0x0 0x23000000    5847                         reg = <0x0 0x23000000 0x0 0x10000>,
5848                               <0x0 0x23016000    5848                               <0x0 0x23016000 0x0 0x100>;
5849                         reg-names = "stmmacet    5849                         reg-names = "stmmaceth", "rgmii";
5850                                                  5850 
5851                         clocks = <&gcc GCC_EM    5851                         clocks = <&gcc GCC_EMAC1_AXI_CLK>,
5852                                  <&gcc GCC_EM    5852                                  <&gcc GCC_EMAC1_SLV_AHB_CLK>,
5853                                  <&gcc GCC_EM    5853                                  <&gcc GCC_EMAC1_PTP_CLK>,
5854                                  <&gcc GCC_EM    5854                                  <&gcc GCC_EMAC1_RGMII_CLK>;
5855                         clock-names = "stmmac    5855                         clock-names = "stmmaceth",
5856                                       "pclk",    5856                                       "pclk",
5857                                       "ptp_re    5857                                       "ptp_ref",
5858                                       "rgmii"    5858                                       "rgmii";
5859                                                  5859 
5860                         interrupts = <GIC_SPI    5860                         interrupts = <GIC_SPI 929 IRQ_TYPE_LEVEL_HIGH>,
5861                                      <GIC_SPI    5861                                      <GIC_SPI 919 IRQ_TYPE_LEVEL_HIGH>;
5862                         interrupt-names = "ma    5862                         interrupt-names = "macirq", "eth_lpi";
5863                                                  5863 
5864                         iommus = <&apps_smmu     5864                         iommus = <&apps_smmu 0x40 0xf>;
5865                         power-domains = <&gcc    5865                         power-domains = <&gcc EMAC_1_GDSC>;
5866                                                  5866 
5867                         snps,tso;                5867                         snps,tso;
5868                         snps,pbl = <32>;         5868                         snps,pbl = <32>;
5869                         rx-fifo-depth = <4096    5869                         rx-fifo-depth = <4096>;
5870                         tx-fifo-depth = <4096    5870                         tx-fifo-depth = <4096>;
5871                                                  5871 
5872                         status = "disabled";     5872                         status = "disabled";
5873                 };                               5873                 };
5874         };                                       5874         };
5875                                                  5875 
5876         sound: sound {                           5876         sound: sound {
5877         };                                       5877         };
5878                                                  5878 
5879         thermal-zones {                          5879         thermal-zones {
5880                 cpu0-thermal {                   5880                 cpu0-thermal {
5881                         polling-delay-passive    5881                         polling-delay-passive = <250>;
5882                                                  5882 
5883                         thermal-sensors = <&t    5883                         thermal-sensors = <&tsens0 1>;
5884                                                  5884 
5885                         trips {                  5885                         trips {
5886                                 cpu-crit {       5886                                 cpu-crit {
5887                                         tempe    5887                                         temperature = <110000>;
5888                                         hyste    5888                                         hysteresis = <1000>;
5889                                         type     5889                                         type = "critical";
5890                                 };               5890                                 };
5891                         };                       5891                         };
5892                 };                               5892                 };
5893                                                  5893 
5894                 cpu1-thermal {                   5894                 cpu1-thermal {
5895                         polling-delay-passive    5895                         polling-delay-passive = <250>;
5896                                                  5896 
5897                         thermal-sensors = <&t    5897                         thermal-sensors = <&tsens0 2>;
5898                                                  5898 
5899                         trips {                  5899                         trips {
5900                                 cpu-crit {       5900                                 cpu-crit {
5901                                         tempe    5901                                         temperature = <110000>;
5902                                         hyste    5902                                         hysteresis = <1000>;
5903                                         type     5903                                         type = "critical";
5904                                 };               5904                                 };
5905                         };                       5905                         };
5906                 };                               5906                 };
5907                                                  5907 
5908                 cpu2-thermal {                   5908                 cpu2-thermal {
5909                         polling-delay-passive    5909                         polling-delay-passive = <250>;
5910                                                  5910 
5911                         thermal-sensors = <&t    5911                         thermal-sensors = <&tsens0 3>;
5912                                                  5912 
5913                         trips {                  5913                         trips {
5914                                 cpu-crit {       5914                                 cpu-crit {
5915                                         tempe    5915                                         temperature = <110000>;
5916                                         hyste    5916                                         hysteresis = <1000>;
5917                                         type     5917                                         type = "critical";
5918                                 };               5918                                 };
5919                         };                       5919                         };
5920                 };                               5920                 };
5921                                                  5921 
5922                 cpu3-thermal {                   5922                 cpu3-thermal {
5923                         polling-delay-passive    5923                         polling-delay-passive = <250>;
5924                                                  5924 
5925                         thermal-sensors = <&t    5925                         thermal-sensors = <&tsens0 4>;
5926                                                  5926 
5927                         trips {                  5927                         trips {
5928                                 cpu-crit {       5928                                 cpu-crit {
5929                                         tempe    5929                                         temperature = <110000>;
5930                                         hyste    5930                                         hysteresis = <1000>;
5931                                         type     5931                                         type = "critical";
5932                                 };               5932                                 };
5933                         };                       5933                         };
5934                 };                               5934                 };
5935                                                  5935 
5936                 cpu4-thermal {                   5936                 cpu4-thermal {
5937                         polling-delay-passive    5937                         polling-delay-passive = <250>;
5938                                                  5938 
5939                         thermal-sensors = <&t    5939                         thermal-sensors = <&tsens0 5>;
5940                                                  5940 
5941                         trips {                  5941                         trips {
5942                                 cpu-crit {       5942                                 cpu-crit {
5943                                         tempe    5943                                         temperature = <110000>;
5944                                         hyste    5944                                         hysteresis = <1000>;
5945                                         type     5945                                         type = "critical";
5946                                 };               5946                                 };
5947                         };                       5947                         };
5948                 };                               5948                 };
5949                                                  5949 
5950                 cpu5-thermal {                   5950                 cpu5-thermal {
5951                         polling-delay-passive    5951                         polling-delay-passive = <250>;
5952                                                  5952 
5953                         thermal-sensors = <&t    5953                         thermal-sensors = <&tsens0 6>;
5954                                                  5954 
5955                         trips {                  5955                         trips {
5956                                 cpu-crit {       5956                                 cpu-crit {
5957                                         tempe    5957                                         temperature = <110000>;
5958                                         hyste    5958                                         hysteresis = <1000>;
5959                                         type     5959                                         type = "critical";
5960                                 };               5960                                 };
5961                         };                       5961                         };
5962                 };                               5962                 };
5963                                                  5963 
5964                 cpu6-thermal {                   5964                 cpu6-thermal {
5965                         polling-delay-passive    5965                         polling-delay-passive = <250>;
5966                                                  5966 
5967                         thermal-sensors = <&t    5967                         thermal-sensors = <&tsens0 7>;
5968                                                  5968 
5969                         trips {                  5969                         trips {
5970                                 cpu-crit {       5970                                 cpu-crit {
5971                                         tempe    5971                                         temperature = <110000>;
5972                                         hyste    5972                                         hysteresis = <1000>;
5973                                         type     5973                                         type = "critical";
5974                                 };               5974                                 };
5975                         };                       5975                         };
5976                 };                               5976                 };
5977                                                  5977 
5978                 cpu7-thermal {                   5978                 cpu7-thermal {
5979                         polling-delay-passive    5979                         polling-delay-passive = <250>;
5980                                                  5980 
5981                         thermal-sensors = <&t    5981                         thermal-sensors = <&tsens0 8>;
5982                                                  5982 
5983                         trips {                  5983                         trips {
5984                                 cpu-crit {       5984                                 cpu-crit {
5985                                         tempe    5985                                         temperature = <110000>;
5986                                         hyste    5986                                         hysteresis = <1000>;
5987                                         type     5987                                         type = "critical";
5988                                 };               5988                                 };
5989                         };                       5989                         };
5990                 };                               5990                 };
5991                                                  5991 
5992                 cluster0-thermal {               5992                 cluster0-thermal {
5993                         polling-delay-passive    5993                         polling-delay-passive = <250>;
5994                                                  5994 
5995                         thermal-sensors = <&t    5995                         thermal-sensors = <&tsens0 9>;
5996                                                  5996 
5997                         trips {                  5997                         trips {
5998                                 cpu-crit {       5998                                 cpu-crit {
5999                                         tempe    5999                                         temperature = <110000>;
6000                                         hyste    6000                                         hysteresis = <1000>;
6001                                         type     6001                                         type = "critical";
6002                                 };               6002                                 };
6003                         };                       6003                         };
6004                 };                               6004                 };
6005                                                  6005 
6006                 gpu-thermal {                    6006                 gpu-thermal {
6007                         polling-delay-passive    6007                         polling-delay-passive = <250>;
6008                                                  6008 
6009                         thermal-sensors = <&t    6009                         thermal-sensors = <&tsens2 2>;
6010                                                  6010 
6011                         cooling-maps {           6011                         cooling-maps {
6012                                 map0 {           6012                                 map0 {
6013                                         trip     6013                                         trip = <&gpu_alert0>;
6014                                         cooli    6014                                         cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6015                                 };               6015                                 };
6016                         };                       6016                         };
6017                                                  6017 
6018                         trips {                  6018                         trips {
6019                                 gpu_alert0: t    6019                                 gpu_alert0: trip-point0 {
6020                                         tempe    6020                                         temperature = <85000>;
6021                                         hyste    6021                                         hysteresis = <1000>;
6022                                         type     6022                                         type = "passive";
6023                                 };               6023                                 };
6024                                                  6024 
6025                                 trip-point1 {    6025                                 trip-point1 {
6026                                         tempe    6026                                         temperature = <110000>;
6027                                         hyste    6027                                         hysteresis = <1000>;
6028                                         type     6028                                         type = "critical";
6029                                 };               6029                                 };
6030                         };                       6030                         };
6031                 };                               6031                 };
6032                                                  6032 
6033                 mem-thermal {                    6033                 mem-thermal {
6034                         polling-delay-passive    6034                         polling-delay-passive = <250>;
6035                                                  6035 
6036                         thermal-sensors = <&t    6036                         thermal-sensors = <&tsens1 15>;
6037                                                  6037 
6038                         trips {                  6038                         trips {
6039                                 trip-point0 {    6039                                 trip-point0 {
6040                                         tempe    6040                                         temperature = <90000>;
6041                                         hyste    6041                                         hysteresis = <2000>;
6042                                         type     6042                                         type = "hot";
6043                                 };               6043                                 };
6044                         };                       6044                         };
6045                 };                               6045                 };
6046         };                                       6046         };
6047                                                  6047 
6048         timer {                                  6048         timer {
6049                 compatible = "arm,armv8-timer    6049                 compatible = "arm,armv8-timer";
6050                 interrupts = <GIC_PPI 13 (GIC    6050                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
6051                              <GIC_PPI 14 (GIC    6051                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
6052                              <GIC_PPI 11 (GIC    6052                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
6053                              <GIC_PPI 10 (GIC    6053                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
6054         };                                       6054         };
6055 };                                               6055 };
                                                      

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