1 // SPDX-License-Identifier: BSD-3-Clause
2 /*
3 * Copyright (c) 2020, Konrad Dybcio <konradybc
4 * Copyright (c) 2020, AngeloGioacchino Del Re<
5 */
6
7 #include <dt-bindings/clock/qcom,gcc-sdm660.h>
8 #include <dt-bindings/clock/qcom,gpucc-sdm660.
9 #include <dt-bindings/clock/qcom,mmcc-sdm660.h
10 #include <dt-bindings/clock/qcom,rpmcc.h>
11 #include <dt-bindings/firmware/qcom,scm.h>
12 #include <dt-bindings/interconnect/qcom,sdm660
13 #include <dt-bindings/power/qcom-rpmpd.h>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/interrupt-controller/arm
16 #include <dt-bindings/thermal/thermal.h>
17 #include <dt-bindings/soc/qcom,apr.h>
18
19 / {
20 interrupt-parent = <&intc>;
21
22 #address-cells = <2>;
23 #size-cells = <2>;
24
25 aliases {
26 mmc1 = &sdhc_1;
27 mmc2 = &sdhc_2;
28 };
29
30 chosen { };
31
32 clocks {
33 xo_board: xo-board {
34 compatible = "fixed-cl
35 #clock-cells = <0>;
36 clock-frequency = <192
37 clock-output-names = "
38 };
39
40 sleep_clk: sleep-clk {
41 compatible = "fixed-cl
42 #clock-cells = <0>;
43 clock-frequency = <327
44 clock-output-names = "
45 };
46 };
47
48 cpus {
49 #address-cells = <2>;
50 #size-cells = <0>;
51
52 CPU0: cpu@100 {
53 device_type = "cpu";
54 compatible = "arm,cort
55 reg = <0x0 0x100>;
56 enable-method = "psci"
57 cpu-idle-states = <&PE
58
59
60
61
62 capacity-dmips-mhz = <
63 #cooling-cells = <2>;
64 next-level-cache = <&L
65 L2_1: l2-cache {
66 compatible = "
67 cache-level =
68 cache-unified;
69 };
70 };
71
72 CPU1: cpu@101 {
73 device_type = "cpu";
74 compatible = "arm,cort
75 reg = <0x0 0x101>;
76 enable-method = "psci"
77 cpu-idle-states = <&PE
78
79
80
81
82 capacity-dmips-mhz = <
83 #cooling-cells = <2>;
84 next-level-cache = <&L
85 };
86
87 CPU2: cpu@102 {
88 device_type = "cpu";
89 compatible = "arm,cort
90 reg = <0x0 0x102>;
91 enable-method = "psci"
92 cpu-idle-states = <&PE
93
94
95
96
97 capacity-dmips-mhz = <
98 #cooling-cells = <2>;
99 next-level-cache = <&L
100 };
101
102 CPU3: cpu@103 {
103 device_type = "cpu";
104 compatible = "arm,cort
105 reg = <0x0 0x103>;
106 enable-method = "psci"
107 cpu-idle-states = <&PE
108
109
110
111
112 capacity-dmips-mhz = <
113 #cooling-cells = <2>;
114 next-level-cache = <&L
115 };
116
117 CPU4: cpu@0 {
118 device_type = "cpu";
119 compatible = "arm,cort
120 reg = <0x0 0x0>;
121 enable-method = "psci"
122 cpu-idle-states = <&PW
123
124
125
126
127 capacity-dmips-mhz = <
128 #cooling-cells = <2>;
129 next-level-cache = <&L
130 L2_0: l2-cache {
131 compatible = "
132 cache-level =
133 cache-unified;
134 };
135 };
136
137 CPU5: cpu@1 {
138 device_type = "cpu";
139 compatible = "arm,cort
140 reg = <0x0 0x1>;
141 enable-method = "psci"
142 cpu-idle-states = <&PW
143
144
145
146
147 capacity-dmips-mhz = <
148 #cooling-cells = <2>;
149 next-level-cache = <&L
150 };
151
152 CPU6: cpu@2 {
153 device_type = "cpu";
154 compatible = "arm,cort
155 reg = <0x0 0x2>;
156 enable-method = "psci"
157 cpu-idle-states = <&PW
158
159
160
161
162 capacity-dmips-mhz = <
163 #cooling-cells = <2>;
164 next-level-cache = <&L
165 };
166
167 CPU7: cpu@3 {
168 device_type = "cpu";
169 compatible = "arm,cort
170 reg = <0x0 0x3>;
171 enable-method = "psci"
172 cpu-idle-states = <&PW
173
174
175
176
177 capacity-dmips-mhz = <
178 #cooling-cells = <2>;
179 next-level-cache = <&L
180 };
181
182 cpu-map {
183 cluster0 {
184 core0 {
185 cpu =
186 };
187
188 core1 {
189 cpu =
190 };
191
192 core2 {
193 cpu =
194 };
195
196 core3 {
197 cpu =
198 };
199 };
200
201 cluster1 {
202 core0 {
203 cpu =
204 };
205
206 core1 {
207 cpu =
208 };
209
210 core2 {
211 cpu =
212 };
213
214 core3 {
215 cpu =
216 };
217 };
218 };
219
220 idle-states {
221 entry-method = "psci";
222
223 PWR_CPU_SLEEP_0: cpu-s
224 compatible = "
225 idle-state-nam
226 arm,psci-suspe
227 entry-latency-
228 exit-latency-u
229 min-residency-
230 };
231
232 PWR_CPU_SLEEP_1: cpu-s
233 compatible = "
234 idle-state-nam
235 arm,psci-suspe
236 entry-latency-
237 exit-latency-u
238 min-residency-
239 local-timer-st
240 };
241
242 PERF_CPU_SLEEP_0: cpu-
243 compatible = "
244 idle-state-nam
245 arm,psci-suspe
246 entry-latency-
247 exit-latency-u
248 min-residency-
249 };
250
251 PERF_CPU_SLEEP_1: cpu-
252 compatible = "
253 idle-state-nam
254 arm,psci-suspe
255 entry-latency-
256 exit-latency-u
257 min-residency-
258 local-timer-st
259 };
260
261 PWR_CLUSTER_SLEEP_0: c
262 compatible = "
263 idle-state-nam
264 arm,psci-suspe
265 entry-latency-
266 exit-latency-u
267 min-residency-
268 local-timer-st
269 };
270
271 PWR_CLUSTER_SLEEP_1: c
272 compatible = "
273 idle-state-nam
274 arm,psci-suspe
275 entry-latency-
276 exit-latency-u
277 min-residency-
278 local-timer-st
279 };
280
281 PWR_CLUSTER_SLEEP_2: c
282 compatible = "
283 idle-state-nam
284 arm,psci-suspe
285 entry-latency-
286 exit-latency-u
287 min-residency-
288 local-timer-st
289 };
290
291 PERF_CLUSTER_SLEEP_0:
292 compatible = "
293 idle-state-nam
294 arm,psci-suspe
295 entry-latency-
296 exit-latency-u
297 min-residency-
298 local-timer-st
299 };
300
301 PERF_CLUSTER_SLEEP_1:
302 compatible = "
303 idle-state-nam
304 arm,psci-suspe
305 entry-latency-
306 exit-latency-u
307 min-residency-
308 local-timer-st
309 };
310
311 PERF_CLUSTER_SLEEP_2:
312 compatible = "
313 idle-state-nam
314 arm,psci-suspe
315 entry-latency-
316 exit-latency-u
317 min-residency-
318 local-timer-st
319 };
320 };
321 };
322
323 firmware {
324 scm {
325 compatible = "qcom,scm
326 };
327 };
328
329 memory@80000000 {
330 device_type = "memory";
331 /* We expect the bootloader to
332 reg = <0x0 0x80000000 0x0 0x0>
333 };
334
335 dsi_opp_table: opp-table-dsi {
336 compatible = "operating-points
337
338 opp-131250000 {
339 opp-hz = /bits/ 64 <13
340 required-opps = <&rpmp
341 };
342
343 opp-210000000 {
344 opp-hz = /bits/ 64 <21
345 required-opps = <&rpmp
346 };
347
348 opp-262500000 {
349 opp-hz = /bits/ 64 <26
350 required-opps = <&rpmp
351 };
352 };
353
354 pmu {
355 compatible = "arm,armv8-pmuv3"
356 interrupts = <GIC_PPI 6 IRQ_TY
357 };
358
359 psci {
360 compatible = "arm,psci-1.0";
361 method = "smc";
362 };
363
364 rpm: remoteproc {
365 compatible = "qcom,sdm660-rpm-
366
367 glink-edge {
368 compatible = "qcom,gli
369
370 interrupts = <GIC_SPI
371 qcom,rpm-msg-ram = <&r
372 mboxes = <&apcs_glb 0>
373
374 rpm_requests: rpm-requ
375 compatible = "
376 qcom,glink-cha
377
378 rpmcc: clock-c
379 compat
380 #clock
381 };
382
383 rpmpd: power-c
384 compat
385 #power
386 operat
387
388 rpmpd_
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426 };
427 };
428 };
429 };
430 };
431
432 reserved-memory {
433 #address-cells = <2>;
434 #size-cells = <2>;
435 ranges;
436
437 wlan_msa_guard: wlan-msa-guard
438 reg = <0x0 0x85600000
439 no-map;
440 };
441
442 wlan_msa_mem: wlan-msa-mem@857
443 reg = <0x0 0x85700000
444 no-map;
445 };
446
447 qhee_code: qhee-code@85800000
448 reg = <0x0 0x85800000
449 no-map;
450 };
451
452 rmtfs_mem: memory@85e00000 {
453 compatible = "qcom,rmt
454 reg = <0x0 0x85e00000
455 no-map;
456
457 qcom,client-id = <1>;
458 qcom,vmid = <QCOM_SCM_
459 };
460
461 smem_region: smem-mem@86000000
462 reg = <0 0x86000000 0
463 no-map;
464 };
465
466 tz_mem: memory@86200000 {
467 reg = <0x0 0x86200000
468 no-map;
469 };
470
471 mpss_region: mpss@8ac00000 {
472 reg = <0x0 0x8ac00000
473 no-map;
474 };
475
476 adsp_region: adsp@92a00000 {
477 reg = <0x0 0x92a00000
478 no-map;
479 };
480
481 mba_region: mba@94800000 {
482 reg = <0x0 0x94800000
483 no-map;
484 };
485
486 buffer_mem: tzbuffer@94a00000
487 reg = <0x0 0x94a00000
488 no-map;
489 };
490
491 venus_region: venus@9f800000 {
492 reg = <0x0 0x9f800000
493 no-map;
494 };
495
496 adsp_mem: adsp-region@f6000000
497 reg = <0x0 0xf6000000
498 no-map;
499 };
500
501 qseecom_mem: qseecom-region@f6
502 reg = <0x0 0xf6800000
503 no-map;
504 };
505
506 zap_shader_region: gpu@fed0000
507 compatible = "shared-d
508 reg = <0x0 0xfed00000
509 no-map;
510 };
511 };
512
513 smem: smem {
514 compatible = "qcom,smem";
515 memory-region = <&smem_region>
516 hwlocks = <&tcsr_mutex 3>;
517 };
518
519 smp2p-adsp {
520 compatible = "qcom,smp2p";
521 qcom,smem = <443>, <429>;
522 interrupts = <GIC_SPI 158 IRQ_
523 mboxes = <&apcs_glb 10>;
524 qcom,local-pid = <0>;
525 qcom,remote-pid = <2>;
526
527 adsp_smp2p_out: master-kernel
528 qcom,entry-name = "mas
529 #qcom,smem-state-cells
530 };
531
532 adsp_smp2p_in: slave-kernel {
533 qcom,entry-name = "sla
534 interrupt-controller;
535 #interrupt-cells = <2>
536 };
537 };
538
539 smp2p-mpss {
540 compatible = "qcom,smp2p";
541 qcom,smem = <435>, <428>;
542 interrupts = <GIC_SPI 451 IRQ_
543 mboxes = <&apcs_glb 14>;
544 qcom,local-pid = <0>;
545 qcom,remote-pid = <1>;
546
547 modem_smp2p_out: master-kernel
548 qcom,entry-name = "mas
549 #qcom,smem-state-cells
550 };
551
552 modem_smp2p_in: slave-kernel {
553 qcom,entry-name = "sla
554 interrupt-controller;
555 #interrupt-cells = <2>
556 };
557 };
558
559 soc@0 {
560 #address-cells = <1>;
561 #size-cells = <1>;
562 ranges = <0 0 0 0xffffffff>;
563 compatible = "simple-bus";
564
565 gcc: clock-controller@100000 {
566 compatible = "qcom,gcc
567 #clock-cells = <1>;
568 #reset-cells = <1>;
569 #power-domain-cells =
570 reg = <0x00100000 0x94
571
572 clock-names = "xo", "s
573 clocks = <&xo_board>,
574 <&slee
575 };
576
577 rpm_msg_ram: sram@778000 {
578 compatible = "qcom,rpm
579 reg = <0x00778000 0x70
580 };
581
582 qfprom: qfprom@780000 {
583 compatible = "qcom,sdm
584 reg = <0x00780000 0x62
585 #address-cells = <1>;
586 #size-cells = <1>;
587
588 qusb2_hstx_trim: hstx-
589 reg = <0x243 0
590 bits = <1 3>;
591 };
592
593 gpu_speed_bin: gpu-spe
594 reg = <0x41a2
595 bits = <5 7>;
596 };
597 };
598
599 rng: rng@793000 {
600 compatible = "qcom,prn
601 reg = <0x00793000 0x10
602 clocks = <&gcc GCC_PRN
603 clock-names = "core";
604 };
605
606 bimc: interconnect@1008000 {
607 compatible = "qcom,sdm
608 reg = <0x01008000 0x78
609 #interconnect-cells =
610 };
611
612 restart@10ac000 {
613 compatible = "qcom,psh
614 reg = <0x010ac000 0x4>
615 };
616
617 cnoc: interconnect@1500000 {
618 compatible = "qcom,sdm
619 reg = <0x01500000 0x10
620 #interconnect-cells =
621 };
622
623 snoc: interconnect@1626000 {
624 compatible = "qcom,sdm
625 reg = <0x01626000 0x70
626 #interconnect-cells =
627 };
628
629 anoc2_smmu: iommu@16c0000 {
630 compatible = "qcom,sdm
631 reg = <0x016c0000 0x40
632 #global-interrupts = <
633 #iommu-cells = <1>;
634
635 interrupts =
636 <GIC_SPI 229 I
637 <GIC_SPI 231 I
638
639 <GIC_SPI 373 I
640 <GIC_SPI 374 I
641 <GIC_SPI 375 I
642 <GIC_SPI 376 I
643 <GIC_SPI 377 I
644 <GIC_SPI 378 I
645 <GIC_SPI 462 I
646 <GIC_SPI 463 I
647 <GIC_SPI 464 I
648 <GIC_SPI 465 I
649 <GIC_SPI 466 I
650 <GIC_SPI 467 I
651 <GIC_SPI 353 I
652 <GIC_SPI 354 I
653 <GIC_SPI 355 I
654 <GIC_SPI 356 I
655 <GIC_SPI 357 I
656 <GIC_SPI 358 I
657 <GIC_SPI 359 I
658 <GIC_SPI 360 I
659 <GIC_SPI 442 I
660 <GIC_SPI 443 I
661 <GIC_SPI 444 I
662 <GIC_SPI 447 I
663 <GIC_SPI 468 I
664 <GIC_SPI 469 I
665 <GIC_SPI 472 I
666 <GIC_SPI 473 I
667 <GIC_SPI 474 I
668
669 status = "disabled";
670 };
671
672 a2noc: interconnect@1704000 {
673 compatible = "qcom,sdm
674 reg = <0x01704000 0xc1
675 #interconnect-cells =
676 clock-names = "ipa",
677 "ufs_axi
678 "aggre2_
679 "aggre2_
680 "cfg_noc
681 clocks = <&rpmcc RPM_S
682 <&gcc GCC_UFS
683 <&gcc GCC_AGG
684 <&gcc GCC_AGG
685 <&gcc GCC_CFG
686 };
687
688 mnoc: interconnect@1745000 {
689 compatible = "qcom,sdm
690 reg = <0x01745000 0xa0
691 #interconnect-cells =
692 clock-names = "iface";
693 clocks = <&mmcc AHB_CL
694 };
695
696 tsens: thermal-sensor@10ae000
697 compatible = "qcom,sdm
698 reg = <0x010ae000 0x10
699 <0x010ad000
700 #qcom,sensors = <12>;
701 interrupts = <GIC_SPI
702 <GIC_
703 interrupt-names = "upl
704 #thermal-sensor-cells
705 };
706
707 tcsr_mutex: hwlock@1f40000 {
708 compatible = "qcom,tcs
709 reg = <0x01f40000 0x20
710 #hwlock-cells = <1>;
711 };
712
713 tcsr_regs_1: syscon@1f60000 {
714 compatible = "qcom,sdm
715 reg = <0x01f60000 0x20
716 };
717
718 tlmm: pinctrl@3100000 {
719 compatible = "qcom,sdm
720 reg = <0x03100000 0x40
721 <0x03500000
722 <0x03900000
723 reg-names = "south", "
724 interrupts = <GIC_SPI
725 gpio-controller;
726 gpio-ranges = <&tlmm 0
727 #gpio-cells = <2>;
728 interrupt-controller;
729 #interrupt-cells = <2>
730
731 blsp1_uart1_default: b
732 pins = "gpio0"
733 function = "bl
734 drive-strength
735 bias-disable;
736 };
737
738 blsp1_uart1_sleep: bls
739 pins = "gpio0"
740 function = "gp
741 drive-strength
742 bias-disable;
743 };
744
745 blsp1_uart2_default: b
746 pins = "gpio4"
747 function = "bl
748 drive-strength
749 bias-disable;
750 };
751
752 blsp2_uart1_default: b
753 tx-rts-pins {
754 pins =
755 functi
756 drive-
757 bias-d
758 };
759
760 rx-pins {
761 /*
762 * Avo
763 * is
764 */
765 pins =
766 functi
767 drive-
768 bias-p
769 };
770
771 cts-pins {
772 /* Mat
773 pins =
774 functi
775 drive-
776 bias-p
777 };
778 };
779
780 blsp2_uart1_sleep: bls
781 tx-pins {
782 pins =
783 functi
784 drive-
785 bias-p
786 };
787
788 rx-cts-rts-pin
789 pins =
790 functi
791 drive-
792 bias-d
793 };
794 };
795
796 i2c1_default: i2c1-def
797 pins = "gpio2"
798 function = "bl
799 drive-strength
800 bias-disable;
801 };
802
803 i2c1_sleep: i2c1-sleep
804 pins = "gpio2"
805 function = "bl
806 drive-strength
807 bias-pull-up;
808 };
809
810 i2c2_default: i2c2-def
811 pins = "gpio6"
812 function = "bl
813 drive-strength
814 bias-disable;
815 };
816
817 i2c2_sleep: i2c2-sleep
818 pins = "gpio6"
819 function = "bl
820 drive-strength
821 bias-pull-up;
822 };
823
824 i2c3_default: i2c3-def
825 pins = "gpio10
826 function = "bl
827 drive-strength
828 bias-disable;
829 };
830
831 i2c3_sleep: i2c3-sleep
832 pins = "gpio10
833 function = "bl
834 drive-strength
835 bias-pull-up;
836 };
837
838 i2c4_default: i2c4-def
839 pins = "gpio14
840 function = "bl
841 drive-strength
842 bias-disable;
843 };
844
845 i2c4_sleep: i2c4-sleep
846 pins = "gpio14
847 function = "bl
848 drive-strength
849 bias-pull-up;
850 };
851
852 i2c5_default: i2c5-def
853 pins = "gpio18
854 function = "bl
855 drive-strength
856 bias-disable;
857 };
858
859 i2c5_sleep: i2c5-sleep
860 pins = "gpio18
861 function = "bl
862 drive-strength
863 bias-pull-up;
864 };
865
866 i2c6_default: i2c6-def
867 pins = "gpio22
868 function = "bl
869 drive-strength
870 bias-disable;
871 };
872
873 i2c6_sleep: i2c6-sleep
874 pins = "gpio22
875 function = "bl
876 drive-strength
877 bias-pull-up;
878 };
879
880 i2c7_default: i2c7-def
881 pins = "gpio26
882 function = "bl
883 drive-strength
884 bias-disable;
885 };
886
887 i2c7_sleep: i2c7-sleep
888 pins = "gpio26
889 function = "bl
890 drive-strength
891 bias-pull-up;
892 };
893
894 i2c8_default: i2c8-def
895 pins = "gpio30
896 function = "bl
897 drive-strength
898 bias-disable;
899 };
900
901 i2c8_sleep: i2c8-sleep
902 pins = "gpio30
903 function = "bl
904 drive-strength
905 bias-pull-up;
906 };
907
908 cci0_default: cci0-def
909 pins = "gpio36
910 function = "cc
911 bias-pull-up;
912 drive-strength
913 };
914
915 cci1_default: cci1-def
916 pins = "gpio38
917 function = "cc
918 bias-pull-up;
919 drive-strength
920 };
921
922 sdc1_state_on: sdc1-on
923 clk-pins {
924 pins =
925 bias-d
926 drive-
927 };
928
929 cmd-pins {
930 pins =
931 bias-p
932 drive-
933 };
934
935 data-pins {
936 pins =
937 bias-p
938 drive-
939 };
940
941 rclk-pins {
942 pins =
943 bias-p
944 };
945 };
946
947 sdc1_state_off: sdc1-o
948 clk-pins {
949 pins =
950 bias-d
951 drive-
952 };
953
954 cmd-pins {
955 pins =
956 bias-p
957 drive-
958 };
959
960 data-pins {
961 pins =
962 bias-p
963 drive-
964 };
965
966 rclk-pins {
967 pins =
968 bias-p
969 };
970 };
971
972 sdc2_state_on: sdc2-on
973 clk-pins {
974 pins =
975 bias-d
976 drive-
977 };
978
979 cmd-pins {
980 pins =
981 bias-p
982 drive-
983 };
984
985 data-pins {
986 pins =
987 bias-p
988 drive-
989 };
990 };
991
992 sdc2_state_off: sdc2-o
993 clk-pins {
994 pins =
995 bias-d
996 drive-
997 };
998
999 cmd-pins {
1000 pins
1001 bias-
1002 drive
1003 };
1004
1005 data-pins {
1006 pins
1007 bias-
1008 drive
1009 };
1010 };
1011 };
1012
1013 remoteproc_mss: remoteproc@40
1014 compatible = "qcom,sd
1015 reg = <0x04080000 0x1
1016 reg-names = "qdsp6",
1017
1018 interrupts-extended =
1019
1020
1021
1022
1023
1024 interrupt-names = "wd
1025 "fa
1026 "re
1027 "ha
1028 "st
1029 "sh
1030
1031 clocks = <&gcc GCC_MS
1032 <&gcc GCC_BI
1033 <&gcc GCC_BO
1034 <&gcc GPLL0_
1035 <&gcc GCC_MS
1036 <&gcc GCC_MS
1037 <&rpmcc RPM_
1038 <&rpmcc RPM_
1039 clock-names = "iface"
1040 "bus",
1041 "mem",
1042 "gpll0_
1043 "snoc_a
1044 "mnoc_a
1045 "qdss",
1046 "xo";
1047
1048 qcom,smem-states = <&
1049 qcom,smem-state-names
1050
1051 resets = <&gcc GCC_MS
1052 reset-names = "mss_re
1053
1054 qcom,halt-regs = <&tc
1055
1056 power-domains = <&rpm
1057 <&rpm
1058 power-domain-names =
1059
1060 memory-region = <&mba
1061
1062 status = "disabled";
1063
1064 glink-edge {
1065 interrupts =
1066 label = "mode
1067 qcom,remote-p
1068 mboxes = <&ap
1069 };
1070 };
1071
1072 adreno_gpu: gpu@5000000 {
1073 compatible = "qcom,ad
1074
1075 reg = <0x05000000 0x4
1076 reg-names = "kgsl_3d0
1077
1078 interrupts = <GIC_SPI
1079
1080 clocks = <&gcc GCC_GP
1081 <&gpucc GPUCC
1082 <&gcc GCC_BIM
1083 <&gcc GCC_GPU
1084 <&gpucc GPUCC
1085 <&gpucc GPUCC
1086
1087 clock-names = "iface"
1088 "rbbmtimer",
1089 "mem",
1090 "mem_iface",
1091 "rbcpr",
1092 "core";
1093
1094 power-domains = <&rpm
1095 iommus = <&kgsl_smmu
1096
1097 nvmem-cells = <&gpu_s
1098 nvmem-cell-names = "s
1099
1100 interconnects = <&bim
1101 interconnect-names =
1102
1103 operating-points-v2 =
1104 #cooling-cells = <2>;
1105
1106 status = "disabled";
1107
1108 gpu_sdm630_opp_table:
1109 compatible =
1110 opp-775000000
1111 opp-h
1112 opp-l
1113 opp-p
1114 opp-s
1115 };
1116 opp-647000000
1117 opp-h
1118 opp-l
1119 opp-p
1120 opp-s
1121 };
1122 opp-588000000
1123 opp-h
1124 opp-l
1125 opp-p
1126 opp-s
1127 };
1128 opp-465000000
1129 opp-h
1130 opp-l
1131 opp-p
1132 opp-s
1133 };
1134 opp-370000000
1135 opp-h
1136 opp-l
1137 opp-p
1138 opp-s
1139 };
1140 opp-240000000
1141 opp-h
1142 opp-l
1143 opp-p
1144 opp-s
1145 };
1146 opp-160000000
1147 opp-h
1148 opp-l
1149 opp-p
1150 opp-s
1151 };
1152 };
1153 };
1154
1155 kgsl_smmu: iommu@5040000 {
1156 compatible = "qcom,sd
1157 "qcom,ad
1158 reg = <0x05040000 0x1
1159
1160 /*
1161 * GX GDSC parent is
1162 * but we need both u
1163 * need to manage the
1164 * Enable CX/GX GDSCs
1165 * RPM Power Domain i
1166 */
1167 power-domains = <&gpu
1168 clocks = <&gcc GCC_GP
1169 <&gcc GCC_BI
1170 <&gcc GCC_GP
1171 clock-names = "iface"
1172 "mem",
1173 "mem_if
1174 #global-interrupts =
1175 #iommu-cells = <1>;
1176
1177 interrupts =
1178 <GIC_SPI 229
1179 <GIC_SPI 231
1180
1181 <GIC_SPI 329
1182 <GIC_SPI 330
1183 <GIC_SPI 331
1184 <GIC_SPI 332
1185 <GIC_SPI 116
1186 <GIC_SPI 117
1187 <GIC_SPI 349
1188 <GIC_SPI 350
1189
1190 status = "disabled";
1191 };
1192
1193 gpucc: clock-controller@50650
1194 compatible = "qcom,gp
1195 #clock-cells = <1>;
1196 #reset-cells = <1>;
1197 #power-domain-cells =
1198 reg = <0x05065000 0x9
1199
1200 clocks = <&xo_board>,
1201 <&gcc GCC_GP
1202 <&gcc GCC_GP
1203 clock-names = "xo",
1204 "gcc_gp
1205 "gcc_gp
1206 status = "disabled";
1207 };
1208
1209 lpass_smmu: iommu@5100000 {
1210 compatible = "qcom,sd
1211 reg = <0x05100000 0x4
1212 #iommu-cells = <1>;
1213
1214 #global-interrupts =
1215 interrupts =
1216 <GIC_SPI 229
1217 <GIC_SPI 231
1218
1219 <GIC_SPI 226
1220 <GIC_SPI 393
1221 <GIC_SPI 394
1222 <GIC_SPI 395
1223 <GIC_SPI 396
1224 <GIC_SPI 397
1225 <GIC_SPI 398
1226 <GIC_SPI 399
1227 <GIC_SPI 400
1228 <GIC_SPI 401
1229 <GIC_SPI 402
1230 <GIC_SPI 403
1231 <GIC_SPI 137
1232 <GIC_SPI 224
1233 <GIC_SPI 225
1234 <GIC_SPI 310
1235 <GIC_SPI 404
1236
1237 status = "disabled";
1238 };
1239
1240 sram@290000 {
1241 compatible = "qcom,rp
1242 reg = <0x00290000 0x1
1243 };
1244
1245 spmi_bus: spmi@800f000 {
1246 compatible = "qcom,sp
1247 reg = <0x0800f000 0x1
1248 <0x08400000 0x1
1249 <0x09400000 0x1
1250 <0x0a400000 0x2
1251 <0x0800a000 0x3
1252 reg-names = "core", "
1253 interrupt-names = "pe
1254 interrupts = <GIC_SPI
1255 qcom,ee = <0>;
1256 qcom,channel = <0>;
1257 #address-cells = <2>;
1258 #size-cells = <0>;
1259 interrupt-controller;
1260 #interrupt-cells = <4
1261 };
1262
1263 usb3: usb@a8f8800 {
1264 compatible = "qcom,sd
1265 reg = <0x0a8f8800 0x4
1266 status = "disabled";
1267 #address-cells = <1>;
1268 #size-cells = <1>;
1269 ranges;
1270
1271 clocks = <&gcc GCC_CF
1272 <&gcc GCC_US
1273 <&gcc GCC_AG
1274 <&gcc GCC_US
1275 <&gcc GCC_US
1276 clock-names = "cfg_no
1277 "core",
1278 "iface"
1279 "sleep"
1280 "mock_u
1281
1282 assigned-clocks = <&g
1283 <&g
1284 assigned-clock-rates
1285
1286 interrupts = <GIC_SPI
1287 <GIC_SPI
1288 <GIC_SPI
1289 <GIC_SPI
1290 interrupt-names = "pw
1291 "qu
1292 "hs
1293 "ss
1294
1295 power-domains = <&gcc
1296
1297 resets = <&gcc GCC_US
1298
1299 usb3_dwc3: usb@a80000
1300 compatible =
1301 reg = <0x0a80
1302 interrupts =
1303 snps,dis_u2_s
1304 snps,dis_enbl
1305 snps,parkmode
1306
1307 phys = <&qusb
1308 phy-names = "
1309 snps,hird-thr
1310 };
1311 };
1312
1313 usb3_qmpphy: phy@c010000 {
1314 compatible = "qcom,sd
1315 reg = <0x0c010000 0x1
1316
1317 clocks = <&gcc GCC_US
1318 <&gcc GCC_US
1319 <&gcc GCC_US
1320 <&gcc GCC_US
1321 clock-names = "aux",
1322 "ref",
1323 "cfg_ah
1324 "pipe";
1325 clock-output-names =
1326 #clock-cells = <0>;
1327 #phy-cells = <0>;
1328
1329 resets = <&gcc GCC_US
1330 <&gcc GCC_US
1331 reset-names = "phy",
1332 "phy_ph
1333
1334 qcom,tcsr-reg = <&tcs
1335
1336 status = "disabled";
1337 };
1338
1339 qusb2phy0: phy@c012000 {
1340 compatible = "qcom,sd
1341 reg = <0x0c012000 0x1
1342 #phy-cells = <0>;
1343
1344 clocks = <&gcc GCC_US
1345 <&gcc GCC_RX
1346 clock-names = "cfg_ah
1347
1348 resets = <&gcc GCC_QU
1349 nvmem-cells = <&qusb2
1350 status = "disabled";
1351 };
1352
1353 qusb2phy1: phy@c014000 {
1354 compatible = "qcom,sd
1355 reg = <0x0c014000 0x1
1356 #phy-cells = <0>;
1357
1358 clocks = <&gcc GCC_US
1359 <&gcc GCC_RX
1360 clock-names = "cfg_ah
1361
1362 resets = <&gcc GCC_QU
1363 nvmem-cells = <&qusb2
1364 status = "disabled";
1365 };
1366
1367 sdhc_2: mmc@c084000 {
1368 compatible = "qcom,sd
1369 reg = <0x0c084000 0x1
1370 reg-names = "hc";
1371
1372 interrupts = <GIC_SPI
1373 <GIC_
1374 interrupt-names = "hc
1375
1376 bus-width = <4>;
1377
1378 clocks = <&gcc GCC_SD
1379 <&gcc
1380 <&xo_
1381 clock-names = "iface"
1382
1383
1384 interconnects = <&a2n
1385 <&gno
1386 interconnect-names =
1387 operating-points-v2 =
1388
1389 pinctrl-names = "defa
1390 pinctrl-0 = <&sdc2_st
1391 pinctrl-1 = <&sdc2_st
1392 power-domains = <&rpm
1393
1394 status = "disabled";
1395
1396 sdhc2_opp_table: opp-
1397 compatible =
1398
1399 opp-50000000
1400 opp-h
1401 requi
1402 opp-p
1403 opp-a
1404 };
1405 opp-10000000
1406 opp-h
1407 requi
1408 opp-p
1409 opp-a
1410 };
1411 opp-20000000
1412 opp-h
1413 requi
1414 opp-p
1415 opp-a
1416 };
1417 };
1418 };
1419
1420 sdhc_1: mmc@c0c4000 {
1421 compatible = "qcom,sd
1422 reg = <0x0c0c4000 0x1
1423 <0x0c0c5000 0x1
1424 <0x0c0c8000 0x8
1425 reg-names = "hc", "cq
1426
1427 interrupts = <GIC_SPI
1428 <GIC_
1429 interrupt-names = "hc
1430
1431 clocks = <&gcc GCC_SD
1432 <&gcc GCC_SD
1433 <&xo_board>,
1434 <&gcc GCC_SD
1435 clock-names = "iface"
1436
1437 interconnects = <&a2n
1438 <&gno
1439 interconnect-names =
1440 operating-points-v2 =
1441 pinctrl-names = "defa
1442 pinctrl-0 = <&sdc1_st
1443 pinctrl-1 = <&sdc1_st
1444 power-domains = <&rpm
1445
1446 bus-width = <8>;
1447 non-removable;
1448
1449 status = "disabled";
1450
1451 sdhc1_opp_table: opp-
1452 compatible =
1453
1454 opp-50000000
1455 opp-h
1456 requi
1457 opp-p
1458 opp-a
1459 };
1460 opp-100000000
1461 opp-h
1462 requi
1463 opp-p
1464 opp-a
1465 };
1466 opp-384000000
1467 opp-h
1468 requi
1469 opp-p
1470 opp-a
1471 };
1472 };
1473 };
1474
1475 usb2: usb@c2f8800 {
1476 compatible = "qcom,sd
1477 reg = <0x0c2f8800 0x4
1478 status = "disabled";
1479 #address-cells = <1>;
1480 #size-cells = <1>;
1481 ranges;
1482
1483 clocks = <&gcc GCC_CF
1484 <&gcc GCC_US
1485 <&gcc GCC_US
1486 <&gcc GCC_US
1487 clock-names = "cfg_no
1488 "sleep"
1489
1490 assigned-clocks = <&g
1491 <&g
1492 assigned-clock-rates
1493
1494 interrupts = <GIC_SPI
1495 <GIC_SPI
1496 <GIC_SPI
1497 interrupt-names = "pw
1498 "qu
1499 "hs
1500
1501 qcom,select-utmi-as-p
1502
1503 resets = <&gcc GCC_US
1504
1505 usb2_dwc3: usb@c20000
1506 compatible =
1507 reg = <0x0c20
1508 interrupts =
1509 snps,dis_u2_s
1510 snps,dis_enbl
1511
1512 /* This is th
1513 maximum-speed
1514 phys = <&qusb
1515 phy-names = "
1516 snps,hird-thr
1517 };
1518 };
1519
1520 mmcc: clock-controller@c8c000
1521 compatible = "qcom,mm
1522 reg = <0x0c8c0000 0x4
1523 #clock-cells = <1>;
1524 #reset-cells = <1>;
1525 #power-domain-cells =
1526 clock-names = "xo",
1527 "slee
1528 "gpll
1529 "gpll
1530 "dsi0
1531 "dsi0
1532 "dsi1
1533 "dsi1
1534 "dp_l
1535 "dp_v
1536 clocks = <&rpmcc RPM_
1537 <&sle
1538 <&gcc
1539 <&gcc
1540 <&mds
1541 <&mds
1542 <0>,
1543 <0>,
1544 <0>,
1545 <0>;
1546 };
1547
1548 mdss: display-subsystem@c9000
1549 compatible = "qcom,md
1550 reg = <0x0c900000 0x1
1551 <0x0c9b0000 0x1
1552 reg-names = "mdss_phy
1553
1554 power-domains = <&mmc
1555
1556 clocks = <&mmcc MDSS_
1557 <&mmcc MDSS_
1558 <&mmcc MDSS_
1559 <&mmcc MDSS_
1560 clock-names = "iface"
1561 "bus",
1562 "vsync"
1563 "core";
1564
1565 interrupts = <GIC_SPI
1566
1567 interrupt-controller;
1568 #interrupt-cells = <1
1569
1570 #address-cells = <1>;
1571 #size-cells = <1>;
1572 ranges;
1573 status = "disabled";
1574
1575 mdp: display-controll
1576 compatible =
1577 reg = <0x0c90
1578 reg-names = "
1579
1580 interrupt-par
1581 interrupts =
1582
1583 assigned-cloc
1584
1585 assigned-cloc
1586
1587 clocks = <&mm
1588 <&mm
1589 <&mm
1590 <&mm
1591 clock-names =
1592
1593
1594
1595
1596 interconnects
1597
1598
1599 interconnect-
1600
1601
1602 iommus = <&mm
1603 operating-poi
1604 power-domains
1605
1606 ports {
1607 #addr
1608 #size
1609
1610 port@
1611
1612
1613
1614
1615 };
1616 };
1617
1618 mdp_opp_table
1619 compa
1620
1621 opp-1
1622
1623
1624
1625 };
1626 opp-2
1627
1628
1629
1630 };
1631 opp-3
1632
1633
1634
1635 };
1636 opp-3
1637
1638
1639
1640 };
1641 opp-4
1642
1643
1644
1645 };
1646 };
1647 };
1648
1649 mdss_dsi0: dsi@c99400
1650 compatible =
1651
1652 reg = <0x0c99
1653 reg-names = "
1654
1655 operating-poi
1656 power-domains
1657
1658 interrupt-par
1659 interrupts =
1660
1661 assigned-cloc
1662
1663 assigned-cloc
1664
1665
1666 clocks = <&mm
1667 <&mm
1668 <&mm
1669 <&mm
1670 <&mm
1671 <&mm
1672 <&mm
1673 <&mm
1674 <&mm
1675 clock-names =
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685 phys = <&mdss
1686
1687 status = "dis
1688
1689 ports {
1690 #addr
1691 #size
1692
1693 port@
1694
1695
1696
1697
1698 };
1699
1700 port@
1701
1702
1703
1704 };
1705 };
1706 };
1707
1708 mdss_dsi0_phy: phy@c9
1709 compatible =
1710 reg = <0x0c99
1711 <0x0c99
1712 <0x0c99
1713 reg-names = "
1714 "
1715 "
1716
1717 #clock-cells
1718 #phy-cells =
1719
1720 clocks = <&mm
1721 clock-names =
1722 status = "dis
1723 };
1724 };
1725
1726 blsp1_dma: dma-controller@c14
1727 compatible = "qcom,ba
1728 reg = <0x0c144000 0x1
1729 interrupts = <GIC_SPI
1730 clocks = <&gcc GCC_BL
1731 clock-names = "bam_cl
1732 #dma-cells = <1>;
1733 qcom,ee = <0>;
1734 qcom,controlled-remot
1735 num-channels = <18>;
1736 qcom,num-ees = <4>;
1737 };
1738
1739 blsp1_uart1: serial@c16f000 {
1740 compatible = "qcom,ms
1741 reg = <0x0c16f000 0x2
1742 interrupts = <GIC_SPI
1743 clocks = <&gcc GCC_BL
1744 <&gcc GCC_BL
1745 clock-names = "core",
1746 dmas = <&blsp1_dma 0>
1747 dma-names = "tx", "rx
1748 pinctrl-names = "defa
1749 pinctrl-0 = <&blsp1_u
1750 pinctrl-1 = <&blsp1_u
1751 status = "disabled";
1752 };
1753
1754 blsp1_uart2: serial@c170000 {
1755 compatible = "qcom,ms
1756 reg = <0x0c170000 0x1
1757 interrupts = <GIC_SPI
1758 clocks = <&gcc GCC_BL
1759 <&gcc GCC_BL
1760 clock-names = "core",
1761 dmas = <&blsp1_dma 2>
1762 dma-names = "tx", "rx
1763 pinctrl-names = "defa
1764 pinctrl-0 = <&blsp1_u
1765 status = "disabled";
1766 };
1767
1768 blsp_i2c1: i2c@c175000 {
1769 compatible = "qcom,i2
1770 reg = <0x0c175000 0x6
1771 interrupts = <GIC_SPI
1772
1773 clocks = <&gcc GCC_BL
1774 <&gcc
1775 clock-names = "core",
1776 clock-frequency = <40
1777 dmas = <&blsp1_dma 4>
1778 dma-names = "tx", "rx
1779
1780 pinctrl-names = "defa
1781 pinctrl-0 = <&i2c1_de
1782 pinctrl-1 = <&i2c1_sl
1783 #address-cells = <1>;
1784 #size-cells = <0>;
1785 status = "disabled";
1786 };
1787
1788 blsp_i2c2: i2c@c176000 {
1789 compatible = "qcom,i2
1790 reg = <0x0c176000 0x6
1791 interrupts = <GIC_SPI
1792
1793 clocks = <&gcc GCC_BL
1794 <&gcc GCC_BL
1795 clock-names = "core",
1796 clock-frequency = <40
1797 dmas = <&blsp1_dma 6>
1798 dma-names = "tx", "rx
1799
1800 pinctrl-names = "defa
1801 pinctrl-0 = <&i2c2_de
1802 pinctrl-1 = <&i2c2_sl
1803 #address-cells = <1>;
1804 #size-cells = <0>;
1805 status = "disabled";
1806 };
1807
1808 blsp_i2c3: i2c@c177000 {
1809 compatible = "qcom,i2
1810 reg = <0x0c177000 0x6
1811 interrupts = <GIC_SPI
1812
1813 clocks = <&gcc GCC_BL
1814 <&gcc GCC_BL
1815 clock-names = "core",
1816 clock-frequency = <40
1817 dmas = <&blsp1_dma 8>
1818 dma-names = "tx", "rx
1819
1820 pinctrl-names = "defa
1821 pinctrl-0 = <&i2c3_de
1822 pinctrl-1 = <&i2c3_sl
1823 #address-cells = <1>;
1824 #size-cells = <0>;
1825 status = "disabled";
1826 };
1827
1828 blsp_i2c4: i2c@c178000 {
1829 compatible = "qcom,i2
1830 reg = <0x0c178000 0x6
1831 interrupts = <GIC_SPI
1832
1833 clocks = <&gcc GCC_BL
1834 <&gcc GCC_BL
1835 clock-names = "core",
1836 clock-frequency = <40
1837 dmas = <&blsp1_dma 10
1838 dma-names = "tx", "rx
1839
1840 pinctrl-names = "defa
1841 pinctrl-0 = <&i2c4_de
1842 pinctrl-1 = <&i2c4_sl
1843 #address-cells = <1>;
1844 #size-cells = <0>;
1845 status = "disabled";
1846 };
1847
1848 blsp2_dma: dma-controller@c18
1849 compatible = "qcom,ba
1850 reg = <0x0c184000 0x1
1851 interrupts = <GIC_SPI
1852 clocks = <&gcc GCC_BL
1853 clock-names = "bam_cl
1854 #dma-cells = <1>;
1855 qcom,ee = <0>;
1856 qcom,controlled-remot
1857 num-channels = <18>;
1858 qcom,num-ees = <4>;
1859 };
1860
1861 blsp2_uart1: serial@c1af000 {
1862 compatible = "qcom,ms
1863 reg = <0x0c1af000 0x2
1864 interrupts = <GIC_SPI
1865 clocks = <&gcc GCC_BL
1866 <&gcc GCC_BL
1867 clock-names = "core",
1868 dmas = <&blsp2_dma 0>
1869 dma-names = "tx", "rx
1870 pinctrl-names = "defa
1871 pinctrl-0 = <&blsp2_u
1872 pinctrl-1 = <&blsp2_u
1873 status = "disabled";
1874 };
1875
1876 blsp_i2c5: i2c@c1b5000 {
1877 compatible = "qcom,i2
1878 reg = <0x0c1b5000 0x6
1879 interrupts = <GIC_SPI
1880
1881 clocks = <&gcc GCC_BL
1882 <&gcc GCC_BL
1883 clock-names = "core",
1884 clock-frequency = <40
1885 dmas = <&blsp2_dma 4>
1886 dma-names = "tx", "rx
1887
1888 pinctrl-names = "defa
1889 pinctrl-0 = <&i2c5_de
1890 pinctrl-1 = <&i2c5_sl
1891 #address-cells = <1>;
1892 #size-cells = <0>;
1893 status = "disabled";
1894 };
1895
1896 blsp_i2c6: i2c@c1b6000 {
1897 compatible = "qcom,i2
1898 reg = <0x0c1b6000 0x6
1899 interrupts = <GIC_SPI
1900
1901 clocks = <&gcc GCC_BL
1902 <&gcc GCC_BL
1903 clock-names = "core",
1904 clock-frequency = <40
1905 dmas = <&blsp2_dma 6>
1906 dma-names = "tx", "rx
1907
1908 pinctrl-names = "defa
1909 pinctrl-0 = <&i2c6_de
1910 pinctrl-1 = <&i2c6_sl
1911 #address-cells = <1>;
1912 #size-cells = <0>;
1913 status = "disabled";
1914 };
1915
1916 blsp_i2c7: i2c@c1b7000 {
1917 compatible = "qcom,i2
1918 reg = <0x0c1b7000 0x6
1919 interrupts = <GIC_SPI
1920
1921 clocks = <&gcc GCC_BL
1922 <&gcc GCC_BL
1923 clock-names = "core",
1924 clock-frequency = <40
1925 dmas = <&blsp2_dma 8>
1926 dma-names = "tx", "rx
1927
1928 pinctrl-names = "defa
1929 pinctrl-0 = <&i2c7_de
1930 pinctrl-1 = <&i2c7_sl
1931 #address-cells = <1>;
1932 #size-cells = <0>;
1933 status = "disabled";
1934 };
1935
1936 blsp_i2c8: i2c@c1b8000 {
1937 compatible = "qcom,i2
1938 reg = <0x0c1b8000 0x6
1939 interrupts = <GIC_SPI
1940
1941 clocks = <&gcc GCC_BL
1942 <&gcc GCC_BL
1943 clock-names = "core",
1944 clock-frequency = <40
1945 dmas = <&blsp2_dma 10
1946 dma-names = "tx", "rx
1947
1948 pinctrl-names = "defa
1949 pinctrl-0 = <&i2c8_de
1950 pinctrl-1 = <&i2c8_sl
1951 #address-cells = <1>;
1952 #size-cells = <0>;
1953 status = "disabled";
1954 };
1955
1956 sram@146bf000 {
1957 compatible = "qcom,sd
1958 reg = <0x146bf000 0x1
1959
1960 #address-cells = <1>;
1961 #size-cells = <1>;
1962
1963 ranges = <0 0x146bf00
1964
1965 pil-reloc@94c {
1966 compatible =
1967 reg = <0x94c
1968 };
1969 };
1970
1971 camss: camss@ca00020 {
1972 compatible = "qcom,sd
1973 reg = <0x0ca00020 0x1
1974 <0x0ca30000 0x1
1975 <0x0ca30400 0x1
1976 <0x0ca30800 0x1
1977 <0x0ca30c00 0x1
1978 <0x0c824000 0x1
1979 <0x0ca00120 0x4
1980 <0x0c825000 0x1
1981 <0x0ca00124 0x4
1982 <0x0c826000 0x1
1983 <0x0ca00128 0x4
1984 <0x0ca31000 0x5
1985 <0x0ca10000 0x1
1986 <0x0ca14000 0x1
1987 reg-names = "csi_clk_
1988 "csid0",
1989 "csid1",
1990 "csid2",
1991 "csid3",
1992 "csiphy0"
1993 "csiphy0_
1994 "csiphy1"
1995 "csiphy1_
1996 "csiphy2"
1997 "csiphy2_
1998 "ispif",
1999 "vfe0",
2000 "vfe1";
2001 interrupts = <GIC_SPI
2002 <GIC_SPI
2003 <GIC_SPI
2004 <GIC_SPI
2005 <GIC_SPI
2006 <GIC_SPI
2007 <GIC_SPI
2008 <GIC_SPI
2009 <GIC_SPI
2010 <GIC_SPI
2011 interrupt-names = "cs
2012 "cs
2013 "cs
2014 "cs
2015 "cs
2016 "cs
2017 "cs
2018 "is
2019 "vf
2020 "vf
2021 clocks = <&mmcc CAMSS
2022 <&mmcc CAMSS
2023 <&mmcc CAMSS
2024 <&mmcc CAMSS
2025 <&mmcc CAMSS
2026 <&mmcc CAMSS
2027 <&mmcc CAMSS
2028 <&mmcc CAMSS
2029 <&mmcc CAMSS
2030 <&mmcc CAMSS
2031 <&mmcc CAMSS
2032 <&mmcc CAMSS
2033 <&mmcc CAMSS
2034 <&mmcc CAMSS
2035 <&mmcc CAMSS
2036 <&mmcc CAMSS
2037 <&mmcc CAMSS
2038 <&mmcc CAMSS
2039 <&mmcc CAMSS
2040 <&mmcc CAMSS
2041 <&mmcc CAMSS
2042 <&mmcc CAMSS
2043 <&mmcc CAMSS
2044 <&mmcc CAMSS
2045 <&mmcc CAMSS
2046 <&mmcc CAMSS
2047 <&mmcc CAMSS
2048 <&mmcc CAMSS
2049 <&mmcc CSIPH
2050 <&mmcc CAMSS
2051 <&mmcc CAMSS
2052 <&mmcc CAMSS
2053 <&mmcc THROT
2054 <&mmcc CAMSS
2055 <&mmcc CAMSS
2056 <&mmcc CAMSS
2057 <&mmcc CAMSS
2058 <&mmcc CAMSS
2059 <&mmcc CAMSS
2060 <&mmcc CAMSS
2061 <&mmcc CAMSS
2062 <&mmcc CAMSS
2063 clock-names = "ahb",
2064 "cphy_c
2065 "cphy_c
2066 "cphy_c
2067 "cphy_c
2068 "csi0_a
2069 "csi0",
2070 "csi0_p
2071 "csi0_p
2072 "csi0_r
2073 "csi1_a
2074 "csi1",
2075 "csi1_p
2076 "csi1_p
2077 "csi1_r
2078 "csi2_a
2079 "csi2",
2080 "csi2_p
2081 "csi2_p
2082 "csi2_r
2083 "csi3_a
2084 "csi3",
2085 "csi3_p
2086 "csi3_p
2087 "csi3_r
2088 "csiphy
2089 "csiphy
2090 "csiphy
2091 "csiphy
2092 "csi_vf
2093 "csi_vf
2094 "ispif_
2095 "thrott
2096 "top_ah
2097 "vfe0_a
2098 "vfe0",
2099 "vfe0_s
2100 "vfe1_a
2101 "vfe1",
2102 "vfe1_s
2103 "vfe_ah
2104 "vfe_ax
2105 interconnects = <&mno
2106 interconnect-names =
2107 iommus = <&mmss_smmu
2108 <&mmss_smmu
2109 <&mmss_smmu
2110 <&mmss_smmu
2111 power-domains = <&mmc
2112 <&mmc
2113 status = "disabled";
2114
2115 ports {
2116 #address-cell
2117 #size-cells =
2118 };
2119 };
2120
2121 cci: cci@ca0c000 {
2122 compatible = "qcom,ms
2123 #address-cells = <1>;
2124 #size-cells = <0>;
2125 reg = <0x0ca0c000 0x1
2126 interrupts = <GIC_SPI
2127
2128 assigned-clocks = <&m
2129 <&m
2130 assigned-clock-rates
2131 clocks = <&mmcc CAMSS
2132 <&mmcc CAMSS
2133 <&mmcc CAMSS
2134 <&mmcc CAMSS
2135 clock-names = "camss_
2136 "cci_ah
2137 "cci",
2138 "camss_
2139
2140 pinctrl-names = "defa
2141 pinctrl-0 = <&cci0_de
2142 power-domains = <&mmc
2143 status = "disabled";
2144
2145 cci_i2c0: i2c-bus@0 {
2146 reg = <0>;
2147 clock-frequen
2148 #address-cell
2149 #size-cells =
2150 };
2151
2152 cci_i2c1: i2c-bus@1 {
2153 reg = <1>;
2154 clock-frequen
2155 #address-cell
2156 #size-cells =
2157 };
2158 };
2159
2160 venus: video-codec@cc00000 {
2161 compatible = "qcom,sd
2162 reg = <0x0cc00000 0xf
2163 clocks = <&mmcc VIDEO
2164 <&mmcc VIDEO
2165 <&mmcc VIDEO
2166 <&mmcc THROT
2167 clock-names = "core",
2168 interconnects = <&gno
2169 <&mno
2170 interconnect-names =
2171 interrupts = <GIC_SPI
2172 iommus = <&mmss_smmu
2173 <&mmss_smmu
2174 <&mmss_smmu
2175 <&mmss_smmu
2176 <&mmss_smmu
2177 <&mmss_smmu
2178 <&mmss_smmu
2179 <&mmss_smmu
2180 <&mmss_smmu
2181 <&mmss_smmu
2182 <&mmss_smmu
2183 <&mmss_smmu
2184 <&mmss_smmu
2185 <&mmss_smmu
2186 <&mmss_smmu
2187 <&mmss_smmu
2188 <&mmss_smmu
2189 <&mmss_smmu
2190 <&mmss_smmu
2191 <&mmss_smmu
2192 memory-region = <&ven
2193 power-domains = <&mmc
2194 status = "disabled";
2195
2196 video-decoder {
2197 compatible =
2198 clocks = <&mm
2199 clock-names =
2200 power-domains
2201 };
2202
2203 video-encoder {
2204 compatible =
2205 clocks = <&mm
2206 clock-names =
2207 power-domains
2208 };
2209 };
2210
2211 mmss_smmu: iommu@cd00000 {
2212 compatible = "qcom,sd
2213 reg = <0x0cd00000 0x4
2214
2215 clocks = <&mmcc MNOC_
2216 <&mmcc BIMC_
2217 <&mmcc BIMC_
2218 clock-names = "iface-
2219 "bus-sm
2220 #global-interrupts =
2221 #iommu-cells = <1>;
2222
2223 interrupts =
2224 <GIC_SPI 229
2225 <GIC_SPI 231
2226
2227 <GIC_SPI 263
2228 <GIC_SPI 266
2229 <GIC_SPI 267
2230 <GIC_SPI 268
2231 <GIC_SPI 244
2232 <GIC_SPI 245
2233 <GIC_SPI 247
2234 <GIC_SPI 248
2235 <GIC_SPI 249
2236 <GIC_SPI 250
2237 <GIC_SPI 251
2238 <GIC_SPI 252
2239 <GIC_SPI 253
2240 <GIC_SPI 254
2241 <GIC_SPI 255
2242 <GIC_SPI 256
2243 <GIC_SPI 260
2244 <GIC_SPI 261
2245 <GIC_SPI 262
2246 <GIC_SPI 272
2247 <GIC_SPI 273
2248 <GIC_SPI 274
2249 <GIC_SPI 275
2250 <GIC_SPI 276
2251
2252 status = "disabled";
2253 };
2254
2255 adsp_pil: remoteproc@15700000
2256 compatible = "qcom,sd
2257 reg = <0x15700000 0x4
2258
2259 interrupts-extended =
2260 <&intc GIC_SP
2261 <&adsp_smp2p_
2262 <&adsp_smp2p_
2263 <&adsp_smp2p_
2264 <&adsp_smp2p_
2265 interrupt-names = "wd
2266 "ha
2267
2268 clocks = <&rpmcc RPM_
2269 clock-names = "xo";
2270
2271 memory-region = <&ads
2272 power-domains = <&rpm
2273 power-domain-names =
2274
2275 qcom,smem-states = <&
2276 qcom,smem-state-names
2277
2278 glink-edge {
2279 interrupts =
2280
2281 label = "lpas
2282 mboxes = <&ap
2283 qcom,remote-p
2284
2285 apr {
2286 compa
2287 qcom,
2288 qcom,
2289 #addr
2290 #size
2291
2292 servi
2293
2294
2295 };
2296
2297 q6afe
2298
2299
2300
2301
2302
2303
2304
2305
2306 };
2307
2308 q6asm
2309
2310
2311
2312
2313
2314
2315
2316
2317
2318 };
2319
2320 q6adm
2321
2322
2323
2324
2325
2326
2327 };
2328 };
2329 };
2330 };
2331
2332 gnoc: interconnect@17900000 {
2333 compatible = "qcom,sd
2334 reg = <0x17900000 0xe
2335 #interconnect-cells =
2336 };
2337
2338 apcs_glb: mailbox@17911000 {
2339 compatible = "qcom,sd
2340 "qcom,ms
2341 reg = <0x17911000 0x1
2342
2343 #mbox-cells = <1>;
2344 };
2345
2346 timer@17920000 {
2347 #address-cells = <1>;
2348 #size-cells = <1>;
2349 ranges;
2350 compatible = "arm,arm
2351 reg = <0x17920000 0x1
2352 clock-frequency = <19
2353
2354 frame@17921000 {
2355 frame-number
2356 interrupts =
2357
2358 reg = <0x1792
2359 <0x17
2360 };
2361
2362 frame@17923000 {
2363 frame-number
2364 interrupts =
2365 reg = <0x1792
2366 status = "dis
2367 };
2368
2369 frame@17924000 {
2370 frame-number
2371 interrupts =
2372 reg = <0x1792
2373 status = "dis
2374 };
2375
2376 frame@17925000 {
2377 frame-number
2378 interrupts =
2379 reg = <0x1792
2380 status = "dis
2381 };
2382
2383 frame@17926000 {
2384 frame-number
2385 interrupts =
2386 reg = <0x1792
2387 status = "dis
2388 };
2389
2390 frame@17927000 {
2391 frame-number
2392 interrupts =
2393 reg = <0x1792
2394 status = "dis
2395 };
2396
2397 frame@17928000 {
2398 frame-number
2399 interrupts =
2400 reg = <0x1792
2401 status = "dis
2402 };
2403 };
2404
2405 intc: interrupt-controller@17
2406 compatible = "arm,gic
2407 reg = <0x17a00000 0x1
2408 <0x17b00000
2409 #interrupt-cells = <3
2410 #address-cells = <1>;
2411 #size-cells = <1>;
2412 ranges;
2413 interrupt-controller;
2414 #redistributor-region
2415 redistributor-stride
2416 interrupts = <GIC_PPI
2417 };
2418 };
2419
2420 sound: sound {
2421 };
2422
2423 thermal-zones {
2424 aoss-thermal {
2425 polling-delay-passive
2426
2427 thermal-sensors = <&t
2428
2429 trips {
2430 aoss_alert0:
2431 tempe
2432 hyste
2433 type
2434 };
2435 };
2436 };
2437
2438 cpuss0-thermal {
2439 polling-delay-passive
2440
2441 thermal-sensors = <&t
2442
2443 trips {
2444 cpuss0_alert0
2445 tempe
2446 hyste
2447 type
2448 };
2449 };
2450 };
2451
2452 cpuss1-thermal {
2453 polling-delay-passive
2454
2455 thermal-sensors = <&t
2456
2457 trips {
2458 cpuss1_alert0
2459 tempe
2460 hyste
2461 type
2462 };
2463 };
2464 };
2465
2466 cpu0-thermal {
2467 polling-delay-passive
2468
2469 thermal-sensors = <&t
2470
2471 trips {
2472 cpu0_alert0:
2473 tempe
2474 hyste
2475 type
2476 };
2477
2478 cpu0_crit: cp
2479 tempe
2480 hyste
2481 type
2482 };
2483 };
2484 };
2485
2486 cpu1-thermal {
2487 polling-delay-passive
2488
2489 thermal-sensors = <&t
2490
2491 trips {
2492 cpu1_alert0:
2493 tempe
2494 hyste
2495 type
2496 };
2497
2498 cpu1_crit: cp
2499 tempe
2500 hyste
2501 type
2502 };
2503 };
2504 };
2505
2506 cpu2-thermal {
2507 polling-delay-passive
2508
2509 thermal-sensors = <&t
2510
2511 trips {
2512 cpu2_alert0:
2513 tempe
2514 hyste
2515 type
2516 };
2517
2518 cpu2_crit: cp
2519 tempe
2520 hyste
2521 type
2522 };
2523 };
2524 };
2525
2526 cpu3-thermal {
2527 polling-delay-passive
2528
2529 thermal-sensors = <&t
2530
2531 trips {
2532 cpu3_alert0:
2533 tempe
2534 hyste
2535 type
2536 };
2537
2538 cpu3_crit: cp
2539 tempe
2540 hyste
2541 type
2542 };
2543 };
2544 };
2545
2546 /*
2547 * According to what downstre
2548 * the entire power efficient
2549 * only a single thermal sens
2550 */
2551
2552 pwr-cluster-thermal {
2553 polling-delay-passive
2554
2555 thermal-sensors = <&t
2556
2557 trips {
2558 pwr_cluster_a
2559 tempe
2560 hyste
2561 type
2562 };
2563
2564 pwr_cluster_c
2565 tempe
2566 hyste
2567 type
2568 };
2569 };
2570 };
2571
2572 gpu-thermal {
2573 polling-delay-passive
2574
2575 thermal-sensors = <&t
2576
2577 cooling-maps {
2578 map0 {
2579 trip
2580 cooli
2581 };
2582 };
2583
2584 trips {
2585 gpu_alert0: t
2586 tempe
2587 hyste
2588 type
2589 };
2590
2591 trip-point1 {
2592 tempe
2593 hyste
2594 type
2595 };
2596
2597 trip-point2 {
2598 tempe
2599 hyste
2600 type
2601 };
2602 };
2603 };
2604 };
2605
2606 timer {
2607 compatible = "arm,armv8-timer
2608 interrupts = <GIC_PPI 1 (GIC_
2609 <GIC_PPI 2 (GIC_
2610 <GIC_PPI 3 (GIC_
2611 <GIC_PPI 0 (GIC_
2612 };
2613 };
2614
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