1 // SPDX-License-Identifier: BSD-3-Clause 1 // SPDX-License-Identifier: BSD-3-Clause
2 /* 2 /*
3 * Copyright (c) 2020, Konrad Dybcio <konradybc !! 3 * Copyright (c) 2020, Konrad Dybcio
4 * Copyright (c) 2020, AngeloGioacchino Del Re< <<
5 */ 4 */
6 5
7 #include <dt-bindings/clock/qcom,gcc-sdm660.h> 6 #include <dt-bindings/clock/qcom,gcc-sdm660.h>
8 #include <dt-bindings/clock/qcom,gpucc-sdm660. <<
9 #include <dt-bindings/clock/qcom,mmcc-sdm660.h <<
10 #include <dt-bindings/clock/qcom,rpmcc.h> 7 #include <dt-bindings/clock/qcom,rpmcc.h>
11 #include <dt-bindings/firmware/qcom,scm.h> <<
12 #include <dt-bindings/interconnect/qcom,sdm660 <<
13 #include <dt-bindings/power/qcom-rpmpd.h> <<
14 #include <dt-bindings/gpio/gpio.h> 8 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/interrupt-controller/arm 9 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/thermal/thermal.h> <<
17 #include <dt-bindings/soc/qcom,apr.h> <<
18 10
19 / { 11 / {
20 interrupt-parent = <&intc>; 12 interrupt-parent = <&intc>;
21 13
22 #address-cells = <2>; 14 #address-cells = <2>;
23 #size-cells = <2>; 15 #size-cells = <2>;
24 16
25 aliases { <<
26 mmc1 = &sdhc_1; <<
27 mmc2 = &sdhc_2; <<
28 }; <<
29 <<
30 chosen { }; 17 chosen { };
31 18
32 clocks { 19 clocks {
33 xo_board: xo-board { !! 20 xo_board: xo_board {
34 compatible = "fixed-cl 21 compatible = "fixed-clock";
35 #clock-cells = <0>; 22 #clock-cells = <0>;
36 clock-frequency = <192 23 clock-frequency = <19200000>;
37 clock-output-names = " 24 clock-output-names = "xo_board";
38 }; 25 };
39 26
40 sleep_clk: sleep-clk { !! 27 sleep_clk: sleep_clk {
41 compatible = "fixed-cl 28 compatible = "fixed-clock";
42 #clock-cells = <0>; 29 #clock-cells = <0>;
43 clock-frequency = <327 30 clock-frequency = <32764>;
44 clock-output-names = " 31 clock-output-names = "sleep_clk";
45 }; 32 };
46 }; 33 };
47 34
48 cpus { 35 cpus {
49 #address-cells = <2>; 36 #address-cells = <2>;
50 #size-cells = <0>; 37 #size-cells = <0>;
51 38
52 CPU0: cpu@100 { 39 CPU0: cpu@100 {
53 device_type = "cpu"; 40 device_type = "cpu";
54 compatible = "arm,cort 41 compatible = "arm,cortex-a53";
55 reg = <0x0 0x100>; 42 reg = <0x0 0x100>;
56 enable-method = "psci" 43 enable-method = "psci";
57 cpu-idle-states = <&PE 44 cpu-idle-states = <&PERF_CPU_SLEEP_0
58 45 &PERF_CPU_SLEEP_1
59 46 &PERF_CLUSTER_SLEEP_0
60 47 &PERF_CLUSTER_SLEEP_1
61 48 &PERF_CLUSTER_SLEEP_2>;
62 capacity-dmips-mhz = < 49 capacity-dmips-mhz = <1126>;
63 #cooling-cells = <2>; 50 #cooling-cells = <2>;
64 next-level-cache = <&L 51 next-level-cache = <&L2_1>;
65 L2_1: l2-cache { 52 L2_1: l2-cache {
66 compatible = " 53 compatible = "cache";
67 cache-level = 54 cache-level = <2>;
68 cache-unified; <<
69 }; 55 };
70 }; 56 };
71 57
72 CPU1: cpu@101 { 58 CPU1: cpu@101 {
73 device_type = "cpu"; 59 device_type = "cpu";
74 compatible = "arm,cort 60 compatible = "arm,cortex-a53";
75 reg = <0x0 0x101>; 61 reg = <0x0 0x101>;
76 enable-method = "psci" 62 enable-method = "psci";
77 cpu-idle-states = <&PE 63 cpu-idle-states = <&PERF_CPU_SLEEP_0
78 64 &PERF_CPU_SLEEP_1
79 65 &PERF_CLUSTER_SLEEP_0
80 66 &PERF_CLUSTER_SLEEP_1
81 67 &PERF_CLUSTER_SLEEP_2>;
82 capacity-dmips-mhz = < 68 capacity-dmips-mhz = <1126>;
83 #cooling-cells = <2>; 69 #cooling-cells = <2>;
84 next-level-cache = <&L 70 next-level-cache = <&L2_1>;
85 }; 71 };
86 72
87 CPU2: cpu@102 { 73 CPU2: cpu@102 {
88 device_type = "cpu"; 74 device_type = "cpu";
89 compatible = "arm,cort 75 compatible = "arm,cortex-a53";
90 reg = <0x0 0x102>; 76 reg = <0x0 0x102>;
91 enable-method = "psci" 77 enable-method = "psci";
92 cpu-idle-states = <&PE 78 cpu-idle-states = <&PERF_CPU_SLEEP_0
93 79 &PERF_CPU_SLEEP_1
94 80 &PERF_CLUSTER_SLEEP_0
95 81 &PERF_CLUSTER_SLEEP_1
96 82 &PERF_CLUSTER_SLEEP_2>;
97 capacity-dmips-mhz = < 83 capacity-dmips-mhz = <1126>;
98 #cooling-cells = <2>; 84 #cooling-cells = <2>;
99 next-level-cache = <&L 85 next-level-cache = <&L2_1>;
100 }; 86 };
101 87
102 CPU3: cpu@103 { 88 CPU3: cpu@103 {
103 device_type = "cpu"; 89 device_type = "cpu";
104 compatible = "arm,cort 90 compatible = "arm,cortex-a53";
105 reg = <0x0 0x103>; 91 reg = <0x0 0x103>;
106 enable-method = "psci" 92 enable-method = "psci";
107 cpu-idle-states = <&PE 93 cpu-idle-states = <&PERF_CPU_SLEEP_0
108 94 &PERF_CPU_SLEEP_1
109 95 &PERF_CLUSTER_SLEEP_0
110 96 &PERF_CLUSTER_SLEEP_1
111 97 &PERF_CLUSTER_SLEEP_2>;
112 capacity-dmips-mhz = < 98 capacity-dmips-mhz = <1126>;
113 #cooling-cells = <2>; 99 #cooling-cells = <2>;
114 next-level-cache = <&L 100 next-level-cache = <&L2_1>;
115 }; 101 };
116 102
117 CPU4: cpu@0 { 103 CPU4: cpu@0 {
118 device_type = "cpu"; 104 device_type = "cpu";
119 compatible = "arm,cort 105 compatible = "arm,cortex-a53";
120 reg = <0x0 0x0>; 106 reg = <0x0 0x0>;
121 enable-method = "psci" 107 enable-method = "psci";
122 cpu-idle-states = <&PW 108 cpu-idle-states = <&PWR_CPU_SLEEP_0
123 109 &PWR_CPU_SLEEP_1
124 110 &PWR_CLUSTER_SLEEP_0
125 111 &PWR_CLUSTER_SLEEP_1
126 112 &PWR_CLUSTER_SLEEP_2>;
127 capacity-dmips-mhz = < 113 capacity-dmips-mhz = <1024>;
128 #cooling-cells = <2>; 114 #cooling-cells = <2>;
129 next-level-cache = <&L 115 next-level-cache = <&L2_0>;
130 L2_0: l2-cache { 116 L2_0: l2-cache {
131 compatible = " 117 compatible = "cache";
132 cache-level = 118 cache-level = <2>;
133 cache-unified; <<
134 }; 119 };
135 }; 120 };
136 121
137 CPU5: cpu@1 { 122 CPU5: cpu@1 {
138 device_type = "cpu"; 123 device_type = "cpu";
139 compatible = "arm,cort 124 compatible = "arm,cortex-a53";
140 reg = <0x0 0x1>; 125 reg = <0x0 0x1>;
141 enable-method = "psci" 126 enable-method = "psci";
142 cpu-idle-states = <&PW 127 cpu-idle-states = <&PWR_CPU_SLEEP_0
143 128 &PWR_CPU_SLEEP_1
144 129 &PWR_CLUSTER_SLEEP_0
145 130 &PWR_CLUSTER_SLEEP_1
146 131 &PWR_CLUSTER_SLEEP_2>;
147 capacity-dmips-mhz = < 132 capacity-dmips-mhz = <1024>;
148 #cooling-cells = <2>; 133 #cooling-cells = <2>;
149 next-level-cache = <&L 134 next-level-cache = <&L2_0>;
150 }; 135 };
151 136
152 CPU6: cpu@2 { 137 CPU6: cpu@2 {
153 device_type = "cpu"; 138 device_type = "cpu";
154 compatible = "arm,cort 139 compatible = "arm,cortex-a53";
155 reg = <0x0 0x2>; 140 reg = <0x0 0x2>;
156 enable-method = "psci" 141 enable-method = "psci";
157 cpu-idle-states = <&PW 142 cpu-idle-states = <&PWR_CPU_SLEEP_0
158 143 &PWR_CPU_SLEEP_1
159 144 &PWR_CLUSTER_SLEEP_0
160 145 &PWR_CLUSTER_SLEEP_1
161 146 &PWR_CLUSTER_SLEEP_2>;
162 capacity-dmips-mhz = < 147 capacity-dmips-mhz = <1024>;
163 #cooling-cells = <2>; 148 #cooling-cells = <2>;
164 next-level-cache = <&L 149 next-level-cache = <&L2_0>;
165 }; 150 };
166 151
167 CPU7: cpu@3 { 152 CPU7: cpu@3 {
168 device_type = "cpu"; 153 device_type = "cpu";
169 compatible = "arm,cort 154 compatible = "arm,cortex-a53";
170 reg = <0x0 0x3>; 155 reg = <0x0 0x3>;
171 enable-method = "psci" 156 enable-method = "psci";
172 cpu-idle-states = <&PW 157 cpu-idle-states = <&PWR_CPU_SLEEP_0
173 158 &PWR_CPU_SLEEP_1
174 159 &PWR_CLUSTER_SLEEP_0
175 160 &PWR_CLUSTER_SLEEP_1
176 161 &PWR_CLUSTER_SLEEP_2>;
177 capacity-dmips-mhz = < 162 capacity-dmips-mhz = <1024>;
178 #cooling-cells = <2>; 163 #cooling-cells = <2>;
179 next-level-cache = <&L 164 next-level-cache = <&L2_0>;
180 }; 165 };
181 166
182 cpu-map { 167 cpu-map {
183 cluster0 { 168 cluster0 {
184 core0 { 169 core0 {
185 cpu = 170 cpu = <&CPU4>;
186 }; 171 };
187 172
188 core1 { 173 core1 {
189 cpu = 174 cpu = <&CPU5>;
190 }; 175 };
191 176
192 core2 { 177 core2 {
193 cpu = 178 cpu = <&CPU6>;
194 }; 179 };
195 180
196 core3 { 181 core3 {
197 cpu = 182 cpu = <&CPU7>;
198 }; 183 };
199 }; 184 };
200 185
201 cluster1 { 186 cluster1 {
202 core0 { 187 core0 {
203 cpu = 188 cpu = <&CPU0>;
204 }; 189 };
205 190
206 core1 { 191 core1 {
207 cpu = 192 cpu = <&CPU1>;
208 }; 193 };
209 194
210 core2 { 195 core2 {
211 cpu = 196 cpu = <&CPU2>;
212 }; 197 };
213 198
214 core3 { 199 core3 {
215 cpu = 200 cpu = <&CPU3>;
216 }; 201 };
217 }; 202 };
218 }; 203 };
219 204
220 idle-states { 205 idle-states {
221 entry-method = "psci"; 206 entry-method = "psci";
222 207
223 PWR_CPU_SLEEP_0: cpu-s 208 PWR_CPU_SLEEP_0: cpu-sleep-0-0 {
224 compatible = " 209 compatible = "arm,idle-state";
225 idle-state-nam 210 idle-state-name = "pwr-retention";
226 arm,psci-suspe 211 arm,psci-suspend-param = <0x40000002>;
227 entry-latency- 212 entry-latency-us = <338>;
228 exit-latency-u 213 exit-latency-us = <423>;
229 min-residency- 214 min-residency-us = <200>;
230 }; 215 };
231 216
232 PWR_CPU_SLEEP_1: cpu-s 217 PWR_CPU_SLEEP_1: cpu-sleep-0-1 {
233 compatible = " 218 compatible = "arm,idle-state";
234 idle-state-nam 219 idle-state-name = "pwr-power-collapse";
235 arm,psci-suspe 220 arm,psci-suspend-param = <0x40000003>;
236 entry-latency- 221 entry-latency-us = <515>;
237 exit-latency-u 222 exit-latency-us = <1821>;
238 min-residency- 223 min-residency-us = <1000>;
239 local-timer-st 224 local-timer-stop;
240 }; 225 };
241 226
242 PERF_CPU_SLEEP_0: cpu- 227 PERF_CPU_SLEEP_0: cpu-sleep-1-0 {
243 compatible = " 228 compatible = "arm,idle-state";
244 idle-state-nam 229 idle-state-name = "perf-retention";
245 arm,psci-suspe 230 arm,psci-suspend-param = <0x40000002>;
246 entry-latency- 231 entry-latency-us = <154>;
247 exit-latency-u 232 exit-latency-us = <87>;
248 min-residency- 233 min-residency-us = <200>;
249 }; 234 };
250 235
251 PERF_CPU_SLEEP_1: cpu- 236 PERF_CPU_SLEEP_1: cpu-sleep-1-1 {
252 compatible = " 237 compatible = "arm,idle-state";
253 idle-state-nam 238 idle-state-name = "perf-power-collapse";
254 arm,psci-suspe 239 arm,psci-suspend-param = <0x40000003>;
255 entry-latency- 240 entry-latency-us = <262>;
256 exit-latency-u 241 exit-latency-us = <301>;
257 min-residency- 242 min-residency-us = <1000>;
258 local-timer-st 243 local-timer-stop;
259 }; 244 };
260 245
261 PWR_CLUSTER_SLEEP_0: c 246 PWR_CLUSTER_SLEEP_0: cluster-sleep-0-0 {
262 compatible = " 247 compatible = "arm,idle-state";
263 idle-state-nam 248 idle-state-name = "pwr-cluster-dynamic-retention";
264 arm,psci-suspe 249 arm,psci-suspend-param = <0x400000F2>;
265 entry-latency- 250 entry-latency-us = <284>;
266 exit-latency-u 251 exit-latency-us = <384>;
267 min-residency- 252 min-residency-us = <9987>;
268 local-timer-st 253 local-timer-stop;
269 }; 254 };
270 255
271 PWR_CLUSTER_SLEEP_1: c 256 PWR_CLUSTER_SLEEP_1: cluster-sleep-0-1 {
272 compatible = " 257 compatible = "arm,idle-state";
273 idle-state-nam 258 idle-state-name = "pwr-cluster-retention";
274 arm,psci-suspe 259 arm,psci-suspend-param = <0x400000F3>;
275 entry-latency- 260 entry-latency-us = <338>;
276 exit-latency-u 261 exit-latency-us = <423>;
277 min-residency- 262 min-residency-us = <9987>;
278 local-timer-st 263 local-timer-stop;
279 }; 264 };
280 265
281 PWR_CLUSTER_SLEEP_2: c 266 PWR_CLUSTER_SLEEP_2: cluster-sleep-0-2 {
282 compatible = " 267 compatible = "arm,idle-state";
283 idle-state-nam 268 idle-state-name = "pwr-cluster-retention";
284 arm,psci-suspe 269 arm,psci-suspend-param = <0x400000F4>;
285 entry-latency- 270 entry-latency-us = <515>;
286 exit-latency-u 271 exit-latency-us = <1821>;
287 min-residency- 272 min-residency-us = <9987>;
288 local-timer-st 273 local-timer-stop;
289 }; 274 };
290 275
291 PERF_CLUSTER_SLEEP_0: 276 PERF_CLUSTER_SLEEP_0: cluster-sleep-1-0 {
292 compatible = " 277 compatible = "arm,idle-state";
293 idle-state-nam 278 idle-state-name = "perf-cluster-dynamic-retention";
294 arm,psci-suspe 279 arm,psci-suspend-param = <0x400000F2>;
295 entry-latency- 280 entry-latency-us = <272>;
296 exit-latency-u 281 exit-latency-us = <329>;
297 min-residency- 282 min-residency-us = <9987>;
298 local-timer-st 283 local-timer-stop;
299 }; 284 };
300 285
301 PERF_CLUSTER_SLEEP_1: 286 PERF_CLUSTER_SLEEP_1: cluster-sleep-1-1 {
302 compatible = " 287 compatible = "arm,idle-state";
303 idle-state-nam 288 idle-state-name = "perf-cluster-retention";
304 arm,psci-suspe 289 arm,psci-suspend-param = <0x400000F3>;
305 entry-latency- 290 entry-latency-us = <332>;
306 exit-latency-u 291 exit-latency-us = <368>;
307 min-residency- 292 min-residency-us = <9987>;
308 local-timer-st 293 local-timer-stop;
309 }; 294 };
310 295
311 PERF_CLUSTER_SLEEP_2: 296 PERF_CLUSTER_SLEEP_2: cluster-sleep-1-2 {
312 compatible = " 297 compatible = "arm,idle-state";
313 idle-state-nam 298 idle-state-name = "perf-cluster-retention";
314 arm,psci-suspe 299 arm,psci-suspend-param = <0x400000F4>;
315 entry-latency- 300 entry-latency-us = <545>;
316 exit-latency-u 301 exit-latency-us = <1609>;
317 min-residency- 302 min-residency-us = <9987>;
318 local-timer-st 303 local-timer-stop;
319 }; 304 };
320 }; 305 };
321 }; 306 };
322 307
323 firmware { 308 firmware {
324 scm { 309 scm {
325 compatible = "qcom,scm 310 compatible = "qcom,scm-msm8998", "qcom,scm";
326 }; 311 };
327 }; 312 };
328 313
329 memory@80000000 { !! 314 memory {
330 device_type = "memory"; 315 device_type = "memory";
331 /* We expect the bootloader to 316 /* We expect the bootloader to fill in the reg */
332 reg = <0x0 0x80000000 0x0 0x0> !! 317 reg = <0 0 0 0>;
333 }; <<
334 <<
335 dsi_opp_table: opp-table-dsi { <<
336 compatible = "operating-points <<
337 <<
338 opp-131250000 { <<
339 opp-hz = /bits/ 64 <13 <<
340 required-opps = <&rpmp <<
341 }; <<
342 <<
343 opp-210000000 { <<
344 opp-hz = /bits/ 64 <21 <<
345 required-opps = <&rpmp <<
346 }; <<
347 <<
348 opp-262500000 { <<
349 opp-hz = /bits/ 64 <26 <<
350 required-opps = <&rpmp <<
351 }; <<
352 }; 318 };
353 319
354 pmu { 320 pmu {
355 compatible = "arm,armv8-pmuv3" 321 compatible = "arm,armv8-pmuv3";
356 interrupts = <GIC_PPI 6 IRQ_TY 322 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>;
357 }; 323 };
358 324
359 psci { 325 psci {
360 compatible = "arm,psci-1.0"; 326 compatible = "arm,psci-1.0";
361 method = "smc"; 327 method = "smc";
362 }; 328 };
363 329
364 rpm: remoteproc { <<
365 compatible = "qcom,sdm660-rpm- <<
366 <<
367 glink-edge { <<
368 compatible = "qcom,gli <<
369 <<
370 interrupts = <GIC_SPI <<
371 qcom,rpm-msg-ram = <&r <<
372 mboxes = <&apcs_glb 0> <<
373 <<
374 rpm_requests: rpm-requ <<
375 compatible = " <<
376 qcom,glink-cha <<
377 <<
378 rpmcc: clock-c <<
379 compat <<
380 #clock <<
381 }; <<
382 <<
383 rpmpd: power-c <<
384 compat <<
385 #power <<
386 operat <<
387 <<
388 rpmpd_ <<
389 <<
390 <<
391 <<
392 <<
393 <<
394 <<
395 <<
396 <<
397 <<
398 <<
399 <<
400 <<
401 <<
402 <<
403 <<
404 <<
405 <<
406 <<
407 <<
408 <<
409 <<
410 <<
411 <<
412 <<
413 <<
414 <<
415 <<
416 <<
417 <<
418 <<
419 <<
420 <<
421 <<
422 <<
423 <<
424 <<
425 <<
426 }; <<
427 }; <<
428 }; <<
429 }; <<
430 }; <<
431 <<
432 reserved-memory { 330 reserved-memory {
433 #address-cells = <2>; 331 #address-cells = <2>;
434 #size-cells = <2>; 332 #size-cells = <2>;
435 ranges; 333 ranges;
436 334
437 wlan_msa_guard: wlan-msa-guard 335 wlan_msa_guard: wlan-msa-guard@85600000 {
438 reg = <0x0 0x85600000 336 reg = <0x0 0x85600000 0x0 0x100000>;
439 no-map; 337 no-map;
440 }; 338 };
441 339
442 wlan_msa_mem: wlan-msa-mem@857 340 wlan_msa_mem: wlan-msa-mem@85700000 {
443 reg = <0x0 0x85700000 341 reg = <0x0 0x85700000 0x0 0x100000>;
444 no-map; 342 no-map;
445 }; 343 };
446 344
447 qhee_code: qhee-code@85800000 345 qhee_code: qhee-code@85800000 {
448 reg = <0x0 0x85800000 !! 346 reg = <0x0 0x85800000 0x0 0x3700000>;
449 no-map; 347 no-map;
450 }; 348 };
451 349
452 rmtfs_mem: memory@85e00000 { <<
453 compatible = "qcom,rmt <<
454 reg = <0x0 0x85e00000 <<
455 no-map; <<
456 <<
457 qcom,client-id = <1>; <<
458 qcom,vmid = <QCOM_SCM_ <<
459 }; <<
460 <<
461 smem_region: smem-mem@86000000 350 smem_region: smem-mem@86000000 {
462 reg = <0 0x86000000 0 351 reg = <0 0x86000000 0 0x200000>;
463 no-map; 352 no-map;
464 }; 353 };
465 354
466 tz_mem: memory@86200000 { 355 tz_mem: memory@86200000 {
467 reg = <0x0 0x86200000 356 reg = <0x0 0x86200000 0x0 0x3300000>;
468 no-map; 357 no-map;
469 }; 358 };
470 359
471 mpss_region: mpss@8ac00000 { !! 360 modem_fw_mem: modem-fw-region@8ac00000 {
472 reg = <0x0 0x8ac00000 361 reg = <0x0 0x8ac00000 0x0 0x7e00000>;
473 no-map; 362 no-map;
474 }; 363 };
475 364
476 adsp_region: adsp@92a00000 { !! 365 adsp_fw_mem: adsp-fw-region@92a00000 {
477 reg = <0x0 0x92a00000 366 reg = <0x0 0x92a00000 0x0 0x1e00000>;
478 no-map; 367 no-map;
479 }; 368 };
480 369
481 mba_region: mba@94800000 { !! 370 pil_mba_mem: pil-mba-region@94800000 {
482 reg = <0x0 0x94800000 371 reg = <0x0 0x94800000 0x0 0x200000>;
483 no-map; 372 no-map;
484 }; 373 };
485 374
486 buffer_mem: tzbuffer@94a00000 !! 375 buffer_mem: buffer-region@94a00000 {
487 reg = <0x0 0x94a00000 376 reg = <0x0 0x94a00000 0x0 0x100000>;
488 no-map; 377 no-map;
489 }; 378 };
490 379
491 venus_region: venus@9f800000 { !! 380 venus_fw_mem: venus-fw-region@9f800000 {
492 reg = <0x0 0x9f800000 381 reg = <0x0 0x9f800000 0x0 0x800000>;
493 no-map; 382 no-map;
494 }; 383 };
495 384
>> 385 secure_region2: secure-region2@f7c00000 {
>> 386 reg = <0x0 0xf7c00000 0x0 0x5c00000>;
>> 387 no-map;
>> 388 };
>> 389
496 adsp_mem: adsp-region@f6000000 390 adsp_mem: adsp-region@f6000000 {
497 reg = <0x0 0xf6000000 391 reg = <0x0 0xf6000000 0x0 0x800000>;
498 no-map; 392 no-map;
499 }; 393 };
500 394
>> 395 qseecom_ta_mem: qseecom-ta-region@fec00000 {
>> 396 reg = <0x0 0xfec00000 0x0 0x1000000>;
>> 397 no-map;
>> 398 };
>> 399
501 qseecom_mem: qseecom-region@f6 400 qseecom_mem: qseecom-region@f6800000 {
502 reg = <0x0 0xf6800000 401 reg = <0x0 0xf6800000 0x0 0x1400000>;
503 no-map; 402 no-map;
504 }; 403 };
505 404
506 zap_shader_region: gpu@fed0000 !! 405 secure_display_memory: secure-region@f5c00000 {
507 compatible = "shared-d !! 406 reg = <0x0 0xf5c00000 0x0 0x5c00000>;
508 reg = <0x0 0xfed00000 <<
509 no-map; 407 no-map;
510 }; 408 };
511 }; <<
512 409
513 smem: smem { !! 410 cont_splash_mem: cont-splash-region@9d400000 {
514 compatible = "qcom,smem"; !! 411 reg = <0x0 0x9d400000 0x0 0x23ff000>;
515 memory-region = <&smem_region> !! 412 no-map;
516 hwlocks = <&tcsr_mutex 3>; !! 413 };
517 }; 414 };
518 415
519 smp2p-adsp { !! 416 rpm-glink {
520 compatible = "qcom,smp2p"; !! 417 compatible = "qcom,glink-rpm";
521 qcom,smem = <443>, <429>; <<
522 interrupts = <GIC_SPI 158 IRQ_ <<
523 mboxes = <&apcs_glb 10>; <<
524 qcom,local-pid = <0>; <<
525 qcom,remote-pid = <2>; <<
526 <<
527 adsp_smp2p_out: master-kernel <<
528 qcom,entry-name = "mas <<
529 #qcom,smem-state-cells <<
530 }; <<
531 418
532 adsp_smp2p_in: slave-kernel { !! 419 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
533 qcom,entry-name = "sla !! 420 qcom,rpm-msg-ram = <&rpm_msg_ram>;
534 interrupt-controller; !! 421 mboxes = <&apcs_glb 0>;
535 #interrupt-cells = <2> !! 422
536 }; !! 423 rpm_requests: rpm-requests {
537 }; !! 424 compatible = "qcom,rpm-sdm660";
>> 425 qcom,glink-channels = "rpm_requests";
538 426
539 smp2p-mpss { !! 427 rpmcc: clock-controller {
540 compatible = "qcom,smp2p"; !! 428 compatible = "qcom,rpmcc-sdm660", "qcom,rpmcc";
541 qcom,smem = <435>, <428>; !! 429 #clock-cells = <1>;
542 interrupts = <GIC_SPI 451 IRQ_ !! 430 };
543 mboxes = <&apcs_glb 14>; <<
544 qcom,local-pid = <0>; <<
545 qcom,remote-pid = <1>; <<
546 <<
547 modem_smp2p_out: master-kernel <<
548 qcom,entry-name = "mas <<
549 #qcom,smem-state-cells <<
550 }; 431 };
>> 432 };
551 433
552 modem_smp2p_in: slave-kernel { !! 434 smem: smem {
553 qcom,entry-name = "sla !! 435 compatible = "qcom,smem";
554 interrupt-controller; !! 436 memory-region = <&smem_region>;
555 #interrupt-cells = <2> !! 437 hwlocks = <&tcsr_mutex 3>;
556 }; <<
557 }; 438 };
558 439
559 soc@0 { !! 440 soc {
560 #address-cells = <1>; 441 #address-cells = <1>;
561 #size-cells = <1>; 442 #size-cells = <1>;
562 ranges = <0 0 0 0xffffffff>; 443 ranges = <0 0 0 0xffffffff>;
563 compatible = "simple-bus"; 444 compatible = "simple-bus";
564 445
565 gcc: clock-controller@100000 { 446 gcc: clock-controller@100000 {
566 compatible = "qcom,gcc 447 compatible = "qcom,gcc-sdm630";
567 #clock-cells = <1>; 448 #clock-cells = <1>;
568 #reset-cells = <1>; 449 #reset-cells = <1>;
569 #power-domain-cells = 450 #power-domain-cells = <1>;
570 reg = <0x00100000 0x94 451 reg = <0x00100000 0x94000>;
571 452
572 clock-names = "xo", "s 453 clock-names = "xo", "sleep_clk";
573 clocks = <&xo_board>, 454 clocks = <&xo_board>,
574 <&slee 455 <&sleep_clk>;
575 }; 456 };
576 457
577 rpm_msg_ram: sram@778000 { !! 458 rpm_msg_ram: memory@778000 {
578 compatible = "qcom,rpm 459 compatible = "qcom,rpm-msg-ram";
579 reg = <0x00778000 0x70 460 reg = <0x00778000 0x7000>;
580 }; 461 };
581 462
582 qfprom: qfprom@780000 { 463 qfprom: qfprom@780000 {
583 compatible = "qcom,sdm !! 464 compatible = "qcom,qfprom";
584 reg = <0x00780000 0x62 465 reg = <0x00780000 0x621c>;
585 #address-cells = <1>; 466 #address-cells = <1>;
586 #size-cells = <1>; 467 #size-cells = <1>;
587 <<
588 qusb2_hstx_trim: hstx- <<
589 reg = <0x243 0 <<
590 bits = <1 3>; <<
591 }; <<
592 <<
593 gpu_speed_bin: gpu-spe <<
594 reg = <0x41a2 <<
595 bits = <5 7>; <<
596 }; <<
597 }; 468 };
598 469
599 rng: rng@793000 { 470 rng: rng@793000 {
600 compatible = "qcom,prn 471 compatible = "qcom,prng-ee";
601 reg = <0x00793000 0x10 472 reg = <0x00793000 0x1000>;
602 clocks = <&gcc GCC_PRN 473 clocks = <&gcc GCC_PRNG_AHB_CLK>;
603 clock-names = "core"; 474 clock-names = "core";
604 }; 475 };
605 476
606 bimc: interconnect@1008000 { <<
607 compatible = "qcom,sdm <<
608 reg = <0x01008000 0x78 <<
609 #interconnect-cells = <<
610 }; <<
611 <<
612 restart@10ac000 { 477 restart@10ac000 {
613 compatible = "qcom,psh 478 compatible = "qcom,pshold";
614 reg = <0x010ac000 0x4> 479 reg = <0x010ac000 0x4>;
615 }; 480 };
616 481
617 cnoc: interconnect@1500000 { <<
618 compatible = "qcom,sdm <<
619 reg = <0x01500000 0x10 <<
620 #interconnect-cells = <<
621 }; <<
622 <<
623 snoc: interconnect@1626000 { <<
624 compatible = "qcom,sdm <<
625 reg = <0x01626000 0x70 <<
626 #interconnect-cells = <<
627 }; <<
628 <<
629 anoc2_smmu: iommu@16c0000 { 482 anoc2_smmu: iommu@16c0000 {
630 compatible = "qcom,sdm 483 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
631 reg = <0x016c0000 0x40 484 reg = <0x016c0000 0x40000>;
632 #global-interrupts = < <<
633 #iommu-cells = <1>; 485 #iommu-cells = <1>;
634 486
>> 487 #global-interrupts = <2>;
635 interrupts = 488 interrupts =
636 <GIC_SPI 229 I 489 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
637 <GIC_SPI 231 I 490 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
638 491
639 <GIC_SPI 373 I 492 <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>,
640 <GIC_SPI 374 I 493 <GIC_SPI 374 IRQ_TYPE_LEVEL_LOW>,
641 <GIC_SPI 375 I 494 <GIC_SPI 375 IRQ_TYPE_LEVEL_LOW>,
642 <GIC_SPI 376 I 495 <GIC_SPI 376 IRQ_TYPE_LEVEL_LOW>,
643 <GIC_SPI 377 I 496 <GIC_SPI 377 IRQ_TYPE_LEVEL_LOW>,
644 <GIC_SPI 378 I 497 <GIC_SPI 378 IRQ_TYPE_LEVEL_LOW>,
645 <GIC_SPI 462 I 498 <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
646 <GIC_SPI 463 I 499 <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
647 <GIC_SPI 464 I 500 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
648 <GIC_SPI 465 I 501 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
649 <GIC_SPI 466 I 502 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
650 <GIC_SPI 467 I 503 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
651 <GIC_SPI 353 I 504 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
652 <GIC_SPI 354 I 505 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
653 <GIC_SPI 355 I 506 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,
654 <GIC_SPI 356 I 507 <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>,
655 <GIC_SPI 357 I 508 <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>,
656 <GIC_SPI 358 I 509 <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
657 <GIC_SPI 359 I 510 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
658 <GIC_SPI 360 I 511 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
659 <GIC_SPI 442 I 512 <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>,
660 <GIC_SPI 443 I 513 <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>,
661 <GIC_SPI 444 I 514 <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
662 <GIC_SPI 447 I 515 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
663 <GIC_SPI 468 I 516 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
664 <GIC_SPI 469 I 517 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
665 <GIC_SPI 472 I 518 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
666 <GIC_SPI 473 I 519 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
667 <GIC_SPI 474 I 520 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
668 521
669 status = "disabled"; 522 status = "disabled";
670 }; 523 };
671 524
672 a2noc: interconnect@1704000 { !! 525 tcsr_mutex_regs: syscon@1f40000 {
673 compatible = "qcom,sdm !! 526 compatible = "syscon";
674 reg = <0x01704000 0xc1 <<
675 #interconnect-cells = <<
676 clock-names = "ipa", <<
677 "ufs_axi <<
678 "aggre2_ <<
679 "aggre2_ <<
680 "cfg_noc <<
681 clocks = <&rpmcc RPM_S <<
682 <&gcc GCC_UFS <<
683 <&gcc GCC_AGG <<
684 <&gcc GCC_AGG <<
685 <&gcc GCC_CFG <<
686 }; <<
687 <<
688 mnoc: interconnect@1745000 { <<
689 compatible = "qcom,sdm <<
690 reg = <0x01745000 0xa0 <<
691 #interconnect-cells = <<
692 clock-names = "iface"; <<
693 clocks = <&mmcc AHB_CL <<
694 }; <<
695 <<
696 tsens: thermal-sensor@10ae000 <<
697 compatible = "qcom,sdm <<
698 reg = <0x010ae000 0x10 <<
699 <0x010ad000 <<
700 #qcom,sensors = <12>; <<
701 interrupts = <GIC_SPI <<
702 <GIC_ <<
703 interrupt-names = "upl <<
704 #thermal-sensor-cells <<
705 }; <<
706 <<
707 tcsr_mutex: hwlock@1f40000 { <<
708 compatible = "qcom,tcs <<
709 reg = <0x01f40000 0x20 527 reg = <0x01f40000 0x20000>;
710 #hwlock-cells = <1>; <<
711 }; 528 };
712 529
713 tcsr_regs_1: syscon@1f60000 { !! 530 tlmm: pinctrl@3000000 {
714 compatible = "qcom,sdm <<
715 reg = <0x01f60000 0x20 <<
716 }; <<
717 <<
718 tlmm: pinctrl@3100000 { <<
719 compatible = "qcom,sdm 531 compatible = "qcom,sdm630-pinctrl";
720 reg = <0x03100000 0x40 !! 532 reg = <0x03000000 0xc00000>;
721 <0x03500000 <<
722 <0x03900000 <<
723 reg-names = "south", " <<
724 interrupts = <GIC_SPI 533 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
725 gpio-controller; 534 gpio-controller;
726 gpio-ranges = <&tlmm 0 !! 535 #gpio-cells = <0x2>;
727 #gpio-cells = <2>; <<
728 interrupt-controller; 536 interrupt-controller;
729 #interrupt-cells = <2> !! 537 #interrupt-cells = <0x2>;
730 538
731 blsp1_uart1_default: b !! 539 blsp1_uart1_default: blsp1-uart1-default {
732 pins = "gpio0" 540 pins = "gpio0", "gpio1", "gpio2", "gpio3";
733 function = "bl <<
734 drive-strength 541 drive-strength = <2>;
735 bias-disable; 542 bias-disable;
736 }; 543 };
737 544
738 blsp1_uart1_sleep: bls !! 545 blsp1_uart1_sleep: blsp1-uart1-sleep {
739 pins = "gpio0" 546 pins = "gpio0", "gpio1", "gpio2", "gpio3";
740 function = "gp <<
741 drive-strength 547 drive-strength = <2>;
742 bias-disable; 548 bias-disable;
743 }; 549 };
744 550
745 blsp1_uart2_default: b !! 551 blsp1_uart2_default: blsp1-uart2-default {
746 pins = "gpio4" 552 pins = "gpio4", "gpio5";
747 function = "bl <<
748 drive-strength 553 drive-strength = <2>;
749 bias-disable; 554 bias-disable;
750 }; 555 };
751 556
752 blsp2_uart1_default: b !! 557 blsp2_uart1_tx_active: blsp2-uart1-tx-active {
753 tx-rts-pins { !! 558 pins = "gpio16";
754 pins = !! 559 drive-strength = <2>;
755 functi !! 560 bias-disable;
756 drive- !! 561 };
757 bias-d <<
758 }; <<
759 562
760 rx-pins { !! 563 blsp2_uart1_tx_sleep: blsp2-uart1-tx-sleep {
761 /* !! 564 pins = "gpio16";
762 * Avo !! 565 drive-strength = <2>;
763 * is !! 566 bias-pull-up;
764 */ !! 567 };
765 pins = <<
766 functi <<
767 drive- <<
768 bias-p <<
769 }; <<
770 568
771 cts-pins { !! 569 blsp2_uart1_rxcts_active: blsp2-uart1-rxcts-active {
772 /* Mat !! 570 pins = "gpio17", "gpio18";
773 pins = !! 571 drive-strength = <2>;
774 functi !! 572 bias-disable;
775 drive- <<
776 bias-p <<
777 }; <<
778 }; 573 };
779 574
780 blsp2_uart1_sleep: bls !! 575 blsp2_uart1_rxcts_sleep: blsp2-uart1-rxcts-sleep {
781 tx-pins { !! 576 pins = "gpio17", "gpio18";
782 pins = !! 577 drive-strength = <2>;
783 functi !! 578 bias-no-pull;
784 drive- !! 579 };
785 bias-p <<
786 }; <<
787 580
788 rx-cts-rts-pin !! 581 blsp2_uart1_rfr_active: blsp2-uart1-rfr-active {
789 pins = !! 582 pins = "gpio19";
790 functi !! 583 drive-strength = <2>;
791 drive- !! 584 bias-disable;
792 bias-d !! 585 };
793 }; !! 586
>> 587 blsp2_uart1_rfr_sleep: blsp2-uart1-rfr-sleep {
>> 588 pins = "gpio19";
>> 589 drive-strength = <2>;
>> 590 bias-no-pull;
794 }; 591 };
795 592
796 i2c1_default: i2c1-def !! 593 i2c1_default: i2c1-default {
797 pins = "gpio2" 594 pins = "gpio2", "gpio3";
798 function = "bl <<
799 drive-strength 595 drive-strength = <2>;
800 bias-disable; 596 bias-disable;
801 }; 597 };
802 598
803 i2c1_sleep: i2c1-sleep !! 599 i2c1_sleep: i2c1-sleep {
804 pins = "gpio2" 600 pins = "gpio2", "gpio3";
805 function = "bl <<
806 drive-strength 601 drive-strength = <2>;
807 bias-pull-up; 602 bias-pull-up;
808 }; 603 };
809 604
810 i2c2_default: i2c2-def !! 605 i2c2_default: i2c2-default {
811 pins = "gpio6" 606 pins = "gpio6", "gpio7";
812 function = "bl <<
813 drive-strength 607 drive-strength = <2>;
814 bias-disable; 608 bias-disable;
815 }; 609 };
816 610
817 i2c2_sleep: i2c2-sleep !! 611 i2c2_sleep: i2c2-sleep {
818 pins = "gpio6" 612 pins = "gpio6", "gpio7";
819 function = "bl <<
820 drive-strength 613 drive-strength = <2>;
821 bias-pull-up; 614 bias-pull-up;
822 }; 615 };
823 616
824 i2c3_default: i2c3-def !! 617 i2c3_default: i2c3-default {
825 pins = "gpio10 618 pins = "gpio10", "gpio11";
826 function = "bl <<
827 drive-strength 619 drive-strength = <2>;
828 bias-disable; 620 bias-disable;
829 }; 621 };
830 622
831 i2c3_sleep: i2c3-sleep !! 623 i2c3_sleep: i2c3-sleep {
832 pins = "gpio10 624 pins = "gpio10", "gpio11";
833 function = "bl <<
834 drive-strength 625 drive-strength = <2>;
835 bias-pull-up; 626 bias-pull-up;
836 }; 627 };
837 628
838 i2c4_default: i2c4-def !! 629 i2c4_default: i2c4-default {
839 pins = "gpio14 630 pins = "gpio14", "gpio15";
840 function = "bl <<
841 drive-strength 631 drive-strength = <2>;
842 bias-disable; 632 bias-disable;
843 }; 633 };
844 634
845 i2c4_sleep: i2c4-sleep !! 635 i2c4_sleep: i2c4-sleep {
846 pins = "gpio14 636 pins = "gpio14", "gpio15";
847 function = "bl <<
848 drive-strength 637 drive-strength = <2>;
849 bias-pull-up; 638 bias-pull-up;
850 }; 639 };
851 640
852 i2c5_default: i2c5-def !! 641 i2c5_default: i2c5-default {
853 pins = "gpio18 642 pins = "gpio18", "gpio19";
854 function = "bl <<
855 drive-strength 643 drive-strength = <2>;
856 bias-disable; 644 bias-disable;
857 }; 645 };
858 646
859 i2c5_sleep: i2c5-sleep !! 647 i2c5_sleep: i2c5-sleep {
860 pins = "gpio18 648 pins = "gpio18", "gpio19";
861 function = "bl <<
862 drive-strength 649 drive-strength = <2>;
863 bias-pull-up; 650 bias-pull-up;
864 }; 651 };
865 652
866 i2c6_default: i2c6-def !! 653 i2c6_default: i2c6-default {
867 pins = "gpio22 654 pins = "gpio22", "gpio23";
868 function = "bl <<
869 drive-strength 655 drive-strength = <2>;
870 bias-disable; 656 bias-disable;
871 }; 657 };
872 658
873 i2c6_sleep: i2c6-sleep !! 659 i2c6_sleep: i2c6-sleep {
874 pins = "gpio22 660 pins = "gpio22", "gpio23";
875 function = "bl <<
876 drive-strength 661 drive-strength = <2>;
877 bias-pull-up; 662 bias-pull-up;
878 }; 663 };
879 664
880 i2c7_default: i2c7-def !! 665 i2c7_default: i2c7-default {
881 pins = "gpio26 666 pins = "gpio26", "gpio27";
882 function = "bl <<
883 drive-strength 667 drive-strength = <2>;
884 bias-disable; 668 bias-disable;
885 }; 669 };
886 670
887 i2c7_sleep: i2c7-sleep !! 671 i2c7_sleep: i2c7-sleep {
888 pins = "gpio26 672 pins = "gpio26", "gpio27";
889 function = "bl <<
890 drive-strength 673 drive-strength = <2>;
891 bias-pull-up; 674 bias-pull-up;
892 }; 675 };
893 676
894 i2c8_default: i2c8-def !! 677 i2c8_default: i2c8-default {
895 pins = "gpio30 678 pins = "gpio30", "gpio31";
896 function = "bl <<
897 drive-strength 679 drive-strength = <2>;
898 bias-disable; 680 bias-disable;
899 }; 681 };
900 682
901 i2c8_sleep: i2c8-sleep !! 683 i2c8_sleep: i2c8-sleep {
902 pins = "gpio30 684 pins = "gpio30", "gpio31";
903 function = "bl <<
904 drive-strength 685 drive-strength = <2>;
905 bias-pull-up; 686 bias-pull-up;
906 }; 687 };
907 688
908 cci0_default: cci0-def !! 689 sdc1_clk_on: sdc1-clk-on {
909 pins = "gpio36 !! 690 pins = "sdc1_clk";
910 function = "cc !! 691 bias-disable;
911 bias-pull-up; !! 692 drive-strength = <16>;
912 drive-strength <<
913 }; 693 };
914 694
915 cci1_default: cci1-def !! 695 sdc1_clk_off: sdc1-clk-off {
916 pins = "gpio38 !! 696 pins = "sdc1_clk";
917 function = "cc !! 697 bias-disable;
918 bias-pull-up; <<
919 drive-strength 698 drive-strength = <2>;
920 }; 699 };
921 700
922 sdc1_state_on: sdc1-on !! 701 sdc1_cmd_on: sdc1-cmd-on {
923 clk-pins { !! 702 pins = "sdc1_cmd";
924 pins = !! 703 bias-pull-up;
925 bias-d !! 704 drive-strength = <10>;
926 drive- <<
927 }; <<
928 <<
929 cmd-pins { <<
930 pins = <<
931 bias-p <<
932 drive- <<
933 }; <<
934 <<
935 data-pins { <<
936 pins = <<
937 bias-p <<
938 drive- <<
939 }; <<
940 <<
941 rclk-pins { <<
942 pins = <<
943 bias-p <<
944 }; <<
945 }; 705 };
946 706
947 sdc1_state_off: sdc1-o !! 707 sdc1_cmd_off: sdc1-cmd-off {
948 clk-pins { !! 708 pins = "sdc1_cmd";
949 pins = !! 709 bias-pull-up;
950 bias-d !! 710 drive-strength = <2>;
951 drive- <<
952 }; <<
953 <<
954 cmd-pins { <<
955 pins = <<
956 bias-p <<
957 drive- <<
958 }; <<
959 <<
960 data-pins { <<
961 pins = <<
962 bias-p <<
963 drive- <<
964 }; <<
965 <<
966 rclk-pins { <<
967 pins = <<
968 bias-p <<
969 }; <<
970 }; 711 };
971 712
972 sdc2_state_on: sdc2-on !! 713 sdc1_data_on: sdc1-data-on {
973 clk-pins { !! 714 pins = "sdc1_data";
974 pins = !! 715 bias-pull-up;
975 bias-d !! 716 drive-strength = <8>;
976 drive- <<
977 }; <<
978 <<
979 cmd-pins { <<
980 pins = <<
981 bias-p <<
982 drive- <<
983 }; <<
984 <<
985 data-pins { <<
986 pins = <<
987 bias-p <<
988 drive- <<
989 }; <<
990 }; 717 };
991 718
992 sdc2_state_off: sdc2-o !! 719 sdc1_data_off: sdc1-data-off {
993 clk-pins { !! 720 pins = "sdc1_data";
994 pins = !! 721 bias-pull-up;
995 bias-d !! 722 drive-strength = <2>;
996 drive- <<
997 }; <<
998 <<
999 cmd-pins { <<
1000 pins <<
1001 bias- <<
1002 drive <<
1003 }; <<
1004 <<
1005 data-pins { <<
1006 pins <<
1007 bias- <<
1008 drive <<
1009 }; <<
1010 }; 723 };
1011 }; <<
1012 <<
1013 remoteproc_mss: remoteproc@40 <<
1014 compatible = "qcom,sd <<
1015 reg = <0x04080000 0x1 <<
1016 reg-names = "qdsp6", <<
1017 <<
1018 interrupts-extended = <<
1019 <<
1020 <<
1021 <<
1022 <<
1023 <<
1024 interrupt-names = "wd <<
1025 "fa <<
1026 "re <<
1027 "ha <<
1028 "st <<
1029 "sh <<
1030 <<
1031 clocks = <&gcc GCC_MS <<
1032 <&gcc GCC_BI <<
1033 <&gcc GCC_BO <<
1034 <&gcc GPLL0_ <<
1035 <&gcc GCC_MS <<
1036 <&gcc GCC_MS <<
1037 <&rpmcc RPM_ <<
1038 <&rpmcc RPM_ <<
1039 clock-names = "iface" <<
1040 "bus", <<
1041 "mem", <<
1042 "gpll0_ <<
1043 "snoc_a <<
1044 "mnoc_a <<
1045 "qdss", <<
1046 "xo"; <<
1047 <<
1048 qcom,smem-states = <& <<
1049 qcom,smem-state-names <<
1050 <<
1051 resets = <&gcc GCC_MS <<
1052 reset-names = "mss_re <<
1053 <<
1054 qcom,halt-regs = <&tc <<
1055 <<
1056 power-domains = <&rpm <<
1057 <&rpm <<
1058 power-domain-names = <<
1059 <<
1060 memory-region = <&mba <<
1061 <<
1062 status = "disabled"; <<
1063 724
1064 glink-edge { !! 725 sdc1_rclk_on: sdc1-rclk-on {
1065 interrupts = !! 726 pins = "sdc1_rclk";
1066 label = "mode !! 727 bias-pull-down;
1067 qcom,remote-p <<
1068 mboxes = <&ap <<
1069 }; 728 };
1070 }; <<
1071 <<
1072 adreno_gpu: gpu@5000000 { <<
1073 compatible = "qcom,ad <<
1074 <<
1075 reg = <0x05000000 0x4 <<
1076 reg-names = "kgsl_3d0 <<
1077 <<
1078 interrupts = <GIC_SPI <<
1079 <<
1080 clocks = <&gcc GCC_GP <<
1081 <&gpucc GPUCC <<
1082 <&gcc GCC_BIM <<
1083 <&gcc GCC_GPU <<
1084 <&gpucc GPUCC <<
1085 <&gpucc GPUCC <<
1086 <<
1087 clock-names = "iface" <<
1088 "rbbmtimer", <<
1089 "mem", <<
1090 "mem_iface", <<
1091 "rbcpr", <<
1092 "core"; <<
1093 <<
1094 power-domains = <&rpm <<
1095 iommus = <&kgsl_smmu <<
1096 <<
1097 nvmem-cells = <&gpu_s <<
1098 nvmem-cell-names = "s <<
1099 <<
1100 interconnects = <&bim <<
1101 interconnect-names = <<
1102 <<
1103 operating-points-v2 = <<
1104 #cooling-cells = <2>; <<
1105 <<
1106 status = "disabled"; <<
1107 729
1108 gpu_sdm630_opp_table: !! 730 sdc1_rclk_off: sdc1-rclk-off {
1109 compatible = !! 731 pins = "sdc1_rclk";
1110 opp-775000000 !! 732 bias-pull-down;
1111 opp-h <<
1112 opp-l <<
1113 opp-p <<
1114 opp-s <<
1115 }; <<
1116 opp-647000000 <<
1117 opp-h <<
1118 opp-l <<
1119 opp-p <<
1120 opp-s <<
1121 }; <<
1122 opp-588000000 <<
1123 opp-h <<
1124 opp-l <<
1125 opp-p <<
1126 opp-s <<
1127 }; <<
1128 opp-465000000 <<
1129 opp-h <<
1130 opp-l <<
1131 opp-p <<
1132 opp-s <<
1133 }; <<
1134 opp-370000000 <<
1135 opp-h <<
1136 opp-l <<
1137 opp-p <<
1138 opp-s <<
1139 }; <<
1140 opp-240000000 <<
1141 opp-h <<
1142 opp-l <<
1143 opp-p <<
1144 opp-s <<
1145 }; <<
1146 opp-160000000 <<
1147 opp-h <<
1148 opp-l <<
1149 opp-p <<
1150 opp-s <<
1151 }; <<
1152 }; 733 };
1153 }; 734 };
1154 735
1155 kgsl_smmu: iommu@5040000 { 736 kgsl_smmu: iommu@5040000 {
1156 compatible = "qcom,sd !! 737 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
1157 "qcom,ad <<
1158 reg = <0x05040000 0x1 738 reg = <0x05040000 0x10000>;
1159 <<
1160 /* <<
1161 * GX GDSC parent is <<
1162 * but we need both u <<
1163 * need to manage the <<
1164 * Enable CX/GX GDSCs <<
1165 * RPM Power Domain i <<
1166 */ <<
1167 power-domains = <&gpu <<
1168 clocks = <&gcc GCC_GP <<
1169 <&gcc GCC_BI <<
1170 <&gcc GCC_GP <<
1171 clock-names = "iface" <<
1172 "mem", <<
1173 "mem_if <<
1174 #global-interrupts = <<
1175 #iommu-cells = <1>; 739 #iommu-cells = <1>;
1176 740
>> 741 #global-interrupts = <2>;
1177 interrupts = 742 interrupts =
1178 <GIC_SPI 229 743 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
1179 <GIC_SPI 231 744 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
1180 745
1181 <GIC_SPI 329 746 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1182 <GIC_SPI 330 747 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
1183 <GIC_SPI 331 748 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
1184 <GIC_SPI 332 749 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
1185 <GIC_SPI 116 750 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1186 <GIC_SPI 117 751 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1187 <GIC_SPI 349 752 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
1188 <GIC_SPI 350 753 <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>;
1189 754
1190 status = "disabled"; 755 status = "disabled";
1191 }; 756 };
1192 757
1193 gpucc: clock-controller@50650 <<
1194 compatible = "qcom,gp <<
1195 #clock-cells = <1>; <<
1196 #reset-cells = <1>; <<
1197 #power-domain-cells = <<
1198 reg = <0x05065000 0x9 <<
1199 <<
1200 clocks = <&xo_board>, <<
1201 <&gcc GCC_GP <<
1202 <&gcc GCC_GP <<
1203 clock-names = "xo", <<
1204 "gcc_gp <<
1205 "gcc_gp <<
1206 status = "disabled"; <<
1207 }; <<
1208 <<
1209 lpass_smmu: iommu@5100000 { 758 lpass_smmu: iommu@5100000 {
1210 compatible = "qcom,sd 759 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
1211 reg = <0x05100000 0x4 760 reg = <0x05100000 0x40000>;
1212 #iommu-cells = <1>; 761 #iommu-cells = <1>;
1213 762
1214 #global-interrupts = 763 #global-interrupts = <2>;
1215 interrupts = 764 interrupts =
1216 <GIC_SPI 229 765 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
1217 <GIC_SPI 231 766 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
1218 767
1219 <GIC_SPI 226 768 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
1220 <GIC_SPI 393 769 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
1221 <GIC_SPI 394 770 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
1222 <GIC_SPI 395 771 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
1223 <GIC_SPI 396 772 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
1224 <GIC_SPI 397 773 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
1225 <GIC_SPI 398 774 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
1226 <GIC_SPI 399 775 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
1227 <GIC_SPI 400 776 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
1228 <GIC_SPI 401 777 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
1229 <GIC_SPI 402 778 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
1230 <GIC_SPI 403 779 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
1231 <GIC_SPI 137 780 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
1232 <GIC_SPI 224 781 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>,
1233 <GIC_SPI 225 782 <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>,
1234 <GIC_SPI 310 783 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
1235 <GIC_SPI 404 784 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
1236 785
1237 status = "disabled"; 786 status = "disabled";
1238 }; 787 };
1239 788
1240 sram@290000 { <<
1241 compatible = "qcom,rp <<
1242 reg = <0x00290000 0x1 <<
1243 }; <<
1244 <<
1245 spmi_bus: spmi@800f000 { 789 spmi_bus: spmi@800f000 {
1246 compatible = "qcom,sp 790 compatible = "qcom,spmi-pmic-arb";
1247 reg = <0x0800f000 0x1 !! 791 reg = <0x0800f000 0x1000>,
1248 <0x08400000 0x1 !! 792 <0x08400000 0x1000000>,
1249 <0x09400000 0x1 !! 793 <0x09400000 0x1000000>,
1250 <0x0a400000 0x2 !! 794 <0x0a400000 0x220000>,
1251 <0x0800a000 0x3 !! 795 <0x0800a000 0x3000>;
1252 reg-names = "core", " 796 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1253 interrupt-names = "pe 797 interrupt-names = "periph_irq";
1254 interrupts = <GIC_SPI 798 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
1255 qcom,ee = <0>; 799 qcom,ee = <0>;
1256 qcom,channel = <0>; 800 qcom,channel = <0>;
1257 #address-cells = <2>; 801 #address-cells = <2>;
1258 #size-cells = <0>; 802 #size-cells = <0>;
1259 interrupt-controller; 803 interrupt-controller;
1260 #interrupt-cells = <4 804 #interrupt-cells = <4>;
>> 805 cell-index = <0>;
1261 }; 806 };
1262 807
1263 usb3: usb@a8f8800 { !! 808 sdhc_1: sdhci@c0c4000 {
1264 compatible = "qcom,sd <<
1265 reg = <0x0a8f8800 0x4 <<
1266 status = "disabled"; <<
1267 #address-cells = <1>; <<
1268 #size-cells = <1>; <<
1269 ranges; <<
1270 <<
1271 clocks = <&gcc GCC_CF <<
1272 <&gcc GCC_US <<
1273 <&gcc GCC_AG <<
1274 <&gcc GCC_US <<
1275 <&gcc GCC_US <<
1276 clock-names = "cfg_no <<
1277 "core", <<
1278 "iface" <<
1279 "sleep" <<
1280 "mock_u <<
1281 <<
1282 assigned-clocks = <&g <<
1283 <&g <<
1284 assigned-clock-rates <<
1285 <<
1286 interrupts = <GIC_SPI <<
1287 <GIC_SPI <<
1288 <GIC_SPI <<
1289 <GIC_SPI <<
1290 interrupt-names = "pw <<
1291 "qu <<
1292 "hs <<
1293 "ss <<
1294 <<
1295 power-domains = <&gcc <<
1296 <<
1297 resets = <&gcc GCC_US <<
1298 <<
1299 usb3_dwc3: usb@a80000 <<
1300 compatible = <<
1301 reg = <0x0a80 <<
1302 interrupts = <<
1303 snps,dis_u2_s <<
1304 snps,dis_enbl <<
1305 snps,parkmode <<
1306 <<
1307 phys = <&qusb <<
1308 phy-names = " <<
1309 snps,hird-thr <<
1310 }; <<
1311 }; <<
1312 <<
1313 usb3_qmpphy: phy@c010000 { <<
1314 compatible = "qcom,sd <<
1315 reg = <0x0c010000 0x1 <<
1316 <<
1317 clocks = <&gcc GCC_US <<
1318 <&gcc GCC_US <<
1319 <&gcc GCC_US <<
1320 <&gcc GCC_US <<
1321 clock-names = "aux", <<
1322 "ref", <<
1323 "cfg_ah <<
1324 "pipe"; <<
1325 clock-output-names = <<
1326 #clock-cells = <0>; <<
1327 #phy-cells = <0>; <<
1328 <<
1329 resets = <&gcc GCC_US <<
1330 <&gcc GCC_US <<
1331 reset-names = "phy", <<
1332 "phy_ph <<
1333 <<
1334 qcom,tcsr-reg = <&tcs <<
1335 <<
1336 status = "disabled"; <<
1337 }; <<
1338 <<
1339 qusb2phy0: phy@c012000 { <<
1340 compatible = "qcom,sd <<
1341 reg = <0x0c012000 0x1 <<
1342 #phy-cells = <0>; <<
1343 <<
1344 clocks = <&gcc GCC_US <<
1345 <&gcc GCC_RX <<
1346 clock-names = "cfg_ah <<
1347 <<
1348 resets = <&gcc GCC_QU <<
1349 nvmem-cells = <&qusb2 <<
1350 status = "disabled"; <<
1351 }; <<
1352 <<
1353 qusb2phy1: phy@c014000 { <<
1354 compatible = "qcom,sd <<
1355 reg = <0x0c014000 0x1 <<
1356 #phy-cells = <0>; <<
1357 <<
1358 clocks = <&gcc GCC_US <<
1359 <&gcc GCC_RX <<
1360 clock-names = "cfg_ah <<
1361 <<
1362 resets = <&gcc GCC_QU <<
1363 nvmem-cells = <&qusb2 <<
1364 status = "disabled"; <<
1365 }; <<
1366 <<
1367 sdhc_2: mmc@c084000 { <<
1368 compatible = "qcom,sd <<
1369 reg = <0x0c084000 0x1 <<
1370 reg-names = "hc"; <<
1371 <<
1372 interrupts = <GIC_SPI <<
1373 <GIC_ <<
1374 interrupt-names = "hc <<
1375 <<
1376 bus-width = <4>; <<
1377 <<
1378 clocks = <&gcc GCC_SD <<
1379 <&gcc <<
1380 <&xo_ <<
1381 clock-names = "iface" <<
1382 <<
1383 <<
1384 interconnects = <&a2n <<
1385 <&gno <<
1386 interconnect-names = <<
1387 operating-points-v2 = <<
1388 <<
1389 pinctrl-names = "defa <<
1390 pinctrl-0 = <&sdc2_st <<
1391 pinctrl-1 = <&sdc2_st <<
1392 power-domains = <&rpm <<
1393 <<
1394 status = "disabled"; <<
1395 <<
1396 sdhc2_opp_table: opp- <<
1397 compatible = <<
1398 <<
1399 opp-50000000 <<
1400 opp-h <<
1401 requi <<
1402 opp-p <<
1403 opp-a <<
1404 }; <<
1405 opp-10000000 <<
1406 opp-h <<
1407 requi <<
1408 opp-p <<
1409 opp-a <<
1410 }; <<
1411 opp-20000000 <<
1412 opp-h <<
1413 requi <<
1414 opp-p <<
1415 opp-a <<
1416 }; <<
1417 }; <<
1418 }; <<
1419 <<
1420 sdhc_1: mmc@c0c4000 { <<
1421 compatible = "qcom,sd 809 compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5";
1422 reg = <0x0c0c4000 0x1 810 reg = <0x0c0c4000 0x1000>,
1423 <0x0c0c5000 0x1 !! 811 <0x0c0c5000 0x1000>;
1424 <0x0c0c8000 0x8 !! 812 reg-names = "hc", "cqhci";
1425 reg-names = "hc", "cq <<
1426 813
1427 interrupts = <GIC_SPI 814 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
1428 <GIC_ 815 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1429 interrupt-names = "hc 816 interrupt-names = "hc_irq", "pwr_irq";
1430 817
1431 clocks = <&gcc GCC_SD !! 818 clocks = <&gcc GCC_SDCC1_APPS_CLK>,
1432 <&gcc GCC_SD !! 819 <&gcc GCC_SDCC1_AHB_CLK>,
1433 <&xo_board>, !! 820 <&xo_board>;
1434 <&gcc GCC_SD !! 821 clock-names = "core", "iface", "xo";
1435 clock-names = "iface" !! 822
1436 <<
1437 interconnects = <&a2n <<
1438 <&gno <<
1439 interconnect-names = <<
1440 operating-points-v2 = <<
1441 pinctrl-names = "defa 823 pinctrl-names = "default", "sleep";
1442 pinctrl-0 = <&sdc1_st !! 824 pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
1443 pinctrl-1 = <&sdc1_st !! 825 pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;
1444 power-domains = <&rpm <<
1445 826
1446 bus-width = <8>; 827 bus-width = <8>;
1447 non-removable; 828 non-removable;
1448 829
1449 status = "disabled"; 830 status = "disabled";
1450 <<
1451 sdhc1_opp_table: opp- <<
1452 compatible = <<
1453 <<
1454 opp-50000000 <<
1455 opp-h <<
1456 requi <<
1457 opp-p <<
1458 opp-a <<
1459 }; <<
1460 opp-100000000 <<
1461 opp-h <<
1462 requi <<
1463 opp-p <<
1464 opp-a <<
1465 }; <<
1466 opp-384000000 <<
1467 opp-h <<
1468 requi <<
1469 opp-p <<
1470 opp-a <<
1471 }; <<
1472 }; <<
1473 }; <<
1474 <<
1475 usb2: usb@c2f8800 { <<
1476 compatible = "qcom,sd <<
1477 reg = <0x0c2f8800 0x4 <<
1478 status = "disabled"; <<
1479 #address-cells = <1>; <<
1480 #size-cells = <1>; <<
1481 ranges; <<
1482 <<
1483 clocks = <&gcc GCC_CF <<
1484 <&gcc GCC_US <<
1485 <&gcc GCC_US <<
1486 <&gcc GCC_US <<
1487 clock-names = "cfg_no <<
1488 "sleep" <<
1489 <<
1490 assigned-clocks = <&g <<
1491 <&g <<
1492 assigned-clock-rates <<
1493 <<
1494 interrupts = <GIC_SPI <<
1495 <GIC_SPI <<
1496 <GIC_SPI <<
1497 interrupt-names = "pw <<
1498 "qu <<
1499 "hs <<
1500 <<
1501 qcom,select-utmi-as-p <<
1502 <<
1503 resets = <&gcc GCC_US <<
1504 <<
1505 usb2_dwc3: usb@c20000 <<
1506 compatible = <<
1507 reg = <0x0c20 <<
1508 interrupts = <<
1509 snps,dis_u2_s <<
1510 snps,dis_enbl <<
1511 <<
1512 /* This is th <<
1513 maximum-speed <<
1514 phys = <&qusb <<
1515 phy-names = " <<
1516 snps,hird-thr <<
1517 }; <<
1518 }; <<
1519 <<
1520 mmcc: clock-controller@c8c000 <<
1521 compatible = "qcom,mm <<
1522 reg = <0x0c8c0000 0x4 <<
1523 #clock-cells = <1>; <<
1524 #reset-cells = <1>; <<
1525 #power-domain-cells = <<
1526 clock-names = "xo", <<
1527 "slee <<
1528 "gpll <<
1529 "gpll <<
1530 "dsi0 <<
1531 "dsi0 <<
1532 "dsi1 <<
1533 "dsi1 <<
1534 "dp_l <<
1535 "dp_v <<
1536 clocks = <&rpmcc RPM_ <<
1537 <&sle <<
1538 <&gcc <<
1539 <&gcc <<
1540 <&mds <<
1541 <&mds <<
1542 <0>, <<
1543 <0>, <<
1544 <0>, <<
1545 <0>; <<
1546 }; <<
1547 <<
1548 mdss: display-subsystem@c9000 <<
1549 compatible = "qcom,md <<
1550 reg = <0x0c900000 0x1 <<
1551 <0x0c9b0000 0x1 <<
1552 reg-names = "mdss_phy <<
1553 <<
1554 power-domains = <&mmc <<
1555 <<
1556 clocks = <&mmcc MDSS_ <<
1557 <&mmcc MDSS_ <<
1558 <&mmcc MDSS_ <<
1559 <&mmcc MDSS_ <<
1560 clock-names = "iface" <<
1561 "bus", <<
1562 "vsync" <<
1563 "core"; <<
1564 <<
1565 interrupts = <GIC_SPI <<
1566 <<
1567 interrupt-controller; <<
1568 #interrupt-cells = <1 <<
1569 <<
1570 #address-cells = <1>; <<
1571 #size-cells = <1>; <<
1572 ranges; <<
1573 status = "disabled"; <<
1574 <<
1575 mdp: display-controll <<
1576 compatible = <<
1577 reg = <0x0c90 <<
1578 reg-names = " <<
1579 <<
1580 interrupt-par <<
1581 interrupts = <<
1582 <<
1583 assigned-cloc <<
1584 <<
1585 assigned-cloc <<
1586 <<
1587 clocks = <&mm <<
1588 <&mm <<
1589 <&mm <<
1590 <&mm <<
1591 clock-names = <<
1592 <<
1593 <<
1594 <<
1595 <<
1596 interconnects <<
1597 <<
1598 <<
1599 interconnect- <<
1600 <<
1601 <<
1602 iommus = <&mm <<
1603 operating-poi <<
1604 power-domains <<
1605 <<
1606 ports { <<
1607 #addr <<
1608 #size <<
1609 <<
1610 port@ <<
1611 <<
1612 <<
1613 <<
1614 <<
1615 }; <<
1616 }; <<
1617 <<
1618 mdp_opp_table <<
1619 compa <<
1620 <<
1621 opp-1 <<
1622 <<
1623 <<
1624 <<
1625 }; <<
1626 opp-2 <<
1627 <<
1628 <<
1629 <<
1630 }; <<
1631 opp-3 <<
1632 <<
1633 <<
1634 <<
1635 }; <<
1636 opp-3 <<
1637 <<
1638 <<
1639 <<
1640 }; <<
1641 opp-4 <<
1642 <<
1643 <<
1644 <<
1645 }; <<
1646 }; <<
1647 }; <<
1648 <<
1649 mdss_dsi0: dsi@c99400 <<
1650 compatible = <<
1651 <<
1652 reg = <0x0c99 <<
1653 reg-names = " <<
1654 <<
1655 operating-poi <<
1656 power-domains <<
1657 <<
1658 interrupt-par <<
1659 interrupts = <<
1660 <<
1661 assigned-cloc <<
1662 <<
1663 assigned-cloc <<
1664 <<
1665 <<
1666 clocks = <&mm <<
1667 <&mm <<
1668 <&mm <<
1669 <&mm <<
1670 <&mm <<
1671 <&mm <<
1672 <&mm <<
1673 <&mm <<
1674 <&mm <<
1675 clock-names = <<
1676 <<
1677 <<
1678 <<
1679 <<
1680 <<
1681 <<
1682 <<
1683 <<
1684 <<
1685 phys = <&mdss <<
1686 <<
1687 status = "dis <<
1688 <<
1689 ports { <<
1690 #addr <<
1691 #size <<
1692 <<
1693 port@ <<
1694 <<
1695 <<
1696 <<
1697 <<
1698 }; <<
1699 <<
1700 port@ <<
1701 <<
1702 <<
1703 <<
1704 }; <<
1705 }; <<
1706 }; <<
1707 <<
1708 mdss_dsi0_phy: phy@c9 <<
1709 compatible = <<
1710 reg = <0x0c99 <<
1711 <0x0c99 <<
1712 <0x0c99 <<
1713 reg-names = " <<
1714 " <<
1715 " <<
1716 <<
1717 #clock-cells <<
1718 #phy-cells = <<
1719 <<
1720 clocks = <&mm <<
1721 clock-names = <<
1722 status = "dis <<
1723 }; <<
1724 }; 831 };
1725 832
1726 blsp1_dma: dma-controller@c14 833 blsp1_dma: dma-controller@c144000 {
1727 compatible = "qcom,ba 834 compatible = "qcom,bam-v1.7.0";
1728 reg = <0x0c144000 0x1 835 reg = <0x0c144000 0x1f000>;
1729 interrupts = <GIC_SPI 836 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
1730 clocks = <&gcc GCC_BL 837 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
1731 clock-names = "bam_cl 838 clock-names = "bam_clk";
1732 #dma-cells = <1>; 839 #dma-cells = <1>;
1733 qcom,ee = <0>; 840 qcom,ee = <0>;
1734 qcom,controlled-remot 841 qcom,controlled-remotely;
1735 num-channels = <18>; 842 num-channels = <18>;
1736 qcom,num-ees = <4>; 843 qcom,num-ees = <4>;
1737 }; 844 };
1738 845
1739 blsp1_uart1: serial@c16f000 { 846 blsp1_uart1: serial@c16f000 {
1740 compatible = "qcom,ms 847 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1741 reg = <0x0c16f000 0x2 848 reg = <0x0c16f000 0x200>;
1742 interrupts = <GIC_SPI 849 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1743 clocks = <&gcc GCC_BL 850 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
1744 <&gcc GCC_BL 851 <&gcc GCC_BLSP1_AHB_CLK>;
1745 clock-names = "core", 852 clock-names = "core", "iface";
1746 dmas = <&blsp1_dma 0> 853 dmas = <&blsp1_dma 0>, <&blsp1_dma 1>;
1747 dma-names = "tx", "rx 854 dma-names = "tx", "rx";
1748 pinctrl-names = "defa 855 pinctrl-names = "default", "sleep";
1749 pinctrl-0 = <&blsp1_u 856 pinctrl-0 = <&blsp1_uart1_default>;
1750 pinctrl-1 = <&blsp1_u 857 pinctrl-1 = <&blsp1_uart1_sleep>;
1751 status = "disabled"; 858 status = "disabled";
1752 }; 859 };
1753 860
1754 blsp1_uart2: serial@c170000 { 861 blsp1_uart2: serial@c170000 {
1755 compatible = "qcom,ms 862 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1756 reg = <0x0c170000 0x1 863 reg = <0x0c170000 0x1000>;
1757 interrupts = <GIC_SPI 864 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1758 clocks = <&gcc GCC_BL 865 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
1759 <&gcc GCC_BL 866 <&gcc GCC_BLSP1_AHB_CLK>;
1760 clock-names = "core", 867 clock-names = "core", "iface";
1761 dmas = <&blsp1_dma 2> 868 dmas = <&blsp1_dma 2>, <&blsp1_dma 3>;
1762 dma-names = "tx", "rx 869 dma-names = "tx", "rx";
1763 pinctrl-names = "defa 870 pinctrl-names = "default";
1764 pinctrl-0 = <&blsp1_u 871 pinctrl-0 = <&blsp1_uart2_default>;
1765 status = "disabled"; 872 status = "disabled";
1766 }; 873 };
1767 874
1768 blsp_i2c1: i2c@c175000 { 875 blsp_i2c1: i2c@c175000 {
1769 compatible = "qcom,i2 876 compatible = "qcom,i2c-qup-v2.2.1";
1770 reg = <0x0c175000 0x6 877 reg = <0x0c175000 0x600>;
1771 interrupts = <GIC_SPI 878 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1772 879
1773 clocks = <&gcc GCC_BL 880 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
1774 <&gcc 881 <&gcc GCC_BLSP1_AHB_CLK>;
1775 clock-names = "core", 882 clock-names = "core", "iface";
1776 clock-frequency = <40 883 clock-frequency = <400000>;
1777 dmas = <&blsp1_dma 4> <<
1778 dma-names = "tx", "rx <<
1779 884
1780 pinctrl-names = "defa 885 pinctrl-names = "default", "sleep";
1781 pinctrl-0 = <&i2c1_de 886 pinctrl-0 = <&i2c1_default>;
1782 pinctrl-1 = <&i2c1_sl 887 pinctrl-1 = <&i2c1_sleep>;
1783 #address-cells = <1>; 888 #address-cells = <1>;
1784 #size-cells = <0>; 889 #size-cells = <0>;
1785 status = "disabled"; 890 status = "disabled";
1786 }; 891 };
1787 892
1788 blsp_i2c2: i2c@c176000 { 893 blsp_i2c2: i2c@c176000 {
1789 compatible = "qcom,i2 894 compatible = "qcom,i2c-qup-v2.2.1";
1790 reg = <0x0c176000 0x6 895 reg = <0x0c176000 0x600>;
1791 interrupts = <GIC_SPI 896 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1792 897
1793 clocks = <&gcc GCC_BL 898 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
1794 <&gcc GCC_BL 899 <&gcc GCC_BLSP1_AHB_CLK>;
1795 clock-names = "core", 900 clock-names = "core", "iface";
1796 clock-frequency = <40 901 clock-frequency = <400000>;
1797 dmas = <&blsp1_dma 6> <<
1798 dma-names = "tx", "rx <<
1799 902
1800 pinctrl-names = "defa 903 pinctrl-names = "default", "sleep";
1801 pinctrl-0 = <&i2c2_de 904 pinctrl-0 = <&i2c2_default>;
1802 pinctrl-1 = <&i2c2_sl 905 pinctrl-1 = <&i2c2_sleep>;
1803 #address-cells = <1>; 906 #address-cells = <1>;
1804 #size-cells = <0>; 907 #size-cells = <0>;
1805 status = "disabled"; 908 status = "disabled";
1806 }; 909 };
1807 910
1808 blsp_i2c3: i2c@c177000 { 911 blsp_i2c3: i2c@c177000 {
1809 compatible = "qcom,i2 912 compatible = "qcom,i2c-qup-v2.2.1";
1810 reg = <0x0c177000 0x6 913 reg = <0x0c177000 0x600>;
1811 interrupts = <GIC_SPI 914 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1812 915
1813 clocks = <&gcc GCC_BL 916 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
1814 <&gcc GCC_BL 917 <&gcc GCC_BLSP1_AHB_CLK>;
1815 clock-names = "core", 918 clock-names = "core", "iface";
1816 clock-frequency = <40 919 clock-frequency = <400000>;
1817 dmas = <&blsp1_dma 8> <<
1818 dma-names = "tx", "rx <<
1819 920
1820 pinctrl-names = "defa 921 pinctrl-names = "default", "sleep";
1821 pinctrl-0 = <&i2c3_de 922 pinctrl-0 = <&i2c3_default>;
1822 pinctrl-1 = <&i2c3_sl 923 pinctrl-1 = <&i2c3_sleep>;
1823 #address-cells = <1>; 924 #address-cells = <1>;
1824 #size-cells = <0>; 925 #size-cells = <0>;
1825 status = "disabled"; 926 status = "disabled";
1826 }; 927 };
1827 928
1828 blsp_i2c4: i2c@c178000 { 929 blsp_i2c4: i2c@c178000 {
1829 compatible = "qcom,i2 930 compatible = "qcom,i2c-qup-v2.2.1";
1830 reg = <0x0c178000 0x6 931 reg = <0x0c178000 0x600>;
1831 interrupts = <GIC_SPI 932 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1832 933
1833 clocks = <&gcc GCC_BL 934 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
1834 <&gcc GCC_BL 935 <&gcc GCC_BLSP1_AHB_CLK>;
1835 clock-names = "core", 936 clock-names = "core", "iface";
1836 clock-frequency = <40 937 clock-frequency = <400000>;
1837 dmas = <&blsp1_dma 10 <<
1838 dma-names = "tx", "rx <<
1839 938
1840 pinctrl-names = "defa 939 pinctrl-names = "default", "sleep";
1841 pinctrl-0 = <&i2c4_de 940 pinctrl-0 = <&i2c4_default>;
1842 pinctrl-1 = <&i2c4_sl 941 pinctrl-1 = <&i2c4_sleep>;
1843 #address-cells = <1>; 942 #address-cells = <1>;
1844 #size-cells = <0>; 943 #size-cells = <0>;
1845 status = "disabled"; 944 status = "disabled";
1846 }; 945 };
1847 946
1848 blsp2_dma: dma-controller@c18 947 blsp2_dma: dma-controller@c184000 {
1849 compatible = "qcom,ba 948 compatible = "qcom,bam-v1.7.0";
1850 reg = <0x0c184000 0x1 949 reg = <0x0c184000 0x1f000>;
1851 interrupts = <GIC_SPI 950 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
1852 clocks = <&gcc GCC_BL 951 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
1853 clock-names = "bam_cl 952 clock-names = "bam_clk";
1854 #dma-cells = <1>; 953 #dma-cells = <1>;
1855 qcom,ee = <0>; 954 qcom,ee = <0>;
1856 qcom,controlled-remot 955 qcom,controlled-remotely;
1857 num-channels = <18>; 956 num-channels = <18>;
1858 qcom,num-ees = <4>; 957 qcom,num-ees = <4>;
1859 }; 958 };
1860 959
1861 blsp2_uart1: serial@c1af000 { 960 blsp2_uart1: serial@c1af000 {
1862 compatible = "qcom,ms 961 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1863 reg = <0x0c1af000 0x2 962 reg = <0x0c1af000 0x200>;
1864 interrupts = <GIC_SPI 963 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1865 clocks = <&gcc GCC_BL 964 clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>,
1866 <&gcc GCC_BL 965 <&gcc GCC_BLSP2_AHB_CLK>;
1867 clock-names = "core", 966 clock-names = "core", "iface";
1868 dmas = <&blsp2_dma 0> 967 dmas = <&blsp2_dma 0>, <&blsp2_dma 1>;
1869 dma-names = "tx", "rx 968 dma-names = "tx", "rx";
1870 pinctrl-names = "defa 969 pinctrl-names = "default", "sleep";
1871 pinctrl-0 = <&blsp2_u !! 970 pinctrl-0 = <&blsp2_uart1_tx_active &blsp2_uart1_rxcts_active
1872 pinctrl-1 = <&blsp2_u !! 971 &blsp2_uart1_rfr_active>;
>> 972 pinctrl-1 = <&blsp2_uart1_tx_sleep &blsp2_uart1_rxcts_sleep
>> 973 &blsp2_uart1_rfr_sleep>;
1873 status = "disabled"; 974 status = "disabled";
1874 }; 975 };
1875 976
1876 blsp_i2c5: i2c@c1b5000 { 977 blsp_i2c5: i2c@c1b5000 {
1877 compatible = "qcom,i2 978 compatible = "qcom,i2c-qup-v2.2.1";
1878 reg = <0x0c1b5000 0x6 979 reg = <0x0c1b5000 0x600>;
1879 interrupts = <GIC_SPI 980 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1880 981
1881 clocks = <&gcc GCC_BL 982 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
1882 <&gcc GCC_BL 983 <&gcc GCC_BLSP2_AHB_CLK>;
1883 clock-names = "core", 984 clock-names = "core", "iface";
1884 clock-frequency = <40 985 clock-frequency = <400000>;
1885 dmas = <&blsp2_dma 4> <<
1886 dma-names = "tx", "rx <<
1887 986
1888 pinctrl-names = "defa 987 pinctrl-names = "default", "sleep";
1889 pinctrl-0 = <&i2c5_de 988 pinctrl-0 = <&i2c5_default>;
1890 pinctrl-1 = <&i2c5_sl 989 pinctrl-1 = <&i2c5_sleep>;
1891 #address-cells = <1>; 990 #address-cells = <1>;
1892 #size-cells = <0>; 991 #size-cells = <0>;
1893 status = "disabled"; 992 status = "disabled";
1894 }; 993 };
1895 994
1896 blsp_i2c6: i2c@c1b6000 { 995 blsp_i2c6: i2c@c1b6000 {
1897 compatible = "qcom,i2 996 compatible = "qcom,i2c-qup-v2.2.1";
1898 reg = <0x0c1b6000 0x6 997 reg = <0x0c1b6000 0x600>;
1899 interrupts = <GIC_SPI 998 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1900 999
1901 clocks = <&gcc GCC_BL 1000 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
1902 <&gcc GCC_BL 1001 <&gcc GCC_BLSP2_AHB_CLK>;
1903 clock-names = "core", 1002 clock-names = "core", "iface";
1904 clock-frequency = <40 1003 clock-frequency = <400000>;
1905 dmas = <&blsp2_dma 6> <<
1906 dma-names = "tx", "rx <<
1907 1004
1908 pinctrl-names = "defa 1005 pinctrl-names = "default", "sleep";
1909 pinctrl-0 = <&i2c6_de 1006 pinctrl-0 = <&i2c6_default>;
1910 pinctrl-1 = <&i2c6_sl 1007 pinctrl-1 = <&i2c6_sleep>;
1911 #address-cells = <1>; 1008 #address-cells = <1>;
1912 #size-cells = <0>; 1009 #size-cells = <0>;
1913 status = "disabled"; 1010 status = "disabled";
1914 }; 1011 };
1915 1012
1916 blsp_i2c7: i2c@c1b7000 { 1013 blsp_i2c7: i2c@c1b7000 {
1917 compatible = "qcom,i2 1014 compatible = "qcom,i2c-qup-v2.2.1";
1918 reg = <0x0c1b7000 0x6 1015 reg = <0x0c1b7000 0x600>;
1919 interrupts = <GIC_SPI 1016 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1920 1017
1921 clocks = <&gcc GCC_BL 1018 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
1922 <&gcc GCC_BL 1019 <&gcc GCC_BLSP2_AHB_CLK>;
1923 clock-names = "core", 1020 clock-names = "core", "iface";
1924 clock-frequency = <40 1021 clock-frequency = <400000>;
1925 dmas = <&blsp2_dma 8> <<
1926 dma-names = "tx", "rx <<
1927 1022
1928 pinctrl-names = "defa 1023 pinctrl-names = "default", "sleep";
1929 pinctrl-0 = <&i2c7_de 1024 pinctrl-0 = <&i2c7_default>;
1930 pinctrl-1 = <&i2c7_sl 1025 pinctrl-1 = <&i2c7_sleep>;
1931 #address-cells = <1>; 1026 #address-cells = <1>;
1932 #size-cells = <0>; 1027 #size-cells = <0>;
1933 status = "disabled"; 1028 status = "disabled";
1934 }; 1029 };
1935 1030
1936 blsp_i2c8: i2c@c1b8000 { 1031 blsp_i2c8: i2c@c1b8000 {
1937 compatible = "qcom,i2 1032 compatible = "qcom,i2c-qup-v2.2.1";
1938 reg = <0x0c1b8000 0x6 1033 reg = <0x0c1b8000 0x600>;
1939 interrupts = <GIC_SPI 1034 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1940 1035
1941 clocks = <&gcc GCC_BL 1036 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>,
1942 <&gcc GCC_BL 1037 <&gcc GCC_BLSP2_AHB_CLK>;
1943 clock-names = "core", 1038 clock-names = "core", "iface";
1944 clock-frequency = <40 1039 clock-frequency = <400000>;
1945 dmas = <&blsp2_dma 10 <<
1946 dma-names = "tx", "rx <<
1947 1040
1948 pinctrl-names = "defa 1041 pinctrl-names = "default", "sleep";
1949 pinctrl-0 = <&i2c8_de 1042 pinctrl-0 = <&i2c8_default>;
1950 pinctrl-1 = <&i2c8_sl 1043 pinctrl-1 = <&i2c8_sleep>;
1951 #address-cells = <1>; 1044 #address-cells = <1>;
1952 #size-cells = <0>; 1045 #size-cells = <0>;
1953 status = "disabled"; 1046 status = "disabled";
1954 }; 1047 };
1955 1048
1956 sram@146bf000 { <<
1957 compatible = "qcom,sd <<
1958 reg = <0x146bf000 0x1 <<
1959 <<
1960 #address-cells = <1>; <<
1961 #size-cells = <1>; <<
1962 <<
1963 ranges = <0 0x146bf00 <<
1964 <<
1965 pil-reloc@94c { <<
1966 compatible = <<
1967 reg = <0x94c <<
1968 }; <<
1969 }; <<
1970 <<
1971 camss: camss@ca00020 { <<
1972 compatible = "qcom,sd <<
1973 reg = <0x0ca00020 0x1 <<
1974 <0x0ca30000 0x1 <<
1975 <0x0ca30400 0x1 <<
1976 <0x0ca30800 0x1 <<
1977 <0x0ca30c00 0x1 <<
1978 <0x0c824000 0x1 <<
1979 <0x0ca00120 0x4 <<
1980 <0x0c825000 0x1 <<
1981 <0x0ca00124 0x4 <<
1982 <0x0c826000 0x1 <<
1983 <0x0ca00128 0x4 <<
1984 <0x0ca31000 0x5 <<
1985 <0x0ca10000 0x1 <<
1986 <0x0ca14000 0x1 <<
1987 reg-names = "csi_clk_ <<
1988 "csid0", <<
1989 "csid1", <<
1990 "csid2", <<
1991 "csid3", <<
1992 "csiphy0" <<
1993 "csiphy0_ <<
1994 "csiphy1" <<
1995 "csiphy1_ <<
1996 "csiphy2" <<
1997 "csiphy2_ <<
1998 "ispif", <<
1999 "vfe0", <<
2000 "vfe1"; <<
2001 interrupts = <GIC_SPI <<
2002 <GIC_SPI <<
2003 <GIC_SPI <<
2004 <GIC_SPI <<
2005 <GIC_SPI <<
2006 <GIC_SPI <<
2007 <GIC_SPI <<
2008 <GIC_SPI <<
2009 <GIC_SPI <<
2010 <GIC_SPI <<
2011 interrupt-names = "cs <<
2012 "cs <<
2013 "cs <<
2014 "cs <<
2015 "cs <<
2016 "cs <<
2017 "cs <<
2018 "is <<
2019 "vf <<
2020 "vf <<
2021 clocks = <&mmcc CAMSS <<
2022 <&mmcc CAMSS <<
2023 <&mmcc CAMSS <<
2024 <&mmcc CAMSS <<
2025 <&mmcc CAMSS <<
2026 <&mmcc CAMSS <<
2027 <&mmcc CAMSS <<
2028 <&mmcc CAMSS <<
2029 <&mmcc CAMSS <<
2030 <&mmcc CAMSS <<
2031 <&mmcc CAMSS <<
2032 <&mmcc CAMSS <<
2033 <&mmcc CAMSS <<
2034 <&mmcc CAMSS <<
2035 <&mmcc CAMSS <<
2036 <&mmcc CAMSS <<
2037 <&mmcc CAMSS <<
2038 <&mmcc CAMSS <<
2039 <&mmcc CAMSS <<
2040 <&mmcc CAMSS <<
2041 <&mmcc CAMSS <<
2042 <&mmcc CAMSS <<
2043 <&mmcc CAMSS <<
2044 <&mmcc CAMSS <<
2045 <&mmcc CAMSS <<
2046 <&mmcc CAMSS <<
2047 <&mmcc CAMSS <<
2048 <&mmcc CAMSS <<
2049 <&mmcc CSIPH <<
2050 <&mmcc CAMSS <<
2051 <&mmcc CAMSS <<
2052 <&mmcc CAMSS <<
2053 <&mmcc THROT <<
2054 <&mmcc CAMSS <<
2055 <&mmcc CAMSS <<
2056 <&mmcc CAMSS <<
2057 <&mmcc CAMSS <<
2058 <&mmcc CAMSS <<
2059 <&mmcc CAMSS <<
2060 <&mmcc CAMSS <<
2061 <&mmcc CAMSS <<
2062 <&mmcc CAMSS <<
2063 clock-names = "ahb", <<
2064 "cphy_c <<
2065 "cphy_c <<
2066 "cphy_c <<
2067 "cphy_c <<
2068 "csi0_a <<
2069 "csi0", <<
2070 "csi0_p <<
2071 "csi0_p <<
2072 "csi0_r <<
2073 "csi1_a <<
2074 "csi1", <<
2075 "csi1_p <<
2076 "csi1_p <<
2077 "csi1_r <<
2078 "csi2_a <<
2079 "csi2", <<
2080 "csi2_p <<
2081 "csi2_p <<
2082 "csi2_r <<
2083 "csi3_a <<
2084 "csi3", <<
2085 "csi3_p <<
2086 "csi3_p <<
2087 "csi3_r <<
2088 "csiphy <<
2089 "csiphy <<
2090 "csiphy <<
2091 "csiphy <<
2092 "csi_vf <<
2093 "csi_vf <<
2094 "ispif_ <<
2095 "thrott <<
2096 "top_ah <<
2097 "vfe0_a <<
2098 "vfe0", <<
2099 "vfe0_s <<
2100 "vfe1_a <<
2101 "vfe1", <<
2102 "vfe1_s <<
2103 "vfe_ah <<
2104 "vfe_ax <<
2105 interconnects = <&mno <<
2106 interconnect-names = <<
2107 iommus = <&mmss_smmu <<
2108 <&mmss_smmu <<
2109 <&mmss_smmu <<
2110 <&mmss_smmu <<
2111 power-domains = <&mmc <<
2112 <&mmc <<
2113 status = "disabled"; <<
2114 <<
2115 ports { <<
2116 #address-cell <<
2117 #size-cells = <<
2118 }; <<
2119 }; <<
2120 <<
2121 cci: cci@ca0c000 { <<
2122 compatible = "qcom,ms <<
2123 #address-cells = <1>; <<
2124 #size-cells = <0>; <<
2125 reg = <0x0ca0c000 0x1 <<
2126 interrupts = <GIC_SPI <<
2127 <<
2128 assigned-clocks = <&m <<
2129 <&m <<
2130 assigned-clock-rates <<
2131 clocks = <&mmcc CAMSS <<
2132 <&mmcc CAMSS <<
2133 <&mmcc CAMSS <<
2134 <&mmcc CAMSS <<
2135 clock-names = "camss_ <<
2136 "cci_ah <<
2137 "cci", <<
2138 "camss_ <<
2139 <<
2140 pinctrl-names = "defa <<
2141 pinctrl-0 = <&cci0_de <<
2142 power-domains = <&mmc <<
2143 status = "disabled"; <<
2144 <<
2145 cci_i2c0: i2c-bus@0 { <<
2146 reg = <0>; <<
2147 clock-frequen <<
2148 #address-cell <<
2149 #size-cells = <<
2150 }; <<
2151 <<
2152 cci_i2c1: i2c-bus@1 { <<
2153 reg = <1>; <<
2154 clock-frequen <<
2155 #address-cell <<
2156 #size-cells = <<
2157 }; <<
2158 }; <<
2159 <<
2160 venus: video-codec@cc00000 { <<
2161 compatible = "qcom,sd <<
2162 reg = <0x0cc00000 0xf <<
2163 clocks = <&mmcc VIDEO <<
2164 <&mmcc VIDEO <<
2165 <&mmcc VIDEO <<
2166 <&mmcc THROT <<
2167 clock-names = "core", <<
2168 interconnects = <&gno <<
2169 <&mno <<
2170 interconnect-names = <<
2171 interrupts = <GIC_SPI <<
2172 iommus = <&mmss_smmu <<
2173 <&mmss_smmu <<
2174 <&mmss_smmu <<
2175 <&mmss_smmu <<
2176 <&mmss_smmu <<
2177 <&mmss_smmu <<
2178 <&mmss_smmu <<
2179 <&mmss_smmu <<
2180 <&mmss_smmu <<
2181 <&mmss_smmu <<
2182 <&mmss_smmu <<
2183 <&mmss_smmu <<
2184 <&mmss_smmu <<
2185 <&mmss_smmu <<
2186 <&mmss_smmu <<
2187 <&mmss_smmu <<
2188 <&mmss_smmu <<
2189 <&mmss_smmu <<
2190 <&mmss_smmu <<
2191 <&mmss_smmu <<
2192 memory-region = <&ven <<
2193 power-domains = <&mmc <<
2194 status = "disabled"; <<
2195 <<
2196 video-decoder { <<
2197 compatible = <<
2198 clocks = <&mm <<
2199 clock-names = <<
2200 power-domains <<
2201 }; <<
2202 <<
2203 video-encoder { <<
2204 compatible = <<
2205 clocks = <&mm <<
2206 clock-names = <<
2207 power-domains <<
2208 }; <<
2209 }; <<
2210 <<
2211 mmss_smmu: iommu@cd00000 { 1049 mmss_smmu: iommu@cd00000 {
2212 compatible = "qcom,sd 1050 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
2213 reg = <0x0cd00000 0x4 1051 reg = <0x0cd00000 0x40000>;
2214 <<
2215 clocks = <&mmcc MNOC_ <<
2216 <&mmcc BIMC_ <<
2217 <&mmcc BIMC_ <<
2218 clock-names = "iface- <<
2219 "bus-sm <<
2220 #global-interrupts = <<
2221 #iommu-cells = <1>; 1052 #iommu-cells = <1>;
2222 1053
>> 1054 #global-interrupts = <2>;
2223 interrupts = 1055 interrupts =
2224 <GIC_SPI 229 1056 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
2225 <GIC_SPI 231 1057 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
2226 1058
2227 <GIC_SPI 263 1059 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
2228 <GIC_SPI 266 1060 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
2229 <GIC_SPI 267 1061 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
2230 <GIC_SPI 268 1062 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
2231 <GIC_SPI 244 1063 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
2232 <GIC_SPI 245 1064 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
2233 <GIC_SPI 247 1065 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
2234 <GIC_SPI 248 1066 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
2235 <GIC_SPI 249 1067 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
2236 <GIC_SPI 250 1068 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
2237 <GIC_SPI 251 1069 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
2238 <GIC_SPI 252 1070 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
2239 <GIC_SPI 253 1071 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
2240 <GIC_SPI 254 1072 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
2241 <GIC_SPI 255 1073 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
2242 <GIC_SPI 256 1074 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
2243 <GIC_SPI 260 1075 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
2244 <GIC_SPI 261 1076 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
2245 <GIC_SPI 262 1077 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
2246 <GIC_SPI 272 1078 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
2247 <GIC_SPI 273 1079 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
2248 <GIC_SPI 274 1080 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
2249 <GIC_SPI 275 1081 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
2250 <GIC_SPI 276 1082 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
2251 1083
2252 status = "disabled"; 1084 status = "disabled";
2253 }; 1085 };
2254 1086
2255 adsp_pil: remoteproc@15700000 <<
2256 compatible = "qcom,sd <<
2257 reg = <0x15700000 0x4 <<
2258 <<
2259 interrupts-extended = <<
2260 <&intc GIC_SP <<
2261 <&adsp_smp2p_ <<
2262 <&adsp_smp2p_ <<
2263 <&adsp_smp2p_ <<
2264 <&adsp_smp2p_ <<
2265 interrupt-names = "wd <<
2266 "ha <<
2267 <<
2268 clocks = <&rpmcc RPM_ <<
2269 clock-names = "xo"; <<
2270 <<
2271 memory-region = <&ads <<
2272 power-domains = <&rpm <<
2273 power-domain-names = <<
2274 <<
2275 qcom,smem-states = <& <<
2276 qcom,smem-state-names <<
2277 <<
2278 glink-edge { <<
2279 interrupts = <<
2280 <<
2281 label = "lpas <<
2282 mboxes = <&ap <<
2283 qcom,remote-p <<
2284 <<
2285 apr { <<
2286 compa <<
2287 qcom, <<
2288 qcom, <<
2289 #addr <<
2290 #size <<
2291 <<
2292 servi <<
2293 <<
2294 <<
2295 }; <<
2296 <<
2297 q6afe <<
2298 <<
2299 <<
2300 <<
2301 <<
2302 <<
2303 <<
2304 <<
2305 <<
2306 }; <<
2307 <<
2308 q6asm <<
2309 <<
2310 <<
2311 <<
2312 <<
2313 <<
2314 <<
2315 <<
2316 <<
2317 <<
2318 }; <<
2319 <<
2320 q6adm <<
2321 <<
2322 <<
2323 <<
2324 <<
2325 <<
2326 <<
2327 }; <<
2328 }; <<
2329 }; <<
2330 }; <<
2331 <<
2332 gnoc: interconnect@17900000 { <<
2333 compatible = "qcom,sd <<
2334 reg = <0x17900000 0xe <<
2335 #interconnect-cells = <<
2336 }; <<
2337 <<
2338 apcs_glb: mailbox@17911000 { 1087 apcs_glb: mailbox@17911000 {
2339 compatible = "qcom,sd !! 1088 compatible = "qcom,sdm660-apcs-hmss-global";
2340 "qcom,ms <<
2341 reg = <0x17911000 0x1 1089 reg = <0x17911000 0x1000>;
2342 1090
2343 #mbox-cells = <1>; 1091 #mbox-cells = <1>;
2344 }; 1092 };
2345 1093
2346 timer@17920000 { 1094 timer@17920000 {
2347 #address-cells = <1>; 1095 #address-cells = <1>;
2348 #size-cells = <1>; 1096 #size-cells = <1>;
2349 ranges; 1097 ranges;
2350 compatible = "arm,arm 1098 compatible = "arm,armv7-timer-mem";
2351 reg = <0x17920000 0x1 1099 reg = <0x17920000 0x1000>;
2352 clock-frequency = <19 1100 clock-frequency = <19200000>;
2353 1101
2354 frame@17921000 { 1102 frame@17921000 {
2355 frame-number 1103 frame-number = <0>;
2356 interrupts = !! 1104 interrupts = <0 8 0x4>,
2357 !! 1105 <0 7 0x4>;
2358 reg = <0x1792 1106 reg = <0x17921000 0x1000>,
2359 <0x17 1107 <0x17922000 0x1000>;
2360 }; 1108 };
2361 1109
2362 frame@17923000 { 1110 frame@17923000 {
2363 frame-number 1111 frame-number = <1>;
2364 interrupts = !! 1112 interrupts = <0 9 0x4>;
2365 reg = <0x1792 1113 reg = <0x17923000 0x1000>;
2366 status = "dis 1114 status = "disabled";
2367 }; 1115 };
2368 1116
2369 frame@17924000 { 1117 frame@17924000 {
2370 frame-number 1118 frame-number = <2>;
2371 interrupts = !! 1119 interrupts = <0 10 0x4>;
2372 reg = <0x1792 1120 reg = <0x17924000 0x1000>;
2373 status = "dis 1121 status = "disabled";
2374 }; 1122 };
2375 1123
2376 frame@17925000 { 1124 frame@17925000 {
2377 frame-number 1125 frame-number = <3>;
2378 interrupts = !! 1126 interrupts = <0 11 0x4>;
2379 reg = <0x1792 1127 reg = <0x17925000 0x1000>;
2380 status = "dis 1128 status = "disabled";
2381 }; 1129 };
2382 1130
2383 frame@17926000 { 1131 frame@17926000 {
2384 frame-number 1132 frame-number = <4>;
2385 interrupts = !! 1133 interrupts = <0 12 0x4>;
2386 reg = <0x1792 1134 reg = <0x17926000 0x1000>;
2387 status = "dis 1135 status = "disabled";
2388 }; 1136 };
2389 1137
2390 frame@17927000 { 1138 frame@17927000 {
2391 frame-number 1139 frame-number = <5>;
2392 interrupts = !! 1140 interrupts = <0 13 0x4>;
2393 reg = <0x1792 1141 reg = <0x17927000 0x1000>;
2394 status = "dis 1142 status = "disabled";
2395 }; 1143 };
2396 1144
2397 frame@17928000 { 1145 frame@17928000 {
2398 frame-number 1146 frame-number = <6>;
2399 interrupts = !! 1147 interrupts = <0 14 0x4>;
2400 reg = <0x1792 1148 reg = <0x17928000 0x1000>;
2401 status = "dis 1149 status = "disabled";
2402 }; 1150 };
2403 }; 1151 };
2404 1152
2405 intc: interrupt-controller@17 1153 intc: interrupt-controller@17a00000 {
2406 compatible = "arm,gic 1154 compatible = "arm,gic-v3";
2407 reg = <0x17a00000 0x1 1155 reg = <0x17a00000 0x10000>, /* GICD */
2408 <0x17b00000 1156 <0x17b00000 0x100000>; /* GICR * 8 */
2409 #interrupt-cells = <3 1157 #interrupt-cells = <3>;
2410 #address-cells = <1>; 1158 #address-cells = <1>;
2411 #size-cells = <1>; 1159 #size-cells = <1>;
2412 ranges; 1160 ranges;
2413 interrupt-controller; 1161 interrupt-controller;
2414 #redistributor-region 1162 #redistributor-regions = <1>;
2415 redistributor-stride 1163 redistributor-stride = <0x0 0x20000>;
2416 interrupts = <GIC_PPI 1164 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
2417 }; 1165 };
2418 }; 1166 };
2419 1167
2420 sound: sound { !! 1168 tcsr_mutex: hwlock {
2421 }; !! 1169 compatible = "qcom,tcsr-mutex";
2422 !! 1170 syscon = <&tcsr_mutex_regs 0 0x1000>;
2423 thermal-zones { !! 1171 #hwlock-cells = <1>;
2424 aoss-thermal { <<
2425 polling-delay-passive <<
2426 <<
2427 thermal-sensors = <&t <<
2428 <<
2429 trips { <<
2430 aoss_alert0: <<
2431 tempe <<
2432 hyste <<
2433 type <<
2434 }; <<
2435 }; <<
2436 }; <<
2437 <<
2438 cpuss0-thermal { <<
2439 polling-delay-passive <<
2440 <<
2441 thermal-sensors = <&t <<
2442 <<
2443 trips { <<
2444 cpuss0_alert0 <<
2445 tempe <<
2446 hyste <<
2447 type <<
2448 }; <<
2449 }; <<
2450 }; <<
2451 <<
2452 cpuss1-thermal { <<
2453 polling-delay-passive <<
2454 <<
2455 thermal-sensors = <&t <<
2456 <<
2457 trips { <<
2458 cpuss1_alert0 <<
2459 tempe <<
2460 hyste <<
2461 type <<
2462 }; <<
2463 }; <<
2464 }; <<
2465 <<
2466 cpu0-thermal { <<
2467 polling-delay-passive <<
2468 <<
2469 thermal-sensors = <&t <<
2470 <<
2471 trips { <<
2472 cpu0_alert0: <<
2473 tempe <<
2474 hyste <<
2475 type <<
2476 }; <<
2477 <<
2478 cpu0_crit: cp <<
2479 tempe <<
2480 hyste <<
2481 type <<
2482 }; <<
2483 }; <<
2484 }; <<
2485 <<
2486 cpu1-thermal { <<
2487 polling-delay-passive <<
2488 <<
2489 thermal-sensors = <&t <<
2490 <<
2491 trips { <<
2492 cpu1_alert0: <<
2493 tempe <<
2494 hyste <<
2495 type <<
2496 }; <<
2497 <<
2498 cpu1_crit: cp <<
2499 tempe <<
2500 hyste <<
2501 type <<
2502 }; <<
2503 }; <<
2504 }; <<
2505 <<
2506 cpu2-thermal { <<
2507 polling-delay-passive <<
2508 <<
2509 thermal-sensors = <&t <<
2510 <<
2511 trips { <<
2512 cpu2_alert0: <<
2513 tempe <<
2514 hyste <<
2515 type <<
2516 }; <<
2517 <<
2518 cpu2_crit: cp <<
2519 tempe <<
2520 hyste <<
2521 type <<
2522 }; <<
2523 }; <<
2524 }; <<
2525 <<
2526 cpu3-thermal { <<
2527 polling-delay-passive <<
2528 <<
2529 thermal-sensors = <&t <<
2530 <<
2531 trips { <<
2532 cpu3_alert0: <<
2533 tempe <<
2534 hyste <<
2535 type <<
2536 }; <<
2537 <<
2538 cpu3_crit: cp <<
2539 tempe <<
2540 hyste <<
2541 type <<
2542 }; <<
2543 }; <<
2544 }; <<
2545 <<
2546 /* <<
2547 * According to what downstre <<
2548 * the entire power efficient <<
2549 * only a single thermal sens <<
2550 */ <<
2551 <<
2552 pwr-cluster-thermal { <<
2553 polling-delay-passive <<
2554 <<
2555 thermal-sensors = <&t <<
2556 <<
2557 trips { <<
2558 pwr_cluster_a <<
2559 tempe <<
2560 hyste <<
2561 type <<
2562 }; <<
2563 <<
2564 pwr_cluster_c <<
2565 tempe <<
2566 hyste <<
2567 type <<
2568 }; <<
2569 }; <<
2570 }; <<
2571 <<
2572 gpu-thermal { <<
2573 polling-delay-passive <<
2574 <<
2575 thermal-sensors = <&t <<
2576 <<
2577 cooling-maps { <<
2578 map0 { <<
2579 trip <<
2580 cooli <<
2581 }; <<
2582 }; <<
2583 <<
2584 trips { <<
2585 gpu_alert0: t <<
2586 tempe <<
2587 hyste <<
2588 type <<
2589 }; <<
2590 <<
2591 trip-point1 { <<
2592 tempe <<
2593 hyste <<
2594 type <<
2595 }; <<
2596 <<
2597 trip-point2 { <<
2598 tempe <<
2599 hyste <<
2600 type <<
2601 }; <<
2602 }; <<
2603 }; <<
2604 }; 1172 };
2605 1173
2606 timer { 1174 timer {
2607 compatible = "arm,armv8-timer 1175 compatible = "arm,armv8-timer";
2608 interrupts = <GIC_PPI 1 (GIC_ !! 1176 interrupts = <GIC_PPI 1 0xf08>,
2609 <GIC_PPI 2 (GIC_ !! 1177 <GIC_PPI 2 0xf08>,
2610 <GIC_PPI 3 (GIC_ !! 1178 <GIC_PPI 3 0xf08>,
2611 <GIC_PPI 0 (GIC_ !! 1179 <GIC_PPI 0 0xf08>;
2612 }; 1180 };
2613 }; 1181 };
2614 1182
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