1 // SPDX-License-Identifier: BSD-3-Clause 1 // SPDX-License-Identifier: BSD-3-Clause
2 /* 2 /*
3 * Copyright (c) 2020, Konrad Dybcio <konradybc 3 * Copyright (c) 2020, Konrad Dybcio <konradybcio@gmail.com>
4 * Copyright (c) 2020, AngeloGioacchino Del Re< 4 * Copyright (c) 2020, AngeloGioacchino Del Regno <kholk11@gmail.com>
5 */ 5 */
6 6
7 #include <dt-bindings/clock/qcom,gcc-sdm660.h> 7 #include <dt-bindings/clock/qcom,gcc-sdm660.h>
8 #include <dt-bindings/clock/qcom,gpucc-sdm660. 8 #include <dt-bindings/clock/qcom,gpucc-sdm660.h>
9 #include <dt-bindings/clock/qcom,mmcc-sdm660.h 9 #include <dt-bindings/clock/qcom,mmcc-sdm660.h>
10 #include <dt-bindings/clock/qcom,rpmcc.h> 10 #include <dt-bindings/clock/qcom,rpmcc.h>
11 #include <dt-bindings/firmware/qcom,scm.h> <<
12 #include <dt-bindings/interconnect/qcom,sdm660 <<
13 #include <dt-bindings/power/qcom-rpmpd.h> 11 #include <dt-bindings/power/qcom-rpmpd.h>
14 #include <dt-bindings/gpio/gpio.h> 12 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/interrupt-controller/arm 13 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/thermal/thermal.h> <<
17 #include <dt-bindings/soc/qcom,apr.h> 14 #include <dt-bindings/soc/qcom,apr.h>
18 15
19 / { 16 / {
20 interrupt-parent = <&intc>; 17 interrupt-parent = <&intc>;
21 18
22 #address-cells = <2>; 19 #address-cells = <2>;
23 #size-cells = <2>; 20 #size-cells = <2>;
24 21
25 aliases { 22 aliases {
26 mmc1 = &sdhc_1; 23 mmc1 = &sdhc_1;
27 mmc2 = &sdhc_2; 24 mmc2 = &sdhc_2;
28 }; 25 };
29 26
30 chosen { }; 27 chosen { };
31 28
32 clocks { 29 clocks {
33 xo_board: xo-board { 30 xo_board: xo-board {
34 compatible = "fixed-cl 31 compatible = "fixed-clock";
35 #clock-cells = <0>; 32 #clock-cells = <0>;
36 clock-frequency = <192 33 clock-frequency = <19200000>;
37 clock-output-names = " 34 clock-output-names = "xo_board";
38 }; 35 };
39 36
40 sleep_clk: sleep-clk { 37 sleep_clk: sleep-clk {
41 compatible = "fixed-cl 38 compatible = "fixed-clock";
42 #clock-cells = <0>; 39 #clock-cells = <0>;
43 clock-frequency = <327 40 clock-frequency = <32764>;
44 clock-output-names = " 41 clock-output-names = "sleep_clk";
45 }; 42 };
46 }; 43 };
47 44
48 cpus { 45 cpus {
49 #address-cells = <2>; 46 #address-cells = <2>;
50 #size-cells = <0>; 47 #size-cells = <0>;
51 48
52 CPU0: cpu@100 { 49 CPU0: cpu@100 {
53 device_type = "cpu"; 50 device_type = "cpu";
54 compatible = "arm,cort 51 compatible = "arm,cortex-a53";
55 reg = <0x0 0x100>; 52 reg = <0x0 0x100>;
56 enable-method = "psci" 53 enable-method = "psci";
57 cpu-idle-states = <&PE 54 cpu-idle-states = <&PERF_CPU_SLEEP_0
58 55 &PERF_CPU_SLEEP_1
59 56 &PERF_CLUSTER_SLEEP_0
60 57 &PERF_CLUSTER_SLEEP_1
61 58 &PERF_CLUSTER_SLEEP_2>;
62 capacity-dmips-mhz = < 59 capacity-dmips-mhz = <1126>;
63 #cooling-cells = <2>; 60 #cooling-cells = <2>;
64 next-level-cache = <&L 61 next-level-cache = <&L2_1>;
65 L2_1: l2-cache { 62 L2_1: l2-cache {
66 compatible = " 63 compatible = "cache";
67 cache-level = 64 cache-level = <2>;
68 cache-unified; <<
69 }; 65 };
70 }; 66 };
71 67
72 CPU1: cpu@101 { 68 CPU1: cpu@101 {
73 device_type = "cpu"; 69 device_type = "cpu";
74 compatible = "arm,cort 70 compatible = "arm,cortex-a53";
75 reg = <0x0 0x101>; 71 reg = <0x0 0x101>;
76 enable-method = "psci" 72 enable-method = "psci";
77 cpu-idle-states = <&PE 73 cpu-idle-states = <&PERF_CPU_SLEEP_0
78 74 &PERF_CPU_SLEEP_1
79 75 &PERF_CLUSTER_SLEEP_0
80 76 &PERF_CLUSTER_SLEEP_1
81 77 &PERF_CLUSTER_SLEEP_2>;
82 capacity-dmips-mhz = < 78 capacity-dmips-mhz = <1126>;
83 #cooling-cells = <2>; 79 #cooling-cells = <2>;
84 next-level-cache = <&L 80 next-level-cache = <&L2_1>;
85 }; 81 };
86 82
87 CPU2: cpu@102 { 83 CPU2: cpu@102 {
88 device_type = "cpu"; 84 device_type = "cpu";
89 compatible = "arm,cort 85 compatible = "arm,cortex-a53";
90 reg = <0x0 0x102>; 86 reg = <0x0 0x102>;
91 enable-method = "psci" 87 enable-method = "psci";
92 cpu-idle-states = <&PE 88 cpu-idle-states = <&PERF_CPU_SLEEP_0
93 89 &PERF_CPU_SLEEP_1
94 90 &PERF_CLUSTER_SLEEP_0
95 91 &PERF_CLUSTER_SLEEP_1
96 92 &PERF_CLUSTER_SLEEP_2>;
97 capacity-dmips-mhz = < 93 capacity-dmips-mhz = <1126>;
98 #cooling-cells = <2>; 94 #cooling-cells = <2>;
99 next-level-cache = <&L 95 next-level-cache = <&L2_1>;
100 }; 96 };
101 97
102 CPU3: cpu@103 { 98 CPU3: cpu@103 {
103 device_type = "cpu"; 99 device_type = "cpu";
104 compatible = "arm,cort 100 compatible = "arm,cortex-a53";
105 reg = <0x0 0x103>; 101 reg = <0x0 0x103>;
106 enable-method = "psci" 102 enable-method = "psci";
107 cpu-idle-states = <&PE 103 cpu-idle-states = <&PERF_CPU_SLEEP_0
108 104 &PERF_CPU_SLEEP_1
109 105 &PERF_CLUSTER_SLEEP_0
110 106 &PERF_CLUSTER_SLEEP_1
111 107 &PERF_CLUSTER_SLEEP_2>;
112 capacity-dmips-mhz = < 108 capacity-dmips-mhz = <1126>;
113 #cooling-cells = <2>; 109 #cooling-cells = <2>;
114 next-level-cache = <&L 110 next-level-cache = <&L2_1>;
115 }; 111 };
116 112
117 CPU4: cpu@0 { 113 CPU4: cpu@0 {
118 device_type = "cpu"; 114 device_type = "cpu";
119 compatible = "arm,cort 115 compatible = "arm,cortex-a53";
120 reg = <0x0 0x0>; 116 reg = <0x0 0x0>;
121 enable-method = "psci" 117 enable-method = "psci";
122 cpu-idle-states = <&PW 118 cpu-idle-states = <&PWR_CPU_SLEEP_0
123 119 &PWR_CPU_SLEEP_1
124 120 &PWR_CLUSTER_SLEEP_0
125 121 &PWR_CLUSTER_SLEEP_1
126 122 &PWR_CLUSTER_SLEEP_2>;
127 capacity-dmips-mhz = < 123 capacity-dmips-mhz = <1024>;
128 #cooling-cells = <2>; 124 #cooling-cells = <2>;
129 next-level-cache = <&L 125 next-level-cache = <&L2_0>;
130 L2_0: l2-cache { 126 L2_0: l2-cache {
131 compatible = " 127 compatible = "cache";
132 cache-level = 128 cache-level = <2>;
133 cache-unified; <<
134 }; 129 };
135 }; 130 };
136 131
137 CPU5: cpu@1 { 132 CPU5: cpu@1 {
138 device_type = "cpu"; 133 device_type = "cpu";
139 compatible = "arm,cort 134 compatible = "arm,cortex-a53";
140 reg = <0x0 0x1>; 135 reg = <0x0 0x1>;
141 enable-method = "psci" 136 enable-method = "psci";
142 cpu-idle-states = <&PW 137 cpu-idle-states = <&PWR_CPU_SLEEP_0
143 138 &PWR_CPU_SLEEP_1
144 139 &PWR_CLUSTER_SLEEP_0
145 140 &PWR_CLUSTER_SLEEP_1
146 141 &PWR_CLUSTER_SLEEP_2>;
147 capacity-dmips-mhz = < 142 capacity-dmips-mhz = <1024>;
148 #cooling-cells = <2>; 143 #cooling-cells = <2>;
149 next-level-cache = <&L 144 next-level-cache = <&L2_0>;
150 }; 145 };
151 146
152 CPU6: cpu@2 { 147 CPU6: cpu@2 {
153 device_type = "cpu"; 148 device_type = "cpu";
154 compatible = "arm,cort 149 compatible = "arm,cortex-a53";
155 reg = <0x0 0x2>; 150 reg = <0x0 0x2>;
156 enable-method = "psci" 151 enable-method = "psci";
157 cpu-idle-states = <&PW 152 cpu-idle-states = <&PWR_CPU_SLEEP_0
158 153 &PWR_CPU_SLEEP_1
159 154 &PWR_CLUSTER_SLEEP_0
160 155 &PWR_CLUSTER_SLEEP_1
161 156 &PWR_CLUSTER_SLEEP_2>;
162 capacity-dmips-mhz = < 157 capacity-dmips-mhz = <1024>;
163 #cooling-cells = <2>; 158 #cooling-cells = <2>;
164 next-level-cache = <&L 159 next-level-cache = <&L2_0>;
165 }; 160 };
166 161
167 CPU7: cpu@3 { 162 CPU7: cpu@3 {
168 device_type = "cpu"; 163 device_type = "cpu";
169 compatible = "arm,cort 164 compatible = "arm,cortex-a53";
170 reg = <0x0 0x3>; 165 reg = <0x0 0x3>;
171 enable-method = "psci" 166 enable-method = "psci";
172 cpu-idle-states = <&PW 167 cpu-idle-states = <&PWR_CPU_SLEEP_0
173 168 &PWR_CPU_SLEEP_1
174 169 &PWR_CLUSTER_SLEEP_0
175 170 &PWR_CLUSTER_SLEEP_1
176 171 &PWR_CLUSTER_SLEEP_2>;
177 capacity-dmips-mhz = < 172 capacity-dmips-mhz = <1024>;
178 #cooling-cells = <2>; 173 #cooling-cells = <2>;
179 next-level-cache = <&L 174 next-level-cache = <&L2_0>;
180 }; 175 };
181 176
182 cpu-map { 177 cpu-map {
183 cluster0 { 178 cluster0 {
184 core0 { 179 core0 {
185 cpu = 180 cpu = <&CPU4>;
186 }; 181 };
187 182
188 core1 { 183 core1 {
189 cpu = 184 cpu = <&CPU5>;
190 }; 185 };
191 186
192 core2 { 187 core2 {
193 cpu = 188 cpu = <&CPU6>;
194 }; 189 };
195 190
196 core3 { 191 core3 {
197 cpu = 192 cpu = <&CPU7>;
198 }; 193 };
199 }; 194 };
200 195
201 cluster1 { 196 cluster1 {
202 core0 { 197 core0 {
203 cpu = 198 cpu = <&CPU0>;
204 }; 199 };
205 200
206 core1 { 201 core1 {
207 cpu = 202 cpu = <&CPU1>;
208 }; 203 };
209 204
210 core2 { 205 core2 {
211 cpu = 206 cpu = <&CPU2>;
212 }; 207 };
213 208
214 core3 { 209 core3 {
215 cpu = 210 cpu = <&CPU3>;
216 }; 211 };
217 }; 212 };
218 }; 213 };
219 214
220 idle-states { 215 idle-states {
221 entry-method = "psci"; 216 entry-method = "psci";
222 217
223 PWR_CPU_SLEEP_0: cpu-s 218 PWR_CPU_SLEEP_0: cpu-sleep-0-0 {
224 compatible = " 219 compatible = "arm,idle-state";
225 idle-state-nam 220 idle-state-name = "pwr-retention";
226 arm,psci-suspe 221 arm,psci-suspend-param = <0x40000002>;
227 entry-latency- 222 entry-latency-us = <338>;
228 exit-latency-u 223 exit-latency-us = <423>;
229 min-residency- 224 min-residency-us = <200>;
230 }; 225 };
231 226
232 PWR_CPU_SLEEP_1: cpu-s 227 PWR_CPU_SLEEP_1: cpu-sleep-0-1 {
233 compatible = " 228 compatible = "arm,idle-state";
234 idle-state-nam 229 idle-state-name = "pwr-power-collapse";
235 arm,psci-suspe 230 arm,psci-suspend-param = <0x40000003>;
236 entry-latency- 231 entry-latency-us = <515>;
237 exit-latency-u 232 exit-latency-us = <1821>;
238 min-residency- 233 min-residency-us = <1000>;
239 local-timer-st 234 local-timer-stop;
240 }; 235 };
241 236
242 PERF_CPU_SLEEP_0: cpu- 237 PERF_CPU_SLEEP_0: cpu-sleep-1-0 {
243 compatible = " 238 compatible = "arm,idle-state";
244 idle-state-nam 239 idle-state-name = "perf-retention";
245 arm,psci-suspe 240 arm,psci-suspend-param = <0x40000002>;
246 entry-latency- 241 entry-latency-us = <154>;
247 exit-latency-u 242 exit-latency-us = <87>;
248 min-residency- 243 min-residency-us = <200>;
249 }; 244 };
250 245
251 PERF_CPU_SLEEP_1: cpu- 246 PERF_CPU_SLEEP_1: cpu-sleep-1-1 {
252 compatible = " 247 compatible = "arm,idle-state";
253 idle-state-nam 248 idle-state-name = "perf-power-collapse";
254 arm,psci-suspe 249 arm,psci-suspend-param = <0x40000003>;
255 entry-latency- 250 entry-latency-us = <262>;
256 exit-latency-u 251 exit-latency-us = <301>;
257 min-residency- 252 min-residency-us = <1000>;
258 local-timer-st 253 local-timer-stop;
259 }; 254 };
260 255
261 PWR_CLUSTER_SLEEP_0: c 256 PWR_CLUSTER_SLEEP_0: cluster-sleep-0-0 {
262 compatible = " 257 compatible = "arm,idle-state";
263 idle-state-nam 258 idle-state-name = "pwr-cluster-dynamic-retention";
264 arm,psci-suspe 259 arm,psci-suspend-param = <0x400000F2>;
265 entry-latency- 260 entry-latency-us = <284>;
266 exit-latency-u 261 exit-latency-us = <384>;
267 min-residency- 262 min-residency-us = <9987>;
268 local-timer-st 263 local-timer-stop;
269 }; 264 };
270 265
271 PWR_CLUSTER_SLEEP_1: c 266 PWR_CLUSTER_SLEEP_1: cluster-sleep-0-1 {
272 compatible = " 267 compatible = "arm,idle-state";
273 idle-state-nam 268 idle-state-name = "pwr-cluster-retention";
274 arm,psci-suspe 269 arm,psci-suspend-param = <0x400000F3>;
275 entry-latency- 270 entry-latency-us = <338>;
276 exit-latency-u 271 exit-latency-us = <423>;
277 min-residency- 272 min-residency-us = <9987>;
278 local-timer-st 273 local-timer-stop;
279 }; 274 };
280 275
281 PWR_CLUSTER_SLEEP_2: c 276 PWR_CLUSTER_SLEEP_2: cluster-sleep-0-2 {
282 compatible = " 277 compatible = "arm,idle-state";
283 idle-state-nam 278 idle-state-name = "pwr-cluster-retention";
284 arm,psci-suspe 279 arm,psci-suspend-param = <0x400000F4>;
285 entry-latency- 280 entry-latency-us = <515>;
286 exit-latency-u 281 exit-latency-us = <1821>;
287 min-residency- 282 min-residency-us = <9987>;
288 local-timer-st 283 local-timer-stop;
289 }; 284 };
290 285
291 PERF_CLUSTER_SLEEP_0: 286 PERF_CLUSTER_SLEEP_0: cluster-sleep-1-0 {
292 compatible = " 287 compatible = "arm,idle-state";
293 idle-state-nam 288 idle-state-name = "perf-cluster-dynamic-retention";
294 arm,psci-suspe 289 arm,psci-suspend-param = <0x400000F2>;
295 entry-latency- 290 entry-latency-us = <272>;
296 exit-latency-u 291 exit-latency-us = <329>;
297 min-residency- 292 min-residency-us = <9987>;
298 local-timer-st 293 local-timer-stop;
299 }; 294 };
300 295
301 PERF_CLUSTER_SLEEP_1: 296 PERF_CLUSTER_SLEEP_1: cluster-sleep-1-1 {
302 compatible = " 297 compatible = "arm,idle-state";
303 idle-state-nam 298 idle-state-name = "perf-cluster-retention";
304 arm,psci-suspe 299 arm,psci-suspend-param = <0x400000F3>;
305 entry-latency- 300 entry-latency-us = <332>;
306 exit-latency-u 301 exit-latency-us = <368>;
307 min-residency- 302 min-residency-us = <9987>;
308 local-timer-st 303 local-timer-stop;
309 }; 304 };
310 305
311 PERF_CLUSTER_SLEEP_2: 306 PERF_CLUSTER_SLEEP_2: cluster-sleep-1-2 {
312 compatible = " 307 compatible = "arm,idle-state";
313 idle-state-nam 308 idle-state-name = "perf-cluster-retention";
314 arm,psci-suspe 309 arm,psci-suspend-param = <0x400000F4>;
315 entry-latency- 310 entry-latency-us = <545>;
316 exit-latency-u 311 exit-latency-us = <1609>;
317 min-residency- 312 min-residency-us = <9987>;
318 local-timer-st 313 local-timer-stop;
319 }; 314 };
320 }; 315 };
321 }; 316 };
322 317
323 firmware { 318 firmware {
324 scm { 319 scm {
325 compatible = "qcom,scm 320 compatible = "qcom,scm-msm8998", "qcom,scm";
326 }; 321 };
327 }; 322 };
328 323
329 memory@80000000 { 324 memory@80000000 {
330 device_type = "memory"; 325 device_type = "memory";
331 /* We expect the bootloader to 326 /* We expect the bootloader to fill in the reg */
332 reg = <0x0 0x80000000 0x0 0x0> 327 reg = <0x0 0x80000000 0x0 0x0>;
333 }; 328 };
334 329
335 dsi_opp_table: opp-table-dsi { <<
336 compatible = "operating-points <<
337 <<
338 opp-131250000 { <<
339 opp-hz = /bits/ 64 <13 <<
340 required-opps = <&rpmp <<
341 }; <<
342 <<
343 opp-210000000 { <<
344 opp-hz = /bits/ 64 <21 <<
345 required-opps = <&rpmp <<
346 }; <<
347 <<
348 opp-262500000 { <<
349 opp-hz = /bits/ 64 <26 <<
350 required-opps = <&rpmp <<
351 }; <<
352 }; <<
353 <<
354 pmu { 330 pmu {
355 compatible = "arm,armv8-pmuv3" 331 compatible = "arm,armv8-pmuv3";
356 interrupts = <GIC_PPI 6 IRQ_TY 332 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>;
357 }; 333 };
358 334
359 psci { 335 psci {
360 compatible = "arm,psci-1.0"; 336 compatible = "arm,psci-1.0";
361 method = "smc"; 337 method = "smc";
362 }; 338 };
363 339
364 rpm: remoteproc { <<
365 compatible = "qcom,sdm660-rpm- <<
366 <<
367 glink-edge { <<
368 compatible = "qcom,gli <<
369 <<
370 interrupts = <GIC_SPI <<
371 qcom,rpm-msg-ram = <&r <<
372 mboxes = <&apcs_glb 0> <<
373 <<
374 rpm_requests: rpm-requ <<
375 compatible = " <<
376 qcom,glink-cha <<
377 <<
378 rpmcc: clock-c <<
379 compat <<
380 #clock <<
381 }; <<
382 <<
383 rpmpd: power-c <<
384 compat <<
385 #power <<
386 operat <<
387 <<
388 rpmpd_ <<
389 <<
390 <<
391 <<
392 <<
393 <<
394 <<
395 <<
396 <<
397 <<
398 <<
399 <<
400 <<
401 <<
402 <<
403 <<
404 <<
405 <<
406 <<
407 <<
408 <<
409 <<
410 <<
411 <<
412 <<
413 <<
414 <<
415 <<
416 <<
417 <<
418 <<
419 <<
420 <<
421 <<
422 <<
423 <<
424 <<
425 <<
426 }; <<
427 }; <<
428 }; <<
429 }; <<
430 }; <<
431 <<
432 reserved-memory { 340 reserved-memory {
433 #address-cells = <2>; 341 #address-cells = <2>;
434 #size-cells = <2>; 342 #size-cells = <2>;
435 ranges; 343 ranges;
436 344
437 wlan_msa_guard: wlan-msa-guard 345 wlan_msa_guard: wlan-msa-guard@85600000 {
438 reg = <0x0 0x85600000 346 reg = <0x0 0x85600000 0x0 0x100000>;
439 no-map; 347 no-map;
440 }; 348 };
441 349
442 wlan_msa_mem: wlan-msa-mem@857 350 wlan_msa_mem: wlan-msa-mem@85700000 {
443 reg = <0x0 0x85700000 351 reg = <0x0 0x85700000 0x0 0x100000>;
444 no-map; 352 no-map;
445 }; 353 };
446 354
447 qhee_code: qhee-code@85800000 355 qhee_code: qhee-code@85800000 {
448 reg = <0x0 0x85800000 356 reg = <0x0 0x85800000 0x0 0x600000>;
449 no-map; 357 no-map;
450 }; 358 };
451 359
452 rmtfs_mem: memory@85e00000 { 360 rmtfs_mem: memory@85e00000 {
453 compatible = "qcom,rmt 361 compatible = "qcom,rmtfs-mem";
454 reg = <0x0 0x85e00000 362 reg = <0x0 0x85e00000 0x0 0x200000>;
455 no-map; 363 no-map;
456 364
457 qcom,client-id = <1>; 365 qcom,client-id = <1>;
458 qcom,vmid = <QCOM_SCM_ !! 366 qcom,vmid = <15>;
459 }; 367 };
460 368
461 smem_region: smem-mem@86000000 369 smem_region: smem-mem@86000000 {
462 reg = <0 0x86000000 0 370 reg = <0 0x86000000 0 0x200000>;
463 no-map; 371 no-map;
464 }; 372 };
465 373
466 tz_mem: memory@86200000 { 374 tz_mem: memory@86200000 {
467 reg = <0x0 0x86200000 375 reg = <0x0 0x86200000 0x0 0x3300000>;
468 no-map; 376 no-map;
469 }; 377 };
470 378
471 mpss_region: mpss@8ac00000 { 379 mpss_region: mpss@8ac00000 {
472 reg = <0x0 0x8ac00000 380 reg = <0x0 0x8ac00000 0x0 0x7e00000>;
473 no-map; 381 no-map;
474 }; 382 };
475 383
476 adsp_region: adsp@92a00000 { 384 adsp_region: adsp@92a00000 {
477 reg = <0x0 0x92a00000 385 reg = <0x0 0x92a00000 0x0 0x1e00000>;
478 no-map; 386 no-map;
479 }; 387 };
480 388
481 mba_region: mba@94800000 { 389 mba_region: mba@94800000 {
482 reg = <0x0 0x94800000 390 reg = <0x0 0x94800000 0x0 0x200000>;
483 no-map; 391 no-map;
484 }; 392 };
485 393
486 buffer_mem: tzbuffer@94a00000 394 buffer_mem: tzbuffer@94a00000 {
487 reg = <0x0 0x94a00000 395 reg = <0x0 0x94a00000 0x0 0x100000>;
488 no-map; 396 no-map;
489 }; 397 };
490 398
491 venus_region: venus@9f800000 { 399 venus_region: venus@9f800000 {
492 reg = <0x0 0x9f800000 400 reg = <0x0 0x9f800000 0x0 0x800000>;
493 no-map; 401 no-map;
494 }; 402 };
495 403
496 adsp_mem: adsp-region@f6000000 404 adsp_mem: adsp-region@f6000000 {
497 reg = <0x0 0xf6000000 405 reg = <0x0 0xf6000000 0x0 0x800000>;
498 no-map; 406 no-map;
499 }; 407 };
500 408
501 qseecom_mem: qseecom-region@f6 409 qseecom_mem: qseecom-region@f6800000 {
502 reg = <0x0 0xf6800000 410 reg = <0x0 0xf6800000 0x0 0x1400000>;
503 no-map; 411 no-map;
504 }; 412 };
505 413
506 zap_shader_region: gpu@fed0000 414 zap_shader_region: gpu@fed00000 {
507 compatible = "shared-d 415 compatible = "shared-dma-pool";
508 reg = <0x0 0xfed00000 416 reg = <0x0 0xfed00000 0x0 0xa00000>;
509 no-map; 417 no-map;
510 }; 418 };
511 }; 419 };
512 420
>> 421 rpm-glink {
>> 422 compatible = "qcom,glink-rpm";
>> 423
>> 424 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
>> 425 qcom,rpm-msg-ram = <&rpm_msg_ram>;
>> 426 mboxes = <&apcs_glb 0>;
>> 427
>> 428 rpm_requests: rpm-requests {
>> 429 compatible = "qcom,rpm-sdm660";
>> 430 qcom,glink-channels = "rpm_requests";
>> 431
>> 432 rpmcc: clock-controller {
>> 433 compatible = "qcom,rpmcc-sdm660", "qcom,rpmcc";
>> 434 #clock-cells = <1>;
>> 435 };
>> 436
>> 437 rpmpd: power-controller {
>> 438 compatible = "qcom,sdm660-rpmpd";
>> 439 #power-domain-cells = <1>;
>> 440 operating-points-v2 = <&rpmpd_opp_table>;
>> 441
>> 442 rpmpd_opp_table: opp-table {
>> 443 compatible = "operating-points-v2";
>> 444
>> 445 rpmpd_opp_ret: opp1 {
>> 446 opp-level = <RPM_SMD_LEVEL_RETENTION>;
>> 447 };
>> 448
>> 449 rpmpd_opp_ret_plus: opp2 {
>> 450 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
>> 451 };
>> 452
>> 453 rpmpd_opp_min_svs: opp3 {
>> 454 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
>> 455 };
>> 456
>> 457 rpmpd_opp_low_svs: opp4 {
>> 458 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
>> 459 };
>> 460
>> 461 rpmpd_opp_svs: opp5 {
>> 462 opp-level = <RPM_SMD_LEVEL_SVS>;
>> 463 };
>> 464
>> 465 rpmpd_opp_svs_plus: opp6 {
>> 466 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
>> 467 };
>> 468
>> 469 rpmpd_opp_nom: opp7 {
>> 470 opp-level = <RPM_SMD_LEVEL_NOM>;
>> 471 };
>> 472
>> 473 rpmpd_opp_nom_plus: opp8 {
>> 474 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
>> 475 };
>> 476
>> 477 rpmpd_opp_turbo: opp9 {
>> 478 opp-level = <RPM_SMD_LEVEL_TURBO>;
>> 479 };
>> 480 };
>> 481 };
>> 482 };
>> 483 };
>> 484
513 smem: smem { 485 smem: smem {
514 compatible = "qcom,smem"; 486 compatible = "qcom,smem";
515 memory-region = <&smem_region> 487 memory-region = <&smem_region>;
516 hwlocks = <&tcsr_mutex 3>; 488 hwlocks = <&tcsr_mutex 3>;
517 }; 489 };
518 490
519 smp2p-adsp { 491 smp2p-adsp {
520 compatible = "qcom,smp2p"; 492 compatible = "qcom,smp2p";
521 qcom,smem = <443>, <429>; 493 qcom,smem = <443>, <429>;
522 interrupts = <GIC_SPI 158 IRQ_ 494 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
523 mboxes = <&apcs_glb 10>; 495 mboxes = <&apcs_glb 10>;
524 qcom,local-pid = <0>; 496 qcom,local-pid = <0>;
525 qcom,remote-pid = <2>; 497 qcom,remote-pid = <2>;
526 498
527 adsp_smp2p_out: master-kernel 499 adsp_smp2p_out: master-kernel {
528 qcom,entry-name = "mas 500 qcom,entry-name = "master-kernel";
529 #qcom,smem-state-cells 501 #qcom,smem-state-cells = <1>;
530 }; 502 };
531 503
532 adsp_smp2p_in: slave-kernel { 504 adsp_smp2p_in: slave-kernel {
533 qcom,entry-name = "sla 505 qcom,entry-name = "slave-kernel";
534 interrupt-controller; 506 interrupt-controller;
535 #interrupt-cells = <2> 507 #interrupt-cells = <2>;
536 }; 508 };
537 }; 509 };
538 510
539 smp2p-mpss { 511 smp2p-mpss {
540 compatible = "qcom,smp2p"; 512 compatible = "qcom,smp2p";
541 qcom,smem = <435>, <428>; 513 qcom,smem = <435>, <428>;
542 interrupts = <GIC_SPI 451 IRQ_ 514 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
543 mboxes = <&apcs_glb 14>; 515 mboxes = <&apcs_glb 14>;
544 qcom,local-pid = <0>; 516 qcom,local-pid = <0>;
545 qcom,remote-pid = <1>; 517 qcom,remote-pid = <1>;
546 518
547 modem_smp2p_out: master-kernel 519 modem_smp2p_out: master-kernel {
548 qcom,entry-name = "mas 520 qcom,entry-name = "master-kernel";
549 #qcom,smem-state-cells 521 #qcom,smem-state-cells = <1>;
550 }; 522 };
551 523
552 modem_smp2p_in: slave-kernel { 524 modem_smp2p_in: slave-kernel {
553 qcom,entry-name = "sla 525 qcom,entry-name = "slave-kernel";
554 interrupt-controller; 526 interrupt-controller;
555 #interrupt-cells = <2> 527 #interrupt-cells = <2>;
556 }; 528 };
557 }; 529 };
558 530
559 soc@0 { !! 531 soc {
560 #address-cells = <1>; 532 #address-cells = <1>;
561 #size-cells = <1>; 533 #size-cells = <1>;
562 ranges = <0 0 0 0xffffffff>; 534 ranges = <0 0 0 0xffffffff>;
563 compatible = "simple-bus"; 535 compatible = "simple-bus";
564 536
565 gcc: clock-controller@100000 { 537 gcc: clock-controller@100000 {
566 compatible = "qcom,gcc 538 compatible = "qcom,gcc-sdm630";
567 #clock-cells = <1>; 539 #clock-cells = <1>;
568 #reset-cells = <1>; 540 #reset-cells = <1>;
569 #power-domain-cells = 541 #power-domain-cells = <1>;
570 reg = <0x00100000 0x94 542 reg = <0x00100000 0x94000>;
571 543
572 clock-names = "xo", "s 544 clock-names = "xo", "sleep_clk";
573 clocks = <&xo_board>, 545 clocks = <&xo_board>,
574 <&slee 546 <&sleep_clk>;
575 }; 547 };
576 548
577 rpm_msg_ram: sram@778000 { 549 rpm_msg_ram: sram@778000 {
578 compatible = "qcom,rpm 550 compatible = "qcom,rpm-msg-ram";
579 reg = <0x00778000 0x70 551 reg = <0x00778000 0x7000>;
580 }; 552 };
581 553
582 qfprom: qfprom@780000 { 554 qfprom: qfprom@780000 {
583 compatible = "qcom,sdm !! 555 compatible = "qcom,qfprom";
584 reg = <0x00780000 0x62 556 reg = <0x00780000 0x621c>;
585 #address-cells = <1>; 557 #address-cells = <1>;
586 #size-cells = <1>; 558 #size-cells = <1>;
587 559
588 qusb2_hstx_trim: hstx- 560 qusb2_hstx_trim: hstx-trim@240 {
589 reg = <0x243 0 !! 561 reg = <0x240 0x1>;
590 bits = <1 3>; !! 562 bits = <25 3>;
591 }; 563 };
592 564
593 gpu_speed_bin: gpu-spe 565 gpu_speed_bin: gpu-speed-bin@41a0 {
594 reg = <0x41a2 !! 566 reg = <0x41a0 0x1>;
595 bits = <5 7>; !! 567 bits = <21 7>;
596 }; 568 };
597 }; 569 };
598 570
599 rng: rng@793000 { 571 rng: rng@793000 {
600 compatible = "qcom,prn 572 compatible = "qcom,prng-ee";
601 reg = <0x00793000 0x10 573 reg = <0x00793000 0x1000>;
602 clocks = <&gcc GCC_PRN 574 clocks = <&gcc GCC_PRNG_AHB_CLK>;
603 clock-names = "core"; 575 clock-names = "core";
604 }; 576 };
605 577
606 bimc: interconnect@1008000 { 578 bimc: interconnect@1008000 {
607 compatible = "qcom,sdm 579 compatible = "qcom,sdm660-bimc";
608 reg = <0x01008000 0x78 580 reg = <0x01008000 0x78000>;
609 #interconnect-cells = 581 #interconnect-cells = <1>;
>> 582 clock-names = "bus", "bus_a";
>> 583 clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
>> 584 <&rpmcc RPM_SMD_BIMC_A_CLK>;
610 }; 585 };
611 586
612 restart@10ac000 { 587 restart@10ac000 {
613 compatible = "qcom,psh 588 compatible = "qcom,pshold";
614 reg = <0x010ac000 0x4> 589 reg = <0x010ac000 0x4>;
615 }; 590 };
616 591
617 cnoc: interconnect@1500000 { 592 cnoc: interconnect@1500000 {
618 compatible = "qcom,sdm 593 compatible = "qcom,sdm660-cnoc";
619 reg = <0x01500000 0x10 594 reg = <0x01500000 0x10000>;
620 #interconnect-cells = 595 #interconnect-cells = <1>;
>> 596 clock-names = "bus", "bus_a";
>> 597 clocks = <&rpmcc RPM_SMD_CNOC_CLK>,
>> 598 <&rpmcc RPM_SMD_CNOC_A_CLK>;
621 }; 599 };
622 600
623 snoc: interconnect@1626000 { 601 snoc: interconnect@1626000 {
624 compatible = "qcom,sdm 602 compatible = "qcom,sdm660-snoc";
625 reg = <0x01626000 0x70 603 reg = <0x01626000 0x7090>;
626 #interconnect-cells = 604 #interconnect-cells = <1>;
>> 605 clock-names = "bus", "bus_a";
>> 606 clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
>> 607 <&rpmcc RPM_SMD_SNOC_A_CLK>;
627 }; 608 };
628 609
629 anoc2_smmu: iommu@16c0000 { 610 anoc2_smmu: iommu@16c0000 {
630 compatible = "qcom,sdm 611 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
631 reg = <0x016c0000 0x40 612 reg = <0x016c0000 0x40000>;
>> 613
>> 614 assigned-clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
>> 615 assigned-clock-rates = <1000>;
>> 616 clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
>> 617 clock-names = "bus";
632 #global-interrupts = < 618 #global-interrupts = <2>;
633 #iommu-cells = <1>; 619 #iommu-cells = <1>;
634 620
635 interrupts = 621 interrupts =
636 <GIC_SPI 229 I 622 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
637 <GIC_SPI 231 I 623 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
638 624
639 <GIC_SPI 373 I 625 <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>,
640 <GIC_SPI 374 I 626 <GIC_SPI 374 IRQ_TYPE_LEVEL_LOW>,
641 <GIC_SPI 375 I 627 <GIC_SPI 375 IRQ_TYPE_LEVEL_LOW>,
642 <GIC_SPI 376 I 628 <GIC_SPI 376 IRQ_TYPE_LEVEL_LOW>,
643 <GIC_SPI 377 I 629 <GIC_SPI 377 IRQ_TYPE_LEVEL_LOW>,
644 <GIC_SPI 378 I 630 <GIC_SPI 378 IRQ_TYPE_LEVEL_LOW>,
645 <GIC_SPI 462 I 631 <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
646 <GIC_SPI 463 I 632 <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
647 <GIC_SPI 464 I 633 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
648 <GIC_SPI 465 I 634 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
649 <GIC_SPI 466 I 635 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
650 <GIC_SPI 467 I 636 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
651 <GIC_SPI 353 I 637 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
652 <GIC_SPI 354 I 638 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
653 <GIC_SPI 355 I 639 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,
654 <GIC_SPI 356 I 640 <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>,
655 <GIC_SPI 357 I 641 <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>,
656 <GIC_SPI 358 I 642 <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
657 <GIC_SPI 359 I 643 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
658 <GIC_SPI 360 I 644 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
659 <GIC_SPI 442 I 645 <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>,
660 <GIC_SPI 443 I 646 <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>,
661 <GIC_SPI 444 I 647 <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
662 <GIC_SPI 447 I 648 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
663 <GIC_SPI 468 I 649 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
664 <GIC_SPI 469 I 650 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
665 <GIC_SPI 472 I 651 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
666 <GIC_SPI 473 I 652 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
667 <GIC_SPI 474 I 653 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
668 654
669 status = "disabled"; 655 status = "disabled";
670 }; 656 };
671 657
672 a2noc: interconnect@1704000 { 658 a2noc: interconnect@1704000 {
673 compatible = "qcom,sdm 659 compatible = "qcom,sdm660-a2noc";
674 reg = <0x01704000 0xc1 660 reg = <0x01704000 0xc100>;
675 #interconnect-cells = 661 #interconnect-cells = <1>;
676 clock-names = "ipa", !! 662 clock-names = "bus",
>> 663 "bus_a",
>> 664 "ipa",
677 "ufs_axi 665 "ufs_axi",
678 "aggre2_ 666 "aggre2_ufs_axi",
679 "aggre2_ 667 "aggre2_usb3_axi",
680 "cfg_noc 668 "cfg_noc_usb2_axi";
681 clocks = <&rpmcc RPM_S !! 669 clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>,
>> 670 <&rpmcc RPM_SMD_AGGR2_NOC_A_CLK>,
>> 671 <&rpmcc RPM_SMD_IPA_CLK>,
682 <&gcc GCC_UFS 672 <&gcc GCC_UFS_AXI_CLK>,
683 <&gcc GCC_AGG 673 <&gcc GCC_AGGRE2_UFS_AXI_CLK>,
684 <&gcc GCC_AGG 674 <&gcc GCC_AGGRE2_USB3_AXI_CLK>,
685 <&gcc GCC_CFG 675 <&gcc GCC_CFG_NOC_USB2_AXI_CLK>;
686 }; 676 };
687 677
688 mnoc: interconnect@1745000 { 678 mnoc: interconnect@1745000 {
689 compatible = "qcom,sdm 679 compatible = "qcom,sdm660-mnoc";
690 reg = <0x01745000 0xa0 !! 680 reg = <0x01745000 0xA010>;
691 #interconnect-cells = 681 #interconnect-cells = <1>;
692 clock-names = "iface"; !! 682 clock-names = "bus", "bus_a", "iface";
693 clocks = <&mmcc AHB_CL !! 683 clocks = <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK>,
>> 684 <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK_A>,
>> 685 <&mmcc AHB_CLK_SRC>;
694 }; 686 };
695 687
696 tsens: thermal-sensor@10ae000 688 tsens: thermal-sensor@10ae000 {
697 compatible = "qcom,sdm 689 compatible = "qcom,sdm630-tsens", "qcom,tsens-v2";
698 reg = <0x010ae000 0x10 690 reg = <0x010ae000 0x1000>, /* TM */
699 <0x010ad000 691 <0x010ad000 0x1000>; /* SROT */
700 #qcom,sensors = <12>; 692 #qcom,sensors = <12>;
701 interrupts = <GIC_SPI 693 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
702 <GIC_ 694 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
703 interrupt-names = "upl 695 interrupt-names = "uplow", "critical";
704 #thermal-sensor-cells 696 #thermal-sensor-cells = <1>;
705 }; 697 };
706 698
707 tcsr_mutex: hwlock@1f40000 { !! 699 tcsr_mutex_regs: syscon@1f40000 {
708 compatible = "qcom,tcs !! 700 compatible = "syscon";
709 reg = <0x01f40000 0x20 !! 701 reg = <0x01f40000 0x40000>;
710 #hwlock-cells = <1>; <<
711 }; <<
712 <<
713 tcsr_regs_1: syscon@1f60000 { <<
714 compatible = "qcom,sdm <<
715 reg = <0x01f60000 0x20 <<
716 }; 702 };
717 703
718 tlmm: pinctrl@3100000 { 704 tlmm: pinctrl@3100000 {
719 compatible = "qcom,sdm 705 compatible = "qcom,sdm630-pinctrl";
720 reg = <0x03100000 0x40 706 reg = <0x03100000 0x400000>,
721 <0x03500000 707 <0x03500000 0x400000>,
722 <0x03900000 708 <0x03900000 0x400000>;
723 reg-names = "south", " 709 reg-names = "south", "center", "north";
724 interrupts = <GIC_SPI 710 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
725 gpio-controller; 711 gpio-controller;
726 gpio-ranges = <&tlmm 0 712 gpio-ranges = <&tlmm 0 0 114>;
727 #gpio-cells = <2>; 713 #gpio-cells = <2>;
728 interrupt-controller; 714 interrupt-controller;
729 #interrupt-cells = <2> 715 #interrupt-cells = <2>;
730 716
731 blsp1_uart1_default: b !! 717 blsp1_uart1_default: blsp1-uart1-default {
732 pins = "gpio0" 718 pins = "gpio0", "gpio1", "gpio2", "gpio3";
733 function = "bl <<
734 drive-strength 719 drive-strength = <2>;
735 bias-disable; 720 bias-disable;
736 }; 721 };
737 722
738 blsp1_uart1_sleep: bls !! 723 blsp1_uart1_sleep: blsp1-uart1-sleep {
739 pins = "gpio0" 724 pins = "gpio0", "gpio1", "gpio2", "gpio3";
740 function = "gp <<
741 drive-strength 725 drive-strength = <2>;
742 bias-disable; 726 bias-disable;
743 }; 727 };
744 728
745 blsp1_uart2_default: b !! 729 blsp1_uart2_default: blsp1-uart2-default {
746 pins = "gpio4" 730 pins = "gpio4", "gpio5";
747 function = "bl <<
748 drive-strength 731 drive-strength = <2>;
749 bias-disable; 732 bias-disable;
750 }; 733 };
751 734
752 blsp2_uart1_default: b !! 735 blsp2_uart1_default: blsp2-uart1-active {
753 tx-rts-pins { !! 736 tx-rts {
754 pins = 737 pins = "gpio16", "gpio19";
755 functi 738 function = "blsp_uart5";
756 drive- 739 drive-strength = <2>;
757 bias-d 740 bias-disable;
758 }; 741 };
759 742
760 rx-pins { !! 743 rx {
761 /* 744 /*
762 * Avo 745 * Avoid garbage data while BT module
763 * is 746 * is powered off or not driving signal
764 */ 747 */
765 pins = 748 pins = "gpio17";
766 functi 749 function = "blsp_uart5";
767 drive- 750 drive-strength = <2>;
768 bias-p 751 bias-pull-up;
769 }; 752 };
770 753
771 cts-pins { !! 754 cts {
772 /* Mat 755 /* Match the pull of the BT module */
773 pins = 756 pins = "gpio18";
774 functi 757 function = "blsp_uart5";
775 drive- 758 drive-strength = <2>;
776 bias-p 759 bias-pull-down;
777 }; 760 };
778 }; 761 };
779 762
780 blsp2_uart1_sleep: bls !! 763 blsp2_uart1_sleep: blsp2-uart1-sleep {
781 tx-pins { !! 764 tx {
782 pins = 765 pins = "gpio16";
783 functi 766 function = "gpio";
784 drive- 767 drive-strength = <2>;
785 bias-p 768 bias-pull-up;
786 }; 769 };
787 770
788 rx-cts-rts-pin !! 771 rx-cts-rts {
789 pins = 772 pins = "gpio17", "gpio18", "gpio19";
790 functi 773 function = "gpio";
791 drive- 774 drive-strength = <2>;
792 bias-d !! 775 bias-no-pull;
793 }; 776 };
794 }; 777 };
795 778
796 i2c1_default: i2c1-def !! 779 i2c1_default: i2c1-default {
797 pins = "gpio2" 780 pins = "gpio2", "gpio3";
798 function = "bl 781 function = "blsp_i2c1";
799 drive-strength 782 drive-strength = <2>;
800 bias-disable; 783 bias-disable;
801 }; 784 };
802 785
803 i2c1_sleep: i2c1-sleep !! 786 i2c1_sleep: i2c1-sleep {
804 pins = "gpio2" 787 pins = "gpio2", "gpio3";
805 function = "bl 788 function = "blsp_i2c1";
806 drive-strength 789 drive-strength = <2>;
807 bias-pull-up; 790 bias-pull-up;
808 }; 791 };
809 792
810 i2c2_default: i2c2-def !! 793 i2c2_default: i2c2-default {
811 pins = "gpio6" 794 pins = "gpio6", "gpio7";
812 function = "bl 795 function = "blsp_i2c2";
813 drive-strength 796 drive-strength = <2>;
814 bias-disable; 797 bias-disable;
815 }; 798 };
816 799
817 i2c2_sleep: i2c2-sleep !! 800 i2c2_sleep: i2c2-sleep {
818 pins = "gpio6" 801 pins = "gpio6", "gpio7";
819 function = "bl 802 function = "blsp_i2c2";
820 drive-strength 803 drive-strength = <2>;
821 bias-pull-up; 804 bias-pull-up;
822 }; 805 };
823 806
824 i2c3_default: i2c3-def !! 807 i2c3_default: i2c3-default {
825 pins = "gpio10 808 pins = "gpio10", "gpio11";
826 function = "bl 809 function = "blsp_i2c3";
827 drive-strength 810 drive-strength = <2>;
828 bias-disable; 811 bias-disable;
829 }; 812 };
830 813
831 i2c3_sleep: i2c3-sleep !! 814 i2c3_sleep: i2c3-sleep {
832 pins = "gpio10 815 pins = "gpio10", "gpio11";
833 function = "bl 816 function = "blsp_i2c3";
834 drive-strength 817 drive-strength = <2>;
835 bias-pull-up; 818 bias-pull-up;
836 }; 819 };
837 820
838 i2c4_default: i2c4-def !! 821 i2c4_default: i2c4-default {
839 pins = "gpio14 822 pins = "gpio14", "gpio15";
840 function = "bl 823 function = "blsp_i2c4";
841 drive-strength 824 drive-strength = <2>;
842 bias-disable; 825 bias-disable;
843 }; 826 };
844 827
845 i2c4_sleep: i2c4-sleep !! 828 i2c4_sleep: i2c4-sleep {
846 pins = "gpio14 829 pins = "gpio14", "gpio15";
847 function = "bl 830 function = "blsp_i2c4";
848 drive-strength 831 drive-strength = <2>;
849 bias-pull-up; 832 bias-pull-up;
850 }; 833 };
851 834
852 i2c5_default: i2c5-def !! 835 i2c5_default: i2c5-default {
853 pins = "gpio18 836 pins = "gpio18", "gpio19";
854 function = "bl 837 function = "blsp_i2c5";
855 drive-strength 838 drive-strength = <2>;
856 bias-disable; 839 bias-disable;
857 }; 840 };
858 841
859 i2c5_sleep: i2c5-sleep !! 842 i2c5_sleep: i2c5-sleep {
860 pins = "gpio18 843 pins = "gpio18", "gpio19";
861 function = "bl 844 function = "blsp_i2c5";
862 drive-strength 845 drive-strength = <2>;
863 bias-pull-up; 846 bias-pull-up;
864 }; 847 };
865 848
866 i2c6_default: i2c6-def !! 849 i2c6_default: i2c6-default {
867 pins = "gpio22 850 pins = "gpio22", "gpio23";
868 function = "bl 851 function = "blsp_i2c6";
869 drive-strength 852 drive-strength = <2>;
870 bias-disable; 853 bias-disable;
871 }; 854 };
872 855
873 i2c6_sleep: i2c6-sleep !! 856 i2c6_sleep: i2c6-sleep {
874 pins = "gpio22 857 pins = "gpio22", "gpio23";
875 function = "bl 858 function = "blsp_i2c6";
876 drive-strength 859 drive-strength = <2>;
877 bias-pull-up; 860 bias-pull-up;
878 }; 861 };
879 862
880 i2c7_default: i2c7-def !! 863 i2c7_default: i2c7-default {
881 pins = "gpio26 864 pins = "gpio26", "gpio27";
882 function = "bl 865 function = "blsp_i2c7";
883 drive-strength 866 drive-strength = <2>;
884 bias-disable; 867 bias-disable;
885 }; 868 };
886 869
887 i2c7_sleep: i2c7-sleep !! 870 i2c7_sleep: i2c7-sleep {
888 pins = "gpio26 871 pins = "gpio26", "gpio27";
889 function = "bl 872 function = "blsp_i2c7";
890 drive-strength 873 drive-strength = <2>;
891 bias-pull-up; 874 bias-pull-up;
892 }; 875 };
893 876
894 i2c8_default: i2c8-def !! 877 i2c8_default: i2c8-default {
895 pins = "gpio30 878 pins = "gpio30", "gpio31";
896 function = "bl !! 879 function = "blsp_i2c8";
897 drive-strength 880 drive-strength = <2>;
898 bias-disable; 881 bias-disable;
899 }; 882 };
900 883
901 i2c8_sleep: i2c8-sleep !! 884 i2c8_sleep: i2c8-sleep {
902 pins = "gpio30 885 pins = "gpio30", "gpio31";
903 function = "bl !! 886 function = "blsp_i2c8";
904 drive-strength 887 drive-strength = <2>;
905 bias-pull-up; 888 bias-pull-up;
906 }; 889 };
907 890
908 cci0_default: cci0-def !! 891 cci0_default: cci0_default {
909 pins = "gpio36 !! 892 pinmux {
910 function = "cc !! 893 pins = "gpio36","gpio37";
911 bias-pull-up; !! 894 function = "cci_i2c";
912 drive-strength !! 895 };
>> 896
>> 897 pinconf {
>> 898 pins = "gpio36","gpio37";
>> 899 bias-pull-up;
>> 900 drive-strength = <2>;
>> 901 };
913 }; 902 };
914 903
915 cci1_default: cci1-def !! 904 cci1_default: cci1_default {
916 pins = "gpio38 !! 905 pinmux {
917 function = "cc !! 906 pins = "gpio38","gpio39";
918 bias-pull-up; !! 907 function = "cci_i2c";
919 drive-strength !! 908 };
>> 909
>> 910 pinconf {
>> 911 pins = "gpio38","gpio39";
>> 912 bias-pull-up;
>> 913 drive-strength = <2>;
>> 914 };
920 }; 915 };
921 916
922 sdc1_state_on: sdc1-on !! 917 sdc1_state_on: sdc1-on {
923 clk-pins { !! 918 clk {
924 pins = 919 pins = "sdc1_clk";
925 bias-d 920 bias-disable;
926 drive- 921 drive-strength = <16>;
927 }; 922 };
928 923
929 cmd-pins { !! 924 cmd {
930 pins = 925 pins = "sdc1_cmd";
931 bias-p 926 bias-pull-up;
932 drive- 927 drive-strength = <10>;
933 }; 928 };
934 929
935 data-pins { !! 930 data {
936 pins = 931 pins = "sdc1_data";
937 bias-p 932 bias-pull-up;
938 drive- 933 drive-strength = <10>;
939 }; 934 };
940 935
941 rclk-pins { !! 936 rclk {
942 pins = 937 pins = "sdc1_rclk";
943 bias-p 938 bias-pull-down;
944 }; 939 };
945 }; 940 };
946 941
947 sdc1_state_off: sdc1-o !! 942 sdc1_state_off: sdc1-off {
948 clk-pins { !! 943 clk {
949 pins = 944 pins = "sdc1_clk";
950 bias-d 945 bias-disable;
951 drive- 946 drive-strength = <2>;
952 }; 947 };
953 948
954 cmd-pins { !! 949 cmd {
955 pins = 950 pins = "sdc1_cmd";
956 bias-p 951 bias-pull-up;
957 drive- 952 drive-strength = <2>;
958 }; 953 };
959 954
960 data-pins { !! 955 data {
961 pins = 956 pins = "sdc1_data";
962 bias-p 957 bias-pull-up;
963 drive- 958 drive-strength = <2>;
964 }; 959 };
965 960
966 rclk-pins { !! 961 rclk {
967 pins = 962 pins = "sdc1_rclk";
968 bias-p 963 bias-pull-down;
969 }; 964 };
970 }; 965 };
971 966
972 sdc2_state_on: sdc2-on !! 967 sdc2_state_on: sdc2-on {
973 clk-pins { !! 968 clk {
974 pins = 969 pins = "sdc2_clk";
975 bias-d 970 bias-disable;
976 drive- 971 drive-strength = <16>;
977 }; 972 };
978 973
979 cmd-pins { !! 974 cmd {
980 pins = 975 pins = "sdc2_cmd";
981 bias-p 976 bias-pull-up;
982 drive- 977 drive-strength = <10>;
983 }; 978 };
984 979
985 data-pins { !! 980 data {
986 pins = 981 pins = "sdc2_data";
987 bias-p 982 bias-pull-up;
988 drive- 983 drive-strength = <10>;
989 }; 984 };
>> 985
>> 986 sd-cd {
>> 987 pins = "gpio54";
>> 988 bias-pull-up;
>> 989 drive-strength = <2>;
>> 990 };
990 }; 991 };
991 992
992 sdc2_state_off: sdc2-o !! 993 sdc2_state_off: sdc2-off {
993 clk-pins { !! 994 clk {
994 pins = 995 pins = "sdc2_clk";
995 bias-d 996 bias-disable;
996 drive- 997 drive-strength = <2>;
997 }; 998 };
998 999
999 cmd-pins { !! 1000 cmd {
1000 pins 1001 pins = "sdc2_cmd";
1001 bias- 1002 bias-pull-up;
1002 drive 1003 drive-strength = <2>;
1003 }; 1004 };
1004 1005
1005 data-pins { !! 1006 data {
1006 pins 1007 pins = "sdc2_data";
1007 bias- 1008 bias-pull-up;
1008 drive 1009 drive-strength = <2>;
1009 }; 1010 };
1010 }; <<
1011 }; <<
1012 <<
1013 remoteproc_mss: remoteproc@40 <<
1014 compatible = "qcom,sd <<
1015 reg = <0x04080000 0x1 <<
1016 reg-names = "qdsp6", <<
1017 <<
1018 interrupts-extended = <<
1019 <<
1020 <<
1021 <<
1022 <<
1023 <<
1024 interrupt-names = "wd <<
1025 "fa <<
1026 "re <<
1027 "ha <<
1028 "st <<
1029 "sh <<
1030 <<
1031 clocks = <&gcc GCC_MS <<
1032 <&gcc GCC_BI <<
1033 <&gcc GCC_BO <<
1034 <&gcc GPLL0_ <<
1035 <&gcc GCC_MS <<
1036 <&gcc GCC_MS <<
1037 <&rpmcc RPM_ <<
1038 <&rpmcc RPM_ <<
1039 clock-names = "iface" <<
1040 "bus", <<
1041 "mem", <<
1042 "gpll0_ <<
1043 "snoc_a <<
1044 "mnoc_a <<
1045 "qdss", <<
1046 "xo"; <<
1047 <<
1048 qcom,smem-states = <& <<
1049 qcom,smem-state-names <<
1050 <<
1051 resets = <&gcc GCC_MS <<
1052 reset-names = "mss_re <<
1053 1011
1054 qcom,halt-regs = <&tc !! 1012 sd-cd {
1055 !! 1013 pins = "gpio54";
1056 power-domains = <&rpm !! 1014 bias-disable;
1057 <&rpm !! 1015 drive-strength = <2>;
1058 power-domain-names = !! 1016 };
1059 <<
1060 memory-region = <&mba <<
1061 <<
1062 status = "disabled"; <<
1063 <<
1064 glink-edge { <<
1065 interrupts = <<
1066 label = "mode <<
1067 qcom,remote-p <<
1068 mboxes = <&ap <<
1069 }; 1017 };
1070 }; 1018 };
1071 1019
1072 adreno_gpu: gpu@5000000 { 1020 adreno_gpu: gpu@5000000 {
1073 compatible = "qcom,ad 1021 compatible = "qcom,adreno-508.0", "qcom,adreno";
1074 1022
1075 reg = <0x05000000 0x4 1023 reg = <0x05000000 0x40000>;
1076 reg-names = "kgsl_3d0 1024 reg-names = "kgsl_3d0_reg_memory";
1077 1025
1078 interrupts = <GIC_SPI !! 1026 interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
1079 1027
1080 clocks = <&gcc GCC_GP 1028 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
1081 <&gpucc GPUCC 1029 <&gpucc GPUCC_RBBMTIMER_CLK>,
1082 <&gcc GCC_BIM 1030 <&gcc GCC_BIMC_GFX_CLK>,
1083 <&gcc GCC_GPU 1031 <&gcc GCC_GPU_BIMC_GFX_CLK>,
1084 <&gpucc GPUCC 1032 <&gpucc GPUCC_RBCPR_CLK>,
1085 <&gpucc GPUCC 1033 <&gpucc GPUCC_GFX3D_CLK>;
1086 1034
1087 clock-names = "iface" 1035 clock-names = "iface",
1088 "rbbmtimer", 1036 "rbbmtimer",
1089 "mem", 1037 "mem",
1090 "mem_iface", 1038 "mem_iface",
1091 "rbcpr", 1039 "rbcpr",
1092 "core"; 1040 "core";
1093 1041
1094 power-domains = <&rpm 1042 power-domains = <&rpmpd SDM660_VDDMX>;
1095 iommus = <&kgsl_smmu 1043 iommus = <&kgsl_smmu 0>;
1096 1044
1097 nvmem-cells = <&gpu_s 1045 nvmem-cells = <&gpu_speed_bin>;
1098 nvmem-cell-names = "s 1046 nvmem-cell-names = "speed_bin";
1099 1047
1100 interconnects = <&bim !! 1048 interconnects = <&gnoc 1 &bimc 5>;
1101 interconnect-names = 1049 interconnect-names = "gfx-mem";
1102 1050
1103 operating-points-v2 = 1051 operating-points-v2 = <&gpu_sdm630_opp_table>;
1104 #cooling-cells = <2>; <<
1105 <<
1106 status = "disabled"; <<
1107 1052
1108 gpu_sdm630_opp_table: 1053 gpu_sdm630_opp_table: opp-table {
1109 compatible = !! 1054 compatible = "operating-points-v2";
1110 opp-775000000 1055 opp-775000000 {
1111 opp-h 1056 opp-hz = /bits/ 64 <775000000>;
1112 opp-l 1057 opp-level = <RPM_SMD_LEVEL_TURBO>;
1113 opp-p 1058 opp-peak-kBps = <5412000>;
1114 opp-s !! 1059 opp-supported-hw = <0xA2>;
1115 }; 1060 };
1116 opp-647000000 1061 opp-647000000 {
1117 opp-h 1062 opp-hz = /bits/ 64 <647000000>;
1118 opp-l 1063 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
1119 opp-p 1064 opp-peak-kBps = <4068000>;
1120 opp-s !! 1065 opp-supported-hw = <0xFF>;
1121 }; 1066 };
1122 opp-588000000 1067 opp-588000000 {
1123 opp-h 1068 opp-hz = /bits/ 64 <588000000>;
1124 opp-l 1069 opp-level = <RPM_SMD_LEVEL_NOM>;
1125 opp-p 1070 opp-peak-kBps = <3072000>;
1126 opp-s !! 1071 opp-supported-hw = <0xFF>;
1127 }; 1072 };
1128 opp-465000000 1073 opp-465000000 {
1129 opp-h 1074 opp-hz = /bits/ 64 <465000000>;
1130 opp-l 1075 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
1131 opp-p 1076 opp-peak-kBps = <2724000>;
1132 opp-s !! 1077 opp-supported-hw = <0xFF>;
1133 }; 1078 };
1134 opp-370000000 1079 opp-370000000 {
1135 opp-h 1080 opp-hz = /bits/ 64 <370000000>;
1136 opp-l 1081 opp-level = <RPM_SMD_LEVEL_SVS>;
1137 opp-p 1082 opp-peak-kBps = <2188000>;
1138 opp-s !! 1083 opp-supported-hw = <0xFF>;
1139 }; 1084 };
1140 opp-240000000 1085 opp-240000000 {
1141 opp-h 1086 opp-hz = /bits/ 64 <240000000>;
1142 opp-l 1087 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
1143 opp-p 1088 opp-peak-kBps = <1648000>;
1144 opp-s !! 1089 opp-supported-hw = <0xFF>;
1145 }; 1090 };
1146 opp-160000000 1091 opp-160000000 {
1147 opp-h 1092 opp-hz = /bits/ 64 <160000000>;
1148 opp-l 1093 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
1149 opp-p 1094 opp-peak-kBps = <1200000>;
1150 opp-s !! 1095 opp-supported-hw = <0xFF>;
1151 }; 1096 };
1152 }; 1097 };
1153 }; 1098 };
1154 1099
1155 kgsl_smmu: iommu@5040000 { 1100 kgsl_smmu: iommu@5040000 {
1156 compatible = "qcom,sd 1101 compatible = "qcom,sdm630-smmu-v2",
1157 "qcom,ad 1102 "qcom,adreno-smmu", "qcom,smmu-v2";
1158 reg = <0x05040000 0x1 1103 reg = <0x05040000 0x10000>;
1159 1104
1160 /* 1105 /*
1161 * GX GDSC parent is 1106 * GX GDSC parent is CX. We need to bring up CX for SMMU
1162 * but we need both u 1107 * but we need both up for Adreno. On the other hand, we
1163 * need to manage the 1108 * need to manage the GX rpmpd domain in the adreno driver.
1164 * Enable CX/GX GDSCs 1109 * Enable CX/GX GDSCs here so that we can manage just the GX
1165 * RPM Power Domain i 1110 * RPM Power Domain in the Adreno driver.
1166 */ 1111 */
1167 power-domains = <&gpu 1112 power-domains = <&gpucc GPU_GX_GDSC>;
1168 clocks = <&gcc GCC_GP 1113 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
1169 <&gcc GCC_BI 1114 <&gcc GCC_BIMC_GFX_CLK>,
1170 <&gcc GCC_GP 1115 <&gcc GCC_GPU_BIMC_GFX_CLK>;
1171 clock-names = "iface" !! 1116 clock-names = "iface", "mem", "mem_iface";
1172 "mem", <<
1173 "mem_if <<
1174 #global-interrupts = 1117 #global-interrupts = <2>;
1175 #iommu-cells = <1>; 1118 #iommu-cells = <1>;
1176 1119
1177 interrupts = 1120 interrupts =
1178 <GIC_SPI 229 1121 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
1179 <GIC_SPI 231 1122 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
1180 1123
1181 <GIC_SPI 329 1124 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1182 <GIC_SPI 330 1125 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
1183 <GIC_SPI 331 1126 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
1184 <GIC_SPI 332 1127 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
1185 <GIC_SPI 116 1128 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1186 <GIC_SPI 117 1129 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1187 <GIC_SPI 349 1130 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
1188 <GIC_SPI 350 1131 <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>;
1189 1132
1190 status = "disabled"; 1133 status = "disabled";
1191 }; 1134 };
1192 1135
1193 gpucc: clock-controller@50650 1136 gpucc: clock-controller@5065000 {
1194 compatible = "qcom,gp 1137 compatible = "qcom,gpucc-sdm630";
1195 #clock-cells = <1>; 1138 #clock-cells = <1>;
1196 #reset-cells = <1>; 1139 #reset-cells = <1>;
1197 #power-domain-cells = 1140 #power-domain-cells = <1>;
1198 reg = <0x05065000 0x9 1141 reg = <0x05065000 0x9038>;
1199 1142
1200 clocks = <&xo_board>, 1143 clocks = <&xo_board>,
1201 <&gcc GCC_GP 1144 <&gcc GCC_GPU_GPLL0_CLK>,
1202 <&gcc GCC_GP 1145 <&gcc GCC_GPU_GPLL0_DIV_CLK>;
1203 clock-names = "xo", 1146 clock-names = "xo",
1204 "gcc_gp 1147 "gcc_gpu_gpll0_clk",
1205 "gcc_gp 1148 "gcc_gpu_gpll0_div_clk";
1206 status = "disabled"; 1149 status = "disabled";
1207 }; 1150 };
1208 1151
1209 lpass_smmu: iommu@5100000 { 1152 lpass_smmu: iommu@5100000 {
1210 compatible = "qcom,sd 1153 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
1211 reg = <0x05100000 0x4 1154 reg = <0x05100000 0x40000>;
1212 #iommu-cells = <1>; 1155 #iommu-cells = <1>;
1213 1156
1214 #global-interrupts = 1157 #global-interrupts = <2>;
1215 interrupts = 1158 interrupts =
1216 <GIC_SPI 229 1159 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
1217 <GIC_SPI 231 1160 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
1218 1161
1219 <GIC_SPI 226 1162 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
1220 <GIC_SPI 393 1163 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
1221 <GIC_SPI 394 1164 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
1222 <GIC_SPI 395 1165 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
1223 <GIC_SPI 396 1166 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
1224 <GIC_SPI 397 1167 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
1225 <GIC_SPI 398 1168 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
1226 <GIC_SPI 399 1169 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
1227 <GIC_SPI 400 1170 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
1228 <GIC_SPI 401 1171 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
1229 <GIC_SPI 402 1172 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
1230 <GIC_SPI 403 1173 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
1231 <GIC_SPI 137 1174 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
1232 <GIC_SPI 224 1175 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>,
1233 <GIC_SPI 225 1176 <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>,
1234 <GIC_SPI 310 1177 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
1235 <GIC_SPI 404 1178 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
1236 1179
1237 status = "disabled"; 1180 status = "disabled";
1238 }; 1181 };
1239 1182
1240 sram@290000 { 1183 sram@290000 {
1241 compatible = "qcom,rp 1184 compatible = "qcom,rpm-stats";
1242 reg = <0x00290000 0x1 1185 reg = <0x00290000 0x10000>;
1243 }; 1186 };
1244 1187
1245 spmi_bus: spmi@800f000 { 1188 spmi_bus: spmi@800f000 {
1246 compatible = "qcom,sp 1189 compatible = "qcom,spmi-pmic-arb";
1247 reg = <0x0800f000 0x1 !! 1190 reg = <0x0800f000 0x1000>,
1248 <0x08400000 0x1 !! 1191 <0x08400000 0x1000000>,
1249 <0x09400000 0x1 !! 1192 <0x09400000 0x1000000>,
1250 <0x0a400000 0x2 !! 1193 <0x0a400000 0x220000>,
1251 <0x0800a000 0x3 !! 1194 <0x0800a000 0x3000>;
1252 reg-names = "core", " 1195 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1253 interrupt-names = "pe 1196 interrupt-names = "periph_irq";
1254 interrupts = <GIC_SPI 1197 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
1255 qcom,ee = <0>; 1198 qcom,ee = <0>;
1256 qcom,channel = <0>; 1199 qcom,channel = <0>;
1257 #address-cells = <2>; 1200 #address-cells = <2>;
1258 #size-cells = <0>; 1201 #size-cells = <0>;
1259 interrupt-controller; 1202 interrupt-controller;
1260 #interrupt-cells = <4 1203 #interrupt-cells = <4>;
>> 1204 cell-index = <0>;
1261 }; 1205 };
1262 1206
1263 usb3: usb@a8f8800 { 1207 usb3: usb@a8f8800 {
1264 compatible = "qcom,sd 1208 compatible = "qcom,sdm660-dwc3", "qcom,dwc3";
1265 reg = <0x0a8f8800 0x4 1209 reg = <0x0a8f8800 0x400>;
1266 status = "disabled"; 1210 status = "disabled";
1267 #address-cells = <1>; 1211 #address-cells = <1>;
1268 #size-cells = <1>; 1212 #size-cells = <1>;
1269 ranges; 1213 ranges;
1270 1214
1271 clocks = <&gcc GCC_CF 1215 clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>,
1272 <&gcc GCC_US 1216 <&gcc GCC_USB30_MASTER_CLK>,
1273 <&gcc GCC_AG 1217 <&gcc GCC_AGGRE2_USB3_AXI_CLK>,
1274 <&gcc GCC_US !! 1218 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>,
1275 <&gcc GCC_US !! 1219 <&gcc GCC_USB30_MOCK_UTMI_CLK>,
1276 clock-names = "cfg_no !! 1220 <&gcc GCC_USB30_SLEEP_CLK>;
1277 "core", !! 1221 clock-names = "cfg_noc", "core", "iface", "bus",
1278 "iface" !! 1222 "mock_utmi", "sleep";
1279 "sleep" <<
1280 "mock_u <<
1281 1223
1282 assigned-clocks = <&g 1224 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
1283 <&g !! 1225 <&gcc GCC_USB30_MASTER_CLK>,
1284 assigned-clock-rates !! 1226 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
>> 1227 assigned-clock-rates = <19200000>, <120000000>,
>> 1228 <19200000>;
1285 1229
1286 interrupts = <GIC_SPI !! 1230 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
1287 <GIC_SPI <<
1288 <GIC_SPI <<
1289 <GIC_SPI 1231 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
1290 interrupt-names = "pw !! 1232 interrupt-names = "hs_phy_irq", "ss_phy_irq";
1291 "qu <<
1292 "hs <<
1293 "ss <<
1294 1233
1295 power-domains = <&gcc 1234 power-domains = <&gcc USB_30_GDSC>;
>> 1235 qcom,select-utmi-as-pipe-clk;
1296 1236
1297 resets = <&gcc GCC_US 1237 resets = <&gcc GCC_USB_30_BCR>;
1298 1238
1299 usb3_dwc3: usb@a80000 1239 usb3_dwc3: usb@a800000 {
1300 compatible = 1240 compatible = "snps,dwc3";
1301 reg = <0x0a80 1241 reg = <0x0a800000 0xc8d0>;
1302 interrupts = 1242 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
1303 snps,dis_u2_s 1243 snps,dis_u2_susphy_quirk;
1304 snps,dis_enbl 1244 snps,dis_enblslpm_quirk;
1305 snps,parkmode <<
1306 1245
1307 phys = <&qusb !! 1246 /*
1308 phy-names = " !! 1247 * SDM630 technically supports USB3 but I
>> 1248 * haven't seen any devices making use of it.
>> 1249 */
>> 1250 maximum-speed = "high-speed";
>> 1251 phys = <&qusb2phy>;
>> 1252 phy-names = "usb2-phy";
1309 snps,hird-thr 1253 snps,hird-threshold = /bits/ 8 <0>;
1310 }; 1254 };
1311 }; 1255 };
1312 1256
1313 usb3_qmpphy: phy@c010000 { !! 1257 qusb2phy: phy@c012000 {
1314 compatible = "qcom,sd <<
1315 reg = <0x0c010000 0x1 <<
1316 <<
1317 clocks = <&gcc GCC_US <<
1318 <&gcc GCC_US <<
1319 <&gcc GCC_US <<
1320 <&gcc GCC_US <<
1321 clock-names = "aux", <<
1322 "ref", <<
1323 "cfg_ah <<
1324 "pipe"; <<
1325 clock-output-names = <<
1326 #clock-cells = <0>; <<
1327 #phy-cells = <0>; <<
1328 <<
1329 resets = <&gcc GCC_US <<
1330 <&gcc GCC_US <<
1331 reset-names = "phy", <<
1332 "phy_ph <<
1333 <<
1334 qcom,tcsr-reg = <&tcs <<
1335 <<
1336 status = "disabled"; <<
1337 }; <<
1338 <<
1339 qusb2phy0: phy@c012000 { <<
1340 compatible = "qcom,sd 1258 compatible = "qcom,sdm660-qusb2-phy";
1341 reg = <0x0c012000 0x1 1259 reg = <0x0c012000 0x180>;
1342 #phy-cells = <0>; 1260 #phy-cells = <0>;
1343 1261
1344 clocks = <&gcc GCC_US 1262 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
1345 <&gcc GCC_RX !! 1263 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
1346 clock-names = "cfg_ah 1264 clock-names = "cfg_ahb", "ref";
1347 1265
1348 resets = <&gcc GCC_QU 1266 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
1349 nvmem-cells = <&qusb2 1267 nvmem-cells = <&qusb2_hstx_trim>;
1350 status = "disabled"; 1268 status = "disabled";
1351 }; 1269 };
1352 1270
1353 qusb2phy1: phy@c014000 { !! 1271 sdhc_2: sdhci@c084000 {
1354 compatible = "qcom,sd <<
1355 reg = <0x0c014000 0x1 <<
1356 #phy-cells = <0>; <<
1357 <<
1358 clocks = <&gcc GCC_US <<
1359 <&gcc GCC_RX <<
1360 clock-names = "cfg_ah <<
1361 <<
1362 resets = <&gcc GCC_QU <<
1363 nvmem-cells = <&qusb2 <<
1364 status = "disabled"; <<
1365 }; <<
1366 <<
1367 sdhc_2: mmc@c084000 { <<
1368 compatible = "qcom,sd 1272 compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5";
1369 reg = <0x0c084000 0x1 1273 reg = <0x0c084000 0x1000>;
1370 reg-names = "hc"; 1274 reg-names = "hc";
1371 1275
1372 interrupts = <GIC_SPI 1276 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1373 <GIC_ 1277 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
1374 interrupt-names = "hc 1278 interrupt-names = "hc_irq", "pwr_irq";
1375 1279
1376 bus-width = <4>; 1280 bus-width = <4>;
1377 !! 1281 clocks = <&gcc GCC_SDCC2_APPS_CLK>,
1378 clocks = <&gcc GCC_SD !! 1282 <&gcc GCC_SDCC2_AHB_CLK>,
1379 <&gcc <<
1380 <&xo_ 1283 <&xo_board>;
1381 clock-names = "iface" !! 1284 clock-names = "core", "iface", "xo";
1382 <<
1383 1285
1384 interconnects = <&a2n 1286 interconnects = <&a2noc 3 &a2noc 10>,
1385 <&gno 1287 <&gnoc 0 &cnoc 28>;
1386 interconnect-names = <<
1387 operating-points-v2 = 1288 operating-points-v2 = <&sdhc2_opp_table>;
1388 1289
1389 pinctrl-names = "defa 1290 pinctrl-names = "default", "sleep";
1390 pinctrl-0 = <&sdc2_st 1291 pinctrl-0 = <&sdc2_state_on>;
1391 pinctrl-1 = <&sdc2_st 1292 pinctrl-1 = <&sdc2_state_off>;
1392 power-domains = <&rpm 1293 power-domains = <&rpmpd SDM660_VDDCX>;
1393 1294
1394 status = "disabled"; 1295 status = "disabled";
1395 1296
1396 sdhc2_opp_table: opp- 1297 sdhc2_opp_table: opp-table {
1397 compatible = 1298 compatible = "operating-points-v2";
1398 1299
1399 opp-50000000 1300 opp-50000000 {
1400 opp-h 1301 opp-hz = /bits/ 64 <50000000>;
1401 requi 1302 required-opps = <&rpmpd_opp_low_svs>;
1402 opp-p 1303 opp-peak-kBps = <200000 140000>;
1403 opp-a 1304 opp-avg-kBps = <130718 133320>;
1404 }; 1305 };
1405 opp-10000000 1306 opp-100000000 {
1406 opp-h 1307 opp-hz = /bits/ 64 <100000000>;
1407 requi 1308 required-opps = <&rpmpd_opp_svs>;
1408 opp-p 1309 opp-peak-kBps = <250000 160000>;
1409 opp-a 1310 opp-avg-kBps = <196078 150000>;
1410 }; 1311 };
1411 opp-20000000 1312 opp-200000000 {
1412 opp-h 1313 opp-hz = /bits/ 64 <200000000>;
1413 requi 1314 required-opps = <&rpmpd_opp_nom>;
1414 opp-p 1315 opp-peak-kBps = <4096000 4096000>;
1415 opp-a 1316 opp-avg-kBps = <1338562 1338562>;
1416 }; 1317 };
1417 }; 1318 };
1418 }; 1319 };
1419 1320
1420 sdhc_1: mmc@c0c4000 { !! 1321 sdhc_1: sdhci@c0c4000 {
1421 compatible = "qcom,sd 1322 compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5";
1422 reg = <0x0c0c4000 0x1 1323 reg = <0x0c0c4000 0x1000>,
1423 <0x0c0c5000 0x1 1324 <0x0c0c5000 0x1000>,
1424 <0x0c0c8000 0x8 1325 <0x0c0c8000 0x8000>;
1425 reg-names = "hc", "cq 1326 reg-names = "hc", "cqhci", "ice";
1426 1327
1427 interrupts = <GIC_SPI 1328 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
1428 <GIC_ 1329 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1429 interrupt-names = "hc 1330 interrupt-names = "hc_irq", "pwr_irq";
1430 1331
1431 clocks = <&gcc GCC_SD !! 1332 clocks = <&gcc GCC_SDCC1_APPS_CLK>,
1432 <&gcc GCC_SD !! 1333 <&gcc GCC_SDCC1_AHB_CLK>,
1433 <&xo_board>, 1334 <&xo_board>,
1434 <&gcc GCC_SD 1335 <&gcc GCC_SDCC1_ICE_CORE_CLK>;
1435 clock-names = "iface" !! 1336 clock-names = "core", "iface", "xo", "ice";
1436 1337
1437 interconnects = <&a2n 1338 interconnects = <&a2noc 2 &a2noc 10>,
1438 <&gno 1339 <&gnoc 0 &cnoc 27>;
1439 interconnect-names = !! 1340 interconnect-names = "sdhc1-ddr", "cpu-sdhc1";
1440 operating-points-v2 = 1341 operating-points-v2 = <&sdhc1_opp_table>;
1441 pinctrl-names = "defa 1342 pinctrl-names = "default", "sleep";
1442 pinctrl-0 = <&sdc1_st 1343 pinctrl-0 = <&sdc1_state_on>;
1443 pinctrl-1 = <&sdc1_st 1344 pinctrl-1 = <&sdc1_state_off>;
1444 power-domains = <&rpm 1345 power-domains = <&rpmpd SDM660_VDDCX>;
1445 1346
1446 bus-width = <8>; 1347 bus-width = <8>;
1447 non-removable; 1348 non-removable;
1448 1349
1449 status = "disabled"; 1350 status = "disabled";
1450 1351
1451 sdhc1_opp_table: opp- 1352 sdhc1_opp_table: opp-table {
1452 compatible = 1353 compatible = "operating-points-v2";
1453 1354
1454 opp-50000000 1355 opp-50000000 {
1455 opp-h 1356 opp-hz = /bits/ 64 <50000000>;
1456 requi 1357 required-opps = <&rpmpd_opp_low_svs>;
1457 opp-p 1358 opp-peak-kBps = <200000 140000>;
1458 opp-a 1359 opp-avg-kBps = <130718 133320>;
1459 }; 1360 };
1460 opp-100000000 1361 opp-100000000 {
1461 opp-h 1362 opp-hz = /bits/ 64 <100000000>;
1462 requi 1363 required-opps = <&rpmpd_opp_svs>;
1463 opp-p 1364 opp-peak-kBps = <250000 160000>;
1464 opp-a 1365 opp-avg-kBps = <196078 150000>;
1465 }; 1366 };
1466 opp-384000000 1367 opp-384000000 {
1467 opp-h 1368 opp-hz = /bits/ 64 <384000000>;
1468 requi 1369 required-opps = <&rpmpd_opp_nom>;
1469 opp-p 1370 opp-peak-kBps = <4096000 4096000>;
1470 opp-a 1371 opp-avg-kBps = <1338562 1338562>;
1471 }; 1372 };
1472 }; 1373 };
1473 }; 1374 };
1474 1375
1475 usb2: usb@c2f8800 { <<
1476 compatible = "qcom,sd <<
1477 reg = <0x0c2f8800 0x4 <<
1478 status = "disabled"; <<
1479 #address-cells = <1>; <<
1480 #size-cells = <1>; <<
1481 ranges; <<
1482 <<
1483 clocks = <&gcc GCC_CF <<
1484 <&gcc GCC_US <<
1485 <&gcc GCC_US <<
1486 <&gcc GCC_US <<
1487 clock-names = "cfg_no <<
1488 "sleep" <<
1489 <<
1490 assigned-clocks = <&g <<
1491 <&g <<
1492 assigned-clock-rates <<
1493 <<
1494 interrupts = <GIC_SPI <<
1495 <GIC_SPI <<
1496 <GIC_SPI <<
1497 interrupt-names = "pw <<
1498 "qu <<
1499 "hs <<
1500 <<
1501 qcom,select-utmi-as-p <<
1502 <<
1503 resets = <&gcc GCC_US <<
1504 <<
1505 usb2_dwc3: usb@c20000 <<
1506 compatible = <<
1507 reg = <0x0c20 <<
1508 interrupts = <<
1509 snps,dis_u2_s <<
1510 snps,dis_enbl <<
1511 <<
1512 /* This is th <<
1513 maximum-speed <<
1514 phys = <&qusb <<
1515 phy-names = " <<
1516 snps,hird-thr <<
1517 }; <<
1518 }; <<
1519 <<
1520 mmcc: clock-controller@c8c000 1376 mmcc: clock-controller@c8c0000 {
1521 compatible = "qcom,mm 1377 compatible = "qcom,mmcc-sdm630";
1522 reg = <0x0c8c0000 0x4 1378 reg = <0x0c8c0000 0x40000>;
1523 #clock-cells = <1>; 1379 #clock-cells = <1>;
1524 #reset-cells = <1>; 1380 #reset-cells = <1>;
1525 #power-domain-cells = 1381 #power-domain-cells = <1>;
1526 clock-names = "xo", 1382 clock-names = "xo",
1527 "slee 1383 "sleep_clk",
1528 "gpll 1384 "gpll0",
1529 "gpll 1385 "gpll0_div",
1530 "dsi0 1386 "dsi0pll",
1531 "dsi0 1387 "dsi0pllbyte",
1532 "dsi1 1388 "dsi1pll",
1533 "dsi1 1389 "dsi1pllbyte",
1534 "dp_l 1390 "dp_link_2x_clk_divsel_five",
1535 "dp_v 1391 "dp_vco_divided_clk_src_mux";
1536 clocks = <&rpmcc RPM_ 1392 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1537 <&sle 1393 <&sleep_clk>,
1538 <&gcc 1394 <&gcc GCC_MMSS_GPLL0_CLK>,
1539 <&gcc 1395 <&gcc GCC_MMSS_GPLL0_DIV_CLK>,
1540 <&mds !! 1396 <&dsi0_phy 1>,
1541 <&mds !! 1397 <&dsi0_phy 0>,
1542 <0>, 1398 <0>,
1543 <0>, 1399 <0>,
1544 <0>, 1400 <0>,
1545 <0>; 1401 <0>;
1546 }; 1402 };
1547 1403
1548 mdss: display-subsystem@c9000 !! 1404 dsi_opp_table: dsi-opp-table {
>> 1405 compatible = "operating-points-v2";
>> 1406
>> 1407 opp-131250000 {
>> 1408 opp-hz = /bits/ 64 <131250000>;
>> 1409 required-opps = <&rpmpd_opp_svs>;
>> 1410 };
>> 1411
>> 1412 opp-210000000 {
>> 1413 opp-hz = /bits/ 64 <210000000>;
>> 1414 required-opps = <&rpmpd_opp_svs_plus>;
>> 1415 };
>> 1416
>> 1417 opp-262500000 {
>> 1418 opp-hz = /bits/ 64 <262500000>;
>> 1419 required-opps = <&rpmpd_opp_nom>;
>> 1420 };
>> 1421 };
>> 1422
>> 1423 mdss: mdss@c900000 {
1549 compatible = "qcom,md 1424 compatible = "qcom,mdss";
1550 reg = <0x0c900000 0x1 1425 reg = <0x0c900000 0x1000>,
1551 <0x0c9b0000 0x1 1426 <0x0c9b0000 0x1040>;
1552 reg-names = "mdss_phy 1427 reg-names = "mdss_phys", "vbif_phys";
1553 1428
1554 power-domains = <&mmc 1429 power-domains = <&mmcc MDSS_GDSC>;
1555 1430
1556 clocks = <&mmcc MDSS_ 1431 clocks = <&mmcc MDSS_AHB_CLK>,
1557 <&mmcc MDSS_ 1432 <&mmcc MDSS_AXI_CLK>,
1558 <&mmcc MDSS_ 1433 <&mmcc MDSS_VSYNC_CLK>,
1559 <&mmcc MDSS_ 1434 <&mmcc MDSS_MDP_CLK>;
1560 clock-names = "iface" 1435 clock-names = "iface",
1561 "bus", 1436 "bus",
1562 "vsync" 1437 "vsync",
1563 "core"; 1438 "core";
1564 1439
1565 interrupts = <GIC_SPI 1440 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1566 1441
1567 interrupt-controller; 1442 interrupt-controller;
1568 #interrupt-cells = <1 1443 #interrupt-cells = <1>;
1569 1444
1570 #address-cells = <1>; 1445 #address-cells = <1>;
1571 #size-cells = <1>; 1446 #size-cells = <1>;
1572 ranges; 1447 ranges;
1573 status = "disabled"; 1448 status = "disabled";
1574 1449
1575 mdp: display-controll !! 1450 mdp: mdp@c901000 {
1576 compatible = !! 1451 compatible = "qcom,mdp5";
1577 reg = <0x0c90 1452 reg = <0x0c901000 0x89000>;
1578 reg-names = " 1453 reg-names = "mdp_phys";
1579 1454
1580 interrupt-par 1455 interrupt-parent = <&mdss>;
1581 interrupts = !! 1456 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
1582 1457
1583 assigned-cloc 1458 assigned-clocks = <&mmcc MDSS_MDP_CLK>,
1584 1459 <&mmcc MDSS_VSYNC_CLK>;
1585 assigned-cloc 1460 assigned-clock-rates = <300000000>,
1586 1461 <19200000>;
1587 clocks = <&mm 1462 clocks = <&mmcc MDSS_AHB_CLK>,
1588 <&mm 1463 <&mmcc MDSS_AXI_CLK>,
1589 <&mm 1464 <&mmcc MDSS_MDP_CLK>,
1590 <&mm 1465 <&mmcc MDSS_VSYNC_CLK>;
1591 clock-names = 1466 clock-names = "iface",
1592 1467 "bus",
1593 1468 "core",
1594 1469 "vsync";
1595 1470
1596 interconnects 1471 interconnects = <&mnoc 2 &bimc 5>,
1597 1472 <&mnoc 3 &bimc 5>,
1598 1473 <&gnoc 0 &mnoc 17>;
1599 interconnect- 1474 interconnect-names = "mdp0-mem",
1600 1475 "mdp1-mem",
1601 1476 "rotator-mem";
1602 iommus = <&mm 1477 iommus = <&mmss_smmu 0>;
1603 operating-poi 1478 operating-points-v2 = <&mdp_opp_table>;
1604 power-domains 1479 power-domains = <&rpmpd SDM660_VDDCX>;
1605 1480
1606 ports { 1481 ports {
1607 #addr 1482 #address-cells = <1>;
1608 #size 1483 #size-cells = <0>;
1609 1484
1610 port@ 1485 port@0 {
1611 1486 reg = <0>;
1612 1487 mdp5_intf1_out: endpoint {
1613 !! 1488 remote-endpoint = <&dsi0_in>;
1614 1489 };
1615 }; 1490 };
1616 }; 1491 };
1617 1492
1618 mdp_opp_table !! 1493 mdp_opp_table: mdp-opp {
1619 compa 1494 compatible = "operating-points-v2";
1620 1495
1621 opp-1 1496 opp-150000000 {
1622 1497 opp-hz = /bits/ 64 <150000000>;
1623 1498 opp-peak-kBps = <320000 320000 76800>;
1624 1499 required-opps = <&rpmpd_opp_low_svs>;
1625 }; 1500 };
1626 opp-2 1501 opp-275000000 {
1627 1502 opp-hz = /bits/ 64 <275000000>;
1628 1503 opp-peak-kBps = <6400000 6400000 160000>;
1629 1504 required-opps = <&rpmpd_opp_svs>;
1630 }; 1505 };
1631 opp-3 1506 opp-300000000 {
1632 1507 opp-hz = /bits/ 64 <300000000>;
1633 1508 opp-peak-kBps = <6400000 6400000 190000>;
1634 1509 required-opps = <&rpmpd_opp_svs_plus>;
1635 }; 1510 };
1636 opp-3 1511 opp-330000000 {
1637 1512 opp-hz = /bits/ 64 <330000000>;
1638 1513 opp-peak-kBps = <6400000 6400000 240000>;
1639 1514 required-opps = <&rpmpd_opp_nom>;
1640 }; 1515 };
1641 opp-4 1516 opp-412500000 {
1642 1517 opp-hz = /bits/ 64 <412500000>;
1643 1518 opp-peak-kBps = <6400000 6400000 320000>;
1644 1519 required-opps = <&rpmpd_opp_turbo>;
1645 }; 1520 };
1646 }; 1521 };
1647 }; 1522 };
1648 1523
1649 mdss_dsi0: dsi@c99400 !! 1524 dsi0: dsi@c994000 {
1650 compatible = !! 1525 compatible = "qcom,mdss-dsi-ctrl";
1651 <<
1652 reg = <0x0c99 1526 reg = <0x0c994000 0x400>;
1653 reg-names = " 1527 reg-names = "dsi_ctrl";
1654 1528
1655 operating-poi 1529 operating-points-v2 = <&dsi_opp_table>;
1656 power-domains 1530 power-domains = <&rpmpd SDM660_VDDCX>;
1657 1531
1658 interrupt-par 1532 interrupt-parent = <&mdss>;
1659 interrupts = !! 1533 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
1660 1534
1661 assigned-cloc 1535 assigned-clocks = <&mmcc BYTE0_CLK_SRC>,
1662 1536 <&mmcc PCLK0_CLK_SRC>;
1663 assigned-cloc !! 1537 assigned-clock-parents = <&dsi0_phy 0>,
1664 !! 1538 <&dsi0_phy 1>;
1665 1539
1666 clocks = <&mm 1540 clocks = <&mmcc MDSS_MDP_CLK>,
1667 <&mm 1541 <&mmcc MDSS_BYTE0_CLK>,
1668 <&mm 1542 <&mmcc MDSS_BYTE0_INTF_CLK>,
1669 <&mm 1543 <&mmcc MNOC_AHB_CLK>,
1670 <&mm 1544 <&mmcc MDSS_AHB_CLK>,
1671 <&mm 1545 <&mmcc MDSS_AXI_CLK>,
1672 <&mm 1546 <&mmcc MISC_AHB_CLK>,
1673 <&mm 1547 <&mmcc MDSS_PCLK0_CLK>,
1674 <&mm 1548 <&mmcc MDSS_ESC0_CLK>;
1675 clock-names = 1549 clock-names = "mdp_core",
1676 1550 "byte",
1677 1551 "byte_intf",
1678 1552 "mnoc",
1679 1553 "iface",
1680 1554 "bus",
1681 1555 "core_mmss",
1682 1556 "pixel",
1683 1557 "core";
1684 1558
1685 phys = <&mdss !! 1559 phys = <&dsi0_phy>;
1686 !! 1560 phy-names = "dsi";
1687 status = "dis <<
1688 1561
1689 ports { 1562 ports {
1690 #addr 1563 #address-cells = <1>;
1691 #size 1564 #size-cells = <0>;
1692 1565
1693 port@ 1566 port@0 {
1694 1567 reg = <0>;
1695 !! 1568 dsi0_in: endpoint {
1696 1569 remote-endpoint = <&mdp5_intf1_out>;
1697 1570 };
1698 }; 1571 };
1699 1572
1700 port@ 1573 port@1 {
1701 1574 reg = <1>;
1702 !! 1575 dsi0_out: endpoint {
1703 1576 };
1704 }; 1577 };
1705 }; 1578 };
1706 }; 1579 };
1707 1580
1708 mdss_dsi0_phy: phy@c9 !! 1581 dsi0_phy: dsi-phy@c994400 {
1709 compatible = 1582 compatible = "qcom,dsi-phy-14nm-660";
1710 reg = <0x0c99 1583 reg = <0x0c994400 0x100>,
1711 <0x0c99 1584 <0x0c994500 0x300>,
1712 <0x0c99 1585 <0x0c994800 0x188>;
1713 reg-names = " 1586 reg-names = "dsi_phy",
1714 " 1587 "dsi_phy_lane",
1715 " 1588 "dsi_pll";
1716 1589
1717 #clock-cells 1590 #clock-cells = <1>;
1718 #phy-cells = 1591 #phy-cells = <0>;
1719 1592
1720 clocks = <&mm 1593 clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>;
1721 clock-names = 1594 clock-names = "iface", "ref";
1722 status = "dis <<
1723 }; 1595 };
1724 }; 1596 };
1725 1597
1726 blsp1_dma: dma-controller@c14 1598 blsp1_dma: dma-controller@c144000 {
1727 compatible = "qcom,ba 1599 compatible = "qcom,bam-v1.7.0";
1728 reg = <0x0c144000 0x1 1600 reg = <0x0c144000 0x1f000>;
1729 interrupts = <GIC_SPI 1601 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
1730 clocks = <&gcc GCC_BL 1602 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
1731 clock-names = "bam_cl 1603 clock-names = "bam_clk";
1732 #dma-cells = <1>; 1604 #dma-cells = <1>;
1733 qcom,ee = <0>; 1605 qcom,ee = <0>;
1734 qcom,controlled-remot 1606 qcom,controlled-remotely;
1735 num-channels = <18>; 1607 num-channels = <18>;
1736 qcom,num-ees = <4>; 1608 qcom,num-ees = <4>;
1737 }; 1609 };
1738 1610
1739 blsp1_uart1: serial@c16f000 { 1611 blsp1_uart1: serial@c16f000 {
1740 compatible = "qcom,ms 1612 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1741 reg = <0x0c16f000 0x2 1613 reg = <0x0c16f000 0x200>;
1742 interrupts = <GIC_SPI 1614 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1743 clocks = <&gcc GCC_BL 1615 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
1744 <&gcc GCC_BL 1616 <&gcc GCC_BLSP1_AHB_CLK>;
1745 clock-names = "core", 1617 clock-names = "core", "iface";
1746 dmas = <&blsp1_dma 0> 1618 dmas = <&blsp1_dma 0>, <&blsp1_dma 1>;
1747 dma-names = "tx", "rx 1619 dma-names = "tx", "rx";
1748 pinctrl-names = "defa 1620 pinctrl-names = "default", "sleep";
1749 pinctrl-0 = <&blsp1_u 1621 pinctrl-0 = <&blsp1_uart1_default>;
1750 pinctrl-1 = <&blsp1_u 1622 pinctrl-1 = <&blsp1_uart1_sleep>;
1751 status = "disabled"; 1623 status = "disabled";
1752 }; 1624 };
1753 1625
1754 blsp1_uart2: serial@c170000 { 1626 blsp1_uart2: serial@c170000 {
1755 compatible = "qcom,ms 1627 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1756 reg = <0x0c170000 0x1 1628 reg = <0x0c170000 0x1000>;
1757 interrupts = <GIC_SPI 1629 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1758 clocks = <&gcc GCC_BL 1630 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
1759 <&gcc GCC_BL 1631 <&gcc GCC_BLSP1_AHB_CLK>;
1760 clock-names = "core", 1632 clock-names = "core", "iface";
1761 dmas = <&blsp1_dma 2> 1633 dmas = <&blsp1_dma 2>, <&blsp1_dma 3>;
1762 dma-names = "tx", "rx 1634 dma-names = "tx", "rx";
1763 pinctrl-names = "defa 1635 pinctrl-names = "default";
1764 pinctrl-0 = <&blsp1_u 1636 pinctrl-0 = <&blsp1_uart2_default>;
1765 status = "disabled"; 1637 status = "disabled";
1766 }; 1638 };
1767 1639
1768 blsp_i2c1: i2c@c175000 { 1640 blsp_i2c1: i2c@c175000 {
1769 compatible = "qcom,i2 1641 compatible = "qcom,i2c-qup-v2.2.1";
1770 reg = <0x0c175000 0x6 1642 reg = <0x0c175000 0x600>;
1771 interrupts = <GIC_SPI 1643 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1772 1644
1773 clocks = <&gcc GCC_BL 1645 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
1774 <&gcc 1646 <&gcc GCC_BLSP1_AHB_CLK>;
1775 clock-names = "core", 1647 clock-names = "core", "iface";
1776 clock-frequency = <40 1648 clock-frequency = <400000>;
1777 dmas = <&blsp1_dma 4> 1649 dmas = <&blsp1_dma 4>, <&blsp1_dma 5>;
1778 dma-names = "tx", "rx 1650 dma-names = "tx", "rx";
1779 1651
1780 pinctrl-names = "defa 1652 pinctrl-names = "default", "sleep";
1781 pinctrl-0 = <&i2c1_de 1653 pinctrl-0 = <&i2c1_default>;
1782 pinctrl-1 = <&i2c1_sl 1654 pinctrl-1 = <&i2c1_sleep>;
1783 #address-cells = <1>; 1655 #address-cells = <1>;
1784 #size-cells = <0>; 1656 #size-cells = <0>;
1785 status = "disabled"; 1657 status = "disabled";
1786 }; 1658 };
1787 1659
1788 blsp_i2c2: i2c@c176000 { 1660 blsp_i2c2: i2c@c176000 {
1789 compatible = "qcom,i2 1661 compatible = "qcom,i2c-qup-v2.2.1";
1790 reg = <0x0c176000 0x6 1662 reg = <0x0c176000 0x600>;
1791 interrupts = <GIC_SPI 1663 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1792 1664
1793 clocks = <&gcc GCC_BL 1665 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
1794 <&gcc GCC_BL 1666 <&gcc GCC_BLSP1_AHB_CLK>;
1795 clock-names = "core", 1667 clock-names = "core", "iface";
1796 clock-frequency = <40 1668 clock-frequency = <400000>;
1797 dmas = <&blsp1_dma 6> 1669 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>;
1798 dma-names = "tx", "rx 1670 dma-names = "tx", "rx";
1799 1671
1800 pinctrl-names = "defa 1672 pinctrl-names = "default", "sleep";
1801 pinctrl-0 = <&i2c2_de 1673 pinctrl-0 = <&i2c2_default>;
1802 pinctrl-1 = <&i2c2_sl 1674 pinctrl-1 = <&i2c2_sleep>;
1803 #address-cells = <1>; 1675 #address-cells = <1>;
1804 #size-cells = <0>; 1676 #size-cells = <0>;
1805 status = "disabled"; 1677 status = "disabled";
1806 }; 1678 };
1807 1679
1808 blsp_i2c3: i2c@c177000 { 1680 blsp_i2c3: i2c@c177000 {
1809 compatible = "qcom,i2 1681 compatible = "qcom,i2c-qup-v2.2.1";
1810 reg = <0x0c177000 0x6 1682 reg = <0x0c177000 0x600>;
1811 interrupts = <GIC_SPI 1683 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1812 1684
1813 clocks = <&gcc GCC_BL 1685 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
1814 <&gcc GCC_BL 1686 <&gcc GCC_BLSP1_AHB_CLK>;
1815 clock-names = "core", 1687 clock-names = "core", "iface";
1816 clock-frequency = <40 1688 clock-frequency = <400000>;
1817 dmas = <&blsp1_dma 8> 1689 dmas = <&blsp1_dma 8>, <&blsp1_dma 9>;
1818 dma-names = "tx", "rx 1690 dma-names = "tx", "rx";
1819 1691
1820 pinctrl-names = "defa 1692 pinctrl-names = "default", "sleep";
1821 pinctrl-0 = <&i2c3_de 1693 pinctrl-0 = <&i2c3_default>;
1822 pinctrl-1 = <&i2c3_sl 1694 pinctrl-1 = <&i2c3_sleep>;
1823 #address-cells = <1>; 1695 #address-cells = <1>;
1824 #size-cells = <0>; 1696 #size-cells = <0>;
1825 status = "disabled"; 1697 status = "disabled";
1826 }; 1698 };
1827 1699
1828 blsp_i2c4: i2c@c178000 { 1700 blsp_i2c4: i2c@c178000 {
1829 compatible = "qcom,i2 1701 compatible = "qcom,i2c-qup-v2.2.1";
1830 reg = <0x0c178000 0x6 1702 reg = <0x0c178000 0x600>;
1831 interrupts = <GIC_SPI 1703 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1832 1704
1833 clocks = <&gcc GCC_BL 1705 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
1834 <&gcc GCC_BL 1706 <&gcc GCC_BLSP1_AHB_CLK>;
1835 clock-names = "core", 1707 clock-names = "core", "iface";
1836 clock-frequency = <40 1708 clock-frequency = <400000>;
1837 dmas = <&blsp1_dma 10 1709 dmas = <&blsp1_dma 10>, <&blsp1_dma 11>;
1838 dma-names = "tx", "rx 1710 dma-names = "tx", "rx";
1839 1711
1840 pinctrl-names = "defa 1712 pinctrl-names = "default", "sleep";
1841 pinctrl-0 = <&i2c4_de 1713 pinctrl-0 = <&i2c4_default>;
1842 pinctrl-1 = <&i2c4_sl 1714 pinctrl-1 = <&i2c4_sleep>;
1843 #address-cells = <1>; 1715 #address-cells = <1>;
1844 #size-cells = <0>; 1716 #size-cells = <0>;
1845 status = "disabled"; 1717 status = "disabled";
1846 }; 1718 };
1847 1719
1848 blsp2_dma: dma-controller@c18 1720 blsp2_dma: dma-controller@c184000 {
1849 compatible = "qcom,ba 1721 compatible = "qcom,bam-v1.7.0";
1850 reg = <0x0c184000 0x1 1722 reg = <0x0c184000 0x1f000>;
1851 interrupts = <GIC_SPI 1723 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
1852 clocks = <&gcc GCC_BL 1724 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
1853 clock-names = "bam_cl 1725 clock-names = "bam_clk";
1854 #dma-cells = <1>; 1726 #dma-cells = <1>;
1855 qcom,ee = <0>; 1727 qcom,ee = <0>;
1856 qcom,controlled-remot 1728 qcom,controlled-remotely;
1857 num-channels = <18>; 1729 num-channels = <18>;
1858 qcom,num-ees = <4>; 1730 qcom,num-ees = <4>;
1859 }; 1731 };
1860 1732
1861 blsp2_uart1: serial@c1af000 { 1733 blsp2_uart1: serial@c1af000 {
1862 compatible = "qcom,ms 1734 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1863 reg = <0x0c1af000 0x2 1735 reg = <0x0c1af000 0x200>;
1864 interrupts = <GIC_SPI 1736 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1865 clocks = <&gcc GCC_BL 1737 clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>,
1866 <&gcc GCC_BL 1738 <&gcc GCC_BLSP2_AHB_CLK>;
1867 clock-names = "core", 1739 clock-names = "core", "iface";
1868 dmas = <&blsp2_dma 0> 1740 dmas = <&blsp2_dma 0>, <&blsp2_dma 1>;
1869 dma-names = "tx", "rx 1741 dma-names = "tx", "rx";
1870 pinctrl-names = "defa 1742 pinctrl-names = "default", "sleep";
1871 pinctrl-0 = <&blsp2_u 1743 pinctrl-0 = <&blsp2_uart1_default>;
1872 pinctrl-1 = <&blsp2_u 1744 pinctrl-1 = <&blsp2_uart1_sleep>;
1873 status = "disabled"; 1745 status = "disabled";
1874 }; 1746 };
1875 1747
1876 blsp_i2c5: i2c@c1b5000 { 1748 blsp_i2c5: i2c@c1b5000 {
1877 compatible = "qcom,i2 1749 compatible = "qcom,i2c-qup-v2.2.1";
1878 reg = <0x0c1b5000 0x6 1750 reg = <0x0c1b5000 0x600>;
1879 interrupts = <GIC_SPI 1751 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1880 1752
1881 clocks = <&gcc GCC_BL 1753 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
1882 <&gcc GCC_BL 1754 <&gcc GCC_BLSP2_AHB_CLK>;
1883 clock-names = "core", 1755 clock-names = "core", "iface";
1884 clock-frequency = <40 1756 clock-frequency = <400000>;
1885 dmas = <&blsp2_dma 4> 1757 dmas = <&blsp2_dma 4>, <&blsp2_dma 5>;
1886 dma-names = "tx", "rx 1758 dma-names = "tx", "rx";
1887 1759
1888 pinctrl-names = "defa 1760 pinctrl-names = "default", "sleep";
1889 pinctrl-0 = <&i2c5_de 1761 pinctrl-0 = <&i2c5_default>;
1890 pinctrl-1 = <&i2c5_sl 1762 pinctrl-1 = <&i2c5_sleep>;
1891 #address-cells = <1>; 1763 #address-cells = <1>;
1892 #size-cells = <0>; 1764 #size-cells = <0>;
1893 status = "disabled"; 1765 status = "disabled";
1894 }; 1766 };
1895 1767
1896 blsp_i2c6: i2c@c1b6000 { 1768 blsp_i2c6: i2c@c1b6000 {
1897 compatible = "qcom,i2 1769 compatible = "qcom,i2c-qup-v2.2.1";
1898 reg = <0x0c1b6000 0x6 1770 reg = <0x0c1b6000 0x600>;
1899 interrupts = <GIC_SPI 1771 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1900 1772
1901 clocks = <&gcc GCC_BL 1773 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
1902 <&gcc GCC_BL 1774 <&gcc GCC_BLSP2_AHB_CLK>;
1903 clock-names = "core", 1775 clock-names = "core", "iface";
1904 clock-frequency = <40 1776 clock-frequency = <400000>;
1905 dmas = <&blsp2_dma 6> 1777 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>;
1906 dma-names = "tx", "rx 1778 dma-names = "tx", "rx";
1907 1779
1908 pinctrl-names = "defa 1780 pinctrl-names = "default", "sleep";
1909 pinctrl-0 = <&i2c6_de 1781 pinctrl-0 = <&i2c6_default>;
1910 pinctrl-1 = <&i2c6_sl 1782 pinctrl-1 = <&i2c6_sleep>;
1911 #address-cells = <1>; 1783 #address-cells = <1>;
1912 #size-cells = <0>; 1784 #size-cells = <0>;
1913 status = "disabled"; 1785 status = "disabled";
1914 }; 1786 };
1915 1787
1916 blsp_i2c7: i2c@c1b7000 { 1788 blsp_i2c7: i2c@c1b7000 {
1917 compatible = "qcom,i2 1789 compatible = "qcom,i2c-qup-v2.2.1";
1918 reg = <0x0c1b7000 0x6 1790 reg = <0x0c1b7000 0x600>;
1919 interrupts = <GIC_SPI 1791 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1920 1792
1921 clocks = <&gcc GCC_BL 1793 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
1922 <&gcc GCC_BL 1794 <&gcc GCC_BLSP2_AHB_CLK>;
1923 clock-names = "core", 1795 clock-names = "core", "iface";
1924 clock-frequency = <40 1796 clock-frequency = <400000>;
1925 dmas = <&blsp2_dma 8> 1797 dmas = <&blsp2_dma 8>, <&blsp2_dma 9>;
1926 dma-names = "tx", "rx 1798 dma-names = "tx", "rx";
1927 1799
1928 pinctrl-names = "defa 1800 pinctrl-names = "default", "sleep";
1929 pinctrl-0 = <&i2c7_de 1801 pinctrl-0 = <&i2c7_default>;
1930 pinctrl-1 = <&i2c7_sl 1802 pinctrl-1 = <&i2c7_sleep>;
1931 #address-cells = <1>; 1803 #address-cells = <1>;
1932 #size-cells = <0>; 1804 #size-cells = <0>;
1933 status = "disabled"; 1805 status = "disabled";
1934 }; 1806 };
1935 1807
1936 blsp_i2c8: i2c@c1b8000 { 1808 blsp_i2c8: i2c@c1b8000 {
1937 compatible = "qcom,i2 1809 compatible = "qcom,i2c-qup-v2.2.1";
1938 reg = <0x0c1b8000 0x6 1810 reg = <0x0c1b8000 0x600>;
1939 interrupts = <GIC_SPI 1811 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1940 1812
1941 clocks = <&gcc GCC_BL 1813 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>,
1942 <&gcc GCC_BL 1814 <&gcc GCC_BLSP2_AHB_CLK>;
1943 clock-names = "core", 1815 clock-names = "core", "iface";
1944 clock-frequency = <40 1816 clock-frequency = <400000>;
1945 dmas = <&blsp2_dma 10 1817 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>;
1946 dma-names = "tx", "rx 1818 dma-names = "tx", "rx";
1947 1819
1948 pinctrl-names = "defa 1820 pinctrl-names = "default", "sleep";
1949 pinctrl-0 = <&i2c8_de 1821 pinctrl-0 = <&i2c8_default>;
1950 pinctrl-1 = <&i2c8_sl 1822 pinctrl-1 = <&i2c8_sleep>;
1951 #address-cells = <1>; 1823 #address-cells = <1>;
1952 #size-cells = <0>; 1824 #size-cells = <0>;
1953 status = "disabled"; 1825 status = "disabled";
1954 }; 1826 };
1955 1827
1956 sram@146bf000 { !! 1828 imem@146bf000 {
1957 compatible = "qcom,sd !! 1829 compatible = "simple-mfd";
1958 reg = <0x146bf000 0x1 1830 reg = <0x146bf000 0x1000>;
1959 1831
1960 #address-cells = <1>; 1832 #address-cells = <1>;
1961 #size-cells = <1>; 1833 #size-cells = <1>;
1962 1834
1963 ranges = <0 0x146bf00 1835 ranges = <0 0x146bf000 0x1000>;
1964 1836
1965 pil-reloc@94c { 1837 pil-reloc@94c {
1966 compatible = 1838 compatible = "qcom,pil-reloc-info";
1967 reg = <0x94c 1839 reg = <0x94c 0xc8>;
1968 }; 1840 };
1969 }; 1841 };
1970 1842
1971 camss: camss@ca00020 { !! 1843 camss: camss@ca00000 {
1972 compatible = "qcom,sd 1844 compatible = "qcom,sdm660-camss";
1973 reg = <0x0ca00020 0x1 !! 1845 reg = <0x0c824000 0x1000>,
1974 <0x0ca30000 0x1 <<
1975 <0x0ca30400 0x1 <<
1976 <0x0ca30800 0x1 <<
1977 <0x0ca30c00 0x1 <<
1978 <0x0c824000 0x1 <<
1979 <0x0ca00120 0x4 1846 <0x0ca00120 0x4>,
1980 <0x0c825000 0x1 1847 <0x0c825000 0x1000>,
1981 <0x0ca00124 0x4 1848 <0x0ca00124 0x4>,
1982 <0x0c826000 0x1 1849 <0x0c826000 0x1000>,
1983 <0x0ca00128 0x4 1850 <0x0ca00128 0x4>,
>> 1851 <0x0ca30000 0x100>,
>> 1852 <0x0ca30400 0x100>,
>> 1853 <0x0ca30800 0x100>,
>> 1854 <0x0ca30c00 0x100>,
1984 <0x0ca31000 0x5 1855 <0x0ca31000 0x500>,
>> 1856 <0x0ca00020 0x10>,
1985 <0x0ca10000 0x1 1857 <0x0ca10000 0x1000>,
1986 <0x0ca14000 0x1 1858 <0x0ca14000 0x1000>;
1987 reg-names = "csi_clk_ !! 1859 reg-names = "csiphy0",
1988 "csid0", <<
1989 "csid1", <<
1990 "csid2", <<
1991 "csid3", <<
1992 "csiphy0" <<
1993 "csiphy0_ 1860 "csiphy0_clk_mux",
1994 "csiphy1" 1861 "csiphy1",
1995 "csiphy1_ 1862 "csiphy1_clk_mux",
1996 "csiphy2" 1863 "csiphy2",
1997 "csiphy2_ 1864 "csiphy2_clk_mux",
>> 1865 "csid0",
>> 1866 "csid1",
>> 1867 "csid2",
>> 1868 "csid3",
1998 "ispif", 1869 "ispif",
>> 1870 "csi_clk_mux",
1999 "vfe0", 1871 "vfe0",
2000 "vfe1"; 1872 "vfe1";
2001 interrupts = <GIC_SPI !! 1873 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
>> 1874 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
>> 1875 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
>> 1876 <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
2002 <GIC_SPI 1877 <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
2003 <GIC_SPI 1878 <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
2004 <GIC_SPI 1879 <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
2005 <GIC_SPI <<
2006 <GIC_SPI <<
2007 <GIC_SPI <<
2008 <GIC_SPI 1880 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>,
2009 <GIC_SPI 1881 <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
2010 <GIC_SPI 1882 <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>;
2011 interrupt-names = "cs !! 1883 interrupt-names = "csiphy0",
>> 1884 "csiphy1",
>> 1885 "csiphy2",
>> 1886 "csid0",
2012 "cs 1887 "csid1",
2013 "cs 1888 "csid2",
2014 "cs 1889 "csid3",
2015 "cs <<
2016 "cs <<
2017 "cs <<
2018 "is 1890 "ispif",
2019 "vf 1891 "vfe0",
2020 "vf 1892 "vfe1";
2021 clocks = <&mmcc CAMSS !! 1893 clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
2022 <&mmcc CAMSS !! 1894 <&mmcc THROTTLE_CAMSS_AXI_CLK>,
2023 <&mmcc CAMSS !! 1895 <&mmcc CAMSS_ISPIF_AHB_CLK>,
2024 <&mmcc CAMSS !! 1896 <&mmcc CAMSS_CSI0PHYTIMER_CLK>,
2025 <&mmcc CAMSS !! 1897 <&mmcc CAMSS_CSI1PHYTIMER_CLK>,
2026 <&mmcc CAMSS !! 1898 <&mmcc CAMSS_CSI2PHYTIMER_CLK>,
2027 <&mmcc CAMSS !! 1899 <&mmcc CAMSS_CSI0_AHB_CLK>,
2028 <&mmcc CAMSS !! 1900 <&mmcc CAMSS_CSI0_CLK>,
2029 <&mmcc CAMSS !! 1901 <&mmcc CAMSS_CPHY_CSID0_CLK>,
2030 <&mmcc CAMSS !! 1902 <&mmcc CAMSS_CSI0PIX_CLK>,
2031 <&mmcc CAMSS !! 1903 <&mmcc CAMSS_CSI0RDI_CLK>,
2032 <&mmcc CAMSS !! 1904 <&mmcc CAMSS_CSI1_AHB_CLK>,
2033 <&mmcc CAMSS !! 1905 <&mmcc CAMSS_CSI1_CLK>,
2034 <&mmcc CAMSS !! 1906 <&mmcc CAMSS_CPHY_CSID1_CLK>,
2035 <&mmcc CAMSS !! 1907 <&mmcc CAMSS_CSI1PIX_CLK>,
2036 <&mmcc CAMSS !! 1908 <&mmcc CAMSS_CSI1RDI_CLK>,
2037 <&mmcc CAMSS !! 1909 <&mmcc CAMSS_CSI2_AHB_CLK>,
2038 <&mmcc CAMSS !! 1910 <&mmcc CAMSS_CSI2_CLK>,
2039 <&mmcc CAMSS !! 1911 <&mmcc CAMSS_CPHY_CSID2_CLK>,
2040 <&mmcc CAMSS !! 1912 <&mmcc CAMSS_CSI2PIX_CLK>,
2041 <&mmcc CAMSS !! 1913 <&mmcc CAMSS_CSI2RDI_CLK>,
2042 <&mmcc CAMSS !! 1914 <&mmcc CAMSS_CSI3_AHB_CLK>,
2043 <&mmcc CAMSS !! 1915 <&mmcc CAMSS_CSI3_CLK>,
2044 <&mmcc CAMSS !! 1916 <&mmcc CAMSS_CPHY_CSID3_CLK>,
2045 <&mmcc CAMSS !! 1917 <&mmcc CAMSS_CSI3PIX_CLK>,
2046 <&mmcc CAMSS !! 1918 <&mmcc CAMSS_CSI3RDI_CLK>,
2047 <&mmcc CAMSS !! 1919 <&mmcc CAMSS_AHB_CLK>,
2048 <&mmcc CAMSS !! 1920 <&mmcc CAMSS_VFE0_CLK>,
2049 <&mmcc CSIPH !! 1921 <&mmcc CAMSS_CSI_VFE0_CLK>,
2050 <&mmcc CAMSS !! 1922 <&mmcc CAMSS_VFE0_AHB_CLK>,
2051 <&mmcc CAMSS !! 1923 <&mmcc CAMSS_VFE0_STREAM_CLK>,
2052 <&mmcc CAMSS !! 1924 <&mmcc CAMSS_VFE1_CLK>,
2053 <&mmcc THROT !! 1925 <&mmcc CAMSS_CSI_VFE1_CLK>,
2054 <&mmcc CAMSS !! 1926 <&mmcc CAMSS_VFE1_AHB_CLK>,
2055 <&mmcc CAMSS !! 1927 <&mmcc CAMSS_VFE1_STREAM_CLK>,
2056 <&mmcc CAMSS !! 1928 <&mmcc CAMSS_VFE_VBIF_AHB_CLK>,
2057 <&mmcc CAMSS !! 1929 <&mmcc CAMSS_VFE_VBIF_AXI_CLK>,
2058 <&mmcc CAMSS !! 1930 <&mmcc CSIPHY_AHB2CRIF_CLK>,
2059 <&mmcc CAMSS !! 1931 <&mmcc CAMSS_CPHY_CSID0_CLK>,
2060 <&mmcc CAMSS !! 1932 <&mmcc CAMSS_CPHY_CSID1_CLK>,
2061 <&mmcc CAMSS !! 1933 <&mmcc CAMSS_CPHY_CSID2_CLK>,
2062 <&mmcc CAMSS !! 1934 <&mmcc CAMSS_CPHY_CSID3_CLK>;
2063 clock-names = "ahb", !! 1935 clock-names = "top_ahb",
2064 "cphy_c !! 1936 "throttle_axi",
2065 "cphy_c !! 1937 "ispif_ahb",
2066 "cphy_c !! 1938 "csiphy0_timer",
2067 "cphy_c !! 1939 "csiphy1_timer",
2068 "csi0_a !! 1940 "csiphy2_timer",
2069 "csi0", !! 1941 "csi0_ahb",
2070 "csi0_p !! 1942 "csi0",
2071 "csi0_p !! 1943 "csi0_phy",
2072 "csi0_r !! 1944 "csi0_pix",
2073 "csi1_a !! 1945 "csi0_rdi",
2074 "csi1", !! 1946 "csi1_ahb",
2075 "csi1_p !! 1947 "csi1",
2076 "csi1_p !! 1948 "csi1_phy",
2077 "csi1_r !! 1949 "csi1_pix",
2078 "csi2_a !! 1950 "csi1_rdi",
2079 "csi2", !! 1951 "csi2_ahb",
2080 "csi2_p !! 1952 "csi2",
2081 "csi2_p !! 1953 "csi2_phy",
2082 "csi2_r !! 1954 "csi2_pix",
2083 "csi3_a !! 1955 "csi2_rdi",
2084 "csi3", !! 1956 "csi3_ahb",
2085 "csi3_p !! 1957 "csi3",
2086 "csi3_p !! 1958 "csi3_phy",
2087 "csi3_r !! 1959 "csi3_pix",
2088 "csiphy !! 1960 "csi3_rdi",
2089 "csiphy !! 1961 "ahb",
2090 "csiphy !! 1962 "vfe0",
2091 "csiphy !! 1963 "csi_vfe0",
2092 "csi_vf !! 1964 "vfe0_ahb",
2093 "csi_vf !! 1965 "vfe0_stream",
2094 "ispif_ !! 1966 "vfe1",
2095 "thrott !! 1967 "csi_vfe1",
2096 "top_ah !! 1968 "vfe1_ahb",
2097 "vfe0_a !! 1969 "vfe1_stream",
2098 "vfe0", !! 1970 "vfe_ahb",
2099 "vfe0_s !! 1971 "vfe_axi",
2100 "vfe1_a !! 1972 "csiphy_ahb2crif",
2101 "vfe1", !! 1973 "cphy_csid0",
2102 "vfe1_s !! 1974 "cphy_csid1",
2103 "vfe_ah !! 1975 "cphy_csid2",
2104 "vfe_ax !! 1976 "cphy_csid3";
2105 interconnects = <&mno 1977 interconnects = <&mnoc 5 &bimc 5>;
2106 interconnect-names = 1978 interconnect-names = "vfe-mem";
2107 iommus = <&mmss_smmu 1979 iommus = <&mmss_smmu 0xc00>,
2108 <&mmss_smmu 1980 <&mmss_smmu 0xc01>,
2109 <&mmss_smmu 1981 <&mmss_smmu 0xc02>,
2110 <&mmss_smmu 1982 <&mmss_smmu 0xc03>;
2111 power-domains = <&mmc 1983 power-domains = <&mmcc CAMSS_VFE0_GDSC>,
2112 <&mmc 1984 <&mmcc CAMSS_VFE1_GDSC>;
2113 status = "disabled"; 1985 status = "disabled";
2114 1986
2115 ports { 1987 ports {
2116 #address-cell 1988 #address-cells = <1>;
2117 #size-cells = 1989 #size-cells = <0>;
2118 }; 1990 };
2119 }; 1991 };
2120 1992
2121 cci: cci@ca0c000 { 1993 cci: cci@ca0c000 {
2122 compatible = "qcom,ms 1994 compatible = "qcom,msm8996-cci";
2123 #address-cells = <1>; 1995 #address-cells = <1>;
2124 #size-cells = <0>; 1996 #size-cells = <0>;
2125 reg = <0x0ca0c000 0x1 1997 reg = <0x0ca0c000 0x1000>;
2126 interrupts = <GIC_SPI 1998 interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>;
2127 1999
2128 assigned-clocks = <&m 2000 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>,
2129 <&m 2001 <&mmcc CAMSS_CCI_CLK>;
2130 assigned-clock-rates 2002 assigned-clock-rates = <80800000>, <37500000>;
2131 clocks = <&mmcc CAMSS 2003 clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
2132 <&mmcc CAMSS 2004 <&mmcc CAMSS_CCI_AHB_CLK>,
2133 <&mmcc CAMSS 2005 <&mmcc CAMSS_CCI_CLK>,
2134 <&mmcc CAMSS 2006 <&mmcc CAMSS_AHB_CLK>;
2135 clock-names = "camss_ 2007 clock-names = "camss_top_ahb",
2136 "cci_ah 2008 "cci_ahb",
2137 "cci", 2009 "cci",
2138 "camss_ 2010 "camss_ahb";
2139 2011
2140 pinctrl-names = "defa 2012 pinctrl-names = "default";
2141 pinctrl-0 = <&cci0_de 2013 pinctrl-0 = <&cci0_default &cci1_default>;
2142 power-domains = <&mmc 2014 power-domains = <&mmcc CAMSS_TOP_GDSC>;
2143 status = "disabled"; 2015 status = "disabled";
2144 2016
2145 cci_i2c0: i2c-bus@0 { 2017 cci_i2c0: i2c-bus@0 {
2146 reg = <0>; 2018 reg = <0>;
2147 clock-frequen 2019 clock-frequency = <400000>;
2148 #address-cell 2020 #address-cells = <1>;
2149 #size-cells = 2021 #size-cells = <0>;
2150 }; 2022 };
2151 2023
2152 cci_i2c1: i2c-bus@1 { 2024 cci_i2c1: i2c-bus@1 {
2153 reg = <1>; 2025 reg = <1>;
2154 clock-frequen 2026 clock-frequency = <400000>;
2155 #address-cell 2027 #address-cells = <1>;
2156 #size-cells = 2028 #size-cells = <0>;
2157 }; 2029 };
2158 }; 2030 };
2159 2031
2160 venus: video-codec@cc00000 { 2032 venus: video-codec@cc00000 {
2161 compatible = "qcom,sd 2033 compatible = "qcom,sdm660-venus";
2162 reg = <0x0cc00000 0xf 2034 reg = <0x0cc00000 0xff000>;
2163 clocks = <&mmcc VIDEO 2035 clocks = <&mmcc VIDEO_CORE_CLK>,
2164 <&mmcc VIDEO 2036 <&mmcc VIDEO_AHB_CLK>,
2165 <&mmcc VIDEO 2037 <&mmcc VIDEO_AXI_CLK>,
2166 <&mmcc THROT 2038 <&mmcc THROTTLE_VIDEO_AXI_CLK>;
2167 clock-names = "core", 2039 clock-names = "core", "iface", "bus", "bus_throttle";
2168 interconnects = <&gno 2040 interconnects = <&gnoc 0 &mnoc 13>,
2169 <&mno 2041 <&mnoc 4 &bimc 5>;
2170 interconnect-names = 2042 interconnect-names = "cpu-cfg", "video-mem";
2171 interrupts = <GIC_SPI 2043 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
2172 iommus = <&mmss_smmu 2044 iommus = <&mmss_smmu 0x400>,
2173 <&mmss_smmu 2045 <&mmss_smmu 0x401>,
2174 <&mmss_smmu 2046 <&mmss_smmu 0x40a>,
2175 <&mmss_smmu 2047 <&mmss_smmu 0x407>,
2176 <&mmss_smmu 2048 <&mmss_smmu 0x40e>,
2177 <&mmss_smmu 2049 <&mmss_smmu 0x40f>,
2178 <&mmss_smmu 2050 <&mmss_smmu 0x408>,
2179 <&mmss_smmu 2051 <&mmss_smmu 0x409>,
2180 <&mmss_smmu 2052 <&mmss_smmu 0x40b>,
2181 <&mmss_smmu 2053 <&mmss_smmu 0x40c>,
2182 <&mmss_smmu 2054 <&mmss_smmu 0x40d>,
2183 <&mmss_smmu 2055 <&mmss_smmu 0x410>,
2184 <&mmss_smmu 2056 <&mmss_smmu 0x421>,
2185 <&mmss_smmu 2057 <&mmss_smmu 0x428>,
2186 <&mmss_smmu 2058 <&mmss_smmu 0x429>,
2187 <&mmss_smmu 2059 <&mmss_smmu 0x42b>,
2188 <&mmss_smmu 2060 <&mmss_smmu 0x42c>,
2189 <&mmss_smmu 2061 <&mmss_smmu 0x42d>,
2190 <&mmss_smmu 2062 <&mmss_smmu 0x411>,
2191 <&mmss_smmu 2063 <&mmss_smmu 0x431>;
2192 memory-region = <&ven 2064 memory-region = <&venus_region>;
2193 power-domains = <&mmc 2065 power-domains = <&mmcc VENUS_GDSC>;
2194 status = "disabled"; 2066 status = "disabled";
2195 2067
2196 video-decoder { 2068 video-decoder {
2197 compatible = 2069 compatible = "venus-decoder";
2198 clocks = <&mm 2070 clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
2199 clock-names = 2071 clock-names = "vcodec0_core";
2200 power-domains 2072 power-domains = <&mmcc VENUS_CORE0_GDSC>;
2201 }; 2073 };
2202 2074
2203 video-encoder { 2075 video-encoder {
2204 compatible = 2076 compatible = "venus-encoder";
2205 clocks = <&mm 2077 clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
2206 clock-names = 2078 clock-names = "vcodec0_core";
2207 power-domains 2079 power-domains = <&mmcc VENUS_CORE0_GDSC>;
2208 }; 2080 };
2209 }; 2081 };
2210 2082
2211 mmss_smmu: iommu@cd00000 { 2083 mmss_smmu: iommu@cd00000 {
2212 compatible = "qcom,sd 2084 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
2213 reg = <0x0cd00000 0x4 2085 reg = <0x0cd00000 0x40000>;
2214 2086
2215 clocks = <&mmcc MNOC_ 2087 clocks = <&mmcc MNOC_AHB_CLK>,
2216 <&mmcc BIMC_ 2088 <&mmcc BIMC_SMMU_AHB_CLK>,
>> 2089 <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK>,
2217 <&mmcc BIMC_ 2090 <&mmcc BIMC_SMMU_AXI_CLK>;
2218 clock-names = "iface- 2091 clock-names = "iface-mm", "iface-smmu",
2219 "bus-sm !! 2092 "bus-mm", "bus-smmu";
2220 #global-interrupts = 2093 #global-interrupts = <2>;
2221 #iommu-cells = <1>; 2094 #iommu-cells = <1>;
2222 2095
2223 interrupts = 2096 interrupts =
2224 <GIC_SPI 229 2097 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
2225 <GIC_SPI 231 2098 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
2226 2099
2227 <GIC_SPI 263 2100 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
2228 <GIC_SPI 266 2101 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
2229 <GIC_SPI 267 2102 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
2230 <GIC_SPI 268 2103 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
2231 <GIC_SPI 244 2104 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
2232 <GIC_SPI 245 2105 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
2233 <GIC_SPI 247 2106 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
2234 <GIC_SPI 248 2107 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
2235 <GIC_SPI 249 2108 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
2236 <GIC_SPI 250 2109 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
2237 <GIC_SPI 251 2110 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
2238 <GIC_SPI 252 2111 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
2239 <GIC_SPI 253 2112 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
2240 <GIC_SPI 254 2113 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
2241 <GIC_SPI 255 2114 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
2242 <GIC_SPI 256 2115 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
2243 <GIC_SPI 260 2116 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
2244 <GIC_SPI 261 2117 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
2245 <GIC_SPI 262 2118 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
2246 <GIC_SPI 272 2119 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
2247 <GIC_SPI 273 2120 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
2248 <GIC_SPI 274 2121 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
2249 <GIC_SPI 275 2122 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
2250 <GIC_SPI 276 2123 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
2251 2124
2252 status = "disabled"; 2125 status = "disabled";
2253 }; 2126 };
2254 2127
2255 adsp_pil: remoteproc@15700000 2128 adsp_pil: remoteproc@15700000 {
2256 compatible = "qcom,sd 2129 compatible = "qcom,sdm660-adsp-pas";
2257 reg = <0x15700000 0x4 2130 reg = <0x15700000 0x4040>;
2258 2131
2259 interrupts-extended = 2132 interrupts-extended =
2260 <&intc GIC_SP 2133 <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
2261 <&adsp_smp2p_ 2134 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2262 <&adsp_smp2p_ 2135 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2263 <&adsp_smp2p_ 2136 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2264 <&adsp_smp2p_ 2137 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2265 interrupt-names = "wd 2138 interrupt-names = "wdog", "fatal", "ready",
2266 "ha 2139 "handover", "stop-ack";
2267 2140
2268 clocks = <&rpmcc RPM_ 2141 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
2269 clock-names = "xo"; 2142 clock-names = "xo";
2270 2143
2271 memory-region = <&ads 2144 memory-region = <&adsp_region>;
2272 power-domains = <&rpm 2145 power-domains = <&rpmpd SDM660_VDDCX>;
2273 power-domain-names = 2146 power-domain-names = "cx";
2274 2147
2275 qcom,smem-states = <& 2148 qcom,smem-states = <&adsp_smp2p_out 0>;
2276 qcom,smem-state-names 2149 qcom,smem-state-names = "stop";
2277 2150
2278 glink-edge { 2151 glink-edge {
2279 interrupts = 2152 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
2280 2153
2281 label = "lpas 2154 label = "lpass";
2282 mboxes = <&ap 2155 mboxes = <&apcs_glb 9>;
2283 qcom,remote-p 2156 qcom,remote-pid = <2>;
>> 2157 #address-cells = <1>;
>> 2158 #size-cells = <0>;
2284 2159
2285 apr { 2160 apr {
2286 compa 2161 compatible = "qcom,apr-v2";
2287 qcom, 2162 qcom,glink-channels = "apr_audio_svc";
2288 qcom, !! 2163 qcom,apr-domain = <APR_DOMAIN_ADSP>;
2289 #addr 2164 #address-cells = <1>;
2290 #size 2165 #size-cells = <0>;
2291 2166
2292 servi !! 2167 q6core {
2293 2168 reg = <APR_SVC_ADSP_CORE>;
2294 2169 compatible = "qcom,q6core";
2295 }; 2170 };
2296 2171
2297 q6afe !! 2172 q6afe: apr-service@4 {
2298 2173 compatible = "qcom,q6afe";
2299 2174 reg = <APR_SVC_AFE>;
2300 2175 q6afedai: dais {
2301 2176 compatible = "qcom,q6afe-dais";
2302 2177 #address-cells = <1>;
2303 2178 #size-cells = <0>;
2304 2179 #sound-dai-cells = <1>;
2305 2180 };
2306 }; 2181 };
2307 2182
2308 q6asm !! 2183 q6asm: apr-service@7 {
2309 2184 compatible = "qcom,q6asm";
2310 2185 reg = <APR_SVC_ASM>;
2311 2186 q6asmdai: dais {
2312 2187 compatible = "qcom,q6asm-dais";
2313 2188 #address-cells = <1>;
2314 2189 #size-cells = <0>;
2315 2190 #sound-dai-cells = <1>;
2316 2191 iommus = <&lpass_smmu 1>;
2317 2192 };
2318 }; 2193 };
2319 2194
2320 q6adm !! 2195 q6adm: apr-service@8 {
2321 2196 compatible = "qcom,q6adm";
2322 2197 reg = <APR_SVC_ADM>;
2323 2198 q6routing: routing {
2324 2199 compatible = "qcom,q6adm-routing";
2325 2200 #sound-dai-cells = <0>;
2326 2201 };
2327 }; 2202 };
2328 }; 2203 };
2329 }; 2204 };
2330 }; 2205 };
2331 2206
2332 gnoc: interconnect@17900000 { 2207 gnoc: interconnect@17900000 {
2333 compatible = "qcom,sd 2208 compatible = "qcom,sdm660-gnoc";
2334 reg = <0x17900000 0xe 2209 reg = <0x17900000 0xe000>;
2335 #interconnect-cells = 2210 #interconnect-cells = <1>;
>> 2211 /*
>> 2212 * This one apparently features no clocks,
>> 2213 * so let's not mess with the driver needlessly
>> 2214 */
>> 2215 clock-names = "bus", "bus_a";
>> 2216 clocks = <&xo_board>, <&xo_board>;
2336 }; 2217 };
2337 2218
2338 apcs_glb: mailbox@17911000 { 2219 apcs_glb: mailbox@17911000 {
2339 compatible = "qcom,sd !! 2220 compatible = "qcom,sdm660-apcs-hmss-global";
2340 "qcom,ms <<
2341 reg = <0x17911000 0x1 2221 reg = <0x17911000 0x1000>;
2342 2222
2343 #mbox-cells = <1>; 2223 #mbox-cells = <1>;
2344 }; 2224 };
2345 2225
2346 timer@17920000 { 2226 timer@17920000 {
2347 #address-cells = <1>; 2227 #address-cells = <1>;
2348 #size-cells = <1>; 2228 #size-cells = <1>;
2349 ranges; 2229 ranges;
2350 compatible = "arm,arm 2230 compatible = "arm,armv7-timer-mem";
2351 reg = <0x17920000 0x1 2231 reg = <0x17920000 0x1000>;
2352 clock-frequency = <19 2232 clock-frequency = <19200000>;
2353 2233
2354 frame@17921000 { 2234 frame@17921000 {
2355 frame-number 2235 frame-number = <0>;
2356 interrupts = !! 2236 interrupts = <0 8 0x4>,
2357 !! 2237 <0 7 0x4>;
2358 reg = <0x1792 2238 reg = <0x17921000 0x1000>,
2359 <0x17 2239 <0x17922000 0x1000>;
2360 }; 2240 };
2361 2241
2362 frame@17923000 { 2242 frame@17923000 {
2363 frame-number 2243 frame-number = <1>;
2364 interrupts = !! 2244 interrupts = <0 9 0x4>;
2365 reg = <0x1792 2245 reg = <0x17923000 0x1000>;
2366 status = "dis 2246 status = "disabled";
2367 }; 2247 };
2368 2248
2369 frame@17924000 { 2249 frame@17924000 {
2370 frame-number 2250 frame-number = <2>;
2371 interrupts = !! 2251 interrupts = <0 10 0x4>;
2372 reg = <0x1792 2252 reg = <0x17924000 0x1000>;
2373 status = "dis 2253 status = "disabled";
2374 }; 2254 };
2375 2255
2376 frame@17925000 { 2256 frame@17925000 {
2377 frame-number 2257 frame-number = <3>;
2378 interrupts = !! 2258 interrupts = <0 11 0x4>;
2379 reg = <0x1792 2259 reg = <0x17925000 0x1000>;
2380 status = "dis 2260 status = "disabled";
2381 }; 2261 };
2382 2262
2383 frame@17926000 { 2263 frame@17926000 {
2384 frame-number 2264 frame-number = <4>;
2385 interrupts = !! 2265 interrupts = <0 12 0x4>;
2386 reg = <0x1792 2266 reg = <0x17926000 0x1000>;
2387 status = "dis 2267 status = "disabled";
2388 }; 2268 };
2389 2269
2390 frame@17927000 { 2270 frame@17927000 {
2391 frame-number 2271 frame-number = <5>;
2392 interrupts = !! 2272 interrupts = <0 13 0x4>;
2393 reg = <0x1792 2273 reg = <0x17927000 0x1000>;
2394 status = "dis 2274 status = "disabled";
2395 }; 2275 };
2396 2276
2397 frame@17928000 { 2277 frame@17928000 {
2398 frame-number 2278 frame-number = <6>;
2399 interrupts = !! 2279 interrupts = <0 14 0x4>;
2400 reg = <0x1792 2280 reg = <0x17928000 0x1000>;
2401 status = "dis 2281 status = "disabled";
2402 }; 2282 };
2403 }; 2283 };
2404 2284
2405 intc: interrupt-controller@17 2285 intc: interrupt-controller@17a00000 {
2406 compatible = "arm,gic 2286 compatible = "arm,gic-v3";
2407 reg = <0x17a00000 0x1 2287 reg = <0x17a00000 0x10000>, /* GICD */
2408 <0x17b00000 2288 <0x17b00000 0x100000>; /* GICR * 8 */
2409 #interrupt-cells = <3 2289 #interrupt-cells = <3>;
2410 #address-cells = <1>; 2290 #address-cells = <1>;
2411 #size-cells = <1>; 2291 #size-cells = <1>;
2412 ranges; 2292 ranges;
2413 interrupt-controller; 2293 interrupt-controller;
2414 #redistributor-region 2294 #redistributor-regions = <1>;
2415 redistributor-stride 2295 redistributor-stride = <0x0 0x20000>;
2416 interrupts = <GIC_PPI 2296 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
2417 }; 2297 };
2418 }; 2298 };
2419 2299
>> 2300 tcsr_mutex: hwlock {
>> 2301 compatible = "qcom,tcsr-mutex";
>> 2302 syscon = <&tcsr_mutex_regs 0 0x1000>;
>> 2303 #hwlock-cells = <1>;
>> 2304 };
>> 2305
2420 sound: sound { 2306 sound: sound {
2421 }; 2307 };
2422 2308
2423 thermal-zones { 2309 thermal-zones {
2424 aoss-thermal { 2310 aoss-thermal {
2425 polling-delay-passive 2311 polling-delay-passive = <250>;
>> 2312 polling-delay = <1000>;
2426 2313
2427 thermal-sensors = <&t 2314 thermal-sensors = <&tsens 0>;
2428 2315
2429 trips { 2316 trips {
2430 aoss_alert0: 2317 aoss_alert0: trip-point0 {
2431 tempe 2318 temperature = <105000>;
2432 hyste 2319 hysteresis = <1000>;
2433 type 2320 type = "hot";
2434 }; 2321 };
2435 }; 2322 };
2436 }; 2323 };
2437 2324
2438 cpuss0-thermal { 2325 cpuss0-thermal {
2439 polling-delay-passive 2326 polling-delay-passive = <250>;
>> 2327 polling-delay = <1000>;
2440 2328
2441 thermal-sensors = <&t 2329 thermal-sensors = <&tsens 1>;
2442 2330
2443 trips { 2331 trips {
2444 cpuss0_alert0 2332 cpuss0_alert0: trip-point0 {
2445 tempe 2333 temperature = <125000>;
2446 hyste 2334 hysteresis = <1000>;
2447 type 2335 type = "hot";
2448 }; 2336 };
2449 }; 2337 };
2450 }; 2338 };
2451 2339
2452 cpuss1-thermal { 2340 cpuss1-thermal {
2453 polling-delay-passive 2341 polling-delay-passive = <250>;
>> 2342 polling-delay = <1000>;
2454 2343
2455 thermal-sensors = <&t 2344 thermal-sensors = <&tsens 2>;
2456 2345
2457 trips { 2346 trips {
2458 cpuss1_alert0 2347 cpuss1_alert0: trip-point0 {
2459 tempe 2348 temperature = <125000>;
2460 hyste 2349 hysteresis = <1000>;
2461 type 2350 type = "hot";
2462 }; 2351 };
2463 }; 2352 };
2464 }; 2353 };
2465 2354
2466 cpu0-thermal { 2355 cpu0-thermal {
2467 polling-delay-passive 2356 polling-delay-passive = <250>;
>> 2357 polling-delay = <1000>;
2468 2358
2469 thermal-sensors = <&t 2359 thermal-sensors = <&tsens 3>;
2470 2360
2471 trips { 2361 trips {
2472 cpu0_alert0: 2362 cpu0_alert0: trip-point0 {
2473 tempe 2363 temperature = <70000>;
2474 hyste 2364 hysteresis = <1000>;
2475 type 2365 type = "passive";
2476 }; 2366 };
2477 2367
2478 cpu0_crit: cp !! 2368 cpu0_crit: cpu_crit {
2479 tempe 2369 temperature = <110000>;
2480 hyste 2370 hysteresis = <1000>;
2481 type 2371 type = "critical";
2482 }; 2372 };
2483 }; 2373 };
2484 }; 2374 };
2485 2375
2486 cpu1-thermal { 2376 cpu1-thermal {
2487 polling-delay-passive 2377 polling-delay-passive = <250>;
>> 2378 polling-delay = <1000>;
2488 2379
2489 thermal-sensors = <&t 2380 thermal-sensors = <&tsens 4>;
2490 2381
2491 trips { 2382 trips {
2492 cpu1_alert0: 2383 cpu1_alert0: trip-point0 {
2493 tempe 2384 temperature = <70000>;
2494 hyste 2385 hysteresis = <1000>;
2495 type 2386 type = "passive";
2496 }; 2387 };
2497 2388
2498 cpu1_crit: cp !! 2389 cpu1_crit: cpu_crit {
2499 tempe 2390 temperature = <110000>;
2500 hyste 2391 hysteresis = <1000>;
2501 type 2392 type = "critical";
2502 }; 2393 };
2503 }; 2394 };
2504 }; 2395 };
2505 2396
2506 cpu2-thermal { 2397 cpu2-thermal {
2507 polling-delay-passive 2398 polling-delay-passive = <250>;
>> 2399 polling-delay = <1000>;
2508 2400
2509 thermal-sensors = <&t 2401 thermal-sensors = <&tsens 5>;
2510 2402
2511 trips { 2403 trips {
2512 cpu2_alert0: 2404 cpu2_alert0: trip-point0 {
2513 tempe 2405 temperature = <70000>;
2514 hyste 2406 hysteresis = <1000>;
2515 type 2407 type = "passive";
2516 }; 2408 };
2517 2409
2518 cpu2_crit: cp !! 2410 cpu2_crit: cpu_crit {
2519 tempe 2411 temperature = <110000>;
2520 hyste 2412 hysteresis = <1000>;
2521 type 2413 type = "critical";
2522 }; 2414 };
2523 }; 2415 };
2524 }; 2416 };
2525 2417
2526 cpu3-thermal { 2418 cpu3-thermal {
2527 polling-delay-passive 2419 polling-delay-passive = <250>;
>> 2420 polling-delay = <1000>;
2528 2421
2529 thermal-sensors = <&t 2422 thermal-sensors = <&tsens 6>;
2530 2423
2531 trips { 2424 trips {
2532 cpu3_alert0: 2425 cpu3_alert0: trip-point0 {
2533 tempe 2426 temperature = <70000>;
2534 hyste 2427 hysteresis = <1000>;
2535 type 2428 type = "passive";
2536 }; 2429 };
2537 2430
2538 cpu3_crit: cp !! 2431 cpu3_crit: cpu_crit {
2539 tempe 2432 temperature = <110000>;
2540 hyste 2433 hysteresis = <1000>;
2541 type 2434 type = "critical";
2542 }; 2435 };
2543 }; 2436 };
2544 }; 2437 };
2545 2438
2546 /* 2439 /*
2547 * According to what downstre 2440 * According to what downstream DTS says,
2548 * the entire power efficient 2441 * the entire power efficient cluster has
2549 * only a single thermal sens 2442 * only a single thermal sensor.
2550 */ 2443 */
2551 2444
2552 pwr-cluster-thermal { 2445 pwr-cluster-thermal {
2553 polling-delay-passive 2446 polling-delay-passive = <250>;
>> 2447 polling-delay = <1000>;
2554 2448
2555 thermal-sensors = <&t 2449 thermal-sensors = <&tsens 7>;
2556 2450
2557 trips { 2451 trips {
2558 pwr_cluster_a 2452 pwr_cluster_alert0: trip-point0 {
2559 tempe 2453 temperature = <70000>;
2560 hyste 2454 hysteresis = <1000>;
2561 type 2455 type = "passive";
2562 }; 2456 };
2563 2457
2564 pwr_cluster_c !! 2458 pwr_cluster_crit: cpu_crit {
2565 tempe 2459 temperature = <110000>;
2566 hyste 2460 hysteresis = <1000>;
2567 type 2461 type = "critical";
2568 }; 2462 };
2569 }; 2463 };
2570 }; 2464 };
2571 2465
2572 gpu-thermal { 2466 gpu-thermal {
2573 polling-delay-passive 2467 polling-delay-passive = <250>;
>> 2468 polling-delay = <1000>;
2574 2469
2575 thermal-sensors = <&t 2470 thermal-sensors = <&tsens 8>;
2576 2471
2577 cooling-maps { <<
2578 map0 { <<
2579 trip <<
2580 cooli <<
2581 }; <<
2582 }; <<
2583 <<
2584 trips { 2472 trips {
2585 gpu_alert0: t 2473 gpu_alert0: trip-point0 {
2586 tempe <<
2587 hyste <<
2588 type <<
2589 }; <<
2590 <<
2591 trip-point1 { <<
2592 tempe 2474 temperature = <90000>;
2593 hyste 2475 hysteresis = <1000>;
2594 type 2476 type = "hot";
2595 }; 2477 };
2596 <<
2597 trip-point2 { <<
2598 tempe <<
2599 hyste <<
2600 type <<
2601 }; <<
2602 }; 2478 };
2603 }; 2479 };
2604 }; 2480 };
2605 2481
2606 timer { 2482 timer {
2607 compatible = "arm,armv8-timer 2483 compatible = "arm,armv8-timer";
2608 interrupts = <GIC_PPI 1 (GIC_ !! 2484 interrupts = <GIC_PPI 1 0xf08>,
2609 <GIC_PPI 2 (GIC_ !! 2485 <GIC_PPI 2 0xf08>,
2610 <GIC_PPI 3 (GIC_ !! 2486 <GIC_PPI 3 0xf08>,
2611 <GIC_PPI 0 (GIC_ !! 2487 <GIC_PPI 0 0xf08>;
2612 }; 2488 };
2613 }; 2489 };
2614 2490
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